C Specification
The VkMemoryBarrier2KHR structure is defined as:
// Provided by VK_KHR_synchronization2
typedef struct VkMemoryBarrier2KHR {
VkStructureType sType;
const void* pNext;
VkPipelineStageFlags2KHR srcStageMask;
VkAccessFlags2KHR srcAccessMask;
VkPipelineStageFlags2KHR dstStageMask;
VkAccessFlags2KHR dstAccessMask;
} VkMemoryBarrier2KHR;
Members
-
sTypeis the type of this structure. -
pNextisNULLor a pointer to a structure extending this structure. -
srcStageMaskis a VkPipelineStageFlags2KHR mask of pipeline stages to be included in the first synchronization scope. -
srcAccessMaskis a VkAccessFlags2KHR mask of pipeline first access scope. -
dstStageMaskis a VkPipelineStageFlags2KHR mask of pipeline stages to be included in the second synchronization scope. -
dstStageMaskis a VkAccessFlags2KHR mask of pipeline second access scope.
Description
This structure defines a memory dependency affecting all device memory.
The first synchronization scope and
access scope described by
this structure include only operations and memory accesses specified by
srcStageMask and srcAccessMask.
The second synchronization scope
and access scope described
by this structure include only operations and memory accesses specified by
dstStageMask and dstAccessMask.
-
VUID-VkMemoryBarrier2KHR-sType-sType
sTypemust beVK_STRUCTURE_TYPE_MEMORY_BARRIER_2_KHR -
VUID-VkMemoryBarrier2KHR-srcStageMask-parameter
srcStageMaskmust be a valid combination of VkPipelineStageFlagBits2KHR values -
VUID-VkMemoryBarrier2KHR-srcAccessMask-parameter
srcAccessMaskmust be a valid combination of VkAccessFlagBits2KHR values -
VUID-VkMemoryBarrier2KHR-dstStageMask-parameter
dstStageMaskmust be a valid combination of VkPipelineStageFlagBits2KHR values -
VUID-VkMemoryBarrier2KHR-dstAccessMask-parameter
dstAccessMaskmust be a valid combination of VkAccessFlagBits2KHR values
-
VUID-VkMemoryBarrier2KHR-srcStageMask-03929
If the geometry shaders feature is not enabled,srcStageMaskmust not containVK_PIPELINE_STAGE_2_GEOMETRY_SHADER_BIT_KHR -
VUID-VkMemoryBarrier2KHR-srcStageMask-03930
If the tessellation shaders feature is not enabled,srcStageMaskmust not containVK_PIPELINE_STAGE_2_TESSELLATION_CONTROL_SHADER_BIT_KHRorVK_PIPELINE_STAGE_2_TESSELLATION_EVALUATION_SHADER_BIT_KHR -
VUID-VkMemoryBarrier2KHR-srcStageMask-03931
If the conditional rendering feature is not enabled,srcStageMaskmust not containVK_PIPELINE_STAGE_2_CONDITIONAL_RENDERING_BIT_EXT -
VUID-VkMemoryBarrier2KHR-srcStageMask-03932
If the fragment density map feature is not enabled,srcStageMaskmust not containVK_PIPELINE_STAGE_2_FRAGMENT_DENSITY_PROCESS_BIT_EXT -
VUID-VkMemoryBarrier2KHR-srcStageMask-03933
If the transform feedback feature is not enabled,srcStageMaskmust not containVK_PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT -
VUID-VkMemoryBarrier2KHR-srcStageMask-03934
If the mesh shaders feature is not enabled,srcStageMaskmust not containVK_PIPELINE_STAGE_2_MESH_SHADER_BIT_NV -
VUID-VkMemoryBarrier2KHR-srcStageMask-03935
If the task shaders feature is not enabled,srcStageMaskmust not containVK_PIPELINE_STAGE_2_TASK_SHADER_BIT_NV -
VUID-VkMemoryBarrier2KHR-srcStageMask-03936
If the shading rate image feature is not enabled,srcStageMaskmust not containVK_PIPELINE_STAGE_2_SHADING_RATE_IMAGE_BIT_NV -
VUID-VkMemoryBarrier2KHR-srcAccessMask-03900
IfsrcAccessMaskincludesVK_ACCESS_2_INDIRECT_COMMAND_READ_BIT_KHR,srcStageMaskmust includeVK_PIPELINE_STAGE_2_DRAW_INDIRECT_BIT_KHR,VK_PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR,VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, orVK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR -
VUID-VkMemoryBarrier2KHR-srcAccessMask-03901
IfsrcAccessMaskincludesVK_ACCESS_2_INDEX_READ_BIT_KHR,srcStageMaskmust includeVK_PIPELINE_STAGE_2_INDEX_INPUT_BIT_KHR,VK_PIPELINE_STAGE_2_VERTEX_INPUT_BIT_KHR,VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, orVK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR -
VUID-VkMemoryBarrier2KHR-srcAccessMask-03902
IfsrcAccessMaskincludesVK_ACCESS_2_VERTEX_ATTRIBUTE_READ_BIT_KHR,srcStageMaskmust includeVK_PIPELINE_STAGE_2_VERTEX_ATTRIBUTE_INPUT_BIT_KHR,VK_PIPELINE_STAGE_2_VERTEX_INPUT_BIT_KHR,VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, orVK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR -
VUID-VkMemoryBarrier2KHR-srcAccessMask-03903
IfsrcAccessMaskincludesVK_ACCESS_2_INPUT_ATTACHMENT_READ_BIT_KHR,srcStageMaskmust includeVK_PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT_KHR,VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, orVK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR -
VUID-VkMemoryBarrier2KHR-srcAccessMask-03904
IfsrcAccessMaskincludesVK_ACCESS_2_UNIFORM_READ_BIT_KHR,srcStageMaskmust includeVK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR,VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR, or one of theVK_PIPELINE_STAGE_*_SHADER_BITstages -
VUID-VkMemoryBarrier2KHR-srcAccessMask-03905
IfsrcAccessMaskincludesVK_ACCESS_2_SHADER_SAMPLED_READ_BIT_KHR,srcStageMaskmust includeVK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR,VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR, or one of theVK_PIPELINE_STAGE_*_SHADER_BITstages -
VUID-VkMemoryBarrier2KHR-srcAccessMask-03906
IfsrcAccessMaskincludesVK_ACCESS_2_SHADER_STORAGE_READ_BIT_KHR,srcStageMaskmust includeVK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR,VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR, or one of theVK_PIPELINE_STAGE_*_SHADER_BITstages -
VUID-VkMemoryBarrier2KHR-srcAccessMask-03907
IfsrcAccessMaskincludesVK_ACCESS_2_SHADER_STORAGE_WRITE_BIT_KHR,srcStageMaskmust includeVK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR,VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR, or one of theVK_PIPELINE_STAGE_*_SHADER_BITstages -
VUID-VkMemoryBarrier2KHR-srcAccessMask-03908
IfsrcAccessMaskincludesVK_ACCESS_2_SHADER_READ_BIT_KHR,srcStageMaskmust includeVK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR,VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR,VK_PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR, or one of theVK_PIPELINE_STAGE_*_SHADER_BITstages -
VUID-VkMemoryBarrier2KHR-srcAccessMask-03909
IfsrcAccessMaskincludesVK_ACCESS_2_SHADER_WRITE_BIT_KHR,srcStageMaskmust includeVK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR,VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR, or one of theVK_PIPELINE_STAGE_*_SHADER_BITstages -
VUID-VkMemoryBarrier2KHR-srcAccessMask-03910
IfsrcAccessMaskincludesVK_ACCESS_2_COLOR_ATTACHMENT_READ_BIT_KHR,srcStageMaskmust includeVK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT_KHRVK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, orVK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR -
VUID-VkMemoryBarrier2KHR-srcAccessMask-03911
IfsrcAccessMaskincludesVK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT_KHR,srcStageMaskmust includeVK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT_KHRVK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, orVK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR -
VUID-VkMemoryBarrier2KHR-srcAccessMask-03912
IfsrcAccessMaskincludesVK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_READ_BIT_KHR,srcStageMaskmust includeVK_PIPELINE_STAGE_2_EARLY_FRAGMENT_TESTS_BIT_KHR,VK_PIPELINE_STAGE_2_LATE_FRAGMENT_TESTS_BIT_KHR,VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, orVK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR -
VUID-VkMemoryBarrier2KHR-srcAccessMask-03913
IfsrcAccessMaskincludesVK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT_KHR,srcStageMaskmust includeVK_PIPELINE_STAGE_2_EARLY_FRAGMENT_TESTS_BIT_KHR,VK_PIPELINE_STAGE_2_LATE_FRAGMENT_TESTS_BIT_KHR,VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, orVK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR -
VUID-VkMemoryBarrier2KHR-srcAccessMask-03914
IfsrcAccessMaskincludesVK_ACCESS_2_TRANSFER_READ_BIT_KHR,srcStageMaskmust includeVK_PIPELINE_STAGE_2_COPY_BIT_KHR,VK_PIPELINE_STAGE_2_BLIT_BIT_KHR,VK_PIPELINE_STAGE_2_RESOLVE_BIT_KHR,VK_PIPELINE_STAGE_2_ALL_TRANSFER_BIT_KHR,VK_PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR, orVK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR -
VUID-VkMemoryBarrier2KHR-srcAccessMask-03915
IfsrcAccessMaskincludesVK_ACCESS_2_TRANSFER_WRITE_BIT_KHR,srcStageMaskmust includeVK_PIPELINE_STAGE_2_COPY_BIT_KHR,VK_PIPELINE_STAGE_2_BLIT_BIT_KHR,VK_PIPELINE_STAGE_2_RESOLVE_BIT_KHR,VK_PIPELINE_STAGE_2_CLEAR_BIT_KHR,VK_PIPELINE_STAGE_2_ALL_TRANSFER_BIT_KHR,VK_PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR, orVK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR -
VUID-VkMemoryBarrier2KHR-srcAccessMask-03916
IfsrcAccessMaskincludesVK_ACCESS_2_HOST_READ_BIT_KHR,srcStageMaskmust includeVK_PIPELINE_STAGE_2_HOST_BIT_KHR -
VUID-VkMemoryBarrier2KHR-srcAccessMask-03917
IfsrcAccessMaskincludesVK_ACCESS_2_HOST_WRITE_BIT_KHR,srcStageMaskmust includeVK_PIPELINE_STAGE_2_HOST_BIT_KHR -
VUID-VkMemoryBarrier2KHR-srcAccessMask-03918
IfsrcAccessMaskincludesVK_ACCESS_2_CONDITIONAL_RENDERING_READ_BIT_EXT,srcStageMaskmust includeVK_PIPELINE_STAGE_2_CONDITIONAL_RENDERING_BIT_EXT,VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, orVK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR -
VUID-VkMemoryBarrier2KHR-srcAccessMask-03919
IfsrcAccessMaskincludesVK_ACCESS_2_FRAGMENT_DENSITY_MAP_READ_BIT_EXT,srcStageMaskmust includeVK_PIPELINE_STAGE_2_FRAGMENT_DENSITY_PROCESS_BIT_EXT,VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, orVK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR -
VUID-VkMemoryBarrier2KHR-srcAccessMask-03920
IfsrcAccessMaskincludesVK_ACCESS_2_TRANSFORM_FEEDBACK_WRITE_BIT_EXT,srcStageMaskmust includeVK_PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT,VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, orVK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR -
VUID-VkMemoryBarrier2KHR-srcAccessMask-03921
IfsrcAccessMaskincludesVK_ACCESS_2_TRANSFORM_FEEDBACK_COUNTER_READ_BIT_EXT,srcStageMaskmust includeVK_PIPELINE_STAGE_2_DRAW_INDIRECT_BIT_KHR,VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, orVK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR -
VUID-VkMemoryBarrier2KHR-srcAccessMask-03922
IfsrcAccessMaskincludesVK_ACCESS_2_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT,srcStageMaskmust includeVK_PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT,VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, orVK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR -
VUID-VkMemoryBarrier2KHR-srcAccessMask-03923
IfsrcAccessMaskincludesVK_ACCESS_2_SHADING_RATE_IMAGE_READ_BIT_NV,srcStageMaskmust includeVK_PIPELINE_STAGE_2_SHADING_RATE_IMAGE_BIT_NV,VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, orVK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR -
VUID-VkMemoryBarrier2KHR-srcAccessMask-03924
IfsrcAccessMaskincludesVK_ACCESS_2_COMMAND_PREPROCESS_READ_BIT_NV,srcStageMaskmust includeVK_PIPELINE_STAGE_2_COMMAND_PREPROCESS_BIT_NVorVK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR -
VUID-VkMemoryBarrier2KHR-srcAccessMask-03925
IfsrcAccessMaskincludesVK_ACCESS_2_COMMAND_PREPROCESS_WRITE_BIT_NV,srcStageMaskmust includeVK_PIPELINE_STAGE_2_COMMAND_PREPROCESS_BIT_NVorVK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR -
VUID-VkMemoryBarrier2KHR-srcAccessMask-03926
IfsrcAccessMaskincludesVK_ACCESS_2_COLOR_ATTACHMENT_READ_NONCOHERENT_BIT_EXT,srcStageMaskmust includeVK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT_KHRVK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, orVK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR -
VUID-VkMemoryBarrier2KHR-srcAccessMask-03927
IfsrcAccessMaskincludesVK_ACCESS_2_ACCELERATION_STRUCTURE_READ_BIT_KHR,srcStageMaskmust includeVK_PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR,VK_PIPELINE_STAGE_2_RAY_TRACING_SHADER_BIT_KHR, orVK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR -
VUID-VkMemoryBarrier2KHR-srcAccessMask-03928
IfsrcAccessMaskincludesVK_ACCESS_2_ACCELERATION_STRUCTURE_WRITE_BIT_KHR,srcStageMaskmust includeVK_PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHRorVK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR
-
VUID-VkMemoryBarrier2KHR-dstStageMask-03929
If the geometry shaders feature is not enabled,dstStageMaskmust not containVK_PIPELINE_STAGE_2_GEOMETRY_SHADER_BIT_KHR -
VUID-VkMemoryBarrier2KHR-dstStageMask-03930
If the tessellation shaders feature is not enabled,dstStageMaskmust not containVK_PIPELINE_STAGE_2_TESSELLATION_CONTROL_SHADER_BIT_KHRorVK_PIPELINE_STAGE_2_TESSELLATION_EVALUATION_SHADER_BIT_KHR -
VUID-VkMemoryBarrier2KHR-dstStageMask-03931
If the conditional rendering feature is not enabled,dstStageMaskmust not containVK_PIPELINE_STAGE_2_CONDITIONAL_RENDERING_BIT_EXT -
VUID-VkMemoryBarrier2KHR-dstStageMask-03932
If the fragment density map feature is not enabled,dstStageMaskmust not containVK_PIPELINE_STAGE_2_FRAGMENT_DENSITY_PROCESS_BIT_EXT -
VUID-VkMemoryBarrier2KHR-dstStageMask-03933
If the transform feedback feature is not enabled,dstStageMaskmust not containVK_PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT -
VUID-VkMemoryBarrier2KHR-dstStageMask-03934
If the mesh shaders feature is not enabled,dstStageMaskmust not containVK_PIPELINE_STAGE_2_MESH_SHADER_BIT_NV -
VUID-VkMemoryBarrier2KHR-dstStageMask-03935
If the task shaders feature is not enabled,dstStageMaskmust not containVK_PIPELINE_STAGE_2_TASK_SHADER_BIT_NV -
VUID-VkMemoryBarrier2KHR-dstStageMask-03936
If the shading rate image feature is not enabled,dstStageMaskmust not containVK_PIPELINE_STAGE_2_SHADING_RATE_IMAGE_BIT_NV -
VUID-VkMemoryBarrier2KHR-dstAccessMask-03900
IfdstAccessMaskincludesVK_ACCESS_2_INDIRECT_COMMAND_READ_BIT_KHR,dstStageMaskmust includeVK_PIPELINE_STAGE_2_DRAW_INDIRECT_BIT_KHR,VK_PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR,VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, orVK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR -
VUID-VkMemoryBarrier2KHR-dstAccessMask-03901
IfdstAccessMaskincludesVK_ACCESS_2_INDEX_READ_BIT_KHR,dstStageMaskmust includeVK_PIPELINE_STAGE_2_INDEX_INPUT_BIT_KHR,VK_PIPELINE_STAGE_2_VERTEX_INPUT_BIT_KHR,VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, orVK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR -
VUID-VkMemoryBarrier2KHR-dstAccessMask-03902
IfdstAccessMaskincludesVK_ACCESS_2_VERTEX_ATTRIBUTE_READ_BIT_KHR,dstStageMaskmust includeVK_PIPELINE_STAGE_2_VERTEX_ATTRIBUTE_INPUT_BIT_KHR,VK_PIPELINE_STAGE_2_VERTEX_INPUT_BIT_KHR,VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, orVK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR -
VUID-VkMemoryBarrier2KHR-dstAccessMask-03903
IfdstAccessMaskincludesVK_ACCESS_2_INPUT_ATTACHMENT_READ_BIT_KHR,dstStageMaskmust includeVK_PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT_KHR,VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, orVK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR -
VUID-VkMemoryBarrier2KHR-dstAccessMask-03904
IfdstAccessMaskincludesVK_ACCESS_2_UNIFORM_READ_BIT_KHR,dstStageMaskmust includeVK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR,VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR, or one of theVK_PIPELINE_STAGE_*_SHADER_BITstages -
VUID-VkMemoryBarrier2KHR-dstAccessMask-03905
IfdstAccessMaskincludesVK_ACCESS_2_SHADER_SAMPLED_READ_BIT_KHR,dstStageMaskmust includeVK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR,VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR, or one of theVK_PIPELINE_STAGE_*_SHADER_BITstages -
VUID-VkMemoryBarrier2KHR-dstAccessMask-03906
IfdstAccessMaskincludesVK_ACCESS_2_SHADER_STORAGE_READ_BIT_KHR,dstStageMaskmust includeVK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR,VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR, or one of theVK_PIPELINE_STAGE_*_SHADER_BITstages -
VUID-VkMemoryBarrier2KHR-dstAccessMask-03907
IfdstAccessMaskincludesVK_ACCESS_2_SHADER_STORAGE_WRITE_BIT_KHR,dstStageMaskmust includeVK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR,VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR, or one of theVK_PIPELINE_STAGE_*_SHADER_BITstages -
VUID-VkMemoryBarrier2KHR-dstAccessMask-03908
IfdstAccessMaskincludesVK_ACCESS_2_SHADER_READ_BIT_KHR,dstStageMaskmust includeVK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR,VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR,VK_PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR, or one of theVK_PIPELINE_STAGE_*_SHADER_BITstages -
VUID-VkMemoryBarrier2KHR-dstAccessMask-03909
IfdstAccessMaskincludesVK_ACCESS_2_SHADER_WRITE_BIT_KHR,dstStageMaskmust includeVK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR,VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR, or one of theVK_PIPELINE_STAGE_*_SHADER_BITstages -
VUID-VkMemoryBarrier2KHR-dstAccessMask-03910
IfdstAccessMaskincludesVK_ACCESS_2_COLOR_ATTACHMENT_READ_BIT_KHR,dstStageMaskmust includeVK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT_KHRVK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, orVK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR -
VUID-VkMemoryBarrier2KHR-dstAccessMask-03911
IfdstAccessMaskincludesVK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT_KHR,dstStageMaskmust includeVK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT_KHRVK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, orVK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR -
VUID-VkMemoryBarrier2KHR-dstAccessMask-03912
IfdstAccessMaskincludesVK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_READ_BIT_KHR,dstStageMaskmust includeVK_PIPELINE_STAGE_2_EARLY_FRAGMENT_TESTS_BIT_KHR,VK_PIPELINE_STAGE_2_LATE_FRAGMENT_TESTS_BIT_KHR,VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, orVK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR -
VUID-VkMemoryBarrier2KHR-dstAccessMask-03913
IfdstAccessMaskincludesVK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT_KHR,dstStageMaskmust includeVK_PIPELINE_STAGE_2_EARLY_FRAGMENT_TESTS_BIT_KHR,VK_PIPELINE_STAGE_2_LATE_FRAGMENT_TESTS_BIT_KHR,VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, orVK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR -
VUID-VkMemoryBarrier2KHR-dstAccessMask-03914
IfdstAccessMaskincludesVK_ACCESS_2_TRANSFER_READ_BIT_KHR,dstStageMaskmust includeVK_PIPELINE_STAGE_2_COPY_BIT_KHR,VK_PIPELINE_STAGE_2_BLIT_BIT_KHR,VK_PIPELINE_STAGE_2_RESOLVE_BIT_KHR,VK_PIPELINE_STAGE_2_ALL_TRANSFER_BIT_KHR,VK_PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR, orVK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR -
VUID-VkMemoryBarrier2KHR-dstAccessMask-03915
IfdstAccessMaskincludesVK_ACCESS_2_TRANSFER_WRITE_BIT_KHR,dstStageMaskmust includeVK_PIPELINE_STAGE_2_COPY_BIT_KHR,VK_PIPELINE_STAGE_2_BLIT_BIT_KHR,VK_PIPELINE_STAGE_2_RESOLVE_BIT_KHR,VK_PIPELINE_STAGE_2_CLEAR_BIT_KHR,VK_PIPELINE_STAGE_2_ALL_TRANSFER_BIT_KHR,VK_PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR, orVK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR -
VUID-VkMemoryBarrier2KHR-dstAccessMask-03916
IfdstAccessMaskincludesVK_ACCESS_2_HOST_READ_BIT_KHR,dstStageMaskmust includeVK_PIPELINE_STAGE_2_HOST_BIT_KHR -
VUID-VkMemoryBarrier2KHR-dstAccessMask-03917
IfdstAccessMaskincludesVK_ACCESS_2_HOST_WRITE_BIT_KHR,dstStageMaskmust includeVK_PIPELINE_STAGE_2_HOST_BIT_KHR -
VUID-VkMemoryBarrier2KHR-dstAccessMask-03918
IfdstAccessMaskincludesVK_ACCESS_2_CONDITIONAL_RENDERING_READ_BIT_EXT,dstStageMaskmust includeVK_PIPELINE_STAGE_2_CONDITIONAL_RENDERING_BIT_EXT,VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, orVK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR -
VUID-VkMemoryBarrier2KHR-dstAccessMask-03919
IfdstAccessMaskincludesVK_ACCESS_2_FRAGMENT_DENSITY_MAP_READ_BIT_EXT,dstStageMaskmust includeVK_PIPELINE_STAGE_2_FRAGMENT_DENSITY_PROCESS_BIT_EXT,VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, orVK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR -
VUID-VkMemoryBarrier2KHR-dstAccessMask-03920
IfdstAccessMaskincludesVK_ACCESS_2_TRANSFORM_FEEDBACK_WRITE_BIT_EXT,dstStageMaskmust includeVK_PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT,VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, orVK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR -
VUID-VkMemoryBarrier2KHR-dstAccessMask-03921
IfdstAccessMaskincludesVK_ACCESS_2_TRANSFORM_FEEDBACK_COUNTER_READ_BIT_EXT,dstStageMaskmust includeVK_PIPELINE_STAGE_2_DRAW_INDIRECT_BIT_KHR,VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, orVK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR -
VUID-VkMemoryBarrier2KHR-dstAccessMask-03922
IfdstAccessMaskincludesVK_ACCESS_2_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT,dstStageMaskmust includeVK_PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT,VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, orVK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR -
VUID-VkMemoryBarrier2KHR-dstAccessMask-03923
IfdstAccessMaskincludesVK_ACCESS_2_SHADING_RATE_IMAGE_READ_BIT_NV,dstStageMaskmust includeVK_PIPELINE_STAGE_2_SHADING_RATE_IMAGE_BIT_NV,VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, orVK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR -
VUID-VkMemoryBarrier2KHR-dstAccessMask-03924
IfdstAccessMaskincludesVK_ACCESS_2_COMMAND_PREPROCESS_READ_BIT_NV,dstStageMaskmust includeVK_PIPELINE_STAGE_2_COMMAND_PREPROCESS_BIT_NVorVK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR -
VUID-VkMemoryBarrier2KHR-dstAccessMask-03925
IfdstAccessMaskincludesVK_ACCESS_2_COMMAND_PREPROCESS_WRITE_BIT_NV,dstStageMaskmust includeVK_PIPELINE_STAGE_2_COMMAND_PREPROCESS_BIT_NVorVK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR -
VUID-VkMemoryBarrier2KHR-dstAccessMask-03926
IfdstAccessMaskincludesVK_ACCESS_2_COLOR_ATTACHMENT_READ_NONCOHERENT_BIT_EXT,dstStageMaskmust includeVK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT_KHRVK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR, orVK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR -
VUID-VkMemoryBarrier2KHR-dstAccessMask-03927
IfdstAccessMaskincludesVK_ACCESS_2_ACCELERATION_STRUCTURE_READ_BIT_KHR,dstStageMaskmust includeVK_PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR,VK_PIPELINE_STAGE_2_RAY_TRACING_SHADER_BIT_KHR, orVK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR -
VUID-VkMemoryBarrier2KHR-dstAccessMask-03928
IfdstAccessMaskincludesVK_ACCESS_2_ACCELERATION_STRUCTURE_WRITE_BIT_KHR,dstStageMaskmust includeVK_PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHRorVK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR
Document Notes
For more information, see the Vulkan Specification
This page is extracted from the Vulkan Specification. Fixes and changes should be made to the Specification, not directly.