PIC18F96J60
Author: Molnár Károly

All Enhanced Extended Regular 12 bits 14 bits 16 bits RAM
size ROM
size EEPROM
size Common
SFRs
Features Configuration Bits RAM map SFR map

PIC18F96J60
CONFIG1L (address:0x00FFF8, mask:0xE1, default:0xE1)
WDT -- Watchdog Timer Enable bit (bitmask:0x01)
WDT = OFF | 0x00 | WDT disabled (control is placed on SWDTEN bit).
WDT = ON | 0x01 | WDT enabled.
STVR -- Stack Overflow/Underflow Reset Enable bit (bitmask:0x20)
STVR = OFF | 0x00 | Reset on stack overflow/underflow disabled.
STVR = ON | 0x20 | Reset on stack overflow/underflow enabled.
XINST -- Extended Instruction Set Enable bit (bitmask:0x40)
XINST = OFF | 0x00 | Instruction set extension and Indexed Addressing mode disabled (Legacy mode).
XINST = ON | 0x40 | Instruction set extension and Indexed Addressing mode enabled.
DEBUG -- Background Debugger Enable bit (bitmask:0x80)
DEBUG = ON | 0x00 | Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug.
DEBUG = OFF | 0x80 | Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins.
CONFIG1H (address:0x00FFF9, mask:0x04, default:0x04)
CP0 -- Code Protection bit (bitmask:0x04)
CP0 = ON | 0x00 | Program memory is code-protected.
CP0 = OFF | 0x04 | Program memory is not code-protected.
CONFIG2L (address:0x00FFFA, mask:0xC7, default:0xC7)
FOSC -- Oscillator Selection bits (bitmask:0x03)
FOSC = HS | 0x00 | HS oscillator.
FOSC = HSPLL | 0x01 | HS oscillator, PLL enabled and under software control.
FOSC = EC | 0x02 | EC oscillator, CLKO function on OSC2.
FOSC = ECPLL | 0x03 | EC oscillator, PLL enabled and under software control, CLKO function on OSC2.
FOSC2 -- Default/Reset System Clock Select bit (bitmask:0x04)
FOSC2 = OFF | 0x00 | INTRC enabled as system clock when OSCCON<1:0> = 00.
FOSC2 = ON | 0x04 | Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00.
FCMEN -- Fail-Safe Clock Monitor Enable (bitmask:0x40)
FCMEN = OFF | 0x00 | Fail-Safe Clock Monitor disabled.
FCMEN = ON | 0x40 | Fail-Safe Clock Monitor enabled.
IESO -- Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit (bitmask:0x80)
IESO = OFF | 0x00 | Two-Speed Start-up disabled.
IESO = ON | 0x80 | Two-Speed Start-up enabled.
CONFIG2H (address:0x00FFFB, mask:0x0F, default:0x0F)
WDTPS -- Watchdog Timer Postscaler Select bits (bitmask:0x0F)
WDTPS = 1 | 0x00 | 1:1.
WDTPS = 2 | 0x01 | 1:2.
WDTPS = 4 | 0x02 | 1:4.
WDTPS = 8 | 0x03 | 1:8.
WDTPS = 16 | 0x04 | 1:16.
WDTPS = 32 | 0x05 | 1:32.
WDTPS = 64 | 0x06 | 1:64.
WDTPS = 128 | 0x07 | 1:128.
WDTPS = 256 | 0x08 | 1:256.
WDTPS = 512 | 0x09 | 1:512.
WDTPS = 1024 | 0x0A | 1:1024.
WDTPS = 2048 | 0x0B | 1:2048.
WDTPS = 4096 | 0x0C | 1:4096.
WDTPS = 8192 | 0x0D | 1:8192.
WDTPS = 16384 | 0x0E | 1:16384.
WDTPS = 32768 | 0x0F | 1:32768.
CONFIG3L (address:0x00FFFC, mask:0xF8, default:0xF8)
EASHFT -- External Address Bus Shift Enable bit (bitmask:0x08)
EASHFT = OFF | 0x00 | Address shifting disabled; address on external bus reflects the PC value.
EASHFT = ON | 0x08 | Address shifting enabled; address on external bus is offset to start at 000000h.
MODE -- External Memory Bus (bitmask:0x30)
MODE = XM20 | 0x00 | Extended Microcontroller mode, 20-Bit Address mode.
MODE = XM16 | 0x10 | Extended Microcontroller mode,16-Bit Address mode.
MODE = XM12 | 0x20 | Extended Microcontroller mode,12-Bit Address mode.
MODE = MM | 0x30 | Microcontroller mode, external bus disabled.
BW -- Data Bus Width Select bit (bitmask:0x40)
BW = 8 | 0x00 | 8-Bit Data Width mode.
BW = 16 | 0x40 | 16-Bit Data Width mode.
WAIT -- External Bus Wait Enable bit (bitmask:0x80)
WAIT = ON | 0x00 | Wait states for operations on external memory bus enabled and selected by MEMCON<5:4>.
WAIT = OFF | 0x80 | Wait states for operations on external memory bus disabled.
CONFIG3H (address:0x00FFFD, mask:0x07, default:0x07)
CCP2MX -- ECCP2 MUX bit (bitmask:0x01)
CCP2MX = OFF | 0x00 | ECCP2/P2A is multiplexed with RE7 in Microcontroller mode (80-pin and 100-pin devices) or with RB3 in Extended Microcontroller mode (100-pin devices only).
CCP2MX = ON | 0x01 | ECCP2/P2A is multiplexed with RC1.
ECCPMX -- ECCP MUX bit (bitmask:0x02)
ECCPMX = OFF | 0x00 | ECCP1 outputs (P1B/P1C) are multiplexed with RH7 and RH6; ECCP3 outputs (P3B/P3C) are multiplexed with RH5 and RH4.
ECCPMX = ON | 0x02 | ECCP1 outputs (P1B/P1C) are multiplexed with RE6 and RE5; ECCP3 outputs (P3B/P3C) are multiplexed with RE4 and RE3.
ETHLED -- Ethernet LED Enable bit (bitmask:0x04)
ETHLED = OFF | 0x00 | RA0/RA1 function as I/O regardless of Ethernet module status.
ETHLED = ON | 0x04 | RA0/RA1 are multiplexed with LEDA/LEDB when Ethernet module is enabled and function as I/O when Ethernet is disabled.

This page generated automatically by the device-help.pl program (2014-09-27 07:53:48 UTC) from the 8bit_device.info file (rev: 1.21) of mpasmx and from the gputils source package (rev: svn 1103). The mpasmx is included in the MPLAB X.