# AMD Family 14 processor performance events
#
# Copyright OProfile authors
# Copyright (c) 2006-2011 Advanced Micro Devices
# Contributed by Ray Bryant <raybry at amd.com>,
#		Jason Yeh <jason.yeh at amd.com>
#		Suravee Suthikulpanit <suravee.suthikulpanit at amd.com>
#		Paul Drongowski <paul.drongowski at amd.com>
#
# Sources: BIOS and Kernel Developer's Guide for AMD Family 14h Processors,
#          Publication# 43170, Revision 3.04, Feb 16, 2011
#
# Revision: 1.3
#
# ChangeLog:
# 	1.3: 11 August 2014
# 	- Remove IBS events due to missing support in Operf
#
#	1.2: 11 March 2011
# 	- Update to BKDG Rev.3.04
#
#	1.1: 25 January 2011.
#	- Update to BKDG Revision 3.00
#       - Update minimum value for RETIRED_UOPS
#
#	1.0: 29 November 2010.
# 	- Preliminary version
event:0x000 counters:0,1,2,3 um:fpu_ops minimum:500 name:DISPATCHED_FPU_OPS : Dispatched FPU Operations
event:0x001 counters:0,1,2,3 um:zero minimum:500 name:CYCLES_FPU_EMPTY : Cycles in which the FPU is Empty
event:0x002 counters:0,1,2,3 um:zero minimum:500 name:DISPATCHED_FPU_OPS_FAST_FLAG : Dispatched Fast Flag FPU Operations
event:0x003 counters:0,1,2,3 um:sse_ops minimum:500 name:RETIRED_SSE_OPS : Retired SSE Operations
event:0x004 counters:0,1,2,3 um:move_ops minimum:500 name:RETIRED_MOVE_OPS : Retired Move Ops
event:0x005 counters:0,1,2,3 um:serial_ops minimum:500 name:RETIRED_SERIALIZING_OPS : Retired Serializing Ops
event:0x011 counters:0,1,2,3 um:retired_x87_fp minimum:500 name:RETIRED_X87_FP_OPS : Retired x87 Floating Point Operations
event:0x020 counters:0,1,2,3 um:segregload minimum:500 name:SEGMENT_REGISTER_LOADS : Segment Register Loads
event:0x021 counters:0,1,2,3 um:zero minimum:500 name:PIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODE : Pipeline Restart Due to Self-Modifying Code
event:0x022 counters:0,1,2,3 um:zero minimum:500 name:PIPELINE_RESTART_DUE_TO_PROBE_HIT : Pipeline Restart Due to Probe Hit
event:0x023 counters:0,1,2,3 um:zero minimum:500 name:RSQ_FULL : RSQ Full
event:0x024 counters:0,1,2,3 um:lock_ops minimum:500 name:LOCKED_OPS : Locked Operations
event:0x026 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_CLFLUSH_INSTRUCTIONS : Retired CLFLUSH Instructions
event:0x027 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_CPUID_INSTRUCTIONS : Retired CPUID Instructions
event:0x02a counters:0,1,2,3 um:store_to_load minimum:500 name:CANCELLED_STORE_TO_LOAD : Store to Load Forward Operations Block Loads
event:0x040 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_ACCESSES : Data Cache Accesses
event:0x041 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_MISSES : Data Cache Misses
event:0x042 counters:0,1,2,3 um:moess minimum:500 name:DATA_CACHE_REFILLS_FROM_L2_OR_NORTHBRIDGE : Data Cache Refills from L2 or Northbridge
event:0x043 counters:0,1,2,3 um:moesi minimum:500 name:DATA_CACHE_REFILLS_FROM_NORTHBRIDGE : Data Cache Refills from the northbridge
event:0x044 counters:0,1,2,3 um:moesi_gh minimum:500 name:DATA_CACHE_LINES_EVICTED : Data Cache Lines Evicted
event:0x045 counters:0,1,2,3 um:zero minimum:500 name:L1_DTLB_MISS_AND_L2_DTLB_HIT : L1 DTLB Miss and L2 DTLB Hit
event:0x046 counters:0,1,2,3 um:l1_l2_dtlb_miss minimum:500 name:DTLB_MISS : DTLB Miss
event:0x047 counters:0,1,2,3 um:zero minimum:500 name:MISALIGNED_ACCESSES : Misaligned Accesses
event:0x04b counters:0,1,2,3 um:prefetch minimum:500 name:PREFETCH_INSTRUCTIONS_DISPATCHED : Prefetch Instructions Dispatched
event:0x04c counters:0,1,2,3 um:zero minimum:500 name:LOCKED_INSTRUCTIONS_DCACHE_MISSES : DCACHE Misses by Locked Instructions
event:0x04d counters:0,1,2,3 um:l1_dtlb_hit minimum:500 name:L1_DTLB_HIT : L1 DTLB Hit
event:0x052 counters:0,1,2,3 um:soft_prefetch minimum:500 name:INEFFECTIVE_SW_PREFETCHES : DCACHE Ineffective Software Prefetches
event:0x054 counters:0,1,2,3 um:zero minimum:500 name:GLOBAL_TLB_FLUSHES : Global Page Invalidations
event:0x065 counters:0,1,2,3 um:memreqtype minimum:500 name:MEMORY_REQUESTS : Memory Requests by Type
event:0x068 counters:0,1,2,3 um:mab_buffer minimum:500 name:MAB_REQS : MAB Requests
event:0x069 counters:0,1,2,3 um:mab_buffer minimum:500 name:MAB_WAIT : MAB Wait Cycles
event:0x06c counters:0,1,2,3 um:systemreadresponse minimum:500 name:NORTHBRIDGE_READ_RESPONSES : System Response by Coherence State
event:0x076 counters:0,1,2,3 um:zero minimum:50000 name:CPU_CLK_UNHALTED : CPU Clocks not Halted
event:0x07d counters:0,1,2,3 um:l2_internal minimum:500 name:REQUESTS_TO_L2 : Requests to L2 Cache
event:0x07e counters:0,1,2,3 um:l2_req_miss minimum:500 name:L2_CACHE_MISS : L2 Cache Misses
event:0x07f counters:0,1,2,3 um:l2_fill minimum:500 name:L2_CACHE_FILL_WRITEBACK : L2 Fill/Writeback
event:0x162 counters:0,1,2,3 um:pdc_miss minimum:500 name:PDC_MISS : PDC Miss
event:0x080 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_CACHE_FETCHES : Instruction Cache Fetches
event:0x081 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_CACHE_MISSES : Instruction Cache Misses
event:0x082 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_CACHE_REFILLS_FROM_L2 : Instruction Cache Refills from L2
event:0x083 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM : Instruction Cache Refills from System
event:0x085 counters:0,1,2,3 um:l1_l2_itlb_miss minimum:500 name:ITLB_MISS : ITLB Miss
event:0x087 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_FETCH_STALL : Instruction Fetch Stall
event:0x088 counters:0,1,2,3 um:zero minimum:500 name:RETURN_STACK_HITS : Return Stack Hits
event:0x089 counters:0,1,2,3 um:zero minimum:500 name:RETURN_STACK_OVERFLOWS : Return Stack Overflows
event:0x08b counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_CACHE_VICTIMS : Instruction Cache Victims
event:0x08c counters:0,1,2,3 um:icache_invalidated minimum:500 name:INSTRUCTION_CACHE_INVALIDATED : Instruction Cache Lines Invalidated
event:0x099 counters:0,1,2,3 um:zero minimum:500 name:ITLB_RELOADS : ITLB Reloads
event:0x09a counters:0,1,2,3 um:zero minimum:500 name:ITLB_RELOADS_ABORTED : ITLB Reloads Aborted
event:0x0c0 counters:0,1,2,3 um:zero minimum:50000 name:RETIRED_INSTRUCTIONS : Retired Instructions
event:0x0c1 counters:0,1,2,3 um:zero minimum:50000 name:RETIRED_UOPS : Retired uops
event:0x0c2 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_BRANCH_INSTRUCTIONS : Retired Branch Instructions
event:0x0c3 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS : Retired Mispredicted Branch Instructions
event:0x0c4 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_TAKEN_BRANCH_INSTRUCTIONS : Retired Taken Branch Instructions
event:0x0c5 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTED : Retired Taken Branch Instructions Mispredicted
event:0x0c6 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_FAR_CONTROL_TRANSFERS : Retired Far Control Transfers
event:0x0c7 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_BRANCH_RESYNCS : Retired Branch Resyncs
event:0x0c8 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_NEAR_RETURNS : Retired Near Returns
event:0x0c9 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_NEAR_RETURNS_MISPREDICTED : Retired Near Returns Mispredicted
event:0x0ca counters:0,1,2,3 um:zero minimum:500 name:RETIRED_INDIRECT_BRANCHES_MISPREDICTED : Retired Mispredicted Taken Branch Instructions due to Target Mismatch
event:0x0cb counters:0,1,2,3 um:fpu_instr minimum:500 name:RETIRED_MMX_FP_INSTRUCTIONS : Retired a Floating Point Instruction
event:0x0cd counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_MASKED_CYCLES : Interrupts-Masked Cycles
event:0x0ce counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING : Interrupts-Masked Cycles with Interrupt Pending
event:0x0cf counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_TAKEN : Interrupts Taken
event:0x0db counters:0,1,2,3 um:fpu_exceptions minimum:500 name:FPU_EXCEPTIONS : FPU Exceptions
event:0x0dc counters:0,1,2,3 um:zero minimum:500 name:DR0_BREAKPOINTS : DR0 Breakpoint Matches
event:0x0dd counters:0,1,2,3 um:zero minimum:500 name:DR1_BREAKPOINTS : DR1 Breakpoint Matches
event:0x0de counters:0,1,2,3 um:zero minimum:500 name:DR2_BREAKPOINTS : DR2 Breakpoint Matches
event:0x0df counters:0,1,2,3 um:zero minimum:500 name:DR3_BREAKPOINTS : DR3 Breakpoint Matches
event:0x0e0 counters:0,1,2,3 um:page_access minimum:500 name:DRAM_ACCESSES : DRAM Accesses
event:0x0e1 counters:0,1,2,3 um:mem_page_overflow minimum:500 name:DCT0_PAGE_TABLE_EVENTS : DRAM Controller Page Table Events
event:0x0e2 counters:0,1,2,3 um:slot_missed minimum:500 name:MEMORY_CONTROLLER_SLOT_MISSED : Memory Controller DRAM Command Slots Missed
event:0x0e3 counters:0,1,2,3 um:turnaround minimum:500 name:MEMORY_CONTROLLER_TURNAROUNDS : Memory Controller Turnarounds
event:0x0e4 counters:0,1,2,3 um:saturation minimum:500 name:MEMORY_CONTROLLER_RBD_QUEUE_EVENTS : Memory Controller RBD Queue Events
event:0x0e8 counters:0,1,2,3 um:thermal_status minimum:500 name:THERMAL_STATUS : Thermal Status
event:0x0e9 counters:0,1,2,3 um:cpiorequests minimum:500 name:CPU_IO_REQUESTS_TO_MEMORY_IO : CPU/IO Requests to Memory/IO
event:0x0ea counters:0,1,2,3 um:cacheblock minimum:500 name:CACHE_BLOCK_COMMANDS : Cache Block Commands
event:0x0eb counters:0,1,2,3 um:sizecmds minimum:500 name:SIZED_COMMANDS : Sized Commands
event:0x0ec counters:0,1,2,3 um:probe minimum:500 name:PROBE_RESPONSES_AND_UPSTREAM_REQUESTS : Probe Responses and Upstream Requests
event:0x0ee counters:0,1,2,3 um:gart minimum:500 name:DEV_EVENTS : DEV Events
event:0x1f0 counters:0,1,2,3 um:mem_control_request minimum:500 name:MEMORY_CONTROLLER_REQUESTS : Memory Controller Requests
event:0x1e9 counters:0,1,2,3 um:sideband_signals minimum:500 name:SIDEBAND_SIGNALS : Sideband Signals and Special Cycles
event:0x1ea counters:0,1,2,3 um:interrupt_events minimum:500 name:INTERRUPT_EVENTS : Interrupt Events
