/**
 * This file is automaticly generated by genregs.awk. Please do not edit it 
 * Base files are ../ucode/register.h ../ucode/dos_register.h 
 *   ../ucode/c_always_on_pointer.h ../ucode/ddr3_reg.h 
 *   ../ucode/dmc_reg.h 
 *   ../ucode/c_stb_define.h ../ucode/secure_apb.h from VLSI team
 * Sat Feb  8 16:58:10 CST 2014 
 */
#ifndef __MACH_MESON8_REG_ADDR_H_
#define __MACH_MESON8_REG_ADDR_H_
#define STB_TOP_CONFIG 0x16f0 	///../ucode/register.h:68
#define P_STB_TOP_CONFIG 		CBUS_REG_ADDR(STB_TOP_CONFIG)
#define TS_TOP_CONFIG 0x16f1 	///../ucode/register.h:81
#define P_TS_TOP_CONFIG 		CBUS_REG_ADDR(TS_TOP_CONFIG)
#define TS_FILE_CONFIG 0x16f2 	///../ucode/register.h:87
#define P_TS_FILE_CONFIG 		CBUS_REG_ADDR(TS_FILE_CONFIG)
#define TS_PL_PID_INDEX 0x16f3 	///../ucode/register.h:91
#define P_TS_PL_PID_INDEX 		CBUS_REG_ADDR(TS_PL_PID_INDEX)
#define TS_PL_PID_DATA 0x16f4 	///../ucode/register.h:94
#define P_TS_PL_PID_DATA 		CBUS_REG_ADDR(TS_PL_PID_DATA)
#define COMM_DESC_KEY0 0x16f5 	///../ucode/register.h:95
#define P_COMM_DESC_KEY0 		CBUS_REG_ADDR(COMM_DESC_KEY0)
#define COMM_DESC_KEY1 0x16f6 	///../ucode/register.h:96
#define P_COMM_DESC_KEY1 		CBUS_REG_ADDR(COMM_DESC_KEY1)
#define COMM_DESC_KEY_RW 0x16f7 	///../ucode/register.h:97
#define P_COMM_DESC_KEY_RW 		CBUS_REG_ADDR(COMM_DESC_KEY_RW)
#define CIPLUS_KEY0 0x16f8 	///../ucode/register.h:100
#define P_CIPLUS_KEY0 		CBUS_REG_ADDR(CIPLUS_KEY0)
#define CIPLUS_KEY1 0x16f9 	///../ucode/register.h:102
#define P_CIPLUS_KEY1 		CBUS_REG_ADDR(CIPLUS_KEY1)
#define CIPLUS_KEY2 0x16fa 	///../ucode/register.h:104
#define P_CIPLUS_KEY2 		CBUS_REG_ADDR(CIPLUS_KEY2)
#define CIPLUS_KEY3 0x16fb 	///../ucode/register.h:106
#define P_CIPLUS_KEY3 		CBUS_REG_ADDR(CIPLUS_KEY3)
#define CIPLUS_KEY_WR 0x16fc 	///../ucode/register.h:113
#define P_CIPLUS_KEY_WR 		CBUS_REG_ADDR(CIPLUS_KEY_WR)
#define CIPLUS_CONFIG 0x16fd 	///../ucode/register.h:119
#define P_CIPLUS_CONFIG 		CBUS_REG_ADDR(CIPLUS_CONFIG)
#define CIPLUS_ENDIAN 0x16fe 	///../ucode/register.h:128
#define P_CIPLUS_ENDIAN 		CBUS_REG_ADDR(CIPLUS_ENDIAN)
#define PREG_CTLREG0_ADDR 0x2000 	///../ucode/register.h:366
#define P_PREG_CTLREG0_ADDR 		CBUS_REG_ADDR(PREG_CTLREG0_ADDR)
#define PREG_PAD_GPIO6_EN_N 0x2008 	///../ucode/register.h:368
#define P_PREG_PAD_GPIO6_EN_N 		CBUS_REG_ADDR(PREG_PAD_GPIO6_EN_N)
#define PREG_PAD_GPIO6_O 0x2009 	///../ucode/register.h:369
#define P_PREG_PAD_GPIO6_O 		CBUS_REG_ADDR(PREG_PAD_GPIO6_O)
#define PREG_PAD_GPIO6_I 0x200a 	///../ucode/register.h:370
#define P_PREG_PAD_GPIO6_I 		CBUS_REG_ADDR(PREG_PAD_GPIO6_I)
#define PREG_JTAG_GPIO_ADDR 0x200b 	///../ucode/register.h:373
#define P_PREG_JTAG_GPIO_ADDR 		CBUS_REG_ADDR(PREG_JTAG_GPIO_ADDR)
#define PREG_PAD_GPIO0_EN_N 0x200c 	///../ucode/register.h:377
#define P_PREG_PAD_GPIO0_EN_N 		CBUS_REG_ADDR(PREG_PAD_GPIO0_EN_N)
#define PREG_PAD_GPIO0_O 0x200d 	///../ucode/register.h:378
#define P_PREG_PAD_GPIO0_O 		CBUS_REG_ADDR(PREG_PAD_GPIO0_O)
#define PREG_PAD_GPIO0_I 0x200e 	///../ucode/register.h:379
#define P_PREG_PAD_GPIO0_I 		CBUS_REG_ADDR(PREG_PAD_GPIO0_I)
#define PREG_PAD_GPIO1_EN_N 0x200f 	///../ucode/register.h:381
#define P_PREG_PAD_GPIO1_EN_N 		CBUS_REG_ADDR(PREG_PAD_GPIO1_EN_N)
#define PREG_PAD_GPIO1_O 0x2010 	///../ucode/register.h:382
#define P_PREG_PAD_GPIO1_O 		CBUS_REG_ADDR(PREG_PAD_GPIO1_O)
#define PREG_PAD_GPIO1_I 0x2011 	///../ucode/register.h:383
#define P_PREG_PAD_GPIO1_I 		CBUS_REG_ADDR(PREG_PAD_GPIO1_I)
#define PREG_PAD_GPIO2_EN_N 0x2012 	///../ucode/register.h:385
#define P_PREG_PAD_GPIO2_EN_N 		CBUS_REG_ADDR(PREG_PAD_GPIO2_EN_N)
#define PREG_PAD_GPIO2_O 0x2013 	///../ucode/register.h:386
#define P_PREG_PAD_GPIO2_O 		CBUS_REG_ADDR(PREG_PAD_GPIO2_O)
#define PREG_PAD_GPIO2_I 0x2014 	///../ucode/register.h:387
#define P_PREG_PAD_GPIO2_I 		CBUS_REG_ADDR(PREG_PAD_GPIO2_I)
#define PREG_PAD_GPIO3_EN_N 0x2015 	///../ucode/register.h:389
#define P_PREG_PAD_GPIO3_EN_N 		CBUS_REG_ADDR(PREG_PAD_GPIO3_EN_N)
#define PREG_PAD_GPIO3_O 0x2016 	///../ucode/register.h:390
#define P_PREG_PAD_GPIO3_O 		CBUS_REG_ADDR(PREG_PAD_GPIO3_O)
#define PREG_PAD_GPIO3_I 0x2017 	///../ucode/register.h:391
#define P_PREG_PAD_GPIO3_I 		CBUS_REG_ADDR(PREG_PAD_GPIO3_I)
#define PREG_PAD_GPIO4_EN_N 0x2018 	///../ucode/register.h:393
#define P_PREG_PAD_GPIO4_EN_N 		CBUS_REG_ADDR(PREG_PAD_GPIO4_EN_N)
#define PREG_PAD_GPIO4_O 0x2019 	///../ucode/register.h:394
#define P_PREG_PAD_GPIO4_O 		CBUS_REG_ADDR(PREG_PAD_GPIO4_O)
#define PREG_PAD_GPIO4_I 0x201a 	///../ucode/register.h:395
#define P_PREG_PAD_GPIO4_I 		CBUS_REG_ADDR(PREG_PAD_GPIO4_I)
#define PREG_PAD_GPIO5_EN_N 0x201b 	///../ucode/register.h:397
#define P_PREG_PAD_GPIO5_EN_N 		CBUS_REG_ADDR(PREG_PAD_GPIO5_EN_N)
#define PREG_PAD_GPIO5_O 0x201c 	///../ucode/register.h:398
#define P_PREG_PAD_GPIO5_O 		CBUS_REG_ADDR(PREG_PAD_GPIO5_O)
#define PREG_PAD_GPIO5_I 0x201d 	///../ucode/register.h:399
#define P_PREG_PAD_GPIO5_I 		CBUS_REG_ADDR(PREG_PAD_GPIO5_I)
#define A9_STATUS1 0x201f 	///../ucode/register.h:403
#define P_A9_STATUS1 		CBUS_REG_ADDR(A9_STATUS1)
#define A9_CFG0 0x2020 	///../ucode/register.h:404
#define P_A9_CFG0 		CBUS_REG_ADDR(A9_CFG0)
#define A9_CFG1 0x2021 	///../ucode/register.h:405
#define P_A9_CFG1 		CBUS_REG_ADDR(A9_CFG1)
#define A9_CFG2 0x2022 	///../ucode/register.h:406
#define P_A9_CFG2 		CBUS_REG_ADDR(A9_CFG2)
#define A9_PERIPH_BASE 0x2023 	///../ucode/register.h:407
#define P_A9_PERIPH_BASE 		CBUS_REG_ADDR(A9_PERIPH_BASE)
#define A9_L2_REG_BASE 0x2024 	///../ucode/register.h:408
#define P_A9_L2_REG_BASE 		CBUS_REG_ADDR(A9_L2_REG_BASE)
#define A9_L2_STATUS 0x2025 	///../ucode/register.h:409
#define P_A9_L2_STATUS 		CBUS_REG_ADDR(A9_L2_STATUS)
#define A9_POR_CFG 0x2026 	///../ucode/register.h:410
#define P_A9_POR_CFG 		CBUS_REG_ADDR(A9_POR_CFG)
#define A9_STATUS2 0x2027 	///../ucode/register.h:411
#define P_A9_STATUS2 		CBUS_REG_ADDR(A9_STATUS2)
#define AXI_REG_EN 0x2028 	///../ucode/register.h:412
#define P_AXI_REG_EN 		CBUS_REG_ADDR(AXI_REG_EN)
#define A9_CFG3 0x2029 	///../ucode/register.h:413
#define P_A9_CFG3 		CBUS_REG_ADDR(A9_CFG3)
#define A9_CFG4 0x202a 	///../ucode/register.h:414
#define P_A9_CFG4 		CBUS_REG_ADDR(A9_CFG4)
#define A9_STATUS3 0x202b 	///../ucode/register.h:415
#define P_A9_STATUS3 		CBUS_REG_ADDR(A9_STATUS3)
#define PERIPHS_PIN_MUX_0 0x202c 	///../ucode/register.h:419
#define P_PERIPHS_PIN_MUX_0 		CBUS_REG_ADDR(PERIPHS_PIN_MUX_0)
#define PERIPHS_PIN_MUX_1 0x202d 	///../ucode/register.h:420
#define P_PERIPHS_PIN_MUX_1 		CBUS_REG_ADDR(PERIPHS_PIN_MUX_1)
#define PERIPHS_PIN_MUX_2 0x202e 	///../ucode/register.h:421
#define P_PERIPHS_PIN_MUX_2 		CBUS_REG_ADDR(PERIPHS_PIN_MUX_2)
#define PERIPHS_PIN_MUX_3 0x202f 	///../ucode/register.h:422
#define P_PERIPHS_PIN_MUX_3 		CBUS_REG_ADDR(PERIPHS_PIN_MUX_3)
#define PERIPHS_PIN_MUX_4 0x2030 	///../ucode/register.h:423
#define P_PERIPHS_PIN_MUX_4 		CBUS_REG_ADDR(PERIPHS_PIN_MUX_4)
#define PERIPHS_PIN_MUX_5 0x2031 	///../ucode/register.h:424
#define P_PERIPHS_PIN_MUX_5 		CBUS_REG_ADDR(PERIPHS_PIN_MUX_5)
#define PERIPHS_PIN_MUX_6 0x2032 	///../ucode/register.h:425
#define P_PERIPHS_PIN_MUX_6 		CBUS_REG_ADDR(PERIPHS_PIN_MUX_6)
#define PERIPHS_PIN_MUX_7 0x2033 	///../ucode/register.h:426
#define P_PERIPHS_PIN_MUX_7 		CBUS_REG_ADDR(PERIPHS_PIN_MUX_7)
#define PERIPHS_PIN_MUX_8 0x2034 	///../ucode/register.h:427
#define P_PERIPHS_PIN_MUX_8 		CBUS_REG_ADDR(PERIPHS_PIN_MUX_8)
#define PERIPHS_PIN_MUX_9 0x2035 	///../ucode/register.h:428
#define P_PERIPHS_PIN_MUX_9 		CBUS_REG_ADDR(PERIPHS_PIN_MUX_9)
#define PERIPHS_PIN_MUX_10 0x2036 	///../ucode/register.h:429
#define P_PERIPHS_PIN_MUX_10 		CBUS_REG_ADDR(PERIPHS_PIN_MUX_10)
#define PERIPHS_PIN_MUX_11 0x2037 	///../ucode/register.h:430
#define P_PERIPHS_PIN_MUX_11 		CBUS_REG_ADDR(PERIPHS_PIN_MUX_11)
#define PERIPHS_PIN_MUX_12 0x2038 	///../ucode/register.h:431
#define P_PERIPHS_PIN_MUX_12 		CBUS_REG_ADDR(PERIPHS_PIN_MUX_12)
#define PAD_PULL_UP_REG6 0x2039 	///../ucode/register.h:435
#define P_PAD_PULL_UP_REG6 		CBUS_REG_ADDR(PAD_PULL_UP_REG6)
#define PAD_PULL_UP_REG0 0x203a 	///../ucode/register.h:436
#define P_PAD_PULL_UP_REG0 		CBUS_REG_ADDR(PAD_PULL_UP_REG0)
#define PAD_PULL_UP_REG1 0x203b 	///../ucode/register.h:437
#define P_PAD_PULL_UP_REG1 		CBUS_REG_ADDR(PAD_PULL_UP_REG1)
#define PAD_PULL_UP_REG2 0x203c 	///../ucode/register.h:438
#define P_PAD_PULL_UP_REG2 		CBUS_REG_ADDR(PAD_PULL_UP_REG2)
#define PAD_PULL_UP_REG3 0x203d 	///../ucode/register.h:439
#define P_PAD_PULL_UP_REG3 		CBUS_REG_ADDR(PAD_PULL_UP_REG3)
#define PAD_PULL_UP_REG4 0x203e 	///../ucode/register.h:440
#define P_PAD_PULL_UP_REG4 		CBUS_REG_ADDR(PAD_PULL_UP_REG4)
#define PAD_PULL_UP_REG5 0x203f 	///../ucode/register.h:441
#define P_PAD_PULL_UP_REG5 		CBUS_REG_ADDR(PAD_PULL_UP_REG5)
#define RAND64_ADDR0 0x2040 	///../ucode/register.h:445
#define P_RAND64_ADDR0 		CBUS_REG_ADDR(RAND64_ADDR0)
#define RAND64_ADDR1 0x2041 	///../ucode/register.h:446
#define P_RAND64_ADDR1 		CBUS_REG_ADDR(RAND64_ADDR1)
#define PREG_ETHERNET_ADDR0 0x2042 	///../ucode/register.h:450
#define P_PREG_ETHERNET_ADDR0 		CBUS_REG_ADDR(PREG_ETHERNET_ADDR0)
#define PREG_AM_ANALOG_ADDR 0x2043 	///../ucode/register.h:454
#define P_PREG_AM_ANALOG_ADDR 		CBUS_REG_ADDR(PREG_AM_ANALOG_ADDR)
#define PREG_MALI_BYTE_CNTL 0x2044 	///../ucode/register.h:458
#define P_PREG_MALI_BYTE_CNTL 		CBUS_REG_ADDR(PREG_MALI_BYTE_CNTL)
#define PREG_WIFI_CNTL 0x2045 	///../ucode/register.h:462
#define P_PREG_WIFI_CNTL 		CBUS_REG_ADDR(PREG_WIFI_CNTL)
#define PAD_PULL_UP_EN_REG0 0x2048 	///../ucode/register.h:463
#define P_PAD_PULL_UP_EN_REG0 		CBUS_REG_ADDR(PAD_PULL_UP_EN_REG0)
#define PAD_PULL_UP_EN_REG1 0x2049 	///../ucode/register.h:464
#define P_PAD_PULL_UP_EN_REG1 		CBUS_REG_ADDR(PAD_PULL_UP_EN_REG1)
#define PAD_PULL_UP_EN_REG2 0x204a 	///../ucode/register.h:465
#define P_PAD_PULL_UP_EN_REG2 		CBUS_REG_ADDR(PAD_PULL_UP_EN_REG2)
#define PAD_PULL_UP_EN_REG3 0x204b 	///../ucode/register.h:466
#define P_PAD_PULL_UP_EN_REG3 		CBUS_REG_ADDR(PAD_PULL_UP_EN_REG3)
#define PAD_PULL_UP_EN_REG4 0x204c 	///../ucode/register.h:467
#define P_PAD_PULL_UP_EN_REG4 		CBUS_REG_ADDR(PAD_PULL_UP_EN_REG4)
#define PAD_PULL_UP_EN_REG5 0x204d 	///../ucode/register.h:468
#define P_PAD_PULL_UP_EN_REG5 		CBUS_REG_ADDR(PAD_PULL_UP_EN_REG5)
#define PAD_PULL_UP_EN_REG6 0x204e 	///../ucode/register.h:469
#define P_PAD_PULL_UP_EN_REG6 		CBUS_REG_ADDR(PAD_PULL_UP_EN_REG6)
#define PREG_ETH_REG0 0x2050 	///../ucode/register.h:473
#define P_PREG_ETH_REG0 		CBUS_REG_ADDR(PREG_ETH_REG0)
#define PREG_ETH_REG1 0x2051 	///../ucode/register.h:474
#define P_PREG_ETH_REG1 		CBUS_REG_ADDR(PREG_ETH_REG1)
#define PROD_TEST_REG0 0x2068 	///../ucode/register.h:482
#define P_PROD_TEST_REG0 		CBUS_REG_ADDR(PROD_TEST_REG0)
#define PROD_TEST_REG1 0x2067 	///../ucode/register.h:483
#define P_PROD_TEST_REG1 		CBUS_REG_ADDR(PROD_TEST_REG1)
#define METAL_REVISION 0x206a 	///../ucode/register.h:487
#define P_METAL_REVISION 		CBUS_REG_ADDR(METAL_REVISION)
#define ADC_TOP_MISC 0x206b 	///../ucode/register.h:488
#define P_ADC_TOP_MISC 		CBUS_REG_ADDR(ADC_TOP_MISC)
#define DPLL_TOP_MISC 0x206c 	///../ucode/register.h:489
#define P_DPLL_TOP_MISC 		CBUS_REG_ADDR(DPLL_TOP_MISC)
#define ANALOG_TOP_MISC 0x206d 	///../ucode/register.h:490
#define P_ANALOG_TOP_MISC 		CBUS_REG_ADDR(ANALOG_TOP_MISC)
#define AM_ANALOG_TOP_REG0 0x206e 	///../ucode/register.h:491
#define P_AM_ANALOG_TOP_REG0 		CBUS_REG_ADDR(AM_ANALOG_TOP_REG0)
#define AM_ANALOG_TOP_REG1 0x206f 	///../ucode/register.h:492
#define P_AM_ANALOG_TOP_REG1 		CBUS_REG_ADDR(AM_ANALOG_TOP_REG1)
#define PREG_STICKY_REG0 0x207c 	///../ucode/register.h:496
#define P_PREG_STICKY_REG0 		CBUS_REG_ADDR(PREG_STICKY_REG0)
#define PREG_STICKY_REG1 0x207d 	///../ucode/register.h:497
#define P_PREG_STICKY_REG1 		CBUS_REG_ADDR(PREG_STICKY_REG1)
#define PREG_WRITE_ONCE_REG 0x207e 	///../ucode/register.h:498
#define P_PREG_WRITE_ONCE_REG 		CBUS_REG_ADDR(PREG_WRITE_ONCE_REG)
#define AM_RING_OSC_REG0 0x207f 	///../ucode/register.h:502
#define P_AM_RING_OSC_REG0 		CBUS_REG_ADDR(AM_RING_OSC_REG0)
#define SMARTCARD_REG0 0x2110 	///../ucode/register.h:532
#define P_SMARTCARD_REG0 		CBUS_REG_ADDR(SMARTCARD_REG0)
#define SMARTCARD_REG1 0x2111 	///../ucode/register.h:533
#define P_SMARTCARD_REG1 		CBUS_REG_ADDR(SMARTCARD_REG1)
#define SMARTCARD_REG2 0x2112 	///../ucode/register.h:534
#define P_SMARTCARD_REG2 		CBUS_REG_ADDR(SMARTCARD_REG2)
#define SMARTCARD_STATUS 0x2113 	///../ucode/register.h:535
#define P_SMARTCARD_STATUS 		CBUS_REG_ADDR(SMARTCARD_STATUS)
#define SMARTCARD_INTR 0x2114 	///../ucode/register.h:536
#define P_SMARTCARD_INTR 		CBUS_REG_ADDR(SMARTCARD_INTR)
#define SMARTCARD_REG5 0x2115 	///../ucode/register.h:537
#define P_SMARTCARD_REG5 		CBUS_REG_ADDR(SMARTCARD_REG5)
#define SMARTCARD_REG6 0x2116 	///../ucode/register.h:538
#define P_SMARTCARD_REG6 		CBUS_REG_ADDR(SMARTCARD_REG6)
#define SMARTCARD_FIFO 0x2117 	///../ucode/register.h:539
#define P_SMARTCARD_FIFO 		CBUS_REG_ADDR(SMARTCARD_FIFO)
#define SMARTCARD_REG8 0x2118 	///../ucode/register.h:540
#define P_SMARTCARD_REG8 		CBUS_REG_ADDR(SMARTCARD_REG8)
#define IR_DEC_LDR_ACTIVE 0x2120 	///../ucode/register.h:544
#define P_IR_DEC_LDR_ACTIVE 		CBUS_REG_ADDR(IR_DEC_LDR_ACTIVE)
#define IR_DEC_LDR_IDLE 0x2121 	///../ucode/register.h:545
#define P_IR_DEC_LDR_IDLE 		CBUS_REG_ADDR(IR_DEC_LDR_IDLE)
#define IR_DEC_LDR_REPEAT 0x2122 	///../ucode/register.h:546
#define P_IR_DEC_LDR_REPEAT 		CBUS_REG_ADDR(IR_DEC_LDR_REPEAT)
#define IR_DEC_BIT_0 0x2123 	///../ucode/register.h:547
#define P_IR_DEC_BIT_0 		CBUS_REG_ADDR(IR_DEC_BIT_0)
#define IR_DEC_REG0 0x2124 	///../ucode/register.h:548
#define P_IR_DEC_REG0 		CBUS_REG_ADDR(IR_DEC_REG0)
#define IR_DEC_FRAME 0x2125 	///../ucode/register.h:549
#define P_IR_DEC_FRAME 		CBUS_REG_ADDR(IR_DEC_FRAME)
#define IR_DEC_STATUS 0x2126 	///../ucode/register.h:550
#define P_IR_DEC_STATUS 		CBUS_REG_ADDR(IR_DEC_STATUS)
#define IR_DEC_REG1 0x2127 	///../ucode/register.h:551
#define P_IR_DEC_REG1 		CBUS_REG_ADDR(IR_DEC_REG1)
#define DEMOD_ADC_SAMPLING 0x212d 	///../ucode/register.h:555
#define P_DEMOD_ADC_SAMPLING 		CBUS_REG_ADDR(DEMOD_ADC_SAMPLING)
#define UART0_WFIFO 0x2130 	///../ucode/register.h:564
#define P_UART0_WFIFO 		CBUS_REG_ADDR(UART0_WFIFO)
#define UART0_RFIFO 0x2131 	///../ucode/register.h:565
#define P_UART0_RFIFO 		CBUS_REG_ADDR(UART0_RFIFO)
#define UART0_CONTROL 0x2132 	///../ucode/register.h:566
#define P_UART0_CONTROL 		CBUS_REG_ADDR(UART0_CONTROL)
#define UART0_STATUS 0x2133 	///../ucode/register.h:567
#define P_UART0_STATUS 		CBUS_REG_ADDR(UART0_STATUS)
#define UART0_MISC 0x2134 	///../ucode/register.h:568
#define P_UART0_MISC 		CBUS_REG_ADDR(UART0_MISC)
#define UART0_REG5 0x2135 	///../ucode/register.h:569
#define P_UART0_REG5 		CBUS_REG_ADDR(UART0_REG5)
#define UART1_WFIFO 0x2137 	///../ucode/register.h:573
#define P_UART1_WFIFO 		CBUS_REG_ADDR(UART1_WFIFO)
#define UART1_RFIFO 0x2138 	///../ucode/register.h:574
#define P_UART1_RFIFO 		CBUS_REG_ADDR(UART1_RFIFO)
#define UART1_CONTROL 0x2139 	///../ucode/register.h:575
#define P_UART1_CONTROL 		CBUS_REG_ADDR(UART1_CONTROL)
#define UART1_STATUS 0x213a 	///../ucode/register.h:576
#define P_UART1_STATUS 		CBUS_REG_ADDR(UART1_STATUS)
#define UART1_MISC 0x213b 	///../ucode/register.h:577
#define P_UART1_MISC 		CBUS_REG_ADDR(UART1_MISC)
#define UART1_REG5 0x213c 	///../ucode/register.h:578
#define P_UART1_REG5 		CBUS_REG_ADDR(UART1_REG5)
#define I2C_M_0_CONTROL_REG 0x2140 	///../ucode/register.h:582
#define P_I2C_M_0_CONTROL_REG 		CBUS_REG_ADDR(I2C_M_0_CONTROL_REG)
#define I2C_M_0_SLAVE_ADDR 0x2141 	///../ucode/register.h:598
#define P_I2C_M_0_SLAVE_ADDR 		CBUS_REG_ADDR(I2C_M_0_SLAVE_ADDR)
#define I2C_M_0_TOKEN_LIST0 0x2142 	///../ucode/register.h:599
#define P_I2C_M_0_TOKEN_LIST0 		CBUS_REG_ADDR(I2C_M_0_TOKEN_LIST0)
#define I2C_M_0_TOKEN_LIST1 0x2143 	///../ucode/register.h:600
#define P_I2C_M_0_TOKEN_LIST1 		CBUS_REG_ADDR(I2C_M_0_TOKEN_LIST1)
#define I2C_M_0_WDATA_REG0 0x2144 	///../ucode/register.h:601
#define P_I2C_M_0_WDATA_REG0 		CBUS_REG_ADDR(I2C_M_0_WDATA_REG0)
#define I2C_M_0_WDATA_REG1 0x2145 	///../ucode/register.h:602
#define P_I2C_M_0_WDATA_REG1 		CBUS_REG_ADDR(I2C_M_0_WDATA_REG1)
#define I2C_M_0_RDATA_REG0 0x2146 	///../ucode/register.h:603
#define P_I2C_M_0_RDATA_REG0 		CBUS_REG_ADDR(I2C_M_0_RDATA_REG0)
#define I2C_M_0_RDATA_REG1 0x2147 	///../ucode/register.h:604
#define P_I2C_M_0_RDATA_REG1 		CBUS_REG_ADDR(I2C_M_0_RDATA_REG1)
#define I2C_S_CONTROL_REG 0x2150 	///../ucode/register.h:608
#define P_I2C_S_CONTROL_REG 		CBUS_REG_ADDR(I2C_S_CONTROL_REG)
#define I2C_S_SEND_REG 0x2151 	///../ucode/register.h:609
#define P_I2C_S_SEND_REG 		CBUS_REG_ADDR(I2C_S_SEND_REG)
#define I2C_S_RECV_REG 0x2152 	///../ucode/register.h:610
#define P_I2C_S_RECV_REG 		CBUS_REG_ADDR(I2C_S_RECV_REG)
#define I2C_S_CNTL1_REG 0x2153 	///../ucode/register.h:611
#define P_I2C_S_CNTL1_REG 		CBUS_REG_ADDR(I2C_S_CNTL1_REG)
#define PWM_PWM_A 0x2154 	///../ucode/register.h:615
#define P_PWM_PWM_A 		CBUS_REG_ADDR(PWM_PWM_A)
#define PWM_PWM_B 0x2155 	///../ucode/register.h:616
#define P_PWM_PWM_B 		CBUS_REG_ADDR(PWM_PWM_B)
#define PWM_MISC_REG_AB 0x2156 	///../ucode/register.h:617
#define P_PWM_MISC_REG_AB 		CBUS_REG_ADDR(PWM_MISC_REG_AB)
#define PWM_DELTA_SIGMA_AB 0x2157 	///../ucode/register.h:618
#define P_PWM_DELTA_SIGMA_AB 		CBUS_REG_ADDR(PWM_DELTA_SIGMA_AB)
#define ATAPI_IDEREG0 0x2160 	///../ucode/register.h:632
#define P_ATAPI_IDEREG0 		CBUS_REG_ADDR(ATAPI_IDEREG0)
#define ATAPI_IDEREG1 0x2161 	///../ucode/register.h:645
#define P_ATAPI_IDEREG1 		CBUS_REG_ADDR(ATAPI_IDEREG1)
#define ATAPI_IDEREG2 0x2162 	///../ucode/register.h:646
#define P_ATAPI_IDEREG2 		CBUS_REG_ADDR(ATAPI_IDEREG2)
#define ATAPI_CYCTIME 0x2163 	///../ucode/register.h:649
#define P_ATAPI_CYCTIME 		CBUS_REG_ADDR(ATAPI_CYCTIME)
#define ATAPI_IDETIME 0x2164 	///../ucode/register.h:650
#define P_ATAPI_IDETIME 		CBUS_REG_ADDR(ATAPI_IDETIME)
#define ATAPI_PIO_TIMING 0x2165 	///../ucode/register.h:651
#define P_ATAPI_PIO_TIMING 		CBUS_REG_ADDR(ATAPI_PIO_TIMING)
#define ATAPI_TABLE_ADD_REG 0x2166 	///../ucode/register.h:652
#define P_ATAPI_TABLE_ADD_REG 		CBUS_REG_ADDR(ATAPI_TABLE_ADD_REG)
#define ATAPI_IDEREG3 0x2167 	///../ucode/register.h:653
#define P_ATAPI_IDEREG3 		CBUS_REG_ADDR(ATAPI_IDEREG3)
#define ATAPI_UDMA_REG0 0x2168 	///../ucode/register.h:654
#define P_ATAPI_UDMA_REG0 		CBUS_REG_ADDR(ATAPI_UDMA_REG0)
#define ATAPI_UDMA_REG1 0x2169 	///../ucode/register.h:655
#define P_ATAPI_UDMA_REG1 		CBUS_REG_ADDR(ATAPI_UDMA_REG1)
#define TRANS_PWMA_REG0 0x2170 	///../ucode/register.h:657
#define P_TRANS_PWMA_REG0 		CBUS_REG_ADDR(TRANS_PWMA_REG0)
#define TRANS_PWMA_REG1 0x2171 	///../ucode/register.h:658
#define P_TRANS_PWMA_REG1 		CBUS_REG_ADDR(TRANS_PWMA_REG1)
#define TRANS_PWMA_MUX0 0x2172 	///../ucode/register.h:659
#define P_TRANS_PWMA_MUX0 		CBUS_REG_ADDR(TRANS_PWMA_MUX0)
#define TRANS_PWMA_MUX1 0x2173 	///../ucode/register.h:660
#define P_TRANS_PWMA_MUX1 		CBUS_REG_ADDR(TRANS_PWMA_MUX1)
#define TRANS_PWMA_MUX2 0x2174 	///../ucode/register.h:661
#define P_TRANS_PWMA_MUX2 		CBUS_REG_ADDR(TRANS_PWMA_MUX2)
#define TRANS_PWMA_MUX3 0x2175 	///../ucode/register.h:662
#define P_TRANS_PWMA_MUX3 		CBUS_REG_ADDR(TRANS_PWMA_MUX3)
#define TRANS_PWMA_MUX4 0x2176 	///../ucode/register.h:663
#define P_TRANS_PWMA_MUX4 		CBUS_REG_ADDR(TRANS_PWMA_MUX4)
#define TRANS_PWMA_MUX5 0x2177 	///../ucode/register.h:664
#define P_TRANS_PWMA_MUX5 		CBUS_REG_ADDR(TRANS_PWMA_MUX5)
#define TRANS_PWMB_REG0 0x2178 	///../ucode/register.h:665
#define P_TRANS_PWMB_REG0 		CBUS_REG_ADDR(TRANS_PWMB_REG0)
#define TRANS_PWMB_REG1 0x2179 	///../ucode/register.h:666
#define P_TRANS_PWMB_REG1 		CBUS_REG_ADDR(TRANS_PWMB_REG1)
#define TRANS_PWMB_MUX0 0x217a 	///../ucode/register.h:667
#define P_TRANS_PWMB_MUX0 		CBUS_REG_ADDR(TRANS_PWMB_MUX0)
#define TRANS_PWMB_MUX1 0x217b 	///../ucode/register.h:668
#define P_TRANS_PWMB_MUX1 		CBUS_REG_ADDR(TRANS_PWMB_MUX1)
#define TRANS_PWMB_MUX2 0x217c 	///../ucode/register.h:669
#define P_TRANS_PWMB_MUX2 		CBUS_REG_ADDR(TRANS_PWMB_MUX2)
#define TRANS_PWMB_MUX3 0x217d 	///../ucode/register.h:670
#define P_TRANS_PWMB_MUX3 		CBUS_REG_ADDR(TRANS_PWMB_MUX3)
#define TRANS_PWMB_MUX4 0x217e 	///../ucode/register.h:671
#define P_TRANS_PWMB_MUX4 		CBUS_REG_ADDR(TRANS_PWMB_MUX4)
#define TRANS_PWMB_MUX5 0x217f 	///../ucode/register.h:672
#define P_TRANS_PWMB_MUX5 		CBUS_REG_ADDR(TRANS_PWMB_MUX5)
#define NAND_START 0x2180 	///../ucode/register.h:676
#define P_NAND_START 		CBUS_REG_ADDR(NAND_START)
#define NAND_ADR_CMD 0x218a 	///../ucode/register.h:677
#define P_NAND_ADR_CMD 		CBUS_REG_ADDR(NAND_ADR_CMD)
#define NAND_ADR_STS 0x218b 	///../ucode/register.h:678
#define P_NAND_ADR_STS 		CBUS_REG_ADDR(NAND_ADR_STS)
#define NAND_END 0x218f 	///../ucode/register.h:679
#define P_NAND_END 		CBUS_REG_ADDR(NAND_END)
#define PWM_PWM_C 0x2194 	///../ucode/register.h:683
#define P_PWM_PWM_C 		CBUS_REG_ADDR(PWM_PWM_C)
#define PWM_PWM_D 0x2195 	///../ucode/register.h:684
#define P_PWM_PWM_D 		CBUS_REG_ADDR(PWM_PWM_D)
#define PWM_MISC_REG_CD 0x2196 	///../ucode/register.h:685
#define P_PWM_MISC_REG_CD 		CBUS_REG_ADDR(PWM_MISC_REG_CD)
#define PWM_DELTA_SIGMA_CD 0x2197 	///../ucode/register.h:686
#define P_PWM_DELTA_SIGMA_CD 		CBUS_REG_ADDR(PWM_DELTA_SIGMA_CD)
#define ISP_LED_CTRL 0x2198 	///../ucode/register.h:703
#define P_ISP_LED_CTRL 		CBUS_REG_ADDR(ISP_LED_CTRL)
#define ISP_LED_TIMING1 0x2199 	///../ucode/register.h:707
#define P_ISP_LED_TIMING1 		CBUS_REG_ADDR(ISP_LED_TIMING1)
#define ISP_LED_TIMING2 0x219a 	///../ucode/register.h:711
#define P_ISP_LED_TIMING2 		CBUS_REG_ADDR(ISP_LED_TIMING2)
#define ISP_LED_TIMING3 0x219b 	///../ucode/register.h:714
#define P_ISP_LED_TIMING3 		CBUS_REG_ADDR(ISP_LED_TIMING3)
#define ISP_LED_TIMING4 0x219c 	///../ucode/register.h:716
#define P_ISP_LED_TIMING4 		CBUS_REG_ADDR(ISP_LED_TIMING4)
#define ISP_LED_TIMING5 0x219d 	///../ucode/register.h:719
#define P_ISP_LED_TIMING5 		CBUS_REG_ADDR(ISP_LED_TIMING5)
#define ISP_LED_TIMING6 0x219e 	///../ucode/register.h:722
#define P_ISP_LED_TIMING6 		CBUS_REG_ADDR(ISP_LED_TIMING6)
#define SAR_ADC_REG0 0x21a0 	///../ucode/register.h:726
#define P_SAR_ADC_REG0 		CBUS_REG_ADDR(SAR_ADC_REG0)
#define SAR_ADC_CHAN_LIST 0x21a1 	///../ucode/register.h:727
#define P_SAR_ADC_CHAN_LIST 		CBUS_REG_ADDR(SAR_ADC_CHAN_LIST)
#define SAR_ADC_AVG_CNTL 0x21a2 	///../ucode/register.h:728
#define P_SAR_ADC_AVG_CNTL 		CBUS_REG_ADDR(SAR_ADC_AVG_CNTL)
#define SAR_ADC_REG3 0x21a3 	///../ucode/register.h:729
#define P_SAR_ADC_REG3 		CBUS_REG_ADDR(SAR_ADC_REG3)
#define SAR_ADC_DELAY 0x21a4 	///../ucode/register.h:730
#define P_SAR_ADC_DELAY 		CBUS_REG_ADDR(SAR_ADC_DELAY)
#define SAR_ADC_LAST_RD 0x21a5 	///../ucode/register.h:731
#define P_SAR_ADC_LAST_RD 		CBUS_REG_ADDR(SAR_ADC_LAST_RD)
#define SAR_ADC_FIFO_RD 0x21a6 	///../ucode/register.h:732
#define P_SAR_ADC_FIFO_RD 		CBUS_REG_ADDR(SAR_ADC_FIFO_RD)
#define SAR_ADC_AUX_SW 0x21a7 	///../ucode/register.h:733
#define P_SAR_ADC_AUX_SW 		CBUS_REG_ADDR(SAR_ADC_AUX_SW)
#define SAR_ADC_CHAN_10_SW 0x21a8 	///../ucode/register.h:734
#define P_SAR_ADC_CHAN_10_SW 		CBUS_REG_ADDR(SAR_ADC_CHAN_10_SW)
#define SAR_ADC_DETECT_IDLE_SW 0x21a9 	///../ucode/register.h:735
#define P_SAR_ADC_DETECT_IDLE_SW 		CBUS_REG_ADDR(SAR_ADC_DETECT_IDLE_SW)
#define SAR_ADC_DELTA_10 0x21aa 	///../ucode/register.h:736
#define P_SAR_ADC_DELTA_10 		CBUS_REG_ADDR(SAR_ADC_DELTA_10)
#define PWM_PWM_E 0x21b0 	///../ucode/register.h:740
#define P_PWM_PWM_E 		CBUS_REG_ADDR(PWM_PWM_E)
#define PWM_PWM_F 0x21b1 	///../ucode/register.h:741
#define P_PWM_PWM_F 		CBUS_REG_ADDR(PWM_PWM_F)
#define PWM_MISC_REG_EF 0x21b2 	///../ucode/register.h:742
#define P_PWM_MISC_REG_EF 		CBUS_REG_ADDR(PWM_MISC_REG_EF)
#define PWM_DELTA_SIGMA_EF 0x21b3 	///../ucode/register.h:743
#define P_PWM_DELTA_SIGMA_EF 		CBUS_REG_ADDR(PWM_DELTA_SIGMA_EF)
#define UART2_WFIFO 0x21c0 	///../ucode/register.h:747
#define P_UART2_WFIFO 		CBUS_REG_ADDR(UART2_WFIFO)
#define UART2_RFIFO 0x21c1 	///../ucode/register.h:748
#define P_UART2_RFIFO 		CBUS_REG_ADDR(UART2_RFIFO)
#define UART2_CONTROL 0x21c2 	///../ucode/register.h:749
#define P_UART2_CONTROL 		CBUS_REG_ADDR(UART2_CONTROL)
#define UART2_STATUS 0x21c3 	///../ucode/register.h:750
#define P_UART2_STATUS 		CBUS_REG_ADDR(UART2_STATUS)
#define UART2_MISC 0x21c4 	///../ucode/register.h:751
#define P_UART2_MISC 		CBUS_REG_ADDR(UART2_MISC)
#define UART2_REG5 0x21c5 	///../ucode/register.h:752
#define P_UART2_REG5 		CBUS_REG_ADDR(UART2_REG5)
#define UART3_WFIFO 0x21c8 	///../ucode/register.h:756
#define P_UART3_WFIFO 		CBUS_REG_ADDR(UART3_WFIFO)
#define UART3_RFIFO 0x21c9 	///../ucode/register.h:757
#define P_UART3_RFIFO 		CBUS_REG_ADDR(UART3_RFIFO)
#define UART3_CONTROL 0x21ca 	///../ucode/register.h:758
#define P_UART3_CONTROL 		CBUS_REG_ADDR(UART3_CONTROL)
#define UART3_STATUS 0x21cb 	///../ucode/register.h:759
#define P_UART3_STATUS 		CBUS_REG_ADDR(UART3_STATUS)
#define UART3_MISC 0x21cc 	///../ucode/register.h:760
#define P_UART3_MISC 		CBUS_REG_ADDR(UART3_MISC)
#define UART3_REG5 0x21cd 	///../ucode/register.h:761
#define P_UART3_REG5 		CBUS_REG_ADDR(UART3_REG5)
#define RTC_ADDR0 0x21d0 	///../ucode/register.h:765
#define P_RTC_ADDR0 		CBUS_REG_ADDR(RTC_ADDR0)
#define RTC_ADDR1 0x21d1 	///../ucode/register.h:766
#define P_RTC_ADDR1 		CBUS_REG_ADDR(RTC_ADDR1)
#define RTC_ADDR2 0x21d2 	///../ucode/register.h:767
#define P_RTC_ADDR2 		CBUS_REG_ADDR(RTC_ADDR2)
#define RTC_ADDR3 0x21d3 	///../ucode/register.h:768
#define P_RTC_ADDR3 		CBUS_REG_ADDR(RTC_ADDR3)
#define RTC_ADDR4 0x21d4 	///../ucode/register.h:769
#define P_RTC_ADDR4 		CBUS_REG_ADDR(RTC_ADDR4)
#define MSR_CLK_DUTY 0x21d6 	///../ucode/register.h:773
#define P_MSR_CLK_DUTY 		CBUS_REG_ADDR(MSR_CLK_DUTY)
#define MSR_CLK_REG0 0x21d7 	///../ucode/register.h:774
#define P_MSR_CLK_REG0 		CBUS_REG_ADDR(MSR_CLK_REG0)
#define MSR_CLK_REG1 0x21d8 	///../ucode/register.h:775
#define P_MSR_CLK_REG1 		CBUS_REG_ADDR(MSR_CLK_REG1)
#define MSR_CLK_REG2 0x21d9 	///../ucode/register.h:776
#define P_MSR_CLK_REG2 		CBUS_REG_ADDR(MSR_CLK_REG2)
#define MSR_CLK_REG3 0x21da 	///../ucode/register.h:777
#define P_MSR_CLK_REG3 		CBUS_REG_ADDR(MSR_CLK_REG3)
#define MSR_CLK_REG4 0x21db 	///../ucode/register.h:778
#define P_MSR_CLK_REG4 		CBUS_REG_ADDR(MSR_CLK_REG4)
#define MSR_CLK_REG5 0x21de 	///../ucode/register.h:779
#define P_MSR_CLK_REG5 		CBUS_REG_ADDR(MSR_CLK_REG5)
#define LED_PWM_REG0 0x21da 	///../ucode/register.h:780
#define P_LED_PWM_REG0 		CBUS_REG_ADDR(LED_PWM_REG0)
#define LED_PWM_REG1 0x21db 	///../ucode/register.h:781
#define P_LED_PWM_REG1 		CBUS_REG_ADDR(LED_PWM_REG1)
#define LED_PWM_REG2 0x21dc 	///../ucode/register.h:782
#define P_LED_PWM_REG2 		CBUS_REG_ADDR(LED_PWM_REG2)
#define LED_PWM_REG3 0x21dd 	///../ucode/register.h:783
#define P_LED_PWM_REG3 		CBUS_REG_ADDR(LED_PWM_REG3)
#define LED_PWM_REG4 0x21de 	///../ucode/register.h:784
#define P_LED_PWM_REG4 		CBUS_REG_ADDR(LED_PWM_REG4)
#define LED_PWM_REG5 0x21df 	///../ucode/register.h:785
#define P_LED_PWM_REG5 		CBUS_REG_ADDR(LED_PWM_REG5)
#define LED_PWM_REG6 0x21e0 	///../ucode/register.h:786
#define P_LED_PWM_REG6 		CBUS_REG_ADDR(LED_PWM_REG6)
#define VGHL_PWM_REG0 0x21e1 	///../ucode/register.h:790
#define P_VGHL_PWM_REG0 		CBUS_REG_ADDR(VGHL_PWM_REG0)
#define VGHL_PWM_REG1 0x21e2 	///../ucode/register.h:791
#define P_VGHL_PWM_REG1 		CBUS_REG_ADDR(VGHL_PWM_REG1)
#define VGHL_PWM_REG2 0x21e3 	///../ucode/register.h:792
#define P_VGHL_PWM_REG2 		CBUS_REG_ADDR(VGHL_PWM_REG2)
#define VGHL_PWM_REG3 0x21e4 	///../ucode/register.h:793
#define P_VGHL_PWM_REG3 		CBUS_REG_ADDR(VGHL_PWM_REG3)
#define VGHL_PWM_REG4 0x21e5 	///../ucode/register.h:794
#define P_VGHL_PWM_REG4 		CBUS_REG_ADDR(VGHL_PWM_REG4)
#define VGHL_PWM_REG5 0x21e6 	///../ucode/register.h:795
#define P_VGHL_PWM_REG5 		CBUS_REG_ADDR(VGHL_PWM_REG5)
#define VGHL_PWM_REG6 0x21e7 	///../ucode/register.h:796
#define P_VGHL_PWM_REG6 		CBUS_REG_ADDR(VGHL_PWM_REG6)
#define I2C_M_1_CONTROL_REG 0x21f0 	///../ucode/register.h:803
#define P_I2C_M_1_CONTROL_REG 		CBUS_REG_ADDR(I2C_M_1_CONTROL_REG)
#define I2C_M_1_SLAVE_ADDR 0x21f1 	///../ucode/register.h:804
#define P_I2C_M_1_SLAVE_ADDR 		CBUS_REG_ADDR(I2C_M_1_SLAVE_ADDR)
#define I2C_M_1_TOKEN_LIST0 0x21f2 	///../ucode/register.h:805
#define P_I2C_M_1_TOKEN_LIST0 		CBUS_REG_ADDR(I2C_M_1_TOKEN_LIST0)
#define I2C_M_1_TOKEN_LIST1 0x21f3 	///../ucode/register.h:806
#define P_I2C_M_1_TOKEN_LIST1 		CBUS_REG_ADDR(I2C_M_1_TOKEN_LIST1)
#define I2C_M_1_WDATA_REG0 0x21f4 	///../ucode/register.h:807
#define P_I2C_M_1_WDATA_REG0 		CBUS_REG_ADDR(I2C_M_1_WDATA_REG0)
#define I2C_M_1_WDATA_REG1 0x21f5 	///../ucode/register.h:808
#define P_I2C_M_1_WDATA_REG1 		CBUS_REG_ADDR(I2C_M_1_WDATA_REG1)
#define I2C_M_1_RDATA_REG0 0x21f6 	///../ucode/register.h:809
#define P_I2C_M_1_RDATA_REG0 		CBUS_REG_ADDR(I2C_M_1_RDATA_REG0)
#define I2C_M_1_RDATA_REG1 0x21f7 	///../ucode/register.h:810
#define P_I2C_M_1_RDATA_REG1 		CBUS_REG_ADDR(I2C_M_1_RDATA_REG1)
#define I2C_M_2_CONTROL_REG 0x21f8 	///../ucode/register.h:814
#define P_I2C_M_2_CONTROL_REG 		CBUS_REG_ADDR(I2C_M_2_CONTROL_REG)
#define I2C_M_2_SLAVE_ADDR 0x21f9 	///../ucode/register.h:815
#define P_I2C_M_2_SLAVE_ADDR 		CBUS_REG_ADDR(I2C_M_2_SLAVE_ADDR)
#define I2C_M_2_TOKEN_LIST0 0x21fa 	///../ucode/register.h:816
#define P_I2C_M_2_TOKEN_LIST0 		CBUS_REG_ADDR(I2C_M_2_TOKEN_LIST0)
#define I2C_M_2_TOKEN_LIST1 0x21fb 	///../ucode/register.h:817
#define P_I2C_M_2_TOKEN_LIST1 		CBUS_REG_ADDR(I2C_M_2_TOKEN_LIST1)
#define I2C_M_2_WDATA_REG0 0x21fc 	///../ucode/register.h:818
#define P_I2C_M_2_WDATA_REG0 		CBUS_REG_ADDR(I2C_M_2_WDATA_REG0)
#define I2C_M_2_WDATA_REG1 0x21fd 	///../ucode/register.h:819
#define P_I2C_M_2_WDATA_REG1 		CBUS_REG_ADDR(I2C_M_2_WDATA_REG1)
#define I2C_M_2_RDATA_REG0 0x21fe 	///../ucode/register.h:820
#define P_I2C_M_2_RDATA_REG0 		CBUS_REG_ADDR(I2C_M_2_RDATA_REG0)
#define I2C_M_2_RDATA_REG1 0x21ff 	///../ucode/register.h:821
#define P_I2C_M_2_RDATA_REG1 		CBUS_REG_ADDR(I2C_M_2_RDATA_REG1)
#define USB_ADDR0 0x2200 	///../ucode/register.h:828
#define P_USB_ADDR0 		CBUS_REG_ADDR(USB_ADDR0)
#define USB_ADDR1 0x2201 	///../ucode/register.h:829
#define P_USB_ADDR1 		CBUS_REG_ADDR(USB_ADDR1)
#define USB_ADDR2 0x2202 	///../ucode/register.h:830
#define P_USB_ADDR2 		CBUS_REG_ADDR(USB_ADDR2)
#define USB_ADDR3 0x2203 	///../ucode/register.h:831
#define P_USB_ADDR3 		CBUS_REG_ADDR(USB_ADDR3)
#define USB_ADDR4 0x2204 	///../ucode/register.h:832
#define P_USB_ADDR4 		CBUS_REG_ADDR(USB_ADDR4)
#define USB_ADDR5 0x2205 	///../ucode/register.h:833
#define P_USB_ADDR5 		CBUS_REG_ADDR(USB_ADDR5)
#define USB_ADDR6 0x2206 	///../ucode/register.h:834
#define P_USB_ADDR6 		CBUS_REG_ADDR(USB_ADDR6)
#define USB_ADDR7 0x2207 	///../ucode/register.h:835
#define P_USB_ADDR7 		CBUS_REG_ADDR(USB_ADDR7)
#define USB_ADDR8 0x2208 	///../ucode/register.h:836
#define P_USB_ADDR8 		CBUS_REG_ADDR(USB_ADDR8)
#define USB_ADDR9 0x2209 	///../ucode/register.h:837
#define P_USB_ADDR9 		CBUS_REG_ADDR(USB_ADDR9)
#define USB_ADDR10 0x220a 	///../ucode/register.h:838
#define P_USB_ADDR10 		CBUS_REG_ADDR(USB_ADDR10)
#define USB_ADDR11 0x220b 	///../ucode/register.h:839
#define P_USB_ADDR11 		CBUS_REG_ADDR(USB_ADDR11)
#define USB_ADDR12 0x220c 	///../ucode/register.h:840
#define P_USB_ADDR12 		CBUS_REG_ADDR(USB_ADDR12)
#define USB_ADDR13 0x220d 	///../ucode/register.h:841
#define P_USB_ADDR13 		CBUS_REG_ADDR(USB_ADDR13)
#define USB_ADDR14 0x220e 	///../ucode/register.h:842
#define P_USB_ADDR14 		CBUS_REG_ADDR(USB_ADDR14)
#define USB_ADDR15 0x220f 	///../ucode/register.h:843
#define P_USB_ADDR15 		CBUS_REG_ADDR(USB_ADDR15)
#define USB_ADDR16 0x2210 	///../ucode/register.h:844
#define P_USB_ADDR16 		CBUS_REG_ADDR(USB_ADDR16)
#define USB_ADDR17 0x2211 	///../ucode/register.h:845
#define P_USB_ADDR17 		CBUS_REG_ADDR(USB_ADDR17)
#define USB_ADDR18 0x2212 	///../ucode/register.h:846
#define P_USB_ADDR18 		CBUS_REG_ADDR(USB_ADDR18)
#define USB_ADDR19 0x2213 	///../ucode/register.h:847
#define P_USB_ADDR19 		CBUS_REG_ADDR(USB_ADDR19)
#define USB_ADDR20 0x2214 	///../ucode/register.h:848
#define P_USB_ADDR20 		CBUS_REG_ADDR(USB_ADDR20)
#define USB_ADDR21 0x2215 	///../ucode/register.h:849
#define P_USB_ADDR21 		CBUS_REG_ADDR(USB_ADDR21)
#define USB_ADDR22 0x2216 	///../ucode/register.h:850
#define P_USB_ADDR22 		CBUS_REG_ADDR(USB_ADDR22)
#define USB_ADDR23 0x2217 	///../ucode/register.h:851
#define P_USB_ADDR23 		CBUS_REG_ADDR(USB_ADDR23)
#define USB_ADDR24 0x2218 	///../ucode/register.h:852
#define P_USB_ADDR24 		CBUS_REG_ADDR(USB_ADDR24)
#define USB_ADDR25 0x2219 	///../ucode/register.h:853
#define P_USB_ADDR25 		CBUS_REG_ADDR(USB_ADDR25)
#define USB_ADDR26 0x221a 	///../ucode/register.h:854
#define P_USB_ADDR26 		CBUS_REG_ADDR(USB_ADDR26)
#define USB_ADDR27 0x221b 	///../ucode/register.h:855
#define P_USB_ADDR27 		CBUS_REG_ADDR(USB_ADDR27)
#define USB_ADDR28 0x221c 	///../ucode/register.h:856
#define P_USB_ADDR28 		CBUS_REG_ADDR(USB_ADDR28)
#define USB_ADDR29 0x221d 	///../ucode/register.h:857
#define P_USB_ADDR29 		CBUS_REG_ADDR(USB_ADDR29)
#define USB_ADDR30 0x221e 	///../ucode/register.h:858
#define P_USB_ADDR30 		CBUS_REG_ADDR(USB_ADDR30)
#define USB_ADDR31 0x221f 	///../ucode/register.h:859
#define P_USB_ADDR31 		CBUS_REG_ADDR(USB_ADDR31)
#define SANA_STREAM_CONTROL 0x2220 	///../ucode/register.h:871
#define P_SANA_STREAM_CONTROL 		CBUS_REG_ADDR(SANA_STREAM_CONTROL)
#define SANA_STREAM_START_ADDR 0x2221 	///../ucode/register.h:872
#define P_SANA_STREAM_START_ADDR 		CBUS_REG_ADDR(SANA_STREAM_START_ADDR)
#define SANA_STREAM_END_ADDR 0x2222 	///../ucode/register.h:873
#define P_SANA_STREAM_END_ADDR 		CBUS_REG_ADDR(SANA_STREAM_END_ADDR)
#define SANA_STREAM_WR_PTR 0x2223 	///../ucode/register.h:875
#define P_SANA_STREAM_WR_PTR 		CBUS_REG_ADDR(SANA_STREAM_WR_PTR)
#define SANA_STREAM_RD_PTR 0x2224 	///../ucode/register.h:876
#define P_SANA_STREAM_RD_PTR 		CBUS_REG_ADDR(SANA_STREAM_RD_PTR)
#define SANA_STREAM_LEVEL 0x2225 	///../ucode/register.h:878
#define P_SANA_STREAM_LEVEL 		CBUS_REG_ADDR(SANA_STREAM_LEVEL)
#define SANA_STREAM_FIFO_CTL 0x2226 	///../ucode/register.h:886
#define P_SANA_STREAM_FIFO_CTL 		CBUS_REG_ADDR(SANA_STREAM_FIFO_CTL)
#define SANA_SHIFT_CONTROL 0x2227 	///../ucode/register.h:897
#define P_SANA_SHIFT_CONTROL 		CBUS_REG_ADDR(SANA_SHIFT_CONTROL)
#define SANA_SHIFT_STARTCODE 0x2228 	///../ucode/register.h:899
#define P_SANA_SHIFT_STARTCODE 		CBUS_REG_ADDR(SANA_SHIFT_STARTCODE)
#define SANA_SHIFT_EMULATECODE 0x2229 	///../ucode/register.h:901
#define P_SANA_SHIFT_EMULATECODE 		CBUS_REG_ADDR(SANA_SHIFT_EMULATECODE)
#define SANA_SHIFT_STATUS 0x222a 	///../ucode/register.h:906
#define P_SANA_SHIFT_STATUS 		CBUS_REG_ADDR(SANA_SHIFT_STATUS)
#define SANA_SHIFTED_DATA 0x222b 	///../ucode/register.h:908
#define P_SANA_SHIFTED_DATA 		CBUS_REG_ADDR(SANA_SHIFTED_DATA)
#define SANA_SHIFT_BYTE_COUNT 0x222c 	///../ucode/register.h:910
#define P_SANA_SHIFT_BYTE_COUNT 		CBUS_REG_ADDR(SANA_SHIFT_BYTE_COUNT)
#define SANA_SHIFT_COMMAND 0x222d 	///../ucode/register.h:918
#define P_SANA_SHIFT_COMMAND 		CBUS_REG_ADDR(SANA_SHIFT_COMMAND)
#define SANA_ELEMENT_RESULT 0x222e 	///../ucode/register.h:922
#define P_SANA_ELEMENT_RESULT 		CBUS_REG_ADDR(SANA_ELEMENT_RESULT)
#define ATOM_LOCK 0x222f 	///../ucode/register.h:927
#define P_ATOM_LOCK 		CBUS_REG_ADDR(ATOM_LOCK)
#define NDMA_CNTL_REG0 0x2270 	///../ucode/register.h:931
#define P_NDMA_CNTL_REG0 		CBUS_REG_ADDR(NDMA_CNTL_REG0)
#define NDMA_TABLE_ADD_REG 0x2272 	///../ucode/register.h:939
#define P_NDMA_TABLE_ADD_REG 		CBUS_REG_ADDR(NDMA_TABLE_ADD_REG)
#define NDMA_TDES_KEY_LO 0x2273 	///../ucode/register.h:940
#define P_NDMA_TDES_KEY_LO 		CBUS_REG_ADDR(NDMA_TDES_KEY_LO)
#define NDMA_TDES_KEY_HI 0x2274 	///../ucode/register.h:941
#define P_NDMA_TDES_KEY_HI 		CBUS_REG_ADDR(NDMA_TDES_KEY_HI)
#define NDMA_TDES_CONTROL 0x2275 	///../ucode/register.h:942
#define P_NDMA_TDES_CONTROL 		CBUS_REG_ADDR(NDMA_TDES_CONTROL)
#define NDMA_RIJNDAEL_CONTROL 0x2276 	///../ucode/register.h:943
#define P_NDMA_RIJNDAEL_CONTROL 		CBUS_REG_ADDR(NDMA_RIJNDAEL_CONTROL)
#define NDMA_RIJNDAEL_RK_FIFO 0x2277 	///../ucode/register.h:944
#define P_NDMA_RIJNDAEL_RK_FIFO 		CBUS_REG_ADDR(NDMA_RIJNDAEL_RK_FIFO)
#define NDMA_CRC_OUT 0x2278 	///../ucode/register.h:945
#define P_NDMA_CRC_OUT 		CBUS_REG_ADDR(NDMA_CRC_OUT)
#define NDMA_THREAD_REG 0x2279 	///../ucode/register.h:946
#define P_NDMA_THREAD_REG 		CBUS_REG_ADDR(NDMA_THREAD_REG)
#define NDMA_THREAD_TABLE_START0 0x2280 	///../ucode/register.h:947
#define P_NDMA_THREAD_TABLE_START0 		CBUS_REG_ADDR(NDMA_THREAD_TABLE_START0)
#define NDMA_THREAD_TABLE_CURR0 0x2281 	///../ucode/register.h:948
#define P_NDMA_THREAD_TABLE_CURR0 		CBUS_REG_ADDR(NDMA_THREAD_TABLE_CURR0)
#define NDMA_THREAD_TABLE_END0 0x2282 	///../ucode/register.h:949
#define P_NDMA_THREAD_TABLE_END0 		CBUS_REG_ADDR(NDMA_THREAD_TABLE_END0)
#define NDMA_THREAD_TABLE_START1 0x2283 	///../ucode/register.h:950
#define P_NDMA_THREAD_TABLE_START1 		CBUS_REG_ADDR(NDMA_THREAD_TABLE_START1)
#define NDMA_THREAD_TABLE_CURR1 0x2284 	///../ucode/register.h:951
#define P_NDMA_THREAD_TABLE_CURR1 		CBUS_REG_ADDR(NDMA_THREAD_TABLE_CURR1)
#define NDMA_THREAD_TABLE_END1 0x2285 	///../ucode/register.h:952
#define P_NDMA_THREAD_TABLE_END1 		CBUS_REG_ADDR(NDMA_THREAD_TABLE_END1)
#define NDMA_THREAD_TABLE_START2 0x2286 	///../ucode/register.h:953
#define P_NDMA_THREAD_TABLE_START2 		CBUS_REG_ADDR(NDMA_THREAD_TABLE_START2)
#define NDMA_THREAD_TABLE_CURR2 0x2287 	///../ucode/register.h:954
#define P_NDMA_THREAD_TABLE_CURR2 		CBUS_REG_ADDR(NDMA_THREAD_TABLE_CURR2)
#define NDMA_THREAD_TABLE_END2 0x2288 	///../ucode/register.h:955
#define P_NDMA_THREAD_TABLE_END2 		CBUS_REG_ADDR(NDMA_THREAD_TABLE_END2)
#define NDMA_THREAD_TABLE_START3 0x2289 	///../ucode/register.h:956
#define P_NDMA_THREAD_TABLE_START3 		CBUS_REG_ADDR(NDMA_THREAD_TABLE_START3)
#define NDMA_THREAD_TABLE_CURR3 0x228a 	///../ucode/register.h:957
#define P_NDMA_THREAD_TABLE_CURR3 		CBUS_REG_ADDR(NDMA_THREAD_TABLE_CURR3)
#define NDMA_THREAD_TABLE_END3 0x228b 	///../ucode/register.h:958
#define P_NDMA_THREAD_TABLE_END3 		CBUS_REG_ADDR(NDMA_THREAD_TABLE_END3)
#define NDMA_CNTL_REG1 0x228c 	///../ucode/register.h:959
#define P_NDMA_CNTL_REG1 		CBUS_REG_ADDR(NDMA_CNTL_REG1)
#define NDMA_AES_KEY_0 0x2290 	///../ucode/register.h:960
#define P_NDMA_AES_KEY_0 		CBUS_REG_ADDR(NDMA_AES_KEY_0)
#define NDMA_AES_KEY_1 0x2291 	///../ucode/register.h:961
#define P_NDMA_AES_KEY_1 		CBUS_REG_ADDR(NDMA_AES_KEY_1)
#define NDMA_AES_KEY_2 0x2292 	///../ucode/register.h:962
#define P_NDMA_AES_KEY_2 		CBUS_REG_ADDR(NDMA_AES_KEY_2)
#define NDMA_AES_KEY_3 0x2293 	///../ucode/register.h:963
#define P_NDMA_AES_KEY_3 		CBUS_REG_ADDR(NDMA_AES_KEY_3)
#define NDMA_AES_KEY_4 0x2294 	///../ucode/register.h:964
#define P_NDMA_AES_KEY_4 		CBUS_REG_ADDR(NDMA_AES_KEY_4)
#define NDMA_AES_KEY_5 0x2295 	///../ucode/register.h:965
#define P_NDMA_AES_KEY_5 		CBUS_REG_ADDR(NDMA_AES_KEY_5)
#define NDMA_AES_KEY_6 0x2296 	///../ucode/register.h:966
#define P_NDMA_AES_KEY_6 		CBUS_REG_ADDR(NDMA_AES_KEY_6)
#define NDMA_AES_KEY_7 0x2297 	///../ucode/register.h:967
#define P_NDMA_AES_KEY_7 		CBUS_REG_ADDR(NDMA_AES_KEY_7)
#define NDMA_AES_IV_0 0x2298 	///../ucode/register.h:968
#define P_NDMA_AES_IV_0 		CBUS_REG_ADDR(NDMA_AES_IV_0)
#define NDMA_AES_IV_1 0x2299 	///../ucode/register.h:969
#define P_NDMA_AES_IV_1 		CBUS_REG_ADDR(NDMA_AES_IV_1)
#define NDMA_AES_IV_2 0x229a 	///../ucode/register.h:970
#define P_NDMA_AES_IV_2 		CBUS_REG_ADDR(NDMA_AES_IV_2)
#define NDMA_AES_IV_3 0x229b 	///../ucode/register.h:971
#define P_NDMA_AES_IV_3 		CBUS_REG_ADDR(NDMA_AES_IV_3)
#define NDMA_AES_REG0 0x229c 	///../ucode/register.h:972
#define P_NDMA_AES_REG0 		CBUS_REG_ADDR(NDMA_AES_REG0)
#define STREAM_EVENT_INFO 0x2300 	///../ucode/register.h:988
#define P_STREAM_EVENT_INFO 		CBUS_REG_ADDR(STREAM_EVENT_INFO)
#define STREAM_OUTPUT_CONFIG 0x2301 	///../ucode/register.h:995
#define P_STREAM_OUTPUT_CONFIG 		CBUS_REG_ADDR(STREAM_OUTPUT_CONFIG)
#define C_D_BUS_CONTROL 0x2302 	///../ucode/register.h:1008
#define P_C_D_BUS_CONTROL 		CBUS_REG_ADDR(C_D_BUS_CONTROL)
#define C_DATA 0x2303 	///../ucode/register.h:1010
#define P_C_DATA 		CBUS_REG_ADDR(C_DATA)
#define STREAM_BUS_CONFIG 0x2304 	///../ucode/register.h:1017
#define P_STREAM_BUS_CONFIG 		CBUS_REG_ADDR(STREAM_BUS_CONFIG)
#define STREAM_DATA_IN_CONFIG 0x2305 	///../ucode/register.h:1034
#define P_STREAM_DATA_IN_CONFIG 		CBUS_REG_ADDR(STREAM_DATA_IN_CONFIG)
#define STREAM_WAIT_IRQ_CONFIG 0x2306 	///../ucode/register.h:1047
#define P_STREAM_WAIT_IRQ_CONFIG 		CBUS_REG_ADDR(STREAM_WAIT_IRQ_CONFIG)
#define STREAM_EVENT_CTL 0x2307 	///../ucode/register.h:1052
#define P_STREAM_EVENT_CTL 		CBUS_REG_ADDR(STREAM_EVENT_CTL)
#define CMD_ARGUMENT 0x2308 	///../ucode/register.h:1058
#define P_CMD_ARGUMENT 		CBUS_REG_ADDR(CMD_ARGUMENT)
#define CMD_SEND 0x2309 	///../ucode/register.h:1068
#define P_CMD_SEND 		CBUS_REG_ADDR(CMD_SEND)
#define SDIO_CONFIG 0x230a 	///../ucode/register.h:1079
#define P_SDIO_CONFIG 		CBUS_REG_ADDR(SDIO_CONFIG)
#define SDIO_STATUS_IRQ 0x230b 	///../ucode/register.h:1094
#define P_SDIO_STATUS_IRQ 		CBUS_REG_ADDR(SDIO_STATUS_IRQ)
#define SDIO_IRQ_CONFIG 0x230c 	///../ucode/register.h:1110
#define P_SDIO_IRQ_CONFIG 		CBUS_REG_ADDR(SDIO_IRQ_CONFIG)
#define SDIO_MULT_CONFIG 0x230d 	///../ucode/register.h:1125
#define P_SDIO_MULT_CONFIG 		CBUS_REG_ADDR(SDIO_MULT_CONFIG)
#define SDIO_M_ADDR 0x230e 	///../ucode/register.h:1127
#define P_SDIO_M_ADDR 		CBUS_REG_ADDR(SDIO_M_ADDR)
#define SDIO_EXTENSION 0x230f 	///../ucode/register.h:1132
#define P_SDIO_EXTENSION 		CBUS_REG_ADDR(SDIO_EXTENSION)
#define ASYNC_FIFO_REG0 0x2310 	///../ucode/register.h:1136
#define P_ASYNC_FIFO_REG0 		CBUS_REG_ADDR(ASYNC_FIFO_REG0)
#define ASYNC_FIFO_REG1 0x2311 	///../ucode/register.h:1137
#define P_ASYNC_FIFO_REG1 		CBUS_REG_ADDR(ASYNC_FIFO_REG1)
#define ASYNC_FIFO_REG2 0x2312 	///../ucode/register.h:1150
#define P_ASYNC_FIFO_REG2 		CBUS_REG_ADDR(ASYNC_FIFO_REG2)
#define ASYNC_FIFO_REG3 0x2313 	///../ucode/register.h:1160
#define P_ASYNC_FIFO_REG3 		CBUS_REG_ADDR(ASYNC_FIFO_REG3)
#define ASYNC_FIFO2_REG0 0x2314 	///../ucode/register.h:1166
#define P_ASYNC_FIFO2_REG0 		CBUS_REG_ADDR(ASYNC_FIFO2_REG0)
#define ASYNC_FIFO2_REG1 0x2315 	///../ucode/register.h:1167
#define P_ASYNC_FIFO2_REG1 		CBUS_REG_ADDR(ASYNC_FIFO2_REG1)
#define ASYNC_FIFO2_REG2 0x2316 	///../ucode/register.h:1168
#define P_ASYNC_FIFO2_REG2 		CBUS_REG_ADDR(ASYNC_FIFO2_REG2)
#define ASYNC_FIFO2_REG3 0x2317 	///../ucode/register.h:1169
#define P_ASYNC_FIFO2_REG3 		CBUS_REG_ADDR(ASYNC_FIFO2_REG3)
#define SDIO_AHB_CBUS_CTRL 0x2318 	///../ucode/register.h:1181
#define P_SDIO_AHB_CBUS_CTRL 		CBUS_REG_ADDR(SDIO_AHB_CBUS_CTRL)
#define SDIO_AHB_CBUS_M_DATA 0x2319 	///../ucode/register.h:1184
#define P_SDIO_AHB_CBUS_M_DATA 		CBUS_REG_ADDR(SDIO_AHB_CBUS_M_DATA)
#define SPI_FLASH_CMD 0x2320 	///../ucode/register.h:1188
#define P_SPI_FLASH_CMD 		CBUS_REG_ADDR(SPI_FLASH_CMD)
#define SPI_FLASH_ADDR 0x2321 	///../ucode/register.h:1209
#define P_SPI_FLASH_ADDR 		CBUS_REG_ADDR(SPI_FLASH_ADDR)
#define SPI_FLASH_CTRL 0x2322 	///../ucode/register.h:1212
#define P_SPI_FLASH_CTRL 		CBUS_REG_ADDR(SPI_FLASH_CTRL)
#define SPI_FLASH_CTRL1 0x2323 	///../ucode/register.h:1222
#define P_SPI_FLASH_CTRL1 		CBUS_REG_ADDR(SPI_FLASH_CTRL1)
#define SPI_FLASH_STATUS 0x2324 	///../ucode/register.h:1223
#define P_SPI_FLASH_STATUS 		CBUS_REG_ADDR(SPI_FLASH_STATUS)
#define SPI_FLASH_CTRL2 0x2325 	///../ucode/register.h:1224
#define P_SPI_FLASH_CTRL2 		CBUS_REG_ADDR(SPI_FLASH_CTRL2)
#define SPI_FLASH_CLOCK 0x2326 	///../ucode/register.h:1225
#define P_SPI_FLASH_CLOCK 		CBUS_REG_ADDR(SPI_FLASH_CLOCK)
#define SPI_FLASH_USER 0x2327 	///../ucode/register.h:1226
#define P_SPI_FLASH_USER 		CBUS_REG_ADDR(SPI_FLASH_USER)
#define SPI_FLASH_USER1 0x2328 	///../ucode/register.h:1227
#define P_SPI_FLASH_USER1 		CBUS_REG_ADDR(SPI_FLASH_USER1)
#define SPI_FLASH_USER2 0x2329 	///../ucode/register.h:1228
#define P_SPI_FLASH_USER2 		CBUS_REG_ADDR(SPI_FLASH_USER2)
#define SPI_FLASH_USER3 0x232a 	///../ucode/register.h:1229
#define P_SPI_FLASH_USER3 		CBUS_REG_ADDR(SPI_FLASH_USER3)
#define SPI_FLASH_USER4 0x232b 	///../ucode/register.h:1230
#define P_SPI_FLASH_USER4 		CBUS_REG_ADDR(SPI_FLASH_USER4)
#define SPI_FLASH_SLAVE 0x232c 	///../ucode/register.h:1231
#define P_SPI_FLASH_SLAVE 		CBUS_REG_ADDR(SPI_FLASH_SLAVE)
#define SPI_FLASH_SLAVE1 0x232d 	///../ucode/register.h:1232
#define P_SPI_FLASH_SLAVE1 		CBUS_REG_ADDR(SPI_FLASH_SLAVE1)
#define SPI_FLASH_SLAVE2 0x232e 	///../ucode/register.h:1233
#define P_SPI_FLASH_SLAVE2 		CBUS_REG_ADDR(SPI_FLASH_SLAVE2)
#define SPI_FLASH_SLAVE3 0x232f 	///../ucode/register.h:1234
#define P_SPI_FLASH_SLAVE3 		CBUS_REG_ADDR(SPI_FLASH_SLAVE3)
#define SPI_FLASH_C0 0x2330 	///../ucode/register.h:1235
#define P_SPI_FLASH_C0 		CBUS_REG_ADDR(SPI_FLASH_C0)
#define SPI_FLASH_C1 0x2331 	///../ucode/register.h:1236
#define P_SPI_FLASH_C1 		CBUS_REG_ADDR(SPI_FLASH_C1)
#define SPI_FLASH_C2 0x2332 	///../ucode/register.h:1237
#define P_SPI_FLASH_C2 		CBUS_REG_ADDR(SPI_FLASH_C2)
#define SPI_FLASH_C3 0x2333 	///../ucode/register.h:1238
#define P_SPI_FLASH_C3 		CBUS_REG_ADDR(SPI_FLASH_C3)
#define SPI_FLASH_C4 0x2334 	///../ucode/register.h:1239
#define P_SPI_FLASH_C4 		CBUS_REG_ADDR(SPI_FLASH_C4)
#define SPI_FLASH_C5 0x2335 	///../ucode/register.h:1240
#define P_SPI_FLASH_C5 		CBUS_REG_ADDR(SPI_FLASH_C5)
#define SPI_FLASH_C6 0x2336 	///../ucode/register.h:1241
#define P_SPI_FLASH_C6 		CBUS_REG_ADDR(SPI_FLASH_C6)
#define SPI_FLASH_C7 0x2337 	///../ucode/register.h:1242
#define P_SPI_FLASH_C7 		CBUS_REG_ADDR(SPI_FLASH_C7)
#define SPI_FLASH_B8 0x2338 	///../ucode/register.h:1243
#define P_SPI_FLASH_B8 		CBUS_REG_ADDR(SPI_FLASH_B8)
#define SPI_FLASH_B9 0x2339 	///../ucode/register.h:1244
#define P_SPI_FLASH_B9 		CBUS_REG_ADDR(SPI_FLASH_B9)
#define SPI_FLASH_B10 0x233a 	///../ucode/register.h:1245
#define P_SPI_FLASH_B10 		CBUS_REG_ADDR(SPI_FLASH_B10)
#define SPI_FLASH_B11 0x233b 	///../ucode/register.h:1246
#define P_SPI_FLASH_B11 		CBUS_REG_ADDR(SPI_FLASH_B11)
#define SPI_FLASH_B12 0x233c 	///../ucode/register.h:1247
#define P_SPI_FLASH_B12 		CBUS_REG_ADDR(SPI_FLASH_B12)
#define SPI_FLASH_B13 0x233d 	///../ucode/register.h:1248
#define P_SPI_FLASH_B13 		CBUS_REG_ADDR(SPI_FLASH_B13)
#define SPI_FLASH_B14 0x233e 	///../ucode/register.h:1249
#define P_SPI_FLASH_B14 		CBUS_REG_ADDR(SPI_FLASH_B14)
#define SPI_FLASH_B15 0x233f 	///../ucode/register.h:1250
#define P_SPI_FLASH_B15 		CBUS_REG_ADDR(SPI_FLASH_B15)
#define I2C_M_3_CONTROL_REG 0x2348 	///../ucode/register.h:1254
#define P_I2C_M_3_CONTROL_REG 		CBUS_REG_ADDR(I2C_M_3_CONTROL_REG)
#define I2C_M_3_SLAVE_ADDR 0x2349 	///../ucode/register.h:1255
#define P_I2C_M_3_SLAVE_ADDR 		CBUS_REG_ADDR(I2C_M_3_SLAVE_ADDR)
#define I2C_M_3_TOKEN_LIST0 0x234a 	///../ucode/register.h:1256
#define P_I2C_M_3_TOKEN_LIST0 		CBUS_REG_ADDR(I2C_M_3_TOKEN_LIST0)
#define I2C_M_3_TOKEN_LIST1 0x234b 	///../ucode/register.h:1257
#define P_I2C_M_3_TOKEN_LIST1 		CBUS_REG_ADDR(I2C_M_3_TOKEN_LIST1)
#define I2C_M_3_WDATA_REG0 0x234c 	///../ucode/register.h:1258
#define P_I2C_M_3_WDATA_REG0 		CBUS_REG_ADDR(I2C_M_3_WDATA_REG0)
#define I2C_M_3_WDATA_REG1 0x234d 	///../ucode/register.h:1259
#define P_I2C_M_3_WDATA_REG1 		CBUS_REG_ADDR(I2C_M_3_WDATA_REG1)
#define I2C_M_3_RDATA_REG0 0x234e 	///../ucode/register.h:1260
#define P_I2C_M_3_RDATA_REG0 		CBUS_REG_ADDR(I2C_M_3_RDATA_REG0)
#define I2C_M_3_RDATA_REG1 0x234f 	///../ucode/register.h:1261
#define P_I2C_M_3_RDATA_REG1 		CBUS_REG_ADDR(I2C_M_3_RDATA_REG1)
#define SPICC_RXDATA 0x2360 	///../ucode/register.h:1265
#define P_SPICC_RXDATA 		CBUS_REG_ADDR(SPICC_RXDATA)
#define SPICC_TXDATA 0x2361 	///../ucode/register.h:1266
#define P_SPICC_TXDATA 		CBUS_REG_ADDR(SPICC_TXDATA)
#define SPICC_CONREG 0x2362 	///../ucode/register.h:1267
#define P_SPICC_CONREG 		CBUS_REG_ADDR(SPICC_CONREG)
#define SPICC_INTREG 0x2363 	///../ucode/register.h:1268
#define P_SPICC_INTREG 		CBUS_REG_ADDR(SPICC_INTREG)
#define SPICC_DMAREG 0x2364 	///../ucode/register.h:1269
#define P_SPICC_DMAREG 		CBUS_REG_ADDR(SPICC_DMAREG)
#define SPICC_STATREG 0x2365 	///../ucode/register.h:1270
#define P_SPICC_STATREG 		CBUS_REG_ADDR(SPICC_STATREG)
#define SPICC_PERIODREG 0x2366 	///../ucode/register.h:1271
#define P_SPICC_PERIODREG 		CBUS_REG_ADDR(SPICC_PERIODREG)
#define SPICC_TESTREG 0x2367 	///../ucode/register.h:1272
#define P_SPICC_TESTREG 		CBUS_REG_ADDR(SPICC_TESTREG)
#define SPICC_DRADDR 0x2368 	///../ucode/register.h:1273
#define P_SPICC_DRADDR 		CBUS_REG_ADDR(SPICC_DRADDR)
#define SPICC_DWADDR 0x2369 	///../ucode/register.h:1274
#define P_SPICC_DWADDR 		CBUS_REG_ADDR(SPICC_DWADDR)
#define SD_REG0_ARGU 0x2380 	///../ucode/register.h:1278
#define P_SD_REG0_ARGU 		CBUS_REG_ADDR(SD_REG0_ARGU)
#define SD_REG1_SEND 0x2381 	///../ucode/register.h:1279
#define P_SD_REG1_SEND 		CBUS_REG_ADDR(SD_REG1_SEND)
#define SD_REG2_CNTL 0x2382 	///../ucode/register.h:1280
#define P_SD_REG2_CNTL 		CBUS_REG_ADDR(SD_REG2_CNTL)
#define SD_REG3_STAT 0x2383 	///../ucode/register.h:1281
#define P_SD_REG3_STAT 		CBUS_REG_ADDR(SD_REG3_STAT)
#define SD_REG4_CLKC 0x2384 	///../ucode/register.h:1282
#define P_SD_REG4_CLKC 		CBUS_REG_ADDR(SD_REG4_CLKC)
#define SD_REG5_ADDR 0x2385 	///../ucode/register.h:1283
#define P_SD_REG5_ADDR 		CBUS_REG_ADDR(SD_REG5_ADDR)
#define SD_REG6_PDMA 0x2386 	///../ucode/register.h:1284
#define P_SD_REG6_PDMA 		CBUS_REG_ADDR(SD_REG6_PDMA)
#define SD_REG7_MISC 0x2387 	///../ucode/register.h:1285
#define P_SD_REG7_MISC 		CBUS_REG_ADDR(SD_REG7_MISC)
#define SD_REG8_DATA 0x2388 	///../ucode/register.h:1286
#define P_SD_REG8_DATA 		CBUS_REG_ADDR(SD_REG8_DATA)
#define SD_REG9_ICTL 0x2389 	///../ucode/register.h:1287
#define P_SD_REG9_ICTL 		CBUS_REG_ADDR(SD_REG9_ICTL)
#define SD_REGA_ISTA 0x238a 	///../ucode/register.h:1288
#define P_SD_REGA_ISTA 		CBUS_REG_ADDR(SD_REGA_ISTA)
#define SD_REGB_SRST 0x238b 	///../ucode/register.h:1289
#define P_SD_REGB_SRST 		CBUS_REG_ADDR(SD_REGB_SRST)
#define SD_REGC_ESTA 0x238c 	///../ucode/register.h:1290
#define P_SD_REGC_ESTA 		CBUS_REG_ADDR(SD_REGC_ESTA)
#define SD_REGD_ENHC 0x238d 	///../ucode/register.h:1291
#define P_SD_REGD_ENHC 		CBUS_REG_ADDR(SD_REGD_ENHC)
#define SD_REGE_CLK2 0x238e 	///../ucode/register.h:1292
#define P_SD_REGE_CLK2 		CBUS_REG_ADDR(SD_REGE_CLK2)
#define ISA_DEBUG_REG0 0x2600 	///../ucode/register.h:1305
#define P_ISA_DEBUG_REG0 		CBUS_REG_ADDR(ISA_DEBUG_REG0)
#define ISA_DEBUG_REG1 0x2601 	///../ucode/register.h:1306
#define P_ISA_DEBUG_REG1 		CBUS_REG_ADDR(ISA_DEBUG_REG1)
#define ISA_DEBUG_REG2 0x2602 	///../ucode/register.h:1307
#define P_ISA_DEBUG_REG2 		CBUS_REG_ADDR(ISA_DEBUG_REG2)
#define ISA_DEBUG_REG3 0x2603 	///../ucode/register.h:1308
#define P_ISA_DEBUG_REG3 		CBUS_REG_ADDR(ISA_DEBUG_REG3)
#define ISA_PLL_CLK_SIM0 0x2608 	///../ucode/register.h:1309
#define P_ISA_PLL_CLK_SIM0 		CBUS_REG_ADDR(ISA_PLL_CLK_SIM0)
#define ISA_CNTL_REG0 0x2609 	///../ucode/register.h:1310
#define P_ISA_CNTL_REG0 		CBUS_REG_ADDR(ISA_CNTL_REG0)
#define AO_CPU_IRQ_IN0_INTR_STAT 0x2610 	///../ucode/register.h:1312
#define P_AO_CPU_IRQ_IN0_INTR_STAT 		CBUS_REG_ADDR(AO_CPU_IRQ_IN0_INTR_STAT)
#define AO_CPU_IRQ_IN0_INTR_STAT_CLR 0x2611 	///../ucode/register.h:1313
#define P_AO_CPU_IRQ_IN0_INTR_STAT_CLR 		CBUS_REG_ADDR(AO_CPU_IRQ_IN0_INTR_STAT_CLR)
#define AO_CPU_IRQ_IN0_INTR_MASK 0x2612 	///../ucode/register.h:1314
#define P_AO_CPU_IRQ_IN0_INTR_MASK 		CBUS_REG_ADDR(AO_CPU_IRQ_IN0_INTR_MASK)
#define AO_CPU_IRQ_IN0_INTR_FIRQ_SEL 0x2613 	///../ucode/register.h:1315
#define P_AO_CPU_IRQ_IN0_INTR_FIRQ_SEL 		CBUS_REG_ADDR(AO_CPU_IRQ_IN0_INTR_FIRQ_SEL)
#define GPIO_INTR_EDGE_POL 0x2620 	///../ucode/register.h:1330
#define P_GPIO_INTR_EDGE_POL 		CBUS_REG_ADDR(GPIO_INTR_EDGE_POL)
#define GPIO_INTR_GPIO_SEL0 0x2621 	///../ucode/register.h:1331
#define P_GPIO_INTR_GPIO_SEL0 		CBUS_REG_ADDR(GPIO_INTR_GPIO_SEL0)
#define GPIO_INTR_GPIO_SEL1 0x2622 	///../ucode/register.h:1332
#define P_GPIO_INTR_GPIO_SEL1 		CBUS_REG_ADDR(GPIO_INTR_GPIO_SEL1)
#define GPIO_INTR_FILTER_SEL0 0x2623 	///../ucode/register.h:1333
#define P_GPIO_INTR_FILTER_SEL0 		CBUS_REG_ADDR(GPIO_INTR_FILTER_SEL0)
#define MEDIA_CPU_INTR_STAT 0x2628 	///../ucode/register.h:1335
#define P_MEDIA_CPU_INTR_STAT 		CBUS_REG_ADDR(MEDIA_CPU_INTR_STAT)
#define MEDIA_CPU_INTR_STAT_CLR 0x2629 	///../ucode/register.h:1336
#define P_MEDIA_CPU_INTR_STAT_CLR 		CBUS_REG_ADDR(MEDIA_CPU_INTR_STAT_CLR)
#define MEDIA_CPU_INTR_MASK 0x262a 	///../ucode/register.h:1337
#define P_MEDIA_CPU_INTR_MASK 		CBUS_REG_ADDR(MEDIA_CPU_INTR_MASK)
#define MEDIA_CPU_INTR_FIRQ_SEL 0x262b 	///../ucode/register.h:1338
#define P_MEDIA_CPU_INTR_FIRQ_SEL 		CBUS_REG_ADDR(MEDIA_CPU_INTR_FIRQ_SEL)
#define ISA_BIST_REG0 0x2630 	///../ucode/register.h:1340
#define P_ISA_BIST_REG0 		CBUS_REG_ADDR(ISA_BIST_REG0)
#define ISA_BIST_REG1 0x2631 	///../ucode/register.h:1341
#define P_ISA_BIST_REG1 		CBUS_REG_ADDR(ISA_BIST_REG1)
#define WATCHDOG_TC 0x2640 	///../ucode/register.h:1343
#define P_WATCHDOG_TC 		CBUS_REG_ADDR(WATCHDOG_TC)
#define WATCHDOG_RESET 0x2641 	///../ucode/register.h:1344
#define P_WATCHDOG_RESET 		CBUS_REG_ADDR(WATCHDOG_RESET)
#define AHB_ARBITER_REG 0x2642 	///../ucode/register.h:1346
#define P_AHB_ARBITER_REG 		CBUS_REG_ADDR(AHB_ARBITER_REG)
#define AHB_ARBDEC_REG 0x2643 	///../ucode/register.h:1347
#define P_AHB_ARBDEC_REG 		CBUS_REG_ADDR(AHB_ARBDEC_REG)
#define AHB_ARBITER2_REG 0x264a 	///../ucode/register.h:1348
#define P_AHB_ARBITER2_REG 		CBUS_REG_ADDR(AHB_ARBITER2_REG)
#define DEVICE_MMCP_CNTL 0x264b 	///../ucode/register.h:1349
#define P_DEVICE_MMCP_CNTL 		CBUS_REG_ADDR(DEVICE_MMCP_CNTL)
#define AUDIO_MMCP_CNTL 0x264c 	///../ucode/register.h:1350
#define P_AUDIO_MMCP_CNTL 		CBUS_REG_ADDR(AUDIO_MMCP_CNTL)
#define ISA_TIMER_MUX 0x2650 	///../ucode/register.h:1352
#define P_ISA_TIMER_MUX 		CBUS_REG_ADDR(ISA_TIMER_MUX)
#define ISA_TIMERA 0x2651 	///../ucode/register.h:1353
#define P_ISA_TIMERA 		CBUS_REG_ADDR(ISA_TIMERA)
#define ISA_TIMERB 0x2652 	///../ucode/register.h:1354
#define P_ISA_TIMERB 		CBUS_REG_ADDR(ISA_TIMERB)
#define ISA_TIMERC 0x2653 	///../ucode/register.h:1355
#define P_ISA_TIMERC 		CBUS_REG_ADDR(ISA_TIMERC)
#define ISA_TIMERD 0x2654 	///../ucode/register.h:1356
#define P_ISA_TIMERD 		CBUS_REG_ADDR(ISA_TIMERD)
#define ISA_TIMERE 0x2655 	///../ucode/register.h:1357
#define P_ISA_TIMERE 		CBUS_REG_ADDR(ISA_TIMERE)
#define FBUF_ADDR 0x2656 	///../ucode/register.h:1358
#define P_FBUF_ADDR 		CBUS_REG_ADDR(FBUF_ADDR)
#define SDRAM_CTL0 0x2657 	///../ucode/register.h:1361
#define P_SDRAM_CTL0 		CBUS_REG_ADDR(SDRAM_CTL0)
#define SDRAM_CTL2 0x2658 	///../ucode/register.h:1362
#define P_SDRAM_CTL2 		CBUS_REG_ADDR(SDRAM_CTL2)
#define SDRAM_CTL4 0x265a 	///../ucode/register.h:1364
#define P_SDRAM_CTL4 		CBUS_REG_ADDR(SDRAM_CTL4)
#define SDRAM_CTL5 0x265b 	///../ucode/register.h:1365
#define P_SDRAM_CTL5 		CBUS_REG_ADDR(SDRAM_CTL5)
#define SDRAM_CTL6 0x265c 	///../ucode/register.h:1366
#define P_SDRAM_CTL6 		CBUS_REG_ADDR(SDRAM_CTL6)
#define SDRAM_CTL7 0x265d 	///../ucode/register.h:1367
#define P_SDRAM_CTL7 		CBUS_REG_ADDR(SDRAM_CTL7)
#define SDRAM_CTL8 0x265e 	///../ucode/register.h:1368
#define P_SDRAM_CTL8 		CBUS_REG_ADDR(SDRAM_CTL8)
#define AHB_MP4_MC_CTL 0x265f 	///../ucode/register.h:1369
#define P_AHB_MP4_MC_CTL 		CBUS_REG_ADDR(AHB_MP4_MC_CTL)
#define MEDIA_CPU_PCR 0x2660 	///../ucode/register.h:1370
#define P_MEDIA_CPU_PCR 		CBUS_REG_ADDR(MEDIA_CPU_PCR)
#define MEDIA_CPU_CTL 0x2661 	///../ucode/register.h:1371
#define P_MEDIA_CPU_CTL 		CBUS_REG_ADDR(MEDIA_CPU_CTL)
#define ISA_TIMER_MUX1 0x2664 	///../ucode/register.h:1372
#define P_ISA_TIMER_MUX1 		CBUS_REG_ADDR(ISA_TIMER_MUX1)
#define ISA_TIMERF 0x2665 	///../ucode/register.h:1373
#define P_ISA_TIMERF 		CBUS_REG_ADDR(ISA_TIMERF)
#define ISA_TIMERG 0x2666 	///../ucode/register.h:1374
#define P_ISA_TIMERG 		CBUS_REG_ADDR(ISA_TIMERG)
#define ISA_TIMERH 0x2667 	///../ucode/register.h:1375
#define P_ISA_TIMERH 		CBUS_REG_ADDR(ISA_TIMERH)
#define ISA_TIMERI 0x2668 	///../ucode/register.h:1376
#define P_ISA_TIMERI 		CBUS_REG_ADDR(ISA_TIMERI)
#define ABUF_WR_CTL0 0x2670 	///../ucode/register.h:1378
#define P_ABUF_WR_CTL0 		CBUS_REG_ADDR(ABUF_WR_CTL0)
#define ABUF_WR_CTL1 0x2671 	///../ucode/register.h:1384
#define P_ABUF_WR_CTL1 		CBUS_REG_ADDR(ABUF_WR_CTL1)
#define ABUF_WR_CTL2 0x2672 	///../ucode/register.h:1390
#define P_ABUF_WR_CTL2 		CBUS_REG_ADDR(ABUF_WR_CTL2)
#define ABUF_WR_CTL3 0x2673 	///../ucode/register.h:1395
#define P_ABUF_WR_CTL3 		CBUS_REG_ADDR(ABUF_WR_CTL3)
#define ABUF_RD_CTL0 0x2674 	///../ucode/register.h:1400
#define P_ABUF_RD_CTL0 		CBUS_REG_ADDR(ABUF_RD_CTL0)
#define ABUF_RD_CTL1 0x2675 	///../ucode/register.h:1401
#define P_ABUF_RD_CTL1 		CBUS_REG_ADDR(ABUF_RD_CTL1)
#define ABUF_RD_CTL2 0x2676 	///../ucode/register.h:1407
#define P_ABUF_RD_CTL2 		CBUS_REG_ADDR(ABUF_RD_CTL2)
#define ABUF_RD_CTL3 0x2677 	///../ucode/register.h:1412
#define P_ABUF_RD_CTL3 		CBUS_REG_ADDR(ABUF_RD_CTL3)
#define ABUF_ARB_CTL0 0x2678 	///../ucode/register.h:1418
#define P_ABUF_ARB_CTL0 		CBUS_REG_ADDR(ABUF_ARB_CTL0)
#define ABUF_FIFO_CTL0 0x2679 	///../ucode/register.h:1419
#define P_ABUF_FIFO_CTL0 		CBUS_REG_ADDR(ABUF_FIFO_CTL0)
#define AHB_BRIDGE_CNTL_WR 0x2680 	///../ucode/register.h:1425
#define P_AHB_BRIDGE_CNTL_WR 		CBUS_REG_ADDR(AHB_BRIDGE_CNTL_WR)
#define AHB_BRIDGE_REMAP0 0x2681 	///../ucode/register.h:1426
#define P_AHB_BRIDGE_REMAP0 		CBUS_REG_ADDR(AHB_BRIDGE_REMAP0)
#define AHB_BRIDGE_REMAP1 0x2682 	///../ucode/register.h:1427
#define P_AHB_BRIDGE_REMAP1 		CBUS_REG_ADDR(AHB_BRIDGE_REMAP1)
#define AHB_BRIDGE_REMAP2 0x2683 	///../ucode/register.h:1428
#define P_AHB_BRIDGE_REMAP2 		CBUS_REG_ADDR(AHB_BRIDGE_REMAP2)
#define AHB_BRIDGE_REMAP3 0x2684 	///../ucode/register.h:1429
#define P_AHB_BRIDGE_REMAP3 		CBUS_REG_ADDR(AHB_BRIDGE_REMAP3)
#define AHB_BRIDGE_CNTL_REG1 0x2685 	///../ucode/register.h:1430
#define P_AHB_BRIDGE_CNTL_REG1 		CBUS_REG_ADDR(AHB_BRIDGE_CNTL_REG1)
#define AHB_BRIDGE_CNTL_REG2 0x2686 	///../ucode/register.h:1431
#define P_AHB_BRIDGE_CNTL_REG2 		CBUS_REG_ADDR(AHB_BRIDGE_CNTL_REG2)
#define IQ_OM_WIDTH 0x2510 	///../ucode/register.h:1548
#define P_IQ_OM_WIDTH 		CBUS_REG_ADDR(IQ_OM_WIDTH)
#define DBG_ADDR_START 0x2ff0 	///../ucode/register.h:1550
#define P_DBG_ADDR_START 		CBUS_REG_ADDR(DBG_ADDR_START)
#define DBG_ADDR_END 0x2fff 	///../ucode/register.h:1551
#define P_DBG_ADDR_END 		CBUS_REG_ADDR(DBG_ADDR_END)
#define DBG_CTRL 0x2ff1 	///../ucode/register.h:1552
#define P_DBG_CTRL 		CBUS_REG_ADDR(DBG_CTRL)
#define DBG_LED 0x2ff2 	///../ucode/register.h:1553
#define P_DBG_LED 		CBUS_REG_ADDR(DBG_LED)
#define DBG_SWITCH 0x2ff3 	///../ucode/register.h:1554
#define P_DBG_SWITCH 		CBUS_REG_ADDR(DBG_SWITCH)
#define DBG_VERSION 0x2ff4 	///../ucode/register.h:1555
#define P_DBG_VERSION 		CBUS_REG_ADDR(DBG_VERSION)
#define VERSION_CTRL 0x1100 	///../ucode/register.h:1563
#define P_VERSION_CTRL 		CBUS_REG_ADDR(VERSION_CTRL)
#define RESET0_REGISTER 0x1101 	///../ucode/register.h:1564
#define P_RESET0_REGISTER 		CBUS_REG_ADDR(RESET0_REGISTER)
#define RESET1_REGISTER 0x1102 	///../ucode/register.h:1565
#define P_RESET1_REGISTER 		CBUS_REG_ADDR(RESET1_REGISTER)
#define RESET2_REGISTER 0x1103 	///../ucode/register.h:1566
#define P_RESET2_REGISTER 		CBUS_REG_ADDR(RESET2_REGISTER)
#define RESET3_REGISTER 0x1104 	///../ucode/register.h:1567
#define P_RESET3_REGISTER 		CBUS_REG_ADDR(RESET3_REGISTER)
#define RESET4_REGISTER 0x1105 	///../ucode/register.h:1568
#define P_RESET4_REGISTER 		CBUS_REG_ADDR(RESET4_REGISTER)
#define RESET5_REGISTER 0x1106 	///../ucode/register.h:1569
#define P_RESET5_REGISTER 		CBUS_REG_ADDR(RESET5_REGISTER)
#define RESET6_REGISTER 0x1107 	///../ucode/register.h:1570
#define P_RESET6_REGISTER 		CBUS_REG_ADDR(RESET6_REGISTER)
#define RESET7_REGISTER 0x1108 	///../ucode/register.h:1571
#define P_RESET7_REGISTER 		CBUS_REG_ADDR(RESET7_REGISTER)
#define RESET0_MASK 0x1110 	///../ucode/register.h:1572
#define P_RESET0_MASK 		CBUS_REG_ADDR(RESET0_MASK)
#define RESET1_MASK 0x1111 	///../ucode/register.h:1573
#define P_RESET1_MASK 		CBUS_REG_ADDR(RESET1_MASK)
#define RESET2_MASK 0x1112 	///../ucode/register.h:1574
#define P_RESET2_MASK 		CBUS_REG_ADDR(RESET2_MASK)
#define RESET3_MASK 0x1113 	///../ucode/register.h:1575
#define P_RESET3_MASK 		CBUS_REG_ADDR(RESET3_MASK)
#define RESET4_MASK 0x1114 	///../ucode/register.h:1576
#define P_RESET4_MASK 		CBUS_REG_ADDR(RESET4_MASK)
#define RESET5_MASK 0x1115 	///../ucode/register.h:1577
#define P_RESET5_MASK 		CBUS_REG_ADDR(RESET5_MASK)
#define RESET6_MASK 0x1116 	///../ucode/register.h:1578
#define P_RESET6_MASK 		CBUS_REG_ADDR(RESET6_MASK)
#define CRT_MASK 0x1117 	///../ucode/register.h:1579
#define P_CRT_MASK 		CBUS_REG_ADDR(CRT_MASK)
#define RESET7_MASK 0x1118 	///../ucode/register.h:1580
#define P_RESET7_MASK 		CBUS_REG_ADDR(RESET7_MASK)
#define RESET0_LEVEL 0x1120 	///../ucode/register.h:1581
#define P_RESET0_LEVEL 		CBUS_REG_ADDR(RESET0_LEVEL)
#define RESET1_LEVEL 0x1121 	///../ucode/register.h:1582
#define P_RESET1_LEVEL 		CBUS_REG_ADDR(RESET1_LEVEL)
#define RESET2_LEVEL 0x1122 	///../ucode/register.h:1583
#define P_RESET2_LEVEL 		CBUS_REG_ADDR(RESET2_LEVEL)
#define RESET3_LEVEL 0x1123 	///../ucode/register.h:1584
#define P_RESET3_LEVEL 		CBUS_REG_ADDR(RESET3_LEVEL)
#define RESET4_LEVEL 0x1124 	///../ucode/register.h:1585
#define P_RESET4_LEVEL 		CBUS_REG_ADDR(RESET4_LEVEL)
#define RESET5_LEVEL 0x1125 	///../ucode/register.h:1586
#define P_RESET5_LEVEL 		CBUS_REG_ADDR(RESET5_LEVEL)
#define RESET6_LEVEL 0x1126 	///../ucode/register.h:1587
#define P_RESET6_LEVEL 		CBUS_REG_ADDR(RESET6_LEVEL)
#define RESET7_LEVEL 0x1127 	///../ucode/register.h:1588
#define P_RESET7_LEVEL 		CBUS_REG_ADDR(RESET7_LEVEL)
#define SCR_HIU 0x100b 	///../ucode/register.h:1610
#define P_SCR_HIU 		CBUS_REG_ADDR(SCR_HIU)
#define HPG_TIMER 0x100f 	///../ucode/register.h:1611
#define P_HPG_TIMER 		CBUS_REG_ADDR(HPG_TIMER)
#define HARM_ASB_MB0 0x1030 	///../ucode/register.h:1612
#define P_HARM_ASB_MB0 		CBUS_REG_ADDR(HARM_ASB_MB0)
#define HARM_ASB_MB1 0x1031 	///../ucode/register.h:1613
#define P_HARM_ASB_MB1 		CBUS_REG_ADDR(HARM_ASB_MB1)
#define HARM_ASB_MB2 0x1032 	///../ucode/register.h:1614
#define P_HARM_ASB_MB2 		CBUS_REG_ADDR(HARM_ASB_MB2)
#define HARM_ASB_MB3 0x1033 	///../ucode/register.h:1615
#define P_HARM_ASB_MB3 		CBUS_REG_ADDR(HARM_ASB_MB3)
#define HASB_ARM_MB0 0x1034 	///../ucode/register.h:1616
#define P_HASB_ARM_MB0 		CBUS_REG_ADDR(HASB_ARM_MB0)
#define HASB_ARM_MB1 0x1035 	///../ucode/register.h:1617
#define P_HASB_ARM_MB1 		CBUS_REG_ADDR(HASB_ARM_MB1)
#define HASB_ARM_MB2 0x1036 	///../ucode/register.h:1618
#define P_HASB_ARM_MB2 		CBUS_REG_ADDR(HASB_ARM_MB2)
#define HASB_ARM_MB3 0x1037 	///../ucode/register.h:1619
#define P_HASB_ARM_MB3 		CBUS_REG_ADDR(HASB_ARM_MB3)
#define HHI_TIMER90K 0x103b 	///../ucode/register.h:1620
#define P_HHI_TIMER90K 		CBUS_REG_ADDR(HHI_TIMER90K)
#define HHI_MEM_PD_REG0 0x1040 	///../ucode/register.h:1621
#define P_HHI_MEM_PD_REG0 		CBUS_REG_ADDR(HHI_MEM_PD_REG0)
#define HHI_VPU_MEM_PD_REG0 0x1041 	///../ucode/register.h:1622
#define P_HHI_VPU_MEM_PD_REG0 		CBUS_REG_ADDR(HHI_VPU_MEM_PD_REG0)
#define HHI_VPU_MEM_PD_REG1 0x1042 	///../ucode/register.h:1623
#define P_HHI_VPU_MEM_PD_REG1 		CBUS_REG_ADDR(HHI_VPU_MEM_PD_REG1)
#define HHI_AUD_DAC_CTRL 0x1044 	///../ucode/register.h:1624
#define P_HHI_AUD_DAC_CTRL 		CBUS_REG_ADDR(HHI_AUD_DAC_CTRL)
#define HHI_VIID_CLK_DIV 0x104a 	///../ucode/register.h:1629
#define P_HHI_VIID_CLK_DIV 		CBUS_REG_ADDR(HHI_VIID_CLK_DIV)
#define HHI_VIID_CLK_CNTL 0x104b 	///../ucode/register.h:1630
#define P_HHI_VIID_CLK_CNTL 		CBUS_REG_ADDR(HHI_VIID_CLK_CNTL)
#define HHI_VIID_DIVIDER_CNTL 0x104c 	///../ucode/register.h:1631
#define P_HHI_VIID_DIVIDER_CNTL 		CBUS_REG_ADDR(HHI_VIID_DIVIDER_CNTL)
#define HHI_GCLK_MPEG0 0x1050 	///../ucode/register.h:1633
#define P_HHI_GCLK_MPEG0 		CBUS_REG_ADDR(HHI_GCLK_MPEG0)
#define HHI_GCLK_MPEG1 0x1051 	///../ucode/register.h:1634
#define P_HHI_GCLK_MPEG1 		CBUS_REG_ADDR(HHI_GCLK_MPEG1)
#define HHI_GCLK_MPEG2 0x1052 	///../ucode/register.h:1635
#define P_HHI_GCLK_MPEG2 		CBUS_REG_ADDR(HHI_GCLK_MPEG2)
#define HHI_GCLK_OTHER 0x1054 	///../ucode/register.h:1636
#define P_HHI_GCLK_OTHER 		CBUS_REG_ADDR(HHI_GCLK_OTHER)
#define HHI_GCLK_AO 0x1055 	///../ucode/register.h:1637
#define P_HHI_GCLK_AO 		CBUS_REG_ADDR(HHI_GCLK_AO)
#define HHI_SYS_CPU_CLK_CNTL1 0x1057 	///../ucode/register.h:1638
#define P_HHI_SYS_CPU_CLK_CNTL1 		CBUS_REG_ADDR(HHI_SYS_CPU_CLK_CNTL1)
#define HHI_VID_CLK_DIV 0x1059 	///../ucode/register.h:1640
#define P_HHI_VID_CLK_DIV 		CBUS_REG_ADDR(HHI_VID_CLK_DIV)
#define HHI_MPEG_CLK_CNTL 0x105d 	///../ucode/register.h:1641
#define P_HHI_MPEG_CLK_CNTL 		CBUS_REG_ADDR(HHI_MPEG_CLK_CNTL)
#define HHI_AUD_CLK_CNTL 0x105e 	///../ucode/register.h:1642
#define P_HHI_AUD_CLK_CNTL 		CBUS_REG_ADDR(HHI_AUD_CLK_CNTL)
#define HHI_VID_CLK_CNTL 0x105f 	///../ucode/register.h:1643
#define P_HHI_VID_CLK_CNTL 		CBUS_REG_ADDR(HHI_VID_CLK_CNTL)
#define HHI_WIFI_CLK_CNTL 0x1060 	///../ucode/register.h:1644
#define P_HHI_WIFI_CLK_CNTL 		CBUS_REG_ADDR(HHI_WIFI_CLK_CNTL)
#define HHI_WIFI_PLL_CNTL 0x1061 	///../ucode/register.h:1645
#define P_HHI_WIFI_PLL_CNTL 		CBUS_REG_ADDR(HHI_WIFI_PLL_CNTL)
#define HHI_WIFI_PLL_CNTL2 0x1062 	///../ucode/register.h:1646
#define P_HHI_WIFI_PLL_CNTL2 		CBUS_REG_ADDR(HHI_WIFI_PLL_CNTL2)
#define HHI_WIFI_PLL_CNTL3 0x1063 	///../ucode/register.h:1647
#define P_HHI_WIFI_PLL_CNTL3 		CBUS_REG_ADDR(HHI_WIFI_PLL_CNTL3)
#define HHI_AUD_CLK_CNTL2 0x1064 	///../ucode/register.h:1648
#define P_HHI_AUD_CLK_CNTL2 		CBUS_REG_ADDR(HHI_AUD_CLK_CNTL2)
#define HHI_VID_CLK_CNTL2 0x1065 	///../ucode/register.h:1649
#define P_HHI_VID_CLK_CNTL2 		CBUS_REG_ADDR(HHI_VID_CLK_CNTL2)
#define HHI_VID_DIVIDER_CNTL 0x1066 	///../ucode/register.h:1650
#define P_HHI_VID_DIVIDER_CNTL 		CBUS_REG_ADDR(HHI_VID_DIVIDER_CNTL)
#define HHI_SYS_CPU_CLK_CNTL 0x1067 	///../ucode/register.h:1651
#define P_HHI_SYS_CPU_CLK_CNTL 		CBUS_REG_ADDR(HHI_SYS_CPU_CLK_CNTL)
#define HHI_MALI_CLK_CNTL 0x106c 	///../ucode/register.h:1656
#define P_HHI_MALI_CLK_CNTL 		CBUS_REG_ADDR(HHI_MALI_CLK_CNTL)
#define HHI_MIPI_PHY_CLK_CNTL 0x106e 	///../ucode/register.h:1657
#define P_HHI_MIPI_PHY_CLK_CNTL 		CBUS_REG_ADDR(HHI_MIPI_PHY_CLK_CNTL)
#define HHI_VPU_CLK_CNTL 0x106f 	///../ucode/register.h:1658
#define P_HHI_VPU_CLK_CNTL 		CBUS_REG_ADDR(HHI_VPU_CLK_CNTL)
#define HHI_OTHER_PLL_CNTL 0x1070 	///../ucode/register.h:1659
#define P_HHI_OTHER_PLL_CNTL 		CBUS_REG_ADDR(HHI_OTHER_PLL_CNTL)
#define HHI_OTHER_PLL_CNTL2 0x1071 	///../ucode/register.h:1660
#define P_HHI_OTHER_PLL_CNTL2 		CBUS_REG_ADDR(HHI_OTHER_PLL_CNTL2)
#define HHI_OTHER_PLL_CNTL3 0x1072 	///../ucode/register.h:1661
#define P_HHI_OTHER_PLL_CNTL3 		CBUS_REG_ADDR(HHI_OTHER_PLL_CNTL3)
#define HHI_HDMI_CLK_CNTL 0x1073 	///../ucode/register.h:1662
#define P_HHI_HDMI_CLK_CNTL 		CBUS_REG_ADDR(HHI_HDMI_CLK_CNTL)
#define HHI_DEMOD_CLK_CNTL 0x1074 	///../ucode/register.h:1663
#define P_HHI_DEMOD_CLK_CNTL 		CBUS_REG_ADDR(HHI_DEMOD_CLK_CNTL)
#define HHI_SATA_CLK_CNTL 0x1075 	///../ucode/register.h:1664
#define P_HHI_SATA_CLK_CNTL 		CBUS_REG_ADDR(HHI_SATA_CLK_CNTL)
#define HHI_ETH_CLK_CNTL 0x1076 	///../ucode/register.h:1665
#define P_HHI_ETH_CLK_CNTL 		CBUS_REG_ADDR(HHI_ETH_CLK_CNTL)
#define HHI_CLK_DOUBLE_CNTL 0x1077 	///../ucode/register.h:1666
#define P_HHI_CLK_DOUBLE_CNTL 		CBUS_REG_ADDR(HHI_CLK_DOUBLE_CNTL)
#define HHI_VDEC_CLK_CNTL 0x1078 	///../ucode/register.h:1667
#define P_HHI_VDEC_CLK_CNTL 		CBUS_REG_ADDR(HHI_VDEC_CLK_CNTL)
#define HHI_VDEC2_CLK_CNTL 0x1079 	///../ucode/register.h:1668
#define P_HHI_VDEC2_CLK_CNTL 		CBUS_REG_ADDR(HHI_VDEC2_CLK_CNTL)
#define HHI_VDEC3_CLK_CNTL 0x107a 	///../ucode/register.h:1669
#define P_HHI_VDEC3_CLK_CNTL 		CBUS_REG_ADDR(HHI_VDEC3_CLK_CNTL)
#define HHI_EDP_APB_CLK_CNTL 0x107b 	///../ucode/register.h:1589
#define P_HHI_EDP_APB_CLK_CNTL 		CBUS_REG_ADDR(HHI_EDP_APB_CLK_CNTL)

#define HHI_VDEC4_CLK_CNTL 0x107b 	///../ucode/register.h:1670
#define P_HHI_VDEC4_CLK_CNTL 		CBUS_REG_ADDR(HHI_VDEC4_CLK_CNTL)
#define HHI_HDMI_PLL_CNTL 0x107c 	///../ucode/register.h:1676
#define P_HHI_HDMI_PLL_CNTL 		CBUS_REG_ADDR(HHI_HDMI_PLL_CNTL)
#define HHI_HDMI_PLL_CNTL1 0x107d 	///../ucode/register.h:1677
#define P_HHI_HDMI_PLL_CNTL1 		CBUS_REG_ADDR(HHI_HDMI_PLL_CNTL1)
#define HHI_HDMI_PLL_CNTL2 0x107e 	///../ucode/register.h:1678
#define P_HHI_HDMI_PLL_CNTL2 		CBUS_REG_ADDR(HHI_HDMI_PLL_CNTL2)
#define HHI_HDMI_AFC_CNTL 0x107f 	///../ucode/register.h:1679
#define P_HHI_HDMI_AFC_CNTL 		CBUS_REG_ADDR(HHI_HDMI_AFC_CNTL)
#define HHI_HDMIRX_CLK_CNTL 0x1080 	///../ucode/register.h:1680
#define P_HHI_HDMIRX_CLK_CNTL 		CBUS_REG_ADDR(HHI_HDMIRX_CLK_CNTL)
#define HHI_HDMIRX_AUD_CLK_CNTL 0x1081 	///../ucode/register.h:1681
#define P_HHI_HDMIRX_AUD_CLK_CNTL 		CBUS_REG_ADDR(HHI_HDMIRX_AUD_CLK_CNTL)
#define HHI_VID_PLL_MOD_CNTL0 0x1084 	///../ucode/register.h:1682
#define P_HHI_VID_PLL_MOD_CNTL0 		CBUS_REG_ADDR(HHI_VID_PLL_MOD_CNTL0)
#define HHI_VID_PLL_MOD_LOW_TCNT 0x1085 	///../ucode/register.h:1683
#define P_HHI_VID_PLL_MOD_LOW_TCNT 		CBUS_REG_ADDR(HHI_VID_PLL_MOD_LOW_TCNT)
#define HHI_VID_PLL_MOD_HIGH_TCNT 0x1086 	///../ucode/register.h:1684
#define P_HHI_VID_PLL_MOD_HIGH_TCNT 		CBUS_REG_ADDR(HHI_VID_PLL_MOD_HIGH_TCNT)
#define HHI_VID_PLL_MOD_NOM_TCNT 0x1087 	///../ucode/register.h:1685
#define P_HHI_VID_PLL_MOD_NOM_TCNT 		CBUS_REG_ADDR(HHI_VID_PLL_MOD_NOM_TCNT)
#define HHI_USB_CLK_CNTL 0x1089 	///../ucode/register.h:1687
#define P_HHI_USB_CLK_CNTL 		CBUS_REG_ADDR(HHI_USB_CLK_CNTL)
#define HHI_GEN_CLK_CNTL 0x108a 	///../ucode/register.h:1688
#define P_HHI_GEN_CLK_CNTL 		CBUS_REG_ADDR(HHI_GEN_CLK_CNTL)
#define HHI_GEN_CLK_CNTL2 0x108b 	///../ucode/register.h:1689
#define P_HHI_GEN_CLK_CNTL2 		CBUS_REG_ADDR(HHI_GEN_CLK_CNTL2)
#define HHI_JTAG_CONFIG 0x108e 	///../ucode/register.h:1690
#define P_HHI_JTAG_CONFIG 		CBUS_REG_ADDR(HHI_JTAG_CONFIG)
#define HHI_VAFE_CLKXTALIN_CNTL 0x108f 	///../ucode/register.h:1691
#define P_HHI_VAFE_CLKXTALIN_CNTL 		CBUS_REG_ADDR(HHI_VAFE_CLKXTALIN_CNTL)
#define HHI_VAFE_CLKOSCIN_CNTL 0x1090 	///../ucode/register.h:1692
#define P_HHI_VAFE_CLKOSCIN_CNTL 		CBUS_REG_ADDR(HHI_VAFE_CLKOSCIN_CNTL)
#define HHI_VAFE_CLKIN_CNTL 0x1091 	///../ucode/register.h:1693
#define P_HHI_VAFE_CLKIN_CNTL 		CBUS_REG_ADDR(HHI_VAFE_CLKIN_CNTL)
#define HHI_TVFE_AUTOMODE_CLK_CNTL 0x1092 	///../ucode/register.h:1694
#define P_HHI_TVFE_AUTOMODE_CLK_CNTL 		CBUS_REG_ADDR(HHI_TVFE_AUTOMODE_CLK_CNTL)
#define HHI_VAFE_CLKPI_CNTL 0x1093 	///../ucode/register.h:1695
#define P_HHI_VAFE_CLKPI_CNTL 		CBUS_REG_ADDR(HHI_VAFE_CLKPI_CNTL)
#define HHI_VDIN_MEAS_CLK_CNTL 0x1094 	///../ucode/register.h:1696
#define P_HHI_VDIN_MEAS_CLK_CNTL 		CBUS_REG_ADDR(HHI_VDIN_MEAS_CLK_CNTL)
#define HHI_PCM_CLK_CNTL 0x1096 	///../ucode/register.h:1698
#define P_HHI_PCM_CLK_CNTL 		CBUS_REG_ADDR(HHI_PCM_CLK_CNTL)
#define HHI_NAND_CLK_CNTL 0x1097 	///../ucode/register.h:1699
#define P_HHI_NAND_CLK_CNTL 		CBUS_REG_ADDR(HHI_NAND_CLK_CNTL)
#define HHI_ISP_LED_CLK_CNTL 0x1098 	///../ucode/register.h:1700
#define P_HHI_ISP_LED_CLK_CNTL 		CBUS_REG_ADDR(HHI_ISP_LED_CLK_CNTL)
#define HHI_EDP_TX_PHY_CNTL0 0x109c 	///../ucode/register.h:1619
#define P_HHI_EDP_TX_PHY_CNTL0 		CBUS_REG_ADDR(HHI_EDP_TX_PHY_CNTL0)
#define HHI_EDP_TX_PHY_CNTL1 0x109d 	///../ucode/register.h:1620
#define P_HHI_EDP_TX_PHY_CNTL1 		CBUS_REG_ADDR(HHI_EDP_TX_PHY_CNTL1)
#define HHI_MPLL_CNTL 0x10a0 	///../ucode/register.h:1621
#define P_HHI_MPLL_CNTL 		CBUS_REG_ADDR(HHI_MPLL_CNTL)
#define HHI_MPLL_CNTL2 0x10a1 	///../ucode/register.h:1704
#define P_HHI_MPLL_CNTL2 		CBUS_REG_ADDR(HHI_MPLL_CNTL2)
#define HHI_MPLL_CNTL3 0x10a2 	///../ucode/register.h:1705
#define P_HHI_MPLL_CNTL3 		CBUS_REG_ADDR(HHI_MPLL_CNTL3)
#define HHI_MPLL_CNTL4 0x10a3 	///../ucode/register.h:1706
#define P_HHI_MPLL_CNTL4 		CBUS_REG_ADDR(HHI_MPLL_CNTL4)
#define HHI_MPLL_CNTL5 0x10a4 	///../ucode/register.h:1707
#define P_HHI_MPLL_CNTL5 		CBUS_REG_ADDR(HHI_MPLL_CNTL5)
#define HHI_MPLL_CNTL6 0x10a5 	///../ucode/register.h:1708
#define P_HHI_MPLL_CNTL6 		CBUS_REG_ADDR(HHI_MPLL_CNTL6)
#define HHI_MPLL_CNTL7 0x10a6 	///../ucode/register.h:1709
#define P_HHI_MPLL_CNTL7 		CBUS_REG_ADDR(HHI_MPLL_CNTL7)
#define HHI_MPLL_CNTL8 0x10a7 	///../ucode/register.h:1710
#define P_HHI_MPLL_CNTL8 		CBUS_REG_ADDR(HHI_MPLL_CNTL8)
#define HHI_MPLL_CNTL9 0x10a8 	///../ucode/register.h:1711
#define P_HHI_MPLL_CNTL9 		CBUS_REG_ADDR(HHI_MPLL_CNTL9)
#define HHI_MPLL_CNTL10 0x10a9 	///../ucode/register.h:1712
#define P_HHI_MPLL_CNTL10 		CBUS_REG_ADDR(HHI_MPLL_CNTL10)
#define HHI_ADC_PLL_CNTL 0x10aa 	///../ucode/register.h:1713
#define P_HHI_ADC_PLL_CNTL 		CBUS_REG_ADDR(HHI_ADC_PLL_CNTL)
#define HHI_ADC_PLL_CNTL2 0x10ab 	///../ucode/register.h:1714
#define P_HHI_ADC_PLL_CNTL2 		CBUS_REG_ADDR(HHI_ADC_PLL_CNTL2)
#define HHI_ADC_PLL_CNTL3 0x10ac 	///../ucode/register.h:1715
#define P_HHI_ADC_PLL_CNTL3 		CBUS_REG_ADDR(HHI_ADC_PLL_CNTL3)
#define HHI_ADC_PLL_CNTL4 0x10ad 	///../ucode/register.h:1716
#define P_HHI_ADC_PLL_CNTL4 		CBUS_REG_ADDR(HHI_ADC_PLL_CNTL4)
#define HHI_ADC_PLL_CNTL5 0x10ae 	///../ucode/register.h:1717
#define P_HHI_ADC_PLL_CNTL5 		CBUS_REG_ADDR(HHI_ADC_PLL_CNTL5)
#define HHI_ADC_PLL_CNTL6 0x10af 	///../ucode/register.h:1718
#define P_HHI_ADC_PLL_CNTL6 		CBUS_REG_ADDR(HHI_ADC_PLL_CNTL6)
#define HHI_AUDCLK_PLL_CNTL 0x10b0 	///../ucode/register.h:1719
#define P_HHI_AUDCLK_PLL_CNTL 		CBUS_REG_ADDR(HHI_AUDCLK_PLL_CNTL)
#define HHI_AUDCLK_PLL_CNTL2 0x10b1 	///../ucode/register.h:1720
#define P_HHI_AUDCLK_PLL_CNTL2 		CBUS_REG_ADDR(HHI_AUDCLK_PLL_CNTL2)
#define HHI_AUDCLK_PLL_CNTL3 0x10b2 	///../ucode/register.h:1721
#define P_HHI_AUDCLK_PLL_CNTL3 		CBUS_REG_ADDR(HHI_AUDCLK_PLL_CNTL3)
#define HHI_AUDCLK_PLL_CNTL4 0x10b3 	///../ucode/register.h:1722
#define P_HHI_AUDCLK_PLL_CNTL4 		CBUS_REG_ADDR(HHI_AUDCLK_PLL_CNTL4)
#define HHI_AUDCLK_PLL_CNTL5 0x10b4 	///../ucode/register.h:1723
#define P_HHI_AUDCLK_PLL_CNTL5 		CBUS_REG_ADDR(HHI_AUDCLK_PLL_CNTL5)
#define HHI_AUDCLK_PLL_CNTL6 0x10b5 	///../ucode/register.h:1724
#define P_HHI_AUDCLK_PLL_CNTL6 		CBUS_REG_ADDR(HHI_AUDCLK_PLL_CNTL6)
#define HHI_L2_DDR_CLK_CNTL 0x10b6 	///../ucode/register.h:1725
#define P_HHI_L2_DDR_CLK_CNTL 		CBUS_REG_ADDR(HHI_L2_DDR_CLK_CNTL)
#define HHI_VDAC_CNTL0 0x10bd 	///../ucode/register.h:1726
#define P_HHI_VDAC_CNTL0 		CBUS_REG_ADDR(HHI_VDAC_CNTL0)
#define HHI_VDAC_CNTL1 0x10be 	///../ucode/register.h:1727
#define P_HHI_VDAC_CNTL1 		CBUS_REG_ADDR(HHI_VDAC_CNTL1)
#define HHI_SYS_PLL_CNTL 0x10c0 	///../ucode/register.h:1728
#define P_HHI_SYS_PLL_CNTL 		CBUS_REG_ADDR(HHI_SYS_PLL_CNTL)
#define HHI_SYS_PLL_CNTL2 0x10c1 	///../ucode/register.h:1729
#define P_HHI_SYS_PLL_CNTL2 		CBUS_REG_ADDR(HHI_SYS_PLL_CNTL2)
#define HHI_SYS_PLL_CNTL3 0x10c2 	///../ucode/register.h:1730
#define P_HHI_SYS_PLL_CNTL3 		CBUS_REG_ADDR(HHI_SYS_PLL_CNTL3)
#define HHI_SYS_PLL_CNTL4 0x10c3 	///../ucode/register.h:1731
#define P_HHI_SYS_PLL_CNTL4 		CBUS_REG_ADDR(HHI_SYS_PLL_CNTL4)
#define HHI_SYS_PLL_CNTL5 0x10c4 	///../ucode/register.h:1732
#define P_HHI_SYS_PLL_CNTL5 		CBUS_REG_ADDR(HHI_SYS_PLL_CNTL5)
#define HHI_DPLL_TOP_0 0x10c6 	///../ucode/register.h:1733
#define P_HHI_DPLL_TOP_0 		CBUS_REG_ADDR(HHI_DPLL_TOP_0)
#define HHI_DPLL_TOP_1 0x10c7 	///../ucode/register.h:1734
#define P_HHI_DPLL_TOP_1 		CBUS_REG_ADDR(HHI_DPLL_TOP_1)
#define HHI_VID_PLL_CNTL 0x10c8 	///../ucode/register.h:1735
#define P_HHI_VID_PLL_CNTL 		CBUS_REG_ADDR(HHI_VID_PLL_CNTL)
#define HHI_VID_PLL_CNTL2 0x10c9 	///../ucode/register.h:1736
#define P_HHI_VID_PLL_CNTL2 		CBUS_REG_ADDR(HHI_VID_PLL_CNTL2)
#define HHI_VID_PLL_CNTL3 0x10ca 	///../ucode/register.h:1737
#define P_HHI_VID_PLL_CNTL3 		CBUS_REG_ADDR(HHI_VID_PLL_CNTL3)
#define HHI_VID_PLL_CNTL4 0x10cb 	///../ucode/register.h:1738
#define P_HHI_VID_PLL_CNTL4 		CBUS_REG_ADDR(HHI_VID_PLL_CNTL4)
#define HHI_VID_PLL_CNTL5 0x10cc 	///../ucode/register.h:1739
#define P_HHI_VID_PLL_CNTL5 		CBUS_REG_ADDR(HHI_VID_PLL_CNTL5)
#define HHI_VID_PLL_CNTL6 0x10cd 	///../ucode/register.h:1740
#define P_HHI_VID_PLL_CNTL6 		CBUS_REG_ADDR(HHI_VID_PLL_CNTL6)
#define HHI_DSI_LVDS_EDP_CNTL0 0x10d1 	///../ucode/register.h:1741
#define P_HHI_DSI_LVDS_EDP_CNTL0 		CBUS_REG_ADDR(HHI_DSI_LVDS_EDP_CNTL0)
#define HHI_DSI_LVDS_EDP_CNTL1 0x10d2 	///../ucode/register.h:1742
#define P_HHI_DSI_LVDS_EDP_CNTL1 		CBUS_REG_ADDR(HHI_DSI_LVDS_EDP_CNTL1)
#define HHI_CSI_PHY_CNTL0 0x10d3 	///../ucode/register.h:1743
#define P_HHI_CSI_PHY_CNTL0 		CBUS_REG_ADDR(HHI_CSI_PHY_CNTL0)
#define HHI_CSI_PHY_CNTL1 0x10d4 	///../ucode/register.h:1744
#define P_HHI_CSI_PHY_CNTL1 		CBUS_REG_ADDR(HHI_CSI_PHY_CNTL1)
#define HHI_CSI_PHY_CNTL2 0x10d5 	///../ucode/register.h:1745
#define P_HHI_CSI_PHY_CNTL2 		CBUS_REG_ADDR(HHI_CSI_PHY_CNTL2)
#define HHI_CSI_PHY_CNTL3 0x10d6 	///../ucode/register.h:1746
#define P_HHI_CSI_PHY_CNTL3 		CBUS_REG_ADDR(HHI_CSI_PHY_CNTL3)
#define HHI_CSI_PHY_CNTL4 0x10d7 	///../ucode/register.h:1747
#define P_HHI_CSI_PHY_CNTL4 		CBUS_REG_ADDR(HHI_CSI_PHY_CNTL4)
#define HHI_DIF_CSI_PHY_CNTL0 0x10d8 	///../ucode/register.h:1748
#define P_HHI_DIF_CSI_PHY_CNTL0 		CBUS_REG_ADDR(HHI_DIF_CSI_PHY_CNTL0)
#define HHI_DIF_CSI_PHY_CNTL1 0x10d9 	///../ucode/register.h:1749
#define P_HHI_DIF_CSI_PHY_CNTL1 		CBUS_REG_ADDR(HHI_DIF_CSI_PHY_CNTL1)
#define HHI_DIF_CSI_PHY_CNTL2 0x10da 	///../ucode/register.h:1750
#define P_HHI_DIF_CSI_PHY_CNTL2 		CBUS_REG_ADDR(HHI_DIF_CSI_PHY_CNTL2)
#define HHI_DIF_CSI_PHY_CNTL3 0x10db 	///../ucode/register.h:1751
#define P_HHI_DIF_CSI_PHY_CNTL3 		CBUS_REG_ADDR(HHI_DIF_CSI_PHY_CNTL3)
#define HHI_DIF_CSI_PHY_CNTL4 0x10dc 	///../ucode/register.h:1752
#define P_HHI_DIF_CSI_PHY_CNTL4 		CBUS_REG_ADDR(HHI_DIF_CSI_PHY_CNTL4)
#define HHI_DIF_CSI_PHY_CNTL5 0x10dd 	///../ucode/register.h:1753
#define P_HHI_DIF_CSI_PHY_CNTL5 		CBUS_REG_ADDR(HHI_DIF_CSI_PHY_CNTL5)
#define HHI_LVDS_TX_PHY_CNTL0 0x10de 	///../ucode/register.h:1754
#define P_HHI_LVDS_TX_PHY_CNTL0 		CBUS_REG_ADDR(HHI_LVDS_TX_PHY_CNTL0)
#define HHI_LVDS_TX_PHY_CNTL1 0x10df 	///../ucode/register.h:1755
#define P_HHI_LVDS_TX_PHY_CNTL1 		CBUS_REG_ADDR(HHI_LVDS_TX_PHY_CNTL1)
#define HHI_VID2_PLL_CNTL 0x10e0 	///../ucode/register.h:1756
#define P_HHI_VID2_PLL_CNTL 		CBUS_REG_ADDR(HHI_VID2_PLL_CNTL)
#define HHI_VID2_PLL_CNTL2 0x10e1 	///../ucode/register.h:1757
#define P_HHI_VID2_PLL_CNTL2 		CBUS_REG_ADDR(HHI_VID2_PLL_CNTL2)
#define HHI_VID2_PLL_CNTL3 0x10e2 	///../ucode/register.h:1758
#define P_HHI_VID2_PLL_CNTL3 		CBUS_REG_ADDR(HHI_VID2_PLL_CNTL3)
#define HHI_VID2_PLL_CNTL4 0x10e3 	///../ucode/register.h:1759
#define P_HHI_VID2_PLL_CNTL4 		CBUS_REG_ADDR(HHI_VID2_PLL_CNTL4)
#define HHI_VID2_PLL_CNTL5 0x10e4 	///../ucode/register.h:1760
#define P_HHI_VID2_PLL_CNTL5 		CBUS_REG_ADDR(HHI_VID2_PLL_CNTL5)
#define HHI_VID2_PLL_CNTL6 0x10e5 	///../ucode/register.h:1761
#define P_HHI_VID2_PLL_CNTL6 		CBUS_REG_ADDR(HHI_VID2_PLL_CNTL6)
#define HHI_HDMI_PHY_CNTL0 0x10e8 	///../ucode/register.h:1762
#define P_HHI_HDMI_PHY_CNTL0 		CBUS_REG_ADDR(HHI_HDMI_PHY_CNTL0)
#define HHI_HDMI_PHY_CNTL1 0x10e9 	///../ucode/register.h:1763
#define P_HHI_HDMI_PHY_CNTL1 		CBUS_REG_ADDR(HHI_HDMI_PHY_CNTL1)
#define HHI_HDMI_PHY_CNTL2 0x10ea 	///../ucode/register.h:1764
#define P_HHI_HDMI_PHY_CNTL2 		CBUS_REG_ADDR(HHI_HDMI_PHY_CNTL2)
#define PARSER_CONTROL 0x2960 	///../ucode/register.h:1779
#define P_PARSER_CONTROL 		CBUS_REG_ADDR(PARSER_CONTROL)
#define PARSER_FETCH_ADDR 0x2961 	///../ucode/register.h:1784
#define P_PARSER_FETCH_ADDR 		CBUS_REG_ADDR(PARSER_FETCH_ADDR)
#define PARSER_FETCH_CMD 0x2962 	///../ucode/register.h:1798
#define P_PARSER_FETCH_CMD 		CBUS_REG_ADDR(PARSER_FETCH_CMD)
#define PARSER_FETCH_STOP_ADDR 0x2963 	///../ucode/register.h:1800
#define P_PARSER_FETCH_STOP_ADDR 		CBUS_REG_ADDR(PARSER_FETCH_STOP_ADDR)
#define PARSER_FETCH_LEVEL 0x2964 	///../ucode/register.h:1802
#define P_PARSER_FETCH_LEVEL 		CBUS_REG_ADDR(PARSER_FETCH_LEVEL)
#define PARSER_CONFIG 0x2965 	///../ucode/register.h:1815
#define P_PARSER_CONFIG 		CBUS_REG_ADDR(PARSER_CONFIG)
#define PFIFO_WR_PTR 0x2966 	///../ucode/register.h:1818
#define P_PFIFO_WR_PTR 		CBUS_REG_ADDR(PFIFO_WR_PTR)
#define PFIFO_RD_PTR 0x2967 	///../ucode/register.h:1820
#define P_PFIFO_RD_PTR 		CBUS_REG_ADDR(PFIFO_RD_PTR)
#define PFIFO_DATA 0x2968 	///../ucode/register.h:1822
#define P_PFIFO_DATA 		CBUS_REG_ADDR(PFIFO_DATA)
#define PARSER_SEARCH_PATTERN 0x2969 	///../ucode/register.h:1824
#define P_PARSER_SEARCH_PATTERN 		CBUS_REG_ADDR(PARSER_SEARCH_PATTERN)
#define PARSER_SEARCH_MASK 0x296a 	///../ucode/register.h:1826
#define P_PARSER_SEARCH_MASK 		CBUS_REG_ADDR(PARSER_SEARCH_MASK)
#define PARSER_INT_ENABLE 0x296b 	///../ucode/register.h:1830
#define P_PARSER_INT_ENABLE 		CBUS_REG_ADDR(PARSER_INT_ENABLE)
#define PARSER_INT_STATUS 0x296c 	///../ucode/register.h:1840
#define P_PARSER_INT_STATUS 		CBUS_REG_ADDR(PARSER_INT_STATUS)
#define PARSER_SCR_CTL 0x296d 	///../ucode/register.h:1846
#define P_PARSER_SCR_CTL 		CBUS_REG_ADDR(PARSER_SCR_CTL)
#define PARSER_SCR 0x296e 	///../ucode/register.h:1848
#define P_PARSER_SCR 		CBUS_REG_ADDR(PARSER_SCR)
#define PARSER_PARAMETER 0x296f 	///../ucode/register.h:1853
#define P_PARSER_PARAMETER 		CBUS_REG_ADDR(PARSER_PARAMETER)
#define PARSER_INSERT_DATA 0x2970 	///../ucode/register.h:1857
#define P_PARSER_INSERT_DATA 		CBUS_REG_ADDR(PARSER_INSERT_DATA)
#define VAS_STREAM_ID 0x2971 	///../ucode/register.h:1862
#define P_VAS_STREAM_ID 		CBUS_REG_ADDR(VAS_STREAM_ID)
#define VIDEO_DTS 0x2972 	///../ucode/register.h:1864
#define P_VIDEO_DTS 		CBUS_REG_ADDR(VIDEO_DTS)
#define VIDEO_PTS 0x2973 	///../ucode/register.h:1866
#define P_VIDEO_PTS 		CBUS_REG_ADDR(VIDEO_PTS)
#define VIDEO_PTS_DTS_WR_PTR 0x2974 	///../ucode/register.h:1868
#define P_VIDEO_PTS_DTS_WR_PTR 		CBUS_REG_ADDR(VIDEO_PTS_DTS_WR_PTR)
#define AUDIO_PTS 0x2975 	///../ucode/register.h:1870
#define P_AUDIO_PTS 		CBUS_REG_ADDR(AUDIO_PTS)
#define AUDIO_PTS_WR_PTR 0x2976 	///../ucode/register.h:1872
#define P_AUDIO_PTS_WR_PTR 		CBUS_REG_ADDR(AUDIO_PTS_WR_PTR)
#define PARSER_ES_CONTROL 0x2977 	///../ucode/register.h:1885
#define P_PARSER_ES_CONTROL 		CBUS_REG_ADDR(PARSER_ES_CONTROL)
#define PFIFO_MONITOR 0x2978 	///../ucode/register.h:1887
#define P_PFIFO_MONITOR 		CBUS_REG_ADDR(PFIFO_MONITOR)
#define PARSER_VIDEO_START_PTR 0x2980 	///../ucode/register.h:1894
#define P_PARSER_VIDEO_START_PTR 		CBUS_REG_ADDR(PARSER_VIDEO_START_PTR)
#define PARSER_VIDEO_END_PTR 0x2981 	///../ucode/register.h:1895
#define P_PARSER_VIDEO_END_PTR 		CBUS_REG_ADDR(PARSER_VIDEO_END_PTR)
#define PARSER_VIDEO_WP 0x2982 	///../ucode/register.h:1899
#define P_PARSER_VIDEO_WP 		CBUS_REG_ADDR(PARSER_VIDEO_WP)
#define PARSER_VIDEO_RP 0x2983 	///../ucode/register.h:1900
#define P_PARSER_VIDEO_RP 		CBUS_REG_ADDR(PARSER_VIDEO_RP)
#define PARSER_VIDEO_HOLE 0x2984 	///../ucode/register.h:1901
#define P_PARSER_VIDEO_HOLE 		CBUS_REG_ADDR(PARSER_VIDEO_HOLE)
#define PARSER_AUDIO_START_PTR 0x2985 	///../ucode/register.h:1908
#define P_PARSER_AUDIO_START_PTR 		CBUS_REG_ADDR(PARSER_AUDIO_START_PTR)
#define PARSER_AUDIO_END_PTR 0x2986 	///../ucode/register.h:1909
#define P_PARSER_AUDIO_END_PTR 		CBUS_REG_ADDR(PARSER_AUDIO_END_PTR)
#define PARSER_AUDIO_WP 0x2987 	///../ucode/register.h:1913
#define P_PARSER_AUDIO_WP 		CBUS_REG_ADDR(PARSER_AUDIO_WP)
#define PARSER_AUDIO_RP 0x2988 	///../ucode/register.h:1914
#define P_PARSER_AUDIO_RP 		CBUS_REG_ADDR(PARSER_AUDIO_RP)
#define PARSER_AUDIO_HOLE 0x2989 	///../ucode/register.h:1915
#define P_PARSER_AUDIO_HOLE 		CBUS_REG_ADDR(PARSER_AUDIO_HOLE)
#define PARSER_SUB_START_PTR 0x298a 	///../ucode/register.h:1922
#define P_PARSER_SUB_START_PTR 		CBUS_REG_ADDR(PARSER_SUB_START_PTR)
#define PARSER_SUB_END_PTR 0x298b 	///../ucode/register.h:1923
#define P_PARSER_SUB_END_PTR 		CBUS_REG_ADDR(PARSER_SUB_END_PTR)
#define PARSER_SUB_WP 0x298c 	///../ucode/register.h:1927
#define P_PARSER_SUB_WP 		CBUS_REG_ADDR(PARSER_SUB_WP)
#define PARSER_SUB_RP 0x298d 	///../ucode/register.h:1928
#define P_PARSER_SUB_RP 		CBUS_REG_ADDR(PARSER_SUB_RP)
#define PARSER_SUB_HOLE 0x298e 	///../ucode/register.h:1929
#define P_PARSER_SUB_HOLE 		CBUS_REG_ADDR(PARSER_SUB_HOLE)
#define PARSER_FETCH_INFO 0x298f 	///../ucode/register.h:1935
#define P_PARSER_FETCH_INFO 		CBUS_REG_ADDR(PARSER_FETCH_INFO)
#define PARSER_STATUS 0x2990 	///../ucode/register.h:1939
#define P_PARSER_STATUS 		CBUS_REG_ADDR(PARSER_STATUS)
#define PARSER_AV_WRAP_COUNT 0x2991 	///../ucode/register.h:1942
#define P_PARSER_AV_WRAP_COUNT 		CBUS_REG_ADDR(PARSER_AV_WRAP_COUNT)
#define WRRSP_PARSER 0x2992 	///../ucode/register.h:1946
#define P_WRRSP_PARSER 		CBUS_REG_ADDR(WRRSP_PARSER)
#define PARSER_VIDEO2_START_PTR 0x2993 	///../ucode/register.h:1966
#define P_PARSER_VIDEO2_START_PTR 		CBUS_REG_ADDR(PARSER_VIDEO2_START_PTR)
#define PARSER_VIDEO2_END_PTR 0x2994 	///../ucode/register.h:1967
#define P_PARSER_VIDEO2_END_PTR 		CBUS_REG_ADDR(PARSER_VIDEO2_END_PTR)
#define PARSER_VIDEO2_WP 0x2995 	///../ucode/register.h:1971
#define P_PARSER_VIDEO2_WP 		CBUS_REG_ADDR(PARSER_VIDEO2_WP)
#define PARSER_VIDEO2_RP 0x2996 	///../ucode/register.h:1972
#define P_PARSER_VIDEO2_RP 		CBUS_REG_ADDR(PARSER_VIDEO2_RP)
#define PARSER_VIDEO2_HOLE 0x2997 	///../ucode/register.h:1973
#define P_PARSER_VIDEO2_HOLE 		CBUS_REG_ADDR(PARSER_VIDEO2_HOLE)
#define PARSER_AV2_WRAP_COUNT 0x2998 	///../ucode/register.h:1976
#define P_PARSER_AV2_WRAP_COUNT 		CBUS_REG_ADDR(PARSER_AV2_WRAP_COUNT)
#define DVIN_FRONT_END_CTRL 0x12e0 	///../ucode/register.h:2002
#define P_DVIN_FRONT_END_CTRL 		CBUS_REG_ADDR(DVIN_FRONT_END_CTRL)
#define DVIN_HS_LEAD_VS_ODD 0x12e1 	///../ucode/register.h:2009
#define P_DVIN_HS_LEAD_VS_ODD 		CBUS_REG_ADDR(DVIN_HS_LEAD_VS_ODD)
#define DVIN_ACTIVE_START_PIX 0x12e2 	///../ucode/register.h:2014
#define P_DVIN_ACTIVE_START_PIX 		CBUS_REG_ADDR(DVIN_ACTIVE_START_PIX)
#define DVIN_ACTIVE_START_LINE 0x12e3 	///../ucode/register.h:2019
#define P_DVIN_ACTIVE_START_LINE 		CBUS_REG_ADDR(DVIN_ACTIVE_START_LINE)
#define DVIN_DISPLAY_SIZE 0x12e4 	///../ucode/register.h:2024
#define P_DVIN_DISPLAY_SIZE 		CBUS_REG_ADDR(DVIN_DISPLAY_SIZE)
#define DVIN_CTRL_STAT 0x12e5 	///../ucode/register.h:2040
#define P_DVIN_CTRL_STAT 		CBUS_REG_ADDR(DVIN_CTRL_STAT)
#define AIU_958_BPF 0x1500 	///../ucode/register.h:2078
#define P_AIU_958_BPF 		CBUS_REG_ADDR(AIU_958_BPF)
#define AIU_958_BRST 0x1501 	///../ucode/register.h:2081
#define P_AIU_958_BRST 		CBUS_REG_ADDR(AIU_958_BRST)
#define AIU_958_LENGTH 0x1502 	///../ucode/register.h:2084
#define P_AIU_958_LENGTH 		CBUS_REG_ADDR(AIU_958_LENGTH)
#define AIU_958_PADDSIZE 0x1503 	///../ucode/register.h:2088
#define P_AIU_958_PADDSIZE 		CBUS_REG_ADDR(AIU_958_PADDSIZE)
#define AIU_958_MISC 0x1504 	///../ucode/register.h:2110
#define P_AIU_958_MISC 		CBUS_REG_ADDR(AIU_958_MISC)
#define AIU_958_FORCE_LEFT 0x1505 	///../ucode/register.h:2114
#define P_AIU_958_FORCE_LEFT 		CBUS_REG_ADDR(AIU_958_FORCE_LEFT)
#define AIU_958_DISCARD_NUM 0x1506 	///../ucode/register.h:2118
#define P_AIU_958_DISCARD_NUM 		CBUS_REG_ADDR(AIU_958_DISCARD_NUM)
#define AIU_958_DCU_FF_CTRL 0x1507 	///../ucode/register.h:2135
#define P_AIU_958_DCU_FF_CTRL 		CBUS_REG_ADDR(AIU_958_DCU_FF_CTRL)
#define AIU_958_CHSTAT_L0 0x1508 	///../ucode/register.h:2141
#define P_AIU_958_CHSTAT_L0 		CBUS_REG_ADDR(AIU_958_CHSTAT_L0)
#define AIU_958_CHSTAT_L1 0x1509 	///../ucode/register.h:2142
#define P_AIU_958_CHSTAT_L1 		CBUS_REG_ADDR(AIU_958_CHSTAT_L1)
#define AIU_958_CTRL 0x150a 	///../ucode/register.h:2165
#define P_AIU_958_CTRL 		CBUS_REG_ADDR(AIU_958_CTRL)
#define AIU_958_RPT 0x150b 	///../ucode/register.h:2170
#define P_AIU_958_RPT 		CBUS_REG_ADDR(AIU_958_RPT)
#define AIU_I2S_MUTE_SWAP 0x150c 	///../ucode/register.h:2189
#define P_AIU_I2S_MUTE_SWAP 		CBUS_REG_ADDR(AIU_I2S_MUTE_SWAP)
#define AIU_I2S_SOURCE_DESC 0x150d 	///../ucode/register.h:2193
#define P_AIU_I2S_SOURCE_DESC 		CBUS_REG_ADDR(AIU_I2S_SOURCE_DESC)
#define AIU_I2S_MED_CTRL 0x150e 	///../ucode/register.h:2198
#define P_AIU_I2S_MED_CTRL 		CBUS_REG_ADDR(AIU_I2S_MED_CTRL)
#define AIU_I2S_MED_THRESH 0x150f 	///../ucode/register.h:2202
#define P_AIU_I2S_MED_THRESH 		CBUS_REG_ADDR(AIU_I2S_MED_THRESH)
#define AIU_I2S_DAC_CFG 0x1510 	///../ucode/register.h:2220
#define P_AIU_I2S_DAC_CFG 		CBUS_REG_ADDR(AIU_I2S_DAC_CFG)
#define AIU_I2S_SYNC 0x1511 	///../ucode/register.h:2226
#define P_AIU_I2S_SYNC 		CBUS_REG_ADDR(AIU_I2S_SYNC)
#define AIU_I2S_MISC 0x1512 	///../ucode/register.h:2236
#define P_AIU_I2S_MISC 		CBUS_REG_ADDR(AIU_I2S_MISC)
#define AIU_I2S_OUT_CFG 0x1513 	///../ucode/register.h:2245
#define P_AIU_I2S_OUT_CFG 		CBUS_REG_ADDR(AIU_I2S_OUT_CFG)
#define AIU_I2S_FF_CTRL 0x1514 	///../ucode/register.h:2247
#define P_AIU_I2S_FF_CTRL 		CBUS_REG_ADDR(AIU_I2S_FF_CTRL)
#define AIU_RST_SOFT 0x1515 	///../ucode/register.h:2253
#define P_AIU_RST_SOFT 		CBUS_REG_ADDR(AIU_RST_SOFT)
#define AIU_CLK_CTRL 0x1516 	///../ucode/register.h:2282
#define P_AIU_CLK_CTRL 		CBUS_REG_ADDR(AIU_CLK_CTRL)
#define AIU_MIX_ADCCFG 0x1517 	///../ucode/register.h:2304
#define P_AIU_MIX_ADCCFG 		CBUS_REG_ADDR(AIU_MIX_ADCCFG)
#define AIU_MIX_CTRL 0x1518 	///../ucode/register.h:2332
#define P_AIU_MIX_CTRL 		CBUS_REG_ADDR(AIU_MIX_CTRL)
#define AIU_CLK_CTRL_MORE 0x1519 	///../ucode/register.h:2347
#define P_AIU_CLK_CTRL_MORE 		CBUS_REG_ADDR(AIU_CLK_CTRL_MORE)
#define AIU_958_POP 0x151a 	///../ucode/register.h:2350
#define P_AIU_958_POP 		CBUS_REG_ADDR(AIU_958_POP)
#define AIU_MIX_GAIN 0x151b 	///../ucode/register.h:2374
#define P_AIU_MIX_GAIN 		CBUS_REG_ADDR(AIU_MIX_GAIN)
#define AIU_958_SYNWORD1 0x151c 	///../ucode/register.h:2382
#define P_AIU_958_SYNWORD1 		CBUS_REG_ADDR(AIU_958_SYNWORD1)
#define AIU_958_SYNWORD2 0x151d 	///../ucode/register.h:2384
#define P_AIU_958_SYNWORD2 		CBUS_REG_ADDR(AIU_958_SYNWORD2)
#define AIU_958_SYNWORD3 0x151e 	///../ucode/register.h:2386
#define P_AIU_958_SYNWORD3 		CBUS_REG_ADDR(AIU_958_SYNWORD3)
#define AIU_958_SYNWORD1_MASK 0x151f 	///../ucode/register.h:2388
#define P_AIU_958_SYNWORD1_MASK 		CBUS_REG_ADDR(AIU_958_SYNWORD1_MASK)
#define AIU_958_SYNWORD2_MASK 0x1520 	///../ucode/register.h:2390
#define P_AIU_958_SYNWORD2_MASK 		CBUS_REG_ADDR(AIU_958_SYNWORD2_MASK)
#define AIU_958_SYNWORD3_MASK 0x1521 	///../ucode/register.h:2392
#define P_AIU_958_SYNWORD3_MASK 		CBUS_REG_ADDR(AIU_958_SYNWORD3_MASK)
#define AIU_958_FFRDOUT_THD 0x1522 	///../ucode/register.h:2396
#define P_AIU_958_FFRDOUT_THD 		CBUS_REG_ADDR(AIU_958_FFRDOUT_THD)
#define AIU_958_LENGTH_PER_PAUSE 0x1523 	///../ucode/register.h:2402
#define P_AIU_958_LENGTH_PER_PAUSE 		CBUS_REG_ADDR(AIU_958_LENGTH_PER_PAUSE)
#define AIU_958_PAUSE_NUM 0x1524 	///../ucode/register.h:2407
#define P_AIU_958_PAUSE_NUM 		CBUS_REG_ADDR(AIU_958_PAUSE_NUM)
#define AIU_958_PAUSE_PAYLOAD 0x1525 	///../ucode/register.h:2410
#define P_AIU_958_PAUSE_PAYLOAD 		CBUS_REG_ADDR(AIU_958_PAUSE_PAYLOAD)
#define AIU_958_AUTO_PAUSE 0x1526 	///../ucode/register.h:2417
#define P_AIU_958_AUTO_PAUSE 		CBUS_REG_ADDR(AIU_958_AUTO_PAUSE)
#define AIU_958_PAUSE_PD_LENGTH 0x1527 	///../ucode/register.h:2420
#define P_AIU_958_PAUSE_PD_LENGTH 		CBUS_REG_ADDR(AIU_958_PAUSE_PD_LENGTH)
#define AIU_CODEC_DAC_LRCLK_CTRL 0x1528 	///../ucode/register.h:2424
#define P_AIU_CODEC_DAC_LRCLK_CTRL 		CBUS_REG_ADDR(AIU_CODEC_DAC_LRCLK_CTRL)
#define AIU_CODEC_ADC_LRCLK_CTRL 0x1529 	///../ucode/register.h:2430
#define P_AIU_CODEC_ADC_LRCLK_CTRL 		CBUS_REG_ADDR(AIU_CODEC_ADC_LRCLK_CTRL)
#define AIU_HDMI_CLK_DATA_CTRL 0x152a 	///../ucode/register.h:2436
#define P_AIU_HDMI_CLK_DATA_CTRL 		CBUS_REG_ADDR(AIU_HDMI_CLK_DATA_CTRL)
#define AIU_CODEC_CLK_DATA_CTRL 0x152b 	///../ucode/register.h:2442
#define P_AIU_CODEC_CLK_DATA_CTRL 		CBUS_REG_ADDR(AIU_CODEC_CLK_DATA_CTRL)
#define AIU_958_CHSTAT_R0 0x1530 	///../ucode/register.h:2448
#define P_AIU_958_CHSTAT_R0 		CBUS_REG_ADDR(AIU_958_CHSTAT_R0)
#define AIU_958_CHSTAT_R1 0x1531 	///../ucode/register.h:2449
#define P_AIU_958_CHSTAT_R1 		CBUS_REG_ADDR(AIU_958_CHSTAT_R1)
#define AIU_958_VALID_CTRL 0x1532 	///../ucode/register.h:2452
#define P_AIU_958_VALID_CTRL 		CBUS_REG_ADDR(AIU_958_VALID_CTRL)
#define AIU_AUDIO_AMP_REG0 0x153c 	///../ucode/register.h:2456
#define P_AIU_AUDIO_AMP_REG0 		CBUS_REG_ADDR(AIU_AUDIO_AMP_REG0)
#define AIU_AUDIO_AMP_REG1 0x153d 	///../ucode/register.h:2457
#define P_AIU_AUDIO_AMP_REG1 		CBUS_REG_ADDR(AIU_AUDIO_AMP_REG1)
#define AIU_AUDIO_AMP_REG2 0x153e 	///../ucode/register.h:2458
#define P_AIU_AUDIO_AMP_REG2 		CBUS_REG_ADDR(AIU_AUDIO_AMP_REG2)
#define AIU_AUDIO_AMP_REG3 0x153f 	///../ucode/register.h:2459
#define P_AIU_AUDIO_AMP_REG3 		CBUS_REG_ADDR(AIU_AUDIO_AMP_REG3)
#define AIU_AIFIFO2_CTRL 0x1540 	///../ucode/register.h:2467
#define P_AIU_AIFIFO2_CTRL 		CBUS_REG_ADDR(AIU_AIFIFO2_CTRL)
#define AIU_AIFIFO2_STATUS 0x1541 	///../ucode/register.h:2471
#define P_AIU_AIFIFO2_STATUS 		CBUS_REG_ADDR(AIU_AIFIFO2_STATUS)
#define AIU_AIFIFO2_GBIT 0x1542 	///../ucode/register.h:2475
#define P_AIU_AIFIFO2_GBIT 		CBUS_REG_ADDR(AIU_AIFIFO2_GBIT)
#define AIU_AIFIFO2_CLB 0x1543 	///../ucode/register.h:2478
#define P_AIU_AIFIFO2_CLB 		CBUS_REG_ADDR(AIU_AIFIFO2_CLB)
#define AIU_CRC_CTRL 0x1544 	///../ucode/register.h:2485
#define P_AIU_CRC_CTRL 		CBUS_REG_ADDR(AIU_CRC_CTRL)
#define AIU_CRC_STATUS 0x1545 	///../ucode/register.h:2493
#define P_AIU_CRC_STATUS 		CBUS_REG_ADDR(AIU_CRC_STATUS)
#define AIU_CRC_SHIFT_REG 0x1546 	///../ucode/register.h:2495
#define P_AIU_CRC_SHIFT_REG 		CBUS_REG_ADDR(AIU_CRC_SHIFT_REG)
#define AIU_CRC_IREG 0x1547 	///../ucode/register.h:2497
#define P_AIU_CRC_IREG 		CBUS_REG_ADDR(AIU_CRC_IREG)
#define AIU_CRC_CAL_REG1 0x1548 	///../ucode/register.h:2500
#define P_AIU_CRC_CAL_REG1 		CBUS_REG_ADDR(AIU_CRC_CAL_REG1)
#define AIU_CRC_CAL_REG0 0x1549 	///../ucode/register.h:2502
#define P_AIU_CRC_CAL_REG0 		CBUS_REG_ADDR(AIU_CRC_CAL_REG0)
#define AIU_CRC_POLY_COEF1 0x154a 	///../ucode/register.h:2505
#define P_AIU_CRC_POLY_COEF1 		CBUS_REG_ADDR(AIU_CRC_POLY_COEF1)
#define AIU_CRC_POLY_COEF0 0x154b 	///../ucode/register.h:2507
#define P_AIU_CRC_POLY_COEF0 		CBUS_REG_ADDR(AIU_CRC_POLY_COEF0)
#define AIU_CRC_BIT_SIZE1 0x154c 	///../ucode/register.h:2510
#define P_AIU_CRC_BIT_SIZE1 		CBUS_REG_ADDR(AIU_CRC_BIT_SIZE1)
#define AIU_CRC_BIT_SIZE0 0x154d 	///../ucode/register.h:2512
#define P_AIU_CRC_BIT_SIZE0 		CBUS_REG_ADDR(AIU_CRC_BIT_SIZE0)
#define AIU_CRC_BIT_CNT1 0x154e 	///../ucode/register.h:2516
#define P_AIU_CRC_BIT_CNT1 		CBUS_REG_ADDR(AIU_CRC_BIT_CNT1)
#define AIU_CRC_BIT_CNT0 0x154f 	///../ucode/register.h:2518
#define P_AIU_CRC_BIT_CNT0 		CBUS_REG_ADDR(AIU_CRC_BIT_CNT0)
#define AIU_AMCLK_GATE_HI 0x1550 	///../ucode/register.h:2523
#define P_AIU_AMCLK_GATE_HI 		CBUS_REG_ADDR(AIU_AMCLK_GATE_HI)
#define AIU_AMCLK_GATE_LO 0x1551 	///../ucode/register.h:2524
#define P_AIU_AMCLK_GATE_LO 		CBUS_REG_ADDR(AIU_AMCLK_GATE_LO)
#define AIU_AMCLK_MSR 0x1552 	///../ucode/register.h:2525
#define P_AIU_AMCLK_MSR 		CBUS_REG_ADDR(AIU_AMCLK_MSR)
#define AIU_AUDAC_CTRL0 0x1553 	///../ucode/register.h:2526
#define P_AIU_AUDAC_CTRL0 		CBUS_REG_ADDR(AIU_AUDAC_CTRL0)
#define AIU_DELTA_SIGMA0 0x1555 	///../ucode/register.h:2549
#define P_AIU_DELTA_SIGMA0 		CBUS_REG_ADDR(AIU_DELTA_SIGMA0)
#define AIU_DELTA_SIGMA1 0x1556 	///../ucode/register.h:2551
#define P_AIU_DELTA_SIGMA1 		CBUS_REG_ADDR(AIU_DELTA_SIGMA1)
#define AIU_DELTA_SIGMA2 0x1557 	///../ucode/register.h:2553
#define P_AIU_DELTA_SIGMA2 		CBUS_REG_ADDR(AIU_DELTA_SIGMA2)
#define AIU_DELTA_SIGMA3 0x1558 	///../ucode/register.h:2564
#define P_AIU_DELTA_SIGMA3 		CBUS_REG_ADDR(AIU_DELTA_SIGMA3)
#define AIU_DELTA_SIGMA4 0x1559 	///../ucode/register.h:2568
#define P_AIU_DELTA_SIGMA4 		CBUS_REG_ADDR(AIU_DELTA_SIGMA4)
#define AIU_DELTA_SIGMA5 0x155a 	///../ucode/register.h:2572
#define P_AIU_DELTA_SIGMA5 		CBUS_REG_ADDR(AIU_DELTA_SIGMA5)
#define AIU_DELTA_SIGMA6 0x155b 	///../ucode/register.h:2577
#define P_AIU_DELTA_SIGMA6 		CBUS_REG_ADDR(AIU_DELTA_SIGMA6)
#define AIU_DELTA_SIGMA7 0x155c 	///../ucode/register.h:2581
#define P_AIU_DELTA_SIGMA7 		CBUS_REG_ADDR(AIU_DELTA_SIGMA7)
#define AIU_DELTA_SIGMA_LCNTS 0x155d 	///../ucode/register.h:2586
#define P_AIU_DELTA_SIGMA_LCNTS 		CBUS_REG_ADDR(AIU_DELTA_SIGMA_LCNTS)
#define AIU_DELTA_SIGMA_RCNTS 0x155e 	///../ucode/register.h:2591
#define P_AIU_DELTA_SIGMA_RCNTS 		CBUS_REG_ADDR(AIU_DELTA_SIGMA_RCNTS)
#define AIU_MEM_I2S_START_PTR 0x1560 	///../ucode/register.h:2596
#define P_AIU_MEM_I2S_START_PTR 		CBUS_REG_ADDR(AIU_MEM_I2S_START_PTR)
#define AIU_MEM_I2S_RD_PTR 0x1561 	///../ucode/register.h:2597
#define P_AIU_MEM_I2S_RD_PTR 		CBUS_REG_ADDR(AIU_MEM_I2S_RD_PTR)
#define AIU_MEM_I2S_END_PTR 0x1562 	///../ucode/register.h:2598
#define P_AIU_MEM_I2S_END_PTR 		CBUS_REG_ADDR(AIU_MEM_I2S_END_PTR)
#define AIU_MEM_I2S_MASKS 0x1563 	///../ucode/register.h:2603
#define P_AIU_MEM_I2S_MASKS 		CBUS_REG_ADDR(AIU_MEM_I2S_MASKS)
#define AIU_MEM_I2S_CONTROL 0x1564 	///../ucode/register.h:2621
#define P_AIU_MEM_I2S_CONTROL 		CBUS_REG_ADDR(AIU_MEM_I2S_CONTROL)
#define AIU_MEM_IEC958_START_PTR 0x1565 	///../ucode/register.h:2626
#define P_AIU_MEM_IEC958_START_PTR 		CBUS_REG_ADDR(AIU_MEM_IEC958_START_PTR)
#define AIU_MEM_IEC958_RD_PTR 0x1566 	///../ucode/register.h:2627
#define P_AIU_MEM_IEC958_RD_PTR 		CBUS_REG_ADDR(AIU_MEM_IEC958_RD_PTR)
#define AIU_MEM_IEC958_END_PTR 0x1567 	///../ucode/register.h:2628
#define P_AIU_MEM_IEC958_END_PTR 		CBUS_REG_ADDR(AIU_MEM_IEC958_END_PTR)
#define AIU_MEM_IEC958_MASKS 0x1568 	///../ucode/register.h:2632
#define P_AIU_MEM_IEC958_MASKS 		CBUS_REG_ADDR(AIU_MEM_IEC958_MASKS)
#define AIU_MEM_IEC958_CONTROL 0x1569 	///../ucode/register.h:2659
#define P_AIU_MEM_IEC958_CONTROL 		CBUS_REG_ADDR(AIU_MEM_IEC958_CONTROL)
#define AIU_MEM_AIFIFO2_START_PTR 0x156a 	///../ucode/register.h:2666
#define P_AIU_MEM_AIFIFO2_START_PTR 		CBUS_REG_ADDR(AIU_MEM_AIFIFO2_START_PTR)
#define AIU_MEM_AIFIFO2_CURR_PTR 0x156b 	///../ucode/register.h:2670
#define P_AIU_MEM_AIFIFO2_CURR_PTR 		CBUS_REG_ADDR(AIU_MEM_AIFIFO2_CURR_PTR)
#define AIU_MEM_AIFIFO2_END_PTR 0x156c 	///../ucode/register.h:2671
#define P_AIU_MEM_AIFIFO2_END_PTR 		CBUS_REG_ADDR(AIU_MEM_AIFIFO2_END_PTR)
#define AIU_MEM_AIFIFO2_BYTES_AVAIL 0x156d 	///../ucode/register.h:2672
#define P_AIU_MEM_AIFIFO2_BYTES_AVAIL 		CBUS_REG_ADDR(AIU_MEM_AIFIFO2_BYTES_AVAIL)
#define AIU_MEM_AIFIFO2_CONTROL 0x156e 	///../ucode/register.h:2692
#define P_AIU_MEM_AIFIFO2_CONTROL 		CBUS_REG_ADDR(AIU_MEM_AIFIFO2_CONTROL)
#define AIU_MEM_AIFIFO2_MAN_WP 0x156f 	///../ucode/register.h:2696
#define P_AIU_MEM_AIFIFO2_MAN_WP 		CBUS_REG_ADDR(AIU_MEM_AIFIFO2_MAN_WP)
#define AIU_MEM_AIFIFO2_MAN_RP 0x1570 	///../ucode/register.h:2697
#define P_AIU_MEM_AIFIFO2_MAN_RP 		CBUS_REG_ADDR(AIU_MEM_AIFIFO2_MAN_RP)
#define AIU_MEM_AIFIFO2_LEVEL 0x1571 	///../ucode/register.h:2698
#define P_AIU_MEM_AIFIFO2_LEVEL 		CBUS_REG_ADDR(AIU_MEM_AIFIFO2_LEVEL)
#define AIU_MEM_AIFIFO2_BUF_CNTL 0x1572 	///../ucode/register.h:2702
#define P_AIU_MEM_AIFIFO2_BUF_CNTL 		CBUS_REG_ADDR(AIU_MEM_AIFIFO2_BUF_CNTL)
#define AIU_MEM_I2S_MAN_WP 0x1573 	///../ucode/register.h:2706
#define P_AIU_MEM_I2S_MAN_WP 		CBUS_REG_ADDR(AIU_MEM_I2S_MAN_WP)
#define AIU_MEM_I2S_MAN_RP 0x1574 	///../ucode/register.h:2707
#define P_AIU_MEM_I2S_MAN_RP 		CBUS_REG_ADDR(AIU_MEM_I2S_MAN_RP)
#define AIU_MEM_I2S_LEVEL 0x1575 	///../ucode/register.h:2708
#define P_AIU_MEM_I2S_LEVEL 		CBUS_REG_ADDR(AIU_MEM_I2S_LEVEL)
#define AIU_MEM_I2S_BUF_CNTL 0x1576 	///../ucode/register.h:2713
#define P_AIU_MEM_I2S_BUF_CNTL 		CBUS_REG_ADDR(AIU_MEM_I2S_BUF_CNTL)
#define AIU_MEM_I2S_BUF_WRAP_COUNT 0x1577 	///../ucode/register.h:2714
#define P_AIU_MEM_I2S_BUF_WRAP_COUNT 		CBUS_REG_ADDR(AIU_MEM_I2S_BUF_WRAP_COUNT)
#define AIU_MEM_I2S_MEM_CTL 0x1578 	///../ucode/register.h:2718
#define P_AIU_MEM_I2S_MEM_CTL 		CBUS_REG_ADDR(AIU_MEM_I2S_MEM_CTL)
#define AIU_MEM_IEC958_MEM_CTL 0x1579 	///../ucode/register.h:2725
#define P_AIU_MEM_IEC958_MEM_CTL 		CBUS_REG_ADDR(AIU_MEM_IEC958_MEM_CTL)
#define AIU_MEM_IEC958_WRAP_COUNT 0x157a 	///../ucode/register.h:2726
#define P_AIU_MEM_IEC958_WRAP_COUNT 		CBUS_REG_ADDR(AIU_MEM_IEC958_WRAP_COUNT)
#define AIU_MEM_IEC958_IRQ_LEVEL 0x157b 	///../ucode/register.h:2727
#define P_AIU_MEM_IEC958_IRQ_LEVEL 		CBUS_REG_ADDR(AIU_MEM_IEC958_IRQ_LEVEL)
#define AIU_MEM_IEC958_MAN_WP 0x157c 	///../ucode/register.h:2728
#define P_AIU_MEM_IEC958_MAN_WP 		CBUS_REG_ADDR(AIU_MEM_IEC958_MAN_WP)
#define AIU_MEM_IEC958_MAN_RP 0x157d 	///../ucode/register.h:2729
#define P_AIU_MEM_IEC958_MAN_RP 		CBUS_REG_ADDR(AIU_MEM_IEC958_MAN_RP)
#define AIU_MEM_IEC958_LEVEL 0x157e 	///../ucode/register.h:2730
#define P_AIU_MEM_IEC958_LEVEL 		CBUS_REG_ADDR(AIU_MEM_IEC958_LEVEL)
#define AIU_MEM_IEC958_BUF_CNTL 0x157f 	///../ucode/register.h:2731
#define P_AIU_MEM_IEC958_BUF_CNTL 		CBUS_REG_ADDR(AIU_MEM_IEC958_BUF_CNTL)
#define AIU_AIFIFO_CTRL 0x1580 	///../ucode/register.h:2739
#define P_AIU_AIFIFO_CTRL 		CBUS_REG_ADDR(AIU_AIFIFO_CTRL)
#define AIU_AIFIFO_STATUS 0x1581 	///../ucode/register.h:2746
#define P_AIU_AIFIFO_STATUS 		CBUS_REG_ADDR(AIU_AIFIFO_STATUS)
#define AIU_AIFIFO_GBIT 0x1582 	///../ucode/register.h:2750
#define P_AIU_AIFIFO_GBIT 		CBUS_REG_ADDR(AIU_AIFIFO_GBIT)
#define AIU_AIFIFO_CLB 0x1583 	///../ucode/register.h:2753
#define P_AIU_AIFIFO_CLB 		CBUS_REG_ADDR(AIU_AIFIFO_CLB)
#define AIU_MEM_AIFIFO_START_PTR 0x1584 	///../ucode/register.h:2760
#define P_AIU_MEM_AIFIFO_START_PTR 		CBUS_REG_ADDR(AIU_MEM_AIFIFO_START_PTR)
#define AIU_MEM_AIFIFO_CURR_PTR 0x1585 	///../ucode/register.h:2764
#define P_AIU_MEM_AIFIFO_CURR_PTR 		CBUS_REG_ADDR(AIU_MEM_AIFIFO_CURR_PTR)
#define AIU_MEM_AIFIFO_END_PTR 0x1586 	///../ucode/register.h:2765
#define P_AIU_MEM_AIFIFO_END_PTR 		CBUS_REG_ADDR(AIU_MEM_AIFIFO_END_PTR)
#define AIU_MEM_AIFIFO_BYTES_AVAIL 0x1587 	///../ucode/register.h:2766
#define P_AIU_MEM_AIFIFO_BYTES_AVAIL 		CBUS_REG_ADDR(AIU_MEM_AIFIFO_BYTES_AVAIL)
#define AIU_MEM_AIFIFO_CONTROL 0x1588 	///../ucode/register.h:2786
#define P_AIU_MEM_AIFIFO_CONTROL 		CBUS_REG_ADDR(AIU_MEM_AIFIFO_CONTROL)
#define AIU_MEM_AIFIFO_MAN_WP 0x1589 	///../ucode/register.h:2790
#define P_AIU_MEM_AIFIFO_MAN_WP 		CBUS_REG_ADDR(AIU_MEM_AIFIFO_MAN_WP)
#define AIU_MEM_AIFIFO_MAN_RP 0x158a 	///../ucode/register.h:2791
#define P_AIU_MEM_AIFIFO_MAN_RP 		CBUS_REG_ADDR(AIU_MEM_AIFIFO_MAN_RP)
#define AIU_MEM_AIFIFO_LEVEL 0x158b 	///../ucode/register.h:2792
#define P_AIU_MEM_AIFIFO_LEVEL 		CBUS_REG_ADDR(AIU_MEM_AIFIFO_LEVEL)
#define AIU_MEM_AIFIFO_BUF_CNTL 0x158c 	///../ucode/register.h:2796
#define P_AIU_MEM_AIFIFO_BUF_CNTL 		CBUS_REG_ADDR(AIU_MEM_AIFIFO_BUF_CNTL)
#define AIU_MEM_AIFIFO_BUF_WRAP_COUNT 0x158d 	///../ucode/register.h:2797
#define P_AIU_MEM_AIFIFO_BUF_WRAP_COUNT 		CBUS_REG_ADDR(AIU_MEM_AIFIFO_BUF_WRAP_COUNT)
#define AIU_MEM_AIFIFO2_BUF_WRAP_COUNT 0x158e 	///../ucode/register.h:2798
#define P_AIU_MEM_AIFIFO2_BUF_WRAP_COUNT 		CBUS_REG_ADDR(AIU_MEM_AIFIFO2_BUF_WRAP_COUNT)
#define AIU_MEM_AIFIFO_MEM_CTL 0x158f 	///../ucode/register.h:2802
#define P_AIU_MEM_AIFIFO_MEM_CTL 		CBUS_REG_ADDR(AIU_MEM_AIFIFO_MEM_CTL)
#define AIFIFO_TIME_STAMP_CNTL 0x1590 	///../ucode/register.h:2812
#define P_AIFIFO_TIME_STAMP_CNTL 		CBUS_REG_ADDR(AIFIFO_TIME_STAMP_CNTL)
#define AIFIFO_TIME_STAMP_SYNC_0 0x1591 	///../ucode/register.h:2814
#define P_AIFIFO_TIME_STAMP_SYNC_0 		CBUS_REG_ADDR(AIFIFO_TIME_STAMP_SYNC_0)
#define AIFIFO_TIME_STAMP_SYNC_1 0x1592 	///../ucode/register.h:2816
#define P_AIFIFO_TIME_STAMP_SYNC_1 		CBUS_REG_ADDR(AIFIFO_TIME_STAMP_SYNC_1)
#define AIFIFO_TIME_STAMP_0 0x1593 	///../ucode/register.h:2818
#define P_AIFIFO_TIME_STAMP_0 		CBUS_REG_ADDR(AIFIFO_TIME_STAMP_0)
#define AIFIFO_TIME_STAMP_1 0x1594 	///../ucode/register.h:2820
#define P_AIFIFO_TIME_STAMP_1 		CBUS_REG_ADDR(AIFIFO_TIME_STAMP_1)
#define AIFIFO_TIME_STAMP_2 0x1595 	///../ucode/register.h:2822
#define P_AIFIFO_TIME_STAMP_2 		CBUS_REG_ADDR(AIFIFO_TIME_STAMP_2)
#define AIFIFO_TIME_STAMP_3 0x1596 	///../ucode/register.h:2824
#define P_AIFIFO_TIME_STAMP_3 		CBUS_REG_ADDR(AIFIFO_TIME_STAMP_3)
#define AIFIFO_TIME_STAMP_LENGTH 0x1597 	///../ucode/register.h:2826
#define P_AIFIFO_TIME_STAMP_LENGTH 		CBUS_REG_ADDR(AIFIFO_TIME_STAMP_LENGTH)
#define AIFIFO2_TIME_STAMP_CNTL 0x1598 	///../ucode/register.h:2836
#define P_AIFIFO2_TIME_STAMP_CNTL 		CBUS_REG_ADDR(AIFIFO2_TIME_STAMP_CNTL)
#define AIFIFO2_TIME_STAMP_SYNC_0 0x1599 	///../ucode/register.h:2838
#define P_AIFIFO2_TIME_STAMP_SYNC_0 		CBUS_REG_ADDR(AIFIFO2_TIME_STAMP_SYNC_0)
#define AIFIFO2_TIME_STAMP_SYNC_1 0x159a 	///../ucode/register.h:2840
#define P_AIFIFO2_TIME_STAMP_SYNC_1 		CBUS_REG_ADDR(AIFIFO2_TIME_STAMP_SYNC_1)
#define AIFIFO2_TIME_STAMP_0 0x159b 	///../ucode/register.h:2842
#define P_AIFIFO2_TIME_STAMP_0 		CBUS_REG_ADDR(AIFIFO2_TIME_STAMP_0)
#define AIFIFO2_TIME_STAMP_1 0x159c 	///../ucode/register.h:2844
#define P_AIFIFO2_TIME_STAMP_1 		CBUS_REG_ADDR(AIFIFO2_TIME_STAMP_1)
#define AIFIFO2_TIME_STAMP_2 0x159d 	///../ucode/register.h:2846
#define P_AIFIFO2_TIME_STAMP_2 		CBUS_REG_ADDR(AIFIFO2_TIME_STAMP_2)
#define AIFIFO2_TIME_STAMP_3 0x159e 	///../ucode/register.h:2848
#define P_AIFIFO2_TIME_STAMP_3 		CBUS_REG_ADDR(AIFIFO2_TIME_STAMP_3)
#define AIFIFO2_TIME_STAMP_LENGTH 0x159f 	///../ucode/register.h:2850
#define P_AIFIFO2_TIME_STAMP_LENGTH 		CBUS_REG_ADDR(AIFIFO2_TIME_STAMP_LENGTH)
#define IEC958_TIME_STAMP_CNTL 0x15a0 	///../ucode/register.h:2860
#define P_IEC958_TIME_STAMP_CNTL 		CBUS_REG_ADDR(IEC958_TIME_STAMP_CNTL)
#define IEC958_TIME_STAMP_SYNC_0 0x15a1 	///../ucode/register.h:2862
#define P_IEC958_TIME_STAMP_SYNC_0 		CBUS_REG_ADDR(IEC958_TIME_STAMP_SYNC_0)
#define IEC958_TIME_STAMP_SYNC_1 0x15a2 	///../ucode/register.h:2864
#define P_IEC958_TIME_STAMP_SYNC_1 		CBUS_REG_ADDR(IEC958_TIME_STAMP_SYNC_1)
#define IEC958_TIME_STAMP_0 0x15a3 	///../ucode/register.h:2866
#define P_IEC958_TIME_STAMP_0 		CBUS_REG_ADDR(IEC958_TIME_STAMP_0)
#define IEC958_TIME_STAMP_1 0x15a4 	///../ucode/register.h:2868
#define P_IEC958_TIME_STAMP_1 		CBUS_REG_ADDR(IEC958_TIME_STAMP_1)
#define IEC958_TIME_STAMP_2 0x15a5 	///../ucode/register.h:2870
#define P_IEC958_TIME_STAMP_2 		CBUS_REG_ADDR(IEC958_TIME_STAMP_2)
#define IEC958_TIME_STAMP_3 0x15a6 	///../ucode/register.h:2872
#define P_IEC958_TIME_STAMP_3 		CBUS_REG_ADDR(IEC958_TIME_STAMP_3)
#define IEC958_TIME_STAMP_LENGTH 0x15a7 	///../ucode/register.h:2874
#define P_IEC958_TIME_STAMP_LENGTH 		CBUS_REG_ADDR(IEC958_TIME_STAMP_LENGTH)
#define AIU_MEM_AIFIFO2_MEM_CTL 0x15a8 	///../ucode/register.h:2878
#define P_AIU_MEM_AIFIFO2_MEM_CTL 		CBUS_REG_ADDR(AIU_MEM_AIFIFO2_MEM_CTL)
#define AIU_I2S_CBUS_DDR_CNTL 0x15a9 	///../ucode/register.h:2895
#define P_AIU_I2S_CBUS_DDR_CNTL 		CBUS_REG_ADDR(AIU_I2S_CBUS_DDR_CNTL)
#define AIU_I2S_CBUS_DDR_WDATA 0x15aa 	///../ucode/register.h:2897
#define P_AIU_I2S_CBUS_DDR_WDATA 		CBUS_REG_ADDR(AIU_I2S_CBUS_DDR_WDATA)
#define AIU_I2S_CBUS_DDR_ADDR 0x15ab 	///../ucode/register.h:2899
#define P_AIU_I2S_CBUS_DDR_ADDR 		CBUS_REG_ADDR(AIU_I2S_CBUS_DDR_ADDR)
#define GE2D_GEN_CTRL0 0x18a0 	///../ucode/register.h:2944
#define P_GE2D_GEN_CTRL0 		CBUS_REG_ADDR(GE2D_GEN_CTRL0)
#define GE2D_GEN_CTRL1 0x18a1 	///../ucode/register.h:2961
#define P_GE2D_GEN_CTRL1 		CBUS_REG_ADDR(GE2D_GEN_CTRL1)
#define GE2D_GEN_CTRL2 0x18a2 	///../ucode/register.h:3043
#define P_GE2D_GEN_CTRL2 		CBUS_REG_ADDR(GE2D_GEN_CTRL2)
#define GE2D_CMD_CTRL 0x18a3 	///../ucode/register.h:3054
#define P_GE2D_CMD_CTRL 		CBUS_REG_ADDR(GE2D_CMD_CTRL)
#define GE2D_STATUS0 0x18a4 	///../ucode/register.h:3065
#define P_GE2D_STATUS0 		CBUS_REG_ADDR(GE2D_STATUS0)
#define GE2D_STATUS1 0x18a5 	///../ucode/register.h:3081
#define P_GE2D_STATUS1 		CBUS_REG_ADDR(GE2D_STATUS1)
#define GE2D_SRC1_DEF_COLOR 0x18a6 	///../ucode/register.h:3084
#define P_GE2D_SRC1_DEF_COLOR 		CBUS_REG_ADDR(GE2D_SRC1_DEF_COLOR)
#define GE2D_SRC1_CLIPX_START_END 0x18a7 	///../ucode/register.h:3089
#define P_GE2D_SRC1_CLIPX_START_END 		CBUS_REG_ADDR(GE2D_SRC1_CLIPX_START_END)
#define GE2D_SRC1_CLIPY_START_END 0x18a8 	///../ucode/register.h:3094
#define P_GE2D_SRC1_CLIPY_START_END 		CBUS_REG_ADDR(GE2D_SRC1_CLIPY_START_END)
#define GE2D_SRC1_CANVAS 0x18a9 	///../ucode/register.h:3098
#define P_GE2D_SRC1_CANVAS 		CBUS_REG_ADDR(GE2D_SRC1_CANVAS)
#define GE2D_SRC1_X_START_END 0x18aa 	///../ucode/register.h:3107
#define P_GE2D_SRC1_X_START_END 		CBUS_REG_ADDR(GE2D_SRC1_X_START_END)
#define GE2D_SRC1_Y_START_END 0x18ab 	///../ucode/register.h:3116
#define P_GE2D_SRC1_Y_START_END 		CBUS_REG_ADDR(GE2D_SRC1_Y_START_END)
#define GE2D_SRC1_LUT_ADDR 0x18ac 	///../ucode/register.h:3120
#define P_GE2D_SRC1_LUT_ADDR 		CBUS_REG_ADDR(GE2D_SRC1_LUT_ADDR)
#define GE2D_SRC1_LUT_DAT 0x18ad 	///../ucode/register.h:3125
#define P_GE2D_SRC1_LUT_DAT 		CBUS_REG_ADDR(GE2D_SRC1_LUT_DAT)
#define GE2D_SRC1_FMT_CTRL 0x18ae 	///../ucode/register.h:3138
#define P_GE2D_SRC1_FMT_CTRL 		CBUS_REG_ADDR(GE2D_SRC1_FMT_CTRL)
#define GE2D_SRC2_DEF_COLOR 0x18af 	///../ucode/register.h:3141
#define P_GE2D_SRC2_DEF_COLOR 		CBUS_REG_ADDR(GE2D_SRC2_DEF_COLOR)
#define GE2D_SRC2_CLIPX_START_END 0x18b0 	///../ucode/register.h:3144
#define P_GE2D_SRC2_CLIPX_START_END 		CBUS_REG_ADDR(GE2D_SRC2_CLIPX_START_END)
#define GE2D_SRC2_CLIPY_START_END 0x18b1 	///../ucode/register.h:3147
#define P_GE2D_SRC2_CLIPY_START_END 		CBUS_REG_ADDR(GE2D_SRC2_CLIPY_START_END)
#define GE2D_SRC2_X_START_END 0x18b2 	///../ucode/register.h:3150
#define P_GE2D_SRC2_X_START_END 		CBUS_REG_ADDR(GE2D_SRC2_X_START_END)
#define GE2D_SRC2_Y_START_END 0x18b3 	///../ucode/register.h:3153
#define P_GE2D_SRC2_Y_START_END 		CBUS_REG_ADDR(GE2D_SRC2_Y_START_END)
#define GE2D_DST_CLIPX_START_END 0x18b4 	///../ucode/register.h:3156
#define P_GE2D_DST_CLIPX_START_END 		CBUS_REG_ADDR(GE2D_DST_CLIPX_START_END)
#define GE2D_DST_CLIPY_START_END 0x18b5 	///../ucode/register.h:3160
#define P_GE2D_DST_CLIPY_START_END 		CBUS_REG_ADDR(GE2D_DST_CLIPY_START_END)
#define GE2D_DST_X_START_END 0x18b6 	///../ucode/register.h:3163
#define P_GE2D_DST_X_START_END 		CBUS_REG_ADDR(GE2D_DST_X_START_END)
#define GE2D_DST_Y_START_END 0x18b7 	///../ucode/register.h:3167
#define P_GE2D_DST_Y_START_END 		CBUS_REG_ADDR(GE2D_DST_Y_START_END)
#define GE2D_SRC2_DST_CANVAS 0x18b8 	///../ucode/register.h:3171
#define P_GE2D_SRC2_DST_CANVAS 		CBUS_REG_ADDR(GE2D_SRC2_DST_CANVAS)
#define GE2D_VSC_START_PHASE_STEP 0x18b9 	///../ucode/register.h:3174
#define P_GE2D_VSC_START_PHASE_STEP 		CBUS_REG_ADDR(GE2D_VSC_START_PHASE_STEP)
#define GE2D_VSC_PHASE_SLOPE 0x18ba 	///../ucode/register.h:3177
#define P_GE2D_VSC_PHASE_SLOPE 		CBUS_REG_ADDR(GE2D_VSC_PHASE_SLOPE)
#define GE2D_VSC_INI_CTRL 0x18bb 	///../ucode/register.h:3180
#define P_GE2D_VSC_INI_CTRL 		CBUS_REG_ADDR(GE2D_VSC_INI_CTRL)
#define GE2D_HSC_START_PHASE_STEP 0x18bc 	///../ucode/register.h:3183
#define P_GE2D_HSC_START_PHASE_STEP 		CBUS_REG_ADDR(GE2D_HSC_START_PHASE_STEP)
#define GE2D_HSC_PHASE_SLOPE 0x18bd 	///../ucode/register.h:3186
#define P_GE2D_HSC_PHASE_SLOPE 		CBUS_REG_ADDR(GE2D_HSC_PHASE_SLOPE)
#define GE2D_HSC_INI_CTRL 0x18be 	///../ucode/register.h:3189
#define P_GE2D_HSC_INI_CTRL 		CBUS_REG_ADDR(GE2D_HSC_INI_CTRL)
#define GE2D_HSC_ADV_CTRL 0x18bf 	///../ucode/register.h:3192
#define P_GE2D_HSC_ADV_CTRL 		CBUS_REG_ADDR(GE2D_HSC_ADV_CTRL)
#define GE2D_SC_MISC_CTRL 0x18c0 	///../ucode/register.h:3209
#define P_GE2D_SC_MISC_CTRL 		CBUS_REG_ADDR(GE2D_SC_MISC_CTRL)
#define GE2D_VSC_NRND_POINT 0x18c1 	///../ucode/register.h:3213
#define P_GE2D_VSC_NRND_POINT 		CBUS_REG_ADDR(GE2D_VSC_NRND_POINT)
#define GE2D_VSC_NRND_PHASE 0x18c2 	///../ucode/register.h:3217
#define P_GE2D_VSC_NRND_PHASE 		CBUS_REG_ADDR(GE2D_VSC_NRND_PHASE)
#define GE2D_HSC_NRND_POINT 0x18c3 	///../ucode/register.h:3221
#define P_GE2D_HSC_NRND_POINT 		CBUS_REG_ADDR(GE2D_HSC_NRND_POINT)
#define GE2D_HSC_NRND_PHASE 0x18c4 	///../ucode/register.h:3225
#define P_GE2D_HSC_NRND_PHASE 		CBUS_REG_ADDR(GE2D_HSC_NRND_PHASE)
#define GE2D_MATRIX_PRE_OFFSET 0x18c5 	///../ucode/register.h:3230
#define P_GE2D_MATRIX_PRE_OFFSET 		CBUS_REG_ADDR(GE2D_MATRIX_PRE_OFFSET)
#define GE2D_MATRIX_COEF00_01 0x18c6 	///../ucode/register.h:3233
#define P_GE2D_MATRIX_COEF00_01 		CBUS_REG_ADDR(GE2D_MATRIX_COEF00_01)
#define GE2D_MATRIX_COEF02_10 0x18c7 	///../ucode/register.h:3236
#define P_GE2D_MATRIX_COEF02_10 		CBUS_REG_ADDR(GE2D_MATRIX_COEF02_10)
#define GE2D_MATRIX_COEF11_12 0x18c8 	///../ucode/register.h:3239
#define P_GE2D_MATRIX_COEF11_12 		CBUS_REG_ADDR(GE2D_MATRIX_COEF11_12)
#define GE2D_MATRIX_COEF20_21 0x18c9 	///../ucode/register.h:3242
#define P_GE2D_MATRIX_COEF20_21 		CBUS_REG_ADDR(GE2D_MATRIX_COEF20_21)
#define GE2D_MATRIX_COEF22_CTRL 0x18ca 	///../ucode/register.h:3246
#define P_GE2D_MATRIX_COEF22_CTRL 		CBUS_REG_ADDR(GE2D_MATRIX_COEF22_CTRL)
#define GE2D_MATRIX_OFFSET 0x18cb 	///../ucode/register.h:3250
#define P_GE2D_MATRIX_OFFSET 		CBUS_REG_ADDR(GE2D_MATRIX_OFFSET)
#define GE2D_ALU_OP_CTRL 0x18cc 	///../ucode/register.h:3359
#define P_GE2D_ALU_OP_CTRL 		CBUS_REG_ADDR(GE2D_ALU_OP_CTRL)
#define GE2D_ALU_CONST_COLOR 0x18cd 	///../ucode/register.h:3361
#define P_GE2D_ALU_CONST_COLOR 		CBUS_REG_ADDR(GE2D_ALU_CONST_COLOR)
#define GE2D_SRC1_KEY 0x18ce 	///../ucode/register.h:3364
#define P_GE2D_SRC1_KEY 		CBUS_REG_ADDR(GE2D_SRC1_KEY)
#define GE2D_SRC1_KEY_MASK 0x18cf 	///../ucode/register.h:3367
#define P_GE2D_SRC1_KEY_MASK 		CBUS_REG_ADDR(GE2D_SRC1_KEY_MASK)
#define GE2D_SRC2_KEY 0x18d0 	///../ucode/register.h:3370
#define P_GE2D_SRC2_KEY 		CBUS_REG_ADDR(GE2D_SRC2_KEY)
#define GE2D_SRC2_KEY_MASK 0x18d1 	///../ucode/register.h:3373
#define P_GE2D_SRC2_KEY_MASK 		CBUS_REG_ADDR(GE2D_SRC2_KEY_MASK)
#define GE2D_DST_BITMASK 0x18d2 	///../ucode/register.h:3376
#define P_GE2D_DST_BITMASK 		CBUS_REG_ADDR(GE2D_DST_BITMASK)
#define GE2D_DP_ONOFF_CTRL 0x18d3 	///../ucode/register.h:3382
#define P_GE2D_DP_ONOFF_CTRL 		CBUS_REG_ADDR(GE2D_DP_ONOFF_CTRL)
#define GE2D_SCALE_COEF_IDX 0x18d4 	///../ucode/register.h:3393
#define P_GE2D_SCALE_COEF_IDX 		CBUS_REG_ADDR(GE2D_SCALE_COEF_IDX)
#define GE2D_SCALE_COEF 0x18d5 	///../ucode/register.h:3395
#define P_GE2D_SCALE_COEF 		CBUS_REG_ADDR(GE2D_SCALE_COEF)
#define GE2D_SRC_OUTSIDE_ALPHA 0x18d6 	///../ucode/register.h:3405
#define P_GE2D_SRC_OUTSIDE_ALPHA 		CBUS_REG_ADDR(GE2D_SRC_OUTSIDE_ALPHA)
#define GE2D_ANTIFLICK_CTRL0 0x18d8 	///../ucode/register.h:3411
#define P_GE2D_ANTIFLICK_CTRL0 		CBUS_REG_ADDR(GE2D_ANTIFLICK_CTRL0)
#define GE2D_ANTIFLICK_CTRL1 0x18d9 	///../ucode/register.h:3418
#define P_GE2D_ANTIFLICK_CTRL1 		CBUS_REG_ADDR(GE2D_ANTIFLICK_CTRL1)
#define GE2D_ANTIFLICK_COLOR_FILT0 0x18da 	///../ucode/register.h:3424
#define P_GE2D_ANTIFLICK_COLOR_FILT0 		CBUS_REG_ADDR(GE2D_ANTIFLICK_COLOR_FILT0)
#define GE2D_ANTIFLICK_COLOR_FILT1 0x18db 	///../ucode/register.h:3429
#define P_GE2D_ANTIFLICK_COLOR_FILT1 		CBUS_REG_ADDR(GE2D_ANTIFLICK_COLOR_FILT1)
#define GE2D_ANTIFLICK_COLOR_FILT2 0x18dc 	///../ucode/register.h:3434
#define P_GE2D_ANTIFLICK_COLOR_FILT2 		CBUS_REG_ADDR(GE2D_ANTIFLICK_COLOR_FILT2)
#define GE2D_ANTIFLICK_COLOR_FILT3 0x18dd 	///../ucode/register.h:3438
#define P_GE2D_ANTIFLICK_COLOR_FILT3 		CBUS_REG_ADDR(GE2D_ANTIFLICK_COLOR_FILT3)
#define GE2D_ANTIFLICK_ALPHA_FILT0 0x18de 	///../ucode/register.h:3444
#define P_GE2D_ANTIFLICK_ALPHA_FILT0 		CBUS_REG_ADDR(GE2D_ANTIFLICK_ALPHA_FILT0)
#define GE2D_ANTIFLICK_ALPHA_FILT1 0x18df 	///../ucode/register.h:3449
#define P_GE2D_ANTIFLICK_ALPHA_FILT1 		CBUS_REG_ADDR(GE2D_ANTIFLICK_ALPHA_FILT1)
#define GE2D_ANTIFLICK_ALPHA_FILT2 0x18e0 	///../ucode/register.h:3454
#define P_GE2D_ANTIFLICK_ALPHA_FILT2 		CBUS_REG_ADDR(GE2D_ANTIFLICK_ALPHA_FILT2)
#define GE2D_ANTIFLICK_ALPHA_FILT3 0x18e1 	///../ucode/register.h:3458
#define P_GE2D_ANTIFLICK_ALPHA_FILT3 		CBUS_REG_ADDR(GE2D_ANTIFLICK_ALPHA_FILT3)
#define GE2D_SRC1_RANGE_MAP_Y_CTRL 0x18e3 	///../ucode/register.h:3465
#define P_GE2D_SRC1_RANGE_MAP_Y_CTRL 		CBUS_REG_ADDR(GE2D_SRC1_RANGE_MAP_Y_CTRL)
#define GE2D_SRC1_RANGE_MAP_CB_CTRL 0x18e4 	///../ucode/register.h:3472
#define P_GE2D_SRC1_RANGE_MAP_CB_CTRL 		CBUS_REG_ADDR(GE2D_SRC1_RANGE_MAP_CB_CTRL)
#define GE2D_SRC1_RANGE_MAP_CR_CTRL 0x18e5 	///../ucode/register.h:3479
#define P_GE2D_SRC1_RANGE_MAP_CR_CTRL 		CBUS_REG_ADDR(GE2D_SRC1_RANGE_MAP_CR_CTRL)
#define GE2D_ARB_BURST_NUM 0x18e6 	///../ucode/register.h:3483
#define P_GE2D_ARB_BURST_NUM 		CBUS_REG_ADDR(GE2D_ARB_BURST_NUM)
#define GE2D_TID_TOKEN 0x18e7 	///../ucode/register.h:3488
#define P_GE2D_TID_TOKEN 		CBUS_REG_ADDR(GE2D_TID_TOKEN)
#define GE2D_GEN_CTRL3 0x18e8 	///../ucode/register.h:3527
#define P_GE2D_GEN_CTRL3 		CBUS_REG_ADDR(GE2D_GEN_CTRL3)
#define GE2D_STATUS2 0x18e9 	///../ucode/register.h:3530
#define P_GE2D_STATUS2 		CBUS_REG_ADDR(GE2D_STATUS2)
#define GE2D_GEN_CTRL4 0x18ea 	///../ucode/register.h:3532
#define P_GE2D_GEN_CTRL4 		CBUS_REG_ADDR(GE2D_GEN_CTRL4)
#define AUDIO_COP_CTL2 0x1f01 	///../ucode/register.h:3545
#define P_AUDIO_COP_CTL2 		CBUS_REG_ADDR(AUDIO_COP_CTL2)
#define OPERAND_M_CTL 0x1f02 	///../ucode/register.h:3547
#define P_OPERAND_M_CTL 		CBUS_REG_ADDR(OPERAND_M_CTL)
#define OPERAND1_ADDR 0x1f03 	///../ucode/register.h:3548
#define P_OPERAND1_ADDR 		CBUS_REG_ADDR(OPERAND1_ADDR)
#define OPERAND2_ADDR 0x1f04 	///../ucode/register.h:3549
#define P_OPERAND2_ADDR 		CBUS_REG_ADDR(OPERAND2_ADDR)
#define RESULT_M_CTL 0x1f05 	///../ucode/register.h:3550
#define P_RESULT_M_CTL 		CBUS_REG_ADDR(RESULT_M_CTL)
#define RESULT1_ADDR 0x1f06 	///../ucode/register.h:3551
#define P_RESULT1_ADDR 		CBUS_REG_ADDR(RESULT1_ADDR)
#define RESULT2_ADDR 0x1f07 	///../ucode/register.h:3552
#define P_RESULT2_ADDR 		CBUS_REG_ADDR(RESULT2_ADDR)
#define ADD_SHFT_CTL 0x1f08 	///../ucode/register.h:3553
#define P_ADD_SHFT_CTL 		CBUS_REG_ADDR(ADD_SHFT_CTL)
#define OPERAND_ONE_H 0x1f09 	///../ucode/register.h:3554
#define P_OPERAND_ONE_H 		CBUS_REG_ADDR(OPERAND_ONE_H)
#define OPERAND_ONE_L 0x1f0a 	///../ucode/register.h:3555
#define P_OPERAND_ONE_L 		CBUS_REG_ADDR(OPERAND_ONE_L)
#define OPERAND_TWO_H 0x1f0b 	///../ucode/register.h:3556
#define P_OPERAND_TWO_H 		CBUS_REG_ADDR(OPERAND_TWO_H)
#define OPERAND_TWO_L 0x1f0c 	///../ucode/register.h:3557
#define P_OPERAND_TWO_L 		CBUS_REG_ADDR(OPERAND_TWO_L)
#define RESULT_H 0x1f0d 	///../ucode/register.h:3558
#define P_RESULT_H 		CBUS_REG_ADDR(RESULT_H)
#define RESULT_M 0x1f0e 	///../ucode/register.h:3559
#define P_RESULT_M 		CBUS_REG_ADDR(RESULT_M)
#define RESULT_L 0x1f0f 	///../ucode/register.h:3561
#define P_RESULT_L 		CBUS_REG_ADDR(RESULT_L)
#define WMEM_R_PTR 0x1f10 	///../ucode/register.h:3563
#define P_WMEM_R_PTR 		CBUS_REG_ADDR(WMEM_R_PTR)
#define WMEM_W_PTR 0x1f11 	///../ucode/register.h:3564
#define P_WMEM_W_PTR 		CBUS_REG_ADDR(WMEM_W_PTR)
#define AUDIO_LAYER 0x1f20 	///../ucode/register.h:3565
#define P_AUDIO_LAYER 		CBUS_REG_ADDR(AUDIO_LAYER)
#define AC3_DECODING 0x1f21 	///../ucode/register.h:3566
#define P_AC3_DECODING 		CBUS_REG_ADDR(AC3_DECODING)
#define AC3_DYNAMIC 0x1f22 	///../ucode/register.h:3567
#define P_AC3_DYNAMIC 		CBUS_REG_ADDR(AC3_DYNAMIC)
#define AC3_MELODY 0x1f23 	///../ucode/register.h:3568
#define P_AC3_MELODY 		CBUS_REG_ADDR(AC3_MELODY)
#define AC3_VOCAL 0x1f24 	///../ucode/register.h:3569
#define P_AC3_VOCAL 		CBUS_REG_ADDR(AC3_VOCAL)
#define ASSIST_AMR_SCRATCH0 0x1f4f 	///../ucode/register.h:3579
#define P_ASSIST_AMR_SCRATCH0 		CBUS_REG_ADDR(ASSIST_AMR_SCRATCH0)
#define ASSIST_AMR_SCRATCH1 0x1f50 	///../ucode/register.h:3580
#define P_ASSIST_AMR_SCRATCH1 		CBUS_REG_ADDR(ASSIST_AMR_SCRATCH1)
#define ASSIST_AMR_SCRATCH2 0x1f51 	///../ucode/register.h:3581
#define P_ASSIST_AMR_SCRATCH2 		CBUS_REG_ADDR(ASSIST_AMR_SCRATCH2)
#define ASSIST_AMR_SCRATCH3 0x1f52 	///../ucode/register.h:3582
#define P_ASSIST_AMR_SCRATCH3 		CBUS_REG_ADDR(ASSIST_AMR_SCRATCH3)
#define ASSIST_HW_REV 0x1f53 	///../ucode/register.h:3583
#define P_ASSIST_HW_REV 		CBUS_REG_ADDR(ASSIST_HW_REV)
#define ASSIST_POR_CONFIG 0x1f55 	///../ucode/register.h:3585
#define P_ASSIST_POR_CONFIG 		CBUS_REG_ADDR(ASSIST_POR_CONFIG)
#define ASSIST_SPARE16_REG1 0x1f56 	///../ucode/register.h:3586
#define P_ASSIST_SPARE16_REG1 		CBUS_REG_ADDR(ASSIST_SPARE16_REG1)
#define ASSIST_SPARE16_REG2 0x1f57 	///../ucode/register.h:3587
#define P_ASSIST_SPARE16_REG2 		CBUS_REG_ADDR(ASSIST_SPARE16_REG2)
#define ASSIST_SPARE8_REG1 0x1f58 	///../ucode/register.h:3588
#define P_ASSIST_SPARE8_REG1 		CBUS_REG_ADDR(ASSIST_SPARE8_REG1)
#define ASSIST_SPARE8_REG2 0x1f59 	///../ucode/register.h:3589
#define P_ASSIST_SPARE8_REG2 		CBUS_REG_ADDR(ASSIST_SPARE8_REG2)
#define ASSIST_SPARE8_REG3 0x1f5a 	///../ucode/register.h:3592
#define P_ASSIST_SPARE8_REG3 		CBUS_REG_ADDR(ASSIST_SPARE8_REG3)
#define AC3_CTRL_REG1 0x1f5b 	///../ucode/register.h:3597
#define P_AC3_CTRL_REG1 		CBUS_REG_ADDR(AC3_CTRL_REG1)
#define AC3_CTRL_REG2 0x1f5c 	///../ucode/register.h:3598
#define P_AC3_CTRL_REG2 		CBUS_REG_ADDR(AC3_CTRL_REG2)
#define AC3_CTRL_REG3 0x1f5d 	///../ucode/register.h:3599
#define P_AC3_CTRL_REG3 		CBUS_REG_ADDR(AC3_CTRL_REG3)
#define AC3_CTRL_REG4 0x1f5e 	///../ucode/register.h:3600
#define P_AC3_CTRL_REG4 		CBUS_REG_ADDR(AC3_CTRL_REG4)
#define ASSIST_GEN_CNTL 0x1f68 	///../ucode/register.h:3602
#define P_ASSIST_GEN_CNTL 		CBUS_REG_ADDR(ASSIST_GEN_CNTL)
#define EE_ASSIST_MBOX0_IRQ_REG 0x1f70 	///../ucode/register.h:3603
#define P_EE_ASSIST_MBOX0_IRQ_REG 		CBUS_REG_ADDR(EE_ASSIST_MBOX0_IRQ_REG)
#define EE_ASSIST_MBOX0_CLR_REG 0x1f71 	///../ucode/register.h:3604
#define P_EE_ASSIST_MBOX0_CLR_REG 		CBUS_REG_ADDR(EE_ASSIST_MBOX0_CLR_REG)
#define EE_ASSIST_MBOX0_MASK 0x1f72 	///../ucode/register.h:3605
#define P_EE_ASSIST_MBOX0_MASK 		CBUS_REG_ADDR(EE_ASSIST_MBOX0_MASK)
#define EE_ASSIST_MBOX0_FIQ_SEL 0x1f73 	///../ucode/register.h:3606
#define P_EE_ASSIST_MBOX0_FIQ_SEL 		CBUS_REG_ADDR(EE_ASSIST_MBOX0_FIQ_SEL)
#define EE_ASSIST_MBOX1_IRQ_REG 0x1f74 	///../ucode/register.h:3607
#define P_EE_ASSIST_MBOX1_IRQ_REG 		CBUS_REG_ADDR(EE_ASSIST_MBOX1_IRQ_REG)
#define EE_ASSIST_MBOX1_CLR_REG 0x1f75 	///../ucode/register.h:3608
#define P_EE_ASSIST_MBOX1_CLR_REG 		CBUS_REG_ADDR(EE_ASSIST_MBOX1_CLR_REG)
#define EE_ASSIST_MBOX1_MASK 0x1f76 	///../ucode/register.h:3609
#define P_EE_ASSIST_MBOX1_MASK 		CBUS_REG_ADDR(EE_ASSIST_MBOX1_MASK)
#define EE_ASSIST_MBOX1_FIQ_SEL 0x1f77 	///../ucode/register.h:3610
#define P_EE_ASSIST_MBOX1_FIQ_SEL 		CBUS_REG_ADDR(EE_ASSIST_MBOX1_FIQ_SEL)
#define EE_ASSIST_MBOX2_IRQ_REG 0x1f78 	///../ucode/register.h:3611
#define P_EE_ASSIST_MBOX2_IRQ_REG 		CBUS_REG_ADDR(EE_ASSIST_MBOX2_IRQ_REG)
#define EE_ASSIST_MBOX2_CLR_REG 0x1f79 	///../ucode/register.h:3612
#define P_EE_ASSIST_MBOX2_CLR_REG 		CBUS_REG_ADDR(EE_ASSIST_MBOX2_CLR_REG)
#define EE_ASSIST_MBOX2_MASK 0x1f7a 	///../ucode/register.h:3613
#define P_EE_ASSIST_MBOX2_MASK 		CBUS_REG_ADDR(EE_ASSIST_MBOX2_MASK)
#define EE_ASSIST_MBOX2_FIQ_SEL 0x1f7b 	///../ucode/register.h:3614
#define P_EE_ASSIST_MBOX2_FIQ_SEL 		CBUS_REG_ADDR(EE_ASSIST_MBOX2_FIQ_SEL)
#define EE_ASSIST_MBOX3_IRQ_REG 0x1f7c 	///../ucode/register.h:3615
#define P_EE_ASSIST_MBOX3_IRQ_REG 		CBUS_REG_ADDR(EE_ASSIST_MBOX3_IRQ_REG)
#define EE_ASSIST_MBOX3_CLR_REG 0x1f7d 	///../ucode/register.h:3616
#define P_EE_ASSIST_MBOX3_CLR_REG 		CBUS_REG_ADDR(EE_ASSIST_MBOX3_CLR_REG)
#define EE_ASSIST_MBOX3_MASK 0x1f7e 	///../ucode/register.h:3617
#define P_EE_ASSIST_MBOX3_MASK 		CBUS_REG_ADDR(EE_ASSIST_MBOX3_MASK)
#define EE_ASSIST_MBOX3_FIQ_SEL 0x1f7f 	///../ucode/register.h:3618
#define P_EE_ASSIST_MBOX3_FIQ_SEL 		CBUS_REG_ADDR(EE_ASSIST_MBOX3_FIQ_SEL)
#define AUDIN_SPDIF_MODE 0x2800 	///../ucode/register.h:3625
#define P_AUDIN_SPDIF_MODE 		CBUS_REG_ADDR(AUDIN_SPDIF_MODE)
#define AUDIN_SPDIF_FS_CLK_RLTN 0x2801 	///../ucode/register.h:3637
#define P_AUDIN_SPDIF_FS_CLK_RLTN 		CBUS_REG_ADDR(AUDIN_SPDIF_FS_CLK_RLTN)
#define AUDIN_SPDIF_CHNL_STS_A 0x2802 	///../ucode/register.h:3643
#define P_AUDIN_SPDIF_CHNL_STS_A 		CBUS_REG_ADDR(AUDIN_SPDIF_CHNL_STS_A)
#define AUDIN_SPDIF_CHNL_STS_B 0x2803 	///../ucode/register.h:3644
#define P_AUDIN_SPDIF_CHNL_STS_B 		CBUS_REG_ADDR(AUDIN_SPDIF_CHNL_STS_B)
#define AUDIN_SPDIF_MISC 0x2804 	///../ucode/register.h:3645
#define P_AUDIN_SPDIF_MISC 		CBUS_REG_ADDR(AUDIN_SPDIF_MISC)
#define AUDIN_SPDIF_NPCM_PCPD 0x2805 	///../ucode/register.h:3646
#define P_AUDIN_SPDIF_NPCM_PCPD 		CBUS_REG_ADDR(AUDIN_SPDIF_NPCM_PCPD)
#define AUDIN_SPDIF_END 0x280f 	///../ucode/register.h:3647
#define P_AUDIN_SPDIF_END 		CBUS_REG_ADDR(AUDIN_SPDIF_END)
#define AUDIN_I2SIN_CTRL 0x2810 	///../ucode/register.h:3648
#define P_AUDIN_I2SIN_CTRL 		CBUS_REG_ADDR(AUDIN_I2SIN_CTRL)
#define AUDIN_SOURCE_SEL 0x2811 	///../ucode/register.h:3665
#define P_AUDIN_SOURCE_SEL 		CBUS_REG_ADDR(AUDIN_SOURCE_SEL)
#define AUDIN_DECODE_FORMAT 0x2812 	///../ucode/register.h:3682
#define P_AUDIN_DECODE_FORMAT 		CBUS_REG_ADDR(AUDIN_DECODE_FORMAT)
#define AUDIN_DECODE_CONTROL_STATUS 0x2813 	///../ucode/register.h:3692
#define P_AUDIN_DECODE_CONTROL_STATUS 		CBUS_REG_ADDR(AUDIN_DECODE_CONTROL_STATUS)
#define AUDIN_DECODE_CHANNEL_STATUS_A_0 0x2814 	///../ucode/register.h:3694
#define P_AUDIN_DECODE_CHANNEL_STATUS_A_0 		CBUS_REG_ADDR(AUDIN_DECODE_CHANNEL_STATUS_A_0)
#define AUDIN_DECODE_CHANNEL_STATUS_A_1 0x2815 	///../ucode/register.h:3695
#define P_AUDIN_DECODE_CHANNEL_STATUS_A_1 		CBUS_REG_ADDR(AUDIN_DECODE_CHANNEL_STATUS_A_1)
#define AUDIN_DECODE_CHANNEL_STATUS_A_2 0x2816 	///../ucode/register.h:3696
#define P_AUDIN_DECODE_CHANNEL_STATUS_A_2 		CBUS_REG_ADDR(AUDIN_DECODE_CHANNEL_STATUS_A_2)
#define AUDIN_DECODE_CHANNEL_STATUS_A_3 0x2817 	///../ucode/register.h:3697
#define P_AUDIN_DECODE_CHANNEL_STATUS_A_3 		CBUS_REG_ADDR(AUDIN_DECODE_CHANNEL_STATUS_A_3)
#define AUDIN_DECODE_CHANNEL_STATUS_A_4 0x2818 	///../ucode/register.h:3698
#define P_AUDIN_DECODE_CHANNEL_STATUS_A_4 		CBUS_REG_ADDR(AUDIN_DECODE_CHANNEL_STATUS_A_4)
#define AUDIN_DECODE_CHANNEL_STATUS_A_5 0x2819 	///../ucode/register.h:3699
#define P_AUDIN_DECODE_CHANNEL_STATUS_A_5 		CBUS_REG_ADDR(AUDIN_DECODE_CHANNEL_STATUS_A_5)
#define AUDIN_FIFO0_START 0x2820 	///../ucode/register.h:3700
#define P_AUDIN_FIFO0_START 		CBUS_REG_ADDR(AUDIN_FIFO0_START)
#define AUDIN_FIFO0_END 0x2821 	///../ucode/register.h:3701
#define P_AUDIN_FIFO0_END 		CBUS_REG_ADDR(AUDIN_FIFO0_END)
#define AUDIN_FIFO0_PTR 0x2822 	///../ucode/register.h:3702
#define P_AUDIN_FIFO0_PTR 		CBUS_REG_ADDR(AUDIN_FIFO0_PTR)
#define AUDIN_FIFO0_INTR 0x2823 	///../ucode/register.h:3703
#define P_AUDIN_FIFO0_INTR 		CBUS_REG_ADDR(AUDIN_FIFO0_INTR)
#define AUDIN_FIFO0_RDPTR 0x2824 	///../ucode/register.h:3704
#define P_AUDIN_FIFO0_RDPTR 		CBUS_REG_ADDR(AUDIN_FIFO0_RDPTR)
#define AUDIN_FIFO0_CTRL 0x2825 	///../ucode/register.h:3705
#define P_AUDIN_FIFO0_CTRL 		CBUS_REG_ADDR(AUDIN_FIFO0_CTRL)
#define AUDIN_FIFO0_CTRL1 0x2826 	///../ucode/register.h:3728
#define P_AUDIN_FIFO0_CTRL1 		CBUS_REG_ADDR(AUDIN_FIFO0_CTRL1)
#define AUDIN_FIFO0_LVL0 0x2827 	///../ucode/register.h:3741
#define P_AUDIN_FIFO0_LVL0 		CBUS_REG_ADDR(AUDIN_FIFO0_LVL0)
#define AUDIN_FIFO0_LVL1 0x2828 	///../ucode/register.h:3742
#define P_AUDIN_FIFO0_LVL1 		CBUS_REG_ADDR(AUDIN_FIFO0_LVL1)
#define AUDIN_FIFO0_LVL2 0x2829 	///../ucode/register.h:3743
#define P_AUDIN_FIFO0_LVL2 		CBUS_REG_ADDR(AUDIN_FIFO0_LVL2)
#define AUDIN_FIFO0_REQID 0x2830 	///../ucode/register.h:3744
#define P_AUDIN_FIFO0_REQID 		CBUS_REG_ADDR(AUDIN_FIFO0_REQID)
#define AUDIN_FIFO0_WRAP 0x2831 	///../ucode/register.h:3745
#define P_AUDIN_FIFO0_WRAP 		CBUS_REG_ADDR(AUDIN_FIFO0_WRAP)
#define AUDIN_FIFO1_START 0x2833 	///../ucode/register.h:3746
#define P_AUDIN_FIFO1_START 		CBUS_REG_ADDR(AUDIN_FIFO1_START)
#define AUDIN_FIFO1_END 0x2834 	///../ucode/register.h:3747
#define P_AUDIN_FIFO1_END 		CBUS_REG_ADDR(AUDIN_FIFO1_END)
#define AUDIN_FIFO1_PTR 0x2835 	///../ucode/register.h:3748
#define P_AUDIN_FIFO1_PTR 		CBUS_REG_ADDR(AUDIN_FIFO1_PTR)
#define AUDIN_FIFO1_INTR 0x2836 	///../ucode/register.h:3749
#define P_AUDIN_FIFO1_INTR 		CBUS_REG_ADDR(AUDIN_FIFO1_INTR)
#define AUDIN_FIFO1_RDPTR 0x2837 	///../ucode/register.h:3750
#define P_AUDIN_FIFO1_RDPTR 		CBUS_REG_ADDR(AUDIN_FIFO1_RDPTR)
#define AUDIN_FIFO1_CTRL 0x2838 	///../ucode/register.h:3751
#define P_AUDIN_FIFO1_CTRL 		CBUS_REG_ADDR(AUDIN_FIFO1_CTRL)
#define AUDIN_FIFO1_CTRL1 0x2839 	///../ucode/register.h:3772
#define P_AUDIN_FIFO1_CTRL1 		CBUS_REG_ADDR(AUDIN_FIFO1_CTRL1)
#define AUDIN_FIFO1_LVL0 0x2840 	///../ucode/register.h:3785
#define P_AUDIN_FIFO1_LVL0 		CBUS_REG_ADDR(AUDIN_FIFO1_LVL0)
#define AUDIN_FIFO1_LVL1 0x2841 	///../ucode/register.h:3786
#define P_AUDIN_FIFO1_LVL1 		CBUS_REG_ADDR(AUDIN_FIFO1_LVL1)
#define AUDIN_FIFO1_LVL2 0x2842 	///../ucode/register.h:3787
#define P_AUDIN_FIFO1_LVL2 		CBUS_REG_ADDR(AUDIN_FIFO1_LVL2)
#define AUDIN_FIFO1_REQID 0x2843 	///../ucode/register.h:3788
#define P_AUDIN_FIFO1_REQID 		CBUS_REG_ADDR(AUDIN_FIFO1_REQID)
#define AUDIN_FIFO1_WRAP 0x2844 	///../ucode/register.h:3789
#define P_AUDIN_FIFO1_WRAP 		CBUS_REG_ADDR(AUDIN_FIFO1_WRAP)
#define AUDIN_FIFO2_START 0x2845 	///../ucode/register.h:3790
#define P_AUDIN_FIFO2_START 		CBUS_REG_ADDR(AUDIN_FIFO2_START)
#define AUDIN_FIFO2_END 0x2846 	///../ucode/register.h:3791
#define P_AUDIN_FIFO2_END 		CBUS_REG_ADDR(AUDIN_FIFO2_END)
#define AUDIN_FIFO2_PTR 0x2847 	///../ucode/register.h:3792
#define P_AUDIN_FIFO2_PTR 		CBUS_REG_ADDR(AUDIN_FIFO2_PTR)
#define AUDIN_FIFO2_INTR 0x2848 	///../ucode/register.h:3793
#define P_AUDIN_FIFO2_INTR 		CBUS_REG_ADDR(AUDIN_FIFO2_INTR)
#define AUDIN_FIFO2_RDPTR 0x2849 	///../ucode/register.h:3794
#define P_AUDIN_FIFO2_RDPTR 		CBUS_REG_ADDR(AUDIN_FIFO2_RDPTR)
#define AUDIN_FIFO2_CTRL 0x284a 	///../ucode/register.h:3795
#define P_AUDIN_FIFO2_CTRL 		CBUS_REG_ADDR(AUDIN_FIFO2_CTRL)
#define AUDIN_FIFO2_CTRL1 0x284b 	///../ucode/register.h:3796
#define P_AUDIN_FIFO2_CTRL1 		CBUS_REG_ADDR(AUDIN_FIFO2_CTRL1)
#define AUDIN_FIFO2_LVL0 0x284c 	///../ucode/register.h:3797
#define P_AUDIN_FIFO2_LVL0 		CBUS_REG_ADDR(AUDIN_FIFO2_LVL0)
#define AUDIN_FIFO2_LVL1 0x284d 	///../ucode/register.h:3798
#define P_AUDIN_FIFO2_LVL1 		CBUS_REG_ADDR(AUDIN_FIFO2_LVL1)
#define AUDIN_FIFO2_LVL2 0x284e 	///../ucode/register.h:3799
#define P_AUDIN_FIFO2_LVL2 		CBUS_REG_ADDR(AUDIN_FIFO2_LVL2)
#define AUDIN_FIFO2_REQID 0x284f 	///../ucode/register.h:3800
#define P_AUDIN_FIFO2_REQID 		CBUS_REG_ADDR(AUDIN_FIFO2_REQID)
#define AUDIN_FIFO2_WRAP 0x2850 	///../ucode/register.h:3801
#define P_AUDIN_FIFO2_WRAP 		CBUS_REG_ADDR(AUDIN_FIFO2_WRAP)
#define AUDIN_INT_CTRL 0x2851 	///../ucode/register.h:3802
#define P_AUDIN_INT_CTRL 		CBUS_REG_ADDR(AUDIN_INT_CTRL)
#define AUDIN_FIFO_INT 0x2852 	///../ucode/register.h:3815
#define P_AUDIN_FIFO_INT 		CBUS_REG_ADDR(AUDIN_FIFO_INT)
#define PCMIN_CTRL0 0x2860 	///../ucode/register.h:3827
#define P_PCMIN_CTRL0 		CBUS_REG_ADDR(PCMIN_CTRL0)
#define PCMIN_CTRL1 0x2861 	///../ucode/register.h:3846
#define P_PCMIN_CTRL1 		CBUS_REG_ADDR(PCMIN_CTRL1)
#define PCMOUT_CTRL0 0x2870 	///../ucode/register.h:3879
#define P_PCMOUT_CTRL0 		CBUS_REG_ADDR(PCMOUT_CTRL0)
#define PCMOUT_CTRL1 0x2871 	///../ucode/register.h:3890
#define P_PCMOUT_CTRL1 		CBUS_REG_ADDR(PCMOUT_CTRL1)
#define PCMOUT_CTRL2 0x2872 	///../ucode/register.h:3900
#define P_PCMOUT_CTRL2 		CBUS_REG_ADDR(PCMOUT_CTRL2)
#define PCMOUT_CTRL3 0x2873 	///../ucode/register.h:3906
#define P_PCMOUT_CTRL3 		CBUS_REG_ADDR(PCMOUT_CTRL3)
#define AUDOUT_CTRL 0x2880 	///../ucode/register.h:3937
#define P_AUDOUT_CTRL 		CBUS_REG_ADDR(AUDOUT_CTRL)
#define AUDOUT_CTRL1 0x2881 	///../ucode/register.h:3953
#define P_AUDOUT_CTRL1 		CBUS_REG_ADDR(AUDOUT_CTRL1)
#define AUDOUT_BUF0_STA 0x2882 	///../ucode/register.h:3956
#define P_AUDOUT_BUF0_STA 		CBUS_REG_ADDR(AUDOUT_BUF0_STA)
#define AUDOUT_BUF0_EDA 0x2883 	///../ucode/register.h:3958
#define P_AUDOUT_BUF0_EDA 		CBUS_REG_ADDR(AUDOUT_BUF0_EDA)
#define AUDOUT_BUF0_WPTR 0x2884 	///../ucode/register.h:3960
#define P_AUDOUT_BUF0_WPTR 		CBUS_REG_ADDR(AUDOUT_BUF0_WPTR)
#define AUDOUT_BUF1_STA 0x2885 	///../ucode/register.h:3962
#define P_AUDOUT_BUF1_STA 		CBUS_REG_ADDR(AUDOUT_BUF1_STA)
#define AUDOUT_BUF1_EDA 0x2886 	///../ucode/register.h:3964
#define P_AUDOUT_BUF1_EDA 		CBUS_REG_ADDR(AUDOUT_BUF1_EDA)
#define AUDOUT_BUF1_WPTR 0x2887 	///../ucode/register.h:3966
#define P_AUDOUT_BUF1_WPTR 		CBUS_REG_ADDR(AUDOUT_BUF1_WPTR)
#define AUDOUT_FIFO_RPTR 0x2888 	///../ucode/register.h:3968
#define P_AUDOUT_FIFO_RPTR 		CBUS_REG_ADDR(AUDOUT_FIFO_RPTR)
#define AUDOUT_INTR_PTR 0x2889 	///../ucode/register.h:3970
#define P_AUDOUT_INTR_PTR 		CBUS_REG_ADDR(AUDOUT_INTR_PTR)
#define AUDOUT_FIFO_STS 0x288a 	///../ucode/register.h:3972
#define P_AUDOUT_FIFO_STS 		CBUS_REG_ADDR(AUDOUT_FIFO_STS)
#define AUDIN_HDMI_MEAS_CTRL 0x28a0 	///../ucode/register.h:3987
#define P_AUDIN_HDMI_MEAS_CTRL 		CBUS_REG_ADDR(AUDIN_HDMI_MEAS_CTRL)
#define AUDIN_HDMI_MEAS_CYCLES_M1 0x28a1 	///../ucode/register.h:3988
#define P_AUDIN_HDMI_MEAS_CYCLES_M1 		CBUS_REG_ADDR(AUDIN_HDMI_MEAS_CYCLES_M1)
#define AUDIN_HDMI_MEAS_INTR_MASKN 0x28a2 	///../ucode/register.h:3989
#define P_AUDIN_HDMI_MEAS_INTR_MASKN 		CBUS_REG_ADDR(AUDIN_HDMI_MEAS_INTR_MASKN)
#define AUDIN_HDMI_MEAS_INTR_STAT 0x28a3 	///../ucode/register.h:3990
#define P_AUDIN_HDMI_MEAS_INTR_STAT 		CBUS_REG_ADDR(AUDIN_HDMI_MEAS_INTR_STAT)
#define AUDIN_HDMI_REF_CYCLES_STAT_0 0x28a4 	///../ucode/register.h:3991
#define P_AUDIN_HDMI_REF_CYCLES_STAT_0 		CBUS_REG_ADDR(AUDIN_HDMI_REF_CYCLES_STAT_0)
#define AUDIN_HDMI_REF_CYCLES_STAT_1 0x28a5 	///../ucode/register.h:3992
#define P_AUDIN_HDMI_REF_CYCLES_STAT_1 		CBUS_REG_ADDR(AUDIN_HDMI_REF_CYCLES_STAT_1)
#define AUDIN_HDMIRX_AFIFO_STAT 0x28a6 	///../ucode/register.h:3993
#define P_AUDIN_HDMIRX_AFIFO_STAT 		CBUS_REG_ADDR(AUDIN_HDMIRX_AFIFO_STAT)
#define AUDIN_FIFO0_PIO_STS 0x28b0 	///../ucode/register.h:3994
#define P_AUDIN_FIFO0_PIO_STS 		CBUS_REG_ADDR(AUDIN_FIFO0_PIO_STS)
#define AUDIN_FIFO0_PIO_RDL 0x28b1 	///../ucode/register.h:3995
#define P_AUDIN_FIFO0_PIO_RDL 		CBUS_REG_ADDR(AUDIN_FIFO0_PIO_RDL)
#define AUDIN_FIFO0_PIO_RDH 0x28b2 	///../ucode/register.h:3996
#define P_AUDIN_FIFO0_PIO_RDH 		CBUS_REG_ADDR(AUDIN_FIFO0_PIO_RDH)
#define AUDIN_FIFO1_PIO_STS 0x28b3 	///../ucode/register.h:3997
#define P_AUDIN_FIFO1_PIO_STS 		CBUS_REG_ADDR(AUDIN_FIFO1_PIO_STS)
#define AUDIN_FIFO1_PIO_RDL 0x28b4 	///../ucode/register.h:3998
#define P_AUDIN_FIFO1_PIO_RDL 		CBUS_REG_ADDR(AUDIN_FIFO1_PIO_RDL)
#define AUDIN_FIFO1_PIO_RDH 0x28b5 	///../ucode/register.h:3999
#define P_AUDIN_FIFO1_PIO_RDH 		CBUS_REG_ADDR(AUDIN_FIFO1_PIO_RDH)
#define AUDIN_FIFO2_PIO_STS 0x28b6 	///../ucode/register.h:4000
#define P_AUDIN_FIFO2_PIO_STS 		CBUS_REG_ADDR(AUDIN_FIFO2_PIO_STS)
#define AUDIN_FIFO2_PIO_RDL 0x28b7 	///../ucode/register.h:4001
#define P_AUDIN_FIFO2_PIO_RDL 		CBUS_REG_ADDR(AUDIN_FIFO2_PIO_RDL)
#define AUDIN_FIFO2_PIO_RDH 0x28b8 	///../ucode/register.h:4002
#define P_AUDIN_FIFO2_PIO_RDH 		CBUS_REG_ADDR(AUDIN_FIFO2_PIO_RDH)
#define AUDOUT_FIFO_PIO_STS 0x28b9 	///../ucode/register.h:4003
#define P_AUDOUT_FIFO_PIO_STS 		CBUS_REG_ADDR(AUDOUT_FIFO_PIO_STS)
#define AUDOUT_FIFO_PIO_WRL 0x28ba 	///../ucode/register.h:4004
#define P_AUDOUT_FIFO_PIO_WRL 		CBUS_REG_ADDR(AUDOUT_FIFO_PIO_WRL)
#define AUDOUT_FIFO_PIO_WRH 0x28bb 	///../ucode/register.h:4006
#define P_AUDOUT_FIFO_PIO_WRH 		CBUS_REG_ADDR(AUDOUT_FIFO_PIO_WRH)
#define AUDIN_ADDR_END 0x28bf 	///../ucode/register.h:4013
#define P_AUDIN_ADDR_END 		CBUS_REG_ADDR(AUDIN_ADDR_END)
#define VDIN_SCALE_COEF_IDX 0x1200 	///../ucode/register.h:4035
#define P_VDIN_SCALE_COEF_IDX 		VCBUS_REG_ADDR(VDIN_SCALE_COEF_IDX)
#define VDIN_SCALE_COEF 0x1201 	///../ucode/register.h:4036
#define P_VDIN_SCALE_COEF 		VCBUS_REG_ADDR(VDIN_SCALE_COEF)
#define VDIN_COM_CTRL0 0x1202 	///../ucode/register.h:4051
#define P_VDIN_COM_CTRL0 		VCBUS_REG_ADDR(VDIN_COM_CTRL0)
#define VDIN_ACTIVE_MAX_PIX_CNT_STATUS 0x1203 	///../ucode/register.h:4054
#define P_VDIN_ACTIVE_MAX_PIX_CNT_STATUS 		VCBUS_REG_ADDR(VDIN_ACTIVE_MAX_PIX_CNT_STATUS)
#define VDIN_LCNT_STATUS 0x1204 	///../ucode/register.h:4057
#define P_VDIN_LCNT_STATUS 		VCBUS_REG_ADDR(VDIN_LCNT_STATUS)
#define VDIN_COM_STATUS0 0x1205 	///../ucode/register.h:4063
#define P_VDIN_COM_STATUS0 		VCBUS_REG_ADDR(VDIN_COM_STATUS0)
#define VDIN_COM_STATUS1 0x1206 	///../ucode/register.h:4073
#define P_VDIN_COM_STATUS1 		VCBUS_REG_ADDR(VDIN_COM_STATUS1)
#define VDIN_LCNT_SHADOW_STATUS 0x1207 	///../ucode/register.h:4076
#define P_VDIN_LCNT_SHADOW_STATUS 		VCBUS_REG_ADDR(VDIN_LCNT_SHADOW_STATUS)
#define VDIN_ASFIFO_CTRL0 0x1208 	///../ucode/register.h:4088
#define P_VDIN_ASFIFO_CTRL0 		VCBUS_REG_ADDR(VDIN_ASFIFO_CTRL0)
#define VDIN_ASFIFO_CTRL1 0x1209 	///../ucode/register.h:4091
#define P_VDIN_ASFIFO_CTRL1 		VCBUS_REG_ADDR(VDIN_ASFIFO_CTRL1)
#define VDIN_WIDTHM1I_WIDTHM1O 0x120a 	///../ucode/register.h:4094
#define P_VDIN_WIDTHM1I_WIDTHM1O 		VCBUS_REG_ADDR(VDIN_WIDTHM1I_WIDTHM1O)
#define VDIN_SC_MISC_CTRL 0x120b 	///../ucode/register.h:4105
#define P_VDIN_SC_MISC_CTRL 		VCBUS_REG_ADDR(VDIN_SC_MISC_CTRL)
#define VDIN_HSC_PHASE_STEP 0x120c 	///../ucode/register.h:4108
#define P_VDIN_HSC_PHASE_STEP 		VCBUS_REG_ADDR(VDIN_HSC_PHASE_STEP)
#define VDIN_HSC_INI_CTRL 0x120d 	///../ucode/register.h:4112
#define P_VDIN_HSC_INI_CTRL 		VCBUS_REG_ADDR(VDIN_HSC_INI_CTRL)
#define VDIN_COM_STATUS2 0x120e 	///../ucode/register.h:4120
#define P_VDIN_COM_STATUS2 		VCBUS_REG_ADDR(VDIN_COM_STATUS2)
#define VDIN_ASFIFO_CTRL2 0x120f 	///../ucode/register.h:4128
#define P_VDIN_ASFIFO_CTRL2 		VCBUS_REG_ADDR(VDIN_ASFIFO_CTRL2)
#define VDIN_MATRIX_CTRL 0x1210 	///../ucode/register.h:4135
#define P_VDIN_MATRIX_CTRL 		VCBUS_REG_ADDR(VDIN_MATRIX_CTRL)
#define VDIN_MATRIX_COEF00_01 0x1211 	///../ucode/register.h:4138
#define P_VDIN_MATRIX_COEF00_01 		VCBUS_REG_ADDR(VDIN_MATRIX_COEF00_01)
#define VDIN_MATRIX_COEF02_10 0x1212 	///../ucode/register.h:4141
#define P_VDIN_MATRIX_COEF02_10 		VCBUS_REG_ADDR(VDIN_MATRIX_COEF02_10)
#define VDIN_MATRIX_COEF11_12 0x1213 	///../ucode/register.h:4144
#define P_VDIN_MATRIX_COEF11_12 		VCBUS_REG_ADDR(VDIN_MATRIX_COEF11_12)
#define VDIN_MATRIX_COEF20_21 0x1214 	///../ucode/register.h:4147
#define P_VDIN_MATRIX_COEF20_21 		VCBUS_REG_ADDR(VDIN_MATRIX_COEF20_21)
#define VDIN_MATRIX_COEF22 0x1215 	///../ucode/register.h:4148
#define P_VDIN_MATRIX_COEF22 		VCBUS_REG_ADDR(VDIN_MATRIX_COEF22)
#define VDIN_MATRIX_OFFSET0_1 0x1216 	///../ucode/register.h:4151
#define P_VDIN_MATRIX_OFFSET0_1 		VCBUS_REG_ADDR(VDIN_MATRIX_OFFSET0_1)
#define VDIN_MATRIX_OFFSET2 0x1217 	///../ucode/register.h:4153
#define P_VDIN_MATRIX_OFFSET2 		VCBUS_REG_ADDR(VDIN_MATRIX_OFFSET2)
#define VDIN_MATRIX_PRE_OFFSET0_1 0x1218 	///../ucode/register.h:4156
#define P_VDIN_MATRIX_PRE_OFFSET0_1 		VCBUS_REG_ADDR(VDIN_MATRIX_PRE_OFFSET0_1)
#define VDIN_MATRIX_PRE_OFFSET2 0x1219 	///../ucode/register.h:4158
#define P_VDIN_MATRIX_PRE_OFFSET2 		VCBUS_REG_ADDR(VDIN_MATRIX_PRE_OFFSET2)
#define VDIN_LFIFO_CTRL 0x121a 	///../ucode/register.h:4160
#define P_VDIN_LFIFO_CTRL 		VCBUS_REG_ADDR(VDIN_LFIFO_CTRL)
#define VDIN_COM_GCLK_CTRL 0x121b 	///../ucode/register.h:4161
#define P_VDIN_COM_GCLK_CTRL 		VCBUS_REG_ADDR(VDIN_COM_GCLK_CTRL)
#define VDIN_INTF_WIDTHM1 0x121c 	///../ucode/register.h:4163
#define P_VDIN_INTF_WIDTHM1 		VCBUS_REG_ADDR(VDIN_INTF_WIDTHM1)
#define VDIN_WR_CTRL2 0x121f 	///../ucode/register.h:4166
#define P_VDIN_WR_CTRL2 		VCBUS_REG_ADDR(VDIN_WR_CTRL2)
#define VDIN_WR_CTRL 0x1220 	///../ucode/register.h:4193
#define P_VDIN_WR_CTRL 		VCBUS_REG_ADDR(VDIN_WR_CTRL)
#define VDIN_WR_H_START_END 0x1221 	///../ucode/register.h:4197
#define P_VDIN_WR_H_START_END 		VCBUS_REG_ADDR(VDIN_WR_H_START_END)
#define VDIN_WR_V_START_END 0x1222 	///../ucode/register.h:4201
#define P_VDIN_WR_V_START_END 		VCBUS_REG_ADDR(VDIN_WR_V_START_END)
#define VDIN_VSC_PHASE_STEP 0x1223 	///../ucode/register.h:4204
#define P_VDIN_VSC_PHASE_STEP 		VCBUS_REG_ADDR(VDIN_VSC_PHASE_STEP)
#define VDIN_VSC_INI_CTRL 0x1224 	///../ucode/register.h:4209
#define P_VDIN_VSC_INI_CTRL 		VCBUS_REG_ADDR(VDIN_VSC_INI_CTRL)
#define VDIN_SCIN_HEIGHTM1 0x1225 	///../ucode/register.h:4211
#define P_VDIN_SCIN_HEIGHTM1 		VCBUS_REG_ADDR(VDIN_SCIN_HEIGHTM1)
#define VDIN_DUMMY_DATA 0x1226 	///../ucode/register.h:4215
#define P_VDIN_DUMMY_DATA 		VCBUS_REG_ADDR(VDIN_DUMMY_DATA)
#define VDIN_MATRIX_PROBE_COLOR 0x1228 	///../ucode/register.h:4220
#define P_VDIN_MATRIX_PROBE_COLOR 		VCBUS_REG_ADDR(VDIN_MATRIX_PROBE_COLOR)
#define VDIN_MATRIX_HL_COLOR 0x1229 	///../ucode/register.h:4224
#define P_VDIN_MATRIX_HL_COLOR 		VCBUS_REG_ADDR(VDIN_MATRIX_HL_COLOR)
#define VDIN_MATRIX_PROBE_POS 0x122a 	///../ucode/register.h:4227
#define P_VDIN_MATRIX_PROBE_POS 		VCBUS_REG_ADDR(VDIN_MATRIX_PROBE_POS)
#define VDIN_CHROMA_ADDR_PORT 0x122b 	///../ucode/register.h:4228
#define P_VDIN_CHROMA_ADDR_PORT 		VCBUS_REG_ADDR(VDIN_CHROMA_ADDR_PORT)
#define VDIN_CHROMA_DATA_PORT 0x122c 	///../ucode/register.h:4229
#define P_VDIN_CHROMA_DATA_PORT 		VCBUS_REG_ADDR(VDIN_CHROMA_DATA_PORT)
#define VDIN_CM_BRI_CON_CTRL 0x122d 	///../ucode/register.h:4231
#define P_VDIN_CM_BRI_CON_CTRL 		VCBUS_REG_ADDR(VDIN_CM_BRI_CON_CTRL)
#define VDIN_GO_LINE_CTRL 0x122f 	///../ucode/register.h:4235
#define P_VDIN_GO_LINE_CTRL 		VCBUS_REG_ADDR(VDIN_GO_LINE_CTRL)
#define VDIN_HIST_CTRL 0x1230 	///../ucode/register.h:4242
#define P_VDIN_HIST_CTRL 		VCBUS_REG_ADDR(VDIN_HIST_CTRL)
#define VDIN_HIST_H_START_END 0x1231 	///../ucode/register.h:4245
#define P_VDIN_HIST_H_START_END 		VCBUS_REG_ADDR(VDIN_HIST_H_START_END)
#define VDIN_HIST_V_START_END 0x1232 	///../ucode/register.h:4248
#define P_VDIN_HIST_V_START_END 		VCBUS_REG_ADDR(VDIN_HIST_V_START_END)
#define VDIN_HIST_MAX_MIN 0x1233 	///../ucode/register.h:4252
#define P_VDIN_HIST_MAX_MIN 		VCBUS_REG_ADDR(VDIN_HIST_MAX_MIN)
#define VDIN_HIST_SPL_VAL 0x1234 	///../ucode/register.h:4256
#define P_VDIN_HIST_SPL_VAL 		VCBUS_REG_ADDR(VDIN_HIST_SPL_VAL)
#define VDIN_HIST_SPL_PIX_CNT 0x1235 	///../ucode/register.h:4260
#define P_VDIN_HIST_SPL_PIX_CNT 		VCBUS_REG_ADDR(VDIN_HIST_SPL_PIX_CNT)
#define VDIN_HIST_CHROMA_SUM 0x1236 	///../ucode/register.h:4264
#define P_VDIN_HIST_CHROMA_SUM 		VCBUS_REG_ADDR(VDIN_HIST_CHROMA_SUM)
#define VDIN_DNLP_HIST00 0x1237 	///../ucode/register.h:4275
#define P_VDIN_DNLP_HIST00 		VCBUS_REG_ADDR(VDIN_DNLP_HIST00)
#define VDIN_DNLP_HIST01 0x1238 	///../ucode/register.h:4276
#define P_VDIN_DNLP_HIST01 		VCBUS_REG_ADDR(VDIN_DNLP_HIST01)
#define VDIN_DNLP_HIST02 0x1239 	///../ucode/register.h:4277
#define P_VDIN_DNLP_HIST02 		VCBUS_REG_ADDR(VDIN_DNLP_HIST02)
#define VDIN_DNLP_HIST03 0x123a 	///../ucode/register.h:4278
#define P_VDIN_DNLP_HIST03 		VCBUS_REG_ADDR(VDIN_DNLP_HIST03)
#define VDIN_DNLP_HIST04 0x123b 	///../ucode/register.h:4279
#define P_VDIN_DNLP_HIST04 		VCBUS_REG_ADDR(VDIN_DNLP_HIST04)
#define VDIN_DNLP_HIST05 0x123c 	///../ucode/register.h:4280
#define P_VDIN_DNLP_HIST05 		VCBUS_REG_ADDR(VDIN_DNLP_HIST05)
#define VDIN_DNLP_HIST06 0x123d 	///../ucode/register.h:4281
#define P_VDIN_DNLP_HIST06 		VCBUS_REG_ADDR(VDIN_DNLP_HIST06)
#define VDIN_DNLP_HIST07 0x123e 	///../ucode/register.h:4282
#define P_VDIN_DNLP_HIST07 		VCBUS_REG_ADDR(VDIN_DNLP_HIST07)
#define VDIN_DNLP_HIST08 0x123f 	///../ucode/register.h:4283
#define P_VDIN_DNLP_HIST08 		VCBUS_REG_ADDR(VDIN_DNLP_HIST08)
#define VDIN_DNLP_HIST09 0x1240 	///../ucode/register.h:4284
#define P_VDIN_DNLP_HIST09 		VCBUS_REG_ADDR(VDIN_DNLP_HIST09)
#define VDIN_DNLP_HIST10 0x1241 	///../ucode/register.h:4285
#define P_VDIN_DNLP_HIST10 		VCBUS_REG_ADDR(VDIN_DNLP_HIST10)
#define VDIN_DNLP_HIST11 0x1242 	///../ucode/register.h:4286
#define P_VDIN_DNLP_HIST11 		VCBUS_REG_ADDR(VDIN_DNLP_HIST11)
#define VDIN_DNLP_HIST12 0x1243 	///../ucode/register.h:4287
#define P_VDIN_DNLP_HIST12 		VCBUS_REG_ADDR(VDIN_DNLP_HIST12)
#define VDIN_DNLP_HIST13 0x1244 	///../ucode/register.h:4288
#define P_VDIN_DNLP_HIST13 		VCBUS_REG_ADDR(VDIN_DNLP_HIST13)
#define VDIN_DNLP_HIST14 0x1245 	///../ucode/register.h:4289
#define P_VDIN_DNLP_HIST14 		VCBUS_REG_ADDR(VDIN_DNLP_HIST14)
#define VDIN_DNLP_HIST15 0x1246 	///../ucode/register.h:4290
#define P_VDIN_DNLP_HIST15 		VCBUS_REG_ADDR(VDIN_DNLP_HIST15)
#define VDIN_DNLP_HIST16 0x1247 	///../ucode/register.h:4291
#define P_VDIN_DNLP_HIST16 		VCBUS_REG_ADDR(VDIN_DNLP_HIST16)
#define VDIN_DNLP_HIST17 0x1248 	///../ucode/register.h:4292
#define P_VDIN_DNLP_HIST17 		VCBUS_REG_ADDR(VDIN_DNLP_HIST17)
#define VDIN_DNLP_HIST18 0x1249 	///../ucode/register.h:4293
#define P_VDIN_DNLP_HIST18 		VCBUS_REG_ADDR(VDIN_DNLP_HIST18)
#define VDIN_DNLP_HIST19 0x124a 	///../ucode/register.h:4294
#define P_VDIN_DNLP_HIST19 		VCBUS_REG_ADDR(VDIN_DNLP_HIST19)
#define VDIN_DNLP_HIST20 0x124b 	///../ucode/register.h:4295
#define P_VDIN_DNLP_HIST20 		VCBUS_REG_ADDR(VDIN_DNLP_HIST20)
#define VDIN_DNLP_HIST21 0x124c 	///../ucode/register.h:4296
#define P_VDIN_DNLP_HIST21 		VCBUS_REG_ADDR(VDIN_DNLP_HIST21)
#define VDIN_DNLP_HIST22 0x124d 	///../ucode/register.h:4297
#define P_VDIN_DNLP_HIST22 		VCBUS_REG_ADDR(VDIN_DNLP_HIST22)
#define VDIN_DNLP_HIST23 0x124e 	///../ucode/register.h:4298
#define P_VDIN_DNLP_HIST23 		VCBUS_REG_ADDR(VDIN_DNLP_HIST23)
#define VDIN_DNLP_HIST24 0x124f 	///../ucode/register.h:4299
#define P_VDIN_DNLP_HIST24 		VCBUS_REG_ADDR(VDIN_DNLP_HIST24)
#define VDIN_DNLP_HIST25 0x1250 	///../ucode/register.h:4300
#define P_VDIN_DNLP_HIST25 		VCBUS_REG_ADDR(VDIN_DNLP_HIST25)
#define VDIN_DNLP_HIST26 0x1251 	///../ucode/register.h:4301
#define P_VDIN_DNLP_HIST26 		VCBUS_REG_ADDR(VDIN_DNLP_HIST26)
#define VDIN_DNLP_HIST27 0x1252 	///../ucode/register.h:4302
#define P_VDIN_DNLP_HIST27 		VCBUS_REG_ADDR(VDIN_DNLP_HIST27)
#define VDIN_DNLP_HIST28 0x1253 	///../ucode/register.h:4303
#define P_VDIN_DNLP_HIST28 		VCBUS_REG_ADDR(VDIN_DNLP_HIST28)
#define VDIN_DNLP_HIST29 0x1254 	///../ucode/register.h:4304
#define P_VDIN_DNLP_HIST29 		VCBUS_REG_ADDR(VDIN_DNLP_HIST29)
#define VDIN_DNLP_HIST30 0x1255 	///../ucode/register.h:4305
#define P_VDIN_DNLP_HIST30 		VCBUS_REG_ADDR(VDIN_DNLP_HIST30)
#define VDIN_DNLP_HIST31 0x1256 	///../ucode/register.h:4306
#define P_VDIN_DNLP_HIST31 		VCBUS_REG_ADDR(VDIN_DNLP_HIST31)
#define VDIN_LDIM_STTS_HIST_REGION_IDX 0x1257 	///../ucode/register.h:4315
#define P_VDIN_LDIM_STTS_HIST_REGION_IDX 		VCBUS_REG_ADDR(VDIN_LDIM_STTS_HIST_REGION_IDX)
#define VDIN_LDIM_STTS_HIST_SET_REGION 0x1258 	///../ucode/register.h:4338
#define P_VDIN_LDIM_STTS_HIST_SET_REGION 		VCBUS_REG_ADDR(VDIN_LDIM_STTS_HIST_SET_REGION)
#define VDIN_LDIM_STTS_HIST_READ_REGION 0x1259 	///../ucode/register.h:4340
#define P_VDIN_LDIM_STTS_HIST_READ_REGION 		VCBUS_REG_ADDR(VDIN_LDIM_STTS_HIST_READ_REGION)
#define VDIN_MEAS_CTRL0 0x125a 	///../ucode/register.h:4347
#define P_VDIN_MEAS_CTRL0 		VCBUS_REG_ADDR(VDIN_MEAS_CTRL0)
#define VDIN_MEAS_VS_COUNT_HI 0x125b 	///../ucode/register.h:4351
#define P_VDIN_MEAS_VS_COUNT_HI 		VCBUS_REG_ADDR(VDIN_MEAS_VS_COUNT_HI)
#define VDIN_MEAS_VS_COUNT_LO 0x125c 	///../ucode/register.h:4354
#define P_VDIN_MEAS_VS_COUNT_LO 		VCBUS_REG_ADDR(VDIN_MEAS_VS_COUNT_LO)
#define VDIN_MEAS_HS_RANGE 0x125d 	///../ucode/register.h:4362
#define P_VDIN_MEAS_HS_RANGE 		VCBUS_REG_ADDR(VDIN_MEAS_HS_RANGE)
#define VDIN_MEAS_HS_COUNT 0x125e 	///../ucode/register.h:4370
#define P_VDIN_MEAS_HS_COUNT 		VCBUS_REG_ADDR(VDIN_MEAS_HS_COUNT)
#define VDIN_BLKBAR_CTRL1 0x125f 	///../ucode/register.h:4373
#define P_VDIN_BLKBAR_CTRL1 		VCBUS_REG_ADDR(VDIN_BLKBAR_CTRL1)
#define VDIN_BLKBAR_CTRL0 0x1260 	///../ucode/register.h:4382
#define P_VDIN_BLKBAR_CTRL0 		VCBUS_REG_ADDR(VDIN_BLKBAR_CTRL0)
#define VDIN_BLKBAR_H_START_END 0x1261 	///../ucode/register.h:4387
#define P_VDIN_BLKBAR_H_START_END 		VCBUS_REG_ADDR(VDIN_BLKBAR_H_START_END)
#define VDIN_BLKBAR_V_START_END 0x1262 	///../ucode/register.h:4392
#define P_VDIN_BLKBAR_V_START_END 		VCBUS_REG_ADDR(VDIN_BLKBAR_V_START_END)
#define VDIN_BLKBAR_CNT_THRESHOLD 0x1263 	///../ucode/register.h:4395
#define P_VDIN_BLKBAR_CNT_THRESHOLD 		VCBUS_REG_ADDR(VDIN_BLKBAR_CNT_THRESHOLD)
#define VDIN_BLKBAR_ROW_TH1_TH2 0x1264 	///../ucode/register.h:4400
#define P_VDIN_BLKBAR_ROW_TH1_TH2 		VCBUS_REG_ADDR(VDIN_BLKBAR_ROW_TH1_TH2)
#define VDIN_BLKBAR_IND_LEFT_START_END 0x1265 	///../ucode/register.h:4406
#define P_VDIN_BLKBAR_IND_LEFT_START_END 		VCBUS_REG_ADDR(VDIN_BLKBAR_IND_LEFT_START_END)
#define VDIN_BLKBAR_IND_RIGHT_START_END 0x1266 	///../ucode/register.h:4412
#define P_VDIN_BLKBAR_IND_RIGHT_START_END 		VCBUS_REG_ADDR(VDIN_BLKBAR_IND_RIGHT_START_END)
#define VDIN_BLKBAR_IND_LEFT1_CNT 0x1267 	///../ucode/register.h:4416
#define P_VDIN_BLKBAR_IND_LEFT1_CNT 		VCBUS_REG_ADDR(VDIN_BLKBAR_IND_LEFT1_CNT)
#define VDIN_BLKBAR_IND_LEFT2_CNT 0x1268 	///../ucode/register.h:4420
#define P_VDIN_BLKBAR_IND_LEFT2_CNT 		VCBUS_REG_ADDR(VDIN_BLKBAR_IND_LEFT2_CNT)
#define VDIN_BLKBAR_IND_RIGHT1_CNT 0x1269 	///../ucode/register.h:4424
#define P_VDIN_BLKBAR_IND_RIGHT1_CNT 		VCBUS_REG_ADDR(VDIN_BLKBAR_IND_RIGHT1_CNT)
#define VDIN_BLKBAR_IND_RIGHT2_CNT 0x126a 	///../ucode/register.h:4428
#define P_VDIN_BLKBAR_IND_RIGHT2_CNT 		VCBUS_REG_ADDR(VDIN_BLKBAR_IND_RIGHT2_CNT)
#define VDIN_BLKBAR_STATUS0 0x126b 	///../ucode/register.h:4435
#define P_VDIN_BLKBAR_STATUS0 		VCBUS_REG_ADDR(VDIN_BLKBAR_STATUS0)
#define VDIN_BLKBAR_STATUS1 0x126c 	///../ucode/register.h:4441
#define P_VDIN_BLKBAR_STATUS1 		VCBUS_REG_ADDR(VDIN_BLKBAR_STATUS1)
#define VDIN_WIN_H_START_END 0x126d 	///../ucode/register.h:4444
#define P_VDIN_WIN_H_START_END 		VCBUS_REG_ADDR(VDIN_WIN_H_START_END)
#define VDIN_WIN_V_START_END 0x126e 	///../ucode/register.h:4447
#define P_VDIN_WIN_V_START_END 		VCBUS_REG_ADDR(VDIN_WIN_V_START_END)
#define VDIN_ASFIFO_CTRL3 0x126f 	///../ucode/register.h:4451
#define P_VDIN_ASFIFO_CTRL3 		VCBUS_REG_ADDR(VDIN_ASFIFO_CTRL3)
#define VDIN0_SCALE_COEF_IDX ((0x00 << 2) + VDIN_SCALE_COEF_IDX )) 	///../ucode/register.h:4454
#define P_VDIN0_SCALE_COEF_IDX 		VCBUS_REG_ADDR(VDIN0_SCALE_COEF_IDX)
#define VDIN0_SCALE_COEF ((0x00 << 2) + VDIN_SCALE_COEF )) 	///../ucode/register.h:4455
#define P_VDIN0_SCALE_COEF 		VCBUS_REG_ADDR(VDIN0_SCALE_COEF)
#define VDIN0_COM_CTRL0 ((0x00 << 2) + VDIN_COM_CTRL0 )) 	///../ucode/register.h:4456
#define P_VDIN0_COM_CTRL0 		VCBUS_REG_ADDR(VDIN0_COM_CTRL0)
#define VDIN0_ACTIVE_MAX_PIX_CNT_STATUS ((0x00 << 2) + VDIN_ACTIVE_MAX_PIX_CNT_STATUS )) 	///../ucode/register.h:4457
#define P_VDIN0_ACTIVE_MAX_PIX_CNT_STATUS 		VCBUS_REG_ADDR(VDIN0_ACTIVE_MAX_PIX_CNT_STATUS)
#define VDIN0_LCNT_STATUS ((0x00 << 2) + VDIN_LCNT_STATUS )) 	///../ucode/register.h:4458
#define P_VDIN0_LCNT_STATUS 		VCBUS_REG_ADDR(VDIN0_LCNT_STATUS)
#define VDIN0_COM_STATUS0 ((0x00 << 2) + VDIN_COM_STATUS0 )) 	///../ucode/register.h:4459
#define P_VDIN0_COM_STATUS0 		VCBUS_REG_ADDR(VDIN0_COM_STATUS0)
#define VDIN0_COM_STATUS1 ((0x00 << 2) + VDIN_COM_STATUS1 )) 	///../ucode/register.h:4460
#define P_VDIN0_COM_STATUS1 		VCBUS_REG_ADDR(VDIN0_COM_STATUS1)
#define VDIN0_LCNT_SHADOW_STATUS ((0x00 << 2) + VDIN_LCNT_SHADOW_STATUS )) 	///../ucode/register.h:4461
#define P_VDIN0_LCNT_SHADOW_STATUS 		VCBUS_REG_ADDR(VDIN0_LCNT_SHADOW_STATUS)
#define VDIN0_ASFIFO_CTRL0 ((0x00 << 2) + VDIN_ASFIFO_CTRL0 )) 	///../ucode/register.h:4462
#define P_VDIN0_ASFIFO_CTRL0 		VCBUS_REG_ADDR(VDIN0_ASFIFO_CTRL0)
#define VDIN0_ASFIFO_CTRL1 ((0x00 << 2) + VDIN_ASFIFO_CTRL1 )) 	///../ucode/register.h:4463
#define P_VDIN0_ASFIFO_CTRL1 		VCBUS_REG_ADDR(VDIN0_ASFIFO_CTRL1)
#define VDIN0_WIDTHM1I_WIDTHM1O ((0x00 << 2) + VDIN_WIDTHM1I_WIDTHM1O )) 	///../ucode/register.h:4464
#define P_VDIN0_WIDTHM1I_WIDTHM1O 		VCBUS_REG_ADDR(VDIN0_WIDTHM1I_WIDTHM1O)
#define VDIN0_SC_MISC_CTRL ((0x00 << 2) + VDIN_SC_MISC_CTRL )) 	///../ucode/register.h:4465
#define P_VDIN0_SC_MISC_CTRL 		VCBUS_REG_ADDR(VDIN0_SC_MISC_CTRL)
#define VDIN0_HSC_PHASE_STEP ((0x00 << 2) + VDIN_HSC_PHASE_STEP )) 	///../ucode/register.h:4466
#define P_VDIN0_HSC_PHASE_STEP 		VCBUS_REG_ADDR(VDIN0_HSC_PHASE_STEP)
#define VDIN0_HSC_INI_CTRL ((0x00 << 2) + VDIN_HSC_INI_CTRL )) 	///../ucode/register.h:4467
#define P_VDIN0_HSC_INI_CTRL 		VCBUS_REG_ADDR(VDIN0_HSC_INI_CTRL)
#define VDIN0_COM_STATUS2 ((0x00 << 2) + VDIN_COM_STATUS2 )) 	///../ucode/register.h:4468
#define P_VDIN0_COM_STATUS2 		VCBUS_REG_ADDR(VDIN0_COM_STATUS2)
#define VDIN0_ASFIFO_CTRL2 ((0x00 << 2) + VDIN_ASFIFO_CTRL2 )) 	///../ucode/register.h:4469
#define P_VDIN0_ASFIFO_CTRL2 		VCBUS_REG_ADDR(VDIN0_ASFIFO_CTRL2)
#define VDIN0_MATRIX_CTRL ((0x00 << 2) + VDIN_MATRIX_CTRL )) 	///../ucode/register.h:4470
#define P_VDIN0_MATRIX_CTRL 		VCBUS_REG_ADDR(VDIN0_MATRIX_CTRL)
#define VDIN0_MATRIX_COEF00_01 ((0x00 << 2) + VDIN_MATRIX_COEF00_01 )) 	///../ucode/register.h:4471
#define P_VDIN0_MATRIX_COEF00_01 		VCBUS_REG_ADDR(VDIN0_MATRIX_COEF00_01)
#define VDIN0_MATRIX_COEF02_10 ((0x00 << 2) + VDIN_MATRIX_COEF02_10 )) 	///../ucode/register.h:4472
#define P_VDIN0_MATRIX_COEF02_10 		VCBUS_REG_ADDR(VDIN0_MATRIX_COEF02_10)
#define VDIN0_MATRIX_COEF11_12 ((0x00 << 2) + VDIN_MATRIX_COEF11_12 )) 	///../ucode/register.h:4473
#define P_VDIN0_MATRIX_COEF11_12 		VCBUS_REG_ADDR(VDIN0_MATRIX_COEF11_12)
#define VDIN0_MATRIX_COEF20_21 ((0x00 << 2) + VDIN_MATRIX_COEF20_21 )) 	///../ucode/register.h:4474
#define P_VDIN0_MATRIX_COEF20_21 		VCBUS_REG_ADDR(VDIN0_MATRIX_COEF20_21)
#define VDIN0_MATRIX_COEF22 ((0x00 << 2) + VDIN_MATRIX_COEF22 )) 	///../ucode/register.h:4475
#define P_VDIN0_MATRIX_COEF22 		VCBUS_REG_ADDR(VDIN0_MATRIX_COEF22)
#define VDIN0_MATRIX_OFFSET0_1 ((0x00 << 2) + VDIN_MATRIX_OFFSET0_1 )) 	///../ucode/register.h:4476
#define P_VDIN0_MATRIX_OFFSET0_1 		VCBUS_REG_ADDR(VDIN0_MATRIX_OFFSET0_1)
#define VDIN0_MATRIX_OFFSET2 ((0x00 << 2) + VDIN_MATRIX_OFFSET2 )) 	///../ucode/register.h:4477
#define P_VDIN0_MATRIX_OFFSET2 		VCBUS_REG_ADDR(VDIN0_MATRIX_OFFSET2)
#define VDIN0_MATRIX_PRE_OFFSET0_1 ((0x00 << 2) + VDIN_MATRIX_PRE_OFFSET0_1 )) 	///../ucode/register.h:4478
#define P_VDIN0_MATRIX_PRE_OFFSET0_1 		VCBUS_REG_ADDR(VDIN0_MATRIX_PRE_OFFSET0_1)
#define VDIN0_MATRIX_PRE_OFFSET2 ((0x00 << 2) + VDIN_MATRIX_PRE_OFFSET2 )) 	///../ucode/register.h:4479
#define P_VDIN0_MATRIX_PRE_OFFSET2 		VCBUS_REG_ADDR(VDIN0_MATRIX_PRE_OFFSET2)
#define VDIN0_LFIFO_CTRL ((0x00 << 2) + VDIN_LFIFO_CTRL )) 	///../ucode/register.h:4480
#define P_VDIN0_LFIFO_CTRL 		VCBUS_REG_ADDR(VDIN0_LFIFO_CTRL)
#define VDIN0_COM_GCLK_CTRL ((0x00 << 2) + VDIN_COM_GCLK_CTRL )) 	///../ucode/register.h:4481
#define P_VDIN0_COM_GCLK_CTRL 		VCBUS_REG_ADDR(VDIN0_COM_GCLK_CTRL)
#define VDIN0_INTF_WIDTHM1 ((0x00 << 2) + VDIN_INTF_WIDTHM1 )) 	///../ucode/register.h:4482
#define P_VDIN0_INTF_WIDTHM1 		VCBUS_REG_ADDR(VDIN0_INTF_WIDTHM1)
#define VDIN0_WR_CTRL2 ((0x00 << 2) + VDIN_WR_CTRL2 )) 	///../ucode/register.h:4483
#define P_VDIN0_WR_CTRL2 		VCBUS_REG_ADDR(VDIN0_WR_CTRL2)
#define VDIN0_WR_CTRL ((0x00 << 2) + VDIN_WR_CTRL )) 	///../ucode/register.h:4484
#define P_VDIN0_WR_CTRL 		VCBUS_REG_ADDR(VDIN0_WR_CTRL)
#define VDIN0_WR_H_START_END ((0x00 << 2) + VDIN_WR_H_START_END )) 	///../ucode/register.h:4485
#define P_VDIN0_WR_H_START_END 		VCBUS_REG_ADDR(VDIN0_WR_H_START_END)
#define VDIN0_WR_V_START_END ((0x00 << 2) + VDIN_WR_V_START_END )) 	///../ucode/register.h:4486
#define P_VDIN0_WR_V_START_END 		VCBUS_REG_ADDR(VDIN0_WR_V_START_END)
#define VDIN0_VSC_PHASE_STEP ((0x00 << 2) + VDIN_VSC_PHASE_STEP )) 	///../ucode/register.h:4487
#define P_VDIN0_VSC_PHASE_STEP 		VCBUS_REG_ADDR(VDIN0_VSC_PHASE_STEP)
#define VDIN0_VSC_INI_CTRL ((0x00 << 2) + VDIN_VSC_INI_CTRL )) 	///../ucode/register.h:4488
#define P_VDIN0_VSC_INI_CTRL 		VCBUS_REG_ADDR(VDIN0_VSC_INI_CTRL)
#define VDIN0_SCIN_HEIGHTM1 ((0x00 << 2) + VDIN_SCIN_HEIGHTM1 )) 	///../ucode/register.h:4489
#define P_VDIN0_SCIN_HEIGHTM1 		VCBUS_REG_ADDR(VDIN0_SCIN_HEIGHTM1)
#define VDIN0_DUMMY_DATA ((0x00 << 2) + VDIN_DUMMY_DATA )) 	///../ucode/register.h:4490
#define P_VDIN0_DUMMY_DATA 		VCBUS_REG_ADDR(VDIN0_DUMMY_DATA)
#define VDIN0_MATRIX_PROBE_COLOR ((0x00 << 2) + VDIN_MATRIX_PROBE_COLOR )) 	///../ucode/register.h:4491
#define P_VDIN0_MATRIX_PROBE_COLOR 		VCBUS_REG_ADDR(VDIN0_MATRIX_PROBE_COLOR)
#define VDIN0_MATRIX_HL_COLOR ((0x00 << 2) + VDIN_MATRIX_HL_COLOR )) 	///../ucode/register.h:4492
#define P_VDIN0_MATRIX_HL_COLOR 		VCBUS_REG_ADDR(VDIN0_MATRIX_HL_COLOR)
#define VDIN0_MATRIX_PROBE_POS ((0x00 << 2) + VDIN_MATRIX_PROBE_POS )) 	///../ucode/register.h:4493
#define P_VDIN0_MATRIX_PROBE_POS 		VCBUS_REG_ADDR(VDIN0_MATRIX_PROBE_POS)
#define VDIN0_CHROMA_ADDR_PORT ((0x00 << 2) + VDIN_CHROMA_ADDR_PORT )) 	///../ucode/register.h:4494
#define P_VDIN0_CHROMA_ADDR_PORT 		VCBUS_REG_ADDR(VDIN0_CHROMA_ADDR_PORT)
#define VDIN0_CHROMA_DATA_PORT ((0x00 << 2) + VDIN_CHROMA_DATA_PORT )) 	///../ucode/register.h:4495
#define P_VDIN0_CHROMA_DATA_PORT 		VCBUS_REG_ADDR(VDIN0_CHROMA_DATA_PORT)
#define VDIN0_CM_BRI_CON_CTRL ((0x00 << 2) + VDIN_CM_BRI_CON_CTRL )) 	///../ucode/register.h:4496
#define P_VDIN0_CM_BRI_CON_CTRL 		VCBUS_REG_ADDR(VDIN0_CM_BRI_CON_CTRL)
#define VDIN0_HIST_CTRL ((0x00 << 2) + VDIN_HIST_CTRL )) 	///../ucode/register.h:4497
#define P_VDIN0_HIST_CTRL 		VCBUS_REG_ADDR(VDIN0_HIST_CTRL)
#define VDIN0_HIST_H_START_END ((0x00 << 2) + VDIN_HIST_H_START_END )) 	///../ucode/register.h:4498
#define P_VDIN0_HIST_H_START_END 		VCBUS_REG_ADDR(VDIN0_HIST_H_START_END)
#define VDIN0_HIST_V_START_END ((0x00 << 2) + VDIN_HIST_V_START_END )) 	///../ucode/register.h:4499
#define P_VDIN0_HIST_V_START_END 		VCBUS_REG_ADDR(VDIN0_HIST_V_START_END)
#define VDIN0_HIST_MAX_MIN ((0x00 << 2) + VDIN_HIST_MAX_MIN )) 	///../ucode/register.h:4500
#define P_VDIN0_HIST_MAX_MIN 		VCBUS_REG_ADDR(VDIN0_HIST_MAX_MIN)
#define VDIN0_HIST_SPL_VAL ((0x00 << 2) + VDIN_HIST_SPL_VAL )) 	///../ucode/register.h:4501
#define P_VDIN0_HIST_SPL_VAL 		VCBUS_REG_ADDR(VDIN0_HIST_SPL_VAL)
#define VDIN0_HIST_SPL_PIX_CNT ((0x00 << 2) + VDIN_HIST_SPL_PIX_CNT )) 	///../ucode/register.h:4502
#define P_VDIN0_HIST_SPL_PIX_CNT 		VCBUS_REG_ADDR(VDIN0_HIST_SPL_PIX_CNT)
#define VDIN0_HIST_CHROMA_SUM ((0x00 << 2) + VDIN_HIST_CHROMA_SUM )) 	///../ucode/register.h:4503
#define P_VDIN0_HIST_CHROMA_SUM 		VCBUS_REG_ADDR(VDIN0_HIST_CHROMA_SUM)
#define VDIN0_DNLP_HIST00 ((0x00 << 2) + VDIN_DNLP_HIST00 )) 	///../ucode/register.h:4504
#define P_VDIN0_DNLP_HIST00 		VCBUS_REG_ADDR(VDIN0_DNLP_HIST00)
#define VDIN0_DNLP_HIST01 ((0x00 << 2) + VDIN_DNLP_HIST01 )) 	///../ucode/register.h:4505
#define P_VDIN0_DNLP_HIST01 		VCBUS_REG_ADDR(VDIN0_DNLP_HIST01)
#define VDIN0_DNLP_HIST02 ((0x00 << 2) + VDIN_DNLP_HIST02 )) 	///../ucode/register.h:4506
#define P_VDIN0_DNLP_HIST02 		VCBUS_REG_ADDR(VDIN0_DNLP_HIST02)
#define VDIN0_DNLP_HIST03 ((0x00 << 2) + VDIN_DNLP_HIST03 )) 	///../ucode/register.h:4507
#define P_VDIN0_DNLP_HIST03 		VCBUS_REG_ADDR(VDIN0_DNLP_HIST03)
#define VDIN0_DNLP_HIST04 ((0x00 << 2) + VDIN_DNLP_HIST04 )) 	///../ucode/register.h:4508
#define P_VDIN0_DNLP_HIST04 		VCBUS_REG_ADDR(VDIN0_DNLP_HIST04)
#define VDIN0_DNLP_HIST05 ((0x00 << 2) + VDIN_DNLP_HIST05 )) 	///../ucode/register.h:4509
#define P_VDIN0_DNLP_HIST05 		VCBUS_REG_ADDR(VDIN0_DNLP_HIST05)
#define VDIN0_DNLP_HIST06 ((0x00 << 2) + VDIN_DNLP_HIST06 )) 	///../ucode/register.h:4510
#define P_VDIN0_DNLP_HIST06 		VCBUS_REG_ADDR(VDIN0_DNLP_HIST06)
#define VDIN0_DNLP_HIST07 ((0x00 << 2) + VDIN_DNLP_HIST07 )) 	///../ucode/register.h:4511
#define P_VDIN0_DNLP_HIST07 		VCBUS_REG_ADDR(VDIN0_DNLP_HIST07)
#define VDIN0_DNLP_HIST08 ((0x00 << 2) + VDIN_DNLP_HIST08 )) 	///../ucode/register.h:4512
#define P_VDIN0_DNLP_HIST08 		VCBUS_REG_ADDR(VDIN0_DNLP_HIST08)
#define VDIN0_DNLP_HIST09 ((0x00 << 2) + VDIN_DNLP_HIST09 )) 	///../ucode/register.h:4513
#define P_VDIN0_DNLP_HIST09 		VCBUS_REG_ADDR(VDIN0_DNLP_HIST09)
#define VDIN0_DNLP_HIST10 ((0x00 << 2) + VDIN_DNLP_HIST10 )) 	///../ucode/register.h:4514
#define P_VDIN0_DNLP_HIST10 		VCBUS_REG_ADDR(VDIN0_DNLP_HIST10)
#define VDIN0_DNLP_HIST11 ((0x00 << 2) + VDIN_DNLP_HIST11 )) 	///../ucode/register.h:4515
#define P_VDIN0_DNLP_HIST11 		VCBUS_REG_ADDR(VDIN0_DNLP_HIST11)
#define VDIN0_DNLP_HIST12 ((0x00 << 2) + VDIN_DNLP_HIST12 )) 	///../ucode/register.h:4516
#define P_VDIN0_DNLP_HIST12 		VCBUS_REG_ADDR(VDIN0_DNLP_HIST12)
#define VDIN0_DNLP_HIST13 ((0x00 << 2) + VDIN_DNLP_HIST13 )) 	///../ucode/register.h:4517
#define P_VDIN0_DNLP_HIST13 		VCBUS_REG_ADDR(VDIN0_DNLP_HIST13)
#define VDIN0_DNLP_HIST14 ((0x00 << 2) + VDIN_DNLP_HIST14 )) 	///../ucode/register.h:4518
#define P_VDIN0_DNLP_HIST14 		VCBUS_REG_ADDR(VDIN0_DNLP_HIST14)
#define VDIN0_DNLP_HIST15 ((0x00 << 2) + VDIN_DNLP_HIST15 )) 	///../ucode/register.h:4519
#define P_VDIN0_DNLP_HIST15 		VCBUS_REG_ADDR(VDIN0_DNLP_HIST15)
#define VDIN0_DNLP_HIST16 ((0x00 << 2) + VDIN_DNLP_HIST16 )) 	///../ucode/register.h:4520
#define P_VDIN0_DNLP_HIST16 		VCBUS_REG_ADDR(VDIN0_DNLP_HIST16)
#define VDIN0_DNLP_HIST17 ((0x00 << 2) + VDIN_DNLP_HIST17 )) 	///../ucode/register.h:4521
#define P_VDIN0_DNLP_HIST17 		VCBUS_REG_ADDR(VDIN0_DNLP_HIST17)
#define VDIN0_DNLP_HIST18 ((0x00 << 2) + VDIN_DNLP_HIST18 )) 	///../ucode/register.h:4522
#define P_VDIN0_DNLP_HIST18 		VCBUS_REG_ADDR(VDIN0_DNLP_HIST18)
#define VDIN0_DNLP_HIST19 ((0x00 << 2) + VDIN_DNLP_HIST19 )) 	///../ucode/register.h:4523
#define P_VDIN0_DNLP_HIST19 		VCBUS_REG_ADDR(VDIN0_DNLP_HIST19)
#define VDIN0_DNLP_HIST20 ((0x00 << 2) + VDIN_DNLP_HIST20 )) 	///../ucode/register.h:4524
#define P_VDIN0_DNLP_HIST20 		VCBUS_REG_ADDR(VDIN0_DNLP_HIST20)
#define VDIN0_DNLP_HIST21 ((0x00 << 2) + VDIN_DNLP_HIST21 )) 	///../ucode/register.h:4525
#define P_VDIN0_DNLP_HIST21 		VCBUS_REG_ADDR(VDIN0_DNLP_HIST21)
#define VDIN0_DNLP_HIST22 ((0x00 << 2) + VDIN_DNLP_HIST22 )) 	///../ucode/register.h:4526
#define P_VDIN0_DNLP_HIST22 		VCBUS_REG_ADDR(VDIN0_DNLP_HIST22)
#define VDIN0_DNLP_HIST23 ((0x00 << 2) + VDIN_DNLP_HIST23 )) 	///../ucode/register.h:4527
#define P_VDIN0_DNLP_HIST23 		VCBUS_REG_ADDR(VDIN0_DNLP_HIST23)
#define VDIN0_DNLP_HIST24 ((0x00 << 2) + VDIN_DNLP_HIST24 )) 	///../ucode/register.h:4528
#define P_VDIN0_DNLP_HIST24 		VCBUS_REG_ADDR(VDIN0_DNLP_HIST24)
#define VDIN0_DNLP_HIST25 ((0x00 << 2) + VDIN_DNLP_HIST25 )) 	///../ucode/register.h:4529
#define P_VDIN0_DNLP_HIST25 		VCBUS_REG_ADDR(VDIN0_DNLP_HIST25)
#define VDIN0_DNLP_HIST26 ((0x00 << 2) + VDIN_DNLP_HIST26 )) 	///../ucode/register.h:4530
#define P_VDIN0_DNLP_HIST26 		VCBUS_REG_ADDR(VDIN0_DNLP_HIST26)
#define VDIN0_DNLP_HIST27 ((0x00 << 2) + VDIN_DNLP_HIST27 )) 	///../ucode/register.h:4531
#define P_VDIN0_DNLP_HIST27 		VCBUS_REG_ADDR(VDIN0_DNLP_HIST27)
#define VDIN0_DNLP_HIST28 ((0x00 << 2) + VDIN_DNLP_HIST28 )) 	///../ucode/register.h:4532
#define P_VDIN0_DNLP_HIST28 		VCBUS_REG_ADDR(VDIN0_DNLP_HIST28)
#define VDIN0_DNLP_HIST29 ((0x00 << 2) + VDIN_DNLP_HIST29 )) 	///../ucode/register.h:4533
#define P_VDIN0_DNLP_HIST29 		VCBUS_REG_ADDR(VDIN0_DNLP_HIST29)
#define VDIN0_DNLP_HIST30 ((0x00 << 2) + VDIN_DNLP_HIST30 )) 	///../ucode/register.h:4534
#define P_VDIN0_DNLP_HIST30 		VCBUS_REG_ADDR(VDIN0_DNLP_HIST30)
#define VDIN0_DNLP_HIST31 ((0x00 << 2) + VDIN_DNLP_HIST31 )) 	///../ucode/register.h:4535
#define P_VDIN0_DNLP_HIST31 		VCBUS_REG_ADDR(VDIN0_DNLP_HIST31)
#define VDIN0_LDIM_STTS_HIST_REGION_IDX ((0x00 << 2) + VDIN_LDIM_STTS_HIST_REGION_IDX )) 	///../ucode/register.h:4536
#define P_VDIN0_LDIM_STTS_HIST_REGION_IDX 		VCBUS_REG_ADDR(VDIN0_LDIM_STTS_HIST_REGION_IDX)
#define VDIN0_LDIM_STTS_HIST_SET_REGION ((0x00 << 2) + VDIN_LDIM_STTS_HIST_SET_REGION )) 	///../ucode/register.h:4537
#define P_VDIN0_LDIM_STTS_HIST_SET_REGION 		VCBUS_REG_ADDR(VDIN0_LDIM_STTS_HIST_SET_REGION)
#define VDIN0_LDIM_STTS_HIST_READ_REGION ((0x00 << 2) + VDIN_LDIM_STTS_HIST_READ_REGION )) 	///../ucode/register.h:4538
#define P_VDIN0_LDIM_STTS_HIST_READ_REGION 		VCBUS_REG_ADDR(VDIN0_LDIM_STTS_HIST_READ_REGION)
#define VDIN0_MEAS_CTRL0 ((0x00 << 2) + VDIN_MEAS_CTRL0 )) 	///../ucode/register.h:4539
#define P_VDIN0_MEAS_CTRL0 		VCBUS_REG_ADDR(VDIN0_MEAS_CTRL0)
#define VDIN0_MEAS_VS_COUNT_HI ((0x00 << 2) + VDIN_MEAS_VS_COUNT_HI )) 	///../ucode/register.h:4540
#define P_VDIN0_MEAS_VS_COUNT_HI 		VCBUS_REG_ADDR(VDIN0_MEAS_VS_COUNT_HI)
#define VDIN0_MEAS_VS_COUNT_LO ((0x00 << 2) + VDIN_MEAS_VS_COUNT_LO )) 	///../ucode/register.h:4541
#define P_VDIN0_MEAS_VS_COUNT_LO 		VCBUS_REG_ADDR(VDIN0_MEAS_VS_COUNT_LO)
#define VDIN0_MEAS_HS_RANGE ((0x00 << 2) + VDIN_MEAS_HS_RANGE )) 	///../ucode/register.h:4542
#define P_VDIN0_MEAS_HS_RANGE 		VCBUS_REG_ADDR(VDIN0_MEAS_HS_RANGE)
#define VDIN0_MEAS_HS_COUNT ((0x00 << 2) + VDIN_MEAS_HS_COUNT )) 	///../ucode/register.h:4543
#define P_VDIN0_MEAS_HS_COUNT 		VCBUS_REG_ADDR(VDIN0_MEAS_HS_COUNT)
#define VDIN0_BLKBAR_CTRL1 ((0x00 << 2) + VDIN_BLKBAR_CTRL1 )) 	///../ucode/register.h:4544
#define P_VDIN0_BLKBAR_CTRL1 		VCBUS_REG_ADDR(VDIN0_BLKBAR_CTRL1)
#define VDIN0_BLKBAR_CTRL0 ((0x00 << 2) + VDIN_BLKBAR_CTRL0 )) 	///../ucode/register.h:4545
#define P_VDIN0_BLKBAR_CTRL0 		VCBUS_REG_ADDR(VDIN0_BLKBAR_CTRL0)
#define VDIN0_BLKBAR_H_START_END ((0x00 << 2) + VDIN_BLKBAR_H_START_END )) 	///../ucode/register.h:4546
#define P_VDIN0_BLKBAR_H_START_END 		VCBUS_REG_ADDR(VDIN0_BLKBAR_H_START_END)
#define VDIN0_BLKBAR_V_START_END ((0x00 << 2) + VDIN_BLKBAR_V_START_END )) 	///../ucode/register.h:4547
#define P_VDIN0_BLKBAR_V_START_END 		VCBUS_REG_ADDR(VDIN0_BLKBAR_V_START_END)
#define VDIN0_BLKBAR_CNT_THRESHOLD ((0x00 << 2) + VDIN_BLKBAR_CNT_THRESHOLD )) 	///../ucode/register.h:4548
#define P_VDIN0_BLKBAR_CNT_THRESHOLD 		VCBUS_REG_ADDR(VDIN0_BLKBAR_CNT_THRESHOLD)
#define VDIN0_BLKBAR_ROW_TH1_TH2 ((0x00 << 2) + VDIN_BLKBAR_ROW_TH1_TH2 )) 	///../ucode/register.h:4549
#define P_VDIN0_BLKBAR_ROW_TH1_TH2 		VCBUS_REG_ADDR(VDIN0_BLKBAR_ROW_TH1_TH2)
#define VDIN0_BLKBAR_IND_LEFT_START_END ((0x00 << 2) + VDIN_BLKBAR_IND_LEFT_START_END )) 	///../ucode/register.h:4550
#define P_VDIN0_BLKBAR_IND_LEFT_START_END 		VCBUS_REG_ADDR(VDIN0_BLKBAR_IND_LEFT_START_END)
#define VDIN0_BLKBAR_IND_RIGHT_START_END ((0x00 << 2) + VDIN_BLKBAR_IND_RIGHT_START_END )) 	///../ucode/register.h:4551
#define P_VDIN0_BLKBAR_IND_RIGHT_START_END 		VCBUS_REG_ADDR(VDIN0_BLKBAR_IND_RIGHT_START_END)
#define VDIN0_BLKBAR_IND_LEFT1_CNT ((0x00 << 2) + VDIN_BLKBAR_IND_LEFT1_CNT )) 	///../ucode/register.h:4552
#define P_VDIN0_BLKBAR_IND_LEFT1_CNT 		VCBUS_REG_ADDR(VDIN0_BLKBAR_IND_LEFT1_CNT)
#define VDIN0_BLKBAR_IND_LEFT2_CNT ((0x00 << 2) + VDIN_BLKBAR_IND_LEFT2_CNT )) 	///../ucode/register.h:4553
#define P_VDIN0_BLKBAR_IND_LEFT2_CNT 		VCBUS_REG_ADDR(VDIN0_BLKBAR_IND_LEFT2_CNT)
#define VDIN0_BLKBAR_IND_RIGHT1_CNT ((0x00 << 2) + VDIN_BLKBAR_IND_RIGHT1_CNT )) 	///../ucode/register.h:4554
#define P_VDIN0_BLKBAR_IND_RIGHT1_CNT 		VCBUS_REG_ADDR(VDIN0_BLKBAR_IND_RIGHT1_CNT)
#define VDIN0_BLKBAR_IND_RIGHT2_CNT ((0x00 << 2) + VDIN_BLKBAR_IND_RIGHT2_CNT )) 	///../ucode/register.h:4555
#define P_VDIN0_BLKBAR_IND_RIGHT2_CNT 		VCBUS_REG_ADDR(VDIN0_BLKBAR_IND_RIGHT2_CNT)
#define VDIN0_BLKBAR_STATUS0 ((0x00 << 2) + VDIN_BLKBAR_STATUS0 )) 	///../ucode/register.h:4556
#define P_VDIN0_BLKBAR_STATUS0 		VCBUS_REG_ADDR(VDIN0_BLKBAR_STATUS0)
#define VDIN0_BLKBAR_STATUS1 ((0x00 << 2) + VDIN_BLKBAR_STATUS1 )) 	///../ucode/register.h:4557
#define P_VDIN0_BLKBAR_STATUS1 		VCBUS_REG_ADDR(VDIN0_BLKBAR_STATUS1)
#define VDIN0_WIN_H_START_END ((0x00 << 2) + VDIN_WIN_H_START_END )) 	///../ucode/register.h:4558
#define P_VDIN0_WIN_H_START_END 		VCBUS_REG_ADDR(VDIN0_WIN_H_START_END)
#define VDIN0_WIN_V_START_END ((0x00 << 2) + VDIN_WIN_V_START_END )) 	///../ucode/register.h:4559
#define P_VDIN0_WIN_V_START_END 		VCBUS_REG_ADDR(VDIN0_WIN_V_START_END)
#define VDIN0_ASFIFO_CTRL3 ((0x00 << 2) + VDIN_ASFIFO_CTRL3 )) 	///../ucode/register.h:4560
#define P_VDIN0_ASFIFO_CTRL3 		VCBUS_REG_ADDR(VDIN0_ASFIFO_CTRL3)
#define VDIN1_SCALE_COEF_IDX ((0x70 << 2) + VDIN_SCALE_COEF_IDX )) 	///../ucode/register.h:4563
#define P_VDIN1_SCALE_COEF_IDX 		VCBUS_REG_ADDR(VDIN1_SCALE_COEF_IDX)
#define VDIN1_SCALE_COEF ((0x70 << 2) + VDIN_SCALE_COEF )) 	///../ucode/register.h:4564
#define P_VDIN1_SCALE_COEF 		VCBUS_REG_ADDR(VDIN1_SCALE_COEF)
#define VDIN1_COM_CTRL0 ((0x70 << 2) + VDIN_COM_CTRL0 )) 	///../ucode/register.h:4565
#define P_VDIN1_COM_CTRL0 		VCBUS_REG_ADDR(VDIN1_COM_CTRL0)
#define VDIN1_ACTIVE_MAX_PIX_CNT_STATUS ((0x70 << 2) + VDIN_ACTIVE_MAX_PIX_CNT_STATUS )) 	///../ucode/register.h:4566
#define P_VDIN1_ACTIVE_MAX_PIX_CNT_STATUS 		VCBUS_REG_ADDR(VDIN1_ACTIVE_MAX_PIX_CNT_STATUS)
#define VDIN1_LCNT_STATUS ((0x70 << 2) + VDIN_LCNT_STATUS )) 	///../ucode/register.h:4567
#define P_VDIN1_LCNT_STATUS 		VCBUS_REG_ADDR(VDIN1_LCNT_STATUS)
#define VDIN1_COM_STATUS0 ((0x70 << 2) + VDIN_COM_STATUS0 )) 	///../ucode/register.h:4568
#define P_VDIN1_COM_STATUS0 		VCBUS_REG_ADDR(VDIN1_COM_STATUS0)
#define VDIN1_COM_STATUS1 ((0x70 << 2) + VDIN_COM_STATUS1 )) 	///../ucode/register.h:4569
#define P_VDIN1_COM_STATUS1 		VCBUS_REG_ADDR(VDIN1_COM_STATUS1)
#define VDIN1_LCNT_SHADOW_STATUS ((0x70 << 2) + VDIN_LCNT_SHADOW_STATUS )) 	///../ucode/register.h:4570
#define P_VDIN1_LCNT_SHADOW_STATUS 		VCBUS_REG_ADDR(VDIN1_LCNT_SHADOW_STATUS)
#define VDIN1_ASFIFO_CTRL0 ((0x70 << 2) + VDIN_ASFIFO_CTRL0 )) 	///../ucode/register.h:4571
#define P_VDIN1_ASFIFO_CTRL0 		VCBUS_REG_ADDR(VDIN1_ASFIFO_CTRL0)
#define VDIN1_ASFIFO_CTRL1 ((0x70 << 2) + VDIN_ASFIFO_CTRL1 )) 	///../ucode/register.h:4572
#define P_VDIN1_ASFIFO_CTRL1 		VCBUS_REG_ADDR(VDIN1_ASFIFO_CTRL1)
#define VDIN1_WIDTHM1I_WIDTHM1O ((0x70 << 2) + VDIN_WIDTHM1I_WIDTHM1O )) 	///../ucode/register.h:4573
#define P_VDIN1_WIDTHM1I_WIDTHM1O 		VCBUS_REG_ADDR(VDIN1_WIDTHM1I_WIDTHM1O)
#define VDIN1_SC_MISC_CTRL ((0x70 << 2) + VDIN_SC_MISC_CTRL )) 	///../ucode/register.h:4574
#define P_VDIN1_SC_MISC_CTRL 		VCBUS_REG_ADDR(VDIN1_SC_MISC_CTRL)
#define VDIN1_HSC_PHASE_STEP ((0x70 << 2) + VDIN_HSC_PHASE_STEP )) 	///../ucode/register.h:4575
#define P_VDIN1_HSC_PHASE_STEP 		VCBUS_REG_ADDR(VDIN1_HSC_PHASE_STEP)
#define VDIN1_HSC_INI_CTRL ((0x70 << 2) + VDIN_HSC_INI_CTRL )) 	///../ucode/register.h:4576
#define P_VDIN1_HSC_INI_CTRL 		VCBUS_REG_ADDR(VDIN1_HSC_INI_CTRL)
#define VDIN1_COM_STATUS2 ((0x70 << 2) + VDIN_COM_STATUS2 )) 	///../ucode/register.h:4577
#define P_VDIN1_COM_STATUS2 		VCBUS_REG_ADDR(VDIN1_COM_STATUS2)
#define VDIN1_ASFIFO_CTRL2 ((0x70 << 2) + VDIN_ASFIFO_CTRL2 )) 	///../ucode/register.h:4578
#define P_VDIN1_ASFIFO_CTRL2 		VCBUS_REG_ADDR(VDIN1_ASFIFO_CTRL2)
#define VDIN1_MATRIX_CTRL ((0x70 << 2) + VDIN_MATRIX_CTRL )) 	///../ucode/register.h:4579
#define P_VDIN1_MATRIX_CTRL 		VCBUS_REG_ADDR(VDIN1_MATRIX_CTRL)
#define VDIN1_MATRIX_COEF00_01 ((0x70 << 2) + VDIN_MATRIX_COEF00_01 )) 	///../ucode/register.h:4580
#define P_VDIN1_MATRIX_COEF00_01 		VCBUS_REG_ADDR(VDIN1_MATRIX_COEF00_01)
#define VDIN1_MATRIX_COEF02_10 ((0x70 << 2) + VDIN_MATRIX_COEF02_10 )) 	///../ucode/register.h:4581
#define P_VDIN1_MATRIX_COEF02_10 		VCBUS_REG_ADDR(VDIN1_MATRIX_COEF02_10)
#define VDIN1_MATRIX_COEF11_12 ((0x70 << 2) + VDIN_MATRIX_COEF11_12 )) 	///../ucode/register.h:4582
#define P_VDIN1_MATRIX_COEF11_12 		VCBUS_REG_ADDR(VDIN1_MATRIX_COEF11_12)
#define VDIN1_MATRIX_COEF20_21 ((0x70 << 2) + VDIN_MATRIX_COEF20_21 )) 	///../ucode/register.h:4583
#define P_VDIN1_MATRIX_COEF20_21 		VCBUS_REG_ADDR(VDIN1_MATRIX_COEF20_21)
#define VDIN1_MATRIX_COEF22 ((0x70 << 2) + VDIN_MATRIX_COEF22 )) 	///../ucode/register.h:4584
#define P_VDIN1_MATRIX_COEF22 		VCBUS_REG_ADDR(VDIN1_MATRIX_COEF22)
#define VDIN1_MATRIX_OFFSET0_1 ((0x70 << 2) + VDIN_MATRIX_OFFSET0_1 )) 	///../ucode/register.h:4585
#define P_VDIN1_MATRIX_OFFSET0_1 		VCBUS_REG_ADDR(VDIN1_MATRIX_OFFSET0_1)
#define VDIN1_MATRIX_OFFSET2 ((0x70 << 2) + VDIN_MATRIX_OFFSET2 )) 	///../ucode/register.h:4586
#define P_VDIN1_MATRIX_OFFSET2 		VCBUS_REG_ADDR(VDIN1_MATRIX_OFFSET2)
#define VDIN1_MATRIX_PRE_OFFSET0_1 ((0x70 << 2) + VDIN_MATRIX_PRE_OFFSET0_1 )) 	///../ucode/register.h:4587
#define P_VDIN1_MATRIX_PRE_OFFSET0_1 		VCBUS_REG_ADDR(VDIN1_MATRIX_PRE_OFFSET0_1)
#define VDIN1_MATRIX_PRE_OFFSET2 ((0x70 << 2) + VDIN_MATRIX_PRE_OFFSET2 )) 	///../ucode/register.h:4588
#define P_VDIN1_MATRIX_PRE_OFFSET2 		VCBUS_REG_ADDR(VDIN1_MATRIX_PRE_OFFSET2)
#define VDIN1_LFIFO_CTRL ((0x70 << 2) + VDIN_LFIFO_CTRL )) 	///../ucode/register.h:4589
#define P_VDIN1_LFIFO_CTRL 		VCBUS_REG_ADDR(VDIN1_LFIFO_CTRL)
#define VDIN1_COM_GCLK_CTRL ((0x70 << 2) + VDIN_COM_GCLK_CTRL )) 	///../ucode/register.h:4590
#define P_VDIN1_COM_GCLK_CTRL 		VCBUS_REG_ADDR(VDIN1_COM_GCLK_CTRL)
#define VDIN1_INTF_WIDTHM1 ((0x70 << 2) + VDIN_INTF_WIDTHM1 )) 	///../ucode/register.h:4591
#define P_VDIN1_INTF_WIDTHM1 		VCBUS_REG_ADDR(VDIN1_INTF_WIDTHM1)
#define VDIN1_WR_CTRL2 ((0x70 << 2) + VDIN_WR_CTRL2 )) 	///../ucode/register.h:4592
#define P_VDIN1_WR_CTRL2 		VCBUS_REG_ADDR(VDIN1_WR_CTRL2)
#define VDIN1_WR_CTRL ((0x70 << 2) + VDIN_WR_CTRL )) 	///../ucode/register.h:4593
#define P_VDIN1_WR_CTRL 		VCBUS_REG_ADDR(VDIN1_WR_CTRL)
#define VDIN1_WR_H_START_END ((0x70 << 2) + VDIN_WR_H_START_END )) 	///../ucode/register.h:4594
#define P_VDIN1_WR_H_START_END 		VCBUS_REG_ADDR(VDIN1_WR_H_START_END)
#define VDIN1_WR_V_START_END ((0x70 << 2) + VDIN_WR_V_START_END )) 	///../ucode/register.h:4595
#define P_VDIN1_WR_V_START_END 		VCBUS_REG_ADDR(VDIN1_WR_V_START_END)
#define VDIN1_VSC_PHASE_STEP ((0x70 << 2) + VDIN_VSC_PHASE_STEP )) 	///../ucode/register.h:4596
#define P_VDIN1_VSC_PHASE_STEP 		VCBUS_REG_ADDR(VDIN1_VSC_PHASE_STEP)
#define VDIN1_VSC_INI_CTRL ((0x70 << 2) + VDIN_VSC_INI_CTRL )) 	///../ucode/register.h:4597
#define P_VDIN1_VSC_INI_CTRL 		VCBUS_REG_ADDR(VDIN1_VSC_INI_CTRL)
#define VDIN1_SCIN_HEIGHTM1 ((0x70 << 2) + VDIN_SCIN_HEIGHTM1 )) 	///../ucode/register.h:4598
#define P_VDIN1_SCIN_HEIGHTM1 		VCBUS_REG_ADDR(VDIN1_SCIN_HEIGHTM1)
#define VDIN1_DUMMY_DATA ((0x70 << 2) + VDIN_DUMMY_DATA )) 	///../ucode/register.h:4599
#define P_VDIN1_DUMMY_DATA 		VCBUS_REG_ADDR(VDIN1_DUMMY_DATA)
#define VDIN1_MATRIX_PROBE_COLOR ((0x70 << 2) + VDIN_MATRIX_PROBE_COLOR )) 	///../ucode/register.h:4600
#define P_VDIN1_MATRIX_PROBE_COLOR 		VCBUS_REG_ADDR(VDIN1_MATRIX_PROBE_COLOR)
#define VDIN1_MATRIX_HL_COLOR ((0x70 << 2) + VDIN_MATRIX_HL_COLOR )) 	///../ucode/register.h:4601
#define P_VDIN1_MATRIX_HL_COLOR 		VCBUS_REG_ADDR(VDIN1_MATRIX_HL_COLOR)
#define VDIN1_MATRIX_PROBE_POS ((0x70 << 2) + VDIN_MATRIX_PROBE_POS )) 	///../ucode/register.h:4602
#define P_VDIN1_MATRIX_PROBE_POS 		VCBUS_REG_ADDR(VDIN1_MATRIX_PROBE_POS)
#define VDIN1_CHROMA_ADDR_PORT ((0x70 << 2) + VDIN_CHROMA_ADDR_PORT )) 	///../ucode/register.h:4603
#define P_VDIN1_CHROMA_ADDR_PORT 		VCBUS_REG_ADDR(VDIN1_CHROMA_ADDR_PORT)
#define VDIN1_CHROMA_DATA_PORT ((0x70 << 2) + VDIN_CHROMA_DATA_PORT )) 	///../ucode/register.h:4604
#define P_VDIN1_CHROMA_DATA_PORT 		VCBUS_REG_ADDR(VDIN1_CHROMA_DATA_PORT)
#define VDIN1_CM_BRI_CON_CTRL ((0x70 << 2) + VDIN_CM_BRI_CON_CTRL )) 	///../ucode/register.h:4605
#define P_VDIN1_CM_BRI_CON_CTRL 		VCBUS_REG_ADDR(VDIN1_CM_BRI_CON_CTRL)
#define VDIN1_HIST_CTRL ((0x70 << 2) + VDIN_HIST_CTRL )) 	///../ucode/register.h:4606
#define P_VDIN1_HIST_CTRL 		VCBUS_REG_ADDR(VDIN1_HIST_CTRL)
#define VDIN1_HIST_H_START_END ((0x70 << 2) + VDIN_HIST_H_START_END )) 	///../ucode/register.h:4607
#define P_VDIN1_HIST_H_START_END 		VCBUS_REG_ADDR(VDIN1_HIST_H_START_END)
#define VDIN1_HIST_V_START_END ((0x70 << 2) + VDIN_HIST_V_START_END )) 	///../ucode/register.h:4608
#define P_VDIN1_HIST_V_START_END 		VCBUS_REG_ADDR(VDIN1_HIST_V_START_END)
#define VDIN1_HIST_MAX_MIN ((0x70 << 2) + VDIN_HIST_MAX_MIN )) 	///../ucode/register.h:4609
#define P_VDIN1_HIST_MAX_MIN 		VCBUS_REG_ADDR(VDIN1_HIST_MAX_MIN)
#define VDIN1_HIST_SPL_VAL ((0x70 << 2) + VDIN_HIST_SPL_VAL )) 	///../ucode/register.h:4610
#define P_VDIN1_HIST_SPL_VAL 		VCBUS_REG_ADDR(VDIN1_HIST_SPL_VAL)
#define VDIN1_HIST_SPL_PIX_CNT ((0x70 << 2) + VDIN_HIST_SPL_PIX_CNT )) 	///../ucode/register.h:4611
#define P_VDIN1_HIST_SPL_PIX_CNT 		VCBUS_REG_ADDR(VDIN1_HIST_SPL_PIX_CNT)
#define VDIN1_HIST_CHROMA_SUM ((0x70 << 2) + VDIN_HIST_CHROMA_SUM )) 	///../ucode/register.h:4612
#define P_VDIN1_HIST_CHROMA_SUM 		VCBUS_REG_ADDR(VDIN1_HIST_CHROMA_SUM)
#define VDIN1_DNLP_HIST00 ((0x70 << 2) + VDIN_DNLP_HIST00 )) 	///../ucode/register.h:4613
#define P_VDIN1_DNLP_HIST00 		VCBUS_REG_ADDR(VDIN1_DNLP_HIST00)
#define VDIN1_DNLP_HIST01 ((0x70 << 2) + VDIN_DNLP_HIST01 )) 	///../ucode/register.h:4614
#define P_VDIN1_DNLP_HIST01 		VCBUS_REG_ADDR(VDIN1_DNLP_HIST01)
#define VDIN1_DNLP_HIST02 ((0x70 << 2) + VDIN_DNLP_HIST02 )) 	///../ucode/register.h:4615
#define P_VDIN1_DNLP_HIST02 		VCBUS_REG_ADDR(VDIN1_DNLP_HIST02)
#define VDIN1_DNLP_HIST03 ((0x70 << 2) + VDIN_DNLP_HIST03 )) 	///../ucode/register.h:4616
#define P_VDIN1_DNLP_HIST03 		VCBUS_REG_ADDR(VDIN1_DNLP_HIST03)
#define VDIN1_DNLP_HIST04 ((0x70 << 2) + VDIN_DNLP_HIST04 )) 	///../ucode/register.h:4617
#define P_VDIN1_DNLP_HIST04 		VCBUS_REG_ADDR(VDIN1_DNLP_HIST04)
#define VDIN1_DNLP_HIST05 ((0x70 << 2) + VDIN_DNLP_HIST05 )) 	///../ucode/register.h:4618
#define P_VDIN1_DNLP_HIST05 		VCBUS_REG_ADDR(VDIN1_DNLP_HIST05)
#define VDIN1_DNLP_HIST06 ((0x70 << 2) + VDIN_DNLP_HIST06 )) 	///../ucode/register.h:4619
#define P_VDIN1_DNLP_HIST06 		VCBUS_REG_ADDR(VDIN1_DNLP_HIST06)
#define VDIN1_DNLP_HIST07 ((0x70 << 2) + VDIN_DNLP_HIST07 )) 	///../ucode/register.h:4620
#define P_VDIN1_DNLP_HIST07 		VCBUS_REG_ADDR(VDIN1_DNLP_HIST07)
#define VDIN1_DNLP_HIST08 ((0x70 << 2) + VDIN_DNLP_HIST08 )) 	///../ucode/register.h:4621
#define P_VDIN1_DNLP_HIST08 		VCBUS_REG_ADDR(VDIN1_DNLP_HIST08)
#define VDIN1_DNLP_HIST09 ((0x70 << 2) + VDIN_DNLP_HIST09 )) 	///../ucode/register.h:4622
#define P_VDIN1_DNLP_HIST09 		VCBUS_REG_ADDR(VDIN1_DNLP_HIST09)
#define VDIN1_DNLP_HIST10 ((0x70 << 2) + VDIN_DNLP_HIST10 )) 	///../ucode/register.h:4623
#define P_VDIN1_DNLP_HIST10 		VCBUS_REG_ADDR(VDIN1_DNLP_HIST10)
#define VDIN1_DNLP_HIST11 ((0x70 << 2) + VDIN_DNLP_HIST11 )) 	///../ucode/register.h:4624
#define P_VDIN1_DNLP_HIST11 		VCBUS_REG_ADDR(VDIN1_DNLP_HIST11)
#define VDIN1_DNLP_HIST12 ((0x70 << 2) + VDIN_DNLP_HIST12 )) 	///../ucode/register.h:4625
#define P_VDIN1_DNLP_HIST12 		VCBUS_REG_ADDR(VDIN1_DNLP_HIST12)
#define VDIN1_DNLP_HIST13 ((0x70 << 2) + VDIN_DNLP_HIST13 )) 	///../ucode/register.h:4626
#define P_VDIN1_DNLP_HIST13 		VCBUS_REG_ADDR(VDIN1_DNLP_HIST13)
#define VDIN1_DNLP_HIST14 ((0x70 << 2) + VDIN_DNLP_HIST14 )) 	///../ucode/register.h:4627
#define P_VDIN1_DNLP_HIST14 		VCBUS_REG_ADDR(VDIN1_DNLP_HIST14)
#define VDIN1_DNLP_HIST15 ((0x70 << 2) + VDIN_DNLP_HIST15 )) 	///../ucode/register.h:4628
#define P_VDIN1_DNLP_HIST15 		VCBUS_REG_ADDR(VDIN1_DNLP_HIST15)
#define VDIN1_DNLP_HIST16 ((0x70 << 2) + VDIN_DNLP_HIST16 )) 	///../ucode/register.h:4629
#define P_VDIN1_DNLP_HIST16 		VCBUS_REG_ADDR(VDIN1_DNLP_HIST16)
#define VDIN1_DNLP_HIST17 ((0x70 << 2) + VDIN_DNLP_HIST17 )) 	///../ucode/register.h:4630
#define P_VDIN1_DNLP_HIST17 		VCBUS_REG_ADDR(VDIN1_DNLP_HIST17)
#define VDIN1_DNLP_HIST18 ((0x70 << 2) + VDIN_DNLP_HIST18 )) 	///../ucode/register.h:4631
#define P_VDIN1_DNLP_HIST18 		VCBUS_REG_ADDR(VDIN1_DNLP_HIST18)
#define VDIN1_DNLP_HIST19 ((0x70 << 2) + VDIN_DNLP_HIST19 )) 	///../ucode/register.h:4632
#define P_VDIN1_DNLP_HIST19 		VCBUS_REG_ADDR(VDIN1_DNLP_HIST19)
#define VDIN1_DNLP_HIST20 ((0x70 << 2) + VDIN_DNLP_HIST20 )) 	///../ucode/register.h:4633
#define P_VDIN1_DNLP_HIST20 		VCBUS_REG_ADDR(VDIN1_DNLP_HIST20)
#define VDIN1_DNLP_HIST21 ((0x70 << 2) + VDIN_DNLP_HIST21 )) 	///../ucode/register.h:4634
#define P_VDIN1_DNLP_HIST21 		VCBUS_REG_ADDR(VDIN1_DNLP_HIST21)
#define VDIN1_DNLP_HIST22 ((0x70 << 2) + VDIN_DNLP_HIST22 )) 	///../ucode/register.h:4635
#define P_VDIN1_DNLP_HIST22 		VCBUS_REG_ADDR(VDIN1_DNLP_HIST22)
#define VDIN1_DNLP_HIST23 ((0x70 << 2) + VDIN_DNLP_HIST23 )) 	///../ucode/register.h:4636
#define P_VDIN1_DNLP_HIST23 		VCBUS_REG_ADDR(VDIN1_DNLP_HIST23)
#define VDIN1_DNLP_HIST24 ((0x70 << 2) + VDIN_DNLP_HIST24 )) 	///../ucode/register.h:4637
#define P_VDIN1_DNLP_HIST24 		VCBUS_REG_ADDR(VDIN1_DNLP_HIST24)
#define VDIN1_DNLP_HIST25 ((0x70 << 2) + VDIN_DNLP_HIST25 )) 	///../ucode/register.h:4638
#define P_VDIN1_DNLP_HIST25 		VCBUS_REG_ADDR(VDIN1_DNLP_HIST25)
#define VDIN1_DNLP_HIST26 ((0x70 << 2) + VDIN_DNLP_HIST26 )) 	///../ucode/register.h:4639
#define P_VDIN1_DNLP_HIST26 		VCBUS_REG_ADDR(VDIN1_DNLP_HIST26)
#define VDIN1_DNLP_HIST27 ((0x70 << 2) + VDIN_DNLP_HIST27 )) 	///../ucode/register.h:4640
#define P_VDIN1_DNLP_HIST27 		VCBUS_REG_ADDR(VDIN1_DNLP_HIST27)
#define VDIN1_DNLP_HIST28 ((0x70 << 2) + VDIN_DNLP_HIST28 )) 	///../ucode/register.h:4641
#define P_VDIN1_DNLP_HIST28 		VCBUS_REG_ADDR(VDIN1_DNLP_HIST28)
#define VDIN1_DNLP_HIST29 ((0x70 << 2) + VDIN_DNLP_HIST29 )) 	///../ucode/register.h:4642
#define P_VDIN1_DNLP_HIST29 		VCBUS_REG_ADDR(VDIN1_DNLP_HIST29)
#define VDIN1_DNLP_HIST30 ((0x70 << 2) + VDIN_DNLP_HIST30 )) 	///../ucode/register.h:4643
#define P_VDIN1_DNLP_HIST30 		VCBUS_REG_ADDR(VDIN1_DNLP_HIST30)
#define VDIN1_DNLP_HIST31 ((0x70 << 2) + VDIN_DNLP_HIST31 )) 	///../ucode/register.h:4644
#define P_VDIN1_DNLP_HIST31 		VCBUS_REG_ADDR(VDIN1_DNLP_HIST31)
#define VDIN1_LDIM_STTS_HIST_REGION_IDX ((0x70 << 2) + VDIN_LDIM_STTS_HIST_REGION_IDX )) 	///../ucode/register.h:4645
#define P_VDIN1_LDIM_STTS_HIST_REGION_IDX 		VCBUS_REG_ADDR(VDIN1_LDIM_STTS_HIST_REGION_IDX)
#define VDIN1_LDIM_STTS_HIST_SET_REGION ((0x70 << 2) + VDIN_LDIM_STTS_HIST_SET_REGION )) 	///../ucode/register.h:4646
#define P_VDIN1_LDIM_STTS_HIST_SET_REGION 		VCBUS_REG_ADDR(VDIN1_LDIM_STTS_HIST_SET_REGION)
#define VDIN1_LDIM_STTS_HIST_READ_REGION ((0x70 << 2) + VDIN_LDIM_STTS_HIST_READ_REGION )) 	///../ucode/register.h:4647
#define P_VDIN1_LDIM_STTS_HIST_READ_REGION 		VCBUS_REG_ADDR(VDIN1_LDIM_STTS_HIST_READ_REGION)
#define VDIN1_MEAS_CTRL0 ((0x70 << 2) + VDIN_MEAS_CTRL0 )) 	///../ucode/register.h:4648
#define P_VDIN1_MEAS_CTRL0 		VCBUS_REG_ADDR(VDIN1_MEAS_CTRL0)
#define VDIN1_MEAS_VS_COUNT_HI ((0x70 << 2) + VDIN_MEAS_VS_COUNT_HI )) 	///../ucode/register.h:4649
#define P_VDIN1_MEAS_VS_COUNT_HI 		VCBUS_REG_ADDR(VDIN1_MEAS_VS_COUNT_HI)
#define VDIN1_MEAS_VS_COUNT_LO ((0x70 << 2) + VDIN_MEAS_VS_COUNT_LO )) 	///../ucode/register.h:4650
#define P_VDIN1_MEAS_VS_COUNT_LO 		VCBUS_REG_ADDR(VDIN1_MEAS_VS_COUNT_LO)
#define VDIN1_MEAS_HS_RANGE ((0x70 << 2) + VDIN_MEAS_HS_RANGE )) 	///../ucode/register.h:4651
#define P_VDIN1_MEAS_HS_RANGE 		VCBUS_REG_ADDR(VDIN1_MEAS_HS_RANGE)
#define VDIN1_MEAS_HS_COUNT ((0x70 << 2) + VDIN_MEAS_HS_COUNT )) 	///../ucode/register.h:4652
#define P_VDIN1_MEAS_HS_COUNT 		VCBUS_REG_ADDR(VDIN1_MEAS_HS_COUNT)
#define VDIN1_BLKBAR_CTRL1 ((0x70 << 2) + VDIN_BLKBAR_CTRL1 )) 	///../ucode/register.h:4653
#define P_VDIN1_BLKBAR_CTRL1 		VCBUS_REG_ADDR(VDIN1_BLKBAR_CTRL1)
#define VDIN1_BLKBAR_CTRL0 ((0x70 << 2) + VDIN_BLKBAR_CTRL0 )) 	///../ucode/register.h:4654
#define P_VDIN1_BLKBAR_CTRL0 		VCBUS_REG_ADDR(VDIN1_BLKBAR_CTRL0)
#define VDIN1_BLKBAR_H_START_END ((0x70 << 2) + VDIN_BLKBAR_H_START_END )) 	///../ucode/register.h:4655
#define P_VDIN1_BLKBAR_H_START_END 		VCBUS_REG_ADDR(VDIN1_BLKBAR_H_START_END)
#define VDIN1_BLKBAR_V_START_END ((0x70 << 2) + VDIN_BLKBAR_V_START_END )) 	///../ucode/register.h:4656
#define P_VDIN1_BLKBAR_V_START_END 		VCBUS_REG_ADDR(VDIN1_BLKBAR_V_START_END)
#define VDIN1_BLKBAR_CNT_THRESHOLD ((0x70 << 2) + VDIN_BLKBAR_CNT_THRESHOLD )) 	///../ucode/register.h:4657
#define P_VDIN1_BLKBAR_CNT_THRESHOLD 		VCBUS_REG_ADDR(VDIN1_BLKBAR_CNT_THRESHOLD)
#define VDIN1_BLKBAR_ROW_TH1_TH2 ((0x70 << 2) + VDIN_BLKBAR_ROW_TH1_TH2 )) 	///../ucode/register.h:4658
#define P_VDIN1_BLKBAR_ROW_TH1_TH2 		VCBUS_REG_ADDR(VDIN1_BLKBAR_ROW_TH1_TH2)
#define VDIN1_BLKBAR_IND_LEFT_START_END ((0x70 << 2) + VDIN_BLKBAR_IND_LEFT_START_END )) 	///../ucode/register.h:4659
#define P_VDIN1_BLKBAR_IND_LEFT_START_END 		VCBUS_REG_ADDR(VDIN1_BLKBAR_IND_LEFT_START_END)
#define VDIN1_BLKBAR_IND_RIGHT_START_END ((0x70 << 2) + VDIN_BLKBAR_IND_RIGHT_START_END )) 	///../ucode/register.h:4660
#define P_VDIN1_BLKBAR_IND_RIGHT_START_END 		VCBUS_REG_ADDR(VDIN1_BLKBAR_IND_RIGHT_START_END)
#define VDIN1_BLKBAR_IND_LEFT1_CNT ((0x70 << 2) + VDIN_BLKBAR_IND_LEFT1_CNT )) 	///../ucode/register.h:4661
#define P_VDIN1_BLKBAR_IND_LEFT1_CNT 		VCBUS_REG_ADDR(VDIN1_BLKBAR_IND_LEFT1_CNT)
#define VDIN1_BLKBAR_IND_LEFT2_CNT ((0x70 << 2) + VDIN_BLKBAR_IND_LEFT2_CNT )) 	///../ucode/register.h:4662
#define P_VDIN1_BLKBAR_IND_LEFT2_CNT 		VCBUS_REG_ADDR(VDIN1_BLKBAR_IND_LEFT2_CNT)
#define VDIN1_BLKBAR_IND_RIGHT1_CNT ((0x70 << 2) + VDIN_BLKBAR_IND_RIGHT1_CNT )) 	///../ucode/register.h:4663
#define P_VDIN1_BLKBAR_IND_RIGHT1_CNT 		VCBUS_REG_ADDR(VDIN1_BLKBAR_IND_RIGHT1_CNT)
#define VDIN1_BLKBAR_IND_RIGHT2_CNT ((0x70 << 2) + VDIN_BLKBAR_IND_RIGHT2_CNT )) 	///../ucode/register.h:4664
#define P_VDIN1_BLKBAR_IND_RIGHT2_CNT 		VCBUS_REG_ADDR(VDIN1_BLKBAR_IND_RIGHT2_CNT)
#define VDIN1_BLKBAR_STATUS0 ((0x70 << 2) + VDIN_BLKBAR_STATUS0 )) 	///../ucode/register.h:4665
#define P_VDIN1_BLKBAR_STATUS0 		VCBUS_REG_ADDR(VDIN1_BLKBAR_STATUS0)
#define VDIN1_BLKBAR_STATUS1 ((0x70 << 2) + VDIN_BLKBAR_STATUS1 )) 	///../ucode/register.h:4666
#define P_VDIN1_BLKBAR_STATUS1 		VCBUS_REG_ADDR(VDIN1_BLKBAR_STATUS1)
#define VDIN1_WIN_H_START_END ((0x70 << 2) + VDIN_WIN_H_START_END )) 	///../ucode/register.h:4667
#define P_VDIN1_WIN_H_START_END 		VCBUS_REG_ADDR(VDIN1_WIN_H_START_END)
#define VDIN1_WIN_V_START_END ((0x70 << 2) + VDIN_WIN_V_START_END )) 	///../ucode/register.h:4668
#define P_VDIN1_WIN_V_START_END 		VCBUS_REG_ADDR(VDIN1_WIN_V_START_END)
#define VDIN1_ASFIFO_CTRL3 ((0x70 << 2) + VDIN_ASFIFO_CTRL3 )) 	///../ucode/register.h:4669
#define P_VDIN1_ASFIFO_CTRL3 		VCBUS_REG_ADDR(VDIN1_ASFIFO_CTRL3)
#define VPP_DUMMY_DATA 0x1d00 	///../ucode/register.h:4689
#define P_VPP_DUMMY_DATA 		VCBUS_REG_ADDR(VPP_DUMMY_DATA)
#define VPP_LINE_IN_LENGTH 0x1d01 	///../ucode/register.h:4691
#define P_VPP_LINE_IN_LENGTH 		VCBUS_REG_ADDR(VPP_LINE_IN_LENGTH)
#define VPP_PIC_IN_HEIGHT 0x1d02 	///../ucode/register.h:4693
#define P_VPP_PIC_IN_HEIGHT 		VCBUS_REG_ADDR(VPP_PIC_IN_HEIGHT)
#define VPP_SCALE_COEF_IDX 0x1d03 	///../ucode/register.h:4704
#define P_VPP_SCALE_COEF_IDX 		VCBUS_REG_ADDR(VPP_SCALE_COEF_IDX)
#define VPP_SCALE_COEF 0x1d04 	///../ucode/register.h:4706
#define P_VPP_SCALE_COEF 		VCBUS_REG_ADDR(VPP_SCALE_COEF)
#define VPP_VSC_REGION12_STARTP 0x1d05 	///../ucode/register.h:4742
#define P_VPP_VSC_REGION12_STARTP 		VCBUS_REG_ADDR(VPP_VSC_REGION12_STARTP)
#define VPP_VSC_REGION34_STARTP 0x1d06 	///../ucode/register.h:4745
#define P_VPP_VSC_REGION34_STARTP 		VCBUS_REG_ADDR(VPP_VSC_REGION34_STARTP)
#define VPP_VSC_REGION4_ENDP 0x1d07 	///../ucode/register.h:4746
#define P_VPP_VSC_REGION4_ENDP 		VCBUS_REG_ADDR(VPP_VSC_REGION4_ENDP)
#define VPP_VSC_START_PHASE_STEP 0x1d08 	///../ucode/register.h:4750
#define P_VPP_VSC_START_PHASE_STEP 		VCBUS_REG_ADDR(VPP_VSC_START_PHASE_STEP)
#define VPP_VSC_REGION0_PHASE_SLOPE 0x1d09 	///../ucode/register.h:4752
#define P_VPP_VSC_REGION0_PHASE_SLOPE 		VCBUS_REG_ADDR(VPP_VSC_REGION0_PHASE_SLOPE)
#define VPP_VSC_REGION1_PHASE_SLOPE 0x1d0a 	///../ucode/register.h:4754
#define P_VPP_VSC_REGION1_PHASE_SLOPE 		VCBUS_REG_ADDR(VPP_VSC_REGION1_PHASE_SLOPE)
#define VPP_VSC_REGION3_PHASE_SLOPE 0x1d0b 	///../ucode/register.h:4756
#define P_VPP_VSC_REGION3_PHASE_SLOPE 		VCBUS_REG_ADDR(VPP_VSC_REGION3_PHASE_SLOPE)
#define VPP_VSC_REGION4_PHASE_SLOPE 0x1d0c 	///../ucode/register.h:4758
#define P_VPP_VSC_REGION4_PHASE_SLOPE 		VCBUS_REG_ADDR(VPP_VSC_REGION4_PHASE_SLOPE)
#define VPP_VSC_PHASE_CTRL 0x1d0d 	///../ucode/register.h:4769
#define P_VPP_VSC_PHASE_CTRL 		VCBUS_REG_ADDR(VPP_VSC_PHASE_CTRL)
#define VPP_VSC_INI_PHASE 0x1d0e 	///../ucode/register.h:4772
#define P_VPP_VSC_INI_PHASE 		VCBUS_REG_ADDR(VPP_VSC_INI_PHASE)
#define VPP_HSC_REGION12_STARTP 0x1d10 	///../ucode/register.h:4775
#define P_VPP_HSC_REGION12_STARTP 		VCBUS_REG_ADDR(VPP_HSC_REGION12_STARTP)
#define VPP_HSC_REGION34_STARTP 0x1d11 	///../ucode/register.h:4778
#define P_VPP_HSC_REGION34_STARTP 		VCBUS_REG_ADDR(VPP_HSC_REGION34_STARTP)
#define VPP_HSC_REGION4_ENDP 0x1d12 	///../ucode/register.h:4779
#define P_VPP_HSC_REGION4_ENDP 		VCBUS_REG_ADDR(VPP_HSC_REGION4_ENDP)
#define VPP_HSC_START_PHASE_STEP 0x1d13 	///../ucode/register.h:4783
#define P_VPP_HSC_START_PHASE_STEP 		VCBUS_REG_ADDR(VPP_HSC_START_PHASE_STEP)
#define VPP_HSC_REGION0_PHASE_SLOPE 0x1d14 	///../ucode/register.h:4785
#define P_VPP_HSC_REGION0_PHASE_SLOPE 		VCBUS_REG_ADDR(VPP_HSC_REGION0_PHASE_SLOPE)
#define VPP_HSC_REGION1_PHASE_SLOPE 0x1d15 	///../ucode/register.h:4787
#define P_VPP_HSC_REGION1_PHASE_SLOPE 		VCBUS_REG_ADDR(VPP_HSC_REGION1_PHASE_SLOPE)
#define VPP_HSC_REGION3_PHASE_SLOPE 0x1d16 	///../ucode/register.h:4789
#define P_VPP_HSC_REGION3_PHASE_SLOPE 		VCBUS_REG_ADDR(VPP_HSC_REGION3_PHASE_SLOPE)
#define VPP_HSC_REGION4_PHASE_SLOPE 0x1d17 	///../ucode/register.h:4791
#define P_VPP_HSC_REGION4_PHASE_SLOPE 		VCBUS_REG_ADDR(VPP_HSC_REGION4_PHASE_SLOPE)
#define VPP_HSC_PHASE_CTRL 0x1d18 	///../ucode/register.h:4795
#define P_VPP_HSC_PHASE_CTRL 		VCBUS_REG_ADDR(VPP_HSC_PHASE_CTRL)
#define VPP_SC_MISC 0x1d19 	///../ucode/register.h:4810
#define P_VPP_SC_MISC 		VCBUS_REG_ADDR(VPP_SC_MISC)
#define VPP_PREBLEND_VD1_H_START_END 0x1d1a 	///../ucode/register.h:4814
#define P_VPP_PREBLEND_VD1_H_START_END 		VCBUS_REG_ADDR(VPP_PREBLEND_VD1_H_START_END)
#define VPP_PREBLEND_VD1_V_START_END 0x1d1b 	///../ucode/register.h:4818
#define P_VPP_PREBLEND_VD1_V_START_END 		VCBUS_REG_ADDR(VPP_PREBLEND_VD1_V_START_END)
#define VPP_POSTBLEND_VD1_H_START_END 0x1d1c 	///../ucode/register.h:4822
#define P_VPP_POSTBLEND_VD1_H_START_END 		VCBUS_REG_ADDR(VPP_POSTBLEND_VD1_H_START_END)
#define VPP_POSTBLEND_VD1_V_START_END 0x1d1d 	///../ucode/register.h:4826
#define P_VPP_POSTBLEND_VD1_V_START_END 		VCBUS_REG_ADDR(VPP_POSTBLEND_VD1_V_START_END)
#define VPP_BLEND_VD2_H_START_END 0x1d1e 	///../ucode/register.h:4830
#define P_VPP_BLEND_VD2_H_START_END 		VCBUS_REG_ADDR(VPP_BLEND_VD2_H_START_END)
#define VPP_BLEND_VD2_V_START_END 0x1d1f 	///../ucode/register.h:4834
#define P_VPP_BLEND_VD2_V_START_END 		VCBUS_REG_ADDR(VPP_BLEND_VD2_V_START_END)
#define VPP_PREBLEND_H_SIZE 0x1d20 	///../ucode/register.h:4836
#define P_VPP_PREBLEND_H_SIZE 		VCBUS_REG_ADDR(VPP_PREBLEND_H_SIZE)
#define VPP_POSTBLEND_H_SIZE 0x1d21 	///../ucode/register.h:4838
#define P_VPP_POSTBLEND_H_SIZE 		VCBUS_REG_ADDR(VPP_POSTBLEND_H_SIZE)
#define VPP_HOLD_LINES 0x1d22 	///../ucode/register.h:4844
#define P_VPP_HOLD_LINES 		VCBUS_REG_ADDR(VPP_HOLD_LINES)
#define VPP_BLEND_ONECOLOR_CTRL 0x1d23 	///../ucode/register.h:4850
#define P_VPP_BLEND_ONECOLOR_CTRL 		VCBUS_REG_ADDR(VPP_BLEND_ONECOLOR_CTRL)
#define VPP_PREBLEND_CURRENT_XY 0x1d24 	///../ucode/register.h:4854
#define P_VPP_PREBLEND_CURRENT_XY 		VCBUS_REG_ADDR(VPP_PREBLEND_CURRENT_XY)
#define VPP_POSTBLEND_CURRENT_XY 0x1d25 	///../ucode/register.h:4858
#define P_VPP_POSTBLEND_CURRENT_XY 		VCBUS_REG_ADDR(VPP_POSTBLEND_CURRENT_XY)
#define VPP_MISC 0x1d26 	///../ucode/register.h:4883
#define P_VPP_MISC 		VCBUS_REG_ADDR(VPP_MISC)
#define VPP_OFIFO_SIZE 0x1d27 	///../ucode/register.h:4892
#define P_VPP_OFIFO_SIZE 		VCBUS_REG_ADDR(VPP_OFIFO_SIZE)
#define VPP_FIFO_STATUS 0x1d28 	///../ucode/register.h:4897
#define P_VPP_FIFO_STATUS 		VCBUS_REG_ADDR(VPP_FIFO_STATUS)
#define VPP_SMOKE_CTRL 0x1d29 	///../ucode/register.h:4904
#define P_VPP_SMOKE_CTRL 		VCBUS_REG_ADDR(VPP_SMOKE_CTRL)
#define VPP_SMOKE1_VAL 0x1d2a 	///../ucode/register.h:4913
#define P_VPP_SMOKE1_VAL 		VCBUS_REG_ADDR(VPP_SMOKE1_VAL)
#define VPP_SMOKE2_VAL 0x1d2b 	///../ucode/register.h:4914
#define P_VPP_SMOKE2_VAL 		VCBUS_REG_ADDR(VPP_SMOKE2_VAL)
#define VPP_SMOKE3_VAL 0x1d2c 	///../ucode/register.h:4915
#define P_VPP_SMOKE3_VAL 		VCBUS_REG_ADDR(VPP_SMOKE3_VAL)
#define VPP_SMOKE1_H_START_END 0x1d2d 	///../ucode/register.h:4918
#define P_VPP_SMOKE1_H_START_END 		VCBUS_REG_ADDR(VPP_SMOKE1_H_START_END)
#define VPP_SMOKE1_V_START_END 0x1d2e 	///../ucode/register.h:4921
#define P_VPP_SMOKE1_V_START_END 		VCBUS_REG_ADDR(VPP_SMOKE1_V_START_END)
#define VPP_SMOKE2_H_START_END 0x1d2f 	///../ucode/register.h:4924
#define P_VPP_SMOKE2_H_START_END 		VCBUS_REG_ADDR(VPP_SMOKE2_H_START_END)
#define VPP_SMOKE2_V_START_END 0x1d30 	///../ucode/register.h:4927
#define P_VPP_SMOKE2_V_START_END 		VCBUS_REG_ADDR(VPP_SMOKE2_V_START_END)
#define VPP_SMOKE3_H_START_END 0x1d31 	///../ucode/register.h:4930
#define P_VPP_SMOKE3_H_START_END 		VCBUS_REG_ADDR(VPP_SMOKE3_H_START_END)
#define VPP_SMOKE3_V_START_END 0x1d32 	///../ucode/register.h:4933
#define P_VPP_SMOKE3_V_START_END 		VCBUS_REG_ADDR(VPP_SMOKE3_V_START_END)
#define VPP_SCO_FIFO_CTRL 0x1d33 	///../ucode/register.h:4936
#define P_VPP_SCO_FIFO_CTRL 		VCBUS_REG_ADDR(VPP_SCO_FIFO_CTRL)
#define VPP_HSC_PHASE_CTRL1 0x1d34 	///../ucode/register.h:4944
#define P_VPP_HSC_PHASE_CTRL1 		VCBUS_REG_ADDR(VPP_HSC_PHASE_CTRL1)
#define VPP_HSC_INI_PAT_CTRL 0x1d35 	///../ucode/register.h:4952
#define P_VPP_HSC_INI_PAT_CTRL 		VCBUS_REG_ADDR(VPP_HSC_INI_PAT_CTRL)
#define VPP_VADJ_CTRL 0x1d40 	///../ucode/register.h:4957
#define P_VPP_VADJ_CTRL 		VCBUS_REG_ADDR(VPP_VADJ_CTRL)
#define VPP_VADJ1_Y 0x1d41 	///../ucode/register.h:4960
#define P_VPP_VADJ1_Y 		VCBUS_REG_ADDR(VPP_VADJ1_Y)
#define VPP_VADJ1_MA_MB 0x1d42 	///../ucode/register.h:4964
#define P_VPP_VADJ1_MA_MB 		VCBUS_REG_ADDR(VPP_VADJ1_MA_MB)
#define VPP_VADJ1_MC_MD 0x1d43 	///../ucode/register.h:4965
#define P_VPP_VADJ1_MC_MD 		VCBUS_REG_ADDR(VPP_VADJ1_MC_MD)
#define VPP_VADJ2_Y 0x1d44 	///../ucode/register.h:4968
#define P_VPP_VADJ2_Y 		VCBUS_REG_ADDR(VPP_VADJ2_Y)
#define VPP_VADJ2_MA_MB 0x1d45 	///../ucode/register.h:4972
#define P_VPP_VADJ2_MA_MB 		VCBUS_REG_ADDR(VPP_VADJ2_MA_MB)
#define VPP_VADJ2_MC_MD 0x1d46 	///../ucode/register.h:4973
#define P_VPP_VADJ2_MC_MD 		VCBUS_REG_ADDR(VPP_VADJ2_MC_MD)
#define VPP_HSHARP_CTRL 0x1d50 	///../ucode/register.h:4977
#define P_VPP_HSHARP_CTRL 		VCBUS_REG_ADDR(VPP_HSHARP_CTRL)
#define VPP_HSHARP_LUMA_THRESH01 0x1d51 	///../ucode/register.h:4981
#define P_VPP_HSHARP_LUMA_THRESH01 		VCBUS_REG_ADDR(VPP_HSHARP_LUMA_THRESH01)
#define VPP_HSHARP_LUMA_THRESH23 0x1d52 	///../ucode/register.h:4985
#define P_VPP_HSHARP_LUMA_THRESH23 		VCBUS_REG_ADDR(VPP_HSHARP_LUMA_THRESH23)
#define VPP_HSHARP_CHROMA_THRESH01 0x1d53 	///../ucode/register.h:4988
#define P_VPP_HSHARP_CHROMA_THRESH01 		VCBUS_REG_ADDR(VPP_HSHARP_CHROMA_THRESH01)
#define VPP_HSHARP_CHROMA_THRESH23 0x1d54 	///../ucode/register.h:4991
#define P_VPP_HSHARP_CHROMA_THRESH23 		VCBUS_REG_ADDR(VPP_HSHARP_CHROMA_THRESH23)
#define VPP_HSHARP_LUMA_GAIN 0x1d55 	///../ucode/register.h:4995
#define P_VPP_HSHARP_LUMA_GAIN 		VCBUS_REG_ADDR(VPP_HSHARP_LUMA_GAIN)
#define VPP_HSHARP_CHROMA_GAIN 0x1d56 	///../ucode/register.h:5000
#define P_VPP_HSHARP_CHROMA_GAIN 		VCBUS_REG_ADDR(VPP_HSHARP_CHROMA_GAIN)
#define VPP_MATRIX_PROBE_COLOR 0x1d5c 	///../ucode/register.h:5006
#define P_VPP_MATRIX_PROBE_COLOR 		VCBUS_REG_ADDR(VPP_MATRIX_PROBE_COLOR)
#define VPP_MATRIX_HL_COLOR 0x1d5d 	///../ucode/register.h:5010
#define P_VPP_MATRIX_HL_COLOR 		VCBUS_REG_ADDR(VPP_MATRIX_HL_COLOR)
#define VPP_MATRIX_PROBE_POS 0x1d5e 	///../ucode/register.h:5013
#define P_VPP_MATRIX_PROBE_POS 		VCBUS_REG_ADDR(VPP_MATRIX_PROBE_POS)
#define VPP_MATRIX_CTRL 0x1d5f 	///../ucode/register.h:5023
#define P_VPP_MATRIX_CTRL 		VCBUS_REG_ADDR(VPP_MATRIX_CTRL)
#define VPP_MATRIX_COEF00_01 0x1d60 	///../ucode/register.h:5026
#define P_VPP_MATRIX_COEF00_01 		VCBUS_REG_ADDR(VPP_MATRIX_COEF00_01)
#define VPP_MATRIX_COEF02_10 0x1d61 	///../ucode/register.h:5029
#define P_VPP_MATRIX_COEF02_10 		VCBUS_REG_ADDR(VPP_MATRIX_COEF02_10)
#define VPP_MATRIX_COEF11_12 0x1d62 	///../ucode/register.h:5032
#define P_VPP_MATRIX_COEF11_12 		VCBUS_REG_ADDR(VPP_MATRIX_COEF11_12)
#define VPP_MATRIX_COEF20_21 0x1d63 	///../ucode/register.h:5035
#define P_VPP_MATRIX_COEF20_21 		VCBUS_REG_ADDR(VPP_MATRIX_COEF20_21)
#define VPP_MATRIX_COEF22 0x1d64 	///../ucode/register.h:5036
#define P_VPP_MATRIX_COEF22 		VCBUS_REG_ADDR(VPP_MATRIX_COEF22)
#define VPP_MATRIX_OFFSET0_1 0x1d65 	///../ucode/register.h:5039
#define P_VPP_MATRIX_OFFSET0_1 		VCBUS_REG_ADDR(VPP_MATRIX_OFFSET0_1)
#define VPP_MATRIX_OFFSET2 0x1d66 	///../ucode/register.h:5041
#define P_VPP_MATRIX_OFFSET2 		VCBUS_REG_ADDR(VPP_MATRIX_OFFSET2)
#define VPP_MATRIX_PRE_OFFSET0_1 0x1d67 	///../ucode/register.h:5044
#define P_VPP_MATRIX_PRE_OFFSET0_1 		VCBUS_REG_ADDR(VPP_MATRIX_PRE_OFFSET0_1)
#define VPP_MATRIX_PRE_OFFSET2 0x1d68 	///../ucode/register.h:5046
#define P_VPP_MATRIX_PRE_OFFSET2 		VCBUS_REG_ADDR(VPP_MATRIX_PRE_OFFSET2)
#define VPP_DUMMY_DATA1 0x1d69 	///../ucode/register.h:5051
#define P_VPP_DUMMY_DATA1 		VCBUS_REG_ADDR(VPP_DUMMY_DATA1)
#define VPP_GAINOFF_CTRL0 0x1d6a 	///../ucode/register.h:5055
#define P_VPP_GAINOFF_CTRL0 		VCBUS_REG_ADDR(VPP_GAINOFF_CTRL0)
#define VPP_GAINOFF_CTRL1 0x1d6b 	///../ucode/register.h:5058
#define P_VPP_GAINOFF_CTRL1 		VCBUS_REG_ADDR(VPP_GAINOFF_CTRL1)
#define VPP_GAINOFF_CTRL2 0x1d6c 	///../ucode/register.h:5061
#define P_VPP_GAINOFF_CTRL2 		VCBUS_REG_ADDR(VPP_GAINOFF_CTRL2)
#define VPP_GAINOFF_CTRL3 0x1d6d 	///../ucode/register.h:5064
#define P_VPP_GAINOFF_CTRL3 		VCBUS_REG_ADDR(VPP_GAINOFF_CTRL3)
#define VPP_GAINOFF_CTRL4 0x1d6e 	///../ucode/register.h:5066
#define P_VPP_GAINOFF_CTRL4 		VCBUS_REG_ADDR(VPP_GAINOFF_CTRL4)
#define VPP_CHROMA_ADDR_PORT 0x1d70 	///../ucode/register.h:5088
#define P_VPP_CHROMA_ADDR_PORT 		VCBUS_REG_ADDR(VPP_CHROMA_ADDR_PORT)
#define VPP_CHROMA_DATA_PORT 0x1d71 	///../ucode/register.h:5089
#define P_VPP_CHROMA_DATA_PORT 		VCBUS_REG_ADDR(VPP_CHROMA_DATA_PORT)
#define VPP_GCLK_CTRL0 0x1d72 	///../ucode/register.h:5666
#define P_VPP_GCLK_CTRL0 		VCBUS_REG_ADDR(VPP_GCLK_CTRL0)
#define VPP_GCLK_CTRL1 0x1d73 	///../ucode/register.h:5669
#define P_VPP_GCLK_CTRL1 		VCBUS_REG_ADDR(VPP_GCLK_CTRL1)
#define VPP_SC_GCLK_CTRL 0x1d74 	///../ucode/register.h:5672
#define P_VPP_SC_GCLK_CTRL 		VCBUS_REG_ADDR(VPP_SC_GCLK_CTRL)
#define VPP_MISC1 0x1d76 	///../ucode/register.h:5675
#define P_VPP_MISC1 		VCBUS_REG_ADDR(VPP_MISC1)
#define VPP_BLACKEXT_CTRL 0x1d80 	///../ucode/register.h:5680
#define P_VPP_BLACKEXT_CTRL 		VCBUS_REG_ADDR(VPP_BLACKEXT_CTRL)
#define VPP_DNLP_CTRL_00 0x1d81 	///../ucode/register.h:5685
#define P_VPP_DNLP_CTRL_00 		VCBUS_REG_ADDR(VPP_DNLP_CTRL_00)
#define VPP_DNLP_CTRL_01 0x1d82 	///../ucode/register.h:5690
#define P_VPP_DNLP_CTRL_01 		VCBUS_REG_ADDR(VPP_DNLP_CTRL_01)
#define VPP_DNLP_CTRL_02 0x1d83 	///../ucode/register.h:5695
#define P_VPP_DNLP_CTRL_02 		VCBUS_REG_ADDR(VPP_DNLP_CTRL_02)
#define VPP_DNLP_CTRL_03 0x1d84 	///../ucode/register.h:5700
#define P_VPP_DNLP_CTRL_03 		VCBUS_REG_ADDR(VPP_DNLP_CTRL_03)
#define VPP_DNLP_CTRL_04 0x1d85 	///../ucode/register.h:5705
#define P_VPP_DNLP_CTRL_04 		VCBUS_REG_ADDR(VPP_DNLP_CTRL_04)
#define VPP_DNLP_CTRL_05 0x1d86 	///../ucode/register.h:5710
#define P_VPP_DNLP_CTRL_05 		VCBUS_REG_ADDR(VPP_DNLP_CTRL_05)
#define VPP_DNLP_CTRL_06 0x1d87 	///../ucode/register.h:5715
#define P_VPP_DNLP_CTRL_06 		VCBUS_REG_ADDR(VPP_DNLP_CTRL_06)
#define VPP_DNLP_CTRL_07 0x1d88 	///../ucode/register.h:5720
#define P_VPP_DNLP_CTRL_07 		VCBUS_REG_ADDR(VPP_DNLP_CTRL_07)
#define VPP_DNLP_CTRL_08 0x1d89 	///../ucode/register.h:5725
#define P_VPP_DNLP_CTRL_08 		VCBUS_REG_ADDR(VPP_DNLP_CTRL_08)
#define VPP_DNLP_CTRL_09 0x1d8a 	///../ucode/register.h:5730
#define P_VPP_DNLP_CTRL_09 		VCBUS_REG_ADDR(VPP_DNLP_CTRL_09)
#define VPP_DNLP_CTRL_10 0x1d8b 	///../ucode/register.h:5735
#define P_VPP_DNLP_CTRL_10 		VCBUS_REG_ADDR(VPP_DNLP_CTRL_10)
#define VPP_DNLP_CTRL_11 0x1d8c 	///../ucode/register.h:5740
#define P_VPP_DNLP_CTRL_11 		VCBUS_REG_ADDR(VPP_DNLP_CTRL_11)
#define VPP_DNLP_CTRL_12 0x1d8d 	///../ucode/register.h:5745
#define P_VPP_DNLP_CTRL_12 		VCBUS_REG_ADDR(VPP_DNLP_CTRL_12)
#define VPP_DNLP_CTRL_13 0x1d8e 	///../ucode/register.h:5750
#define P_VPP_DNLP_CTRL_13 		VCBUS_REG_ADDR(VPP_DNLP_CTRL_13)
#define VPP_DNLP_CTRL_14 0x1d8f 	///../ucode/register.h:5755
#define P_VPP_DNLP_CTRL_14 		VCBUS_REG_ADDR(VPP_DNLP_CTRL_14)
#define VPP_DNLP_CTRL_15 0x1d90 	///../ucode/register.h:5760
#define P_VPP_DNLP_CTRL_15 		VCBUS_REG_ADDR(VPP_DNLP_CTRL_15)
#define VPP_PEAKING_HGAIN 0x1d91 	///../ucode/register.h:5769
#define P_VPP_PEAKING_HGAIN 		VCBUS_REG_ADDR(VPP_PEAKING_HGAIN)
#define VPP_PEAKING_VGAIN 0x1d92 	///../ucode/register.h:5778
#define P_VPP_PEAKING_VGAIN 		VCBUS_REG_ADDR(VPP_PEAKING_VGAIN)
#define VPP_PEAKING_NLP_1 0x1d93 	///../ucode/register.h:5784
#define P_VPP_PEAKING_NLP_1 		VCBUS_REG_ADDR(VPP_PEAKING_NLP_1)
#define VPP_PEAKING_NLP_2 0x1d94 	///../ucode/register.h:5789
#define P_VPP_PEAKING_NLP_2 		VCBUS_REG_ADDR(VPP_PEAKING_NLP_2)
#define VPP_PEAKING_NLP_3 0x1d95 	///../ucode/register.h:5795
#define P_VPP_PEAKING_NLP_3 		VCBUS_REG_ADDR(VPP_PEAKING_NLP_3)
#define VPP_PEAKING_NLP_4 0x1d96 	///../ucode/register.h:5800
#define P_VPP_PEAKING_NLP_4 		VCBUS_REG_ADDR(VPP_PEAKING_NLP_4)
#define VPP_PEAKING_NLP_5 0x1d97 	///../ucode/register.h:5805
#define P_VPP_PEAKING_NLP_5 		VCBUS_REG_ADDR(VPP_PEAKING_NLP_5)
#define VPP_SHARP_LIMIT 0x1d98 	///../ucode/register.h:5812
#define P_VPP_SHARP_LIMIT 		VCBUS_REG_ADDR(VPP_SHARP_LIMIT)
#define VPP_VLTI_CTRL 0x1d99 	///../ucode/register.h:5817
#define P_VPP_VLTI_CTRL 		VCBUS_REG_ADDR(VPP_VLTI_CTRL)
#define VPP_HLTI_CTRL 0x1d9a 	///../ucode/register.h:5822
#define P_VPP_HLTI_CTRL 		VCBUS_REG_ADDR(VPP_HLTI_CTRL)
#define VPP_CTI_CTRL 0x1d9b 	///../ucode/register.h:5832
#define P_VPP_CTI_CTRL 		VCBUS_REG_ADDR(VPP_CTI_CTRL)
#define VPP_BLUE_STRETCH_1 0x1d9c 	///../ucode/register.h:5842
#define P_VPP_BLUE_STRETCH_1 		VCBUS_REG_ADDR(VPP_BLUE_STRETCH_1)
#define VPP_BLUE_STRETCH_2 0x1d9d 	///../ucode/register.h:5847
#define P_VPP_BLUE_STRETCH_2 		VCBUS_REG_ADDR(VPP_BLUE_STRETCH_2)
#define VPP_BLUE_STRETCH_3 0x1d9e 	///../ucode/register.h:5852
#define P_VPP_BLUE_STRETCH_3 		VCBUS_REG_ADDR(VPP_BLUE_STRETCH_3)
#define VPP_CCORING_CTRL 0x1da0 	///../ucode/register.h:5856
#define P_VPP_CCORING_CTRL 		VCBUS_REG_ADDR(VPP_CCORING_CTRL)
#define VPP_VE_ENABLE_CTRL 0x1da1 	///../ucode/register.h:5868
#define P_VPP_VE_ENABLE_CTRL 		VCBUS_REG_ADDR(VPP_VE_ENABLE_CTRL)
#define VPP_VE_DEMO_LEFT_TOP_SCREEN_WIDTH 0x1da2 	///../ucode/register.h:5870
#define P_VPP_VE_DEMO_LEFT_TOP_SCREEN_WIDTH 		VCBUS_REG_ADDR(VPP_VE_DEMO_LEFT_TOP_SCREEN_WIDTH)
#define VPP_VE_DEMO_CENTER_BAR 0x1da3 	///../ucode/register.h:5876
#define P_VPP_VE_DEMO_CENTER_BAR 		VCBUS_REG_ADDR(VPP_VE_DEMO_CENTER_BAR)
#define VPP_VE_H_V_SIZE 0x1da4 	///../ucode/register.h:5879
#define P_VPP_VE_H_V_SIZE 		VCBUS_REG_ADDR(VPP_VE_H_V_SIZE)
#define VPP_VDO_MEAS_CTRL 0x1da8 	///../ucode/register.h:5884
#define P_VPP_VDO_MEAS_CTRL 		VCBUS_REG_ADDR(VPP_VDO_MEAS_CTRL)
#define VPP_VDO_MEAS_VS_COUNT_HI 0x1da9 	///../ucode/register.h:5888
#define P_VPP_VDO_MEAS_VS_COUNT_HI 		VCBUS_REG_ADDR(VPP_VDO_MEAS_VS_COUNT_HI)
#define VPP_VDO_MEAS_VS_COUNT_LO 0x1daa 	///../ucode/register.h:5891
#define P_VPP_VDO_MEAS_VS_COUNT_LO 		VCBUS_REG_ADDR(VPP_VDO_MEAS_VS_COUNT_LO)
#define VPP_INPUT_CTRL 0x1dab 	///../ucode/register.h:5899
#define P_VPP_INPUT_CTRL 		VCBUS_REG_ADDR(VPP_INPUT_CTRL)
#define VPP_CTI_CTRL2 0x1dac 	///../ucode/register.h:5904
#define P_VPP_CTI_CTRL2 		VCBUS_REG_ADDR(VPP_CTI_CTRL2)
#define VPP_PEAKING_SAT_THD1 0x1dad 	///../ucode/register.h:5905
#define P_VPP_PEAKING_SAT_THD1 		VCBUS_REG_ADDR(VPP_PEAKING_SAT_THD1)
#define VPP_PEAKING_SAT_THD2 0x1dae 	///../ucode/register.h:5906
#define P_VPP_PEAKING_SAT_THD2 		VCBUS_REG_ADDR(VPP_PEAKING_SAT_THD2)
#define VPP_PEAKING_SAT_THD3 0x1daf 	///../ucode/register.h:5907
#define P_VPP_PEAKING_SAT_THD3 		VCBUS_REG_ADDR(VPP_PEAKING_SAT_THD3)
#define VPP_PEAKING_SAT_THD4 0x1db0 	///../ucode/register.h:5908
#define P_VPP_PEAKING_SAT_THD4 		VCBUS_REG_ADDR(VPP_PEAKING_SAT_THD4)
#define VPP_PEAKING_SAT_THD5 0x1db1 	///../ucode/register.h:5909
#define P_VPP_PEAKING_SAT_THD5 		VCBUS_REG_ADDR(VPP_PEAKING_SAT_THD5)
#define VPP_PEAKING_SAT_THD6 0x1db2 	///../ucode/register.h:5910
#define P_VPP_PEAKING_SAT_THD6 		VCBUS_REG_ADDR(VPP_PEAKING_SAT_THD6)
#define VPP_PEAKING_SAT_THD7 0x1db3 	///../ucode/register.h:5911
#define P_VPP_PEAKING_SAT_THD7 		VCBUS_REG_ADDR(VPP_PEAKING_SAT_THD7)
#define VPP_PEAKING_SAT_THD8 0x1db4 	///../ucode/register.h:5912
#define P_VPP_PEAKING_SAT_THD8 		VCBUS_REG_ADDR(VPP_PEAKING_SAT_THD8)
#define VPP_PEAKING_SAT_THD9 0x1db5 	///../ucode/register.h:5913
#define P_VPP_PEAKING_SAT_THD9 		VCBUS_REG_ADDR(VPP_PEAKING_SAT_THD9)
#define VPP_PEAKING_GAIN_ADD1 0x1db6 	///../ucode/register.h:5914
#define P_VPP_PEAKING_GAIN_ADD1 		VCBUS_REG_ADDR(VPP_PEAKING_GAIN_ADD1)
#define VPP_PEAKING_GAIN_ADD2 0x1db7 	///../ucode/register.h:5915
#define P_VPP_PEAKING_GAIN_ADD2 		VCBUS_REG_ADDR(VPP_PEAKING_GAIN_ADD2)
#define VPP_PEAKING_DNLP 0x1db8 	///../ucode/register.h:5920
#define P_VPP_PEAKING_DNLP 		VCBUS_REG_ADDR(VPP_PEAKING_DNLP)
#define VPP_SHARP_DEMO_WIN_CTRL1 0x1db9 	///../ucode/register.h:5924
#define P_VPP_SHARP_DEMO_WIN_CTRL1 		VCBUS_REG_ADDR(VPP_SHARP_DEMO_WIN_CTRL1)
#define VPP_SHARP_DEMO_WIN_CTRL2 0x1dba 	///../ucode/register.h:5927
#define P_VPP_SHARP_DEMO_WIN_CTRL2 		VCBUS_REG_ADDR(VPP_SHARP_DEMO_WIN_CTRL2)
#define VPP_FRONT_HLTI_CTRL 0x1dbb 	///../ucode/register.h:5932
#define P_VPP_FRONT_HLTI_CTRL 		VCBUS_REG_ADDR(VPP_FRONT_HLTI_CTRL)
#define VPP_FRONT_CTI_CTRL 0x1dbc 	///../ucode/register.h:5940
#define P_VPP_FRONT_CTI_CTRL 		VCBUS_REG_ADDR(VPP_FRONT_CTI_CTRL)
#define VPP_FRONT_CTI_CTRL2 0x1dbd 	///../ucode/register.h:5946
#define P_VPP_FRONT_CTI_CTRL2 		VCBUS_REG_ADDR(VPP_FRONT_CTI_CTRL2)
#define VPP_OSD_VSC_PHASE_STEP 0x1dc0 	///../ucode/register.h:5949
#define P_VPP_OSD_VSC_PHASE_STEP 		VCBUS_REG_ADDR(VPP_OSD_VSC_PHASE_STEP)
#define VPP_OSD_VSC_INI_PHASE 0x1dc1 	///../ucode/register.h:5952
#define P_VPP_OSD_VSC_INI_PHASE 		VCBUS_REG_ADDR(VPP_OSD_VSC_INI_PHASE)
#define VPP_OSD_VSC_CTRL0 0x1dc2 	///../ucode/register.h:5963
#define P_VPP_OSD_VSC_CTRL0 		VCBUS_REG_ADDR(VPP_OSD_VSC_CTRL0)
#define VPP_OSD_HSC_PHASE_STEP 0x1dc3 	///../ucode/register.h:5966
#define P_VPP_OSD_HSC_PHASE_STEP 		VCBUS_REG_ADDR(VPP_OSD_HSC_PHASE_STEP)
#define VPP_OSD_HSC_INI_PHASE 0x1dc4 	///../ucode/register.h:5969
#define P_VPP_OSD_HSC_INI_PHASE 		VCBUS_REG_ADDR(VPP_OSD_HSC_INI_PHASE)
#define VPP_OSD_HSC_CTRL0 0x1dc5 	///../ucode/register.h:5979
#define P_VPP_OSD_HSC_CTRL0 		VCBUS_REG_ADDR(VPP_OSD_HSC_CTRL0)
#define VPP_OSD_HSC_INI_PAT_CTRL 0x1dc6 	///../ucode/register.h:5984
#define P_VPP_OSD_HSC_INI_PAT_CTRL 		VCBUS_REG_ADDR(VPP_OSD_HSC_INI_PAT_CTRL)
#define VPP_OSD_SC_DUMMY_DATA 0x1dc7 	///../ucode/register.h:5989
#define P_VPP_OSD_SC_DUMMY_DATA 		VCBUS_REG_ADDR(VPP_OSD_SC_DUMMY_DATA)
#define VPP_OSD_SC_CTRL0 0x1dc8 	///../ucode/register.h:5997
#define P_VPP_OSD_SC_CTRL0 		VCBUS_REG_ADDR(VPP_OSD_SC_CTRL0)
#define VPP_OSD_SCI_WH_M1 0x1dc9 	///../ucode/register.h:6000
#define P_VPP_OSD_SCI_WH_M1 		VCBUS_REG_ADDR(VPP_OSD_SCI_WH_M1)
#define VPP_OSD_SCO_H_START_END 0x1dca 	///../ucode/register.h:6003
#define P_VPP_OSD_SCO_H_START_END 		VCBUS_REG_ADDR(VPP_OSD_SCO_H_START_END)
#define VPP_OSD_SCO_V_START_END 0x1dcb 	///../ucode/register.h:6006
#define P_VPP_OSD_SCO_V_START_END 		VCBUS_REG_ADDR(VPP_OSD_SCO_V_START_END)
#define VPP_OSD_SCALE_COEF_IDX 0x1dcc 	///../ucode/register.h:6016
#define P_VPP_OSD_SCALE_COEF_IDX 		VCBUS_REG_ADDR(VPP_OSD_SCALE_COEF_IDX)
#define VPP_OSD_SCALE_COEF 0x1dcd 	///../ucode/register.h:6018
#define P_VPP_OSD_SCALE_COEF 		VCBUS_REG_ADDR(VPP_OSD_SCALE_COEF)
#define VPP_INT_LINE_NUM 0x1dce 	///../ucode/register.h:6020
#define P_VPP_INT_LINE_NUM 		VCBUS_REG_ADDR(VPP_INT_LINE_NUM)
#define VPP2_DUMMY_DATA 0x1900 	///../ucode/register.h:6041
#define P_VPP2_DUMMY_DATA 		VCBUS_REG_ADDR(VPP2_DUMMY_DATA)
#define VPP2_LINE_IN_LENGTH 0x1901 	///../ucode/register.h:6043
#define P_VPP2_LINE_IN_LENGTH 		VCBUS_REG_ADDR(VPP2_LINE_IN_LENGTH)
#define VPP2_PIC_IN_HEIGHT 0x1902 	///../ucode/register.h:6045
#define P_VPP2_PIC_IN_HEIGHT 		VCBUS_REG_ADDR(VPP2_PIC_IN_HEIGHT)
#define VPP2_SCALE_COEF_IDX 0x1903 	///../ucode/register.h:6056
#define P_VPP2_SCALE_COEF_IDX 		VCBUS_REG_ADDR(VPP2_SCALE_COEF_IDX)
#define VPP2_SCALE_COEF 0x1904 	///../ucode/register.h:6058
#define P_VPP2_SCALE_COEF 		VCBUS_REG_ADDR(VPP2_SCALE_COEF)
#define VPP2_VSC_REGION12_STARTP 0x1905 	///../ucode/register.h:6094
#define P_VPP2_VSC_REGION12_STARTP 		VCBUS_REG_ADDR(VPP2_VSC_REGION12_STARTP)
#define VPP2_VSC_REGION34_STARTP 0x1906 	///../ucode/register.h:6097
#define P_VPP2_VSC_REGION34_STARTP 		VCBUS_REG_ADDR(VPP2_VSC_REGION34_STARTP)
#define VPP2_VSC_REGION4_ENDP 0x1907 	///../ucode/register.h:6098
#define P_VPP2_VSC_REGION4_ENDP 		VCBUS_REG_ADDR(VPP2_VSC_REGION4_ENDP)
#define VPP2_VSC_START_PHASE_STEP 0x1908 	///../ucode/register.h:6102
#define P_VPP2_VSC_START_PHASE_STEP 		VCBUS_REG_ADDR(VPP2_VSC_START_PHASE_STEP)
#define VPP2_VSC_REGION0_PHASE_SLOPE 0x1909 	///../ucode/register.h:6104
#define P_VPP2_VSC_REGION0_PHASE_SLOPE 		VCBUS_REG_ADDR(VPP2_VSC_REGION0_PHASE_SLOPE)
#define VPP2_VSC_REGION1_PHASE_SLOPE 0x190a 	///../ucode/register.h:6106
#define P_VPP2_VSC_REGION1_PHASE_SLOPE 		VCBUS_REG_ADDR(VPP2_VSC_REGION1_PHASE_SLOPE)
#define VPP2_VSC_REGION3_PHASE_SLOPE 0x190b 	///../ucode/register.h:6108
#define P_VPP2_VSC_REGION3_PHASE_SLOPE 		VCBUS_REG_ADDR(VPP2_VSC_REGION3_PHASE_SLOPE)
#define VPP2_VSC_REGION4_PHASE_SLOPE 0x190c 	///../ucode/register.h:6110
#define P_VPP2_VSC_REGION4_PHASE_SLOPE 		VCBUS_REG_ADDR(VPP2_VSC_REGION4_PHASE_SLOPE)
#define VPP2_VSC_PHASE_CTRL 0x190d 	///../ucode/register.h:6121
#define P_VPP2_VSC_PHASE_CTRL 		VCBUS_REG_ADDR(VPP2_VSC_PHASE_CTRL)
#define VPP2_VSC_INI_PHASE 0x190e 	///../ucode/register.h:6124
#define P_VPP2_VSC_INI_PHASE 		VCBUS_REG_ADDR(VPP2_VSC_INI_PHASE)
#define VPP2_HSC_REGION12_STARTP 0x1910 	///../ucode/register.h:6127
#define P_VPP2_HSC_REGION12_STARTP 		VCBUS_REG_ADDR(VPP2_HSC_REGION12_STARTP)
#define VPP2_HSC_REGION34_STARTP 0x1911 	///../ucode/register.h:6130
#define P_VPP2_HSC_REGION34_STARTP 		VCBUS_REG_ADDR(VPP2_HSC_REGION34_STARTP)
#define VPP2_HSC_REGION4_ENDP 0x1912 	///../ucode/register.h:6131
#define P_VPP2_HSC_REGION4_ENDP 		VCBUS_REG_ADDR(VPP2_HSC_REGION4_ENDP)
#define VPP2_HSC_START_PHASE_STEP 0x1913 	///../ucode/register.h:6135
#define P_VPP2_HSC_START_PHASE_STEP 		VCBUS_REG_ADDR(VPP2_HSC_START_PHASE_STEP)
#define VPP2_HSC_REGION0_PHASE_SLOPE 0x1914 	///../ucode/register.h:6137
#define P_VPP2_HSC_REGION0_PHASE_SLOPE 		VCBUS_REG_ADDR(VPP2_HSC_REGION0_PHASE_SLOPE)
#define VPP2_HSC_REGION1_PHASE_SLOPE 0x1915 	///../ucode/register.h:6139
#define P_VPP2_HSC_REGION1_PHASE_SLOPE 		VCBUS_REG_ADDR(VPP2_HSC_REGION1_PHASE_SLOPE)
#define VPP2_HSC_REGION3_PHASE_SLOPE 0x1916 	///../ucode/register.h:6141
#define P_VPP2_HSC_REGION3_PHASE_SLOPE 		VCBUS_REG_ADDR(VPP2_HSC_REGION3_PHASE_SLOPE)
#define VPP2_HSC_REGION4_PHASE_SLOPE 0x1917 	///../ucode/register.h:6143
#define P_VPP2_HSC_REGION4_PHASE_SLOPE 		VCBUS_REG_ADDR(VPP2_HSC_REGION4_PHASE_SLOPE)
#define VPP2_HSC_PHASE_CTRL 0x1918 	///../ucode/register.h:6147
#define P_VPP2_HSC_PHASE_CTRL 		VCBUS_REG_ADDR(VPP2_HSC_PHASE_CTRL)
#define VPP2_SC_MISC 0x1919 	///../ucode/register.h:6162
#define P_VPP2_SC_MISC 		VCBUS_REG_ADDR(VPP2_SC_MISC)
#define VPP2_PREBLEND_VD1_H_START_END 0x191a 	///../ucode/register.h:6166
#define P_VPP2_PREBLEND_VD1_H_START_END 		VCBUS_REG_ADDR(VPP2_PREBLEND_VD1_H_START_END)
#define VPP2_PREBLEND_VD1_V_START_END 0x191b 	///../ucode/register.h:6170
#define P_VPP2_PREBLEND_VD1_V_START_END 		VCBUS_REG_ADDR(VPP2_PREBLEND_VD1_V_START_END)
#define VPP2_POSTBLEND_VD1_H_START_END 0x191c 	///../ucode/register.h:6174
#define P_VPP2_POSTBLEND_VD1_H_START_END 		VCBUS_REG_ADDR(VPP2_POSTBLEND_VD1_H_START_END)
#define VPP2_POSTBLEND_VD1_V_START_END 0x191d 	///../ucode/register.h:6178
#define P_VPP2_POSTBLEND_VD1_V_START_END 		VCBUS_REG_ADDR(VPP2_POSTBLEND_VD1_V_START_END)
#define VPP2_PREBLEND_H_SIZE 0x1920 	///../ucode/register.h:6180
#define P_VPP2_PREBLEND_H_SIZE 		VCBUS_REG_ADDR(VPP2_PREBLEND_H_SIZE)
#define VPP2_POSTBLEND_H_SIZE 0x1921 	///../ucode/register.h:6182
#define P_VPP2_POSTBLEND_H_SIZE 		VCBUS_REG_ADDR(VPP2_POSTBLEND_H_SIZE)
#define VPP2_HOLD_LINES 0x1922 	///../ucode/register.h:6188
#define P_VPP2_HOLD_LINES 		VCBUS_REG_ADDR(VPP2_HOLD_LINES)
#define VPP2_BLEND_ONECOLOR_CTRL 0x1923 	///../ucode/register.h:6194
#define P_VPP2_BLEND_ONECOLOR_CTRL 		VCBUS_REG_ADDR(VPP2_BLEND_ONECOLOR_CTRL)
#define VPP2_PREBLEND_CURRENT_XY 0x1924 	///../ucode/register.h:6198
#define P_VPP2_PREBLEND_CURRENT_XY 		VCBUS_REG_ADDR(VPP2_PREBLEND_CURRENT_XY)
#define VPP2_POSTBLEND_CURRENT_XY 0x1925 	///../ucode/register.h:6202
#define P_VPP2_POSTBLEND_CURRENT_XY 		VCBUS_REG_ADDR(VPP2_POSTBLEND_CURRENT_XY)
#define VPP2_MISC 0x1926 	///../ucode/register.h:6227
#define P_VPP2_MISC 		VCBUS_REG_ADDR(VPP2_MISC)
#define VPP2_OFIFO_SIZE 0x1927 	///../ucode/register.h:6236
#define P_VPP2_OFIFO_SIZE 		VCBUS_REG_ADDR(VPP2_OFIFO_SIZE)
#define VPP2_FIFO_STATUS 0x1928 	///../ucode/register.h:6241
#define P_VPP2_FIFO_STATUS 		VCBUS_REG_ADDR(VPP2_FIFO_STATUS)
#define VPP2_SMOKE_CTRL 0x1929 	///../ucode/register.h:6246
#define P_VPP2_SMOKE_CTRL 		VCBUS_REG_ADDR(VPP2_SMOKE_CTRL)
#define VPP2_SMOKE1_VAL 0x192a 	///../ucode/register.h:6254
#define P_VPP2_SMOKE1_VAL 		VCBUS_REG_ADDR(VPP2_SMOKE1_VAL)
#define VPP2_SMOKE2_VAL 0x192b 	///../ucode/register.h:6255
#define P_VPP2_SMOKE2_VAL 		VCBUS_REG_ADDR(VPP2_SMOKE2_VAL)
#define VPP2_SMOKE1_H_START_END 0x192d 	///../ucode/register.h:6258
#define P_VPP2_SMOKE1_H_START_END 		VCBUS_REG_ADDR(VPP2_SMOKE1_H_START_END)
#define VPP2_SMOKE1_V_START_END 0x192e 	///../ucode/register.h:6261
#define P_VPP2_SMOKE1_V_START_END 		VCBUS_REG_ADDR(VPP2_SMOKE1_V_START_END)
#define VPP2_SMOKE2_H_START_END 0x192f 	///../ucode/register.h:6264
#define P_VPP2_SMOKE2_H_START_END 		VCBUS_REG_ADDR(VPP2_SMOKE2_H_START_END)
#define VPP2_SMOKE2_V_START_END 0x1930 	///../ucode/register.h:6267
#define P_VPP2_SMOKE2_V_START_END 		VCBUS_REG_ADDR(VPP2_SMOKE2_V_START_END)
#define VPP2_SCO_FIFO_CTRL 0x1933 	///../ucode/register.h:6270
#define P_VPP2_SCO_FIFO_CTRL 		VCBUS_REG_ADDR(VPP2_SCO_FIFO_CTRL)
#define VPP2_HSC_PHASE_CTRL1 0x1934 	///../ucode/register.h:6278
#define P_VPP2_HSC_PHASE_CTRL1 		VCBUS_REG_ADDR(VPP2_HSC_PHASE_CTRL1)
#define VPP2_HSC_INI_PAT_CTRL 0x1935 	///../ucode/register.h:6286
#define P_VPP2_HSC_INI_PAT_CTRL 		VCBUS_REG_ADDR(VPP2_HSC_INI_PAT_CTRL)
#define VPP2_VADJ_CTRL 0x1940 	///../ucode/register.h:6291
#define P_VPP2_VADJ_CTRL 		VCBUS_REG_ADDR(VPP2_VADJ_CTRL)
#define VPP2_VADJ1_Y 0x1941 	///../ucode/register.h:6294
#define P_VPP2_VADJ1_Y 		VCBUS_REG_ADDR(VPP2_VADJ1_Y)
#define VPP2_VADJ1_MA_MB 0x1942 	///../ucode/register.h:6298
#define P_VPP2_VADJ1_MA_MB 		VCBUS_REG_ADDR(VPP2_VADJ1_MA_MB)
#define VPP2_VADJ1_MC_MD 0x1943 	///../ucode/register.h:6299
#define P_VPP2_VADJ1_MC_MD 		VCBUS_REG_ADDR(VPP2_VADJ1_MC_MD)
#define VPP2_VADJ2_Y 0x1944 	///../ucode/register.h:6302
#define P_VPP2_VADJ2_Y 		VCBUS_REG_ADDR(VPP2_VADJ2_Y)
#define VPP2_VADJ2_MA_MB 0x1945 	///../ucode/register.h:6306
#define P_VPP2_VADJ2_MA_MB 		VCBUS_REG_ADDR(VPP2_VADJ2_MA_MB)
#define VPP2_VADJ2_MC_MD 0x1946 	///../ucode/register.h:6307
#define P_VPP2_VADJ2_MC_MD 		VCBUS_REG_ADDR(VPP2_VADJ2_MC_MD)
#define VPP2_MATRIX_PROBE_COLOR 0x195c 	///../ucode/register.h:6313
#define P_VPP2_MATRIX_PROBE_COLOR 		VCBUS_REG_ADDR(VPP2_MATRIX_PROBE_COLOR)
#define VPP2_MATRIX_HL_COLOR 0x195d 	///../ucode/register.h:6317
#define P_VPP2_MATRIX_HL_COLOR 		VCBUS_REG_ADDR(VPP2_MATRIX_HL_COLOR)
#define VPP2_MATRIX_PROBE_POS 0x195e 	///../ucode/register.h:6320
#define P_VPP2_MATRIX_PROBE_POS 		VCBUS_REG_ADDR(VPP2_MATRIX_PROBE_POS)
#define VPP2_MATRIX_CTRL 0x195f 	///../ucode/register.h:6330
#define P_VPP2_MATRIX_CTRL 		VCBUS_REG_ADDR(VPP2_MATRIX_CTRL)
#define VPP2_MATRIX_COEF00_01 0x1960 	///../ucode/register.h:6333
#define P_VPP2_MATRIX_COEF00_01 		VCBUS_REG_ADDR(VPP2_MATRIX_COEF00_01)
#define VPP2_MATRIX_COEF02_10 0x1961 	///../ucode/register.h:6336
#define P_VPP2_MATRIX_COEF02_10 		VCBUS_REG_ADDR(VPP2_MATRIX_COEF02_10)
#define VPP2_MATRIX_COEF11_12 0x1962 	///../ucode/register.h:6339
#define P_VPP2_MATRIX_COEF11_12 		VCBUS_REG_ADDR(VPP2_MATRIX_COEF11_12)
#define VPP2_MATRIX_COEF20_21 0x1963 	///../ucode/register.h:6342
#define P_VPP2_MATRIX_COEF20_21 		VCBUS_REG_ADDR(VPP2_MATRIX_COEF20_21)
#define VPP2_MATRIX_COEF22 0x1964 	///../ucode/register.h:6343
#define P_VPP2_MATRIX_COEF22 		VCBUS_REG_ADDR(VPP2_MATRIX_COEF22)
#define VPP2_MATRIX_OFFSET0_1 0x1965 	///../ucode/register.h:6346
#define P_VPP2_MATRIX_OFFSET0_1 		VCBUS_REG_ADDR(VPP2_MATRIX_OFFSET0_1)
#define VPP2_MATRIX_OFFSET2 0x1966 	///../ucode/register.h:6348
#define P_VPP2_MATRIX_OFFSET2 		VCBUS_REG_ADDR(VPP2_MATRIX_OFFSET2)
#define VPP2_MATRIX_PRE_OFFSET0_1 0x1967 	///../ucode/register.h:6351
#define P_VPP2_MATRIX_PRE_OFFSET0_1 		VCBUS_REG_ADDR(VPP2_MATRIX_PRE_OFFSET0_1)
#define VPP2_MATRIX_PRE_OFFSET2 0x1968 	///../ucode/register.h:6353
#define P_VPP2_MATRIX_PRE_OFFSET2 		VCBUS_REG_ADDR(VPP2_MATRIX_PRE_OFFSET2)
#define VPP2_DUMMY_DATA1 0x1969 	///../ucode/register.h:6358
#define P_VPP2_DUMMY_DATA1 		VCBUS_REG_ADDR(VPP2_DUMMY_DATA1)
#define VPP2_GAINOFF_CTRL0 0x196a 	///../ucode/register.h:6362
#define P_VPP2_GAINOFF_CTRL0 		VCBUS_REG_ADDR(VPP2_GAINOFF_CTRL0)
#define VPP2_GAINOFF_CTRL1 0x196b 	///../ucode/register.h:6365
#define P_VPP2_GAINOFF_CTRL1 		VCBUS_REG_ADDR(VPP2_GAINOFF_CTRL1)
#define VPP2_GAINOFF_CTRL2 0x196c 	///../ucode/register.h:6368
#define P_VPP2_GAINOFF_CTRL2 		VCBUS_REG_ADDR(VPP2_GAINOFF_CTRL2)
#define VPP2_GAINOFF_CTRL3 0x196d 	///../ucode/register.h:6371
#define P_VPP2_GAINOFF_CTRL3 		VCBUS_REG_ADDR(VPP2_GAINOFF_CTRL3)
#define VPP2_GAINOFF_CTRL4 0x196e 	///../ucode/register.h:6373
#define P_VPP2_GAINOFF_CTRL4 		VCBUS_REG_ADDR(VPP2_GAINOFF_CTRL4)
#define VPP2_CHROMA_ADDR_PORT 0x1970 	///../ucode/register.h:6375
#define P_VPP2_CHROMA_ADDR_PORT 		VCBUS_REG_ADDR(VPP2_CHROMA_ADDR_PORT)
#define VPP2_CHROMA_DATA_PORT 0x1971 	///../ucode/register.h:6376
#define P_VPP2_CHROMA_DATA_PORT 		VCBUS_REG_ADDR(VPP2_CHROMA_DATA_PORT)
#define VPP2_GCLK_CTRL0 0x1972 	///../ucode/register.h:6383
#define P_VPP2_GCLK_CTRL0 		VCBUS_REG_ADDR(VPP2_GCLK_CTRL0)
#define VPP2_GCLK_CTRL1 0x1973 	///../ucode/register.h:6386
#define P_VPP2_GCLK_CTRL1 		VCBUS_REG_ADDR(VPP2_GCLK_CTRL1)
#define VPP2_SC_GCLK_CTRL 0x1974 	///../ucode/register.h:6389
#define P_VPP2_SC_GCLK_CTRL 		VCBUS_REG_ADDR(VPP2_SC_GCLK_CTRL)
#define VPP2_MISC1 0x1976 	///../ucode/register.h:6392
#define P_VPP2_MISC1 		VCBUS_REG_ADDR(VPP2_MISC1)
#define VPP2_DNLP_CTRL_00 0x1981 	///../ucode/register.h:6397
#define P_VPP2_DNLP_CTRL_00 		VCBUS_REG_ADDR(VPP2_DNLP_CTRL_00)
#define VPP2_DNLP_CTRL_01 0x1982 	///../ucode/register.h:6402
#define P_VPP2_DNLP_CTRL_01 		VCBUS_REG_ADDR(VPP2_DNLP_CTRL_01)
#define VPP2_DNLP_CTRL_02 0x1983 	///../ucode/register.h:6407
#define P_VPP2_DNLP_CTRL_02 		VCBUS_REG_ADDR(VPP2_DNLP_CTRL_02)
#define VPP2_DNLP_CTRL_03 0x1984 	///../ucode/register.h:6412
#define P_VPP2_DNLP_CTRL_03 		VCBUS_REG_ADDR(VPP2_DNLP_CTRL_03)
#define VPP2_DNLP_CTRL_04 0x1985 	///../ucode/register.h:6417
#define P_VPP2_DNLP_CTRL_04 		VCBUS_REG_ADDR(VPP2_DNLP_CTRL_04)
#define VPP2_DNLP_CTRL_05 0x1986 	///../ucode/register.h:6422
#define P_VPP2_DNLP_CTRL_05 		VCBUS_REG_ADDR(VPP2_DNLP_CTRL_05)
#define VPP2_DNLP_CTRL_06 0x1987 	///../ucode/register.h:6427
#define P_VPP2_DNLP_CTRL_06 		VCBUS_REG_ADDR(VPP2_DNLP_CTRL_06)
#define VPP2_DNLP_CTRL_07 0x1988 	///../ucode/register.h:6432
#define P_VPP2_DNLP_CTRL_07 		VCBUS_REG_ADDR(VPP2_DNLP_CTRL_07)
#define VPP2_DNLP_CTRL_08 0x1989 	///../ucode/register.h:6437
#define P_VPP2_DNLP_CTRL_08 		VCBUS_REG_ADDR(VPP2_DNLP_CTRL_08)
#define VPP2_DNLP_CTRL_09 0x198a 	///../ucode/register.h:6442
#define P_VPP2_DNLP_CTRL_09 		VCBUS_REG_ADDR(VPP2_DNLP_CTRL_09)
#define VPP2_DNLP_CTRL_10 0x198b 	///../ucode/register.h:6447
#define P_VPP2_DNLP_CTRL_10 		VCBUS_REG_ADDR(VPP2_DNLP_CTRL_10)
#define VPP2_DNLP_CTRL_11 0x198c 	///../ucode/register.h:6452
#define P_VPP2_DNLP_CTRL_11 		VCBUS_REG_ADDR(VPP2_DNLP_CTRL_11)
#define VPP2_DNLP_CTRL_12 0x198d 	///../ucode/register.h:6457
#define P_VPP2_DNLP_CTRL_12 		VCBUS_REG_ADDR(VPP2_DNLP_CTRL_12)
#define VPP2_DNLP_CTRL_13 0x198e 	///../ucode/register.h:6462
#define P_VPP2_DNLP_CTRL_13 		VCBUS_REG_ADDR(VPP2_DNLP_CTRL_13)
#define VPP2_DNLP_CTRL_14 0x198f 	///../ucode/register.h:6467
#define P_VPP2_DNLP_CTRL_14 		VCBUS_REG_ADDR(VPP2_DNLP_CTRL_14)
#define VPP2_DNLP_CTRL_15 0x1990 	///../ucode/register.h:6472
#define P_VPP2_DNLP_CTRL_15 		VCBUS_REG_ADDR(VPP2_DNLP_CTRL_15)
#define VPP2_VE_ENABLE_CTRL 0x19a1 	///../ucode/register.h:6484
#define P_VPP2_VE_ENABLE_CTRL 		VCBUS_REG_ADDR(VPP2_VE_ENABLE_CTRL)
#define VPP2_VE_DEMO_LEFT_TOP_SCREEN_WIDTH 0x19a2 	///../ucode/register.h:6486
#define P_VPP2_VE_DEMO_LEFT_TOP_SCREEN_WIDTH 		VCBUS_REG_ADDR(VPP2_VE_DEMO_LEFT_TOP_SCREEN_WIDTH)
#define VPP2_VE_DEMO_CENTER_BAR 0x19a3 	///../ucode/register.h:6492
#define P_VPP2_VE_DEMO_CENTER_BAR 		VCBUS_REG_ADDR(VPP2_VE_DEMO_CENTER_BAR)
#define VPP2_VE_H_V_SIZE 0x19a4 	///../ucode/register.h:6495
#define P_VPP2_VE_H_V_SIZE 		VCBUS_REG_ADDR(VPP2_VE_H_V_SIZE)
#define VPP2_VDO_MEAS_CTRL 0x19a8 	///../ucode/register.h:6500
#define P_VPP2_VDO_MEAS_CTRL 		VCBUS_REG_ADDR(VPP2_VDO_MEAS_CTRL)
#define VPP2_VDO_MEAS_VS_COUNT_HI 0x19a9 	///../ucode/register.h:6504
#define P_VPP2_VDO_MEAS_VS_COUNT_HI 		VCBUS_REG_ADDR(VPP2_VDO_MEAS_VS_COUNT_HI)
#define VPP2_VDO_MEAS_VS_COUNT_LO 0x19aa 	///../ucode/register.h:6507
#define P_VPP2_VDO_MEAS_VS_COUNT_LO 		VCBUS_REG_ADDR(VPP2_VDO_MEAS_VS_COUNT_LO)
#define VPP2_OSD_VSC_PHASE_STEP 0x19c0 	///../ucode/register.h:6510
#define P_VPP2_OSD_VSC_PHASE_STEP 		VCBUS_REG_ADDR(VPP2_OSD_VSC_PHASE_STEP)
#define VPP2_OSD_VSC_INI_PHASE 0x19c1 	///../ucode/register.h:6513
#define P_VPP2_OSD_VSC_INI_PHASE 		VCBUS_REG_ADDR(VPP2_OSD_VSC_INI_PHASE)
#define VPP2_OSD_VSC_CTRL0 0x19c2 	///../ucode/register.h:6524
#define P_VPP2_OSD_VSC_CTRL0 		VCBUS_REG_ADDR(VPP2_OSD_VSC_CTRL0)
#define VPP2_OSD_HSC_PHASE_STEP 0x19c3 	///../ucode/register.h:6527
#define P_VPP2_OSD_HSC_PHASE_STEP 		VCBUS_REG_ADDR(VPP2_OSD_HSC_PHASE_STEP)
#define VPP2_OSD_HSC_INI_PHASE 0x19c4 	///../ucode/register.h:6530
#define P_VPP2_OSD_HSC_INI_PHASE 		VCBUS_REG_ADDR(VPP2_OSD_HSC_INI_PHASE)
#define VPP2_OSD_HSC_CTRL0 0x19c5 	///../ucode/register.h:6540
#define P_VPP2_OSD_HSC_CTRL0 		VCBUS_REG_ADDR(VPP2_OSD_HSC_CTRL0)
#define VPP2_OSD_HSC_INI_PAT_CTRL 0x19c6 	///../ucode/register.h:6545
#define P_VPP2_OSD_HSC_INI_PAT_CTRL 		VCBUS_REG_ADDR(VPP2_OSD_HSC_INI_PAT_CTRL)
#define VPP2_OSD_SC_DUMMY_DATA 0x19c7 	///../ucode/register.h:6550
#define P_VPP2_OSD_SC_DUMMY_DATA 		VCBUS_REG_ADDR(VPP2_OSD_SC_DUMMY_DATA)
#define VPP2_OSD_SC_CTRL0 0x19c8 	///../ucode/register.h:6558
#define P_VPP2_OSD_SC_CTRL0 		VCBUS_REG_ADDR(VPP2_OSD_SC_CTRL0)
#define VPP2_OSD_SCI_WH_M1 0x19c9 	///../ucode/register.h:6561
#define P_VPP2_OSD_SCI_WH_M1 		VCBUS_REG_ADDR(VPP2_OSD_SCI_WH_M1)
#define VPP2_OSD_SCO_H_START_END 0x19ca 	///../ucode/register.h:6564
#define P_VPP2_OSD_SCO_H_START_END 		VCBUS_REG_ADDR(VPP2_OSD_SCO_H_START_END)
#define VPP2_OSD_SCO_V_START_END 0x19cb 	///../ucode/register.h:6567
#define P_VPP2_OSD_SCO_V_START_END 		VCBUS_REG_ADDR(VPP2_OSD_SCO_V_START_END)
#define VPP2_OSD_SCALE_COEF_IDX 0x19cc 	///../ucode/register.h:6577
#define P_VPP2_OSD_SCALE_COEF_IDX 		VCBUS_REG_ADDR(VPP2_OSD_SCALE_COEF_IDX)
#define VPP2_OSD_SCALE_COEF 0x19cd 	///../ucode/register.h:6579
#define P_VPP2_OSD_SCALE_COEF 		VCBUS_REG_ADDR(VPP2_OSD_SCALE_COEF)
#define VPP2_INT_LINE_NUM 0x19ce 	///../ucode/register.h:6581
#define P_VPP2_INT_LINE_NUM 		VCBUS_REG_ADDR(VPP2_INT_LINE_NUM)
#define VIU_ADDR_START 0x1a00 	///../ucode/register.h:6596
#define P_VIU_ADDR_START 		VCBUS_REG_ADDR(VIU_ADDR_START)
#define VIU_ADDR_END 0x1aff 	///../ucode/register.h:6597
#define P_VIU_ADDR_END 		VCBUS_REG_ADDR(VIU_ADDR_END)
#define VIU_SW_RESET 0x1a01 	///../ucode/register.h:6631
#define P_VIU_SW_RESET 		VCBUS_REG_ADDR(VIU_SW_RESET)
#define VIU_MISC_CTRL0 0x1a06 	///../ucode/register.h:6633
#define P_VIU_MISC_CTRL0 		VCBUS_REG_ADDR(VIU_MISC_CTRL0)
#define D2D3_INTF_LENGTH 0x1a08 	///../ucode/register.h:6634
#define P_D2D3_INTF_LENGTH 		VCBUS_REG_ADDR(D2D3_INTF_LENGTH)
#define D2D3_INTF_CTRL0 0x1a09 	///../ucode/register.h:6652
#define P_D2D3_INTF_CTRL0 		VCBUS_REG_ADDR(D2D3_INTF_CTRL0)
#define VIU_OSD1_CTRL_STAT 0x1a10 	///../ucode/register.h:6672
#define P_VIU_OSD1_CTRL_STAT 		VCBUS_REG_ADDR(VIU_OSD1_CTRL_STAT)
#define VIU_OSD1_CTRL_STAT2 0x1a2d 	///../ucode/register.h:6681
#define P_VIU_OSD1_CTRL_STAT2 		VCBUS_REG_ADDR(VIU_OSD1_CTRL_STAT2)
#define VIU_OSD1_COLOR_ADDR 0x1a11 	///../ucode/register.h:6685
#define P_VIU_OSD1_COLOR_ADDR 		VCBUS_REG_ADDR(VIU_OSD1_COLOR_ADDR)
#define VIU_OSD1_COLOR 0x1a12 	///../ucode/register.h:6690
#define P_VIU_OSD1_COLOR 		VCBUS_REG_ADDR(VIU_OSD1_COLOR)
#define VIU_OSD1_TCOLOR_AG0 0x1a17 	///../ucode/register.h:6695
#define P_VIU_OSD1_TCOLOR_AG0 		VCBUS_REG_ADDR(VIU_OSD1_TCOLOR_AG0)
#define VIU_OSD1_TCOLOR_AG1 0x1a18 	///../ucode/register.h:6696
#define P_VIU_OSD1_TCOLOR_AG1 		VCBUS_REG_ADDR(VIU_OSD1_TCOLOR_AG1)
#define VIU_OSD1_TCOLOR_AG2 0x1a19 	///../ucode/register.h:6697
#define P_VIU_OSD1_TCOLOR_AG2 		VCBUS_REG_ADDR(VIU_OSD1_TCOLOR_AG2)
#define VIU_OSD1_TCOLOR_AG3 0x1a1a 	///../ucode/register.h:6698
#define P_VIU_OSD1_TCOLOR_AG3 		VCBUS_REG_ADDR(VIU_OSD1_TCOLOR_AG3)
#define VIU_OSD1_BLK0_CFG_W0 0x1a1b 	///../ucode/register.h:6715
#define P_VIU_OSD1_BLK0_CFG_W0 		VCBUS_REG_ADDR(VIU_OSD1_BLK0_CFG_W0)
#define VIU_OSD1_BLK1_CFG_W0 0x1a1f 	///../ucode/register.h:6716
#define P_VIU_OSD1_BLK1_CFG_W0 		VCBUS_REG_ADDR(VIU_OSD1_BLK1_CFG_W0)
#define VIU_OSD1_BLK2_CFG_W0 0x1a23 	///../ucode/register.h:6717
#define P_VIU_OSD1_BLK2_CFG_W0 		VCBUS_REG_ADDR(VIU_OSD1_BLK2_CFG_W0)
#define VIU_OSD1_BLK3_CFG_W0 0x1a27 	///../ucode/register.h:6718
#define P_VIU_OSD1_BLK3_CFG_W0 		VCBUS_REG_ADDR(VIU_OSD1_BLK3_CFG_W0)
#define VIU_OSD1_BLK0_CFG_W1 0x1a1c 	///../ucode/register.h:6723
#define P_VIU_OSD1_BLK0_CFG_W1 		VCBUS_REG_ADDR(VIU_OSD1_BLK0_CFG_W1)
#define VIU_OSD1_BLK1_CFG_W1 0x1a20 	///../ucode/register.h:6724
#define P_VIU_OSD1_BLK1_CFG_W1 		VCBUS_REG_ADDR(VIU_OSD1_BLK1_CFG_W1)
#define VIU_OSD1_BLK2_CFG_W1 0x1a24 	///../ucode/register.h:6725
#define P_VIU_OSD1_BLK2_CFG_W1 		VCBUS_REG_ADDR(VIU_OSD1_BLK2_CFG_W1)
#define VIU_OSD1_BLK3_CFG_W1 0x1a28 	///../ucode/register.h:6726
#define P_VIU_OSD1_BLK3_CFG_W1 		VCBUS_REG_ADDR(VIU_OSD1_BLK3_CFG_W1)
#define VIU_OSD1_BLK0_CFG_W2 0x1a1d 	///../ucode/register.h:6731
#define P_VIU_OSD1_BLK0_CFG_W2 		VCBUS_REG_ADDR(VIU_OSD1_BLK0_CFG_W2)
#define VIU_OSD1_BLK1_CFG_W2 0x1a21 	///../ucode/register.h:6732
#define P_VIU_OSD1_BLK1_CFG_W2 		VCBUS_REG_ADDR(VIU_OSD1_BLK1_CFG_W2)
#define VIU_OSD1_BLK2_CFG_W2 0x1a25 	///../ucode/register.h:6733
#define P_VIU_OSD1_BLK2_CFG_W2 		VCBUS_REG_ADDR(VIU_OSD1_BLK2_CFG_W2)
#define VIU_OSD1_BLK3_CFG_W2 0x1a29 	///../ucode/register.h:6734
#define P_VIU_OSD1_BLK3_CFG_W2 		VCBUS_REG_ADDR(VIU_OSD1_BLK3_CFG_W2)
#define VIU_OSD1_BLK0_CFG_W3 0x1a1e 	///../ucode/register.h:6739
#define P_VIU_OSD1_BLK0_CFG_W3 		VCBUS_REG_ADDR(VIU_OSD1_BLK0_CFG_W3)
#define VIU_OSD1_BLK1_CFG_W3 0x1a22 	///../ucode/register.h:6740
#define P_VIU_OSD1_BLK1_CFG_W3 		VCBUS_REG_ADDR(VIU_OSD1_BLK1_CFG_W3)
#define VIU_OSD1_BLK2_CFG_W3 0x1a26 	///../ucode/register.h:6741
#define P_VIU_OSD1_BLK2_CFG_W3 		VCBUS_REG_ADDR(VIU_OSD1_BLK2_CFG_W3)
#define VIU_OSD1_BLK3_CFG_W3 0x1a2a 	///../ucode/register.h:6742
#define P_VIU_OSD1_BLK3_CFG_W3 		VCBUS_REG_ADDR(VIU_OSD1_BLK3_CFG_W3)
#define VIU_OSD1_BLK0_CFG_W4 0x1a13 	///../ucode/register.h:6747
#define P_VIU_OSD1_BLK0_CFG_W4 		VCBUS_REG_ADDR(VIU_OSD1_BLK0_CFG_W4)
#define VIU_OSD1_BLK1_CFG_W4 0x1a14 	///../ucode/register.h:6748
#define P_VIU_OSD1_BLK1_CFG_W4 		VCBUS_REG_ADDR(VIU_OSD1_BLK1_CFG_W4)
#define VIU_OSD1_BLK2_CFG_W4 0x1a15 	///../ucode/register.h:6749
#define P_VIU_OSD1_BLK2_CFG_W4 		VCBUS_REG_ADDR(VIU_OSD1_BLK2_CFG_W4)
#define VIU_OSD1_BLK3_CFG_W4 0x1a16 	///../ucode/register.h:6750
#define P_VIU_OSD1_BLK3_CFG_W4 		VCBUS_REG_ADDR(VIU_OSD1_BLK3_CFG_W4)
#define VIU_OSD1_FIFO_CTRL_STAT 0x1a2b 	///../ucode/register.h:6766
#define P_VIU_OSD1_FIFO_CTRL_STAT 		VCBUS_REG_ADDR(VIU_OSD1_FIFO_CTRL_STAT)
#define VIU_OSD1_TEST_RDDATA 0x1a2c 	///../ucode/register.h:6771
#define P_VIU_OSD1_TEST_RDDATA 		VCBUS_REG_ADDR(VIU_OSD1_TEST_RDDATA)
#define VIU_OSD1_PROT_CTRL 0x1a2e 	///../ucode/register.h:6774
#define P_VIU_OSD1_PROT_CTRL 		VCBUS_REG_ADDR(VIU_OSD1_PROT_CTRL)
#define VIU_OSD2_CTRL_STAT 0x1a30 	///../ucode/register.h:6795
#define P_VIU_OSD2_CTRL_STAT 		VCBUS_REG_ADDR(VIU_OSD2_CTRL_STAT)
#define VIU_OSD2_CTRL_STAT2 0x1a4d 	///../ucode/register.h:6804
#define P_VIU_OSD2_CTRL_STAT2 		VCBUS_REG_ADDR(VIU_OSD2_CTRL_STAT2)
#define VIU_OSD2_COLOR_ADDR 0x1a31 	///../ucode/register.h:6808
#define P_VIU_OSD2_COLOR_ADDR 		VCBUS_REG_ADDR(VIU_OSD2_COLOR_ADDR)
#define VIU_OSD2_COLOR 0x1a32 	///../ucode/register.h:6813
#define P_VIU_OSD2_COLOR 		VCBUS_REG_ADDR(VIU_OSD2_COLOR)
#define VIU_OSD2_HL1_H_START_END 0x1a33 	///../ucode/register.h:6818
#define P_VIU_OSD2_HL1_H_START_END 		VCBUS_REG_ADDR(VIU_OSD2_HL1_H_START_END)
#define VIU_OSD2_HL1_V_START_END 0x1a34 	///../ucode/register.h:6819
#define P_VIU_OSD2_HL1_V_START_END 		VCBUS_REG_ADDR(VIU_OSD2_HL1_V_START_END)
#define VIU_OSD2_HL2_H_START_END 0x1a35 	///../ucode/register.h:6820
#define P_VIU_OSD2_HL2_H_START_END 		VCBUS_REG_ADDR(VIU_OSD2_HL2_H_START_END)
#define VIU_OSD2_HL2_V_START_END 0x1a36 	///../ucode/register.h:6821
#define P_VIU_OSD2_HL2_V_START_END 		VCBUS_REG_ADDR(VIU_OSD2_HL2_V_START_END)
#define VIU_OSD2_TCOLOR_AG0 0x1a37 	///../ucode/register.h:6826
#define P_VIU_OSD2_TCOLOR_AG0 		VCBUS_REG_ADDR(VIU_OSD2_TCOLOR_AG0)
#define VIU_OSD2_TCOLOR_AG1 0x1a38 	///../ucode/register.h:6827
#define P_VIU_OSD2_TCOLOR_AG1 		VCBUS_REG_ADDR(VIU_OSD2_TCOLOR_AG1)
#define VIU_OSD2_TCOLOR_AG2 0x1a39 	///../ucode/register.h:6828
#define P_VIU_OSD2_TCOLOR_AG2 		VCBUS_REG_ADDR(VIU_OSD2_TCOLOR_AG2)
#define VIU_OSD2_TCOLOR_AG3 0x1a3a 	///../ucode/register.h:6829
#define P_VIU_OSD2_TCOLOR_AG3 		VCBUS_REG_ADDR(VIU_OSD2_TCOLOR_AG3)
#define VIU_OSD2_BLK0_CFG_W0 0x1a3b 	///../ucode/register.h:6843
#define P_VIU_OSD2_BLK0_CFG_W0 		VCBUS_REG_ADDR(VIU_OSD2_BLK0_CFG_W0)
#define VIU_OSD2_BLK1_CFG_W0 0x1a3f 	///../ucode/register.h:6844
#define P_VIU_OSD2_BLK1_CFG_W0 		VCBUS_REG_ADDR(VIU_OSD2_BLK1_CFG_W0)
#define VIU_OSD2_BLK2_CFG_W0 0x1a43 	///../ucode/register.h:6845
#define P_VIU_OSD2_BLK2_CFG_W0 		VCBUS_REG_ADDR(VIU_OSD2_BLK2_CFG_W0)
#define VIU_OSD2_BLK3_CFG_W0 0x1a47 	///../ucode/register.h:6846
#define P_VIU_OSD2_BLK3_CFG_W0 		VCBUS_REG_ADDR(VIU_OSD2_BLK3_CFG_W0)
#define VIU_OSD2_BLK0_CFG_W1 0x1a3c 	///../ucode/register.h:6851
#define P_VIU_OSD2_BLK0_CFG_W1 		VCBUS_REG_ADDR(VIU_OSD2_BLK0_CFG_W1)
#define VIU_OSD2_BLK1_CFG_W1 0x1a40 	///../ucode/register.h:6852
#define P_VIU_OSD2_BLK1_CFG_W1 		VCBUS_REG_ADDR(VIU_OSD2_BLK1_CFG_W1)
#define VIU_OSD2_BLK2_CFG_W1 0x1a44 	///../ucode/register.h:6853
#define P_VIU_OSD2_BLK2_CFG_W1 		VCBUS_REG_ADDR(VIU_OSD2_BLK2_CFG_W1)
#define VIU_OSD2_BLK3_CFG_W1 0x1a48 	///../ucode/register.h:6854
#define P_VIU_OSD2_BLK3_CFG_W1 		VCBUS_REG_ADDR(VIU_OSD2_BLK3_CFG_W1)
#define VIU_OSD2_BLK0_CFG_W2 0x1a3d 	///../ucode/register.h:6859
#define P_VIU_OSD2_BLK0_CFG_W2 		VCBUS_REG_ADDR(VIU_OSD2_BLK0_CFG_W2)
#define VIU_OSD2_BLK1_CFG_W2 0x1a41 	///../ucode/register.h:6860
#define P_VIU_OSD2_BLK1_CFG_W2 		VCBUS_REG_ADDR(VIU_OSD2_BLK1_CFG_W2)
#define VIU_OSD2_BLK2_CFG_W2 0x1a45 	///../ucode/register.h:6861
#define P_VIU_OSD2_BLK2_CFG_W2 		VCBUS_REG_ADDR(VIU_OSD2_BLK2_CFG_W2)
#define VIU_OSD2_BLK3_CFG_W2 0x1a49 	///../ucode/register.h:6862
#define P_VIU_OSD2_BLK3_CFG_W2 		VCBUS_REG_ADDR(VIU_OSD2_BLK3_CFG_W2)
#define VIU_OSD2_BLK0_CFG_W3 0x1a3e 	///../ucode/register.h:6867
#define P_VIU_OSD2_BLK0_CFG_W3 		VCBUS_REG_ADDR(VIU_OSD2_BLK0_CFG_W3)
#define VIU_OSD2_BLK1_CFG_W3 0x1a42 	///../ucode/register.h:6868
#define P_VIU_OSD2_BLK1_CFG_W3 		VCBUS_REG_ADDR(VIU_OSD2_BLK1_CFG_W3)
#define VIU_OSD2_BLK2_CFG_W3 0x1a46 	///../ucode/register.h:6869
#define P_VIU_OSD2_BLK2_CFG_W3 		VCBUS_REG_ADDR(VIU_OSD2_BLK2_CFG_W3)
#define VIU_OSD2_BLK3_CFG_W3 0x1a4a 	///../ucode/register.h:6870
#define P_VIU_OSD2_BLK3_CFG_W3 		VCBUS_REG_ADDR(VIU_OSD2_BLK3_CFG_W3)
#define VIU_OSD2_BLK0_CFG_W4 0x1a64 	///../ucode/register.h:6875
#define P_VIU_OSD2_BLK0_CFG_W4 		VCBUS_REG_ADDR(VIU_OSD2_BLK0_CFG_W4)
#define VIU_OSD2_BLK1_CFG_W4 0x1a65 	///../ucode/register.h:6876
#define P_VIU_OSD2_BLK1_CFG_W4 		VCBUS_REG_ADDR(VIU_OSD2_BLK1_CFG_W4)
#define VIU_OSD2_BLK2_CFG_W4 0x1a66 	///../ucode/register.h:6877
#define P_VIU_OSD2_BLK2_CFG_W4 		VCBUS_REG_ADDR(VIU_OSD2_BLK2_CFG_W4)
#define VIU_OSD2_BLK3_CFG_W4 0x1a67 	///../ucode/register.h:6878
#define P_VIU_OSD2_BLK3_CFG_W4 		VCBUS_REG_ADDR(VIU_OSD2_BLK3_CFG_W4)
#define VIU_OSD2_FIFO_CTRL_STAT 0x1a4b 	///../ucode/register.h:6894
#define P_VIU_OSD2_FIFO_CTRL_STAT 		VCBUS_REG_ADDR(VIU_OSD2_FIFO_CTRL_STAT)
#define VIU_OSD2_TEST_RDDATA 0x1a4c 	///../ucode/register.h:6899
#define P_VIU_OSD2_TEST_RDDATA 		VCBUS_REG_ADDR(VIU_OSD2_TEST_RDDATA)
#define VIU_OSD2_PROT_CTRL 0x1a4e 	///../ucode/register.h:6902
#define P_VIU_OSD2_PROT_CTRL 		VCBUS_REG_ADDR(VIU_OSD2_PROT_CTRL)
#define VD1_IF0_GEN_REG 0x1a50 	///../ucode/register.h:6906
#define P_VD1_IF0_GEN_REG 		VCBUS_REG_ADDR(VD1_IF0_GEN_REG)
#define VD1_IF0_CANVAS0 0x1a51 	///../ucode/register.h:6907
#define P_VD1_IF0_CANVAS0 		VCBUS_REG_ADDR(VD1_IF0_CANVAS0)
#define VD1_IF0_CANVAS1 0x1a52 	///../ucode/register.h:6908
#define P_VD1_IF0_CANVAS1 		VCBUS_REG_ADDR(VD1_IF0_CANVAS1)
#define VD1_IF0_LUMA_X0 0x1a53 	///../ucode/register.h:6909
#define P_VD1_IF0_LUMA_X0 		VCBUS_REG_ADDR(VD1_IF0_LUMA_X0)
#define VD1_IF0_LUMA_Y0 0x1a54 	///../ucode/register.h:6910
#define P_VD1_IF0_LUMA_Y0 		VCBUS_REG_ADDR(VD1_IF0_LUMA_Y0)
#define VD1_IF0_CHROMA_X0 0x1a55 	///../ucode/register.h:6911
#define P_VD1_IF0_CHROMA_X0 		VCBUS_REG_ADDR(VD1_IF0_CHROMA_X0)
#define VD1_IF0_CHROMA_Y0 0x1a56 	///../ucode/register.h:6912
#define P_VD1_IF0_CHROMA_Y0 		VCBUS_REG_ADDR(VD1_IF0_CHROMA_Y0)
#define VD1_IF0_LUMA_X1 0x1a57 	///../ucode/register.h:6913
#define P_VD1_IF0_LUMA_X1 		VCBUS_REG_ADDR(VD1_IF0_LUMA_X1)
#define VD1_IF0_LUMA_Y1 0x1a58 	///../ucode/register.h:6914
#define P_VD1_IF0_LUMA_Y1 		VCBUS_REG_ADDR(VD1_IF0_LUMA_Y1)
#define VD1_IF0_CHROMA_X1 0x1a59 	///../ucode/register.h:6915
#define P_VD1_IF0_CHROMA_X1 		VCBUS_REG_ADDR(VD1_IF0_CHROMA_X1)
#define VD1_IF0_CHROMA_Y1 0x1a5a 	///../ucode/register.h:6916
#define P_VD1_IF0_CHROMA_Y1 		VCBUS_REG_ADDR(VD1_IF0_CHROMA_Y1)
#define VD1_IF0_RPT_LOOP 0x1a5b 	///../ucode/register.h:6917
#define P_VD1_IF0_RPT_LOOP 		VCBUS_REG_ADDR(VD1_IF0_RPT_LOOP)
#define VD1_IF0_LUMA0_RPT_PAT 0x1a5c 	///../ucode/register.h:6918
#define P_VD1_IF0_LUMA0_RPT_PAT 		VCBUS_REG_ADDR(VD1_IF0_LUMA0_RPT_PAT)
#define VD1_IF0_CHROMA0_RPT_PAT 0x1a5d 	///../ucode/register.h:6919
#define P_VD1_IF0_CHROMA0_RPT_PAT 		VCBUS_REG_ADDR(VD1_IF0_CHROMA0_RPT_PAT)
#define VD1_IF0_LUMA1_RPT_PAT 0x1a5e 	///../ucode/register.h:6920
#define P_VD1_IF0_LUMA1_RPT_PAT 		VCBUS_REG_ADDR(VD1_IF0_LUMA1_RPT_PAT)
#define VD1_IF0_CHROMA1_RPT_PAT 0x1a5f 	///../ucode/register.h:6921
#define P_VD1_IF0_CHROMA1_RPT_PAT 		VCBUS_REG_ADDR(VD1_IF0_CHROMA1_RPT_PAT)
#define VD1_IF0_LUMA_PSEL 0x1a60 	///../ucode/register.h:6922
#define P_VD1_IF0_LUMA_PSEL 		VCBUS_REG_ADDR(VD1_IF0_LUMA_PSEL)
#define VD1_IF0_CHROMA_PSEL 0x1a61 	///../ucode/register.h:6923
#define P_VD1_IF0_CHROMA_PSEL 		VCBUS_REG_ADDR(VD1_IF0_CHROMA_PSEL)
#define VD1_IF0_DUMMY_PIXEL 0x1a62 	///../ucode/register.h:6924
#define P_VD1_IF0_DUMMY_PIXEL 		VCBUS_REG_ADDR(VD1_IF0_DUMMY_PIXEL)
#define VD1_IF0_LUMA_FIFO_SIZE 0x1a63 	///../ucode/register.h:6925
#define P_VD1_IF0_LUMA_FIFO_SIZE 		VCBUS_REG_ADDR(VD1_IF0_LUMA_FIFO_SIZE)
#define VD1_IF0_RANGE_MAP_Y 0x1a6a 	///../ucode/register.h:6926
#define P_VD1_IF0_RANGE_MAP_Y 		VCBUS_REG_ADDR(VD1_IF0_RANGE_MAP_Y)
#define VD1_IF0_RANGE_MAP_CB 0x1a6b 	///../ucode/register.h:6927
#define P_VD1_IF0_RANGE_MAP_CB 		VCBUS_REG_ADDR(VD1_IF0_RANGE_MAP_CB)
#define VD1_IF0_RANGE_MAP_CR 0x1a6c 	///../ucode/register.h:6928
#define P_VD1_IF0_RANGE_MAP_CR 		VCBUS_REG_ADDR(VD1_IF0_RANGE_MAP_CR)
#define VD1_IF0_GEN_REG2 0x1a6d 	///../ucode/register.h:6929
#define P_VD1_IF0_GEN_REG2 		VCBUS_REG_ADDR(VD1_IF0_GEN_REG2)
#define VD1_IF0_PROT_CNTL 0x1a6e 	///../ucode/register.h:6930
#define P_VD1_IF0_PROT_CNTL 		VCBUS_REG_ADDR(VD1_IF0_PROT_CNTL)
#define VIU_VD1_FMT_CTRL 0x1a68 	///../ucode/register.h:6947
#define P_VIU_VD1_FMT_CTRL 		VCBUS_REG_ADDR(VIU_VD1_FMT_CTRL)
#define VIU_VD1_FMT_W 0x1a69 	///../ucode/register.h:6950
#define P_VIU_VD1_FMT_W 		VCBUS_REG_ADDR(VIU_VD1_FMT_W)
#define VD2_IF0_GEN_REG 0x1a70 	///../ucode/register.h:6954
#define P_VD2_IF0_GEN_REG 		VCBUS_REG_ADDR(VD2_IF0_GEN_REG)
#define VD2_IF0_CANVAS0 0x1a71 	///../ucode/register.h:6955
#define P_VD2_IF0_CANVAS0 		VCBUS_REG_ADDR(VD2_IF0_CANVAS0)
#define VD2_IF0_CANVAS1 0x1a72 	///../ucode/register.h:6956
#define P_VD2_IF0_CANVAS1 		VCBUS_REG_ADDR(VD2_IF0_CANVAS1)
#define VD2_IF0_LUMA_X0 0x1a73 	///../ucode/register.h:6957
#define P_VD2_IF0_LUMA_X0 		VCBUS_REG_ADDR(VD2_IF0_LUMA_X0)
#define VD2_IF0_LUMA_Y0 0x1a74 	///../ucode/register.h:6958
#define P_VD2_IF0_LUMA_Y0 		VCBUS_REG_ADDR(VD2_IF0_LUMA_Y0)
#define VD2_IF0_CHROMA_X0 0x1a75 	///../ucode/register.h:6959
#define P_VD2_IF0_CHROMA_X0 		VCBUS_REG_ADDR(VD2_IF0_CHROMA_X0)
#define VD2_IF0_CHROMA_Y0 0x1a76 	///../ucode/register.h:6960
#define P_VD2_IF0_CHROMA_Y0 		VCBUS_REG_ADDR(VD2_IF0_CHROMA_Y0)
#define VD2_IF0_LUMA_X1 0x1a77 	///../ucode/register.h:6961
#define P_VD2_IF0_LUMA_X1 		VCBUS_REG_ADDR(VD2_IF0_LUMA_X1)
#define VD2_IF0_LUMA_Y1 0x1a78 	///../ucode/register.h:6962
#define P_VD2_IF0_LUMA_Y1 		VCBUS_REG_ADDR(VD2_IF0_LUMA_Y1)
#define VD2_IF0_CHROMA_X1 0x1a79 	///../ucode/register.h:6963
#define P_VD2_IF0_CHROMA_X1 		VCBUS_REG_ADDR(VD2_IF0_CHROMA_X1)
#define VD2_IF0_CHROMA_Y1 0x1a7a 	///../ucode/register.h:6964
#define P_VD2_IF0_CHROMA_Y1 		VCBUS_REG_ADDR(VD2_IF0_CHROMA_Y1)
#define VD2_IF0_RPT_LOOP 0x1a7b 	///../ucode/register.h:6965
#define P_VD2_IF0_RPT_LOOP 		VCBUS_REG_ADDR(VD2_IF0_RPT_LOOP)
#define VD2_IF0_LUMA0_RPT_PAT 0x1a7c 	///../ucode/register.h:6966
#define P_VD2_IF0_LUMA0_RPT_PAT 		VCBUS_REG_ADDR(VD2_IF0_LUMA0_RPT_PAT)
#define VD2_IF0_CHROMA0_RPT_PAT 0x1a7d 	///../ucode/register.h:6967
#define P_VD2_IF0_CHROMA0_RPT_PAT 		VCBUS_REG_ADDR(VD2_IF0_CHROMA0_RPT_PAT)
#define VD2_IF0_LUMA1_RPT_PAT 0x1a7e 	///../ucode/register.h:6968
#define P_VD2_IF0_LUMA1_RPT_PAT 		VCBUS_REG_ADDR(VD2_IF0_LUMA1_RPT_PAT)
#define VD2_IF0_CHROMA1_RPT_PAT 0x1a7f 	///../ucode/register.h:6969
#define P_VD2_IF0_CHROMA1_RPT_PAT 		VCBUS_REG_ADDR(VD2_IF0_CHROMA1_RPT_PAT)
#define VD2_IF0_LUMA_PSEL 0x1a80 	///../ucode/register.h:6970
#define P_VD2_IF0_LUMA_PSEL 		VCBUS_REG_ADDR(VD2_IF0_LUMA_PSEL)
#define VD2_IF0_CHROMA_PSEL 0x1a81 	///../ucode/register.h:6971
#define P_VD2_IF0_CHROMA_PSEL 		VCBUS_REG_ADDR(VD2_IF0_CHROMA_PSEL)
#define VD2_IF0_DUMMY_PIXEL 0x1a82 	///../ucode/register.h:6972
#define P_VD2_IF0_DUMMY_PIXEL 		VCBUS_REG_ADDR(VD2_IF0_DUMMY_PIXEL)
#define VD2_IF0_LUMA_FIFO_SIZE 0x1a83 	///../ucode/register.h:6973
#define P_VD2_IF0_LUMA_FIFO_SIZE 		VCBUS_REG_ADDR(VD2_IF0_LUMA_FIFO_SIZE)
#define VD2_IF0_RANGE_MAP_Y 0x1a8a 	///../ucode/register.h:6974
#define P_VD2_IF0_RANGE_MAP_Y 		VCBUS_REG_ADDR(VD2_IF0_RANGE_MAP_Y)
#define VD2_IF0_RANGE_MAP_CB 0x1a8b 	///../ucode/register.h:6975
#define P_VD2_IF0_RANGE_MAP_CB 		VCBUS_REG_ADDR(VD2_IF0_RANGE_MAP_CB)
#define VD2_IF0_RANGE_MAP_CR 0x1a8c 	///../ucode/register.h:6976
#define P_VD2_IF0_RANGE_MAP_CR 		VCBUS_REG_ADDR(VD2_IF0_RANGE_MAP_CR)
#define VD2_IF0_GEN_REG2 0x1a8d 	///../ucode/register.h:6977
#define P_VD2_IF0_GEN_REG2 		VCBUS_REG_ADDR(VD2_IF0_GEN_REG2)
#define VD2_IF0_PROT_CNTL 0x1a8e 	///../ucode/register.h:6978
#define P_VD2_IF0_PROT_CNTL 		VCBUS_REG_ADDR(VD2_IF0_PROT_CNTL)
#define VIU_VD2_FMT_CTRL 0x1a88 	///../ucode/register.h:6992
#define P_VIU_VD2_FMT_CTRL 		VCBUS_REG_ADDR(VIU_VD2_FMT_CTRL)
#define VIU_VD2_FMT_W 0x1a89 	///../ucode/register.h:6995
#define P_VIU_VD2_FMT_W 		VCBUS_REG_ADDR(VIU_VD2_FMT_W)
#define LDIM_STTS_GCLK_CTRL0 0x1a90 	///../ucode/register.h:6997
#define P_LDIM_STTS_GCLK_CTRL0 		VCBUS_REG_ADDR(LDIM_STTS_GCLK_CTRL0)
#define LDIM_STTS_CTRL0 0x1a91 	///../ucode/register.h:6998
#define P_LDIM_STTS_CTRL0 		VCBUS_REG_ADDR(LDIM_STTS_CTRL0)
#define LDIM_STTS_WIDTHM1_HEIGHTM1 0x1a92 	///../ucode/register.h:6999
#define P_LDIM_STTS_WIDTHM1_HEIGHTM1 		VCBUS_REG_ADDR(LDIM_STTS_WIDTHM1_HEIGHTM1)
#define LDIM_STTS_MATRIX_COEF00_01 0x1a93 	///../ucode/register.h:7000
#define P_LDIM_STTS_MATRIX_COEF00_01 		VCBUS_REG_ADDR(LDIM_STTS_MATRIX_COEF00_01)
#define LDIM_STTS_MATRIX_COEF02_10 0x1a94 	///../ucode/register.h:7001
#define P_LDIM_STTS_MATRIX_COEF02_10 		VCBUS_REG_ADDR(LDIM_STTS_MATRIX_COEF02_10)
#define LDIM_STTS_MATRIX_COEF11_12 0x1a95 	///../ucode/register.h:7002
#define P_LDIM_STTS_MATRIX_COEF11_12 		VCBUS_REG_ADDR(LDIM_STTS_MATRIX_COEF11_12)
#define LDIM_STTS_MATRIX_COEF20_21 0x1a96 	///../ucode/register.h:7003
#define P_LDIM_STTS_MATRIX_COEF20_21 		VCBUS_REG_ADDR(LDIM_STTS_MATRIX_COEF20_21)
#define LDIM_STTS_MATRIX_COEF22 0x1a97 	///../ucode/register.h:7004
#define P_LDIM_STTS_MATRIX_COEF22 		VCBUS_REG_ADDR(LDIM_STTS_MATRIX_COEF22)
#define LDIM_STTS_MATRIX_OFFSET0_1 0x1a98 	///../ucode/register.h:7005
#define P_LDIM_STTS_MATRIX_OFFSET0_1 		VCBUS_REG_ADDR(LDIM_STTS_MATRIX_OFFSET0_1)
#define LDIM_STTS_MATRIX_OFFSET2 0x1a99 	///../ucode/register.h:7006
#define P_LDIM_STTS_MATRIX_OFFSET2 		VCBUS_REG_ADDR(LDIM_STTS_MATRIX_OFFSET2)
#define LDIM_STTS_MATRIX_PRE_OFFSET0_1 0x1a9a 	///../ucode/register.h:7007
#define P_LDIM_STTS_MATRIX_PRE_OFFSET0_1 		VCBUS_REG_ADDR(LDIM_STTS_MATRIX_PRE_OFFSET0_1)
#define LDIM_STTS_MATRIX_PRE_OFFSET2 0x1a9b 	///../ucode/register.h:7008
#define P_LDIM_STTS_MATRIX_PRE_OFFSET2 		VCBUS_REG_ADDR(LDIM_STTS_MATRIX_PRE_OFFSET2)
#define LDIM_STTS_MATRIX_HL_COLOR 0x1a9c 	///../ucode/register.h:7009
#define P_LDIM_STTS_MATRIX_HL_COLOR 		VCBUS_REG_ADDR(LDIM_STTS_MATRIX_HL_COLOR)
#define LDIM_STTS_MATRIX_PROBE_POS 0x1a9d 	///../ucode/register.h:7010
#define P_LDIM_STTS_MATRIX_PROBE_POS 		VCBUS_REG_ADDR(LDIM_STTS_MATRIX_PROBE_POS)
#define LDIM_STTS_MATRIX_PROBE_COLOR 0x1a9e 	///../ucode/register.h:7012
#define P_LDIM_STTS_MATRIX_PROBE_COLOR 		VCBUS_REG_ADDR(LDIM_STTS_MATRIX_PROBE_COLOR)
#define LDIM_STTS_HIST_REGION_IDX 0x1aa0 	///../ucode/register.h:7025
#define P_LDIM_STTS_HIST_REGION_IDX 		VCBUS_REG_ADDR(LDIM_STTS_HIST_REGION_IDX)
#define LDIM_STTS_HIST_SET_REGION 0x1aa1 	///../ucode/register.h:7048
#define P_LDIM_STTS_HIST_SET_REGION 		VCBUS_REG_ADDR(LDIM_STTS_HIST_SET_REGION)
#define LDIM_STTS_HIST_READ_REGION 0x1aa2 	///../ucode/register.h:7061
#define P_LDIM_STTS_HIST_READ_REGION 		VCBUS_REG_ADDR(LDIM_STTS_HIST_READ_REGION)
#define DI_PRE_CTRL 0x1700 	///../ucode/register.h:7066
#define P_DI_PRE_CTRL 		VCBUS_REG_ADDR(DI_PRE_CTRL)
#define DI_POST_CTRL 0x1701 	///../ucode/register.h:7089
#define P_DI_POST_CTRL 		VCBUS_REG_ADDR(DI_POST_CTRL)
#define DI_POST_SIZE 0x1702 	///../ucode/register.h:7108
#define P_DI_POST_SIZE 		VCBUS_REG_ADDR(DI_POST_SIZE)
#define DI_PRE_SIZE 0x1703 	///../ucode/register.h:7111
#define P_DI_PRE_SIZE 		VCBUS_REG_ADDR(DI_PRE_SIZE)
#define DI_EI_CTRL0 0x1704 	///../ucode/register.h:7114
#define P_DI_EI_CTRL0 		VCBUS_REG_ADDR(DI_EI_CTRL0)
#define DI_EI_CTRL1 0x1705 	///../ucode/register.h:7120
#define P_DI_EI_CTRL1 		VCBUS_REG_ADDR(DI_EI_CTRL1)
#define DI_EI_CTRL2 0x1706 	///../ucode/register.h:7125
#define P_DI_EI_CTRL2 		VCBUS_REG_ADDR(DI_EI_CTRL2)
#define DI_NR_CTRL0 0x1707 	///../ucode/register.h:7130
#define P_DI_NR_CTRL0 		VCBUS_REG_ADDR(DI_NR_CTRL0)
#define DI_NR_CTRL1 0x1708 	///../ucode/register.h:7133
#define P_DI_NR_CTRL1 		VCBUS_REG_ADDR(DI_NR_CTRL1)
#define DI_NR_CTRL2 0x1709 	///../ucode/register.h:7139
#define P_DI_NR_CTRL2 		VCBUS_REG_ADDR(DI_NR_CTRL2)
#define DI_NR_CTRL3 0x170a 	///../ucode/register.h:7144
#define P_DI_NR_CTRL3 		VCBUS_REG_ADDR(DI_NR_CTRL3)
#define DI_MTN_CTRL 0x170b 	///../ucode/register.h:7146
#define P_DI_MTN_CTRL 		VCBUS_REG_ADDR(DI_MTN_CTRL)
#define DI_MTN_CTRL1 0x170c 	///../ucode/register.h:7154
#define P_DI_MTN_CTRL1 		VCBUS_REG_ADDR(DI_MTN_CTRL1)
#define DI_BLEND_CTRL 0x170d 	///../ucode/register.h:7157
#define P_DI_BLEND_CTRL 		VCBUS_REG_ADDR(DI_BLEND_CTRL)
#define DI_BLEND_CTRL1 0x170e 	///../ucode/register.h:7177
#define P_DI_BLEND_CTRL1 		VCBUS_REG_ADDR(DI_BLEND_CTRL1)
#define DI_BLEND_CTRL2 0x170f 	///../ucode/register.h:7182
#define P_DI_BLEND_CTRL2 		VCBUS_REG_ADDR(DI_BLEND_CTRL2)
#define DI_BLEND_REG0_X 0x1710 	///../ucode/register.h:7185
#define P_DI_BLEND_REG0_X 		VCBUS_REG_ADDR(DI_BLEND_REG0_X)
#define DI_BLEND_REG0_Y 0x1711 	///../ucode/register.h:7188
#define P_DI_BLEND_REG0_Y 		VCBUS_REG_ADDR(DI_BLEND_REG0_Y)
#define DI_BLEND_REG1_X 0x1712 	///../ucode/register.h:7189
#define P_DI_BLEND_REG1_X 		VCBUS_REG_ADDR(DI_BLEND_REG1_X)
#define DI_BLEND_REG1_Y 0x1713 	///../ucode/register.h:7190
#define P_DI_BLEND_REG1_Y 		VCBUS_REG_ADDR(DI_BLEND_REG1_Y)
#define DI_BLEND_REG2_X 0x1714 	///../ucode/register.h:7191
#define P_DI_BLEND_REG2_X 		VCBUS_REG_ADDR(DI_BLEND_REG2_X)
#define DI_BLEND_REG2_Y 0x1715 	///../ucode/register.h:7192
#define P_DI_BLEND_REG2_Y 		VCBUS_REG_ADDR(DI_BLEND_REG2_Y)
#define DI_BLEND_REG3_X 0x1716 	///../ucode/register.h:7193
#define P_DI_BLEND_REG3_X 		VCBUS_REG_ADDR(DI_BLEND_REG3_X)
#define DI_BLEND_REG3_Y 0x1717 	///../ucode/register.h:7194
#define P_DI_BLEND_REG3_Y 		VCBUS_REG_ADDR(DI_BLEND_REG3_Y)
#define DI_CLKG_CTRL 0x1718 	///../ucode/register.h:7195
#define P_DI_CLKG_CTRL 		VCBUS_REG_ADDR(DI_CLKG_CTRL)
#define DI_EI_CTRL3 0x1719 	///../ucode/register.h:7200
#define P_DI_EI_CTRL3 		VCBUS_REG_ADDR(DI_EI_CTRL3)
#define DI_EI_CTRL4 0x171a 	///../ucode/register.h:7208
#define P_DI_EI_CTRL4 		VCBUS_REG_ADDR(DI_EI_CTRL4)
#define DI_EI_CTRL5 0x171b 	///../ucode/register.h:7217
#define P_DI_EI_CTRL5 		VCBUS_REG_ADDR(DI_EI_CTRL5)
#define DI_EI_CTRL6 0x171c 	///../ucode/register.h:7230
#define P_DI_EI_CTRL6 		VCBUS_REG_ADDR(DI_EI_CTRL6)
#define DI_EI_CTRL7 0x171d 	///../ucode/register.h:7236
#define P_DI_EI_CTRL7 		VCBUS_REG_ADDR(DI_EI_CTRL7)
#define DI_EI_CTRL8 0x171e 	///../ucode/register.h:7246
#define P_DI_EI_CTRL8 		VCBUS_REG_ADDR(DI_EI_CTRL8)
#define DI_EI_CTRL9 0x171f 	///../ucode/register.h:7258
#define P_DI_EI_CTRL9 		VCBUS_REG_ADDR(DI_EI_CTRL9)
#define DI_EI_CTRL10 0x1793 	///../ucode/register.h:7270
#define P_DI_EI_CTRL10 		VCBUS_REG_ADDR(DI_EI_CTRL10)
#define DI_EI_CTRL11 0x179e 	///../ucode/register.h:7284
#define P_DI_EI_CTRL11 		VCBUS_REG_ADDR(DI_EI_CTRL11)
#define DI_EI_CTRL12 0x179f 	///../ucode/register.h:7299
#define P_DI_EI_CTRL12 		VCBUS_REG_ADDR(DI_EI_CTRL12)
#define DI_EI_CTRL13 0x17a8 	///../ucode/register.h:7312
#define P_DI_EI_CTRL13 		VCBUS_REG_ADDR(DI_EI_CTRL13)
#define DI_EI_XWIN0 0x1798 	///../ucode/register.h:7318
#define P_DI_EI_XWIN0 		VCBUS_REG_ADDR(DI_EI_XWIN0)
#define DI_EI_XWIN1 0x1799 	///../ucode/register.h:7321
#define P_DI_EI_XWIN1 		VCBUS_REG_ADDR(DI_EI_XWIN1)
#define DI_MC_REG0_X 0x1720 	///../ucode/register.h:7323
#define P_DI_MC_REG0_X 		VCBUS_REG_ADDR(DI_MC_REG0_X)
#define DI_MC_REG0_Y 0x1721 	///../ucode/register.h:7326
#define P_DI_MC_REG0_Y 		VCBUS_REG_ADDR(DI_MC_REG0_Y)
#define DI_MC_REG1_X 0x1722 	///../ucode/register.h:7327
#define P_DI_MC_REG1_X 		VCBUS_REG_ADDR(DI_MC_REG1_X)
#define DI_MC_REG1_Y 0x1723 	///../ucode/register.h:7328
#define P_DI_MC_REG1_Y 		VCBUS_REG_ADDR(DI_MC_REG1_Y)
#define DI_MC_REG2_X 0x1724 	///../ucode/register.h:7329
#define P_DI_MC_REG2_X 		VCBUS_REG_ADDR(DI_MC_REG2_X)
#define DI_MC_REG2_Y 0x1725 	///../ucode/register.h:7330
#define P_DI_MC_REG2_Y 		VCBUS_REG_ADDR(DI_MC_REG2_Y)
#define DI_MC_REG3_X 0x1726 	///../ucode/register.h:7331
#define P_DI_MC_REG3_X 		VCBUS_REG_ADDR(DI_MC_REG3_X)
#define DI_MC_REG3_Y 0x1727 	///../ucode/register.h:7332
#define P_DI_MC_REG3_Y 		VCBUS_REG_ADDR(DI_MC_REG3_Y)
#define DI_MC_REG4_X 0x1728 	///../ucode/register.h:7333
#define P_DI_MC_REG4_X 		VCBUS_REG_ADDR(DI_MC_REG4_X)
#define DI_MC_REG4_Y 0x1729 	///../ucode/register.h:7334
#define P_DI_MC_REG4_Y 		VCBUS_REG_ADDR(DI_MC_REG4_Y)
#define DI_MC_32LVL0 0x172a 	///../ucode/register.h:7335
#define P_DI_MC_32LVL0 		VCBUS_REG_ADDR(DI_MC_32LVL0)
#define DI_MC_32LVL1 0x172b 	///../ucode/register.h:7340
#define P_DI_MC_32LVL1 		VCBUS_REG_ADDR(DI_MC_32LVL1)
#define DI_MC_22LVL0 0x172c 	///../ucode/register.h:7343
#define P_DI_MC_22LVL0 		VCBUS_REG_ADDR(DI_MC_22LVL0)
#define DI_MC_22LVL1 0x172d 	///../ucode/register.h:7346
#define P_DI_MC_22LVL1 		VCBUS_REG_ADDR(DI_MC_22LVL1)
#define DI_MC_22LVL2 0x172e 	///../ucode/register.h:7349
#define P_DI_MC_22LVL2 		VCBUS_REG_ADDR(DI_MC_22LVL2)
#define DI_MC_CTRL 0x172f 	///../ucode/register.h:7352
#define P_DI_MC_CTRL 		VCBUS_REG_ADDR(DI_MC_CTRL)
#define DI_INTR_CTRL 0x1730 	///../ucode/register.h:7358
#define P_DI_INTR_CTRL 		VCBUS_REG_ADDR(DI_INTR_CTRL)
#define DI_INFO_ADDR 0x1731 	///../ucode/register.h:7359
#define P_DI_INFO_ADDR 		VCBUS_REG_ADDR(DI_INFO_ADDR)
#define DI_INFO_DATA 0x1732 	///../ucode/register.h:7360
#define P_DI_INFO_DATA 		VCBUS_REG_ADDR(DI_INFO_DATA)
#define DI_PRE_HOLD 0x1733 	///../ucode/register.h:7361
#define P_DI_PRE_HOLD 		VCBUS_REG_ADDR(DI_PRE_HOLD)
#define DI_MTN_1_CTRL1 0x1740 	///../ucode/register.h:7362
#define P_DI_MTN_1_CTRL1 		VCBUS_REG_ADDR(DI_MTN_1_CTRL1)
#define DI_MTN_1_CTRL2 0x1741 	///../ucode/register.h:7371
#define P_DI_MTN_1_CTRL2 		VCBUS_REG_ADDR(DI_MTN_1_CTRL2)
#define DI_MTN_1_CTRL3 0x1742 	///../ucode/register.h:7376
#define P_DI_MTN_1_CTRL3 		VCBUS_REG_ADDR(DI_MTN_1_CTRL3)
#define DI_MTN_1_CTRL4 0x1743 	///../ucode/register.h:7381
#define P_DI_MTN_1_CTRL4 		VCBUS_REG_ADDR(DI_MTN_1_CTRL4)
#define DI_MTN_1_CTRL5 0x1744 	///../ucode/register.h:7386
#define P_DI_MTN_1_CTRL5 		VCBUS_REG_ADDR(DI_MTN_1_CTRL5)
#define DI_MTN_1_CTRL6 0x17a9 	///../ucode/register.h:7391
#define P_DI_MTN_1_CTRL6 		VCBUS_REG_ADDR(DI_MTN_1_CTRL6)
#define DI_MTN_1_CTRL7 0x17aa 	///../ucode/register.h:7396
#define P_DI_MTN_1_CTRL7 		VCBUS_REG_ADDR(DI_MTN_1_CTRL7)
#define DI_MTN_1_CTRL8 0x17ab 	///../ucode/register.h:7401
#define P_DI_MTN_1_CTRL8 		VCBUS_REG_ADDR(DI_MTN_1_CTRL8)
#define DI_MTN_1_CTRL9 0x17ac 	///../ucode/register.h:7406
#define P_DI_MTN_1_CTRL9 		VCBUS_REG_ADDR(DI_MTN_1_CTRL9)
#define DI_MTN_1_CTRL10 0x17ad 	///../ucode/register.h:7411
#define P_DI_MTN_1_CTRL10 		VCBUS_REG_ADDR(DI_MTN_1_CTRL10)
#define DI_MTN_1_CTRL11 0x17ae 	///../ucode/register.h:7416
#define P_DI_MTN_1_CTRL11 		VCBUS_REG_ADDR(DI_MTN_1_CTRL11)
#define DI_MTN_1_CTRL12 0x17af 	///../ucode/register.h:7421
#define P_DI_MTN_1_CTRL12 		VCBUS_REG_ADDR(DI_MTN_1_CTRL12)
#define DET3D_MOTN_CFG 0x1734 	///../ucode/register.h:7428
#define P_DET3D_MOTN_CFG 		VCBUS_REG_ADDR(DET3D_MOTN_CFG)
#define DET3D_CB_CFG 0x1735 	///../ucode/register.h:7429
#define P_DET3D_CB_CFG 		VCBUS_REG_ADDR(DET3D_CB_CFG)
#define DET3D_SPLT_CFG 0x1736 	///../ucode/register.h:7430
#define P_DET3D_SPLT_CFG 		VCBUS_REG_ADDR(DET3D_SPLT_CFG)
#define DET3D_HV_MUTE 0x1737 	///../ucode/register.h:7431
#define P_DET3D_HV_MUTE 		VCBUS_REG_ADDR(DET3D_HV_MUTE)
#define DET3D_MAT_STA_P1M1 0x1738 	///../ucode/register.h:7432
#define P_DET3D_MAT_STA_P1M1 		VCBUS_REG_ADDR(DET3D_MAT_STA_P1M1)
#define DET3D_MAT_STA_P1TH 0x1739 	///../ucode/register.h:7433
#define P_DET3D_MAT_STA_P1TH 		VCBUS_REG_ADDR(DET3D_MAT_STA_P1TH)
#define DET3D_MAT_STA_M1TH 0x173a 	///../ucode/register.h:7434
#define P_DET3D_MAT_STA_M1TH 		VCBUS_REG_ADDR(DET3D_MAT_STA_M1TH)
#define DET3D_MAT_STA_RSFT 0x173b 	///../ucode/register.h:7435
#define P_DET3D_MAT_STA_RSFT 		VCBUS_REG_ADDR(DET3D_MAT_STA_RSFT)
#define DET3D_MAT_SYMTC_TH 0x173c 	///../ucode/register.h:7436
#define P_DET3D_MAT_SYMTC_TH 		VCBUS_REG_ADDR(DET3D_MAT_SYMTC_TH)
#define DET3D_RO_DET_CB_HOR 0x173d 	///../ucode/register.h:7437
#define P_DET3D_RO_DET_CB_HOR 		VCBUS_REG_ADDR(DET3D_RO_DET_CB_HOR)
#define DET3D_RO_DET_CB_VER 0x173e 	///../ucode/register.h:7438
#define P_DET3D_RO_DET_CB_VER 		VCBUS_REG_ADDR(DET3D_RO_DET_CB_VER)
#define DET3D_RO_SPLT_HT 0x173f 	///../ucode/register.h:7439
#define P_DET3D_RO_SPLT_HT 		VCBUS_REG_ADDR(DET3D_RO_SPLT_HT)
#define NR2_MET_NM_CTRL 0x1745 	///../ucode/register.h:7442
#define P_NR2_MET_NM_CTRL 		VCBUS_REG_ADDR(NR2_MET_NM_CTRL)
#define NR2_MET_NM_YCTRL 0x1746 	///../ucode/register.h:7443
#define P_NR2_MET_NM_YCTRL 		VCBUS_REG_ADDR(NR2_MET_NM_YCTRL)
#define NR2_MET_NM_CCTRL 0x1747 	///../ucode/register.h:7444
#define P_NR2_MET_NM_CCTRL 		VCBUS_REG_ADDR(NR2_MET_NM_CCTRL)
#define NR2_MET_NM_TNR 0x1748 	///../ucode/register.h:7445
#define P_NR2_MET_NM_TNR 		VCBUS_REG_ADDR(NR2_MET_NM_TNR)
#define NR2_MET_NMFRM_TNR_YLEV 0x1749 	///../ucode/register.h:7446
#define P_NR2_MET_NMFRM_TNR_YLEV 		VCBUS_REG_ADDR(NR2_MET_NMFRM_TNR_YLEV)
#define NR2_MET_NMFRM_TNR_YCNT 0x174a 	///../ucode/register.h:7447
#define P_NR2_MET_NMFRM_TNR_YCNT 		VCBUS_REG_ADDR(NR2_MET_NMFRM_TNR_YCNT)
#define NR2_MET_NMFRM_TNR_CLEV 0x174b 	///../ucode/register.h:7448
#define P_NR2_MET_NMFRM_TNR_CLEV 		VCBUS_REG_ADDR(NR2_MET_NMFRM_TNR_CLEV)
#define NR2_MET_NMFRM_TNR_CCNT 0x174c 	///../ucode/register.h:7449
#define P_NR2_MET_NMFRM_TNR_CCNT 		VCBUS_REG_ADDR(NR2_MET_NMFRM_TNR_CCNT)
#define NR2_3DEN_MODE 0x174d 	///../ucode/register.h:7450
#define P_NR2_3DEN_MODE 		VCBUS_REG_ADDR(NR2_3DEN_MODE)
#define NR2_IIR_CTRL 0x174e 	///../ucode/register.h:7451
#define P_NR2_IIR_CTRL 		VCBUS_REG_ADDR(NR2_IIR_CTRL)
#define NR2_SW_EN 0x174f 	///../ucode/register.h:7452
#define P_NR2_SW_EN 		VCBUS_REG_ADDR(NR2_SW_EN)
#define NR2_FRM_SIZE 0x1750 	///../ucode/register.h:7453
#define P_NR2_FRM_SIZE 		VCBUS_REG_ADDR(NR2_FRM_SIZE)
#define NR2_SNR_SAD_CFG 0x1751 	///../ucode/register.h:7454
#define P_NR2_SNR_SAD_CFG 		VCBUS_REG_ADDR(NR2_SNR_SAD_CFG)
#define NR2_MATNR_SNR_OS 0x1752 	///../ucode/register.h:7455
#define P_NR2_MATNR_SNR_OS 		VCBUS_REG_ADDR(NR2_MATNR_SNR_OS)
#define NR2_MATNR_SNR_NRM_CFG 0x1753 	///../ucode/register.h:7456
#define P_NR2_MATNR_SNR_NRM_CFG 		VCBUS_REG_ADDR(NR2_MATNR_SNR_NRM_CFG)
#define NR2_MATNR_SNR_NRM_GAIN 0x1754 	///../ucode/register.h:7457
#define P_NR2_MATNR_SNR_NRM_GAIN 		VCBUS_REG_ADDR(NR2_MATNR_SNR_NRM_GAIN)
#define NR2_MATNR_SNR_LPF_CFG 0x1755 	///../ucode/register.h:7458
#define P_NR2_MATNR_SNR_LPF_CFG 		VCBUS_REG_ADDR(NR2_MATNR_SNR_LPF_CFG)
#define NR2_MATNR_SNR_USF_GAIN 0x1756 	///../ucode/register.h:7459
#define P_NR2_MATNR_SNR_USF_GAIN 		VCBUS_REG_ADDR(NR2_MATNR_SNR_USF_GAIN)
#define NR2_MATNR_SNR_EDGE2B 0x1757 	///../ucode/register.h:7460
#define P_NR2_MATNR_SNR_EDGE2B 		VCBUS_REG_ADDR(NR2_MATNR_SNR_EDGE2B)
#define NR2_MATNR_BETA_EGAIN 0x1758 	///../ucode/register.h:7461
#define P_NR2_MATNR_BETA_EGAIN 		VCBUS_REG_ADDR(NR2_MATNR_BETA_EGAIN)
#define NR2_MATNR_BETA_BRT 0x1759 	///../ucode/register.h:7462
#define P_NR2_MATNR_BETA_BRT 		VCBUS_REG_ADDR(NR2_MATNR_BETA_BRT)
#define NR2_MATNR_XBETA_CFG 0x175a 	///../ucode/register.h:7463
#define P_NR2_MATNR_XBETA_CFG 		VCBUS_REG_ADDR(NR2_MATNR_XBETA_CFG)
#define NR2_MATNR_YBETA_SCL 0x175b 	///../ucode/register.h:7464
#define P_NR2_MATNR_YBETA_SCL 		VCBUS_REG_ADDR(NR2_MATNR_YBETA_SCL)
#define NR2_MATNR_CBETA_SCL 0x175c 	///../ucode/register.h:7465
#define P_NR2_MATNR_CBETA_SCL 		VCBUS_REG_ADDR(NR2_MATNR_CBETA_SCL)
#define NR2_SNR_MASK 0x175d 	///../ucode/register.h:7466
#define P_NR2_SNR_MASK 		VCBUS_REG_ADDR(NR2_SNR_MASK)
#define NR2_SAD2NORM_LUT0 0x175e 	///../ucode/register.h:7467
#define P_NR2_SAD2NORM_LUT0 		VCBUS_REG_ADDR(NR2_SAD2NORM_LUT0)
#define NR2_SAD2NORM_LUT1 0x175f 	///../ucode/register.h:7468
#define P_NR2_SAD2NORM_LUT1 		VCBUS_REG_ADDR(NR2_SAD2NORM_LUT1)
#define NR2_SAD2NORM_LUT2 0x1760 	///../ucode/register.h:7469
#define P_NR2_SAD2NORM_LUT2 		VCBUS_REG_ADDR(NR2_SAD2NORM_LUT2)
#define NR2_SAD2NORM_LUT3 0x1761 	///../ucode/register.h:7470
#define P_NR2_SAD2NORM_LUT3 		VCBUS_REG_ADDR(NR2_SAD2NORM_LUT3)
#define NR2_EDGE2BETA_LUT0 0x1762 	///../ucode/register.h:7471
#define P_NR2_EDGE2BETA_LUT0 		VCBUS_REG_ADDR(NR2_EDGE2BETA_LUT0)
#define NR2_EDGE2BETA_LUT1 0x1763 	///../ucode/register.h:7472
#define P_NR2_EDGE2BETA_LUT1 		VCBUS_REG_ADDR(NR2_EDGE2BETA_LUT1)
#define NR2_EDGE2BETA_LUT2 0x1764 	///../ucode/register.h:7473
#define P_NR2_EDGE2BETA_LUT2 		VCBUS_REG_ADDR(NR2_EDGE2BETA_LUT2)
#define NR2_EDGE2BETA_LUT3 0x1765 	///../ucode/register.h:7474
#define P_NR2_EDGE2BETA_LUT3 		VCBUS_REG_ADDR(NR2_EDGE2BETA_LUT3)
#define NR2_MOTION2BETA_LUT0 0x1766 	///../ucode/register.h:7475
#define P_NR2_MOTION2BETA_LUT0 		VCBUS_REG_ADDR(NR2_MOTION2BETA_LUT0)
#define NR2_MOTION2BETA_LUT1 0x1767 	///../ucode/register.h:7476
#define P_NR2_MOTION2BETA_LUT1 		VCBUS_REG_ADDR(NR2_MOTION2BETA_LUT1)
#define NR2_MOTION2BETA_LUT2 0x1768 	///../ucode/register.h:7477
#define P_NR2_MOTION2BETA_LUT2 		VCBUS_REG_ADDR(NR2_MOTION2BETA_LUT2)
#define NR2_MOTION2BETA_LUT3 0x1769 	///../ucode/register.h:7478
#define P_NR2_MOTION2BETA_LUT3 		VCBUS_REG_ADDR(NR2_MOTION2BETA_LUT3)
#define NR2_MATNR_MTN_CRTL 0x176a 	///../ucode/register.h:7479
#define P_NR2_MATNR_MTN_CRTL 		VCBUS_REG_ADDR(NR2_MATNR_MTN_CRTL)
#define NR2_MATNR_MTN_CRTL2 0x176b 	///../ucode/register.h:7480
#define P_NR2_MATNR_MTN_CRTL2 		VCBUS_REG_ADDR(NR2_MATNR_MTN_CRTL2)
#define NR2_MATNR_MTN_COR 0x176c 	///../ucode/register.h:7481
#define P_NR2_MATNR_MTN_COR 		VCBUS_REG_ADDR(NR2_MATNR_MTN_COR)
#define NR2_MATNR_MTN_GAIN 0x176d 	///../ucode/register.h:7482
#define P_NR2_MATNR_MTN_GAIN 		VCBUS_REG_ADDR(NR2_MATNR_MTN_GAIN)
#define NR2_MATNR_DEGHOST 0x176e 	///../ucode/register.h:7483
#define P_NR2_MATNR_DEGHOST 		VCBUS_REG_ADDR(NR2_MATNR_DEGHOST)
#define NR2_MATNR_ALPHALP_LUT0 0x176f 	///../ucode/register.h:7484
#define P_NR2_MATNR_ALPHALP_LUT0 		VCBUS_REG_ADDR(NR2_MATNR_ALPHALP_LUT0)
#define NR2_MATNR_ALPHALP_LUT1 0x1770 	///../ucode/register.h:7485
#define P_NR2_MATNR_ALPHALP_LUT1 		VCBUS_REG_ADDR(NR2_MATNR_ALPHALP_LUT1)
#define NR2_MATNR_ALPHALP_LUT2 0x1771 	///../ucode/register.h:7486
#define P_NR2_MATNR_ALPHALP_LUT2 		VCBUS_REG_ADDR(NR2_MATNR_ALPHALP_LUT2)
#define NR2_MATNR_ALPHALP_LUT3 0x1772 	///../ucode/register.h:7487
#define P_NR2_MATNR_ALPHALP_LUT3 		VCBUS_REG_ADDR(NR2_MATNR_ALPHALP_LUT3)
#define NR2_MATNR_ALPHAHP_LUT0 0x1773 	///../ucode/register.h:7488
#define P_NR2_MATNR_ALPHAHP_LUT0 		VCBUS_REG_ADDR(NR2_MATNR_ALPHAHP_LUT0)
#define NR2_MATNR_ALPHAHP_LUT1 0x1774 	///../ucode/register.h:7489
#define P_NR2_MATNR_ALPHAHP_LUT1 		VCBUS_REG_ADDR(NR2_MATNR_ALPHAHP_LUT1)
#define NR2_MATNR_ALPHAHP_LUT2 0x1775 	///../ucode/register.h:7490
#define P_NR2_MATNR_ALPHAHP_LUT2 		VCBUS_REG_ADDR(NR2_MATNR_ALPHAHP_LUT2)
#define NR2_MATNR_ALPHAHP_LUT3 0x1776 	///../ucode/register.h:7491
#define P_NR2_MATNR_ALPHAHP_LUT3 		VCBUS_REG_ADDR(NR2_MATNR_ALPHAHP_LUT3)
#define NR2_MATNR_MTNB_BRT 0x1777 	///../ucode/register.h:7492
#define P_NR2_MATNR_MTNB_BRT 		VCBUS_REG_ADDR(NR2_MATNR_MTNB_BRT)
#define NR2_CUE_MODE 0x1778 	///../ucode/register.h:7493
#define P_NR2_CUE_MODE 		VCBUS_REG_ADDR(NR2_CUE_MODE)
#define NR2_CUE_CON_MOT_TH 0x1779 	///../ucode/register.h:7494
#define P_NR2_CUE_CON_MOT_TH 		VCBUS_REG_ADDR(NR2_CUE_CON_MOT_TH)
#define NR2_CUE_CON_DIF0 0x177a 	///../ucode/register.h:7495
#define P_NR2_CUE_CON_DIF0 		VCBUS_REG_ADDR(NR2_CUE_CON_DIF0)
#define NR2_CUE_CON_DIF1 0x177b 	///../ucode/register.h:7496
#define P_NR2_CUE_CON_DIF1 		VCBUS_REG_ADDR(NR2_CUE_CON_DIF1)
#define NR2_CUE_CON_DIF2 0x177c 	///../ucode/register.h:7497
#define P_NR2_CUE_CON_DIF2 		VCBUS_REG_ADDR(NR2_CUE_CON_DIF2)
#define NR2_CUE_CON_DIF3 0x177d 	///../ucode/register.h:7498
#define P_NR2_CUE_CON_DIF3 		VCBUS_REG_ADDR(NR2_CUE_CON_DIF3)
#define NR2_CUE_PRG_DIF 0x177e 	///../ucode/register.h:7499
#define P_NR2_CUE_PRG_DIF 		VCBUS_REG_ADDR(NR2_CUE_PRG_DIF)
#define NR2_CONV_MODE 0x177f 	///../ucode/register.h:7500
#define P_NR2_CONV_MODE 		VCBUS_REG_ADDR(NR2_CONV_MODE)
#define DET3D_RO_SPLT_HB 0x1780 	///../ucode/register.h:7504
#define P_DET3D_RO_SPLT_HB 		VCBUS_REG_ADDR(DET3D_RO_SPLT_HB)
#define DET3D_RO_SPLT_VL 0x1781 	///../ucode/register.h:7505
#define P_DET3D_RO_SPLT_VL 		VCBUS_REG_ADDR(DET3D_RO_SPLT_VL)
#define DET3D_RO_SPLT_VR 0x1782 	///../ucode/register.h:7506
#define P_DET3D_RO_SPLT_VR 		VCBUS_REG_ADDR(DET3D_RO_SPLT_VR)
#define DET3D_RO_MAT_LUMA_LR 0x1783 	///../ucode/register.h:7507
#define P_DET3D_RO_MAT_LUMA_LR 		VCBUS_REG_ADDR(DET3D_RO_MAT_LUMA_LR)
#define DET3D_RO_MAT_LUMA_TB 0x1784 	///../ucode/register.h:7508
#define P_DET3D_RO_MAT_LUMA_TB 		VCBUS_REG_ADDR(DET3D_RO_MAT_LUMA_TB)
#define DET3D_RO_MAT_CHRU_LR 0x1785 	///../ucode/register.h:7509
#define P_DET3D_RO_MAT_CHRU_LR 		VCBUS_REG_ADDR(DET3D_RO_MAT_CHRU_LR)
#define DET3D_RO_MAT_CHRU_TB 0x1786 	///../ucode/register.h:7510
#define P_DET3D_RO_MAT_CHRU_TB 		VCBUS_REG_ADDR(DET3D_RO_MAT_CHRU_TB)
#define DET3D_RO_MAT_CHRV_LR 0x1787 	///../ucode/register.h:7511
#define P_DET3D_RO_MAT_CHRV_LR 		VCBUS_REG_ADDR(DET3D_RO_MAT_CHRV_LR)
#define DET3D_RO_MAT_CHRV_TB 0x1788 	///../ucode/register.h:7512
#define P_DET3D_RO_MAT_CHRV_TB 		VCBUS_REG_ADDR(DET3D_RO_MAT_CHRV_TB)
#define DET3D_RO_MAT_HEDG_LR 0x1789 	///../ucode/register.h:7513
#define P_DET3D_RO_MAT_HEDG_LR 		VCBUS_REG_ADDR(DET3D_RO_MAT_HEDG_LR)
#define DET3D_RO_MAT_HEDG_TB 0x178a 	///../ucode/register.h:7514
#define P_DET3D_RO_MAT_HEDG_TB 		VCBUS_REG_ADDR(DET3D_RO_MAT_HEDG_TB)
#define DET3D_RO_MAT_VEDG_LR 0x178b 	///../ucode/register.h:7515
#define P_DET3D_RO_MAT_VEDG_LR 		VCBUS_REG_ADDR(DET3D_RO_MAT_VEDG_LR)
#define DET3D_RO_MAT_VEDG_TB 0x178c 	///../ucode/register.h:7516
#define P_DET3D_RO_MAT_VEDG_TB 		VCBUS_REG_ADDR(DET3D_RO_MAT_VEDG_TB)
#define DET3D_RO_MAT_MOTN_LR 0x178d 	///../ucode/register.h:7517
#define P_DET3D_RO_MAT_MOTN_LR 		VCBUS_REG_ADDR(DET3D_RO_MAT_MOTN_LR)
#define DET3D_RO_MAT_MOTN_TB 0x178e 	///../ucode/register.h:7518
#define P_DET3D_RO_MAT_MOTN_TB 		VCBUS_REG_ADDR(DET3D_RO_MAT_MOTN_TB)
#define DET3D_RO_FRM_MOTN 0x178f 	///../ucode/register.h:7519
#define P_DET3D_RO_FRM_MOTN 		VCBUS_REG_ADDR(DET3D_RO_FRM_MOTN)
#define DET3D_RAMRD_ADDR_PORT 0x179a 	///../ucode/register.h:7521
#define P_DET3D_RAMRD_ADDR_PORT 		VCBUS_REG_ADDR(DET3D_RAMRD_ADDR_PORT)
#define DET3D_RAMRD_DATA_PORT 0x179b 	///../ucode/register.h:7522
#define P_DET3D_RAMRD_DATA_PORT 		VCBUS_REG_ADDR(DET3D_RAMRD_DATA_PORT)
#define NR2_CFR_PARA_CFG0 0x179c 	///../ucode/register.h:7523
#define P_NR2_CFR_PARA_CFG0 		VCBUS_REG_ADDR(NR2_CFR_PARA_CFG0)
#define NR2_CFR_PARA_CFG1 0x179d 	///../ucode/register.h:7524
#define P_NR2_CFR_PARA_CFG1 		VCBUS_REG_ADDR(NR2_CFR_PARA_CFG1)
#define DI_NR_1_CTRL0 0x1794 	///../ucode/register.h:7526
#define P_DI_NR_1_CTRL0 		VCBUS_REG_ADDR(DI_NR_1_CTRL0)
#define DI_NR_1_CTRL1 0x1795 	///../ucode/register.h:7527
#define P_DI_NR_1_CTRL1 		VCBUS_REG_ADDR(DI_NR_1_CTRL1)
#define DI_NR_1_CTRL2 0x1796 	///../ucode/register.h:7528
#define P_DI_NR_1_CTRL2 		VCBUS_REG_ADDR(DI_NR_1_CTRL2)
#define DI_NR_1_CTRL3 0x1797 	///../ucode/register.h:7529
#define P_DI_NR_1_CTRL3 		VCBUS_REG_ADDR(DI_NR_1_CTRL3)
#define DI_CONTWR_X 0x17a0 	///../ucode/register.h:7530
#define P_DI_CONTWR_X 		VCBUS_REG_ADDR(DI_CONTWR_X)
#define DI_CONTWR_Y 0x17a1 	///../ucode/register.h:7531
#define P_DI_CONTWR_Y 		VCBUS_REG_ADDR(DI_CONTWR_Y)
#define DI_CONTWR_CTRL 0x17a2 	///../ucode/register.h:7532
#define P_DI_CONTWR_CTRL 		VCBUS_REG_ADDR(DI_CONTWR_CTRL)
#define DI_CONTPRD_X 0x17a3 	///../ucode/register.h:7533
#define P_DI_CONTPRD_X 		VCBUS_REG_ADDR(DI_CONTPRD_X)
#define DI_CONTPRD_Y 0x17a4 	///../ucode/register.h:7534
#define P_DI_CONTPRD_Y 		VCBUS_REG_ADDR(DI_CONTPRD_Y)
#define DI_CONTP2RD_X 0x17a5 	///../ucode/register.h:7535
#define P_DI_CONTP2RD_X 		VCBUS_REG_ADDR(DI_CONTP2RD_X)
#define DI_CONTP2RD_Y 0x17a6 	///../ucode/register.h:7536
#define P_DI_CONTP2RD_Y 		VCBUS_REG_ADDR(DI_CONTP2RD_Y)
#define DI_CONTRD_CTRL 0x17a7 	///../ucode/register.h:7537
#define P_DI_CONTRD_CTRL 		VCBUS_REG_ADDR(DI_CONTRD_CTRL)
#define DI_NRWR_X 0x17c0 	///../ucode/register.h:7538
#define P_DI_NRWR_X 		VCBUS_REG_ADDR(DI_NRWR_X)
#define DI_NRWR_Y 0x17c1 	///../ucode/register.h:7539
#define P_DI_NRWR_Y 		VCBUS_REG_ADDR(DI_NRWR_Y)
#define DI_NRWR_CTRL 0x17c2 	///../ucode/register.h:7540
#define P_DI_NRWR_CTRL 		VCBUS_REG_ADDR(DI_NRWR_CTRL)
#define DI_MTNWR_X 0x17c3 	///../ucode/register.h:7541
#define P_DI_MTNWR_X 		VCBUS_REG_ADDR(DI_MTNWR_X)
#define DI_MTNWR_Y 0x17c4 	///../ucode/register.h:7542
#define P_DI_MTNWR_Y 		VCBUS_REG_ADDR(DI_MTNWR_Y)
#define DI_MTNWR_CTRL 0x17c5 	///../ucode/register.h:7543
#define P_DI_MTNWR_CTRL 		VCBUS_REG_ADDR(DI_MTNWR_CTRL)
#define DI_DIWR_X 0x17c6 	///../ucode/register.h:7544
#define P_DI_DIWR_X 		VCBUS_REG_ADDR(DI_DIWR_X)
#define DI_DIWR_Y 0x17c7 	///../ucode/register.h:7545
#define P_DI_DIWR_Y 		VCBUS_REG_ADDR(DI_DIWR_Y)
#define DI_DIWR_CTRL 0x17c8 	///../ucode/register.h:7546
#define P_DI_DIWR_CTRL 		VCBUS_REG_ADDR(DI_DIWR_CTRL)
#define DI_MTNCRD_X 0x17c9 	///../ucode/register.h:7547
#define P_DI_MTNCRD_X 		VCBUS_REG_ADDR(DI_MTNCRD_X)
#define DI_MTNCRD_Y 0x17ca 	///../ucode/register.h:7548
#define P_DI_MTNCRD_Y 		VCBUS_REG_ADDR(DI_MTNCRD_Y)
#define DI_MTNPRD_X 0x17cb 	///../ucode/register.h:7549
#define P_DI_MTNPRD_X 		VCBUS_REG_ADDR(DI_MTNPRD_X)
#define DI_MTNPRD_Y 0x17cc 	///../ucode/register.h:7550
#define P_DI_MTNPRD_Y 		VCBUS_REG_ADDR(DI_MTNPRD_Y)
#define DI_MTNRD_CTRL 0x17cd 	///../ucode/register.h:7551
#define P_DI_MTNRD_CTRL 		VCBUS_REG_ADDR(DI_MTNRD_CTRL)
#define DI_INP_GEN_REG 0x17ce 	///../ucode/register.h:7552
#define P_DI_INP_GEN_REG 		VCBUS_REG_ADDR(DI_INP_GEN_REG)
#define DI_INP_CANVAS0 0x17cf 	///../ucode/register.h:7553
#define P_DI_INP_CANVAS0 		VCBUS_REG_ADDR(DI_INP_CANVAS0)
#define DI_INP_LUMA_X0 0x17d0 	///../ucode/register.h:7554
#define P_DI_INP_LUMA_X0 		VCBUS_REG_ADDR(DI_INP_LUMA_X0)
#define DI_INP_LUMA_Y0 0x17d1 	///../ucode/register.h:7555
#define P_DI_INP_LUMA_Y0 		VCBUS_REG_ADDR(DI_INP_LUMA_Y0)
#define DI_INP_CHROMA_X0 0x17d2 	///../ucode/register.h:7556
#define P_DI_INP_CHROMA_X0 		VCBUS_REG_ADDR(DI_INP_CHROMA_X0)
#define DI_INP_CHROMA_Y0 0x17d3 	///../ucode/register.h:7557
#define P_DI_INP_CHROMA_Y0 		VCBUS_REG_ADDR(DI_INP_CHROMA_Y0)
#define DI_INP_RPT_LOOP 0x17d4 	///../ucode/register.h:7558
#define P_DI_INP_RPT_LOOP 		VCBUS_REG_ADDR(DI_INP_RPT_LOOP)
#define DI_INP_LUMA0_RPT_PAT 0x17d5 	///../ucode/register.h:7559
#define P_DI_INP_LUMA0_RPT_PAT 		VCBUS_REG_ADDR(DI_INP_LUMA0_RPT_PAT)
#define DI_INP_CHROMA0_RPT_PAT 0x17d6 	///../ucode/register.h:7560
#define P_DI_INP_CHROMA0_RPT_PAT 		VCBUS_REG_ADDR(DI_INP_CHROMA0_RPT_PAT)
#define DI_INP_DUMMY_PIXEL 0x17d7 	///../ucode/register.h:7561
#define P_DI_INP_DUMMY_PIXEL 		VCBUS_REG_ADDR(DI_INP_DUMMY_PIXEL)
#define DI_INP_LUMA_FIFO_SIZE 0x17d8 	///../ucode/register.h:7562
#define P_DI_INP_LUMA_FIFO_SIZE 		VCBUS_REG_ADDR(DI_INP_LUMA_FIFO_SIZE)
#define DI_INP_RANGE_MAP_Y 0x17ba 	///../ucode/register.h:7563
#define P_DI_INP_RANGE_MAP_Y 		VCBUS_REG_ADDR(DI_INP_RANGE_MAP_Y)
#define DI_INP_RANGE_MAP_CB 0x17bb 	///../ucode/register.h:7564
#define P_DI_INP_RANGE_MAP_CB 		VCBUS_REG_ADDR(DI_INP_RANGE_MAP_CB)
#define DI_INP_RANGE_MAP_CR 0x17bc 	///../ucode/register.h:7565
#define P_DI_INP_RANGE_MAP_CR 		VCBUS_REG_ADDR(DI_INP_RANGE_MAP_CR)
#define DI_INP_GEN_REG2 0x1791 	///../ucode/register.h:7566
#define P_DI_INP_GEN_REG2 		VCBUS_REG_ADDR(DI_INP_GEN_REG2)
#define DI_INP_FMT_CTRL 0x17d9 	///../ucode/register.h:7567
#define P_DI_INP_FMT_CTRL 		VCBUS_REG_ADDR(DI_INP_FMT_CTRL)
#define DI_INP_FMT_W 0x17da 	///../ucode/register.h:7568
#define P_DI_INP_FMT_W 		VCBUS_REG_ADDR(DI_INP_FMT_W)
#define DI_MEM_GEN_REG 0x17db 	///../ucode/register.h:7569
#define P_DI_MEM_GEN_REG 		VCBUS_REG_ADDR(DI_MEM_GEN_REG)
#define DI_MEM_CANVAS0 0x17dc 	///../ucode/register.h:7570
#define P_DI_MEM_CANVAS0 		VCBUS_REG_ADDR(DI_MEM_CANVAS0)
#define DI_MEM_LUMA_X0 0x17dd 	///../ucode/register.h:7571
#define P_DI_MEM_LUMA_X0 		VCBUS_REG_ADDR(DI_MEM_LUMA_X0)
#define DI_MEM_LUMA_Y0 0x17de 	///../ucode/register.h:7572
#define P_DI_MEM_LUMA_Y0 		VCBUS_REG_ADDR(DI_MEM_LUMA_Y0)
#define DI_MEM_CHROMA_X0 0x17df 	///../ucode/register.h:7573
#define P_DI_MEM_CHROMA_X0 		VCBUS_REG_ADDR(DI_MEM_CHROMA_X0)
#define DI_MEM_CHROMA_Y0 0x17e0 	///../ucode/register.h:7574
#define P_DI_MEM_CHROMA_Y0 		VCBUS_REG_ADDR(DI_MEM_CHROMA_Y0)
#define DI_MEM_RPT_LOOP 0x17e1 	///../ucode/register.h:7575
#define P_DI_MEM_RPT_LOOP 		VCBUS_REG_ADDR(DI_MEM_RPT_LOOP)
#define DI_MEM_LUMA0_RPT_PAT 0x17e2 	///../ucode/register.h:7576
#define P_DI_MEM_LUMA0_RPT_PAT 		VCBUS_REG_ADDR(DI_MEM_LUMA0_RPT_PAT)
#define DI_MEM_CHROMA0_RPT_PAT 0x17e3 	///../ucode/register.h:7577
#define P_DI_MEM_CHROMA0_RPT_PAT 		VCBUS_REG_ADDR(DI_MEM_CHROMA0_RPT_PAT)
#define DI_MEM_DUMMY_PIXEL 0x17e4 	///../ucode/register.h:7578
#define P_DI_MEM_DUMMY_PIXEL 		VCBUS_REG_ADDR(DI_MEM_DUMMY_PIXEL)
#define DI_MEM_LUMA_FIFO_SIZE 0x17e5 	///../ucode/register.h:7579
#define P_DI_MEM_LUMA_FIFO_SIZE 		VCBUS_REG_ADDR(DI_MEM_LUMA_FIFO_SIZE)
#define DI_MEM_RANGE_MAP_Y 0x17bd 	///../ucode/register.h:7580
#define P_DI_MEM_RANGE_MAP_Y 		VCBUS_REG_ADDR(DI_MEM_RANGE_MAP_Y)
#define DI_MEM_RANGE_MAP_CB 0x17be 	///../ucode/register.h:7581
#define P_DI_MEM_RANGE_MAP_CB 		VCBUS_REG_ADDR(DI_MEM_RANGE_MAP_CB)
#define DI_MEM_RANGE_MAP_CR 0x17bf 	///../ucode/register.h:7582
#define P_DI_MEM_RANGE_MAP_CR 		VCBUS_REG_ADDR(DI_MEM_RANGE_MAP_CR)
#define DI_MEM_GEN_REG2 0x1792 	///../ucode/register.h:7583
#define P_DI_MEM_GEN_REG2 		VCBUS_REG_ADDR(DI_MEM_GEN_REG2)
#define DI_MEM_FMT_CTRL 0x17e6 	///../ucode/register.h:7584
#define P_DI_MEM_FMT_CTRL 		VCBUS_REG_ADDR(DI_MEM_FMT_CTRL)
#define DI_MEM_FMT_W 0x17e7 	///../ucode/register.h:7585
#define P_DI_MEM_FMT_W 		VCBUS_REG_ADDR(DI_MEM_FMT_W)
#define DI_IF1_GEN_REG 0x17e8 	///../ucode/register.h:7586
#define P_DI_IF1_GEN_REG 		VCBUS_REG_ADDR(DI_IF1_GEN_REG)
#define DI_IF1_CANVAS0 0x17e9 	///../ucode/register.h:7587
#define P_DI_IF1_CANVAS0 		VCBUS_REG_ADDR(DI_IF1_CANVAS0)
#define DI_IF1_LUMA_X0 0x17ea 	///../ucode/register.h:7588
#define P_DI_IF1_LUMA_X0 		VCBUS_REG_ADDR(DI_IF1_LUMA_X0)
#define DI_IF1_LUMA_Y0 0x17eb 	///../ucode/register.h:7589
#define P_DI_IF1_LUMA_Y0 		VCBUS_REG_ADDR(DI_IF1_LUMA_Y0)
#define DI_IF1_CHROMA_X0 0x17ec 	///../ucode/register.h:7590
#define P_DI_IF1_CHROMA_X0 		VCBUS_REG_ADDR(DI_IF1_CHROMA_X0)
#define DI_IF1_CHROMA_Y0 0x17ed 	///../ucode/register.h:7591
#define P_DI_IF1_CHROMA_Y0 		VCBUS_REG_ADDR(DI_IF1_CHROMA_Y0)
#define DI_IF1_RPT_LOOP 0x17ee 	///../ucode/register.h:7592
#define P_DI_IF1_RPT_LOOP 		VCBUS_REG_ADDR(DI_IF1_RPT_LOOP)
#define DI_IF1_LUMA0_RPT_PAT 0x17ef 	///../ucode/register.h:7593
#define P_DI_IF1_LUMA0_RPT_PAT 		VCBUS_REG_ADDR(DI_IF1_LUMA0_RPT_PAT)
#define DI_IF1_CHROMA0_RPT_PAT 0x17f0 	///../ucode/register.h:7594
#define P_DI_IF1_CHROMA0_RPT_PAT 		VCBUS_REG_ADDR(DI_IF1_CHROMA0_RPT_PAT)
#define DI_IF1_DUMMY_PIXEL 0x17f1 	///../ucode/register.h:7595
#define P_DI_IF1_DUMMY_PIXEL 		VCBUS_REG_ADDR(DI_IF1_DUMMY_PIXEL)
#define DI_IF1_LUMA_FIFO_SIZE 0x17f2 	///../ucode/register.h:7596
#define P_DI_IF1_LUMA_FIFO_SIZE 		VCBUS_REG_ADDR(DI_IF1_LUMA_FIFO_SIZE)
#define DI_IF1_RANGE_MAP_Y 0x17fc 	///../ucode/register.h:7597
#define P_DI_IF1_RANGE_MAP_Y 		VCBUS_REG_ADDR(DI_IF1_RANGE_MAP_Y)
#define DI_IF1_RANGE_MAP_CB 0x17fd 	///../ucode/register.h:7598
#define P_DI_IF1_RANGE_MAP_CB 		VCBUS_REG_ADDR(DI_IF1_RANGE_MAP_CB)
#define DI_IF1_RANGE_MAP_CR 0x17fe 	///../ucode/register.h:7599
#define P_DI_IF1_RANGE_MAP_CR 		VCBUS_REG_ADDR(DI_IF1_RANGE_MAP_CR)
#define DI_IF1_GEN_REG2 0x1790 	///../ucode/register.h:7600
#define P_DI_IF1_GEN_REG2 		VCBUS_REG_ADDR(DI_IF1_GEN_REG2)
#define DI_IF1_FMT_CTRL 0x17f3 	///../ucode/register.h:7601
#define P_DI_IF1_FMT_CTRL 		VCBUS_REG_ADDR(DI_IF1_FMT_CTRL)
#define DI_IF1_FMT_W 0x17f4 	///../ucode/register.h:7602
#define P_DI_IF1_FMT_W 		VCBUS_REG_ADDR(DI_IF1_FMT_W)
#define DI_CHAN2_GEN_REG 0x17f5 	///../ucode/register.h:7603
#define P_DI_CHAN2_GEN_REG 		VCBUS_REG_ADDR(DI_CHAN2_GEN_REG)
#define DI_CHAN2_CANVAS0 0x17f6 	///../ucode/register.h:7604
#define P_DI_CHAN2_CANVAS0 		VCBUS_REG_ADDR(DI_CHAN2_CANVAS0)
#define DI_CHAN2_LUMA_X0 0x17f7 	///../ucode/register.h:7605
#define P_DI_CHAN2_LUMA_X0 		VCBUS_REG_ADDR(DI_CHAN2_LUMA_X0)
#define DI_CHAN2_LUMA_Y0 0x17f8 	///../ucode/register.h:7606
#define P_DI_CHAN2_LUMA_Y0 		VCBUS_REG_ADDR(DI_CHAN2_LUMA_Y0)
#define DI_CHAN2_CHROMA_X0 0x17f9 	///../ucode/register.h:7607
#define P_DI_CHAN2_CHROMA_X0 		VCBUS_REG_ADDR(DI_CHAN2_CHROMA_X0)
#define DI_CHAN2_CHROMA_Y0 0x17fa 	///../ucode/register.h:7608
#define P_DI_CHAN2_CHROMA_Y0 		VCBUS_REG_ADDR(DI_CHAN2_CHROMA_Y0)
#define DI_CHAN2_RPT_LOOP 0x17fb 	///../ucode/register.h:7609
#define P_DI_CHAN2_RPT_LOOP 		VCBUS_REG_ADDR(DI_CHAN2_RPT_LOOP)
#define DI_CHAN2_LUMA0_RPT_PAT 0x17b0 	///../ucode/register.h:7610
#define P_DI_CHAN2_LUMA0_RPT_PAT 		VCBUS_REG_ADDR(DI_CHAN2_LUMA0_RPT_PAT)
#define DI_CHAN2_CHROMA0_RPT_PAT 0x17b1 	///../ucode/register.h:7611
#define P_DI_CHAN2_CHROMA0_RPT_PAT 		VCBUS_REG_ADDR(DI_CHAN2_CHROMA0_RPT_PAT)
#define DI_CHAN2_DUMMY_PIXEL 0x17b2 	///../ucode/register.h:7612
#define P_DI_CHAN2_DUMMY_PIXEL 		VCBUS_REG_ADDR(DI_CHAN2_DUMMY_PIXEL)
#define DI_CHAN2_LUMA_FIFO_SIZE 0x17b3 	///../ucode/register.h:7613
#define P_DI_CHAN2_LUMA_FIFO_SIZE 		VCBUS_REG_ADDR(DI_CHAN2_LUMA_FIFO_SIZE)
#define DI_CHAN2_RANGE_MAP_Y 0x17b4 	///../ucode/register.h:7614
#define P_DI_CHAN2_RANGE_MAP_Y 		VCBUS_REG_ADDR(DI_CHAN2_RANGE_MAP_Y)
#define DI_CHAN2_RANGE_MAP_CB 0x17b5 	///../ucode/register.h:7615
#define P_DI_CHAN2_RANGE_MAP_CB 		VCBUS_REG_ADDR(DI_CHAN2_RANGE_MAP_CB)
#define DI_CHAN2_RANGE_MAP_CR 0x17b6 	///../ucode/register.h:7616
#define P_DI_CHAN2_RANGE_MAP_CR 		VCBUS_REG_ADDR(DI_CHAN2_RANGE_MAP_CR)
#define DI_CHAN2_GEN_REG2 0x17b7 	///../ucode/register.h:7617
#define P_DI_CHAN2_GEN_REG2 		VCBUS_REG_ADDR(DI_CHAN2_GEN_REG2)
#define DI_CHAN2_FMT_CTRL 0x17b8 	///../ucode/register.h:7618
#define P_DI_CHAN2_FMT_CTRL 		VCBUS_REG_ADDR(DI_CHAN2_FMT_CTRL)
#define DI_CHAN2_FMT_W 0x17b9 	///../ucode/register.h:7619
#define P_DI_CHAN2_FMT_W 		VCBUS_REG_ADDR(DI_CHAN2_FMT_W)
#define VIU2_ADDR_START 0x1e00 	///../ucode/register.h:7634
#define P_VIU2_ADDR_START 		VCBUS_REG_ADDR(VIU2_ADDR_START)
#define VIU2_ADDR_END 0x1eff 	///../ucode/register.h:7635
#define P_VIU2_ADDR_END 		VCBUS_REG_ADDR(VIU2_ADDR_END)
#define VIU2_SW_RESET 0x1e01 	///../ucode/register.h:7644
#define P_VIU2_SW_RESET 		VCBUS_REG_ADDR(VIU2_SW_RESET)
#define VIU2_OSD1_CTRL_STAT 0x1e10 	///../ucode/register.h:7664
#define P_VIU2_OSD1_CTRL_STAT 		VCBUS_REG_ADDR(VIU2_OSD1_CTRL_STAT)
#define VIU2_OSD1_CTRL_STAT2 0x1e2d 	///../ucode/register.h:7673
#define P_VIU2_OSD1_CTRL_STAT2 		VCBUS_REG_ADDR(VIU2_OSD1_CTRL_STAT2)
#define VIU2_OSD1_COLOR_ADDR 0x1e11 	///../ucode/register.h:7677
#define P_VIU2_OSD1_COLOR_ADDR 		VCBUS_REG_ADDR(VIU2_OSD1_COLOR_ADDR)
#define VIU2_OSD1_COLOR 0x1e12 	///../ucode/register.h:7682
#define P_VIU2_OSD1_COLOR 		VCBUS_REG_ADDR(VIU2_OSD1_COLOR)
#define VIU2_OSD1_TCOLOR_AG0 0x1e17 	///../ucode/register.h:7687
#define P_VIU2_OSD1_TCOLOR_AG0 		VCBUS_REG_ADDR(VIU2_OSD1_TCOLOR_AG0)
#define VIU2_OSD1_TCOLOR_AG1 0x1e18 	///../ucode/register.h:7688
#define P_VIU2_OSD1_TCOLOR_AG1 		VCBUS_REG_ADDR(VIU2_OSD1_TCOLOR_AG1)
#define VIU2_OSD1_TCOLOR_AG2 0x1e19 	///../ucode/register.h:7689
#define P_VIU2_OSD1_TCOLOR_AG2 		VCBUS_REG_ADDR(VIU2_OSD1_TCOLOR_AG2)
#define VIU2_OSD1_TCOLOR_AG3 0x1e1a 	///../ucode/register.h:7690
#define P_VIU2_OSD1_TCOLOR_AG3 		VCBUS_REG_ADDR(VIU2_OSD1_TCOLOR_AG3)
#define VIU2_OSD1_BLK0_CFG_W0 0x1e1b 	///../ucode/register.h:7707
#define P_VIU2_OSD1_BLK0_CFG_W0 		VCBUS_REG_ADDR(VIU2_OSD1_BLK0_CFG_W0)
#define VIU2_OSD1_BLK1_CFG_W0 0x1e1f 	///../ucode/register.h:7708
#define P_VIU2_OSD1_BLK1_CFG_W0 		VCBUS_REG_ADDR(VIU2_OSD1_BLK1_CFG_W0)
#define VIU2_OSD1_BLK2_CFG_W0 0x1e23 	///../ucode/register.h:7709
#define P_VIU2_OSD1_BLK2_CFG_W0 		VCBUS_REG_ADDR(VIU2_OSD1_BLK2_CFG_W0)
#define VIU2_OSD1_BLK3_CFG_W0 0x1e27 	///../ucode/register.h:7710
#define P_VIU2_OSD1_BLK3_CFG_W0 		VCBUS_REG_ADDR(VIU2_OSD1_BLK3_CFG_W0)
#define VIU2_OSD1_BLK0_CFG_W1 0x1e1c 	///../ucode/register.h:7715
#define P_VIU2_OSD1_BLK0_CFG_W1 		VCBUS_REG_ADDR(VIU2_OSD1_BLK0_CFG_W1)
#define VIU2_OSD1_BLK1_CFG_W1 0x1e20 	///../ucode/register.h:7716
#define P_VIU2_OSD1_BLK1_CFG_W1 		VCBUS_REG_ADDR(VIU2_OSD1_BLK1_CFG_W1)
#define VIU2_OSD1_BLK2_CFG_W1 0x1e24 	///../ucode/register.h:7717
#define P_VIU2_OSD1_BLK2_CFG_W1 		VCBUS_REG_ADDR(VIU2_OSD1_BLK2_CFG_W1)
#define VIU2_OSD1_BLK3_CFG_W1 0x1e28 	///../ucode/register.h:7718
#define P_VIU2_OSD1_BLK3_CFG_W1 		VCBUS_REG_ADDR(VIU2_OSD1_BLK3_CFG_W1)
#define VIU2_OSD1_BLK0_CFG_W2 0x1e1d 	///../ucode/register.h:7723
#define P_VIU2_OSD1_BLK0_CFG_W2 		VCBUS_REG_ADDR(VIU2_OSD1_BLK0_CFG_W2)
#define VIU2_OSD1_BLK1_CFG_W2 0x1e21 	///../ucode/register.h:7724
#define P_VIU2_OSD1_BLK1_CFG_W2 		VCBUS_REG_ADDR(VIU2_OSD1_BLK1_CFG_W2)
#define VIU2_OSD1_BLK2_CFG_W2 0x1e25 	///../ucode/register.h:7725
#define P_VIU2_OSD1_BLK2_CFG_W2 		VCBUS_REG_ADDR(VIU2_OSD1_BLK2_CFG_W2)
#define VIU2_OSD1_BLK3_CFG_W2 0x1e29 	///../ucode/register.h:7726
#define P_VIU2_OSD1_BLK3_CFG_W2 		VCBUS_REG_ADDR(VIU2_OSD1_BLK3_CFG_W2)
#define VIU2_OSD1_BLK0_CFG_W3 0x1e1e 	///../ucode/register.h:7731
#define P_VIU2_OSD1_BLK0_CFG_W3 		VCBUS_REG_ADDR(VIU2_OSD1_BLK0_CFG_W3)
#define VIU2_OSD1_BLK1_CFG_W3 0x1e22 	///../ucode/register.h:7732
#define P_VIU2_OSD1_BLK1_CFG_W3 		VCBUS_REG_ADDR(VIU2_OSD1_BLK1_CFG_W3)
#define VIU2_OSD1_BLK2_CFG_W3 0x1e26 	///../ucode/register.h:7733
#define P_VIU2_OSD1_BLK2_CFG_W3 		VCBUS_REG_ADDR(VIU2_OSD1_BLK2_CFG_W3)
#define VIU2_OSD1_BLK3_CFG_W3 0x1e2a 	///../ucode/register.h:7734
#define P_VIU2_OSD1_BLK3_CFG_W3 		VCBUS_REG_ADDR(VIU2_OSD1_BLK3_CFG_W3)
#define VIU2_OSD1_BLK0_CFG_W4 0x1e13 	///../ucode/register.h:7739
#define P_VIU2_OSD1_BLK0_CFG_W4 		VCBUS_REG_ADDR(VIU2_OSD1_BLK0_CFG_W4)
#define VIU2_OSD1_BLK1_CFG_W4 0x1e14 	///../ucode/register.h:7740
#define P_VIU2_OSD1_BLK1_CFG_W4 		VCBUS_REG_ADDR(VIU2_OSD1_BLK1_CFG_W4)
#define VIU2_OSD1_BLK2_CFG_W4 0x1e15 	///../ucode/register.h:7741
#define P_VIU2_OSD1_BLK2_CFG_W4 		VCBUS_REG_ADDR(VIU2_OSD1_BLK2_CFG_W4)
#define VIU2_OSD1_BLK3_CFG_W4 0x1e16 	///../ucode/register.h:7742
#define P_VIU2_OSD1_BLK3_CFG_W4 		VCBUS_REG_ADDR(VIU2_OSD1_BLK3_CFG_W4)
#define VIU2_OSD1_FIFO_CTRL_STAT 0x1e2b 	///../ucode/register.h:7758
#define P_VIU2_OSD1_FIFO_CTRL_STAT 		VCBUS_REG_ADDR(VIU2_OSD1_FIFO_CTRL_STAT)
#define VIU2_OSD1_TEST_RDDATA 0x1e2c 	///../ucode/register.h:7763
#define P_VIU2_OSD1_TEST_RDDATA 		VCBUS_REG_ADDR(VIU2_OSD1_TEST_RDDATA)
#define VIU2_OSD1_PROT_CTRL 0x1e2e 	///../ucode/register.h:7766
#define P_VIU2_OSD1_PROT_CTRL 		VCBUS_REG_ADDR(VIU2_OSD1_PROT_CTRL)
#define VIU2_OSD2_CTRL_STAT 0x1e30 	///../ucode/register.h:7787
#define P_VIU2_OSD2_CTRL_STAT 		VCBUS_REG_ADDR(VIU2_OSD2_CTRL_STAT)
#define VIU2_OSD2_CTRL_STAT2 0x1e4d 	///../ucode/register.h:7796
#define P_VIU2_OSD2_CTRL_STAT2 		VCBUS_REG_ADDR(VIU2_OSD2_CTRL_STAT2)
#define VIU2_OSD2_COLOR_ADDR 0x1e31 	///../ucode/register.h:7800
#define P_VIU2_OSD2_COLOR_ADDR 		VCBUS_REG_ADDR(VIU2_OSD2_COLOR_ADDR)
#define VIU2_OSD2_COLOR 0x1e32 	///../ucode/register.h:7805
#define P_VIU2_OSD2_COLOR 		VCBUS_REG_ADDR(VIU2_OSD2_COLOR)
#define VIU2_OSD2_HL1_H_START_END 0x1e33 	///../ucode/register.h:7810
#define P_VIU2_OSD2_HL1_H_START_END 		VCBUS_REG_ADDR(VIU2_OSD2_HL1_H_START_END)
#define VIU2_OSD2_HL1_V_START_END 0x1e34 	///../ucode/register.h:7811
#define P_VIU2_OSD2_HL1_V_START_END 		VCBUS_REG_ADDR(VIU2_OSD2_HL1_V_START_END)
#define VIU2_OSD2_HL2_H_START_END 0x1e35 	///../ucode/register.h:7812
#define P_VIU2_OSD2_HL2_H_START_END 		VCBUS_REG_ADDR(VIU2_OSD2_HL2_H_START_END)
#define VIU2_OSD2_HL2_V_START_END 0x1e36 	///../ucode/register.h:7813
#define P_VIU2_OSD2_HL2_V_START_END 		VCBUS_REG_ADDR(VIU2_OSD2_HL2_V_START_END)
#define VIU2_OSD2_TCOLOR_AG0 0x1e37 	///../ucode/register.h:7818
#define P_VIU2_OSD2_TCOLOR_AG0 		VCBUS_REG_ADDR(VIU2_OSD2_TCOLOR_AG0)
#define VIU2_OSD2_TCOLOR_AG1 0x1e38 	///../ucode/register.h:7819
#define P_VIU2_OSD2_TCOLOR_AG1 		VCBUS_REG_ADDR(VIU2_OSD2_TCOLOR_AG1)
#define VIU2_OSD2_TCOLOR_AG2 0x1e39 	///../ucode/register.h:7820
#define P_VIU2_OSD2_TCOLOR_AG2 		VCBUS_REG_ADDR(VIU2_OSD2_TCOLOR_AG2)
#define VIU2_OSD2_TCOLOR_AG3 0x1e3a 	///../ucode/register.h:7821
#define P_VIU2_OSD2_TCOLOR_AG3 		VCBUS_REG_ADDR(VIU2_OSD2_TCOLOR_AG3)
#define VIU2_OSD2_BLK0_CFG_W0 0x1e3b 	///../ucode/register.h:7835
#define P_VIU2_OSD2_BLK0_CFG_W0 		VCBUS_REG_ADDR(VIU2_OSD2_BLK0_CFG_W0)
#define VIU2_OSD2_BLK1_CFG_W0 0x1e3f 	///../ucode/register.h:7836
#define P_VIU2_OSD2_BLK1_CFG_W0 		VCBUS_REG_ADDR(VIU2_OSD2_BLK1_CFG_W0)
#define VIU2_OSD2_BLK2_CFG_W0 0x1e43 	///../ucode/register.h:7837
#define P_VIU2_OSD2_BLK2_CFG_W0 		VCBUS_REG_ADDR(VIU2_OSD2_BLK2_CFG_W0)
#define VIU2_OSD2_BLK3_CFG_W0 0x1e47 	///../ucode/register.h:7838
#define P_VIU2_OSD2_BLK3_CFG_W0 		VCBUS_REG_ADDR(VIU2_OSD2_BLK3_CFG_W0)
#define VIU2_OSD2_BLK0_CFG_W1 0x1e3c 	///../ucode/register.h:7843
#define P_VIU2_OSD2_BLK0_CFG_W1 		VCBUS_REG_ADDR(VIU2_OSD2_BLK0_CFG_W1)
#define VIU2_OSD2_BLK1_CFG_W1 0x1e40 	///../ucode/register.h:7844
#define P_VIU2_OSD2_BLK1_CFG_W1 		VCBUS_REG_ADDR(VIU2_OSD2_BLK1_CFG_W1)
#define VIU2_OSD2_BLK2_CFG_W1 0x1e44 	///../ucode/register.h:7845
#define P_VIU2_OSD2_BLK2_CFG_W1 		VCBUS_REG_ADDR(VIU2_OSD2_BLK2_CFG_W1)
#define VIU2_OSD2_BLK3_CFG_W1 0x1e48 	///../ucode/register.h:7846
#define P_VIU2_OSD2_BLK3_CFG_W1 		VCBUS_REG_ADDR(VIU2_OSD2_BLK3_CFG_W1)
#define VIU2_OSD2_BLK0_CFG_W2 0x1e3d 	///../ucode/register.h:7851
#define P_VIU2_OSD2_BLK0_CFG_W2 		VCBUS_REG_ADDR(VIU2_OSD2_BLK0_CFG_W2)
#define VIU2_OSD2_BLK1_CFG_W2 0x1e41 	///../ucode/register.h:7852
#define P_VIU2_OSD2_BLK1_CFG_W2 		VCBUS_REG_ADDR(VIU2_OSD2_BLK1_CFG_W2)
#define VIU2_OSD2_BLK2_CFG_W2 0x1e45 	///../ucode/register.h:7853
#define P_VIU2_OSD2_BLK2_CFG_W2 		VCBUS_REG_ADDR(VIU2_OSD2_BLK2_CFG_W2)
#define VIU2_OSD2_BLK3_CFG_W2 0x1e49 	///../ucode/register.h:7854
#define P_VIU2_OSD2_BLK3_CFG_W2 		VCBUS_REG_ADDR(VIU2_OSD2_BLK3_CFG_W2)
#define VIU2_OSD2_BLK0_CFG_W3 0x1e3e 	///../ucode/register.h:7859
#define P_VIU2_OSD2_BLK0_CFG_W3 		VCBUS_REG_ADDR(VIU2_OSD2_BLK0_CFG_W3)
#define VIU2_OSD2_BLK1_CFG_W3 0x1e42 	///../ucode/register.h:7860
#define P_VIU2_OSD2_BLK1_CFG_W3 		VCBUS_REG_ADDR(VIU2_OSD2_BLK1_CFG_W3)
#define VIU2_OSD2_BLK2_CFG_W3 0x1e46 	///../ucode/register.h:7861
#define P_VIU2_OSD2_BLK2_CFG_W3 		VCBUS_REG_ADDR(VIU2_OSD2_BLK2_CFG_W3)
#define VIU2_OSD2_BLK3_CFG_W3 0x1e4a 	///../ucode/register.h:7862
#define P_VIU2_OSD2_BLK3_CFG_W3 		VCBUS_REG_ADDR(VIU2_OSD2_BLK3_CFG_W3)
#define VIU2_OSD2_BLK0_CFG_W4 0x1e64 	///../ucode/register.h:7867
#define P_VIU2_OSD2_BLK0_CFG_W4 		VCBUS_REG_ADDR(VIU2_OSD2_BLK0_CFG_W4)
#define VIU2_OSD2_BLK1_CFG_W4 0x1e65 	///../ucode/register.h:7868
#define P_VIU2_OSD2_BLK1_CFG_W4 		VCBUS_REG_ADDR(VIU2_OSD2_BLK1_CFG_W4)
#define VIU2_OSD2_BLK2_CFG_W4 0x1e66 	///../ucode/register.h:7869
#define P_VIU2_OSD2_BLK2_CFG_W4 		VCBUS_REG_ADDR(VIU2_OSD2_BLK2_CFG_W4)
#define VIU2_OSD2_BLK3_CFG_W4 0x1e67 	///../ucode/register.h:7870
#define P_VIU2_OSD2_BLK3_CFG_W4 		VCBUS_REG_ADDR(VIU2_OSD2_BLK3_CFG_W4)
#define VIU2_OSD2_FIFO_CTRL_STAT 0x1e4b 	///../ucode/register.h:7886
#define P_VIU2_OSD2_FIFO_CTRL_STAT 		VCBUS_REG_ADDR(VIU2_OSD2_FIFO_CTRL_STAT)
#define VIU2_OSD2_TEST_RDDATA 0x1e4c 	///../ucode/register.h:7891
#define P_VIU2_OSD2_TEST_RDDATA 		VCBUS_REG_ADDR(VIU2_OSD2_TEST_RDDATA)
#define VIU2_OSD2_PROT_CTRL 0x1e4e 	///../ucode/register.h:7894
#define P_VIU2_OSD2_PROT_CTRL 		VCBUS_REG_ADDR(VIU2_OSD2_PROT_CTRL)
#define VIU2_VD1_IF0_GEN_REG 0x1e50 	///../ucode/register.h:7898
#define P_VIU2_VD1_IF0_GEN_REG 		VCBUS_REG_ADDR(VIU2_VD1_IF0_GEN_REG)
#define VIU2_VD1_IF0_CANVAS0 0x1e51 	///../ucode/register.h:7899
#define P_VIU2_VD1_IF0_CANVAS0 		VCBUS_REG_ADDR(VIU2_VD1_IF0_CANVAS0)
#define VIU2_VD1_IF0_CANVAS1 0x1e52 	///../ucode/register.h:7900
#define P_VIU2_VD1_IF0_CANVAS1 		VCBUS_REG_ADDR(VIU2_VD1_IF0_CANVAS1)
#define VIU2_VD1_IF0_LUMA_X0 0x1e53 	///../ucode/register.h:7901
#define P_VIU2_VD1_IF0_LUMA_X0 		VCBUS_REG_ADDR(VIU2_VD1_IF0_LUMA_X0)
#define VIU2_VD1_IF0_LUMA_Y0 0x1e54 	///../ucode/register.h:7902
#define P_VIU2_VD1_IF0_LUMA_Y0 		VCBUS_REG_ADDR(VIU2_VD1_IF0_LUMA_Y0)
#define VIU2_VD1_IF0_CHROMA_X0 0x1e55 	///../ucode/register.h:7903
#define P_VIU2_VD1_IF0_CHROMA_X0 		VCBUS_REG_ADDR(VIU2_VD1_IF0_CHROMA_X0)
#define VIU2_VD1_IF0_CHROMA_Y0 0x1e56 	///../ucode/register.h:7904
#define P_VIU2_VD1_IF0_CHROMA_Y0 		VCBUS_REG_ADDR(VIU2_VD1_IF0_CHROMA_Y0)
#define VIU2_VD1_IF0_LUMA_X1 0x1e57 	///../ucode/register.h:7905
#define P_VIU2_VD1_IF0_LUMA_X1 		VCBUS_REG_ADDR(VIU2_VD1_IF0_LUMA_X1)
#define VIU2_VD1_IF0_LUMA_Y1 0x1e58 	///../ucode/register.h:7906
#define P_VIU2_VD1_IF0_LUMA_Y1 		VCBUS_REG_ADDR(VIU2_VD1_IF0_LUMA_Y1)
#define VIU2_VD1_IF0_CHROMA_X1 0x1e59 	///../ucode/register.h:7907
#define P_VIU2_VD1_IF0_CHROMA_X1 		VCBUS_REG_ADDR(VIU2_VD1_IF0_CHROMA_X1)
#define VIU2_VD1_IF0_CHROMA_Y1 0x1e5a 	///../ucode/register.h:7908
#define P_VIU2_VD1_IF0_CHROMA_Y1 		VCBUS_REG_ADDR(VIU2_VD1_IF0_CHROMA_Y1)
#define VIU2_VD1_IF0_RPT_LOOP 0x1e5b 	///../ucode/register.h:7909
#define P_VIU2_VD1_IF0_RPT_LOOP 		VCBUS_REG_ADDR(VIU2_VD1_IF0_RPT_LOOP)
#define VIU2_VD1_IF0_LUMA0_RPT_PAT 0x1e5c 	///../ucode/register.h:7910
#define P_VIU2_VD1_IF0_LUMA0_RPT_PAT 		VCBUS_REG_ADDR(VIU2_VD1_IF0_LUMA0_RPT_PAT)
#define VIU2_VD1_IF0_CHROMA0_RPT_PAT 0x1e5d 	///../ucode/register.h:7911
#define P_VIU2_VD1_IF0_CHROMA0_RPT_PAT 		VCBUS_REG_ADDR(VIU2_VD1_IF0_CHROMA0_RPT_PAT)
#define VIU2_VD1_IF0_LUMA1_RPT_PAT 0x1e5e 	///../ucode/register.h:7912
#define P_VIU2_VD1_IF0_LUMA1_RPT_PAT 		VCBUS_REG_ADDR(VIU2_VD1_IF0_LUMA1_RPT_PAT)
#define VIU2_VD1_IF0_CHROMA1_RPT_PAT 0x1e5f 	///../ucode/register.h:7913
#define P_VIU2_VD1_IF0_CHROMA1_RPT_PAT 		VCBUS_REG_ADDR(VIU2_VD1_IF0_CHROMA1_RPT_PAT)
#define VIU2_VD1_IF0_LUMA_PSEL 0x1e60 	///../ucode/register.h:7914
#define P_VIU2_VD1_IF0_LUMA_PSEL 		VCBUS_REG_ADDR(VIU2_VD1_IF0_LUMA_PSEL)
#define VIU2_VD1_IF0_CHROMA_PSEL 0x1e61 	///../ucode/register.h:7915
#define P_VIU2_VD1_IF0_CHROMA_PSEL 		VCBUS_REG_ADDR(VIU2_VD1_IF0_CHROMA_PSEL)
#define VIU2_VD1_IF0_DUMMY_PIXEL 0x1e62 	///../ucode/register.h:7916
#define P_VIU2_VD1_IF0_DUMMY_PIXEL 		VCBUS_REG_ADDR(VIU2_VD1_IF0_DUMMY_PIXEL)
#define VIU2_VD1_IF0_LUMA_FIFO_SIZE 0x1e63 	///../ucode/register.h:7917
#define P_VIU2_VD1_IF0_LUMA_FIFO_SIZE 		VCBUS_REG_ADDR(VIU2_VD1_IF0_LUMA_FIFO_SIZE)
#define VIU2_VD1_IF0_RANGE_MAP_Y 0x1e6a 	///../ucode/register.h:7918
#define P_VIU2_VD1_IF0_RANGE_MAP_Y 		VCBUS_REG_ADDR(VIU2_VD1_IF0_RANGE_MAP_Y)
#define VIU2_VD1_IF0_RANGE_MAP_CB 0x1e6b 	///../ucode/register.h:7919
#define P_VIU2_VD1_IF0_RANGE_MAP_CB 		VCBUS_REG_ADDR(VIU2_VD1_IF0_RANGE_MAP_CB)
#define VIU2_VD1_IF0_RANGE_MAP_CR 0x1e6c 	///../ucode/register.h:7920
#define P_VIU2_VD1_IF0_RANGE_MAP_CR 		VCBUS_REG_ADDR(VIU2_VD1_IF0_RANGE_MAP_CR)
#define VIU2_VD1_IF0_GEN_REG2 0x1e6d 	///../ucode/register.h:7921
#define P_VIU2_VD1_IF0_GEN_REG2 		VCBUS_REG_ADDR(VIU2_VD1_IF0_GEN_REG2)
#define VIU2_VD1_IF0_PROT_CNTL 0x1e6e 	///../ucode/register.h:7922
#define P_VIU2_VD1_IF0_PROT_CNTL 		VCBUS_REG_ADDR(VIU2_VD1_IF0_PROT_CNTL)
#define VIU2_VD1_FMT_CTRL 0x1e68 	///../ucode/register.h:7939
#define P_VIU2_VD1_FMT_CTRL 		VCBUS_REG_ADDR(VIU2_VD1_FMT_CTRL)
#define VIU2_VD1_FMT_W 0x1e69 	///../ucode/register.h:7942
#define P_VIU2_VD1_FMT_W 		VCBUS_REG_ADDR(VIU2_VD1_FMT_W)
#define ENCP_VFIFO2VD_CTL 0x1b58 	///../ucode/register.h:7959
#define P_ENCP_VFIFO2VD_CTL 		VCBUS_REG_ADDR(ENCP_VFIFO2VD_CTL)
#define ENCP_VFIFO2VD_PIXEL_START 0x1b59 	///../ucode/register.h:7961
#define P_ENCP_VFIFO2VD_PIXEL_START 		VCBUS_REG_ADDR(ENCP_VFIFO2VD_PIXEL_START)
#define ENCP_VFIFO2VD_PIXEL_END 0x1b5a 	///../ucode/register.h:7963
#define P_ENCP_VFIFO2VD_PIXEL_END 		VCBUS_REG_ADDR(ENCP_VFIFO2VD_PIXEL_END)
#define ENCP_VFIFO2VD_LINE_TOP_START 0x1b5b 	///../ucode/register.h:7965
#define P_ENCP_VFIFO2VD_LINE_TOP_START 		VCBUS_REG_ADDR(ENCP_VFIFO2VD_LINE_TOP_START)
#define ENCP_VFIFO2VD_LINE_TOP_END 0x1b5c 	///../ucode/register.h:7967
#define P_ENCP_VFIFO2VD_LINE_TOP_END 		VCBUS_REG_ADDR(ENCP_VFIFO2VD_LINE_TOP_END)
#define ENCP_VFIFO2VD_LINE_BOT_START 0x1b5d 	///../ucode/register.h:7969
#define P_ENCP_VFIFO2VD_LINE_BOT_START 		VCBUS_REG_ADDR(ENCP_VFIFO2VD_LINE_BOT_START)
#define ENCP_VFIFO2VD_LINE_BOT_END 0x1b5e 	///../ucode/register.h:7971
#define P_ENCP_VFIFO2VD_LINE_BOT_END 		VCBUS_REG_ADDR(ENCP_VFIFO2VD_LINE_BOT_END)
#define VENC_SYNC_ROUTE 0x1b60 	///../ucode/register.h:7980
#define P_VENC_SYNC_ROUTE 		VCBUS_REG_ADDR(VENC_SYNC_ROUTE)
#define VENC_VIDEO_EXSRC 0x1b61 	///../ucode/register.h:7984
#define P_VENC_VIDEO_EXSRC 		VCBUS_REG_ADDR(VENC_VIDEO_EXSRC)
#define VENC_DVI_SETTING 0x1b62 	///../ucode/register.h:7985
#define P_VENC_DVI_SETTING 		VCBUS_REG_ADDR(VENC_DVI_SETTING)
#define VENC_C656_CTRL 0x1b63 	///../ucode/register.h:7986
#define P_VENC_C656_CTRL 		VCBUS_REG_ADDR(VENC_C656_CTRL)
#define VENC_UPSAMPLE_CTRL0 0x1b64 	///../ucode/register.h:7987
#define P_VENC_UPSAMPLE_CTRL0 		VCBUS_REG_ADDR(VENC_UPSAMPLE_CTRL0)
#define VENC_UPSAMPLE_CTRL1 0x1b65 	///../ucode/register.h:7988
#define P_VENC_UPSAMPLE_CTRL1 		VCBUS_REG_ADDR(VENC_UPSAMPLE_CTRL1)
#define VENC_UPSAMPLE_CTRL2 0x1b66 	///../ucode/register.h:7989
#define P_VENC_UPSAMPLE_CTRL2 		VCBUS_REG_ADDR(VENC_UPSAMPLE_CTRL2)
#define TCON_INVERT_CTL 0x1b67 	///../ucode/register.h:7993
#define P_TCON_INVERT_CTL 		VCBUS_REG_ADDR(TCON_INVERT_CTL)
#define VENC_VIDEO_PROG_MODE 0x1b68 	///../ucode/register.h:7994
#define P_VENC_VIDEO_PROG_MODE 		VCBUS_REG_ADDR(VENC_VIDEO_PROG_MODE)
#define VENC_ENCI_LINE 0x1b69 	///../ucode/register.h:7996
#define P_VENC_ENCI_LINE 		VCBUS_REG_ADDR(VENC_ENCI_LINE)
#define VENC_ENCI_PIXEL 0x1b6a 	///../ucode/register.h:7997
#define P_VENC_ENCI_PIXEL 		VCBUS_REG_ADDR(VENC_ENCI_PIXEL)
#define VENC_ENCP_LINE 0x1b6b 	///../ucode/register.h:7998
#define P_VENC_ENCP_LINE 		VCBUS_REG_ADDR(VENC_ENCP_LINE)
#define VENC_ENCP_PIXEL 0x1b6c 	///../ucode/register.h:7999
#define P_VENC_ENCP_PIXEL 		VCBUS_REG_ADDR(VENC_ENCP_PIXEL)
#define VENC_STATA 0x1b6d 	///../ucode/register.h:8001
#define P_VENC_STATA 		VCBUS_REG_ADDR(VENC_STATA)
#define VENC_INTCTRL 0x1b6e 	///../ucode/register.h:8003
#define P_VENC_INTCTRL 		VCBUS_REG_ADDR(VENC_INTCTRL)
#define VENC_INTFLAG 0x1b6f 	///../ucode/register.h:8004
#define P_VENC_INTFLAG 		VCBUS_REG_ADDR(VENC_INTFLAG)
#define VENC_VIDEO_TST_EN 0x1b70 	///../ucode/register.h:8006
#define P_VENC_VIDEO_TST_EN 		VCBUS_REG_ADDR(VENC_VIDEO_TST_EN)
#define VENC_VIDEO_TST_MDSEL 0x1b71 	///../ucode/register.h:8007
#define P_VENC_VIDEO_TST_MDSEL 		VCBUS_REG_ADDR(VENC_VIDEO_TST_MDSEL)
#define VENC_VIDEO_TST_Y 0x1b72 	///../ucode/register.h:8008
#define P_VENC_VIDEO_TST_Y 		VCBUS_REG_ADDR(VENC_VIDEO_TST_Y)
#define VENC_VIDEO_TST_CB 0x1b73 	///../ucode/register.h:8009
#define P_VENC_VIDEO_TST_CB 		VCBUS_REG_ADDR(VENC_VIDEO_TST_CB)
#define VENC_VIDEO_TST_CR 0x1b74 	///../ucode/register.h:8010
#define P_VENC_VIDEO_TST_CR 		VCBUS_REG_ADDR(VENC_VIDEO_TST_CR)
#define VENC_VIDEO_TST_CLRBAR_STRT 0x1b75 	///../ucode/register.h:8011
#define P_VENC_VIDEO_TST_CLRBAR_STRT 		VCBUS_REG_ADDR(VENC_VIDEO_TST_CLRBAR_STRT)
#define VENC_VIDEO_TST_CLRBAR_WIDTH 0x1b76 	///../ucode/register.h:8012
#define P_VENC_VIDEO_TST_CLRBAR_WIDTH 		VCBUS_REG_ADDR(VENC_VIDEO_TST_CLRBAR_WIDTH)
#define VENC_VIDEO_TST_VDCNT_STSET 0x1b77 	///../ucode/register.h:8013
#define P_VENC_VIDEO_TST_VDCNT_STSET 		VCBUS_REG_ADDR(VENC_VIDEO_TST_VDCNT_STSET)
#define VENC_VDAC_DACSEL0 0x1b78 	///../ucode/register.h:8015
#define P_VENC_VDAC_DACSEL0 		VCBUS_REG_ADDR(VENC_VDAC_DACSEL0)
#define VENC_VDAC_DACSEL1 0x1b79 	///../ucode/register.h:8016
#define P_VENC_VDAC_DACSEL1 		VCBUS_REG_ADDR(VENC_VDAC_DACSEL1)
#define VENC_VDAC_DACSEL2 0x1b7a 	///../ucode/register.h:8017
#define P_VENC_VDAC_DACSEL2 		VCBUS_REG_ADDR(VENC_VDAC_DACSEL2)
#define VENC_VDAC_DACSEL3 0x1b7b 	///../ucode/register.h:8018
#define P_VENC_VDAC_DACSEL3 		VCBUS_REG_ADDR(VENC_VDAC_DACSEL3)
#define VENC_VDAC_DACSEL4 0x1b7c 	///../ucode/register.h:8019
#define P_VENC_VDAC_DACSEL4 		VCBUS_REG_ADDR(VENC_VDAC_DACSEL4)
#define VENC_VDAC_DACSEL5 0x1b7d 	///../ucode/register.h:8020
#define P_VENC_VDAC_DACSEL5 		VCBUS_REG_ADDR(VENC_VDAC_DACSEL5)
#define VENC_VDAC_SETTING 0x1b7e 	///../ucode/register.h:8021
#define P_VENC_VDAC_SETTING 		VCBUS_REG_ADDR(VENC_VDAC_SETTING)
#define VENC_VDAC_TST_VAL 0x1b7f 	///../ucode/register.h:8022
#define P_VENC_VDAC_TST_VAL 		VCBUS_REG_ADDR(VENC_VDAC_TST_VAL)
#define VENC_VDAC_DAC0_GAINCTRL 0x1bf0 	///../ucode/register.h:8023
#define P_VENC_VDAC_DAC0_GAINCTRL 		VCBUS_REG_ADDR(VENC_VDAC_DAC0_GAINCTRL)
#define VENC_VDAC_DAC0_OFFSET 0x1bf1 	///../ucode/register.h:8024
#define P_VENC_VDAC_DAC0_OFFSET 		VCBUS_REG_ADDR(VENC_VDAC_DAC0_OFFSET)
#define VENC_VDAC_DAC1_GAINCTRL 0x1bf2 	///../ucode/register.h:8025
#define P_VENC_VDAC_DAC1_GAINCTRL 		VCBUS_REG_ADDR(VENC_VDAC_DAC1_GAINCTRL)
#define VENC_VDAC_DAC1_OFFSET 0x1bf3 	///../ucode/register.h:8026
#define P_VENC_VDAC_DAC1_OFFSET 		VCBUS_REG_ADDR(VENC_VDAC_DAC1_OFFSET)
#define VENC_VDAC_DAC2_GAINCTRL 0x1bf4 	///../ucode/register.h:8027
#define P_VENC_VDAC_DAC2_GAINCTRL 		VCBUS_REG_ADDR(VENC_VDAC_DAC2_GAINCTRL)
#define VENC_VDAC_DAC2_OFFSET 0x1bf5 	///../ucode/register.h:8028
#define P_VENC_VDAC_DAC2_OFFSET 		VCBUS_REG_ADDR(VENC_VDAC_DAC2_OFFSET)
#define VENC_VDAC_DAC3_GAINCTRL 0x1bf6 	///../ucode/register.h:8029
#define P_VENC_VDAC_DAC3_GAINCTRL 		VCBUS_REG_ADDR(VENC_VDAC_DAC3_GAINCTRL)
#define VENC_VDAC_DAC3_OFFSET 0x1bf7 	///../ucode/register.h:8030
#define P_VENC_VDAC_DAC3_OFFSET 		VCBUS_REG_ADDR(VENC_VDAC_DAC3_OFFSET)
#define VENC_VDAC_DAC4_GAINCTRL 0x1bf8 	///../ucode/register.h:8031
#define P_VENC_VDAC_DAC4_GAINCTRL 		VCBUS_REG_ADDR(VENC_VDAC_DAC4_GAINCTRL)
#define VENC_VDAC_DAC4_OFFSET 0x1bf9 	///../ucode/register.h:8032
#define P_VENC_VDAC_DAC4_OFFSET 		VCBUS_REG_ADDR(VENC_VDAC_DAC4_OFFSET)
#define VENC_VDAC_DAC5_GAINCTRL 0x1bfa 	///../ucode/register.h:8033
#define P_VENC_VDAC_DAC5_GAINCTRL 		VCBUS_REG_ADDR(VENC_VDAC_DAC5_GAINCTRL)
#define VENC_VDAC_DAC5_OFFSET 0x1bfb 	///../ucode/register.h:8034
#define P_VENC_VDAC_DAC5_OFFSET 		VCBUS_REG_ADDR(VENC_VDAC_DAC5_OFFSET)
#define VENC_VDAC_FIFO_CTRL 0x1bfc 	///../ucode/register.h:8035
#define P_VENC_VDAC_FIFO_CTRL 		VCBUS_REG_ADDR(VENC_VDAC_FIFO_CTRL)
#define ENCL_TCON_INVERT_CTL 0x1bfd 	///../ucode/register.h:8036
#define P_ENCL_TCON_INVERT_CTL 		VCBUS_REG_ADDR(ENCL_TCON_INVERT_CTL)
#define ENCP_VIDEO_EN 0x1b80 	///../ucode/register.h:8049
#define P_ENCP_VIDEO_EN 		VCBUS_REG_ADDR(ENCP_VIDEO_EN)
#define ENCP_VIDEO_SYNC_MODE 0x1b81 	///../ucode/register.h:8050
#define P_ENCP_VIDEO_SYNC_MODE 		VCBUS_REG_ADDR(ENCP_VIDEO_SYNC_MODE)
#define ENCP_MACV_EN 0x1b82 	///../ucode/register.h:8051
#define P_ENCP_MACV_EN 		VCBUS_REG_ADDR(ENCP_MACV_EN)
#define ENCP_VIDEO_Y_SCL 0x1b83 	///../ucode/register.h:8052
#define P_ENCP_VIDEO_Y_SCL 		VCBUS_REG_ADDR(ENCP_VIDEO_Y_SCL)
#define ENCP_VIDEO_PB_SCL 0x1b84 	///../ucode/register.h:8053
#define P_ENCP_VIDEO_PB_SCL 		VCBUS_REG_ADDR(ENCP_VIDEO_PB_SCL)
#define ENCP_VIDEO_PR_SCL 0x1b85 	///../ucode/register.h:8054
#define P_ENCP_VIDEO_PR_SCL 		VCBUS_REG_ADDR(ENCP_VIDEO_PR_SCL)
#define ENCP_VIDEO_SYNC_SCL 0x1b86 	///../ucode/register.h:8055
#define P_ENCP_VIDEO_SYNC_SCL 		VCBUS_REG_ADDR(ENCP_VIDEO_SYNC_SCL)
#define ENCP_VIDEO_MACV_SCL 0x1b87 	///../ucode/register.h:8056
#define P_ENCP_VIDEO_MACV_SCL 		VCBUS_REG_ADDR(ENCP_VIDEO_MACV_SCL)
#define ENCP_VIDEO_Y_OFFST 0x1b88 	///../ucode/register.h:8057
#define P_ENCP_VIDEO_Y_OFFST 		VCBUS_REG_ADDR(ENCP_VIDEO_Y_OFFST)
#define ENCP_VIDEO_PB_OFFST 0x1b89 	///../ucode/register.h:8058
#define P_ENCP_VIDEO_PB_OFFST 		VCBUS_REG_ADDR(ENCP_VIDEO_PB_OFFST)
#define ENCP_VIDEO_PR_OFFST 0x1b8a 	///../ucode/register.h:8059
#define P_ENCP_VIDEO_PR_OFFST 		VCBUS_REG_ADDR(ENCP_VIDEO_PR_OFFST)
#define ENCP_VIDEO_SYNC_OFFST 0x1b8b 	///../ucode/register.h:8060
#define P_ENCP_VIDEO_SYNC_OFFST 		VCBUS_REG_ADDR(ENCP_VIDEO_SYNC_OFFST)
#define ENCP_VIDEO_MACV_OFFST 0x1b8c 	///../ucode/register.h:8061
#define P_ENCP_VIDEO_MACV_OFFST 		VCBUS_REG_ADDR(ENCP_VIDEO_MACV_OFFST)
#define ENCP_VIDEO_MODE 0x1b8d 	///../ucode/register.h:8063
#define P_ENCP_VIDEO_MODE 		VCBUS_REG_ADDR(ENCP_VIDEO_MODE)
#define ENCP_VIDEO_MODE_ADV 0x1b8e 	///../ucode/register.h:8064
#define P_ENCP_VIDEO_MODE_ADV 		VCBUS_REG_ADDR(ENCP_VIDEO_MODE_ADV)
#define ENCP_DBG_PX_RST 0x1b90 	///../ucode/register.h:8066
#define P_ENCP_DBG_PX_RST 		VCBUS_REG_ADDR(ENCP_DBG_PX_RST)
#define ENCP_DBG_LN_RST 0x1b91 	///../ucode/register.h:8067
#define P_ENCP_DBG_LN_RST 		VCBUS_REG_ADDR(ENCP_DBG_LN_RST)
#define ENCP_DBG_PX_INT 0x1b92 	///../ucode/register.h:8068
#define P_ENCP_DBG_PX_INT 		VCBUS_REG_ADDR(ENCP_DBG_PX_INT)
#define ENCP_DBG_LN_INT 0x1b93 	///../ucode/register.h:8069
#define P_ENCP_DBG_LN_INT 		VCBUS_REG_ADDR(ENCP_DBG_LN_INT)
#define ENCP_VIDEO_YFP1_HTIME 0x1b94 	///../ucode/register.h:8071
#define P_ENCP_VIDEO_YFP1_HTIME 		VCBUS_REG_ADDR(ENCP_VIDEO_YFP1_HTIME)
#define ENCP_VIDEO_YFP2_HTIME 0x1b95 	///../ucode/register.h:8072
#define P_ENCP_VIDEO_YFP2_HTIME 		VCBUS_REG_ADDR(ENCP_VIDEO_YFP2_HTIME)
#define ENCP_VIDEO_YC_DLY 0x1b96 	///../ucode/register.h:8073
#define P_ENCP_VIDEO_YC_DLY 		VCBUS_REG_ADDR(ENCP_VIDEO_YC_DLY)
#define ENCP_VIDEO_MAX_PXCNT 0x1b97 	///../ucode/register.h:8074
#define P_ENCP_VIDEO_MAX_PXCNT 		VCBUS_REG_ADDR(ENCP_VIDEO_MAX_PXCNT)
#define ENCP_VIDEO_HSPULS_BEGIN 0x1b98 	///../ucode/register.h:8075
#define P_ENCP_VIDEO_HSPULS_BEGIN 		VCBUS_REG_ADDR(ENCP_VIDEO_HSPULS_BEGIN)
#define ENCP_VIDEO_HSPULS_END 0x1b99 	///../ucode/register.h:8076
#define P_ENCP_VIDEO_HSPULS_END 		VCBUS_REG_ADDR(ENCP_VIDEO_HSPULS_END)
#define ENCP_VIDEO_HSPULS_SWITCH 0x1b9a 	///../ucode/register.h:8077
#define P_ENCP_VIDEO_HSPULS_SWITCH 		VCBUS_REG_ADDR(ENCP_VIDEO_HSPULS_SWITCH)
#define ENCP_VIDEO_VSPULS_BEGIN 0x1b9b 	///../ucode/register.h:8078
#define P_ENCP_VIDEO_VSPULS_BEGIN 		VCBUS_REG_ADDR(ENCP_VIDEO_VSPULS_BEGIN)
#define ENCP_VIDEO_VSPULS_END 0x1b9c 	///../ucode/register.h:8079
#define P_ENCP_VIDEO_VSPULS_END 		VCBUS_REG_ADDR(ENCP_VIDEO_VSPULS_END)
#define ENCP_VIDEO_VSPULS_BLINE 0x1b9d 	///../ucode/register.h:8080
#define P_ENCP_VIDEO_VSPULS_BLINE 		VCBUS_REG_ADDR(ENCP_VIDEO_VSPULS_BLINE)
#define ENCP_VIDEO_VSPULS_ELINE 0x1b9e 	///../ucode/register.h:8081
#define P_ENCP_VIDEO_VSPULS_ELINE 		VCBUS_REG_ADDR(ENCP_VIDEO_VSPULS_ELINE)
#define ENCP_VIDEO_EQPULS_BEGIN 0x1b9f 	///../ucode/register.h:8082
#define P_ENCP_VIDEO_EQPULS_BEGIN 		VCBUS_REG_ADDR(ENCP_VIDEO_EQPULS_BEGIN)
#define ENCP_VIDEO_EQPULS_END 0x1ba0 	///../ucode/register.h:8083
#define P_ENCP_VIDEO_EQPULS_END 		VCBUS_REG_ADDR(ENCP_VIDEO_EQPULS_END)
#define ENCP_VIDEO_EQPULS_BLINE 0x1ba1 	///../ucode/register.h:8084
#define P_ENCP_VIDEO_EQPULS_BLINE 		VCBUS_REG_ADDR(ENCP_VIDEO_EQPULS_BLINE)
#define ENCP_VIDEO_EQPULS_ELINE 0x1ba2 	///../ucode/register.h:8085
#define P_ENCP_VIDEO_EQPULS_ELINE 		VCBUS_REG_ADDR(ENCP_VIDEO_EQPULS_ELINE)
#define ENCP_VIDEO_HAVON_END 0x1ba3 	///../ucode/register.h:8086
#define P_ENCP_VIDEO_HAVON_END 		VCBUS_REG_ADDR(ENCP_VIDEO_HAVON_END)
#define ENCP_VIDEO_HAVON_BEGIN 0x1ba4 	///../ucode/register.h:8087
#define P_ENCP_VIDEO_HAVON_BEGIN 		VCBUS_REG_ADDR(ENCP_VIDEO_HAVON_BEGIN)
#define ENCP_VIDEO_VAVON_ELINE 0x1baf 	///../ucode/register.h:8088
#define P_ENCP_VIDEO_VAVON_ELINE 		VCBUS_REG_ADDR(ENCP_VIDEO_VAVON_ELINE)
#define ENCP_VIDEO_VAVON_BLINE 0x1ba6 	///../ucode/register.h:8089
#define P_ENCP_VIDEO_VAVON_BLINE 		VCBUS_REG_ADDR(ENCP_VIDEO_VAVON_BLINE)
#define ENCP_VIDEO_HSO_BEGIN 0x1ba7 	///../ucode/register.h:8090
#define P_ENCP_VIDEO_HSO_BEGIN 		VCBUS_REG_ADDR(ENCP_VIDEO_HSO_BEGIN)
#define ENCP_VIDEO_HSO_END 0x1ba8 	///../ucode/register.h:8091
#define P_ENCP_VIDEO_HSO_END 		VCBUS_REG_ADDR(ENCP_VIDEO_HSO_END)
#define ENCP_VIDEO_VSO_BEGIN 0x1ba9 	///../ucode/register.h:8092
#define P_ENCP_VIDEO_VSO_BEGIN 		VCBUS_REG_ADDR(ENCP_VIDEO_VSO_BEGIN)
#define ENCP_VIDEO_VSO_END 0x1baa 	///../ucode/register.h:8093
#define P_ENCP_VIDEO_VSO_END 		VCBUS_REG_ADDR(ENCP_VIDEO_VSO_END)
#define ENCP_VIDEO_VSO_BLINE 0x1bab 	///../ucode/register.h:8094
#define P_ENCP_VIDEO_VSO_BLINE 		VCBUS_REG_ADDR(ENCP_VIDEO_VSO_BLINE)
#define ENCP_VIDEO_VSO_ELINE 0x1bac 	///../ucode/register.h:8095
#define P_ENCP_VIDEO_VSO_ELINE 		VCBUS_REG_ADDR(ENCP_VIDEO_VSO_ELINE)
#define ENCP_VIDEO_SYNC_WAVE_CURVE 0x1bad 	///../ucode/register.h:8096
#define P_ENCP_VIDEO_SYNC_WAVE_CURVE 		VCBUS_REG_ADDR(ENCP_VIDEO_SYNC_WAVE_CURVE)
#define ENCP_VIDEO_MAX_LNCNT 0x1bae 	///../ucode/register.h:8097
#define P_ENCP_VIDEO_MAX_LNCNT 		VCBUS_REG_ADDR(ENCP_VIDEO_MAX_LNCNT)
#define ENCP_VIDEO_SY_VAL 0x1bb0 	///../ucode/register.h:8098
#define P_ENCP_VIDEO_SY_VAL 		VCBUS_REG_ADDR(ENCP_VIDEO_SY_VAL)
#define ENCP_VIDEO_SY2_VAL 0x1bb1 	///../ucode/register.h:8099
#define P_ENCP_VIDEO_SY2_VAL 		VCBUS_REG_ADDR(ENCP_VIDEO_SY2_VAL)
#define ENCP_VIDEO_BLANKY_VAL 0x1bb2 	///../ucode/register.h:8100
#define P_ENCP_VIDEO_BLANKY_VAL 		VCBUS_REG_ADDR(ENCP_VIDEO_BLANKY_VAL)
#define ENCP_VIDEO_BLANKPB_VAL 0x1bb3 	///../ucode/register.h:8101
#define P_ENCP_VIDEO_BLANKPB_VAL 		VCBUS_REG_ADDR(ENCP_VIDEO_BLANKPB_VAL)
#define ENCP_VIDEO_BLANKPR_VAL 0x1bb4 	///../ucode/register.h:8102
#define P_ENCP_VIDEO_BLANKPR_VAL 		VCBUS_REG_ADDR(ENCP_VIDEO_BLANKPR_VAL)
#define ENCP_VIDEO_HOFFST 0x1bb5 	///../ucode/register.h:8103
#define P_ENCP_VIDEO_HOFFST 		VCBUS_REG_ADDR(ENCP_VIDEO_HOFFST)
#define ENCP_VIDEO_VOFFST 0x1bb6 	///../ucode/register.h:8104
#define P_ENCP_VIDEO_VOFFST 		VCBUS_REG_ADDR(ENCP_VIDEO_VOFFST)
#define ENCP_VIDEO_RGB_CTRL 0x1bb7 	///../ucode/register.h:8105
#define P_ENCP_VIDEO_RGB_CTRL 		VCBUS_REG_ADDR(ENCP_VIDEO_RGB_CTRL)
#define ENCP_VIDEO_FILT_CTRL 0x1bb8 	///../ucode/register.h:8106
#define P_ENCP_VIDEO_FILT_CTRL 		VCBUS_REG_ADDR(ENCP_VIDEO_FILT_CTRL)
#define ENCP_VIDEO_OFLD_VPEQ_OFST 0x1bb9 	///../ucode/register.h:8107
#define P_ENCP_VIDEO_OFLD_VPEQ_OFST 		VCBUS_REG_ADDR(ENCP_VIDEO_OFLD_VPEQ_OFST)
#define ENCP_VIDEO_OFLD_VOAV_OFST 0x1bba 	///../ucode/register.h:8108
#define P_ENCP_VIDEO_OFLD_VOAV_OFST 		VCBUS_REG_ADDR(ENCP_VIDEO_OFLD_VOAV_OFST)
#define ENCP_VIDEO_MATRIX_CB 0x1bbb 	///../ucode/register.h:8109
#define P_ENCP_VIDEO_MATRIX_CB 		VCBUS_REG_ADDR(ENCP_VIDEO_MATRIX_CB)
#define ENCP_VIDEO_MATRIX_CR 0x1bbc 	///../ucode/register.h:8110
#define P_ENCP_VIDEO_MATRIX_CR 		VCBUS_REG_ADDR(ENCP_VIDEO_MATRIX_CR)
#define ENCP_VIDEO_RGBIN_CTRL 0x1bbd 	///../ucode/register.h:8111
#define P_ENCP_VIDEO_RGBIN_CTRL 		VCBUS_REG_ADDR(ENCP_VIDEO_RGBIN_CTRL)
#define ENCP_MACV_BLANKY_VAL 0x1bc0 	///../ucode/register.h:8113
#define P_ENCP_MACV_BLANKY_VAL 		VCBUS_REG_ADDR(ENCP_MACV_BLANKY_VAL)
#define ENCP_MACV_MAXY_VAL 0x1bc1 	///../ucode/register.h:8114
#define P_ENCP_MACV_MAXY_VAL 		VCBUS_REG_ADDR(ENCP_MACV_MAXY_VAL)
#define ENCP_MACV_1ST_PSSYNC_STRT 0x1bc2 	///../ucode/register.h:8115
#define P_ENCP_MACV_1ST_PSSYNC_STRT 		VCBUS_REG_ADDR(ENCP_MACV_1ST_PSSYNC_STRT)
#define ENCP_MACV_PSSYNC_STRT 0x1bc3 	///../ucode/register.h:8116
#define P_ENCP_MACV_PSSYNC_STRT 		VCBUS_REG_ADDR(ENCP_MACV_PSSYNC_STRT)
#define ENCP_MACV_AGC_STRT 0x1bc4 	///../ucode/register.h:8117
#define P_ENCP_MACV_AGC_STRT 		VCBUS_REG_ADDR(ENCP_MACV_AGC_STRT)
#define ENCP_MACV_AGC_END 0x1bc5 	///../ucode/register.h:8118
#define P_ENCP_MACV_AGC_END 		VCBUS_REG_ADDR(ENCP_MACV_AGC_END)
#define ENCP_MACV_WAVE_END 0x1bc6 	///../ucode/register.h:8119
#define P_ENCP_MACV_WAVE_END 		VCBUS_REG_ADDR(ENCP_MACV_WAVE_END)
#define ENCP_MACV_STRTLINE 0x1bc7 	///../ucode/register.h:8120
#define P_ENCP_MACV_STRTLINE 		VCBUS_REG_ADDR(ENCP_MACV_STRTLINE)
#define ENCP_MACV_ENDLINE 0x1bc8 	///../ucode/register.h:8121
#define P_ENCP_MACV_ENDLINE 		VCBUS_REG_ADDR(ENCP_MACV_ENDLINE)
#define ENCP_MACV_TS_CNT_MAX_L 0x1bc9 	///../ucode/register.h:8122
#define P_ENCP_MACV_TS_CNT_MAX_L 		VCBUS_REG_ADDR(ENCP_MACV_TS_CNT_MAX_L)
#define ENCP_MACV_TS_CNT_MAX_H 0x1bca 	///../ucode/register.h:8123
#define P_ENCP_MACV_TS_CNT_MAX_H 		VCBUS_REG_ADDR(ENCP_MACV_TS_CNT_MAX_H)
#define ENCP_MACV_TIME_DOWN 0x1bcb 	///../ucode/register.h:8124
#define P_ENCP_MACV_TIME_DOWN 		VCBUS_REG_ADDR(ENCP_MACV_TIME_DOWN)
#define ENCP_MACV_TIME_LO 0x1bcc 	///../ucode/register.h:8125
#define P_ENCP_MACV_TIME_LO 		VCBUS_REG_ADDR(ENCP_MACV_TIME_LO)
#define ENCP_MACV_TIME_UP 0x1bcd 	///../ucode/register.h:8126
#define P_ENCP_MACV_TIME_UP 		VCBUS_REG_ADDR(ENCP_MACV_TIME_UP)
#define ENCP_MACV_TIME_RST 0x1bce 	///../ucode/register.h:8127
#define P_ENCP_MACV_TIME_RST 		VCBUS_REG_ADDR(ENCP_MACV_TIME_RST)
#define ENCP_VBI_CTRL 0x1bd0 	///../ucode/register.h:8129
#define P_ENCP_VBI_CTRL 		VCBUS_REG_ADDR(ENCP_VBI_CTRL)
#define ENCP_VBI_SETTING 0x1bd1 	///../ucode/register.h:8130
#define P_ENCP_VBI_SETTING 		VCBUS_REG_ADDR(ENCP_VBI_SETTING)
#define ENCP_VBI_BEGIN 0x1bd2 	///../ucode/register.h:8131
#define P_ENCP_VBI_BEGIN 		VCBUS_REG_ADDR(ENCP_VBI_BEGIN)
#define ENCP_VBI_WIDTH 0x1bd3 	///../ucode/register.h:8132
#define P_ENCP_VBI_WIDTH 		VCBUS_REG_ADDR(ENCP_VBI_WIDTH)
#define ENCP_VBI_HVAL 0x1bd4 	///../ucode/register.h:8133
#define P_ENCP_VBI_HVAL 		VCBUS_REG_ADDR(ENCP_VBI_HVAL)
#define ENCP_VBI_DATA0 0x1bd5 	///../ucode/register.h:8134
#define P_ENCP_VBI_DATA0 		VCBUS_REG_ADDR(ENCP_VBI_DATA0)
#define ENCP_VBI_DATA1 0x1bd6 	///../ucode/register.h:8135
#define P_ENCP_VBI_DATA1 		VCBUS_REG_ADDR(ENCP_VBI_DATA1)
#define C656_HS_ST 0x1be0 	///../ucode/register.h:8137
#define P_C656_HS_ST 		VCBUS_REG_ADDR(C656_HS_ST)
#define C656_HS_ED 0x1be1 	///../ucode/register.h:8138
#define P_C656_HS_ED 		VCBUS_REG_ADDR(C656_HS_ED)
#define C656_VS_LNST_E 0x1be2 	///../ucode/register.h:8139
#define P_C656_VS_LNST_E 		VCBUS_REG_ADDR(C656_VS_LNST_E)
#define C656_VS_LNST_O 0x1be3 	///../ucode/register.h:8140
#define P_C656_VS_LNST_O 		VCBUS_REG_ADDR(C656_VS_LNST_O)
#define C656_VS_LNED_E 0x1be4 	///../ucode/register.h:8141
#define P_C656_VS_LNED_E 		VCBUS_REG_ADDR(C656_VS_LNED_E)
#define C656_VS_LNED_O 0x1be5 	///../ucode/register.h:8142
#define P_C656_VS_LNED_O 		VCBUS_REG_ADDR(C656_VS_LNED_O)
#define C656_FS_LNST 0x1be6 	///../ucode/register.h:8143
#define P_C656_FS_LNST 		VCBUS_REG_ADDR(C656_FS_LNST)
#define C656_FS_LNED 0x1be7 	///../ucode/register.h:8144
#define P_C656_FS_LNED 		VCBUS_REG_ADDR(C656_FS_LNED)
#define ENCI_VIDEO_MODE 0x1b00 	///../ucode/register.h:8156
#define P_ENCI_VIDEO_MODE 		VCBUS_REG_ADDR(ENCI_VIDEO_MODE)
#define ENCI_VIDEO_MODE_ADV 0x1b01 	///../ucode/register.h:8157
#define P_ENCI_VIDEO_MODE_ADV 		VCBUS_REG_ADDR(ENCI_VIDEO_MODE_ADV)
#define ENCI_VIDEO_FSC_ADJ 0x1b02 	///../ucode/register.h:8158
#define P_ENCI_VIDEO_FSC_ADJ 		VCBUS_REG_ADDR(ENCI_VIDEO_FSC_ADJ)
#define ENCI_VIDEO_BRIGHT 0x1b03 	///../ucode/register.h:8159
#define P_ENCI_VIDEO_BRIGHT 		VCBUS_REG_ADDR(ENCI_VIDEO_BRIGHT)
#define ENCI_VIDEO_CONT 0x1b04 	///../ucode/register.h:8160
#define P_ENCI_VIDEO_CONT 		VCBUS_REG_ADDR(ENCI_VIDEO_CONT)
#define ENCI_VIDEO_SAT 0x1b05 	///../ucode/register.h:8161
#define P_ENCI_VIDEO_SAT 		VCBUS_REG_ADDR(ENCI_VIDEO_SAT)
#define ENCI_VIDEO_HUE 0x1b06 	///../ucode/register.h:8162
#define P_ENCI_VIDEO_HUE 		VCBUS_REG_ADDR(ENCI_VIDEO_HUE)
#define ENCI_VIDEO_SCH 0x1b07 	///../ucode/register.h:8163
#define P_ENCI_VIDEO_SCH 		VCBUS_REG_ADDR(ENCI_VIDEO_SCH)
#define ENCI_SYNC_MODE 0x1b08 	///../ucode/register.h:8164
#define P_ENCI_SYNC_MODE 		VCBUS_REG_ADDR(ENCI_SYNC_MODE)
#define ENCI_SYNC_CTRL 0x1b09 	///../ucode/register.h:8165
#define P_ENCI_SYNC_CTRL 		VCBUS_REG_ADDR(ENCI_SYNC_CTRL)
#define ENCI_SYNC_HSO_BEGIN 0x1b0a 	///../ucode/register.h:8166
#define P_ENCI_SYNC_HSO_BEGIN 		VCBUS_REG_ADDR(ENCI_SYNC_HSO_BEGIN)
#define ENCI_SYNC_HSO_END 0x1b0b 	///../ucode/register.h:8167
#define P_ENCI_SYNC_HSO_END 		VCBUS_REG_ADDR(ENCI_SYNC_HSO_END)
#define ENCI_SYNC_VSO_EVN 0x1b0c 	///../ucode/register.h:8168
#define P_ENCI_SYNC_VSO_EVN 		VCBUS_REG_ADDR(ENCI_SYNC_VSO_EVN)
#define ENCI_SYNC_VSO_ODD 0x1b0d 	///../ucode/register.h:8169
#define P_ENCI_SYNC_VSO_ODD 		VCBUS_REG_ADDR(ENCI_SYNC_VSO_ODD)
#define ENCI_SYNC_VSO_EVNLN 0x1b0e 	///../ucode/register.h:8170
#define P_ENCI_SYNC_VSO_EVNLN 		VCBUS_REG_ADDR(ENCI_SYNC_VSO_EVNLN)
#define ENCI_SYNC_VSO_ODDLN 0x1b0f 	///../ucode/register.h:8171
#define P_ENCI_SYNC_VSO_ODDLN 		VCBUS_REG_ADDR(ENCI_SYNC_VSO_ODDLN)
#define ENCI_SYNC_HOFFST 0x1b10 	///../ucode/register.h:8172
#define P_ENCI_SYNC_HOFFST 		VCBUS_REG_ADDR(ENCI_SYNC_HOFFST)
#define ENCI_SYNC_VOFFST 0x1b11 	///../ucode/register.h:8173
#define P_ENCI_SYNC_VOFFST 		VCBUS_REG_ADDR(ENCI_SYNC_VOFFST)
#define ENCI_SYNC_ADJ 0x1b12 	///../ucode/register.h:8174
#define P_ENCI_SYNC_ADJ 		VCBUS_REG_ADDR(ENCI_SYNC_ADJ)
#define ENCI_RGB_SETTING 0x1b13 	///../ucode/register.h:8175
#define P_ENCI_RGB_SETTING 		VCBUS_REG_ADDR(ENCI_RGB_SETTING)
#define ENCI_DE_H_BEGIN 0x1b16 	///../ucode/register.h:8178
#define P_ENCI_DE_H_BEGIN 		VCBUS_REG_ADDR(ENCI_DE_H_BEGIN)
#define ENCI_DE_H_END 0x1b17 	///../ucode/register.h:8179
#define P_ENCI_DE_H_END 		VCBUS_REG_ADDR(ENCI_DE_H_END)
#define ENCI_DE_V_BEGIN_EVEN 0x1b18 	///../ucode/register.h:8180
#define P_ENCI_DE_V_BEGIN_EVEN 		VCBUS_REG_ADDR(ENCI_DE_V_BEGIN_EVEN)
#define ENCI_DE_V_END_EVEN 0x1b19 	///../ucode/register.h:8181
#define P_ENCI_DE_V_END_EVEN 		VCBUS_REG_ADDR(ENCI_DE_V_END_EVEN)
#define ENCI_DE_V_BEGIN_ODD 0x1b1a 	///../ucode/register.h:8182
#define P_ENCI_DE_V_BEGIN_ODD 		VCBUS_REG_ADDR(ENCI_DE_V_BEGIN_ODD)
#define ENCI_DE_V_END_ODD 0x1b1b 	///../ucode/register.h:8183
#define P_ENCI_DE_V_END_ODD 		VCBUS_REG_ADDR(ENCI_DE_V_END_ODD)
#define ENCI_VBI_SETTING 0x1b20 	///../ucode/register.h:8184
#define P_ENCI_VBI_SETTING 		VCBUS_REG_ADDR(ENCI_VBI_SETTING)
#define ENCI_VBI_CCDT_EVN 0x1b21 	///../ucode/register.h:8185
#define P_ENCI_VBI_CCDT_EVN 		VCBUS_REG_ADDR(ENCI_VBI_CCDT_EVN)
#define ENCI_VBI_CCDT_ODD 0x1b22 	///../ucode/register.h:8186
#define P_ENCI_VBI_CCDT_ODD 		VCBUS_REG_ADDR(ENCI_VBI_CCDT_ODD)
#define ENCI_VBI_CC525_LN 0x1b23 	///../ucode/register.h:8187
#define P_ENCI_VBI_CC525_LN 		VCBUS_REG_ADDR(ENCI_VBI_CC525_LN)
#define ENCI_VBI_CC625_LN 0x1b24 	///../ucode/register.h:8188
#define P_ENCI_VBI_CC625_LN 		VCBUS_REG_ADDR(ENCI_VBI_CC625_LN)
#define ENCI_VBI_WSSDT 0x1b25 	///../ucode/register.h:8189
#define P_ENCI_VBI_WSSDT 		VCBUS_REG_ADDR(ENCI_VBI_WSSDT)
#define ENCI_VBI_WSS_LN 0x1b26 	///../ucode/register.h:8190
#define P_ENCI_VBI_WSS_LN 		VCBUS_REG_ADDR(ENCI_VBI_WSS_LN)
#define ENCI_VBI_CGMSDT_L 0x1b27 	///../ucode/register.h:8191
#define P_ENCI_VBI_CGMSDT_L 		VCBUS_REG_ADDR(ENCI_VBI_CGMSDT_L)
#define ENCI_VBI_CGMSDT_H 0x1b28 	///../ucode/register.h:8192
#define P_ENCI_VBI_CGMSDT_H 		VCBUS_REG_ADDR(ENCI_VBI_CGMSDT_H)
#define ENCI_VBI_CGMS_LN 0x1b29 	///../ucode/register.h:8193
#define P_ENCI_VBI_CGMS_LN 		VCBUS_REG_ADDR(ENCI_VBI_CGMS_LN)
#define ENCI_VBI_TTX_HTIME 0x1b2a 	///../ucode/register.h:8194
#define P_ENCI_VBI_TTX_HTIME 		VCBUS_REG_ADDR(ENCI_VBI_TTX_HTIME)
#define ENCI_VBI_TTX_LN 0x1b2b 	///../ucode/register.h:8195
#define P_ENCI_VBI_TTX_LN 		VCBUS_REG_ADDR(ENCI_VBI_TTX_LN)
#define ENCI_VBI_TTXDT0 0x1b2c 	///../ucode/register.h:8196
#define P_ENCI_VBI_TTXDT0 		VCBUS_REG_ADDR(ENCI_VBI_TTXDT0)
#define ENCI_VBI_TTXDT1 0x1b2d 	///../ucode/register.h:8197
#define P_ENCI_VBI_TTXDT1 		VCBUS_REG_ADDR(ENCI_VBI_TTXDT1)
#define ENCI_VBI_TTXDT2 0x1b2e 	///../ucode/register.h:8198
#define P_ENCI_VBI_TTXDT2 		VCBUS_REG_ADDR(ENCI_VBI_TTXDT2)
#define ENCI_VBI_TTXDT3 0x1b2f 	///../ucode/register.h:8199
#define P_ENCI_VBI_TTXDT3 		VCBUS_REG_ADDR(ENCI_VBI_TTXDT3)
#define ENCI_MACV_N0 0x1b30 	///../ucode/register.h:8200
#define P_ENCI_MACV_N0 		VCBUS_REG_ADDR(ENCI_MACV_N0)
#define ENCI_MACV_N1 0x1b31 	///../ucode/register.h:8201
#define P_ENCI_MACV_N1 		VCBUS_REG_ADDR(ENCI_MACV_N1)
#define ENCI_MACV_N2 0x1b32 	///../ucode/register.h:8202
#define P_ENCI_MACV_N2 		VCBUS_REG_ADDR(ENCI_MACV_N2)
#define ENCI_MACV_N3 0x1b33 	///../ucode/register.h:8203
#define P_ENCI_MACV_N3 		VCBUS_REG_ADDR(ENCI_MACV_N3)
#define ENCI_MACV_N4 0x1b34 	///../ucode/register.h:8204
#define P_ENCI_MACV_N4 		VCBUS_REG_ADDR(ENCI_MACV_N4)
#define ENCI_MACV_N5 0x1b35 	///../ucode/register.h:8205
#define P_ENCI_MACV_N5 		VCBUS_REG_ADDR(ENCI_MACV_N5)
#define ENCI_MACV_N6 0x1b36 	///../ucode/register.h:8206
#define P_ENCI_MACV_N6 		VCBUS_REG_ADDR(ENCI_MACV_N6)
#define ENCI_MACV_N7 0x1b37 	///../ucode/register.h:8207
#define P_ENCI_MACV_N7 		VCBUS_REG_ADDR(ENCI_MACV_N7)
#define ENCI_MACV_N8 0x1b38 	///../ucode/register.h:8208
#define P_ENCI_MACV_N8 		VCBUS_REG_ADDR(ENCI_MACV_N8)
#define ENCI_MACV_N9 0x1b39 	///../ucode/register.h:8209
#define P_ENCI_MACV_N9 		VCBUS_REG_ADDR(ENCI_MACV_N9)
#define ENCI_MACV_N10 0x1b3a 	///../ucode/register.h:8210
#define P_ENCI_MACV_N10 		VCBUS_REG_ADDR(ENCI_MACV_N10)
#define ENCI_MACV_N11 0x1b3b 	///../ucode/register.h:8211
#define P_ENCI_MACV_N11 		VCBUS_REG_ADDR(ENCI_MACV_N11)
#define ENCI_MACV_N12 0x1b3c 	///../ucode/register.h:8212
#define P_ENCI_MACV_N12 		VCBUS_REG_ADDR(ENCI_MACV_N12)
#define ENCI_MACV_N13 0x1b3d 	///../ucode/register.h:8213
#define P_ENCI_MACV_N13 		VCBUS_REG_ADDR(ENCI_MACV_N13)
#define ENCI_MACV_N14 0x1b3e 	///../ucode/register.h:8214
#define P_ENCI_MACV_N14 		VCBUS_REG_ADDR(ENCI_MACV_N14)
#define ENCI_MACV_N15 0x1b3f 	///../ucode/register.h:8215
#define P_ENCI_MACV_N15 		VCBUS_REG_ADDR(ENCI_MACV_N15)
#define ENCI_MACV_N16 0x1b40 	///../ucode/register.h:8216
#define P_ENCI_MACV_N16 		VCBUS_REG_ADDR(ENCI_MACV_N16)
#define ENCI_MACV_N17 0x1b41 	///../ucode/register.h:8217
#define P_ENCI_MACV_N17 		VCBUS_REG_ADDR(ENCI_MACV_N17)
#define ENCI_MACV_N18 0x1b42 	///../ucode/register.h:8218
#define P_ENCI_MACV_N18 		VCBUS_REG_ADDR(ENCI_MACV_N18)
#define ENCI_MACV_N19 0x1b43 	///../ucode/register.h:8219
#define P_ENCI_MACV_N19 		VCBUS_REG_ADDR(ENCI_MACV_N19)
#define ENCI_MACV_N20 0x1b44 	///../ucode/register.h:8220
#define P_ENCI_MACV_N20 		VCBUS_REG_ADDR(ENCI_MACV_N20)
#define ENCI_MACV_N21 0x1b45 	///../ucode/register.h:8221
#define P_ENCI_MACV_N21 		VCBUS_REG_ADDR(ENCI_MACV_N21)
#define ENCI_MACV_N22 0x1b46 	///../ucode/register.h:8222
#define P_ENCI_MACV_N22 		VCBUS_REG_ADDR(ENCI_MACV_N22)
#define ENCI_DBG_PX_RST 0x1b48 	///../ucode/register.h:8224
#define P_ENCI_DBG_PX_RST 		VCBUS_REG_ADDR(ENCI_DBG_PX_RST)
#define ENCI_DBG_FLDLN_RST 0x1b49 	///../ucode/register.h:8225
#define P_ENCI_DBG_FLDLN_RST 		VCBUS_REG_ADDR(ENCI_DBG_FLDLN_RST)
#define ENCI_DBG_PX_INT 0x1b4a 	///../ucode/register.h:8226
#define P_ENCI_DBG_PX_INT 		VCBUS_REG_ADDR(ENCI_DBG_PX_INT)
#define ENCI_DBG_FLDLN_INT 0x1b4b 	///../ucode/register.h:8227
#define P_ENCI_DBG_FLDLN_INT 		VCBUS_REG_ADDR(ENCI_DBG_FLDLN_INT)
#define ENCI_DBG_MAXPX 0x1b4c 	///../ucode/register.h:8228
#define P_ENCI_DBG_MAXPX 		VCBUS_REG_ADDR(ENCI_DBG_MAXPX)
#define ENCI_DBG_MAXLN 0x1b4d 	///../ucode/register.h:8229
#define P_ENCI_DBG_MAXLN 		VCBUS_REG_ADDR(ENCI_DBG_MAXLN)
#define ENCI_MACV_MAX_AMP 0x1b50 	///../ucode/register.h:8230
#define P_ENCI_MACV_MAX_AMP 		VCBUS_REG_ADDR(ENCI_MACV_MAX_AMP)
#define ENCI_MACV_PULSE_LO 0x1b51 	///../ucode/register.h:8231
#define P_ENCI_MACV_PULSE_LO 		VCBUS_REG_ADDR(ENCI_MACV_PULSE_LO)
#define ENCI_MACV_PULSE_HI 0x1b52 	///../ucode/register.h:8232
#define P_ENCI_MACV_PULSE_HI 		VCBUS_REG_ADDR(ENCI_MACV_PULSE_HI)
#define ENCI_MACV_BKP_MAX 0x1b53 	///../ucode/register.h:8233
#define P_ENCI_MACV_BKP_MAX 		VCBUS_REG_ADDR(ENCI_MACV_BKP_MAX)
#define ENCI_CFILT_CTRL 0x1b54 	///../ucode/register.h:8234
#define P_ENCI_CFILT_CTRL 		VCBUS_REG_ADDR(ENCI_CFILT_CTRL)
#define ENCI_CFILT7 0x1b55 	///../ucode/register.h:8235
#define P_ENCI_CFILT7 		VCBUS_REG_ADDR(ENCI_CFILT7)
#define ENCI_YC_DELAY 0x1b56 	///../ucode/register.h:8236
#define P_ENCI_YC_DELAY 		VCBUS_REG_ADDR(ENCI_YC_DELAY)
#define ENCI_VIDEO_EN 0x1b57 	///../ucode/register.h:8237
#define P_ENCI_VIDEO_EN 		VCBUS_REG_ADDR(ENCI_VIDEO_EN)
#define ENCI_DVI_HSO_BEGIN 0x1c00 	///../ucode/register.h:8251
#define P_ENCI_DVI_HSO_BEGIN 		VCBUS_REG_ADDR(ENCI_DVI_HSO_BEGIN)
#define ENCI_DVI_HSO_END 0x1c01 	///../ucode/register.h:8252
#define P_ENCI_DVI_HSO_END 		VCBUS_REG_ADDR(ENCI_DVI_HSO_END)
#define ENCI_DVI_VSO_BLINE_EVN 0x1c02 	///../ucode/register.h:8253
#define P_ENCI_DVI_VSO_BLINE_EVN 		VCBUS_REG_ADDR(ENCI_DVI_VSO_BLINE_EVN)
#define ENCI_DVI_VSO_BLINE_ODD 0x1c03 	///../ucode/register.h:8254
#define P_ENCI_DVI_VSO_BLINE_ODD 		VCBUS_REG_ADDR(ENCI_DVI_VSO_BLINE_ODD)
#define ENCI_DVI_VSO_ELINE_EVN 0x1c04 	///../ucode/register.h:8255
#define P_ENCI_DVI_VSO_ELINE_EVN 		VCBUS_REG_ADDR(ENCI_DVI_VSO_ELINE_EVN)
#define ENCI_DVI_VSO_ELINE_ODD 0x1c05 	///../ucode/register.h:8256
#define P_ENCI_DVI_VSO_ELINE_ODD 		VCBUS_REG_ADDR(ENCI_DVI_VSO_ELINE_ODD)
#define ENCI_DVI_VSO_BEGIN_EVN 0x1c06 	///../ucode/register.h:8257
#define P_ENCI_DVI_VSO_BEGIN_EVN 		VCBUS_REG_ADDR(ENCI_DVI_VSO_BEGIN_EVN)
#define ENCI_DVI_VSO_BEGIN_ODD 0x1c07 	///../ucode/register.h:8258
#define P_ENCI_DVI_VSO_BEGIN_ODD 		VCBUS_REG_ADDR(ENCI_DVI_VSO_BEGIN_ODD)
#define ENCI_DVI_VSO_END_EVN 0x1c08 	///../ucode/register.h:8259
#define P_ENCI_DVI_VSO_END_EVN 		VCBUS_REG_ADDR(ENCI_DVI_VSO_END_EVN)
#define ENCI_DVI_VSO_END_ODD 0x1c09 	///../ucode/register.h:8260
#define P_ENCI_DVI_VSO_END_ODD 		VCBUS_REG_ADDR(ENCI_DVI_VSO_END_ODD)
#define ENCI_CFILT_CTRL2 0x1c0a 	///../ucode/register.h:8266
#define P_ENCI_CFILT_CTRL2 		VCBUS_REG_ADDR(ENCI_CFILT_CTRL2)
#define ENCI_DACSEL_0 0x1c0b 	///../ucode/register.h:8267
#define P_ENCI_DACSEL_0 		VCBUS_REG_ADDR(ENCI_DACSEL_0)
#define ENCI_DACSEL_1 0x1c0c 	///../ucode/register.h:8268
#define P_ENCI_DACSEL_1 		VCBUS_REG_ADDR(ENCI_DACSEL_1)
#define ENCP_DACSEL_0 0x1c0d 	///../ucode/register.h:8269
#define P_ENCP_DACSEL_0 		VCBUS_REG_ADDR(ENCP_DACSEL_0)
#define ENCP_DACSEL_1 0x1c0e 	///../ucode/register.h:8270
#define P_ENCP_DACSEL_1 		VCBUS_REG_ADDR(ENCP_DACSEL_1)
#define ENCP_MAX_LINE_SWITCH_POINT 0x1c0f 	///../ucode/register.h:8271
#define P_ENCP_MAX_LINE_SWITCH_POINT 		VCBUS_REG_ADDR(ENCP_MAX_LINE_SWITCH_POINT)
#define ENCI_TST_EN 0x1c10 	///../ucode/register.h:8272
#define P_ENCI_TST_EN 		VCBUS_REG_ADDR(ENCI_TST_EN)
#define ENCI_TST_MDSEL 0x1c11 	///../ucode/register.h:8273
#define P_ENCI_TST_MDSEL 		VCBUS_REG_ADDR(ENCI_TST_MDSEL)
#define ENCI_TST_Y 0x1c12 	///../ucode/register.h:8274
#define P_ENCI_TST_Y 		VCBUS_REG_ADDR(ENCI_TST_Y)
#define ENCI_TST_CB 0x1c13 	///../ucode/register.h:8275
#define P_ENCI_TST_CB 		VCBUS_REG_ADDR(ENCI_TST_CB)
#define ENCI_TST_CR 0x1c14 	///../ucode/register.h:8276
#define P_ENCI_TST_CR 		VCBUS_REG_ADDR(ENCI_TST_CR)
#define ENCI_TST_CLRBAR_STRT 0x1c15 	///../ucode/register.h:8277
#define P_ENCI_TST_CLRBAR_STRT 		VCBUS_REG_ADDR(ENCI_TST_CLRBAR_STRT)
#define ENCI_TST_CLRBAR_WIDTH 0x1c16 	///../ucode/register.h:8278
#define P_ENCI_TST_CLRBAR_WIDTH 		VCBUS_REG_ADDR(ENCI_TST_CLRBAR_WIDTH)
#define ENCI_TST_VDCNT_STSET 0x1c17 	///../ucode/register.h:8279
#define P_ENCI_TST_VDCNT_STSET 		VCBUS_REG_ADDR(ENCI_TST_VDCNT_STSET)
#define ENCI_VFIFO2VD_CTL 0x1c18 	///../ucode/register.h:8284
#define P_ENCI_VFIFO2VD_CTL 		VCBUS_REG_ADDR(ENCI_VFIFO2VD_CTL)
#define ENCI_VFIFO2VD_PIXEL_START 0x1c19 	///../ucode/register.h:8286
#define P_ENCI_VFIFO2VD_PIXEL_START 		VCBUS_REG_ADDR(ENCI_VFIFO2VD_PIXEL_START)
#define ENCI_VFIFO2VD_PIXEL_END 0x1c1a 	///../ucode/register.h:8288
#define P_ENCI_VFIFO2VD_PIXEL_END 		VCBUS_REG_ADDR(ENCI_VFIFO2VD_PIXEL_END)
#define ENCI_VFIFO2VD_LINE_TOP_START 0x1c1b 	///../ucode/register.h:8290
#define P_ENCI_VFIFO2VD_LINE_TOP_START 		VCBUS_REG_ADDR(ENCI_VFIFO2VD_LINE_TOP_START)
#define ENCI_VFIFO2VD_LINE_TOP_END 0x1c1c 	///../ucode/register.h:8292
#define P_ENCI_VFIFO2VD_LINE_TOP_END 		VCBUS_REG_ADDR(ENCI_VFIFO2VD_LINE_TOP_END)
#define ENCI_VFIFO2VD_LINE_BOT_START 0x1c1d 	///../ucode/register.h:8294
#define P_ENCI_VFIFO2VD_LINE_BOT_START 		VCBUS_REG_ADDR(ENCI_VFIFO2VD_LINE_BOT_START)
#define ENCI_VFIFO2VD_LINE_BOT_END 0x1c1e 	///../ucode/register.h:8296
#define P_ENCI_VFIFO2VD_LINE_BOT_END 		VCBUS_REG_ADDR(ENCI_VFIFO2VD_LINE_BOT_END)
#define ENCI_VFIFO2VD_CTL2 0x1c1f 	///../ucode/register.h:8297
#define P_ENCI_VFIFO2VD_CTL2 		VCBUS_REG_ADDR(ENCI_VFIFO2VD_CTL2)
#define ENCT_VFIFO2VD_CTL 0x1c20 	///../ucode/register.h:8302
#define P_ENCT_VFIFO2VD_CTL 		VCBUS_REG_ADDR(ENCT_VFIFO2VD_CTL)
#define ENCT_VFIFO2VD_PIXEL_START 0x1c21 	///../ucode/register.h:8304
#define P_ENCT_VFIFO2VD_PIXEL_START 		VCBUS_REG_ADDR(ENCT_VFIFO2VD_PIXEL_START)
#define ENCT_VFIFO2VD_PIXEL_END 0x1c22 	///../ucode/register.h:8306
#define P_ENCT_VFIFO2VD_PIXEL_END 		VCBUS_REG_ADDR(ENCT_VFIFO2VD_PIXEL_END)
#define ENCT_VFIFO2VD_LINE_TOP_START 0x1c23 	///../ucode/register.h:8308
#define P_ENCT_VFIFO2VD_LINE_TOP_START 		VCBUS_REG_ADDR(ENCT_VFIFO2VD_LINE_TOP_START)
#define ENCT_VFIFO2VD_LINE_TOP_END 0x1c24 	///../ucode/register.h:8310
#define P_ENCT_VFIFO2VD_LINE_TOP_END 		VCBUS_REG_ADDR(ENCT_VFIFO2VD_LINE_TOP_END)
#define ENCT_VFIFO2VD_LINE_BOT_START 0x1c25 	///../ucode/register.h:8312
#define P_ENCT_VFIFO2VD_LINE_BOT_START 		VCBUS_REG_ADDR(ENCT_VFIFO2VD_LINE_BOT_START)
#define ENCT_VFIFO2VD_LINE_BOT_END 0x1c26 	///../ucode/register.h:8314
#define P_ENCT_VFIFO2VD_LINE_BOT_END 		VCBUS_REG_ADDR(ENCT_VFIFO2VD_LINE_BOT_END)
#define ENCT_VFIFO2VD_CTL2 0x1c27 	///../ucode/register.h:8315
#define P_ENCT_VFIFO2VD_CTL2 		VCBUS_REG_ADDR(ENCT_VFIFO2VD_CTL2)
#define ENCT_TST_EN 0x1c28 	///../ucode/register.h:8316
#define P_ENCT_TST_EN 		VCBUS_REG_ADDR(ENCT_TST_EN)
#define ENCT_TST_MDSEL 0x1c29 	///../ucode/register.h:8317
#define P_ENCT_TST_MDSEL 		VCBUS_REG_ADDR(ENCT_TST_MDSEL)
#define ENCT_TST_Y 0x1c2a 	///../ucode/register.h:8318
#define P_ENCT_TST_Y 		VCBUS_REG_ADDR(ENCT_TST_Y)
#define ENCT_TST_CB 0x1c2b 	///../ucode/register.h:8319
#define P_ENCT_TST_CB 		VCBUS_REG_ADDR(ENCT_TST_CB)
#define ENCT_TST_CR 0x1c2c 	///../ucode/register.h:8320
#define P_ENCT_TST_CR 		VCBUS_REG_ADDR(ENCT_TST_CR)
#define ENCT_TST_CLRBAR_STRT 0x1c2d 	///../ucode/register.h:8321
#define P_ENCT_TST_CLRBAR_STRT 		VCBUS_REG_ADDR(ENCT_TST_CLRBAR_STRT)
#define ENCT_TST_CLRBAR_WIDTH 0x1c2e 	///../ucode/register.h:8322
#define P_ENCT_TST_CLRBAR_WIDTH 		VCBUS_REG_ADDR(ENCT_TST_CLRBAR_WIDTH)
#define ENCT_TST_VDCNT_STSET 0x1c2f 	///../ucode/register.h:8323
#define P_ENCT_TST_VDCNT_STSET 		VCBUS_REG_ADDR(ENCT_TST_VDCNT_STSET)
#define ENCP_DVI_HSO_BEGIN 0x1c30 	///../ucode/register.h:8325
#define P_ENCP_DVI_HSO_BEGIN 		VCBUS_REG_ADDR(ENCP_DVI_HSO_BEGIN)
#define ENCP_DVI_HSO_END 0x1c31 	///../ucode/register.h:8326
#define P_ENCP_DVI_HSO_END 		VCBUS_REG_ADDR(ENCP_DVI_HSO_END)
#define ENCP_DVI_VSO_BLINE_EVN 0x1c32 	///../ucode/register.h:8327
#define P_ENCP_DVI_VSO_BLINE_EVN 		VCBUS_REG_ADDR(ENCP_DVI_VSO_BLINE_EVN)
#define ENCP_DVI_VSO_BLINE_ODD 0x1c33 	///../ucode/register.h:8328
#define P_ENCP_DVI_VSO_BLINE_ODD 		VCBUS_REG_ADDR(ENCP_DVI_VSO_BLINE_ODD)
#define ENCP_DVI_VSO_ELINE_EVN 0x1c34 	///../ucode/register.h:8329
#define P_ENCP_DVI_VSO_ELINE_EVN 		VCBUS_REG_ADDR(ENCP_DVI_VSO_ELINE_EVN)
#define ENCP_DVI_VSO_ELINE_ODD 0x1c35 	///../ucode/register.h:8330
#define P_ENCP_DVI_VSO_ELINE_ODD 		VCBUS_REG_ADDR(ENCP_DVI_VSO_ELINE_ODD)
#define ENCP_DVI_VSO_BEGIN_EVN 0x1c36 	///../ucode/register.h:8331
#define P_ENCP_DVI_VSO_BEGIN_EVN 		VCBUS_REG_ADDR(ENCP_DVI_VSO_BEGIN_EVN)
#define ENCP_DVI_VSO_BEGIN_ODD 0x1c37 	///../ucode/register.h:8332
#define P_ENCP_DVI_VSO_BEGIN_ODD 		VCBUS_REG_ADDR(ENCP_DVI_VSO_BEGIN_ODD)
#define ENCP_DVI_VSO_END_EVN 0x1c38 	///../ucode/register.h:8333
#define P_ENCP_DVI_VSO_END_EVN 		VCBUS_REG_ADDR(ENCP_DVI_VSO_END_EVN)
#define ENCP_DVI_VSO_END_ODD 0x1c39 	///../ucode/register.h:8334
#define P_ENCP_DVI_VSO_END_ODD 		VCBUS_REG_ADDR(ENCP_DVI_VSO_END_ODD)
#define ENCP_DE_H_BEGIN 0x1c3a 	///../ucode/register.h:8335
#define P_ENCP_DE_H_BEGIN 		VCBUS_REG_ADDR(ENCP_DE_H_BEGIN)
#define ENCP_DE_H_END 0x1c3b 	///../ucode/register.h:8336
#define P_ENCP_DE_H_END 		VCBUS_REG_ADDR(ENCP_DE_H_END)
#define ENCP_DE_V_BEGIN_EVEN 0x1c3c 	///../ucode/register.h:8337
#define P_ENCP_DE_V_BEGIN_EVEN 		VCBUS_REG_ADDR(ENCP_DE_V_BEGIN_EVEN)
#define ENCP_DE_V_END_EVEN 0x1c3d 	///../ucode/register.h:8338
#define P_ENCP_DE_V_END_EVEN 		VCBUS_REG_ADDR(ENCP_DE_V_END_EVEN)
#define ENCP_DE_V_BEGIN_ODD 0x1c3e 	///../ucode/register.h:8339
#define P_ENCP_DE_V_BEGIN_ODD 		VCBUS_REG_ADDR(ENCP_DE_V_BEGIN_ODD)
#define ENCP_DE_V_END_ODD 0x1c3f 	///../ucode/register.h:8340
#define P_ENCP_DE_V_END_ODD 		VCBUS_REG_ADDR(ENCP_DE_V_END_ODD)
#define ENCI_SYNC_LINE_LENGTH 0x1c40 	///../ucode/register.h:8343
#define P_ENCI_SYNC_LINE_LENGTH 		VCBUS_REG_ADDR(ENCI_SYNC_LINE_LENGTH)
#define ENCI_SYNC_PIXEL_EN 0x1c41 	///../ucode/register.h:8346
#define P_ENCI_SYNC_PIXEL_EN 		VCBUS_REG_ADDR(ENCI_SYNC_PIXEL_EN)
#define ENCI_SYNC_TO_LINE_EN 0x1c42 	///../ucode/register.h:8353
#define P_ENCI_SYNC_TO_LINE_EN 		VCBUS_REG_ADDR(ENCI_SYNC_TO_LINE_EN)
#define ENCI_SYNC_TO_PIXEL 0x1c43 	///../ucode/register.h:8355
#define P_ENCI_SYNC_TO_PIXEL 		VCBUS_REG_ADDR(ENCI_SYNC_TO_PIXEL)
#define ENCP_SYNC_LINE_LENGTH 0x1c44 	///../ucode/register.h:8358
#define P_ENCP_SYNC_LINE_LENGTH 		VCBUS_REG_ADDR(ENCP_SYNC_LINE_LENGTH)
#define ENCP_SYNC_PIXEL_EN 0x1c45 	///../ucode/register.h:8361
#define P_ENCP_SYNC_PIXEL_EN 		VCBUS_REG_ADDR(ENCP_SYNC_PIXEL_EN)
#define ENCP_SYNC_TO_LINE_EN 0x1c46 	///../ucode/register.h:8368
#define P_ENCP_SYNC_TO_LINE_EN 		VCBUS_REG_ADDR(ENCP_SYNC_TO_LINE_EN)
#define ENCP_SYNC_TO_PIXEL 0x1c47 	///../ucode/register.h:8370
#define P_ENCP_SYNC_TO_PIXEL 		VCBUS_REG_ADDR(ENCP_SYNC_TO_PIXEL)
#define ENCT_SYNC_LINE_LENGTH 0x1c48 	///../ucode/register.h:8373
#define P_ENCT_SYNC_LINE_LENGTH 		VCBUS_REG_ADDR(ENCT_SYNC_LINE_LENGTH)
#define ENCT_SYNC_PIXEL_EN 0x1c49 	///../ucode/register.h:8376
#define P_ENCT_SYNC_PIXEL_EN 		VCBUS_REG_ADDR(ENCT_SYNC_PIXEL_EN)
#define ENCT_SYNC_TO_LINE_EN 0x1c4a 	///../ucode/register.h:8383
#define P_ENCT_SYNC_TO_LINE_EN 		VCBUS_REG_ADDR(ENCT_SYNC_TO_LINE_EN)
#define ENCT_SYNC_TO_PIXEL 0x1c4b 	///../ucode/register.h:8385
#define P_ENCT_SYNC_TO_PIXEL 		VCBUS_REG_ADDR(ENCT_SYNC_TO_PIXEL)
#define ENCL_SYNC_LINE_LENGTH 0x1c4c 	///../ucode/register.h:8388
#define P_ENCL_SYNC_LINE_LENGTH 		VCBUS_REG_ADDR(ENCL_SYNC_LINE_LENGTH)
#define ENCL_SYNC_PIXEL_EN 0x1c4d 	///../ucode/register.h:8391
#define P_ENCL_SYNC_PIXEL_EN 		VCBUS_REG_ADDR(ENCL_SYNC_PIXEL_EN)
#define ENCL_SYNC_TO_LINE_EN 0x1c4e 	///../ucode/register.h:8398
#define P_ENCL_SYNC_TO_LINE_EN 		VCBUS_REG_ADDR(ENCL_SYNC_TO_LINE_EN)
#define ENCL_SYNC_TO_PIXEL 0x1c4f 	///../ucode/register.h:8400
#define P_ENCL_SYNC_TO_PIXEL 		VCBUS_REG_ADDR(ENCL_SYNC_TO_PIXEL)
#define ENCP_VFIFO2VD_CTL2 0x1c50 	///../ucode/register.h:8409
#define P_ENCP_VFIFO2VD_CTL2 		VCBUS_REG_ADDR(ENCP_VFIFO2VD_CTL2)
#define VENC_DVI_SETTING_MORE 0x1c51 	///../ucode/register.h:8415
#define P_VENC_DVI_SETTING_MORE 		VCBUS_REG_ADDR(VENC_DVI_SETTING_MORE)
#define VENC_VDAC_DAC4_FILT_CTRL0 0x1c54 	///../ucode/register.h:8416
#define P_VENC_VDAC_DAC4_FILT_CTRL0 		VCBUS_REG_ADDR(VENC_VDAC_DAC4_FILT_CTRL0)
#define VENC_VDAC_DAC4_FILT_CTRL1 0x1c55 	///../ucode/register.h:8417
#define P_VENC_VDAC_DAC4_FILT_CTRL1 		VCBUS_REG_ADDR(VENC_VDAC_DAC4_FILT_CTRL1)
#define VENC_VDAC_DAC5_FILT_CTRL0 0x1c56 	///../ucode/register.h:8418
#define P_VENC_VDAC_DAC5_FILT_CTRL0 		VCBUS_REG_ADDR(VENC_VDAC_DAC5_FILT_CTRL0)
#define VENC_VDAC_DAC5_FILT_CTRL1 0x1c57 	///../ucode/register.h:8419
#define P_VENC_VDAC_DAC5_FILT_CTRL1 		VCBUS_REG_ADDR(VENC_VDAC_DAC5_FILT_CTRL1)
#define VENC_VDAC_DAC0_FILT_CTRL0 0x1c58 	///../ucode/register.h:8421
#define P_VENC_VDAC_DAC0_FILT_CTRL0 		VCBUS_REG_ADDR(VENC_VDAC_DAC0_FILT_CTRL0)
#define VENC_VDAC_DAC0_FILT_CTRL1 0x1c59 	///../ucode/register.h:8425
#define P_VENC_VDAC_DAC0_FILT_CTRL1 		VCBUS_REG_ADDR(VENC_VDAC_DAC0_FILT_CTRL1)
#define VENC_VDAC_DAC1_FILT_CTRL0 0x1c5a 	///../ucode/register.h:8427
#define P_VENC_VDAC_DAC1_FILT_CTRL0 		VCBUS_REG_ADDR(VENC_VDAC_DAC1_FILT_CTRL0)
#define VENC_VDAC_DAC1_FILT_CTRL1 0x1c5b 	///../ucode/register.h:8431
#define P_VENC_VDAC_DAC1_FILT_CTRL1 		VCBUS_REG_ADDR(VENC_VDAC_DAC1_FILT_CTRL1)
#define VENC_VDAC_DAC2_FILT_CTRL0 0x1c5c 	///../ucode/register.h:8433
#define P_VENC_VDAC_DAC2_FILT_CTRL0 		VCBUS_REG_ADDR(VENC_VDAC_DAC2_FILT_CTRL0)
#define VENC_VDAC_DAC2_FILT_CTRL1 0x1c5d 	///../ucode/register.h:8437
#define P_VENC_VDAC_DAC2_FILT_CTRL1 		VCBUS_REG_ADDR(VENC_VDAC_DAC2_FILT_CTRL1)
#define VENC_VDAC_DAC3_FILT_CTRL0 0x1c5e 	///../ucode/register.h:8439
#define P_VENC_VDAC_DAC3_FILT_CTRL0 		VCBUS_REG_ADDR(VENC_VDAC_DAC3_FILT_CTRL0)
#define VENC_VDAC_DAC3_FILT_CTRL1 0x1c5f 	///../ucode/register.h:8443
#define P_VENC_VDAC_DAC3_FILT_CTRL1 		VCBUS_REG_ADDR(VENC_VDAC_DAC3_FILT_CTRL1)
#define ENCT_VIDEO_EN 0x1c60 	///../ucode/register.h:8446
#define P_ENCT_VIDEO_EN 		VCBUS_REG_ADDR(ENCT_VIDEO_EN)
#define ENCT_VIDEO_Y_SCL 0x1c61 	///../ucode/register.h:8447
#define P_ENCT_VIDEO_Y_SCL 		VCBUS_REG_ADDR(ENCT_VIDEO_Y_SCL)
#define ENCT_VIDEO_PB_SCL 0x1c62 	///../ucode/register.h:8448
#define P_ENCT_VIDEO_PB_SCL 		VCBUS_REG_ADDR(ENCT_VIDEO_PB_SCL)
#define ENCT_VIDEO_PR_SCL 0x1c63 	///../ucode/register.h:8449
#define P_ENCT_VIDEO_PR_SCL 		VCBUS_REG_ADDR(ENCT_VIDEO_PR_SCL)
#define ENCT_VIDEO_Y_OFFST 0x1c64 	///../ucode/register.h:8450
#define P_ENCT_VIDEO_Y_OFFST 		VCBUS_REG_ADDR(ENCT_VIDEO_Y_OFFST)
#define ENCT_VIDEO_PB_OFFST 0x1c65 	///../ucode/register.h:8451
#define P_ENCT_VIDEO_PB_OFFST 		VCBUS_REG_ADDR(ENCT_VIDEO_PB_OFFST)
#define ENCT_VIDEO_PR_OFFST 0x1c66 	///../ucode/register.h:8452
#define P_ENCT_VIDEO_PR_OFFST 		VCBUS_REG_ADDR(ENCT_VIDEO_PR_OFFST)
#define ENCT_VIDEO_MODE 0x1c67 	///../ucode/register.h:8454
#define P_ENCT_VIDEO_MODE 		VCBUS_REG_ADDR(ENCT_VIDEO_MODE)
#define ENCT_VIDEO_MODE_ADV 0x1c68 	///../ucode/register.h:8455
#define P_ENCT_VIDEO_MODE_ADV 		VCBUS_REG_ADDR(ENCT_VIDEO_MODE_ADV)
#define ENCT_DBG_PX_RST 0x1c69 	///../ucode/register.h:8457
#define P_ENCT_DBG_PX_RST 		VCBUS_REG_ADDR(ENCT_DBG_PX_RST)
#define ENCT_DBG_LN_RST 0x1c6a 	///../ucode/register.h:8458
#define P_ENCT_DBG_LN_RST 		VCBUS_REG_ADDR(ENCT_DBG_LN_RST)
#define ENCT_DBG_PX_INT 0x1c6b 	///../ucode/register.h:8459
#define P_ENCT_DBG_PX_INT 		VCBUS_REG_ADDR(ENCT_DBG_PX_INT)
#define ENCT_DBG_LN_INT 0x1c6c 	///../ucode/register.h:8460
#define P_ENCT_DBG_LN_INT 		VCBUS_REG_ADDR(ENCT_DBG_LN_INT)
#define ENCT_VIDEO_YFP1_HTIME 0x1c6d 	///../ucode/register.h:8462
#define P_ENCT_VIDEO_YFP1_HTIME 		VCBUS_REG_ADDR(ENCT_VIDEO_YFP1_HTIME)
#define ENCT_VIDEO_YFP2_HTIME 0x1c6e 	///../ucode/register.h:8463
#define P_ENCT_VIDEO_YFP2_HTIME 		VCBUS_REG_ADDR(ENCT_VIDEO_YFP2_HTIME)
#define ENCT_VIDEO_YC_DLY 0x1c6f 	///../ucode/register.h:8464
#define P_ENCT_VIDEO_YC_DLY 		VCBUS_REG_ADDR(ENCT_VIDEO_YC_DLY)
#define ENCT_VIDEO_MAX_PXCNT 0x1c70 	///../ucode/register.h:8465
#define P_ENCT_VIDEO_MAX_PXCNT 		VCBUS_REG_ADDR(ENCT_VIDEO_MAX_PXCNT)
#define ENCT_VIDEO_HAVON_END 0x1c71 	///../ucode/register.h:8466
#define P_ENCT_VIDEO_HAVON_END 		VCBUS_REG_ADDR(ENCT_VIDEO_HAVON_END)
#define ENCT_VIDEO_HAVON_BEGIN 0x1c72 	///../ucode/register.h:8467
#define P_ENCT_VIDEO_HAVON_BEGIN 		VCBUS_REG_ADDR(ENCT_VIDEO_HAVON_BEGIN)
#define ENCT_VIDEO_VAVON_ELINE 0x1c73 	///../ucode/register.h:8468
#define P_ENCT_VIDEO_VAVON_ELINE 		VCBUS_REG_ADDR(ENCT_VIDEO_VAVON_ELINE)
#define ENCT_VIDEO_VAVON_BLINE 0x1c74 	///../ucode/register.h:8469
#define P_ENCT_VIDEO_VAVON_BLINE 		VCBUS_REG_ADDR(ENCT_VIDEO_VAVON_BLINE)
#define ENCT_VIDEO_HSO_BEGIN 0x1c75 	///../ucode/register.h:8470
#define P_ENCT_VIDEO_HSO_BEGIN 		VCBUS_REG_ADDR(ENCT_VIDEO_HSO_BEGIN)
#define ENCT_VIDEO_HSO_END 0x1c76 	///../ucode/register.h:8471
#define P_ENCT_VIDEO_HSO_END 		VCBUS_REG_ADDR(ENCT_VIDEO_HSO_END)
#define ENCT_VIDEO_VSO_BEGIN 0x1c77 	///../ucode/register.h:8472
#define P_ENCT_VIDEO_VSO_BEGIN 		VCBUS_REG_ADDR(ENCT_VIDEO_VSO_BEGIN)
#define ENCT_VIDEO_VSO_END 0x1c78 	///../ucode/register.h:8473
#define P_ENCT_VIDEO_VSO_END 		VCBUS_REG_ADDR(ENCT_VIDEO_VSO_END)
#define ENCT_VIDEO_VSO_BLINE 0x1c79 	///../ucode/register.h:8474
#define P_ENCT_VIDEO_VSO_BLINE 		VCBUS_REG_ADDR(ENCT_VIDEO_VSO_BLINE)
#define ENCT_VIDEO_VSO_ELINE 0x1c7a 	///../ucode/register.h:8475
#define P_ENCT_VIDEO_VSO_ELINE 		VCBUS_REG_ADDR(ENCT_VIDEO_VSO_ELINE)
#define ENCT_VIDEO_MAX_LNCNT 0x1c7b 	///../ucode/register.h:8476
#define P_ENCT_VIDEO_MAX_LNCNT 		VCBUS_REG_ADDR(ENCT_VIDEO_MAX_LNCNT)
#define ENCT_VIDEO_BLANKY_VAL 0x1c7c 	///../ucode/register.h:8477
#define P_ENCT_VIDEO_BLANKY_VAL 		VCBUS_REG_ADDR(ENCT_VIDEO_BLANKY_VAL)
#define ENCT_VIDEO_BLANKPB_VAL 0x1c7d 	///../ucode/register.h:8478
#define P_ENCT_VIDEO_BLANKPB_VAL 		VCBUS_REG_ADDR(ENCT_VIDEO_BLANKPB_VAL)
#define ENCT_VIDEO_BLANKPR_VAL 0x1c7e 	///../ucode/register.h:8479
#define P_ENCT_VIDEO_BLANKPR_VAL 		VCBUS_REG_ADDR(ENCT_VIDEO_BLANKPR_VAL)
#define ENCT_VIDEO_HOFFST 0x1c7f 	///../ucode/register.h:8480
#define P_ENCT_VIDEO_HOFFST 		VCBUS_REG_ADDR(ENCT_VIDEO_HOFFST)
#define ENCT_VIDEO_VOFFST 0x1c80 	///../ucode/register.h:8481
#define P_ENCT_VIDEO_VOFFST 		VCBUS_REG_ADDR(ENCT_VIDEO_VOFFST)
#define ENCT_VIDEO_RGB_CTRL 0x1c81 	///../ucode/register.h:8482
#define P_ENCT_VIDEO_RGB_CTRL 		VCBUS_REG_ADDR(ENCT_VIDEO_RGB_CTRL)
#define ENCT_VIDEO_FILT_CTRL 0x1c82 	///../ucode/register.h:8483
#define P_ENCT_VIDEO_FILT_CTRL 		VCBUS_REG_ADDR(ENCT_VIDEO_FILT_CTRL)
#define ENCT_VIDEO_OFLD_VPEQ_OFST 0x1c83 	///../ucode/register.h:8484
#define P_ENCT_VIDEO_OFLD_VPEQ_OFST 		VCBUS_REG_ADDR(ENCT_VIDEO_OFLD_VPEQ_OFST)
#define ENCT_VIDEO_OFLD_VOAV_OFST 0x1c84 	///../ucode/register.h:8485
#define P_ENCT_VIDEO_OFLD_VOAV_OFST 		VCBUS_REG_ADDR(ENCT_VIDEO_OFLD_VOAV_OFST)
#define ENCT_VIDEO_MATRIX_CB 0x1c85 	///../ucode/register.h:8486
#define P_ENCT_VIDEO_MATRIX_CB 		VCBUS_REG_ADDR(ENCT_VIDEO_MATRIX_CB)
#define ENCT_VIDEO_MATRIX_CR 0x1c86 	///../ucode/register.h:8487
#define P_ENCT_VIDEO_MATRIX_CR 		VCBUS_REG_ADDR(ENCT_VIDEO_MATRIX_CR)
#define ENCT_VIDEO_RGBIN_CTRL 0x1c87 	///../ucode/register.h:8488
#define P_ENCT_VIDEO_RGBIN_CTRL 		VCBUS_REG_ADDR(ENCT_VIDEO_RGBIN_CTRL)
#define ENCT_MAX_LINE_SWITCH_POINT 0x1c88 	///../ucode/register.h:8489
#define P_ENCT_MAX_LINE_SWITCH_POINT 		VCBUS_REG_ADDR(ENCT_MAX_LINE_SWITCH_POINT)
#define ENCT_DACSEL_0 0x1c89 	///../ucode/register.h:8490
#define P_ENCT_DACSEL_0 		VCBUS_REG_ADDR(ENCT_DACSEL_0)
#define ENCT_DACSEL_1 0x1c8a 	///../ucode/register.h:8491
#define P_ENCT_DACSEL_1 		VCBUS_REG_ADDR(ENCT_DACSEL_1)
#define ENCL_VFIFO2VD_CTL 0x1c90 	///../ucode/register.h:8499
#define P_ENCL_VFIFO2VD_CTL 		VCBUS_REG_ADDR(ENCL_VFIFO2VD_CTL)
#define ENCL_VFIFO2VD_PIXEL_START 0x1c91 	///../ucode/register.h:8501
#define P_ENCL_VFIFO2VD_PIXEL_START 		VCBUS_REG_ADDR(ENCL_VFIFO2VD_PIXEL_START)
#define ENCL_VFIFO2VD_PIXEL_END 0x1c92 	///../ucode/register.h:8503
#define P_ENCL_VFIFO2VD_PIXEL_END 		VCBUS_REG_ADDR(ENCL_VFIFO2VD_PIXEL_END)
#define ENCL_VFIFO2VD_LINE_TOP_START 0x1c93 	///../ucode/register.h:8505
#define P_ENCL_VFIFO2VD_LINE_TOP_START 		VCBUS_REG_ADDR(ENCL_VFIFO2VD_LINE_TOP_START)
#define ENCL_VFIFO2VD_LINE_TOP_END 0x1c94 	///../ucode/register.h:8507
#define P_ENCL_VFIFO2VD_LINE_TOP_END 		VCBUS_REG_ADDR(ENCL_VFIFO2VD_LINE_TOP_END)
#define ENCL_VFIFO2VD_LINE_BOT_START 0x1c95 	///../ucode/register.h:8509
#define P_ENCL_VFIFO2VD_LINE_BOT_START 		VCBUS_REG_ADDR(ENCL_VFIFO2VD_LINE_BOT_START)
#define ENCL_VFIFO2VD_LINE_BOT_END 0x1c96 	///../ucode/register.h:8511
#define P_ENCL_VFIFO2VD_LINE_BOT_END 		VCBUS_REG_ADDR(ENCL_VFIFO2VD_LINE_BOT_END)
#define ENCL_VFIFO2VD_CTL2 0x1c97 	///../ucode/register.h:8512
#define P_ENCL_VFIFO2VD_CTL2 		VCBUS_REG_ADDR(ENCL_VFIFO2VD_CTL2)
#define ENCL_TST_EN 0x1c98 	///../ucode/register.h:8513
#define P_ENCL_TST_EN 		VCBUS_REG_ADDR(ENCL_TST_EN)
#define ENCL_TST_MDSEL 0x1c99 	///../ucode/register.h:8514
#define P_ENCL_TST_MDSEL 		VCBUS_REG_ADDR(ENCL_TST_MDSEL)
#define ENCL_TST_Y 0x1c9a 	///../ucode/register.h:8515
#define P_ENCL_TST_Y 		VCBUS_REG_ADDR(ENCL_TST_Y)
#define ENCL_TST_CB 0x1c9b 	///../ucode/register.h:8516
#define P_ENCL_TST_CB 		VCBUS_REG_ADDR(ENCL_TST_CB)
#define ENCL_TST_CR 0x1c9c 	///../ucode/register.h:8517
#define P_ENCL_TST_CR 		VCBUS_REG_ADDR(ENCL_TST_CR)
#define ENCL_TST_CLRBAR_STRT 0x1c9d 	///../ucode/register.h:8518
#define P_ENCL_TST_CLRBAR_STRT 		VCBUS_REG_ADDR(ENCL_TST_CLRBAR_STRT)
#define ENCL_TST_CLRBAR_WIDTH 0x1c9e 	///../ucode/register.h:8519
#define P_ENCL_TST_CLRBAR_WIDTH 		VCBUS_REG_ADDR(ENCL_TST_CLRBAR_WIDTH)
#define ENCL_TST_VDCNT_STSET 0x1c9f 	///../ucode/register.h:8520
#define P_ENCL_TST_VDCNT_STSET 		VCBUS_REG_ADDR(ENCL_TST_VDCNT_STSET)
#define ENCL_VIDEO_EN 0x1ca0 	///../ucode/register.h:8523
#define P_ENCL_VIDEO_EN 		VCBUS_REG_ADDR(ENCL_VIDEO_EN)
#define ENCL_VIDEO_Y_SCL 0x1ca1 	///../ucode/register.h:8524
#define P_ENCL_VIDEO_Y_SCL 		VCBUS_REG_ADDR(ENCL_VIDEO_Y_SCL)
#define ENCL_VIDEO_PB_SCL 0x1ca2 	///../ucode/register.h:8525
#define P_ENCL_VIDEO_PB_SCL 		VCBUS_REG_ADDR(ENCL_VIDEO_PB_SCL)
#define ENCL_VIDEO_PR_SCL 0x1ca3 	///../ucode/register.h:8526
#define P_ENCL_VIDEO_PR_SCL 		VCBUS_REG_ADDR(ENCL_VIDEO_PR_SCL)
#define ENCL_VIDEO_Y_OFFST 0x1ca4 	///../ucode/register.h:8527
#define P_ENCL_VIDEO_Y_OFFST 		VCBUS_REG_ADDR(ENCL_VIDEO_Y_OFFST)
#define ENCL_VIDEO_PB_OFFST 0x1ca5 	///../ucode/register.h:8528
#define P_ENCL_VIDEO_PB_OFFST 		VCBUS_REG_ADDR(ENCL_VIDEO_PB_OFFST)
#define ENCL_VIDEO_PR_OFFST 0x1ca6 	///../ucode/register.h:8529
#define P_ENCL_VIDEO_PR_OFFST 		VCBUS_REG_ADDR(ENCL_VIDEO_PR_OFFST)
#define ENCL_VIDEO_MODE 0x1ca7 	///../ucode/register.h:8531
#define P_ENCL_VIDEO_MODE 		VCBUS_REG_ADDR(ENCL_VIDEO_MODE)
#define ENCL_VIDEO_MODE_ADV 0x1ca8 	///../ucode/register.h:8532
#define P_ENCL_VIDEO_MODE_ADV 		VCBUS_REG_ADDR(ENCL_VIDEO_MODE_ADV)
#define ENCL_DBG_PX_RST 0x1ca9 	///../ucode/register.h:8534
#define P_ENCL_DBG_PX_RST 		VCBUS_REG_ADDR(ENCL_DBG_PX_RST)
#define ENCL_DBG_LN_RST 0x1caa 	///../ucode/register.h:8535
#define P_ENCL_DBG_LN_RST 		VCBUS_REG_ADDR(ENCL_DBG_LN_RST)
#define ENCL_DBG_PX_INT 0x1cab 	///../ucode/register.h:8536
#define P_ENCL_DBG_PX_INT 		VCBUS_REG_ADDR(ENCL_DBG_PX_INT)
#define ENCL_DBG_LN_INT 0x1cac 	///../ucode/register.h:8537
#define P_ENCL_DBG_LN_INT 		VCBUS_REG_ADDR(ENCL_DBG_LN_INT)
#define ENCL_VIDEO_YFP1_HTIME 0x1cad 	///../ucode/register.h:8539
#define P_ENCL_VIDEO_YFP1_HTIME 		VCBUS_REG_ADDR(ENCL_VIDEO_YFP1_HTIME)
#define ENCL_VIDEO_YFP2_HTIME 0x1cae 	///../ucode/register.h:8540
#define P_ENCL_VIDEO_YFP2_HTIME 		VCBUS_REG_ADDR(ENCL_VIDEO_YFP2_HTIME)
#define ENCL_VIDEO_YC_DLY 0x1caf 	///../ucode/register.h:8541
#define P_ENCL_VIDEO_YC_DLY 		VCBUS_REG_ADDR(ENCL_VIDEO_YC_DLY)
#define ENCL_VIDEO_MAX_PXCNT 0x1cb0 	///../ucode/register.h:8542
#define P_ENCL_VIDEO_MAX_PXCNT 		VCBUS_REG_ADDR(ENCL_VIDEO_MAX_PXCNT)
#define ENCL_VIDEO_HAVON_END 0x1cb1 	///../ucode/register.h:8543
#define P_ENCL_VIDEO_HAVON_END 		VCBUS_REG_ADDR(ENCL_VIDEO_HAVON_END)
#define ENCL_VIDEO_HAVON_BEGIN 0x1cb2 	///../ucode/register.h:8544
#define P_ENCL_VIDEO_HAVON_BEGIN 		VCBUS_REG_ADDR(ENCL_VIDEO_HAVON_BEGIN)
#define ENCL_VIDEO_VAVON_ELINE 0x1cb3 	///../ucode/register.h:8545
#define P_ENCL_VIDEO_VAVON_ELINE 		VCBUS_REG_ADDR(ENCL_VIDEO_VAVON_ELINE)
#define ENCL_VIDEO_VAVON_BLINE 0x1cb4 	///../ucode/register.h:8546
#define P_ENCL_VIDEO_VAVON_BLINE 		VCBUS_REG_ADDR(ENCL_VIDEO_VAVON_BLINE)
#define ENCL_VIDEO_HSO_BEGIN 0x1cb5 	///../ucode/register.h:8547
#define P_ENCL_VIDEO_HSO_BEGIN 		VCBUS_REG_ADDR(ENCL_VIDEO_HSO_BEGIN)
#define ENCL_VIDEO_HSO_END 0x1cb6 	///../ucode/register.h:8548
#define P_ENCL_VIDEO_HSO_END 		VCBUS_REG_ADDR(ENCL_VIDEO_HSO_END)
#define ENCL_VIDEO_VSO_BEGIN 0x1cb7 	///../ucode/register.h:8549
#define P_ENCL_VIDEO_VSO_BEGIN 		VCBUS_REG_ADDR(ENCL_VIDEO_VSO_BEGIN)
#define ENCL_VIDEO_VSO_END 0x1cb8 	///../ucode/register.h:8550
#define P_ENCL_VIDEO_VSO_END 		VCBUS_REG_ADDR(ENCL_VIDEO_VSO_END)
#define ENCL_VIDEO_VSO_BLINE 0x1cb9 	///../ucode/register.h:8551
#define P_ENCL_VIDEO_VSO_BLINE 		VCBUS_REG_ADDR(ENCL_VIDEO_VSO_BLINE)
#define ENCL_VIDEO_VSO_ELINE 0x1cba 	///../ucode/register.h:8552
#define P_ENCL_VIDEO_VSO_ELINE 		VCBUS_REG_ADDR(ENCL_VIDEO_VSO_ELINE)
#define ENCL_VIDEO_MAX_LNCNT 0x1cbb 	///../ucode/register.h:8553
#define P_ENCL_VIDEO_MAX_LNCNT 		VCBUS_REG_ADDR(ENCL_VIDEO_MAX_LNCNT)
#define ENCL_VIDEO_BLANKY_VAL 0x1cbc 	///../ucode/register.h:8554
#define P_ENCL_VIDEO_BLANKY_VAL 		VCBUS_REG_ADDR(ENCL_VIDEO_BLANKY_VAL)
#define ENCL_VIDEO_BLANKPB_VAL 0x1cbd 	///../ucode/register.h:8555
#define P_ENCL_VIDEO_BLANKPB_VAL 		VCBUS_REG_ADDR(ENCL_VIDEO_BLANKPB_VAL)
#define ENCL_VIDEO_BLANKPR_VAL 0x1cbe 	///../ucode/register.h:8556
#define P_ENCL_VIDEO_BLANKPR_VAL 		VCBUS_REG_ADDR(ENCL_VIDEO_BLANKPR_VAL)
#define ENCL_VIDEO_HOFFST 0x1cbf 	///../ucode/register.h:8557
#define P_ENCL_VIDEO_HOFFST 		VCBUS_REG_ADDR(ENCL_VIDEO_HOFFST)
#define ENCL_VIDEO_VOFFST 0x1cc0 	///../ucode/register.h:8558
#define P_ENCL_VIDEO_VOFFST 		VCBUS_REG_ADDR(ENCL_VIDEO_VOFFST)
#define ENCL_VIDEO_RGB_CTRL 0x1cc1 	///../ucode/register.h:8559
#define P_ENCL_VIDEO_RGB_CTRL 		VCBUS_REG_ADDR(ENCL_VIDEO_RGB_CTRL)
#define ENCL_VIDEO_FILT_CTRL 0x1cc2 	///../ucode/register.h:8560
#define P_ENCL_VIDEO_FILT_CTRL 		VCBUS_REG_ADDR(ENCL_VIDEO_FILT_CTRL)
#define ENCL_VIDEO_OFLD_VPEQ_OFST 0x1cc3 	///../ucode/register.h:8561
#define P_ENCL_VIDEO_OFLD_VPEQ_OFST 		VCBUS_REG_ADDR(ENCL_VIDEO_OFLD_VPEQ_OFST)
#define ENCL_VIDEO_OFLD_VOAV_OFST 0x1cc4 	///../ucode/register.h:8562
#define P_ENCL_VIDEO_OFLD_VOAV_OFST 		VCBUS_REG_ADDR(ENCL_VIDEO_OFLD_VOAV_OFST)
#define ENCL_VIDEO_MATRIX_CB 0x1cc5 	///../ucode/register.h:8563
#define P_ENCL_VIDEO_MATRIX_CB 		VCBUS_REG_ADDR(ENCL_VIDEO_MATRIX_CB)
#define ENCL_VIDEO_MATRIX_CR 0x1cc6 	///../ucode/register.h:8564
#define P_ENCL_VIDEO_MATRIX_CR 		VCBUS_REG_ADDR(ENCL_VIDEO_MATRIX_CR)
#define ENCL_VIDEO_RGBIN_CTRL 0x1cc7 	///../ucode/register.h:8565
#define P_ENCL_VIDEO_RGBIN_CTRL 		VCBUS_REG_ADDR(ENCL_VIDEO_RGBIN_CTRL)
#define ENCL_MAX_LINE_SWITCH_POINT 0x1cc8 	///../ucode/register.h:8566
#define P_ENCL_MAX_LINE_SWITCH_POINT 		VCBUS_REG_ADDR(ENCL_MAX_LINE_SWITCH_POINT)
#define ENCL_DACSEL_0 0x1cc9 	///../ucode/register.h:8567
#define P_ENCL_DACSEL_0 		VCBUS_REG_ADDR(ENCL_DACSEL_0)
#define ENCL_DACSEL_1 0x1cca 	///../ucode/register.h:8568
#define P_ENCL_DACSEL_1 		VCBUS_REG_ADDR(ENCL_DACSEL_1)
#define RDMA_AHB_START_ADDR_MAN 0x1cf0 	///../ucode/register.h:8572
#define P_RDMA_AHB_START_ADDR_MAN 		VCBUS_REG_ADDR(RDMA_AHB_START_ADDR_MAN)
#define RDMA_AHB_END_ADDR_MAN 0x1cf1 	///../ucode/register.h:8574
#define P_RDMA_AHB_END_ADDR_MAN 		VCBUS_REG_ADDR(RDMA_AHB_END_ADDR_MAN)
#define RDMA_AHB_START_ADDR_1 0x1cf2 	///../ucode/register.h:8576
#define P_RDMA_AHB_START_ADDR_1 		VCBUS_REG_ADDR(RDMA_AHB_START_ADDR_1)
#define RDMA_AHB_END_ADDR_1 0x1cf3 	///../ucode/register.h:8578
#define P_RDMA_AHB_END_ADDR_1 		VCBUS_REG_ADDR(RDMA_AHB_END_ADDR_1)
#define RDMA_AHB_START_ADDR_2 0x1cf4 	///../ucode/register.h:8580
#define P_RDMA_AHB_START_ADDR_2 		VCBUS_REG_ADDR(RDMA_AHB_START_ADDR_2)
#define RDMA_AHB_END_ADDR_2 0x1cf5 	///../ucode/register.h:8582
#define P_RDMA_AHB_END_ADDR_2 		VCBUS_REG_ADDR(RDMA_AHB_END_ADDR_2)
#define RDMA_AHB_START_ADDR_3 0x1cf6 	///../ucode/register.h:8584
#define P_RDMA_AHB_START_ADDR_3 		VCBUS_REG_ADDR(RDMA_AHB_START_ADDR_3)
#define RDMA_AHB_END_ADDR_3 0x1cf7 	///../ucode/register.h:8586
#define P_RDMA_AHB_END_ADDR_3 		VCBUS_REG_ADDR(RDMA_AHB_END_ADDR_3)
#define RDMA_ACCESS_AUTO 0x1cf8 	///../ucode/register.h:8599
#define P_RDMA_ACCESS_AUTO 		VCBUS_REG_ADDR(RDMA_ACCESS_AUTO)
#define RDMA_ACCESS_MAN 0x1cf9 	///../ucode/register.h:8605
#define P_RDMA_ACCESS_MAN 		VCBUS_REG_ADDR(RDMA_ACCESS_MAN)
#define RDMA_CTRL 0x1cfa 	///../ucode/register.h:8623
#define P_RDMA_CTRL 		VCBUS_REG_ADDR(RDMA_CTRL)
#define RDMA_STATUS 0x1cfb 	///../ucode/register.h:8633
#define P_RDMA_STATUS 		VCBUS_REG_ADDR(RDMA_STATUS)
#define L_GAMMA_CNTL_PORT 0x1400 	///../ucode/register.h:8646
#define P_L_GAMMA_CNTL_PORT 		VCBUS_REG_ADDR(L_GAMMA_CNTL_PORT)
#define L_GAMMA_DATA_PORT 0x1401 	///../ucode/register.h:8647
#define P_L_GAMMA_DATA_PORT 		VCBUS_REG_ADDR(L_GAMMA_DATA_PORT)
#define L_GAMMA_ADDR_PORT 0x1402 	///../ucode/register.h:8648
#define P_L_GAMMA_ADDR_PORT 		VCBUS_REG_ADDR(L_GAMMA_ADDR_PORT)
#define L_GAMMA_VCOM_HSWITCH_ADDR 0x1403 	///../ucode/register.h:8649
#define P_L_GAMMA_VCOM_HSWITCH_ADDR 		VCBUS_REG_ADDR(L_GAMMA_VCOM_HSWITCH_ADDR)
#define L_RGB_BASE_ADDR 0x1405 	///../ucode/register.h:8650
#define P_L_RGB_BASE_ADDR 		VCBUS_REG_ADDR(L_RGB_BASE_ADDR)
#define L_RGB_COEFF_ADDR 0x1406 	///../ucode/register.h:8651
#define P_L_RGB_COEFF_ADDR 		VCBUS_REG_ADDR(L_RGB_COEFF_ADDR)
#define L_POL_CNTL_ADDR 0x1407 	///../ucode/register.h:8652
#define P_L_POL_CNTL_ADDR 		VCBUS_REG_ADDR(L_POL_CNTL_ADDR)
#define L_DITH_CNTL_ADDR 0x1408 	///../ucode/register.h:8653
#define P_L_DITH_CNTL_ADDR 		VCBUS_REG_ADDR(L_DITH_CNTL_ADDR)
#define L_GAMMA_PROBE_CTRL 0x1409 	///../ucode/register.h:8654
#define P_L_GAMMA_PROBE_CTRL 		VCBUS_REG_ADDR(L_GAMMA_PROBE_CTRL)
#define L_GAMMA_PROBE_COLOR_L 0x140a 	///../ucode/register.h:8656
#define P_L_GAMMA_PROBE_COLOR_L 		VCBUS_REG_ADDR(L_GAMMA_PROBE_COLOR_L)
#define L_GAMMA_PROBE_COLOR_H 0x140b 	///../ucode/register.h:8657
#define P_L_GAMMA_PROBE_COLOR_H 		VCBUS_REG_ADDR(L_GAMMA_PROBE_COLOR_H)
#define L_GAMMA_PROBE_HL_COLOR 0x140c 	///../ucode/register.h:8658
#define P_L_GAMMA_PROBE_HL_COLOR 		VCBUS_REG_ADDR(L_GAMMA_PROBE_HL_COLOR)
#define L_GAMMA_PROBE_POS_X 0x140d 	///../ucode/register.h:8659
#define P_L_GAMMA_PROBE_POS_X 		VCBUS_REG_ADDR(L_GAMMA_PROBE_POS_X)
#define L_GAMMA_PROBE_POS_Y 0x140e 	///../ucode/register.h:8660
#define P_L_GAMMA_PROBE_POS_Y 		VCBUS_REG_ADDR(L_GAMMA_PROBE_POS_Y)
#define L_STH1_HS_ADDR 0x1410 	///../ucode/register.h:8661
#define P_L_STH1_HS_ADDR 		VCBUS_REG_ADDR(L_STH1_HS_ADDR)
#define L_STH1_HE_ADDR 0x1411 	///../ucode/register.h:8662
#define P_L_STH1_HE_ADDR 		VCBUS_REG_ADDR(L_STH1_HE_ADDR)
#define L_STH1_VS_ADDR 0x1412 	///../ucode/register.h:8663
#define P_L_STH1_VS_ADDR 		VCBUS_REG_ADDR(L_STH1_VS_ADDR)
#define L_STH1_VE_ADDR 0x1413 	///../ucode/register.h:8664
#define P_L_STH1_VE_ADDR 		VCBUS_REG_ADDR(L_STH1_VE_ADDR)
#define L_STH2_HS_ADDR 0x1414 	///../ucode/register.h:8665
#define P_L_STH2_HS_ADDR 		VCBUS_REG_ADDR(L_STH2_HS_ADDR)
#define L_STH2_HE_ADDR 0x1415 	///../ucode/register.h:8666
#define P_L_STH2_HE_ADDR 		VCBUS_REG_ADDR(L_STH2_HE_ADDR)
#define L_STH2_VS_ADDR 0x1416 	///../ucode/register.h:8667
#define P_L_STH2_VS_ADDR 		VCBUS_REG_ADDR(L_STH2_VS_ADDR)
#define L_STH2_VE_ADDR 0x1417 	///../ucode/register.h:8668
#define P_L_STH2_VE_ADDR 		VCBUS_REG_ADDR(L_STH2_VE_ADDR)
#define L_OEH_HS_ADDR 0x1418 	///../ucode/register.h:8669
#define P_L_OEH_HS_ADDR 		VCBUS_REG_ADDR(L_OEH_HS_ADDR)
#define L_OEH_HE_ADDR 0x1419 	///../ucode/register.h:8670
#define P_L_OEH_HE_ADDR 		VCBUS_REG_ADDR(L_OEH_HE_ADDR)
#define L_OEH_VS_ADDR 0x141a 	///../ucode/register.h:8671
#define P_L_OEH_VS_ADDR 		VCBUS_REG_ADDR(L_OEH_VS_ADDR)
#define L_OEH_VE_ADDR 0x141b 	///../ucode/register.h:8672
#define P_L_OEH_VE_ADDR 		VCBUS_REG_ADDR(L_OEH_VE_ADDR)
#define L_VCOM_HSWITCH_ADDR 0x141c 	///../ucode/register.h:8673
#define P_L_VCOM_HSWITCH_ADDR 		VCBUS_REG_ADDR(L_VCOM_HSWITCH_ADDR)
#define L_VCOM_VS_ADDR 0x141d 	///../ucode/register.h:8674
#define P_L_VCOM_VS_ADDR 		VCBUS_REG_ADDR(L_VCOM_VS_ADDR)
#define L_VCOM_VE_ADDR 0x141e 	///../ucode/register.h:8675
#define P_L_VCOM_VE_ADDR 		VCBUS_REG_ADDR(L_VCOM_VE_ADDR)
#define L_CPV1_HS_ADDR 0x141f 	///../ucode/register.h:8676
#define P_L_CPV1_HS_ADDR 		VCBUS_REG_ADDR(L_CPV1_HS_ADDR)
#define L_CPV1_HE_ADDR 0x1420 	///../ucode/register.h:8677
#define P_L_CPV1_HE_ADDR 		VCBUS_REG_ADDR(L_CPV1_HE_ADDR)
#define L_CPV1_VS_ADDR 0x1421 	///../ucode/register.h:8678
#define P_L_CPV1_VS_ADDR 		VCBUS_REG_ADDR(L_CPV1_VS_ADDR)
#define L_CPV1_VE_ADDR 0x1422 	///../ucode/register.h:8679
#define P_L_CPV1_VE_ADDR 		VCBUS_REG_ADDR(L_CPV1_VE_ADDR)
#define L_CPV2_HS_ADDR 0x1423 	///../ucode/register.h:8680
#define P_L_CPV2_HS_ADDR 		VCBUS_REG_ADDR(L_CPV2_HS_ADDR)
#define L_CPV2_HE_ADDR 0x1424 	///../ucode/register.h:8681
#define P_L_CPV2_HE_ADDR 		VCBUS_REG_ADDR(L_CPV2_HE_ADDR)
#define L_CPV2_VS_ADDR 0x1425 	///../ucode/register.h:8682
#define P_L_CPV2_VS_ADDR 		VCBUS_REG_ADDR(L_CPV2_VS_ADDR)
#define L_CPV2_VE_ADDR 0x1426 	///../ucode/register.h:8683
#define P_L_CPV2_VE_ADDR 		VCBUS_REG_ADDR(L_CPV2_VE_ADDR)
#define L_STV1_HS_ADDR 0x1427 	///../ucode/register.h:8684
#define P_L_STV1_HS_ADDR 		VCBUS_REG_ADDR(L_STV1_HS_ADDR)
#define L_STV1_HE_ADDR 0x1428 	///../ucode/register.h:8685
#define P_L_STV1_HE_ADDR 		VCBUS_REG_ADDR(L_STV1_HE_ADDR)
#define L_STV1_VS_ADDR 0x1429 	///../ucode/register.h:8686
#define P_L_STV1_VS_ADDR 		VCBUS_REG_ADDR(L_STV1_VS_ADDR)
#define L_STV1_VE_ADDR 0x142a 	///../ucode/register.h:8687
#define P_L_STV1_VE_ADDR 		VCBUS_REG_ADDR(L_STV1_VE_ADDR)
#define L_STV2_HS_ADDR 0x142b 	///../ucode/register.h:8688
#define P_L_STV2_HS_ADDR 		VCBUS_REG_ADDR(L_STV2_HS_ADDR)
#define L_STV2_HE_ADDR 0x142c 	///../ucode/register.h:8689
#define P_L_STV2_HE_ADDR 		VCBUS_REG_ADDR(L_STV2_HE_ADDR)
#define L_STV2_VS_ADDR 0x142d 	///../ucode/register.h:8690
#define P_L_STV2_VS_ADDR 		VCBUS_REG_ADDR(L_STV2_VS_ADDR)
#define L_STV2_VE_ADDR 0x142e 	///../ucode/register.h:8691
#define P_L_STV2_VE_ADDR 		VCBUS_REG_ADDR(L_STV2_VE_ADDR)
#define L_OEV1_HS_ADDR 0x142f 	///../ucode/register.h:8692
#define P_L_OEV1_HS_ADDR 		VCBUS_REG_ADDR(L_OEV1_HS_ADDR)
#define L_OEV1_HE_ADDR 0x1430 	///../ucode/register.h:8693
#define P_L_OEV1_HE_ADDR 		VCBUS_REG_ADDR(L_OEV1_HE_ADDR)
#define L_OEV1_VS_ADDR 0x1431 	///../ucode/register.h:8694
#define P_L_OEV1_VS_ADDR 		VCBUS_REG_ADDR(L_OEV1_VS_ADDR)
#define L_OEV1_VE_ADDR 0x1432 	///../ucode/register.h:8695
#define P_L_OEV1_VE_ADDR 		VCBUS_REG_ADDR(L_OEV1_VE_ADDR)
#define L_OEV2_HS_ADDR 0x1433 	///../ucode/register.h:8696
#define P_L_OEV2_HS_ADDR 		VCBUS_REG_ADDR(L_OEV2_HS_ADDR)
#define L_OEV2_HE_ADDR 0x1434 	///../ucode/register.h:8697
#define P_L_OEV2_HE_ADDR 		VCBUS_REG_ADDR(L_OEV2_HE_ADDR)
#define L_OEV2_VS_ADDR 0x1435 	///../ucode/register.h:8698
#define P_L_OEV2_VS_ADDR 		VCBUS_REG_ADDR(L_OEV2_VS_ADDR)
#define L_OEV2_VE_ADDR 0x1436 	///../ucode/register.h:8699
#define P_L_OEV2_VE_ADDR 		VCBUS_REG_ADDR(L_OEV2_VE_ADDR)
#define L_OEV3_HS_ADDR 0x1437 	///../ucode/register.h:8700
#define P_L_OEV3_HS_ADDR 		VCBUS_REG_ADDR(L_OEV3_HS_ADDR)
#define L_OEV3_HE_ADDR 0x1438 	///../ucode/register.h:8701
#define P_L_OEV3_HE_ADDR 		VCBUS_REG_ADDR(L_OEV3_HE_ADDR)
#define L_OEV3_VS_ADDR 0x1439 	///../ucode/register.h:8702
#define P_L_OEV3_VS_ADDR 		VCBUS_REG_ADDR(L_OEV3_VS_ADDR)
#define L_OEV3_VE_ADDR 0x143a 	///../ucode/register.h:8703
#define P_L_OEV3_VE_ADDR 		VCBUS_REG_ADDR(L_OEV3_VE_ADDR)
#define L_LCD_PWR_ADDR 0x143b 	///../ucode/register.h:8704
#define P_L_LCD_PWR_ADDR 		VCBUS_REG_ADDR(L_LCD_PWR_ADDR)
#define L_LCD_PWM0_LO_ADDR 0x143c 	///../ucode/register.h:8705
#define P_L_LCD_PWM0_LO_ADDR 		VCBUS_REG_ADDR(L_LCD_PWM0_LO_ADDR)
#define L_LCD_PWM0_HI_ADDR 0x143d 	///../ucode/register.h:8706
#define P_L_LCD_PWM0_HI_ADDR 		VCBUS_REG_ADDR(L_LCD_PWM0_HI_ADDR)
#define L_LCD_PWM1_LO_ADDR 0x143e 	///../ucode/register.h:8707
#define P_L_LCD_PWM1_LO_ADDR 		VCBUS_REG_ADDR(L_LCD_PWM1_LO_ADDR)
#define L_LCD_PWM1_HI_ADDR 0x143f 	///../ucode/register.h:8708
#define P_L_LCD_PWM1_HI_ADDR 		VCBUS_REG_ADDR(L_LCD_PWM1_HI_ADDR)
#define L_INV_CNT_ADDR 0x1440 	///../ucode/register.h:8709
#define P_L_INV_CNT_ADDR 		VCBUS_REG_ADDR(L_INV_CNT_ADDR)
#define L_TCON_MISC_SEL_ADDR 0x1441 	///../ucode/register.h:8710
#define P_L_TCON_MISC_SEL_ADDR 		VCBUS_REG_ADDR(L_TCON_MISC_SEL_ADDR)
#define L_DUAL_PORT_CNTL_ADDR 0x1442 	///../ucode/register.h:8711
#define P_L_DUAL_PORT_CNTL_ADDR 		VCBUS_REG_ADDR(L_DUAL_PORT_CNTL_ADDR)
#define MLVDS_CLK_CTL1_HI 0x1443 	///../ucode/register.h:8712
#define P_MLVDS_CLK_CTL1_HI 		VCBUS_REG_ADDR(MLVDS_CLK_CTL1_HI)
#define MLVDS_CLK_CTL1_LO 0x1444 	///../ucode/register.h:8713
#define P_MLVDS_CLK_CTL1_LO 		VCBUS_REG_ADDR(MLVDS_CLK_CTL1_LO)
#define L_TCON_DOUBLE_CTL 0x1449 	///../ucode/register.h:8717
#define P_L_TCON_DOUBLE_CTL 		VCBUS_REG_ADDR(L_TCON_DOUBLE_CTL)
#define L_TCON_PATTERN_HI 0x144a 	///../ucode/register.h:8718
#define P_L_TCON_PATTERN_HI 		VCBUS_REG_ADDR(L_TCON_PATTERN_HI)
#define L_TCON_PATTERN_LO 0x144b 	///../ucode/register.h:8719
#define P_L_TCON_PATTERN_LO 		VCBUS_REG_ADDR(L_TCON_PATTERN_LO)
#define LDIM_BL_ADDR_PORT 0x144e 	///../ucode/register.h:8720
#define P_LDIM_BL_ADDR_PORT 		VCBUS_REG_ADDR(LDIM_BL_ADDR_PORT)
#define LDIM_BL_DATA_PORT 0x144f 	///../ucode/register.h:8721
#define P_LDIM_BL_DATA_PORT 		VCBUS_REG_ADDR(LDIM_BL_DATA_PORT)
#define L_DE_HS_ADDR 0x1451 	///../ucode/register.h:8722
#define P_L_DE_HS_ADDR 		VCBUS_REG_ADDR(L_DE_HS_ADDR)
#define L_DE_HE_ADDR 0x1452 	///../ucode/register.h:8723
#define P_L_DE_HE_ADDR 		VCBUS_REG_ADDR(L_DE_HE_ADDR)
#define L_DE_VS_ADDR 0x1453 	///../ucode/register.h:8724
#define P_L_DE_VS_ADDR 		VCBUS_REG_ADDR(L_DE_VS_ADDR)
#define L_DE_VE_ADDR 0x1454 	///../ucode/register.h:8725
#define P_L_DE_VE_ADDR 		VCBUS_REG_ADDR(L_DE_VE_ADDR)
#define L_HSYNC_HS_ADDR 0x1455 	///../ucode/register.h:8726
#define P_L_HSYNC_HS_ADDR 		VCBUS_REG_ADDR(L_HSYNC_HS_ADDR)
#define L_HSYNC_HE_ADDR 0x1456 	///../ucode/register.h:8727
#define P_L_HSYNC_HE_ADDR 		VCBUS_REG_ADDR(L_HSYNC_HE_ADDR)
#define L_HSYNC_VS_ADDR 0x1457 	///../ucode/register.h:8728
#define P_L_HSYNC_VS_ADDR 		VCBUS_REG_ADDR(L_HSYNC_VS_ADDR)
#define L_HSYNC_VE_ADDR 0x1458 	///../ucode/register.h:8729
#define P_L_HSYNC_VE_ADDR 		VCBUS_REG_ADDR(L_HSYNC_VE_ADDR)
#define L_VSYNC_HS_ADDR 0x1459 	///../ucode/register.h:8730
#define P_L_VSYNC_HS_ADDR 		VCBUS_REG_ADDR(L_VSYNC_HS_ADDR)
#define L_VSYNC_HE_ADDR 0x145a 	///../ucode/register.h:8731
#define P_L_VSYNC_HE_ADDR 		VCBUS_REG_ADDR(L_VSYNC_HE_ADDR)
#define L_VSYNC_VS_ADDR 0x145b 	///../ucode/register.h:8732
#define P_L_VSYNC_VS_ADDR 		VCBUS_REG_ADDR(L_VSYNC_VS_ADDR)
#define L_VSYNC_VE_ADDR 0x145c 	///../ucode/register.h:8733
#define P_L_VSYNC_VE_ADDR 		VCBUS_REG_ADDR(L_VSYNC_VE_ADDR)
#define L_LCD_MCU_CTL 0x145d 	///../ucode/register.h:8743
#define P_L_LCD_MCU_CTL 		VCBUS_REG_ADDR(L_LCD_MCU_CTL)
#define DUAL_MLVDS_CTL 0x1460 	///../ucode/register.h:8751
#define P_DUAL_MLVDS_CTL 		VCBUS_REG_ADDR(DUAL_MLVDS_CTL)
#define DUAL_MLVDS_LINE_START 0x1461 	///../ucode/register.h:8753
#define P_DUAL_MLVDS_LINE_START 		VCBUS_REG_ADDR(DUAL_MLVDS_LINE_START)
#define DUAL_MLVDS_LINE_END 0x1462 	///../ucode/register.h:8755
#define P_DUAL_MLVDS_LINE_END 		VCBUS_REG_ADDR(DUAL_MLVDS_LINE_END)
#define DUAL_MLVDS_PIXEL_W_START_L 0x1463 	///../ucode/register.h:8757
#define P_DUAL_MLVDS_PIXEL_W_START_L 		VCBUS_REG_ADDR(DUAL_MLVDS_PIXEL_W_START_L)
#define DUAL_MLVDS_PIXEL_W_END_L 0x1464 	///../ucode/register.h:8759
#define P_DUAL_MLVDS_PIXEL_W_END_L 		VCBUS_REG_ADDR(DUAL_MLVDS_PIXEL_W_END_L)
#define DUAL_MLVDS_PIXEL_W_START_R 0x1465 	///../ucode/register.h:8761
#define P_DUAL_MLVDS_PIXEL_W_START_R 		VCBUS_REG_ADDR(DUAL_MLVDS_PIXEL_W_START_R)
#define DUAL_MLVDS_PIXEL_W_END_R 0x1466 	///../ucode/register.h:8763
#define P_DUAL_MLVDS_PIXEL_W_END_R 		VCBUS_REG_ADDR(DUAL_MLVDS_PIXEL_W_END_R)
#define DUAL_MLVDS_PIXEL_R_START_L 0x1467 	///../ucode/register.h:8765
#define P_DUAL_MLVDS_PIXEL_R_START_L 		VCBUS_REG_ADDR(DUAL_MLVDS_PIXEL_R_START_L)
#define DUAL_MLVDS_PIXEL_R_CNT_L 0x1468 	///../ucode/register.h:8767
#define P_DUAL_MLVDS_PIXEL_R_CNT_L 		VCBUS_REG_ADDR(DUAL_MLVDS_PIXEL_R_CNT_L)
#define DUAL_MLVDS_PIXEL_R_START_R 0x1469 	///../ucode/register.h:8769
#define P_DUAL_MLVDS_PIXEL_R_START_R 		VCBUS_REG_ADDR(DUAL_MLVDS_PIXEL_R_START_R)
#define DUAL_MLVDS_PIXEL_R_CNT_R 0x146a 	///../ucode/register.h:8771
#define P_DUAL_MLVDS_PIXEL_R_CNT_R 		VCBUS_REG_ADDR(DUAL_MLVDS_PIXEL_R_CNT_R)
#define V_INVERSION_PIXEL 0x1470 	///../ucode/register.h:8774
#define P_V_INVERSION_PIXEL 		VCBUS_REG_ADDR(V_INVERSION_PIXEL)
#define V_INVERSION_LINE 0x1471 	///../ucode/register.h:8777
#define P_V_INVERSION_LINE 		VCBUS_REG_ADDR(V_INVERSION_LINE)
#define V_INVERSION_CONTROL 0x1472 	///../ucode/register.h:8784
#define P_V_INVERSION_CONTROL 		VCBUS_REG_ADDR(V_INVERSION_CONTROL)
#define MLVDS2_CONTROL 0x1474 	///../ucode/register.h:8785
#define P_MLVDS2_CONTROL 		VCBUS_REG_ADDR(MLVDS2_CONTROL)
#define MLVDS2_CONFIG_HI 0x1475 	///../ucode/register.h:8797
#define P_MLVDS2_CONFIG_HI 		VCBUS_REG_ADDR(MLVDS2_CONFIG_HI)
#define MLVDS2_CONFIG_LO 0x1476 	///../ucode/register.h:8798
#define P_MLVDS2_CONFIG_LO 		VCBUS_REG_ADDR(MLVDS2_CONFIG_LO)
#define MLVDS2_DUAL_GATE_WR_START 0x1477 	///../ucode/register.h:8811
#define P_MLVDS2_DUAL_GATE_WR_START 		VCBUS_REG_ADDR(MLVDS2_DUAL_GATE_WR_START)
#define MLVDS2_DUAL_GATE_WR_END 0x1478 	///../ucode/register.h:8813
#define P_MLVDS2_DUAL_GATE_WR_END 		VCBUS_REG_ADDR(MLVDS2_DUAL_GATE_WR_END)
#define MLVDS2_DUAL_GATE_RD_START 0x1479 	///../ucode/register.h:8815
#define P_MLVDS2_DUAL_GATE_RD_START 		VCBUS_REG_ADDR(MLVDS2_DUAL_GATE_RD_START)
#define MLVDS2_DUAL_GATE_RD_END 0x147a 	///../ucode/register.h:8817
#define P_MLVDS2_DUAL_GATE_RD_END 		VCBUS_REG_ADDR(MLVDS2_DUAL_GATE_RD_END)
#define MLVDS2_SECOND_RESET_CTL 0x147b 	///../ucode/register.h:8819
#define P_MLVDS2_SECOND_RESET_CTL 		VCBUS_REG_ADDR(MLVDS2_SECOND_RESET_CTL)
#define MLVDS2_DUAL_GATE_CTL_HI 0x147c 	///../ucode/register.h:8821
#define P_MLVDS2_DUAL_GATE_CTL_HI 		VCBUS_REG_ADDR(MLVDS2_DUAL_GATE_CTL_HI)
#define MLVDS2_DUAL_GATE_CTL_LO 0x147d 	///../ucode/register.h:8822
#define P_MLVDS2_DUAL_GATE_CTL_LO 		VCBUS_REG_ADDR(MLVDS2_DUAL_GATE_CTL_LO)
#define MLVDS2_RESET_CONFIG_HI 0x147e 	///../ucode/register.h:8829
#define P_MLVDS2_RESET_CONFIG_HI 		VCBUS_REG_ADDR(MLVDS2_RESET_CONFIG_HI)
#define MLVDS2_RESET_CONFIG_LO 0x147f 	///../ucode/register.h:8830
#define P_MLVDS2_RESET_CONFIG_LO 		VCBUS_REG_ADDR(MLVDS2_RESET_CONFIG_LO)
#define GAMMA_CNTL_PORT 0x1480 	///../ucode/register.h:8840
#define P_GAMMA_CNTL_PORT 		VCBUS_REG_ADDR(GAMMA_CNTL_PORT)
#define GAMMA_DATA_PORT 0x1481 	///../ucode/register.h:8849
#define P_GAMMA_DATA_PORT 		VCBUS_REG_ADDR(GAMMA_DATA_PORT)
#define GAMMA_ADDR_PORT 0x1482 	///../ucode/register.h:8850
#define P_GAMMA_ADDR_PORT 		VCBUS_REG_ADDR(GAMMA_ADDR_PORT)
#define GAMMA_VCOM_HSWITCH_ADDR 0x1483 	///../ucode/register.h:8858
#define P_GAMMA_VCOM_HSWITCH_ADDR 		VCBUS_REG_ADDR(GAMMA_VCOM_HSWITCH_ADDR)
#define RGB_BASE_ADDR 0x1485 	///../ucode/register.h:8859
#define P_RGB_BASE_ADDR 		VCBUS_REG_ADDR(RGB_BASE_ADDR)
#define RGB_COEFF_ADDR 0x1486 	///../ucode/register.h:8860
#define P_RGB_COEFF_ADDR 		VCBUS_REG_ADDR(RGB_COEFF_ADDR)
#define POL_CNTL_ADDR 0x1487 	///../ucode/register.h:8861
#define P_POL_CNTL_ADDR 		VCBUS_REG_ADDR(POL_CNTL_ADDR)
#define DITH_CNTL_ADDR 0x1488 	///../ucode/register.h:8875
#define P_DITH_CNTL_ADDR 		VCBUS_REG_ADDR(DITH_CNTL_ADDR)
#define GAMMA_PROBE_CTRL 0x1489 	///../ucode/register.h:8885
#define P_GAMMA_PROBE_CTRL 		VCBUS_REG_ADDR(GAMMA_PROBE_CTRL)
#define GAMMA_PROBE_COLOR_L 0x148a 	///../ucode/register.h:8888
#define P_GAMMA_PROBE_COLOR_L 		VCBUS_REG_ADDR(GAMMA_PROBE_COLOR_L)
#define GAMMA_PROBE_COLOR_H 0x148b 	///../ucode/register.h:8892
#define P_GAMMA_PROBE_COLOR_H 		VCBUS_REG_ADDR(GAMMA_PROBE_COLOR_H)
#define GAMMA_PROBE_HL_COLOR 0x148c 	///../ucode/register.h:8894
#define P_GAMMA_PROBE_HL_COLOR 		VCBUS_REG_ADDR(GAMMA_PROBE_HL_COLOR)
#define GAMMA_PROBE_POS_X 0x148d 	///../ucode/register.h:8896
#define P_GAMMA_PROBE_POS_X 		VCBUS_REG_ADDR(GAMMA_PROBE_POS_X)
#define GAMMA_PROBE_POS_Y 0x148e 	///../ucode/register.h:8898
#define P_GAMMA_PROBE_POS_Y 		VCBUS_REG_ADDR(GAMMA_PROBE_POS_Y)
#define STH1_HS_ADDR 0x1490 	///../ucode/register.h:8899
#define P_STH1_HS_ADDR 		VCBUS_REG_ADDR(STH1_HS_ADDR)
#define STH1_HE_ADDR 0x1491 	///../ucode/register.h:8900
#define P_STH1_HE_ADDR 		VCBUS_REG_ADDR(STH1_HE_ADDR)
#define STH1_VS_ADDR 0x1492 	///../ucode/register.h:8901
#define P_STH1_VS_ADDR 		VCBUS_REG_ADDR(STH1_VS_ADDR)
#define STH1_VE_ADDR 0x1493 	///../ucode/register.h:8902
#define P_STH1_VE_ADDR 		VCBUS_REG_ADDR(STH1_VE_ADDR)
#define STH2_HS_ADDR 0x1494 	///../ucode/register.h:8903
#define P_STH2_HS_ADDR 		VCBUS_REG_ADDR(STH2_HS_ADDR)
#define STH2_HE_ADDR 0x1495 	///../ucode/register.h:8904
#define P_STH2_HE_ADDR 		VCBUS_REG_ADDR(STH2_HE_ADDR)
#define STH2_VS_ADDR 0x1496 	///../ucode/register.h:8905
#define P_STH2_VS_ADDR 		VCBUS_REG_ADDR(STH2_VS_ADDR)
#define STH2_VE_ADDR 0x1497 	///../ucode/register.h:8906
#define P_STH2_VE_ADDR 		VCBUS_REG_ADDR(STH2_VE_ADDR)
#define OEH_HS_ADDR 0x1498 	///../ucode/register.h:8907
#define P_OEH_HS_ADDR 		VCBUS_REG_ADDR(OEH_HS_ADDR)
#define OEH_HE_ADDR 0x1499 	///../ucode/register.h:8908
#define P_OEH_HE_ADDR 		VCBUS_REG_ADDR(OEH_HE_ADDR)
#define OEH_VS_ADDR 0x149a 	///../ucode/register.h:8909
#define P_OEH_VS_ADDR 		VCBUS_REG_ADDR(OEH_VS_ADDR)
#define OEH_VE_ADDR 0x149b 	///../ucode/register.h:8910
#define P_OEH_VE_ADDR 		VCBUS_REG_ADDR(OEH_VE_ADDR)
#define VCOM_HSWITCH_ADDR 0x149c 	///../ucode/register.h:8911
#define P_VCOM_HSWITCH_ADDR 		VCBUS_REG_ADDR(VCOM_HSWITCH_ADDR)
#define VCOM_VS_ADDR 0x149d 	///../ucode/register.h:8912
#define P_VCOM_VS_ADDR 		VCBUS_REG_ADDR(VCOM_VS_ADDR)
#define VCOM_VE_ADDR 0x149e 	///../ucode/register.h:8913
#define P_VCOM_VE_ADDR 		VCBUS_REG_ADDR(VCOM_VE_ADDR)
#define CPV1_HS_ADDR 0x149f 	///../ucode/register.h:8914
#define P_CPV1_HS_ADDR 		VCBUS_REG_ADDR(CPV1_HS_ADDR)
#define CPV1_HE_ADDR 0x14a0 	///../ucode/register.h:8915
#define P_CPV1_HE_ADDR 		VCBUS_REG_ADDR(CPV1_HE_ADDR)
#define CPV1_VS_ADDR 0x14a1 	///../ucode/register.h:8916
#define P_CPV1_VS_ADDR 		VCBUS_REG_ADDR(CPV1_VS_ADDR)
#define CPV1_VE_ADDR 0x14a2 	///../ucode/register.h:8917
#define P_CPV1_VE_ADDR 		VCBUS_REG_ADDR(CPV1_VE_ADDR)
#define CPV2_HS_ADDR 0x14a3 	///../ucode/register.h:8918
#define P_CPV2_HS_ADDR 		VCBUS_REG_ADDR(CPV2_HS_ADDR)
#define CPV2_HE_ADDR 0x14a4 	///../ucode/register.h:8919
#define P_CPV2_HE_ADDR 		VCBUS_REG_ADDR(CPV2_HE_ADDR)
#define CPV2_VS_ADDR 0x14a5 	///../ucode/register.h:8920
#define P_CPV2_VS_ADDR 		VCBUS_REG_ADDR(CPV2_VS_ADDR)
#define CPV2_VE_ADDR 0x14a6 	///../ucode/register.h:8921
#define P_CPV2_VE_ADDR 		VCBUS_REG_ADDR(CPV2_VE_ADDR)
#define STV1_HS_ADDR 0x14a7 	///../ucode/register.h:8922
#define P_STV1_HS_ADDR 		VCBUS_REG_ADDR(STV1_HS_ADDR)
#define STV1_HE_ADDR 0x14a8 	///../ucode/register.h:8923
#define P_STV1_HE_ADDR 		VCBUS_REG_ADDR(STV1_HE_ADDR)
#define STV1_VS_ADDR 0x14a9 	///../ucode/register.h:8924
#define P_STV1_VS_ADDR 		VCBUS_REG_ADDR(STV1_VS_ADDR)
#define STV1_VE_ADDR 0x14aa 	///../ucode/register.h:8925
#define P_STV1_VE_ADDR 		VCBUS_REG_ADDR(STV1_VE_ADDR)
#define STV2_HS_ADDR 0x14ab 	///../ucode/register.h:8926
#define P_STV2_HS_ADDR 		VCBUS_REG_ADDR(STV2_HS_ADDR)
#define STV2_HE_ADDR 0x14ac 	///../ucode/register.h:8927
#define P_STV2_HE_ADDR 		VCBUS_REG_ADDR(STV2_HE_ADDR)
#define STV2_VS_ADDR 0x14ad 	///../ucode/register.h:8928
#define P_STV2_VS_ADDR 		VCBUS_REG_ADDR(STV2_VS_ADDR)
#define STV2_VE_ADDR 0x14ae 	///../ucode/register.h:8929
#define P_STV2_VE_ADDR 		VCBUS_REG_ADDR(STV2_VE_ADDR)
#define OEV1_HS_ADDR 0x14af 	///../ucode/register.h:8930
#define P_OEV1_HS_ADDR 		VCBUS_REG_ADDR(OEV1_HS_ADDR)
#define OEV1_HE_ADDR 0x14b0 	///../ucode/register.h:8931
#define P_OEV1_HE_ADDR 		VCBUS_REG_ADDR(OEV1_HE_ADDR)
#define OEV1_VS_ADDR 0x14b1 	///../ucode/register.h:8932
#define P_OEV1_VS_ADDR 		VCBUS_REG_ADDR(OEV1_VS_ADDR)
#define OEV1_VE_ADDR 0x14b2 	///../ucode/register.h:8933
#define P_OEV1_VE_ADDR 		VCBUS_REG_ADDR(OEV1_VE_ADDR)
#define OEV2_HS_ADDR 0x14b3 	///../ucode/register.h:8934
#define P_OEV2_HS_ADDR 		VCBUS_REG_ADDR(OEV2_HS_ADDR)
#define OEV2_HE_ADDR 0x14b4 	///../ucode/register.h:8935
#define P_OEV2_HE_ADDR 		VCBUS_REG_ADDR(OEV2_HE_ADDR)
#define OEV2_VS_ADDR 0x14b5 	///../ucode/register.h:8936
#define P_OEV2_VS_ADDR 		VCBUS_REG_ADDR(OEV2_VS_ADDR)
#define OEV2_VE_ADDR 0x14b6 	///../ucode/register.h:8937
#define P_OEV2_VE_ADDR 		VCBUS_REG_ADDR(OEV2_VE_ADDR)
#define OEV3_HS_ADDR 0x14b7 	///../ucode/register.h:8938
#define P_OEV3_HS_ADDR 		VCBUS_REG_ADDR(OEV3_HS_ADDR)
#define OEV3_HE_ADDR 0x14b8 	///../ucode/register.h:8939
#define P_OEV3_HE_ADDR 		VCBUS_REG_ADDR(OEV3_HE_ADDR)
#define OEV3_VS_ADDR 0x14b9 	///../ucode/register.h:8940
#define P_OEV3_VS_ADDR 		VCBUS_REG_ADDR(OEV3_VS_ADDR)
#define OEV3_VE_ADDR 0x14ba 	///../ucode/register.h:8941
#define P_OEV3_VE_ADDR 		VCBUS_REG_ADDR(OEV3_VE_ADDR)
#define LCD_PWR_ADDR 0x14bb 	///../ucode/register.h:8942
#define P_LCD_PWR_ADDR 		VCBUS_REG_ADDR(LCD_PWR_ADDR)
#define LCD_PWM0_LO_ADDR 0x14bc 	///../ucode/register.h:8947
#define P_LCD_PWM0_LO_ADDR 		VCBUS_REG_ADDR(LCD_PWM0_LO_ADDR)
#define LCD_PWM0_HI_ADDR 0x14bd 	///../ucode/register.h:8948
#define P_LCD_PWM0_HI_ADDR 		VCBUS_REG_ADDR(LCD_PWM0_HI_ADDR)
#define LCD_PWM1_LO_ADDR 0x14be 	///../ucode/register.h:8949
#define P_LCD_PWM1_LO_ADDR 		VCBUS_REG_ADDR(LCD_PWM1_LO_ADDR)
#define LCD_PWM1_HI_ADDR 0x14bf 	///../ucode/register.h:8950
#define P_LCD_PWM1_HI_ADDR 		VCBUS_REG_ADDR(LCD_PWM1_HI_ADDR)
#define INV_CNT_ADDR 0x14c0 	///../ucode/register.h:8951
#define P_INV_CNT_ADDR 		VCBUS_REG_ADDR(INV_CNT_ADDR)
#define TCON_MISC_SEL_ADDR 0x14c1 	///../ucode/register.h:8955
#define P_TCON_MISC_SEL_ADDR 		VCBUS_REG_ADDR(TCON_MISC_SEL_ADDR)
#define DUAL_PORT_CNTL_ADDR 0x14c2 	///../ucode/register.h:8969
#define P_DUAL_PORT_CNTL_ADDR 		VCBUS_REG_ADDR(DUAL_PORT_CNTL_ADDR)
#define MLVDS_CONTROL 0x14c3 	///../ucode/register.h:8982
#define P_MLVDS_CONTROL 		VCBUS_REG_ADDR(MLVDS_CONTROL)
#define MLVDS_RESET_PATTERN_HI 0x14c4 	///../ucode/register.h:8994
#define P_MLVDS_RESET_PATTERN_HI 		VCBUS_REG_ADDR(MLVDS_RESET_PATTERN_HI)
#define MLVDS_RESET_PATTERN_LO 0x14c5 	///../ucode/register.h:8995
#define P_MLVDS_RESET_PATTERN_LO 		VCBUS_REG_ADDR(MLVDS_RESET_PATTERN_LO)
#define MLVDS_RESET_PATTERN_EXT 0x14c6 	///../ucode/register.h:8997
#define P_MLVDS_RESET_PATTERN_EXT 		VCBUS_REG_ADDR(MLVDS_RESET_PATTERN_EXT)
#define MLVDS_CONFIG_HI 0x14c7 	///../ucode/register.h:8999
#define P_MLVDS_CONFIG_HI 		VCBUS_REG_ADDR(MLVDS_CONFIG_HI)
#define MLVDS_CONFIG_LO 0x14c8 	///../ucode/register.h:9000
#define P_MLVDS_CONFIG_LO 		VCBUS_REG_ADDR(MLVDS_CONFIG_LO)
#define TCON_DOUBLE_CTL 0x14c9 	///../ucode/register.h:9013
#define P_TCON_DOUBLE_CTL 		VCBUS_REG_ADDR(TCON_DOUBLE_CTL)
#define TCON_PATTERN_HI 0x14ca 	///../ucode/register.h:9016
#define P_TCON_PATTERN_HI 		VCBUS_REG_ADDR(TCON_PATTERN_HI)
#define TCON_PATTERN_LO 0x14cb 	///../ucode/register.h:9017
#define P_TCON_PATTERN_LO 		VCBUS_REG_ADDR(TCON_PATTERN_LO)
#define TCON_CONTROL_HI 0x14cc 	///../ucode/register.h:9022
#define P_TCON_CONTROL_HI 		VCBUS_REG_ADDR(TCON_CONTROL_HI)
#define TCON_CONTROL_LO 0x14cd 	///../ucode/register.h:9023
#define P_TCON_CONTROL_LO 		VCBUS_REG_ADDR(TCON_CONTROL_LO)
#define LVDS_BLANK_DATA_HI 0x14ce 	///../ucode/register.h:9027
#define P_LVDS_BLANK_DATA_HI 		VCBUS_REG_ADDR(LVDS_BLANK_DATA_HI)
#define LVDS_BLANK_DATA_LO 0x14cf 	///../ucode/register.h:9028
#define P_LVDS_BLANK_DATA_LO 		VCBUS_REG_ADDR(LVDS_BLANK_DATA_LO)
#define LVDS_PACK_CNTL_ADDR 0x14d0 	///../ucode/register.h:9033
#define P_LVDS_PACK_CNTL_ADDR 		VCBUS_REG_ADDR(LVDS_PACK_CNTL_ADDR)
#define DE_HS_ADDR 0x14d1 	///../ucode/register.h:9044
#define P_DE_HS_ADDR 		VCBUS_REG_ADDR(DE_HS_ADDR)
#define DE_HE_ADDR 0x14d2 	///../ucode/register.h:9047
#define P_DE_HE_ADDR 		VCBUS_REG_ADDR(DE_HE_ADDR)
#define DE_VS_ADDR 0x14d3 	///../ucode/register.h:9048
#define P_DE_VS_ADDR 		VCBUS_REG_ADDR(DE_VS_ADDR)
#define DE_VE_ADDR 0x14d4 	///../ucode/register.h:9049
#define P_DE_VE_ADDR 		VCBUS_REG_ADDR(DE_VE_ADDR)
#define HSYNC_HS_ADDR 0x14d5 	///../ucode/register.h:9050
#define P_HSYNC_HS_ADDR 		VCBUS_REG_ADDR(HSYNC_HS_ADDR)
#define HSYNC_HE_ADDR 0x14d6 	///../ucode/register.h:9051
#define P_HSYNC_HE_ADDR 		VCBUS_REG_ADDR(HSYNC_HE_ADDR)
#define HSYNC_VS_ADDR 0x14d7 	///../ucode/register.h:9052
#define P_HSYNC_VS_ADDR 		VCBUS_REG_ADDR(HSYNC_VS_ADDR)
#define HSYNC_VE_ADDR 0x14d8 	///../ucode/register.h:9053
#define P_HSYNC_VE_ADDR 		VCBUS_REG_ADDR(HSYNC_VE_ADDR)
#define VSYNC_HS_ADDR 0x14d9 	///../ucode/register.h:9054
#define P_VSYNC_HS_ADDR 		VCBUS_REG_ADDR(VSYNC_HS_ADDR)
#define VSYNC_HE_ADDR 0x14da 	///../ucode/register.h:9055
#define P_VSYNC_HE_ADDR 		VCBUS_REG_ADDR(VSYNC_HE_ADDR)
#define VSYNC_VS_ADDR 0x14db 	///../ucode/register.h:9056
#define P_VSYNC_VS_ADDR 		VCBUS_REG_ADDR(VSYNC_VS_ADDR)
#define VSYNC_VE_ADDR 0x14dc 	///../ucode/register.h:9057
#define P_VSYNC_VE_ADDR 		VCBUS_REG_ADDR(VSYNC_VE_ADDR)
#define LCD_MCU_CTL 0x14dd 	///../ucode/register.h:9067
#define P_LCD_MCU_CTL 		VCBUS_REG_ADDR(LCD_MCU_CTL)
#define LCD_MCU_DATA_0 0x14de 	///../ucode/register.h:9072
#define P_LCD_MCU_DATA_0 		VCBUS_REG_ADDR(LCD_MCU_DATA_0)
#define LCD_MCU_DATA_1 0x14df 	///../ucode/register.h:9076
#define P_LCD_MCU_DATA_1 		VCBUS_REG_ADDR(LCD_MCU_DATA_1)
#define LVDS_GEN_CNTL 0x14e0 	///../ucode/register.h:9078
#define P_LVDS_GEN_CNTL 		VCBUS_REG_ADDR(LVDS_GEN_CNTL)
#define LVDS_PHY_CNTL0 0x14e1 	///../ucode/register.h:9079
#define P_LVDS_PHY_CNTL0 		VCBUS_REG_ADDR(LVDS_PHY_CNTL0)
#define LVDS_PHY_CNTL1 0x14e2 	///../ucode/register.h:9080
#define P_LVDS_PHY_CNTL1 		VCBUS_REG_ADDR(LVDS_PHY_CNTL1)
#define LVDS_PHY_CNTL2 0x14e3 	///../ucode/register.h:9081
#define P_LVDS_PHY_CNTL2 		VCBUS_REG_ADDR(LVDS_PHY_CNTL2)
#define LVDS_PHY_CNTL3 0x14e4 	///../ucode/register.h:9082
#define P_LVDS_PHY_CNTL3 		VCBUS_REG_ADDR(LVDS_PHY_CNTL3)
#define LVDS_PHY_CNTL4 0x14e5 	///../ucode/register.h:9083
#define P_LVDS_PHY_CNTL4 		VCBUS_REG_ADDR(LVDS_PHY_CNTL4)
#define LVDS_PHY_CNTL5 0x14e6 	///../ucode/register.h:9084
#define P_LVDS_PHY_CNTL5 		VCBUS_REG_ADDR(LVDS_PHY_CNTL5)
#define LVDS_SRG_TEST 0x14e8 	///../ucode/register.h:9085
#define P_LVDS_SRG_TEST 		VCBUS_REG_ADDR(LVDS_SRG_TEST)
#define LVDS_BIST_MUX0 0x14e9 	///../ucode/register.h:9086
#define P_LVDS_BIST_MUX0 		VCBUS_REG_ADDR(LVDS_BIST_MUX0)
#define LVDS_BIST_MUX1 0x14ea 	///../ucode/register.h:9087
#define P_LVDS_BIST_MUX1 		VCBUS_REG_ADDR(LVDS_BIST_MUX1)
#define LVDS_BIST_FIXED0 0x14eb 	///../ucode/register.h:9088
#define P_LVDS_BIST_FIXED0 		VCBUS_REG_ADDR(LVDS_BIST_FIXED0)
#define LVDS_BIST_FIXED1 0x14ec 	///../ucode/register.h:9089
#define P_LVDS_BIST_FIXED1 		VCBUS_REG_ADDR(LVDS_BIST_FIXED1)
#define LVDS_BIST_CNTL0 0x14ed 	///../ucode/register.h:9090
#define P_LVDS_BIST_CNTL0 		VCBUS_REG_ADDR(LVDS_BIST_CNTL0)
#define LVDS_CLKB_CLKA 0x14ee 	///../ucode/register.h:9091
#define P_LVDS_CLKB_CLKA 		VCBUS_REG_ADDR(LVDS_CLKB_CLKA)
#define LVDS_PHY_CLK_CNTL 0x14ef 	///../ucode/register.h:9092
#define P_LVDS_PHY_CLK_CNTL 		VCBUS_REG_ADDR(LVDS_PHY_CLK_CNTL)
#define LVDS_SER_EN 0x14f0 	///../ucode/register.h:9093
#define P_LVDS_SER_EN 		VCBUS_REG_ADDR(LVDS_SER_EN)
#define LVDS_PHY_CNTL6 0x14f1 	///../ucode/register.h:9094
#define P_LVDS_PHY_CNTL6 		VCBUS_REG_ADDR(LVDS_PHY_CNTL6)
#define LVDS_PHY_CNTL7 0x14f2 	///../ucode/register.h:9095
#define P_LVDS_PHY_CNTL7 		VCBUS_REG_ADDR(LVDS_PHY_CNTL7)
#define LVDS_PHY_CNTL8 0x14f3 	///../ucode/register.h:9096
#define P_LVDS_PHY_CNTL8 		VCBUS_REG_ADDR(LVDS_PHY_CNTL8)
#define MLVDS_CLK_CTL0_HI 0x14f4 	///../ucode/register.h:9097
#define P_MLVDS_CLK_CTL0_HI 		VCBUS_REG_ADDR(MLVDS_CLK_CTL0_HI)
#define MLVDS_CLK_CTL0_LO 0x14f5 	///../ucode/register.h:9098
#define P_MLVDS_CLK_CTL0_LO 		VCBUS_REG_ADDR(MLVDS_CLK_CTL0_LO)
#define MLVDS_DUAL_GATE_WR_START 0x14f6 	///../ucode/register.h:9105
#define P_MLVDS_DUAL_GATE_WR_START 		VCBUS_REG_ADDR(MLVDS_DUAL_GATE_WR_START)
#define MLVDS_DUAL_GATE_WR_END 0x14f7 	///../ucode/register.h:9107
#define P_MLVDS_DUAL_GATE_WR_END 		VCBUS_REG_ADDR(MLVDS_DUAL_GATE_WR_END)
#define MLVDS_DUAL_GATE_RD_START 0x14f8 	///../ucode/register.h:9109
#define P_MLVDS_DUAL_GATE_RD_START 		VCBUS_REG_ADDR(MLVDS_DUAL_GATE_RD_START)
#define MLVDS_DUAL_GATE_RD_END 0x14f9 	///../ucode/register.h:9111
#define P_MLVDS_DUAL_GATE_RD_END 		VCBUS_REG_ADDR(MLVDS_DUAL_GATE_RD_END)
#define MLVDS_SECOND_RESET_CTL 0x14fa 	///../ucode/register.h:9113
#define P_MLVDS_SECOND_RESET_CTL 		VCBUS_REG_ADDR(MLVDS_SECOND_RESET_CTL)
#define MLVDS_DUAL_GATE_CTL_HI 0x14fb 	///../ucode/register.h:9115
#define P_MLVDS_DUAL_GATE_CTL_HI 		VCBUS_REG_ADDR(MLVDS_DUAL_GATE_CTL_HI)
#define MLVDS_DUAL_GATE_CTL_LO 0x14fc 	///../ucode/register.h:9116
#define P_MLVDS_DUAL_GATE_CTL_LO 		VCBUS_REG_ADDR(MLVDS_DUAL_GATE_CTL_LO)
#define MLVDS_RESET_CONFIG_HI 0x14fd 	///../ucode/register.h:9123
#define P_MLVDS_RESET_CONFIG_HI 		VCBUS_REG_ADDR(MLVDS_RESET_CONFIG_HI)
#define MLVDS_RESET_CONFIG_LO 0x14fe 	///../ucode/register.h:9124
#define P_MLVDS_RESET_CONFIG_LO 		VCBUS_REG_ADDR(MLVDS_RESET_CONFIG_LO)
#define VPU_OSD1_MMC_CTRL 0x2701 	///../ucode/register.h:9143
#define P_VPU_OSD1_MMC_CTRL 		VCBUS_REG_ADDR(VPU_OSD1_MMC_CTRL)
#define VPU_OSD2_MMC_CTRL 0x2702 	///../ucode/register.h:9144
#define P_VPU_OSD2_MMC_CTRL 		VCBUS_REG_ADDR(VPU_OSD2_MMC_CTRL)
#define VPU_VD1_MMC_CTRL 0x2703 	///../ucode/register.h:9145
#define P_VPU_VD1_MMC_CTRL 		VCBUS_REG_ADDR(VPU_VD1_MMC_CTRL)
#define VPU_VD2_MMC_CTRL 0x2704 	///../ucode/register.h:9146
#define P_VPU_VD2_MMC_CTRL 		VCBUS_REG_ADDR(VPU_VD2_MMC_CTRL)
#define VPU_DI_IF1_MMC_CTRL 0x2705 	///../ucode/register.h:9147
#define P_VPU_DI_IF1_MMC_CTRL 		VCBUS_REG_ADDR(VPU_DI_IF1_MMC_CTRL)
#define VPU_DI_MEM_MMC_CTRL 0x2706 	///../ucode/register.h:9148
#define P_VPU_DI_MEM_MMC_CTRL 		VCBUS_REG_ADDR(VPU_DI_MEM_MMC_CTRL)
#define VPU_DI_INP_MMC_CTRL 0x2707 	///../ucode/register.h:9149
#define P_VPU_DI_INP_MMC_CTRL 		VCBUS_REG_ADDR(VPU_DI_INP_MMC_CTRL)
#define VPU_DI_MTNRD_MMC_CTRL 0x2708 	///../ucode/register.h:9150
#define P_VPU_DI_MTNRD_MMC_CTRL 		VCBUS_REG_ADDR(VPU_DI_MTNRD_MMC_CTRL)
#define VPU_DI_CHAN2_MMC_CTRL 0x2709 	///../ucode/register.h:9151
#define P_VPU_DI_CHAN2_MMC_CTRL 		VCBUS_REG_ADDR(VPU_DI_CHAN2_MMC_CTRL)
#define VPU_DI_MTNWR_MMC_CTRL 0x270a 	///../ucode/register.h:9152
#define P_VPU_DI_MTNWR_MMC_CTRL 		VCBUS_REG_ADDR(VPU_DI_MTNWR_MMC_CTRL)
#define VPU_DI_NRWR_MMC_CTRL 0x270b 	///../ucode/register.h:9153
#define P_VPU_DI_NRWR_MMC_CTRL 		VCBUS_REG_ADDR(VPU_DI_NRWR_MMC_CTRL)
#define VPU_DI_DIWR_MMC_CTRL 0x270c 	///../ucode/register.h:9154
#define P_VPU_DI_DIWR_MMC_CTRL 		VCBUS_REG_ADDR(VPU_DI_DIWR_MMC_CTRL)
#define VPU_VDIN0_MMC_CTRL 0x270d 	///../ucode/register.h:9155
#define P_VPU_VDIN0_MMC_CTRL 		VCBUS_REG_ADDR(VPU_VDIN0_MMC_CTRL)
#define VPU_VDIN1_MMC_CTRL 0x270e 	///../ucode/register.h:9156
#define P_VPU_VDIN1_MMC_CTRL 		VCBUS_REG_ADDR(VPU_VDIN1_MMC_CTRL)
#define VPU_BT656_MMC_CTRL 0x270f 	///../ucode/register.h:9157
#define P_VPU_BT656_MMC_CTRL 		VCBUS_REG_ADDR(VPU_BT656_MMC_CTRL)
#define VPU_TVD3D_MMC_CTRL 0x2710 	///../ucode/register.h:9158
#define P_VPU_TVD3D_MMC_CTRL 		VCBUS_REG_ADDR(VPU_TVD3D_MMC_CTRL)
#define VPU_TVDVBI_MMC_CTRL 0x2711 	///../ucode/register.h:9159
#define P_VPU_TVDVBI_MMC_CTRL 		VCBUS_REG_ADDR(VPU_TVDVBI_MMC_CTRL)
#define VPU_TVDVBI_VSLATCH_ADDR 0x2712 	///../ucode/register.h:9161
#define P_VPU_TVDVBI_VSLATCH_ADDR 		VCBUS_REG_ADDR(VPU_TVDVBI_VSLATCH_ADDR)
#define VPU_TVDVBI_WRRSP_ADDR 0x2713 	///../ucode/register.h:9163
#define P_VPU_TVDVBI_WRRSP_ADDR 		VCBUS_REG_ADDR(VPU_TVDVBI_WRRSP_ADDR)
#define VPU_VDIN_PRE_ARB_CTRL 0x2714 	///../ucode/register.h:9164
#define P_VPU_VDIN_PRE_ARB_CTRL 		VCBUS_REG_ADDR(VPU_VDIN_PRE_ARB_CTRL)
#define VPU_VDISP_PRE_ARB_CTRL 0x2715 	///../ucode/register.h:9165
#define P_VPU_VDISP_PRE_ARB_CTRL 		VCBUS_REG_ADDR(VPU_VDISP_PRE_ARB_CTRL)
#define VPU_VPUARB2_PRE_ARB_CTRL 0x2716 	///../ucode/register.h:9166
#define P_VPU_VPUARB2_PRE_ARB_CTRL 		VCBUS_REG_ADDR(VPU_VPUARB2_PRE_ARB_CTRL)
#define VPU_OSD3_MMC_CTRL 0x2717 	///../ucode/register.h:9167
#define P_VPU_OSD3_MMC_CTRL 		VCBUS_REG_ADDR(VPU_OSD3_MMC_CTRL)
#define VPU_OSD4_MMC_CTRL 0x2718 	///../ucode/register.h:9168
#define P_VPU_OSD4_MMC_CTRL 		VCBUS_REG_ADDR(VPU_OSD4_MMC_CTRL)
#define VPU_VD3_MMC_CTRL 0x2719 	///../ucode/register.h:9169
#define P_VPU_VD3_MMC_CTRL 		VCBUS_REG_ADDR(VPU_VD3_MMC_CTRL)
#define VPU_VIU_VENC_MUX_CTRL 0x271a 	///../ucode/register.h:9185
#define P_VPU_VIU_VENC_MUX_CTRL 		VCBUS_REG_ADDR(VPU_VIU_VENC_MUX_CTRL)
#define VPU_HDMI_SETTING 0x271b 	///../ucode/register.h:9200
#define P_VPU_HDMI_SETTING 		VCBUS_REG_ADDR(VPU_HDMI_SETTING)
#define ENCI_INFO_READ 0x271c 	///../ucode/register.h:9201
#define P_ENCI_INFO_READ 		VCBUS_REG_ADDR(ENCI_INFO_READ)
#define ENCP_INFO_READ 0x271d 	///../ucode/register.h:9202
#define P_ENCP_INFO_READ 		VCBUS_REG_ADDR(ENCP_INFO_READ)
#define ENCT_INFO_READ 0x271e 	///../ucode/register.h:9203
#define P_ENCT_INFO_READ 		VCBUS_REG_ADDR(ENCT_INFO_READ)
#define ENCL_INFO_READ 0x271f 	///../ucode/register.h:9204
#define P_ENCL_INFO_READ 		VCBUS_REG_ADDR(ENCL_INFO_READ)
#define VPU_SW_RESET 0x2720 	///../ucode/register.h:9209
#define P_VPU_SW_RESET 		VCBUS_REG_ADDR(VPU_SW_RESET)
#define VPU_D2D3_MMC_CTRL 0x2721 	///../ucode/register.h:9216
#define P_VPU_D2D3_MMC_CTRL 		VCBUS_REG_ADDR(VPU_D2D3_MMC_CTRL)
#define VPU_CONT_MMC_CTRL 0x2722 	///../ucode/register.h:9223
#define P_VPU_CONT_MMC_CTRL 		VCBUS_REG_ADDR(VPU_CONT_MMC_CTRL)
#define VPU_CLK_GATE 0x2723 	///../ucode/register.h:9231
#define P_VPU_CLK_GATE 		VCBUS_REG_ADDR(VPU_CLK_GATE)
#define VPU_RDMA_MMC_CTRL 0x2724 	///../ucode/register.h:9235
#define P_VPU_RDMA_MMC_CTRL 		VCBUS_REG_ADDR(VPU_RDMA_MMC_CTRL)
#define VPU_MEM_PD_REG0 0x2725 	///../ucode/register.h:9236
#define P_VPU_MEM_PD_REG0 		VCBUS_REG_ADDR(VPU_MEM_PD_REG0)
#define VPU_MEM_PD_REG1 0x2726 	///../ucode/register.h:9237
#define P_VPU_MEM_PD_REG1 		VCBUS_REG_ADDR(VPU_MEM_PD_REG1)
#define VPU_HDMI_DATA_OVR 0x2727 	///../ucode/register.h:9241
#define P_VPU_HDMI_DATA_OVR 		VCBUS_REG_ADDR(VPU_HDMI_DATA_OVR)
#define VPU_ARB4_V1_MMC_CTRL 0x272b 	///../ucode/register.h:9246
#define P_VPU_ARB4_V1_MMC_CTRL 		VCBUS_REG_ADDR(VPU_ARB4_V1_MMC_CTRL)
#define VPU_ARB4_V2_MMC_CTRL 0x272c 	///../ucode/register.h:9251
#define P_VPU_ARB4_V2_MMC_CTRL 		VCBUS_REG_ADDR(VPU_ARB4_V2_MMC_CTRL)
#define VPU_VPU_PWM_V0 0x2730 	///../ucode/register.h:9256
#define P_VPU_VPU_PWM_V0 		VCBUS_REG_ADDR(VPU_VPU_PWM_V0)
#define VPU_VPU_PWM_V1 0x2731 	///../ucode/register.h:9259
#define P_VPU_VPU_PWM_V1 		VCBUS_REG_ADDR(VPU_VPU_PWM_V1)
#define VPU_VPU_PWM_V2 0x2732 	///../ucode/register.h:9262
#define P_VPU_VPU_PWM_V2 		VCBUS_REG_ADDR(VPU_VPU_PWM_V2)
#define VPU_VPU_PWM_V3 0x2733 	///../ucode/register.h:9265
#define P_VPU_VPU_PWM_V3 		VCBUS_REG_ADDR(VPU_VPU_PWM_V3)
#define VPU_VPU_PWM_H0 0x2734 	///../ucode/register.h:9268
#define P_VPU_VPU_PWM_H0 		VCBUS_REG_ADDR(VPU_VPU_PWM_H0)
#define VPU_VPU_PWM_H1 0x2735 	///../ucode/register.h:9271
#define P_VPU_VPU_PWM_H1 		VCBUS_REG_ADDR(VPU_VPU_PWM_H1)
#define VPU_VPU_PWM_H2 0x2736 	///../ucode/register.h:9274
#define P_VPU_VPU_PWM_H2 		VCBUS_REG_ADDR(VPU_VPU_PWM_H2)
#define VPU_VPU_PWM_H3 0x2737 	///../ucode/register.h:9277
#define P_VPU_VPU_PWM_H3 		VCBUS_REG_ADDR(VPU_VPU_PWM_H3)
#define VPU_MISC_CTRL 0x2740 	///../ucode/register.h:9281
#define P_VPU_MISC_CTRL 		VCBUS_REG_ADDR(VPU_MISC_CTRL)
#define VPU_ISP_GCLK_CTRL0 0x2741 	///../ucode/register.h:9282
#define P_VPU_ISP_GCLK_CTRL0 		VCBUS_REG_ADDR(VPU_ISP_GCLK_CTRL0)
#define VPU_ISP_GCLK_CTRL1 0x2742 	///../ucode/register.h:9283
#define P_VPU_ISP_GCLK_CTRL1 		VCBUS_REG_ADDR(VPU_ISP_GCLK_CTRL1)
#define CSI2_CLK_RESET 0x2a00 	///../ucode/register.h:9304
#define P_CSI2_CLK_RESET 		VCBUS_REG_ADDR(CSI2_CLK_RESET)
#define CSI2_GEN_CTRL0 0x2a01 	///../ucode/register.h:9357
#define P_CSI2_GEN_CTRL0 		VCBUS_REG_ADDR(CSI2_GEN_CTRL0)
#define CSI2_FORCE_PIC_SIZE 0x2a02 	///../ucode/register.h:9364
#define P_CSI2_FORCE_PIC_SIZE 		VCBUS_REG_ADDR(CSI2_FORCE_PIC_SIZE)
#define CSI2_DDR_START_ADDR 0x2a03 	///../ucode/register.h:9366
#define P_CSI2_DDR_START_ADDR 		VCBUS_REG_ADDR(CSI2_DDR_START_ADDR)
#define CSI2_DDR_END_ADDR 0x2a04 	///../ucode/register.h:9368
#define P_CSI2_DDR_END_ADDR 		VCBUS_REG_ADDR(CSI2_DDR_END_ADDR)
#define CSI2_INTERRUPT_CTRL_STAT 0x2a05 	///../ucode/register.h:9379
#define P_CSI2_INTERRUPT_CTRL_STAT 		VCBUS_REG_ADDR(CSI2_INTERRUPT_CTRL_STAT)
#define CSI2_PIC_SIZE_STAT 0x2a06 	///../ucode/register.h:9382
#define P_CSI2_PIC_SIZE_STAT 		VCBUS_REG_ADDR(CSI2_PIC_SIZE_STAT)
#define CSI2_GEN_STAT0 0x2a07 	///../ucode/register.h:9391
#define P_CSI2_GEN_STAT0 		VCBUS_REG_ADDR(CSI2_GEN_STAT0)
#define CSI2_DDR_WRPT_STAT 0x2a08 	///../ucode/register.h:9393
#define P_CSI2_DDR_WRPT_STAT 		VCBUS_REG_ADDR(CSI2_DDR_WRPT_STAT)
#define CSI2_FS_EMBED_DDR_START 0x2a09 	///../ucode/register.h:9395
#define P_CSI2_FS_EMBED_DDR_START 		VCBUS_REG_ADDR(CSI2_FS_EMBED_DDR_START)
#define CSI2_FS_EMBED_DDR_END 0x2a0a 	///../ucode/register.h:9397
#define P_CSI2_FS_EMBED_DDR_END 		VCBUS_REG_ADDR(CSI2_FS_EMBED_DDR_END)
#define CSI2_FE_EMBED_DDR_START 0x2a0b 	///../ucode/register.h:9399
#define P_CSI2_FE_EMBED_DDR_START 		VCBUS_REG_ADDR(CSI2_FE_EMBED_DDR_START)
#define CSI2_FE_EMBED_DDR_END 0x2a0c 	///../ucode/register.h:9401
#define P_CSI2_FE_EMBED_DDR_END 		VCBUS_REG_ADDR(CSI2_FE_EMBED_DDR_END)
#define CSI2_MEM_PIXEL_BYTE_CNT 0x2a0d 	///../ucode/register.h:9407
#define P_CSI2_MEM_PIXEL_BYTE_CNT 		VCBUS_REG_ADDR(CSI2_MEM_PIXEL_BYTE_CNT)
#define CSI2_MEM_PIXEL_LINE_CNT 0x2a0e 	///../ucode/register.h:9410
#define P_CSI2_MEM_PIXEL_LINE_CNT 		VCBUS_REG_ADDR(CSI2_MEM_PIXEL_LINE_CNT)
#define CSI2_PIXEL_DDR_START 0x2a0f 	///../ucode/register.h:9412
#define P_CSI2_PIXEL_DDR_START 		VCBUS_REG_ADDR(CSI2_PIXEL_DDR_START)
#define CSI2_PIXEL_DDR_END 0x2a10 	///../ucode/register.h:9414
#define P_CSI2_PIXEL_DDR_END 		VCBUS_REG_ADDR(CSI2_PIXEL_DDR_END)
#define CSI2_USER_DDR_START 0x2a11 	///../ucode/register.h:9416
#define P_CSI2_USER_DDR_START 		VCBUS_REG_ADDR(CSI2_USER_DDR_START)
#define CSI2_USER_DDR_END 0x2a12 	///../ucode/register.h:9418
#define P_CSI2_USER_DDR_END 		VCBUS_REG_ADDR(CSI2_USER_DDR_END)
#define CSI2_DATA_TYPE_IN_MEM 0x2a13 	///../ucode/register.h:9429
#define P_CSI2_DATA_TYPE_IN_MEM 		VCBUS_REG_ADDR(CSI2_DATA_TYPE_IN_MEM)
#define CSI2_ERR_STAT0 0x2a14 	///../ucode/register.h:9448
#define P_CSI2_ERR_STAT0 		VCBUS_REG_ADDR(CSI2_ERR_STAT0)
#define CSI2_GEN_CTRL1 0x2a15 	///../ucode/register.h:9470
#define P_CSI2_GEN_CTRL1 		VCBUS_REG_ADDR(CSI2_GEN_CTRL1)
#define D2D3_GLB_CTRL 0x2b00 	///../ucode/register.h:9513
#define P_D2D3_GLB_CTRL 		VCBUS_REG_ADDR(D2D3_GLB_CTRL)
#define D2D3_DPG_INPIC_SIZE 0x2b01 	///../ucode/register.h:9517
#define P_D2D3_DPG_INPIC_SIZE 		VCBUS_REG_ADDR(D2D3_DPG_INPIC_SIZE)
#define D2D3_DBR_OUTPIC_SIZE 0x2b02 	///../ucode/register.h:9521
#define P_D2D3_DBR_OUTPIC_SIZE 		VCBUS_REG_ADDR(D2D3_DBR_OUTPIC_SIZE)
#define D2D3_DGEN_WIN_HOR 0x2b03 	///../ucode/register.h:9525
#define P_D2D3_DGEN_WIN_HOR 		VCBUS_REG_ADDR(D2D3_DGEN_WIN_HOR)
#define D2D3_DGEN_WIN_VER 0x2b04 	///../ucode/register.h:9529
#define P_D2D3_DGEN_WIN_VER 		VCBUS_REG_ADDR(D2D3_DGEN_WIN_VER)
#define D2D3_PRE_SCD_H 0x2b05 	///../ucode/register.h:9540
#define P_D2D3_PRE_SCD_H 		VCBUS_REG_ADDR(D2D3_PRE_SCD_H)
#define D2D3_SCALER_CTRL 0x2b06 	///../ucode/register.h:9558
#define P_D2D3_SCALER_CTRL 		VCBUS_REG_ADDR(D2D3_SCALER_CTRL)
#define D2D3_CG_THRESHOLD_1 0x2b07 	///../ucode/register.h:9563
#define P_D2D3_CG_THRESHOLD_1 		VCBUS_REG_ADDR(D2D3_CG_THRESHOLD_1)
#define D2D3_CG_THRESHOLD_2 0x2b08 	///../ucode/register.h:9568
#define P_D2D3_CG_THRESHOLD_2 		VCBUS_REG_ADDR(D2D3_CG_THRESHOLD_2)
#define D2D3_CG_PARAM_1 0x2b09 	///../ucode/register.h:9573
#define P_D2D3_CG_PARAM_1 		VCBUS_REG_ADDR(D2D3_CG_PARAM_1)
#define D2D3_CG_PARAM_2 0x2b0a 	///../ucode/register.h:9584
#define P_D2D3_CG_PARAM_2 		VCBUS_REG_ADDR(D2D3_CG_PARAM_2)
#define D2D3_PRE_SCD_V 0x2b0b 	///../ucode/register.h:9588
#define P_D2D3_PRE_SCD_V 		VCBUS_REG_ADDR(D2D3_PRE_SCD_V)
#define D2D3_D2P_PARAM_1 0x2b0c 	///../ucode/register.h:9611
#define P_D2D3_D2P_PARAM_1 		VCBUS_REG_ADDR(D2D3_D2P_PARAM_1)
#define D2D3_D2P_PARAM_2 0x2b0d 	///../ucode/register.h:9616
#define P_D2D3_D2P_PARAM_2 		VCBUS_REG_ADDR(D2D3_D2P_PARAM_2)
#define D2D3_D2P_PARAM_3 0x2b0e 	///../ucode/register.h:9621
#define P_D2D3_D2P_PARAM_3 		VCBUS_REG_ADDR(D2D3_D2P_PARAM_3)
#define D2D3_SCU18_STEP 0x2b0f 	///../ucode/register.h:9627
#define P_D2D3_SCU18_STEP 		VCBUS_REG_ADDR(D2D3_SCU18_STEP)
#define D2D3_DPF_LPF_CTRL 0x2b10 	///../ucode/register.h:9648
#define P_D2D3_DPF_LPF_CTRL 		VCBUS_REG_ADDR(D2D3_DPF_LPF_CTRL)
#define D2D3_DBLD_CG_PARAM 0x2b11 	///../ucode/register.h:9657
#define P_D2D3_DBLD_CG_PARAM 		VCBUS_REG_ADDR(D2D3_DBLD_CG_PARAM)
#define D2D3_DBLD_MG_PARAM 0x2b12 	///../ucode/register.h:9662
#define P_D2D3_DBLD_MG_PARAM 		VCBUS_REG_ADDR(D2D3_DBLD_MG_PARAM)
#define D2D3_DBLD_LG_PARAM 0x2b13 	///../ucode/register.h:9667
#define P_D2D3_DBLD_LG_PARAM 		VCBUS_REG_ADDR(D2D3_DBLD_LG_PARAM)
#define D2D3_DBLD_LPF_HCOEFF 0x2b14 	///../ucode/register.h:9672
#define P_D2D3_DBLD_LPF_HCOEFF 		VCBUS_REG_ADDR(D2D3_DBLD_LPF_HCOEFF)
#define D2D3_DBLD_LPF_VCOEFF 0x2b15 	///../ucode/register.h:9677
#define P_D2D3_DBLD_LPF_VCOEFF 		VCBUS_REG_ADDR(D2D3_DBLD_LPF_VCOEFF)
#define D2D3_DBLD_PATH_CTRL 0x2b16 	///../ucode/register.h:9696
#define P_D2D3_DBLD_PATH_CTRL 		VCBUS_REG_ADDR(D2D3_DBLD_PATH_CTRL)
#define D2D3_SCU18_INPIC_SIZE 0x2b17 	///../ucode/register.h:9700
#define P_D2D3_SCU18_INPIC_SIZE 		VCBUS_REG_ADDR(D2D3_SCU18_INPIC_SIZE)
#define D2D3_MBDG_CTRL 0x2b18 	///../ucode/register.h:9713
#define P_D2D3_MBDG_CTRL 		VCBUS_REG_ADDR(D2D3_MBDG_CTRL)
#define D2D3_MBDG_PARAM_0 0x2b19 	///../ucode/register.h:9719
#define P_D2D3_MBDG_PARAM_0 		VCBUS_REG_ADDR(D2D3_MBDG_PARAM_0)
#define D2D3_MBDG_PARAM_1 0x2b1a 	///../ucode/register.h:9725
#define P_D2D3_MBDG_PARAM_1 		VCBUS_REG_ADDR(D2D3_MBDG_PARAM_1)
#define D2D3_MBDG_PARAM_2 0x2b1b 	///../ucode/register.h:9730
#define P_D2D3_MBDG_PARAM_2 		VCBUS_REG_ADDR(D2D3_MBDG_PARAM_2)
#define D2D3_MBDG_PARAM_3 0x2b1c 	///../ucode/register.h:9735
#define P_D2D3_MBDG_PARAM_3 		VCBUS_REG_ADDR(D2D3_MBDG_PARAM_3)
#define D2D3_MBDG_PARAM_4 0x2b1d 	///../ucode/register.h:9744
#define P_D2D3_MBDG_PARAM_4 		VCBUS_REG_ADDR(D2D3_MBDG_PARAM_4)
#define D2D3_MBDG_PARAM_5 0x2b1e 	///../ucode/register.h:9749
#define P_D2D3_MBDG_PARAM_5 		VCBUS_REG_ADDR(D2D3_MBDG_PARAM_5)
#define D2D3_MBDG_PARAM_6 0x2b1f 	///../ucode/register.h:9754
#define P_D2D3_MBDG_PARAM_6 		VCBUS_REG_ADDR(D2D3_MBDG_PARAM_6)
#define D2D3_MBDG_PARAM_7 0x2b20 	///../ucode/register.h:9758
#define P_D2D3_MBDG_PARAM_7 		VCBUS_REG_ADDR(D2D3_MBDG_PARAM_7)
#define D2D3_DBG_CTRL 0x2b23 	///../ucode/register.h:9775
#define P_D2D3_DBG_CTRL 		VCBUS_REG_ADDR(D2D3_DBG_CTRL)
#define D2D3_DWMIF_CTRL 0x2b24 	///../ucode/register.h:9792
#define P_D2D3_DWMIF_CTRL 		VCBUS_REG_ADDR(D2D3_DWMIF_CTRL)
#define D2D3_DWMIF_HPOS 0x2b25 	///../ucode/register.h:9797
#define P_D2D3_DWMIF_HPOS 		VCBUS_REG_ADDR(D2D3_DWMIF_HPOS)
#define D2D3_DWMIF_VPOS 0x2b26 	///../ucode/register.h:9802
#define P_D2D3_DWMIF_VPOS 		VCBUS_REG_ADDR(D2D3_DWMIF_VPOS)
#define D2D3_DWMIF_SIZE 0x2b27 	///../ucode/register.h:9807
#define P_D2D3_DWMIF_SIZE 		VCBUS_REG_ADDR(D2D3_DWMIF_SIZE)
#define D2D3_DRMIF_CTRL 0x2b28 	///../ucode/register.h:9824
#define P_D2D3_DRMIF_CTRL 		VCBUS_REG_ADDR(D2D3_DRMIF_CTRL)
#define D2D3_DRMIF_HPOS 0x2b29 	///../ucode/register.h:9829
#define P_D2D3_DRMIF_HPOS 		VCBUS_REG_ADDR(D2D3_DRMIF_HPOS)
#define D2D3_DRMIF_VPOS 0x2b2a 	///../ucode/register.h:9834
#define P_D2D3_DRMIF_VPOS 		VCBUS_REG_ADDR(D2D3_DRMIF_VPOS)
#define D2D3_DBR_DDD_CTRL 0x2b2c 	///../ucode/register.h:9851
#define P_D2D3_DBR_DDD_CTRL 		VCBUS_REG_ADDR(D2D3_DBR_DDD_CTRL)
#define D2D3_DBR_DDD_DBG 0x2b2d 	///../ucode/register.h:9853
#define P_D2D3_DBR_DDD_DBG 		VCBUS_REG_ADDR(D2D3_DBR_DDD_DBG)
#define D2D3_DBR_LRDMX_CTRL 0x2b2f 	///../ucode/register.h:9867
#define P_D2D3_DBR_LRDMX_CTRL 		VCBUS_REG_ADDR(D2D3_DBR_LRDMX_CTRL)
#define D2D3_CBDG_STATUS_1 0x2b30 	///../ucode/register.h:9874
#define P_D2D3_CBDG_STATUS_1 		VCBUS_REG_ADDR(D2D3_CBDG_STATUS_1)
#define D2D3_MBDG_STATUS_1 0x2b31 	///../ucode/register.h:9879
#define P_D2D3_MBDG_STATUS_1 		VCBUS_REG_ADDR(D2D3_MBDG_STATUS_1)
#define D2D3_MBDG_STATUS_2 0x2b32 	///../ucode/register.h:9884
#define P_D2D3_MBDG_STATUS_2 		VCBUS_REG_ADDR(D2D3_MBDG_STATUS_2)
#define D2D3_MBDG_STATUS_3 0x2b33 	///../ucode/register.h:9889
#define P_D2D3_MBDG_STATUS_3 		VCBUS_REG_ADDR(D2D3_MBDG_STATUS_3)
#define D2D3_MBDG_STATUS_4 0x2b34 	///../ucode/register.h:9892
#define P_D2D3_MBDG_STATUS_4 		VCBUS_REG_ADDR(D2D3_MBDG_STATUS_4)
#define D2D3_MBDG_STATUS_5 0x2b35 	///../ucode/register.h:9895
#define P_D2D3_MBDG_STATUS_5 		VCBUS_REG_ADDR(D2D3_MBDG_STATUS_5)
#define D2D3_MBDG_STATUS_6 0x2b36 	///../ucode/register.h:9898
#define P_D2D3_MBDG_STATUS_6 		VCBUS_REG_ADDR(D2D3_MBDG_STATUS_6)
#define D2D3_MBDG_STATUS_7 0x2b37 	///../ucode/register.h:9901
#define P_D2D3_MBDG_STATUS_7 		VCBUS_REG_ADDR(D2D3_MBDG_STATUS_7)
#define D2D3_DBG_STATUS_1 0x2b38 	///../ucode/register.h:9903
#define P_D2D3_DBG_STATUS_1 		VCBUS_REG_ADDR(D2D3_DBG_STATUS_1)
#define D2D3_DBG_STATUS_2 0x2b39 	///../ucode/register.h:9909
#define P_D2D3_DBG_STATUS_2 		VCBUS_REG_ADDR(D2D3_DBG_STATUS_2)
#define D2D3_DRMIF_STATUS 0x2b3a 	///../ucode/register.h:9911
#define P_D2D3_DRMIF_STATUS 		VCBUS_REG_ADDR(D2D3_DRMIF_STATUS)
#define D2D3_DWMIF_STATUS 0x2b3b 	///../ucode/register.h:9915
#define P_D2D3_DWMIF_STATUS 		VCBUS_REG_ADDR(D2D3_DWMIF_STATUS)
#define D2D3_CBDG_STATUS_2 0x2b3c 	///../ucode/register.h:9918
#define P_D2D3_CBDG_STATUS_2 		VCBUS_REG_ADDR(D2D3_CBDG_STATUS_2)
#define D2D3_DBLD_STATUS 0x2b3d 	///../ucode/register.h:9921
#define P_D2D3_DBLD_STATUS 		VCBUS_REG_ADDR(D2D3_DBLD_STATUS)
#define D2D3_RESEV_STATUS1 0x2b3e 	///../ucode/register.h:9923
#define P_D2D3_RESEV_STATUS1 		VCBUS_REG_ADDR(D2D3_RESEV_STATUS1)
#define D2D3_RESEV_STATUS2 0x2b3f 	///../ucode/register.h:9925
#define P_D2D3_RESEV_STATUS2 		VCBUS_REG_ADDR(D2D3_RESEV_STATUS2)
#define MIPI_DSI_DWC_VERSION_OS 0x2c00 	///../ucode/register.h:9947
#define P_MIPI_DSI_DWC_VERSION_OS 		VCBUS_REG_ADDR(MIPI_DSI_DWC_VERSION_OS)
#define MIPI_DSI_DWC_PWR_UP_OS 0x2c01 	///../ucode/register.h:9948
#define P_MIPI_DSI_DWC_PWR_UP_OS 		VCBUS_REG_ADDR(MIPI_DSI_DWC_PWR_UP_OS)
#define MIPI_DSI_DWC_CLKMGR_CFG_OS 0x2c02 	///../ucode/register.h:9949
#define P_MIPI_DSI_DWC_CLKMGR_CFG_OS 		VCBUS_REG_ADDR(MIPI_DSI_DWC_CLKMGR_CFG_OS)
#define MIPI_DSI_DWC_DPI_VCID_OS 0x2c03 	///../ucode/register.h:9950
#define P_MIPI_DSI_DWC_DPI_VCID_OS 		VCBUS_REG_ADDR(MIPI_DSI_DWC_DPI_VCID_OS)
#define MIPI_DSI_DWC_DPI_COLOR_CODING_OS 0x2c04 	///../ucode/register.h:9951
#define P_MIPI_DSI_DWC_DPI_COLOR_CODING_OS 		VCBUS_REG_ADDR(MIPI_DSI_DWC_DPI_COLOR_CODING_OS)
#define MIPI_DSI_DWC_DPI_CFG_POL_OS 0x2c05 	///../ucode/register.h:9952
#define P_MIPI_DSI_DWC_DPI_CFG_POL_OS 		VCBUS_REG_ADDR(MIPI_DSI_DWC_DPI_CFG_POL_OS)
#define MIPI_DSI_DWC_DPI_LP_CMD_TIM_OS 0x2c06 	///../ucode/register.h:9953
#define P_MIPI_DSI_DWC_DPI_LP_CMD_TIM_OS 		VCBUS_REG_ADDR(MIPI_DSI_DWC_DPI_LP_CMD_TIM_OS)
#define MIPI_DSI_DWC_PCKHDL_CFG_OS 0x2c0b 	///../ucode/register.h:9954
#define P_MIPI_DSI_DWC_PCKHDL_CFG_OS 		VCBUS_REG_ADDR(MIPI_DSI_DWC_PCKHDL_CFG_OS)
#define MIPI_DSI_DWC_GEN_VCID_OS 0x2c0c 	///../ucode/register.h:9955
#define P_MIPI_DSI_DWC_GEN_VCID_OS 		VCBUS_REG_ADDR(MIPI_DSI_DWC_GEN_VCID_OS)
#define MIPI_DSI_DWC_MODE_CFG_OS 0x2c0d 	///../ucode/register.h:9956
#define P_MIPI_DSI_DWC_MODE_CFG_OS 		VCBUS_REG_ADDR(MIPI_DSI_DWC_MODE_CFG_OS)
#define MIPI_DSI_DWC_VID_MODE_CFG_OS 0x2c0e 	///../ucode/register.h:9957
#define P_MIPI_DSI_DWC_VID_MODE_CFG_OS 		VCBUS_REG_ADDR(MIPI_DSI_DWC_VID_MODE_CFG_OS)
#define MIPI_DSI_DWC_VID_PKT_SIZE_OS 0x2c0f 	///../ucode/register.h:9958
#define P_MIPI_DSI_DWC_VID_PKT_SIZE_OS 		VCBUS_REG_ADDR(MIPI_DSI_DWC_VID_PKT_SIZE_OS)
#define MIPI_DSI_DWC_VID_NUM_CHUNKS_OS 0x2c10 	///../ucode/register.h:9959
#define P_MIPI_DSI_DWC_VID_NUM_CHUNKS_OS 		VCBUS_REG_ADDR(MIPI_DSI_DWC_VID_NUM_CHUNKS_OS)
#define MIPI_DSI_DWC_VID_NULL_SIZE_OS 0x2c11 	///../ucode/register.h:9960
#define P_MIPI_DSI_DWC_VID_NULL_SIZE_OS 		VCBUS_REG_ADDR(MIPI_DSI_DWC_VID_NULL_SIZE_OS)
#define MIPI_DSI_DWC_VID_HSA_TIME_OS 0x2c12 	///../ucode/register.h:9961
#define P_MIPI_DSI_DWC_VID_HSA_TIME_OS 		VCBUS_REG_ADDR(MIPI_DSI_DWC_VID_HSA_TIME_OS)
#define MIPI_DSI_DWC_VID_HBP_TIME_OS 0x2c13 	///../ucode/register.h:9962
#define P_MIPI_DSI_DWC_VID_HBP_TIME_OS 		VCBUS_REG_ADDR(MIPI_DSI_DWC_VID_HBP_TIME_OS)
#define MIPI_DSI_DWC_VID_HLINE_TIME_OS 0x2c14 	///../ucode/register.h:9963
#define P_MIPI_DSI_DWC_VID_HLINE_TIME_OS 		VCBUS_REG_ADDR(MIPI_DSI_DWC_VID_HLINE_TIME_OS)
#define MIPI_DSI_DWC_VID_VSA_LINES_OS 0x2c15 	///../ucode/register.h:9964
#define P_MIPI_DSI_DWC_VID_VSA_LINES_OS 		VCBUS_REG_ADDR(MIPI_DSI_DWC_VID_VSA_LINES_OS)
#define MIPI_DSI_DWC_VID_VBP_LINES_OS 0x2c16 	///../ucode/register.h:9965
#define P_MIPI_DSI_DWC_VID_VBP_LINES_OS 		VCBUS_REG_ADDR(MIPI_DSI_DWC_VID_VBP_LINES_OS)
#define MIPI_DSI_DWC_VID_VFP_LINES_OS 0x2c17 	///../ucode/register.h:9966
#define P_MIPI_DSI_DWC_VID_VFP_LINES_OS 		VCBUS_REG_ADDR(MIPI_DSI_DWC_VID_VFP_LINES_OS)
#define MIPI_DSI_DWC_VID_VACTIVE_LINES_OS 0x2c18 	///../ucode/register.h:9967
#define P_MIPI_DSI_DWC_VID_VACTIVE_LINES_OS 		VCBUS_REG_ADDR(MIPI_DSI_DWC_VID_VACTIVE_LINES_OS)
#define MIPI_DSI_DWC_EDPI_CMD_SIZE_OS 0x2c19 	///../ucode/register.h:9968
#define P_MIPI_DSI_DWC_EDPI_CMD_SIZE_OS 		VCBUS_REG_ADDR(MIPI_DSI_DWC_EDPI_CMD_SIZE_OS)
#define MIPI_DSI_DWC_CMD_MODE_CFG_OS 0x2c1a 	///../ucode/register.h:9969
#define P_MIPI_DSI_DWC_CMD_MODE_CFG_OS 		VCBUS_REG_ADDR(MIPI_DSI_DWC_CMD_MODE_CFG_OS)
#define MIPI_DSI_DWC_GEN_HDR_OS 0x2c1b 	///../ucode/register.h:9970
#define P_MIPI_DSI_DWC_GEN_HDR_OS 		VCBUS_REG_ADDR(MIPI_DSI_DWC_GEN_HDR_OS)
#define MIPI_DSI_DWC_GEN_PLD_DATA_OS 0x2c1c 	///../ucode/register.h:9971
#define P_MIPI_DSI_DWC_GEN_PLD_DATA_OS 		VCBUS_REG_ADDR(MIPI_DSI_DWC_GEN_PLD_DATA_OS)
#define MIPI_DSI_DWC_CMD_PKT_STATUS_OS 0x2c1d 	///../ucode/register.h:9972
#define P_MIPI_DSI_DWC_CMD_PKT_STATUS_OS 		VCBUS_REG_ADDR(MIPI_DSI_DWC_CMD_PKT_STATUS_OS)
#define MIPI_DSI_DWC_TO_CNT_CFG_OS 0x2c1e 	///../ucode/register.h:9973
#define P_MIPI_DSI_DWC_TO_CNT_CFG_OS 		VCBUS_REG_ADDR(MIPI_DSI_DWC_TO_CNT_CFG_OS)
#define MIPI_DSI_DWC_HS_RD_TO_CNT_OS 0x2c1f 	///../ucode/register.h:9974
#define P_MIPI_DSI_DWC_HS_RD_TO_CNT_OS 		VCBUS_REG_ADDR(MIPI_DSI_DWC_HS_RD_TO_CNT_OS)
#define MIPI_DSI_DWC_LP_RD_TO_CNT_OS 0x2c20 	///../ucode/register.h:9975
#define P_MIPI_DSI_DWC_LP_RD_TO_CNT_OS 		VCBUS_REG_ADDR(MIPI_DSI_DWC_LP_RD_TO_CNT_OS)
#define MIPI_DSI_DWC_HS_WR_TO_CNT_OS 0x2c21 	///../ucode/register.h:9976
#define P_MIPI_DSI_DWC_HS_WR_TO_CNT_OS 		VCBUS_REG_ADDR(MIPI_DSI_DWC_HS_WR_TO_CNT_OS)
#define MIPI_DSI_DWC_LP_WR_TO_CNT_OS 0x2c22 	///../ucode/register.h:9977
#define P_MIPI_DSI_DWC_LP_WR_TO_CNT_OS 		VCBUS_REG_ADDR(MIPI_DSI_DWC_LP_WR_TO_CNT_OS)
#define MIPI_DSI_DWC_BTA_TO_CNT_OS 0x2c23 	///../ucode/register.h:9978
#define P_MIPI_DSI_DWC_BTA_TO_CNT_OS 		VCBUS_REG_ADDR(MIPI_DSI_DWC_BTA_TO_CNT_OS)
#define MIPI_DSI_DWC_SDF_3D_OS 0x2c24 	///../ucode/register.h:9979
#define P_MIPI_DSI_DWC_SDF_3D_OS 		VCBUS_REG_ADDR(MIPI_DSI_DWC_SDF_3D_OS)
#define MIPI_DSI_DWC_LPCLK_CTRL_OS 0x2c25 	///../ucode/register.h:9980
#define P_MIPI_DSI_DWC_LPCLK_CTRL_OS 		VCBUS_REG_ADDR(MIPI_DSI_DWC_LPCLK_CTRL_OS)
#define MIPI_DSI_DWC_PHY_TMR_LPCLK_CFG_OS 0x2c26 	///../ucode/register.h:9981
#define P_MIPI_DSI_DWC_PHY_TMR_LPCLK_CFG_OS 		VCBUS_REG_ADDR(MIPI_DSI_DWC_PHY_TMR_LPCLK_CFG_OS)
#define MIPI_DSI_DWC_PHY_TMR_CFG_OS 0x2c27 	///../ucode/register.h:9982
#define P_MIPI_DSI_DWC_PHY_TMR_CFG_OS 		VCBUS_REG_ADDR(MIPI_DSI_DWC_PHY_TMR_CFG_OS)
#define MIPI_DSI_DWC_PHY_RSTZ_OS 0x2c28 	///../ucode/register.h:9983
#define P_MIPI_DSI_DWC_PHY_RSTZ_OS 		VCBUS_REG_ADDR(MIPI_DSI_DWC_PHY_RSTZ_OS)
#define MIPI_DSI_DWC_PHY_IF_CFG_OS 0x2c29 	///../ucode/register.h:9984
#define P_MIPI_DSI_DWC_PHY_IF_CFG_OS 		VCBUS_REG_ADDR(MIPI_DSI_DWC_PHY_IF_CFG_OS)
#define MIPI_DSI_DWC_PHY_ULPS_CTRL_OS 0x2c2a 	///../ucode/register.h:9985
#define P_MIPI_DSI_DWC_PHY_ULPS_CTRL_OS 		VCBUS_REG_ADDR(MIPI_DSI_DWC_PHY_ULPS_CTRL_OS)
#define MIPI_DSI_DWC_PHY_TX_TRIGGERS_OS 0x2c2b 	///../ucode/register.h:9986
#define P_MIPI_DSI_DWC_PHY_TX_TRIGGERS_OS 		VCBUS_REG_ADDR(MIPI_DSI_DWC_PHY_TX_TRIGGERS_OS)
#define MIPI_DSI_DWC_PHY_STATUS_OS 0x2c2c 	///../ucode/register.h:9987
#define P_MIPI_DSI_DWC_PHY_STATUS_OS 		VCBUS_REG_ADDR(MIPI_DSI_DWC_PHY_STATUS_OS)
#define MIPI_DSI_DWC_PHY_TST_CTRL0_OS 0x2c2d 	///../ucode/register.h:9988
#define P_MIPI_DSI_DWC_PHY_TST_CTRL0_OS 		VCBUS_REG_ADDR(MIPI_DSI_DWC_PHY_TST_CTRL0_OS)
#define MIPI_DSI_DWC_PHY_TST_CTRL1_OS 0x2c2e 	///../ucode/register.h:9989
#define P_MIPI_DSI_DWC_PHY_TST_CTRL1_OS 		VCBUS_REG_ADDR(MIPI_DSI_DWC_PHY_TST_CTRL1_OS)
#define MIPI_DSI_DWC_INT_ST0_OS 0x2c2f 	///../ucode/register.h:9990
#define P_MIPI_DSI_DWC_INT_ST0_OS 		VCBUS_REG_ADDR(MIPI_DSI_DWC_INT_ST0_OS)
#define MIPI_DSI_DWC_INT_ST1_OS 0x2c30 	///../ucode/register.h:9991
#define P_MIPI_DSI_DWC_INT_ST1_OS 		VCBUS_REG_ADDR(MIPI_DSI_DWC_INT_ST1_OS)
#define MIPI_DSI_DWC_INT_MSK0_OS 0x2c31 	///../ucode/register.h:9992
#define P_MIPI_DSI_DWC_INT_MSK0_OS 		VCBUS_REG_ADDR(MIPI_DSI_DWC_INT_MSK0_OS)
#define MIPI_DSI_DWC_INT_MSK1_OS 0x2c32 	///../ucode/register.h:9993
#define P_MIPI_DSI_DWC_INT_MSK1_OS 		VCBUS_REG_ADDR(MIPI_DSI_DWC_INT_MSK1_OS)
#define MIPI_DSI_TOP_SW_RESET 0x2cf0 	///../ucode/register.h:10002
#define P_MIPI_DSI_TOP_SW_RESET 		VCBUS_REG_ADDR(MIPI_DSI_TOP_SW_RESET)
#define MIPI_DSI_TOP_CLK_CNTL 0x2cf1 	///../ucode/register.h:10009
#define P_MIPI_DSI_TOP_CLK_CNTL 		VCBUS_REG_ADDR(MIPI_DSI_TOP_CLK_CNTL)
#define MIPI_DSI_TOP_CNTL 0x2cf2 	///../ucode/register.h:10049
#define P_MIPI_DSI_TOP_CNTL 		VCBUS_REG_ADDR(MIPI_DSI_TOP_CNTL)
#define MIPI_DSI_TOP_SUSPEND_CNTL 0x2cf3 	///../ucode/register.h:10057
#define P_MIPI_DSI_TOP_SUSPEND_CNTL 		VCBUS_REG_ADDR(MIPI_DSI_TOP_SUSPEND_CNTL)
#define MIPI_DSI_TOP_SUSPEND_LINE 0x2cf4 	///../ucode/register.h:10062
#define P_MIPI_DSI_TOP_SUSPEND_LINE 		VCBUS_REG_ADDR(MIPI_DSI_TOP_SUSPEND_LINE)
#define MIPI_DSI_TOP_SUSPEND_PIX 0x2cf5 	///../ucode/register.h:10067
#define P_MIPI_DSI_TOP_SUSPEND_PIX 		VCBUS_REG_ADDR(MIPI_DSI_TOP_SUSPEND_PIX)
#define MIPI_DSI_TOP_MEAS_CNTL 0x2cf6 	///../ucode/register.h:10079
#define P_MIPI_DSI_TOP_MEAS_CNTL 		VCBUS_REG_ADDR(MIPI_DSI_TOP_MEAS_CNTL)
#define MIPI_DSI_TOP_STAT 0x2cf7 	///../ucode/register.h:10085
#define P_MIPI_DSI_TOP_STAT 		VCBUS_REG_ADDR(MIPI_DSI_TOP_STAT)
#define MIPI_DSI_TOP_MEAS_STAT_TE0 0x2cf8 	///../ucode/register.h:10095
#define P_MIPI_DSI_TOP_MEAS_STAT_TE0 		VCBUS_REG_ADDR(MIPI_DSI_TOP_MEAS_STAT_TE0)
#define MIPI_DSI_TOP_MEAS_STAT_TE1 0x2cf9 	///../ucode/register.h:10098
#define P_MIPI_DSI_TOP_MEAS_STAT_TE1 		VCBUS_REG_ADDR(MIPI_DSI_TOP_MEAS_STAT_TE1)
#define MIPI_DSI_TOP_MEAS_STAT_VS0 0x2cfa 	///../ucode/register.h:10108
#define P_MIPI_DSI_TOP_MEAS_STAT_VS0 		VCBUS_REG_ADDR(MIPI_DSI_TOP_MEAS_STAT_VS0)
#define MIPI_DSI_TOP_MEAS_STAT_VS1 0x2cfb 	///../ucode/register.h:10111
#define P_MIPI_DSI_TOP_MEAS_STAT_VS1 		VCBUS_REG_ADDR(MIPI_DSI_TOP_MEAS_STAT_VS1)
#define MIPI_DSI_TOP_INTR_CNTL_STAT 0x2cfc 	///../ucode/register.h:10129
#define P_MIPI_DSI_TOP_INTR_CNTL_STAT 		VCBUS_REG_ADDR(MIPI_DSI_TOP_INTR_CNTL_STAT)
#define ISP_GAMMA_LUT_ADDR 0x2dc2 	///../ucode/register.h:10147
#define P_ISP_GAMMA_LUT_ADDR 		VCBUS_REG_ADDR(ISP_GAMMA_LUT_ADDR)
#define ISP_GAMMA_LUT_DATA 0x2dc3 	///../ucode/register.h:10148
#define P_ISP_GAMMA_LUT_DATA 		VCBUS_REG_ADDR(ISP_GAMMA_LUT_DATA)
#define ISP_DF1024_LUT_ADDR 0x2dc4 	///../ucode/register.h:10149
#define P_ISP_DF1024_LUT_ADDR 		VCBUS_REG_ADDR(ISP_DF1024_LUT_ADDR)
#define ISP_DF1024_LUT_DATA 0x2dc5 	///../ucode/register.h:10150
#define P_ISP_DF1024_LUT_DATA 		VCBUS_REG_ADDR(ISP_DF1024_LUT_DATA)
#define ISP_LNSD_LUT_ADDR 0x2dc6 	///../ucode/register.h:10151
#define P_ISP_LNSD_LUT_ADDR 		VCBUS_REG_ADDR(ISP_LNSD_LUT_ADDR)
#define ISP_LNSD_LUT_DATA 0x2dc7 	///../ucode/register.h:10152
#define P_ISP_LNSD_LUT_DATA 		VCBUS_REG_ADDR(ISP_LNSD_LUT_DATA)
#define ISP_HV_SIZE 0x2d00 	///../ucode/register.h:10153
#define P_ISP_HV_SIZE 		VCBUS_REG_ADDR(ISP_HV_SIZE)
#define ISP_HBLANK 0x2d01 	///../ucode/register.h:10158
#define P_ISP_HBLANK 		VCBUS_REG_ADDR(ISP_HBLANK)
#define ISP_TIMING_MODE 0x2d02 	///../ucode/register.h:10163
#define P_ISP_TIMING_MODE 		VCBUS_REG_ADDR(ISP_TIMING_MODE)
#define ISP_RST_DLY_NUM 0x2d03 	///../ucode/register.h:10177
#define P_ISP_RST_DLY_NUM 		VCBUS_REG_ADDR(ISP_RST_DLY_NUM)
#define ISP_OUTVS_DLY_NUM 0x2d04 	///../ucode/register.h:10179
#define P_ISP_OUTVS_DLY_NUM 		VCBUS_REG_ADDR(ISP_OUTVS_DLY_NUM)
#define ISP_DIN_WIND_OFST 0x2d05 	///../ucode/register.h:10181
#define P_ISP_DIN_WIND_OFST 		VCBUS_REG_ADDR(ISP_DIN_WIND_OFST)
#define ISP_FRM_SOFT_RST 0x2d06 	///../ucode/register.h:10186
#define P_ISP_FRM_SOFT_RST 		VCBUS_REG_ADDR(ISP_FRM_SOFT_RST)
#define ISP_RST_SYN_SEL 0x2d07 	///../ucode/register.h:10189
#define P_ISP_RST_SYN_SEL 		VCBUS_REG_ADDR(ISP_RST_SYN_SEL)
#define ISP_PAT_GEN_CTRL 0x2d08 	///../ucode/register.h:10197
#define P_ISP_PAT_GEN_CTRL 		VCBUS_REG_ADDR(ISP_PAT_GEN_CTRL)
#define ISP_PAT_XRAMP_SCAL 0x2d09 	///../ucode/register.h:10210
#define P_ISP_PAT_XRAMP_SCAL 		VCBUS_REG_ADDR(ISP_PAT_XRAMP_SCAL)
#define ISP_PAT_YRAMP_SCAL 0x2d0a 	///../ucode/register.h:10215
#define P_ISP_PAT_YRAMP_SCAL 		VCBUS_REG_ADDR(ISP_PAT_YRAMP_SCAL)
#define ISP_PAT_XYIDX_OFST 0x2d0b 	///../ucode/register.h:10220
#define P_ISP_PAT_XYIDX_OFST 		VCBUS_REG_ADDR(ISP_PAT_XYIDX_OFST)
#define ISP_PAT_XYIDX_SCAL 0x2d0c 	///../ucode/register.h:10225
#define P_ISP_PAT_XYIDX_SCAL 		VCBUS_REG_ADDR(ISP_PAT_XYIDX_SCAL)
#define ISP_PAT_BAR16_RED0 0x2d0d 	///../ucode/register.h:10232
#define P_ISP_PAT_BAR16_RED0 		VCBUS_REG_ADDR(ISP_PAT_BAR16_RED0)
#define ISP_PAT_BAR16_RED1 0x2d0e 	///../ucode/register.h:10237
#define P_ISP_PAT_BAR16_RED1 		VCBUS_REG_ADDR(ISP_PAT_BAR16_RED1)
#define ISP_PAT_BAR16_RED2 0x2d0f 	///../ucode/register.h:10242
#define P_ISP_PAT_BAR16_RED2 		VCBUS_REG_ADDR(ISP_PAT_BAR16_RED2)
#define ISP_PAT_BAR16_RED3 0x2d10 	///../ucode/register.h:10247
#define P_ISP_PAT_BAR16_RED3 		VCBUS_REG_ADDR(ISP_PAT_BAR16_RED3)
#define ISP_PAT_BAR16_GRN0 0x2d11 	///../ucode/register.h:10252
#define P_ISP_PAT_BAR16_GRN0 		VCBUS_REG_ADDR(ISP_PAT_BAR16_GRN0)
#define ISP_PAT_BAR16_GRN1 0x2d12 	///../ucode/register.h:10257
#define P_ISP_PAT_BAR16_GRN1 		VCBUS_REG_ADDR(ISP_PAT_BAR16_GRN1)
#define ISP_PAT_BAR16_GRN2 0x2d13 	///../ucode/register.h:10262
#define P_ISP_PAT_BAR16_GRN2 		VCBUS_REG_ADDR(ISP_PAT_BAR16_GRN2)
#define ISP_PAT_BAR16_GRN3 0x2d14 	///../ucode/register.h:10267
#define P_ISP_PAT_BAR16_GRN3 		VCBUS_REG_ADDR(ISP_PAT_BAR16_GRN3)
#define ISP_PAT_BAR16_BLU0 0x2d15 	///../ucode/register.h:10272
#define P_ISP_PAT_BAR16_BLU0 		VCBUS_REG_ADDR(ISP_PAT_BAR16_BLU0)
#define ISP_PAT_BAR16_BLU1 0x2d16 	///../ucode/register.h:10277
#define P_ISP_PAT_BAR16_BLU1 		VCBUS_REG_ADDR(ISP_PAT_BAR16_BLU1)
#define ISP_PAT_BAR16_BLU2 0x2d17 	///../ucode/register.h:10282
#define P_ISP_PAT_BAR16_BLU2 		VCBUS_REG_ADDR(ISP_PAT_BAR16_BLU2)
#define ISP_PAT_BAR16_BLU3 0x2d18 	///../ucode/register.h:10287
#define P_ISP_PAT_BAR16_BLU3 		VCBUS_REG_ADDR(ISP_PAT_BAR16_BLU3)
#define ISP_PAT_DFT_XYIDX 0x2d19 	///../ucode/register.h:10292
#define P_ISP_PAT_DFT_XYIDX 		VCBUS_REG_ADDR(ISP_PAT_DFT_XYIDX)
#define ISP_PAT_DFT_XYWID 0x2d1a 	///../ucode/register.h:10297
#define P_ISP_PAT_DFT_XYWID 		VCBUS_REG_ADDR(ISP_PAT_DFT_XYWID)
#define ISP_PAT_DFT_GAIN 0x2d1b 	///../ucode/register.h:10302
#define P_ISP_PAT_DFT_GAIN 		VCBUS_REG_ADDR(ISP_PAT_DFT_GAIN)
#define ISP_PAT_HVTOTAL 0x2d1c 	///../ucode/register.h:10311
#define P_ISP_PAT_HVTOTAL 		VCBUS_REG_ADDR(ISP_PAT_HVTOTAL)
#define ISP_PAT_VDE_SLINE 0x2d1d 	///../ucode/register.h:10314
#define P_ISP_PAT_VDE_SLINE 		VCBUS_REG_ADDR(ISP_PAT_VDE_SLINE)
#define ISP_OUTHS_PARA 0x2d1e 	///../ucode/register.h:10317
#define P_ISP_OUTHS_PARA 		VCBUS_REG_ADDR(ISP_OUTHS_PARA)
#define ISP_FRM_DONE_PARA 0x2d1f 	///../ucode/register.h:10321
#define P_ISP_FRM_DONE_PARA 		VCBUS_REG_ADDR(ISP_FRM_DONE_PARA)
#define ISP_CLAMPGAIN_CTRL 0x2d20 	///../ucode/register.h:10328
#define P_ISP_CLAMPGAIN_CTRL 		VCBUS_REG_ADDR(ISP_CLAMPGAIN_CTRL)
#define ISP_GAIN_BSCORE_GRBG 0x2d21 	///../ucode/register.h:10338
#define P_ISP_GAIN_BSCORE_GRBG 		VCBUS_REG_ADDR(ISP_GAIN_BSCORE_GRBG)
#define ISP_CLAMP_GRBG01 0x2d22 	///../ucode/register.h:10343
#define P_ISP_CLAMP_GRBG01 		VCBUS_REG_ADDR(ISP_CLAMP_GRBG01)
#define ISP_CLAMP_GRBG23 0x2d23 	///../ucode/register.h:10348
#define P_ISP_CLAMP_GRBG23 		VCBUS_REG_ADDR(ISP_CLAMP_GRBG23)
#define ISP_GAIN_GRBG01 0x2d24 	///../ucode/register.h:10353
#define P_ISP_GAIN_GRBG01 		VCBUS_REG_ADDR(ISP_GAIN_GRBG01)
#define ISP_GAIN_GRBG23 0x2d25 	///../ucode/register.h:10358
#define P_ISP_GAIN_GRBG23 		VCBUS_REG_ADDR(ISP_GAIN_GRBG23)
#define ISP_LNS_CTRL 0x2d28 	///../ucode/register.h:10367
#define P_ISP_LNS_CTRL 		VCBUS_REG_ADDR(ISP_LNS_CTRL)
#define ISP_LNS_XYSCAL 0x2d29 	///../ucode/register.h:10380
#define P_ISP_LNS_XYSCAL 		VCBUS_REG_ADDR(ISP_LNS_XYSCAL)
#define ISP_LNS_XYIDX_SHFT 0x2d2a 	///../ucode/register.h:10385
#define P_ISP_LNS_XYIDX_SHFT 		VCBUS_REG_ADDR(ISP_LNS_XYIDX_SHFT)
#define ISP_LNS_SENSOR_GAINGRBG 0x2d2b 	///../ucode/register.h:10390
#define P_ISP_LNS_SENSOR_GAINGRBG 		VCBUS_REG_ADDR(ISP_LNS_SENSOR_GAINGRBG)
#define ISP_LNS_POST_OFSTGRBG 0x2d2c 	///../ucode/register.h:10395
#define P_ISP_LNS_POST_OFSTGRBG 		VCBUS_REG_ADDR(ISP_LNS_POST_OFSTGRBG)
#define ISP_GMR0_CTRL 0x2d30 	///../ucode/register.h:10405
#define P_ISP_GMR0_CTRL 		VCBUS_REG_ADDR(ISP_GMR0_CTRL)
#define ISP_DFT_CTRL 0x2d31 	///../ucode/register.h:10417
#define P_ISP_DFT_CTRL 		VCBUS_REG_ADDR(ISP_DFT_CTRL)
#define ISP_DFT_VAR_MINMAX 0x2d33 	///../ucode/register.h:10433
#define P_ISP_DFT_VAR_MINMAX 		VCBUS_REG_ADDR(ISP_DFT_VAR_MINMAX)
#define ISP_DFT_THDLOW 0x2d34 	///../ucode/register.h:10438
#define P_ISP_DFT_THDLOW 		VCBUS_REG_ADDR(ISP_DFT_THDLOW)
#define ISP_DFT_THDHIG 0x2d35 	///../ucode/register.h:10443
#define P_ISP_DFT_THDHIG 		VCBUS_REG_ADDR(ISP_DFT_THDHIG)
#define ISP_DFT_CALIBRAT_REF 0x2d36 	///../ucode/register.h:10448
#define P_ISP_DFT_CALIBRAT_REF 		VCBUS_REG_ADDR(ISP_DFT_CALIBRAT_REF)
#define ISP_DFT_CALIBRAT_CTRL 0x2d37 	///../ucode/register.h:10453
#define P_ISP_DFT_CALIBRAT_CTRL 		VCBUS_REG_ADDR(ISP_DFT_CALIBRAT_CTRL)
#define ISP_DFT_DET0_MANUALTH 0x2d38 	///../ucode/register.h:10465
#define P_ISP_DFT_DET0_MANUALTH 		VCBUS_REG_ADDR(ISP_DFT_DET0_MANUALTH)
#define ISP_DFT_DET1_ADPTLOWTH 0x2d39 	///../ucode/register.h:10470
#define P_ISP_DFT_DET1_ADPTLOWTH 		VCBUS_REG_ADDR(ISP_DFT_DET1_ADPTLOWTH)
#define ISP_DFT_DET1_ADPTHIGTH 0x2d3a 	///../ucode/register.h:10475
#define P_ISP_DFT_DET1_ADPTHIGTH 		VCBUS_REG_ADDR(ISP_DFT_DET1_ADPTHIGTH)
#define ISP_DFT_DET1_ADPTNUM0 0x2d3b 	///../ucode/register.h:10480
#define P_ISP_DFT_DET1_ADPTNUM0 		VCBUS_REG_ADDR(ISP_DFT_DET1_ADPTNUM0)
#define ISP_DFT_DET1_ADPTNUM1 0x2d3c 	///../ucode/register.h:10487
#define P_ISP_DFT_DET1_ADPTNUM1 		VCBUS_REG_ADDR(ISP_DFT_DET1_ADPTNUM1)
#define ISP_DMS_CTRL0 0x2d40 	///../ucode/register.h:10498
#define P_ISP_DMS_CTRL0 		VCBUS_REG_ADDR(ISP_DMS_CTRL0)
#define ISP_DMS_CTRL1 0x2d41 	///../ucode/register.h:10510
#define P_ISP_DMS_CTRL1 		VCBUS_REG_ADDR(ISP_DMS_CTRL1)
#define ISP_MATRIX_PRE_OFST0_1 0x2d42 	///../ucode/register.h:10524
#define P_ISP_MATRIX_PRE_OFST0_1 		VCBUS_REG_ADDR(ISP_MATRIX_PRE_OFST0_1)
#define ISP_MATRIX_PRE_OFST2 0x2d43 	///../ucode/register.h:10529
#define P_ISP_MATRIX_PRE_OFST2 		VCBUS_REG_ADDR(ISP_MATRIX_PRE_OFST2)
#define ISP_MATRIX_COEF00_01 0x2d44 	///../ucode/register.h:10534
#define P_ISP_MATRIX_COEF00_01 		VCBUS_REG_ADDR(ISP_MATRIX_COEF00_01)
#define ISP_MATRIX_COEF02_10 0x2d45 	///../ucode/register.h:10539
#define P_ISP_MATRIX_COEF02_10 		VCBUS_REG_ADDR(ISP_MATRIX_COEF02_10)
#define ISP_MATRIX_COEF11_12 0x2d46 	///../ucode/register.h:10544
#define P_ISP_MATRIX_COEF11_12 		VCBUS_REG_ADDR(ISP_MATRIX_COEF11_12)
#define ISP_MATRIX_COEF20_21 0x2d47 	///../ucode/register.h:10549
#define P_ISP_MATRIX_COEF20_21 		VCBUS_REG_ADDR(ISP_MATRIX_COEF20_21)
#define ISP_MATRIX_COEF22 0x2d48 	///../ucode/register.h:10554
#define P_ISP_MATRIX_COEF22 		VCBUS_REG_ADDR(ISP_MATRIX_COEF22)
#define ISP_MATRIX_POS_OFST0_1 0x2d49 	///../ucode/register.h:10557
#define P_ISP_MATRIX_POS_OFST0_1 		VCBUS_REG_ADDR(ISP_MATRIX_POS_OFST0_1)
#define ISP_MATRIX_POS_OFST2 0x2d4a 	///../ucode/register.h:10562
#define P_ISP_MATRIX_POS_OFST2 		VCBUS_REG_ADDR(ISP_MATRIX_POS_OFST2)
#define ISP_PKNR_HVBLANK_NUM 0x2d50 	///../ucode/register.h:10569
#define P_ISP_PKNR_HVBLANK_NUM 		VCBUS_REG_ADDR(ISP_PKNR_HVBLANK_NUM)
#define ISP_NR_GAUSSIAN_MODE 0x2d51 	///../ucode/register.h:10574
#define P_ISP_NR_GAUSSIAN_MODE 		VCBUS_REG_ADDR(ISP_NR_GAUSSIAN_MODE)
#define ISP_PK_HVCON_LPF_MODE 0x2d52 	///../ucode/register.h:10579
#define P_ISP_PK_HVCON_LPF_MODE 		VCBUS_REG_ADDR(ISP_PK_HVCON_LPF_MODE)
#define ISP_PK_CON_BLEND_GAIN 0x2d53 	///../ucode/register.h:10596
#define P_ISP_PK_CON_BLEND_GAIN 		VCBUS_REG_ADDR(ISP_PK_CON_BLEND_GAIN)
#define ISP_PK_CON_2CIRHPGAIN_TH_RATE 0x2d54 	///../ucode/register.h:10605
#define P_ISP_PK_CON_2CIRHPGAIN_TH_RATE 		VCBUS_REG_ADDR(ISP_PK_CON_2CIRHPGAIN_TH_RATE)
#define ISP_PK_CON_2CIRHPGAIN_LIMIT 0x2d55 	///../ucode/register.h:10611
#define P_ISP_PK_CON_2CIRHPGAIN_LIMIT 		VCBUS_REG_ADDR(ISP_PK_CON_2CIRHPGAIN_LIMIT)
#define ISP_PK_CON_2CIRBPGAIN_TH_RATE 0x2d56 	///../ucode/register.h:10617
#define P_ISP_PK_CON_2CIRBPGAIN_TH_RATE 		VCBUS_REG_ADDR(ISP_PK_CON_2CIRBPGAIN_TH_RATE)
#define ISP_PK_CON_2CIRBPGAIN_LIMIT 0x2d57 	///../ucode/register.h:10623
#define P_ISP_PK_CON_2CIRBPGAIN_LIMIT 		VCBUS_REG_ADDR(ISP_PK_CON_2CIRBPGAIN_LIMIT)
#define ISP_PK_CON_2DRTHPGAIN_TH_RATE 0x2d58 	///../ucode/register.h:10629
#define P_ISP_PK_CON_2DRTHPGAIN_TH_RATE 		VCBUS_REG_ADDR(ISP_PK_CON_2DRTHPGAIN_TH_RATE)
#define ISP_PK_CON_2DRTHPGAIN_LIMIT 0x2d59 	///../ucode/register.h:10635
#define P_ISP_PK_CON_2DRTHPGAIN_LIMIT 		VCBUS_REG_ADDR(ISP_PK_CON_2DRTHPGAIN_LIMIT)
#define ISP_PK_CON_2DRTBPGAIN_TH_RATE 0x2d5a 	///../ucode/register.h:10641
#define P_ISP_PK_CON_2DRTBPGAIN_TH_RATE 		VCBUS_REG_ADDR(ISP_PK_CON_2DRTBPGAIN_TH_RATE)
#define ISP_PK_CON_2DRTBPGAIN_LIMIT 0x2d5b 	///../ucode/register.h:10647
#define P_ISP_PK_CON_2DRTBPGAIN_LIMIT 		VCBUS_REG_ADDR(ISP_PK_CON_2DRTBPGAIN_LIMIT)
#define ISP_PK_CIRFB_LPF_MODE 0x2d60 	///../ucode/register.h:10654
#define P_ISP_PK_CIRFB_LPF_MODE 		VCBUS_REG_ADDR(ISP_PK_CIRFB_LPF_MODE)
#define ISP_PK_DRTFB_LPF_MODE 0x2d61 	///../ucode/register.h:10668
#define P_ISP_PK_DRTFB_LPF_MODE 		VCBUS_REG_ADDR(ISP_PK_DRTFB_LPF_MODE)
#define ISP_PK_CIRFB_HP_CORING 0x2d62 	///../ucode/register.h:10682
#define P_ISP_PK_CIRFB_HP_CORING 		VCBUS_REG_ADDR(ISP_PK_CIRFB_HP_CORING)
#define ISP_PK_CIRFB_BP_CORING 0x2d63 	///../ucode/register.h:10689
#define P_ISP_PK_CIRFB_BP_CORING 		VCBUS_REG_ADDR(ISP_PK_CIRFB_BP_CORING)
#define ISP_PK_DRTFB_HP_CORING 0x2d64 	///../ucode/register.h:10696
#define P_ISP_PK_DRTFB_HP_CORING 		VCBUS_REG_ADDR(ISP_PK_DRTFB_HP_CORING)
#define ISP_PK_DRTFB_BP_CORING 0x2d65 	///../ucode/register.h:10703
#define P_ISP_PK_DRTFB_BP_CORING 		VCBUS_REG_ADDR(ISP_PK_DRTFB_BP_CORING)
#define ISP_PK_CIRFB_BLEND_GAIN 0x2d66 	///../ucode/register.h:10710
#define P_ISP_PK_CIRFB_BLEND_GAIN 		VCBUS_REG_ADDR(ISP_PK_CIRFB_BLEND_GAIN)
#define ISP_NR_ALPY_SSD_GAIN_OFST 0x2d68 	///../ucode/register.h:10721
#define P_ISP_NR_ALPY_SSD_GAIN_OFST 		VCBUS_REG_ADDR(ISP_NR_ALPY_SSD_GAIN_OFST)
#define ISP_NR_ALP0Y_ERR2CURV_TH_RATE 0x2d69 	///../ucode/register.h:10726
#define P_ISP_NR_ALP0Y_ERR2CURV_TH_RATE 		VCBUS_REG_ADDR(ISP_NR_ALP0Y_ERR2CURV_TH_RATE)
#define ISP_NR_ALP0Y_ERR2CURV_LIMIT 0x2d6a 	///../ucode/register.h:10733
#define P_ISP_NR_ALP0Y_ERR2CURV_LIMIT 		VCBUS_REG_ADDR(ISP_NR_ALP0Y_ERR2CURV_LIMIT)
#define ISP_NR_ALP0C_ERR2CURV_TH_RATE 0x2d6b 	///../ucode/register.h:10739
#define P_ISP_NR_ALP0C_ERR2CURV_TH_RATE 		VCBUS_REG_ADDR(ISP_NR_ALP0C_ERR2CURV_TH_RATE)
#define ISP_NR_ALP0C_ERR2CURV_LIMIT 0x2d6c 	///../ucode/register.h:10745
#define P_ISP_NR_ALP0C_ERR2CURV_LIMIT 		VCBUS_REG_ADDR(ISP_NR_ALP0C_ERR2CURV_LIMIT)
#define ISP_NR_ALP0_MIN_MAX 0x2d6d 	///../ucode/register.h:10750
#define P_ISP_NR_ALP0_MIN_MAX 		VCBUS_REG_ADDR(ISP_NR_ALP0_MIN_MAX)
#define ISP_NR_ALP1_MIERR_CORING 0x2d6e 	///../ucode/register.h:10759
#define P_ISP_NR_ALP1_MIERR_CORING 		VCBUS_REG_ADDR(ISP_NR_ALP1_MIERR_CORING)
#define ISP_NR_ALP1_ERR2CURV_TH_RATE 0x2d6f 	///../ucode/register.h:10766
#define P_ISP_NR_ALP1_ERR2CURV_TH_RATE 		VCBUS_REG_ADDR(ISP_NR_ALP1_ERR2CURV_TH_RATE)
#define ISP_NR_ALP1_ERR2CURV_LIMIT 0x2d70 	///../ucode/register.h:10772
#define P_ISP_NR_ALP1_ERR2CURV_LIMIT 		VCBUS_REG_ADDR(ISP_NR_ALP1_ERR2CURV_LIMIT)
#define ISP_NR_ALP1_MIN_MAX 0x2d71 	///../ucode/register.h:10778
#define P_ISP_NR_ALP1_MIN_MAX 		VCBUS_REG_ADDR(ISP_NR_ALP1_MIN_MAX)
#define ISP_PK_ALP2_MIERR_CORING 0x2d72 	///../ucode/register.h:10787
#define P_ISP_PK_ALP2_MIERR_CORING 		VCBUS_REG_ADDR(ISP_PK_ALP2_MIERR_CORING)
#define ISP_PK_ALP2_ERR2CURV_TH_RATE 0x2d73 	///../ucode/register.h:10794
#define P_ISP_PK_ALP2_ERR2CURV_TH_RATE 		VCBUS_REG_ADDR(ISP_PK_ALP2_ERR2CURV_TH_RATE)
#define ISP_PK_ALP2_ERR2CURV_LIMIT 0x2d74 	///../ucode/register.h:10800
#define P_ISP_PK_ALP2_ERR2CURV_LIMIT 		VCBUS_REG_ADDR(ISP_PK_ALP2_ERR2CURV_LIMIT)
#define ISP_PK_ALP2_MIN_MAX 0x2d75 	///../ucode/register.h:10806
#define P_ISP_PK_ALP2_MIN_MAX 		VCBUS_REG_ADDR(ISP_PK_ALP2_MIN_MAX)
#define ISP_PK_FINALGAIN_HP_BP 0x2d76 	///../ucode/register.h:10811
#define P_ISP_PK_FINALGAIN_HP_BP 		VCBUS_REG_ADDR(ISP_PK_FINALGAIN_HP_BP)
#define ISP_PK_OS_HORZ_CORE_GAIN 0x2d78 	///../ucode/register.h:10816
#define P_ISP_PK_OS_HORZ_CORE_GAIN 		VCBUS_REG_ADDR(ISP_PK_OS_HORZ_CORE_GAIN)
#define ISP_PK_OS_VERT_CORE_GAIN 0x2d79 	///../ucode/register.h:10821
#define P_ISP_PK_OS_VERT_CORE_GAIN 		VCBUS_REG_ADDR(ISP_PK_OS_VERT_CORE_GAIN)
#define ISP_PK_OS_ADPT_MISC 0x2d7a 	///../ucode/register.h:10826
#define P_ISP_PK_OS_ADPT_MISC 		VCBUS_REG_ADDR(ISP_PK_OS_ADPT_MISC)
#define ISP_PK_OS_STATIC 0x2d7b 	///../ucode/register.h:10831
#define P_ISP_PK_OS_STATIC 		VCBUS_REG_ADDR(ISP_PK_OS_STATIC)
#define ISP_PKSDE_MODE_PKGAIN 0x2d80 	///../ucode/register.h:10844
#define P_ISP_PKSDE_MODE_PKGAIN 		VCBUS_REG_ADDR(ISP_PKSDE_MODE_PKGAIN)
#define ISP_PKSDE_REPLACE_Y_U 0x2d81 	///../ucode/register.h:10855
#define P_ISP_PKSDE_REPLACE_Y_U 		VCBUS_REG_ADDR(ISP_PKSDE_REPLACE_Y_U)
#define ISP_PKSDE_REPLACE_V 0x2d82 	///../ucode/register.h:10864
#define P_ISP_PKSDE_REPLACE_V 		VCBUS_REG_ADDR(ISP_PKSDE_REPLACE_V)
#define ISP_PKSDE_BINARY_HIG 0x2d83 	///../ucode/register.h:10870
#define P_ISP_PKSDE_BINARY_HIG 		VCBUS_REG_ADDR(ISP_PKSDE_BINARY_HIG)
#define ISP_PKSDE_BINARY_LOW 0x2d84 	///../ucode/register.h:10875
#define P_ISP_PKSDE_BINARY_LOW 		VCBUS_REG_ADDR(ISP_PKSDE_BINARY_LOW)
#define ISP_PKNR_ENABLE 0x2d85 	///../ucode/register.h:10880
#define P_ISP_PKNR_ENABLE 		VCBUS_REG_ADDR(ISP_PKNR_ENABLE)
#define ISP_AWB_WIND_LR 0x2d88 	///../ucode/register.h:10888
#define P_ISP_AWB_WIND_LR 		VCBUS_REG_ADDR(ISP_AWB_WIND_LR)
#define ISP_AWB_WIND_TB 0x2d89 	///../ucode/register.h:10893
#define P_ISP_AWB_WIND_TB 		VCBUS_REG_ADDR(ISP_AWB_WIND_TB)
#define ISP_AWB_GBGRBR_THRD 0x2d8a 	///../ucode/register.h:10898
#define P_ISP_AWB_GBGRBR_THRD 		VCBUS_REG_ADDR(ISP_AWB_GBGRBR_THRD)
#define ISP_AWB_UVTH_YPIECE 0x2d8b 	///../ucode/register.h:10903
#define P_ISP_AWB_UVTH_YPIECE 		VCBUS_REG_ADDR(ISP_AWB_UVTH_YPIECE)
#define ISP_AWB_AEC_ENABLE 0x2d8c 	///../ucode/register.h:10908
#define P_ISP_AWB_AEC_ENABLE 		VCBUS_REG_ADDR(ISP_AWB_AEC_ENABLE)
#define ISP_AEC_THRESHOLDS 0x2d90 	///../ucode/register.h:10917
#define P_ISP_AEC_THRESHOLDS 		VCBUS_REG_ADDR(ISP_AEC_THRESHOLDS)
#define ISP_AEC_WIND_XYSTART 0x2d91 	///../ucode/register.h:10922
#define P_ISP_AEC_WIND_XYSTART 		VCBUS_REG_ADDR(ISP_AEC_WIND_XYSTART)
#define ISP_AEC_WIND_XYSTEP 0x2d92 	///../ucode/register.h:10927
#define P_ISP_AEC_WIND_XYSTEP 		VCBUS_REG_ADDR(ISP_AEC_WIND_XYSTEP)
#define ISP_AECRAW_WIND_LR 0x2d93 	///../ucode/register.h:10932
#define P_ISP_AECRAW_WIND_LR 		VCBUS_REG_ADDR(ISP_AECRAW_WIND_LR)
#define ISP_AECRAW_WIND_TB 0x2d94 	///../ucode/register.h:10937
#define P_ISP_AECRAW_WIND_TB 		VCBUS_REG_ADDR(ISP_AECRAW_WIND_TB)
#define ISP_AFC_FILTER_SEL 0x2d98 	///../ucode/register.h:10946
#define P_ISP_AFC_FILTER_SEL 		VCBUS_REG_ADDR(ISP_AFC_FILTER_SEL)
#define ISP_AFC_WIND0_LR 0x2d99 	///../ucode/register.h:10955
#define P_ISP_AFC_WIND0_LR 		VCBUS_REG_ADDR(ISP_AFC_WIND0_LR)
#define ISP_AFC_WIND0_TB 0x2d9a 	///../ucode/register.h:10960
#define P_ISP_AFC_WIND0_TB 		VCBUS_REG_ADDR(ISP_AFC_WIND0_TB)
#define ISP_AFC_WIND1_LR 0x2d9b 	///../ucode/register.h:10965
#define P_ISP_AFC_WIND1_LR 		VCBUS_REG_ADDR(ISP_AFC_WIND1_LR)
#define ISP_AFC_WIND1_TB 0x2d9c 	///../ucode/register.h:10970
#define P_ISP_AFC_WIND1_TB 		VCBUS_REG_ADDR(ISP_AFC_WIND1_TB)
#define ISP_AFC_WIND2_LR 0x2d9d 	///../ucode/register.h:10975
#define P_ISP_AFC_WIND2_LR 		VCBUS_REG_ADDR(ISP_AFC_WIND2_LR)
#define ISP_AFC_WIND2_TB 0x2d9e 	///../ucode/register.h:10980
#define P_ISP_AFC_WIND2_TB 		VCBUS_REG_ADDR(ISP_AFC_WIND2_TB)
#define ISP_AFC_WIND3_LR 0x2d9f 	///../ucode/register.h:10985
#define P_ISP_AFC_WIND3_LR 		VCBUS_REG_ADDR(ISP_AFC_WIND3_LR)
#define ISP_AFC_WIND3_TB 0x2da0 	///../ucode/register.h:10990
#define P_ISP_AFC_WIND3_TB 		VCBUS_REG_ADDR(ISP_AFC_WIND3_TB)
#define ISP_AFC_WIND4_LR 0x2da1 	///../ucode/register.h:10995
#define P_ISP_AFC_WIND4_LR 		VCBUS_REG_ADDR(ISP_AFC_WIND4_LR)
#define ISP_AFC_WIND4_TB 0x2da2 	///../ucode/register.h:11000
#define P_ISP_AFC_WIND4_TB 		VCBUS_REG_ADDR(ISP_AFC_WIND4_TB)
#define ISP_AFC_WIND5_LR 0x2da3 	///../ucode/register.h:11005
#define P_ISP_AFC_WIND5_LR 		VCBUS_REG_ADDR(ISP_AFC_WIND5_LR)
#define ISP_AFC_WIND5_TB 0x2da4 	///../ucode/register.h:11010
#define P_ISP_AFC_WIND5_TB 		VCBUS_REG_ADDR(ISP_AFC_WIND5_TB)
#define ISP_AFC_WIND6_LR 0x2da5 	///../ucode/register.h:11015
#define P_ISP_AFC_WIND6_LR 		VCBUS_REG_ADDR(ISP_AFC_WIND6_LR)
#define ISP_AFC_WIND6_TB 0x2da6 	///../ucode/register.h:11020
#define P_ISP_AFC_WIND6_TB 		VCBUS_REG_ADDR(ISP_AFC_WIND6_TB)
#define ISP_AFC_WIND7_LR 0x2da7 	///../ucode/register.h:11025
#define P_ISP_AFC_WIND7_LR 		VCBUS_REG_ADDR(ISP_AFC_WIND7_LR)
#define ISP_AFC_WIND7_TB 0x2da8 	///../ucode/register.h:11030
#define P_ISP_AFC_WIND7_TB 		VCBUS_REG_ADDR(ISP_AFC_WIND7_TB)
#define ISP_BLNR_CTRL 0x2dac 	///../ucode/register.h:11039
#define P_ISP_BLNR_CTRL 		VCBUS_REG_ADDR(ISP_BLNR_CTRL)
#define ISP_BLNR_WIND_LR 0x2dad 	///../ucode/register.h:11046
#define P_ISP_BLNR_WIND_LR 		VCBUS_REG_ADDR(ISP_BLNR_WIND_LR)
#define ISP_BLNR_WIND_TB 0x2dae 	///../ucode/register.h:11051
#define P_ISP_BLNR_WIND_TB 		VCBUS_REG_ADDR(ISP_BLNR_WIND_TB)
#define ISP_RAM_ACC_MODE 0x2daf 	///../ucode/register.h:11057
#define P_ISP_RAM_ACC_MODE 		VCBUS_REG_ADDR(ISP_RAM_ACC_MODE)
#define ISP_DBG_PIXEL_CTRL 0x2db0 	///../ucode/register.h:11064
#define P_ISP_DBG_PIXEL_CTRL 		VCBUS_REG_ADDR(ISP_DBG_PIXEL_CTRL)
#define ISP_DBG_PIXEL_POSITION 0x2db1 	///../ucode/register.h:11072
#define P_ISP_DBG_PIXEL_POSITION 		VCBUS_REG_ADDR(ISP_DBG_PIXEL_POSITION)
#define ISP_RO_DBG_PIXEL_GRBG0_1 0x2db2 	///../ucode/register.h:11077
#define P_ISP_RO_DBG_PIXEL_GRBG0_1 		VCBUS_REG_ADDR(ISP_RO_DBG_PIXEL_GRBG0_1)
#define ISP_RO_DBG_PIXEL_GRBG2_3 0x2db3 	///../ucode/register.h:11082
#define P_ISP_RO_DBG_PIXEL_GRBG2_3 		VCBUS_REG_ADDR(ISP_RO_DBG_PIXEL_GRBG2_3)
#define ISP_RO_DFT_LUTMEM_CTRL 0x2d32 	///../ucode/register.h:11088
#define P_ISP_RO_DFT_LUTMEM_CTRL 		VCBUS_REG_ADDR(ISP_RO_DFT_LUTMEM_CTRL)
#define ISP_RO_DFT_DET_NUM 0x2d3f 	///../ucode/register.h:11091
#define P_ISP_RO_DFT_DET_NUM 		VCBUS_REG_ADDR(ISP_RO_DFT_DET_NUM)
#define ISP_RO_INFORD_STATE 0x2db4 	///../ucode/register.h:11094
#define P_ISP_RO_INFORD_STATE 		VCBUS_REG_ADDR(ISP_RO_INFORD_STATE)
#define ISP_RO_DINVLD_HVCNT 0x2db5 	///../ucode/register.h:11097
#define P_ISP_RO_DINVLD_HVCNT 		VCBUS_REG_ADDR(ISP_RO_DINVLD_HVCNT)
#define ISP_RO_FRM_HS_STAT 0x2db6 	///../ucode/register.h:11102
#define P_ISP_RO_FRM_HS_STAT 		VCBUS_REG_ADDR(ISP_RO_FRM_HS_STAT)
#define ISP_RO_ADDR_PORT 0x2dc0 	///../ucode/register.h:11110
#define P_ISP_RO_ADDR_PORT 		VCBUS_REG_ADDR(ISP_RO_ADDR_PORT)
#define ISP_RO_DATA_PORT 0x2dc1 	///../ucode/register.h:11111
#define P_ISP_RO_DATA_PORT 		VCBUS_REG_ADDR(ISP_RO_DATA_PORT)
#define BT_CTRL 0x2f40 	///../ucode/register.h:11325
#define P_BT_CTRL 		VCBUS_REG_ADDR(BT_CTRL)
#define BT_VBISTART 0x2f41 	///../ucode/register.h:11346
#define P_BT_VBISTART 		VCBUS_REG_ADDR(BT_VBISTART)
#define BT_VBIEND 0x2f42 	///../ucode/register.h:11347
#define P_BT_VBIEND 		VCBUS_REG_ADDR(BT_VBIEND)
#define BT_FIELDSADR 0x2f43 	///../ucode/register.h:11348
#define P_BT_FIELDSADR 		VCBUS_REG_ADDR(BT_FIELDSADR)
#define BT_LINECTRL 0x2f44 	///../ucode/register.h:11349
#define P_BT_LINECTRL 		VCBUS_REG_ADDR(BT_LINECTRL)
#define BT_VIDEOSTART 0x2f45 	///../ucode/register.h:11350
#define P_BT_VIDEOSTART 		VCBUS_REG_ADDR(BT_VIDEOSTART)
#define BT_VIDEOEND 0x2f46 	///../ucode/register.h:11351
#define P_BT_VIDEOEND 		VCBUS_REG_ADDR(BT_VIDEOEND)
#define BT_SLICELINE0 0x2f47 	///../ucode/register.h:11352
#define P_BT_SLICELINE0 		VCBUS_REG_ADDR(BT_SLICELINE0)
#define BT_SLICELINE1 0x2f48 	///../ucode/register.h:11353
#define P_BT_SLICELINE1 		VCBUS_REG_ADDR(BT_SLICELINE1)
#define BT_PORT_CTRL 0x2f49 	///../ucode/register.h:11354
#define P_BT_PORT_CTRL 		VCBUS_REG_ADDR(BT_PORT_CTRL)
#define BT_SWAP_CTRL 0x2f4a 	///../ucode/register.h:11368
#define P_BT_SWAP_CTRL 		VCBUS_REG_ADDR(BT_SWAP_CTRL)
#define BT_ANCISADR 0x2f4b 	///../ucode/register.h:11369
#define P_BT_ANCISADR 		VCBUS_REG_ADDR(BT_ANCISADR)
#define BT_ANCIEADR 0x2f4c 	///../ucode/register.h:11370
#define P_BT_ANCIEADR 		VCBUS_REG_ADDR(BT_ANCIEADR)
#define BT_AFIFO_CTRL 0x2f4d 	///../ucode/register.h:11371
#define P_BT_AFIFO_CTRL 		VCBUS_REG_ADDR(BT_AFIFO_CTRL)
#define BT_601_CTRL0 0x2f4e 	///../ucode/register.h:11372
#define P_BT_601_CTRL0 		VCBUS_REG_ADDR(BT_601_CTRL0)
#define BT_601_CTRL1 0x2f4f 	///../ucode/register.h:11373
#define P_BT_601_CTRL1 		VCBUS_REG_ADDR(BT_601_CTRL1)
#define BT_601_CTRL2 0x2f50 	///../ucode/register.h:11374
#define P_BT_601_CTRL2 		VCBUS_REG_ADDR(BT_601_CTRL2)
#define BT_601_CTRL3 0x2f51 	///../ucode/register.h:11375
#define P_BT_601_CTRL3 		VCBUS_REG_ADDR(BT_601_CTRL3)
#define BT_FIELD_LUMA 0x2f52 	///../ucode/register.h:11376
#define P_BT_FIELD_LUMA 		VCBUS_REG_ADDR(BT_FIELD_LUMA)
#define BT_RAW_CTRL 0x2f53 	///../ucode/register.h:11377
#define P_BT_RAW_CTRL 		VCBUS_REG_ADDR(BT_RAW_CTRL)
#define BT_STATUS 0x2f54 	///../ucode/register.h:11378
#define P_BT_STATUS 		VCBUS_REG_ADDR(BT_STATUS)
#define BT_INT_CTRL 0x2f55 	///../ucode/register.h:11379
#define P_BT_INT_CTRL 		VCBUS_REG_ADDR(BT_INT_CTRL)
#define BT_ANCI_STATUS 0x2f56 	///../ucode/register.h:11380
#define P_BT_ANCI_STATUS 		VCBUS_REG_ADDR(BT_ANCI_STATUS)
#define BT_VLINE_STATUS 0x2f57 	///../ucode/register.h:11381
#define P_BT_VLINE_STATUS 		VCBUS_REG_ADDR(BT_VLINE_STATUS)
#define BT_AFIFO_PTR 0x2f58 	///../ucode/register.h:11382
#define P_BT_AFIFO_PTR 		VCBUS_REG_ADDR(BT_AFIFO_PTR)
#define BT_JPEGBYTENUM 0x2f59 	///../ucode/register.h:11383
#define P_BT_JPEGBYTENUM 		VCBUS_REG_ADDR(BT_JPEGBYTENUM)
#define BT_ERR_CNT 0x2f5a 	///../ucode/register.h:11384
#define P_BT_ERR_CNT 		VCBUS_REG_ADDR(BT_ERR_CNT)
#define BT_JPEG_STATUS0 0x2f5b 	///../ucode/register.h:11385
#define P_BT_JPEG_STATUS0 		VCBUS_REG_ADDR(BT_JPEG_STATUS0)
#define BT_JPEG_STATUS1 0x2f5c 	///../ucode/register.h:11386
#define P_BT_JPEG_STATUS1 		VCBUS_REG_ADDR(BT_JPEG_STATUS1)
#define BT_LCNT_STATUS 0x2f5d 	///../ucode/register.h:11387
#define P_BT_LCNT_STATUS 		VCBUS_REG_ADDR(BT_LCNT_STATUS)
#define BT_PCNT_STATUS 0x2f5e 	///../ucode/register.h:11388
#define P_BT_PCNT_STATUS 		VCBUS_REG_ADDR(BT_PCNT_STATUS)
#define BT656_ADDR_END 0x2f5f 	///../ucode/register.h:11389
#define P_BT656_ADDR_END 		VCBUS_REG_ADDR(BT656_ADDR_END)
#define VDEC_ASSIST_MMC_CTRL0 0x0001 	///../ucode/dos_register.h:40
#define P_VDEC_ASSIST_MMC_CTRL0 		DOS_REG_ADDR(VDEC_ASSIST_MMC_CTRL0)
#define VDEC_ASSIST_MMC_CTRL1 0x0002 	///../ucode/dos_register.h:41
#define P_VDEC_ASSIST_MMC_CTRL1 		DOS_REG_ADDR(VDEC_ASSIST_MMC_CTRL1)
#define VDEC_ASSIST_AMR1_INT0 0x0025 	///../ucode/dos_register.h:42
#define P_VDEC_ASSIST_AMR1_INT0 		DOS_REG_ADDR(VDEC_ASSIST_AMR1_INT0)
#define VDEC_ASSIST_AMR1_INT1 0x0026 	///../ucode/dos_register.h:43
#define P_VDEC_ASSIST_AMR1_INT1 		DOS_REG_ADDR(VDEC_ASSIST_AMR1_INT1)
#define VDEC_ASSIST_AMR1_INT2 0x0027 	///../ucode/dos_register.h:44
#define P_VDEC_ASSIST_AMR1_INT2 		DOS_REG_ADDR(VDEC_ASSIST_AMR1_INT2)
#define VDEC_ASSIST_AMR1_INT3 0x0028 	///../ucode/dos_register.h:45
#define P_VDEC_ASSIST_AMR1_INT3 		DOS_REG_ADDR(VDEC_ASSIST_AMR1_INT3)
#define VDEC_ASSIST_AMR1_INT4 0x0029 	///../ucode/dos_register.h:46
#define P_VDEC_ASSIST_AMR1_INT4 		DOS_REG_ADDR(VDEC_ASSIST_AMR1_INT4)
#define VDEC_ASSIST_AMR1_INT5 0x002a 	///../ucode/dos_register.h:47
#define P_VDEC_ASSIST_AMR1_INT5 		DOS_REG_ADDR(VDEC_ASSIST_AMR1_INT5)
#define VDEC_ASSIST_AMR1_INT6 0x002b 	///../ucode/dos_register.h:48
#define P_VDEC_ASSIST_AMR1_INT6 		DOS_REG_ADDR(VDEC_ASSIST_AMR1_INT6)
#define VDEC_ASSIST_AMR1_INT7 0x002c 	///../ucode/dos_register.h:49
#define P_VDEC_ASSIST_AMR1_INT7 		DOS_REG_ADDR(VDEC_ASSIST_AMR1_INT7)
#define VDEC_ASSIST_AMR1_INT8 0x002d 	///../ucode/dos_register.h:50
#define P_VDEC_ASSIST_AMR1_INT8 		DOS_REG_ADDR(VDEC_ASSIST_AMR1_INT8)
#define VDEC_ASSIST_AMR1_INT9 0x002e 	///../ucode/dos_register.h:51
#define P_VDEC_ASSIST_AMR1_INT9 		DOS_REG_ADDR(VDEC_ASSIST_AMR1_INT9)
#define VDEC_ASSIST_AMR1_INTA 0x002f 	///../ucode/dos_register.h:52
#define P_VDEC_ASSIST_AMR1_INTA 		DOS_REG_ADDR(VDEC_ASSIST_AMR1_INTA)
#define VDEC_ASSIST_AMR1_INTB 0x0030 	///../ucode/dos_register.h:53
#define P_VDEC_ASSIST_AMR1_INTB 		DOS_REG_ADDR(VDEC_ASSIST_AMR1_INTB)
#define VDEC_ASSIST_AMR1_INTC 0x0031 	///../ucode/dos_register.h:54
#define P_VDEC_ASSIST_AMR1_INTC 		DOS_REG_ADDR(VDEC_ASSIST_AMR1_INTC)
#define VDEC_ASSIST_AMR1_INTD 0x0032 	///../ucode/dos_register.h:55
#define P_VDEC_ASSIST_AMR1_INTD 		DOS_REG_ADDR(VDEC_ASSIST_AMR1_INTD)
#define VDEC_ASSIST_AMR1_INTE 0x0033 	///../ucode/dos_register.h:56
#define P_VDEC_ASSIST_AMR1_INTE 		DOS_REG_ADDR(VDEC_ASSIST_AMR1_INTE)
#define VDEC_ASSIST_AMR1_INTF 0x0034 	///../ucode/dos_register.h:57
#define P_VDEC_ASSIST_AMR1_INTF 		DOS_REG_ADDR(VDEC_ASSIST_AMR1_INTF)
#define VDEC_ASSIST_AMR2_INT0 0x0035 	///../ucode/dos_register.h:58
#define P_VDEC_ASSIST_AMR2_INT0 		DOS_REG_ADDR(VDEC_ASSIST_AMR2_INT0)
#define VDEC_ASSIST_AMR2_INT1 0x0036 	///../ucode/dos_register.h:59
#define P_VDEC_ASSIST_AMR2_INT1 		DOS_REG_ADDR(VDEC_ASSIST_AMR2_INT1)
#define VDEC_ASSIST_AMR2_INT2 0x0037 	///../ucode/dos_register.h:60
#define P_VDEC_ASSIST_AMR2_INT2 		DOS_REG_ADDR(VDEC_ASSIST_AMR2_INT2)
#define VDEC_ASSIST_AMR2_INT3 0x0038 	///../ucode/dos_register.h:61
#define P_VDEC_ASSIST_AMR2_INT3 		DOS_REG_ADDR(VDEC_ASSIST_AMR2_INT3)
#define VDEC_ASSIST_AMR2_INT4 0x0039 	///../ucode/dos_register.h:62
#define P_VDEC_ASSIST_AMR2_INT4 		DOS_REG_ADDR(VDEC_ASSIST_AMR2_INT4)
#define VDEC_ASSIST_AMR2_INT5 0x003a 	///../ucode/dos_register.h:63
#define P_VDEC_ASSIST_AMR2_INT5 		DOS_REG_ADDR(VDEC_ASSIST_AMR2_INT5)
#define VDEC_ASSIST_AMR2_INT6 0x003b 	///../ucode/dos_register.h:64
#define P_VDEC_ASSIST_AMR2_INT6 		DOS_REG_ADDR(VDEC_ASSIST_AMR2_INT6)
#define VDEC_ASSIST_AMR2_INT7 0x003c 	///../ucode/dos_register.h:65
#define P_VDEC_ASSIST_AMR2_INT7 		DOS_REG_ADDR(VDEC_ASSIST_AMR2_INT7)
#define VDEC_ASSIST_AMR2_INT8 0x003d 	///../ucode/dos_register.h:66
#define P_VDEC_ASSIST_AMR2_INT8 		DOS_REG_ADDR(VDEC_ASSIST_AMR2_INT8)
#define VDEC_ASSIST_AMR2_INT9 0x003e 	///../ucode/dos_register.h:67
#define P_VDEC_ASSIST_AMR2_INT9 		DOS_REG_ADDR(VDEC_ASSIST_AMR2_INT9)
#define VDEC_ASSIST_AMR2_INTA 0x003f 	///../ucode/dos_register.h:68
#define P_VDEC_ASSIST_AMR2_INTA 		DOS_REG_ADDR(VDEC_ASSIST_AMR2_INTA)
#define VDEC_ASSIST_AMR2_INTB 0x0040 	///../ucode/dos_register.h:69
#define P_VDEC_ASSIST_AMR2_INTB 		DOS_REG_ADDR(VDEC_ASSIST_AMR2_INTB)
#define VDEC_ASSIST_AMR2_INTC 0x0041 	///../ucode/dos_register.h:70
#define P_VDEC_ASSIST_AMR2_INTC 		DOS_REG_ADDR(VDEC_ASSIST_AMR2_INTC)
#define VDEC_ASSIST_AMR2_INTD 0x0042 	///../ucode/dos_register.h:71
#define P_VDEC_ASSIST_AMR2_INTD 		DOS_REG_ADDR(VDEC_ASSIST_AMR2_INTD)
#define VDEC_ASSIST_AMR2_INTE 0x0043 	///../ucode/dos_register.h:72
#define P_VDEC_ASSIST_AMR2_INTE 		DOS_REG_ADDR(VDEC_ASSIST_AMR2_INTE)
#define VDEC_ASSIST_AMR2_INTF 0x0044 	///../ucode/dos_register.h:73
#define P_VDEC_ASSIST_AMR2_INTF 		DOS_REG_ADDR(VDEC_ASSIST_AMR2_INTF)
#define VDEC_ASSIST_MBX_SSEL 0x0045 	///../ucode/dos_register.h:74
#define P_VDEC_ASSIST_MBX_SSEL 		DOS_REG_ADDR(VDEC_ASSIST_MBX_SSEL)
#define VDEC_ASSIST_TIMER0_LO 0x0060 	///../ucode/dos_register.h:75
#define P_VDEC_ASSIST_TIMER0_LO 		DOS_REG_ADDR(VDEC_ASSIST_TIMER0_LO)
#define VDEC_ASSIST_TIMER0_HI 0x0061 	///../ucode/dos_register.h:76
#define P_VDEC_ASSIST_TIMER0_HI 		DOS_REG_ADDR(VDEC_ASSIST_TIMER0_HI)
#define VDEC_ASSIST_TIMER1_LO 0x0062 	///../ucode/dos_register.h:77
#define P_VDEC_ASSIST_TIMER1_LO 		DOS_REG_ADDR(VDEC_ASSIST_TIMER1_LO)
#define VDEC_ASSIST_TIMER1_HI 0x0063 	///../ucode/dos_register.h:78
#define P_VDEC_ASSIST_TIMER1_HI 		DOS_REG_ADDR(VDEC_ASSIST_TIMER1_HI)
#define VDEC_ASSIST_DMA_INT 0x0064 	///../ucode/dos_register.h:79
#define P_VDEC_ASSIST_DMA_INT 		DOS_REG_ADDR(VDEC_ASSIST_DMA_INT)
#define VDEC_ASSIST_DMA_INT_MSK 0x0065 	///../ucode/dos_register.h:80
#define P_VDEC_ASSIST_DMA_INT_MSK 		DOS_REG_ADDR(VDEC_ASSIST_DMA_INT_MSK)
#define VDEC_ASSIST_DMA_INT2 0x0066 	///../ucode/dos_register.h:81
#define P_VDEC_ASSIST_DMA_INT2 		DOS_REG_ADDR(VDEC_ASSIST_DMA_INT2)
#define VDEC_ASSIST_DMA_INT_MSK2 0x0067 	///../ucode/dos_register.h:82
#define P_VDEC_ASSIST_DMA_INT_MSK2 		DOS_REG_ADDR(VDEC_ASSIST_DMA_INT_MSK2)
#define VDEC_ASSIST_MBOX0_IRQ_REG 0x0070 	///../ucode/dos_register.h:83
#define P_VDEC_ASSIST_MBOX0_IRQ_REG 		DOS_REG_ADDR(VDEC_ASSIST_MBOX0_IRQ_REG)
#define VDEC_ASSIST_MBOX0_CLR_REG 0x0071 	///../ucode/dos_register.h:84
#define P_VDEC_ASSIST_MBOX0_CLR_REG 		DOS_REG_ADDR(VDEC_ASSIST_MBOX0_CLR_REG)
#define VDEC_ASSIST_MBOX0_MASK 0x0072 	///../ucode/dos_register.h:85
#define P_VDEC_ASSIST_MBOX0_MASK 		DOS_REG_ADDR(VDEC_ASSIST_MBOX0_MASK)
#define VDEC_ASSIST_MBOX0_FIQ_SEL 0x0073 	///../ucode/dos_register.h:86
#define P_VDEC_ASSIST_MBOX0_FIQ_SEL 		DOS_REG_ADDR(VDEC_ASSIST_MBOX0_FIQ_SEL)
#define VDEC_ASSIST_MBOX1_IRQ_REG 0x0074 	///../ucode/dos_register.h:87
#define P_VDEC_ASSIST_MBOX1_IRQ_REG 		DOS_REG_ADDR(VDEC_ASSIST_MBOX1_IRQ_REG)
#define VDEC_ASSIST_MBOX1_CLR_REG 0x0075 	///../ucode/dos_register.h:88
#define P_VDEC_ASSIST_MBOX1_CLR_REG 		DOS_REG_ADDR(VDEC_ASSIST_MBOX1_CLR_REG)
#define VDEC_ASSIST_MBOX1_MASK 0x0076 	///../ucode/dos_register.h:89
#define P_VDEC_ASSIST_MBOX1_MASK 		DOS_REG_ADDR(VDEC_ASSIST_MBOX1_MASK)
#define VDEC_ASSIST_MBOX1_FIQ_SEL 0x0077 	///../ucode/dos_register.h:90
#define P_VDEC_ASSIST_MBOX1_FIQ_SEL 		DOS_REG_ADDR(VDEC_ASSIST_MBOX1_FIQ_SEL)
#define VDEC_ASSIST_MBOX2_IRQ_REG 0x0078 	///../ucode/dos_register.h:91
#define P_VDEC_ASSIST_MBOX2_IRQ_REG 		DOS_REG_ADDR(VDEC_ASSIST_MBOX2_IRQ_REG)
#define VDEC_ASSIST_MBOX2_CLR_REG 0x0079 	///../ucode/dos_register.h:92
#define P_VDEC_ASSIST_MBOX2_CLR_REG 		DOS_REG_ADDR(VDEC_ASSIST_MBOX2_CLR_REG)
#define VDEC_ASSIST_MBOX2_MASK 0x007a 	///../ucode/dos_register.h:93
#define P_VDEC_ASSIST_MBOX2_MASK 		DOS_REG_ADDR(VDEC_ASSIST_MBOX2_MASK)
#define VDEC_ASSIST_MBOX2_FIQ_SEL 0x007b 	///../ucode/dos_register.h:94
#define P_VDEC_ASSIST_MBOX2_FIQ_SEL 		DOS_REG_ADDR(VDEC_ASSIST_MBOX2_FIQ_SEL)
#define VDEC2_ASSIST_MMC_CTRL0 0x2001 	///../ucode/dos_register.h:101
#define P_VDEC2_ASSIST_MMC_CTRL0 		DOS_REG_ADDR(VDEC2_ASSIST_MMC_CTRL0)
#define VDEC2_ASSIST_MMC_CTRL1 0x2002 	///../ucode/dos_register.h:102
#define P_VDEC2_ASSIST_MMC_CTRL1 		DOS_REG_ADDR(VDEC2_ASSIST_MMC_CTRL1)
#define VDEC2_ASSIST_AMR1_INT0 0x2025 	///../ucode/dos_register.h:103
#define P_VDEC2_ASSIST_AMR1_INT0 		DOS_REG_ADDR(VDEC2_ASSIST_AMR1_INT0)
#define VDEC2_ASSIST_AMR1_INT1 0x2026 	///../ucode/dos_register.h:104
#define P_VDEC2_ASSIST_AMR1_INT1 		DOS_REG_ADDR(VDEC2_ASSIST_AMR1_INT1)
#define VDEC2_ASSIST_AMR1_INT2 0x2027 	///../ucode/dos_register.h:105
#define P_VDEC2_ASSIST_AMR1_INT2 		DOS_REG_ADDR(VDEC2_ASSIST_AMR1_INT2)
#define VDEC2_ASSIST_AMR1_INT3 0x2028 	///../ucode/dos_register.h:106
#define P_VDEC2_ASSIST_AMR1_INT3 		DOS_REG_ADDR(VDEC2_ASSIST_AMR1_INT3)
#define VDEC2_ASSIST_AMR1_INT4 0x2029 	///../ucode/dos_register.h:107
#define P_VDEC2_ASSIST_AMR1_INT4 		DOS_REG_ADDR(VDEC2_ASSIST_AMR1_INT4)
#define VDEC2_ASSIST_AMR1_INT5 0x202a 	///../ucode/dos_register.h:108
#define P_VDEC2_ASSIST_AMR1_INT5 		DOS_REG_ADDR(VDEC2_ASSIST_AMR1_INT5)
#define VDEC2_ASSIST_AMR1_INT6 0x202b 	///../ucode/dos_register.h:109
#define P_VDEC2_ASSIST_AMR1_INT6 		DOS_REG_ADDR(VDEC2_ASSIST_AMR1_INT6)
#define VDEC2_ASSIST_AMR1_INT7 0x202c 	///../ucode/dos_register.h:110
#define P_VDEC2_ASSIST_AMR1_INT7 		DOS_REG_ADDR(VDEC2_ASSIST_AMR1_INT7)
#define VDEC2_ASSIST_AMR1_INT8 0x202d 	///../ucode/dos_register.h:111
#define P_VDEC2_ASSIST_AMR1_INT8 		DOS_REG_ADDR(VDEC2_ASSIST_AMR1_INT8)
#define VDEC2_ASSIST_AMR1_INT9 0x202e 	///../ucode/dos_register.h:112
#define P_VDEC2_ASSIST_AMR1_INT9 		DOS_REG_ADDR(VDEC2_ASSIST_AMR1_INT9)
#define VDEC2_ASSIST_AMR1_INTA 0x202f 	///../ucode/dos_register.h:113
#define P_VDEC2_ASSIST_AMR1_INTA 		DOS_REG_ADDR(VDEC2_ASSIST_AMR1_INTA)
#define VDEC2_ASSIST_AMR1_INTB 0x2030 	///../ucode/dos_register.h:114
#define P_VDEC2_ASSIST_AMR1_INTB 		DOS_REG_ADDR(VDEC2_ASSIST_AMR1_INTB)
#define VDEC2_ASSIST_AMR1_INTC 0x2031 	///../ucode/dos_register.h:115
#define P_VDEC2_ASSIST_AMR1_INTC 		DOS_REG_ADDR(VDEC2_ASSIST_AMR1_INTC)
#define VDEC2_ASSIST_AMR1_INTD 0x2032 	///../ucode/dos_register.h:116
#define P_VDEC2_ASSIST_AMR1_INTD 		DOS_REG_ADDR(VDEC2_ASSIST_AMR1_INTD)
#define VDEC2_ASSIST_AMR1_INTE 0x2033 	///../ucode/dos_register.h:117
#define P_VDEC2_ASSIST_AMR1_INTE 		DOS_REG_ADDR(VDEC2_ASSIST_AMR1_INTE)
#define VDEC2_ASSIST_AMR1_INTF 0x2034 	///../ucode/dos_register.h:118
#define P_VDEC2_ASSIST_AMR1_INTF 		DOS_REG_ADDR(VDEC2_ASSIST_AMR1_INTF)
#define VDEC2_ASSIST_AMR2_INT0 0x2035 	///../ucode/dos_register.h:119
#define P_VDEC2_ASSIST_AMR2_INT0 		DOS_REG_ADDR(VDEC2_ASSIST_AMR2_INT0)
#define VDEC2_ASSIST_AMR2_INT1 0x2036 	///../ucode/dos_register.h:120
#define P_VDEC2_ASSIST_AMR2_INT1 		DOS_REG_ADDR(VDEC2_ASSIST_AMR2_INT1)
#define VDEC2_ASSIST_AMR2_INT2 0x2037 	///../ucode/dos_register.h:121
#define P_VDEC2_ASSIST_AMR2_INT2 		DOS_REG_ADDR(VDEC2_ASSIST_AMR2_INT2)
#define VDEC2_ASSIST_AMR2_INT3 0x2038 	///../ucode/dos_register.h:122
#define P_VDEC2_ASSIST_AMR2_INT3 		DOS_REG_ADDR(VDEC2_ASSIST_AMR2_INT3)
#define VDEC2_ASSIST_AMR2_INT4 0x2039 	///../ucode/dos_register.h:123
#define P_VDEC2_ASSIST_AMR2_INT4 		DOS_REG_ADDR(VDEC2_ASSIST_AMR2_INT4)
#define VDEC2_ASSIST_AMR2_INT5 0x203a 	///../ucode/dos_register.h:124
#define P_VDEC2_ASSIST_AMR2_INT5 		DOS_REG_ADDR(VDEC2_ASSIST_AMR2_INT5)
#define VDEC2_ASSIST_AMR2_INT6 0x203b 	///../ucode/dos_register.h:125
#define P_VDEC2_ASSIST_AMR2_INT6 		DOS_REG_ADDR(VDEC2_ASSIST_AMR2_INT6)
#define VDEC2_ASSIST_AMR2_INT7 0x203c 	///../ucode/dos_register.h:126
#define P_VDEC2_ASSIST_AMR2_INT7 		DOS_REG_ADDR(VDEC2_ASSIST_AMR2_INT7)
#define VDEC2_ASSIST_AMR2_INT8 0x203d 	///../ucode/dos_register.h:127
#define P_VDEC2_ASSIST_AMR2_INT8 		DOS_REG_ADDR(VDEC2_ASSIST_AMR2_INT8)
#define VDEC2_ASSIST_AMR2_INT9 0x203e 	///../ucode/dos_register.h:128
#define P_VDEC2_ASSIST_AMR2_INT9 		DOS_REG_ADDR(VDEC2_ASSIST_AMR2_INT9)
#define VDEC2_ASSIST_AMR2_INTA 0x203f 	///../ucode/dos_register.h:129
#define P_VDEC2_ASSIST_AMR2_INTA 		DOS_REG_ADDR(VDEC2_ASSIST_AMR2_INTA)
#define VDEC2_ASSIST_AMR2_INTB 0x2040 	///../ucode/dos_register.h:130
#define P_VDEC2_ASSIST_AMR2_INTB 		DOS_REG_ADDR(VDEC2_ASSIST_AMR2_INTB)
#define VDEC2_ASSIST_AMR2_INTC 0x2041 	///../ucode/dos_register.h:131
#define P_VDEC2_ASSIST_AMR2_INTC 		DOS_REG_ADDR(VDEC2_ASSIST_AMR2_INTC)
#define VDEC2_ASSIST_AMR2_INTD 0x2042 	///../ucode/dos_register.h:132
#define P_VDEC2_ASSIST_AMR2_INTD 		DOS_REG_ADDR(VDEC2_ASSIST_AMR2_INTD)
#define VDEC2_ASSIST_AMR2_INTE 0x2043 	///../ucode/dos_register.h:133
#define P_VDEC2_ASSIST_AMR2_INTE 		DOS_REG_ADDR(VDEC2_ASSIST_AMR2_INTE)
#define VDEC2_ASSIST_AMR2_INTF 0x2044 	///../ucode/dos_register.h:134
#define P_VDEC2_ASSIST_AMR2_INTF 		DOS_REG_ADDR(VDEC2_ASSIST_AMR2_INTF)
#define VDEC2_ASSIST_MBX_SSEL 0x2045 	///../ucode/dos_register.h:135
#define P_VDEC2_ASSIST_MBX_SSEL 		DOS_REG_ADDR(VDEC2_ASSIST_MBX_SSEL)
#define VDEC2_ASSIST_TIMER0_LO 0x2060 	///../ucode/dos_register.h:136
#define P_VDEC2_ASSIST_TIMER0_LO 		DOS_REG_ADDR(VDEC2_ASSIST_TIMER0_LO)
#define VDEC2_ASSIST_TIMER0_HI 0x2061 	///../ucode/dos_register.h:137
#define P_VDEC2_ASSIST_TIMER0_HI 		DOS_REG_ADDR(VDEC2_ASSIST_TIMER0_HI)
#define VDEC2_ASSIST_TIMER1_LO 0x2062 	///../ucode/dos_register.h:138
#define P_VDEC2_ASSIST_TIMER1_LO 		DOS_REG_ADDR(VDEC2_ASSIST_TIMER1_LO)
#define VDEC2_ASSIST_TIMER1_HI 0x2063 	///../ucode/dos_register.h:139
#define P_VDEC2_ASSIST_TIMER1_HI 		DOS_REG_ADDR(VDEC2_ASSIST_TIMER1_HI)
#define VDEC2_ASSIST_DMA_INT 0x2064 	///../ucode/dos_register.h:140
#define P_VDEC2_ASSIST_DMA_INT 		DOS_REG_ADDR(VDEC2_ASSIST_DMA_INT)
#define VDEC2_ASSIST_DMA_INT_MSK 0x2065 	///../ucode/dos_register.h:141
#define P_VDEC2_ASSIST_DMA_INT_MSK 		DOS_REG_ADDR(VDEC2_ASSIST_DMA_INT_MSK)
#define VDEC2_ASSIST_DMA_INT2 0x2066 	///../ucode/dos_register.h:142
#define P_VDEC2_ASSIST_DMA_INT2 		DOS_REG_ADDR(VDEC2_ASSIST_DMA_INT2)
#define VDEC2_ASSIST_DMA_INT_MSK2 0x2067 	///../ucode/dos_register.h:143
#define P_VDEC2_ASSIST_DMA_INT_MSK2 		DOS_REG_ADDR(VDEC2_ASSIST_DMA_INT_MSK2)
#define VDEC2_ASSIST_MBOX0_IRQ_REG 0x2070 	///../ucode/dos_register.h:144
#define P_VDEC2_ASSIST_MBOX0_IRQ_REG 		DOS_REG_ADDR(VDEC2_ASSIST_MBOX0_IRQ_REG)
#define VDEC2_ASSIST_MBOX0_CLR_REG 0x2071 	///../ucode/dos_register.h:145
#define P_VDEC2_ASSIST_MBOX0_CLR_REG 		DOS_REG_ADDR(VDEC2_ASSIST_MBOX0_CLR_REG)
#define VDEC2_ASSIST_MBOX0_MASK 0x2072 	///../ucode/dos_register.h:146
#define P_VDEC2_ASSIST_MBOX0_MASK 		DOS_REG_ADDR(VDEC2_ASSIST_MBOX0_MASK)
#define VDEC2_ASSIST_MBOX0_FIQ_SEL 0x2073 	///../ucode/dos_register.h:147
#define P_VDEC2_ASSIST_MBOX0_FIQ_SEL 		DOS_REG_ADDR(VDEC2_ASSIST_MBOX0_FIQ_SEL)
#define VDEC2_ASSIST_MBOX1_IRQ_REG 0x2074 	///../ucode/dos_register.h:148
#define P_VDEC2_ASSIST_MBOX1_IRQ_REG 		DOS_REG_ADDR(VDEC2_ASSIST_MBOX1_IRQ_REG)
#define VDEC2_ASSIST_MBOX1_CLR_REG 0x2075 	///../ucode/dos_register.h:149
#define P_VDEC2_ASSIST_MBOX1_CLR_REG 		DOS_REG_ADDR(VDEC2_ASSIST_MBOX1_CLR_REG)
#define VDEC2_ASSIST_MBOX1_MASK 0x2076 	///../ucode/dos_register.h:150
#define P_VDEC2_ASSIST_MBOX1_MASK 		DOS_REG_ADDR(VDEC2_ASSIST_MBOX1_MASK)
#define VDEC2_ASSIST_MBOX1_FIQ_SEL 0x2077 	///../ucode/dos_register.h:151
#define P_VDEC2_ASSIST_MBOX1_FIQ_SEL 		DOS_REG_ADDR(VDEC2_ASSIST_MBOX1_FIQ_SEL)
#define VDEC2_ASSIST_MBOX2_IRQ_REG 0x2078 	///../ucode/dos_register.h:152
#define P_VDEC2_ASSIST_MBOX2_IRQ_REG 		DOS_REG_ADDR(VDEC2_ASSIST_MBOX2_IRQ_REG)
#define VDEC2_ASSIST_MBOX2_CLR_REG 0x2079 	///../ucode/dos_register.h:153
#define P_VDEC2_ASSIST_MBOX2_CLR_REG 		DOS_REG_ADDR(VDEC2_ASSIST_MBOX2_CLR_REG)
#define VDEC2_ASSIST_MBOX2_MASK 0x207a 	///../ucode/dos_register.h:154
#define P_VDEC2_ASSIST_MBOX2_MASK 		DOS_REG_ADDR(VDEC2_ASSIST_MBOX2_MASK)
#define VDEC2_ASSIST_MBOX2_FIQ_SEL 0x207b 	///../ucode/dos_register.h:155
#define P_VDEC2_ASSIST_MBOX2_FIQ_SEL 		DOS_REG_ADDR(VDEC2_ASSIST_MBOX2_FIQ_SEL)
#define HCODEC_ASSIST_MMC_CTRL0 0x1001 	///../ucode/dos_register.h:162
#define P_HCODEC_ASSIST_MMC_CTRL0 		DOS_REG_ADDR(HCODEC_ASSIST_MMC_CTRL0)
#define HCODEC_ASSIST_MMC_CTRL1 0x1002 	///../ucode/dos_register.h:163
#define P_HCODEC_ASSIST_MMC_CTRL1 		DOS_REG_ADDR(HCODEC_ASSIST_MMC_CTRL1)
#define HCODEC_MFDIN_REG0_CRST 0x1010 	///../ucode/dos_register.h:167
#define P_HCODEC_MFDIN_REG0_CRST 		DOS_REG_ADDR(HCODEC_MFDIN_REG0_CRST)
#define HCODEC_MFDIN_REG1_CTRL 0x1011 	///../ucode/dos_register.h:194
#define P_HCODEC_MFDIN_REG1_CTRL 		DOS_REG_ADDR(HCODEC_MFDIN_REG1_CTRL)
#define HCODEC_MFDIN_REG2_STAT 0x1012 	///../ucode/dos_register.h:196
#define P_HCODEC_MFDIN_REG2_STAT 		DOS_REG_ADDR(HCODEC_MFDIN_REG2_STAT)
#define HCODEC_MFDIN_REG3_CANV 0x1013 	///../ucode/dos_register.h:204
#define P_HCODEC_MFDIN_REG3_CANV 		DOS_REG_ADDR(HCODEC_MFDIN_REG3_CANV)
#define HCODEC_MFDIN_REG4_LNR0 0x1014 	///../ucode/dos_register.h:208
#define P_HCODEC_MFDIN_REG4_LNR0 		DOS_REG_ADDR(HCODEC_MFDIN_REG4_LNR0)
#define HCODEC_MFDIN_REG5_LNR1 0x1015 	///../ucode/dos_register.h:210
#define P_HCODEC_MFDIN_REG5_LNR1 		DOS_REG_ADDR(HCODEC_MFDIN_REG5_LNR1)
#define HCODEC_MFDIN_REG6_DCFG 0x1016 	///../ucode/dos_register.h:215
#define P_HCODEC_MFDIN_REG6_DCFG 		DOS_REG_ADDR(HCODEC_MFDIN_REG6_DCFG)
#define HCODEC_MFDIN_REG7_SCMD 0x1017 	///../ucode/dos_register.h:217
#define P_HCODEC_MFDIN_REG7_SCMD 		DOS_REG_ADDR(HCODEC_MFDIN_REG7_SCMD)
#define HCODEC_MFDIN_REG8_DMBL 0x1018 	///../ucode/dos_register.h:220
#define P_HCODEC_MFDIN_REG8_DMBL 		DOS_REG_ADDR(HCODEC_MFDIN_REG8_DMBL)
#define HCODEC_MFDIN_REG9_ENDN 0x1019 	///../ucode/dos_register.h:222
#define P_HCODEC_MFDIN_REG9_ENDN 		DOS_REG_ADDR(HCODEC_MFDIN_REG9_ENDN)
#define HCODEC_MFDIN_REGA_CAV1 0x101a 	///../ucode/dos_register.h:225
#define P_HCODEC_MFDIN_REGA_CAV1 		DOS_REG_ADDR(HCODEC_MFDIN_REGA_CAV1)
#define HCODEC_MFDIN_REGB_AMPC 0x101b 	///../ucode/dos_register.h:230
#define P_HCODEC_MFDIN_REGB_AMPC 		DOS_REG_ADDR(HCODEC_MFDIN_REGB_AMPC)
#define HCODEC_ASSIST_AMR1_INT0 0x1025 	///../ucode/dos_register.h:231
#define P_HCODEC_ASSIST_AMR1_INT0 		DOS_REG_ADDR(HCODEC_ASSIST_AMR1_INT0)
#define HCODEC_ASSIST_AMR1_INT1 0x1026 	///../ucode/dos_register.h:232
#define P_HCODEC_ASSIST_AMR1_INT1 		DOS_REG_ADDR(HCODEC_ASSIST_AMR1_INT1)
#define HCODEC_ASSIST_AMR1_INT2 0x1027 	///../ucode/dos_register.h:233
#define P_HCODEC_ASSIST_AMR1_INT2 		DOS_REG_ADDR(HCODEC_ASSIST_AMR1_INT2)
#define HCODEC_ASSIST_AMR1_INT3 0x1028 	///../ucode/dos_register.h:234
#define P_HCODEC_ASSIST_AMR1_INT3 		DOS_REG_ADDR(HCODEC_ASSIST_AMR1_INT3)
#define HCODEC_ASSIST_AMR1_INT4 0x1029 	///../ucode/dos_register.h:235
#define P_HCODEC_ASSIST_AMR1_INT4 		DOS_REG_ADDR(HCODEC_ASSIST_AMR1_INT4)
#define HCODEC_ASSIST_AMR1_INT5 0x102a 	///../ucode/dos_register.h:236
#define P_HCODEC_ASSIST_AMR1_INT5 		DOS_REG_ADDR(HCODEC_ASSIST_AMR1_INT5)
#define HCODEC_ASSIST_AMR1_INT6 0x102b 	///../ucode/dos_register.h:237
#define P_HCODEC_ASSIST_AMR1_INT6 		DOS_REG_ADDR(HCODEC_ASSIST_AMR1_INT6)
#define HCODEC_ASSIST_AMR1_INT7 0x102c 	///../ucode/dos_register.h:238
#define P_HCODEC_ASSIST_AMR1_INT7 		DOS_REG_ADDR(HCODEC_ASSIST_AMR1_INT7)
#define HCODEC_ASSIST_AMR1_INT8 0x102d 	///../ucode/dos_register.h:239
#define P_HCODEC_ASSIST_AMR1_INT8 		DOS_REG_ADDR(HCODEC_ASSIST_AMR1_INT8)
#define HCODEC_ASSIST_AMR1_INT9 0x102e 	///../ucode/dos_register.h:240
#define P_HCODEC_ASSIST_AMR1_INT9 		DOS_REG_ADDR(HCODEC_ASSIST_AMR1_INT9)
#define HCODEC_ASSIST_AMR1_INTA 0x102f 	///../ucode/dos_register.h:241
#define P_HCODEC_ASSIST_AMR1_INTA 		DOS_REG_ADDR(HCODEC_ASSIST_AMR1_INTA)
#define HCODEC_ASSIST_AMR1_INTB 0x1030 	///../ucode/dos_register.h:242
#define P_HCODEC_ASSIST_AMR1_INTB 		DOS_REG_ADDR(HCODEC_ASSIST_AMR1_INTB)
#define HCODEC_ASSIST_AMR1_INTC 0x1031 	///../ucode/dos_register.h:243
#define P_HCODEC_ASSIST_AMR1_INTC 		DOS_REG_ADDR(HCODEC_ASSIST_AMR1_INTC)
#define HCODEC_ASSIST_AMR1_INTD 0x1032 	///../ucode/dos_register.h:244
#define P_HCODEC_ASSIST_AMR1_INTD 		DOS_REG_ADDR(HCODEC_ASSIST_AMR1_INTD)
#define HCODEC_ASSIST_AMR1_INTE 0x1033 	///../ucode/dos_register.h:245
#define P_HCODEC_ASSIST_AMR1_INTE 		DOS_REG_ADDR(HCODEC_ASSIST_AMR1_INTE)
#define HCODEC_ASSIST_AMR1_INTF 0x1034 	///../ucode/dos_register.h:246
#define P_HCODEC_ASSIST_AMR1_INTF 		DOS_REG_ADDR(HCODEC_ASSIST_AMR1_INTF)
#define HCODEC_ASSIST_AMR2_INT0 0x1035 	///../ucode/dos_register.h:247
#define P_HCODEC_ASSIST_AMR2_INT0 		DOS_REG_ADDR(HCODEC_ASSIST_AMR2_INT0)
#define HCODEC_ASSIST_AMR2_INT1 0x1036 	///../ucode/dos_register.h:248
#define P_HCODEC_ASSIST_AMR2_INT1 		DOS_REG_ADDR(HCODEC_ASSIST_AMR2_INT1)
#define HCODEC_ASSIST_AMR2_INT2 0x1037 	///../ucode/dos_register.h:249
#define P_HCODEC_ASSIST_AMR2_INT2 		DOS_REG_ADDR(HCODEC_ASSIST_AMR2_INT2)
#define HCODEC_ASSIST_AMR2_INT3 0x1038 	///../ucode/dos_register.h:250
#define P_HCODEC_ASSIST_AMR2_INT3 		DOS_REG_ADDR(HCODEC_ASSIST_AMR2_INT3)
#define HCODEC_ASSIST_AMR2_INT4 0x1039 	///../ucode/dos_register.h:251
#define P_HCODEC_ASSIST_AMR2_INT4 		DOS_REG_ADDR(HCODEC_ASSIST_AMR2_INT4)
#define HCODEC_ASSIST_AMR2_INT5 0x103a 	///../ucode/dos_register.h:252
#define P_HCODEC_ASSIST_AMR2_INT5 		DOS_REG_ADDR(HCODEC_ASSIST_AMR2_INT5)
#define HCODEC_ASSIST_AMR2_INT6 0x103b 	///../ucode/dos_register.h:253
#define P_HCODEC_ASSIST_AMR2_INT6 		DOS_REG_ADDR(HCODEC_ASSIST_AMR2_INT6)
#define HCODEC_ASSIST_AMR2_INT7 0x103c 	///../ucode/dos_register.h:254
#define P_HCODEC_ASSIST_AMR2_INT7 		DOS_REG_ADDR(HCODEC_ASSIST_AMR2_INT7)
#define HCODEC_ASSIST_AMR2_INT8 0x103d 	///../ucode/dos_register.h:255
#define P_HCODEC_ASSIST_AMR2_INT8 		DOS_REG_ADDR(HCODEC_ASSIST_AMR2_INT8)
#define HCODEC_ASSIST_AMR2_INT9 0x103e 	///../ucode/dos_register.h:256
#define P_HCODEC_ASSIST_AMR2_INT9 		DOS_REG_ADDR(HCODEC_ASSIST_AMR2_INT9)
#define HCODEC_ASSIST_AMR2_INTA 0x103f 	///../ucode/dos_register.h:257
#define P_HCODEC_ASSIST_AMR2_INTA 		DOS_REG_ADDR(HCODEC_ASSIST_AMR2_INTA)
#define HCODEC_ASSIST_AMR2_INTB 0x1040 	///../ucode/dos_register.h:258
#define P_HCODEC_ASSIST_AMR2_INTB 		DOS_REG_ADDR(HCODEC_ASSIST_AMR2_INTB)
#define HCODEC_ASSIST_AMR2_INTC 0x1041 	///../ucode/dos_register.h:259
#define P_HCODEC_ASSIST_AMR2_INTC 		DOS_REG_ADDR(HCODEC_ASSIST_AMR2_INTC)
#define HCODEC_ASSIST_AMR2_INTD 0x1042 	///../ucode/dos_register.h:260
#define P_HCODEC_ASSIST_AMR2_INTD 		DOS_REG_ADDR(HCODEC_ASSIST_AMR2_INTD)
#define HCODEC_ASSIST_AMR2_INTE 0x1043 	///../ucode/dos_register.h:261
#define P_HCODEC_ASSIST_AMR2_INTE 		DOS_REG_ADDR(HCODEC_ASSIST_AMR2_INTE)
#define HCODEC_ASSIST_AMR2_INTF 0x1044 	///../ucode/dos_register.h:262
#define P_HCODEC_ASSIST_AMR2_INTF 		DOS_REG_ADDR(HCODEC_ASSIST_AMR2_INTF)
#define HCODEC_ASSIST_MBX_SSEL 0x1045 	///../ucode/dos_register.h:263
#define P_HCODEC_ASSIST_MBX_SSEL 		DOS_REG_ADDR(HCODEC_ASSIST_MBX_SSEL)
#define HCODEC_ASSIST_TIMER0_LO 0x1060 	///../ucode/dos_register.h:264
#define P_HCODEC_ASSIST_TIMER0_LO 		DOS_REG_ADDR(HCODEC_ASSIST_TIMER0_LO)
#define HCODEC_ASSIST_TIMER0_HI 0x1061 	///../ucode/dos_register.h:265
#define P_HCODEC_ASSIST_TIMER0_HI 		DOS_REG_ADDR(HCODEC_ASSIST_TIMER0_HI)
#define HCODEC_ASSIST_TIMER1_LO 0x1062 	///../ucode/dos_register.h:266
#define P_HCODEC_ASSIST_TIMER1_LO 		DOS_REG_ADDR(HCODEC_ASSIST_TIMER1_LO)
#define HCODEC_ASSIST_TIMER1_HI 0x1063 	///../ucode/dos_register.h:267
#define P_HCODEC_ASSIST_TIMER1_HI 		DOS_REG_ADDR(HCODEC_ASSIST_TIMER1_HI)
#define HCODEC_ASSIST_DMA_INT 0x1064 	///../ucode/dos_register.h:268
#define P_HCODEC_ASSIST_DMA_INT 		DOS_REG_ADDR(HCODEC_ASSIST_DMA_INT)
#define HCODEC_ASSIST_DMA_INT_MSK 0x1065 	///../ucode/dos_register.h:269
#define P_HCODEC_ASSIST_DMA_INT_MSK 		DOS_REG_ADDR(HCODEC_ASSIST_DMA_INT_MSK)
#define HCODEC_ASSIST_DMA_INT2 0x1066 	///../ucode/dos_register.h:270
#define P_HCODEC_ASSIST_DMA_INT2 		DOS_REG_ADDR(HCODEC_ASSIST_DMA_INT2)
#define HCODEC_ASSIST_DMA_INT_MSK2 0x1067 	///../ucode/dos_register.h:271
#define P_HCODEC_ASSIST_DMA_INT_MSK2 		DOS_REG_ADDR(HCODEC_ASSIST_DMA_INT_MSK2)
#define HCODEC_ASSIST_MBOX0_IRQ_REG 0x1070 	///../ucode/dos_register.h:272
#define P_HCODEC_ASSIST_MBOX0_IRQ_REG 		DOS_REG_ADDR(HCODEC_ASSIST_MBOX0_IRQ_REG)
#define HCODEC_ASSIST_MBOX0_CLR_REG 0x1071 	///../ucode/dos_register.h:273
#define P_HCODEC_ASSIST_MBOX0_CLR_REG 		DOS_REG_ADDR(HCODEC_ASSIST_MBOX0_CLR_REG)
#define HCODEC_ASSIST_MBOX0_MASK 0x1072 	///../ucode/dos_register.h:274
#define P_HCODEC_ASSIST_MBOX0_MASK 		DOS_REG_ADDR(HCODEC_ASSIST_MBOX0_MASK)
#define HCODEC_ASSIST_MBOX0_FIQ_SEL 0x1073 	///../ucode/dos_register.h:275
#define P_HCODEC_ASSIST_MBOX0_FIQ_SEL 		DOS_REG_ADDR(HCODEC_ASSIST_MBOX0_FIQ_SEL)
#define HCODEC_ASSIST_MBOX1_IRQ_REG 0x1074 	///../ucode/dos_register.h:276
#define P_HCODEC_ASSIST_MBOX1_IRQ_REG 		DOS_REG_ADDR(HCODEC_ASSIST_MBOX1_IRQ_REG)
#define HCODEC_ASSIST_MBOX1_CLR_REG 0x1075 	///../ucode/dos_register.h:277
#define P_HCODEC_ASSIST_MBOX1_CLR_REG 		DOS_REG_ADDR(HCODEC_ASSIST_MBOX1_CLR_REG)
#define HCODEC_ASSIST_MBOX1_MASK 0x1076 	///../ucode/dos_register.h:278
#define P_HCODEC_ASSIST_MBOX1_MASK 		DOS_REG_ADDR(HCODEC_ASSIST_MBOX1_MASK)
#define HCODEC_ASSIST_MBOX1_FIQ_SEL 0x1077 	///../ucode/dos_register.h:279
#define P_HCODEC_ASSIST_MBOX1_FIQ_SEL 		DOS_REG_ADDR(HCODEC_ASSIST_MBOX1_FIQ_SEL)
#define HCODEC_ASSIST_MBOX2_IRQ_REG 0x1078 	///../ucode/dos_register.h:280
#define P_HCODEC_ASSIST_MBOX2_IRQ_REG 		DOS_REG_ADDR(HCODEC_ASSIST_MBOX2_IRQ_REG)
#define HCODEC_ASSIST_MBOX2_CLR_REG 0x1079 	///../ucode/dos_register.h:281
#define P_HCODEC_ASSIST_MBOX2_CLR_REG 		DOS_REG_ADDR(HCODEC_ASSIST_MBOX2_CLR_REG)
#define HCODEC_ASSIST_MBOX2_MASK 0x107a 	///../ucode/dos_register.h:282
#define P_HCODEC_ASSIST_MBOX2_MASK 		DOS_REG_ADDR(HCODEC_ASSIST_MBOX2_MASK)
#define HCODEC_ASSIST_MBOX2_FIQ_SEL 0x107b 	///../ucode/dos_register.h:283
#define P_HCODEC_ASSIST_MBOX2_FIQ_SEL 		DOS_REG_ADDR(HCODEC_ASSIST_MBOX2_FIQ_SEL)
#define MC_CTRL_REG 0x0900 	///../ucode/dos_register.h:296
#define P_MC_CTRL_REG 		DOS_REG_ADDR(MC_CTRL_REG)
#define MC_MB_INFO 0x0901 	///../ucode/dos_register.h:297
#define P_MC_MB_INFO 		DOS_REG_ADDR(MC_MB_INFO)
#define MC_PIC_INFO 0x0902 	///../ucode/dos_register.h:298
#define P_MC_PIC_INFO 		DOS_REG_ADDR(MC_PIC_INFO)
#define MC_HALF_PEL_ONE 0x0903 	///../ucode/dos_register.h:299
#define P_MC_HALF_PEL_ONE 		DOS_REG_ADDR(MC_HALF_PEL_ONE)
#define MC_HALF_PEL_TWO 0x0904 	///../ucode/dos_register.h:300
#define P_MC_HALF_PEL_TWO 		DOS_REG_ADDR(MC_HALF_PEL_TWO)
#define POWER_CTL_MC 0x0905 	///../ucode/dos_register.h:301
#define P_POWER_CTL_MC 		DOS_REG_ADDR(POWER_CTL_MC)
#define MC_CMD 0x0906 	///../ucode/dos_register.h:302
#define P_MC_CMD 		DOS_REG_ADDR(MC_CMD)
#define MC_CTRL0 0x0907 	///../ucode/dos_register.h:303
#define P_MC_CTRL0 		DOS_REG_ADDR(MC_CTRL0)
#define MC_PIC_W_H 0x0908 	///../ucode/dos_register.h:304
#define P_MC_PIC_W_H 		DOS_REG_ADDR(MC_PIC_W_H)
#define MC_STATUS0 0x0909 	///../ucode/dos_register.h:305
#define P_MC_STATUS0 		DOS_REG_ADDR(MC_STATUS0)
#define MC_STATUS1 0x090a 	///../ucode/dos_register.h:306
#define P_MC_STATUS1 		DOS_REG_ADDR(MC_STATUS1)
#define MC_CTRL1 0x090b 	///../ucode/dos_register.h:307
#define P_MC_CTRL1 		DOS_REG_ADDR(MC_CTRL1)
#define MC_MIX_RATIO0 0x090c 	///../ucode/dos_register.h:308
#define P_MC_MIX_RATIO0 		DOS_REG_ADDR(MC_MIX_RATIO0)
#define MC_MIX_RATIO1 0x090d 	///../ucode/dos_register.h:309
#define P_MC_MIX_RATIO1 		DOS_REG_ADDR(MC_MIX_RATIO1)
#define MC_DP_MB_XY 0x090e 	///../ucode/dos_register.h:310
#define P_MC_DP_MB_XY 		DOS_REG_ADDR(MC_DP_MB_XY)
#define MC_OM_MB_XY 0x090f 	///../ucode/dos_register.h:311
#define P_MC_OM_MB_XY 		DOS_REG_ADDR(MC_OM_MB_XY)
#define PSCALE_RST 0x0910 	///../ucode/dos_register.h:312
#define P_PSCALE_RST 		DOS_REG_ADDR(PSCALE_RST)
#define PSCALE_CTRL 0x0911 	///../ucode/dos_register.h:313
#define P_PSCALE_CTRL 		DOS_REG_ADDR(PSCALE_CTRL)
#define PSCALE_PICI_W 0x0912 	///../ucode/dos_register.h:314
#define P_PSCALE_PICI_W 		DOS_REG_ADDR(PSCALE_PICI_W)
#define PSCALE_PICI_H 0x0913 	///../ucode/dos_register.h:315
#define P_PSCALE_PICI_H 		DOS_REG_ADDR(PSCALE_PICI_H)
#define PSCALE_PICO_W 0x0914 	///../ucode/dos_register.h:316
#define P_PSCALE_PICO_W 		DOS_REG_ADDR(PSCALE_PICO_W)
#define PSCALE_PICO_H 0x0915 	///../ucode/dos_register.h:317
#define P_PSCALE_PICO_H 		DOS_REG_ADDR(PSCALE_PICO_H)
#define PSCALE_PICO_START_X 0x0916 	///../ucode/dos_register.h:318
#define P_PSCALE_PICO_START_X 		DOS_REG_ADDR(PSCALE_PICO_START_X)
#define PSCALE_PICO_START_Y 0x0917 	///../ucode/dos_register.h:319
#define P_PSCALE_PICO_START_Y 		DOS_REG_ADDR(PSCALE_PICO_START_Y)
#define PSCALE_DUMMY 0x0918 	///../ucode/dos_register.h:320
#define P_PSCALE_DUMMY 		DOS_REG_ADDR(PSCALE_DUMMY)
#define PSCALE_FILT0_COEF0 0x0919 	///../ucode/dos_register.h:321
#define P_PSCALE_FILT0_COEF0 		DOS_REG_ADDR(PSCALE_FILT0_COEF0)
#define PSCALE_FILT0_COEF1 0x091a 	///../ucode/dos_register.h:322
#define P_PSCALE_FILT0_COEF1 		DOS_REG_ADDR(PSCALE_FILT0_COEF1)
#define PSCALE_CMD_CTRL 0x091b 	///../ucode/dos_register.h:323
#define P_PSCALE_CMD_CTRL 		DOS_REG_ADDR(PSCALE_CMD_CTRL)
#define PSCALE_CMD_BLK_X 0x091c 	///../ucode/dos_register.h:324
#define P_PSCALE_CMD_BLK_X 		DOS_REG_ADDR(PSCALE_CMD_BLK_X)
#define PSCALE_CMD_BLK_Y 0x091d 	///../ucode/dos_register.h:325
#define P_PSCALE_CMD_BLK_Y 		DOS_REG_ADDR(PSCALE_CMD_BLK_Y)
#define PSCALE_STATUS 0x091e 	///../ucode/dos_register.h:326
#define P_PSCALE_STATUS 		DOS_REG_ADDR(PSCALE_STATUS)
#define PSCALE_BMEM_ADDR 0x091f 	///../ucode/dos_register.h:327
#define P_PSCALE_BMEM_ADDR 		DOS_REG_ADDR(PSCALE_BMEM_ADDR)
#define PSCALE_BMEM_DAT 0x0920 	///../ucode/dos_register.h:328
#define P_PSCALE_BMEM_DAT 		DOS_REG_ADDR(PSCALE_BMEM_DAT)
#define PSCALE_DRAM_BUF_CTRL 0x0921 	///../ucode/dos_register.h:329
#define P_PSCALE_DRAM_BUF_CTRL 		DOS_REG_ADDR(PSCALE_DRAM_BUF_CTRL)
#define PSCALE_MCMD_CTRL 0x0922 	///../ucode/dos_register.h:330
#define P_PSCALE_MCMD_CTRL 		DOS_REG_ADDR(PSCALE_MCMD_CTRL)
#define PSCALE_MCMD_XSIZE 0x0923 	///../ucode/dos_register.h:331
#define P_PSCALE_MCMD_XSIZE 		DOS_REG_ADDR(PSCALE_MCMD_XSIZE)
#define PSCALE_MCMD_YSIZE 0x0924 	///../ucode/dos_register.h:332
#define P_PSCALE_MCMD_YSIZE 		DOS_REG_ADDR(PSCALE_MCMD_YSIZE)
#define PSCALE_RBUF_START_BLKX 0x0925 	///../ucode/dos_register.h:333
#define P_PSCALE_RBUF_START_BLKX 		DOS_REG_ADDR(PSCALE_RBUF_START_BLKX)
#define PSCALE_RBUF_START_BLKY 0x0926 	///../ucode/dos_register.h:334
#define P_PSCALE_RBUF_START_BLKY 		DOS_REG_ADDR(PSCALE_RBUF_START_BLKY)
#define PSCALE_PICO_SHIFT_XY 0x0928 	///../ucode/dos_register.h:336
#define P_PSCALE_PICO_SHIFT_XY 		DOS_REG_ADDR(PSCALE_PICO_SHIFT_XY)
#define PSCALE_CTRL1 0x0929 	///../ucode/dos_register.h:337
#define P_PSCALE_CTRL1 		DOS_REG_ADDR(PSCALE_CTRL1)
#define PSCALE_SRCKEY_CTRL0 0x092a 	///../ucode/dos_register.h:345
#define P_PSCALE_SRCKEY_CTRL0 		DOS_REG_ADDR(PSCALE_SRCKEY_CTRL0)
#define PSCALE_SRCKEY_CTRL1 0x092b 	///../ucode/dos_register.h:348
#define P_PSCALE_SRCKEY_CTRL1 		DOS_REG_ADDR(PSCALE_SRCKEY_CTRL1)
#define PSCALE_CANVAS_RD_ADDR 0x092c 	///../ucode/dos_register.h:352
#define P_PSCALE_CANVAS_RD_ADDR 		DOS_REG_ADDR(PSCALE_CANVAS_RD_ADDR)
#define PSCALE_CANVAS_WR_ADDR 0x092d 	///../ucode/dos_register.h:356
#define P_PSCALE_CANVAS_WR_ADDR 		DOS_REG_ADDR(PSCALE_CANVAS_WR_ADDR)
#define PSCALE_CTRL2 0x092e 	///../ucode/dos_register.h:360
#define P_PSCALE_CTRL2 		DOS_REG_ADDR(PSCALE_CTRL2)
#define MC_MPORT_CTRL 0x0940 	///../ucode/dos_register.h:361
#define P_MC_MPORT_CTRL 		DOS_REG_ADDR(MC_MPORT_CTRL)
#define MC_MPORT_DAT 0x0941 	///../ucode/dos_register.h:362
#define P_MC_MPORT_DAT 		DOS_REG_ADDR(MC_MPORT_DAT)
#define MC_WT_PRED_CTRL 0x0942 	///../ucode/dos_register.h:363
#define P_MC_WT_PRED_CTRL 		DOS_REG_ADDR(MC_WT_PRED_CTRL)
#define MC_MBBOT_ST_EVEN_ADDR 0x0944 	///../ucode/dos_register.h:364
#define P_MC_MBBOT_ST_EVEN_ADDR 		DOS_REG_ADDR(MC_MBBOT_ST_EVEN_ADDR)
#define MC_MBBOT_ST_ODD_ADDR 0x0945 	///../ucode/dos_register.h:365
#define P_MC_MBBOT_ST_ODD_ADDR 		DOS_REG_ADDR(MC_MBBOT_ST_ODD_ADDR)
#define MC_DPDN_MB_XY 0x0946 	///../ucode/dos_register.h:366
#define P_MC_DPDN_MB_XY 		DOS_REG_ADDR(MC_DPDN_MB_XY)
#define MC_OMDN_MB_XY 0x0947 	///../ucode/dos_register.h:367
#define P_MC_OMDN_MB_XY 		DOS_REG_ADDR(MC_OMDN_MB_XY)
#define MC_HCMDBUF_H 0x0948 	///../ucode/dos_register.h:368
#define P_MC_HCMDBUF_H 		DOS_REG_ADDR(MC_HCMDBUF_H)
#define MC_HCMDBUF_L 0x0949 	///../ucode/dos_register.h:369
#define P_MC_HCMDBUF_L 		DOS_REG_ADDR(MC_HCMDBUF_L)
#define MC_HCMD_H 0x094a 	///../ucode/dos_register.h:370
#define P_MC_HCMD_H 		DOS_REG_ADDR(MC_HCMD_H)
#define MC_HCMD_L 0x094b 	///../ucode/dos_register.h:371
#define P_MC_HCMD_L 		DOS_REG_ADDR(MC_HCMD_L)
#define MC_IDCT_DAT 0x094c 	///../ucode/dos_register.h:372
#define P_MC_IDCT_DAT 		DOS_REG_ADDR(MC_IDCT_DAT)
#define MC_CTRL_GCLK_CTRL 0x094d 	///../ucode/dos_register.h:373
#define P_MC_CTRL_GCLK_CTRL 		DOS_REG_ADDR(MC_CTRL_GCLK_CTRL)
#define MC_OTHER_GCLK_CTRL 0x094e 	///../ucode/dos_register.h:374
#define P_MC_OTHER_GCLK_CTRL 		DOS_REG_ADDR(MC_OTHER_GCLK_CTRL)
#define MC_CTRL2 0x094f 	///../ucode/dos_register.h:379
#define P_MC_CTRL2 		DOS_REG_ADDR(MC_CTRL2)
#define MDEC_PIC_DC_CTRL 0x098e 	///../ucode/dos_register.h:386
#define P_MDEC_PIC_DC_CTRL 		DOS_REG_ADDR(MDEC_PIC_DC_CTRL)
#define MDEC_PIC_DC_STATUS 0x098f 	///../ucode/dos_register.h:387
#define P_MDEC_PIC_DC_STATUS 		DOS_REG_ADDR(MDEC_PIC_DC_STATUS)
#define ANC0_CANVAS_ADDR 0x0990 	///../ucode/dos_register.h:388
#define P_ANC0_CANVAS_ADDR 		DOS_REG_ADDR(ANC0_CANVAS_ADDR)
#define ANC1_CANVAS_ADDR 0x0991 	///../ucode/dos_register.h:389
#define P_ANC1_CANVAS_ADDR 		DOS_REG_ADDR(ANC1_CANVAS_ADDR)
#define ANC2_CANVAS_ADDR 0x0992 	///../ucode/dos_register.h:390
#define P_ANC2_CANVAS_ADDR 		DOS_REG_ADDR(ANC2_CANVAS_ADDR)
#define ANC3_CANVAS_ADDR 0x0993 	///../ucode/dos_register.h:391
#define P_ANC3_CANVAS_ADDR 		DOS_REG_ADDR(ANC3_CANVAS_ADDR)
#define ANC4_CANVAS_ADDR 0x0994 	///../ucode/dos_register.h:392
#define P_ANC4_CANVAS_ADDR 		DOS_REG_ADDR(ANC4_CANVAS_ADDR)
#define ANC5_CANVAS_ADDR 0x0995 	///../ucode/dos_register.h:393
#define P_ANC5_CANVAS_ADDR 		DOS_REG_ADDR(ANC5_CANVAS_ADDR)
#define ANC6_CANVAS_ADDR 0x0996 	///../ucode/dos_register.h:394
#define P_ANC6_CANVAS_ADDR 		DOS_REG_ADDR(ANC6_CANVAS_ADDR)
#define ANC7_CANVAS_ADDR 0x0997 	///../ucode/dos_register.h:395
#define P_ANC7_CANVAS_ADDR 		DOS_REG_ADDR(ANC7_CANVAS_ADDR)
#define ANC8_CANVAS_ADDR 0x0998 	///../ucode/dos_register.h:396
#define P_ANC8_CANVAS_ADDR 		DOS_REG_ADDR(ANC8_CANVAS_ADDR)
#define ANC9_CANVAS_ADDR 0x0999 	///../ucode/dos_register.h:397
#define P_ANC9_CANVAS_ADDR 		DOS_REG_ADDR(ANC9_CANVAS_ADDR)
#define ANC10_CANVAS_ADDR 0x099a 	///../ucode/dos_register.h:398
#define P_ANC10_CANVAS_ADDR 		DOS_REG_ADDR(ANC10_CANVAS_ADDR)
#define ANC11_CANVAS_ADDR 0x099b 	///../ucode/dos_register.h:399
#define P_ANC11_CANVAS_ADDR 		DOS_REG_ADDR(ANC11_CANVAS_ADDR)
#define ANC12_CANVAS_ADDR 0x099c 	///../ucode/dos_register.h:400
#define P_ANC12_CANVAS_ADDR 		DOS_REG_ADDR(ANC12_CANVAS_ADDR)
#define ANC13_CANVAS_ADDR 0x099d 	///../ucode/dos_register.h:401
#define P_ANC13_CANVAS_ADDR 		DOS_REG_ADDR(ANC13_CANVAS_ADDR)
#define ANC14_CANVAS_ADDR 0x099e 	///../ucode/dos_register.h:402
#define P_ANC14_CANVAS_ADDR 		DOS_REG_ADDR(ANC14_CANVAS_ADDR)
#define ANC15_CANVAS_ADDR 0x099f 	///../ucode/dos_register.h:403
#define P_ANC15_CANVAS_ADDR 		DOS_REG_ADDR(ANC15_CANVAS_ADDR)
#define ANC16_CANVAS_ADDR 0x09a0 	///../ucode/dos_register.h:404
#define P_ANC16_CANVAS_ADDR 		DOS_REG_ADDR(ANC16_CANVAS_ADDR)
#define ANC17_CANVAS_ADDR 0x09a1 	///../ucode/dos_register.h:405
#define P_ANC17_CANVAS_ADDR 		DOS_REG_ADDR(ANC17_CANVAS_ADDR)
#define ANC18_CANVAS_ADDR 0x09a2 	///../ucode/dos_register.h:406
#define P_ANC18_CANVAS_ADDR 		DOS_REG_ADDR(ANC18_CANVAS_ADDR)
#define ANC19_CANVAS_ADDR 0x09a3 	///../ucode/dos_register.h:407
#define P_ANC19_CANVAS_ADDR 		DOS_REG_ADDR(ANC19_CANVAS_ADDR)
#define ANC20_CANVAS_ADDR 0x09a4 	///../ucode/dos_register.h:408
#define P_ANC20_CANVAS_ADDR 		DOS_REG_ADDR(ANC20_CANVAS_ADDR)
#define ANC21_CANVAS_ADDR 0x09a5 	///../ucode/dos_register.h:409
#define P_ANC21_CANVAS_ADDR 		DOS_REG_ADDR(ANC21_CANVAS_ADDR)
#define ANC22_CANVAS_ADDR 0x09a6 	///../ucode/dos_register.h:410
#define P_ANC22_CANVAS_ADDR 		DOS_REG_ADDR(ANC22_CANVAS_ADDR)
#define ANC23_CANVAS_ADDR 0x09a7 	///../ucode/dos_register.h:411
#define P_ANC23_CANVAS_ADDR 		DOS_REG_ADDR(ANC23_CANVAS_ADDR)
#define ANC24_CANVAS_ADDR 0x09a8 	///../ucode/dos_register.h:412
#define P_ANC24_CANVAS_ADDR 		DOS_REG_ADDR(ANC24_CANVAS_ADDR)
#define ANC25_CANVAS_ADDR 0x09a9 	///../ucode/dos_register.h:413
#define P_ANC25_CANVAS_ADDR 		DOS_REG_ADDR(ANC25_CANVAS_ADDR)
#define ANC26_CANVAS_ADDR 0x09aa 	///../ucode/dos_register.h:414
#define P_ANC26_CANVAS_ADDR 		DOS_REG_ADDR(ANC26_CANVAS_ADDR)
#define ANC27_CANVAS_ADDR 0x09ab 	///../ucode/dos_register.h:415
#define P_ANC27_CANVAS_ADDR 		DOS_REG_ADDR(ANC27_CANVAS_ADDR)
#define ANC28_CANVAS_ADDR 0x09ac 	///../ucode/dos_register.h:416
#define P_ANC28_CANVAS_ADDR 		DOS_REG_ADDR(ANC28_CANVAS_ADDR)
#define ANC29_CANVAS_ADDR 0x09ad 	///../ucode/dos_register.h:417
#define P_ANC29_CANVAS_ADDR 		DOS_REG_ADDR(ANC29_CANVAS_ADDR)
#define ANC30_CANVAS_ADDR 0x09ae 	///../ucode/dos_register.h:418
#define P_ANC30_CANVAS_ADDR 		DOS_REG_ADDR(ANC30_CANVAS_ADDR)
#define ANC31_CANVAS_ADDR 0x09af 	///../ucode/dos_register.h:419
#define P_ANC31_CANVAS_ADDR 		DOS_REG_ADDR(ANC31_CANVAS_ADDR)
#define DBKR_CANVAS_ADDR 0x09b0 	///../ucode/dos_register.h:420
#define P_DBKR_CANVAS_ADDR 		DOS_REG_ADDR(DBKR_CANVAS_ADDR)
#define DBKW_CANVAS_ADDR 0x09b1 	///../ucode/dos_register.h:421
#define P_DBKW_CANVAS_ADDR 		DOS_REG_ADDR(DBKW_CANVAS_ADDR)
#define REC_CANVAS_ADDR 0x09b2 	///../ucode/dos_register.h:422
#define P_REC_CANVAS_ADDR 		DOS_REG_ADDR(REC_CANVAS_ADDR)
#define CURR_CANVAS_CTRL 0x09b3 	///../ucode/dos_register.h:425
#define P_CURR_CANVAS_CTRL 		DOS_REG_ADDR(CURR_CANVAS_CTRL)
#define MDEC_PIC_DC_THRESH 0x09b8 	///../ucode/dos_register.h:426
#define P_MDEC_PIC_DC_THRESH 		DOS_REG_ADDR(MDEC_PIC_DC_THRESH)
#define MDEC_PICR_BUF_STATUS 0x09b9 	///../ucode/dos_register.h:427
#define P_MDEC_PICR_BUF_STATUS 		DOS_REG_ADDR(MDEC_PICR_BUF_STATUS)
#define MDEC_PICW_BUF_STATUS 0x09ba 	///../ucode/dos_register.h:428
#define P_MDEC_PICW_BUF_STATUS 		DOS_REG_ADDR(MDEC_PICW_BUF_STATUS)
#define MCW_DBLK_WRRSP_CNT 0x09bb 	///../ucode/dos_register.h:429
#define P_MCW_DBLK_WRRSP_CNT 		DOS_REG_ADDR(MCW_DBLK_WRRSP_CNT)
#define MC_MBBOT_WRRSP_CNT 0x09bc 	///../ucode/dos_register.h:430
#define P_MC_MBBOT_WRRSP_CNT 		DOS_REG_ADDR(MC_MBBOT_WRRSP_CNT)
#define MDEC_PICW_BUF2_STATUS 0x09bd 	///../ucode/dos_register.h:431
#define P_MDEC_PICW_BUF2_STATUS 		DOS_REG_ADDR(MDEC_PICW_BUF2_STATUS)
#define WRRSP_FIFO_PICW_DBK 0x09be 	///../ucode/dos_register.h:432
#define P_WRRSP_FIFO_PICW_DBK 		DOS_REG_ADDR(WRRSP_FIFO_PICW_DBK)
#define WRRSP_FIFO_PICW_MC 0x09bf 	///../ucode/dos_register.h:433
#define P_WRRSP_FIFO_PICW_MC 		DOS_REG_ADDR(WRRSP_FIFO_PICW_MC)
#define AV_SCRATCH_0 0x09c0 	///../ucode/dos_register.h:434
#define P_AV_SCRATCH_0 		DOS_REG_ADDR(AV_SCRATCH_0)
#define AV_SCRATCH_1 0x09c1 	///../ucode/dos_register.h:435
#define P_AV_SCRATCH_1 		DOS_REG_ADDR(AV_SCRATCH_1)
#define AV_SCRATCH_2 0x09c2 	///../ucode/dos_register.h:436
#define P_AV_SCRATCH_2 		DOS_REG_ADDR(AV_SCRATCH_2)
#define AV_SCRATCH_3 0x09c3 	///../ucode/dos_register.h:437
#define P_AV_SCRATCH_3 		DOS_REG_ADDR(AV_SCRATCH_3)
#define AV_SCRATCH_4 0x09c4 	///../ucode/dos_register.h:438
#define P_AV_SCRATCH_4 		DOS_REG_ADDR(AV_SCRATCH_4)
#define AV_SCRATCH_5 0x09c5 	///../ucode/dos_register.h:439
#define P_AV_SCRATCH_5 		DOS_REG_ADDR(AV_SCRATCH_5)
#define AV_SCRATCH_6 0x09c6 	///../ucode/dos_register.h:440
#define P_AV_SCRATCH_6 		DOS_REG_ADDR(AV_SCRATCH_6)
#define AV_SCRATCH_7 0x09c7 	///../ucode/dos_register.h:441
#define P_AV_SCRATCH_7 		DOS_REG_ADDR(AV_SCRATCH_7)
#define AV_SCRATCH_8 0x09c8 	///../ucode/dos_register.h:442
#define P_AV_SCRATCH_8 		DOS_REG_ADDR(AV_SCRATCH_8)
#define AV_SCRATCH_9 0x09c9 	///../ucode/dos_register.h:443
#define P_AV_SCRATCH_9 		DOS_REG_ADDR(AV_SCRATCH_9)
#define AV_SCRATCH_A 0x09ca 	///../ucode/dos_register.h:444
#define P_AV_SCRATCH_A 		DOS_REG_ADDR(AV_SCRATCH_A)
#define AV_SCRATCH_B 0x09cb 	///../ucode/dos_register.h:445
#define P_AV_SCRATCH_B 		DOS_REG_ADDR(AV_SCRATCH_B)
#define AV_SCRATCH_C 0x09cc 	///../ucode/dos_register.h:446
#define P_AV_SCRATCH_C 		DOS_REG_ADDR(AV_SCRATCH_C)
#define AV_SCRATCH_D 0x09cd 	///../ucode/dos_register.h:447
#define P_AV_SCRATCH_D 		DOS_REG_ADDR(AV_SCRATCH_D)
#define AV_SCRATCH_E 0x09ce 	///../ucode/dos_register.h:448
#define P_AV_SCRATCH_E 		DOS_REG_ADDR(AV_SCRATCH_E)
#define AV_SCRATCH_F 0x09cf 	///../ucode/dos_register.h:449
#define P_AV_SCRATCH_F 		DOS_REG_ADDR(AV_SCRATCH_F)
#define AV_SCRATCH_G 0x09d0 	///../ucode/dos_register.h:450
#define P_AV_SCRATCH_G 		DOS_REG_ADDR(AV_SCRATCH_G)
#define AV_SCRATCH_H 0x09d1 	///../ucode/dos_register.h:451
#define P_AV_SCRATCH_H 		DOS_REG_ADDR(AV_SCRATCH_H)
#define AV_SCRATCH_I 0x09d2 	///../ucode/dos_register.h:452
#define P_AV_SCRATCH_I 		DOS_REG_ADDR(AV_SCRATCH_I)
#define AV_SCRATCH_J 0x09d3 	///../ucode/dos_register.h:453
#define P_AV_SCRATCH_J 		DOS_REG_ADDR(AV_SCRATCH_J)
#define AV_SCRATCH_K 0x09d4 	///../ucode/dos_register.h:454
#define P_AV_SCRATCH_K 		DOS_REG_ADDR(AV_SCRATCH_K)
#define AV_SCRATCH_L 0x09d5 	///../ucode/dos_register.h:455
#define P_AV_SCRATCH_L 		DOS_REG_ADDR(AV_SCRATCH_L)
#define AV_SCRATCH_M 0x09d6 	///../ucode/dos_register.h:456
#define P_AV_SCRATCH_M 		DOS_REG_ADDR(AV_SCRATCH_M)
#define AV_SCRATCH_N 0x09d7 	///../ucode/dos_register.h:457
#define P_AV_SCRATCH_N 		DOS_REG_ADDR(AV_SCRATCH_N)
#define WRRSP_CO_MB 0x09d8 	///../ucode/dos_register.h:461
#define P_WRRSP_CO_MB 		DOS_REG_ADDR(WRRSP_CO_MB)
#define WRRSP_DCAC 0x09d9 	///../ucode/dos_register.h:465
#define P_WRRSP_DCAC 		DOS_REG_ADDR(WRRSP_DCAC)
#define WRRSP_VLD 0x09da 	///../ucode/dos_register.h:467
#define P_WRRSP_VLD 		DOS_REG_ADDR(WRRSP_VLD)
#define MDEC_DOUBLEW_CFG0 0x09db 	///../ucode/dos_register.h:483
#define P_MDEC_DOUBLEW_CFG0 		DOS_REG_ADDR(MDEC_DOUBLEW_CFG0)
#define MDEC_DOUBLEW_CFG1 0x09dc 	///../ucode/dos_register.h:489
#define P_MDEC_DOUBLEW_CFG1 		DOS_REG_ADDR(MDEC_DOUBLEW_CFG1)
#define MDEC_DOUBLEW_CFG2 0x09dd 	///../ucode/dos_register.h:494
#define P_MDEC_DOUBLEW_CFG2 		DOS_REG_ADDR(MDEC_DOUBLEW_CFG2)
#define MDEC_DOUBLEW_CFG3 0x09de 	///../ucode/dos_register.h:496
#define P_MDEC_DOUBLEW_CFG3 		DOS_REG_ADDR(MDEC_DOUBLEW_CFG3)
#define MDEC_DOUBLEW_CFG4 0x09df 	///../ucode/dos_register.h:498
#define P_MDEC_DOUBLEW_CFG4 		DOS_REG_ADDR(MDEC_DOUBLEW_CFG4)
#define MDEC_DOUBLEW_CFG5 0x09e0 	///../ucode/dos_register.h:501
#define P_MDEC_DOUBLEW_CFG5 		DOS_REG_ADDR(MDEC_DOUBLEW_CFG5)
#define MDEC_DOUBLEW_CFG6 0x09e1 	///../ucode/dos_register.h:503
#define P_MDEC_DOUBLEW_CFG6 		DOS_REG_ADDR(MDEC_DOUBLEW_CFG6)
#define MDEC_DOUBLEW_CFG7 0x09e2 	///../ucode/dos_register.h:505
#define P_MDEC_DOUBLEW_CFG7 		DOS_REG_ADDR(MDEC_DOUBLEW_CFG7)
#define MDEC_DOUBLEW_STATUS 0x09e3 	///../ucode/dos_register.h:509
#define P_MDEC_DOUBLEW_STATUS 		DOS_REG_ADDR(MDEC_DOUBLEW_STATUS)
#define DBLK_RST 0x0950 	///../ucode/dos_register.h:548
#define P_DBLK_RST 		DOS_REG_ADDR(DBLK_RST)
#define DBLK_CTRL 0x0951 	///../ucode/dos_register.h:549
#define P_DBLK_CTRL 		DOS_REG_ADDR(DBLK_CTRL)
#define DBLK_MB_WID_HEIGHT 0x0952 	///../ucode/dos_register.h:550
#define P_DBLK_MB_WID_HEIGHT 		DOS_REG_ADDR(DBLK_MB_WID_HEIGHT)
#define DBLK_STATUS 0x0953 	///../ucode/dos_register.h:551
#define P_DBLK_STATUS 		DOS_REG_ADDR(DBLK_STATUS)
#define DBLK_CMD_CTRL 0x0954 	///../ucode/dos_register.h:552
#define P_DBLK_CMD_CTRL 		DOS_REG_ADDR(DBLK_CMD_CTRL)
#define DBLK_MB_XY 0x0955 	///../ucode/dos_register.h:553
#define P_DBLK_MB_XY 		DOS_REG_ADDR(DBLK_MB_XY)
#define DBLK_QP 0x0956 	///../ucode/dos_register.h:554
#define P_DBLK_QP 		DOS_REG_ADDR(DBLK_QP)
#define DBLK_Y_BHFILT 0x0957 	///../ucode/dos_register.h:555
#define P_DBLK_Y_BHFILT 		DOS_REG_ADDR(DBLK_Y_BHFILT)
#define DBLK_Y_BHFILT_HIGH 0x0958 	///../ucode/dos_register.h:556
#define P_DBLK_Y_BHFILT_HIGH 		DOS_REG_ADDR(DBLK_Y_BHFILT_HIGH)
#define DBLK_Y_BVFILT 0x0959 	///../ucode/dos_register.h:557
#define P_DBLK_Y_BVFILT 		DOS_REG_ADDR(DBLK_Y_BVFILT)
#define DBLK_CB_BFILT 0x095a 	///../ucode/dos_register.h:558
#define P_DBLK_CB_BFILT 		DOS_REG_ADDR(DBLK_CB_BFILT)
#define DBLK_CR_BFILT 0x095b 	///../ucode/dos_register.h:559
#define P_DBLK_CR_BFILT 		DOS_REG_ADDR(DBLK_CR_BFILT)
#define DBLK_Y_HFILT 0x095c 	///../ucode/dos_register.h:560
#define P_DBLK_Y_HFILT 		DOS_REG_ADDR(DBLK_Y_HFILT)
#define DBLK_Y_HFILT_HIGH 0x095d 	///../ucode/dos_register.h:561
#define P_DBLK_Y_HFILT_HIGH 		DOS_REG_ADDR(DBLK_Y_HFILT_HIGH)
#define DBLK_Y_VFILT 0x095e 	///../ucode/dos_register.h:562
#define P_DBLK_Y_VFILT 		DOS_REG_ADDR(DBLK_Y_VFILT)
#define DBLK_CB_FILT 0x095f 	///../ucode/dos_register.h:563
#define P_DBLK_CB_FILT 		DOS_REG_ADDR(DBLK_CB_FILT)
#define DBLK_CR_FILT 0x0960 	///../ucode/dos_register.h:564
#define P_DBLK_CR_FILT 		DOS_REG_ADDR(DBLK_CR_FILT)
#define DBLK_BETAX_QP_SEL 0x0961 	///../ucode/dos_register.h:565
#define P_DBLK_BETAX_QP_SEL 		DOS_REG_ADDR(DBLK_BETAX_QP_SEL)
#define DBLK_CLIP_CTRL0 0x0962 	///../ucode/dos_register.h:566
#define P_DBLK_CLIP_CTRL0 		DOS_REG_ADDR(DBLK_CLIP_CTRL0)
#define DBLK_CLIP_CTRL1 0x0963 	///../ucode/dos_register.h:567
#define P_DBLK_CLIP_CTRL1 		DOS_REG_ADDR(DBLK_CLIP_CTRL1)
#define DBLK_CLIP_CTRL2 0x0964 	///../ucode/dos_register.h:568
#define P_DBLK_CLIP_CTRL2 		DOS_REG_ADDR(DBLK_CLIP_CTRL2)
#define DBLK_CLIP_CTRL3 0x0965 	///../ucode/dos_register.h:569
#define P_DBLK_CLIP_CTRL3 		DOS_REG_ADDR(DBLK_CLIP_CTRL3)
#define DBLK_CLIP_CTRL4 0x0966 	///../ucode/dos_register.h:570
#define P_DBLK_CLIP_CTRL4 		DOS_REG_ADDR(DBLK_CLIP_CTRL4)
#define DBLK_CLIP_CTRL5 0x0967 	///../ucode/dos_register.h:571
#define P_DBLK_CLIP_CTRL5 		DOS_REG_ADDR(DBLK_CLIP_CTRL5)
#define DBLK_CLIP_CTRL6 0x0968 	///../ucode/dos_register.h:572
#define P_DBLK_CLIP_CTRL6 		DOS_REG_ADDR(DBLK_CLIP_CTRL6)
#define DBLK_CLIP_CTRL7 0x0969 	///../ucode/dos_register.h:573
#define P_DBLK_CLIP_CTRL7 		DOS_REG_ADDR(DBLK_CLIP_CTRL7)
#define DBLK_CLIP_CTRL8 0x096a 	///../ucode/dos_register.h:574
#define P_DBLK_CLIP_CTRL8 		DOS_REG_ADDR(DBLK_CLIP_CTRL8)
#define DBLK_STATUS1 0x096b 	///../ucode/dos_register.h:575
#define P_DBLK_STATUS1 		DOS_REG_ADDR(DBLK_STATUS1)
#define DBLK_GCLK_FREE 0x096c 	///../ucode/dos_register.h:576
#define P_DBLK_GCLK_FREE 		DOS_REG_ADDR(DBLK_GCLK_FREE)
#define DBLK_GCLK_OFF 0x096d 	///../ucode/dos_register.h:577
#define P_DBLK_GCLK_OFF 		DOS_REG_ADDR(DBLK_GCLK_OFF)
#define DBLK_AVSFLAGS 0x096e 	///../ucode/dos_register.h:578
#define P_DBLK_AVSFLAGS 		DOS_REG_ADDR(DBLK_AVSFLAGS)
#define DBLK_CBPY 0x0970 	///../ucode/dos_register.h:580
#define P_DBLK_CBPY 		DOS_REG_ADDR(DBLK_CBPY)
#define DBLK_CBPY_ADJ 0x0971 	///../ucode/dos_register.h:584
#define P_DBLK_CBPY_ADJ 		DOS_REG_ADDR(DBLK_CBPY_ADJ)
#define DBLK_CBPC 0x0972 	///../ucode/dos_register.h:586
#define P_DBLK_CBPC 		DOS_REG_ADDR(DBLK_CBPC)
#define DBLK_CBPC_ADJ 0x0973 	///../ucode/dos_register.h:594
#define P_DBLK_CBPC_ADJ 		DOS_REG_ADDR(DBLK_CBPC_ADJ)
#define DBLK_VHMVD 0x0974 	///../ucode/dos_register.h:597
#define P_DBLK_VHMVD 		DOS_REG_ADDR(DBLK_VHMVD)
#define DBLK_STRONG 0x0975 	///../ucode/dos_register.h:611
#define P_DBLK_STRONG 		DOS_REG_ADDR(DBLK_STRONG)
#define DBLK_RV8_QUANT 0x0976 	///../ucode/dos_register.h:615
#define P_DBLK_RV8_QUANT 		DOS_REG_ADDR(DBLK_RV8_QUANT)
#define DBLK_CBUS_HCMD2 0x0977 	///../ucode/dos_register.h:616
#define P_DBLK_CBUS_HCMD2 		DOS_REG_ADDR(DBLK_CBUS_HCMD2)
#define DBLK_CBUS_HCMD1 0x0978 	///../ucode/dos_register.h:617
#define P_DBLK_CBUS_HCMD1 		DOS_REG_ADDR(DBLK_CBUS_HCMD1)
#define DBLK_CBUS_HCMD0 0x0979 	///../ucode/dos_register.h:618
#define P_DBLK_CBUS_HCMD0 		DOS_REG_ADDR(DBLK_CBUS_HCMD0)
#define DBLK_VLD_HCMD2 0x097a 	///../ucode/dos_register.h:619
#define P_DBLK_VLD_HCMD2 		DOS_REG_ADDR(DBLK_VLD_HCMD2)
#define DBLK_VLD_HCMD1 0x097b 	///../ucode/dos_register.h:620
#define P_DBLK_VLD_HCMD1 		DOS_REG_ADDR(DBLK_VLD_HCMD1)
#define DBLK_VLD_HCMD0 0x097c 	///../ucode/dos_register.h:621
#define P_DBLK_VLD_HCMD0 		DOS_REG_ADDR(DBLK_VLD_HCMD0)
#define DBLK_OST_YBASE 0x097d 	///../ucode/dos_register.h:622
#define P_DBLK_OST_YBASE 		DOS_REG_ADDR(DBLK_OST_YBASE)
#define DBLK_OST_CBCRDIFF 0x097e 	///../ucode/dos_register.h:623
#define P_DBLK_OST_CBCRDIFF 		DOS_REG_ADDR(DBLK_OST_CBCRDIFF)
#define DBLK_CTRL1 0x097f 	///../ucode/dos_register.h:626
#define P_DBLK_CTRL1 		DOS_REG_ADDR(DBLK_CTRL1)
#define MCRCC_CTL1 0x0980 	///../ucode/dos_register.h:632
#define P_MCRCC_CTL1 		DOS_REG_ADDR(MCRCC_CTL1)
#define MCRCC_CTL2 0x0981 	///../ucode/dos_register.h:638
#define P_MCRCC_CTL2 		DOS_REG_ADDR(MCRCC_CTL2)
#define MCRCC_CTL3 0x0982 	///../ucode/dos_register.h:644
#define P_MCRCC_CTL3 		DOS_REG_ADDR(MCRCC_CTL3)
#define GCLK_EN 0x0983 	///../ucode/dos_register.h:657
#define P_GCLK_EN 		DOS_REG_ADDR(GCLK_EN)
#define MDEC_SW_RESET 0x0984 	///../ucode/dos_register.h:672
#define P_MDEC_SW_RESET 		DOS_REG_ADDR(MDEC_SW_RESET)
#define VLD_STATUS_CTRL 0x0c00 	///../ucode/dos_register.h:689
#define P_VLD_STATUS_CTRL 		DOS_REG_ADDR(VLD_STATUS_CTRL)
#define MPEG1_2_REG 0x0c01 	///../ucode/dos_register.h:699
#define P_MPEG1_2_REG 		DOS_REG_ADDR(MPEG1_2_REG)
#define F_CODE_REG 0x0c02 	///../ucode/dos_register.h:700
#define P_F_CODE_REG 		DOS_REG_ADDR(F_CODE_REG)
#define PIC_HEAD_INFO 0x0c03 	///../ucode/dos_register.h:701
#define P_PIC_HEAD_INFO 		DOS_REG_ADDR(PIC_HEAD_INFO)
#define SLICE_VER_POS_PIC_TYPE 0x0c04 	///../ucode/dos_register.h:702
#define P_SLICE_VER_POS_PIC_TYPE 		DOS_REG_ADDR(SLICE_VER_POS_PIC_TYPE)
#define QP_VALUE_REG 0x0c05 	///../ucode/dos_register.h:703
#define P_QP_VALUE_REG 		DOS_REG_ADDR(QP_VALUE_REG)
#define MBA_INC 0x0c06 	///../ucode/dos_register.h:704
#define P_MBA_INC 		DOS_REG_ADDR(MBA_INC)
#define MB_MOTION_MODE 0x0c07 	///../ucode/dos_register.h:705
#define P_MB_MOTION_MODE 		DOS_REG_ADDR(MB_MOTION_MODE)
#define POWER_CTL_VLD 0x0c08 	///../ucode/dos_register.h:713
#define P_POWER_CTL_VLD 		DOS_REG_ADDR(POWER_CTL_VLD)
#define MB_WIDTH 0x0c09 	///../ucode/dos_register.h:714
#define P_MB_WIDTH 		DOS_REG_ADDR(MB_WIDTH)
#define SLICE_QP 0x0c0a 	///../ucode/dos_register.h:715
#define P_SLICE_QP 		DOS_REG_ADDR(SLICE_QP)
#define PRE_START_CODE 0x0c0b 	///../ucode/dos_register.h:717
#define P_PRE_START_CODE 		DOS_REG_ADDR(PRE_START_CODE)
#define SLICE_START_BYTE_01 0x0c0c 	///../ucode/dos_register.h:718
#define P_SLICE_START_BYTE_01 		DOS_REG_ADDR(SLICE_START_BYTE_01)
#define SLICE_START_BYTE_23 0x0c0d 	///../ucode/dos_register.h:719
#define P_SLICE_START_BYTE_23 		DOS_REG_ADDR(SLICE_START_BYTE_23)
#define RESYNC_MARKER_LENGTH 0x0c0e 	///../ucode/dos_register.h:720
#define P_RESYNC_MARKER_LENGTH 		DOS_REG_ADDR(RESYNC_MARKER_LENGTH)
#define DECODER_BUFFER_INFO 0x0c0f 	///../ucode/dos_register.h:724
#define P_DECODER_BUFFER_INFO 		DOS_REG_ADDR(DECODER_BUFFER_INFO)
#define FST_FOR_MV_X 0x0c10 	///../ucode/dos_register.h:725
#define P_FST_FOR_MV_X 		DOS_REG_ADDR(FST_FOR_MV_X)
#define FST_FOR_MV_Y 0x0c11 	///../ucode/dos_register.h:726
#define P_FST_FOR_MV_Y 		DOS_REG_ADDR(FST_FOR_MV_Y)
#define SCD_FOR_MV_X 0x0c12 	///../ucode/dos_register.h:727
#define P_SCD_FOR_MV_X 		DOS_REG_ADDR(SCD_FOR_MV_X)
#define SCD_FOR_MV_Y 0x0c13 	///../ucode/dos_register.h:728
#define P_SCD_FOR_MV_Y 		DOS_REG_ADDR(SCD_FOR_MV_Y)
#define FST_BAK_MV_X 0x0c14 	///../ucode/dos_register.h:729
#define P_FST_BAK_MV_X 		DOS_REG_ADDR(FST_BAK_MV_X)
#define FST_BAK_MV_Y 0x0c15 	///../ucode/dos_register.h:730
#define P_FST_BAK_MV_Y 		DOS_REG_ADDR(FST_BAK_MV_Y)
#define SCD_BAK_MV_X 0x0c16 	///../ucode/dos_register.h:731
#define P_SCD_BAK_MV_X 		DOS_REG_ADDR(SCD_BAK_MV_X)
#define SCD_BAK_MV_Y 0x0c17 	///../ucode/dos_register.h:732
#define P_SCD_BAK_MV_Y 		DOS_REG_ADDR(SCD_BAK_MV_Y)
#define VLD_DECODE_CONTROL 0x0c18 	///../ucode/dos_register.h:738
#define P_VLD_DECODE_CONTROL 		DOS_REG_ADDR(VLD_DECODE_CONTROL)
#define VLD_REVERVED_19 0x0c19 	///../ucode/dos_register.h:739
#define P_VLD_REVERVED_19 		DOS_REG_ADDR(VLD_REVERVED_19)
#define VIFF_BIT_CNT 0x0c1a 	///../ucode/dos_register.h:740
#define P_VIFF_BIT_CNT 		DOS_REG_ADDR(VIFF_BIT_CNT)
#define BYTE_ALIGN_PEAK_HI 0x0c1b 	///../ucode/dos_register.h:741
#define P_BYTE_ALIGN_PEAK_HI 		DOS_REG_ADDR(BYTE_ALIGN_PEAK_HI)
#define BYTE_ALIGN_PEAK_LO 0x0c1c 	///../ucode/dos_register.h:742
#define P_BYTE_ALIGN_PEAK_LO 		DOS_REG_ADDR(BYTE_ALIGN_PEAK_LO)
#define NEXT_ALIGN_PEAK 0x0c1d 	///../ucode/dos_register.h:743
#define P_NEXT_ALIGN_PEAK 		DOS_REG_ADDR(NEXT_ALIGN_PEAK)
#define VC1_CONTROL_REG 0x0c1e 	///../ucode/dos_register.h:759
#define P_VC1_CONTROL_REG 		DOS_REG_ADDR(VC1_CONTROL_REG)
#define PMV1_X 0x0c20 	///../ucode/dos_register.h:760
#define P_PMV1_X 		DOS_REG_ADDR(PMV1_X)
#define PMV1_Y 0x0c21 	///../ucode/dos_register.h:761
#define P_PMV1_Y 		DOS_REG_ADDR(PMV1_Y)
#define PMV2_X 0x0c22 	///../ucode/dos_register.h:762
#define P_PMV2_X 		DOS_REG_ADDR(PMV2_X)
#define PMV2_Y 0x0c23 	///../ucode/dos_register.h:763
#define P_PMV2_Y 		DOS_REG_ADDR(PMV2_Y)
#define PMV3_X 0x0c24 	///../ucode/dos_register.h:764
#define P_PMV3_X 		DOS_REG_ADDR(PMV3_X)
#define PMV3_Y 0x0c25 	///../ucode/dos_register.h:765
#define P_PMV3_Y 		DOS_REG_ADDR(PMV3_Y)
#define PMV4_X 0x0c26 	///../ucode/dos_register.h:766
#define P_PMV4_X 		DOS_REG_ADDR(PMV4_X)
#define PMV4_Y 0x0c27 	///../ucode/dos_register.h:767
#define P_PMV4_Y 		DOS_REG_ADDR(PMV4_Y)
#define M4_TABLE_SELECT 0x0c28 	///../ucode/dos_register.h:774
#define P_M4_TABLE_SELECT 		DOS_REG_ADDR(M4_TABLE_SELECT)
#define M4_CONTROL_REG 0x0c29 	///../ucode/dos_register.h:775
#define P_M4_CONTROL_REG 		DOS_REG_ADDR(M4_CONTROL_REG)
#define BLOCK_NUM 0x0c2a 	///../ucode/dos_register.h:776
#define P_BLOCK_NUM 		DOS_REG_ADDR(BLOCK_NUM)
#define PATTERN_CODE 0x0c2b 	///../ucode/dos_register.h:777
#define P_PATTERN_CODE 		DOS_REG_ADDR(PATTERN_CODE)
#define MB_INFO 0x0c2c 	///../ucode/dos_register.h:778
#define P_MB_INFO 		DOS_REG_ADDR(MB_INFO)
#define VLD_DC_PRED 0x0c2d 	///../ucode/dos_register.h:779
#define P_VLD_DC_PRED 		DOS_REG_ADDR(VLD_DC_PRED)
#define VLD_ERROR_MASK 0x0c2e 	///../ucode/dos_register.h:780
#define P_VLD_ERROR_MASK 		DOS_REG_ADDR(VLD_ERROR_MASK)
#define VLD_DC_PRED_C 0x0c2f 	///../ucode/dos_register.h:781
#define P_VLD_DC_PRED_C 		DOS_REG_ADDR(VLD_DC_PRED_C)
#define LAST_SLICE_MV_ADDR 0x0c30 	///../ucode/dos_register.h:782
#define P_LAST_SLICE_MV_ADDR 		DOS_REG_ADDR(LAST_SLICE_MV_ADDR)
#define LAST_MVX 0x0c31 	///../ucode/dos_register.h:783
#define P_LAST_MVX 		DOS_REG_ADDR(LAST_MVX)
#define LAST_MVY 0x0c32 	///../ucode/dos_register.h:784
#define P_LAST_MVY 		DOS_REG_ADDR(LAST_MVY)
#define VLD_C38 0x0c38 	///../ucode/dos_register.h:785
#define P_VLD_C38 		DOS_REG_ADDR(VLD_C38)
#define VLD_C39 0x0c39 	///../ucode/dos_register.h:786
#define P_VLD_C39 		DOS_REG_ADDR(VLD_C39)
#define VLD_STATUS 0x0c3a 	///../ucode/dos_register.h:787
#define P_VLD_STATUS 		DOS_REG_ADDR(VLD_STATUS)
#define VLD_SHIFT_STATUS 0x0c3b 	///../ucode/dos_register.h:788
#define P_VLD_SHIFT_STATUS 		DOS_REG_ADDR(VLD_SHIFT_STATUS)
#define VOFF_STATUS 0x0c3c 	///../ucode/dos_register.h:790
#define P_VOFF_STATUS 		DOS_REG_ADDR(VOFF_STATUS)
#define VLD_C3D 0x0c3d 	///../ucode/dos_register.h:791
#define P_VLD_C3D 		DOS_REG_ADDR(VLD_C3D)
#define VLD_DBG_INDEX 0x0c3e 	///../ucode/dos_register.h:792
#define P_VLD_DBG_INDEX 		DOS_REG_ADDR(VLD_DBG_INDEX)
#define VLD_DBG_DATA 0x0c3f 	///../ucode/dos_register.h:868
#define P_VLD_DBG_DATA 		DOS_REG_ADDR(VLD_DBG_DATA)
#define VLD_MEM_VIFIFO_START_PTR 0x0c40 	///../ucode/dos_register.h:875
#define P_VLD_MEM_VIFIFO_START_PTR 		DOS_REG_ADDR(VLD_MEM_VIFIFO_START_PTR)
#define VLD_MEM_VIFIFO_CURR_PTR 0x0c41 	///../ucode/dos_register.h:879
#define P_VLD_MEM_VIFIFO_CURR_PTR 		DOS_REG_ADDR(VLD_MEM_VIFIFO_CURR_PTR)
#define VLD_MEM_VIFIFO_END_PTR 0x0c42 	///../ucode/dos_register.h:880
#define P_VLD_MEM_VIFIFO_END_PTR 		DOS_REG_ADDR(VLD_MEM_VIFIFO_END_PTR)
#define VLD_MEM_VIFIFO_BYTES_AVAIL 0x0c43 	///../ucode/dos_register.h:881
#define P_VLD_MEM_VIFIFO_BYTES_AVAIL 		DOS_REG_ADDR(VLD_MEM_VIFIFO_BYTES_AVAIL)
#define VLD_MEM_VIFIFO_CONTROL 0x0c44 	///../ucode/dos_register.h:912
#define P_VLD_MEM_VIFIFO_CONTROL 		DOS_REG_ADDR(VLD_MEM_VIFIFO_CONTROL)
#define VLD_MEM_VIFIFO_WP 0x0c45 	///../ucode/dos_register.h:916
#define P_VLD_MEM_VIFIFO_WP 		DOS_REG_ADDR(VLD_MEM_VIFIFO_WP)
#define VLD_MEM_VIFIFO_RP 0x0c46 	///../ucode/dos_register.h:917
#define P_VLD_MEM_VIFIFO_RP 		DOS_REG_ADDR(VLD_MEM_VIFIFO_RP)
#define VLD_MEM_VIFIFO_LEVEL 0x0c47 	///../ucode/dos_register.h:918
#define P_VLD_MEM_VIFIFO_LEVEL 		DOS_REG_ADDR(VLD_MEM_VIFIFO_LEVEL)
#define VLD_MEM_VIFIFO_BUF_CNTL 0x0c48 	///../ucode/dos_register.h:928
#define P_VLD_MEM_VIFIFO_BUF_CNTL 		DOS_REG_ADDR(VLD_MEM_VIFIFO_BUF_CNTL)
#define VLD_TIME_STAMP_CNTL 0x0c49 	///../ucode/dos_register.h:938
#define P_VLD_TIME_STAMP_CNTL 		DOS_REG_ADDR(VLD_TIME_STAMP_CNTL)
#define VLD_TIME_STAMP_SYNC_0 0x0c4a 	///../ucode/dos_register.h:940
#define P_VLD_TIME_STAMP_SYNC_0 		DOS_REG_ADDR(VLD_TIME_STAMP_SYNC_0)
#define VLD_TIME_STAMP_SYNC_1 0x0c4b 	///../ucode/dos_register.h:942
#define P_VLD_TIME_STAMP_SYNC_1 		DOS_REG_ADDR(VLD_TIME_STAMP_SYNC_1)
#define VLD_TIME_STAMP_0 0x0c4c 	///../ucode/dos_register.h:944
#define P_VLD_TIME_STAMP_0 		DOS_REG_ADDR(VLD_TIME_STAMP_0)
#define VLD_TIME_STAMP_1 0x0c4d 	///../ucode/dos_register.h:946
#define P_VLD_TIME_STAMP_1 		DOS_REG_ADDR(VLD_TIME_STAMP_1)
#define VLD_TIME_STAMP_2 0x0c4e 	///../ucode/dos_register.h:948
#define P_VLD_TIME_STAMP_2 		DOS_REG_ADDR(VLD_TIME_STAMP_2)
#define VLD_TIME_STAMP_3 0x0c4f 	///../ucode/dos_register.h:950
#define P_VLD_TIME_STAMP_3 		DOS_REG_ADDR(VLD_TIME_STAMP_3)
#define VLD_TIME_STAMP_LENGTH 0x0c50 	///../ucode/dos_register.h:952
#define P_VLD_TIME_STAMP_LENGTH 		DOS_REG_ADDR(VLD_TIME_STAMP_LENGTH)
#define VLD_MEM_VIFIFO_WRAP_COUNT 0x0c51 	///../ucode/dos_register.h:954
#define P_VLD_MEM_VIFIFO_WRAP_COUNT 		DOS_REG_ADDR(VLD_MEM_VIFIFO_WRAP_COUNT)
#define VLD_MEM_VIFIFO_MEM_CTL 0x0c52 	///../ucode/dos_register.h:958
#define P_VLD_MEM_VIFIFO_MEM_CTL 		DOS_REG_ADDR(VLD_MEM_VIFIFO_MEM_CTL)
#define VLD_MEM_VBUF_RD_PTR 0x0c53 	///../ucode/dos_register.h:959
#define P_VLD_MEM_VBUF_RD_PTR 		DOS_REG_ADDR(VLD_MEM_VBUF_RD_PTR)
#define VLD_MEM_VBUF2_RD_PTR 0x0c54 	///../ucode/dos_register.h:960
#define P_VLD_MEM_VBUF2_RD_PTR 		DOS_REG_ADDR(VLD_MEM_VBUF2_RD_PTR)
#define VLD_MEM_SWAP_ADDR 0x0c55 	///../ucode/dos_register.h:961
#define P_VLD_MEM_SWAP_ADDR 		DOS_REG_ADDR(VLD_MEM_SWAP_ADDR)
#define VLD_MEM_SWAP_CTL 0x0c56 	///../ucode/dos_register.h:968
#define P_VLD_MEM_SWAP_CTL 		DOS_REG_ADDR(VLD_MEM_SWAP_CTL)
#define VCOP_CTRL_REG 0x0e00 	///../ucode/dos_register.h:984
#define P_VCOP_CTRL_REG 		DOS_REG_ADDR(VCOP_CTRL_REG)
#define QP_CTRL_REG 0x0e01 	///../ucode/dos_register.h:985
#define P_QP_CTRL_REG 		DOS_REG_ADDR(QP_CTRL_REG)
#define INTRA_QUANT_MATRIX 0x0e02 	///../ucode/dos_register.h:986
#define P_INTRA_QUANT_MATRIX 		DOS_REG_ADDR(INTRA_QUANT_MATRIX)
#define NON_I_QUANT_MATRIX 0x0e03 	///../ucode/dos_register.h:987
#define P_NON_I_QUANT_MATRIX 		DOS_REG_ADDR(NON_I_QUANT_MATRIX)
#define DC_SCALER 0x0e04 	///../ucode/dos_register.h:988
#define P_DC_SCALER 		DOS_REG_ADDR(DC_SCALER)
#define DC_AC_CTRL 0x0e05 	///../ucode/dos_register.h:989
#define P_DC_AC_CTRL 		DOS_REG_ADDR(DC_AC_CTRL)
#define DC_AC_SCALE_MUL 0x0e06 	///../ucode/dos_register.h:991
#define P_DC_AC_SCALE_MUL 		DOS_REG_ADDR(DC_AC_SCALE_MUL)
#define DC_AC_SCALE_DIV 0x0e07 	///../ucode/dos_register.h:992
#define P_DC_AC_SCALE_DIV 		DOS_REG_ADDR(DC_AC_SCALE_DIV)
#define POWER_CTL_IQIDCT 0x0e08 	///../ucode/dos_register.h:995
#define P_POWER_CTL_IQIDCT 		DOS_REG_ADDR(POWER_CTL_IQIDCT)
#define RV_AI_Y_X 0x0e09 	///../ucode/dos_register.h:996
#define P_RV_AI_Y_X 		DOS_REG_ADDR(RV_AI_Y_X)
#define RV_AI_U_X 0x0e0a 	///../ucode/dos_register.h:997
#define P_RV_AI_U_X 		DOS_REG_ADDR(RV_AI_U_X)
#define RV_AI_V_X 0x0e0b 	///../ucode/dos_register.h:998
#define P_RV_AI_V_X 		DOS_REG_ADDR(RV_AI_V_X)
#define RV_AI_MB_COUNT 0x0e0c 	///../ucode/dos_register.h:1001
#define P_RV_AI_MB_COUNT 		DOS_REG_ADDR(RV_AI_MB_COUNT)
#define NEXT_INTRA_DMA_ADDRESS 0x0e0d 	///../ucode/dos_register.h:1003
#define P_NEXT_INTRA_DMA_ADDRESS 		DOS_REG_ADDR(NEXT_INTRA_DMA_ADDRESS)
#define IQIDCT_CONTROL 0x0e0e 	///../ucode/dos_register.h:1005
#define P_IQIDCT_CONTROL 		DOS_REG_ADDR(IQIDCT_CONTROL)
#define IQIDCT_DEBUG_INFO_0 0x0e0f 	///../ucode/dos_register.h:1022
#define P_IQIDCT_DEBUG_INFO_0 		DOS_REG_ADDR(IQIDCT_DEBUG_INFO_0)
#define DEBLK_CMD 0x0e10 	///../ucode/dos_register.h:1024
#define P_DEBLK_CMD 		DOS_REG_ADDR(DEBLK_CMD)
#define IQIDCT_DEBUG_IDCT 0x0e11 	///../ucode/dos_register.h:1057
#define P_IQIDCT_DEBUG_IDCT 		DOS_REG_ADDR(IQIDCT_DEBUG_IDCT)
#define DCAC_DMA_CTRL 0x0e12 	///../ucode/dos_register.h:1067
#define P_DCAC_DMA_CTRL 		DOS_REG_ADDR(DCAC_DMA_CTRL)
#define DCAC_DMA_ADDRESS 0x0e13 	///../ucode/dos_register.h:1074
#define P_DCAC_DMA_ADDRESS 		DOS_REG_ADDR(DCAC_DMA_ADDRESS)
#define DCAC_CPU_ADDRESS 0x0e14 	///../ucode/dos_register.h:1076
#define P_DCAC_CPU_ADDRESS 		DOS_REG_ADDR(DCAC_CPU_ADDRESS)
#define DCAC_CPU_DATA 0x0e15 	///../ucode/dos_register.h:1078
#define P_DCAC_CPU_DATA 		DOS_REG_ADDR(DCAC_CPU_DATA)
#define DCAC_MB_COUNT 0x0e16 	///../ucode/dos_register.h:1082
#define P_DCAC_MB_COUNT 		DOS_REG_ADDR(DCAC_MB_COUNT)
#define IQ_QUANT 0x0e17 	///../ucode/dos_register.h:1095
#define P_IQ_QUANT 		DOS_REG_ADDR(IQ_QUANT)
#define VC1_BITPLANE_CTL 0x0e18 	///../ucode/dos_register.h:1103
#define P_VC1_BITPLANE_CTL 		DOS_REG_ADDR(VC1_BITPLANE_CTL)
#define MSP 0x0300 	///../ucode/dos_register.h:1151
#define P_MSP 		DOS_REG_ADDR(MSP)
#define MPSR 0x0301 	///../ucode/dos_register.h:1152
#define P_MPSR 		DOS_REG_ADDR(MPSR)
#define MINT_VEC_BASE 0x0302 	///../ucode/dos_register.h:1153
#define P_MINT_VEC_BASE 		DOS_REG_ADDR(MINT_VEC_BASE)
#define MCPU_INTR_GRP 0x0303 	///../ucode/dos_register.h:1154
#define P_MCPU_INTR_GRP 		DOS_REG_ADDR(MCPU_INTR_GRP)
#define MCPU_INTR_MSK 0x0304 	///../ucode/dos_register.h:1155
#define P_MCPU_INTR_MSK 		DOS_REG_ADDR(MCPU_INTR_MSK)
#define MCPU_INTR_REQ 0x0305 	///../ucode/dos_register.h:1156
#define P_MCPU_INTR_REQ 		DOS_REG_ADDR(MCPU_INTR_REQ)
#define MPC_P 0x0306 	///../ucode/dos_register.h:1157
#define P_MPC_P 		DOS_REG_ADDR(MPC_P)
#define MPC_D 0x0307 	///../ucode/dos_register.h:1158
#define P_MPC_D 		DOS_REG_ADDR(MPC_D)
#define MPC_E 0x0308 	///../ucode/dos_register.h:1159
#define P_MPC_E 		DOS_REG_ADDR(MPC_E)
#define MPC_W 0x0309 	///../ucode/dos_register.h:1160
#define P_MPC_W 		DOS_REG_ADDR(MPC_W)
#define MINDEX0_REG 0x030a 	///../ucode/dos_register.h:1161
#define P_MINDEX0_REG 		DOS_REG_ADDR(MINDEX0_REG)
#define MINDEX1_REG 0x030b 	///../ucode/dos_register.h:1162
#define P_MINDEX1_REG 		DOS_REG_ADDR(MINDEX1_REG)
#define MINDEX2_REG 0x030c 	///../ucode/dos_register.h:1163
#define P_MINDEX2_REG 		DOS_REG_ADDR(MINDEX2_REG)
#define MINDEX3_REG 0x030d 	///../ucode/dos_register.h:1164
#define P_MINDEX3_REG 		DOS_REG_ADDR(MINDEX3_REG)
#define MINDEX4_REG 0x030e 	///../ucode/dos_register.h:1165
#define P_MINDEX4_REG 		DOS_REG_ADDR(MINDEX4_REG)
#define MINDEX5_REG 0x030f 	///../ucode/dos_register.h:1166
#define P_MINDEX5_REG 		DOS_REG_ADDR(MINDEX5_REG)
#define MINDEX6_REG 0x0310 	///../ucode/dos_register.h:1167
#define P_MINDEX6_REG 		DOS_REG_ADDR(MINDEX6_REG)
#define MINDEX7_REG 0x0311 	///../ucode/dos_register.h:1168
#define P_MINDEX7_REG 		DOS_REG_ADDR(MINDEX7_REG)
#define MMIN_REG 0x0312 	///../ucode/dos_register.h:1169
#define P_MMIN_REG 		DOS_REG_ADDR(MMIN_REG)
#define MMAX_REG 0x0313 	///../ucode/dos_register.h:1170
#define P_MMAX_REG 		DOS_REG_ADDR(MMAX_REG)
#define MBREAK0_REG 0x0314 	///../ucode/dos_register.h:1171
#define P_MBREAK0_REG 		DOS_REG_ADDR(MBREAK0_REG)
#define MBREAK1_REG 0x0315 	///../ucode/dos_register.h:1172
#define P_MBREAK1_REG 		DOS_REG_ADDR(MBREAK1_REG)
#define MBREAK2_REG 0x0316 	///../ucode/dos_register.h:1173
#define P_MBREAK2_REG 		DOS_REG_ADDR(MBREAK2_REG)
#define MBREAK3_REG 0x0317 	///../ucode/dos_register.h:1174
#define P_MBREAK3_REG 		DOS_REG_ADDR(MBREAK3_REG)
#define MBREAK_TYPE 0x0318 	///../ucode/dos_register.h:1175
#define P_MBREAK_TYPE 		DOS_REG_ADDR(MBREAK_TYPE)
#define MBREAK_CTRL 0x0319 	///../ucode/dos_register.h:1176
#define P_MBREAK_CTRL 		DOS_REG_ADDR(MBREAK_CTRL)
#define MBREAK_STAUTS 0x031a 	///../ucode/dos_register.h:1177
#define P_MBREAK_STAUTS 		DOS_REG_ADDR(MBREAK_STAUTS)
#define MDB_ADDR_REG 0x031b 	///../ucode/dos_register.h:1178
#define P_MDB_ADDR_REG 		DOS_REG_ADDR(MDB_ADDR_REG)
#define MDB_DATA_REG 0x031c 	///../ucode/dos_register.h:1179
#define P_MDB_DATA_REG 		DOS_REG_ADDR(MDB_DATA_REG)
#define MDB_CTRL 0x031d 	///../ucode/dos_register.h:1180
#define P_MDB_CTRL 		DOS_REG_ADDR(MDB_CTRL)
#define MSFTINT0 0x031e 	///../ucode/dos_register.h:1181
#define P_MSFTINT0 		DOS_REG_ADDR(MSFTINT0)
#define MSFTINT1 0x031f 	///../ucode/dos_register.h:1182
#define P_MSFTINT1 		DOS_REG_ADDR(MSFTINT1)
#define CSP 0x0320 	///../ucode/dos_register.h:1183
#define P_CSP 		DOS_REG_ADDR(CSP)
#define CPSR 0x0321 	///../ucode/dos_register.h:1184
#define P_CPSR 		DOS_REG_ADDR(CPSR)
#define CINT_VEC_BASE 0x0322 	///../ucode/dos_register.h:1185
#define P_CINT_VEC_BASE 		DOS_REG_ADDR(CINT_VEC_BASE)
#define CCPU_INTR_GRP 0x0323 	///../ucode/dos_register.h:1186
#define P_CCPU_INTR_GRP 		DOS_REG_ADDR(CCPU_INTR_GRP)
#define CCPU_INTR_MSK 0x0324 	///../ucode/dos_register.h:1187
#define P_CCPU_INTR_MSK 		DOS_REG_ADDR(CCPU_INTR_MSK)
#define CCPU_INTR_REQ 0x0325 	///../ucode/dos_register.h:1188
#define P_CCPU_INTR_REQ 		DOS_REG_ADDR(CCPU_INTR_REQ)
#define CPC_P 0x0326 	///../ucode/dos_register.h:1189
#define P_CPC_P 		DOS_REG_ADDR(CPC_P)
#define CPC_D 0x0327 	///../ucode/dos_register.h:1190
#define P_CPC_D 		DOS_REG_ADDR(CPC_D)
#define CPC_E 0x0328 	///../ucode/dos_register.h:1191
#define P_CPC_E 		DOS_REG_ADDR(CPC_E)
#define CPC_W 0x0329 	///../ucode/dos_register.h:1192
#define P_CPC_W 		DOS_REG_ADDR(CPC_W)
#define CINDEX0_REG 0x032a 	///../ucode/dos_register.h:1193
#define P_CINDEX0_REG 		DOS_REG_ADDR(CINDEX0_REG)
#define CINDEX1_REG 0x032b 	///../ucode/dos_register.h:1194
#define P_CINDEX1_REG 		DOS_REG_ADDR(CINDEX1_REG)
#define CINDEX2_REG 0x032c 	///../ucode/dos_register.h:1195
#define P_CINDEX2_REG 		DOS_REG_ADDR(CINDEX2_REG)
#define CINDEX3_REG 0x032d 	///../ucode/dos_register.h:1196
#define P_CINDEX3_REG 		DOS_REG_ADDR(CINDEX3_REG)
#define CINDEX4_REG 0x032e 	///../ucode/dos_register.h:1197
#define P_CINDEX4_REG 		DOS_REG_ADDR(CINDEX4_REG)
#define CINDEX5_REG 0x032f 	///../ucode/dos_register.h:1198
#define P_CINDEX5_REG 		DOS_REG_ADDR(CINDEX5_REG)
#define CINDEX6_REG 0x0330 	///../ucode/dos_register.h:1199
#define P_CINDEX6_REG 		DOS_REG_ADDR(CINDEX6_REG)
#define CINDEX7_REG 0x0331 	///../ucode/dos_register.h:1200
#define P_CINDEX7_REG 		DOS_REG_ADDR(CINDEX7_REG)
#define CMIN_REG 0x0332 	///../ucode/dos_register.h:1201
#define P_CMIN_REG 		DOS_REG_ADDR(CMIN_REG)
#define CMAX_REG 0x0333 	///../ucode/dos_register.h:1202
#define P_CMAX_REG 		DOS_REG_ADDR(CMAX_REG)
#define CBREAK0_REG 0x0334 	///../ucode/dos_register.h:1203
#define P_CBREAK0_REG 		DOS_REG_ADDR(CBREAK0_REG)
#define CBREAK1_REG 0x0335 	///../ucode/dos_register.h:1204
#define P_CBREAK1_REG 		DOS_REG_ADDR(CBREAK1_REG)
#define CBREAK2_REG 0x0336 	///../ucode/dos_register.h:1205
#define P_CBREAK2_REG 		DOS_REG_ADDR(CBREAK2_REG)
#define CBREAK3_REG 0x0337 	///../ucode/dos_register.h:1206
#define P_CBREAK3_REG 		DOS_REG_ADDR(CBREAK3_REG)
#define CBREAK_TYPE 0x0338 	///../ucode/dos_register.h:1207
#define P_CBREAK_TYPE 		DOS_REG_ADDR(CBREAK_TYPE)
#define CBREAK_CTRL 0x0339 	///../ucode/dos_register.h:1208
#define P_CBREAK_CTRL 		DOS_REG_ADDR(CBREAK_CTRL)
#define CBREAK_STAUTS 0x033a 	///../ucode/dos_register.h:1209
#define P_CBREAK_STAUTS 		DOS_REG_ADDR(CBREAK_STAUTS)
#define CDB_ADDR_REG 0x033b 	///../ucode/dos_register.h:1210
#define P_CDB_ADDR_REG 		DOS_REG_ADDR(CDB_ADDR_REG)
#define CDB_DATA_REG 0x033c 	///../ucode/dos_register.h:1211
#define P_CDB_DATA_REG 		DOS_REG_ADDR(CDB_DATA_REG)
#define CDB_CTRL 0x033d 	///../ucode/dos_register.h:1212
#define P_CDB_CTRL 		DOS_REG_ADDR(CDB_CTRL)
#define CSFTINT0 0x033e 	///../ucode/dos_register.h:1213
#define P_CSFTINT0 		DOS_REG_ADDR(CSFTINT0)
#define CSFTINT1 0x033f 	///../ucode/dos_register.h:1214
#define P_CSFTINT1 		DOS_REG_ADDR(CSFTINT1)
#define IMEM_DMA_CTRL 0x0340 	///../ucode/dos_register.h:1215
#define P_IMEM_DMA_CTRL 		DOS_REG_ADDR(IMEM_DMA_CTRL)
#define IMEM_DMA_ADR 0x0341 	///../ucode/dos_register.h:1216
#define P_IMEM_DMA_ADR 		DOS_REG_ADDR(IMEM_DMA_ADR)
#define IMEM_DMA_COUNT 0x0342 	///../ucode/dos_register.h:1217
#define P_IMEM_DMA_COUNT 		DOS_REG_ADDR(IMEM_DMA_COUNT)
#define WRRSP_IMEM 0x0343 	///../ucode/dos_register.h:1221
#define P_WRRSP_IMEM 		DOS_REG_ADDR(WRRSP_IMEM)
#define LMEM_DMA_CTRL 0x0350 	///../ucode/dos_register.h:1222
#define P_LMEM_DMA_CTRL 		DOS_REG_ADDR(LMEM_DMA_CTRL)
#define LMEM_DMA_ADR 0x0351 	///../ucode/dos_register.h:1223
#define P_LMEM_DMA_ADR 		DOS_REG_ADDR(LMEM_DMA_ADR)
#define LMEM_DMA_COUNT 0x0352 	///../ucode/dos_register.h:1224
#define P_LMEM_DMA_COUNT 		DOS_REG_ADDR(LMEM_DMA_COUNT)
#define WRRSP_LMEM 0x0353 	///../ucode/dos_register.h:1228
#define P_WRRSP_LMEM 		DOS_REG_ADDR(WRRSP_LMEM)
#define MAC_CTRL1 0x0360 	///../ucode/dos_register.h:1229
#define P_MAC_CTRL1 		DOS_REG_ADDR(MAC_CTRL1)
#define ACC0REG1 0x0361 	///../ucode/dos_register.h:1230
#define P_ACC0REG1 		DOS_REG_ADDR(ACC0REG1)
#define ACC1REG1 0x0362 	///../ucode/dos_register.h:1231
#define P_ACC1REG1 		DOS_REG_ADDR(ACC1REG1)
#define MAC_CTRL2 0x0370 	///../ucode/dos_register.h:1232
#define P_MAC_CTRL2 		DOS_REG_ADDR(MAC_CTRL2)
#define ACC0REG2 0x0371 	///../ucode/dos_register.h:1233
#define P_ACC0REG2 		DOS_REG_ADDR(ACC0REG2)
#define ACC1REG2 0x0372 	///../ucode/dos_register.h:1234
#define P_ACC1REG2 		DOS_REG_ADDR(ACC1REG2)
#define CPU_TRACE 0x0380 	///../ucode/dos_register.h:1235
#define P_CPU_TRACE 		DOS_REG_ADDR(CPU_TRACE)
#define HENC_SCRATCH_0 0x1ac0 	///../ucode/dos_register.h:1251
#define P_HENC_SCRATCH_0 		DOS_REG_ADDR(HENC_SCRATCH_0)
#define HENC_SCRATCH_1 0x1ac1 	///../ucode/dos_register.h:1252
#define P_HENC_SCRATCH_1 		DOS_REG_ADDR(HENC_SCRATCH_1)
#define HENC_SCRATCH_2 0x1ac2 	///../ucode/dos_register.h:1253
#define P_HENC_SCRATCH_2 		DOS_REG_ADDR(HENC_SCRATCH_2)
#define HENC_SCRATCH_3 0x1ac3 	///../ucode/dos_register.h:1254
#define P_HENC_SCRATCH_3 		DOS_REG_ADDR(HENC_SCRATCH_3)
#define HENC_SCRATCH_4 0x1ac4 	///../ucode/dos_register.h:1255
#define P_HENC_SCRATCH_4 		DOS_REG_ADDR(HENC_SCRATCH_4)
#define HENC_SCRATCH_5 0x1ac5 	///../ucode/dos_register.h:1256
#define P_HENC_SCRATCH_5 		DOS_REG_ADDR(HENC_SCRATCH_5)
#define HENC_SCRATCH_6 0x1ac6 	///../ucode/dos_register.h:1257
#define P_HENC_SCRATCH_6 		DOS_REG_ADDR(HENC_SCRATCH_6)
#define HENC_SCRATCH_7 0x1ac7 	///../ucode/dos_register.h:1258
#define P_HENC_SCRATCH_7 		DOS_REG_ADDR(HENC_SCRATCH_7)
#define HENC_SCRATCH_8 0x1ac8 	///../ucode/dos_register.h:1259
#define P_HENC_SCRATCH_8 		DOS_REG_ADDR(HENC_SCRATCH_8)
#define HENC_SCRATCH_9 0x1ac9 	///../ucode/dos_register.h:1260
#define P_HENC_SCRATCH_9 		DOS_REG_ADDR(HENC_SCRATCH_9)
#define HENC_SCRATCH_A 0x1aca 	///../ucode/dos_register.h:1261
#define P_HENC_SCRATCH_A 		DOS_REG_ADDR(HENC_SCRATCH_A)
#define HENC_SCRATCH_B 0x1acb 	///../ucode/dos_register.h:1262
#define P_HENC_SCRATCH_B 		DOS_REG_ADDR(HENC_SCRATCH_B)
#define HENC_SCRATCH_C 0x1acc 	///../ucode/dos_register.h:1263
#define P_HENC_SCRATCH_C 		DOS_REG_ADDR(HENC_SCRATCH_C)
#define HENC_SCRATCH_D 0x1acd 	///../ucode/dos_register.h:1264
#define P_HENC_SCRATCH_D 		DOS_REG_ADDR(HENC_SCRATCH_D)
#define HENC_SCRATCH_E 0x1ace 	///../ucode/dos_register.h:1265
#define P_HENC_SCRATCH_E 		DOS_REG_ADDR(HENC_SCRATCH_E)
#define HENC_SCRATCH_F 0x1acf 	///../ucode/dos_register.h:1266
#define P_HENC_SCRATCH_F 		DOS_REG_ADDR(HENC_SCRATCH_F)
#define HENC_SCRATCH_G 0x1ad0 	///../ucode/dos_register.h:1267
#define P_HENC_SCRATCH_G 		DOS_REG_ADDR(HENC_SCRATCH_G)
#define HENC_SCRATCH_H 0x1ad1 	///../ucode/dos_register.h:1268
#define P_HENC_SCRATCH_H 		DOS_REG_ADDR(HENC_SCRATCH_H)
#define HENC_SCRATCH_I 0x1ad2 	///../ucode/dos_register.h:1269
#define P_HENC_SCRATCH_I 		DOS_REG_ADDR(HENC_SCRATCH_I)
#define HENC_SCRATCH_J 0x1ad3 	///../ucode/dos_register.h:1270
#define P_HENC_SCRATCH_J 		DOS_REG_ADDR(HENC_SCRATCH_J)
#define HENC_SCRATCH_K 0x1ad4 	///../ucode/dos_register.h:1271
#define P_HENC_SCRATCH_K 		DOS_REG_ADDR(HENC_SCRATCH_K)
#define HENC_SCRATCH_L 0x1ad5 	///../ucode/dos_register.h:1272
#define P_HENC_SCRATCH_L 		DOS_REG_ADDR(HENC_SCRATCH_L)
#define HENC_SCRATCH_M 0x1ad6 	///../ucode/dos_register.h:1273
#define P_HENC_SCRATCH_M 		DOS_REG_ADDR(HENC_SCRATCH_M)
#define HENC_SCRATCH_N 0x1ad7 	///../ucode/dos_register.h:1274
#define P_HENC_SCRATCH_N 		DOS_REG_ADDR(HENC_SCRATCH_N)
#define IE_DATA_FEED_BUFF_INFO 0x1ad8 	///../ucode/dos_register.h:1276
#define P_IE_DATA_FEED_BUFF_INFO 		DOS_REG_ADDR(IE_DATA_FEED_BUFF_INFO)
#define VLC_STATUS_CTRL 0x1d00 	///../ucode/dos_register.h:1302
#define P_VLC_STATUS_CTRL 		DOS_REG_ADDR(VLC_STATUS_CTRL)
#define VLC_CONFIG 0x1d01 	///../ucode/dos_register.h:1320
#define P_VLC_CONFIG 		DOS_REG_ADDR(VLC_CONFIG)
#define VLC_VB_START_PTR 0x1d10 	///../ucode/dos_register.h:1324
#define P_VLC_VB_START_PTR 		DOS_REG_ADDR(VLC_VB_START_PTR)
#define VLC_VB_END_PTR 0x1d11 	///../ucode/dos_register.h:1325
#define P_VLC_VB_END_PTR 		DOS_REG_ADDR(VLC_VB_END_PTR)
#define VLC_VB_WR_PTR 0x1d12 	///../ucode/dos_register.h:1326
#define P_VLC_VB_WR_PTR 		DOS_REG_ADDR(VLC_VB_WR_PTR)
#define VLC_VB_RD_PTR 0x1d13 	///../ucode/dos_register.h:1328
#define P_VLC_VB_RD_PTR 		DOS_REG_ADDR(VLC_VB_RD_PTR)
#define VLC_VB_SW_RD_PTR 0x1d14 	///../ucode/dos_register.h:1329
#define P_VLC_VB_SW_RD_PTR 		DOS_REG_ADDR(VLC_VB_SW_RD_PTR)
#define VLC_VB_LEFT 0x1d15 	///../ucode/dos_register.h:1331
#define P_VLC_VB_LEFT 		DOS_REG_ADDR(VLC_VB_LEFT)
#define VLC_VB_CONTROL 0x1d16 	///../ucode/dos_register.h:1357
#define P_VLC_VB_CONTROL 		DOS_REG_ADDR(VLC_VB_CONTROL)
#define VLC_VB_MEM_CTL 0x1d17 	///../ucode/dos_register.h:1364
#define P_VLC_VB_MEM_CTL 		DOS_REG_ADDR(VLC_VB_MEM_CTL)
#define VLC_VB_INT_PTR 0x1d18 	///../ucode/dos_register.h:1366
#define P_VLC_VB_INT_PTR 		DOS_REG_ADDR(VLC_VB_INT_PTR)
#define VLC_WRRSP 0x1d19 	///../ucode/dos_register.h:1369
#define P_VLC_WRRSP 		DOS_REG_ADDR(VLC_WRRSP)
#define VLC_TOTAL_BYTES 0x1d1a 	///../ucode/dos_register.h:1370
#define P_VLC_TOTAL_BYTES 		DOS_REG_ADDR(VLC_TOTAL_BYTES)
#define VLC_VB_BUFF 0x1d1b 	///../ucode/dos_register.h:1377
#define P_VLC_VB_BUFF 		DOS_REG_ADDR(VLC_VB_BUFF)
#define VLC_VB_PRE_BUFF_HI 0x1d1c 	///../ucode/dos_register.h:1382
#define P_VLC_VB_PRE_BUFF_HI 		DOS_REG_ADDR(VLC_VB_PRE_BUFF_HI)
#define VLC_VB_PRE_BUFF_LOW 0x1d1d 	///../ucode/dos_register.h:1384
#define P_VLC_VB_PRE_BUFF_LOW 		DOS_REG_ADDR(VLC_VB_PRE_BUFF_LOW)
#define VLC_STREAM_BUFF 0x1d1e 	///../ucode/dos_register.h:1389
#define P_VLC_STREAM_BUFF 		DOS_REG_ADDR(VLC_STREAM_BUFF)
#define VLC_PUSH_STREAM 0x1d1f 	///../ucode/dos_register.h:1403
#define P_VLC_PUSH_STREAM 		DOS_REG_ADDR(VLC_PUSH_STREAM)
#define VLC_PUSH_ELEMENT 0x1d20 	///../ucode/dos_register.h:1407
#define P_VLC_PUSH_ELEMENT 		DOS_REG_ADDR(VLC_PUSH_ELEMENT)
#define VLC_ELEMENT_DATA 0x1d21 	///../ucode/dos_register.h:1408
#define P_VLC_ELEMENT_DATA 		DOS_REG_ADDR(VLC_ELEMENT_DATA)
#define VLC_INT_CONTROL 0x1d30 	///../ucode/dos_register.h:1445
#define P_VLC_INT_CONTROL 		DOS_REG_ADDR(VLC_INT_CONTROL)
#define VLC_PIC_SIZE 0x1d31 	///../ucode/dos_register.h:1448
#define P_VLC_PIC_SIZE 		DOS_REG_ADDR(VLC_PIC_SIZE)
#define VLC_PIC_INFO 0x1d32 	///../ucode/dos_register.h:1452
#define P_VLC_PIC_INFO 		DOS_REG_ADDR(VLC_PIC_INFO)
#define VLC_PIC_POSITION 0x1d33 	///../ucode/dos_register.h:1456
#define P_VLC_PIC_POSITION 		DOS_REG_ADDR(VLC_PIC_POSITION)
#define VLC_INPUT_STATUS 0x1d34 	///../ucode/dos_register.h:1475
#define P_VLC_INPUT_STATUS 		DOS_REG_ADDR(VLC_INPUT_STATUS)
#define VLC_MB_INFO 0x1d35 	///../ucode/dos_register.h:1480
#define P_VLC_MB_INFO 		DOS_REG_ADDR(VLC_MB_INFO)
#define VLC_ENC_PEND_CMD 0x1d36 	///../ucode/dos_register.h:1492
#define P_VLC_ENC_PEND_CMD 		DOS_REG_ADDR(VLC_ENC_PEND_CMD)
#define HENC_TOP_INFO_0 0x1d37 	///../ucode/dos_register.h:1496
#define P_HENC_TOP_INFO_0 		DOS_REG_ADDR(HENC_TOP_INFO_0)
#define HENC_LEFT_INFO_0 0x1d38 	///../ucode/dos_register.h:1497
#define P_HENC_LEFT_INFO_0 		DOS_REG_ADDR(HENC_LEFT_INFO_0)
#define HENC_TOP_INFO_1 0x1d39 	///../ucode/dos_register.h:1502
#define P_HENC_TOP_INFO_1 		DOS_REG_ADDR(HENC_TOP_INFO_1)
#define HENC_LEFT_INFO_1 0x1d3a 	///../ucode/dos_register.h:1503
#define P_HENC_LEFT_INFO_1 		DOS_REG_ADDR(HENC_LEFT_INFO_1)
#define VLC_IPRED_MODE_HI 0x1d3b 	///../ucode/dos_register.h:1505
#define P_VLC_IPRED_MODE_HI 		DOS_REG_ADDR(VLC_IPRED_MODE_HI)
#define VLC_IPRED_MODE_LO 0x1d3c 	///../ucode/dos_register.h:1506
#define P_VLC_IPRED_MODE_LO 		DOS_REG_ADDR(VLC_IPRED_MODE_LO)
#define VLC_DELTA_QP 0x1d3d 	///../ucode/dos_register.h:1509
#define P_VLC_DELTA_QP 		DOS_REG_ADDR(VLC_DELTA_QP)
#define VLC_MB_HEADER_INFO 0x1d3e 	///../ucode/dos_register.h:1514
#define P_VLC_MB_HEADER_INFO 		DOS_REG_ADDR(VLC_MB_HEADER_INFO)
#define VLC_P_MB_HEADER_INFO 0x1d3f 	///../ucode/dos_register.h:1517
#define P_VLC_P_MB_HEADER_INFO 		DOS_REG_ADDR(VLC_P_MB_HEADER_INFO)
#define VLC_COEFF_BUF_STATUS 0x1d40 	///../ucode/dos_register.h:1523
#define P_VLC_COEFF_BUF_STATUS 		DOS_REG_ADDR(VLC_COEFF_BUF_STATUS)
#define VLC_COEFF_RD_REQ 0x1d41 	///../ucode/dos_register.h:1526
#define P_VLC_COEFF_RD_REQ 		DOS_REG_ADDR(VLC_COEFF_RD_REQ)
#define VLC_COEFF 0x1d42 	///../ucode/dos_register.h:1531
#define P_VLC_COEFF 		DOS_REG_ADDR(VLC_COEFF)
#define VLC_COEFF_INFO 0x1d43 	///../ucode/dos_register.h:1539
#define P_VLC_COEFF_INFO 		DOS_REG_ADDR(VLC_COEFF_INFO)
#define VLC_DC_BUF_STATUS 0x1d44 	///../ucode/dos_register.h:1548
#define P_VLC_DC_BUF_STATUS 		DOS_REG_ADDR(VLC_DC_BUF_STATUS)
#define VLC_DC_RD_REQ 0x1d45 	///../ucode/dos_register.h:1552
#define P_VLC_DC_RD_REQ 		DOS_REG_ADDR(VLC_DC_RD_REQ)
#define VLC_DC 0x1d46 	///../ucode/dos_register.h:1557
#define P_VLC_DC 		DOS_REG_ADDR(VLC_DC)
#define VLC_DC_INFO 0x1d47 	///../ucode/dos_register.h:1566
#define P_VLC_DC_INFO 		DOS_REG_ADDR(VLC_DC_INFO)
#define VLC_MV_INDEX 0x1d48 	///../ucode/dos_register.h:1569
#define P_VLC_MV_INDEX 		DOS_REG_ADDR(VLC_MV_INDEX)
#define VLC_MV 0x1d49 	///../ucode/dos_register.h:1572
#define P_VLC_MV 		DOS_REG_ADDR(VLC_MV)
#define HENC_TOP_MV_0 0x1d4a 	///../ucode/dos_register.h:1577
#define P_HENC_TOP_MV_0 		DOS_REG_ADDR(HENC_TOP_MV_0)
#define HENC_TOP_MV_1 0x1d4b 	///../ucode/dos_register.h:1578
#define P_HENC_TOP_MV_1 		DOS_REG_ADDR(HENC_TOP_MV_1)
#define HENC_TOP_MV_2 0x1d4c 	///../ucode/dos_register.h:1579
#define P_HENC_TOP_MV_2 		DOS_REG_ADDR(HENC_TOP_MV_2)
#define HENC_TOP_MV_3 0x1d4d 	///../ucode/dos_register.h:1580
#define P_HENC_TOP_MV_3 		DOS_REG_ADDR(HENC_TOP_MV_3)
#define HENC_LEFT_MV_0 0x1d4e 	///../ucode/dos_register.h:1581
#define P_HENC_LEFT_MV_0 		DOS_REG_ADDR(HENC_LEFT_MV_0)
#define HENC_LEFT_MV_1 0x1d4f 	///../ucode/dos_register.h:1582
#define P_HENC_LEFT_MV_1 		DOS_REG_ADDR(HENC_LEFT_MV_1)
#define HENC_LEFT_MV_2 0x1d50 	///../ucode/dos_register.h:1583
#define P_HENC_LEFT_MV_2 		DOS_REG_ADDR(HENC_LEFT_MV_2)
#define HENC_LEFT_MV_3 0x1d51 	///../ucode/dos_register.h:1584
#define P_HENC_LEFT_MV_3 		DOS_REG_ADDR(HENC_LEFT_MV_3)
#define TOP_LEFT_READY 0x1d52 	///../ucode/dos_register.h:1587
#define P_TOP_LEFT_READY 		DOS_REG_ADDR(TOP_LEFT_READY)
#define MB_SKIP_RUN 0x1d53 	///../ucode/dos_register.h:1590
#define P_MB_SKIP_RUN 		DOS_REG_ADDR(MB_SKIP_RUN)
#define VLC_HCMD_CONFIG 0x1d54 	///../ucode/dos_register.h:1597
#define P_VLC_HCMD_CONFIG 		DOS_REG_ADDR(VLC_HCMD_CONFIG)
#define VLC_HCMD_DBLK_INFO 0x1d55 	///../ucode/dos_register.h:1599
#define P_VLC_HCMD_DBLK_INFO 		DOS_REG_ADDR(VLC_HCMD_DBLK_INFO)
#define VLC_DBG_IDX 0x1d56 	///../ucode/dos_register.h:1601
#define P_VLC_DBG_IDX 		DOS_REG_ADDR(VLC_DBG_IDX)
#define VLC_DBG_READ 0x1d57 	///../ucode/dos_register.h:1603
#define P_VLC_DBG_READ 		DOS_REG_ADDR(VLC_DBG_READ)
#define VLC_JPEG_CTRL 0x1d58 	///../ucode/dos_register.h:1604
#define P_VLC_JPEG_CTRL 		DOS_REG_ADDR(VLC_JPEG_CTRL)
#define VLC_JPEG_COEFF_BUF_STAT 0x1d59 	///../ucode/dos_register.h:1605
#define P_VLC_JPEG_COEFF_BUF_STAT 		DOS_REG_ADDR(VLC_JPEG_COEFF_BUF_STAT)
#define VLC_HUFFMAN_ADDR 0x1d5a 	///../ucode/dos_register.h:1606
#define P_VLC_HUFFMAN_ADDR 		DOS_REG_ADDR(VLC_HUFFMAN_ADDR)
#define VLC_HUFFMAN_DATA 0x1d5b 	///../ucode/dos_register.h:1607
#define P_VLC_HUFFMAN_DATA 		DOS_REG_ADDR(VLC_HUFFMAN_DATA)
#define VLC_ENC_MV_BITS 0x1d5c 	///../ucode/dos_register.h:1609
#define P_VLC_ENC_MV_BITS 		DOS_REG_ADDR(VLC_ENC_MV_BITS)
#define VLC_ENC_COEFF_BITS 0x1d5d 	///../ucode/dos_register.h:1611
#define P_VLC_ENC_COEFF_BITS 		DOS_REG_ADDR(VLC_ENC_COEFF_BITS)
#define QDCT_STATUS_CTRL 0x1f00 	///../ucode/dos_register.h:1628
#define P_QDCT_STATUS_CTRL 		DOS_REG_ADDR(QDCT_STATUS_CTRL)
#define QDCT_CONFIG 0x1f01 	///../ucode/dos_register.h:1648
#define P_QDCT_CONFIG 		DOS_REG_ADDR(QDCT_CONFIG)
#define IGNORE_CONFIG 0x1f02 	///../ucode/dos_register.h:1657
#define P_IGNORE_CONFIG 		DOS_REG_ADDR(IGNORE_CONFIG)
#define IGNORE_CONFIG_2 0x1f03 	///../ucode/dos_register.h:1663
#define P_IGNORE_CONFIG_2 		DOS_REG_ADDR(IGNORE_CONFIG_2)
#define QDCT_MB_START_PTR 0x1f10 	///../ucode/dos_register.h:1667
#define P_QDCT_MB_START_PTR 		DOS_REG_ADDR(QDCT_MB_START_PTR)
#define QDCT_MB_END_PTR 0x1f11 	///../ucode/dos_register.h:1668
#define P_QDCT_MB_END_PTR 		DOS_REG_ADDR(QDCT_MB_END_PTR)
#define QDCT_MB_WR_PTR 0x1f12 	///../ucode/dos_register.h:1669
#define P_QDCT_MB_WR_PTR 		DOS_REG_ADDR(QDCT_MB_WR_PTR)
#define QDCT_MB_RD_PTR 0x1f13 	///../ucode/dos_register.h:1670
#define P_QDCT_MB_RD_PTR 		DOS_REG_ADDR(QDCT_MB_RD_PTR)
#define QDCT_MB_LEVEL 0x1f14 	///../ucode/dos_register.h:1671
#define P_QDCT_MB_LEVEL 		DOS_REG_ADDR(QDCT_MB_LEVEL)
#define QDCT_MB_CONTROL 0x1f15 	///../ucode/dos_register.h:1702
#define P_QDCT_MB_CONTROL 		DOS_REG_ADDR(QDCT_MB_CONTROL)
#define QDCT_MB_MEM_CTL 0x1f16 	///../ucode/dos_register.h:1710
#define P_QDCT_MB_MEM_CTL 		DOS_REG_ADDR(QDCT_MB_MEM_CTL)
#define QDCT_MB_BUFF 0x1f17 	///../ucode/dos_register.h:1715
#define P_QDCT_MB_BUFF 		DOS_REG_ADDR(QDCT_MB_BUFF)
#define QDCT_MB_MAGIC_WORD 0x1f18 	///../ucode/dos_register.h:1717
#define P_QDCT_MB_MAGIC_WORD 		DOS_REG_ADDR(QDCT_MB_MAGIC_WORD)
#define QDCT_DCT_STATUS 0x1f19 	///../ucode/dos_register.h:1729
#define P_QDCT_DCT_STATUS 		DOS_REG_ADDR(QDCT_DCT_STATUS)
#define QDCT_Q_STATUS 0x1f1a 	///../ucode/dos_register.h:1731
#define P_QDCT_Q_STATUS 		DOS_REG_ADDR(QDCT_Q_STATUS)
#define QDCT_PIC_INFO 0x1f1b 	///../ucode/dos_register.h:1734
#define P_QDCT_PIC_INFO 		DOS_REG_ADDR(QDCT_PIC_INFO)
#define QDCT_Q_QUANT_I 0x1f1c 	///../ucode/dos_register.h:1744
#define P_QDCT_Q_QUANT_I 		DOS_REG_ADDR(QDCT_Q_QUANT_I)
#define QDCT_Q_QUANT_P 0x1f1d 	///../ucode/dos_register.h:1754
#define P_QDCT_Q_QUANT_P 		DOS_REG_ADDR(QDCT_Q_QUANT_P)
#define QDCT_MB_PAUSE_CTL 0x1f1e 	///../ucode/dos_register.h:1758
#define P_QDCT_MB_PAUSE_CTL 		DOS_REG_ADDR(QDCT_MB_PAUSE_CTL)
#define QDCT_TOP_CONTROL 0x1f1f 	///../ucode/dos_register.h:1772
#define P_QDCT_TOP_CONTROL 		DOS_REG_ADDR(QDCT_TOP_CONTROL)
#define QDCT_TOP_BASE_MEM 0x1f20 	///../ucode/dos_register.h:1774
#define P_QDCT_TOP_BASE_MEM 		DOS_REG_ADDR(QDCT_TOP_BASE_MEM)
#define QDCT_TOP_MEM_CTL 0x1f21 	///../ucode/dos_register.h:1779
#define P_QDCT_TOP_MEM_CTL 		DOS_REG_ADDR(QDCT_TOP_MEM_CTL)
#define QDCT_TOP_WRRSP 0x1f22 	///../ucode/dos_register.h:1781
#define P_QDCT_TOP_WRRSP 		DOS_REG_ADDR(QDCT_TOP_WRRSP)
#define QDCT_DBG_IDX 0x1f23 	///../ucode/dos_register.h:1783
#define P_QDCT_DBG_IDX 		DOS_REG_ADDR(QDCT_DBG_IDX)
#define QDCT_DBG_READ 0x1f24 	///../ucode/dos_register.h:1785
#define P_QDCT_DBG_READ 		DOS_REG_ADDR(QDCT_DBG_READ)
#define QDCT_JPEG_CTRL 0x1f25 	///../ucode/dos_register.h:1786
#define P_QDCT_JPEG_CTRL 		DOS_REG_ADDR(QDCT_JPEG_CTRL)
#define QDCT_JPEG_X_START_END 0x1f26 	///../ucode/dos_register.h:1787
#define P_QDCT_JPEG_X_START_END 		DOS_REG_ADDR(QDCT_JPEG_X_START_END)
#define QDCT_JPEG_Y_START_END 0x1f27 	///../ucode/dos_register.h:1788
#define P_QDCT_JPEG_Y_START_END 		DOS_REG_ADDR(QDCT_JPEG_Y_START_END)
#define QDCT_JPEG_QUANT_ADDR 0x1f28 	///../ucode/dos_register.h:1789
#define P_QDCT_JPEG_QUANT_ADDR 		DOS_REG_ADDR(QDCT_JPEG_QUANT_ADDR)
#define QDCT_JPEG_QUANT_DATA 0x1f29 	///../ucode/dos_register.h:1790
#define P_QDCT_JPEG_QUANT_DATA 		DOS_REG_ADDR(QDCT_JPEG_QUANT_DATA)
#define QDCT_JPEG_SOF_RESUME 0x1f2a 	///../ucode/dos_register.h:1791
#define P_QDCT_JPEG_SOF_RESUME 		DOS_REG_ADDR(QDCT_JPEG_SOF_RESUME)
#define QDCT_JPEG_DCT_STATUS0 0x1f2b 	///../ucode/dos_register.h:1792
#define P_QDCT_JPEG_DCT_STATUS0 		DOS_REG_ADDR(QDCT_JPEG_DCT_STATUS0)
#define QDCT_JPEG_DCT_STATUS1 0x1f2c 	///../ucode/dos_register.h:1793
#define P_QDCT_JPEG_DCT_STATUS1 		DOS_REG_ADDR(QDCT_JPEG_DCT_STATUS1)
#define QDCT_JPEG_DCT_COEFF01 0x1f2d 	///../ucode/dos_register.h:1794
#define P_QDCT_JPEG_DCT_COEFF01 		DOS_REG_ADDR(QDCT_JPEG_DCT_COEFF01)
#define QDCT_JPEG_DCT_COEFF23 0x1f2e 	///../ucode/dos_register.h:1795
#define P_QDCT_JPEG_DCT_COEFF23 		DOS_REG_ADDR(QDCT_JPEG_DCT_COEFF23)
#define QDCT_JPEG_DCT_COEFF45 0x1f2f 	///../ucode/dos_register.h:1796
#define P_QDCT_JPEG_DCT_COEFF45 		DOS_REG_ADDR(QDCT_JPEG_DCT_COEFF45)
#define QDCT_JPEG_DCT_COEFF67 0x1f30 	///../ucode/dos_register.h:1797
#define P_QDCT_JPEG_DCT_COEFF67 		DOS_REG_ADDR(QDCT_JPEG_DCT_COEFF67)
#define QDCT_JPEG_DCT_COEFF89 0x1f31 	///../ucode/dos_register.h:1798
#define P_QDCT_JPEG_DCT_COEFF89 		DOS_REG_ADDR(QDCT_JPEG_DCT_COEFF89)
#define IE_CONTROL 0x1f40 	///../ucode/dos_register.h:1809
#define P_IE_CONTROL 		DOS_REG_ADDR(IE_CONTROL)
#define IE_MB_POSITION 0x1f41 	///../ucode/dos_register.h:1812
#define P_IE_MB_POSITION 		DOS_REG_ADDR(IE_MB_POSITION)
#define IE_ME_MB_INFO 0x1f42 	///../ucode/dos_register.h:1817
#define P_IE_ME_MB_INFO 		DOS_REG_ADDR(IE_ME_MB_INFO)
#define SAD_CONTROL 0x1f43 	///../ucode/dos_register.h:1822
#define P_SAD_CONTROL 		DOS_REG_ADDR(SAD_CONTROL)
#define IE_RESULT_BUFFER 0x1f44 	///../ucode/dos_register.h:1829
#define P_IE_RESULT_BUFFER 		DOS_REG_ADDR(IE_RESULT_BUFFER)
#define IE_I4_PRED_MODE_HI 0x1f45 	///../ucode/dos_register.h:1831
#define P_IE_I4_PRED_MODE_HI 		DOS_REG_ADDR(IE_I4_PRED_MODE_HI)
#define IE_I4_PRED_MODE_LO 0x1f46 	///../ucode/dos_register.h:1832
#define P_IE_I4_PRED_MODE_LO 		DOS_REG_ADDR(IE_I4_PRED_MODE_LO)
#define IE_C_PRED_MODE 0x1f47 	///../ucode/dos_register.h:1836
#define P_IE_C_PRED_MODE 		DOS_REG_ADDR(IE_C_PRED_MODE)
#define IE_CUR_REF_SEL 0x1f48 	///../ucode/dos_register.h:1839
#define P_IE_CUR_REF_SEL 		DOS_REG_ADDR(IE_CUR_REF_SEL)
#define ME_CONTROL 0x1f49 	///../ucode/dos_register.h:1860
#define P_ME_CONTROL 		DOS_REG_ADDR(ME_CONTROL)
#define ME_START_POSITION 0x1f4a 	///../ucode/dos_register.h:1865
#define P_ME_START_POSITION 		DOS_REG_ADDR(ME_START_POSITION)
#define ME_STATUS 0x1f4b 	///../ucode/dos_register.h:1874
#define P_ME_STATUS 		DOS_REG_ADDR(ME_STATUS)
#define ME_DEBUG 0x1f4c 	///../ucode/dos_register.h:1881
#define P_ME_DEBUG 		DOS_REG_ADDR(ME_DEBUG)
#define ME_SKIP_LINE 0x1f4d 	///../ucode/dos_register.h:1887
#define P_ME_SKIP_LINE 		DOS_REG_ADDR(ME_SKIP_LINE)
#define ME_AB_MEM_CTL 0x1f4e 	///../ucode/dos_register.h:1892
#define P_ME_AB_MEM_CTL 		DOS_REG_ADDR(ME_AB_MEM_CTL)
#define ME_PIC_INFO 0x1f4f 	///../ucode/dos_register.h:1896
#define P_ME_PIC_INFO 		DOS_REG_ADDR(ME_PIC_INFO)
#define ME_SAD_ENOUGH_01 0x1f50 	///../ucode/dos_register.h:1899
#define P_ME_SAD_ENOUGH_01 		DOS_REG_ADDR(ME_SAD_ENOUGH_01)
#define ME_SAD_ENOUGH_23 0x1f51 	///../ucode/dos_register.h:1902
#define P_ME_SAD_ENOUGH_23 		DOS_REG_ADDR(ME_SAD_ENOUGH_23)
#define ME_STEP0_CLOSE_MV 0x1f52 	///../ucode/dos_register.h:1906
#define P_ME_STEP0_CLOSE_MV 		DOS_REG_ADDR(ME_STEP0_CLOSE_MV)
#define ME_F_SKIP_SAD 0x1f53 	///../ucode/dos_register.h:1911
#define P_ME_F_SKIP_SAD 		DOS_REG_ADDR(ME_F_SKIP_SAD)
#define ME_F_SKIP_WEIGHT 0x1f54 	///../ucode/dos_register.h:1916
#define P_ME_F_SKIP_WEIGHT 		DOS_REG_ADDR(ME_F_SKIP_WEIGHT)
#define ME_MV_MERGE_CTL 0x1f55 	///../ucode/dos_register.h:1935
#define P_ME_MV_MERGE_CTL 		DOS_REG_ADDR(ME_MV_MERGE_CTL)
#define ME_MV_WEIGHT_01 0x1f56 	///../ucode/dos_register.h:1940
#define P_ME_MV_WEIGHT_01 		DOS_REG_ADDR(ME_MV_WEIGHT_01)
#define ME_MV_WEIGHT_23 0x1f57 	///../ucode/dos_register.h:1945
#define P_ME_MV_WEIGHT_23 		DOS_REG_ADDR(ME_MV_WEIGHT_23)
#define ME_SAD_RANGE_INC 0x1f58 	///../ucode/dos_register.h:1950
#define P_ME_SAD_RANGE_INC 		DOS_REG_ADDR(ME_SAD_RANGE_INC)
#define ME_SUB_MERGE_CTL 0x1f59 	///../ucode/dos_register.h:1964
#define P_ME_SUB_MERGE_CTL 		DOS_REG_ADDR(ME_SUB_MERGE_CTL)
#define ME_SUB_REF_MV_CTL 0x1f5a 	///../ucode/dos_register.h:1971
#define P_ME_SUB_REF_MV_CTL 		DOS_REG_ADDR(ME_SUB_REF_MV_CTL)
#define ME_SUB_ANY_WEIGHT_SAD 0x1f5b 	///../ucode/dos_register.h:1976
#define P_ME_SUB_ANY_WEIGHT_SAD 		DOS_REG_ADDR(ME_SUB_ANY_WEIGHT_SAD)
#define ME_SUB_FIX_SAD 0x1f5c 	///../ucode/dos_register.h:1981
#define P_ME_SUB_FIX_SAD 		DOS_REG_ADDR(ME_SUB_FIX_SAD)
#define ME_SUB_FIX_MIN_SAD 0x1f5d 	///../ucode/dos_register.h:1986
#define P_ME_SUB_FIX_MIN_SAD 		DOS_REG_ADDR(ME_SUB_FIX_MIN_SAD)
#define ME_SUB_SNAP_GLITCH 0x1f5e 	///../ucode/dos_register.h:1992
#define P_ME_SUB_SNAP_GLITCH 		DOS_REG_ADDR(ME_SUB_SNAP_GLITCH)
#define ME_SUB_ACT_CTL 0x1f5f 	///../ucode/dos_register.h:2002
#define P_ME_SUB_ACT_CTL 		DOS_REG_ADDR(ME_SUB_ACT_CTL)
#define HEVC_ASSIST_MMC_CTRL0 0x3001 	///../ucode/dos_register.h:2903
#define P_HEVC_ASSIST_MMC_CTRL0 		DOS_REG_ADDR(HEVC_ASSIST_MMC_CTRL0)
#define HEVC_ASSIST_MMC_CTRL1 0x3002 	///../ucode/dos_register.h:2904
#define P_HEVC_ASSIST_MMC_CTRL1 		DOS_REG_ADDR(HEVC_ASSIST_MMC_CTRL1)
#define HEVC_ASSIST_GCLK_EN 0x3003 	///../ucode/dos_register.h:2905
#define P_HEVC_ASSIST_GCLK_EN 		DOS_REG_ADDR(HEVC_ASSIST_GCLK_EN)
#define HEVC_ASSIST_SW_RESET 0x3004 	///../ucode/dos_register.h:2906
#define P_HEVC_ASSIST_SW_RESET 		DOS_REG_ADDR(HEVC_ASSIST_SW_RESET)
#define HEVC_ASSIST_AMR1_INT0 0x3025 	///../ucode/dos_register.h:2907
#define P_HEVC_ASSIST_AMR1_INT0 		DOS_REG_ADDR(HEVC_ASSIST_AMR1_INT0)
#define HEVC_ASSIST_AMR1_INT1 0x3026 	///../ucode/dos_register.h:2908
#define P_HEVC_ASSIST_AMR1_INT1 		DOS_REG_ADDR(HEVC_ASSIST_AMR1_INT1)
#define HEVC_ASSIST_AMR1_INT2 0x3027 	///../ucode/dos_register.h:2909
#define P_HEVC_ASSIST_AMR1_INT2 		DOS_REG_ADDR(HEVC_ASSIST_AMR1_INT2)
#define HEVC_ASSIST_AMR1_INT3 0x3028 	///../ucode/dos_register.h:2910
#define P_HEVC_ASSIST_AMR1_INT3 		DOS_REG_ADDR(HEVC_ASSIST_AMR1_INT3)
#define HEVC_ASSIST_AMR1_INT4 0x3029 	///../ucode/dos_register.h:2911
#define P_HEVC_ASSIST_AMR1_INT4 		DOS_REG_ADDR(HEVC_ASSIST_AMR1_INT4)
#define HEVC_ASSIST_AMR1_INT5 0x302a 	///../ucode/dos_register.h:2912
#define P_HEVC_ASSIST_AMR1_INT5 		DOS_REG_ADDR(HEVC_ASSIST_AMR1_INT5)
#define HEVC_ASSIST_AMR1_INT6 0x302b 	///../ucode/dos_register.h:2913
#define P_HEVC_ASSIST_AMR1_INT6 		DOS_REG_ADDR(HEVC_ASSIST_AMR1_INT6)
#define HEVC_ASSIST_AMR1_INT7 0x302c 	///../ucode/dos_register.h:2914
#define P_HEVC_ASSIST_AMR1_INT7 		DOS_REG_ADDR(HEVC_ASSIST_AMR1_INT7)
#define HEVC_ASSIST_AMR1_INT8 0x302d 	///../ucode/dos_register.h:2915
#define P_HEVC_ASSIST_AMR1_INT8 		DOS_REG_ADDR(HEVC_ASSIST_AMR1_INT8)
#define HEVC_ASSIST_AMR1_INT9 0x302e 	///../ucode/dos_register.h:2916
#define P_HEVC_ASSIST_AMR1_INT9 		DOS_REG_ADDR(HEVC_ASSIST_AMR1_INT9)
#define HEVC_ASSIST_AMR1_INTA 0x302f 	///../ucode/dos_register.h:2917
#define P_HEVC_ASSIST_AMR1_INTA 		DOS_REG_ADDR(HEVC_ASSIST_AMR1_INTA)
#define HEVC_ASSIST_AMR1_INTB 0x3030 	///../ucode/dos_register.h:2918
#define P_HEVC_ASSIST_AMR1_INTB 		DOS_REG_ADDR(HEVC_ASSIST_AMR1_INTB)
#define HEVC_ASSIST_AMR1_INTC 0x3031 	///../ucode/dos_register.h:2919
#define P_HEVC_ASSIST_AMR1_INTC 		DOS_REG_ADDR(HEVC_ASSIST_AMR1_INTC)
#define HEVC_ASSIST_AMR1_INTD 0x3032 	///../ucode/dos_register.h:2920
#define P_HEVC_ASSIST_AMR1_INTD 		DOS_REG_ADDR(HEVC_ASSIST_AMR1_INTD)
#define HEVC_ASSIST_AMR1_INTE 0x3033 	///../ucode/dos_register.h:2921
#define P_HEVC_ASSIST_AMR1_INTE 		DOS_REG_ADDR(HEVC_ASSIST_AMR1_INTE)
#define HEVC_ASSIST_AMR1_INTF 0x3034 	///../ucode/dos_register.h:2922
#define P_HEVC_ASSIST_AMR1_INTF 		DOS_REG_ADDR(HEVC_ASSIST_AMR1_INTF)
#define HEVC_ASSIST_AMR2_INT0 0x3035 	///../ucode/dos_register.h:2923
#define P_HEVC_ASSIST_AMR2_INT0 		DOS_REG_ADDR(HEVC_ASSIST_AMR2_INT0)
#define HEVC_ASSIST_AMR2_INT1 0x3036 	///../ucode/dos_register.h:2924
#define P_HEVC_ASSIST_AMR2_INT1 		DOS_REG_ADDR(HEVC_ASSIST_AMR2_INT1)
#define HEVC_ASSIST_AMR2_INT2 0x3037 	///../ucode/dos_register.h:2925
#define P_HEVC_ASSIST_AMR2_INT2 		DOS_REG_ADDR(HEVC_ASSIST_AMR2_INT2)
#define HEVC_ASSIST_AMR2_INT3 0x3038 	///../ucode/dos_register.h:2926
#define P_HEVC_ASSIST_AMR2_INT3 		DOS_REG_ADDR(HEVC_ASSIST_AMR2_INT3)
#define HEVC_ASSIST_AMR2_INT4 0x3039 	///../ucode/dos_register.h:2927
#define P_HEVC_ASSIST_AMR2_INT4 		DOS_REG_ADDR(HEVC_ASSIST_AMR2_INT4)
#define HEVC_ASSIST_AMR2_INT5 0x303a 	///../ucode/dos_register.h:2928
#define P_HEVC_ASSIST_AMR2_INT5 		DOS_REG_ADDR(HEVC_ASSIST_AMR2_INT5)
#define HEVC_ASSIST_AMR2_INT6 0x303b 	///../ucode/dos_register.h:2929
#define P_HEVC_ASSIST_AMR2_INT6 		DOS_REG_ADDR(HEVC_ASSIST_AMR2_INT6)
#define HEVC_ASSIST_AMR2_INT7 0x303c 	///../ucode/dos_register.h:2930
#define P_HEVC_ASSIST_AMR2_INT7 		DOS_REG_ADDR(HEVC_ASSIST_AMR2_INT7)
#define HEVC_ASSIST_AMR2_INT8 0x303d 	///../ucode/dos_register.h:2931
#define P_HEVC_ASSIST_AMR2_INT8 		DOS_REG_ADDR(HEVC_ASSIST_AMR2_INT8)
#define HEVC_ASSIST_AMR2_INT9 0x303e 	///../ucode/dos_register.h:2932
#define P_HEVC_ASSIST_AMR2_INT9 		DOS_REG_ADDR(HEVC_ASSIST_AMR2_INT9)
#define HEVC_ASSIST_AMR2_INTA 0x303f 	///../ucode/dos_register.h:2933
#define P_HEVC_ASSIST_AMR2_INTA 		DOS_REG_ADDR(HEVC_ASSIST_AMR2_INTA)
#define HEVC_ASSIST_AMR2_INTB 0x3040 	///../ucode/dos_register.h:2934
#define P_HEVC_ASSIST_AMR2_INTB 		DOS_REG_ADDR(HEVC_ASSIST_AMR2_INTB)
#define HEVC_ASSIST_AMR2_INTC 0x3041 	///../ucode/dos_register.h:2935
#define P_HEVC_ASSIST_AMR2_INTC 		DOS_REG_ADDR(HEVC_ASSIST_AMR2_INTC)
#define HEVC_ASSIST_AMR2_INTD 0x3042 	///../ucode/dos_register.h:2936
#define P_HEVC_ASSIST_AMR2_INTD 		DOS_REG_ADDR(HEVC_ASSIST_AMR2_INTD)
#define HEVC_ASSIST_AMR2_INTE 0x3043 	///../ucode/dos_register.h:2937
#define P_HEVC_ASSIST_AMR2_INTE 		DOS_REG_ADDR(HEVC_ASSIST_AMR2_INTE)
#define HEVC_ASSIST_AMR2_INTF 0x3044 	///../ucode/dos_register.h:2938
#define P_HEVC_ASSIST_AMR2_INTF 		DOS_REG_ADDR(HEVC_ASSIST_AMR2_INTF)
#define HEVC_ASSIST_MBX_SSEL 0x3045 	///../ucode/dos_register.h:2939
#define P_HEVC_ASSIST_MBX_SSEL 		DOS_REG_ADDR(HEVC_ASSIST_MBX_SSEL)
#define HEVC_ASSIST_TIMER0_LO 0x3060 	///../ucode/dos_register.h:2940
#define P_HEVC_ASSIST_TIMER0_LO 		DOS_REG_ADDR(HEVC_ASSIST_TIMER0_LO)
#define HEVC_ASSIST_TIMER0_HI 0x3061 	///../ucode/dos_register.h:2941
#define P_HEVC_ASSIST_TIMER0_HI 		DOS_REG_ADDR(HEVC_ASSIST_TIMER0_HI)
#define HEVC_ASSIST_TIMER1_LO 0x3062 	///../ucode/dos_register.h:2942
#define P_HEVC_ASSIST_TIMER1_LO 		DOS_REG_ADDR(HEVC_ASSIST_TIMER1_LO)
#define HEVC_ASSIST_TIMER1_HI 0x3063 	///../ucode/dos_register.h:2943
#define P_HEVC_ASSIST_TIMER1_HI 		DOS_REG_ADDR(HEVC_ASSIST_TIMER1_HI)
#define HEVC_ASSIST_DMA_INT 0x3064 	///../ucode/dos_register.h:2944
#define P_HEVC_ASSIST_DMA_INT 		DOS_REG_ADDR(HEVC_ASSIST_DMA_INT)
#define HEVC_ASSIST_DMA_INT_MSK 0x3065 	///../ucode/dos_register.h:2945
#define P_HEVC_ASSIST_DMA_INT_MSK 		DOS_REG_ADDR(HEVC_ASSIST_DMA_INT_MSK)
#define HEVC_ASSIST_DMA_INT2 0x3066 	///../ucode/dos_register.h:2946
#define P_HEVC_ASSIST_DMA_INT2 		DOS_REG_ADDR(HEVC_ASSIST_DMA_INT2)
#define HEVC_ASSIST_DMA_INT_MSK2 0x3067 	///../ucode/dos_register.h:2947
#define P_HEVC_ASSIST_DMA_INT_MSK2 		DOS_REG_ADDR(HEVC_ASSIST_DMA_INT_MSK2)
#define HEVC_ASSIST_MBOX0_IRQ_REG 0x3070 	///../ucode/dos_register.h:2948
#define P_HEVC_ASSIST_MBOX0_IRQ_REG 		DOS_REG_ADDR(HEVC_ASSIST_MBOX0_IRQ_REG)
#define HEVC_ASSIST_MBOX0_CLR_REG 0x3071 	///../ucode/dos_register.h:2949
#define P_HEVC_ASSIST_MBOX0_CLR_REG 		DOS_REG_ADDR(HEVC_ASSIST_MBOX0_CLR_REG)
#define HEVC_ASSIST_MBOX0_MASK 0x3072 	///../ucode/dos_register.h:2950
#define P_HEVC_ASSIST_MBOX0_MASK 		DOS_REG_ADDR(HEVC_ASSIST_MBOX0_MASK)
#define HEVC_ASSIST_MBOX0_FIQ_SEL 0x3073 	///../ucode/dos_register.h:2951
#define P_HEVC_ASSIST_MBOX0_FIQ_SEL 		DOS_REG_ADDR(HEVC_ASSIST_MBOX0_FIQ_SEL)
#define HEVC_ASSIST_MBOX1_IRQ_REG 0x3074 	///../ucode/dos_register.h:2952
#define P_HEVC_ASSIST_MBOX1_IRQ_REG 		DOS_REG_ADDR(HEVC_ASSIST_MBOX1_IRQ_REG)
#define HEVC_ASSIST_MBOX1_CLR_REG 0x3075 	///../ucode/dos_register.h:2953
#define P_HEVC_ASSIST_MBOX1_CLR_REG 		DOS_REG_ADDR(HEVC_ASSIST_MBOX1_CLR_REG)
#define HEVC_ASSIST_MBOX1_MASK 0x3076 	///../ucode/dos_register.h:2954
#define P_HEVC_ASSIST_MBOX1_MASK 		DOS_REG_ADDR(HEVC_ASSIST_MBOX1_MASK)
#define HEVC_ASSIST_MBOX1_FIQ_SEL 0x3077 	///../ucode/dos_register.h:2955
#define P_HEVC_ASSIST_MBOX1_FIQ_SEL 		DOS_REG_ADDR(HEVC_ASSIST_MBOX1_FIQ_SEL)
#define HEVC_ASSIST_MBOX2_IRQ_REG 0x3078 	///../ucode/dos_register.h:2956
#define P_HEVC_ASSIST_MBOX2_IRQ_REG 		DOS_REG_ADDR(HEVC_ASSIST_MBOX2_IRQ_REG)
#define HEVC_ASSIST_MBOX2_CLR_REG 0x3079 	///../ucode/dos_register.h:2957
#define P_HEVC_ASSIST_MBOX2_CLR_REG 		DOS_REG_ADDR(HEVC_ASSIST_MBOX2_CLR_REG)
#define HEVC_ASSIST_MBOX2_MASK 0x307a 	///../ucode/dos_register.h:2958
#define P_HEVC_ASSIST_MBOX2_MASK 		DOS_REG_ADDR(HEVC_ASSIST_MBOX2_MASK)
#define HEVC_ASSIST_MBOX2_FIQ_SEL 0x307b 	///../ucode/dos_register.h:2959
#define P_HEVC_ASSIST_MBOX2_FIQ_SEL 		DOS_REG_ADDR(HEVC_ASSIST_MBOX2_FIQ_SEL)
#define HEVC_ASSIST_AXI_CTRL 0x307c
#define P_HEVC_ASSIST_AXI_CTRL 		DOS_REG_ADDR(HEVC_ASSIST_AXI_CTRL)
#define HEVC_ASSIST_AXI_STATUS 0x307d
#define P_HEVC_ASSIST_AXI_STATUS 		DOS_REG_ADDR(HEVC_ASSIST_AXI_STATUS)
#define HEVC_ASSIST_SCRATCH_0 0x30c0 	///../ucode/dos_register.h:2960
#define P_HEVC_ASSIST_SCRATCH_0 		DOS_REG_ADDR(HEVC_ASSIST_SCRATCH_0)
#define HEVC_ASSIST_SCRATCH_1 0x30c1 	///../ucode/dos_register.h:2961
#define P_HEVC_ASSIST_SCRATCH_1 		DOS_REG_ADDR(HEVC_ASSIST_SCRATCH_1)
#define HEVC_ASSIST_SCRATCH_2 0x30c2 	///../ucode/dos_register.h:2962
#define P_HEVC_ASSIST_SCRATCH_2 		DOS_REG_ADDR(HEVC_ASSIST_SCRATCH_2)
#define HEVC_ASSIST_SCRATCH_3 0x30c3 	///../ucode/dos_register.h:2963
#define P_HEVC_ASSIST_SCRATCH_3 		DOS_REG_ADDR(HEVC_ASSIST_SCRATCH_3)
#define HEVC_ASSIST_SCRATCH_4 0x30c4 	///../ucode/dos_register.h:2964
#define P_HEVC_ASSIST_SCRATCH_4 		DOS_REG_ADDR(HEVC_ASSIST_SCRATCH_4)
#define HEVC_ASSIST_SCRATCH_5 0x30c5 	///../ucode/dos_register.h:2965
#define P_HEVC_ASSIST_SCRATCH_5 		DOS_REG_ADDR(HEVC_ASSIST_SCRATCH_5)
#define HEVC_ASSIST_SCRATCH_6 0x30c6 	///../ucode/dos_register.h:2966
#define P_HEVC_ASSIST_SCRATCH_6 		DOS_REG_ADDR(HEVC_ASSIST_SCRATCH_6)
#define HEVC_ASSIST_SCRATCH_7 0x30c7 	///../ucode/dos_register.h:2967
#define P_HEVC_ASSIST_SCRATCH_7 		DOS_REG_ADDR(HEVC_ASSIST_SCRATCH_7)
#define HEVC_ASSIST_SCRATCH_8 0x30c8 	///../ucode/dos_register.h:2968
#define P_HEVC_ASSIST_SCRATCH_8 		DOS_REG_ADDR(HEVC_ASSIST_SCRATCH_8)
#define HEVC_ASSIST_SCRATCH_9 0x30c9 	///../ucode/dos_register.h:2969
#define P_HEVC_ASSIST_SCRATCH_9 		DOS_REG_ADDR(HEVC_ASSIST_SCRATCH_9)
#define HEVC_ASSIST_SCRATCH_A 0x30ca 	///../ucode/dos_register.h:2970
#define P_HEVC_ASSIST_SCRATCH_A 		DOS_REG_ADDR(HEVC_ASSIST_SCRATCH_A)
#define HEVC_ASSIST_SCRATCH_B 0x30cb 	///../ucode/dos_register.h:2971
#define P_HEVC_ASSIST_SCRATCH_B 		DOS_REG_ADDR(HEVC_ASSIST_SCRATCH_B)
#define HEVC_ASSIST_SCRATCH_C 0x30cc 	///../ucode/dos_register.h:2972
#define P_HEVC_ASSIST_SCRATCH_C 		DOS_REG_ADDR(HEVC_ASSIST_SCRATCH_C)
#define HEVC_ASSIST_SCRATCH_D 0x30cd 	///../ucode/dos_register.h:2973
#define P_HEVC_ASSIST_SCRATCH_D 		DOS_REG_ADDR(HEVC_ASSIST_SCRATCH_D)
#define HEVC_ASSIST_SCRATCH_E 0x30ce 	///../ucode/dos_register.h:2974
#define P_HEVC_ASSIST_SCRATCH_E 		DOS_REG_ADDR(HEVC_ASSIST_SCRATCH_E)
#define HEVC_ASSIST_SCRATCH_F 0x30cf 	///../ucode/dos_register.h:2975
#define P_HEVC_ASSIST_SCRATCH_F 		DOS_REG_ADDR(HEVC_ASSIST_SCRATCH_F)
#define HEVC_ASSIST_SCRATCH_G 0x30d0 	///../ucode/dos_register.h:2976
#define P_HEVC_ASSIST_SCRATCH_G 		DOS_REG_ADDR(HEVC_ASSIST_SCRATCH_G)
#define HEVC_ASSIST_SCRATCH_H 0x30d1 	///../ucode/dos_register.h:2977
#define P_HEVC_ASSIST_SCRATCH_H 		DOS_REG_ADDR(HEVC_ASSIST_SCRATCH_H)
#define HEVC_ASSIST_SCRATCH_I 0x30d2 	///../ucode/dos_register.h:2978
#define P_HEVC_ASSIST_SCRATCH_I 		DOS_REG_ADDR(HEVC_ASSIST_SCRATCH_I)
#define HEVC_ASSIST_SCRATCH_J 0x30d3 	///../ucode/dos_register.h:2979
#define P_HEVC_ASSIST_SCRATCH_J 		DOS_REG_ADDR(HEVC_ASSIST_SCRATCH_J)
#define HEVC_ASSIST_SCRATCH_K 0x30d4 	///../ucode/dos_register.h:2980
#define P_HEVC_ASSIST_SCRATCH_K 		DOS_REG_ADDR(HEVC_ASSIST_SCRATCH_K)
#define HEVC_ASSIST_SCRATCH_L 0x30d5 	///../ucode/dos_register.h:2981
#define P_HEVC_ASSIST_SCRATCH_L 		DOS_REG_ADDR(HEVC_ASSIST_SCRATCH_L)
#define HEVC_ASSIST_SCRATCH_M 0x30d6 	///../ucode/dos_register.h:2982
#define P_HEVC_ASSIST_SCRATCH_M 		DOS_REG_ADDR(HEVC_ASSIST_SCRATCH_M)
#define HEVC_ASSIST_SCRATCH_N 0x30d7 	///../ucode/dos_register.h:2983
#define P_HEVC_ASSIST_SCRATCH_N 		DOS_REG_ADDR(HEVC_ASSIST_SCRATCH_N)
#define HEVC_PARSER_VERSION 0x3100 	///../ucode/dos_register.h:3001
#define P_HEVC_PARSER_VERSION 		DOS_REG_ADDR(HEVC_PARSER_VERSION)
#define HEVC_STREAM_CONTROL 0x3101 	///../ucode/dos_register.h:3010
#define P_HEVC_STREAM_CONTROL 		DOS_REG_ADDR(HEVC_STREAM_CONTROL)
#define HEVC_STREAM_START_ADDR 0x3102 	///../ucode/dos_register.h:3011
#define P_HEVC_STREAM_START_ADDR 		DOS_REG_ADDR(HEVC_STREAM_START_ADDR)
#define HEVC_STREAM_END_ADDR 0x3103 	///../ucode/dos_register.h:3012
#define P_HEVC_STREAM_END_ADDR 		DOS_REG_ADDR(HEVC_STREAM_END_ADDR)
#define HEVC_STREAM_WR_PTR 0x3104 	///../ucode/dos_register.h:3014
#define P_HEVC_STREAM_WR_PTR 		DOS_REG_ADDR(HEVC_STREAM_WR_PTR)
#define HEVC_STREAM_RD_PTR 0x3105 	///../ucode/dos_register.h:3015
#define P_HEVC_STREAM_RD_PTR 		DOS_REG_ADDR(HEVC_STREAM_RD_PTR)
#define HEVC_STREAM_LEVEL 0x3106 	///../ucode/dos_register.h:3017
#define P_HEVC_STREAM_LEVEL 		DOS_REG_ADDR(HEVC_STREAM_LEVEL)
#define HEVC_STREAM_FIFO_CTL 0x3107 	///../ucode/dos_register.h:3025
#define P_HEVC_STREAM_FIFO_CTL 		DOS_REG_ADDR(HEVC_STREAM_FIFO_CTL)
#define HEVC_SHIFT_CONTROL 0x3108 	///../ucode/dos_register.h:3034
#define P_HEVC_SHIFT_CONTROL 		DOS_REG_ADDR(HEVC_SHIFT_CONTROL)
#define HEVC_SHIFT_STARTCODE 0x3109 	///../ucode/dos_register.h:3036
#define P_HEVC_SHIFT_STARTCODE 		DOS_REG_ADDR(HEVC_SHIFT_STARTCODE)
#define HEVC_SHIFT_EMULATECODE 0x310a 	///../ucode/dos_register.h:3038
#define P_HEVC_SHIFT_EMULATECODE 		DOS_REG_ADDR(HEVC_SHIFT_EMULATECODE)
#define HEVC_SHIFT_STATUS 0x310b 	///../ucode/dos_register.h:3042
#define P_HEVC_SHIFT_STATUS 		DOS_REG_ADDR(HEVC_SHIFT_STATUS)
#define HEVC_SHIFTED_DATA 0x310c 	///../ucode/dos_register.h:3044
#define P_HEVC_SHIFTED_DATA 		DOS_REG_ADDR(HEVC_SHIFTED_DATA)
#define HEVC_SHIFT_BYTE_COUNT 0x310d 	///../ucode/dos_register.h:3046
#define P_HEVC_SHIFT_BYTE_COUNT 		DOS_REG_ADDR(HEVC_SHIFT_BYTE_COUNT)
#define HEVC_SHIFT_COMMAND 0x310e 	///../ucode/dos_register.h:3054
#define P_HEVC_SHIFT_COMMAND 		DOS_REG_ADDR(HEVC_SHIFT_COMMAND)
#define HEVC_ELEMENT_RESULT 0x310f 	///../ucode/dos_register.h:3058
#define P_HEVC_ELEMENT_RESULT 		DOS_REG_ADDR(HEVC_ELEMENT_RESULT)
#define HEVC_CABAC_CONTROL 0x3110 	///../ucode/dos_register.h:3066
#define P_HEVC_CABAC_CONTROL 		DOS_REG_ADDR(HEVC_CABAC_CONTROL)
#define HEVC_PARSER_SLICE_INFO 0x3111 	///../ucode/dos_register.h:3077
#define P_HEVC_PARSER_SLICE_INFO 		DOS_REG_ADDR(HEVC_PARSER_SLICE_INFO)
#define HEVC_PARSER_CMD_WRITE 0x3112 	///../ucode/dos_register.h:3080
#define P_HEVC_PARSER_CMD_WRITE 		DOS_REG_ADDR(HEVC_PARSER_CMD_WRITE)
#define HEVC_PARSER_CORE_CONTROL 0x3113 	///../ucode/dos_register.h:3085
#define P_HEVC_PARSER_CORE_CONTROL 		DOS_REG_ADDR(HEVC_PARSER_CORE_CONTROL)
#define HEVC_PARSER_CMD_FETCH 0x3114 	///../ucode/dos_register.h:3093
#define P_HEVC_PARSER_CMD_FETCH 		DOS_REG_ADDR(HEVC_PARSER_CMD_FETCH)
#define HEVC_PARSER_CMD_STATUS 0x3115 	///../ucode/dos_register.h:3097
#define P_HEVC_PARSER_CMD_STATUS 		DOS_REG_ADDR(HEVC_PARSER_CMD_STATUS)
#define HEVC_PARSER_LCU_INFO 0x3116 	///../ucode/dos_register.h:3105
#define P_HEVC_PARSER_LCU_INFO 		DOS_REG_ADDR(HEVC_PARSER_LCU_INFO)
#define HEVC_PARSER_HEADER_INFO 0x3117 	///../ucode/dos_register.h:3119
#define P_HEVC_PARSER_HEADER_INFO 		DOS_REG_ADDR(HEVC_PARSER_HEADER_INFO)
#define HEVC_PARSER_RESULT_0 0x3118 	///../ucode/dos_register.h:3120
#define P_HEVC_PARSER_RESULT_0 		DOS_REG_ADDR(HEVC_PARSER_RESULT_0)
#define HEVC_PARSER_RESULT_1 0x3119 	///../ucode/dos_register.h:3121
#define P_HEVC_PARSER_RESULT_1 		DOS_REG_ADDR(HEVC_PARSER_RESULT_1)
#define HEVC_PARSER_RESULT_2 0x311a 	///../ucode/dos_register.h:3122
#define P_HEVC_PARSER_RESULT_2 		DOS_REG_ADDR(HEVC_PARSER_RESULT_2)
#define HEVC_PARSER_RESULT_3 0x311b 	///../ucode/dos_register.h:3123
#define P_HEVC_PARSER_RESULT_3 		DOS_REG_ADDR(HEVC_PARSER_RESULT_3)
#define HEVC_CABAC_TOP_INFO 0x311c 	///../ucode/dos_register.h:3130
#define P_HEVC_CABAC_TOP_INFO 		DOS_REG_ADDR(HEVC_CABAC_TOP_INFO)
#define HEVC_CABAC_TOP_INFO_2 0x311d 	///../ucode/dos_register.h:3132
#define P_HEVC_CABAC_TOP_INFO_2 		DOS_REG_ADDR(HEVC_CABAC_TOP_INFO_2)
#define HEVC_CABAC_LEFT_INFO 0x311e 	///../ucode/dos_register.h:3139
#define P_HEVC_CABAC_LEFT_INFO 		DOS_REG_ADDR(HEVC_CABAC_LEFT_INFO)
#define HEVC_CABAC_LEFT_INFO_2 0x311f 	///../ucode/dos_register.h:3141
#define P_HEVC_CABAC_LEFT_INFO_2 		DOS_REG_ADDR(HEVC_CABAC_LEFT_INFO_2)
#define HEVC_PARSER_INT_CONTROL 0x3120 	///../ucode/dos_register.h:3158
#define P_HEVC_PARSER_INT_CONTROL 		DOS_REG_ADDR(HEVC_PARSER_INT_CONTROL)
#define HEVC_PARSER_INT_STATUS 0x3121 	///../ucode/dos_register.h:3164
#define P_HEVC_PARSER_INT_STATUS 		DOS_REG_ADDR(HEVC_PARSER_INT_STATUS)
#define HEVC_PARSER_IF_CONTROL 0x3122 	///../ucode/dos_register.h:3174
#define P_HEVC_PARSER_IF_CONTROL 		DOS_REG_ADDR(HEVC_PARSER_IF_CONTROL)
#define HEVC_PARSER_PICTURE_SIZE 0x3123 	///../ucode/dos_register.h:3177
#define P_HEVC_PARSER_PICTURE_SIZE 		DOS_REG_ADDR(HEVC_PARSER_PICTURE_SIZE)
#define HEVC_PARSER_LCU_START 0x3124 	///../ucode/dos_register.h:3182
#define P_HEVC_PARSER_LCU_START 		DOS_REG_ADDR(HEVC_PARSER_LCU_START)
#define HEVC_PARSER_HEADER_INFO2 0x3125 	///../ucode/dos_register.h:3189
#define P_HEVC_PARSER_HEADER_INFO2 		DOS_REG_ADDR(HEVC_PARSER_HEADER_INFO2)
#define HEVC_PARSER_QUANT_READ 0x3126 	///../ucode/dos_register.h:3200
#define P_HEVC_PARSER_QUANT_READ 		DOS_REG_ADDR(HEVC_PARSER_QUANT_READ)
#define HEVC_PARSER_RESERVED_27 0x3127 	///../ucode/dos_register.h:3201
#define P_HEVC_PARSER_RESERVED_27 		DOS_REG_ADDR(HEVC_PARSER_RESERVED_27)
#define HEVC_PARSER_CMD_SKIP_0 0x3128 	///../ucode/dos_register.h:3204
#define P_HEVC_PARSER_CMD_SKIP_0 		DOS_REG_ADDR(HEVC_PARSER_CMD_SKIP_0)
#define HEVC_PARSER_CMD_SKIP_1 0x3129 	///../ucode/dos_register.h:3209
#define P_HEVC_PARSER_CMD_SKIP_1 		DOS_REG_ADDR(HEVC_PARSER_CMD_SKIP_1)
#define HEVC_PARSER_CMD_SKIP_2 0x312a 	///../ucode/dos_register.h:3214
#define P_HEVC_PARSER_CMD_SKIP_2 		DOS_REG_ADDR(HEVC_PARSER_CMD_SKIP_2)
#define HEVC_PARSER_MANUAL_CMD 0x312b 	///../ucode/dos_register.h:3228
#define P_HEVC_PARSER_MANUAL_CMD 		DOS_REG_ADDR(HEVC_PARSER_MANUAL_CMD)
#define HEVC_PARSER_MEM_RD_ADDR 0x312c 	///../ucode/dos_register.h:3233
#define P_HEVC_PARSER_MEM_RD_ADDR 		DOS_REG_ADDR(HEVC_PARSER_MEM_RD_ADDR)
#define HEVC_PARSER_MEM_WR_ADDR 0x312d 	///../ucode/dos_register.h:3238
#define P_HEVC_PARSER_MEM_WR_ADDR 		DOS_REG_ADDR(HEVC_PARSER_MEM_WR_ADDR)
#define HEVC_PARSER_MEM_RW_DATA 0x312e 	///../ucode/dos_register.h:3240
#define P_HEVC_PARSER_MEM_RW_DATA 		DOS_REG_ADDR(HEVC_PARSER_MEM_RW_DATA)
#define HEVC_SAO_IF_STATUS 0x3130 	///../ucode/dos_register.h:3247
#define P_HEVC_SAO_IF_STATUS 		DOS_REG_ADDR(HEVC_SAO_IF_STATUS)
#define HEVC_SAO_IF_DATA_Y 0x3131 	///../ucode/dos_register.h:3255
#define P_HEVC_SAO_IF_DATA_Y 		DOS_REG_ADDR(HEVC_SAO_IF_DATA_Y)
#define HEVC_SAO_IF_DATA_U 0x3132 	///../ucode/dos_register.h:3256
#define P_HEVC_SAO_IF_DATA_U 		DOS_REG_ADDR(HEVC_SAO_IF_DATA_U)
#define HEVC_SAO_IF_DATA_V 0x3133 	///../ucode/dos_register.h:3257
#define P_HEVC_SAO_IF_DATA_V 		DOS_REG_ADDR(HEVC_SAO_IF_DATA_V)
#define HEVC_STREAM_SWAP_ADDR 0x3134 	///../ucode/dos_register.h:3258
#define P_HEVC_STREAM_SWAP_ADDR 		DOS_REG_ADDR(HEVC_STREAM_SWAP_ADDR)
#define HEVC_STREAM_SWAP_CTRL 0x3135 	///../ucode/dos_register.h:3267
#define P_HEVC_STREAM_SWAP_CTRL 		DOS_REG_ADDR(HEVC_STREAM_SWAP_CTRL)
#define HEVC_IQIT_IF_WAIT_CNT 0x3136
#define P_HEVC_IQIT_IF_WAIT_CNT 		DOS_REG_ADDR(HEVC_IQIT_IF_WAIT_CNT)
#define HEVC_MPRED_IF_WAIT_CNT 0x3137
#define P_HEVC_MPRED_IF_WAIT_CNT 		DOS_REG_ADDR(HEVC_MPRED_IF_WAIT_CNT)
#define HEVC_SAO_IF_WAIT_CNT 0x3138
#define P_HEVC_SAO_IF_WAIT_CNT 		DOS_REG_ADDR(HEVC_SAO_IF_WAIT_CNT)
#define HEVC_PARSER_DEBUG_IDX 0x313e 	///../ucode/dos_register.h:3269
#define P_HEVC_PARSER_DEBUG_IDX 		DOS_REG_ADDR(HEVC_PARSER_DEBUG_IDX)
#define HEVC_PARSER_DEBUG_DAT 0x313f 	///../ucode/dos_register.h:3271
#define P_HEVC_PARSER_DEBUG_DAT 		DOS_REG_ADDR(HEVC_PARSER_DEBUG_DAT)
#define HEVC_MPRED_VERSION 0x3200 	///../ucode/dos_register.h:3284
#define P_HEVC_MPRED_VERSION 		DOS_REG_ADDR(HEVC_MPRED_VERSION)
#define HEVC_MPRED_CTRL0 0x3201 	///../ucode/dos_register.h:3286
#define P_HEVC_MPRED_CTRL0 		DOS_REG_ADDR(HEVC_MPRED_CTRL0)
#define HEVC_MPRED_CTRL1 0x3202 	///../ucode/dos_register.h:3306
#define P_HEVC_MPRED_CTRL1 		DOS_REG_ADDR(HEVC_MPRED_CTRL1)
#define HEVC_MPRED_INT_EN 0x3203 	///../ucode/dos_register.h:3310
#define P_HEVC_MPRED_INT_EN 		DOS_REG_ADDR(HEVC_MPRED_INT_EN)
#define HEVC_MPRED_INT_STATUS 0x3204 	///../ucode/dos_register.h:3317
#define P_HEVC_MPRED_INT_STATUS 		DOS_REG_ADDR(HEVC_MPRED_INT_STATUS)
#define HEVC_MPRED_PIC_SIZE 0x3205 	///../ucode/dos_register.h:3320
#define P_HEVC_MPRED_PIC_SIZE 		DOS_REG_ADDR(HEVC_MPRED_PIC_SIZE)
#define HEVC_MPRED_PIC_SIZE_LCU 0x3206 	///../ucode/dos_register.h:3323
#define P_HEVC_MPRED_PIC_SIZE_LCU 		DOS_REG_ADDR(HEVC_MPRED_PIC_SIZE_LCU)
#define HEVC_MPRED_TILE_START 0x3207 	///../ucode/dos_register.h:3326
#define P_HEVC_MPRED_TILE_START 		DOS_REG_ADDR(HEVC_MPRED_TILE_START)
#define HEVC_MPRED_TILE_SIZE_LCU 0x3208 	///../ucode/dos_register.h:3329
#define P_HEVC_MPRED_TILE_SIZE_LCU 		DOS_REG_ADDR(HEVC_MPRED_TILE_SIZE_LCU)
#define HEVC_MPRED_REF_NUM 0x3209 	///../ucode/dos_register.h:3332
#define P_HEVC_MPRED_REF_NUM 		DOS_REG_ADDR(HEVC_MPRED_REF_NUM)
#define HEVC_MPRED_LT_REF 0x320a 	///../ucode/dos_register.h:3337
#define P_HEVC_MPRED_LT_REF 		DOS_REG_ADDR(HEVC_MPRED_LT_REF)
#define HEVC_MPRED_LT_COLREF 0x320b 	///../ucode/dos_register.h:3346
#define P_HEVC_MPRED_LT_COLREF 		DOS_REG_ADDR(HEVC_MPRED_LT_COLREF)
#define HEVC_MPRED_REF_EN_L0 0x320c 	///../ucode/dos_register.h:3355
#define P_HEVC_MPRED_REF_EN_L0 		DOS_REG_ADDR(HEVC_MPRED_REF_EN_L0)
#define HEVC_MPRED_REF_EN_L1 0x320d 	///../ucode/dos_register.h:3360
#define P_HEVC_MPRED_REF_EN_L1 		DOS_REG_ADDR(HEVC_MPRED_REF_EN_L1)
#define HEVC_MPRED_COLREF_EN_L0 0x320e 	///../ucode/dos_register.h:3365
#define P_HEVC_MPRED_COLREF_EN_L0 		DOS_REG_ADDR(HEVC_MPRED_COLREF_EN_L0)
#define HEVC_MPRED_COLREF_EN_L1 0x320f 	///../ucode/dos_register.h:3370
#define P_HEVC_MPRED_COLREF_EN_L1 		DOS_REG_ADDR(HEVC_MPRED_COLREF_EN_L1)
#define HEVC_MPRED_AXI_WCTRL 0x3210 	///../ucode/dos_register.h:3375
#define P_HEVC_MPRED_AXI_WCTRL 		DOS_REG_ADDR(HEVC_MPRED_AXI_WCTRL)
#define HEVC_MPRED_AXI_RCTRL 0x3211 	///../ucode/dos_register.h:3377
#define P_HEVC_MPRED_AXI_RCTRL 		DOS_REG_ADDR(HEVC_MPRED_AXI_RCTRL)
#define HEVC_MPRED_ABV_START_ADDR 0x3212 	///../ucode/dos_register.h:3379
#define P_HEVC_MPRED_ABV_START_ADDR 		DOS_REG_ADDR(HEVC_MPRED_ABV_START_ADDR)
#define HEVC_MPRED_MV_WR_START_ADDR 0x3213
#define P_HEVC_MPRED_MV_WR_START_ADDR 		DOS_REG_ADDR(HEVC_MPRED_MV_WR_START_ADDR)
#define HEVC_MPRED_MV_RD_START_ADDR 0x3214
#define P_HEVC_MPRED_MV_RD_START_ADDR 		DOS_REG_ADDR(HEVC_MPRED_MV_RD_START_ADDR)
#define HEVC_MPRED_MV_WPTR 0x3215 	///../ucode/dos_register.h:3380
#define P_HEVC_MPRED_MV_WPTR 		DOS_REG_ADDR(HEVC_MPRED_MV_WPTR)
#define HEVC_MPRED_MV_RPTR 0x3216 	///../ucode/dos_register.h:3381
#define P_HEVC_MPRED_MV_RPTR 		DOS_REG_ADDR(HEVC_MPRED_MV_RPTR)
#define HEVC_MPRED_MV_WR_ROW_JUMP 0x3217 	///../ucode/dos_register.h:3382
#define P_HEVC_MPRED_MV_WR_ROW_JUMP 		DOS_REG_ADDR(HEVC_MPRED_MV_WR_ROW_JUMP)
#define HEVC_MPRED_MV_RD_ROW_JUMP 0x3218 	///../ucode/dos_register.h:3383
#define P_HEVC_MPRED_MV_RD_ROW_JUMP 		DOS_REG_ADDR(HEVC_MPRED_MV_RD_ROW_JUMP)
#define HEVC_MPRED_CURR_LCU 0x3219 	///../ucode/dos_register.h:3384
#define P_HEVC_MPRED_CURR_LCU 		DOS_REG_ADDR(HEVC_MPRED_CURR_LCU)
#define HEVC_MPRED_ABV_WPTR 0x321a
#define P_HEVC_MPRED_ABV_WPTR 		DOS_REG_ADDR(HEVC_MPRED_ABV_WPTR)
#define HEVC_MPRED_ABV_RDTR 0x321b
#define P_HEVC_MPRED_ABV_RDTR 		DOS_REG_ADDR(HEVC_MPRED_ABV_RDTR)
#define HEVC_MPRED_CTRL2 0x321c
#define P_HEVC_MPRED_CTRL2 		DOS_REG_ADDR(HEVC_MPRED_CTRL2)
#define HEVC_MPRED_CTRL3 0x321d
#define P_HEVC_MPRED_CTRL3 		DOS_REG_ADDR(HEVC_MPRED_CTRL3)
#define HEVC_MPRED_MV_WLCUY 0x321e
#define P_HEVC_MPRED_MV_WLCUY 		DOS_REG_ADDR(HEVC_MPRED_MV_WLCUY)
#define HEVC_MPRED_MV_RLCUY 0x321f
#define P_HEVC_MPRED_MV_RLCUY 		DOS_REG_ADDR(HEVC_MPRED_MV_RLCUY)
#define HEVC_MPRED_L0_REF00_POC 0x3220 	///../ucode/dos_register.h:3385
#define P_HEVC_MPRED_L0_REF00_POC 		DOS_REG_ADDR(HEVC_MPRED_L0_REF00_POC)
#define HEVC_MPRED_L0_REF01_POC 0x3221 	///../ucode/dos_register.h:3386
#define P_HEVC_MPRED_L0_REF01_POC 		DOS_REG_ADDR(HEVC_MPRED_L0_REF01_POC)
#define HEVC_MPRED_L0_REF02_POC 0x3222 	///../ucode/dos_register.h:3387
#define P_HEVC_MPRED_L0_REF02_POC 		DOS_REG_ADDR(HEVC_MPRED_L0_REF02_POC)
#define HEVC_MPRED_L0_REF03_POC 0x3223 	///../ucode/dos_register.h:3388
#define P_HEVC_MPRED_L0_REF03_POC 		DOS_REG_ADDR(HEVC_MPRED_L0_REF03_POC)
#define HEVC_MPRED_L0_REF04_POC 0x3224 	///../ucode/dos_register.h:3389
#define P_HEVC_MPRED_L0_REF04_POC 		DOS_REG_ADDR(HEVC_MPRED_L0_REF04_POC)
#define HEVC_MPRED_L0_REF05_POC 0x3225 	///../ucode/dos_register.h:3390
#define P_HEVC_MPRED_L0_REF05_POC 		DOS_REG_ADDR(HEVC_MPRED_L0_REF05_POC)
#define HEVC_MPRED_L0_REF06_POC 0x3226 	///../ucode/dos_register.h:3391
#define P_HEVC_MPRED_L0_REF06_POC 		DOS_REG_ADDR(HEVC_MPRED_L0_REF06_POC)
#define HEVC_MPRED_L0_REF07_POC 0x3227 	///../ucode/dos_register.h:3392
#define P_HEVC_MPRED_L0_REF07_POC 		DOS_REG_ADDR(HEVC_MPRED_L0_REF07_POC)
#define HEVC_MPRED_L0_REF08_POC 0x3228 	///../ucode/dos_register.h:3393
#define P_HEVC_MPRED_L0_REF08_POC 		DOS_REG_ADDR(HEVC_MPRED_L0_REF08_POC)
#define HEVC_MPRED_L0_REF09_POC 0x3229 	///../ucode/dos_register.h:3394
#define P_HEVC_MPRED_L0_REF09_POC 		DOS_REG_ADDR(HEVC_MPRED_L0_REF09_POC)
#define HEVC_MPRED_L0_REF10_POC 0x322a 	///../ucode/dos_register.h:3395
#define P_HEVC_MPRED_L0_REF10_POC 		DOS_REG_ADDR(HEVC_MPRED_L0_REF10_POC)
#define HEVC_MPRED_L0_REF11_POC 0x322b 	///../ucode/dos_register.h:3396
#define P_HEVC_MPRED_L0_REF11_POC 		DOS_REG_ADDR(HEVC_MPRED_L0_REF11_POC)
#define HEVC_MPRED_L0_REF12_POC 0x322c 	///../ucode/dos_register.h:3397
#define P_HEVC_MPRED_L0_REF12_POC 		DOS_REG_ADDR(HEVC_MPRED_L0_REF12_POC)
#define HEVC_MPRED_L0_REF13_POC 0x322d 	///../ucode/dos_register.h:3398
#define P_HEVC_MPRED_L0_REF13_POC 		DOS_REG_ADDR(HEVC_MPRED_L0_REF13_POC)
#define HEVC_MPRED_L0_REF14_POC 0x322e 	///../ucode/dos_register.h:3399
#define P_HEVC_MPRED_L0_REF14_POC 		DOS_REG_ADDR(HEVC_MPRED_L0_REF14_POC)
#define HEVC_MPRED_L0_REF15_POC 0x322f 	///../ucode/dos_register.h:3400
#define P_HEVC_MPRED_L0_REF15_POC 		DOS_REG_ADDR(HEVC_MPRED_L0_REF15_POC)
#define HEVC_MPRED_L1_REF00_POC 0x3230 	///../ucode/dos_register.h:3401
#define P_HEVC_MPRED_L1_REF00_POC 		DOS_REG_ADDR(HEVC_MPRED_L1_REF00_POC)
#define HEVC_MPRED_L1_REF01_POC 0x3231 	///../ucode/dos_register.h:3402
#define P_HEVC_MPRED_L1_REF01_POC 		DOS_REG_ADDR(HEVC_MPRED_L1_REF01_POC)
#define HEVC_MPRED_L1_REF02_POC 0x3232 	///../ucode/dos_register.h:3403
#define P_HEVC_MPRED_L1_REF02_POC 		DOS_REG_ADDR(HEVC_MPRED_L1_REF02_POC)
#define HEVC_MPRED_L1_REF03_POC 0x3233 	///../ucode/dos_register.h:3404
#define P_HEVC_MPRED_L1_REF03_POC 		DOS_REG_ADDR(HEVC_MPRED_L1_REF03_POC)
#define HEVC_MPRED_L1_REF04_POC 0x3234 	///../ucode/dos_register.h:3405
#define P_HEVC_MPRED_L1_REF04_POC 		DOS_REG_ADDR(HEVC_MPRED_L1_REF04_POC)
#define HEVC_MPRED_L1_REF05_POC 0x3235 	///../ucode/dos_register.h:3406
#define P_HEVC_MPRED_L1_REF05_POC 		DOS_REG_ADDR(HEVC_MPRED_L1_REF05_POC)
#define HEVC_MPRED_L1_REF06_POC 0x3236 	///../ucode/dos_register.h:3407
#define P_HEVC_MPRED_L1_REF06_POC 		DOS_REG_ADDR(HEVC_MPRED_L1_REF06_POC)
#define HEVC_MPRED_L1_REF07_POC 0x3237 	///../ucode/dos_register.h:3408
#define P_HEVC_MPRED_L1_REF07_POC 		DOS_REG_ADDR(HEVC_MPRED_L1_REF07_POC)
#define HEVC_MPRED_L1_REF08_POC 0x3238 	///../ucode/dos_register.h:3409
#define P_HEVC_MPRED_L1_REF08_POC 		DOS_REG_ADDR(HEVC_MPRED_L1_REF08_POC)
#define HEVC_MPRED_L1_REF09_POC 0x3239 	///../ucode/dos_register.h:3410
#define P_HEVC_MPRED_L1_REF09_POC 		DOS_REG_ADDR(HEVC_MPRED_L1_REF09_POC)
#define HEVC_MPRED_L1_REF10_POC 0x323a 	///../ucode/dos_register.h:3411
#define P_HEVC_MPRED_L1_REF10_POC 		DOS_REG_ADDR(HEVC_MPRED_L1_REF10_POC)
#define HEVC_MPRED_L1_REF11_POC 0x323b 	///../ucode/dos_register.h:3412
#define P_HEVC_MPRED_L1_REF11_POC 		DOS_REG_ADDR(HEVC_MPRED_L1_REF11_POC)
#define HEVC_MPRED_L1_REF12_POC 0x323c 	///../ucode/dos_register.h:3413
#define P_HEVC_MPRED_L1_REF12_POC 		DOS_REG_ADDR(HEVC_MPRED_L1_REF12_POC)
#define HEVC_MPRED_L1_REF13_POC 0x323d 	///../ucode/dos_register.h:3414
#define P_HEVC_MPRED_L1_REF13_POC 		DOS_REG_ADDR(HEVC_MPRED_L1_REF13_POC)
#define HEVC_MPRED_L1_REF14_POC 0x323e 	///../ucode/dos_register.h:3415
#define P_HEVC_MPRED_L1_REF14_POC 		DOS_REG_ADDR(HEVC_MPRED_L1_REF14_POC)
#define HEVC_MPRED_L1_REF15_POC 0x323f 	///../ucode/dos_register.h:3416
#define P_HEVC_MPRED_L1_REF15_POC 		DOS_REG_ADDR(HEVC_MPRED_L1_REF15_POC)
#define HEVC_MPRED_PIC_SIZE_EXT 0x3240 	///../ucode/dos_register.h:3417
#define P_HEVC_MPRED_PIC_SIZE_EXT 		DOS_REG_ADDR(HEVC_MPRED_PIC_SIZE_EXT)
#define HEVC_MPRED_DBG_MODE0 0x3241 	///../ucode/dos_register.h:3418
#define P_HEVC_MPRED_DBG_MODE0 		DOS_REG_ADDR(HEVC_MPRED_DBG_MODE0)
#define HEVC_MPRED_DBG_MODE1 0x3242 	///../ucode/dos_register.h:3419
#define P_HEVC_MPRED_DBG_MODE1 		DOS_REG_ADDR(HEVC_MPRED_DBG_MODE1)
#define HEVC_MPRED_DBG2_MODE 0x3243 	///../ucode/dos_register.h:3420
#define P_HEVC_MPRED_DBG2_MODE 		DOS_REG_ADDR(HEVC_MPRED_DBG2_MODE)
#define HEVC_MPRED_IMP_CMD0 0x3244 	///../ucode/dos_register.h:3421
#define P_HEVC_MPRED_IMP_CMD0 		DOS_REG_ADDR(HEVC_MPRED_IMP_CMD0)
#define HEVC_MPRED_IMP_CMD1 0x3245 	///../ucode/dos_register.h:3422
#define P_HEVC_MPRED_IMP_CMD1 		DOS_REG_ADDR(HEVC_MPRED_IMP_CMD1)
#define HEVC_MPRED_IMP_CMD2 0x3246 	///../ucode/dos_register.h:3423
#define P_HEVC_MPRED_IMP_CMD2 		DOS_REG_ADDR(HEVC_MPRED_IMP_CMD2)
#define HEVC_MPRED_IMP_CMD3 0x3247 	///../ucode/dos_register.h:3424
#define P_HEVC_MPRED_IMP_CMD3 		DOS_REG_ADDR(HEVC_MPRED_IMP_CMD3)
#define HEVC_MPRED_DBG2_DATA_0 0x3248 	///../ucode/dos_register.h:3425
#define P_HEVC_MPRED_DBG2_DATA_0 		DOS_REG_ADDR(HEVC_MPRED_DBG2_DATA_0)
#define HEVC_MPRED_DBG2_DATA_1 0x3249 	///../ucode/dos_register.h:3426
#define P_HEVC_MPRED_DBG2_DATA_1 		DOS_REG_ADDR(HEVC_MPRED_DBG2_DATA_1)
#define HEVC_MPRED_DBG2_DATA_2 0x324a 	///../ucode/dos_register.h:3427
#define P_HEVC_MPRED_DBG2_DATA_2 		DOS_REG_ADDR(HEVC_MPRED_DBG2_DATA_2)
#define HEVC_MPRED_DBG2_DATA_3 0x324b 	///../ucode/dos_register.h:3428
#define P_HEVC_MPRED_DBG2_DATA_3 		DOS_REG_ADDR(HEVC_MPRED_DBG2_DATA_3)
#define HEVC_MPRED_DBG_DATA_0 0x3250 	///../ucode/dos_register.h:3433
#define P_HEVC_MPRED_DBG_DATA_0 		DOS_REG_ADDR(HEVC_MPRED_DBG_DATA_0)
#define HEVC_MPRED_DBG_DATA_1 0x3251 	///../ucode/dos_register.h:3434
#define P_HEVC_MPRED_DBG_DATA_1 		DOS_REG_ADDR(HEVC_MPRED_DBG_DATA_1)
#define HEVC_MPRED_DBG_DATA_2 0x3252 	///../ucode/dos_register.h:3435
#define P_HEVC_MPRED_DBG_DATA_2 		DOS_REG_ADDR(HEVC_MPRED_DBG_DATA_2)
#define HEVC_MPRED_DBG_DATA_3 0x3253 	///../ucode/dos_register.h:3436
#define P_HEVC_MPRED_DBG_DATA_3 		DOS_REG_ADDR(HEVC_MPRED_DBG_DATA_3)
#define HEVC_MPRED_DBG_DATA_4 0x3254 	///../ucode/dos_register.h:3437
#define P_HEVC_MPRED_DBG_DATA_4 		DOS_REG_ADDR(HEVC_MPRED_DBG_DATA_4)
#define HEVC_MPRED_DBG_DATA_5 0x3255 	///../ucode/dos_register.h:3438
#define P_HEVC_MPRED_DBG_DATA_5 		DOS_REG_ADDR(HEVC_MPRED_DBG_DATA_5)
#define HEVC_MPRED_DBG_DATA_6 0x3256 	///../ucode/dos_register.h:3439
#define P_HEVC_MPRED_DBG_DATA_6 		DOS_REG_ADDR(HEVC_MPRED_DBG_DATA_6)
#define HEVC_MPRED_DBG_DATA_7 0x3257 	///../ucode/dos_register.h:3440
#define P_HEVC_MPRED_DBG_DATA_7 		DOS_REG_ADDR(HEVC_MPRED_DBG_DATA_7)
#define HEVC_MPRED_CUR_POC 0x3260 	///../ucode/dos_register.h:3449
#define P_HEVC_MPRED_CUR_POC 		DOS_REG_ADDR(HEVC_MPRED_CUR_POC)
#define HEVC_MPRED_COL_POC 0x3261 	///../ucode/dos_register.h:3450
#define P_HEVC_MPRED_COL_POC 		DOS_REG_ADDR(HEVC_MPRED_COL_POC)
#define HEVC_MPRED_MV_RD_END_ADDR 0x3262 	///../ucode/dos_register.h:3451
#define P_HEVC_MPRED_MV_RD_END_ADDR 		DOS_REG_ADDR(HEVC_MPRED_MV_RD_END_ADDR)
#define HEVCD_IPP_TOP_CNTL 0x3400 	///../ucode/dos_register.h:3467
#define P_HEVCD_IPP_TOP_CNTL 		DOS_REG_ADDR(HEVCD_IPP_TOP_CNTL)
#define HEVCD_IPP_TOP_STATUS 0x3401 	///../ucode/dos_register.h:3471
#define P_HEVCD_IPP_TOP_STATUS 		DOS_REG_ADDR(HEVCD_IPP_TOP_STATUS)
#define HEVCD_IPP_TOP_FRMCONFIG 0x3402 	///../ucode/dos_register.h:3476
#define P_HEVCD_IPP_TOP_FRMCONFIG 		DOS_REG_ADDR(HEVCD_IPP_TOP_FRMCONFIG)
#define HEVCD_IPP_TOP_TILECONFIG1 0x3403 	///../ucode/dos_register.h:3479
#define P_HEVCD_IPP_TOP_TILECONFIG1 		DOS_REG_ADDR(HEVCD_IPP_TOP_TILECONFIG1)
#define HEVCD_IPP_TOP_TILECONFIG2 0x3404 	///../ucode/dos_register.h:3482
#define P_HEVCD_IPP_TOP_TILECONFIG2 		DOS_REG_ADDR(HEVCD_IPP_TOP_TILECONFIG2)
#define HEVCD_IPP_TOP_TILECONFIG3 0x3405 	///../ucode/dos_register.h:3485
#define P_HEVCD_IPP_TOP_TILECONFIG3 		DOS_REG_ADDR(HEVCD_IPP_TOP_TILECONFIG3)
#define HEVCD_IPP_TOP_LCUCONFIG 0x3406 	///../ucode/dos_register.h:3488
#define P_HEVCD_IPP_TOP_LCUCONFIG 		DOS_REG_ADDR(HEVCD_IPP_TOP_LCUCONFIG)
#define HEVCD_IPP_TOP_FRMCTL 0x3407 	///../ucode/dos_register.h:3490
#define P_HEVCD_IPP_TOP_FRMCTL 		DOS_REG_ADDR(HEVCD_IPP_TOP_FRMCTL)
#define HEVCD_IPP_CONFIG 0x3408 	///../ucode/dos_register.h:3492
#define P_HEVCD_IPP_CONFIG 		DOS_REG_ADDR(HEVCD_IPP_CONFIG)
#define HEVCD_IPP_LINEBUFF_BASE 0x3409 	///../ucode/dos_register.h:3496
#define P_HEVCD_IPP_LINEBUFF_BASE 		DOS_REG_ADDR(HEVCD_IPP_LINEBUFF_BASE)
#define HEVCD_IPP_INTR_MASK 0x340a 	///../ucode/dos_register.h:3499
#define P_HEVCD_IPP_INTR_MASK 		DOS_REG_ADDR(HEVCD_IPP_INTR_MASK)
#define HEVCD_IPP_AXIIF_CONFIG 0x340b
#define P_HEVCD_IPP_AXIIF_CONFIG 		DOS_REG_ADDR(HEVCD_IPP_AXIIF_CONFIG)
#define HEVCD_IPP_SWMPREDIF_CONFIG 0x3410 	///../ucode/dos_register.h:3504
#define P_HEVCD_IPP_SWMPREDIF_CONFIG 		DOS_REG_ADDR(HEVCD_IPP_SWMPREDIF_CONFIG)
#define HEVCD_IPP_SWMPREDIF_STATUS 0x3411 	///../ucode/dos_register.h:3507
#define P_HEVCD_IPP_SWMPREDIF_STATUS 		DOS_REG_ADDR(HEVCD_IPP_SWMPREDIF_STATUS)
#define HEVCD_IPP_SWMPREDIF_CTBINFO 0x3412 	///../ucode/dos_register.h:3512
#define P_HEVCD_IPP_SWMPREDIF_CTBINFO 		DOS_REG_ADDR(HEVCD_IPP_SWMPREDIF_CTBINFO)
#define HEVCD_IPP_SWMPREDIF_PUINFO0 0x3413 	///../ucode/dos_register.h:3518
#define P_HEVCD_IPP_SWMPREDIF_PUINFO0 		DOS_REG_ADDR(HEVCD_IPP_SWMPREDIF_PUINFO0)
#define HEVCD_IPP_SWMPREDIF_PUINFO1 0x3414 	///../ucode/dos_register.h:3520
#define P_HEVCD_IPP_SWMPREDIF_PUINFO1 		DOS_REG_ADDR(HEVCD_IPP_SWMPREDIF_PUINFO1)
#define HEVCD_IPP_SWMPREDIF_PUINFO2 0x3415 	///../ucode/dos_register.h:3522
#define P_HEVCD_IPP_SWMPREDIF_PUINFO2 		DOS_REG_ADDR(HEVCD_IPP_SWMPREDIF_PUINFO2)
#define HEVCD_IPP_SWMPREDIF_PUINFO3 0x3416 	///../ucode/dos_register.h:3524
#define P_HEVCD_IPP_SWMPREDIF_PUINFO3 		DOS_REG_ADDR(HEVCD_IPP_SWMPREDIF_PUINFO3)
#define HEVCD_IPP_DYNCLKGATE_CONFIG 0x3420
#define P_HEVCD_IPP_DYNCLKGATE_CONFIG 		DOS_REG_ADDR(HEVCD_IPP_DYNCLKGATE_CONFIG)
#define HEVCD_IPP_DYNCLKGATE_STATUS 0x3421
#define P_HEVCD_IPP_DYNCLKGATE_STATUS 		DOS_REG_ADDR(HEVCD_IPP_DYNCLKGATE_CONFIG)
#define HEVCD_IPP_DBG_SEL 0x3430
#define P_HEVCD_IPP_DBG_SEL 		DOS_REG_ADDR(HEVCD_IPP_DBG_SEL)
#define HEVCD_IPP_DBG_DATA 0x3431
#define P_HEVCD_IPP_DBG_DATA 		DOS_REG_ADDR(HEVCD_IPP_DBG_DATA)
#define HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR 0x3460 	///../ucode/dos_register.h:3532
#define P_HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR 		DOS_REG_ADDR(HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR)
#define HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR 0x3461 	///../ucode/dos_register.h:3534
#define P_HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR 		DOS_REG_ADDR(HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR)
#define HEVCD_MPP_ANC2AXI_TBL_WDATA_ADDR 0x3462 	///../ucode/dos_register.h:3538
#define P_HEVCD_MPP_ANC2AXI_TBL_WDATA_ADDR 		DOS_REG_ADDR(HEVCD_MPP_ANC2AXI_TBL_WDATA_ADDR)
#define HEVCD_MPP_ANC2AXI_TBL_RDATA_ADDR 0x3463 	///../ucode/dos_register.h:3540
#define P_HEVCD_MPP_ANC2AXI_TBL_RDATA_ADDR 		DOS_REG_ADDR(HEVCD_MPP_ANC2AXI_TBL_RDATA_ADDR)
#define HEVCD_MPP_WEIGHTPRED_CNTL_ADDR 0x347b 	///../ucode/dos_register.h:3542
#define P_HEVCD_MPP_WEIGHTPRED_CNTL_ADDR 		DOS_REG_ADDR(HEVCD_MPP_WEIGHTPRED_CNTL_ADDR)
#define HEVCD_MPP_L0_WEIGHT_FLAG_ADDR 0x347c 	///../ucode/dos_register.h:3544
#define P_HEVCD_MPP_L0_WEIGHT_FLAG_ADDR 		DOS_REG_ADDR(HEVCD_MPP_L0_WEIGHT_FLAG_ADDR)
#define HEVCD_MPP_L1_WEIGHT_FLAG_ADDR 0x347d 	///../ucode/dos_register.h:3547
#define P_HEVCD_MPP_L1_WEIGHT_FLAG_ADDR 		DOS_REG_ADDR(HEVCD_MPP_L1_WEIGHT_FLAG_ADDR)
#define HEVCD_MPP_YLOG2WGHTDENOM_ADDR 0x347e 	///../ucode/dos_register.h:3550
#define P_HEVCD_MPP_YLOG2WGHTDENOM_ADDR 		DOS_REG_ADDR(HEVCD_MPP_YLOG2WGHTDENOM_ADDR)
#define HEVCD_MPP_DELTACLOG2WGHTDENOM_ADDR 0x347f 	///../ucode/dos_register.h:3552
#define P_HEVCD_MPP_DELTACLOG2WGHTDENOM_ADDR 		DOS_REG_ADDR(HEVCD_MPP_DELTACLOG2WGHTDENOM_ADDR)
#define HEVCD_MPP_WEIGHT_ADDR 0x3480 	///../ucode/dos_register.h:3554
#define P_HEVCD_MPP_WEIGHT_ADDR 		DOS_REG_ADDR(HEVCD_MPP_WEIGHT_ADDR)
#define HEVCD_MPP_WEIGHT_DATA 0x3481 	///../ucode/dos_register.h:3563
#define P_HEVCD_MPP_WEIGHT_DATA 		DOS_REG_ADDR(HEVCD_MPP_WEIGHT_DATA)
#define HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR 0x34c0 	///../ucode/dos_register.h:3578
#define P_HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR 		DOS_REG_ADDR(HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR)
#define HEVCD_MPP_ANC_CANVAS_DATA_ADDR 0x34c1 	///../ucode/dos_register.h:3580
#define P_HEVCD_MPP_ANC_CANVAS_DATA_ADDR 		DOS_REG_ADDR(HEVCD_MPP_ANC_CANVAS_DATA_ADDR)
#define HEVCD_MCRCC_CTL1 0x34f0 	///../ucode/dos_register.h:3594
#define P_HEVCD_MCRCC_CTL1 		DOS_REG_ADDR(HEVCD_MCRCC_CTL1)
#define HEVCD_MCRCC_CTL2 0x34f1 	///../ucode/dos_register.h:3600
#define P_HEVCD_MCRCC_CTL2 		DOS_REG_ADDR(HEVCD_MCRCC_CTL2)
#define HEVCD_MCRCC_CTL3 0x34f2 	///../ucode/dos_register.h:3606
#define P_HEVCD_MCRCC_CTL3 		DOS_REG_ADDR(HEVCD_MCRCC_CTL3)
#define HEVCD_MCRCC_PERFMON_CTL 0x34f3
#define P_HEVCD_MCRCC_PERFMON_CTL 		DOS_REG_ADDR(HEVCD_MCRCC_PERFMON_CTL)
#define HEVCD_MCRCC_PERFMON_DATA 0x34f3
#define P_HEVCD_MCRCC_PERFMON_DATA 		DOS_REG_ADDR(HEVCD_MCRCC_PERFMON_DATA)
#define HEVC_DBLK_CFG0 0x3500 	///../ucode/dos_register.h:3620
#define P_HEVC_DBLK_CFG0 		DOS_REG_ADDR(HEVC_DBLK_CFG0)
#define HEVC_DBLK_CFG1 0x3501 	///../ucode/dos_register.h:3622
#define P_HEVC_DBLK_CFG1 		DOS_REG_ADDR(HEVC_DBLK_CFG1)
#define HEVC_DBLK_CFG2 0x3502 	///../ucode/dos_register.h:3624
#define P_HEVC_DBLK_CFG2 		DOS_REG_ADDR(HEVC_DBLK_CFG2)
#define HEVC_DBLK_CFG3 0x3503 	///../ucode/dos_register.h:3626
#define P_HEVC_DBLK_CFG3 		DOS_REG_ADDR(HEVC_DBLK_CFG3)
#define HEVC_DBLK_CFG4 0x3504 	///../ucode/dos_register.h:3628
#define P_HEVC_DBLK_CFG4 		DOS_REG_ADDR(HEVC_DBLK_CFG4)
#define HEVC_DBLK_CFG5 0x3505 	///../ucode/dos_register.h:3630
#define P_HEVC_DBLK_CFG5 		DOS_REG_ADDR(HEVC_DBLK_CFG5)
#define HEVC_DBLK_CFG6 0x3506 	///../ucode/dos_register.h:3632
#define P_HEVC_DBLK_CFG6 		DOS_REG_ADDR(HEVC_DBLK_CFG6)
#define HEVC_DBLK_CFG7 0x3507 	///../ucode/dos_register.h:3634
#define P_HEVC_DBLK_CFG7 		DOS_REG_ADDR(HEVC_DBLK_CFG7)
#define HEVC_DBLK_CFG8 0x3508 	///../ucode/dos_register.h:3636
#define P_HEVC_DBLK_CFG8 		DOS_REG_ADDR(HEVC_DBLK_CFG8)
#define HEVC_DBLK_CFG9 0x3509 	///../ucode/dos_register.h:3638
#define P_HEVC_DBLK_CFG9 		DOS_REG_ADDR(HEVC_DBLK_CFG9)
#define HEVC_DBLK_CFGA 0x350a 	///../ucode/dos_register.h:3640
#define P_HEVC_DBLK_CFGA 		DOS_REG_ADDR(HEVC_DBLK_CFGA)
#define HEVC_DBLK_STS0 0x350b 	///../ucode/dos_register.h:3640
#define P_HEVC_DBLK_STS0 		DOS_REG_ADDR(HEVC_DBLK_STS0)
#define HEVC_DBLK_STS1 0x350c 	///../ucode/dos_register.h:3642
#define P_HEVC_DBLK_STS1 		DOS_REG_ADDR(HEVC_DBLK_STS1)
#define HEVC_SAO_VERSION 0x3600 	///../ucode/dos_register.h:3655
#define P_HEVC_SAO_VERSION 		DOS_REG_ADDR(HEVC_SAO_VERSION)
#define HEVC_SAO_CTRL0 0x3601 	///../ucode/dos_register.h:3657
#define P_HEVC_SAO_CTRL0 		DOS_REG_ADDR(HEVC_SAO_CTRL0)
#define HEVC_SAO_CTRL1 0x3602 	///../ucode/dos_register.h:3659
#define P_HEVC_SAO_CTRL1 		DOS_REG_ADDR(HEVC_SAO_CTRL1)
#define HEVC_SAO_INT_EN 0x3603 	///../ucode/dos_register.h:3660
#define P_HEVC_SAO_INT_EN 		DOS_REG_ADDR(HEVC_SAO_INT_EN)
#define HEVC_SAO_INT_STATUS 0x3604 	///../ucode/dos_register.h:3667
#define P_HEVC_SAO_INT_STATUS 		DOS_REG_ADDR(HEVC_SAO_INT_STATUS)
#define HEVC_SAO_PIC_SIZE 0x3605 	///../ucode/dos_register.h:3670
#define P_HEVC_SAO_PIC_SIZE 		DOS_REG_ADDR(HEVC_SAO_PIC_SIZE)
#define HEVC_SAO_PIC_SIZE_LCU 0x3606 	///../ucode/dos_register.h:3673
#define P_HEVC_SAO_PIC_SIZE_LCU 		DOS_REG_ADDR(HEVC_SAO_PIC_SIZE_LCU)
#define HEVC_SAO_TILE_START 0x3607 	///../ucode/dos_register.h:3676
#define P_HEVC_SAO_TILE_START 		DOS_REG_ADDR(HEVC_SAO_TILE_START)
#define HEVC_SAO_TILE_SIZE_LCU 0x3608 	///../ucode/dos_register.h:3679
#define P_HEVC_SAO_TILE_SIZE_LCU 		DOS_REG_ADDR(HEVC_SAO_TILE_SIZE_LCU)
#define HEVC_SAO_AXI_WCTRL 0x3609 	///../ucode/dos_register.h:3682
#define P_HEVC_SAO_AXI_WCTRL 		DOS_REG_ADDR(HEVC_SAO_AXI_WCTRL)
#define HEVC_SAO_AXI_RCTRL 0x360a 	///../ucode/dos_register.h:3683
#define P_HEVC_SAO_AXI_RCTRL 		DOS_REG_ADDR(HEVC_SAO_AXI_RCTRL)
#define HEVC_SAO_Y_START_ADDR 0x360b 	///../ucode/dos_register.h:3684
#define P_HEVC_SAO_Y_START_ADDR 		DOS_REG_ADDR(HEVC_SAO_Y_START_ADDR)
#define HEVC_SAO_Y_LENGTH 0x360c 	///../ucode/dos_register.h:3685
#define P_HEVC_SAO_Y_LENGTH 		DOS_REG_ADDR(HEVC_SAO_Y_LENGTH)
#define HEVC_SAO_C_START_ADDR 0x360d 	///../ucode/dos_register.h:3686
#define P_HEVC_SAO_C_START_ADDR 		DOS_REG_ADDR(HEVC_SAO_C_START_ADDR)
#define HEVC_SAO_C_LENGTH 0x360e 	///../ucode/dos_register.h:3687
#define P_HEVC_SAO_C_LENGTH 		DOS_REG_ADDR(HEVC_SAO_C_LENGTH)
#define HEVC_SAO_Y_WPTR 0x360f 	///../ucode/dos_register.h:3688
#define P_HEVC_SAO_Y_WPTR 		DOS_REG_ADDR(HEVC_SAO_Y_WPTR)
#define HEVC_SAO_C_WPTR 0x3610 	///../ucode/dos_register.h:3689
#define P_HEVC_SAO_C_WPTR 		DOS_REG_ADDR(HEVC_SAO_C_WPTR)
#define HEVC_SAO_ABV_START_ADDR 0x3611 	///../ucode/dos_register.h:3690
#define P_HEVC_SAO_ABV_START_ADDR 		DOS_REG_ADDR(HEVC_SAO_ABV_START_ADDR)
#define HEVC_SAO_VB_WR_START_ADDR 0x3612 	///../ucode/dos_register.h:3691
#define P_HEVC_SAO_VB_WR_START_ADDR 		DOS_REG_ADDR(HEVC_SAO_VB_WR_START_ADDR)
#define HEVC_SAO_VB_RD_START_ADDR 0x3613 	///../ucode/dos_register.h:3692
#define P_HEVC_SAO_VB_RD_START_ADDR 		DOS_REG_ADDR(HEVC_SAO_VB_RD_START_ADDR)
#define HEVC_SAO_ABV_WPTR 0x3614 	///../ucode/dos_register.h:3693
#define P_HEVC_SAO_ABV_WPTR 		DOS_REG_ADDR(HEVC_SAO_ABV_WPTR)
#define HEVC_SAO_ABV_RPTR 0x3615 	///../ucode/dos_register.h:3694
#define P_HEVC_SAO_ABV_RPTR 		DOS_REG_ADDR(HEVC_SAO_ABV_RPTR)
#define HEVC_SAO_VB_WPTR 0x3616 	///../ucode/dos_register.h:3695
#define P_HEVC_SAO_VB_WPTR 		DOS_REG_ADDR(HEVC_SAO_VB_WPTR)
#define HEVC_SAO_VB_RPTR 0x3617 	///../ucode/dos_register.h:3696
#define P_HEVC_SAO_VB_RPTR 		DOS_REG_ADDR(HEVC_SAO_VB_RPTR)
#define HEVC_SAO_DBG_MODE0 0x361e
#define P_HEVC_SAO_DBG_MODE0 		DOS_REG_ADDR(HEVC_SAO_DBG_MODE0)
#define HEVC_SAO_DBG_MODE1 0x361f
#define P_HEVC_SAO_DBG_MODE1 		DOS_REG_ADDR(HEVC_SAO_DBG_MODE1)
#define HEVC_SAO_CTRL2 0x3620 	///../ucode/dos_register.h:3697
#define P_HEVC_SAO_CTRL2 		DOS_REG_ADDR(HEVC_SAO_CTRL2)
#define HEVC_SAO_CTRL3 0x3621 	///../ucode/dos_register.h:3698
#define P_HEVC_SAO_CTRL3 		DOS_REG_ADDR(HEVC_SAO_CTRL3)
#define HEVC_SAO_CTRL4 0x3622 	///../ucode/dos_register.h:3699
#define P_HEVC_SAO_CTRL4 		DOS_REG_ADDR(HEVC_SAO_CTRL4)
#define HEVC_SAO_CTRL5 0x3623 	///../ucode/dos_register.h:3700
#define P_HEVC_SAO_CTRL5 		DOS_REG_ADDR(HEVC_SAO_CTRL5)
#define HEVC_SAO_CTRL6 0x3624 	///../ucode/dos_register.h:3701
#define P_HEVC_SAO_CTRL6 		DOS_REG_ADDR(HEVC_SAO_CTRL6)
#define HEVC_SAO_CTRL7 0x3625 	///../ucode/dos_register.h:3702
#define P_HEVC_SAO_CTRL7 		DOS_REG_ADDR(HEVC_SAO_CTRL7)
#define HEVC_SAO_DBG_DATA_0 0x3630
#define P_HEVC_SAO_DBG_DATA_0 		DOS_REG_ADDR(HEVC_SAO_DBG_DATA_0)
#define HEVC_SAO_DBG_DATA_1 0x3631
#define P_HEVC_SAO_DBG_DATA_1 		DOS_REG_ADDR(HEVC_SAO_DBG_DATA_1)
#define HEVC_SAO_DBG_DATA_2 0x3632
#define P_HEVC_SAO_DBG_DATA_2 		DOS_REG_ADDR(HEVC_SAO_DBG_DATA_2)
#define HEVC_SAO_DBG_DATA_3 0x3633
#define P_HEVC_SAO_DBG_DATA_3 		DOS_REG_ADDR(HEVC_SAO_DBG_DATA_3)
#define HEVC_SAO_DBG_DATA_4 0x3634
#define P_HEVC_SAO_DBG_DATA_4 		DOS_REG_ADDR(HEVC_SAO_DBG_DATA_4)
#define HEVC_SAO_DBG_DATA_5 0x3635
#define P_HEVC_SAO_DBG_DATA_5 		DOS_REG_ADDR(HEVC_SAO_DBG_DATA_5)
#define HEVC_SAO_DBG_DATA_6 0x3636
#define P_HEVC_SAO_DBG_DATA_6 		DOS_REG_ADDR(HEVC_SAO_DBG_DATA_6)
#define HEVC_SAO_DBG_DATA_7 0x3637
#define P_HEVC_SAO_DBG_DATA_7 		DOS_REG_ADDR(HEVC_SAO_DBG_DATA_7)
#define HEVC_IQIT_CLK_RST_CTRL 0x3700 	///../ucode/dos_register.h:3720
#define P_HEVC_IQIT_CLK_RST_CTRL 		DOS_REG_ADDR(HEVC_IQIT_CLK_RST_CTRL)
#define HEVC_IQIT_DEQUANT_CTRL 0x3701 	///../ucode/dos_register.h:3729
#define P_HEVC_IQIT_DEQUANT_CTRL 		DOS_REG_ADDR(HEVC_IQIT_DEQUANT_CTRL)
#define HEVC_IQIT_SCALELUT_WR_ADDR 0x3702 	///../ucode/dos_register.h:3732
#define P_HEVC_IQIT_SCALELUT_WR_ADDR 		DOS_REG_ADDR(HEVC_IQIT_SCALELUT_WR_ADDR)
#define HEVC_IQIT_SCALELUT_RD_ADDR 0x3703 	///../ucode/dos_register.h:3735
#define P_HEVC_IQIT_SCALELUT_RD_ADDR 		DOS_REG_ADDR(HEVC_IQIT_SCALELUT_RD_ADDR)
#define HEVC_IQIT_SCALELUT_DATA 0x3704 	///../ucode/dos_register.h:3737
#define P_HEVC_IQIT_SCALELUT_DATA 		DOS_REG_ADDR(HEVC_IQIT_SCALELUT_DATA)
#define HEVC_IQIT_SCALELUT_IDX_4 0x3705 	///../ucode/dos_register.h:3755
#define P_HEVC_IQIT_SCALELUT_IDX_4 		DOS_REG_ADDR(HEVC_IQIT_SCALELUT_IDX_4)
#define HEVC_IQIT_SCALELUT_IDX_8 0x3706 	///../ucode/dos_register.h:3767
#define P_HEVC_IQIT_SCALELUT_IDX_8 		DOS_REG_ADDR(HEVC_IQIT_SCALELUT_IDX_8)
#define HEVC_IQIT_SCALELUT_IDX_16_32 0x3707 	///../ucode/dos_register.h:3784
#define P_HEVC_IQIT_SCALELUT_IDX_16_32 		DOS_REG_ADDR(HEVC_IQIT_SCALELUT_IDX_16_32)
#define HEVC_IQIT_STAT_GEN0 0x3708 	///../ucode/dos_register.h:3787
#define P_HEVC_IQIT_STAT_GEN0 		DOS_REG_ADDR(HEVC_IQIT_STAT_GEN0)
#define HEVC_QP_WRITE 0x3709 	///../ucode/dos_register.h:3794
#define P_HEVC_QP_WRITE 		DOS_REG_ADDR(HEVC_QP_WRITE)
#define HEVC_IQIT_STAT_GEN1 0x370a 	///../ucode/dos_register.h:3807
#define P_HEVC_IQIT_STAT_GEN1 		DOS_REG_ADDR(HEVC_IQIT_STAT_GEN1)
#define DOS_SW_RESET0 0x3f00 	///../ucode/dos_register.h:3831
#define P_DOS_SW_RESET0 		DOS_REG_ADDR(DOS_SW_RESET0)
#define DOS_GCLK_EN0 0x3f01 	///../ucode/dos_register.h:3856
#define P_DOS_GCLK_EN0 		DOS_REG_ADDR(DOS_GCLK_EN0)
#define DOS_GEN_CTRL0 0x3f02 	///../ucode/dos_register.h:3857
#define P_DOS_GEN_CTRL0 		DOS_REG_ADDR(DOS_GEN_CTRL0)
#define DOS_APB_ERR_CTRL 0x3f03 	///../ucode/dos_register.h:3858
#define P_DOS_APB_ERR_CTRL 		DOS_REG_ADDR(DOS_APB_ERR_CTRL)
#define DOS_APB_ERR_STAT 0x3f04 	///../ucode/dos_register.h:3859
#define P_DOS_APB_ERR_STAT 		DOS_REG_ADDR(DOS_APB_ERR_STAT)
#define DOS_VDEC_INT_EN 0x3f05 	///../ucode/dos_register.h:3860
#define P_DOS_VDEC_INT_EN 		DOS_REG_ADDR(DOS_VDEC_INT_EN)
#define DOS_HCODEC_INT_EN 0x3f06 	///../ucode/dos_register.h:3861
#define P_DOS_HCODEC_INT_EN 		DOS_REG_ADDR(DOS_HCODEC_INT_EN)
#define DOS_SW_RESET1 0x3f07 	///../ucode/dos_register.h:3879
#define P_DOS_SW_RESET1 		DOS_REG_ADDR(DOS_SW_RESET1)
#define DOS_SW_RESET2 0x3f08 	///../ucode/dos_register.h:3894
#define P_DOS_SW_RESET2 		DOS_REG_ADDR(DOS_SW_RESET2)
#define DOS_GCLK_EN1 0x3f09 	///../ucode/dos_register.h:3906
#define P_DOS_GCLK_EN1 		DOS_REG_ADDR(DOS_GCLK_EN1)
#define DOS_VDEC2_INT_EN 0x3f0a 	///../ucode/dos_register.h:3907
#define P_DOS_VDEC2_INT_EN 		DOS_REG_ADDR(DOS_VDEC2_INT_EN)
#define DOS_VDIN_LCNT 0x3f0b 	///../ucode/dos_register.h:3908
#define P_DOS_VDIN_LCNT 		DOS_REG_ADDR(DOS_VDIN_LCNT)
#define DOS_VDIN_FCNT 0x3f0c 	///../ucode/dos_register.h:3909
#define P_DOS_VDIN_FCNT 		DOS_REG_ADDR(DOS_VDIN_FCNT)
#define DOS_VDIN_CCTL 0x3f0d 	///../ucode/dos_register.h:3910
#define P_DOS_VDIN_CCTL 		DOS_REG_ADDR(DOS_VDIN_CCTL)
#define DOS_SCRATCH0 0x3f10 	///../ucode/dos_register.h:3911
#define P_DOS_SCRATCH0 		DOS_REG_ADDR(DOS_SCRATCH0)
#define DOS_SCRATCH1 0x3f11 	///../ucode/dos_register.h:3912
#define P_DOS_SCRATCH1 		DOS_REG_ADDR(DOS_SCRATCH1)
#define DOS_SCRATCH2 0x3f12 	///../ucode/dos_register.h:3913
#define P_DOS_SCRATCH2 		DOS_REG_ADDR(DOS_SCRATCH2)
#define DOS_SCRATCH3 0x3f13 	///../ucode/dos_register.h:3914
#define P_DOS_SCRATCH3 		DOS_REG_ADDR(DOS_SCRATCH3)
#define DOS_SCRATCH4 0x3f14 	///../ucode/dos_register.h:3915
#define P_DOS_SCRATCH4 		DOS_REG_ADDR(DOS_SCRATCH4)
#define DOS_SCRATCH5 0x3f15 	///../ucode/dos_register.h:3916
#define P_DOS_SCRATCH5 		DOS_REG_ADDR(DOS_SCRATCH5)
#define DOS_SCRATCH6 0x3f16 	///../ucode/dos_register.h:3917
#define P_DOS_SCRATCH6 		DOS_REG_ADDR(DOS_SCRATCH6)
#define DOS_SCRATCH7 0x3f17 	///../ucode/dos_register.h:3918
#define P_DOS_SCRATCH7 		DOS_REG_ADDR(DOS_SCRATCH7)
#define DOS_SCRATCH8 0x3f18 	///../ucode/dos_register.h:3919
#define P_DOS_SCRATCH8 		DOS_REG_ADDR(DOS_SCRATCH8)
#define DOS_SCRATCH9 0x3f19 	///../ucode/dos_register.h:3920
#define P_DOS_SCRATCH9 		DOS_REG_ADDR(DOS_SCRATCH9)
#define DOS_SCRATCH10 0x3f1a 	///../ucode/dos_register.h:3921
#define P_DOS_SCRATCH10 		DOS_REG_ADDR(DOS_SCRATCH10)
#define DOS_SCRATCH11 0x3f1b 	///../ucode/dos_register.h:3922
#define P_DOS_SCRATCH11 		DOS_REG_ADDR(DOS_SCRATCH11)
#define DOS_SCRATCH12 0x3f1c 	///../ucode/dos_register.h:3923
#define P_DOS_SCRATCH12 		DOS_REG_ADDR(DOS_SCRATCH12)
#define DOS_SCRATCH13 0x3f1d 	///../ucode/dos_register.h:3924
#define P_DOS_SCRATCH13 		DOS_REG_ADDR(DOS_SCRATCH13)
#define DOS_SCRATCH14 0x3f1e 	///../ucode/dos_register.h:3925
#define P_DOS_SCRATCH14 		DOS_REG_ADDR(DOS_SCRATCH14)
#define DOS_SCRATCH15 0x3f1f 	///../ucode/dos_register.h:3926
#define P_DOS_SCRATCH15 		DOS_REG_ADDR(DOS_SCRATCH15)
#define DOS_SCRATCH16 0x3f20 	///../ucode/dos_register.h:3927
#define P_DOS_SCRATCH16 		DOS_REG_ADDR(DOS_SCRATCH16)
#define DOS_SCRATCH17 0x3f21 	///../ucode/dos_register.h:3928
#define P_DOS_SCRATCH17 		DOS_REG_ADDR(DOS_SCRATCH17)
#define DOS_SCRATCH18 0x3f22 	///../ucode/dos_register.h:3929
#define P_DOS_SCRATCH18 		DOS_REG_ADDR(DOS_SCRATCH18)
#define DOS_SCRATCH19 0x3f23 	///../ucode/dos_register.h:3930
#define P_DOS_SCRATCH19 		DOS_REG_ADDR(DOS_SCRATCH19)
#define DOS_SCRATCH20 0x3f24 	///../ucode/dos_register.h:3931
#define P_DOS_SCRATCH20 		DOS_REG_ADDR(DOS_SCRATCH20)
#define DOS_SCRATCH21 0x3f25 	///../ucode/dos_register.h:3932
#define P_DOS_SCRATCH21 		DOS_REG_ADDR(DOS_SCRATCH21)
#define DOS_SCRATCH22 0x3f26 	///../ucode/dos_register.h:3933
#define P_DOS_SCRATCH22 		DOS_REG_ADDR(DOS_SCRATCH22)
#define DOS_SCRATCH23 0x3f27 	///../ucode/dos_register.h:3934
#define P_DOS_SCRATCH23 		DOS_REG_ADDR(DOS_SCRATCH23)
#define DOS_SCRATCH24 0x3f28 	///../ucode/dos_register.h:3935
#define P_DOS_SCRATCH24 		DOS_REG_ADDR(DOS_SCRATCH24)
#define DOS_SCRATCH25 0x3f29 	///../ucode/dos_register.h:3936
#define P_DOS_SCRATCH25 		DOS_REG_ADDR(DOS_SCRATCH25)
#define DOS_SCRATCH26 0x3f2a 	///../ucode/dos_register.h:3937
#define P_DOS_SCRATCH26 		DOS_REG_ADDR(DOS_SCRATCH26)
#define DOS_SCRATCH27 0x3f2b 	///../ucode/dos_register.h:3938
#define P_DOS_SCRATCH27 		DOS_REG_ADDR(DOS_SCRATCH27)
#define DOS_SCRATCH28 0x3f2c 	///../ucode/dos_register.h:3939
#define P_DOS_SCRATCH28 		DOS_REG_ADDR(DOS_SCRATCH28)
#define DOS_SCRATCH29 0x3f2d 	///../ucode/dos_register.h:3940
#define P_DOS_SCRATCH29 		DOS_REG_ADDR(DOS_SCRATCH29)
#define DOS_SCRATCH30 0x3f2e 	///../ucode/dos_register.h:3941
#define P_DOS_SCRATCH30 		DOS_REG_ADDR(DOS_SCRATCH30)
#define DOS_SCRATCH31 0x3f2f 	///../ucode/dos_register.h:3942
#define P_DOS_SCRATCH31 		DOS_REG_ADDR(DOS_SCRATCH31)
#define DOS_MEM_PD_VDEC 0x3f30 	///../ucode/dos_register.h:3943
#define P_DOS_MEM_PD_VDEC 		DOS_REG_ADDR(DOS_MEM_PD_VDEC)
#define DOS_MEM_PD_VDEC2 0x3f31 	///../ucode/dos_register.h:3944
#define P_DOS_MEM_PD_VDEC2 		DOS_REG_ADDR(DOS_MEM_PD_VDEC2)
#define DOS_MEM_PD_HCODEC 0x3f32 	///../ucode/dos_register.h:3945
#define P_DOS_MEM_PD_HCODEC 		DOS_REG_ADDR(DOS_MEM_PD_HCODEC)
#define DOS_MEM_PD_HEVC 0x3f33 	///../ucode/dos_register.h:3946
#define P_DOS_MEM_PD_HEVC 		DOS_REG_ADDR(DOS_MEM_PD_HEVC)
#define DOS_SW_RESET3 0x3f34 	///../ucode/dos_register.h:3947
#define P_DOS_SW_RESET3 		DOS_REG_ADDR(DOS_SW_RESET3)
#define DOS_GCLK_EN3 0x3f35 	///../ucode/dos_register.h:3948
#define P_DOS_GCLK_EN3 		DOS_REG_ADDR(DOS_GCLK_EN3)
#define DOS_HEVC_INT_EN 0x3f36 	///../ucode/dos_register.h:3949
#define P_DOS_HEVC_INT_EN 		DOS_REG_ADDR(DOS_HEVC_INT_EN)
#define DOS_VDEC_MCRCC_STALL_CTRL 0x3f40 	///../ucode/dos_register.h:3955
#define P_DOS_VDEC_MCRCC_STALL_CTRL 		DOS_REG_ADDR(DOS_VDEC_MCRCC_STALL_CTRL)
#define DOS_VDEC_MCRCC_STALL2_CTRL 0x3f42 	///../ucode/dos_register.h:3956
#define P_DOS_VDEC_MCRCC_STALL2_CTRL 		DOS_REG_ADDR(DOS_VDEC_MCRCC_STALL2_CTRL)
#define DOS_VDEC2_MCRCC_STALL_CTRL 0x3f41 	///../ucode/dos_register.h:3957
#define P_DOS_VDEC2_MCRCC_STALL_CTRL 		DOS_REG_ADDR(DOS_VDEC2_MCRCC_STALL_CTRL)
#define DOS_VDEC2_MCRCC_STALL2_CTRL 0x3f43 	///../ucode/dos_register.h:3958
#define P_DOS_VDEC2_MCRCC_STALL2_CTRL 		DOS_REG_ADDR(DOS_VDEC2_MCRCC_STALL2_CTRL)
#define HCODEC_MC_CTRL_REG 0x1900 	///../ucode/dos_register.h:3971
#define P_HCODEC_MC_CTRL_REG 		DOS_REG_ADDR(HCODEC_MC_CTRL_REG)
#define HCODEC_MC_MB_INFO 0x1901 	///../ucode/dos_register.h:3972
#define P_HCODEC_MC_MB_INFO 		DOS_REG_ADDR(HCODEC_MC_MB_INFO)
#define HCODEC_MC_PIC_INFO 0x1902 	///../ucode/dos_register.h:3973
#define P_HCODEC_MC_PIC_INFO 		DOS_REG_ADDR(HCODEC_MC_PIC_INFO)
#define HCODEC_MC_HALF_PEL_ONE 0x1903 	///../ucode/dos_register.h:3974
#define P_HCODEC_MC_HALF_PEL_ONE 		DOS_REG_ADDR(HCODEC_MC_HALF_PEL_ONE)
#define HCODEC_MC_HALF_PEL_TWO 0x1904 	///../ucode/dos_register.h:3975
#define P_HCODEC_MC_HALF_PEL_TWO 		DOS_REG_ADDR(HCODEC_MC_HALF_PEL_TWO)
#define HCODEC_POWER_CTL_MC 0x1905 	///../ucode/dos_register.h:3976
#define P_HCODEC_POWER_CTL_MC 		DOS_REG_ADDR(HCODEC_POWER_CTL_MC)
#define HCODEC_MC_CMD 0x1906 	///../ucode/dos_register.h:3977
#define P_HCODEC_MC_CMD 		DOS_REG_ADDR(HCODEC_MC_CMD)
#define HCODEC_MC_CTRL0 0x1907 	///../ucode/dos_register.h:3978
#define P_HCODEC_MC_CTRL0 		DOS_REG_ADDR(HCODEC_MC_CTRL0)
#define HCODEC_MC_PIC_W_H 0x1908 	///../ucode/dos_register.h:3979
#define P_HCODEC_MC_PIC_W_H 		DOS_REG_ADDR(HCODEC_MC_PIC_W_H)
#define HCODEC_MC_STATUS0 0x1909 	///../ucode/dos_register.h:3980
#define P_HCODEC_MC_STATUS0 		DOS_REG_ADDR(HCODEC_MC_STATUS0)
#define HCODEC_MC_STATUS1 0x190a 	///../ucode/dos_register.h:3981
#define P_HCODEC_MC_STATUS1 		DOS_REG_ADDR(HCODEC_MC_STATUS1)
#define HCODEC_MC_CTRL1 0x190b 	///../ucode/dos_register.h:3982
#define P_HCODEC_MC_CTRL1 		DOS_REG_ADDR(HCODEC_MC_CTRL1)
#define HCODEC_MC_MIX_RATIO0 0x190c 	///../ucode/dos_register.h:3983
#define P_HCODEC_MC_MIX_RATIO0 		DOS_REG_ADDR(HCODEC_MC_MIX_RATIO0)
#define HCODEC_MC_MIX_RATIO1 0x190d 	///../ucode/dos_register.h:3984
#define P_HCODEC_MC_MIX_RATIO1 		DOS_REG_ADDR(HCODEC_MC_MIX_RATIO1)
#define HCODEC_MC_DP_MB_XY 0x190e 	///../ucode/dos_register.h:3985
#define P_HCODEC_MC_DP_MB_XY 		DOS_REG_ADDR(HCODEC_MC_DP_MB_XY)
#define HCODEC_MC_OM_MB_XY 0x190f 	///../ucode/dos_register.h:3986
#define P_HCODEC_MC_OM_MB_XY 		DOS_REG_ADDR(HCODEC_MC_OM_MB_XY)
#define HCODEC_PSCALE_RST 0x1910 	///../ucode/dos_register.h:3987
#define P_HCODEC_PSCALE_RST 		DOS_REG_ADDR(HCODEC_PSCALE_RST)
#define HCODEC_PSCALE_CTRL 0x1911 	///../ucode/dos_register.h:3988
#define P_HCODEC_PSCALE_CTRL 		DOS_REG_ADDR(HCODEC_PSCALE_CTRL)
#define HCODEC_PSCALE_PICI_W 0x1912 	///../ucode/dos_register.h:3989
#define P_HCODEC_PSCALE_PICI_W 		DOS_REG_ADDR(HCODEC_PSCALE_PICI_W)
#define HCODEC_PSCALE_PICI_H 0x1913 	///../ucode/dos_register.h:3990
#define P_HCODEC_PSCALE_PICI_H 		DOS_REG_ADDR(HCODEC_PSCALE_PICI_H)
#define HCODEC_PSCALE_PICO_W 0x1914 	///../ucode/dos_register.h:3991
#define P_HCODEC_PSCALE_PICO_W 		DOS_REG_ADDR(HCODEC_PSCALE_PICO_W)
#define HCODEC_PSCALE_PICO_H 0x1915 	///../ucode/dos_register.h:3992
#define P_HCODEC_PSCALE_PICO_H 		DOS_REG_ADDR(HCODEC_PSCALE_PICO_H)
#define HCODEC_PSCALE_PICO_START_X 0x1916 	///../ucode/dos_register.h:3993
#define P_HCODEC_PSCALE_PICO_START_X 		DOS_REG_ADDR(HCODEC_PSCALE_PICO_START_X)
#define HCODEC_PSCALE_PICO_START_Y 0x1917 	///../ucode/dos_register.h:3994
#define P_HCODEC_PSCALE_PICO_START_Y 		DOS_REG_ADDR(HCODEC_PSCALE_PICO_START_Y)
#define HCODEC_PSCALE_DUMMY 0x1918 	///../ucode/dos_register.h:3995
#define P_HCODEC_PSCALE_DUMMY 		DOS_REG_ADDR(HCODEC_PSCALE_DUMMY)
#define HCODEC_PSCALE_FILT0_COEF0 0x1919 	///../ucode/dos_register.h:3996
#define P_HCODEC_PSCALE_FILT0_COEF0 		DOS_REG_ADDR(HCODEC_PSCALE_FILT0_COEF0)
#define HCODEC_PSCALE_FILT0_COEF1 0x191a 	///../ucode/dos_register.h:3997
#define P_HCODEC_PSCALE_FILT0_COEF1 		DOS_REG_ADDR(HCODEC_PSCALE_FILT0_COEF1)
#define HCODEC_PSCALE_CMD_CTRL 0x191b 	///../ucode/dos_register.h:3998
#define P_HCODEC_PSCALE_CMD_CTRL 		DOS_REG_ADDR(HCODEC_PSCALE_CMD_CTRL)
#define HCODEC_PSCALE_CMD_BLK_X 0x191c 	///../ucode/dos_register.h:3999
#define P_HCODEC_PSCALE_CMD_BLK_X 		DOS_REG_ADDR(HCODEC_PSCALE_CMD_BLK_X)
#define HCODEC_PSCALE_CMD_BLK_Y 0x191d 	///../ucode/dos_register.h:4000
#define P_HCODEC_PSCALE_CMD_BLK_Y 		DOS_REG_ADDR(HCODEC_PSCALE_CMD_BLK_Y)
#define HCODEC_PSCALE_STATUS 0x191e 	///../ucode/dos_register.h:4001
#define P_HCODEC_PSCALE_STATUS 		DOS_REG_ADDR(HCODEC_PSCALE_STATUS)
#define HCODEC_PSCALE_BMEM_ADDR 0x191f 	///../ucode/dos_register.h:4002
#define P_HCODEC_PSCALE_BMEM_ADDR 		DOS_REG_ADDR(HCODEC_PSCALE_BMEM_ADDR)
#define HCODEC_PSCALE_BMEM_DAT 0x1920 	///../ucode/dos_register.h:4003
#define P_HCODEC_PSCALE_BMEM_DAT 		DOS_REG_ADDR(HCODEC_PSCALE_BMEM_DAT)
#define HCODEC_PSCALE_DRAM_BUF_CTRL 0x1921 	///../ucode/dos_register.h:4004
#define P_HCODEC_PSCALE_DRAM_BUF_CTRL 		DOS_REG_ADDR(HCODEC_PSCALE_DRAM_BUF_CTRL)
#define HCODEC_PSCALE_MCMD_CTRL 0x1922 	///../ucode/dos_register.h:4005
#define P_HCODEC_PSCALE_MCMD_CTRL 		DOS_REG_ADDR(HCODEC_PSCALE_MCMD_CTRL)
#define HCODEC_PSCALE_MCMD_XSIZE 0x1923 	///../ucode/dos_register.h:4006
#define P_HCODEC_PSCALE_MCMD_XSIZE 		DOS_REG_ADDR(HCODEC_PSCALE_MCMD_XSIZE)
#define HCODEC_PSCALE_MCMD_YSIZE 0x1924 	///../ucode/dos_register.h:4007
#define P_HCODEC_PSCALE_MCMD_YSIZE 		DOS_REG_ADDR(HCODEC_PSCALE_MCMD_YSIZE)
#define HCODEC_PSCALE_RBUF_START_BLKX 0x1925 	///../ucode/dos_register.h:4008
#define P_HCODEC_PSCALE_RBUF_START_BLKX 		DOS_REG_ADDR(HCODEC_PSCALE_RBUF_START_BLKX)
#define HCODEC_PSCALE_RBUF_START_BLKY 0x1926 	///../ucode/dos_register.h:4009
#define P_HCODEC_PSCALE_RBUF_START_BLKY 		DOS_REG_ADDR(HCODEC_PSCALE_RBUF_START_BLKY)
#define HCODEC_PSCALE_PICO_SHIFT_XY 0x1928 	///../ucode/dos_register.h:4011
#define P_HCODEC_PSCALE_PICO_SHIFT_XY 		DOS_REG_ADDR(HCODEC_PSCALE_PICO_SHIFT_XY)
#define HCODEC_PSCALE_CTRL1 0x1929 	///../ucode/dos_register.h:4012
#define P_HCODEC_PSCALE_CTRL1 		DOS_REG_ADDR(HCODEC_PSCALE_CTRL1)
#define HCODEC_PSCALE_SRCKEY_CTRL0 0x192a 	///../ucode/dos_register.h:4020
#define P_HCODEC_PSCALE_SRCKEY_CTRL0 		DOS_REG_ADDR(HCODEC_PSCALE_SRCKEY_CTRL0)
#define HCODEC_PSCALE_SRCKEY_CTRL1 0x192b 	///../ucode/dos_register.h:4023
#define P_HCODEC_PSCALE_SRCKEY_CTRL1 		DOS_REG_ADDR(HCODEC_PSCALE_SRCKEY_CTRL1)
#define HCODEC_PSCALE_CANVAS_RD_ADDR 0x192c 	///../ucode/dos_register.h:4027
#define P_HCODEC_PSCALE_CANVAS_RD_ADDR 		DOS_REG_ADDR(HCODEC_PSCALE_CANVAS_RD_ADDR)
#define HCODEC_PSCALE_CANVAS_WR_ADDR 0x192d 	///../ucode/dos_register.h:4031
#define P_HCODEC_PSCALE_CANVAS_WR_ADDR 		DOS_REG_ADDR(HCODEC_PSCALE_CANVAS_WR_ADDR)
#define HCODEC_PSCALE_CTRL2 0x192e 	///../ucode/dos_register.h:4035
#define P_HCODEC_PSCALE_CTRL2 		DOS_REG_ADDR(HCODEC_PSCALE_CTRL2)
#define HCODEC_MC_MPORT_CTRL 0x1940 	///../ucode/dos_register.h:4036
#define P_HCODEC_MC_MPORT_CTRL 		DOS_REG_ADDR(HCODEC_MC_MPORT_CTRL)
#define HCODEC_MC_MPORT_DAT 0x1941 	///../ucode/dos_register.h:4037
#define P_HCODEC_MC_MPORT_DAT 		DOS_REG_ADDR(HCODEC_MC_MPORT_DAT)
#define HCODEC_MC_WT_PRED_CTRL 0x1942 	///../ucode/dos_register.h:4038
#define P_HCODEC_MC_WT_PRED_CTRL 		DOS_REG_ADDR(HCODEC_MC_WT_PRED_CTRL)
#define HCODEC_MC_MBBOT_ST_EVEN_ADDR 0x1944 	///../ucode/dos_register.h:4039
#define P_HCODEC_MC_MBBOT_ST_EVEN_ADDR 		DOS_REG_ADDR(HCODEC_MC_MBBOT_ST_EVEN_ADDR)
#define HCODEC_MC_MBBOT_ST_ODD_ADDR 0x1945 	///../ucode/dos_register.h:4040
#define P_HCODEC_MC_MBBOT_ST_ODD_ADDR 		DOS_REG_ADDR(HCODEC_MC_MBBOT_ST_ODD_ADDR)
#define HCODEC_MC_DPDN_MB_XY 0x1946 	///../ucode/dos_register.h:4041
#define P_HCODEC_MC_DPDN_MB_XY 		DOS_REG_ADDR(HCODEC_MC_DPDN_MB_XY)
#define HCODEC_MC_OMDN_MB_XY 0x1947 	///../ucode/dos_register.h:4042
#define P_HCODEC_MC_OMDN_MB_XY 		DOS_REG_ADDR(HCODEC_MC_OMDN_MB_XY)
#define HCODEC_MC_HCMDBUF_H 0x1948 	///../ucode/dos_register.h:4043
#define P_HCODEC_MC_HCMDBUF_H 		DOS_REG_ADDR(HCODEC_MC_HCMDBUF_H)
#define HCODEC_MC_HCMDBUF_L 0x1949 	///../ucode/dos_register.h:4044
#define P_HCODEC_MC_HCMDBUF_L 		DOS_REG_ADDR(HCODEC_MC_HCMDBUF_L)
#define HCODEC_MC_HCMD_H 0x194a 	///../ucode/dos_register.h:4045
#define P_HCODEC_MC_HCMD_H 		DOS_REG_ADDR(HCODEC_MC_HCMD_H)
#define HCODEC_MC_HCMD_L 0x194b 	///../ucode/dos_register.h:4046
#define P_HCODEC_MC_HCMD_L 		DOS_REG_ADDR(HCODEC_MC_HCMD_L)
#define HCODEC_MC_IDCT_DAT 0x194c 	///../ucode/dos_register.h:4047
#define P_HCODEC_MC_IDCT_DAT 		DOS_REG_ADDR(HCODEC_MC_IDCT_DAT)
#define HCODEC_MC_CTRL_GCLK_CTRL 0x194d 	///../ucode/dos_register.h:4048
#define P_HCODEC_MC_CTRL_GCLK_CTRL 		DOS_REG_ADDR(HCODEC_MC_CTRL_GCLK_CTRL)
#define HCODEC_MC_OTHER_GCLK_CTRL 0x194e 	///../ucode/dos_register.h:4049
#define P_HCODEC_MC_OTHER_GCLK_CTRL 		DOS_REG_ADDR(HCODEC_MC_OTHER_GCLK_CTRL)
#define HCODEC_MC_CTRL2 0x194f 	///../ucode/dos_register.h:4054
#define P_HCODEC_MC_CTRL2 		DOS_REG_ADDR(HCODEC_MC_CTRL2)
#define HCODEC_MDEC_PIC_DC_CTRL 0x198e 	///../ucode/dos_register.h:4061
#define P_HCODEC_MDEC_PIC_DC_CTRL 		DOS_REG_ADDR(HCODEC_MDEC_PIC_DC_CTRL)
#define HCODEC_MDEC_PIC_DC_STATUS 0x198f 	///../ucode/dos_register.h:4062
#define P_HCODEC_MDEC_PIC_DC_STATUS 		DOS_REG_ADDR(HCODEC_MDEC_PIC_DC_STATUS)
#define HCODEC_ANC0_CANVAS_ADDR 0x1990 	///../ucode/dos_register.h:4063
#define P_HCODEC_ANC0_CANVAS_ADDR 		DOS_REG_ADDR(HCODEC_ANC0_CANVAS_ADDR)
#define HCODEC_ANC1_CANVAS_ADDR 0x1991 	///../ucode/dos_register.h:4064
#define P_HCODEC_ANC1_CANVAS_ADDR 		DOS_REG_ADDR(HCODEC_ANC1_CANVAS_ADDR)
#define HCODEC_ANC2_CANVAS_ADDR 0x1992 	///../ucode/dos_register.h:4065
#define P_HCODEC_ANC2_CANVAS_ADDR 		DOS_REG_ADDR(HCODEC_ANC2_CANVAS_ADDR)
#define HCODEC_ANC3_CANVAS_ADDR 0x1993 	///../ucode/dos_register.h:4066
#define P_HCODEC_ANC3_CANVAS_ADDR 		DOS_REG_ADDR(HCODEC_ANC3_CANVAS_ADDR)
#define HCODEC_ANC4_CANVAS_ADDR 0x1994 	///../ucode/dos_register.h:4067
#define P_HCODEC_ANC4_CANVAS_ADDR 		DOS_REG_ADDR(HCODEC_ANC4_CANVAS_ADDR)
#define HCODEC_ANC5_CANVAS_ADDR 0x1995 	///../ucode/dos_register.h:4068
#define P_HCODEC_ANC5_CANVAS_ADDR 		DOS_REG_ADDR(HCODEC_ANC5_CANVAS_ADDR)
#define HCODEC_ANC6_CANVAS_ADDR 0x1996 	///../ucode/dos_register.h:4069
#define P_HCODEC_ANC6_CANVAS_ADDR 		DOS_REG_ADDR(HCODEC_ANC6_CANVAS_ADDR)
#define HCODEC_ANC7_CANVAS_ADDR 0x1997 	///../ucode/dos_register.h:4070
#define P_HCODEC_ANC7_CANVAS_ADDR 		DOS_REG_ADDR(HCODEC_ANC7_CANVAS_ADDR)
#define HCODEC_ANC8_CANVAS_ADDR 0x1998 	///../ucode/dos_register.h:4071
#define P_HCODEC_ANC8_CANVAS_ADDR 		DOS_REG_ADDR(HCODEC_ANC8_CANVAS_ADDR)
#define HCODEC_ANC9_CANVAS_ADDR 0x1999 	///../ucode/dos_register.h:4072
#define P_HCODEC_ANC9_CANVAS_ADDR 		DOS_REG_ADDR(HCODEC_ANC9_CANVAS_ADDR)
#define HCODEC_ANC10_CANVAS_ADDR 0x199a 	///../ucode/dos_register.h:4073
#define P_HCODEC_ANC10_CANVAS_ADDR 		DOS_REG_ADDR(HCODEC_ANC10_CANVAS_ADDR)
#define HCODEC_ANC11_CANVAS_ADDR 0x199b 	///../ucode/dos_register.h:4074
#define P_HCODEC_ANC11_CANVAS_ADDR 		DOS_REG_ADDR(HCODEC_ANC11_CANVAS_ADDR)
#define HCODEC_ANC12_CANVAS_ADDR 0x199c 	///../ucode/dos_register.h:4075
#define P_HCODEC_ANC12_CANVAS_ADDR 		DOS_REG_ADDR(HCODEC_ANC12_CANVAS_ADDR)
#define HCODEC_ANC13_CANVAS_ADDR 0x199d 	///../ucode/dos_register.h:4076
#define P_HCODEC_ANC13_CANVAS_ADDR 		DOS_REG_ADDR(HCODEC_ANC13_CANVAS_ADDR)
#define HCODEC_ANC14_CANVAS_ADDR 0x199e 	///../ucode/dos_register.h:4077
#define P_HCODEC_ANC14_CANVAS_ADDR 		DOS_REG_ADDR(HCODEC_ANC14_CANVAS_ADDR)
#define HCODEC_ANC15_CANVAS_ADDR 0x199f 	///../ucode/dos_register.h:4078
#define P_HCODEC_ANC15_CANVAS_ADDR 		DOS_REG_ADDR(HCODEC_ANC15_CANVAS_ADDR)
#define HCODEC_ANC16_CANVAS_ADDR 0x19a0 	///../ucode/dos_register.h:4079
#define P_HCODEC_ANC16_CANVAS_ADDR 		DOS_REG_ADDR(HCODEC_ANC16_CANVAS_ADDR)
#define HCODEC_ANC17_CANVAS_ADDR 0x19a1 	///../ucode/dos_register.h:4080
#define P_HCODEC_ANC17_CANVAS_ADDR 		DOS_REG_ADDR(HCODEC_ANC17_CANVAS_ADDR)
#define HCODEC_ANC18_CANVAS_ADDR 0x19a2 	///../ucode/dos_register.h:4081
#define P_HCODEC_ANC18_CANVAS_ADDR 		DOS_REG_ADDR(HCODEC_ANC18_CANVAS_ADDR)
#define HCODEC_ANC19_CANVAS_ADDR 0x19a3 	///../ucode/dos_register.h:4082
#define P_HCODEC_ANC19_CANVAS_ADDR 		DOS_REG_ADDR(HCODEC_ANC19_CANVAS_ADDR)
#define HCODEC_ANC20_CANVAS_ADDR 0x19a4 	///../ucode/dos_register.h:4083
#define P_HCODEC_ANC20_CANVAS_ADDR 		DOS_REG_ADDR(HCODEC_ANC20_CANVAS_ADDR)
#define HCODEC_ANC21_CANVAS_ADDR 0x19a5 	///../ucode/dos_register.h:4084
#define P_HCODEC_ANC21_CANVAS_ADDR 		DOS_REG_ADDR(HCODEC_ANC21_CANVAS_ADDR)
#define HCODEC_ANC22_CANVAS_ADDR 0x19a6 	///../ucode/dos_register.h:4085
#define P_HCODEC_ANC22_CANVAS_ADDR 		DOS_REG_ADDR(HCODEC_ANC22_CANVAS_ADDR)
#define HCODEC_ANC23_CANVAS_ADDR 0x19a7 	///../ucode/dos_register.h:4086
#define P_HCODEC_ANC23_CANVAS_ADDR 		DOS_REG_ADDR(HCODEC_ANC23_CANVAS_ADDR)
#define HCODEC_ANC24_CANVAS_ADDR 0x19a8 	///../ucode/dos_register.h:4087
#define P_HCODEC_ANC24_CANVAS_ADDR 		DOS_REG_ADDR(HCODEC_ANC24_CANVAS_ADDR)
#define HCODEC_ANC25_CANVAS_ADDR 0x19a9 	///../ucode/dos_register.h:4088
#define P_HCODEC_ANC25_CANVAS_ADDR 		DOS_REG_ADDR(HCODEC_ANC25_CANVAS_ADDR)
#define HCODEC_ANC26_CANVAS_ADDR 0x19aa 	///../ucode/dos_register.h:4089
#define P_HCODEC_ANC26_CANVAS_ADDR 		DOS_REG_ADDR(HCODEC_ANC26_CANVAS_ADDR)
#define HCODEC_ANC27_CANVAS_ADDR 0x19ab 	///../ucode/dos_register.h:4090
#define P_HCODEC_ANC27_CANVAS_ADDR 		DOS_REG_ADDR(HCODEC_ANC27_CANVAS_ADDR)
#define HCODEC_ANC28_CANVAS_ADDR 0x19ac 	///../ucode/dos_register.h:4091
#define P_HCODEC_ANC28_CANVAS_ADDR 		DOS_REG_ADDR(HCODEC_ANC28_CANVAS_ADDR)
#define HCODEC_ANC29_CANVAS_ADDR 0x19ad 	///../ucode/dos_register.h:4092
#define P_HCODEC_ANC29_CANVAS_ADDR 		DOS_REG_ADDR(HCODEC_ANC29_CANVAS_ADDR)
#define HCODEC_ANC30_CANVAS_ADDR 0x19ae 	///../ucode/dos_register.h:4093
#define P_HCODEC_ANC30_CANVAS_ADDR 		DOS_REG_ADDR(HCODEC_ANC30_CANVAS_ADDR)
#define HCODEC_ANC31_CANVAS_ADDR 0x19af 	///../ucode/dos_register.h:4094
#define P_HCODEC_ANC31_CANVAS_ADDR 		DOS_REG_ADDR(HCODEC_ANC31_CANVAS_ADDR)
#define HCODEC_DBKR_CANVAS_ADDR 0x19b0 	///../ucode/dos_register.h:4095
#define P_HCODEC_DBKR_CANVAS_ADDR 		DOS_REG_ADDR(HCODEC_DBKR_CANVAS_ADDR)
#define HCODEC_DBKW_CANVAS_ADDR 0x19b1 	///../ucode/dos_register.h:4096
#define P_HCODEC_DBKW_CANVAS_ADDR 		DOS_REG_ADDR(HCODEC_DBKW_CANVAS_ADDR)
#define HCODEC_REC_CANVAS_ADDR 0x19b2 	///../ucode/dos_register.h:4097
#define P_HCODEC_REC_CANVAS_ADDR 		DOS_REG_ADDR(HCODEC_REC_CANVAS_ADDR)
#define HCODEC_CURR_CANVAS_CTRL 0x19b3 	///../ucode/dos_register.h:4100
#define P_HCODEC_CURR_CANVAS_CTRL 		DOS_REG_ADDR(HCODEC_CURR_CANVAS_CTRL)
#define HCODEC_MDEC_PIC_DC_THRESH 0x19b8 	///../ucode/dos_register.h:4101
#define P_HCODEC_MDEC_PIC_DC_THRESH 		DOS_REG_ADDR(HCODEC_MDEC_PIC_DC_THRESH)
#define HCODEC_MDEC_PICR_BUF_STATUS 0x19b9 	///../ucode/dos_register.h:4102
#define P_HCODEC_MDEC_PICR_BUF_STATUS 		DOS_REG_ADDR(HCODEC_MDEC_PICR_BUF_STATUS)
#define HCODEC_MDEC_PICW_BUF_STATUS 0x19ba 	///../ucode/dos_register.h:4103
#define P_HCODEC_MDEC_PICW_BUF_STATUS 		DOS_REG_ADDR(HCODEC_MDEC_PICW_BUF_STATUS)
#define HCODEC_MCW_DBLK_WRRSP_CNT 0x19bb 	///../ucode/dos_register.h:4104
#define P_HCODEC_MCW_DBLK_WRRSP_CNT 		DOS_REG_ADDR(HCODEC_MCW_DBLK_WRRSP_CNT)
#define HCODEC_MC_MBBOT_WRRSP_CNT 0x19bc 	///../ucode/dos_register.h:4105
#define P_HCODEC_MC_MBBOT_WRRSP_CNT 		DOS_REG_ADDR(HCODEC_MC_MBBOT_WRRSP_CNT)
#define HCODEC_MDEC_PICW_BUF2_STATUS 0x19bd 	///../ucode/dos_register.h:4106
#define P_HCODEC_MDEC_PICW_BUF2_STATUS 		DOS_REG_ADDR(HCODEC_MDEC_PICW_BUF2_STATUS)
#define HCODEC_WRRSP_FIFO_PICW_DBK 0x19be 	///../ucode/dos_register.h:4107
#define P_HCODEC_WRRSP_FIFO_PICW_DBK 		DOS_REG_ADDR(HCODEC_WRRSP_FIFO_PICW_DBK)
#define HCODEC_WRRSP_FIFO_PICW_MC 0x19bf 	///../ucode/dos_register.h:4108
#define P_HCODEC_WRRSP_FIFO_PICW_MC 		DOS_REG_ADDR(HCODEC_WRRSP_FIFO_PICW_MC)
#define HCODEC_AV_SCRATCH_0 0x19c0 	///../ucode/dos_register.h:4109
#define P_HCODEC_AV_SCRATCH_0 		DOS_REG_ADDR(HCODEC_AV_SCRATCH_0)
#define HCODEC_AV_SCRATCH_1 0x19c1 	///../ucode/dos_register.h:4110
#define P_HCODEC_AV_SCRATCH_1 		DOS_REG_ADDR(HCODEC_AV_SCRATCH_1)
#define HCODEC_AV_SCRATCH_2 0x19c2 	///../ucode/dos_register.h:4111
#define P_HCODEC_AV_SCRATCH_2 		DOS_REG_ADDR(HCODEC_AV_SCRATCH_2)
#define HCODEC_AV_SCRATCH_3 0x19c3 	///../ucode/dos_register.h:4112
#define P_HCODEC_AV_SCRATCH_3 		DOS_REG_ADDR(HCODEC_AV_SCRATCH_3)
#define HCODEC_AV_SCRATCH_4 0x19c4 	///../ucode/dos_register.h:4113
#define P_HCODEC_AV_SCRATCH_4 		DOS_REG_ADDR(HCODEC_AV_SCRATCH_4)
#define HCODEC_AV_SCRATCH_5 0x19c5 	///../ucode/dos_register.h:4114
#define P_HCODEC_AV_SCRATCH_5 		DOS_REG_ADDR(HCODEC_AV_SCRATCH_5)
#define HCODEC_AV_SCRATCH_6 0x19c6 	///../ucode/dos_register.h:4115
#define P_HCODEC_AV_SCRATCH_6 		DOS_REG_ADDR(HCODEC_AV_SCRATCH_6)
#define HCODEC_AV_SCRATCH_7 0x19c7 	///../ucode/dos_register.h:4116
#define P_HCODEC_AV_SCRATCH_7 		DOS_REG_ADDR(HCODEC_AV_SCRATCH_7)
#define HCODEC_AV_SCRATCH_8 0x19c8 	///../ucode/dos_register.h:4117
#define P_HCODEC_AV_SCRATCH_8 		DOS_REG_ADDR(HCODEC_AV_SCRATCH_8)
#define HCODEC_AV_SCRATCH_9 0x19c9 	///../ucode/dos_register.h:4118
#define P_HCODEC_AV_SCRATCH_9 		DOS_REG_ADDR(HCODEC_AV_SCRATCH_9)
#define HCODEC_AV_SCRATCH_A 0x19ca 	///../ucode/dos_register.h:4119
#define P_HCODEC_AV_SCRATCH_A 		DOS_REG_ADDR(HCODEC_AV_SCRATCH_A)
#define HCODEC_AV_SCRATCH_B 0x19cb 	///../ucode/dos_register.h:4120
#define P_HCODEC_AV_SCRATCH_B 		DOS_REG_ADDR(HCODEC_AV_SCRATCH_B)
#define HCODEC_AV_SCRATCH_C 0x19cc 	///../ucode/dos_register.h:4121
#define P_HCODEC_AV_SCRATCH_C 		DOS_REG_ADDR(HCODEC_AV_SCRATCH_C)
#define HCODEC_AV_SCRATCH_D 0x19cd 	///../ucode/dos_register.h:4122
#define P_HCODEC_AV_SCRATCH_D 		DOS_REG_ADDR(HCODEC_AV_SCRATCH_D)
#define HCODEC_AV_SCRATCH_E 0x19ce 	///../ucode/dos_register.h:4123
#define P_HCODEC_AV_SCRATCH_E 		DOS_REG_ADDR(HCODEC_AV_SCRATCH_E)
#define HCODEC_AV_SCRATCH_F 0x19cf 	///../ucode/dos_register.h:4124
#define P_HCODEC_AV_SCRATCH_F 		DOS_REG_ADDR(HCODEC_AV_SCRATCH_F)
#define HCODEC_AV_SCRATCH_G 0x19d0 	///../ucode/dos_register.h:4125
#define P_HCODEC_AV_SCRATCH_G 		DOS_REG_ADDR(HCODEC_AV_SCRATCH_G)
#define HCODEC_AV_SCRATCH_H 0x19d1 	///../ucode/dos_register.h:4126
#define P_HCODEC_AV_SCRATCH_H 		DOS_REG_ADDR(HCODEC_AV_SCRATCH_H)
#define HCODEC_AV_SCRATCH_I 0x19d2 	///../ucode/dos_register.h:4127
#define P_HCODEC_AV_SCRATCH_I 		DOS_REG_ADDR(HCODEC_AV_SCRATCH_I)
#define HCODEC_AV_SCRATCH_J 0x19d3 	///../ucode/dos_register.h:4128
#define P_HCODEC_AV_SCRATCH_J 		DOS_REG_ADDR(HCODEC_AV_SCRATCH_J)
#define HCODEC_AV_SCRATCH_K 0x19d4 	///../ucode/dos_register.h:4129
#define P_HCODEC_AV_SCRATCH_K 		DOS_REG_ADDR(HCODEC_AV_SCRATCH_K)
#define HCODEC_AV_SCRATCH_L 0x19d5 	///../ucode/dos_register.h:4130
#define P_HCODEC_AV_SCRATCH_L 		DOS_REG_ADDR(HCODEC_AV_SCRATCH_L)
#define HCODEC_AV_SCRATCH_M 0x19d6 	///../ucode/dos_register.h:4131
#define P_HCODEC_AV_SCRATCH_M 		DOS_REG_ADDR(HCODEC_AV_SCRATCH_M)
#define HCODEC_AV_SCRATCH_N 0x19d7 	///../ucode/dos_register.h:4132
#define P_HCODEC_AV_SCRATCH_N 		DOS_REG_ADDR(HCODEC_AV_SCRATCH_N)
#define HCODEC_WRRSP_CO_MB 0x19d8 	///../ucode/dos_register.h:4136
#define P_HCODEC_WRRSP_CO_MB 		DOS_REG_ADDR(HCODEC_WRRSP_CO_MB)
#define HCODEC_WRRSP_DCAC 0x19d9 	///../ucode/dos_register.h:4140
#define P_HCODEC_WRRSP_DCAC 		DOS_REG_ADDR(HCODEC_WRRSP_DCAC)
#define HCODEC_WRRSP_VLD 0x19da 	///../ucode/dos_register.h:4142
#define P_HCODEC_WRRSP_VLD 		DOS_REG_ADDR(HCODEC_WRRSP_VLD)
#define HCODEC_MDEC_DOUBLEW_CFG0 0x19db 	///../ucode/dos_register.h:4158
#define P_HCODEC_MDEC_DOUBLEW_CFG0 		DOS_REG_ADDR(HCODEC_MDEC_DOUBLEW_CFG0)
#define HCODEC_MDEC_DOUBLEW_CFG1 0x19dc 	///../ucode/dos_register.h:4164
#define P_HCODEC_MDEC_DOUBLEW_CFG1 		DOS_REG_ADDR(HCODEC_MDEC_DOUBLEW_CFG1)
#define HCODEC_MDEC_DOUBLEW_CFG2 0x19dd 	///../ucode/dos_register.h:4169
#define P_HCODEC_MDEC_DOUBLEW_CFG2 		DOS_REG_ADDR(HCODEC_MDEC_DOUBLEW_CFG2)
#define HCODEC_MDEC_DOUBLEW_CFG3 0x19de 	///../ucode/dos_register.h:4171
#define P_HCODEC_MDEC_DOUBLEW_CFG3 		DOS_REG_ADDR(HCODEC_MDEC_DOUBLEW_CFG3)
#define HCODEC_MDEC_DOUBLEW_CFG4 0x19df 	///../ucode/dos_register.h:4173
#define P_HCODEC_MDEC_DOUBLEW_CFG4 		DOS_REG_ADDR(HCODEC_MDEC_DOUBLEW_CFG4)
#define HCODEC_MDEC_DOUBLEW_CFG5 0x19e0 	///../ucode/dos_register.h:4176
#define P_HCODEC_MDEC_DOUBLEW_CFG5 		DOS_REG_ADDR(HCODEC_MDEC_DOUBLEW_CFG5)
#define HCODEC_MDEC_DOUBLEW_CFG6 0x19e1 	///../ucode/dos_register.h:4178
#define P_HCODEC_MDEC_DOUBLEW_CFG6 		DOS_REG_ADDR(HCODEC_MDEC_DOUBLEW_CFG6)
#define HCODEC_MDEC_DOUBLEW_CFG7 0x19e2 	///../ucode/dos_register.h:4180
#define P_HCODEC_MDEC_DOUBLEW_CFG7 		DOS_REG_ADDR(HCODEC_MDEC_DOUBLEW_CFG7)
#define HCODEC_MDEC_DOUBLEW_STATUS 0x19e3 	///../ucode/dos_register.h:4184
#define P_HCODEC_MDEC_DOUBLEW_STATUS 		DOS_REG_ADDR(HCODEC_MDEC_DOUBLEW_STATUS)
#define HCODEC_DBLK_RST 0x1950 	///../ucode/dos_register.h:4202
#define P_HCODEC_DBLK_RST 		DOS_REG_ADDR(HCODEC_DBLK_RST)
#define HCODEC_DBLK_CTRL 0x1951 	///../ucode/dos_register.h:4203
#define P_HCODEC_DBLK_CTRL 		DOS_REG_ADDR(HCODEC_DBLK_CTRL)
#define HCODEC_DBLK_MB_WID_HEIGHT 0x1952 	///../ucode/dos_register.h:4204
#define P_HCODEC_DBLK_MB_WID_HEIGHT 		DOS_REG_ADDR(HCODEC_DBLK_MB_WID_HEIGHT)
#define HCODEC_DBLK_STATUS 0x1953 	///../ucode/dos_register.h:4205
#define P_HCODEC_DBLK_STATUS 		DOS_REG_ADDR(HCODEC_DBLK_STATUS)
#define HCODEC_DBLK_CMD_CTRL 0x1954 	///../ucode/dos_register.h:4206
#define P_HCODEC_DBLK_CMD_CTRL 		DOS_REG_ADDR(HCODEC_DBLK_CMD_CTRL)
#define HCODEC_DBLK_MB_XY 0x1955 	///../ucode/dos_register.h:4207
#define P_HCODEC_DBLK_MB_XY 		DOS_REG_ADDR(HCODEC_DBLK_MB_XY)
#define HCODEC_DBLK_QP 0x1956 	///../ucode/dos_register.h:4208
#define P_HCODEC_DBLK_QP 		DOS_REG_ADDR(HCODEC_DBLK_QP)
#define HCODEC_DBLK_Y_BHFILT 0x1957 	///../ucode/dos_register.h:4209
#define P_HCODEC_DBLK_Y_BHFILT 		DOS_REG_ADDR(HCODEC_DBLK_Y_BHFILT)
#define HCODEC_DBLK_Y_BHFILT_HIGH 0x1958 	///../ucode/dos_register.h:4210
#define P_HCODEC_DBLK_Y_BHFILT_HIGH 		DOS_REG_ADDR(HCODEC_DBLK_Y_BHFILT_HIGH)
#define HCODEC_DBLK_Y_BVFILT 0x1959 	///../ucode/dos_register.h:4211
#define P_HCODEC_DBLK_Y_BVFILT 		DOS_REG_ADDR(HCODEC_DBLK_Y_BVFILT)
#define HCODEC_DBLK_CB_BFILT 0x195a 	///../ucode/dos_register.h:4212
#define P_HCODEC_DBLK_CB_BFILT 		DOS_REG_ADDR(HCODEC_DBLK_CB_BFILT)
#define HCODEC_DBLK_CR_BFILT 0x195b 	///../ucode/dos_register.h:4213
#define P_HCODEC_DBLK_CR_BFILT 		DOS_REG_ADDR(HCODEC_DBLK_CR_BFILT)
#define HCODEC_DBLK_Y_HFILT 0x195c 	///../ucode/dos_register.h:4214
#define P_HCODEC_DBLK_Y_HFILT 		DOS_REG_ADDR(HCODEC_DBLK_Y_HFILT)
#define HCODEC_DBLK_Y_HFILT_HIGH 0x195d 	///../ucode/dos_register.h:4215
#define P_HCODEC_DBLK_Y_HFILT_HIGH 		DOS_REG_ADDR(HCODEC_DBLK_Y_HFILT_HIGH)
#define HCODEC_DBLK_Y_VFILT 0x195e 	///../ucode/dos_register.h:4216
#define P_HCODEC_DBLK_Y_VFILT 		DOS_REG_ADDR(HCODEC_DBLK_Y_VFILT)
#define HCODEC_DBLK_CB_FILT 0x195f 	///../ucode/dos_register.h:4217
#define P_HCODEC_DBLK_CB_FILT 		DOS_REG_ADDR(HCODEC_DBLK_CB_FILT)
#define HCODEC_DBLK_CR_FILT 0x1960 	///../ucode/dos_register.h:4218
#define P_HCODEC_DBLK_CR_FILT 		DOS_REG_ADDR(HCODEC_DBLK_CR_FILT)
#define HCODEC_DBLK_BETAX_QP_SEL 0x1961 	///../ucode/dos_register.h:4219
#define P_HCODEC_DBLK_BETAX_QP_SEL 		DOS_REG_ADDR(HCODEC_DBLK_BETAX_QP_SEL)
#define HCODEC_DBLK_CLIP_CTRL0 0x1962 	///../ucode/dos_register.h:4220
#define P_HCODEC_DBLK_CLIP_CTRL0 		DOS_REG_ADDR(HCODEC_DBLK_CLIP_CTRL0)
#define HCODEC_DBLK_CLIP_CTRL1 0x1963 	///../ucode/dos_register.h:4221
#define P_HCODEC_DBLK_CLIP_CTRL1 		DOS_REG_ADDR(HCODEC_DBLK_CLIP_CTRL1)
#define HCODEC_DBLK_CLIP_CTRL2 0x1964 	///../ucode/dos_register.h:4222
#define P_HCODEC_DBLK_CLIP_CTRL2 		DOS_REG_ADDR(HCODEC_DBLK_CLIP_CTRL2)
#define HCODEC_DBLK_CLIP_CTRL3 0x1965 	///../ucode/dos_register.h:4223
#define P_HCODEC_DBLK_CLIP_CTRL3 		DOS_REG_ADDR(HCODEC_DBLK_CLIP_CTRL3)
#define HCODEC_DBLK_CLIP_CTRL4 0x1966 	///../ucode/dos_register.h:4224
#define P_HCODEC_DBLK_CLIP_CTRL4 		DOS_REG_ADDR(HCODEC_DBLK_CLIP_CTRL4)
#define HCODEC_DBLK_CLIP_CTRL5 0x1967 	///../ucode/dos_register.h:4225
#define P_HCODEC_DBLK_CLIP_CTRL5 		DOS_REG_ADDR(HCODEC_DBLK_CLIP_CTRL5)
#define HCODEC_DBLK_CLIP_CTRL6 0x1968 	///../ucode/dos_register.h:4226
#define P_HCODEC_DBLK_CLIP_CTRL6 		DOS_REG_ADDR(HCODEC_DBLK_CLIP_CTRL6)
#define HCODEC_DBLK_CLIP_CTRL7 0x1969 	///../ucode/dos_register.h:4227
#define P_HCODEC_DBLK_CLIP_CTRL7 		DOS_REG_ADDR(HCODEC_DBLK_CLIP_CTRL7)
#define HCODEC_DBLK_CLIP_CTRL8 0x196a 	///../ucode/dos_register.h:4228
#define P_HCODEC_DBLK_CLIP_CTRL8 		DOS_REG_ADDR(HCODEC_DBLK_CLIP_CTRL8)
#define HCODEC_DBLK_STATUS1 0x196b 	///../ucode/dos_register.h:4229
#define P_HCODEC_DBLK_STATUS1 		DOS_REG_ADDR(HCODEC_DBLK_STATUS1)
#define HCODEC_DBLK_GCLK_FREE 0x196c 	///../ucode/dos_register.h:4230
#define P_HCODEC_DBLK_GCLK_FREE 		DOS_REG_ADDR(HCODEC_DBLK_GCLK_FREE)
#define HCODEC_DBLK_GCLK_OFF 0x196d 	///../ucode/dos_register.h:4231
#define P_HCODEC_DBLK_GCLK_OFF 		DOS_REG_ADDR(HCODEC_DBLK_GCLK_OFF)
#define HCODEC_DBLK_AVSFLAGS 0x196e 	///../ucode/dos_register.h:4232
#define P_HCODEC_DBLK_AVSFLAGS 		DOS_REG_ADDR(HCODEC_DBLK_AVSFLAGS)
#define HCODEC_DBLK_CBPY 0x1970 	///../ucode/dos_register.h:4234
#define P_HCODEC_DBLK_CBPY 		DOS_REG_ADDR(HCODEC_DBLK_CBPY)
#define HCODEC_DBLK_CBPY_ADJ 0x1971 	///../ucode/dos_register.h:4238
#define P_HCODEC_DBLK_CBPY_ADJ 		DOS_REG_ADDR(HCODEC_DBLK_CBPY_ADJ)
#define HCODEC_DBLK_CBPC 0x1972 	///../ucode/dos_register.h:4240
#define P_HCODEC_DBLK_CBPC 		DOS_REG_ADDR(HCODEC_DBLK_CBPC)
#define HCODEC_DBLK_CBPC_ADJ 0x1973 	///../ucode/dos_register.h:4248
#define P_HCODEC_DBLK_CBPC_ADJ 		DOS_REG_ADDR(HCODEC_DBLK_CBPC_ADJ)
#define HCODEC_DBLK_VHMVD 0x1974 	///../ucode/dos_register.h:4251
#define P_HCODEC_DBLK_VHMVD 		DOS_REG_ADDR(HCODEC_DBLK_VHMVD)
#define HCODEC_DBLK_STRONG 0x1975 	///../ucode/dos_register.h:4265
#define P_HCODEC_DBLK_STRONG 		DOS_REG_ADDR(HCODEC_DBLK_STRONG)
#define HCODEC_DBLK_RV8_QUANT 0x1976 	///../ucode/dos_register.h:4269
#define P_HCODEC_DBLK_RV8_QUANT 		DOS_REG_ADDR(HCODEC_DBLK_RV8_QUANT)
#define HCODEC_DBLK_CBUS_HCMD2 0x1977 	///../ucode/dos_register.h:4270
#define P_HCODEC_DBLK_CBUS_HCMD2 		DOS_REG_ADDR(HCODEC_DBLK_CBUS_HCMD2)
#define HCODEC_DBLK_CBUS_HCMD1 0x1978 	///../ucode/dos_register.h:4271
#define P_HCODEC_DBLK_CBUS_HCMD1 		DOS_REG_ADDR(HCODEC_DBLK_CBUS_HCMD1)
#define HCODEC_DBLK_CBUS_HCMD0 0x1979 	///../ucode/dos_register.h:4272
#define P_HCODEC_DBLK_CBUS_HCMD0 		DOS_REG_ADDR(HCODEC_DBLK_CBUS_HCMD0)
#define HCODEC_DBLK_VLD_HCMD2 0x197a 	///../ucode/dos_register.h:4273
#define P_HCODEC_DBLK_VLD_HCMD2 		DOS_REG_ADDR(HCODEC_DBLK_VLD_HCMD2)
#define HCODEC_DBLK_VLD_HCMD1 0x197b 	///../ucode/dos_register.h:4274
#define P_HCODEC_DBLK_VLD_HCMD1 		DOS_REG_ADDR(HCODEC_DBLK_VLD_HCMD1)
#define HCODEC_DBLK_VLD_HCMD0 0x197c 	///../ucode/dos_register.h:4275
#define P_HCODEC_DBLK_VLD_HCMD0 		DOS_REG_ADDR(HCODEC_DBLK_VLD_HCMD0)
#define HCODEC_DBLK_OST_YBASE 0x197d 	///../ucode/dos_register.h:4276
#define P_HCODEC_DBLK_OST_YBASE 		DOS_REG_ADDR(HCODEC_DBLK_OST_YBASE)
#define HCODEC_DBLK_OST_CBCRDIFF 0x197e 	///../ucode/dos_register.h:4277
#define P_HCODEC_DBLK_OST_CBCRDIFF 		DOS_REG_ADDR(HCODEC_DBLK_OST_CBCRDIFF)
#define HCODEC_DBLK_CTRL1 0x197f 	///../ucode/dos_register.h:4280
#define P_HCODEC_DBLK_CTRL1 		DOS_REG_ADDR(HCODEC_DBLK_CTRL1)
#define HCODEC_MCRCC_CTL1 0x1980 	///../ucode/dos_register.h:4286
#define P_HCODEC_MCRCC_CTL1 		DOS_REG_ADDR(HCODEC_MCRCC_CTL1)
#define HCODEC_MCRCC_CTL2 0x1981 	///../ucode/dos_register.h:4292
#define P_HCODEC_MCRCC_CTL2 		DOS_REG_ADDR(HCODEC_MCRCC_CTL2)
#define HCODEC_MCRCC_CTL3 0x1982 	///../ucode/dos_register.h:4298
#define P_HCODEC_MCRCC_CTL3 		DOS_REG_ADDR(HCODEC_MCRCC_CTL3)
#define HCODEC_GCLK_EN 0x1983 	///../ucode/dos_register.h:4311
#define P_HCODEC_GCLK_EN 		DOS_REG_ADDR(HCODEC_GCLK_EN)
#define HCODEC_MDEC_SW_RESET 0x1984 	///../ucode/dos_register.h:4326
#define P_HCODEC_MDEC_SW_RESET 		DOS_REG_ADDR(HCODEC_MDEC_SW_RESET)
#define VDEC2_MC_CTRL_REG 0x2900 	///../ucode/dos_register.h:4340
#define P_VDEC2_MC_CTRL_REG 		DOS_REG_ADDR(VDEC2_MC_CTRL_REG)
#define VDEC2_MC_MB_INFO 0x2901 	///../ucode/dos_register.h:4341
#define P_VDEC2_MC_MB_INFO 		DOS_REG_ADDR(VDEC2_MC_MB_INFO)
#define VDEC2_MC_PIC_INFO 0x2902 	///../ucode/dos_register.h:4342
#define P_VDEC2_MC_PIC_INFO 		DOS_REG_ADDR(VDEC2_MC_PIC_INFO)
#define VDEC2_MC_HALF_PEL_ONE 0x2903 	///../ucode/dos_register.h:4343
#define P_VDEC2_MC_HALF_PEL_ONE 		DOS_REG_ADDR(VDEC2_MC_HALF_PEL_ONE)
#define VDEC2_MC_HALF_PEL_TWO 0x2904 	///../ucode/dos_register.h:4344
#define P_VDEC2_MC_HALF_PEL_TWO 		DOS_REG_ADDR(VDEC2_MC_HALF_PEL_TWO)
#define VDEC2_POWER_CTL_MC 0x2905 	///../ucode/dos_register.h:4345
#define P_VDEC2_POWER_CTL_MC 		DOS_REG_ADDR(VDEC2_POWER_CTL_MC)
#define VDEC2_MC_CMD 0x2906 	///../ucode/dos_register.h:4346
#define P_VDEC2_MC_CMD 		DOS_REG_ADDR(VDEC2_MC_CMD)
#define VDEC2_MC_CTRL0 0x2907 	///../ucode/dos_register.h:4347
#define P_VDEC2_MC_CTRL0 		DOS_REG_ADDR(VDEC2_MC_CTRL0)
#define VDEC2_MC_PIC_W_H 0x2908 	///../ucode/dos_register.h:4348
#define P_VDEC2_MC_PIC_W_H 		DOS_REG_ADDR(VDEC2_MC_PIC_W_H)
#define VDEC2_MC_STATUS0 0x2909 	///../ucode/dos_register.h:4349
#define P_VDEC2_MC_STATUS0 		DOS_REG_ADDR(VDEC2_MC_STATUS0)
#define VDEC2_MC_STATUS1 0x290a 	///../ucode/dos_register.h:4350
#define P_VDEC2_MC_STATUS1 		DOS_REG_ADDR(VDEC2_MC_STATUS1)
#define VDEC2_MC_CTRL1 0x290b 	///../ucode/dos_register.h:4351
#define P_VDEC2_MC_CTRL1 		DOS_REG_ADDR(VDEC2_MC_CTRL1)
#define VDEC2_MC_MIX_RATIO0 0x290c 	///../ucode/dos_register.h:4352
#define P_VDEC2_MC_MIX_RATIO0 		DOS_REG_ADDR(VDEC2_MC_MIX_RATIO0)
#define VDEC2_MC_MIX_RATIO1 0x290d 	///../ucode/dos_register.h:4353
#define P_VDEC2_MC_MIX_RATIO1 		DOS_REG_ADDR(VDEC2_MC_MIX_RATIO1)
#define VDEC2_MC_DP_MB_XY 0x290e 	///../ucode/dos_register.h:4354
#define P_VDEC2_MC_DP_MB_XY 		DOS_REG_ADDR(VDEC2_MC_DP_MB_XY)
#define VDEC2_MC_OM_MB_XY 0x290f 	///../ucode/dos_register.h:4355
#define P_VDEC2_MC_OM_MB_XY 		DOS_REG_ADDR(VDEC2_MC_OM_MB_XY)
#define VDEC2_PSCALE_RST 0x2910 	///../ucode/dos_register.h:4356
#define P_VDEC2_PSCALE_RST 		DOS_REG_ADDR(VDEC2_PSCALE_RST)
#define VDEC2_PSCALE_CTRL 0x2911 	///../ucode/dos_register.h:4357
#define P_VDEC2_PSCALE_CTRL 		DOS_REG_ADDR(VDEC2_PSCALE_CTRL)
#define VDEC2_PSCALE_PICI_W 0x2912 	///../ucode/dos_register.h:4358
#define P_VDEC2_PSCALE_PICI_W 		DOS_REG_ADDR(VDEC2_PSCALE_PICI_W)
#define VDEC2_PSCALE_PICI_H 0x2913 	///../ucode/dos_register.h:4359
#define P_VDEC2_PSCALE_PICI_H 		DOS_REG_ADDR(VDEC2_PSCALE_PICI_H)
#define VDEC2_PSCALE_PICO_W 0x2914 	///../ucode/dos_register.h:4360
#define P_VDEC2_PSCALE_PICO_W 		DOS_REG_ADDR(VDEC2_PSCALE_PICO_W)
#define VDEC2_PSCALE_PICO_H 0x2915 	///../ucode/dos_register.h:4361
#define P_VDEC2_PSCALE_PICO_H 		DOS_REG_ADDR(VDEC2_PSCALE_PICO_H)
#define VDEC2_PSCALE_PICO_START_X 0x2916 	///../ucode/dos_register.h:4362
#define P_VDEC2_PSCALE_PICO_START_X 		DOS_REG_ADDR(VDEC2_PSCALE_PICO_START_X)
#define VDEC2_PSCALE_PICO_START_Y 0x2917 	///../ucode/dos_register.h:4363
#define P_VDEC2_PSCALE_PICO_START_Y 		DOS_REG_ADDR(VDEC2_PSCALE_PICO_START_Y)
#define VDEC2_PSCALE_DUMMY 0x2918 	///../ucode/dos_register.h:4364
#define P_VDEC2_PSCALE_DUMMY 		DOS_REG_ADDR(VDEC2_PSCALE_DUMMY)
#define VDEC2_PSCALE_FILT0_COEF0 0x2919 	///../ucode/dos_register.h:4365
#define P_VDEC2_PSCALE_FILT0_COEF0 		DOS_REG_ADDR(VDEC2_PSCALE_FILT0_COEF0)
#define VDEC2_PSCALE_FILT0_COEF1 0x291a 	///../ucode/dos_register.h:4366
#define P_VDEC2_PSCALE_FILT0_COEF1 		DOS_REG_ADDR(VDEC2_PSCALE_FILT0_COEF1)
#define VDEC2_PSCALE_CMD_CTRL 0x291b 	///../ucode/dos_register.h:4367
#define P_VDEC2_PSCALE_CMD_CTRL 		DOS_REG_ADDR(VDEC2_PSCALE_CMD_CTRL)
#define VDEC2_PSCALE_CMD_BLK_X 0x291c 	///../ucode/dos_register.h:4368
#define P_VDEC2_PSCALE_CMD_BLK_X 		DOS_REG_ADDR(VDEC2_PSCALE_CMD_BLK_X)
#define VDEC2_PSCALE_CMD_BLK_Y 0x291d 	///../ucode/dos_register.h:4369
#define P_VDEC2_PSCALE_CMD_BLK_Y 		DOS_REG_ADDR(VDEC2_PSCALE_CMD_BLK_Y)
#define VDEC2_PSCALE_STATUS 0x291e 	///../ucode/dos_register.h:4370
#define P_VDEC2_PSCALE_STATUS 		DOS_REG_ADDR(VDEC2_PSCALE_STATUS)
#define VDEC2_PSCALE_BMEM_ADDR 0x291f 	///../ucode/dos_register.h:4371
#define P_VDEC2_PSCALE_BMEM_ADDR 		DOS_REG_ADDR(VDEC2_PSCALE_BMEM_ADDR)
#define VDEC2_PSCALE_BMEM_DAT 0x2920 	///../ucode/dos_register.h:4372
#define P_VDEC2_PSCALE_BMEM_DAT 		DOS_REG_ADDR(VDEC2_PSCALE_BMEM_DAT)
#define VDEC2_PSCALE_DRAM_BUF_CTRL 0x2921 	///../ucode/dos_register.h:4373
#define P_VDEC2_PSCALE_DRAM_BUF_CTRL 		DOS_REG_ADDR(VDEC2_PSCALE_DRAM_BUF_CTRL)
#define VDEC2_PSCALE_MCMD_CTRL 0x2922 	///../ucode/dos_register.h:4374
#define P_VDEC2_PSCALE_MCMD_CTRL 		DOS_REG_ADDR(VDEC2_PSCALE_MCMD_CTRL)
#define VDEC2_PSCALE_MCMD_XSIZE 0x2923 	///../ucode/dos_register.h:4375
#define P_VDEC2_PSCALE_MCMD_XSIZE 		DOS_REG_ADDR(VDEC2_PSCALE_MCMD_XSIZE)
#define VDEC2_PSCALE_MCMD_YSIZE 0x2924 	///../ucode/dos_register.h:4376
#define P_VDEC2_PSCALE_MCMD_YSIZE 		DOS_REG_ADDR(VDEC2_PSCALE_MCMD_YSIZE)
#define VDEC2_PSCALE_RBUF_START_BLKX 0x2925 	///../ucode/dos_register.h:4377
#define P_VDEC2_PSCALE_RBUF_START_BLKX 		DOS_REG_ADDR(VDEC2_PSCALE_RBUF_START_BLKX)
#define VDEC2_PSCALE_RBUF_START_BLKY 0x2926 	///../ucode/dos_register.h:4378
#define P_VDEC2_PSCALE_RBUF_START_BLKY 		DOS_REG_ADDR(VDEC2_PSCALE_RBUF_START_BLKY)
#define VDEC2_PSCALE_PICO_SHIFT_XY 0x2928 	///../ucode/dos_register.h:4380
#define P_VDEC2_PSCALE_PICO_SHIFT_XY 		DOS_REG_ADDR(VDEC2_PSCALE_PICO_SHIFT_XY)
#define VDEC2_PSCALE_CTRL1 0x2929 	///../ucode/dos_register.h:4381
#define P_VDEC2_PSCALE_CTRL1 		DOS_REG_ADDR(VDEC2_PSCALE_CTRL1)
#define VDEC2_PSCALE_SRCKEY_CTRL0 0x292a 	///../ucode/dos_register.h:4389
#define P_VDEC2_PSCALE_SRCKEY_CTRL0 		DOS_REG_ADDR(VDEC2_PSCALE_SRCKEY_CTRL0)
#define VDEC2_PSCALE_SRCKEY_CTRL1 0x292b 	///../ucode/dos_register.h:4392
#define P_VDEC2_PSCALE_SRCKEY_CTRL1 		DOS_REG_ADDR(VDEC2_PSCALE_SRCKEY_CTRL1)
#define VDEC2_PSCALE_CANVAS_RD_ADDR 0x292c 	///../ucode/dos_register.h:4396
#define P_VDEC2_PSCALE_CANVAS_RD_ADDR 		DOS_REG_ADDR(VDEC2_PSCALE_CANVAS_RD_ADDR)
#define VDEC2_PSCALE_CANVAS_WR_ADDR 0x292d 	///../ucode/dos_register.h:4400
#define P_VDEC2_PSCALE_CANVAS_WR_ADDR 		DOS_REG_ADDR(VDEC2_PSCALE_CANVAS_WR_ADDR)
#define VDEC2_PSCALE_CTRL2 0x292e 	///../ucode/dos_register.h:4404
#define P_VDEC2_PSCALE_CTRL2 		DOS_REG_ADDR(VDEC2_PSCALE_CTRL2)
#define VDEC2_MC_MPORT_CTRL 0x2940 	///../ucode/dos_register.h:4405
#define P_VDEC2_MC_MPORT_CTRL 		DOS_REG_ADDR(VDEC2_MC_MPORT_CTRL)
#define VDEC2_MC_MPORT_DAT 0x2941 	///../ucode/dos_register.h:4406
#define P_VDEC2_MC_MPORT_DAT 		DOS_REG_ADDR(VDEC2_MC_MPORT_DAT)
#define VDEC2_MC_WT_PRED_CTRL 0x2942 	///../ucode/dos_register.h:4407
#define P_VDEC2_MC_WT_PRED_CTRL 		DOS_REG_ADDR(VDEC2_MC_WT_PRED_CTRL)
#define VDEC2_MC_MBBOT_ST_EVEN_ADDR 0x2944 	///../ucode/dos_register.h:4408
#define P_VDEC2_MC_MBBOT_ST_EVEN_ADDR 		DOS_REG_ADDR(VDEC2_MC_MBBOT_ST_EVEN_ADDR)
#define VDEC2_MC_MBBOT_ST_ODD_ADDR 0x2945 	///../ucode/dos_register.h:4409
#define P_VDEC2_MC_MBBOT_ST_ODD_ADDR 		DOS_REG_ADDR(VDEC2_MC_MBBOT_ST_ODD_ADDR)
#define VDEC2_MC_DPDN_MB_XY 0x2946 	///../ucode/dos_register.h:4410
#define P_VDEC2_MC_DPDN_MB_XY 		DOS_REG_ADDR(VDEC2_MC_DPDN_MB_XY)
#define VDEC2_MC_OMDN_MB_XY 0x2947 	///../ucode/dos_register.h:4411
#define P_VDEC2_MC_OMDN_MB_XY 		DOS_REG_ADDR(VDEC2_MC_OMDN_MB_XY)
#define VDEC2_MC_HCMDBUF_H 0x2948 	///../ucode/dos_register.h:4412
#define P_VDEC2_MC_HCMDBUF_H 		DOS_REG_ADDR(VDEC2_MC_HCMDBUF_H)
#define VDEC2_MC_HCMDBUF_L 0x2949 	///../ucode/dos_register.h:4413
#define P_VDEC2_MC_HCMDBUF_L 		DOS_REG_ADDR(VDEC2_MC_HCMDBUF_L)
#define VDEC2_MC_HCMD_H 0x294a 	///../ucode/dos_register.h:4414
#define P_VDEC2_MC_HCMD_H 		DOS_REG_ADDR(VDEC2_MC_HCMD_H)
#define VDEC2_MC_HCMD_L 0x294b 	///../ucode/dos_register.h:4415
#define P_VDEC2_MC_HCMD_L 		DOS_REG_ADDR(VDEC2_MC_HCMD_L)
#define VDEC2_MC_IDCT_DAT 0x294c 	///../ucode/dos_register.h:4416
#define P_VDEC2_MC_IDCT_DAT 		DOS_REG_ADDR(VDEC2_MC_IDCT_DAT)
#define VDEC2_MC_CTRL_GCLK_CTRL 0x294d 	///../ucode/dos_register.h:4417
#define P_VDEC2_MC_CTRL_GCLK_CTRL 		DOS_REG_ADDR(VDEC2_MC_CTRL_GCLK_CTRL)
#define VDEC2_MC_OTHER_GCLK_CTRL 0x294e 	///../ucode/dos_register.h:4418
#define P_VDEC2_MC_OTHER_GCLK_CTRL 		DOS_REG_ADDR(VDEC2_MC_OTHER_GCLK_CTRL)
#define VDEC2_MC_CTRL2 0x294f 	///../ucode/dos_register.h:4423
#define P_VDEC2_MC_CTRL2 		DOS_REG_ADDR(VDEC2_MC_CTRL2)
#define VDEC2_MDEC_PIC_DC_CTRL 0x298e 	///../ucode/dos_register.h:4430
#define P_VDEC2_MDEC_PIC_DC_CTRL 		DOS_REG_ADDR(VDEC2_MDEC_PIC_DC_CTRL)
#define VDEC2_MDEC_PIC_DC_STATUS 0x298f 	///../ucode/dos_register.h:4431
#define P_VDEC2_MDEC_PIC_DC_STATUS 		DOS_REG_ADDR(VDEC2_MDEC_PIC_DC_STATUS)
#define VDEC2_ANC0_CANVAS_ADDR 0x2990 	///../ucode/dos_register.h:4432
#define P_VDEC2_ANC0_CANVAS_ADDR 		DOS_REG_ADDR(VDEC2_ANC0_CANVAS_ADDR)
#define VDEC2_ANC1_CANVAS_ADDR 0x2991 	///../ucode/dos_register.h:4433
#define P_VDEC2_ANC1_CANVAS_ADDR 		DOS_REG_ADDR(VDEC2_ANC1_CANVAS_ADDR)
#define VDEC2_ANC2_CANVAS_ADDR 0x2992 	///../ucode/dos_register.h:4434
#define P_VDEC2_ANC2_CANVAS_ADDR 		DOS_REG_ADDR(VDEC2_ANC2_CANVAS_ADDR)
#define VDEC2_ANC3_CANVAS_ADDR 0x2993 	///../ucode/dos_register.h:4435
#define P_VDEC2_ANC3_CANVAS_ADDR 		DOS_REG_ADDR(VDEC2_ANC3_CANVAS_ADDR)
#define VDEC2_ANC4_CANVAS_ADDR 0x2994 	///../ucode/dos_register.h:4436
#define P_VDEC2_ANC4_CANVAS_ADDR 		DOS_REG_ADDR(VDEC2_ANC4_CANVAS_ADDR)
#define VDEC2_ANC5_CANVAS_ADDR 0x2995 	///../ucode/dos_register.h:4437
#define P_VDEC2_ANC5_CANVAS_ADDR 		DOS_REG_ADDR(VDEC2_ANC5_CANVAS_ADDR)
#define VDEC2_ANC6_CANVAS_ADDR 0x2996 	///../ucode/dos_register.h:4438
#define P_VDEC2_ANC6_CANVAS_ADDR 		DOS_REG_ADDR(VDEC2_ANC6_CANVAS_ADDR)
#define VDEC2_ANC7_CANVAS_ADDR 0x2997 	///../ucode/dos_register.h:4439
#define P_VDEC2_ANC7_CANVAS_ADDR 		DOS_REG_ADDR(VDEC2_ANC7_CANVAS_ADDR)
#define VDEC2_ANC8_CANVAS_ADDR 0x2998 	///../ucode/dos_register.h:4440
#define P_VDEC2_ANC8_CANVAS_ADDR 		DOS_REG_ADDR(VDEC2_ANC8_CANVAS_ADDR)
#define VDEC2_ANC9_CANVAS_ADDR 0x2999 	///../ucode/dos_register.h:4441
#define P_VDEC2_ANC9_CANVAS_ADDR 		DOS_REG_ADDR(VDEC2_ANC9_CANVAS_ADDR)
#define VDEC2_ANC10_CANVAS_ADDR 0x299a 	///../ucode/dos_register.h:4442
#define P_VDEC2_ANC10_CANVAS_ADDR 		DOS_REG_ADDR(VDEC2_ANC10_CANVAS_ADDR)
#define VDEC2_ANC11_CANVAS_ADDR 0x299b 	///../ucode/dos_register.h:4443
#define P_VDEC2_ANC11_CANVAS_ADDR 		DOS_REG_ADDR(VDEC2_ANC11_CANVAS_ADDR)
#define VDEC2_ANC12_CANVAS_ADDR 0x299c 	///../ucode/dos_register.h:4444
#define P_VDEC2_ANC12_CANVAS_ADDR 		DOS_REG_ADDR(VDEC2_ANC12_CANVAS_ADDR)
#define VDEC2_ANC13_CANVAS_ADDR 0x299d 	///../ucode/dos_register.h:4445
#define P_VDEC2_ANC13_CANVAS_ADDR 		DOS_REG_ADDR(VDEC2_ANC13_CANVAS_ADDR)
#define VDEC2_ANC14_CANVAS_ADDR 0x299e 	///../ucode/dos_register.h:4446
#define P_VDEC2_ANC14_CANVAS_ADDR 		DOS_REG_ADDR(VDEC2_ANC14_CANVAS_ADDR)
#define VDEC2_ANC15_CANVAS_ADDR 0x299f 	///../ucode/dos_register.h:4447
#define P_VDEC2_ANC15_CANVAS_ADDR 		DOS_REG_ADDR(VDEC2_ANC15_CANVAS_ADDR)
#define VDEC2_ANC16_CANVAS_ADDR 0x29a0 	///../ucode/dos_register.h:4448
#define P_VDEC2_ANC16_CANVAS_ADDR 		DOS_REG_ADDR(VDEC2_ANC16_CANVAS_ADDR)
#define VDEC2_ANC17_CANVAS_ADDR 0x29a1 	///../ucode/dos_register.h:4449
#define P_VDEC2_ANC17_CANVAS_ADDR 		DOS_REG_ADDR(VDEC2_ANC17_CANVAS_ADDR)
#define VDEC2_ANC18_CANVAS_ADDR 0x29a2 	///../ucode/dos_register.h:4450
#define P_VDEC2_ANC18_CANVAS_ADDR 		DOS_REG_ADDR(VDEC2_ANC18_CANVAS_ADDR)
#define VDEC2_ANC19_CANVAS_ADDR 0x29a3 	///../ucode/dos_register.h:4451
#define P_VDEC2_ANC19_CANVAS_ADDR 		DOS_REG_ADDR(VDEC2_ANC19_CANVAS_ADDR)
#define VDEC2_ANC20_CANVAS_ADDR 0x29a4 	///../ucode/dos_register.h:4452
#define P_VDEC2_ANC20_CANVAS_ADDR 		DOS_REG_ADDR(VDEC2_ANC20_CANVAS_ADDR)
#define VDEC2_ANC21_CANVAS_ADDR 0x29a5 	///../ucode/dos_register.h:4453
#define P_VDEC2_ANC21_CANVAS_ADDR 		DOS_REG_ADDR(VDEC2_ANC21_CANVAS_ADDR)
#define VDEC2_ANC22_CANVAS_ADDR 0x29a6 	///../ucode/dos_register.h:4454
#define P_VDEC2_ANC22_CANVAS_ADDR 		DOS_REG_ADDR(VDEC2_ANC22_CANVAS_ADDR)
#define VDEC2_ANC23_CANVAS_ADDR 0x29a7 	///../ucode/dos_register.h:4455
#define P_VDEC2_ANC23_CANVAS_ADDR 		DOS_REG_ADDR(VDEC2_ANC23_CANVAS_ADDR)
#define VDEC2_ANC24_CANVAS_ADDR 0x29a8 	///../ucode/dos_register.h:4456
#define P_VDEC2_ANC24_CANVAS_ADDR 		DOS_REG_ADDR(VDEC2_ANC24_CANVAS_ADDR)
#define VDEC2_ANC25_CANVAS_ADDR 0x29a9 	///../ucode/dos_register.h:4457
#define P_VDEC2_ANC25_CANVAS_ADDR 		DOS_REG_ADDR(VDEC2_ANC25_CANVAS_ADDR)
#define VDEC2_ANC26_CANVAS_ADDR 0x29aa 	///../ucode/dos_register.h:4458
#define P_VDEC2_ANC26_CANVAS_ADDR 		DOS_REG_ADDR(VDEC2_ANC26_CANVAS_ADDR)
#define VDEC2_ANC27_CANVAS_ADDR 0x29ab 	///../ucode/dos_register.h:4459
#define P_VDEC2_ANC27_CANVAS_ADDR 		DOS_REG_ADDR(VDEC2_ANC27_CANVAS_ADDR)
#define VDEC2_ANC28_CANVAS_ADDR 0x29ac 	///../ucode/dos_register.h:4460
#define P_VDEC2_ANC28_CANVAS_ADDR 		DOS_REG_ADDR(VDEC2_ANC28_CANVAS_ADDR)
#define VDEC2_ANC29_CANVAS_ADDR 0x29ad 	///../ucode/dos_register.h:4461
#define P_VDEC2_ANC29_CANVAS_ADDR 		DOS_REG_ADDR(VDEC2_ANC29_CANVAS_ADDR)
#define VDEC2_ANC30_CANVAS_ADDR 0x29ae 	///../ucode/dos_register.h:4462
#define P_VDEC2_ANC30_CANVAS_ADDR 		DOS_REG_ADDR(VDEC2_ANC30_CANVAS_ADDR)
#define VDEC2_ANC31_CANVAS_ADDR 0x29af 	///../ucode/dos_register.h:4463
#define P_VDEC2_ANC31_CANVAS_ADDR 		DOS_REG_ADDR(VDEC2_ANC31_CANVAS_ADDR)
#define VDEC2_DBKR_CANVAS_ADDR 0x29b0 	///../ucode/dos_register.h:4464
#define P_VDEC2_DBKR_CANVAS_ADDR 		DOS_REG_ADDR(VDEC2_DBKR_CANVAS_ADDR)
#define VDEC2_DBKW_CANVAS_ADDR 0x29b1 	///../ucode/dos_register.h:4465
#define P_VDEC2_DBKW_CANVAS_ADDR 		DOS_REG_ADDR(VDEC2_DBKW_CANVAS_ADDR)
#define VDEC2_REC_CANVAS_ADDR 0x29b2 	///../ucode/dos_register.h:4466
#define P_VDEC2_REC_CANVAS_ADDR 		DOS_REG_ADDR(VDEC2_REC_CANVAS_ADDR)
#define VDEC2_CURR_CANVAS_CTRL 0x29b3 	///../ucode/dos_register.h:4469
#define P_VDEC2_CURR_CANVAS_CTRL 		DOS_REG_ADDR(VDEC2_CURR_CANVAS_CTRL)
#define VDEC2_MDEC_PIC_DC_THRESH 0x29b8 	///../ucode/dos_register.h:4470
#define P_VDEC2_MDEC_PIC_DC_THRESH 		DOS_REG_ADDR(VDEC2_MDEC_PIC_DC_THRESH)
#define VDEC2_MDEC_PICR_BUF_STATUS 0x29b9 	///../ucode/dos_register.h:4471
#define P_VDEC2_MDEC_PICR_BUF_STATUS 		DOS_REG_ADDR(VDEC2_MDEC_PICR_BUF_STATUS)
#define VDEC2_MDEC_PICW_BUF_STATUS 0x29ba 	///../ucode/dos_register.h:4472
#define P_VDEC2_MDEC_PICW_BUF_STATUS 		DOS_REG_ADDR(VDEC2_MDEC_PICW_BUF_STATUS)
#define VDEC2_MCW_DBLK_WRRSP_CNT 0x29bb 	///../ucode/dos_register.h:4473
#define P_VDEC2_MCW_DBLK_WRRSP_CNT 		DOS_REG_ADDR(VDEC2_MCW_DBLK_WRRSP_CNT)
#define VDEC2_MC_MBBOT_WRRSP_CNT 0x29bc 	///../ucode/dos_register.h:4474
#define P_VDEC2_MC_MBBOT_WRRSP_CNT 		DOS_REG_ADDR(VDEC2_MC_MBBOT_WRRSP_CNT)
#define VDEC2_MDEC_PICW_BUF2_STATUS 0x29bd 	///../ucode/dos_register.h:4475
#define P_VDEC2_MDEC_PICW_BUF2_STATUS 		DOS_REG_ADDR(VDEC2_MDEC_PICW_BUF2_STATUS)
#define VDEC2_WRRSP_FIFO_PICW_DBK 0x29be 	///../ucode/dos_register.h:4476
#define P_VDEC2_WRRSP_FIFO_PICW_DBK 		DOS_REG_ADDR(VDEC2_WRRSP_FIFO_PICW_DBK)
#define VDEC2_WRRSP_FIFO_PICW_MC 0x29bf 	///../ucode/dos_register.h:4477
#define P_VDEC2_WRRSP_FIFO_PICW_MC 		DOS_REG_ADDR(VDEC2_WRRSP_FIFO_PICW_MC)
#define VDEC2_AV_SCRATCH_0 0x29c0 	///../ucode/dos_register.h:4478
#define P_VDEC2_AV_SCRATCH_0 		DOS_REG_ADDR(VDEC2_AV_SCRATCH_0)
#define VDEC2_AV_SCRATCH_1 0x29c1 	///../ucode/dos_register.h:4479
#define P_VDEC2_AV_SCRATCH_1 		DOS_REG_ADDR(VDEC2_AV_SCRATCH_1)
#define VDEC2_AV_SCRATCH_2 0x29c2 	///../ucode/dos_register.h:4480
#define P_VDEC2_AV_SCRATCH_2 		DOS_REG_ADDR(VDEC2_AV_SCRATCH_2)
#define VDEC2_AV_SCRATCH_3 0x29c3 	///../ucode/dos_register.h:4481
#define P_VDEC2_AV_SCRATCH_3 		DOS_REG_ADDR(VDEC2_AV_SCRATCH_3)
#define VDEC2_AV_SCRATCH_4 0x29c4 	///../ucode/dos_register.h:4482
#define P_VDEC2_AV_SCRATCH_4 		DOS_REG_ADDR(VDEC2_AV_SCRATCH_4)
#define VDEC2_AV_SCRATCH_5 0x29c5 	///../ucode/dos_register.h:4483
#define P_VDEC2_AV_SCRATCH_5 		DOS_REG_ADDR(VDEC2_AV_SCRATCH_5)
#define VDEC2_AV_SCRATCH_6 0x29c6 	///../ucode/dos_register.h:4484
#define P_VDEC2_AV_SCRATCH_6 		DOS_REG_ADDR(VDEC2_AV_SCRATCH_6)
#define VDEC2_AV_SCRATCH_7 0x29c7 	///../ucode/dos_register.h:4485
#define P_VDEC2_AV_SCRATCH_7 		DOS_REG_ADDR(VDEC2_AV_SCRATCH_7)
#define VDEC2_AV_SCRATCH_8 0x29c8 	///../ucode/dos_register.h:4486
#define P_VDEC2_AV_SCRATCH_8 		DOS_REG_ADDR(VDEC2_AV_SCRATCH_8)
#define VDEC2_AV_SCRATCH_9 0x29c9 	///../ucode/dos_register.h:4487
#define P_VDEC2_AV_SCRATCH_9 		DOS_REG_ADDR(VDEC2_AV_SCRATCH_9)
#define VDEC2_AV_SCRATCH_A 0x29ca 	///../ucode/dos_register.h:4488
#define P_VDEC2_AV_SCRATCH_A 		DOS_REG_ADDR(VDEC2_AV_SCRATCH_A)
#define VDEC2_AV_SCRATCH_B 0x29cb 	///../ucode/dos_register.h:4489
#define P_VDEC2_AV_SCRATCH_B 		DOS_REG_ADDR(VDEC2_AV_SCRATCH_B)
#define VDEC2_AV_SCRATCH_C 0x29cc 	///../ucode/dos_register.h:4490
#define P_VDEC2_AV_SCRATCH_C 		DOS_REG_ADDR(VDEC2_AV_SCRATCH_C)
#define VDEC2_AV_SCRATCH_D 0x29cd 	///../ucode/dos_register.h:4491
#define P_VDEC2_AV_SCRATCH_D 		DOS_REG_ADDR(VDEC2_AV_SCRATCH_D)
#define VDEC2_AV_SCRATCH_E 0x29ce 	///../ucode/dos_register.h:4492
#define P_VDEC2_AV_SCRATCH_E 		DOS_REG_ADDR(VDEC2_AV_SCRATCH_E)
#define VDEC2_AV_SCRATCH_F 0x29cf 	///../ucode/dos_register.h:4493
#define P_VDEC2_AV_SCRATCH_F 		DOS_REG_ADDR(VDEC2_AV_SCRATCH_F)
#define VDEC2_AV_SCRATCH_G 0x29d0 	///../ucode/dos_register.h:4494
#define P_VDEC2_AV_SCRATCH_G 		DOS_REG_ADDR(VDEC2_AV_SCRATCH_G)
#define VDEC2_AV_SCRATCH_H 0x29d1 	///../ucode/dos_register.h:4495
#define P_VDEC2_AV_SCRATCH_H 		DOS_REG_ADDR(VDEC2_AV_SCRATCH_H)
#define VDEC2_AV_SCRATCH_I 0x29d2 	///../ucode/dos_register.h:4496
#define P_VDEC2_AV_SCRATCH_I 		DOS_REG_ADDR(VDEC2_AV_SCRATCH_I)
#define VDEC2_AV_SCRATCH_J 0x29d3 	///../ucode/dos_register.h:4497
#define P_VDEC2_AV_SCRATCH_J 		DOS_REG_ADDR(VDEC2_AV_SCRATCH_J)
#define VDEC2_AV_SCRATCH_K 0x29d4 	///../ucode/dos_register.h:4498
#define P_VDEC2_AV_SCRATCH_K 		DOS_REG_ADDR(VDEC2_AV_SCRATCH_K)
#define VDEC2_AV_SCRATCH_L 0x29d5 	///../ucode/dos_register.h:4499
#define P_VDEC2_AV_SCRATCH_L 		DOS_REG_ADDR(VDEC2_AV_SCRATCH_L)
#define VDEC2_AV_SCRATCH_M 0x29d6 	///../ucode/dos_register.h:4500
#define P_VDEC2_AV_SCRATCH_M 		DOS_REG_ADDR(VDEC2_AV_SCRATCH_M)
#define VDEC2_AV_SCRATCH_N 0x29d7 	///../ucode/dos_register.h:4501
#define P_VDEC2_AV_SCRATCH_N 		DOS_REG_ADDR(VDEC2_AV_SCRATCH_N)
#define VDEC2_WRRSP_CO_MB 0x29d8 	///../ucode/dos_register.h:4505
#define P_VDEC2_WRRSP_CO_MB 		DOS_REG_ADDR(VDEC2_WRRSP_CO_MB)
#define VDEC2_WRRSP_DCAC 0x29d9 	///../ucode/dos_register.h:4509
#define P_VDEC2_WRRSP_DCAC 		DOS_REG_ADDR(VDEC2_WRRSP_DCAC)
#define VDEC2_WRRSP_VLD 0x29da 	///../ucode/dos_register.h:4511
#define P_VDEC2_WRRSP_VLD 		DOS_REG_ADDR(VDEC2_WRRSP_VLD)
#define VDEC2_MDEC_DOUBLEW_CFG0 0x29db 	///../ucode/dos_register.h:4527
#define P_VDEC2_MDEC_DOUBLEW_CFG0 		DOS_REG_ADDR(VDEC2_MDEC_DOUBLEW_CFG0)
#define VDEC2_MDEC_DOUBLEW_CFG1 0x29dc 	///../ucode/dos_register.h:4533
#define P_VDEC2_MDEC_DOUBLEW_CFG1 		DOS_REG_ADDR(VDEC2_MDEC_DOUBLEW_CFG1)
#define VDEC2_MDEC_DOUBLEW_CFG2 0x29dd 	///../ucode/dos_register.h:4538
#define P_VDEC2_MDEC_DOUBLEW_CFG2 		DOS_REG_ADDR(VDEC2_MDEC_DOUBLEW_CFG2)
#define VDEC2_MDEC_DOUBLEW_CFG3 0x29de 	///../ucode/dos_register.h:4540
#define P_VDEC2_MDEC_DOUBLEW_CFG3 		DOS_REG_ADDR(VDEC2_MDEC_DOUBLEW_CFG3)
#define VDEC2_MDEC_DOUBLEW_CFG4 0x29df 	///../ucode/dos_register.h:4542
#define P_VDEC2_MDEC_DOUBLEW_CFG4 		DOS_REG_ADDR(VDEC2_MDEC_DOUBLEW_CFG4)
#define VDEC2_MDEC_DOUBLEW_CFG5 0x29e0 	///../ucode/dos_register.h:4545
#define P_VDEC2_MDEC_DOUBLEW_CFG5 		DOS_REG_ADDR(VDEC2_MDEC_DOUBLEW_CFG5)
#define VDEC2_MDEC_DOUBLEW_CFG6 0x29e1 	///../ucode/dos_register.h:4547
#define P_VDEC2_MDEC_DOUBLEW_CFG6 		DOS_REG_ADDR(VDEC2_MDEC_DOUBLEW_CFG6)
#define VDEC2_MDEC_DOUBLEW_CFG7 0x29e2 	///../ucode/dos_register.h:4549
#define P_VDEC2_MDEC_DOUBLEW_CFG7 		DOS_REG_ADDR(VDEC2_MDEC_DOUBLEW_CFG7)
#define VDEC2_MDEC_DOUBLEW_STATUS 0x29e3 	///../ucode/dos_register.h:4553
#define P_VDEC2_MDEC_DOUBLEW_STATUS 		DOS_REG_ADDR(VDEC2_MDEC_DOUBLEW_STATUS)
#define VDEC2_DBLK_RST 0x2950 	///../ucode/dos_register.h:4571
#define P_VDEC2_DBLK_RST 		DOS_REG_ADDR(VDEC2_DBLK_RST)
#define VDEC2_DBLK_CTRL 0x2951 	///../ucode/dos_register.h:4572
#define P_VDEC2_DBLK_CTRL 		DOS_REG_ADDR(VDEC2_DBLK_CTRL)
#define VDEC2_DBLK_MB_WID_HEIGHT 0x2952 	///../ucode/dos_register.h:4573
#define P_VDEC2_DBLK_MB_WID_HEIGHT 		DOS_REG_ADDR(VDEC2_DBLK_MB_WID_HEIGHT)
#define VDEC2_DBLK_STATUS 0x2953 	///../ucode/dos_register.h:4574
#define P_VDEC2_DBLK_STATUS 		DOS_REG_ADDR(VDEC2_DBLK_STATUS)
#define VDEC2_DBLK_CMD_CTRL 0x2954 	///../ucode/dos_register.h:4575
#define P_VDEC2_DBLK_CMD_CTRL 		DOS_REG_ADDR(VDEC2_DBLK_CMD_CTRL)
#define VDEC2_DBLK_MB_XY 0x2955 	///../ucode/dos_register.h:4576
#define P_VDEC2_DBLK_MB_XY 		DOS_REG_ADDR(VDEC2_DBLK_MB_XY)
#define VDEC2_DBLK_QP 0x2956 	///../ucode/dos_register.h:4577
#define P_VDEC2_DBLK_QP 		DOS_REG_ADDR(VDEC2_DBLK_QP)
#define VDEC2_DBLK_Y_BHFILT 0x2957 	///../ucode/dos_register.h:4578
#define P_VDEC2_DBLK_Y_BHFILT 		DOS_REG_ADDR(VDEC2_DBLK_Y_BHFILT)
#define VDEC2_DBLK_Y_BHFILT_HIGH 0x2958 	///../ucode/dos_register.h:4579
#define P_VDEC2_DBLK_Y_BHFILT_HIGH 		DOS_REG_ADDR(VDEC2_DBLK_Y_BHFILT_HIGH)
#define VDEC2_DBLK_Y_BVFILT 0x2959 	///../ucode/dos_register.h:4580
#define P_VDEC2_DBLK_Y_BVFILT 		DOS_REG_ADDR(VDEC2_DBLK_Y_BVFILT)
#define VDEC2_DBLK_CB_BFILT 0x295a 	///../ucode/dos_register.h:4581
#define P_VDEC2_DBLK_CB_BFILT 		DOS_REG_ADDR(VDEC2_DBLK_CB_BFILT)
#define VDEC2_DBLK_CR_BFILT 0x295b 	///../ucode/dos_register.h:4582
#define P_VDEC2_DBLK_CR_BFILT 		DOS_REG_ADDR(VDEC2_DBLK_CR_BFILT)
#define VDEC2_DBLK_Y_HFILT 0x295c 	///../ucode/dos_register.h:4583
#define P_VDEC2_DBLK_Y_HFILT 		DOS_REG_ADDR(VDEC2_DBLK_Y_HFILT)
#define VDEC2_DBLK_Y_HFILT_HIGH 0x295d 	///../ucode/dos_register.h:4584
#define P_VDEC2_DBLK_Y_HFILT_HIGH 		DOS_REG_ADDR(VDEC2_DBLK_Y_HFILT_HIGH)
#define VDEC2_DBLK_Y_VFILT 0x295e 	///../ucode/dos_register.h:4585
#define P_VDEC2_DBLK_Y_VFILT 		DOS_REG_ADDR(VDEC2_DBLK_Y_VFILT)
#define VDEC2_DBLK_CB_FILT 0x295f 	///../ucode/dos_register.h:4586
#define P_VDEC2_DBLK_CB_FILT 		DOS_REG_ADDR(VDEC2_DBLK_CB_FILT)
#define VDEC2_DBLK_CR_FILT 0x2960 	///../ucode/dos_register.h:4587
#define P_VDEC2_DBLK_CR_FILT 		DOS_REG_ADDR(VDEC2_DBLK_CR_FILT)
#define VDEC2_DBLK_BETAX_QP_SEL 0x2961 	///../ucode/dos_register.h:4588
#define P_VDEC2_DBLK_BETAX_QP_SEL 		DOS_REG_ADDR(VDEC2_DBLK_BETAX_QP_SEL)
#define VDEC2_DBLK_CLIP_CTRL0 0x2962 	///../ucode/dos_register.h:4589
#define P_VDEC2_DBLK_CLIP_CTRL0 		DOS_REG_ADDR(VDEC2_DBLK_CLIP_CTRL0)
#define VDEC2_DBLK_CLIP_CTRL1 0x2963 	///../ucode/dos_register.h:4590
#define P_VDEC2_DBLK_CLIP_CTRL1 		DOS_REG_ADDR(VDEC2_DBLK_CLIP_CTRL1)
#define VDEC2_DBLK_CLIP_CTRL2 0x2964 	///../ucode/dos_register.h:4591
#define P_VDEC2_DBLK_CLIP_CTRL2 		DOS_REG_ADDR(VDEC2_DBLK_CLIP_CTRL2)
#define VDEC2_DBLK_CLIP_CTRL3 0x2965 	///../ucode/dos_register.h:4592
#define P_VDEC2_DBLK_CLIP_CTRL3 		DOS_REG_ADDR(VDEC2_DBLK_CLIP_CTRL3)
#define VDEC2_DBLK_CLIP_CTRL4 0x2966 	///../ucode/dos_register.h:4593
#define P_VDEC2_DBLK_CLIP_CTRL4 		DOS_REG_ADDR(VDEC2_DBLK_CLIP_CTRL4)
#define VDEC2_DBLK_CLIP_CTRL5 0x2967 	///../ucode/dos_register.h:4594
#define P_VDEC2_DBLK_CLIP_CTRL5 		DOS_REG_ADDR(VDEC2_DBLK_CLIP_CTRL5)
#define VDEC2_DBLK_CLIP_CTRL6 0x2968 	///../ucode/dos_register.h:4595
#define P_VDEC2_DBLK_CLIP_CTRL6 		DOS_REG_ADDR(VDEC2_DBLK_CLIP_CTRL6)
#define VDEC2_DBLK_CLIP_CTRL7 0x2969 	///../ucode/dos_register.h:4596
#define P_VDEC2_DBLK_CLIP_CTRL7 		DOS_REG_ADDR(VDEC2_DBLK_CLIP_CTRL7)
#define VDEC2_DBLK_CLIP_CTRL8 0x296a 	///../ucode/dos_register.h:4597
#define P_VDEC2_DBLK_CLIP_CTRL8 		DOS_REG_ADDR(VDEC2_DBLK_CLIP_CTRL8)
#define VDEC2_DBLK_STATUS1 0x296b 	///../ucode/dos_register.h:4598
#define P_VDEC2_DBLK_STATUS1 		DOS_REG_ADDR(VDEC2_DBLK_STATUS1)
#define VDEC2_DBLK_GCLK_FREE 0x296c 	///../ucode/dos_register.h:4599
#define P_VDEC2_DBLK_GCLK_FREE 		DOS_REG_ADDR(VDEC2_DBLK_GCLK_FREE)
#define VDEC2_DBLK_GCLK_OFF 0x296d 	///../ucode/dos_register.h:4600
#define P_VDEC2_DBLK_GCLK_OFF 		DOS_REG_ADDR(VDEC2_DBLK_GCLK_OFF)
#define VDEC2_DBLK_AVSFLAGS 0x296e 	///../ucode/dos_register.h:4601
#define P_VDEC2_DBLK_AVSFLAGS 		DOS_REG_ADDR(VDEC2_DBLK_AVSFLAGS)
#define VDEC2_DBLK_CBPY 0x2970 	///../ucode/dos_register.h:4603
#define P_VDEC2_DBLK_CBPY 		DOS_REG_ADDR(VDEC2_DBLK_CBPY)
#define VDEC2_DBLK_CBPY_ADJ 0x2971 	///../ucode/dos_register.h:4607
#define P_VDEC2_DBLK_CBPY_ADJ 		DOS_REG_ADDR(VDEC2_DBLK_CBPY_ADJ)
#define VDEC2_DBLK_CBPC 0x2972 	///../ucode/dos_register.h:4609
#define P_VDEC2_DBLK_CBPC 		DOS_REG_ADDR(VDEC2_DBLK_CBPC)
#define VDEC2_DBLK_CBPC_ADJ 0x2973 	///../ucode/dos_register.h:4617
#define P_VDEC2_DBLK_CBPC_ADJ 		DOS_REG_ADDR(VDEC2_DBLK_CBPC_ADJ)
#define VDEC2_DBLK_VHMVD 0x2974 	///../ucode/dos_register.h:4620
#define P_VDEC2_DBLK_VHMVD 		DOS_REG_ADDR(VDEC2_DBLK_VHMVD)
#define VDEC2_DBLK_STRONG 0x2975 	///../ucode/dos_register.h:4634
#define P_VDEC2_DBLK_STRONG 		DOS_REG_ADDR(VDEC2_DBLK_STRONG)
#define VDEC2_DBLK_RV8_QUANT 0x2976 	///../ucode/dos_register.h:4638
#define P_VDEC2_DBLK_RV8_QUANT 		DOS_REG_ADDR(VDEC2_DBLK_RV8_QUANT)
#define VDEC2_DBLK_CBUS_HCMD2 0x2977 	///../ucode/dos_register.h:4639
#define P_VDEC2_DBLK_CBUS_HCMD2 		DOS_REG_ADDR(VDEC2_DBLK_CBUS_HCMD2)
#define VDEC2_DBLK_CBUS_HCMD1 0x2978 	///../ucode/dos_register.h:4640
#define P_VDEC2_DBLK_CBUS_HCMD1 		DOS_REG_ADDR(VDEC2_DBLK_CBUS_HCMD1)
#define VDEC2_DBLK_CBUS_HCMD0 0x2979 	///../ucode/dos_register.h:4641
#define P_VDEC2_DBLK_CBUS_HCMD0 		DOS_REG_ADDR(VDEC2_DBLK_CBUS_HCMD0)
#define VDEC2_DBLK_VLD_HCMD2 0x297a 	///../ucode/dos_register.h:4642
#define P_VDEC2_DBLK_VLD_HCMD2 		DOS_REG_ADDR(VDEC2_DBLK_VLD_HCMD2)
#define VDEC2_DBLK_VLD_HCMD1 0x297b 	///../ucode/dos_register.h:4643
#define P_VDEC2_DBLK_VLD_HCMD1 		DOS_REG_ADDR(VDEC2_DBLK_VLD_HCMD1)
#define VDEC2_DBLK_VLD_HCMD0 0x297c 	///../ucode/dos_register.h:4644
#define P_VDEC2_DBLK_VLD_HCMD0 		DOS_REG_ADDR(VDEC2_DBLK_VLD_HCMD0)
#define VDEC2_DBLK_OST_YBASE 0x297d 	///../ucode/dos_register.h:4645
#define P_VDEC2_DBLK_OST_YBASE 		DOS_REG_ADDR(VDEC2_DBLK_OST_YBASE)
#define VDEC2_DBLK_OST_CBCRDIFF 0x297e 	///../ucode/dos_register.h:4646
#define P_VDEC2_DBLK_OST_CBCRDIFF 		DOS_REG_ADDR(VDEC2_DBLK_OST_CBCRDIFF)
#define VDEC2_DBLK_CTRL1 0x297f 	///../ucode/dos_register.h:4649
#define P_VDEC2_DBLK_CTRL1 		DOS_REG_ADDR(VDEC2_DBLK_CTRL1)
#define VDEC2_MCRCC_CTL1 0x2980 	///../ucode/dos_register.h:4655
#define P_VDEC2_MCRCC_CTL1 		DOS_REG_ADDR(VDEC2_MCRCC_CTL1)
#define VDEC2_MCRCC_CTL2 0x2981 	///../ucode/dos_register.h:4661
#define P_VDEC2_MCRCC_CTL2 		DOS_REG_ADDR(VDEC2_MCRCC_CTL2)
#define VDEC2_MCRCC_CTL3 0x2982 	///../ucode/dos_register.h:4667
#define P_VDEC2_MCRCC_CTL3 		DOS_REG_ADDR(VDEC2_MCRCC_CTL3)
#define VDEC2_GCLK_EN 0x2983 	///../ucode/dos_register.h:4680
#define P_VDEC2_GCLK_EN 		DOS_REG_ADDR(VDEC2_GCLK_EN)
#define VDEC2_MDEC_SW_RESET 0x2984 	///../ucode/dos_register.h:4695
#define P_VDEC2_MDEC_SW_RESET 		DOS_REG_ADDR(VDEC2_MDEC_SW_RESET)
#define HEVC_MC_CTRL_REG 0x3900 	///../ucode/dos_register.h:4709
#define P_HEVC_MC_CTRL_REG 		DOS_REG_ADDR(HEVC_MC_CTRL_REG)
#define HEVC_MC_MB_INFO 0x3901 	///../ucode/dos_register.h:4710
#define P_HEVC_MC_MB_INFO 		DOS_REG_ADDR(HEVC_MC_MB_INFO)
#define HEVC_MC_PIC_INFO 0x3902 	///../ucode/dos_register.h:4711
#define P_HEVC_MC_PIC_INFO 		DOS_REG_ADDR(HEVC_MC_PIC_INFO)
#define HEVC_MC_HALF_PEL_ONE 0x3903 	///../ucode/dos_register.h:4712
#define P_HEVC_MC_HALF_PEL_ONE 		DOS_REG_ADDR(HEVC_MC_HALF_PEL_ONE)
#define HEVC_MC_HALF_PEL_TWO 0x3904 	///../ucode/dos_register.h:4713
#define P_HEVC_MC_HALF_PEL_TWO 		DOS_REG_ADDR(HEVC_MC_HALF_PEL_TWO)
#define HEVC_POWER_CTL_MC 0x3905 	///../ucode/dos_register.h:4714
#define P_HEVC_POWER_CTL_MC 		DOS_REG_ADDR(HEVC_POWER_CTL_MC)
#define HEVC_MC_CMD 0x3906 	///../ucode/dos_register.h:4715
#define P_HEVC_MC_CMD 		DOS_REG_ADDR(HEVC_MC_CMD)
#define HEVC_MC_CTRL0 0x3907 	///../ucode/dos_register.h:4716
#define P_HEVC_MC_CTRL0 		DOS_REG_ADDR(HEVC_MC_CTRL0)
#define HEVC_MC_PIC_W_H 0x3908 	///../ucode/dos_register.h:4717
#define P_HEVC_MC_PIC_W_H 		DOS_REG_ADDR(HEVC_MC_PIC_W_H)
#define HEVC_MC_STATUS0 0x3909 	///../ucode/dos_register.h:4718
#define P_HEVC_MC_STATUS0 		DOS_REG_ADDR(HEVC_MC_STATUS0)
#define HEVC_MC_STATUS1 0x390a 	///../ucode/dos_register.h:4719
#define P_HEVC_MC_STATUS1 		DOS_REG_ADDR(HEVC_MC_STATUS1)
#define HEVC_MC_CTRL1 0x390b 	///../ucode/dos_register.h:4720
#define P_HEVC_MC_CTRL1 		DOS_REG_ADDR(HEVC_MC_CTRL1)
#define HEVC_MC_MIX_RATIO0 0x390c 	///../ucode/dos_register.h:4721
#define P_HEVC_MC_MIX_RATIO0 		DOS_REG_ADDR(HEVC_MC_MIX_RATIO0)
#define HEVC_MC_MIX_RATIO1 0x390d 	///../ucode/dos_register.h:4722
#define P_HEVC_MC_MIX_RATIO1 		DOS_REG_ADDR(HEVC_MC_MIX_RATIO1)
#define HEVC_MC_DP_MB_XY 0x390e 	///../ucode/dos_register.h:4723
#define P_HEVC_MC_DP_MB_XY 		DOS_REG_ADDR(HEVC_MC_DP_MB_XY)
#define HEVC_MC_OM_MB_XY 0x390f 	///../ucode/dos_register.h:4724
#define P_HEVC_MC_OM_MB_XY 		DOS_REG_ADDR(HEVC_MC_OM_MB_XY)
#define HEVC_PSCALE_RST 0x3910 	///../ucode/dos_register.h:4725
#define P_HEVC_PSCALE_RST 		DOS_REG_ADDR(HEVC_PSCALE_RST)
#define HEVC_PSCALE_CTRL 0x3911 	///../ucode/dos_register.h:4726
#define P_HEVC_PSCALE_CTRL 		DOS_REG_ADDR(HEVC_PSCALE_CTRL)
#define HEVC_PSCALE_PICI_W 0x3912 	///../ucode/dos_register.h:4727
#define P_HEVC_PSCALE_PICI_W 		DOS_REG_ADDR(HEVC_PSCALE_PICI_W)
#define HEVC_PSCALE_PICI_H 0x3913 	///../ucode/dos_register.h:4728
#define P_HEVC_PSCALE_PICI_H 		DOS_REG_ADDR(HEVC_PSCALE_PICI_H)
#define HEVC_PSCALE_PICO_W 0x3914 	///../ucode/dos_register.h:4729
#define P_HEVC_PSCALE_PICO_W 		DOS_REG_ADDR(HEVC_PSCALE_PICO_W)
#define HEVC_PSCALE_PICO_H 0x3915 	///../ucode/dos_register.h:4730
#define P_HEVC_PSCALE_PICO_H 		DOS_REG_ADDR(HEVC_PSCALE_PICO_H)
#define HEVC_PSCALE_PICO_START_X 0x3916 	///../ucode/dos_register.h:4731
#define P_HEVC_PSCALE_PICO_START_X 		DOS_REG_ADDR(HEVC_PSCALE_PICO_START_X)
#define HEVC_PSCALE_PICO_START_Y 0x3917 	///../ucode/dos_register.h:4732
#define P_HEVC_PSCALE_PICO_START_Y 		DOS_REG_ADDR(HEVC_PSCALE_PICO_START_Y)
#define HEVC_PSCALE_DUMMY 0x3918 	///../ucode/dos_register.h:4733
#define P_HEVC_PSCALE_DUMMY 		DOS_REG_ADDR(HEVC_PSCALE_DUMMY)
#define HEVC_PSCALE_FILT0_COEF0 0x3919 	///../ucode/dos_register.h:4734
#define P_HEVC_PSCALE_FILT0_COEF0 		DOS_REG_ADDR(HEVC_PSCALE_FILT0_COEF0)
#define HEVC_PSCALE_FILT0_COEF1 0x391a 	///../ucode/dos_register.h:4735
#define P_HEVC_PSCALE_FILT0_COEF1 		DOS_REG_ADDR(HEVC_PSCALE_FILT0_COEF1)
#define HEVC_PSCALE_CMD_CTRL 0x391b 	///../ucode/dos_register.h:4736
#define P_HEVC_PSCALE_CMD_CTRL 		DOS_REG_ADDR(HEVC_PSCALE_CMD_CTRL)
#define HEVC_PSCALE_CMD_BLK_X 0x391c 	///../ucode/dos_register.h:4737
#define P_HEVC_PSCALE_CMD_BLK_X 		DOS_REG_ADDR(HEVC_PSCALE_CMD_BLK_X)
#define HEVC_PSCALE_CMD_BLK_Y 0x391d 	///../ucode/dos_register.h:4738
#define P_HEVC_PSCALE_CMD_BLK_Y 		DOS_REG_ADDR(HEVC_PSCALE_CMD_BLK_Y)
#define HEVC_PSCALE_STATUS 0x391e 	///../ucode/dos_register.h:4739
#define P_HEVC_PSCALE_STATUS 		DOS_REG_ADDR(HEVC_PSCALE_STATUS)
#define HEVC_PSCALE_BMEM_ADDR 0x391f 	///../ucode/dos_register.h:4740
#define P_HEVC_PSCALE_BMEM_ADDR 		DOS_REG_ADDR(HEVC_PSCALE_BMEM_ADDR)
#define HEVC_PSCALE_BMEM_DAT 0x3920 	///../ucode/dos_register.h:4741
#define P_HEVC_PSCALE_BMEM_DAT 		DOS_REG_ADDR(HEVC_PSCALE_BMEM_DAT)
#define HEVC_PSCALE_DRAM_BUF_CTRL 0x3921 	///../ucode/dos_register.h:4742
#define P_HEVC_PSCALE_DRAM_BUF_CTRL 		DOS_REG_ADDR(HEVC_PSCALE_DRAM_BUF_CTRL)
#define HEVC_PSCALE_MCMD_CTRL 0x3922 	///../ucode/dos_register.h:4743
#define P_HEVC_PSCALE_MCMD_CTRL 		DOS_REG_ADDR(HEVC_PSCALE_MCMD_CTRL)
#define HEVC_PSCALE_MCMD_XSIZE 0x3923 	///../ucode/dos_register.h:4744
#define P_HEVC_PSCALE_MCMD_XSIZE 		DOS_REG_ADDR(HEVC_PSCALE_MCMD_XSIZE)
#define HEVC_PSCALE_MCMD_YSIZE 0x3924 	///../ucode/dos_register.h:4745
#define P_HEVC_PSCALE_MCMD_YSIZE 		DOS_REG_ADDR(HEVC_PSCALE_MCMD_YSIZE)
#define HEVC_PSCALE_RBUF_START_BLKX 0x3925 	///../ucode/dos_register.h:4746
#define P_HEVC_PSCALE_RBUF_START_BLKX 		DOS_REG_ADDR(HEVC_PSCALE_RBUF_START_BLKX)
#define HEVC_PSCALE_RBUF_START_BLKY 0x3926 	///../ucode/dos_register.h:4747
#define P_HEVC_PSCALE_RBUF_START_BLKY 		DOS_REG_ADDR(HEVC_PSCALE_RBUF_START_BLKY)
#define HEVC_PSCALE_PICO_SHIFT_XY 0x3928 	///../ucode/dos_register.h:4749
#define P_HEVC_PSCALE_PICO_SHIFT_XY 		DOS_REG_ADDR(HEVC_PSCALE_PICO_SHIFT_XY)
#define HEVC_PSCALE_CTRL1 0x3929 	///../ucode/dos_register.h:4750
#define P_HEVC_PSCALE_CTRL1 		DOS_REG_ADDR(HEVC_PSCALE_CTRL1)
#define HEVC_PSCALE_SRCKEY_CTRL0 0x392a 	///../ucode/dos_register.h:4758
#define P_HEVC_PSCALE_SRCKEY_CTRL0 		DOS_REG_ADDR(HEVC_PSCALE_SRCKEY_CTRL0)
#define HEVC_PSCALE_SRCKEY_CTRL1 0x392b 	///../ucode/dos_register.h:4761
#define P_HEVC_PSCALE_SRCKEY_CTRL1 		DOS_REG_ADDR(HEVC_PSCALE_SRCKEY_CTRL1)
#define HEVC_PSCALE_CANVAS_RD_ADDR 0x392c 	///../ucode/dos_register.h:4765
#define P_HEVC_PSCALE_CANVAS_RD_ADDR 		DOS_REG_ADDR(HEVC_PSCALE_CANVAS_RD_ADDR)
#define HEVC_PSCALE_CANVAS_WR_ADDR 0x392d 	///../ucode/dos_register.h:4769
#define P_HEVC_PSCALE_CANVAS_WR_ADDR 		DOS_REG_ADDR(HEVC_PSCALE_CANVAS_WR_ADDR)
#define HEVC_PSCALE_CTRL2 0x392e 	///../ucode/dos_register.h:4773
#define P_HEVC_PSCALE_CTRL2 		DOS_REG_ADDR(HEVC_PSCALE_CTRL2)
#define HEVC_MC_MPORT_CTRL 0x3940 	///../ucode/dos_register.h:4774
#define P_HEVC_MC_MPORT_CTRL 		DOS_REG_ADDR(HEVC_MC_MPORT_CTRL)
#define HEVC_MC_MPORT_DAT 0x3941 	///../ucode/dos_register.h:4775
#define P_HEVC_MC_MPORT_DAT 		DOS_REG_ADDR(HEVC_MC_MPORT_DAT)
#define HEVC_MC_WT_PRED_CTRL 0x3942 	///../ucode/dos_register.h:4776
#define P_HEVC_MC_WT_PRED_CTRL 		DOS_REG_ADDR(HEVC_MC_WT_PRED_CTRL)
#define HEVC_MC_MBBOT_ST_EVEN_ADDR 0x3944 	///../ucode/dos_register.h:4777
#define P_HEVC_MC_MBBOT_ST_EVEN_ADDR 		DOS_REG_ADDR(HEVC_MC_MBBOT_ST_EVEN_ADDR)
#define HEVC_MC_MBBOT_ST_ODD_ADDR 0x3945 	///../ucode/dos_register.h:4778
#define P_HEVC_MC_MBBOT_ST_ODD_ADDR 		DOS_REG_ADDR(HEVC_MC_MBBOT_ST_ODD_ADDR)
#define HEVC_MC_DPDN_MB_XY 0x3946 	///../ucode/dos_register.h:4779
#define P_HEVC_MC_DPDN_MB_XY 		DOS_REG_ADDR(HEVC_MC_DPDN_MB_XY)
#define HEVC_MC_OMDN_MB_XY 0x3947 	///../ucode/dos_register.h:4780
#define P_HEVC_MC_OMDN_MB_XY 		DOS_REG_ADDR(HEVC_MC_OMDN_MB_XY)
#define HEVC_MC_HCMDBUF_H 0x3948 	///../ucode/dos_register.h:4781
#define P_HEVC_MC_HCMDBUF_H 		DOS_REG_ADDR(HEVC_MC_HCMDBUF_H)
#define HEVC_MC_HCMDBUF_L 0x3949 	///../ucode/dos_register.h:4782
#define P_HEVC_MC_HCMDBUF_L 		DOS_REG_ADDR(HEVC_MC_HCMDBUF_L)
#define HEVC_MC_HCMD_H 0x394a 	///../ucode/dos_register.h:4783
#define P_HEVC_MC_HCMD_H 		DOS_REG_ADDR(HEVC_MC_HCMD_H)
#define HEVC_MC_HCMD_L 0x394b 	///../ucode/dos_register.h:4784
#define P_HEVC_MC_HCMD_L 		DOS_REG_ADDR(HEVC_MC_HCMD_L)
#define HEVC_MC_IDCT_DAT 0x394c 	///../ucode/dos_register.h:4785
#define P_HEVC_MC_IDCT_DAT 		DOS_REG_ADDR(HEVC_MC_IDCT_DAT)
#define HEVC_MC_CTRL_GCLK_CTRL 0x394d 	///../ucode/dos_register.h:4786
#define P_HEVC_MC_CTRL_GCLK_CTRL 		DOS_REG_ADDR(HEVC_MC_CTRL_GCLK_CTRL)
#define HEVC_MC_OTHER_GCLK_CTRL 0x394e 	///../ucode/dos_register.h:4787
#define P_HEVC_MC_OTHER_GCLK_CTRL 		DOS_REG_ADDR(HEVC_MC_OTHER_GCLK_CTRL)
#define HEVC_MC_CTRL2 0x394f 	///../ucode/dos_register.h:4792
#define P_HEVC_MC_CTRL2 		DOS_REG_ADDR(HEVC_MC_CTRL2)
#define HEVC_MDEC_PIC_DC_CTRL 0x398e 	///../ucode/dos_register.h:4799
#define P_HEVC_MDEC_PIC_DC_CTRL 		DOS_REG_ADDR(HEVC_MDEC_PIC_DC_CTRL)
#define HEVC_MDEC_PIC_DC_STATUS 0x398f 	///../ucode/dos_register.h:4800
#define P_HEVC_MDEC_PIC_DC_STATUS 		DOS_REG_ADDR(HEVC_MDEC_PIC_DC_STATUS)
#define HEVC_ANC0_CANVAS_ADDR 0x3990 	///../ucode/dos_register.h:4801
#define P_HEVC_ANC0_CANVAS_ADDR 		DOS_REG_ADDR(HEVC_ANC0_CANVAS_ADDR)
#define HEVC_ANC1_CANVAS_ADDR 0x3991 	///../ucode/dos_register.h:4802
#define P_HEVC_ANC1_CANVAS_ADDR 		DOS_REG_ADDR(HEVC_ANC1_CANVAS_ADDR)
#define HEVC_ANC2_CANVAS_ADDR 0x3992 	///../ucode/dos_register.h:4803
#define P_HEVC_ANC2_CANVAS_ADDR 		DOS_REG_ADDR(HEVC_ANC2_CANVAS_ADDR)
#define HEVC_ANC3_CANVAS_ADDR 0x3993 	///../ucode/dos_register.h:4804
#define P_HEVC_ANC3_CANVAS_ADDR 		DOS_REG_ADDR(HEVC_ANC3_CANVAS_ADDR)
#define HEVC_ANC4_CANVAS_ADDR 0x3994 	///../ucode/dos_register.h:4805
#define P_HEVC_ANC4_CANVAS_ADDR 		DOS_REG_ADDR(HEVC_ANC4_CANVAS_ADDR)
#define HEVC_ANC5_CANVAS_ADDR 0x3995 	///../ucode/dos_register.h:4806
#define P_HEVC_ANC5_CANVAS_ADDR 		DOS_REG_ADDR(HEVC_ANC5_CANVAS_ADDR)
#define HEVC_ANC6_CANVAS_ADDR 0x3996 	///../ucode/dos_register.h:4807
#define P_HEVC_ANC6_CANVAS_ADDR 		DOS_REG_ADDR(HEVC_ANC6_CANVAS_ADDR)
#define HEVC_ANC7_CANVAS_ADDR 0x3997 	///../ucode/dos_register.h:4808
#define P_HEVC_ANC7_CANVAS_ADDR 		DOS_REG_ADDR(HEVC_ANC7_CANVAS_ADDR)
#define HEVC_ANC8_CANVAS_ADDR 0x3998 	///../ucode/dos_register.h:4809
#define P_HEVC_ANC8_CANVAS_ADDR 		DOS_REG_ADDR(HEVC_ANC8_CANVAS_ADDR)
#define HEVC_ANC9_CANVAS_ADDR 0x3999 	///../ucode/dos_register.h:4810
#define P_HEVC_ANC9_CANVAS_ADDR 		DOS_REG_ADDR(HEVC_ANC9_CANVAS_ADDR)
#define HEVC_ANC10_CANVAS_ADDR 0x399a 	///../ucode/dos_register.h:4811
#define P_HEVC_ANC10_CANVAS_ADDR 		DOS_REG_ADDR(HEVC_ANC10_CANVAS_ADDR)
#define HEVC_ANC11_CANVAS_ADDR 0x399b 	///../ucode/dos_register.h:4812
#define P_HEVC_ANC11_CANVAS_ADDR 		DOS_REG_ADDR(HEVC_ANC11_CANVAS_ADDR)
#define HEVC_ANC12_CANVAS_ADDR 0x399c 	///../ucode/dos_register.h:4813
#define P_HEVC_ANC12_CANVAS_ADDR 		DOS_REG_ADDR(HEVC_ANC12_CANVAS_ADDR)
#define HEVC_ANC13_CANVAS_ADDR 0x399d 	///../ucode/dos_register.h:4814
#define P_HEVC_ANC13_CANVAS_ADDR 		DOS_REG_ADDR(HEVC_ANC13_CANVAS_ADDR)
#define HEVC_ANC14_CANVAS_ADDR 0x399e 	///../ucode/dos_register.h:4815
#define P_HEVC_ANC14_CANVAS_ADDR 		DOS_REG_ADDR(HEVC_ANC14_CANVAS_ADDR)
#define HEVC_ANC15_CANVAS_ADDR 0x399f 	///../ucode/dos_register.h:4816
#define P_HEVC_ANC15_CANVAS_ADDR 		DOS_REG_ADDR(HEVC_ANC15_CANVAS_ADDR)
#define HEVC_ANC16_CANVAS_ADDR 0x39a0 	///../ucode/dos_register.h:4817
#define P_HEVC_ANC16_CANVAS_ADDR 		DOS_REG_ADDR(HEVC_ANC16_CANVAS_ADDR)
#define HEVC_ANC17_CANVAS_ADDR 0x39a1 	///../ucode/dos_register.h:4818
#define P_HEVC_ANC17_CANVAS_ADDR 		DOS_REG_ADDR(HEVC_ANC17_CANVAS_ADDR)
#define HEVC_ANC18_CANVAS_ADDR 0x39a2 	///../ucode/dos_register.h:4819
#define P_HEVC_ANC18_CANVAS_ADDR 		DOS_REG_ADDR(HEVC_ANC18_CANVAS_ADDR)
#define HEVC_ANC19_CANVAS_ADDR 0x39a3 	///../ucode/dos_register.h:4820
#define P_HEVC_ANC19_CANVAS_ADDR 		DOS_REG_ADDR(HEVC_ANC19_CANVAS_ADDR)
#define HEVC_ANC20_CANVAS_ADDR 0x39a4 	///../ucode/dos_register.h:4821
#define P_HEVC_ANC20_CANVAS_ADDR 		DOS_REG_ADDR(HEVC_ANC20_CANVAS_ADDR)
#define HEVC_ANC21_CANVAS_ADDR 0x39a5 	///../ucode/dos_register.h:4822
#define P_HEVC_ANC21_CANVAS_ADDR 		DOS_REG_ADDR(HEVC_ANC21_CANVAS_ADDR)
#define HEVC_ANC22_CANVAS_ADDR 0x39a6 	///../ucode/dos_register.h:4823
#define P_HEVC_ANC22_CANVAS_ADDR 		DOS_REG_ADDR(HEVC_ANC22_CANVAS_ADDR)
#define HEVC_ANC23_CANVAS_ADDR 0x39a7 	///../ucode/dos_register.h:4824
#define P_HEVC_ANC23_CANVAS_ADDR 		DOS_REG_ADDR(HEVC_ANC23_CANVAS_ADDR)
#define HEVC_ANC24_CANVAS_ADDR 0x39a8 	///../ucode/dos_register.h:4825
#define P_HEVC_ANC24_CANVAS_ADDR 		DOS_REG_ADDR(HEVC_ANC24_CANVAS_ADDR)
#define HEVC_ANC25_CANVAS_ADDR 0x39a9 	///../ucode/dos_register.h:4826
#define P_HEVC_ANC25_CANVAS_ADDR 		DOS_REG_ADDR(HEVC_ANC25_CANVAS_ADDR)
#define HEVC_ANC26_CANVAS_ADDR 0x39aa 	///../ucode/dos_register.h:4827
#define P_HEVC_ANC26_CANVAS_ADDR 		DOS_REG_ADDR(HEVC_ANC26_CANVAS_ADDR)
#define HEVC_ANC27_CANVAS_ADDR 0x39ab 	///../ucode/dos_register.h:4828
#define P_HEVC_ANC27_CANVAS_ADDR 		DOS_REG_ADDR(HEVC_ANC27_CANVAS_ADDR)
#define HEVC_ANC28_CANVAS_ADDR 0x39ac 	///../ucode/dos_register.h:4829
#define P_HEVC_ANC28_CANVAS_ADDR 		DOS_REG_ADDR(HEVC_ANC28_CANVAS_ADDR)
#define HEVC_ANC29_CANVAS_ADDR 0x39ad 	///../ucode/dos_register.h:4830
#define P_HEVC_ANC29_CANVAS_ADDR 		DOS_REG_ADDR(HEVC_ANC29_CANVAS_ADDR)
#define HEVC_ANC30_CANVAS_ADDR 0x39ae 	///../ucode/dos_register.h:4831
#define P_HEVC_ANC30_CANVAS_ADDR 		DOS_REG_ADDR(HEVC_ANC30_CANVAS_ADDR)
#define HEVC_ANC31_CANVAS_ADDR 0x39af 	///../ucode/dos_register.h:4832
#define P_HEVC_ANC31_CANVAS_ADDR 		DOS_REG_ADDR(HEVC_ANC31_CANVAS_ADDR)
#define HEVC_DBKR_CANVAS_ADDR 0x39b0 	///../ucode/dos_register.h:4833
#define P_HEVC_DBKR_CANVAS_ADDR 		DOS_REG_ADDR(HEVC_DBKR_CANVAS_ADDR)
#define HEVC_DBKW_CANVAS_ADDR 0x39b1 	///../ucode/dos_register.h:4834
#define P_HEVC_DBKW_CANVAS_ADDR 		DOS_REG_ADDR(HEVC_DBKW_CANVAS_ADDR)
#define HEVC_REC_CANVAS_ADDR 0x39b2 	///../ucode/dos_register.h:4835
#define P_HEVC_REC_CANVAS_ADDR 		DOS_REG_ADDR(HEVC_REC_CANVAS_ADDR)
#define HEVC_CURR_CANVAS_CTRL 0x39b3 	///../ucode/dos_register.h:4838
#define P_HEVC_CURR_CANVAS_CTRL 		DOS_REG_ADDR(HEVC_CURR_CANVAS_CTRL)
#define HEVC_MDEC_PIC_DC_THRESH 0x39b8 	///../ucode/dos_register.h:4839
#define P_HEVC_MDEC_PIC_DC_THRESH 		DOS_REG_ADDR(HEVC_MDEC_PIC_DC_THRESH)
#define HEVC_MDEC_PICR_BUF_STATUS 0x39b9 	///../ucode/dos_register.h:4840
#define P_HEVC_MDEC_PICR_BUF_STATUS 		DOS_REG_ADDR(HEVC_MDEC_PICR_BUF_STATUS)
#define HEVC_MDEC_PICW_BUF_STATUS 0x39ba 	///../ucode/dos_register.h:4841
#define P_HEVC_MDEC_PICW_BUF_STATUS 		DOS_REG_ADDR(HEVC_MDEC_PICW_BUF_STATUS)
#define HEVC_MCW_DBLK_WRRSP_CNT 0x39bb 	///../ucode/dos_register.h:4842
#define P_HEVC_MCW_DBLK_WRRSP_CNT 		DOS_REG_ADDR(HEVC_MCW_DBLK_WRRSP_CNT)
#define HEVC_MC_MBBOT_WRRSP_CNT 0x39bc 	///../ucode/dos_register.h:4843
#define P_HEVC_MC_MBBOT_WRRSP_CNT 		DOS_REG_ADDR(HEVC_MC_MBBOT_WRRSP_CNT)
#define HEVC_MDEC_PICW_BUF2_STATUS 0x39bd 	///../ucode/dos_register.h:4844
#define P_HEVC_MDEC_PICW_BUF2_STATUS 		DOS_REG_ADDR(HEVC_MDEC_PICW_BUF2_STATUS)
#define HEVC_WRRSP_FIFO_PICW_DBK 0x39be 	///../ucode/dos_register.h:4845
#define P_HEVC_WRRSP_FIFO_PICW_DBK 		DOS_REG_ADDR(HEVC_WRRSP_FIFO_PICW_DBK)
#define HEVC_WRRSP_FIFO_PICW_MC 0x39bf 	///../ucode/dos_register.h:4846
#define P_HEVC_WRRSP_FIFO_PICW_MC 		DOS_REG_ADDR(HEVC_WRRSP_FIFO_PICW_MC)
#define HEVC_AV_SCRATCH_0 0x39c0 	///../ucode/dos_register.h:4847
#define P_HEVC_AV_SCRATCH_0 		DOS_REG_ADDR(HEVC_AV_SCRATCH_0)
#define HEVC_AV_SCRATCH_1 0x39c1 	///../ucode/dos_register.h:4848
#define P_HEVC_AV_SCRATCH_1 		DOS_REG_ADDR(HEVC_AV_SCRATCH_1)
#define HEVC_AV_SCRATCH_2 0x39c2 	///../ucode/dos_register.h:4849
#define P_HEVC_AV_SCRATCH_2 		DOS_REG_ADDR(HEVC_AV_SCRATCH_2)
#define HEVC_AV_SCRATCH_3 0x39c3 	///../ucode/dos_register.h:4850
#define P_HEVC_AV_SCRATCH_3 		DOS_REG_ADDR(HEVC_AV_SCRATCH_3)
#define HEVC_AV_SCRATCH_4 0x39c4 	///../ucode/dos_register.h:4851
#define P_HEVC_AV_SCRATCH_4 		DOS_REG_ADDR(HEVC_AV_SCRATCH_4)
#define HEVC_AV_SCRATCH_5 0x39c5 	///../ucode/dos_register.h:4852
#define P_HEVC_AV_SCRATCH_5 		DOS_REG_ADDR(HEVC_AV_SCRATCH_5)
#define HEVC_AV_SCRATCH_6 0x39c6 	///../ucode/dos_register.h:4853
#define P_HEVC_AV_SCRATCH_6 		DOS_REG_ADDR(HEVC_AV_SCRATCH_6)
#define HEVC_AV_SCRATCH_7 0x39c7 	///../ucode/dos_register.h:4854
#define P_HEVC_AV_SCRATCH_7 		DOS_REG_ADDR(HEVC_AV_SCRATCH_7)
#define HEVC_AV_SCRATCH_8 0x39c8 	///../ucode/dos_register.h:4855
#define P_HEVC_AV_SCRATCH_8 		DOS_REG_ADDR(HEVC_AV_SCRATCH_8)
#define HEVC_AV_SCRATCH_9 0x39c9 	///../ucode/dos_register.h:4856
#define P_HEVC_AV_SCRATCH_9 		DOS_REG_ADDR(HEVC_AV_SCRATCH_9)
#define HEVC_AV_SCRATCH_A 0x39ca 	///../ucode/dos_register.h:4857
#define P_HEVC_AV_SCRATCH_A 		DOS_REG_ADDR(HEVC_AV_SCRATCH_A)
#define HEVC_AV_SCRATCH_B 0x39cb 	///../ucode/dos_register.h:4858
#define P_HEVC_AV_SCRATCH_B 		DOS_REG_ADDR(HEVC_AV_SCRATCH_B)
#define HEVC_AV_SCRATCH_C 0x39cc 	///../ucode/dos_register.h:4859
#define P_HEVC_AV_SCRATCH_C 		DOS_REG_ADDR(HEVC_AV_SCRATCH_C)
#define HEVC_AV_SCRATCH_D 0x39cd 	///../ucode/dos_register.h:4860
#define P_HEVC_AV_SCRATCH_D 		DOS_REG_ADDR(HEVC_AV_SCRATCH_D)
#define HEVC_AV_SCRATCH_E 0x39ce 	///../ucode/dos_register.h:4861
#define P_HEVC_AV_SCRATCH_E 		DOS_REG_ADDR(HEVC_AV_SCRATCH_E)
#define HEVC_AV_SCRATCH_F 0x39cf 	///../ucode/dos_register.h:4862
#define P_HEVC_AV_SCRATCH_F 		DOS_REG_ADDR(HEVC_AV_SCRATCH_F)
#define HEVC_AV_SCRATCH_G 0x39d0 	///../ucode/dos_register.h:4863
#define P_HEVC_AV_SCRATCH_G 		DOS_REG_ADDR(HEVC_AV_SCRATCH_G)
#define HEVC_AV_SCRATCH_H 0x39d1 	///../ucode/dos_register.h:4864
#define P_HEVC_AV_SCRATCH_H 		DOS_REG_ADDR(HEVC_AV_SCRATCH_H)
#define HEVC_AV_SCRATCH_I 0x39d2 	///../ucode/dos_register.h:4865
#define P_HEVC_AV_SCRATCH_I 		DOS_REG_ADDR(HEVC_AV_SCRATCH_I)
#define HEVC_AV_SCRATCH_J 0x39d3 	///../ucode/dos_register.h:4866
#define P_HEVC_AV_SCRATCH_J 		DOS_REG_ADDR(HEVC_AV_SCRATCH_J)
#define HEVC_AV_SCRATCH_K 0x39d4 	///../ucode/dos_register.h:4867
#define P_HEVC_AV_SCRATCH_K 		DOS_REG_ADDR(HEVC_AV_SCRATCH_K)
#define HEVC_AV_SCRATCH_L 0x39d5 	///../ucode/dos_register.h:4868
#define P_HEVC_AV_SCRATCH_L 		DOS_REG_ADDR(HEVC_AV_SCRATCH_L)
#define HEVC_AV_SCRATCH_M 0x39d6 	///../ucode/dos_register.h:4869
#define P_HEVC_AV_SCRATCH_M 		DOS_REG_ADDR(HEVC_AV_SCRATCH_M)
#define HEVC_AV_SCRATCH_N 0x39d7 	///../ucode/dos_register.h:4870
#define P_HEVC_AV_SCRATCH_N 		DOS_REG_ADDR(HEVC_AV_SCRATCH_N)
#define HEVC_WRRSP_CO_MB 0x39d8 	///../ucode/dos_register.h:4874
#define P_HEVC_WRRSP_CO_MB 		DOS_REG_ADDR(HEVC_WRRSP_CO_MB)
#define HEVC_WRRSP_DCAC 0x39d9 	///../ucode/dos_register.h:4878
#define P_HEVC_WRRSP_DCAC 		DOS_REG_ADDR(HEVC_WRRSP_DCAC)
#define HEVC_WRRSP_VLD 0x39da 	///../ucode/dos_register.h:4880
#define P_HEVC_WRRSP_VLD 		DOS_REG_ADDR(HEVC_WRRSP_VLD)
#define HEVC_MDEC_DOUBLEW_CFG0 0x39db 	///../ucode/dos_register.h:4896
#define P_HEVC_MDEC_DOUBLEW_CFG0 		DOS_REG_ADDR(HEVC_MDEC_DOUBLEW_CFG0)
#define HEVC_MDEC_DOUBLEW_CFG1 0x39dc 	///../ucode/dos_register.h:4902
#define P_HEVC_MDEC_DOUBLEW_CFG1 		DOS_REG_ADDR(HEVC_MDEC_DOUBLEW_CFG1)
#define HEVC_MDEC_DOUBLEW_CFG2 0x39dd 	///../ucode/dos_register.h:4907
#define P_HEVC_MDEC_DOUBLEW_CFG2 		DOS_REG_ADDR(HEVC_MDEC_DOUBLEW_CFG2)
#define HEVC_MDEC_DOUBLEW_CFG3 0x39de 	///../ucode/dos_register.h:4909
#define P_HEVC_MDEC_DOUBLEW_CFG3 		DOS_REG_ADDR(HEVC_MDEC_DOUBLEW_CFG3)
#define HEVC_MDEC_DOUBLEW_CFG4 0x39df 	///../ucode/dos_register.h:4911
#define P_HEVC_MDEC_DOUBLEW_CFG4 		DOS_REG_ADDR(HEVC_MDEC_DOUBLEW_CFG4)
#define HEVC_MDEC_DOUBLEW_CFG5 0x39e0 	///../ucode/dos_register.h:4914
#define P_HEVC_MDEC_DOUBLEW_CFG5 		DOS_REG_ADDR(HEVC_MDEC_DOUBLEW_CFG5)
#define HEVC_MDEC_DOUBLEW_CFG6 0x39e1 	///../ucode/dos_register.h:4916
#define P_HEVC_MDEC_DOUBLEW_CFG6 		DOS_REG_ADDR(HEVC_MDEC_DOUBLEW_CFG6)
#define HEVC_MDEC_DOUBLEW_CFG7 0x39e2 	///../ucode/dos_register.h:4918
#define P_HEVC_MDEC_DOUBLEW_CFG7 		DOS_REG_ADDR(HEVC_MDEC_DOUBLEW_CFG7)
#define HEVC_MDEC_DOUBLEW_STATUS 0x39e3 	///../ucode/dos_register.h:4922
#define P_HEVC_MDEC_DOUBLEW_STATUS 		DOS_REG_ADDR(HEVC_MDEC_DOUBLEW_STATUS)
#define HEVC_DBLK_RST 0x3950 	///../ucode/dos_register.h:4940
#define P_HEVC_DBLK_RST 		DOS_REG_ADDR(HEVC_DBLK_RST)
#define HEVC_DBLK_CTRL 0x3951 	///../ucode/dos_register.h:4941
#define P_HEVC_DBLK_CTRL 		DOS_REG_ADDR(HEVC_DBLK_CTRL)
#define HEVC_DBLK_MB_WID_HEIGHT 0x3952 	///../ucode/dos_register.h:4942
#define P_HEVC_DBLK_MB_WID_HEIGHT 		DOS_REG_ADDR(HEVC_DBLK_MB_WID_HEIGHT)
#define HEVC_DBLK_STATUS 0x3953 	///../ucode/dos_register.h:4943
#define P_HEVC_DBLK_STATUS 		DOS_REG_ADDR(HEVC_DBLK_STATUS)
#define HEVC_DBLK_CMD_CTRL 0x3954 	///../ucode/dos_register.h:4944
#define P_HEVC_DBLK_CMD_CTRL 		DOS_REG_ADDR(HEVC_DBLK_CMD_CTRL)
#define HEVC_DBLK_MB_XY 0x3955 	///../ucode/dos_register.h:4945
#define P_HEVC_DBLK_MB_XY 		DOS_REG_ADDR(HEVC_DBLK_MB_XY)
#define HEVC_DBLK_QP 0x3956 	///../ucode/dos_register.h:4946
#define P_HEVC_DBLK_QP 		DOS_REG_ADDR(HEVC_DBLK_QP)
#define HEVC_DBLK_Y_BHFILT 0x3957 	///../ucode/dos_register.h:4947
#define P_HEVC_DBLK_Y_BHFILT 		DOS_REG_ADDR(HEVC_DBLK_Y_BHFILT)
#define HEVC_DBLK_Y_BHFILT_HIGH 0x3958 	///../ucode/dos_register.h:4948
#define P_HEVC_DBLK_Y_BHFILT_HIGH 		DOS_REG_ADDR(HEVC_DBLK_Y_BHFILT_HIGH)
#define HEVC_DBLK_Y_BVFILT 0x3959 	///../ucode/dos_register.h:4949
#define P_HEVC_DBLK_Y_BVFILT 		DOS_REG_ADDR(HEVC_DBLK_Y_BVFILT)
#define HEVC_DBLK_CB_BFILT 0x395a 	///../ucode/dos_register.h:4950
#define P_HEVC_DBLK_CB_BFILT 		DOS_REG_ADDR(HEVC_DBLK_CB_BFILT)
#define HEVC_DBLK_CR_BFILT 0x395b 	///../ucode/dos_register.h:4951
#define P_HEVC_DBLK_CR_BFILT 		DOS_REG_ADDR(HEVC_DBLK_CR_BFILT)
#define HEVC_DBLK_Y_HFILT 0x395c 	///../ucode/dos_register.h:4952
#define P_HEVC_DBLK_Y_HFILT 		DOS_REG_ADDR(HEVC_DBLK_Y_HFILT)
#define HEVC_DBLK_Y_HFILT_HIGH 0x395d 	///../ucode/dos_register.h:4953
#define P_HEVC_DBLK_Y_HFILT_HIGH 		DOS_REG_ADDR(HEVC_DBLK_Y_HFILT_HIGH)
#define HEVC_DBLK_Y_VFILT 0x395e 	///../ucode/dos_register.h:4954
#define P_HEVC_DBLK_Y_VFILT 		DOS_REG_ADDR(HEVC_DBLK_Y_VFILT)
#define HEVC_DBLK_CB_FILT 0x395f 	///../ucode/dos_register.h:4955
#define P_HEVC_DBLK_CB_FILT 		DOS_REG_ADDR(HEVC_DBLK_CB_FILT)
#define HEVC_DBLK_CR_FILT 0x3960 	///../ucode/dos_register.h:4956
#define P_HEVC_DBLK_CR_FILT 		DOS_REG_ADDR(HEVC_DBLK_CR_FILT)
#define HEVC_DBLK_BETAX_QP_SEL 0x3961 	///../ucode/dos_register.h:4957
#define P_HEVC_DBLK_BETAX_QP_SEL 		DOS_REG_ADDR(HEVC_DBLK_BETAX_QP_SEL)
#define HEVC_DBLK_CLIP_CTRL0 0x3962 	///../ucode/dos_register.h:4958
#define P_HEVC_DBLK_CLIP_CTRL0 		DOS_REG_ADDR(HEVC_DBLK_CLIP_CTRL0)
#define HEVC_DBLK_CLIP_CTRL1 0x3963 	///../ucode/dos_register.h:4959
#define P_HEVC_DBLK_CLIP_CTRL1 		DOS_REG_ADDR(HEVC_DBLK_CLIP_CTRL1)
#define HEVC_DBLK_CLIP_CTRL2 0x3964 	///../ucode/dos_register.h:4960
#define P_HEVC_DBLK_CLIP_CTRL2 		DOS_REG_ADDR(HEVC_DBLK_CLIP_CTRL2)
#define HEVC_DBLK_CLIP_CTRL3 0x3965 	///../ucode/dos_register.h:4961
#define P_HEVC_DBLK_CLIP_CTRL3 		DOS_REG_ADDR(HEVC_DBLK_CLIP_CTRL3)
#define HEVC_DBLK_CLIP_CTRL4 0x3966 	///../ucode/dos_register.h:4962
#define P_HEVC_DBLK_CLIP_CTRL4 		DOS_REG_ADDR(HEVC_DBLK_CLIP_CTRL4)
#define HEVC_DBLK_CLIP_CTRL5 0x3967 	///../ucode/dos_register.h:4963
#define P_HEVC_DBLK_CLIP_CTRL5 		DOS_REG_ADDR(HEVC_DBLK_CLIP_CTRL5)
#define HEVC_DBLK_CLIP_CTRL6 0x3968 	///../ucode/dos_register.h:4964
#define P_HEVC_DBLK_CLIP_CTRL6 		DOS_REG_ADDR(HEVC_DBLK_CLIP_CTRL6)
#define HEVC_DBLK_CLIP_CTRL7 0x3969 	///../ucode/dos_register.h:4965
#define P_HEVC_DBLK_CLIP_CTRL7 		DOS_REG_ADDR(HEVC_DBLK_CLIP_CTRL7)
#define HEVC_DBLK_CLIP_CTRL8 0x396a 	///../ucode/dos_register.h:4966
#define P_HEVC_DBLK_CLIP_CTRL8 		DOS_REG_ADDR(HEVC_DBLK_CLIP_CTRL8)
#define HEVC_DBLK_STATUS1 0x396b 	///../ucode/dos_register.h:4967
#define P_HEVC_DBLK_STATUS1 		DOS_REG_ADDR(HEVC_DBLK_STATUS1)
#define HEVC_DBLK_GCLK_FREE 0x396c 	///../ucode/dos_register.h:4968
#define P_HEVC_DBLK_GCLK_FREE 		DOS_REG_ADDR(HEVC_DBLK_GCLK_FREE)
#define HEVC_DBLK_GCLK_OFF 0x396d 	///../ucode/dos_register.h:4969
#define P_HEVC_DBLK_GCLK_OFF 		DOS_REG_ADDR(HEVC_DBLK_GCLK_OFF)
#define HEVC_DBLK_AVSFLAGS 0x396e 	///../ucode/dos_register.h:4970
#define P_HEVC_DBLK_AVSFLAGS 		DOS_REG_ADDR(HEVC_DBLK_AVSFLAGS)
#define HEVC_DBLK_CBPY 0x3970 	///../ucode/dos_register.h:4972
#define P_HEVC_DBLK_CBPY 		DOS_REG_ADDR(HEVC_DBLK_CBPY)
#define HEVC_DBLK_CBPY_ADJ 0x3971 	///../ucode/dos_register.h:4976
#define P_HEVC_DBLK_CBPY_ADJ 		DOS_REG_ADDR(HEVC_DBLK_CBPY_ADJ)
#define HEVC_DBLK_CBPC 0x3972 	///../ucode/dos_register.h:4978
#define P_HEVC_DBLK_CBPC 		DOS_REG_ADDR(HEVC_DBLK_CBPC)
#define HEVC_DBLK_CBPC_ADJ 0x3973 	///../ucode/dos_register.h:4986
#define P_HEVC_DBLK_CBPC_ADJ 		DOS_REG_ADDR(HEVC_DBLK_CBPC_ADJ)
#define HEVC_DBLK_VHMVD 0x3974 	///../ucode/dos_register.h:4989
#define P_HEVC_DBLK_VHMVD 		DOS_REG_ADDR(HEVC_DBLK_VHMVD)
#define HEVC_DBLK_STRONG 0x3975 	///../ucode/dos_register.h:5003
#define P_HEVC_DBLK_STRONG 		DOS_REG_ADDR(HEVC_DBLK_STRONG)
#define HEVC_DBLK_RV8_QUANT 0x3976 	///../ucode/dos_register.h:5007
#define P_HEVC_DBLK_RV8_QUANT 		DOS_REG_ADDR(HEVC_DBLK_RV8_QUANT)
#define HEVC_DBLK_CBUS_HCMD2 0x3977 	///../ucode/dos_register.h:5008
#define P_HEVC_DBLK_CBUS_HCMD2 		DOS_REG_ADDR(HEVC_DBLK_CBUS_HCMD2)
#define HEVC_DBLK_CBUS_HCMD1 0x3978 	///../ucode/dos_register.h:5009
#define P_HEVC_DBLK_CBUS_HCMD1 		DOS_REG_ADDR(HEVC_DBLK_CBUS_HCMD1)
#define HEVC_DBLK_CBUS_HCMD0 0x3979 	///../ucode/dos_register.h:5010
#define P_HEVC_DBLK_CBUS_HCMD0 		DOS_REG_ADDR(HEVC_DBLK_CBUS_HCMD0)
#define HEVC_DBLK_VLD_HCMD2 0x397a 	///../ucode/dos_register.h:5011
#define P_HEVC_DBLK_VLD_HCMD2 		DOS_REG_ADDR(HEVC_DBLK_VLD_HCMD2)
#define HEVC_DBLK_VLD_HCMD1 0x397b 	///../ucode/dos_register.h:5012
#define P_HEVC_DBLK_VLD_HCMD1 		DOS_REG_ADDR(HEVC_DBLK_VLD_HCMD1)
#define HEVC_DBLK_VLD_HCMD0 0x397c 	///../ucode/dos_register.h:5013
#define P_HEVC_DBLK_VLD_HCMD0 		DOS_REG_ADDR(HEVC_DBLK_VLD_HCMD0)
#define HEVC_DBLK_OST_YBASE 0x397d 	///../ucode/dos_register.h:5014
#define P_HEVC_DBLK_OST_YBASE 		DOS_REG_ADDR(HEVC_DBLK_OST_YBASE)
#define HEVC_DBLK_OST_CBCRDIFF 0x397e 	///../ucode/dos_register.h:5015
#define P_HEVC_DBLK_OST_CBCRDIFF 		DOS_REG_ADDR(HEVC_DBLK_OST_CBCRDIFF)
#define HEVC_DBLK_CTRL1 0x397f 	///../ucode/dos_register.h:5018
#define P_HEVC_DBLK_CTRL1 		DOS_REG_ADDR(HEVC_DBLK_CTRL1)
#define HEVC_MCRCC_CTL1 0x3980 	///../ucode/dos_register.h:5024
#define P_HEVC_MCRCC_CTL1 		DOS_REG_ADDR(HEVC_MCRCC_CTL1)
#define HEVC_MCRCC_CTL2 0x3981 	///../ucode/dos_register.h:5030
#define P_HEVC_MCRCC_CTL2 		DOS_REG_ADDR(HEVC_MCRCC_CTL2)
#define HEVC_MCRCC_CTL3 0x3982 	///../ucode/dos_register.h:5036
#define P_HEVC_MCRCC_CTL3 		DOS_REG_ADDR(HEVC_MCRCC_CTL3)
#define HEVC_GCLK_EN 0x3983 	///../ucode/dos_register.h:5049
#define P_HEVC_GCLK_EN 		DOS_REG_ADDR(HEVC_GCLK_EN)
#define HEVC_MDEC_SW_RESET 0x3984 	///../ucode/dos_register.h:5064
#define P_HEVC_MDEC_SW_RESET 		DOS_REG_ADDR(HEVC_MDEC_SW_RESET)
#define HCODEC_VLD_STATUS_CTRL 0x1c00 	///../ucode/dos_register.h:5078
#define P_HCODEC_VLD_STATUS_CTRL 		DOS_REG_ADDR(HCODEC_VLD_STATUS_CTRL)
#define HCODEC_MPEG1_2_REG 0x1c01 	///../ucode/dos_register.h:5088
#define P_HCODEC_MPEG1_2_REG 		DOS_REG_ADDR(HCODEC_MPEG1_2_REG)
#define HCODEC_F_CODE_REG 0x1c02 	///../ucode/dos_register.h:5089
#define P_HCODEC_F_CODE_REG 		DOS_REG_ADDR(HCODEC_F_CODE_REG)
#define HCODEC_PIC_HEAD_INFO 0x1c03 	///../ucode/dos_register.h:5090
#define P_HCODEC_PIC_HEAD_INFO 		DOS_REG_ADDR(HCODEC_PIC_HEAD_INFO)
#define HCODEC_SLICE_VER_POS_PIC_TYPE 0x1c04 	///../ucode/dos_register.h:5091
#define P_HCODEC_SLICE_VER_POS_PIC_TYPE 		DOS_REG_ADDR(HCODEC_SLICE_VER_POS_PIC_TYPE)
#define HCODEC_QP_VALUE_REG 0x1c05 	///../ucode/dos_register.h:5092
#define P_HCODEC_QP_VALUE_REG 		DOS_REG_ADDR(HCODEC_QP_VALUE_REG)
#define HCODEC_MBA_INC 0x1c06 	///../ucode/dos_register.h:5093
#define P_HCODEC_MBA_INC 		DOS_REG_ADDR(HCODEC_MBA_INC)
#define HCODEC_MB_MOTION_MODE 0x1c07 	///../ucode/dos_register.h:5094
#define P_HCODEC_MB_MOTION_MODE 		DOS_REG_ADDR(HCODEC_MB_MOTION_MODE)
#define HCODEC_POWER_CTL_VLD 0x1c08 	///../ucode/dos_register.h:5102
#define P_HCODEC_POWER_CTL_VLD 		DOS_REG_ADDR(HCODEC_POWER_CTL_VLD)
#define HCODEC_MB_WIDTH 0x1c09 	///../ucode/dos_register.h:5103
#define P_HCODEC_MB_WIDTH 		DOS_REG_ADDR(HCODEC_MB_WIDTH)
#define HCODEC_SLICE_QP 0x1c0a 	///../ucode/dos_register.h:5104
#define P_HCODEC_SLICE_QP 		DOS_REG_ADDR(HCODEC_SLICE_QP)
#define HCODEC_PRE_START_CODE 0x1c0b 	///../ucode/dos_register.h:5106
#define P_HCODEC_PRE_START_CODE 		DOS_REG_ADDR(HCODEC_PRE_START_CODE)
#define HCODEC_SLICE_START_BYTE_01 0x1c0c 	///../ucode/dos_register.h:5107
#define P_HCODEC_SLICE_START_BYTE_01 		DOS_REG_ADDR(HCODEC_SLICE_START_BYTE_01)
#define HCODEC_SLICE_START_BYTE_23 0x1c0d 	///../ucode/dos_register.h:5108
#define P_HCODEC_SLICE_START_BYTE_23 		DOS_REG_ADDR(HCODEC_SLICE_START_BYTE_23)
#define HCODEC_RESYNC_MARKER_LENGTH 0x1c0e 	///../ucode/dos_register.h:5109
#define P_HCODEC_RESYNC_MARKER_LENGTH 		DOS_REG_ADDR(HCODEC_RESYNC_MARKER_LENGTH)
#define HCODEC_DECODER_BUFFER_INFO 0x1c0f 	///../ucode/dos_register.h:5113
#define P_HCODEC_DECODER_BUFFER_INFO 		DOS_REG_ADDR(HCODEC_DECODER_BUFFER_INFO)
#define HCODEC_FST_FOR_MV_X 0x1c10 	///../ucode/dos_register.h:5114
#define P_HCODEC_FST_FOR_MV_X 		DOS_REG_ADDR(HCODEC_FST_FOR_MV_X)
#define HCODEC_FST_FOR_MV_Y 0x1c11 	///../ucode/dos_register.h:5115
#define P_HCODEC_FST_FOR_MV_Y 		DOS_REG_ADDR(HCODEC_FST_FOR_MV_Y)
#define HCODEC_SCD_FOR_MV_X 0x1c12 	///../ucode/dos_register.h:5116
#define P_HCODEC_SCD_FOR_MV_X 		DOS_REG_ADDR(HCODEC_SCD_FOR_MV_X)
#define HCODEC_SCD_FOR_MV_Y 0x1c13 	///../ucode/dos_register.h:5117
#define P_HCODEC_SCD_FOR_MV_Y 		DOS_REG_ADDR(HCODEC_SCD_FOR_MV_Y)
#define HCODEC_FST_BAK_MV_X 0x1c14 	///../ucode/dos_register.h:5118
#define P_HCODEC_FST_BAK_MV_X 		DOS_REG_ADDR(HCODEC_FST_BAK_MV_X)
#define HCODEC_FST_BAK_MV_Y 0x1c15 	///../ucode/dos_register.h:5119
#define P_HCODEC_FST_BAK_MV_Y 		DOS_REG_ADDR(HCODEC_FST_BAK_MV_Y)
#define HCODEC_SCD_BAK_MV_X 0x1c16 	///../ucode/dos_register.h:5120
#define P_HCODEC_SCD_BAK_MV_X 		DOS_REG_ADDR(HCODEC_SCD_BAK_MV_X)
#define HCODEC_SCD_BAK_MV_Y 0x1c17 	///../ucode/dos_register.h:5121
#define P_HCODEC_SCD_BAK_MV_Y 		DOS_REG_ADDR(HCODEC_SCD_BAK_MV_Y)
#define HCODEC_VLD_DECODE_CONTROL 0x1c18 	///../ucode/dos_register.h:5127
#define P_HCODEC_VLD_DECODE_CONTROL 		DOS_REG_ADDR(HCODEC_VLD_DECODE_CONTROL)
#define HCODEC_VLD_REVERVED_19 0x1c19 	///../ucode/dos_register.h:5128
#define P_HCODEC_VLD_REVERVED_19 		DOS_REG_ADDR(HCODEC_VLD_REVERVED_19)
#define HCODEC_VIFF_BIT_CNT 0x1c1a 	///../ucode/dos_register.h:5129
#define P_HCODEC_VIFF_BIT_CNT 		DOS_REG_ADDR(HCODEC_VIFF_BIT_CNT)
#define HCODEC_BYTE_ALIGN_PEAK_HI 0x1c1b 	///../ucode/dos_register.h:5130
#define P_HCODEC_BYTE_ALIGN_PEAK_HI 		DOS_REG_ADDR(HCODEC_BYTE_ALIGN_PEAK_HI)
#define HCODEC_BYTE_ALIGN_PEAK_LO 0x1c1c 	///../ucode/dos_register.h:5131
#define P_HCODEC_BYTE_ALIGN_PEAK_LO 		DOS_REG_ADDR(HCODEC_BYTE_ALIGN_PEAK_LO)
#define HCODEC_NEXT_ALIGN_PEAK 0x1c1d 	///../ucode/dos_register.h:5132
#define P_HCODEC_NEXT_ALIGN_PEAK 		DOS_REG_ADDR(HCODEC_NEXT_ALIGN_PEAK)
#define HCODEC_VC1_CONTROL_REG 0x1c1e 	///../ucode/dos_register.h:5148
#define P_HCODEC_VC1_CONTROL_REG 		DOS_REG_ADDR(HCODEC_VC1_CONTROL_REG)
#define HCODEC_PMV1_X 0x1c20 	///../ucode/dos_register.h:5149
#define P_HCODEC_PMV1_X 		DOS_REG_ADDR(HCODEC_PMV1_X)
#define HCODEC_PMV1_Y 0x1c21 	///../ucode/dos_register.h:5150
#define P_HCODEC_PMV1_Y 		DOS_REG_ADDR(HCODEC_PMV1_Y)
#define HCODEC_PMV2_X 0x1c22 	///../ucode/dos_register.h:5151
#define P_HCODEC_PMV2_X 		DOS_REG_ADDR(HCODEC_PMV2_X)
#define HCODEC_PMV2_Y 0x1c23 	///../ucode/dos_register.h:5152
#define P_HCODEC_PMV2_Y 		DOS_REG_ADDR(HCODEC_PMV2_Y)
#define HCODEC_PMV3_X 0x1c24 	///../ucode/dos_register.h:5153
#define P_HCODEC_PMV3_X 		DOS_REG_ADDR(HCODEC_PMV3_X)
#define HCODEC_PMV3_Y 0x1c25 	///../ucode/dos_register.h:5154
#define P_HCODEC_PMV3_Y 		DOS_REG_ADDR(HCODEC_PMV3_Y)
#define HCODEC_PMV4_X 0x1c26 	///../ucode/dos_register.h:5155
#define P_HCODEC_PMV4_X 		DOS_REG_ADDR(HCODEC_PMV4_X)
#define HCODEC_PMV4_Y 0x1c27 	///../ucode/dos_register.h:5156
#define P_HCODEC_PMV4_Y 		DOS_REG_ADDR(HCODEC_PMV4_Y)
#define HCODEC_M4_TABLE_SELECT 0x1c28 	///../ucode/dos_register.h:5163
#define P_HCODEC_M4_TABLE_SELECT 		DOS_REG_ADDR(HCODEC_M4_TABLE_SELECT)
#define HCODEC_M4_CONTROL_REG 0x1c29 	///../ucode/dos_register.h:5164
#define P_HCODEC_M4_CONTROL_REG 		DOS_REG_ADDR(HCODEC_M4_CONTROL_REG)
#define HCODEC_BLOCK_NUM 0x1c2a 	///../ucode/dos_register.h:5165
#define P_HCODEC_BLOCK_NUM 		DOS_REG_ADDR(HCODEC_BLOCK_NUM)
#define HCODEC_PATTERN_CODE 0x1c2b 	///../ucode/dos_register.h:5166
#define P_HCODEC_PATTERN_CODE 		DOS_REG_ADDR(HCODEC_PATTERN_CODE)
#define HCODEC_MB_INFO 0x1c2c 	///../ucode/dos_register.h:5167
#define P_HCODEC_MB_INFO 		DOS_REG_ADDR(HCODEC_MB_INFO)
#define HCODEC_VLD_DC_PRED 0x1c2d 	///../ucode/dos_register.h:5168
#define P_HCODEC_VLD_DC_PRED 		DOS_REG_ADDR(HCODEC_VLD_DC_PRED)
#define HCODEC_VLD_ERROR_MASK 0x1c2e 	///../ucode/dos_register.h:5169
#define P_HCODEC_VLD_ERROR_MASK 		DOS_REG_ADDR(HCODEC_VLD_ERROR_MASK)
#define HCODEC_VLD_DC_PRED_C 0x1c2f 	///../ucode/dos_register.h:5170
#define P_HCODEC_VLD_DC_PRED_C 		DOS_REG_ADDR(HCODEC_VLD_DC_PRED_C)
#define HCODEC_LAST_SLICE_MV_ADDR 0x1c30 	///../ucode/dos_register.h:5171
#define P_HCODEC_LAST_SLICE_MV_ADDR 		DOS_REG_ADDR(HCODEC_LAST_SLICE_MV_ADDR)
#define HCODEC_LAST_MVX 0x1c31 	///../ucode/dos_register.h:5172
#define P_HCODEC_LAST_MVX 		DOS_REG_ADDR(HCODEC_LAST_MVX)
#define HCODEC_LAST_MVY 0x1c32 	///../ucode/dos_register.h:5173
#define P_HCODEC_LAST_MVY 		DOS_REG_ADDR(HCODEC_LAST_MVY)
#define HCODEC_VLD_C38 0x1c38 	///../ucode/dos_register.h:5174
#define P_HCODEC_VLD_C38 		DOS_REG_ADDR(HCODEC_VLD_C38)
#define HCODEC_VLD_C39 0x1c39 	///../ucode/dos_register.h:5175
#define P_HCODEC_VLD_C39 		DOS_REG_ADDR(HCODEC_VLD_C39)
#define HCODEC_VLD_STATUS 0x1c3a 	///../ucode/dos_register.h:5176
#define P_HCODEC_VLD_STATUS 		DOS_REG_ADDR(HCODEC_VLD_STATUS)
#define HCODEC_VLD_SHIFT_STATUS 0x1c3b 	///../ucode/dos_register.h:5177
#define P_HCODEC_VLD_SHIFT_STATUS 		DOS_REG_ADDR(HCODEC_VLD_SHIFT_STATUS)
#define HCODEC_VOFF_STATUS 0x1c3c 	///../ucode/dos_register.h:5179
#define P_HCODEC_VOFF_STATUS 		DOS_REG_ADDR(HCODEC_VOFF_STATUS)
#define HCODEC_VLD_C3D 0x1c3d 	///../ucode/dos_register.h:5180
#define P_HCODEC_VLD_C3D 		DOS_REG_ADDR(HCODEC_VLD_C3D)
#define HCODEC_VLD_DBG_INDEX 0x1c3e 	///../ucode/dos_register.h:5181
#define P_HCODEC_VLD_DBG_INDEX 		DOS_REG_ADDR(HCODEC_VLD_DBG_INDEX)
#define HCODEC_VLD_DBG_DATA 0x1c3f 	///../ucode/dos_register.h:5257
#define P_HCODEC_VLD_DBG_DATA 		DOS_REG_ADDR(HCODEC_VLD_DBG_DATA)
#define HCODEC_VLD_MEM_VIFIFO_START_PTR 0x1c40 	///../ucode/dos_register.h:5264
#define P_HCODEC_VLD_MEM_VIFIFO_START_PTR 		DOS_REG_ADDR(HCODEC_VLD_MEM_VIFIFO_START_PTR)
#define HCODEC_VLD_MEM_VIFIFO_CURR_PTR 0x1c41 	///../ucode/dos_register.h:5268
#define P_HCODEC_VLD_MEM_VIFIFO_CURR_PTR 		DOS_REG_ADDR(HCODEC_VLD_MEM_VIFIFO_CURR_PTR)
#define HCODEC_VLD_MEM_VIFIFO_END_PTR 0x1c42 	///../ucode/dos_register.h:5269
#define P_HCODEC_VLD_MEM_VIFIFO_END_PTR 		DOS_REG_ADDR(HCODEC_VLD_MEM_VIFIFO_END_PTR)
#define HCODEC_VLD_MEM_VIFIFO_BYTES_AVAIL 0x1c43 	///../ucode/dos_register.h:5270
#define P_HCODEC_VLD_MEM_VIFIFO_BYTES_AVAIL 		DOS_REG_ADDR(HCODEC_VLD_MEM_VIFIFO_BYTES_AVAIL)
#define HCODEC_VLD_MEM_VIFIFO_CONTROL 0x1c44 	///../ucode/dos_register.h:5301
#define P_HCODEC_VLD_MEM_VIFIFO_CONTROL 		DOS_REG_ADDR(HCODEC_VLD_MEM_VIFIFO_CONTROL)
#define HCODEC_VLD_MEM_VIFIFO_WP 0x1c45 	///../ucode/dos_register.h:5305
#define P_HCODEC_VLD_MEM_VIFIFO_WP 		DOS_REG_ADDR(HCODEC_VLD_MEM_VIFIFO_WP)
#define HCODEC_VLD_MEM_VIFIFO_RP 0x1c46 	///../ucode/dos_register.h:5306
#define P_HCODEC_VLD_MEM_VIFIFO_RP 		DOS_REG_ADDR(HCODEC_VLD_MEM_VIFIFO_RP)
#define HCODEC_VLD_MEM_VIFIFO_LEVEL 0x1c47 	///../ucode/dos_register.h:5307
#define P_HCODEC_VLD_MEM_VIFIFO_LEVEL 		DOS_REG_ADDR(HCODEC_VLD_MEM_VIFIFO_LEVEL)
#define HCODEC_VLD_MEM_VIFIFO_BUF_CNTL 0x1c48 	///../ucode/dos_register.h:5317
#define P_HCODEC_VLD_MEM_VIFIFO_BUF_CNTL 		DOS_REG_ADDR(HCODEC_VLD_MEM_VIFIFO_BUF_CNTL)
#define HCODEC_VLD_TIME_STAMP_CNTL 0x1c49 	///../ucode/dos_register.h:5327
#define P_HCODEC_VLD_TIME_STAMP_CNTL 		DOS_REG_ADDR(HCODEC_VLD_TIME_STAMP_CNTL)
#define HCODEC_VLD_TIME_STAMP_SYNC_0 0x1c4a 	///../ucode/dos_register.h:5329
#define P_HCODEC_VLD_TIME_STAMP_SYNC_0 		DOS_REG_ADDR(HCODEC_VLD_TIME_STAMP_SYNC_0)
#define HCODEC_VLD_TIME_STAMP_SYNC_1 0x1c4b 	///../ucode/dos_register.h:5331
#define P_HCODEC_VLD_TIME_STAMP_SYNC_1 		DOS_REG_ADDR(HCODEC_VLD_TIME_STAMP_SYNC_1)
#define HCODEC_VLD_TIME_STAMP_0 0x1c4c 	///../ucode/dos_register.h:5333
#define P_HCODEC_VLD_TIME_STAMP_0 		DOS_REG_ADDR(HCODEC_VLD_TIME_STAMP_0)
#define HCODEC_VLD_TIME_STAMP_1 0x1c4d 	///../ucode/dos_register.h:5335
#define P_HCODEC_VLD_TIME_STAMP_1 		DOS_REG_ADDR(HCODEC_VLD_TIME_STAMP_1)
#define HCODEC_VLD_TIME_STAMP_2 0x1c4e 	///../ucode/dos_register.h:5337
#define P_HCODEC_VLD_TIME_STAMP_2 		DOS_REG_ADDR(HCODEC_VLD_TIME_STAMP_2)
#define HCODEC_VLD_TIME_STAMP_3 0x1c4f 	///../ucode/dos_register.h:5339
#define P_HCODEC_VLD_TIME_STAMP_3 		DOS_REG_ADDR(HCODEC_VLD_TIME_STAMP_3)
#define HCODEC_VLD_TIME_STAMP_LENGTH 0x1c50 	///../ucode/dos_register.h:5341
#define P_HCODEC_VLD_TIME_STAMP_LENGTH 		DOS_REG_ADDR(HCODEC_VLD_TIME_STAMP_LENGTH)
#define HCODEC_VLD_MEM_VIFIFO_WRAP_COUNT 0x1c51 	///../ucode/dos_register.h:5343
#define P_HCODEC_VLD_MEM_VIFIFO_WRAP_COUNT 		DOS_REG_ADDR(HCODEC_VLD_MEM_VIFIFO_WRAP_COUNT)
#define HCODEC_VLD_MEM_VIFIFO_MEM_CTL 0x1c52 	///../ucode/dos_register.h:5347
#define P_HCODEC_VLD_MEM_VIFIFO_MEM_CTL 		DOS_REG_ADDR(HCODEC_VLD_MEM_VIFIFO_MEM_CTL)
#define HCODEC_VLD_MEM_VBUF_RD_PTR 0x1c53 	///../ucode/dos_register.h:5348
#define P_HCODEC_VLD_MEM_VBUF_RD_PTR 		DOS_REG_ADDR(HCODEC_VLD_MEM_VBUF_RD_PTR)
#define HCODEC_VLD_MEM_VBUF2_RD_PTR 0x1c54 	///../ucode/dos_register.h:5349
#define P_HCODEC_VLD_MEM_VBUF2_RD_PTR 		DOS_REG_ADDR(HCODEC_VLD_MEM_VBUF2_RD_PTR)
#define HCODEC_VLD_MEM_SWAP_ADDR 0x1c55 	///../ucode/dos_register.h:5350
#define P_HCODEC_VLD_MEM_SWAP_ADDR 		DOS_REG_ADDR(HCODEC_VLD_MEM_SWAP_ADDR)
#define HCODEC_VLD_MEM_SWAP_CTL 0x1c56 	///../ucode/dos_register.h:5357
#define P_HCODEC_VLD_MEM_SWAP_CTL 		DOS_REG_ADDR(HCODEC_VLD_MEM_SWAP_CTL)
#define VDEC2_VLD_STATUS_CTRL 0x2c00 	///../ucode/dos_register.h:5370
#define P_VDEC2_VLD_STATUS_CTRL 		DOS_REG_ADDR(VDEC2_VLD_STATUS_CTRL)
#define VDEC2_MPEG1_2_REG 0x2c01 	///../ucode/dos_register.h:5380
#define P_VDEC2_MPEG1_2_REG 		DOS_REG_ADDR(VDEC2_MPEG1_2_REG)
#define VDEC2_F_CODE_REG 0x2c02 	///../ucode/dos_register.h:5381
#define P_VDEC2_F_CODE_REG 		DOS_REG_ADDR(VDEC2_F_CODE_REG)
#define VDEC2_PIC_HEAD_INFO 0x2c03 	///../ucode/dos_register.h:5382
#define P_VDEC2_PIC_HEAD_INFO 		DOS_REG_ADDR(VDEC2_PIC_HEAD_INFO)
#define VDEC2_SLICE_VER_POS_PIC_TYPE 0x2c04 	///../ucode/dos_register.h:5383
#define P_VDEC2_SLICE_VER_POS_PIC_TYPE 		DOS_REG_ADDR(VDEC2_SLICE_VER_POS_PIC_TYPE)
#define VDEC2_QP_VALUE_REG 0x2c05 	///../ucode/dos_register.h:5384
#define P_VDEC2_QP_VALUE_REG 		DOS_REG_ADDR(VDEC2_QP_VALUE_REG)
#define VDEC2_MBA_INC 0x2c06 	///../ucode/dos_register.h:5385
#define P_VDEC2_MBA_INC 		DOS_REG_ADDR(VDEC2_MBA_INC)
#define VDEC2_MB_MOTION_MODE 0x2c07 	///../ucode/dos_register.h:5386
#define P_VDEC2_MB_MOTION_MODE 		DOS_REG_ADDR(VDEC2_MB_MOTION_MODE)
#define VDEC2_POWER_CTL_VLD 0x2c08 	///../ucode/dos_register.h:5394
#define P_VDEC2_POWER_CTL_VLD 		DOS_REG_ADDR(VDEC2_POWER_CTL_VLD)
#define VDEC2_MB_WIDTH 0x2c09 	///../ucode/dos_register.h:5395
#define P_VDEC2_MB_WIDTH 		DOS_REG_ADDR(VDEC2_MB_WIDTH)
#define VDEC2_SLICE_QP 0x2c0a 	///../ucode/dos_register.h:5396
#define P_VDEC2_SLICE_QP 		DOS_REG_ADDR(VDEC2_SLICE_QP)
#define VDEC2_PRE_START_CODE 0x2c0b 	///../ucode/dos_register.h:5398
#define P_VDEC2_PRE_START_CODE 		DOS_REG_ADDR(VDEC2_PRE_START_CODE)
#define VDEC2_SLICE_START_BYTE_01 0x2c0c 	///../ucode/dos_register.h:5399
#define P_VDEC2_SLICE_START_BYTE_01 		DOS_REG_ADDR(VDEC2_SLICE_START_BYTE_01)
#define VDEC2_SLICE_START_BYTE_23 0x2c0d 	///../ucode/dos_register.h:5400
#define P_VDEC2_SLICE_START_BYTE_23 		DOS_REG_ADDR(VDEC2_SLICE_START_BYTE_23)
#define VDEC2_RESYNC_MARKER_LENGTH 0x2c0e 	///../ucode/dos_register.h:5401
#define P_VDEC2_RESYNC_MARKER_LENGTH 		DOS_REG_ADDR(VDEC2_RESYNC_MARKER_LENGTH)
#define VDEC2_DECODER_BUFFER_INFO 0x2c0f 	///../ucode/dos_register.h:5405
#define P_VDEC2_DECODER_BUFFER_INFO 		DOS_REG_ADDR(VDEC2_DECODER_BUFFER_INFO)
#define VDEC2_FST_FOR_MV_X 0x2c10 	///../ucode/dos_register.h:5406
#define P_VDEC2_FST_FOR_MV_X 		DOS_REG_ADDR(VDEC2_FST_FOR_MV_X)
#define VDEC2_FST_FOR_MV_Y 0x2c11 	///../ucode/dos_register.h:5407
#define P_VDEC2_FST_FOR_MV_Y 		DOS_REG_ADDR(VDEC2_FST_FOR_MV_Y)
#define VDEC2_SCD_FOR_MV_X 0x2c12 	///../ucode/dos_register.h:5408
#define P_VDEC2_SCD_FOR_MV_X 		DOS_REG_ADDR(VDEC2_SCD_FOR_MV_X)
#define VDEC2_SCD_FOR_MV_Y 0x2c13 	///../ucode/dos_register.h:5409
#define P_VDEC2_SCD_FOR_MV_Y 		DOS_REG_ADDR(VDEC2_SCD_FOR_MV_Y)
#define VDEC2_FST_BAK_MV_X 0x2c14 	///../ucode/dos_register.h:5410
#define P_VDEC2_FST_BAK_MV_X 		DOS_REG_ADDR(VDEC2_FST_BAK_MV_X)
#define VDEC2_FST_BAK_MV_Y 0x2c15 	///../ucode/dos_register.h:5411
#define P_VDEC2_FST_BAK_MV_Y 		DOS_REG_ADDR(VDEC2_FST_BAK_MV_Y)
#define VDEC2_SCD_BAK_MV_X 0x2c16 	///../ucode/dos_register.h:5412
#define P_VDEC2_SCD_BAK_MV_X 		DOS_REG_ADDR(VDEC2_SCD_BAK_MV_X)
#define VDEC2_SCD_BAK_MV_Y 0x2c17 	///../ucode/dos_register.h:5413
#define P_VDEC2_SCD_BAK_MV_Y 		DOS_REG_ADDR(VDEC2_SCD_BAK_MV_Y)
#define VDEC2_VLD_DECODE_CONTROL 0x2c18 	///../ucode/dos_register.h:5419
#define P_VDEC2_VLD_DECODE_CONTROL 		DOS_REG_ADDR(VDEC2_VLD_DECODE_CONTROL)
#define VDEC2_VLD_REVERVED_19 0x2c19 	///../ucode/dos_register.h:5420
#define P_VDEC2_VLD_REVERVED_19 		DOS_REG_ADDR(VDEC2_VLD_REVERVED_19)
#define VDEC2_VIFF_BIT_CNT 0x2c1a 	///../ucode/dos_register.h:5421
#define P_VDEC2_VIFF_BIT_CNT 		DOS_REG_ADDR(VDEC2_VIFF_BIT_CNT)
#define VDEC2_BYTE_ALIGN_PEAK_HI 0x2c1b 	///../ucode/dos_register.h:5422
#define P_VDEC2_BYTE_ALIGN_PEAK_HI 		DOS_REG_ADDR(VDEC2_BYTE_ALIGN_PEAK_HI)
#define VDEC2_BYTE_ALIGN_PEAK_LO 0x2c1c 	///../ucode/dos_register.h:5423
#define P_VDEC2_BYTE_ALIGN_PEAK_LO 		DOS_REG_ADDR(VDEC2_BYTE_ALIGN_PEAK_LO)
#define VDEC2_NEXT_ALIGN_PEAK 0x2c1d 	///../ucode/dos_register.h:5424
#define P_VDEC2_NEXT_ALIGN_PEAK 		DOS_REG_ADDR(VDEC2_NEXT_ALIGN_PEAK)
#define VDEC2_VC1_CONTROL_REG 0x2c1e 	///../ucode/dos_register.h:5440
#define P_VDEC2_VC1_CONTROL_REG 		DOS_REG_ADDR(VDEC2_VC1_CONTROL_REG)
#define VDEC2_PMV1_X 0x2c20 	///../ucode/dos_register.h:5441
#define P_VDEC2_PMV1_X 		DOS_REG_ADDR(VDEC2_PMV1_X)
#define VDEC2_PMV1_Y 0x2c21 	///../ucode/dos_register.h:5442
#define P_VDEC2_PMV1_Y 		DOS_REG_ADDR(VDEC2_PMV1_Y)
#define VDEC2_PMV2_X 0x2c22 	///../ucode/dos_register.h:5443
#define P_VDEC2_PMV2_X 		DOS_REG_ADDR(VDEC2_PMV2_X)
#define VDEC2_PMV2_Y 0x2c23 	///../ucode/dos_register.h:5444
#define P_VDEC2_PMV2_Y 		DOS_REG_ADDR(VDEC2_PMV2_Y)
#define VDEC2_PMV3_X 0x2c24 	///../ucode/dos_register.h:5445
#define P_VDEC2_PMV3_X 		DOS_REG_ADDR(VDEC2_PMV3_X)
#define VDEC2_PMV3_Y 0x2c25 	///../ucode/dos_register.h:5446
#define P_VDEC2_PMV3_Y 		DOS_REG_ADDR(VDEC2_PMV3_Y)
#define VDEC2_PMV4_X 0x2c26 	///../ucode/dos_register.h:5447
#define P_VDEC2_PMV4_X 		DOS_REG_ADDR(VDEC2_PMV4_X)
#define VDEC2_PMV4_Y 0x2c27 	///../ucode/dos_register.h:5448
#define P_VDEC2_PMV4_Y 		DOS_REG_ADDR(VDEC2_PMV4_Y)
#define VDEC2_M4_TABLE_SELECT 0x2c28 	///../ucode/dos_register.h:5455
#define P_VDEC2_M4_TABLE_SELECT 		DOS_REG_ADDR(VDEC2_M4_TABLE_SELECT)
#define VDEC2_M4_CONTROL_REG 0x2c29 	///../ucode/dos_register.h:5456
#define P_VDEC2_M4_CONTROL_REG 		DOS_REG_ADDR(VDEC2_M4_CONTROL_REG)
#define VDEC2_BLOCK_NUM 0x2c2a 	///../ucode/dos_register.h:5457
#define P_VDEC2_BLOCK_NUM 		DOS_REG_ADDR(VDEC2_BLOCK_NUM)
#define VDEC2_PATTERN_CODE 0x2c2b 	///../ucode/dos_register.h:5458
#define P_VDEC2_PATTERN_CODE 		DOS_REG_ADDR(VDEC2_PATTERN_CODE)
#define VDEC2_MB_INFO 0x2c2c 	///../ucode/dos_register.h:5459
#define P_VDEC2_MB_INFO 		DOS_REG_ADDR(VDEC2_MB_INFO)
#define VDEC2_VLD_DC_PRED 0x2c2d 	///../ucode/dos_register.h:5460
#define P_VDEC2_VLD_DC_PRED 		DOS_REG_ADDR(VDEC2_VLD_DC_PRED)
#define VDEC2_VLD_ERROR_MASK 0x2c2e 	///../ucode/dos_register.h:5461
#define P_VDEC2_VLD_ERROR_MASK 		DOS_REG_ADDR(VDEC2_VLD_ERROR_MASK)
#define VDEC2_VLD_DC_PRED_C 0x2c2f 	///../ucode/dos_register.h:5462
#define P_VDEC2_VLD_DC_PRED_C 		DOS_REG_ADDR(VDEC2_VLD_DC_PRED_C)
#define VDEC2_LAST_SLICE_MV_ADDR 0x2c30 	///../ucode/dos_register.h:5463
#define P_VDEC2_LAST_SLICE_MV_ADDR 		DOS_REG_ADDR(VDEC2_LAST_SLICE_MV_ADDR)
#define VDEC2_LAST_MVX 0x2c31 	///../ucode/dos_register.h:5464
#define P_VDEC2_LAST_MVX 		DOS_REG_ADDR(VDEC2_LAST_MVX)
#define VDEC2_LAST_MVY 0x2c32 	///../ucode/dos_register.h:5465
#define P_VDEC2_LAST_MVY 		DOS_REG_ADDR(VDEC2_LAST_MVY)
#define VDEC2_VLD_C38 0x2c38 	///../ucode/dos_register.h:5466
#define P_VDEC2_VLD_C38 		DOS_REG_ADDR(VDEC2_VLD_C38)
#define VDEC2_VLD_C39 0x2c39 	///../ucode/dos_register.h:5467
#define P_VDEC2_VLD_C39 		DOS_REG_ADDR(VDEC2_VLD_C39)
#define VDEC2_VLD_STATUS 0x2c3a 	///../ucode/dos_register.h:5468
#define P_VDEC2_VLD_STATUS 		DOS_REG_ADDR(VDEC2_VLD_STATUS)
#define VDEC2_VLD_SHIFT_STATUS 0x2c3b 	///../ucode/dos_register.h:5469
#define P_VDEC2_VLD_SHIFT_STATUS 		DOS_REG_ADDR(VDEC2_VLD_SHIFT_STATUS)
#define VDEC2_VOFF_STATUS 0x2c3c 	///../ucode/dos_register.h:5471
#define P_VDEC2_VOFF_STATUS 		DOS_REG_ADDR(VDEC2_VOFF_STATUS)
#define VDEC2_VLD_C3D 0x2c3d 	///../ucode/dos_register.h:5472
#define P_VDEC2_VLD_C3D 		DOS_REG_ADDR(VDEC2_VLD_C3D)
#define VDEC2_VLD_DBG_INDEX 0x2c3e 	///../ucode/dos_register.h:5473
#define P_VDEC2_VLD_DBG_INDEX 		DOS_REG_ADDR(VDEC2_VLD_DBG_INDEX)
#define VDEC2_VLD_DBG_DATA 0x2c3f 	///../ucode/dos_register.h:5549
#define P_VDEC2_VLD_DBG_DATA 		DOS_REG_ADDR(VDEC2_VLD_DBG_DATA)
#define VDEC2_VLD_MEM_VIFIFO_START_PTR 0x2c40 	///../ucode/dos_register.h:5556
#define P_VDEC2_VLD_MEM_VIFIFO_START_PTR 		DOS_REG_ADDR(VDEC2_VLD_MEM_VIFIFO_START_PTR)
#define VDEC2_VLD_MEM_VIFIFO_CURR_PTR 0x2c41 	///../ucode/dos_register.h:5560
#define P_VDEC2_VLD_MEM_VIFIFO_CURR_PTR 		DOS_REG_ADDR(VDEC2_VLD_MEM_VIFIFO_CURR_PTR)
#define VDEC2_VLD_MEM_VIFIFO_END_PTR 0x2c42 	///../ucode/dos_register.h:5561
#define P_VDEC2_VLD_MEM_VIFIFO_END_PTR 		DOS_REG_ADDR(VDEC2_VLD_MEM_VIFIFO_END_PTR)
#define VDEC2_VLD_MEM_VIFIFO_BYTES_AVAIL 0x2c43 	///../ucode/dos_register.h:5562
#define P_VDEC2_VLD_MEM_VIFIFO_BYTES_AVAIL 		DOS_REG_ADDR(VDEC2_VLD_MEM_VIFIFO_BYTES_AVAIL)
#define VDEC2_VLD_MEM_VIFIFO_CONTROL 0x2c44 	///../ucode/dos_register.h:5593
#define P_VDEC2_VLD_MEM_VIFIFO_CONTROL 		DOS_REG_ADDR(VDEC2_VLD_MEM_VIFIFO_CONTROL)
#define VDEC2_VLD_MEM_VIFIFO_WP 0x2c45 	///../ucode/dos_register.h:5597
#define P_VDEC2_VLD_MEM_VIFIFO_WP 		DOS_REG_ADDR(VDEC2_VLD_MEM_VIFIFO_WP)
#define VDEC2_VLD_MEM_VIFIFO_RP 0x2c46 	///../ucode/dos_register.h:5598
#define P_VDEC2_VLD_MEM_VIFIFO_RP 		DOS_REG_ADDR(VDEC2_VLD_MEM_VIFIFO_RP)
#define VDEC2_VLD_MEM_VIFIFO_LEVEL 0x2c47 	///../ucode/dos_register.h:5599
#define P_VDEC2_VLD_MEM_VIFIFO_LEVEL 		DOS_REG_ADDR(VDEC2_VLD_MEM_VIFIFO_LEVEL)
#define VDEC2_VLD_MEM_VIFIFO_BUF_CNTL 0x2c48 	///../ucode/dos_register.h:5609
#define P_VDEC2_VLD_MEM_VIFIFO_BUF_CNTL 		DOS_REG_ADDR(VDEC2_VLD_MEM_VIFIFO_BUF_CNTL)
#define VDEC2_VLD_TIME_STAMP_CNTL 0x2c49 	///../ucode/dos_register.h:5619
#define P_VDEC2_VLD_TIME_STAMP_CNTL 		DOS_REG_ADDR(VDEC2_VLD_TIME_STAMP_CNTL)
#define VDEC2_VLD_TIME_STAMP_SYNC_0 0x2c4a 	///../ucode/dos_register.h:5621
#define P_VDEC2_VLD_TIME_STAMP_SYNC_0 		DOS_REG_ADDR(VDEC2_VLD_TIME_STAMP_SYNC_0)
#define VDEC2_VLD_TIME_STAMP_SYNC_1 0x2c4b 	///../ucode/dos_register.h:5623
#define P_VDEC2_VLD_TIME_STAMP_SYNC_1 		DOS_REG_ADDR(VDEC2_VLD_TIME_STAMP_SYNC_1)
#define VDEC2_VLD_TIME_STAMP_0 0x2c4c 	///../ucode/dos_register.h:5625
#define P_VDEC2_VLD_TIME_STAMP_0 		DOS_REG_ADDR(VDEC2_VLD_TIME_STAMP_0)
#define VDEC2_VLD_TIME_STAMP_1 0x2c4d 	///../ucode/dos_register.h:5627
#define P_VDEC2_VLD_TIME_STAMP_1 		DOS_REG_ADDR(VDEC2_VLD_TIME_STAMP_1)
#define VDEC2_VLD_TIME_STAMP_2 0x2c4e 	///../ucode/dos_register.h:5629
#define P_VDEC2_VLD_TIME_STAMP_2 		DOS_REG_ADDR(VDEC2_VLD_TIME_STAMP_2)
#define VDEC2_VLD_TIME_STAMP_3 0x2c4f 	///../ucode/dos_register.h:5631
#define P_VDEC2_VLD_TIME_STAMP_3 		DOS_REG_ADDR(VDEC2_VLD_TIME_STAMP_3)
#define VDEC2_VLD_TIME_STAMP_LENGTH 0x2c50 	///../ucode/dos_register.h:5633
#define P_VDEC2_VLD_TIME_STAMP_LENGTH 		DOS_REG_ADDR(VDEC2_VLD_TIME_STAMP_LENGTH)
#define VDEC2_VLD_MEM_VIFIFO_WRAP_COUNT 0x2c51 	///../ucode/dos_register.h:5635
#define P_VDEC2_VLD_MEM_VIFIFO_WRAP_COUNT 		DOS_REG_ADDR(VDEC2_VLD_MEM_VIFIFO_WRAP_COUNT)
#define VDEC2_VLD_MEM_VIFIFO_MEM_CTL 0x2c52 	///../ucode/dos_register.h:5639
#define P_VDEC2_VLD_MEM_VIFIFO_MEM_CTL 		DOS_REG_ADDR(VDEC2_VLD_MEM_VIFIFO_MEM_CTL)
#define VDEC2_VLD_MEM_VBUF_RD_PTR 0x2c53 	///../ucode/dos_register.h:5640
#define P_VDEC2_VLD_MEM_VBUF_RD_PTR 		DOS_REG_ADDR(VDEC2_VLD_MEM_VBUF_RD_PTR)
#define VDEC2_VLD_MEM_VBUF2_RD_PTR 0x2c54 	///../ucode/dos_register.h:5641
#define P_VDEC2_VLD_MEM_VBUF2_RD_PTR 		DOS_REG_ADDR(VDEC2_VLD_MEM_VBUF2_RD_PTR)
#define VDEC2_VLD_MEM_SWAP_ADDR 0x2c55 	///../ucode/dos_register.h:5642
#define P_VDEC2_VLD_MEM_SWAP_ADDR 		DOS_REG_ADDR(VDEC2_VLD_MEM_SWAP_ADDR)
#define VDEC2_VLD_MEM_SWAP_CTL 0x2c56 	///../ucode/dos_register.h:5649
#define P_VDEC2_VLD_MEM_SWAP_CTL 		DOS_REG_ADDR(VDEC2_VLD_MEM_SWAP_CTL)
#define HEVC_VLD_STATUS_CTRL 0x3c00 	///../ucode/dos_register.h:5662
#define P_HEVC_VLD_STATUS_CTRL 		DOS_REG_ADDR(HEVC_VLD_STATUS_CTRL)
#define HEVC_MPEG1_2_REG 0x3c01 	///../ucode/dos_register.h:5672
#define P_HEVC_MPEG1_2_REG 		DOS_REG_ADDR(HEVC_MPEG1_2_REG)
#define HEVC_F_CODE_REG 0x3c02 	///../ucode/dos_register.h:5673
#define P_HEVC_F_CODE_REG 		DOS_REG_ADDR(HEVC_F_CODE_REG)
#define HEVC_PIC_HEAD_INFO 0x3c03 	///../ucode/dos_register.h:5674
#define P_HEVC_PIC_HEAD_INFO 		DOS_REG_ADDR(HEVC_PIC_HEAD_INFO)
#define HEVC_SLICE_VER_POS_PIC_TYPE 0x3c04 	///../ucode/dos_register.h:5675
#define P_HEVC_SLICE_VER_POS_PIC_TYPE 		DOS_REG_ADDR(HEVC_SLICE_VER_POS_PIC_TYPE)
#define HEVC_QP_VALUE_REG 0x3c05 	///../ucode/dos_register.h:5676
#define P_HEVC_QP_VALUE_REG 		DOS_REG_ADDR(HEVC_QP_VALUE_REG)
#define HEVC_MBA_INC 0x3c06 	///../ucode/dos_register.h:5677
#define P_HEVC_MBA_INC 		DOS_REG_ADDR(HEVC_MBA_INC)
#define HEVC_MB_MOTION_MODE 0x3c07 	///../ucode/dos_register.h:5678
#define P_HEVC_MB_MOTION_MODE 		DOS_REG_ADDR(HEVC_MB_MOTION_MODE)
#define HEVC_POWER_CTL_VLD 0x3c08 	///../ucode/dos_register.h:5686
#define P_HEVC_POWER_CTL_VLD 		DOS_REG_ADDR(HEVC_POWER_CTL_VLD)
#define HEVC_MB_WIDTH 0x3c09 	///../ucode/dos_register.h:5687
#define P_HEVC_MB_WIDTH 		DOS_REG_ADDR(HEVC_MB_WIDTH)
#define HEVC_SLICE_QP 0x3c0a 	///../ucode/dos_register.h:5688
#define P_HEVC_SLICE_QP 		DOS_REG_ADDR(HEVC_SLICE_QP)
#define HEVC_PRE_START_CODE 0x3c0b 	///../ucode/dos_register.h:5690
#define P_HEVC_PRE_START_CODE 		DOS_REG_ADDR(HEVC_PRE_START_CODE)
#define HEVC_SLICE_START_BYTE_01 0x3c0c 	///../ucode/dos_register.h:5691
#define P_HEVC_SLICE_START_BYTE_01 		DOS_REG_ADDR(HEVC_SLICE_START_BYTE_01)
#define HEVC_SLICE_START_BYTE_23 0x3c0d 	///../ucode/dos_register.h:5692
#define P_HEVC_SLICE_START_BYTE_23 		DOS_REG_ADDR(HEVC_SLICE_START_BYTE_23)
#define HEVC_RESYNC_MARKER_LENGTH 0x3c0e 	///../ucode/dos_register.h:5693
#define P_HEVC_RESYNC_MARKER_LENGTH 		DOS_REG_ADDR(HEVC_RESYNC_MARKER_LENGTH)
#define HEVC_DECODER_BUFFER_INFO 0x3c0f 	///../ucode/dos_register.h:5697
#define P_HEVC_DECODER_BUFFER_INFO 		DOS_REG_ADDR(HEVC_DECODER_BUFFER_INFO)
#define HEVC_FST_FOR_MV_X 0x3c10 	///../ucode/dos_register.h:5698
#define P_HEVC_FST_FOR_MV_X 		DOS_REG_ADDR(HEVC_FST_FOR_MV_X)
#define HEVC_FST_FOR_MV_Y 0x3c11 	///../ucode/dos_register.h:5699
#define P_HEVC_FST_FOR_MV_Y 		DOS_REG_ADDR(HEVC_FST_FOR_MV_Y)
#define HEVC_SCD_FOR_MV_X 0x3c12 	///../ucode/dos_register.h:5700
#define P_HEVC_SCD_FOR_MV_X 		DOS_REG_ADDR(HEVC_SCD_FOR_MV_X)
#define HEVC_SCD_FOR_MV_Y 0x3c13 	///../ucode/dos_register.h:5701
#define P_HEVC_SCD_FOR_MV_Y 		DOS_REG_ADDR(HEVC_SCD_FOR_MV_Y)
#define HEVC_FST_BAK_MV_X 0x3c14 	///../ucode/dos_register.h:5702
#define P_HEVC_FST_BAK_MV_X 		DOS_REG_ADDR(HEVC_FST_BAK_MV_X)
#define HEVC_FST_BAK_MV_Y 0x3c15 	///../ucode/dos_register.h:5703
#define P_HEVC_FST_BAK_MV_Y 		DOS_REG_ADDR(HEVC_FST_BAK_MV_Y)
#define HEVC_SCD_BAK_MV_X 0x3c16 	///../ucode/dos_register.h:5704
#define P_HEVC_SCD_BAK_MV_X 		DOS_REG_ADDR(HEVC_SCD_BAK_MV_X)
#define HEVC_SCD_BAK_MV_Y 0x3c17 	///../ucode/dos_register.h:5705
#define P_HEVC_SCD_BAK_MV_Y 		DOS_REG_ADDR(HEVC_SCD_BAK_MV_Y)
#define HEVC_VLD_DECODE_CONTROL 0x3c18 	///../ucode/dos_register.h:5711
#define P_HEVC_VLD_DECODE_CONTROL 		DOS_REG_ADDR(HEVC_VLD_DECODE_CONTROL)
#define HEVC_VLD_REVERVED_19 0x3c19 	///../ucode/dos_register.h:5712
#define P_HEVC_VLD_REVERVED_19 		DOS_REG_ADDR(HEVC_VLD_REVERVED_19)
#define HEVC_VIFF_BIT_CNT 0x3c1a 	///../ucode/dos_register.h:5713
#define P_HEVC_VIFF_BIT_CNT 		DOS_REG_ADDR(HEVC_VIFF_BIT_CNT)
#define HEVC_BYTE_ALIGN_PEAK_HI 0x3c1b 	///../ucode/dos_register.h:5714
#define P_HEVC_BYTE_ALIGN_PEAK_HI 		DOS_REG_ADDR(HEVC_BYTE_ALIGN_PEAK_HI)
#define HEVC_BYTE_ALIGN_PEAK_LO 0x3c1c 	///../ucode/dos_register.h:5715
#define P_HEVC_BYTE_ALIGN_PEAK_LO 		DOS_REG_ADDR(HEVC_BYTE_ALIGN_PEAK_LO)
#define HEVC_NEXT_ALIGN_PEAK 0x3c1d 	///../ucode/dos_register.h:5716
#define P_HEVC_NEXT_ALIGN_PEAK 		DOS_REG_ADDR(HEVC_NEXT_ALIGN_PEAK)
#define HEVC_VC1_CONTROL_REG 0x3c1e 	///../ucode/dos_register.h:5732
#define P_HEVC_VC1_CONTROL_REG 		DOS_REG_ADDR(HEVC_VC1_CONTROL_REG)
#define HEVC_PMV1_X 0x3c20 	///../ucode/dos_register.h:5733
#define P_HEVC_PMV1_X 		DOS_REG_ADDR(HEVC_PMV1_X)
#define HEVC_PMV1_Y 0x3c21 	///../ucode/dos_register.h:5734
#define P_HEVC_PMV1_Y 		DOS_REG_ADDR(HEVC_PMV1_Y)
#define HEVC_PMV2_X 0x3c22 	///../ucode/dos_register.h:5735
#define P_HEVC_PMV2_X 		DOS_REG_ADDR(HEVC_PMV2_X)
#define HEVC_PMV2_Y 0x3c23 	///../ucode/dos_register.h:5736
#define P_HEVC_PMV2_Y 		DOS_REG_ADDR(HEVC_PMV2_Y)
#define HEVC_PMV3_X 0x3c24 	///../ucode/dos_register.h:5737
#define P_HEVC_PMV3_X 		DOS_REG_ADDR(HEVC_PMV3_X)
#define HEVC_PMV3_Y 0x3c25 	///../ucode/dos_register.h:5738
#define P_HEVC_PMV3_Y 		DOS_REG_ADDR(HEVC_PMV3_Y)
#define HEVC_PMV4_X 0x3c26 	///../ucode/dos_register.h:5739
#define P_HEVC_PMV4_X 		DOS_REG_ADDR(HEVC_PMV4_X)
#define HEVC_PMV4_Y 0x3c27 	///../ucode/dos_register.h:5740
#define P_HEVC_PMV4_Y 		DOS_REG_ADDR(HEVC_PMV4_Y)
#define HEVC_M4_TABLE_SELECT 0x3c28 	///../ucode/dos_register.h:5747
#define P_HEVC_M4_TABLE_SELECT 		DOS_REG_ADDR(HEVC_M4_TABLE_SELECT)
#define HEVC_M4_CONTROL_REG 0x3c29 	///../ucode/dos_register.h:5748
#define P_HEVC_M4_CONTROL_REG 		DOS_REG_ADDR(HEVC_M4_CONTROL_REG)
#define HEVC_BLOCK_NUM 0x3c2a 	///../ucode/dos_register.h:5749
#define P_HEVC_BLOCK_NUM 		DOS_REG_ADDR(HEVC_BLOCK_NUM)
#define HEVC_PATTERN_CODE 0x3c2b 	///../ucode/dos_register.h:5750
#define P_HEVC_PATTERN_CODE 		DOS_REG_ADDR(HEVC_PATTERN_CODE)
#define HEVC_MB_INFO 0x3c2c 	///../ucode/dos_register.h:5751
#define P_HEVC_MB_INFO 		DOS_REG_ADDR(HEVC_MB_INFO)
#define HEVC_VLD_DC_PRED 0x3c2d 	///../ucode/dos_register.h:5752
#define P_HEVC_VLD_DC_PRED 		DOS_REG_ADDR(HEVC_VLD_DC_PRED)
#define HEVC_VLD_ERROR_MASK 0x3c2e 	///../ucode/dos_register.h:5753
#define P_HEVC_VLD_ERROR_MASK 		DOS_REG_ADDR(HEVC_VLD_ERROR_MASK)
#define HEVC_VLD_DC_PRED_C 0x3c2f 	///../ucode/dos_register.h:5754
#define P_HEVC_VLD_DC_PRED_C 		DOS_REG_ADDR(HEVC_VLD_DC_PRED_C)
#define HEVC_LAST_SLICE_MV_ADDR 0x3c30 	///../ucode/dos_register.h:5755
#define P_HEVC_LAST_SLICE_MV_ADDR 		DOS_REG_ADDR(HEVC_LAST_SLICE_MV_ADDR)
#define HEVC_LAST_MVX 0x3c31 	///../ucode/dos_register.h:5756
#define P_HEVC_LAST_MVX 		DOS_REG_ADDR(HEVC_LAST_MVX)
#define HEVC_LAST_MVY 0x3c32 	///../ucode/dos_register.h:5757
#define P_HEVC_LAST_MVY 		DOS_REG_ADDR(HEVC_LAST_MVY)
#define HEVC_VLD_C38 0x3c38 	///../ucode/dos_register.h:5758
#define P_HEVC_VLD_C38 		DOS_REG_ADDR(HEVC_VLD_C38)
#define HEVC_VLD_C39 0x3c39 	///../ucode/dos_register.h:5759
#define P_HEVC_VLD_C39 		DOS_REG_ADDR(HEVC_VLD_C39)
#define HEVC_VLD_STATUS 0x3c3a 	///../ucode/dos_register.h:5760
#define P_HEVC_VLD_STATUS 		DOS_REG_ADDR(HEVC_VLD_STATUS)
#define HEVC_VLD_SHIFT_STATUS 0x3c3b 	///../ucode/dos_register.h:5761
#define P_HEVC_VLD_SHIFT_STATUS 		DOS_REG_ADDR(HEVC_VLD_SHIFT_STATUS)
#define HEVC_VOFF_STATUS 0x3c3c 	///../ucode/dos_register.h:5763
#define P_HEVC_VOFF_STATUS 		DOS_REG_ADDR(HEVC_VOFF_STATUS)
#define HEVC_VLD_C3D 0x3c3d 	///../ucode/dos_register.h:5764
#define P_HEVC_VLD_C3D 		DOS_REG_ADDR(HEVC_VLD_C3D)
#define HEVC_VLD_DBG_INDEX 0x3c3e 	///../ucode/dos_register.h:5765
#define P_HEVC_VLD_DBG_INDEX 		DOS_REG_ADDR(HEVC_VLD_DBG_INDEX)
#define HEVC_VLD_DBG_DATA 0x3c3f 	///../ucode/dos_register.h:5841
#define P_HEVC_VLD_DBG_DATA 		DOS_REG_ADDR(HEVC_VLD_DBG_DATA)
#define HEVC_VLD_MEM_VIFIFO_START_PTR 0x3c40 	///../ucode/dos_register.h:5848
#define P_HEVC_VLD_MEM_VIFIFO_START_PTR 		DOS_REG_ADDR(HEVC_VLD_MEM_VIFIFO_START_PTR)
#define HEVC_VLD_MEM_VIFIFO_CURR_PTR 0x3c41 	///../ucode/dos_register.h:5852
#define P_HEVC_VLD_MEM_VIFIFO_CURR_PTR 		DOS_REG_ADDR(HEVC_VLD_MEM_VIFIFO_CURR_PTR)
#define HEVC_VLD_MEM_VIFIFO_END_PTR 0x3c42 	///../ucode/dos_register.h:5853
#define P_HEVC_VLD_MEM_VIFIFO_END_PTR 		DOS_REG_ADDR(HEVC_VLD_MEM_VIFIFO_END_PTR)
#define HEVC_VLD_MEM_VIFIFO_BYTES_AVAIL 0x3c43 	///../ucode/dos_register.h:5854
#define P_HEVC_VLD_MEM_VIFIFO_BYTES_AVAIL 		DOS_REG_ADDR(HEVC_VLD_MEM_VIFIFO_BYTES_AVAIL)
#define HEVC_VLD_MEM_VIFIFO_CONTROL 0x3c44 	///../ucode/dos_register.h:5885
#define P_HEVC_VLD_MEM_VIFIFO_CONTROL 		DOS_REG_ADDR(HEVC_VLD_MEM_VIFIFO_CONTROL)
#define HEVC_VLD_MEM_VIFIFO_WP 0x3c45 	///../ucode/dos_register.h:5889
#define P_HEVC_VLD_MEM_VIFIFO_WP 		DOS_REG_ADDR(HEVC_VLD_MEM_VIFIFO_WP)
#define HEVC_VLD_MEM_VIFIFO_RP 0x3c46 	///../ucode/dos_register.h:5890
#define P_HEVC_VLD_MEM_VIFIFO_RP 		DOS_REG_ADDR(HEVC_VLD_MEM_VIFIFO_RP)
#define HEVC_VLD_MEM_VIFIFO_LEVEL 0x3c47 	///../ucode/dos_register.h:5891
#define P_HEVC_VLD_MEM_VIFIFO_LEVEL 		DOS_REG_ADDR(HEVC_VLD_MEM_VIFIFO_LEVEL)
#define HEVC_VLD_MEM_VIFIFO_BUF_CNTL 0x3c48 	///../ucode/dos_register.h:5901
#define P_HEVC_VLD_MEM_VIFIFO_BUF_CNTL 		DOS_REG_ADDR(HEVC_VLD_MEM_VIFIFO_BUF_CNTL)
#define HEVC_VLD_TIME_STAMP_CNTL 0x3c49 	///../ucode/dos_register.h:5911
#define P_HEVC_VLD_TIME_STAMP_CNTL 		DOS_REG_ADDR(HEVC_VLD_TIME_STAMP_CNTL)
#define HEVC_VLD_TIME_STAMP_SYNC_0 0x3c4a 	///../ucode/dos_register.h:5913
#define P_HEVC_VLD_TIME_STAMP_SYNC_0 		DOS_REG_ADDR(HEVC_VLD_TIME_STAMP_SYNC_0)
#define HEVC_VLD_TIME_STAMP_SYNC_1 0x3c4b 	///../ucode/dos_register.h:5915
#define P_HEVC_VLD_TIME_STAMP_SYNC_1 		DOS_REG_ADDR(HEVC_VLD_TIME_STAMP_SYNC_1)
#define HEVC_VLD_TIME_STAMP_0 0x3c4c 	///../ucode/dos_register.h:5917
#define P_HEVC_VLD_TIME_STAMP_0 		DOS_REG_ADDR(HEVC_VLD_TIME_STAMP_0)
#define HEVC_VLD_TIME_STAMP_1 0x3c4d 	///../ucode/dos_register.h:5919
#define P_HEVC_VLD_TIME_STAMP_1 		DOS_REG_ADDR(HEVC_VLD_TIME_STAMP_1)
#define HEVC_VLD_TIME_STAMP_2 0x3c4e 	///../ucode/dos_register.h:5921
#define P_HEVC_VLD_TIME_STAMP_2 		DOS_REG_ADDR(HEVC_VLD_TIME_STAMP_2)
#define HEVC_VLD_TIME_STAMP_3 0x3c4f 	///../ucode/dos_register.h:5923
#define P_HEVC_VLD_TIME_STAMP_3 		DOS_REG_ADDR(HEVC_VLD_TIME_STAMP_3)
#define HEVC_VLD_TIME_STAMP_LENGTH 0x3c50 	///../ucode/dos_register.h:5925
#define P_HEVC_VLD_TIME_STAMP_LENGTH 		DOS_REG_ADDR(HEVC_VLD_TIME_STAMP_LENGTH)
#define HEVC_VLD_MEM_VIFIFO_WRAP_COUNT 0x3c51 	///../ucode/dos_register.h:5927
#define P_HEVC_VLD_MEM_VIFIFO_WRAP_COUNT 		DOS_REG_ADDR(HEVC_VLD_MEM_VIFIFO_WRAP_COUNT)
#define HEVC_VLD_MEM_VIFIFO_MEM_CTL 0x3c52 	///../ucode/dos_register.h:5931
#define P_HEVC_VLD_MEM_VIFIFO_MEM_CTL 		DOS_REG_ADDR(HEVC_VLD_MEM_VIFIFO_MEM_CTL)
#define HEVC_VLD_MEM_VBUF_RD_PTR 0x3c53 	///../ucode/dos_register.h:5932
#define P_HEVC_VLD_MEM_VBUF_RD_PTR 		DOS_REG_ADDR(HEVC_VLD_MEM_VBUF_RD_PTR)
#define HEVC_VLD_MEM_VBUF2_RD_PTR 0x3c54 	///../ucode/dos_register.h:5933
#define P_HEVC_VLD_MEM_VBUF2_RD_PTR 		DOS_REG_ADDR(HEVC_VLD_MEM_VBUF2_RD_PTR)
#define HEVC_VLD_MEM_SWAP_ADDR 0x3c55 	///../ucode/dos_register.h:5934
#define P_HEVC_VLD_MEM_SWAP_ADDR 		DOS_REG_ADDR(HEVC_VLD_MEM_SWAP_ADDR)
#define HEVC_VLD_MEM_SWAP_CTL 0x3c56 	///../ucode/dos_register.h:5941
#define P_HEVC_VLD_MEM_SWAP_CTL 		DOS_REG_ADDR(HEVC_VLD_MEM_SWAP_CTL)
#define HCODEC_VCOP_CTRL_REG 0x1e00 	///../ucode/dos_register.h:5954
#define P_HCODEC_VCOP_CTRL_REG 		DOS_REG_ADDR(HCODEC_VCOP_CTRL_REG)
#define HCODEC_QP_CTRL_REG 0x1e01 	///../ucode/dos_register.h:5955
#define P_HCODEC_QP_CTRL_REG 		DOS_REG_ADDR(HCODEC_QP_CTRL_REG)
#define HCODEC_INTRA_QUANT_MATRIX 0x1e02 	///../ucode/dos_register.h:5956
#define P_HCODEC_INTRA_QUANT_MATRIX 		DOS_REG_ADDR(HCODEC_INTRA_QUANT_MATRIX)
#define HCODEC_NON_I_QUANT_MATRIX 0x1e03 	///../ucode/dos_register.h:5957
#define P_HCODEC_NON_I_QUANT_MATRIX 		DOS_REG_ADDR(HCODEC_NON_I_QUANT_MATRIX)
#define HCODEC_DC_SCALER 0x1e04 	///../ucode/dos_register.h:5958
#define P_HCODEC_DC_SCALER 		DOS_REG_ADDR(HCODEC_DC_SCALER)
#define HCODEC_DC_AC_CTRL 0x1e05 	///../ucode/dos_register.h:5959
#define P_HCODEC_DC_AC_CTRL 		DOS_REG_ADDR(HCODEC_DC_AC_CTRL)
#define HCODEC_DC_AC_SCALE_MUL 0x1e06 	///../ucode/dos_register.h:5961
#define P_HCODEC_DC_AC_SCALE_MUL 		DOS_REG_ADDR(HCODEC_DC_AC_SCALE_MUL)
#define HCODEC_DC_AC_SCALE_DIV 0x1e07 	///../ucode/dos_register.h:5962
#define P_HCODEC_DC_AC_SCALE_DIV 		DOS_REG_ADDR(HCODEC_DC_AC_SCALE_DIV)
#define HCODEC_POWER_CTL_IQIDCT 0x1e08 	///../ucode/dos_register.h:5965
#define P_HCODEC_POWER_CTL_IQIDCT 		DOS_REG_ADDR(HCODEC_POWER_CTL_IQIDCT)
#define HCODEC_RV_AI_Y_X 0x1e09 	///../ucode/dos_register.h:5966
#define P_HCODEC_RV_AI_Y_X 		DOS_REG_ADDR(HCODEC_RV_AI_Y_X)
#define HCODEC_RV_AI_U_X 0x1e0a 	///../ucode/dos_register.h:5967
#define P_HCODEC_RV_AI_U_X 		DOS_REG_ADDR(HCODEC_RV_AI_U_X)
#define HCODEC_RV_AI_V_X 0x1e0b 	///../ucode/dos_register.h:5968
#define P_HCODEC_RV_AI_V_X 		DOS_REG_ADDR(HCODEC_RV_AI_V_X)
#define HCODEC_RV_AI_MB_COUNT 0x1e0c 	///../ucode/dos_register.h:5971
#define P_HCODEC_RV_AI_MB_COUNT 		DOS_REG_ADDR(HCODEC_RV_AI_MB_COUNT)
#define HCODEC_NEXT_INTRA_DMA_ADDRESS 0x1e0d 	///../ucode/dos_register.h:5973
#define P_HCODEC_NEXT_INTRA_DMA_ADDRESS 		DOS_REG_ADDR(HCODEC_NEXT_INTRA_DMA_ADDRESS)
#define HCODEC_IQIDCT_CONTROL 0x1e0e 	///../ucode/dos_register.h:5975
#define P_HCODEC_IQIDCT_CONTROL 		DOS_REG_ADDR(HCODEC_IQIDCT_CONTROL)
#define HCODEC_IQIDCT_DEBUG_INFO_0 0x1e0f 	///../ucode/dos_register.h:5992
#define P_HCODEC_IQIDCT_DEBUG_INFO_0 		DOS_REG_ADDR(HCODEC_IQIDCT_DEBUG_INFO_0)
#define HCODEC_DEBLK_CMD 0x1e10 	///../ucode/dos_register.h:5994
#define P_HCODEC_DEBLK_CMD 		DOS_REG_ADDR(HCODEC_DEBLK_CMD)
#define HCODEC_IQIDCT_DEBUG_IDCT 0x1e11 	///../ucode/dos_register.h:6027
#define P_HCODEC_IQIDCT_DEBUG_IDCT 		DOS_REG_ADDR(HCODEC_IQIDCT_DEBUG_IDCT)
#define HCODEC_DCAC_DMA_CTRL 0x1e12 	///../ucode/dos_register.h:6037
#define P_HCODEC_DCAC_DMA_CTRL 		DOS_REG_ADDR(HCODEC_DCAC_DMA_CTRL)
#define HCODEC_DCAC_DMA_ADDRESS 0x1e13 	///../ucode/dos_register.h:6044
#define P_HCODEC_DCAC_DMA_ADDRESS 		DOS_REG_ADDR(HCODEC_DCAC_DMA_ADDRESS)
#define HCODEC_DCAC_CPU_ADDRESS 0x1e14 	///../ucode/dos_register.h:6046
#define P_HCODEC_DCAC_CPU_ADDRESS 		DOS_REG_ADDR(HCODEC_DCAC_CPU_ADDRESS)
#define HCODEC_DCAC_CPU_DATA 0x1e15 	///../ucode/dos_register.h:6048
#define P_HCODEC_DCAC_CPU_DATA 		DOS_REG_ADDR(HCODEC_DCAC_CPU_DATA)
#define HCODEC_DCAC_MB_COUNT 0x1e16 	///../ucode/dos_register.h:6052
#define P_HCODEC_DCAC_MB_COUNT 		DOS_REG_ADDR(HCODEC_DCAC_MB_COUNT)
#define HCODEC_IQ_QUANT 0x1e17 	///../ucode/dos_register.h:6065
#define P_HCODEC_IQ_QUANT 		DOS_REG_ADDR(HCODEC_IQ_QUANT)
#define HCODEC_VC1_BITPLANE_CTL 0x1e18 	///../ucode/dos_register.h:6073
#define P_HCODEC_VC1_BITPLANE_CTL 		DOS_REG_ADDR(HCODEC_VC1_BITPLANE_CTL)
#define VDEC2_VCOP_CTRL_REG 0x2e00 	///../ucode/dos_register.h:6098
#define P_VDEC2_VCOP_CTRL_REG 		DOS_REG_ADDR(VDEC2_VCOP_CTRL_REG)
#define VDEC2_QP_CTRL_REG 0x2e01 	///../ucode/dos_register.h:6099
#define P_VDEC2_QP_CTRL_REG 		DOS_REG_ADDR(VDEC2_QP_CTRL_REG)
#define VDEC2_INTRA_QUANT_MATRIX 0x2e02 	///../ucode/dos_register.h:6100
#define P_VDEC2_INTRA_QUANT_MATRIX 		DOS_REG_ADDR(VDEC2_INTRA_QUANT_MATRIX)
#define VDEC2_NON_I_QUANT_MATRIX 0x2e03 	///../ucode/dos_register.h:6101
#define P_VDEC2_NON_I_QUANT_MATRIX 		DOS_REG_ADDR(VDEC2_NON_I_QUANT_MATRIX)
#define VDEC2_DC_SCALER 0x2e04 	///../ucode/dos_register.h:6102
#define P_VDEC2_DC_SCALER 		DOS_REG_ADDR(VDEC2_DC_SCALER)
#define VDEC2_DC_AC_CTRL 0x2e05 	///../ucode/dos_register.h:6103
#define P_VDEC2_DC_AC_CTRL 		DOS_REG_ADDR(VDEC2_DC_AC_CTRL)
#define VDEC2_DC_AC_SCALE_MUL 0x2e06 	///../ucode/dos_register.h:6105
#define P_VDEC2_DC_AC_SCALE_MUL 		DOS_REG_ADDR(VDEC2_DC_AC_SCALE_MUL)
#define VDEC2_DC_AC_SCALE_DIV 0x2e07 	///../ucode/dos_register.h:6106
#define P_VDEC2_DC_AC_SCALE_DIV 		DOS_REG_ADDR(VDEC2_DC_AC_SCALE_DIV)
#define VDEC2_POWER_CTL_IQIDCT 0x2e08 	///../ucode/dos_register.h:6109
#define P_VDEC2_POWER_CTL_IQIDCT 		DOS_REG_ADDR(VDEC2_POWER_CTL_IQIDCT)
#define VDEC2_RV_AI_Y_X 0x2e09 	///../ucode/dos_register.h:6110
#define P_VDEC2_RV_AI_Y_X 		DOS_REG_ADDR(VDEC2_RV_AI_Y_X)
#define VDEC2_RV_AI_U_X 0x2e0a 	///../ucode/dos_register.h:6111
#define P_VDEC2_RV_AI_U_X 		DOS_REG_ADDR(VDEC2_RV_AI_U_X)
#define VDEC2_RV_AI_V_X 0x2e0b 	///../ucode/dos_register.h:6112
#define P_VDEC2_RV_AI_V_X 		DOS_REG_ADDR(VDEC2_RV_AI_V_X)
#define VDEC2_RV_AI_MB_COUNT 0x2e0c 	///../ucode/dos_register.h:6115
#define P_VDEC2_RV_AI_MB_COUNT 		DOS_REG_ADDR(VDEC2_RV_AI_MB_COUNT)
#define VDEC2_NEXT_INTRA_DMA_ADDRESS 0x2e0d 	///../ucode/dos_register.h:6117
#define P_VDEC2_NEXT_INTRA_DMA_ADDRESS 		DOS_REG_ADDR(VDEC2_NEXT_INTRA_DMA_ADDRESS)
#define VDEC2_IQIDCT_CONTROL 0x2e0e 	///../ucode/dos_register.h:6119
#define P_VDEC2_IQIDCT_CONTROL 		DOS_REG_ADDR(VDEC2_IQIDCT_CONTROL)
#define VDEC2_IQIDCT_DEBUG_INFO_0 0x2e0f 	///../ucode/dos_register.h:6136
#define P_VDEC2_IQIDCT_DEBUG_INFO_0 		DOS_REG_ADDR(VDEC2_IQIDCT_DEBUG_INFO_0)
#define VDEC2_DEBLK_CMD 0x2e10 	///../ucode/dos_register.h:6138
#define P_VDEC2_DEBLK_CMD 		DOS_REG_ADDR(VDEC2_DEBLK_CMD)
#define VDEC2_IQIDCT_DEBUG_IDCT 0x2e11 	///../ucode/dos_register.h:6171
#define P_VDEC2_IQIDCT_DEBUG_IDCT 		DOS_REG_ADDR(VDEC2_IQIDCT_DEBUG_IDCT)
#define VDEC2_DCAC_DMA_CTRL 0x2e12 	///../ucode/dos_register.h:6181
#define P_VDEC2_DCAC_DMA_CTRL 		DOS_REG_ADDR(VDEC2_DCAC_DMA_CTRL)
#define VDEC2_DCAC_DMA_ADDRESS 0x2e13 	///../ucode/dos_register.h:6188
#define P_VDEC2_DCAC_DMA_ADDRESS 		DOS_REG_ADDR(VDEC2_DCAC_DMA_ADDRESS)
#define VDEC2_DCAC_CPU_ADDRESS 0x2e14 	///../ucode/dos_register.h:6190
#define P_VDEC2_DCAC_CPU_ADDRESS 		DOS_REG_ADDR(VDEC2_DCAC_CPU_ADDRESS)
#define VDEC2_DCAC_CPU_DATA 0x2e15 	///../ucode/dos_register.h:6192
#define P_VDEC2_DCAC_CPU_DATA 		DOS_REG_ADDR(VDEC2_DCAC_CPU_DATA)
#define VDEC2_DCAC_MB_COUNT 0x2e16 	///../ucode/dos_register.h:6196
#define P_VDEC2_DCAC_MB_COUNT 		DOS_REG_ADDR(VDEC2_DCAC_MB_COUNT)
#define VDEC2_IQ_QUANT 0x2e17 	///../ucode/dos_register.h:6209
#define P_VDEC2_IQ_QUANT 		DOS_REG_ADDR(VDEC2_IQ_QUANT)
#define VDEC2_VC1_BITPLANE_CTL 0x2e18 	///../ucode/dos_register.h:6217
#define P_VDEC2_VC1_BITPLANE_CTL 		DOS_REG_ADDR(VDEC2_VC1_BITPLANE_CTL)
#define HEVC_VCOP_CTRL_REG 0x3e00 	///../ucode/dos_register.h:6242
#define P_HEVC_VCOP_CTRL_REG 		DOS_REG_ADDR(HEVC_VCOP_CTRL_REG)
#define HEVC_QP_CTRL_REG 0x3e01 	///../ucode/dos_register.h:6243
#define P_HEVC_QP_CTRL_REG 		DOS_REG_ADDR(HEVC_QP_CTRL_REG)
#define HEVC_INTRA_QUANT_MATRIX 0x3e02 	///../ucode/dos_register.h:6244
#define P_HEVC_INTRA_QUANT_MATRIX 		DOS_REG_ADDR(HEVC_INTRA_QUANT_MATRIX)
#define HEVC_NON_I_QUANT_MATRIX 0x3e03 	///../ucode/dos_register.h:6245
#define P_HEVC_NON_I_QUANT_MATRIX 		DOS_REG_ADDR(HEVC_NON_I_QUANT_MATRIX)
#define HEVC_DC_SCALER 0x3e04 	///../ucode/dos_register.h:6246
#define P_HEVC_DC_SCALER 		DOS_REG_ADDR(HEVC_DC_SCALER)
#define HEVC_DC_AC_CTRL 0x3e05 	///../ucode/dos_register.h:6247
#define P_HEVC_DC_AC_CTRL 		DOS_REG_ADDR(HEVC_DC_AC_CTRL)
#define HEVC_DC_AC_SCALE_MUL 0x3e06 	///../ucode/dos_register.h:6249
#define P_HEVC_DC_AC_SCALE_MUL 		DOS_REG_ADDR(HEVC_DC_AC_SCALE_MUL)
#define HEVC_DC_AC_SCALE_DIV 0x3e07 	///../ucode/dos_register.h:6250
#define P_HEVC_DC_AC_SCALE_DIV 		DOS_REG_ADDR(HEVC_DC_AC_SCALE_DIV)
#define HEVC_POWER_CTL_IQIDCT 0x3e08 	///../ucode/dos_register.h:6253
#define P_HEVC_POWER_CTL_IQIDCT 		DOS_REG_ADDR(HEVC_POWER_CTL_IQIDCT)
#define HEVC_RV_AI_Y_X 0x3e09 	///../ucode/dos_register.h:6254
#define P_HEVC_RV_AI_Y_X 		DOS_REG_ADDR(HEVC_RV_AI_Y_X)
#define HEVC_RV_AI_U_X 0x3e0a 	///../ucode/dos_register.h:6255
#define P_HEVC_RV_AI_U_X 		DOS_REG_ADDR(HEVC_RV_AI_U_X)
#define HEVC_RV_AI_V_X 0x3e0b 	///../ucode/dos_register.h:6256
#define P_HEVC_RV_AI_V_X 		DOS_REG_ADDR(HEVC_RV_AI_V_X)
#define HEVC_RV_AI_MB_COUNT 0x3e0c 	///../ucode/dos_register.h:6259
#define P_HEVC_RV_AI_MB_COUNT 		DOS_REG_ADDR(HEVC_RV_AI_MB_COUNT)
#define HEVC_NEXT_INTRA_DMA_ADDRESS 0x3e0d 	///../ucode/dos_register.h:6261
#define P_HEVC_NEXT_INTRA_DMA_ADDRESS 		DOS_REG_ADDR(HEVC_NEXT_INTRA_DMA_ADDRESS)
#define HEVC_IQIDCT_CONTROL 0x3e0e 	///../ucode/dos_register.h:6263
#define P_HEVC_IQIDCT_CONTROL 		DOS_REG_ADDR(HEVC_IQIDCT_CONTROL)
#define HEVC_IQIDCT_DEBUG_INFO_0 0x3e0f 	///../ucode/dos_register.h:6280
#define P_HEVC_IQIDCT_DEBUG_INFO_0 		DOS_REG_ADDR(HEVC_IQIDCT_DEBUG_INFO_0)
#define HEVC_DEBLK_CMD 0x3e10 	///../ucode/dos_register.h:6282
#define P_HEVC_DEBLK_CMD 		DOS_REG_ADDR(HEVC_DEBLK_CMD)
#define HEVC_IQIDCT_DEBUG_IDCT 0x3e11 	///../ucode/dos_register.h:6315
#define P_HEVC_IQIDCT_DEBUG_IDCT 		DOS_REG_ADDR(HEVC_IQIDCT_DEBUG_IDCT)
#define HEVC_DCAC_DMA_CTRL 0x3e12 	///../ucode/dos_register.h:6325
#define P_HEVC_DCAC_DMA_CTRL 		DOS_REG_ADDR(HEVC_DCAC_DMA_CTRL)
#define HEVC_DCAC_DMA_ADDRESS 0x3e13 	///../ucode/dos_register.h:6332
#define P_HEVC_DCAC_DMA_ADDRESS 		DOS_REG_ADDR(HEVC_DCAC_DMA_ADDRESS)
#define HEVC_DCAC_CPU_ADDRESS 0x3e14 	///../ucode/dos_register.h:6334
#define P_HEVC_DCAC_CPU_ADDRESS 		DOS_REG_ADDR(HEVC_DCAC_CPU_ADDRESS)
#define HEVC_DCAC_CPU_DATA 0x3e15 	///../ucode/dos_register.h:6336
#define P_HEVC_DCAC_CPU_DATA 		DOS_REG_ADDR(HEVC_DCAC_CPU_DATA)
#define HEVC_DCAC_MB_COUNT 0x3e16 	///../ucode/dos_register.h:6340
#define P_HEVC_DCAC_MB_COUNT 		DOS_REG_ADDR(HEVC_DCAC_MB_COUNT)
#define HEVC_IQ_QUANT 0x3e17 	///../ucode/dos_register.h:6353
#define P_HEVC_IQ_QUANT 		DOS_REG_ADDR(HEVC_IQ_QUANT)
#define HEVC_VC1_BITPLANE_CTL 0x3e18 	///../ucode/dos_register.h:6361
#define P_HEVC_VC1_BITPLANE_CTL 		DOS_REG_ADDR(HEVC_VC1_BITPLANE_CTL)
#define HCODEC_MSP 0x1300 	///../ucode/dos_register.h:6386
#define P_HCODEC_MSP 		DOS_REG_ADDR(HCODEC_MSP)
#define HCODEC_MPSR 0x1301 	///../ucode/dos_register.h:6387
#define P_HCODEC_MPSR 		DOS_REG_ADDR(HCODEC_MPSR)
#define HCODEC_MINT_VEC_BASE 0x1302 	///../ucode/dos_register.h:6388
#define P_HCODEC_MINT_VEC_BASE 		DOS_REG_ADDR(HCODEC_MINT_VEC_BASE)
#define HCODEC_MCPU_INTR_GRP 0x1303 	///../ucode/dos_register.h:6389
#define P_HCODEC_MCPU_INTR_GRP 		DOS_REG_ADDR(HCODEC_MCPU_INTR_GRP)
#define HCODEC_MCPU_INTR_MSK 0x1304 	///../ucode/dos_register.h:6390
#define P_HCODEC_MCPU_INTR_MSK 		DOS_REG_ADDR(HCODEC_MCPU_INTR_MSK)
#define HCODEC_MCPU_INTR_REQ 0x1305 	///../ucode/dos_register.h:6391
#define P_HCODEC_MCPU_INTR_REQ 		DOS_REG_ADDR(HCODEC_MCPU_INTR_REQ)
#define HCODEC_MPC_P 0x1306 	///../ucode/dos_register.h:6392
#define P_HCODEC_MPC_P 		DOS_REG_ADDR(HCODEC_MPC_P)
#define HCODEC_MPC_D 0x1307 	///../ucode/dos_register.h:6393
#define P_HCODEC_MPC_D 		DOS_REG_ADDR(HCODEC_MPC_D)
#define HCODEC_MPC_E 0x1308 	///../ucode/dos_register.h:6394
#define P_HCODEC_MPC_E 		DOS_REG_ADDR(HCODEC_MPC_E)
#define HCODEC_MPC_W 0x1309 	///../ucode/dos_register.h:6395
#define P_HCODEC_MPC_W 		DOS_REG_ADDR(HCODEC_MPC_W)
#define HCODEC_MINDEX0_REG 0x130a 	///../ucode/dos_register.h:6396
#define P_HCODEC_MINDEX0_REG 		DOS_REG_ADDR(HCODEC_MINDEX0_REG)
#define HCODEC_MINDEX1_REG 0x130b 	///../ucode/dos_register.h:6397
#define P_HCODEC_MINDEX1_REG 		DOS_REG_ADDR(HCODEC_MINDEX1_REG)
#define HCODEC_MINDEX2_REG 0x130c 	///../ucode/dos_register.h:6398
#define P_HCODEC_MINDEX2_REG 		DOS_REG_ADDR(HCODEC_MINDEX2_REG)
#define HCODEC_MINDEX3_REG 0x130d 	///../ucode/dos_register.h:6399
#define P_HCODEC_MINDEX3_REG 		DOS_REG_ADDR(HCODEC_MINDEX3_REG)
#define HCODEC_MINDEX4_REG 0x130e 	///../ucode/dos_register.h:6400
#define P_HCODEC_MINDEX4_REG 		DOS_REG_ADDR(HCODEC_MINDEX4_REG)
#define HCODEC_MINDEX5_REG 0x130f 	///../ucode/dos_register.h:6401
#define P_HCODEC_MINDEX5_REG 		DOS_REG_ADDR(HCODEC_MINDEX5_REG)
#define HCODEC_MINDEX6_REG 0x1310 	///../ucode/dos_register.h:6402
#define P_HCODEC_MINDEX6_REG 		DOS_REG_ADDR(HCODEC_MINDEX6_REG)
#define HCODEC_MINDEX7_REG 0x1311 	///../ucode/dos_register.h:6403
#define P_HCODEC_MINDEX7_REG 		DOS_REG_ADDR(HCODEC_MINDEX7_REG)
#define HCODEC_MMIN_REG 0x1312 	///../ucode/dos_register.h:6404
#define P_HCODEC_MMIN_REG 		DOS_REG_ADDR(HCODEC_MMIN_REG)
#define HCODEC_MMAX_REG 0x1313 	///../ucode/dos_register.h:6405
#define P_HCODEC_MMAX_REG 		DOS_REG_ADDR(HCODEC_MMAX_REG)
#define HCODEC_MBREAK0_REG 0x1314 	///../ucode/dos_register.h:6406
#define P_HCODEC_MBREAK0_REG 		DOS_REG_ADDR(HCODEC_MBREAK0_REG)
#define HCODEC_MBREAK1_REG 0x1315 	///../ucode/dos_register.h:6407
#define P_HCODEC_MBREAK1_REG 		DOS_REG_ADDR(HCODEC_MBREAK1_REG)
#define HCODEC_MBREAK2_REG 0x1316 	///../ucode/dos_register.h:6408
#define P_HCODEC_MBREAK2_REG 		DOS_REG_ADDR(HCODEC_MBREAK2_REG)
#define HCODEC_MBREAK3_REG 0x1317 	///../ucode/dos_register.h:6409
#define P_HCODEC_MBREAK3_REG 		DOS_REG_ADDR(HCODEC_MBREAK3_REG)
#define HCODEC_MBREAK_TYPE 0x1318 	///../ucode/dos_register.h:6410
#define P_HCODEC_MBREAK_TYPE 		DOS_REG_ADDR(HCODEC_MBREAK_TYPE)
#define HCODEC_MBREAK_CTRL 0x1319 	///../ucode/dos_register.h:6411
#define P_HCODEC_MBREAK_CTRL 		DOS_REG_ADDR(HCODEC_MBREAK_CTRL)
#define HCODEC_MBREAK_STAUTS 0x131a 	///../ucode/dos_register.h:6412
#define P_HCODEC_MBREAK_STAUTS 		DOS_REG_ADDR(HCODEC_MBREAK_STAUTS)
#define HCODEC_MDB_ADDR_REG 0x131b 	///../ucode/dos_register.h:6413
#define P_HCODEC_MDB_ADDR_REG 		DOS_REG_ADDR(HCODEC_MDB_ADDR_REG)
#define HCODEC_MDB_DATA_REG 0x131c 	///../ucode/dos_register.h:6414
#define P_HCODEC_MDB_DATA_REG 		DOS_REG_ADDR(HCODEC_MDB_DATA_REG)
#define HCODEC_MDB_CTRL 0x131d 	///../ucode/dos_register.h:6415
#define P_HCODEC_MDB_CTRL 		DOS_REG_ADDR(HCODEC_MDB_CTRL)
#define HCODEC_MSFTINT0 0x131e 	///../ucode/dos_register.h:6416
#define P_HCODEC_MSFTINT0 		DOS_REG_ADDR(HCODEC_MSFTINT0)
#define HCODEC_MSFTINT1 0x131f 	///../ucode/dos_register.h:6417
#define P_HCODEC_MSFTINT1 		DOS_REG_ADDR(HCODEC_MSFTINT1)
#define HCODEC_CSP 0x1320 	///../ucode/dos_register.h:6418
#define P_HCODEC_CSP 		DOS_REG_ADDR(HCODEC_CSP)
#define HCODEC_CPSR 0x1321 	///../ucode/dos_register.h:6419
#define P_HCODEC_CPSR 		DOS_REG_ADDR(HCODEC_CPSR)
#define HCODEC_CINT_VEC_BASE 0x1322 	///../ucode/dos_register.h:6420
#define P_HCODEC_CINT_VEC_BASE 		DOS_REG_ADDR(HCODEC_CINT_VEC_BASE)
#define HCODEC_CCPU_INTR_GRP 0x1323 	///../ucode/dos_register.h:6421
#define P_HCODEC_CCPU_INTR_GRP 		DOS_REG_ADDR(HCODEC_CCPU_INTR_GRP)
#define HCODEC_CCPU_INTR_MSK 0x1324 	///../ucode/dos_register.h:6422
#define P_HCODEC_CCPU_INTR_MSK 		DOS_REG_ADDR(HCODEC_CCPU_INTR_MSK)
#define HCODEC_CCPU_INTR_REQ 0x1325 	///../ucode/dos_register.h:6423
#define P_HCODEC_CCPU_INTR_REQ 		DOS_REG_ADDR(HCODEC_CCPU_INTR_REQ)
#define HCODEC_CPC_P 0x1326 	///../ucode/dos_register.h:6424
#define P_HCODEC_CPC_P 		DOS_REG_ADDR(HCODEC_CPC_P)
#define HCODEC_CPC_D 0x1327 	///../ucode/dos_register.h:6425
#define P_HCODEC_CPC_D 		DOS_REG_ADDR(HCODEC_CPC_D)
#define HCODEC_CPC_E 0x1328 	///../ucode/dos_register.h:6426
#define P_HCODEC_CPC_E 		DOS_REG_ADDR(HCODEC_CPC_E)
#define HCODEC_CPC_W 0x1329 	///../ucode/dos_register.h:6427
#define P_HCODEC_CPC_W 		DOS_REG_ADDR(HCODEC_CPC_W)
#define HCODEC_CINDEX0_REG 0x132a 	///../ucode/dos_register.h:6428
#define P_HCODEC_CINDEX0_REG 		DOS_REG_ADDR(HCODEC_CINDEX0_REG)
#define HCODEC_CINDEX1_REG 0x132b 	///../ucode/dos_register.h:6429
#define P_HCODEC_CINDEX1_REG 		DOS_REG_ADDR(HCODEC_CINDEX1_REG)
#define HCODEC_CINDEX2_REG 0x132c 	///../ucode/dos_register.h:6430
#define P_HCODEC_CINDEX2_REG 		DOS_REG_ADDR(HCODEC_CINDEX2_REG)
#define HCODEC_CINDEX3_REG 0x132d 	///../ucode/dos_register.h:6431
#define P_HCODEC_CINDEX3_REG 		DOS_REG_ADDR(HCODEC_CINDEX3_REG)
#define HCODEC_CINDEX4_REG 0x132e 	///../ucode/dos_register.h:6432
#define P_HCODEC_CINDEX4_REG 		DOS_REG_ADDR(HCODEC_CINDEX4_REG)
#define HCODEC_CINDEX5_REG 0x132f 	///../ucode/dos_register.h:6433
#define P_HCODEC_CINDEX5_REG 		DOS_REG_ADDR(HCODEC_CINDEX5_REG)
#define HCODEC_CINDEX6_REG 0x1330 	///../ucode/dos_register.h:6434
#define P_HCODEC_CINDEX6_REG 		DOS_REG_ADDR(HCODEC_CINDEX6_REG)
#define HCODEC_CINDEX7_REG 0x1331 	///../ucode/dos_register.h:6435
#define P_HCODEC_CINDEX7_REG 		DOS_REG_ADDR(HCODEC_CINDEX7_REG)
#define HCODEC_CMIN_REG 0x1332 	///../ucode/dos_register.h:6436
#define P_HCODEC_CMIN_REG 		DOS_REG_ADDR(HCODEC_CMIN_REG)
#define HCODEC_CMAX_REG 0x1333 	///../ucode/dos_register.h:6437
#define P_HCODEC_CMAX_REG 		DOS_REG_ADDR(HCODEC_CMAX_REG)
#define HCODEC_CBREAK0_REG 0x1334 	///../ucode/dos_register.h:6438
#define P_HCODEC_CBREAK0_REG 		DOS_REG_ADDR(HCODEC_CBREAK0_REG)
#define HCODEC_CBREAK1_REG 0x1335 	///../ucode/dos_register.h:6439
#define P_HCODEC_CBREAK1_REG 		DOS_REG_ADDR(HCODEC_CBREAK1_REG)
#define HCODEC_CBREAK2_REG 0x1336 	///../ucode/dos_register.h:6440
#define P_HCODEC_CBREAK2_REG 		DOS_REG_ADDR(HCODEC_CBREAK2_REG)
#define HCODEC_CBREAK3_REG 0x1337 	///../ucode/dos_register.h:6441
#define P_HCODEC_CBREAK3_REG 		DOS_REG_ADDR(HCODEC_CBREAK3_REG)
#define HCODEC_CBREAK_TYPE 0x1338 	///../ucode/dos_register.h:6442
#define P_HCODEC_CBREAK_TYPE 		DOS_REG_ADDR(HCODEC_CBREAK_TYPE)
#define HCODEC_CBREAK_CTRL 0x1339 	///../ucode/dos_register.h:6443
#define P_HCODEC_CBREAK_CTRL 		DOS_REG_ADDR(HCODEC_CBREAK_CTRL)
#define HCODEC_CBREAK_STAUTS 0x133a 	///../ucode/dos_register.h:6444
#define P_HCODEC_CBREAK_STAUTS 		DOS_REG_ADDR(HCODEC_CBREAK_STAUTS)
#define HCODEC_CDB_ADDR_REG 0x133b 	///../ucode/dos_register.h:6445
#define P_HCODEC_CDB_ADDR_REG 		DOS_REG_ADDR(HCODEC_CDB_ADDR_REG)
#define HCODEC_CDB_DATA_REG 0x133c 	///../ucode/dos_register.h:6446
#define P_HCODEC_CDB_DATA_REG 		DOS_REG_ADDR(HCODEC_CDB_DATA_REG)
#define HCODEC_CDB_CTRL 0x133d 	///../ucode/dos_register.h:6447
#define P_HCODEC_CDB_CTRL 		DOS_REG_ADDR(HCODEC_CDB_CTRL)
#define HCODEC_CSFTINT0 0x133e 	///../ucode/dos_register.h:6448
#define P_HCODEC_CSFTINT0 		DOS_REG_ADDR(HCODEC_CSFTINT0)
#define HCODEC_CSFTINT1 0x133f 	///../ucode/dos_register.h:6449
#define P_HCODEC_CSFTINT1 		DOS_REG_ADDR(HCODEC_CSFTINT1)
#define HCODEC_IMEM_DMA_CTRL 0x1340 	///../ucode/dos_register.h:6450
#define P_HCODEC_IMEM_DMA_CTRL 		DOS_REG_ADDR(HCODEC_IMEM_DMA_CTRL)
#define HCODEC_IMEM_DMA_ADR 0x1341 	///../ucode/dos_register.h:6451
#define P_HCODEC_IMEM_DMA_ADR 		DOS_REG_ADDR(HCODEC_IMEM_DMA_ADR)
#define HCODEC_IMEM_DMA_COUNT 0x1342 	///../ucode/dos_register.h:6452
#define P_HCODEC_IMEM_DMA_COUNT 		DOS_REG_ADDR(HCODEC_IMEM_DMA_COUNT)
#define HCODEC_WRRSP_IMEM 0x1343 	///../ucode/dos_register.h:6456
#define P_HCODEC_WRRSP_IMEM 		DOS_REG_ADDR(HCODEC_WRRSP_IMEM)
#define HCODEC_LMEM_DMA_CTRL 0x1350 	///../ucode/dos_register.h:6457
#define P_HCODEC_LMEM_DMA_CTRL 		DOS_REG_ADDR(HCODEC_LMEM_DMA_CTRL)
#define HCODEC_LMEM_DMA_ADR 0x1351 	///../ucode/dos_register.h:6458
#define P_HCODEC_LMEM_DMA_ADR 		DOS_REG_ADDR(HCODEC_LMEM_DMA_ADR)
#define HCODEC_LMEM_DMA_COUNT 0x1352 	///../ucode/dos_register.h:6459
#define P_HCODEC_LMEM_DMA_COUNT 		DOS_REG_ADDR(HCODEC_LMEM_DMA_COUNT)
#define HCODEC_WRRSP_LMEM 0x1353 	///../ucode/dos_register.h:6463
#define P_HCODEC_WRRSP_LMEM 		DOS_REG_ADDR(HCODEC_WRRSP_LMEM)
#define HCODEC_MAC_CTRL1 0x1360 	///../ucode/dos_register.h:6464
#define P_HCODEC_MAC_CTRL1 		DOS_REG_ADDR(HCODEC_MAC_CTRL1)
#define HCODEC_ACC0REG1 0x1361 	///../ucode/dos_register.h:6465
#define P_HCODEC_ACC0REG1 		DOS_REG_ADDR(HCODEC_ACC0REG1)
#define HCODEC_ACC1REG1 0x1362 	///../ucode/dos_register.h:6466
#define P_HCODEC_ACC1REG1 		DOS_REG_ADDR(HCODEC_ACC1REG1)
#define HCODEC_MAC_CTRL2 0x1370 	///../ucode/dos_register.h:6467
#define P_HCODEC_MAC_CTRL2 		DOS_REG_ADDR(HCODEC_MAC_CTRL2)
#define HCODEC_ACC0REG2 0x1371 	///../ucode/dos_register.h:6468
#define P_HCODEC_ACC0REG2 		DOS_REG_ADDR(HCODEC_ACC0REG2)
#define HCODEC_ACC1REG2 0x1372 	///../ucode/dos_register.h:6469
#define P_HCODEC_ACC1REG2 		DOS_REG_ADDR(HCODEC_ACC1REG2)
#define HCODEC_CPU_TRACE 0x1380 	///../ucode/dos_register.h:6470
#define P_HCODEC_CPU_TRACE 		DOS_REG_ADDR(HCODEC_CPU_TRACE)
#define VDEC2_MSP 0x2300 	///../ucode/dos_register.h:6483
#define P_VDEC2_MSP 		DOS_REG_ADDR(VDEC2_MSP)
#define VDEC2_MPSR 0x2301 	///../ucode/dos_register.h:6484
#define P_VDEC2_MPSR 		DOS_REG_ADDR(VDEC2_MPSR)
#define VDEC2_MINT_VEC_BASE 0x2302 	///../ucode/dos_register.h:6485
#define P_VDEC2_MINT_VEC_BASE 		DOS_REG_ADDR(VDEC2_MINT_VEC_BASE)
#define VDEC2_MCPU_INTR_GRP 0x2303 	///../ucode/dos_register.h:6486
#define P_VDEC2_MCPU_INTR_GRP 		DOS_REG_ADDR(VDEC2_MCPU_INTR_GRP)
#define VDEC2_MCPU_INTR_MSK 0x2304 	///../ucode/dos_register.h:6487
#define P_VDEC2_MCPU_INTR_MSK 		DOS_REG_ADDR(VDEC2_MCPU_INTR_MSK)
#define VDEC2_MCPU_INTR_REQ 0x2305 	///../ucode/dos_register.h:6488
#define P_VDEC2_MCPU_INTR_REQ 		DOS_REG_ADDR(VDEC2_MCPU_INTR_REQ)
#define VDEC2_MPC_P 0x2306 	///../ucode/dos_register.h:6489
#define P_VDEC2_MPC_P 		DOS_REG_ADDR(VDEC2_MPC_P)
#define VDEC2_MPC_D 0x2307 	///../ucode/dos_register.h:6490
#define P_VDEC2_MPC_D 		DOS_REG_ADDR(VDEC2_MPC_D)
#define VDEC2_MPC_E 0x2308 	///../ucode/dos_register.h:6491
#define P_VDEC2_MPC_E 		DOS_REG_ADDR(VDEC2_MPC_E)
#define VDEC2_MPC_W 0x2309 	///../ucode/dos_register.h:6492
#define P_VDEC2_MPC_W 		DOS_REG_ADDR(VDEC2_MPC_W)
#define VDEC2_MINDEX0_REG 0x230a 	///../ucode/dos_register.h:6493
#define P_VDEC2_MINDEX0_REG 		DOS_REG_ADDR(VDEC2_MINDEX0_REG)
#define VDEC2_MINDEX1_REG 0x230b 	///../ucode/dos_register.h:6494
#define P_VDEC2_MINDEX1_REG 		DOS_REG_ADDR(VDEC2_MINDEX1_REG)
#define VDEC2_MINDEX2_REG 0x230c 	///../ucode/dos_register.h:6495
#define P_VDEC2_MINDEX2_REG 		DOS_REG_ADDR(VDEC2_MINDEX2_REG)
#define VDEC2_MINDEX3_REG 0x230d 	///../ucode/dos_register.h:6496
#define P_VDEC2_MINDEX3_REG 		DOS_REG_ADDR(VDEC2_MINDEX3_REG)
#define VDEC2_MINDEX4_REG 0x230e 	///../ucode/dos_register.h:6497
#define P_VDEC2_MINDEX4_REG 		DOS_REG_ADDR(VDEC2_MINDEX4_REG)
#define VDEC2_MINDEX5_REG 0x230f 	///../ucode/dos_register.h:6498
#define P_VDEC2_MINDEX5_REG 		DOS_REG_ADDR(VDEC2_MINDEX5_REG)
#define VDEC2_MINDEX6_REG 0x2310 	///../ucode/dos_register.h:6499
#define P_VDEC2_MINDEX6_REG 		DOS_REG_ADDR(VDEC2_MINDEX6_REG)
#define VDEC2_MINDEX7_REG 0x2311 	///../ucode/dos_register.h:6500
#define P_VDEC2_MINDEX7_REG 		DOS_REG_ADDR(VDEC2_MINDEX7_REG)
#define VDEC2_MMIN_REG 0x2312 	///../ucode/dos_register.h:6501
#define P_VDEC2_MMIN_REG 		DOS_REG_ADDR(VDEC2_MMIN_REG)
#define VDEC2_MMAX_REG 0x2313 	///../ucode/dos_register.h:6502
#define P_VDEC2_MMAX_REG 		DOS_REG_ADDR(VDEC2_MMAX_REG)
#define VDEC2_MBREAK0_REG 0x2314 	///../ucode/dos_register.h:6503
#define P_VDEC2_MBREAK0_REG 		DOS_REG_ADDR(VDEC2_MBREAK0_REG)
#define VDEC2_MBREAK1_REG 0x2315 	///../ucode/dos_register.h:6504
#define P_VDEC2_MBREAK1_REG 		DOS_REG_ADDR(VDEC2_MBREAK1_REG)
#define VDEC2_MBREAK2_REG 0x2316 	///../ucode/dos_register.h:6505
#define P_VDEC2_MBREAK2_REG 		DOS_REG_ADDR(VDEC2_MBREAK2_REG)
#define VDEC2_MBREAK3_REG 0x2317 	///../ucode/dos_register.h:6506
#define P_VDEC2_MBREAK3_REG 		DOS_REG_ADDR(VDEC2_MBREAK3_REG)
#define VDEC2_MBREAK_TYPE 0x2318 	///../ucode/dos_register.h:6507
#define P_VDEC2_MBREAK_TYPE 		DOS_REG_ADDR(VDEC2_MBREAK_TYPE)
#define VDEC2_MBREAK_CTRL 0x2319 	///../ucode/dos_register.h:6508
#define P_VDEC2_MBREAK_CTRL 		DOS_REG_ADDR(VDEC2_MBREAK_CTRL)
#define VDEC2_MBREAK_STAUTS 0x231a 	///../ucode/dos_register.h:6509
#define P_VDEC2_MBREAK_STAUTS 		DOS_REG_ADDR(VDEC2_MBREAK_STAUTS)
#define VDEC2_MDB_ADDR_REG 0x231b 	///../ucode/dos_register.h:6510
#define P_VDEC2_MDB_ADDR_REG 		DOS_REG_ADDR(VDEC2_MDB_ADDR_REG)
#define VDEC2_MDB_DATA_REG 0x231c 	///../ucode/dos_register.h:6511
#define P_VDEC2_MDB_DATA_REG 		DOS_REG_ADDR(VDEC2_MDB_DATA_REG)
#define VDEC2_MDB_CTRL 0x231d 	///../ucode/dos_register.h:6512
#define P_VDEC2_MDB_CTRL 		DOS_REG_ADDR(VDEC2_MDB_CTRL)
#define VDEC2_MSFTINT0 0x231e 	///../ucode/dos_register.h:6513
#define P_VDEC2_MSFTINT0 		DOS_REG_ADDR(VDEC2_MSFTINT0)
#define VDEC2_MSFTINT1 0x231f 	///../ucode/dos_register.h:6514
#define P_VDEC2_MSFTINT1 		DOS_REG_ADDR(VDEC2_MSFTINT1)
#define VDEC2_CSP 0x2320 	///../ucode/dos_register.h:6515
#define P_VDEC2_CSP 		DOS_REG_ADDR(VDEC2_CSP)
#define VDEC2_CPSR 0x2321 	///../ucode/dos_register.h:6516
#define P_VDEC2_CPSR 		DOS_REG_ADDR(VDEC2_CPSR)
#define VDEC2_CINT_VEC_BASE 0x2322 	///../ucode/dos_register.h:6517
#define P_VDEC2_CINT_VEC_BASE 		DOS_REG_ADDR(VDEC2_CINT_VEC_BASE)
#define VDEC2_CCPU_INTR_GRP 0x2323 	///../ucode/dos_register.h:6518
#define P_VDEC2_CCPU_INTR_GRP 		DOS_REG_ADDR(VDEC2_CCPU_INTR_GRP)
#define VDEC2_CCPU_INTR_MSK 0x2324 	///../ucode/dos_register.h:6519
#define P_VDEC2_CCPU_INTR_MSK 		DOS_REG_ADDR(VDEC2_CCPU_INTR_MSK)
#define VDEC2_CCPU_INTR_REQ 0x2325 	///../ucode/dos_register.h:6520
#define P_VDEC2_CCPU_INTR_REQ 		DOS_REG_ADDR(VDEC2_CCPU_INTR_REQ)
#define VDEC2_CPC_P 0x2326 	///../ucode/dos_register.h:6521
#define P_VDEC2_CPC_P 		DOS_REG_ADDR(VDEC2_CPC_P)
#define VDEC2_CPC_D 0x2327 	///../ucode/dos_register.h:6522
#define P_VDEC2_CPC_D 		DOS_REG_ADDR(VDEC2_CPC_D)
#define VDEC2_CPC_E 0x2328 	///../ucode/dos_register.h:6523
#define P_VDEC2_CPC_E 		DOS_REG_ADDR(VDEC2_CPC_E)
#define VDEC2_CPC_W 0x2329 	///../ucode/dos_register.h:6524
#define P_VDEC2_CPC_W 		DOS_REG_ADDR(VDEC2_CPC_W)
#define VDEC2_CINDEX0_REG 0x232a 	///../ucode/dos_register.h:6525
#define P_VDEC2_CINDEX0_REG 		DOS_REG_ADDR(VDEC2_CINDEX0_REG)
#define VDEC2_CINDEX1_REG 0x232b 	///../ucode/dos_register.h:6526
#define P_VDEC2_CINDEX1_REG 		DOS_REG_ADDR(VDEC2_CINDEX1_REG)
#define VDEC2_CINDEX2_REG 0x232c 	///../ucode/dos_register.h:6527
#define P_VDEC2_CINDEX2_REG 		DOS_REG_ADDR(VDEC2_CINDEX2_REG)
#define VDEC2_CINDEX3_REG 0x232d 	///../ucode/dos_register.h:6528
#define P_VDEC2_CINDEX3_REG 		DOS_REG_ADDR(VDEC2_CINDEX3_REG)
#define VDEC2_CINDEX4_REG 0x232e 	///../ucode/dos_register.h:6529
#define P_VDEC2_CINDEX4_REG 		DOS_REG_ADDR(VDEC2_CINDEX4_REG)
#define VDEC2_CINDEX5_REG 0x232f 	///../ucode/dos_register.h:6530
#define P_VDEC2_CINDEX5_REG 		DOS_REG_ADDR(VDEC2_CINDEX5_REG)
#define VDEC2_CINDEX6_REG 0x2330 	///../ucode/dos_register.h:6531
#define P_VDEC2_CINDEX6_REG 		DOS_REG_ADDR(VDEC2_CINDEX6_REG)
#define VDEC2_CINDEX7_REG 0x2331 	///../ucode/dos_register.h:6532
#define P_VDEC2_CINDEX7_REG 		DOS_REG_ADDR(VDEC2_CINDEX7_REG)
#define VDEC2_CMIN_REG 0x2332 	///../ucode/dos_register.h:6533
#define P_VDEC2_CMIN_REG 		DOS_REG_ADDR(VDEC2_CMIN_REG)
#define VDEC2_CMAX_REG 0x2333 	///../ucode/dos_register.h:6534
#define P_VDEC2_CMAX_REG 		DOS_REG_ADDR(VDEC2_CMAX_REG)
#define VDEC2_CBREAK0_REG 0x2334 	///../ucode/dos_register.h:6535
#define P_VDEC2_CBREAK0_REG 		DOS_REG_ADDR(VDEC2_CBREAK0_REG)
#define VDEC2_CBREAK1_REG 0x2335 	///../ucode/dos_register.h:6536
#define P_VDEC2_CBREAK1_REG 		DOS_REG_ADDR(VDEC2_CBREAK1_REG)
#define VDEC2_CBREAK2_REG 0x2336 	///../ucode/dos_register.h:6537
#define P_VDEC2_CBREAK2_REG 		DOS_REG_ADDR(VDEC2_CBREAK2_REG)
#define VDEC2_CBREAK3_REG 0x2337 	///../ucode/dos_register.h:6538
#define P_VDEC2_CBREAK3_REG 		DOS_REG_ADDR(VDEC2_CBREAK3_REG)
#define VDEC2_CBREAK_TYPE 0x2338 	///../ucode/dos_register.h:6539
#define P_VDEC2_CBREAK_TYPE 		DOS_REG_ADDR(VDEC2_CBREAK_TYPE)
#define VDEC2_CBREAK_CTRL 0x2339 	///../ucode/dos_register.h:6540
#define P_VDEC2_CBREAK_CTRL 		DOS_REG_ADDR(VDEC2_CBREAK_CTRL)
#define VDEC2_CBREAK_STAUTS 0x233a 	///../ucode/dos_register.h:6541
#define P_VDEC2_CBREAK_STAUTS 		DOS_REG_ADDR(VDEC2_CBREAK_STAUTS)
#define VDEC2_CDB_ADDR_REG 0x233b 	///../ucode/dos_register.h:6542
#define P_VDEC2_CDB_ADDR_REG 		DOS_REG_ADDR(VDEC2_CDB_ADDR_REG)
#define VDEC2_CDB_DATA_REG 0x233c 	///../ucode/dos_register.h:6543
#define P_VDEC2_CDB_DATA_REG 		DOS_REG_ADDR(VDEC2_CDB_DATA_REG)
#define VDEC2_CDB_CTRL 0x233d 	///../ucode/dos_register.h:6544
#define P_VDEC2_CDB_CTRL 		DOS_REG_ADDR(VDEC2_CDB_CTRL)
#define VDEC2_CSFTINT0 0x233e 	///../ucode/dos_register.h:6545
#define P_VDEC2_CSFTINT0 		DOS_REG_ADDR(VDEC2_CSFTINT0)
#define VDEC2_CSFTINT1 0x233f 	///../ucode/dos_register.h:6546
#define P_VDEC2_CSFTINT1 		DOS_REG_ADDR(VDEC2_CSFTINT1)
#define VDEC2_IMEM_DMA_CTRL 0x2340 	///../ucode/dos_register.h:6547
#define P_VDEC2_IMEM_DMA_CTRL 		DOS_REG_ADDR(VDEC2_IMEM_DMA_CTRL)
#define VDEC2_IMEM_DMA_ADR 0x2341 	///../ucode/dos_register.h:6548
#define P_VDEC2_IMEM_DMA_ADR 		DOS_REG_ADDR(VDEC2_IMEM_DMA_ADR)
#define VDEC2_IMEM_DMA_COUNT 0x2342 	///../ucode/dos_register.h:6549
#define P_VDEC2_IMEM_DMA_COUNT 		DOS_REG_ADDR(VDEC2_IMEM_DMA_COUNT)
#define VDEC2_WRRSP_IMEM 0x2343 	///../ucode/dos_register.h:6553
#define P_VDEC2_WRRSP_IMEM 		DOS_REG_ADDR(VDEC2_WRRSP_IMEM)
#define VDEC2_LMEM_DMA_CTRL 0x2350 	///../ucode/dos_register.h:6554
#define P_VDEC2_LMEM_DMA_CTRL 		DOS_REG_ADDR(VDEC2_LMEM_DMA_CTRL)
#define VDEC2_LMEM_DMA_ADR 0x2351 	///../ucode/dos_register.h:6555
#define P_VDEC2_LMEM_DMA_ADR 		DOS_REG_ADDR(VDEC2_LMEM_DMA_ADR)
#define VDEC2_LMEM_DMA_COUNT 0x2352 	///../ucode/dos_register.h:6556
#define P_VDEC2_LMEM_DMA_COUNT 		DOS_REG_ADDR(VDEC2_LMEM_DMA_COUNT)
#define VDEC2_WRRSP_LMEM 0x2353 	///../ucode/dos_register.h:6560
#define P_VDEC2_WRRSP_LMEM 		DOS_REG_ADDR(VDEC2_WRRSP_LMEM)
#define VDEC2_MAC_CTRL1 0x2360 	///../ucode/dos_register.h:6561
#define P_VDEC2_MAC_CTRL1 		DOS_REG_ADDR(VDEC2_MAC_CTRL1)
#define VDEC2_ACC0REG1 0x2361 	///../ucode/dos_register.h:6562
#define P_VDEC2_ACC0REG1 		DOS_REG_ADDR(VDEC2_ACC0REG1)
#define VDEC2_ACC1REG1 0x2362 	///../ucode/dos_register.h:6563
#define P_VDEC2_ACC1REG1 		DOS_REG_ADDR(VDEC2_ACC1REG1)
#define VDEC2_MAC_CTRL2 0x2370 	///../ucode/dos_register.h:6564
#define P_VDEC2_MAC_CTRL2 		DOS_REG_ADDR(VDEC2_MAC_CTRL2)
#define VDEC2_ACC0REG2 0x2371 	///../ucode/dos_register.h:6565
#define P_VDEC2_ACC0REG2 		DOS_REG_ADDR(VDEC2_ACC0REG2)
#define VDEC2_ACC1REG2 0x2372 	///../ucode/dos_register.h:6566
#define P_VDEC2_ACC1REG2 		DOS_REG_ADDR(VDEC2_ACC1REG2)
#define VDEC2_CPU_TRACE 0x2380 	///../ucode/dos_register.h:6567
#define P_VDEC2_CPU_TRACE 		DOS_REG_ADDR(VDEC2_CPU_TRACE)
#define HEVC_MSP 0x3300 	///../ucode/dos_register.h:6580
#define P_HEVC_MSP 		DOS_REG_ADDR(HEVC_MSP)
#define HEVC_MPSR 0x3301 	///../ucode/dos_register.h:6581
#define P_HEVC_MPSR 		DOS_REG_ADDR(HEVC_MPSR)
#define HEVC_MINT_VEC_BASE 0x3302 	///../ucode/dos_register.h:6582
#define P_HEVC_MINT_VEC_BASE 		DOS_REG_ADDR(HEVC_MINT_VEC_BASE)
#define HEVC_MCPU_INTR_GRP 0x3303 	///../ucode/dos_register.h:6583
#define P_HEVC_MCPU_INTR_GRP 		DOS_REG_ADDR(HEVC_MCPU_INTR_GRP)
#define HEVC_MCPU_INTR_MSK 0x3304 	///../ucode/dos_register.h:6584
#define P_HEVC_MCPU_INTR_MSK 		DOS_REG_ADDR(HEVC_MCPU_INTR_MSK)
#define HEVC_MCPU_INTR_REQ 0x3305 	///../ucode/dos_register.h:6585
#define P_HEVC_MCPU_INTR_REQ 		DOS_REG_ADDR(HEVC_MCPU_INTR_REQ)
#define HEVC_MPC_P 0x3306 	///../ucode/dos_register.h:6586
#define P_HEVC_MPC_P 		DOS_REG_ADDR(HEVC_MPC_P)
#define HEVC_MPC_D 0x3307 	///../ucode/dos_register.h:6587
#define P_HEVC_MPC_D 		DOS_REG_ADDR(HEVC_MPC_D)
#define HEVC_MPC_E 0x3308 	///../ucode/dos_register.h:6588
#define P_HEVC_MPC_E 		DOS_REG_ADDR(HEVC_MPC_E)
#define HEVC_MPC_W 0x3309 	///../ucode/dos_register.h:6589
#define P_HEVC_MPC_W 		DOS_REG_ADDR(HEVC_MPC_W)
#define HEVC_MINDEX0_REG 0x330a 	///../ucode/dos_register.h:6590
#define P_HEVC_MINDEX0_REG 		DOS_REG_ADDR(HEVC_MINDEX0_REG)
#define HEVC_MINDEX1_REG 0x330b 	///../ucode/dos_register.h:6591
#define P_HEVC_MINDEX1_REG 		DOS_REG_ADDR(HEVC_MINDEX1_REG)
#define HEVC_MINDEX2_REG 0x330c 	///../ucode/dos_register.h:6592
#define P_HEVC_MINDEX2_REG 		DOS_REG_ADDR(HEVC_MINDEX2_REG)
#define HEVC_MINDEX3_REG 0x330d 	///../ucode/dos_register.h:6593
#define P_HEVC_MINDEX3_REG 		DOS_REG_ADDR(HEVC_MINDEX3_REG)
#define HEVC_MINDEX4_REG 0x330e 	///../ucode/dos_register.h:6594
#define P_HEVC_MINDEX4_REG 		DOS_REG_ADDR(HEVC_MINDEX4_REG)
#define HEVC_MINDEX5_REG 0x330f 	///../ucode/dos_register.h:6595
#define P_HEVC_MINDEX5_REG 		DOS_REG_ADDR(HEVC_MINDEX5_REG)
#define HEVC_MINDEX6_REG 0x3310 	///../ucode/dos_register.h:6596
#define P_HEVC_MINDEX6_REG 		DOS_REG_ADDR(HEVC_MINDEX6_REG)
#define HEVC_MINDEX7_REG 0x3311 	///../ucode/dos_register.h:6597
#define P_HEVC_MINDEX7_REG 		DOS_REG_ADDR(HEVC_MINDEX7_REG)
#define HEVC_MMIN_REG 0x3312 	///../ucode/dos_register.h:6598
#define P_HEVC_MMIN_REG 		DOS_REG_ADDR(HEVC_MMIN_REG)
#define HEVC_MMAX_REG 0x3313 	///../ucode/dos_register.h:6599
#define P_HEVC_MMAX_REG 		DOS_REG_ADDR(HEVC_MMAX_REG)
#define HEVC_MBREAK0_REG 0x3314 	///../ucode/dos_register.h:6600
#define P_HEVC_MBREAK0_REG 		DOS_REG_ADDR(HEVC_MBREAK0_REG)
#define HEVC_MBREAK1_REG 0x3315 	///../ucode/dos_register.h:6601
#define P_HEVC_MBREAK1_REG 		DOS_REG_ADDR(HEVC_MBREAK1_REG)
#define HEVC_MBREAK2_REG 0x3316 	///../ucode/dos_register.h:6602
#define P_HEVC_MBREAK2_REG 		DOS_REG_ADDR(HEVC_MBREAK2_REG)
#define HEVC_MBREAK3_REG 0x3317 	///../ucode/dos_register.h:6603
#define P_HEVC_MBREAK3_REG 		DOS_REG_ADDR(HEVC_MBREAK3_REG)
#define HEVC_MBREAK_TYPE 0x3318 	///../ucode/dos_register.h:6604
#define P_HEVC_MBREAK_TYPE 		DOS_REG_ADDR(HEVC_MBREAK_TYPE)
#define HEVC_MBREAK_CTRL 0x3319 	///../ucode/dos_register.h:6605
#define P_HEVC_MBREAK_CTRL 		DOS_REG_ADDR(HEVC_MBREAK_CTRL)
#define HEVC_MBREAK_STAUTS 0x331a 	///../ucode/dos_register.h:6606
#define P_HEVC_MBREAK_STAUTS 		DOS_REG_ADDR(HEVC_MBREAK_STAUTS)
#define HEVC_MDB_ADDR_REG 0x331b 	///../ucode/dos_register.h:6607
#define P_HEVC_MDB_ADDR_REG 		DOS_REG_ADDR(HEVC_MDB_ADDR_REG)
#define HEVC_MDB_DATA_REG 0x331c 	///../ucode/dos_register.h:6608
#define P_HEVC_MDB_DATA_REG 		DOS_REG_ADDR(HEVC_MDB_DATA_REG)
#define HEVC_MDB_CTRL 0x331d 	///../ucode/dos_register.h:6609
#define P_HEVC_MDB_CTRL 		DOS_REG_ADDR(HEVC_MDB_CTRL)
#define HEVC_MSFTINT0 0x331e 	///../ucode/dos_register.h:6610
#define P_HEVC_MSFTINT0 		DOS_REG_ADDR(HEVC_MSFTINT0)
#define HEVC_MSFTINT1 0x331f 	///../ucode/dos_register.h:6611
#define P_HEVC_MSFTINT1 		DOS_REG_ADDR(HEVC_MSFTINT1)
#define HEVC_CSP 0x3320 	///../ucode/dos_register.h:6612
#define P_HEVC_CSP 		DOS_REG_ADDR(HEVC_CSP)
#define HEVC_CPSR 0x3321 	///../ucode/dos_register.h:6613
#define P_HEVC_CPSR 		DOS_REG_ADDR(HEVC_CPSR)
#define HEVC_CINT_VEC_BASE 0x3322 	///../ucode/dos_register.h:6614
#define P_HEVC_CINT_VEC_BASE 		DOS_REG_ADDR(HEVC_CINT_VEC_BASE)
#define HEVC_CCPU_INTR_GRP 0x3323 	///../ucode/dos_register.h:6615
#define P_HEVC_CCPU_INTR_GRP 		DOS_REG_ADDR(HEVC_CCPU_INTR_GRP)
#define HEVC_CCPU_INTR_MSK 0x3324 	///../ucode/dos_register.h:6616
#define P_HEVC_CCPU_INTR_MSK 		DOS_REG_ADDR(HEVC_CCPU_INTR_MSK)
#define HEVC_CCPU_INTR_REQ 0x3325 	///../ucode/dos_register.h:6617
#define P_HEVC_CCPU_INTR_REQ 		DOS_REG_ADDR(HEVC_CCPU_INTR_REQ)
#define HEVC_CPC_P 0x3326 	///../ucode/dos_register.h:6618
#define P_HEVC_CPC_P 		DOS_REG_ADDR(HEVC_CPC_P)
#define HEVC_CPC_D 0x3327 	///../ucode/dos_register.h:6619
#define P_HEVC_CPC_D 		DOS_REG_ADDR(HEVC_CPC_D)
#define HEVC_CPC_E 0x3328 	///../ucode/dos_register.h:6620
#define P_HEVC_CPC_E 		DOS_REG_ADDR(HEVC_CPC_E)
#define HEVC_CPC_W 0x3329 	///../ucode/dos_register.h:6621
#define P_HEVC_CPC_W 		DOS_REG_ADDR(HEVC_CPC_W)
#define HEVC_CINDEX0_REG 0x332a 	///../ucode/dos_register.h:6622
#define P_HEVC_CINDEX0_REG 		DOS_REG_ADDR(HEVC_CINDEX0_REG)
#define HEVC_CINDEX1_REG 0x332b 	///../ucode/dos_register.h:6623
#define P_HEVC_CINDEX1_REG 		DOS_REG_ADDR(HEVC_CINDEX1_REG)
#define HEVC_CINDEX2_REG 0x332c 	///../ucode/dos_register.h:6624
#define P_HEVC_CINDEX2_REG 		DOS_REG_ADDR(HEVC_CINDEX2_REG)
#define HEVC_CINDEX3_REG 0x332d 	///../ucode/dos_register.h:6625
#define P_HEVC_CINDEX3_REG 		DOS_REG_ADDR(HEVC_CINDEX3_REG)
#define HEVC_CINDEX4_REG 0x332e 	///../ucode/dos_register.h:6626
#define P_HEVC_CINDEX4_REG 		DOS_REG_ADDR(HEVC_CINDEX4_REG)
#define HEVC_CINDEX5_REG 0x332f 	///../ucode/dos_register.h:6627
#define P_HEVC_CINDEX5_REG 		DOS_REG_ADDR(HEVC_CINDEX5_REG)
#define HEVC_CINDEX6_REG 0x3330 	///../ucode/dos_register.h:6628
#define P_HEVC_CINDEX6_REG 		DOS_REG_ADDR(HEVC_CINDEX6_REG)
#define HEVC_CINDEX7_REG 0x3331 	///../ucode/dos_register.h:6629
#define P_HEVC_CINDEX7_REG 		DOS_REG_ADDR(HEVC_CINDEX7_REG)
#define HEVC_CMIN_REG 0x3332 	///../ucode/dos_register.h:6630
#define P_HEVC_CMIN_REG 		DOS_REG_ADDR(HEVC_CMIN_REG)
#define HEVC_CMAX_REG 0x3333 	///../ucode/dos_register.h:6631
#define P_HEVC_CMAX_REG 		DOS_REG_ADDR(HEVC_CMAX_REG)
#define HEVC_CBREAK0_REG 0x3334 	///../ucode/dos_register.h:6632
#define P_HEVC_CBREAK0_REG 		DOS_REG_ADDR(HEVC_CBREAK0_REG)
#define HEVC_CBREAK1_REG 0x3335 	///../ucode/dos_register.h:6633
#define P_HEVC_CBREAK1_REG 		DOS_REG_ADDR(HEVC_CBREAK1_REG)
#define HEVC_CBREAK2_REG 0x3336 	///../ucode/dos_register.h:6634
#define P_HEVC_CBREAK2_REG 		DOS_REG_ADDR(HEVC_CBREAK2_REG)
#define HEVC_CBREAK3_REG 0x3337 	///../ucode/dos_register.h:6635
#define P_HEVC_CBREAK3_REG 		DOS_REG_ADDR(HEVC_CBREAK3_REG)
#define HEVC_CBREAK_TYPE 0x3338 	///../ucode/dos_register.h:6636
#define P_HEVC_CBREAK_TYPE 		DOS_REG_ADDR(HEVC_CBREAK_TYPE)
#define HEVC_CBREAK_CTRL 0x3339 	///../ucode/dos_register.h:6637
#define P_HEVC_CBREAK_CTRL 		DOS_REG_ADDR(HEVC_CBREAK_CTRL)
#define HEVC_CBREAK_STAUTS 0x333a 	///../ucode/dos_register.h:6638
#define P_HEVC_CBREAK_STAUTS 		DOS_REG_ADDR(HEVC_CBREAK_STAUTS)
#define HEVC_CDB_ADDR_REG 0x333b 	///../ucode/dos_register.h:6639
#define P_HEVC_CDB_ADDR_REG 		DOS_REG_ADDR(HEVC_CDB_ADDR_REG)
#define HEVC_CDB_DATA_REG 0x333c 	///../ucode/dos_register.h:6640
#define P_HEVC_CDB_DATA_REG 		DOS_REG_ADDR(HEVC_CDB_DATA_REG)
#define HEVC_CDB_CTRL 0x333d 	///../ucode/dos_register.h:6641
#define P_HEVC_CDB_CTRL 		DOS_REG_ADDR(HEVC_CDB_CTRL)
#define HEVC_CSFTINT0 0x333e 	///../ucode/dos_register.h:6642
#define P_HEVC_CSFTINT0 		DOS_REG_ADDR(HEVC_CSFTINT0)
#define HEVC_CSFTINT1 0x333f 	///../ucode/dos_register.h:6643
#define P_HEVC_CSFTINT1 		DOS_REG_ADDR(HEVC_CSFTINT1)
#define HEVC_IMEM_DMA_CTRL 0x3340 	///../ucode/dos_register.h:6644
#define P_HEVC_IMEM_DMA_CTRL 		DOS_REG_ADDR(HEVC_IMEM_DMA_CTRL)
#define HEVC_IMEM_DMA_ADR 0x3341 	///../ucode/dos_register.h:6645
#define P_HEVC_IMEM_DMA_ADR 		DOS_REG_ADDR(HEVC_IMEM_DMA_ADR)
#define HEVC_IMEM_DMA_COUNT 0x3342 	///../ucode/dos_register.h:6646
#define P_HEVC_IMEM_DMA_COUNT 		DOS_REG_ADDR(HEVC_IMEM_DMA_COUNT)
#define HEVC_WRRSP_IMEM 0x3343 	///../ucode/dos_register.h:6650
#define P_HEVC_WRRSP_IMEM 		DOS_REG_ADDR(HEVC_WRRSP_IMEM)
#define HEVC_LMEM_DMA_CTRL 0x3350 	///../ucode/dos_register.h:6651
#define P_HEVC_LMEM_DMA_CTRL 		DOS_REG_ADDR(HEVC_LMEM_DMA_CTRL)
#define HEVC_LMEM_DMA_ADR 0x3351 	///../ucode/dos_register.h:6652
#define P_HEVC_LMEM_DMA_ADR 		DOS_REG_ADDR(HEVC_LMEM_DMA_ADR)
#define HEVC_LMEM_DMA_COUNT 0x3352 	///../ucode/dos_register.h:6653
#define P_HEVC_LMEM_DMA_COUNT 		DOS_REG_ADDR(HEVC_LMEM_DMA_COUNT)
#define HEVC_WRRSP_LMEM 0x3353 	///../ucode/dos_register.h:6657
#define P_HEVC_WRRSP_LMEM 		DOS_REG_ADDR(HEVC_WRRSP_LMEM)
#define HEVC_MAC_CTRL1 0x3360 	///../ucode/dos_register.h:6658
#define P_HEVC_MAC_CTRL1 		DOS_REG_ADDR(HEVC_MAC_CTRL1)
#define HEVC_ACC0REG1 0x3361 	///../ucode/dos_register.h:6659
#define P_HEVC_ACC0REG1 		DOS_REG_ADDR(HEVC_ACC0REG1)
#define HEVC_ACC1REG1 0x3362 	///../ucode/dos_register.h:6660
#define P_HEVC_ACC1REG1 		DOS_REG_ADDR(HEVC_ACC1REG1)
#define HEVC_MAC_CTRL2 0x3370 	///../ucode/dos_register.h:6661
#define P_HEVC_MAC_CTRL2 		DOS_REG_ADDR(HEVC_MAC_CTRL2)
#define HEVC_ACC0REG2 0x3371 	///../ucode/dos_register.h:6662
#define P_HEVC_ACC0REG2 		DOS_REG_ADDR(HEVC_ACC0REG2)
#define HEVC_ACC1REG2 0x3372 	///../ucode/dos_register.h:6663
#define P_HEVC_ACC1REG2 		DOS_REG_ADDR(HEVC_ACC1REG2)
#define HEVC_CPU_TRACE 0x3380 	///../ucode/dos_register.h:6664
#define P_HEVC_CPU_TRACE 		DOS_REG_ADDR(HEVC_CPU_TRACE)
#define HCODEC_HENC_SCRATCH_0 0x1ac0 	///../ucode/dos_register.h:6677
#define P_HCODEC_HENC_SCRATCH_0 		DOS_REG_ADDR(HCODEC_HENC_SCRATCH_0)
#define HCODEC_HENC_SCRATCH_1 0x1ac1 	///../ucode/dos_register.h:6678
#define P_HCODEC_HENC_SCRATCH_1 		DOS_REG_ADDR(HCODEC_HENC_SCRATCH_1)
#define HCODEC_HENC_SCRATCH_2 0x1ac2 	///../ucode/dos_register.h:6679
#define P_HCODEC_HENC_SCRATCH_2 		DOS_REG_ADDR(HCODEC_HENC_SCRATCH_2)
#define HCODEC_HENC_SCRATCH_3 0x1ac3 	///../ucode/dos_register.h:6680
#define P_HCODEC_HENC_SCRATCH_3 		DOS_REG_ADDR(HCODEC_HENC_SCRATCH_3)
#define HCODEC_HENC_SCRATCH_4 0x1ac4 	///../ucode/dos_register.h:6681
#define P_HCODEC_HENC_SCRATCH_4 		DOS_REG_ADDR(HCODEC_HENC_SCRATCH_4)
#define HCODEC_HENC_SCRATCH_5 0x1ac5 	///../ucode/dos_register.h:6682
#define P_HCODEC_HENC_SCRATCH_5 		DOS_REG_ADDR(HCODEC_HENC_SCRATCH_5)
#define HCODEC_HENC_SCRATCH_6 0x1ac6 	///../ucode/dos_register.h:6683
#define P_HCODEC_HENC_SCRATCH_6 		DOS_REG_ADDR(HCODEC_HENC_SCRATCH_6)
#define HCODEC_HENC_SCRATCH_7 0x1ac7 	///../ucode/dos_register.h:6684
#define P_HCODEC_HENC_SCRATCH_7 		DOS_REG_ADDR(HCODEC_HENC_SCRATCH_7)
#define HCODEC_HENC_SCRATCH_8 0x1ac8 	///../ucode/dos_register.h:6685
#define P_HCODEC_HENC_SCRATCH_8 		DOS_REG_ADDR(HCODEC_HENC_SCRATCH_8)
#define HCODEC_HENC_SCRATCH_9 0x1ac9 	///../ucode/dos_register.h:6686
#define P_HCODEC_HENC_SCRATCH_9 		DOS_REG_ADDR(HCODEC_HENC_SCRATCH_9)
#define HCODEC_HENC_SCRATCH_A 0x1aca 	///../ucode/dos_register.h:6687
#define P_HCODEC_HENC_SCRATCH_A 		DOS_REG_ADDR(HCODEC_HENC_SCRATCH_A)
#define HCODEC_HENC_SCRATCH_B 0x1acb 	///../ucode/dos_register.h:6688
#define P_HCODEC_HENC_SCRATCH_B 		DOS_REG_ADDR(HCODEC_HENC_SCRATCH_B)
#define HCODEC_HENC_SCRATCH_C 0x1acc 	///../ucode/dos_register.h:6689
#define P_HCODEC_HENC_SCRATCH_C 		DOS_REG_ADDR(HCODEC_HENC_SCRATCH_C)
#define HCODEC_HENC_SCRATCH_D 0x1acd 	///../ucode/dos_register.h:6690
#define P_HCODEC_HENC_SCRATCH_D 		DOS_REG_ADDR(HCODEC_HENC_SCRATCH_D)
#define HCODEC_HENC_SCRATCH_E 0x1ace 	///../ucode/dos_register.h:6691
#define P_HCODEC_HENC_SCRATCH_E 		DOS_REG_ADDR(HCODEC_HENC_SCRATCH_E)
#define HCODEC_HENC_SCRATCH_F 0x1acf 	///../ucode/dos_register.h:6692
#define P_HCODEC_HENC_SCRATCH_F 		DOS_REG_ADDR(HCODEC_HENC_SCRATCH_F)
#define HCODEC_HENC_SCRATCH_G 0x1ad0 	///../ucode/dos_register.h:6693
#define P_HCODEC_HENC_SCRATCH_G 		DOS_REG_ADDR(HCODEC_HENC_SCRATCH_G)
#define HCODEC_HENC_SCRATCH_H 0x1ad1 	///../ucode/dos_register.h:6694
#define P_HCODEC_HENC_SCRATCH_H 		DOS_REG_ADDR(HCODEC_HENC_SCRATCH_H)
#define HCODEC_HENC_SCRATCH_I 0x1ad2 	///../ucode/dos_register.h:6695
#define P_HCODEC_HENC_SCRATCH_I 		DOS_REG_ADDR(HCODEC_HENC_SCRATCH_I)
#define HCODEC_HENC_SCRATCH_J 0x1ad3 	///../ucode/dos_register.h:6696
#define P_HCODEC_HENC_SCRATCH_J 		DOS_REG_ADDR(HCODEC_HENC_SCRATCH_J)
#define HCODEC_HENC_SCRATCH_K 0x1ad4 	///../ucode/dos_register.h:6697
#define P_HCODEC_HENC_SCRATCH_K 		DOS_REG_ADDR(HCODEC_HENC_SCRATCH_K)
#define HCODEC_HENC_SCRATCH_L 0x1ad5 	///../ucode/dos_register.h:6698
#define P_HCODEC_HENC_SCRATCH_L 		DOS_REG_ADDR(HCODEC_HENC_SCRATCH_L)
#define HCODEC_HENC_SCRATCH_M 0x1ad6 	///../ucode/dos_register.h:6699
#define P_HCODEC_HENC_SCRATCH_M 		DOS_REG_ADDR(HCODEC_HENC_SCRATCH_M)
#define HCODEC_HENC_SCRATCH_N 0x1ad7 	///../ucode/dos_register.h:6700
#define P_HCODEC_HENC_SCRATCH_N 		DOS_REG_ADDR(HCODEC_HENC_SCRATCH_N)
#define HCODEC_IE_DATA_FEED_BUFF_INFO 0x1ad8 	///../ucode/dos_register.h:6702
#define P_HCODEC_IE_DATA_FEED_BUFF_INFO 		DOS_REG_ADDR(HCODEC_IE_DATA_FEED_BUFF_INFO)
#define HCODEC_VLC_STATUS_CTRL 0x1d00 	///../ucode/dos_register.h:6725
#define P_HCODEC_VLC_STATUS_CTRL 		DOS_REG_ADDR(HCODEC_VLC_STATUS_CTRL)
#define HCODEC_VLC_CONFIG 0x1d01 	///../ucode/dos_register.h:6743
#define P_HCODEC_VLC_CONFIG 		DOS_REG_ADDR(HCODEC_VLC_CONFIG)
#define HCODEC_VLC_VB_START_PTR 0x1d10 	///../ucode/dos_register.h:6747
#define P_HCODEC_VLC_VB_START_PTR 		DOS_REG_ADDR(HCODEC_VLC_VB_START_PTR)
#define HCODEC_VLC_VB_END_PTR 0x1d11 	///../ucode/dos_register.h:6748
#define P_HCODEC_VLC_VB_END_PTR 		DOS_REG_ADDR(HCODEC_VLC_VB_END_PTR)
#define HCODEC_VLC_VB_WR_PTR 0x1d12 	///../ucode/dos_register.h:6749
#define P_HCODEC_VLC_VB_WR_PTR 		DOS_REG_ADDR(HCODEC_VLC_VB_WR_PTR)
#define HCODEC_VLC_VB_RD_PTR 0x1d13 	///../ucode/dos_register.h:6751
#define P_HCODEC_VLC_VB_RD_PTR 		DOS_REG_ADDR(HCODEC_VLC_VB_RD_PTR)
#define HCODEC_VLC_VB_SW_RD_PTR 0x1d14 	///../ucode/dos_register.h:6752
#define P_HCODEC_VLC_VB_SW_RD_PTR 		DOS_REG_ADDR(HCODEC_VLC_VB_SW_RD_PTR)
#define HCODEC_VLC_VB_LEFT 0x1d15 	///../ucode/dos_register.h:6754
#define P_HCODEC_VLC_VB_LEFT 		DOS_REG_ADDR(HCODEC_VLC_VB_LEFT)
#define HCODEC_VLC_VB_CONTROL 0x1d16 	///../ucode/dos_register.h:6780
#define P_HCODEC_VLC_VB_CONTROL 		DOS_REG_ADDR(HCODEC_VLC_VB_CONTROL)
#define HCODEC_VLC_VB_MEM_CTL 0x1d17 	///../ucode/dos_register.h:6787
#define P_HCODEC_VLC_VB_MEM_CTL 		DOS_REG_ADDR(HCODEC_VLC_VB_MEM_CTL)
#define HCODEC_VLC_VB_INT_PTR 0x1d18 	///../ucode/dos_register.h:6789
#define P_HCODEC_VLC_VB_INT_PTR 		DOS_REG_ADDR(HCODEC_VLC_VB_INT_PTR)
#define HCODEC_VLC_WRRSP 0x1d19 	///../ucode/dos_register.h:6792
#define P_HCODEC_VLC_WRRSP 		DOS_REG_ADDR(HCODEC_VLC_WRRSP)
#define HCODEC_VLC_TOTAL_BYTES 0x1d1a 	///../ucode/dos_register.h:6793
#define P_HCODEC_VLC_TOTAL_BYTES 		DOS_REG_ADDR(HCODEC_VLC_TOTAL_BYTES)
#define HCODEC_VLC_VB_BUFF 0x1d1b 	///../ucode/dos_register.h:6800
#define P_HCODEC_VLC_VB_BUFF 		DOS_REG_ADDR(HCODEC_VLC_VB_BUFF)
#define HCODEC_VLC_VB_PRE_BUFF_HI 0x1d1c 	///../ucode/dos_register.h:6805
#define P_HCODEC_VLC_VB_PRE_BUFF_HI 		DOS_REG_ADDR(HCODEC_VLC_VB_PRE_BUFF_HI)
#define HCODEC_VLC_VB_PRE_BUFF_LOW 0x1d1d 	///../ucode/dos_register.h:6807
#define P_HCODEC_VLC_VB_PRE_BUFF_LOW 		DOS_REG_ADDR(HCODEC_VLC_VB_PRE_BUFF_LOW)
#define HCODEC_VLC_STREAM_BUFF 0x1d1e 	///../ucode/dos_register.h:6812
#define P_HCODEC_VLC_STREAM_BUFF 		DOS_REG_ADDR(HCODEC_VLC_STREAM_BUFF)
#define HCODEC_VLC_PUSH_STREAM 0x1d1f 	///../ucode/dos_register.h:6826
#define P_HCODEC_VLC_PUSH_STREAM 		DOS_REG_ADDR(HCODEC_VLC_PUSH_STREAM)
#define HCODEC_VLC_PUSH_ELEMENT 0x1d20 	///../ucode/dos_register.h:6830
#define P_HCODEC_VLC_PUSH_ELEMENT 		DOS_REG_ADDR(HCODEC_VLC_PUSH_ELEMENT)
#define HCODEC_VLC_ELEMENT_DATA 0x1d21 	///../ucode/dos_register.h:6831
#define P_HCODEC_VLC_ELEMENT_DATA 		DOS_REG_ADDR(HCODEC_VLC_ELEMENT_DATA)
#define HCODEC_VLC_INT_CONTROL 0x1d30 	///../ucode/dos_register.h:6868
#define P_HCODEC_VLC_INT_CONTROL 		DOS_REG_ADDR(HCODEC_VLC_INT_CONTROL)
#define HCODEC_VLC_PIC_SIZE 0x1d31 	///../ucode/dos_register.h:6871
#define P_HCODEC_VLC_PIC_SIZE 		DOS_REG_ADDR(HCODEC_VLC_PIC_SIZE)
#define HCODEC_VLC_PIC_INFO 0x1d32 	///../ucode/dos_register.h:6875
#define P_HCODEC_VLC_PIC_INFO 		DOS_REG_ADDR(HCODEC_VLC_PIC_INFO)
#define HCODEC_VLC_PIC_POSITION 0x1d33 	///../ucode/dos_register.h:6879
#define P_HCODEC_VLC_PIC_POSITION 		DOS_REG_ADDR(HCODEC_VLC_PIC_POSITION)
#define HCODEC_VLC_INPUT_STATUS 0x1d34 	///../ucode/dos_register.h:6898
#define P_HCODEC_VLC_INPUT_STATUS 		DOS_REG_ADDR(HCODEC_VLC_INPUT_STATUS)
#define HCODEC_VLC_MB_INFO 0x1d35 	///../ucode/dos_register.h:6903
#define P_HCODEC_VLC_MB_INFO 		DOS_REG_ADDR(HCODEC_VLC_MB_INFO)
#define HCODEC_VLC_ENC_PEND_CMD 0x1d36 	///../ucode/dos_register.h:6915
#define P_HCODEC_VLC_ENC_PEND_CMD 		DOS_REG_ADDR(HCODEC_VLC_ENC_PEND_CMD)
#define HCODEC_HENC_TOP_INFO_0 0x1d37 	///../ucode/dos_register.h:6919
#define P_HCODEC_HENC_TOP_INFO_0 		DOS_REG_ADDR(HCODEC_HENC_TOP_INFO_0)
#define HCODEC_HENC_LEFT_INFO_0 0x1d38 	///../ucode/dos_register.h:6920
#define P_HCODEC_HENC_LEFT_INFO_0 		DOS_REG_ADDR(HCODEC_HENC_LEFT_INFO_0)
#define HCODEC_HENC_TOP_INFO_1 0x1d39 	///../ucode/dos_register.h:6925
#define P_HCODEC_HENC_TOP_INFO_1 		DOS_REG_ADDR(HCODEC_HENC_TOP_INFO_1)
#define HCODEC_HENC_LEFT_INFO_1 0x1d3a 	///../ucode/dos_register.h:6926
#define P_HCODEC_HENC_LEFT_INFO_1 		DOS_REG_ADDR(HCODEC_HENC_LEFT_INFO_1)
#define HCODEC_VLC_IPRED_MODE_HI 0x1d3b 	///../ucode/dos_register.h:6928
#define P_HCODEC_VLC_IPRED_MODE_HI 		DOS_REG_ADDR(HCODEC_VLC_IPRED_MODE_HI)
#define HCODEC_VLC_IPRED_MODE_LO 0x1d3c 	///../ucode/dos_register.h:6929
#define P_HCODEC_VLC_IPRED_MODE_LO 		DOS_REG_ADDR(HCODEC_VLC_IPRED_MODE_LO)
#define HCODEC_VLC_DELTA_QP 0x1d3d 	///../ucode/dos_register.h:6932
#define P_HCODEC_VLC_DELTA_QP 		DOS_REG_ADDR(HCODEC_VLC_DELTA_QP)
#define HCODEC_VLC_MB_HEADER_INFO 0x1d3e 	///../ucode/dos_register.h:6937
#define P_HCODEC_VLC_MB_HEADER_INFO 		DOS_REG_ADDR(HCODEC_VLC_MB_HEADER_INFO)
#define HCODEC_VLC_P_MB_HEADER_INFO 0x1d3f 	///../ucode/dos_register.h:6940
#define P_HCODEC_VLC_P_MB_HEADER_INFO 		DOS_REG_ADDR(HCODEC_VLC_P_MB_HEADER_INFO)
#define HCODEC_VLC_COEFF_BUF_STATUS 0x1d40 	///../ucode/dos_register.h:6946
#define P_HCODEC_VLC_COEFF_BUF_STATUS 		DOS_REG_ADDR(HCODEC_VLC_COEFF_BUF_STATUS)
#define HCODEC_VLC_COEFF_RD_REQ 0x1d41 	///../ucode/dos_register.h:6949
#define P_HCODEC_VLC_COEFF_RD_REQ 		DOS_REG_ADDR(HCODEC_VLC_COEFF_RD_REQ)
#define HCODEC_VLC_COEFF 0x1d42 	///../ucode/dos_register.h:6954
#define P_HCODEC_VLC_COEFF 		DOS_REG_ADDR(HCODEC_VLC_COEFF)
#define HCODEC_VLC_COEFF_INFO 0x1d43 	///../ucode/dos_register.h:6962
#define P_HCODEC_VLC_COEFF_INFO 		DOS_REG_ADDR(HCODEC_VLC_COEFF_INFO)
#define HCODEC_VLC_DC_BUF_STATUS 0x1d44 	///../ucode/dos_register.h:6971
#define P_HCODEC_VLC_DC_BUF_STATUS 		DOS_REG_ADDR(HCODEC_VLC_DC_BUF_STATUS)
#define HCODEC_VLC_DC_RD_REQ 0x1d45 	///../ucode/dos_register.h:6975
#define P_HCODEC_VLC_DC_RD_REQ 		DOS_REG_ADDR(HCODEC_VLC_DC_RD_REQ)
#define HCODEC_VLC_DC 0x1d46 	///../ucode/dos_register.h:6980
#define P_HCODEC_VLC_DC 		DOS_REG_ADDR(HCODEC_VLC_DC)
#define HCODEC_VLC_DC_INFO 0x1d47 	///../ucode/dos_register.h:6989
#define P_HCODEC_VLC_DC_INFO 		DOS_REG_ADDR(HCODEC_VLC_DC_INFO)
#define HCODEC_VLC_MV_INDEX 0x1d48 	///../ucode/dos_register.h:6992
#define P_HCODEC_VLC_MV_INDEX 		DOS_REG_ADDR(HCODEC_VLC_MV_INDEX)
#define HCODEC_VLC_MV 0x1d49 	///../ucode/dos_register.h:6995
#define P_HCODEC_VLC_MV 		DOS_REG_ADDR(HCODEC_VLC_MV)
#define HCODEC_HENC_TOP_MV_0 0x1d4a 	///../ucode/dos_register.h:7000
#define P_HCODEC_HENC_TOP_MV_0 		DOS_REG_ADDR(HCODEC_HENC_TOP_MV_0)
#define HCODEC_HENC_TOP_MV_1 0x1d4b 	///../ucode/dos_register.h:7001
#define P_HCODEC_HENC_TOP_MV_1 		DOS_REG_ADDR(HCODEC_HENC_TOP_MV_1)
#define HCODEC_HENC_TOP_MV_2 0x1d4c 	///../ucode/dos_register.h:7002
#define P_HCODEC_HENC_TOP_MV_2 		DOS_REG_ADDR(HCODEC_HENC_TOP_MV_2)
#define HCODEC_HENC_TOP_MV_3 0x1d4d 	///../ucode/dos_register.h:7003
#define P_HCODEC_HENC_TOP_MV_3 		DOS_REG_ADDR(HCODEC_HENC_TOP_MV_3)
#define HCODEC_HENC_LEFT_MV_0 0x1d4e 	///../ucode/dos_register.h:7004
#define P_HCODEC_HENC_LEFT_MV_0 		DOS_REG_ADDR(HCODEC_HENC_LEFT_MV_0)
#define HCODEC_HENC_LEFT_MV_1 0x1d4f 	///../ucode/dos_register.h:7005
#define P_HCODEC_HENC_LEFT_MV_1 		DOS_REG_ADDR(HCODEC_HENC_LEFT_MV_1)
#define HCODEC_HENC_LEFT_MV_2 0x1d50 	///../ucode/dos_register.h:7006
#define P_HCODEC_HENC_LEFT_MV_2 		DOS_REG_ADDR(HCODEC_HENC_LEFT_MV_2)
#define HCODEC_HENC_LEFT_MV_3 0x1d51 	///../ucode/dos_register.h:7007
#define P_HCODEC_HENC_LEFT_MV_3 		DOS_REG_ADDR(HCODEC_HENC_LEFT_MV_3)
#define HCODEC_TOP_LEFT_READY 0x1d52 	///../ucode/dos_register.h:7010
#define P_HCODEC_TOP_LEFT_READY 		DOS_REG_ADDR(HCODEC_TOP_LEFT_READY)
#define HCODEC_MB_SKIP_RUN 0x1d53 	///../ucode/dos_register.h:7013
#define P_HCODEC_MB_SKIP_RUN 		DOS_REG_ADDR(HCODEC_MB_SKIP_RUN)
#define HCODEC_VLC_HCMD_CONFIG 0x1d54 	///../ucode/dos_register.h:7020
#define P_HCODEC_VLC_HCMD_CONFIG 		DOS_REG_ADDR(HCODEC_VLC_HCMD_CONFIG)
#define HCODEC_VLC_HCMD_DBLK_INFO 0x1d55 	///../ucode/dos_register.h:7022
#define P_HCODEC_VLC_HCMD_DBLK_INFO 		DOS_REG_ADDR(HCODEC_VLC_HCMD_DBLK_INFO)
#define HCODEC_VLC_DBG_IDX 0x1d56 	///../ucode/dos_register.h:7024
#define P_HCODEC_VLC_DBG_IDX 		DOS_REG_ADDR(HCODEC_VLC_DBG_IDX)
#define HCODEC_VLC_DBG_READ 0x1d57 	///../ucode/dos_register.h:7026
#define P_HCODEC_VLC_DBG_READ 		DOS_REG_ADDR(HCODEC_VLC_DBG_READ)
#define HCODEC_VLC_JPEG_CTRL 0x1d58 	///../ucode/dos_register.h:7027
#define P_HCODEC_VLC_JPEG_CTRL 		DOS_REG_ADDR(HCODEC_VLC_JPEG_CTRL)
#define HCODEC_VLC_JPEG_COEFF_BUF_STAT 0x1d59 	///../ucode/dos_register.h:7028
#define P_HCODEC_VLC_JPEG_COEFF_BUF_STAT 		DOS_REG_ADDR(HCODEC_VLC_JPEG_COEFF_BUF_STAT)
#define HCODEC_VLC_HUFFMAN_ADDR 0x1d5a 	///../ucode/dos_register.h:7029
#define P_HCODEC_VLC_HUFFMAN_ADDR 		DOS_REG_ADDR(HCODEC_VLC_HUFFMAN_ADDR)
#define HCODEC_VLC_HUFFMAN_DATA 0x1d5b 	///../ucode/dos_register.h:7030
#define P_HCODEC_VLC_HUFFMAN_DATA 		DOS_REG_ADDR(HCODEC_VLC_HUFFMAN_DATA)
#define HCODEC_VLC_ENC_MV_BITS 0x1d5c 	///../ucode/dos_register.h:7032
#define P_HCODEC_VLC_ENC_MV_BITS 		DOS_REG_ADDR(HCODEC_VLC_ENC_MV_BITS)
#define HCODEC_VLC_ENC_COEFF_BITS 0x1d5d 	///../ucode/dos_register.h:7034
#define P_HCODEC_VLC_ENC_COEFF_BITS 		DOS_REG_ADDR(HCODEC_VLC_ENC_COEFF_BITS)
#define HCODEC_QDCT_STATUS_CTRL 0x1f00 	///../ucode/dos_register.h:7048
#define P_HCODEC_QDCT_STATUS_CTRL 		DOS_REG_ADDR(HCODEC_QDCT_STATUS_CTRL)
#define HCODEC_QDCT_CONFIG 0x1f01 	///../ucode/dos_register.h:7068
#define P_HCODEC_QDCT_CONFIG 		DOS_REG_ADDR(HCODEC_QDCT_CONFIG)
#define HCODEC_IGNORE_CONFIG 0x1f02 	///../ucode/dos_register.h:7077
#define P_HCODEC_IGNORE_CONFIG 		DOS_REG_ADDR(HCODEC_IGNORE_CONFIG)
#define HCODEC_IGNORE_CONFIG_2 0x1f03 	///../ucode/dos_register.h:7083
#define P_HCODEC_IGNORE_CONFIG_2 		DOS_REG_ADDR(HCODEC_IGNORE_CONFIG_2)
#define HCODEC_QDCT_MB_START_PTR 0x1f10 	///../ucode/dos_register.h:7087
#define P_HCODEC_QDCT_MB_START_PTR 		DOS_REG_ADDR(HCODEC_QDCT_MB_START_PTR)
#define HCODEC_QDCT_MB_END_PTR 0x1f11 	///../ucode/dos_register.h:7088
#define P_HCODEC_QDCT_MB_END_PTR 		DOS_REG_ADDR(HCODEC_QDCT_MB_END_PTR)
#define HCODEC_QDCT_MB_WR_PTR 0x1f12 	///../ucode/dos_register.h:7089
#define P_HCODEC_QDCT_MB_WR_PTR 		DOS_REG_ADDR(HCODEC_QDCT_MB_WR_PTR)
#define HCODEC_QDCT_MB_RD_PTR 0x1f13 	///../ucode/dos_register.h:7090
#define P_HCODEC_QDCT_MB_RD_PTR 		DOS_REG_ADDR(HCODEC_QDCT_MB_RD_PTR)
#define HCODEC_QDCT_MB_LEVEL 0x1f14 	///../ucode/dos_register.h:7091
#define P_HCODEC_QDCT_MB_LEVEL 		DOS_REG_ADDR(HCODEC_QDCT_MB_LEVEL)
#define HCODEC_QDCT_MB_CONTROL 0x1f15 	///../ucode/dos_register.h:7122
#define P_HCODEC_QDCT_MB_CONTROL 		DOS_REG_ADDR(HCODEC_QDCT_MB_CONTROL)
#define HCODEC_QDCT_MB_MEM_CTL 0x1f16 	///../ucode/dos_register.h:7130
#define P_HCODEC_QDCT_MB_MEM_CTL 		DOS_REG_ADDR(HCODEC_QDCT_MB_MEM_CTL)
#define HCODEC_QDCT_MB_BUFF 0x1f17 	///../ucode/dos_register.h:7135
#define P_HCODEC_QDCT_MB_BUFF 		DOS_REG_ADDR(HCODEC_QDCT_MB_BUFF)
#define HCODEC_QDCT_MB_MAGIC_WORD 0x1f18 	///../ucode/dos_register.h:7137
#define P_HCODEC_QDCT_MB_MAGIC_WORD 		DOS_REG_ADDR(HCODEC_QDCT_MB_MAGIC_WORD)
#define HCODEC_QDCT_DCT_STATUS 0x1f19 	///../ucode/dos_register.h:7149
#define P_HCODEC_QDCT_DCT_STATUS 		DOS_REG_ADDR(HCODEC_QDCT_DCT_STATUS)
#define HCODEC_QDCT_Q_STATUS 0x1f1a 	///../ucode/dos_register.h:7151
#define P_HCODEC_QDCT_Q_STATUS 		DOS_REG_ADDR(HCODEC_QDCT_Q_STATUS)
#define HCODEC_QDCT_PIC_INFO 0x1f1b 	///../ucode/dos_register.h:7154
#define P_HCODEC_QDCT_PIC_INFO 		DOS_REG_ADDR(HCODEC_QDCT_PIC_INFO)
#define HCODEC_QDCT_Q_QUANT_I 0x1f1c 	///../ucode/dos_register.h:7164
#define P_HCODEC_QDCT_Q_QUANT_I 		DOS_REG_ADDR(HCODEC_QDCT_Q_QUANT_I)
#define HCODEC_QDCT_Q_QUANT_P 0x1f1d 	///../ucode/dos_register.h:7174
#define P_HCODEC_QDCT_Q_QUANT_P 		DOS_REG_ADDR(HCODEC_QDCT_Q_QUANT_P)
#define HCODEC_QDCT_MB_PAUSE_CTL 0x1f1e 	///../ucode/dos_register.h:7178
#define P_HCODEC_QDCT_MB_PAUSE_CTL 		DOS_REG_ADDR(HCODEC_QDCT_MB_PAUSE_CTL)
#define HCODEC_QDCT_TOP_CONTROL 0x1f1f 	///../ucode/dos_register.h:7192
#define P_HCODEC_QDCT_TOP_CONTROL 		DOS_REG_ADDR(HCODEC_QDCT_TOP_CONTROL)
#define HCODEC_QDCT_TOP_BASE_MEM 0x1f20 	///../ucode/dos_register.h:7194
#define P_HCODEC_QDCT_TOP_BASE_MEM 		DOS_REG_ADDR(HCODEC_QDCT_TOP_BASE_MEM)
#define HCODEC_QDCT_TOP_MEM_CTL 0x1f21 	///../ucode/dos_register.h:7199
#define P_HCODEC_QDCT_TOP_MEM_CTL 		DOS_REG_ADDR(HCODEC_QDCT_TOP_MEM_CTL)
#define HCODEC_QDCT_TOP_WRRSP 0x1f22 	///../ucode/dos_register.h:7201
#define P_HCODEC_QDCT_TOP_WRRSP 		DOS_REG_ADDR(HCODEC_QDCT_TOP_WRRSP)
#define HCODEC_QDCT_DBG_IDX 0x1f23 	///../ucode/dos_register.h:7203
#define P_HCODEC_QDCT_DBG_IDX 		DOS_REG_ADDR(HCODEC_QDCT_DBG_IDX)
#define HCODEC_QDCT_DBG_READ 0x1f24 	///../ucode/dos_register.h:7205
#define P_HCODEC_QDCT_DBG_READ 		DOS_REG_ADDR(HCODEC_QDCT_DBG_READ)
#define HCODEC_QDCT_JPEG_CTRL 0x1f25 	///../ucode/dos_register.h:7206
#define P_HCODEC_QDCT_JPEG_CTRL 		DOS_REG_ADDR(HCODEC_QDCT_JPEG_CTRL)
#define HCODEC_QDCT_JPEG_X_START_END 0x1f26 	///../ucode/dos_register.h:7207
#define P_HCODEC_QDCT_JPEG_X_START_END 		DOS_REG_ADDR(HCODEC_QDCT_JPEG_X_START_END)
#define HCODEC_QDCT_JPEG_Y_START_END 0x1f27 	///../ucode/dos_register.h:7208
#define P_HCODEC_QDCT_JPEG_Y_START_END 		DOS_REG_ADDR(HCODEC_QDCT_JPEG_Y_START_END)
#define HCODEC_QDCT_JPEG_QUANT_ADDR 0x1f28 	///../ucode/dos_register.h:7209
#define P_HCODEC_QDCT_JPEG_QUANT_ADDR 		DOS_REG_ADDR(HCODEC_QDCT_JPEG_QUANT_ADDR)
#define HCODEC_QDCT_JPEG_QUANT_DATA 0x1f29 	///../ucode/dos_register.h:7210
#define P_HCODEC_QDCT_JPEG_QUANT_DATA 		DOS_REG_ADDR(HCODEC_QDCT_JPEG_QUANT_DATA)
#define HCODEC_QDCT_JPEG_SOF_RESUME 0x1f2a 	///../ucode/dos_register.h:7211
#define P_HCODEC_QDCT_JPEG_SOF_RESUME 		DOS_REG_ADDR(HCODEC_QDCT_JPEG_SOF_RESUME)
#define HCODEC_QDCT_JPEG_DCT_STATUS0 0x1f2b 	///../ucode/dos_register.h:7212
#define P_HCODEC_QDCT_JPEG_DCT_STATUS0 		DOS_REG_ADDR(HCODEC_QDCT_JPEG_DCT_STATUS0)
#define HCODEC_QDCT_JPEG_DCT_STATUS1 0x1f2c 	///../ucode/dos_register.h:7213
#define P_HCODEC_QDCT_JPEG_DCT_STATUS1 		DOS_REG_ADDR(HCODEC_QDCT_JPEG_DCT_STATUS1)
#define HCODEC_QDCT_JPEG_DCT_COEFF01 0x1f2d 	///../ucode/dos_register.h:7214
#define P_HCODEC_QDCT_JPEG_DCT_COEFF01 		DOS_REG_ADDR(HCODEC_QDCT_JPEG_DCT_COEFF01)
#define HCODEC_QDCT_JPEG_DCT_COEFF23 0x1f2e 	///../ucode/dos_register.h:7215
#define P_HCODEC_QDCT_JPEG_DCT_COEFF23 		DOS_REG_ADDR(HCODEC_QDCT_JPEG_DCT_COEFF23)
#define HCODEC_QDCT_JPEG_DCT_COEFF45 0x1f2f 	///../ucode/dos_register.h:7216
#define P_HCODEC_QDCT_JPEG_DCT_COEFF45 		DOS_REG_ADDR(HCODEC_QDCT_JPEG_DCT_COEFF45)
#define HCODEC_QDCT_JPEG_DCT_COEFF67 0x1f30 	///../ucode/dos_register.h:7217
#define P_HCODEC_QDCT_JPEG_DCT_COEFF67 		DOS_REG_ADDR(HCODEC_QDCT_JPEG_DCT_COEFF67)
#define HCODEC_QDCT_JPEG_DCT_COEFF89 0x1f31 	///../ucode/dos_register.h:7218
#define P_HCODEC_QDCT_JPEG_DCT_COEFF89 		DOS_REG_ADDR(HCODEC_QDCT_JPEG_DCT_COEFF89)
#define HCODEC_IE_CONTROL 0x1f40 	///../ucode/dos_register.h:7229
#define P_HCODEC_IE_CONTROL 		DOS_REG_ADDR(HCODEC_IE_CONTROL)
#define HCODEC_IE_MB_POSITION 0x1f41 	///../ucode/dos_register.h:7232
#define P_HCODEC_IE_MB_POSITION 		DOS_REG_ADDR(HCODEC_IE_MB_POSITION)
#define HCODEC_IE_ME_MB_INFO 0x1f42 	///../ucode/dos_register.h:7237
#define P_HCODEC_IE_ME_MB_INFO 		DOS_REG_ADDR(HCODEC_IE_ME_MB_INFO)
#define HCODEC_SAD_CONTROL 0x1f43 	///../ucode/dos_register.h:7242
#define P_HCODEC_SAD_CONTROL 		DOS_REG_ADDR(HCODEC_SAD_CONTROL)
#define HCODEC_IE_RESULT_BUFFER 0x1f44 	///../ucode/dos_register.h:7249
#define P_HCODEC_IE_RESULT_BUFFER 		DOS_REG_ADDR(HCODEC_IE_RESULT_BUFFER)
#define HCODEC_IE_I4_PRED_MODE_HI 0x1f45 	///../ucode/dos_register.h:7251
#define P_HCODEC_IE_I4_PRED_MODE_HI 		DOS_REG_ADDR(HCODEC_IE_I4_PRED_MODE_HI)
#define HCODEC_IE_I4_PRED_MODE_LO 0x1f46 	///../ucode/dos_register.h:7252
#define P_HCODEC_IE_I4_PRED_MODE_LO 		DOS_REG_ADDR(HCODEC_IE_I4_PRED_MODE_LO)
#define HCODEC_IE_C_PRED_MODE 0x1f47 	///../ucode/dos_register.h:7256
#define P_HCODEC_IE_C_PRED_MODE 		DOS_REG_ADDR(HCODEC_IE_C_PRED_MODE)
#define HCODEC_IE_CUR_REF_SEL 0x1f48 	///../ucode/dos_register.h:7259
#define P_HCODEC_IE_CUR_REF_SEL 		DOS_REG_ADDR(HCODEC_IE_CUR_REF_SEL)
#define HCODEC_ME_CONTROL 0x1f49 	///../ucode/dos_register.h:7280
#define P_HCODEC_ME_CONTROL 		DOS_REG_ADDR(HCODEC_ME_CONTROL)
#define HCODEC_ME_START_POSITION 0x1f4a 	///../ucode/dos_register.h:7285
#define P_HCODEC_ME_START_POSITION 		DOS_REG_ADDR(HCODEC_ME_START_POSITION)
#define HCODEC_ME_STATUS 0x1f4b 	///../ucode/dos_register.h:7294
#define P_HCODEC_ME_STATUS 		DOS_REG_ADDR(HCODEC_ME_STATUS)
#define HCODEC_ME_DEBUG 0x1f4c 	///../ucode/dos_register.h:7301
#define P_HCODEC_ME_DEBUG 		DOS_REG_ADDR(HCODEC_ME_DEBUG)
#define HCODEC_ME_SKIP_LINE 0x1f4d 	///../ucode/dos_register.h:7307
#define P_HCODEC_ME_SKIP_LINE 		DOS_REG_ADDR(HCODEC_ME_SKIP_LINE)
#define HCODEC_ME_AB_MEM_CTL 0x1f4e 	///../ucode/dos_register.h:7312
#define P_HCODEC_ME_AB_MEM_CTL 		DOS_REG_ADDR(HCODEC_ME_AB_MEM_CTL)
#define HCODEC_ME_PIC_INFO 0x1f4f 	///../ucode/dos_register.h:7316
#define P_HCODEC_ME_PIC_INFO 		DOS_REG_ADDR(HCODEC_ME_PIC_INFO)
#define HCODEC_ME_SAD_ENOUGH_01 0x1f50 	///../ucode/dos_register.h:7319
#define P_HCODEC_ME_SAD_ENOUGH_01 		DOS_REG_ADDR(HCODEC_ME_SAD_ENOUGH_01)
#define HCODEC_ME_SAD_ENOUGH_23 0x1f51 	///../ucode/dos_register.h:7322
#define P_HCODEC_ME_SAD_ENOUGH_23 		DOS_REG_ADDR(HCODEC_ME_SAD_ENOUGH_23)
#define HCODEC_ME_STEP0_CLOSE_MV 0x1f52 	///../ucode/dos_register.h:7326
#define P_HCODEC_ME_STEP0_CLOSE_MV 		DOS_REG_ADDR(HCODEC_ME_STEP0_CLOSE_MV)
#define HCODEC_ME_F_SKIP_SAD 0x1f53 	///../ucode/dos_register.h:7331
#define P_HCODEC_ME_F_SKIP_SAD 		DOS_REG_ADDR(HCODEC_ME_F_SKIP_SAD)
#define HCODEC_ME_F_SKIP_WEIGHT 0x1f54 	///../ucode/dos_register.h:7336
#define P_HCODEC_ME_F_SKIP_WEIGHT 		DOS_REG_ADDR(HCODEC_ME_F_SKIP_WEIGHT)
#define HCODEC_ME_MV_MERGE_CTL 0x1f55 	///../ucode/dos_register.h:7355
#define P_HCODEC_ME_MV_MERGE_CTL 		DOS_REG_ADDR(HCODEC_ME_MV_MERGE_CTL)
#define HCODEC_ME_MV_WEIGHT_01 0x1f56 	///../ucode/dos_register.h:7360
#define P_HCODEC_ME_MV_WEIGHT_01 		DOS_REG_ADDR(HCODEC_ME_MV_WEIGHT_01)
#define HCODEC_ME_MV_WEIGHT_23 0x1f57 	///../ucode/dos_register.h:7365
#define P_HCODEC_ME_MV_WEIGHT_23 		DOS_REG_ADDR(HCODEC_ME_MV_WEIGHT_23)
#define HCODEC_ME_SAD_RANGE_INC 0x1f58 	///../ucode/dos_register.h:7370
#define P_HCODEC_ME_SAD_RANGE_INC 		DOS_REG_ADDR(HCODEC_ME_SAD_RANGE_INC)
#define HCODEC_ME_SUB_MERGE_CTL 0x1f59 	///../ucode/dos_register.h:7384
#define P_HCODEC_ME_SUB_MERGE_CTL 		DOS_REG_ADDR(HCODEC_ME_SUB_MERGE_CTL)
#define HCODEC_ME_SUB_REF_MV_CTL 0x1f5a 	///../ucode/dos_register.h:7391
#define P_HCODEC_ME_SUB_REF_MV_CTL 		DOS_REG_ADDR(HCODEC_ME_SUB_REF_MV_CTL)
#define HCODEC_ME_SUB_ANY_WEIGHT_SAD 0x1f5b 	///../ucode/dos_register.h:7396
#define P_HCODEC_ME_SUB_ANY_WEIGHT_SAD 		DOS_REG_ADDR(HCODEC_ME_SUB_ANY_WEIGHT_SAD)
#define HCODEC_ME_SUB_FIX_SAD 0x1f5c 	///../ucode/dos_register.h:7401
#define P_HCODEC_ME_SUB_FIX_SAD 		DOS_REG_ADDR(HCODEC_ME_SUB_FIX_SAD)
#define HCODEC_ME_SUB_FIX_MIN_SAD 0x1f5d 	///../ucode/dos_register.h:7406
#define P_HCODEC_ME_SUB_FIX_MIN_SAD 		DOS_REG_ADDR(HCODEC_ME_SUB_FIX_MIN_SAD)
#define HCODEC_ME_SUB_SNAP_GLITCH 0x1f5e 	///../ucode/dos_register.h:7412
#define P_HCODEC_ME_SUB_SNAP_GLITCH 		DOS_REG_ADDR(HCODEC_ME_SUB_SNAP_GLITCH)
#define HCODEC_ME_SUB_ACT_CTL 0x1f5f 	///../ucode/dos_register.h:7422
#define P_HCODEC_ME_SUB_ACT_CTL 		DOS_REG_ADDR(HCODEC_ME_SUB_ACT_CTL)
#define AO_RTI_STATUS_REG0 ((0x00 << 10) | (0x00 << 2)) 	///../ucode/c_always_on_pointer.h:13
#define P_AO_RTI_STATUS_REG0 		AOBUS_REG_ADDR(AO_RTI_STATUS_REG0)
#define AO_RTI_STATUS_REG1 ((0x00 << 10) | (0x01 << 2)) 	///../ucode/c_always_on_pointer.h:14
#define P_AO_RTI_STATUS_REG1 		AOBUS_REG_ADDR(AO_RTI_STATUS_REG1)
#define AO_RTI_STATUS_REG2 ((0x00 << 10) | (0x02 << 2)) 	///../ucode/c_always_on_pointer.h:15
#define P_AO_RTI_STATUS_REG2 		AOBUS_REG_ADDR(AO_RTI_STATUS_REG2)
#define AO_RTI_PWR_CNTL_REG1 ((0x00 << 10) | (0x03 << 2)) 	///../ucode/c_always_on_pointer.h:17
#define P_AO_RTI_PWR_CNTL_REG1 		AOBUS_REG_ADDR(AO_RTI_PWR_CNTL_REG1)
#define AO_RTI_PWR_CNTL_REG0 ((0x00 << 10) | (0x04 << 2)) 	///../ucode/c_always_on_pointer.h:18
#define P_AO_RTI_PWR_CNTL_REG0 		AOBUS_REG_ADDR(AO_RTI_PWR_CNTL_REG0)
#define AO_RTI_PIN_MUX_REG ((0x00 << 10) | (0x05 << 2)) 	///../ucode/c_always_on_pointer.h:19
#define P_AO_RTI_PIN_MUX_REG 		AOBUS_REG_ADDR(AO_RTI_PIN_MUX_REG)
#define AO_WD_GPIO_REG ((0x00 << 10) | (0x06 << 2)) 	///../ucode/c_always_on_pointer.h:21
#define P_AO_WD_GPIO_REG 		AOBUS_REG_ADDR(AO_WD_GPIO_REG)
#define AO_REMAP_REG0 ((0x00 << 10) | (0x07 << 2)) 	///../ucode/c_always_on_pointer.h:23
#define P_AO_REMAP_REG0 		AOBUS_REG_ADDR(AO_REMAP_REG0)
#define AO_REMAP_REG1 ((0x00 << 10) | (0x08 << 2)) 	///../ucode/c_always_on_pointer.h:24
#define P_AO_REMAP_REG1 		AOBUS_REG_ADDR(AO_REMAP_REG1)
#define AO_GPIO_O_EN_N ((0x00 << 10) | (0x09 << 2)) 	///../ucode/c_always_on_pointer.h:25
#define P_AO_GPIO_O_EN_N 		AOBUS_REG_ADDR(AO_GPIO_O_EN_N)
#define AO_GPIO_I ((0x00 << 10) | (0x0A << 2)) 	///../ucode/c_always_on_pointer.h:26
#define P_AO_GPIO_I 		AOBUS_REG_ADDR(AO_GPIO_I)
#define AO_RTI_PULL_UP_REG ((0x00 << 10) | (0x0B << 2)) 	///../ucode/c_always_on_pointer.h:28
#define P_AO_RTI_PULL_UP_REG 		AOBUS_REG_ADDR(AO_RTI_PULL_UP_REG)
#define AO_RTI_WD_MARK ((0x00 << 10) | (0x0D << 2)) 	///../ucode/c_always_on_pointer.h:31
#define P_AO_RTI_WD_MARK 		AOBUS_REG_ADDR(AO_RTI_WD_MARK)
#define AO_CPU_CNTL ((0x00 << 10) | (0x0E << 2)) 	///../ucode/c_always_on_pointer.h:33
#define P_AO_CPU_CNTL 		AOBUS_REG_ADDR(AO_CPU_CNTL)
#define AO_CPU_STAT ((0x00 << 10) | (0x0F << 2)) 	///../ucode/c_always_on_pointer.h:35
#define P_AO_CPU_STAT 		AOBUS_REG_ADDR(AO_CPU_STAT)
#define AO_RTI_GEN_CNTL_REG0 ((0x00 << 10) | (0x10 << 2)) 	///../ucode/c_always_on_pointer.h:38
#define P_AO_RTI_GEN_CNTL_REG0 		AOBUS_REG_ADDR(AO_RTI_GEN_CNTL_REG0)
#define AO_WATCHDOG_REG ((0x00 << 10) | (0x11 << 2)) 	///../ucode/c_always_on_pointer.h:39
#define P_AO_WATCHDOG_REG 		AOBUS_REG_ADDR(AO_WATCHDOG_REG)
#define AO_WATCHDOG_RESET ((0x00 << 10) | (0x12 << 2)) 	///../ucode/c_always_on_pointer.h:40
#define P_AO_WATCHDOG_RESET 		AOBUS_REG_ADDR(AO_WATCHDOG_RESET)
#define AO_TIMER_REG ((0x00 << 10) | (0x13 << 2)) 	///../ucode/c_always_on_pointer.h:42
#define P_AO_TIMER_REG 		AOBUS_REG_ADDR(AO_TIMER_REG)
#define AO_TIMERA_REG ((0x00 << 10) | (0x14 << 2)) 	///../ucode/c_always_on_pointer.h:43
#define P_AO_TIMERA_REG 		AOBUS_REG_ADDR(AO_TIMERA_REG)
#define AO_TIMERE_REG ((0x00 << 10) | (0x15 << 2)) 	///../ucode/c_always_on_pointer.h:44
#define P_AO_TIMERE_REG 		AOBUS_REG_ADDR(AO_TIMERE_REG)
#define AO_AHB2DDR_CNTL ((0x00 << 10) | (0x18 << 2)) 	///../ucode/c_always_on_pointer.h:46
#define P_AO_AHB2DDR_CNTL 		AOBUS_REG_ADDR(AO_AHB2DDR_CNTL)
#define AO_IRQ_MASK_FIQ_SEL ((0x00 << 10) | (0x20 << 2)) 	///../ucode/c_always_on_pointer.h:48
#define P_AO_IRQ_MASK_FIQ_SEL 		AOBUS_REG_ADDR(AO_IRQ_MASK_FIQ_SEL)
#define AO_IRQ_GPIO_REG ((0x00 << 10) | (0x21 << 2)) 	///../ucode/c_always_on_pointer.h:49
#define P_AO_IRQ_GPIO_REG 		AOBUS_REG_ADDR(AO_IRQ_GPIO_REG)
#define AO_IRQ_STAT ((0x00 << 10) | (0x22 << 2)) 	///../ucode/c_always_on_pointer.h:50
#define P_AO_IRQ_STAT 		AOBUS_REG_ADDR(AO_IRQ_STAT)
#define AO_IRQ_STAT_CLR ((0x00 << 10) | (0x23 << 2)) 	///../ucode/c_always_on_pointer.h:51
#define P_AO_IRQ_STAT_CLR 		AOBUS_REG_ADDR(AO_IRQ_STAT_CLR)
#define AO_DEBUG_REG0 ((0x00 << 10) | (0x28 << 2)) 	///../ucode/c_always_on_pointer.h:53
#define P_AO_DEBUG_REG0 		AOBUS_REG_ADDR(AO_DEBUG_REG0)
#define AO_DEBUG_REG1 ((0x00 << 10) | (0x29 << 2)) 	///../ucode/c_always_on_pointer.h:54
#define P_AO_DEBUG_REG1 		AOBUS_REG_ADDR(AO_DEBUG_REG1)
#define AO_DEBUG_REG2 ((0x00 << 10) | (0x2a << 2)) 	///../ucode/c_always_on_pointer.h:55
#define P_AO_DEBUG_REG2 		AOBUS_REG_ADDR(AO_DEBUG_REG2)
#define AO_DEBUG_REG3 ((0x00 << 10) | (0x2b << 2)) 	///../ucode/c_always_on_pointer.h:56
#define P_AO_DEBUG_REG3 		AOBUS_REG_ADDR(AO_DEBUG_REG3)
#define AO_IR_BLASTER_ADDR0 ((0x00 << 10) | (0x30 << 2)) 	///../ucode/c_always_on_pointer.h:58
#define P_AO_IR_BLASTER_ADDR0 		AOBUS_REG_ADDR(AO_IR_BLASTER_ADDR0)
#define AO_IR_BLASTER_ADDR1 ((0x00 << 10) | (0x31 << 2)) 	///../ucode/c_always_on_pointer.h:59
#define P_AO_IR_BLASTER_ADDR1 		AOBUS_REG_ADDR(AO_IR_BLASTER_ADDR1)
#define AO_IR_BLASTER_ADDR2 ((0x00 << 10) | (0x32 << 2)) 	///../ucode/c_always_on_pointer.h:60
#define P_AO_IR_BLASTER_ADDR2 		AOBUS_REG_ADDR(AO_IR_BLASTER_ADDR2)
#define AO_RTI_PWR_A9_CNTL0 ((0x00 << 10) | (0x38 << 2)) 	///../ucode/c_always_on_pointer.h:63
#define P_AO_RTI_PWR_A9_CNTL0 		AOBUS_REG_ADDR(AO_RTI_PWR_A9_CNTL0)
#define AO_RTI_PWR_A9_CNTL1 ((0x00 << 10) | (0x39 << 2)) 	///../ucode/c_always_on_pointer.h:64
#define P_AO_RTI_PWR_A9_CNTL1 		AOBUS_REG_ADDR(AO_RTI_PWR_A9_CNTL1)
#define AO_RTI_GEN_PWR_SLEEP0 ((0x00 << 10) | (0x3a << 2)) 	///../ucode/c_always_on_pointer.h:65
#define P_AO_RTI_GEN_PWR_SLEEP0 		AOBUS_REG_ADDR(AO_RTI_GEN_PWR_SLEEP0)
#define AO_RTI_GEN_PWR_ISO0 ((0x00 << 10) | (0x3b << 2)) 	///../ucode/c_always_on_pointer.h:66
#define P_AO_RTI_GEN_PWR_ISO0 		AOBUS_REG_ADDR(AO_RTI_GEN_PWR_ISO0)
#define AO_RTI_GEN_PWR_ACK0 ((0x00 << 10) | (0x3c << 2)) 	///../ucode/c_always_on_pointer.h:67
#define P_AO_RTI_GEN_PWR_ACK0 		AOBUS_REG_ADDR(AO_RTI_GEN_PWR_ACK0)
#define AO_RTI_PWR_A9_MEM_PD0 ((0x00 << 10) | (0x3d << 2)) 	///../ucode/c_always_on_pointer.h:68
#define P_AO_RTI_PWR_A9_MEM_PD0 		AOBUS_REG_ADDR(AO_RTI_PWR_A9_MEM_PD0)
#define AO_RTI_PWR_A9_MEM_PD1 ((0x00 << 10) | (0x3e << 2)) 	///../ucode/c_always_on_pointer.h:69
#define P_AO_RTI_PWR_A9_MEM_PD1 		AOBUS_REG_ADDR(AO_RTI_PWR_A9_MEM_PD1)
#define AO_CEC_GEN_CNTL ((0x00 << 10) | (0x40 << 2)) 	///../ucode/c_always_on_pointer.h:72
#define P_AO_CEC_GEN_CNTL 		AOBUS_REG_ADDR(AO_CEC_GEN_CNTL)
#define AO_CEC_RW_REG ((0x00 << 10) | (0x41 << 2)) 	///../ucode/c_always_on_pointer.h:73
#define P_AO_CEC_RW_REG 		AOBUS_REG_ADDR(AO_CEC_RW_REG)
#define AO_CEC_INTR_MASKN ((0x00 << 10) | (0x42 << 2)) 	///../ucode/c_always_on_pointer.h:74
#define P_AO_CEC_INTR_MASKN 		AOBUS_REG_ADDR(AO_CEC_INTR_MASKN)
#define AO_CEC_INTR_CLR ((0x00 << 10) | (0x43 << 2)) 	///../ucode/c_always_on_pointer.h:75
#define P_AO_CEC_INTR_CLR 		AOBUS_REG_ADDR(AO_CEC_INTR_CLR)
#define AO_CEC_INTR_STAT ((0x00 << 10) | (0x44 << 2)) 	///../ucode/c_always_on_pointer.h:76
#define P_AO_CEC_INTR_STAT 		AOBUS_REG_ADDR(AO_CEC_INTR_STAT)
#define AO_IR_DEC_LDR_ACTIVE ((0x01 << 10) | (0x20 << 2)) 	///../ucode/c_always_on_pointer.h:81
#define P_AO_IR_DEC_LDR_ACTIVE 		AOBUS_REG_ADDR(AO_IR_DEC_LDR_ACTIVE)
#define AO_IR_DEC_LDR_IDLE ((0x01 << 10) | (0x21 << 2)) 	///../ucode/c_always_on_pointer.h:82
#define P_AO_IR_DEC_LDR_IDLE 		AOBUS_REG_ADDR(AO_IR_DEC_LDR_IDLE)
#define AO_IR_DEC_LDR_REPEAT ((0x01 << 10) | (0x22 << 2)) 	///../ucode/c_always_on_pointer.h:83
#define P_AO_IR_DEC_LDR_REPEAT 		AOBUS_REG_ADDR(AO_IR_DEC_LDR_REPEAT)
#define AO_IR_DEC_BIT_0 ((0x01 << 10) | (0x23 << 2)) 	///../ucode/c_always_on_pointer.h:84
#define P_AO_IR_DEC_BIT_0 		AOBUS_REG_ADDR(AO_IR_DEC_BIT_0)
#define AO_IR_DEC_REG0 ((0x01 << 10) | (0x24 << 2)) 	///../ucode/c_always_on_pointer.h:85
#define P_AO_IR_DEC_REG0 		AOBUS_REG_ADDR(AO_IR_DEC_REG0)
#define AO_IR_DEC_FRAME ((0x01 << 10) | (0x25 << 2)) 	///../ucode/c_always_on_pointer.h:86
#define P_AO_IR_DEC_FRAME 		AOBUS_REG_ADDR(AO_IR_DEC_FRAME)
#define AO_IR_DEC_STATUS ((0x01 << 10) | (0x26 << 2)) 	///../ucode/c_always_on_pointer.h:87
#define P_AO_IR_DEC_STATUS 		AOBUS_REG_ADDR(AO_IR_DEC_STATUS)
#define AO_IR_DEC_REG1 ((0x01 << 10) | (0x27 << 2)) 	///../ucode/c_always_on_pointer.h:88
#define P_AO_IR_DEC_REG1 		AOBUS_REG_ADDR(AO_IR_DEC_REG1)
#define AO_UART_WFIFO ((0x01 << 10) | (0x30 << 2)) 	///../ucode/c_always_on_pointer.h:93
#define P_AO_UART_WFIFO 		AOBUS_REG_ADDR(AO_UART_WFIFO)
#define AO_UART_RFIFO ((0x01 << 10) | (0x31 << 2)) 	///../ucode/c_always_on_pointer.h:94
#define P_AO_UART_RFIFO 		AOBUS_REG_ADDR(AO_UART_RFIFO)
#define AO_UART_CONTROL ((0x01 << 10) | (0x32 << 2)) 	///../ucode/c_always_on_pointer.h:95
#define P_AO_UART_CONTROL 		AOBUS_REG_ADDR(AO_UART_CONTROL)
#define AO_UART_STATUS ((0x01 << 10) | (0x33 << 2)) 	///../ucode/c_always_on_pointer.h:96
#define P_AO_UART_STATUS 		AOBUS_REG_ADDR(AO_UART_STATUS)
#define AO_UART_MISC ((0x01 << 10) | (0x34 << 2)) 	///../ucode/c_always_on_pointer.h:97
#define P_AO_UART_MISC 		AOBUS_REG_ADDR(AO_UART_MISC)
#define AO_UART_REG5 ((0x01 << 10) | (0x35 << 2)) 	///../ucode/c_always_on_pointer.h:98
#define P_AO_UART_REG5 		AOBUS_REG_ADDR(AO_UART_REG5)
#define AO_UART2_WFIFO ((0x01 << 10) | (0x38 << 2)) 	///../ucode/c_always_on_pointer.h:103
#define P_AO_UART2_WFIFO 		AOBUS_REG_ADDR(AO_UART2_WFIFO)
#define AO_UART2_RFIFO ((0x01 << 10) | (0x39 << 2)) 	///../ucode/c_always_on_pointer.h:104
#define P_AO_UART2_RFIFO 		AOBUS_REG_ADDR(AO_UART2_RFIFO)
#define AO_UART2_CONTROL ((0x01 << 10) | (0x3a << 2)) 	///../ucode/c_always_on_pointer.h:105
#define P_AO_UART2_CONTROL 		AOBUS_REG_ADDR(AO_UART2_CONTROL)
#define AO_UART2_STATUS ((0x01 << 10) | (0x3b << 2)) 	///../ucode/c_always_on_pointer.h:106
#define P_AO_UART2_STATUS 		AOBUS_REG_ADDR(AO_UART2_STATUS)
#define AO_UART2_MISC ((0x01 << 10) | (0x3c << 2)) 	///../ucode/c_always_on_pointer.h:107
#define P_AO_UART2_MISC 		AOBUS_REG_ADDR(AO_UART2_MISC)
#define AO_UART2_REG5 ((0x01 << 10) | (0x3d << 2)) 	///../ucode/c_always_on_pointer.h:108
#define P_AO_UART2_REG5 		AOBUS_REG_ADDR(AO_UART2_REG5)
#define AO_I2C_M_0_CONTROL_REG ((0x01 << 10) | (0x40 << 2)) 	///../ucode/c_always_on_pointer.h:113
#define P_AO_I2C_M_0_CONTROL_REG 		AOBUS_REG_ADDR(AO_I2C_M_0_CONTROL_REG)
#define AO_I2C_M_0_SLAVE_ADDR ((0x01 << 10) | (0x41 << 2)) 	///../ucode/c_always_on_pointer.h:114
#define P_AO_I2C_M_0_SLAVE_ADDR 		AOBUS_REG_ADDR(AO_I2C_M_0_SLAVE_ADDR)
#define AO_I2C_M_0_TOKEN_LIST0 ((0x01 << 10) | (0x42 << 2)) 	///../ucode/c_always_on_pointer.h:115
#define P_AO_I2C_M_0_TOKEN_LIST0 		AOBUS_REG_ADDR(AO_I2C_M_0_TOKEN_LIST0)
#define AO_I2C_M_0_TOKEN_LIST1 ((0x01 << 10) | (0x43 << 2)) 	///../ucode/c_always_on_pointer.h:116
#define P_AO_I2C_M_0_TOKEN_LIST1 		AOBUS_REG_ADDR(AO_I2C_M_0_TOKEN_LIST1)
#define AO_I2C_M_0_WDATA_REG0 ((0x01 << 10) | (0x44 << 2)) 	///../ucode/c_always_on_pointer.h:117
#define P_AO_I2C_M_0_WDATA_REG0 		AOBUS_REG_ADDR(AO_I2C_M_0_WDATA_REG0)
#define AO_I2C_M_0_WDATA_REG1 ((0x01 << 10) | (0x45 << 2)) 	///../ucode/c_always_on_pointer.h:118
#define P_AO_I2C_M_0_WDATA_REG1 		AOBUS_REG_ADDR(AO_I2C_M_0_WDATA_REG1)
#define AO_I2C_M_0_RDATA_REG0 ((0x01 << 10) | (0x46 << 2)) 	///../ucode/c_always_on_pointer.h:119
#define P_AO_I2C_M_0_RDATA_REG0 		AOBUS_REG_ADDR(AO_I2C_M_0_RDATA_REG0)
#define AO_I2C_M_0_RDATA_REG1 ((0x01 << 10) | (0x47 << 2)) 	///../ucode/c_always_on_pointer.h:120
#define P_AO_I2C_M_0_RDATA_REG1 		AOBUS_REG_ADDR(AO_I2C_M_0_RDATA_REG1)
#define AO_I2C_S_CONTROL_REG ((0x01 << 10) | (0x50 << 2)) 	///../ucode/c_always_on_pointer.h:124
#define P_AO_I2C_S_CONTROL_REG 		AOBUS_REG_ADDR(AO_I2C_S_CONTROL_REG)
#define AO_I2C_S_SEND_REG ((0x01 << 10) | (0x51 << 2)) 	///../ucode/c_always_on_pointer.h:125
#define P_AO_I2C_S_SEND_REG 		AOBUS_REG_ADDR(AO_I2C_S_SEND_REG)
#define AO_I2C_S_RECV_REG ((0x01 << 10) | (0x52 << 2)) 	///../ucode/c_always_on_pointer.h:126
#define P_AO_I2C_S_RECV_REG 		AOBUS_REG_ADDR(AO_I2C_S_RECV_REG)
#define AO_I2C_S_CNTL1_REG ((0x01 << 10) | (0x53 << 2)) 	///../ucode/c_always_on_pointer.h:127
#define P_AO_I2C_S_CNTL1_REG 		AOBUS_REG_ADDR(AO_I2C_S_CNTL1_REG)
#define AO_RTC_ADDR0 ((0x01 << 10) | (0xd0 << 2)) 	///../ucode/c_always_on_pointer.h:139
#define P_AO_RTC_ADDR0 		AOBUS_REG_ADDR(AO_RTC_ADDR0)
#define AO_RTC_ADDR1 ((0x01 << 10) | (0xd1 << 2)) 	///../ucode/c_always_on_pointer.h:140
#define P_AO_RTC_ADDR1 		AOBUS_REG_ADDR(AO_RTC_ADDR1)
#define AO_RTC_ADDR2 ((0x01 << 10) | (0xd2 << 2)) 	///../ucode/c_always_on_pointer.h:141
#define P_AO_RTC_ADDR2 		AOBUS_REG_ADDR(AO_RTC_ADDR2)
#define AO_RTC_ADDR3 ((0x01 << 10) | (0xd3 << 2)) 	///../ucode/c_always_on_pointer.h:142
#define P_AO_RTC_ADDR3 		AOBUS_REG_ADDR(AO_RTC_ADDR3)
#define AO_RTC_ADDR4 ((0x01 << 10) | (0xd4 << 2)) 	///../ucode/c_always_on_pointer.h:143
#define P_AO_RTC_ADDR4 		AOBUS_REG_ADDR(AO_RTC_ADDR4)
#define AO_MF_IR_DEC_LDR_ACTIVE ((0x01 << 10) | (0x60 << 2)) 	///../ucode/c_always_on_pointer.h:145
#define P_AO_MF_IR_DEC_LDR_ACTIVE 		AOBUS_REG_ADDR(AO_MF_IR_DEC_LDR_ACTIVE)
#define AO_MF_IR_DEC_LDR_IDLE ((0x01 << 10) | (0x61 << 2)) 	///../ucode/c_always_on_pointer.h:146
#define P_AO_MF_IR_DEC_LDR_IDLE 		AOBUS_REG_ADDR(AO_MF_IR_DEC_LDR_IDLE)
#define AO_MF_IR_DEC_LDR_REPEAT ((0x01 << 10) | (0x62 << 2)) 	///../ucode/c_always_on_pointer.h:147
#define P_AO_MF_IR_DEC_LDR_REPEAT 		AOBUS_REG_ADDR(AO_MF_IR_DEC_LDR_REPEAT)
#define AO_MF_IR_DEC_BIT_0 ((0x01 << 10) | (0x63 << 2)) 	///../ucode/c_always_on_pointer.h:148
#define P_AO_MF_IR_DEC_BIT_0 		AOBUS_REG_ADDR(AO_MF_IR_DEC_BIT_0)
#define AO_MF_IR_DEC_REG0 ((0x01 << 10) | (0x64 << 2)) 	///../ucode/c_always_on_pointer.h:149
#define P_AO_MF_IR_DEC_REG0 		AOBUS_REG_ADDR(AO_MF_IR_DEC_REG0)
#define AO_MF_IR_DEC_FRAME ((0x01 << 10) | (0x65 << 2)) 	///../ucode/c_always_on_pointer.h:150
#define P_AO_MF_IR_DEC_FRAME 		AOBUS_REG_ADDR(AO_MF_IR_DEC_FRAME)
#define AO_MF_IR_DEC_STATUS ((0x01 << 10) | (0x66 << 2)) 	///../ucode/c_always_on_pointer.h:151
#define P_AO_MF_IR_DEC_STATUS 		AOBUS_REG_ADDR(AO_MF_IR_DEC_STATUS)
#define AO_MF_IR_DEC_REG1 ((0x01 << 10) | (0x67 << 2)) 	///../ucode/c_always_on_pointer.h:152
#define P_AO_MF_IR_DEC_REG1 		AOBUS_REG_ADDR(AO_MF_IR_DEC_REG1)
#define AO_MF_IR_DEC_REG2 ((0x01 << 10) | (0x68 << 2)) 	///../ucode/c_always_on_pointer.h:153
#define P_AO_MF_IR_DEC_REG2 		AOBUS_REG_ADDR(AO_MF_IR_DEC_REG2)
#define AO_MF_IR_DEC_DURATN2 ((0x01 << 10) | (0x69 << 2)) 	///../ucode/c_always_on_pointer.h:154
#define P_AO_MF_IR_DEC_DURATN2 		AOBUS_REG_ADDR(AO_MF_IR_DEC_DURATN2)
#define AO_MF_IR_DEC_DURATN3 ((0x01 << 10) | (0x6a << 2)) 	///../ucode/c_always_on_pointer.h:155
#define P_AO_MF_IR_DEC_DURATN3 		AOBUS_REG_ADDR(AO_MF_IR_DEC_DURATN3)
#define AO_MF_IR_DEC_FRAME1 ((0x01 << 10) | (0x6b << 2)) 	///../ucode/c_always_on_pointer.h:156
#define P_AO_MF_IR_DEC_FRAME1 		AOBUS_REG_ADDR(AO_MF_IR_DEC_FRAME1)
#define AM_DDR_PLL_CNTL 0x0400 	///../ucode/ddr3_reg.h:1
#define P_AM_DDR_PLL_CNTL 		MMC_REG_ADDR(AM_DDR_PLL_CNTL)
#define AM_DDR_PLL_CNTL1 0x0404 	///../ucode/ddr3_reg.h:2
#define P_AM_DDR_PLL_CNTL1 		MMC_REG_ADDR(AM_DDR_PLL_CNTL1)
#define AM_DDR_PLL_CNTL2 0x0408 	///../ucode/ddr3_reg.h:3
#define P_AM_DDR_PLL_CNTL2 		MMC_REG_ADDR(AM_DDR_PLL_CNTL2)
#define AM_DDR_PLL_CNTL3 0x040c 	///../ucode/ddr3_reg.h:4
#define P_AM_DDR_PLL_CNTL3 		MMC_REG_ADDR(AM_DDR_PLL_CNTL3)
#define AM_DDR_PLL_CNTL4 0x0410 	///../ucode/ddr3_reg.h:5
#define P_AM_DDR_PLL_CNTL4 		MMC_REG_ADDR(AM_DDR_PLL_CNTL4)
#define AM_DDR_PLL_STS 0x0414 	///../ucode/ddr3_reg.h:6
#define P_AM_DDR_PLL_STS 		MMC_REG_ADDR(AM_DDR_PLL_STS)
#define DDR_CLK_CNTL 0x0418 	///../ucode/ddr3_reg.h:10
#define P_DDR_CLK_CNTL 		MMC_REG_ADDR(DDR_CLK_CNTL)
#define DDR_CLK_STS 0x041c 	///../ucode/ddr3_reg.h:30
#define P_DDR_CLK_STS 		MMC_REG_ADDR(DDR_CLK_STS)
#define DDR0_CLK_CTRL 0x0800 	///../ucode/ddr3_reg.h:34
#define P_DDR0_CLK_CTRL 		MMC_REG_ADDR(DDR0_CLK_CTRL)
#define DDR0_SOFT_RESET 0x0804 	///../ucode/ddr3_reg.h:45
#define P_DDR0_SOFT_RESET 		MMC_REG_ADDR(DDR0_SOFT_RESET)
#define DDR0_APD_CTRL 0x0808 	///../ucode/ddr3_reg.h:50
#define P_DDR0_APD_CTRL 		MMC_REG_ADDR(DDR0_APD_CTRL)
#define DDR0_PCTL_SCFG 0x0000 	///../ucode/ddr3_reg.h:54
#define P_DDR0_PCTL_SCFG 		MMC_REG_ADDR(DDR0_PCTL_SCFG)
#define DDR0_PCTL_SCTL 0x0004 	///../ucode/ddr3_reg.h:55
#define P_DDR0_PCTL_SCTL 		MMC_REG_ADDR(DDR0_PCTL_SCTL)
#define DDR0_PCTL_STAT 0x0008 	///../ucode/ddr3_reg.h:56
#define P_DDR0_PCTL_STAT 		MMC_REG_ADDR(DDR0_PCTL_STAT)
#define DDR0_PCTL_INTRSTAT 0x000c 	///../ucode/ddr3_reg.h:57
#define P_DDR0_PCTL_INTRSTAT 		MMC_REG_ADDR(DDR0_PCTL_INTRSTAT)
#define DDR0_PCTL_POWSTAT 0x0048 	///../ucode/ddr3_reg.h:58
#define P_DDR0_PCTL_POWSTAT 		MMC_REG_ADDR(DDR0_PCTL_POWSTAT)
#define DDR0_PCTL_MRRSTAT0 0x0064 	///../ucode/ddr3_reg.h:59
#define P_DDR0_PCTL_MRRSTAT0 		MMC_REG_ADDR(DDR0_PCTL_MRRSTAT0)
#define DDR0_PCTL_CMDTSTAT 0x004c 	///../ucode/ddr3_reg.h:60
#define P_DDR0_PCTL_CMDTSTAT 		MMC_REG_ADDR(DDR0_PCTL_CMDTSTAT)
#define DDR0_PCTL_MCMD 0x0040 	///../ucode/ddr3_reg.h:61
#define P_DDR0_PCTL_MCMD 		MMC_REG_ADDR(DDR0_PCTL_MCMD)
#define DDR0_PCTL_MRRSTAT1 0x0068 	///../ucode/ddr3_reg.h:62
#define P_DDR0_PCTL_MRRSTAT1 		MMC_REG_ADDR(DDR0_PCTL_MRRSTAT1)
#define DDR0_PCTL_MRRCFG0 0x0060 	///../ucode/ddr3_reg.h:63
#define P_DDR0_PCTL_MRRCFG0 		MMC_REG_ADDR(DDR0_PCTL_MRRCFG0)
#define DDR0_PCTL_CMDTSTATEN 0x0050 	///../ucode/ddr3_reg.h:64
#define P_DDR0_PCTL_CMDTSTATEN 		MMC_REG_ADDR(DDR0_PCTL_CMDTSTATEN)
#define DDR0_PCTL_POWCTL 0x0044 	///../ucode/ddr3_reg.h:65
#define P_DDR0_PCTL_POWCTL 		MMC_REG_ADDR(DDR0_PCTL_POWCTL)
#define DDR0_PCTL_PPCFG 0x0084 	///../ucode/ddr3_reg.h:66
#define P_DDR0_PCTL_PPCFG 		MMC_REG_ADDR(DDR0_PCTL_PPCFG)
#define DDR0_PCTL_LPDDR23ZQCFG 0x008c 	///../ucode/ddr3_reg.h:67
#define P_DDR0_PCTL_LPDDR23ZQCFG 		MMC_REG_ADDR(DDR0_PCTL_LPDDR23ZQCFG)
#define DDR0_PCTL_MCFG1 0x007c 	///../ucode/ddr3_reg.h:68
#define P_DDR0_PCTL_MCFG1 		MMC_REG_ADDR(DDR0_PCTL_MCFG1)
#define DDR0_PCTL_MSTAT 0x0088 	///../ucode/ddr3_reg.h:69
#define P_DDR0_PCTL_MSTAT 		MMC_REG_ADDR(DDR0_PCTL_MSTAT)
#define DDR0_PCTL_MCFG 0x0080 	///../ucode/ddr3_reg.h:70
#define P_DDR0_PCTL_MCFG 		MMC_REG_ADDR(DDR0_PCTL_MCFG)
#define DDR0_PCTL_DTUAWDT 0x00b0 	///../ucode/ddr3_reg.h:71
#define P_DDR0_PCTL_DTUAWDT 		MMC_REG_ADDR(DDR0_PCTL_DTUAWDT)
#define DDR0_PCTL_DTUPRD2 0x00a8 	///../ucode/ddr3_reg.h:72
#define P_DDR0_PCTL_DTUPRD2 		MMC_REG_ADDR(DDR0_PCTL_DTUPRD2)
#define DDR0_PCTL_DTUPRD3 0x00ac 	///../ucode/ddr3_reg.h:73
#define P_DDR0_PCTL_DTUPRD3 		MMC_REG_ADDR(DDR0_PCTL_DTUPRD3)
#define DDR0_PCTL_DTUNE 0x009c 	///../ucode/ddr3_reg.h:74
#define P_DDR0_PCTL_DTUNE 		MMC_REG_ADDR(DDR0_PCTL_DTUNE)
#define DDR0_PCTL_DTUPDES 0x0094 	///../ucode/ddr3_reg.h:75
#define P_DDR0_PCTL_DTUPDES 		MMC_REG_ADDR(DDR0_PCTL_DTUPDES)
#define DDR0_PCTL_DTUNA 0x0098 	///../ucode/ddr3_reg.h:76
#define P_DDR0_PCTL_DTUNA 		MMC_REG_ADDR(DDR0_PCTL_DTUNA)
#define DDR0_PCTL_DTUPRD0 0x00a0 	///../ucode/ddr3_reg.h:77
#define P_DDR0_PCTL_DTUPRD0 		MMC_REG_ADDR(DDR0_PCTL_DTUPRD0)
#define DDR0_PCTL_DTUPRD1 0x00a4 	///../ucode/ddr3_reg.h:78
#define P_DDR0_PCTL_DTUPRD1 		MMC_REG_ADDR(DDR0_PCTL_DTUPRD1)
#define DDR0_PCTL_TCKSRE 0x0124 	///../ucode/ddr3_reg.h:79
#define P_DDR0_PCTL_TCKSRE 		MMC_REG_ADDR(DDR0_PCTL_TCKSRE)
#define DDR0_PCTL_TZQCSI 0x011c 	///../ucode/ddr3_reg.h:80
#define P_DDR0_PCTL_TZQCSI 		MMC_REG_ADDR(DDR0_PCTL_TZQCSI)
#define DDR0_PCTL_TINIT 0x00c4 	///../ucode/ddr3_reg.h:81
#define P_DDR0_PCTL_TINIT 		MMC_REG_ADDR(DDR0_PCTL_TINIT)
#define DDR0_PCTL_TDPD 0x0144 	///../ucode/ddr3_reg.h:82
#define P_DDR0_PCTL_TDPD 		MMC_REG_ADDR(DDR0_PCTL_TDPD)
#define DDR0_PCTL_TOGCNT1U 0x00c0 	///../ucode/ddr3_reg.h:83
#define P_DDR0_PCTL_TOGCNT1U 		MMC_REG_ADDR(DDR0_PCTL_TOGCNT1U)
#define DDR0_PCTL_TCKE 0x012c 	///../ucode/ddr3_reg.h:84
#define P_DDR0_PCTL_TCKE 		MMC_REG_ADDR(DDR0_PCTL_TCKE)
#define DDR0_PCTL_TMOD 0x0130 	///../ucode/ddr3_reg.h:85
#define P_DDR0_PCTL_TMOD 		MMC_REG_ADDR(DDR0_PCTL_TMOD)
#define DDR0_PCTL_TEXSR 0x010c 	///../ucode/ddr3_reg.h:86
#define P_DDR0_PCTL_TEXSR 		MMC_REG_ADDR(DDR0_PCTL_TEXSR)
#define DDR0_PCTL_TAL 0x00e4 	///../ucode/ddr3_reg.h:87
#define P_DDR0_PCTL_TAL 		MMC_REG_ADDR(DDR0_PCTL_TAL)
#define DDR0_PCTL_TRTP 0x0100 	///../ucode/ddr3_reg.h:88
#define P_DDR0_PCTL_TRTP 		MMC_REG_ADDR(DDR0_PCTL_TRTP)
#define DDR0_PCTL_TCKSRX 0x0128 	///../ucode/ddr3_reg.h:89
#define P_DDR0_PCTL_TCKSRX 		MMC_REG_ADDR(DDR0_PCTL_TCKSRX)
#define DDR0_PCTL_TRTW 0x00e0 	///../ucode/ddr3_reg.h:90
#define P_DDR0_PCTL_TRTW 		MMC_REG_ADDR(DDR0_PCTL_TRTW)
#define DDR0_PCTL_TCWL 0x00ec 	///../ucode/ddr3_reg.h:91
#define P_DDR0_PCTL_TCWL 		MMC_REG_ADDR(DDR0_PCTL_TCWL)
#define DDR0_PCTL_TWR 0x0104 	///../ucode/ddr3_reg.h:92
#define P_DDR0_PCTL_TWR 		MMC_REG_ADDR(DDR0_PCTL_TWR)
#define DDR0_PCTL_TCL 0x00e8 	///../ucode/ddr3_reg.h:93
#define P_DDR0_PCTL_TCL 		MMC_REG_ADDR(DDR0_PCTL_TCL)
#define DDR0_PCTL_TDQS 0x0120 	///../ucode/ddr3_reg.h:94
#define P_DDR0_PCTL_TDQS 		MMC_REG_ADDR(DDR0_PCTL_TDQS)
#define DDR0_PCTL_TRSTH 0x00c8 	///../ucode/ddr3_reg.h:95
#define P_DDR0_PCTL_TRSTH 		MMC_REG_ADDR(DDR0_PCTL_TRSTH)
#define DDR0_PCTL_TRCD 0x00f8 	///../ucode/ddr3_reg.h:96
#define P_DDR0_PCTL_TRCD 		MMC_REG_ADDR(DDR0_PCTL_TRCD)
#define DDR0_PCTL_TXP 0x0110 	///../ucode/ddr3_reg.h:97
#define P_DDR0_PCTL_TXP 		MMC_REG_ADDR(DDR0_PCTL_TXP)
#define DDR0_PCTL_TOGCNT100N 0x00cc 	///../ucode/ddr3_reg.h:98
#define P_DDR0_PCTL_TOGCNT100N 		MMC_REG_ADDR(DDR0_PCTL_TOGCNT100N)
#define DDR0_PCTL_TMRD 0x00d4 	///../ucode/ddr3_reg.h:99
#define P_DDR0_PCTL_TMRD 		MMC_REG_ADDR(DDR0_PCTL_TMRD)
#define DDR0_PCTL_TRSTL 0x0134 	///../ucode/ddr3_reg.h:100
#define P_DDR0_PCTL_TRSTL 		MMC_REG_ADDR(DDR0_PCTL_TRSTL)
#define DDR0_PCTL_TREFI 0x00d0 	///../ucode/ddr3_reg.h:101
#define P_DDR0_PCTL_TREFI 		MMC_REG_ADDR(DDR0_PCTL_TREFI)
#define DDR0_PCTL_TRAS 0x00f0 	///../ucode/ddr3_reg.h:102
#define P_DDR0_PCTL_TRAS 		MMC_REG_ADDR(DDR0_PCTL_TRAS)
#define DDR0_PCTL_TREFI_MEM_DDR3 0x0148 	///../ucode/ddr3_reg.h:103
#define P_DDR0_PCTL_TREFI_MEM_DDR3 		MMC_REG_ADDR(DDR0_PCTL_TREFI_MEM_DDR3)
#define DDR0_PCTL_TWTR 0x0108 	///../ucode/ddr3_reg.h:104
#define P_DDR0_PCTL_TWTR 		MMC_REG_ADDR(DDR0_PCTL_TWTR)
#define DDR0_PCTL_TRC 0x00f4 	///../ucode/ddr3_reg.h:105
#define P_DDR0_PCTL_TRC 		MMC_REG_ADDR(DDR0_PCTL_TRC)
#define DDR0_PCTL_TRFC 0x00d8 	///../ucode/ddr3_reg.h:106
#define P_DDR0_PCTL_TRFC 		MMC_REG_ADDR(DDR0_PCTL_TRFC)
#define DDR0_PCTL_TMRR 0x013c 	///../ucode/ddr3_reg.h:107
#define P_DDR0_PCTL_TMRR 		MMC_REG_ADDR(DDR0_PCTL_TMRR)
#define DDR0_PCTL_TCKESR 0x0140 	///../ucode/ddr3_reg.h:108
#define P_DDR0_PCTL_TCKESR 		MMC_REG_ADDR(DDR0_PCTL_TCKESR)
#define DDR0_PCTL_TZQCL 0x0138 	///../ucode/ddr3_reg.h:109
#define P_DDR0_PCTL_TZQCL 		MMC_REG_ADDR(DDR0_PCTL_TZQCL)
#define DDR0_PCTL_TRRD 0x00fc 	///../ucode/ddr3_reg.h:110
#define P_DDR0_PCTL_TRRD 		MMC_REG_ADDR(DDR0_PCTL_TRRD)
#define DDR0_PCTL_TRP 0x00dc 	///../ucode/ddr3_reg.h:111
#define P_DDR0_PCTL_TRP 		MMC_REG_ADDR(DDR0_PCTL_TRP)
#define DDR0_PCTL_TZQCS 0x0118 	///../ucode/ddr3_reg.h:112
#define P_DDR0_PCTL_TZQCS 		MMC_REG_ADDR(DDR0_PCTL_TZQCS)
#define DDR0_PCTL_TXPDLL 0x0114 	///../ucode/ddr3_reg.h:113
#define P_DDR0_PCTL_TXPDLL 		MMC_REG_ADDR(DDR0_PCTL_TXPDLL)
#define DDR0_PCTL_ECCCFG 0x0180 	///../ucode/ddr3_reg.h:114
#define P_DDR0_PCTL_ECCCFG 		MMC_REG_ADDR(DDR0_PCTL_ECCCFG)
#define DDR0_PCTL_ECCLOG 0x018c 	///../ucode/ddr3_reg.h:115
#define P_DDR0_PCTL_ECCLOG 		MMC_REG_ADDR(DDR0_PCTL_ECCLOG)
#define DDR0_PCTL_ECCCLR 0x0188 	///../ucode/ddr3_reg.h:116
#define P_DDR0_PCTL_ECCCLR 		MMC_REG_ADDR(DDR0_PCTL_ECCCLR)
#define DDR0_PCTL_ECCTST 0x0184 	///../ucode/ddr3_reg.h:117
#define P_DDR0_PCTL_ECCTST 		MMC_REG_ADDR(DDR0_PCTL_ECCTST)
#define DDR0_PCTL_DTUWD0 0x0210 	///../ucode/ddr3_reg.h:118
#define P_DDR0_PCTL_DTUWD0 		MMC_REG_ADDR(DDR0_PCTL_DTUWD0)
#define DDR0_PCTL_DTUWD1 0x0214 	///../ucode/ddr3_reg.h:119
#define P_DDR0_PCTL_DTUWD1 		MMC_REG_ADDR(DDR0_PCTL_DTUWD1)
#define DDR0_PCTL_DTUWACTL 0x0200 	///../ucode/ddr3_reg.h:120
#define P_DDR0_PCTL_DTUWACTL 		MMC_REG_ADDR(DDR0_PCTL_DTUWACTL)
#define DDR0_PCTL_DTULFSRRD 0x0238 	///../ucode/ddr3_reg.h:121
#define P_DDR0_PCTL_DTULFSRRD 		MMC_REG_ADDR(DDR0_PCTL_DTULFSRRD)
#define DDR0_PCTL_DTUWD2 0x0218 	///../ucode/ddr3_reg.h:122
#define P_DDR0_PCTL_DTUWD2 		MMC_REG_ADDR(DDR0_PCTL_DTUWD2)
#define DDR0_PCTL_DTUWD3 0x021c 	///../ucode/ddr3_reg.h:123
#define P_DDR0_PCTL_DTUWD3 		MMC_REG_ADDR(DDR0_PCTL_DTUWD3)
#define DDR0_PCTL_DTULFSRWD 0x0234 	///../ucode/ddr3_reg.h:124
#define P_DDR0_PCTL_DTULFSRWD 		MMC_REG_ADDR(DDR0_PCTL_DTULFSRWD)
#define DDR0_PCTL_DTURACTL 0x0204 	///../ucode/ddr3_reg.h:125
#define P_DDR0_PCTL_DTURACTL 		MMC_REG_ADDR(DDR0_PCTL_DTURACTL)
#define DDR0_PCTL_DTUWDM 0x0220 	///../ucode/ddr3_reg.h:126
#define P_DDR0_PCTL_DTUWDM 		MMC_REG_ADDR(DDR0_PCTL_DTUWDM)
#define DDR0_PCTL_DTURD0 0x0224 	///../ucode/ddr3_reg.h:127
#define P_DDR0_PCTL_DTURD0 		MMC_REG_ADDR(DDR0_PCTL_DTURD0)
#define DDR0_PCTL_DTURD1 0x0228 	///../ucode/ddr3_reg.h:128
#define P_DDR0_PCTL_DTURD1 		MMC_REG_ADDR(DDR0_PCTL_DTURD1)
#define DDR0_PCTL_DTURD2 0x022c 	///../ucode/ddr3_reg.h:129
#define P_DDR0_PCTL_DTURD2 		MMC_REG_ADDR(DDR0_PCTL_DTURD2)
#define DDR0_PCTL_DTURD3 0x0230 	///../ucode/ddr3_reg.h:130
#define P_DDR0_PCTL_DTURD3 		MMC_REG_ADDR(DDR0_PCTL_DTURD3)
#define DDR0_PCTL_DTUCFG 0x0208 	///../ucode/ddr3_reg.h:131
#define P_DDR0_PCTL_DTUCFG 		MMC_REG_ADDR(DDR0_PCTL_DTUCFG)
#define DDR0_PCTL_DTUEAF 0x023c 	///../ucode/ddr3_reg.h:132
#define P_DDR0_PCTL_DTUEAF 		MMC_REG_ADDR(DDR0_PCTL_DTUEAF)
#define DDR0_PCTL_DTUECTL 0x020c 	///../ucode/ddr3_reg.h:133
#define P_DDR0_PCTL_DTUECTL 		MMC_REG_ADDR(DDR0_PCTL_DTUECTL)
#define DDR0_PCTL_DFIODTCFG1 0x0248 	///../ucode/ddr3_reg.h:134
#define P_DDR0_PCTL_DFIODTCFG1 		MMC_REG_ADDR(DDR0_PCTL_DFIODTCFG1)
#define DDR0_PCTL_DFITCTRLDELAY 0x0240 	///../ucode/ddr3_reg.h:135
#define P_DDR0_PCTL_DFITCTRLDELAY 		MMC_REG_ADDR(DDR0_PCTL_DFITCTRLDELAY)
#define DDR0_PCTL_DFIODTRANKMAP 0x024c 	///../ucode/ddr3_reg.h:136
#define P_DDR0_PCTL_DFIODTRANKMAP 		MMC_REG_ADDR(DDR0_PCTL_DFIODTRANKMAP)
#define DDR0_PCTL_DFIODTCFG 0x0244 	///../ucode/ddr3_reg.h:137
#define P_DDR0_PCTL_DFIODTCFG 		MMC_REG_ADDR(DDR0_PCTL_DFIODTCFG)
#define DDR0_PCTL_DFITPHYWRLAT 0x0254 	///../ucode/ddr3_reg.h:138
#define P_DDR0_PCTL_DFITPHYWRLAT 		MMC_REG_ADDR(DDR0_PCTL_DFITPHYWRLAT)
#define DDR0_PCTL_DFITPHYWRDATA 0x0250 	///../ucode/ddr3_reg.h:139
#define P_DDR0_PCTL_DFITPHYWRDATA 		MMC_REG_ADDR(DDR0_PCTL_DFITPHYWRDATA)
#define DDR0_PCTL_DFITRDDATAEN 0x0260 	///../ucode/ddr3_reg.h:140
#define P_DDR0_PCTL_DFITRDDATAEN 		MMC_REG_ADDR(DDR0_PCTL_DFITRDDATAEN)
#define DDR0_PCTL_DFITPHYRDLAT 0x0264 	///../ucode/ddr3_reg.h:141
#define P_DDR0_PCTL_DFITPHYRDLAT 		MMC_REG_ADDR(DDR0_PCTL_DFITPHYRDLAT)
#define DDR0_PCTL_DFITREFMSKI 0x0294 	///../ucode/ddr3_reg.h:142
#define P_DDR0_PCTL_DFITREFMSKI 		MMC_REG_ADDR(DDR0_PCTL_DFITREFMSKI)
#define DDR0_PCTL_DFITPHYUPDTYPE0 0x0270 	///../ucode/ddr3_reg.h:143
#define P_DDR0_PCTL_DFITPHYUPDTYPE0 		MMC_REG_ADDR(DDR0_PCTL_DFITPHYUPDTYPE0)
#define DDR0_PCTL_DFITPHYUPDTYPE1 0x0274 	///../ucode/ddr3_reg.h:144
#define P_DDR0_PCTL_DFITPHYUPDTYPE1 		MMC_REG_ADDR(DDR0_PCTL_DFITPHYUPDTYPE1)
#define DDR0_PCTL_DFITCTRLUPDDLY 0x0288 	///../ucode/ddr3_reg.h:145
#define P_DDR0_PCTL_DFITCTRLUPDDLY 		MMC_REG_ADDR(DDR0_PCTL_DFITCTRLUPDDLY)
#define DDR0_PCTL_DFITPHYUPDTYPE2 0x0278 	///../ucode/ddr3_reg.h:146
#define P_DDR0_PCTL_DFITPHYUPDTYPE2 		MMC_REG_ADDR(DDR0_PCTL_DFITPHYUPDTYPE2)
#define DDR0_PCTL_DFITCTRLUPDMIN 0x0280 	///../ucode/ddr3_reg.h:147
#define P_DDR0_PCTL_DFITCTRLUPDMIN 		MMC_REG_ADDR(DDR0_PCTL_DFITCTRLUPDMIN)
#define DDR0_PCTL_DFITPHYUPDTYPE3 0x027c 	///../ucode/ddr3_reg.h:148
#define P_DDR0_PCTL_DFITPHYUPDTYPE3 		MMC_REG_ADDR(DDR0_PCTL_DFITPHYUPDTYPE3)
#define DDR0_PCTL_DFIUPDCFG 0x0290 	///../ucode/ddr3_reg.h:149
#define P_DDR0_PCTL_DFIUPDCFG 		MMC_REG_ADDR(DDR0_PCTL_DFIUPDCFG)
#define DDR0_PCTL_DFITCTRLUPDMAX 0x0284 	///../ucode/ddr3_reg.h:150
#define P_DDR0_PCTL_DFITCTRLUPDMAX 		MMC_REG_ADDR(DDR0_PCTL_DFITCTRLUPDMAX)
#define DDR0_PCTL_DFITCTRLUPDI 0x0298 	///../ucode/ddr3_reg.h:151
#define P_DDR0_PCTL_DFITCTRLUPDI 		MMC_REG_ADDR(DDR0_PCTL_DFITCTRLUPDI)
#define DDR0_PCTL_DFITRRDLVLEN 0x02b8 	///../ucode/ddr3_reg.h:152
#define P_DDR0_PCTL_DFITRRDLVLEN 		MMC_REG_ADDR(DDR0_PCTL_DFITRRDLVLEN)
#define DDR0_PCTL_DFITRSTAT0 0x02b0 	///../ucode/ddr3_reg.h:153
#define P_DDR0_PCTL_DFITRSTAT0 		MMC_REG_ADDR(DDR0_PCTL_DFITRSTAT0)
#define DDR0_PCTL_DFITRWRLVLEN 0x02b4 	///../ucode/ddr3_reg.h:154
#define P_DDR0_PCTL_DFITRWRLVLEN 		MMC_REG_ADDR(DDR0_PCTL_DFITRWRLVLEN)
#define DDR0_PCTL_DFITRCFG0 0x02ac 	///../ucode/ddr3_reg.h:155
#define P_DDR0_PCTL_DFITRCFG0 		MMC_REG_ADDR(DDR0_PCTL_DFITRCFG0)
#define DDR0_PCTL_DFITRRDLVLGATEEN 0x02bc 	///../ucode/ddr3_reg.h:156
#define P_DDR0_PCTL_DFITRRDLVLGATEEN 		MMC_REG_ADDR(DDR0_PCTL_DFITRRDLVLGATEEN)
#define DDR0_PCTL_DFISTSTAT0 0x02c0 	///../ucode/ddr3_reg.h:157
#define P_DDR0_PCTL_DFISTSTAT0 		MMC_REG_ADDR(DDR0_PCTL_DFISTSTAT0)
#define DDR0_PCTL_DFISTPARLOG 0x02e0 	///../ucode/ddr3_reg.h:158
#define P_DDR0_PCTL_DFISTPARLOG 		MMC_REG_ADDR(DDR0_PCTL_DFISTPARLOG)
#define DDR0_PCTL_DFITDRAMCLKEN 0x02d0 	///../ucode/ddr3_reg.h:159
#define P_DDR0_PCTL_DFITDRAMCLKEN 		MMC_REG_ADDR(DDR0_PCTL_DFITDRAMCLKEN)
#define DDR0_PCTL_DFISTPARCLR 0x02dc 	///../ucode/ddr3_reg.h:160
#define P_DDR0_PCTL_DFISTPARCLR 		MMC_REG_ADDR(DDR0_PCTL_DFISTPARCLR)
#define DDR0_PCTL_DFISTCFG0 0x02c4 	///../ucode/ddr3_reg.h:161
#define P_DDR0_PCTL_DFISTCFG0 		MMC_REG_ADDR(DDR0_PCTL_DFISTCFG0)
#define DDR0_PCTL_DFISTCFG1 0x02c8 	///../ucode/ddr3_reg.h:162
#define P_DDR0_PCTL_DFISTCFG1 		MMC_REG_ADDR(DDR0_PCTL_DFISTCFG1)
#define DDR0_PCTL_DFISTCFG2 0x02d8 	///../ucode/ddr3_reg.h:163
#define P_DDR0_PCTL_DFISTCFG2 		MMC_REG_ADDR(DDR0_PCTL_DFISTCFG2)
#define DDR0_PCTL_DFITDRAMCLKDIS 0x02d4 	///../ucode/ddr3_reg.h:164
#define P_DDR0_PCTL_DFITDRAMCLKDIS 		MMC_REG_ADDR(DDR0_PCTL_DFITDRAMCLKDIS)
#define DDR0_PCTL_DFILPCFG0 0x02f0 	///../ucode/ddr3_reg.h:165
#define P_DDR0_PCTL_DFILPCFG0 		MMC_REG_ADDR(DDR0_PCTL_DFILPCFG0)
#define DDR0_PCTL_DFITRWRLVLDELAY0 0x0318 	///../ucode/ddr3_reg.h:166
#define P_DDR0_PCTL_DFITRWRLVLDELAY0 		MMC_REG_ADDR(DDR0_PCTL_DFITRWRLVLDELAY0)
#define DDR0_PCTL_DFITRWRLVLDELAY1 0x031c 	///../ucode/ddr3_reg.h:167
#define P_DDR0_PCTL_DFITRWRLVLDELAY1 		MMC_REG_ADDR(DDR0_PCTL_DFITRWRLVLDELAY1)
#define DDR0_PCTL_DFITRWRLVLDELAY2 0x0320 	///../ucode/ddr3_reg.h:168
#define P_DDR0_PCTL_DFITRWRLVLDELAY2 		MMC_REG_ADDR(DDR0_PCTL_DFITRWRLVLDELAY2)
#define DDR0_PCTL_DFITRRDLVLRESP0 0x030c 	///../ucode/ddr3_reg.h:169
#define P_DDR0_PCTL_DFITRRDLVLRESP0 		MMC_REG_ADDR(DDR0_PCTL_DFITRRDLVLRESP0)
#define DDR0_PCTL_DFITRRDLVLRESP1 0x0310 	///../ucode/ddr3_reg.h:170
#define P_DDR0_PCTL_DFITRRDLVLRESP1 		MMC_REG_ADDR(DDR0_PCTL_DFITRRDLVLRESP1)
#define DDR0_PCTL_DFITRRDLVLRESP2 0x0314 	///../ucode/ddr3_reg.h:171
#define P_DDR0_PCTL_DFITRRDLVLRESP2 		MMC_REG_ADDR(DDR0_PCTL_DFITRRDLVLRESP2)
#define DDR0_PCTL_DFITRWRLVLRESP0 0x0300 	///../ucode/ddr3_reg.h:172
#define P_DDR0_PCTL_DFITRWRLVLRESP0 		MMC_REG_ADDR(DDR0_PCTL_DFITRWRLVLRESP0)
#define DDR0_PCTL_DFITRRDLVLDELAY0 0x0324 	///../ucode/ddr3_reg.h:173
#define P_DDR0_PCTL_DFITRRDLVLDELAY0 		MMC_REG_ADDR(DDR0_PCTL_DFITRRDLVLDELAY0)
#define DDR0_PCTL_DFITRRDLVLDELAY1 0x0328 	///../ucode/ddr3_reg.h:174
#define P_DDR0_PCTL_DFITRRDLVLDELAY1 		MMC_REG_ADDR(DDR0_PCTL_DFITRRDLVLDELAY1)
#define DDR0_PCTL_DFITRWRLVLRESP1 0x0304 	///../ucode/ddr3_reg.h:175
#define P_DDR0_PCTL_DFITRWRLVLRESP1 		MMC_REG_ADDR(DDR0_PCTL_DFITRWRLVLRESP1)
#define DDR0_PCTL_DFITRRDLVLDELAY2 0x032c 	///../ucode/ddr3_reg.h:176
#define P_DDR0_PCTL_DFITRRDLVLDELAY2 		MMC_REG_ADDR(DDR0_PCTL_DFITRRDLVLDELAY2)
#define DDR0_PCTL_DFITRWRLVLRESP2 0x0308 	///../ucode/ddr3_reg.h:177
#define P_DDR0_PCTL_DFITRWRLVLRESP2 		MMC_REG_ADDR(DDR0_PCTL_DFITRWRLVLRESP2)
#define DDR0_PCTL_DFITRRDLVLGATEDELAY0 0x0330 	///../ucode/ddr3_reg.h:178
#define P_DDR0_PCTL_DFITRRDLVLGATEDELAY0 		MMC_REG_ADDR(DDR0_PCTL_DFITRRDLVLGATEDELAY0)
#define DDR0_PCTL_DFITRCMD 0x033c 	///../ucode/ddr3_reg.h:179
#define P_DDR0_PCTL_DFITRCMD 		MMC_REG_ADDR(DDR0_PCTL_DFITRCMD)
#define DDR0_PCTL_DFITRRDLVLGATEDELAY1 0x0334 	///../ucode/ddr3_reg.h:180
#define P_DDR0_PCTL_DFITRRDLVLGATEDELAY1 		MMC_REG_ADDR(DDR0_PCTL_DFITRRDLVLGATEDELAY1)
#define DDR0_PCTL_DFITRRDLVLGATEDELAY2 0x0338 	///../ucode/ddr3_reg.h:181
#define P_DDR0_PCTL_DFITRRDLVLGATEDELAY2 		MMC_REG_ADDR(DDR0_PCTL_DFITRRDLVLGATEDELAY2)
#define DDR0_PCTL_IPTR 0x03fc 	///../ucode/ddr3_reg.h:182
#define P_DDR0_PCTL_IPTR 		MMC_REG_ADDR(DDR0_PCTL_IPTR)
#define DDR0_PCTL_IPVR 0x03f8 	///../ucode/ddr3_reg.h:183
#define P_DDR0_PCTL_IPVR 		MMC_REG_ADDR(DDR0_PCTL_IPVR)
#define DDR0_PUB_RIDR (0x1000 + (0x00 << 2)) 	///../ucode/ddr3_reg.h:186
#define P_DDR0_PUB_RIDR 		MMC_REG_ADDR(DDR0_PUB_RIDR)
#define DDR0_PUB_PIR (0x1000 + (0x01 << 2)) 	///../ucode/ddr3_reg.h:187
#define P_DDR0_PUB_PIR 		MMC_REG_ADDR(DDR0_PUB_PIR)
#define DDR0_PUB_PGCR0 (0x1000 + (0x02 << 2)) 	///../ucode/ddr3_reg.h:188
#define P_DDR0_PUB_PGCR0 		MMC_REG_ADDR(DDR0_PUB_PGCR0)
#define DDR0_PUB_PGCR1 (0x1000 + (0x03 << 2)) 	///../ucode/ddr3_reg.h:189
#define P_DDR0_PUB_PGCR1 		MMC_REG_ADDR(DDR0_PUB_PGCR1)
#define DDR0_PUB_PGCR2 (0x1000 + (0x04 << 2)) 	///../ucode/ddr3_reg.h:190
#define P_DDR0_PUB_PGCR2 		MMC_REG_ADDR(DDR0_PUB_PGCR2)
#define DDR0_PUB_PGCR3 (0x1000 + (0x05 << 2)) 	///../ucode/ddr3_reg.h:191
#define P_DDR0_PUB_PGCR3 		MMC_REG_ADDR(DDR0_PUB_PGCR3)
#define DDR0_PUB_PGSR0 (0x1000 + (0x06 << 2)) 	///../ucode/ddr3_reg.h:192
#define P_DDR0_PUB_PGSR0 		MMC_REG_ADDR(DDR0_PUB_PGSR0)
#define DDR0_PUB_PGSR1 (0x1000 + (0x07 << 2)) 	///../ucode/ddr3_reg.h:193
#define P_DDR0_PUB_PGSR1 		MMC_REG_ADDR(DDR0_PUB_PGSR1)
#define DDR0_PUB_PLLCR (0x1000 + (0x08 << 2)) 	///../ucode/ddr3_reg.h:194
#define P_DDR0_PUB_PLLCR 		MMC_REG_ADDR(DDR0_PUB_PLLCR)
#define DDR0_PUB_PTR0 (0x1000 + (0x09 << 2)) 	///../ucode/ddr3_reg.h:195
#define P_DDR0_PUB_PTR0 		MMC_REG_ADDR(DDR0_PUB_PTR0)
#define DDR0_PUB_PTR1 (0x1000 + (0x0A << 2)) 	///../ucode/ddr3_reg.h:196
#define P_DDR0_PUB_PTR1 		MMC_REG_ADDR(DDR0_PUB_PTR1)
#define DDR0_PUB_PTR2 (0x1000 + (0x0B << 2)) 	///../ucode/ddr3_reg.h:197
#define P_DDR0_PUB_PTR2 		MMC_REG_ADDR(DDR0_PUB_PTR2)
#define DDR0_PUB_PTR3 (0x1000 + (0x0C << 2)) 	///../ucode/ddr3_reg.h:198
#define P_DDR0_PUB_PTR3 		MMC_REG_ADDR(DDR0_PUB_PTR3)
#define DDR0_PUB_PTR4 (0x1000 + (0x0D << 2)) 	///../ucode/ddr3_reg.h:199
#define P_DDR0_PUB_PTR4 		MMC_REG_ADDR(DDR0_PUB_PTR4)
#define DDR0_PUB_ACMDLR (0x1000 + (0x0E << 2)) 	///../ucode/ddr3_reg.h:200
#define P_DDR0_PUB_ACMDLR 		MMC_REG_ADDR(DDR0_PUB_ACMDLR)
#define DDR0_PUB_ACLCDLR (0x1000 + (0x0F << 2)) 	///../ucode/ddr3_reg.h:201
#define P_DDR0_PUB_ACLCDLR 		MMC_REG_ADDR(DDR0_PUB_ACLCDLR)
#define DDR0_PUB_ACBDLR0 (0x1000 + (0x10 << 2)) 	///../ucode/ddr3_reg.h:202
#define P_DDR0_PUB_ACBDLR0 		MMC_REG_ADDR(DDR0_PUB_ACBDLR0)
#define DDR0_PUB_ACBDLR1 (0x1000 + (0x11 << 2)) 	///../ucode/ddr3_reg.h:203
#define P_DDR0_PUB_ACBDLR1 		MMC_REG_ADDR(DDR0_PUB_ACBDLR1)
#define DDR0_PUB_ACBDLR2 (0x1000 + (0x12 << 2)) 	///../ucode/ddr3_reg.h:204
#define P_DDR0_PUB_ACBDLR2 		MMC_REG_ADDR(DDR0_PUB_ACBDLR2)
#define DDR0_PUB_ACBDLR3 (0x1000 + (0x13 << 2)) 	///../ucode/ddr3_reg.h:205
#define P_DDR0_PUB_ACBDLR3 		MMC_REG_ADDR(DDR0_PUB_ACBDLR3)
#define DDR0_PUB_ACBDLR4 (0x1000 + (0x14 << 2)) 	///../ucode/ddr3_reg.h:206
#define P_DDR0_PUB_ACBDLR4 		MMC_REG_ADDR(DDR0_PUB_ACBDLR4)
#define DDR0_PUB_ACBDLR5 (0x1000 + (0x15 << 2)) 	///../ucode/ddr3_reg.h:207
#define P_DDR0_PUB_ACBDLR5 		MMC_REG_ADDR(DDR0_PUB_ACBDLR5)
#define DDR0_PUB_ACBDLR6 (0x1000 + (0x16 << 2)) 	///../ucode/ddr3_reg.h:208
#define P_DDR0_PUB_ACBDLR6 		MMC_REG_ADDR(DDR0_PUB_ACBDLR6)
#define DDR0_PUB_ACBDLR7 (0x1000 + (0x17 << 2)) 	///../ucode/ddr3_reg.h:209
#define P_DDR0_PUB_ACBDLR7 		MMC_REG_ADDR(DDR0_PUB_ACBDLR7)
#define DDR0_PUB_ACBDLR8 (0x1000 + (0x18 << 2)) 	///../ucode/ddr3_reg.h:210
#define P_DDR0_PUB_ACBDLR8 		MMC_REG_ADDR(DDR0_PUB_ACBDLR8)
#define DDR0_PUB_ACBDLR9 (0x1000 + (0x19 << 2)) 	///../ucode/ddr3_reg.h:211
#define P_DDR0_PUB_ACBDLR9 		MMC_REG_ADDR(DDR0_PUB_ACBDLR9)
#define DDR0_PUB_ACIOCR0 (0x1000 + (0x1A << 2)) 	///../ucode/ddr3_reg.h:212
#define P_DDR0_PUB_ACIOCR0 		MMC_REG_ADDR(DDR0_PUB_ACIOCR0)
#define DDR0_PUB_ACIOCR1 (0x1000 + (0x1B << 2)) 	///../ucode/ddr3_reg.h:213
#define P_DDR0_PUB_ACIOCR1 		MMC_REG_ADDR(DDR0_PUB_ACIOCR1)
#define DDR0_PUB_ACIOCR2 (0x1000 + (0x1C << 2)) 	///../ucode/ddr3_reg.h:214
#define P_DDR0_PUB_ACIOCR2 		MMC_REG_ADDR(DDR0_PUB_ACIOCR2)
#define DDR0_PUB_ACIOCR3 (0x1000 + (0x1D << 2)) 	///../ucode/ddr3_reg.h:215
#define P_DDR0_PUB_ACIOCR3 		MMC_REG_ADDR(DDR0_PUB_ACIOCR3)
#define DDR0_PUB_ACIOCR4 (0x1000 + (0x1E << 2)) 	///../ucode/ddr3_reg.h:216
#define P_DDR0_PUB_ACIOCR4 		MMC_REG_ADDR(DDR0_PUB_ACIOCR4)
#define DDR0_PUB_ACIOCR5 (0x1000 + (0x1F << 2)) 	///../ucode/ddr3_reg.h:217
#define P_DDR0_PUB_ACIOCR5 		MMC_REG_ADDR(DDR0_PUB_ACIOCR5)
#define DDR0_PUB_DXCCR (0x1000 + (0x20 << 2)) 	///../ucode/ddr3_reg.h:218
#define P_DDR0_PUB_DXCCR 		MMC_REG_ADDR(DDR0_PUB_DXCCR)
#define DDR0_PUB_DSGCR (0x1000 + (0x21 << 2)) 	///../ucode/ddr3_reg.h:219
#define P_DDR0_PUB_DSGCR 		MMC_REG_ADDR(DDR0_PUB_DSGCR)
#define DDR0_PUB_DCR (0x1000 + (0x22 << 2)) 	///../ucode/ddr3_reg.h:220
#define P_DDR0_PUB_DCR 		MMC_REG_ADDR(DDR0_PUB_DCR)
#define DDR0_PUB_DTPR0 (0x1000 + (0x23 << 2)) 	///../ucode/ddr3_reg.h:221
#define P_DDR0_PUB_DTPR0 		MMC_REG_ADDR(DDR0_PUB_DTPR0)
#define DDR0_PUB_DTPR1 (0x1000 + (0x24 << 2)) 	///../ucode/ddr3_reg.h:222
#define P_DDR0_PUB_DTPR1 		MMC_REG_ADDR(DDR0_PUB_DTPR1)
#define DDR0_PUB_DTPR2 (0x1000 + (0x25 << 2)) 	///../ucode/ddr3_reg.h:223
#define P_DDR0_PUB_DTPR2 		MMC_REG_ADDR(DDR0_PUB_DTPR2)
#define DDR0_PUB_DTPR3 (0x1000 + (0x26 << 2)) 	///../ucode/ddr3_reg.h:224
#define P_DDR0_PUB_DTPR3 		MMC_REG_ADDR(DDR0_PUB_DTPR3)
#define DDR0_PUB_MR0 (0x1000 + (0x27 << 2)) 	///../ucode/ddr3_reg.h:225
#define P_DDR0_PUB_MR0 		MMC_REG_ADDR(DDR0_PUB_MR0)
#define DDR0_PUB_MR1 (0x1000 + (0x28 << 2)) 	///../ucode/ddr3_reg.h:226
#define P_DDR0_PUB_MR1 		MMC_REG_ADDR(DDR0_PUB_MR1)
#define DDR0_PUB_MR2 (0x1000 + (0x29 << 2)) 	///../ucode/ddr3_reg.h:227
#define P_DDR0_PUB_MR2 		MMC_REG_ADDR(DDR0_PUB_MR2)
#define DDR0_PUB_MR3 (0x1000 + (0x2A << 2)) 	///../ucode/ddr3_reg.h:228
#define P_DDR0_PUB_MR3 		MMC_REG_ADDR(DDR0_PUB_MR3)
#define DDR0_PUB_ODTCR (0x1000 + (0x2B << 2)) 	///../ucode/ddr3_reg.h:229
#define P_DDR0_PUB_ODTCR 		MMC_REG_ADDR(DDR0_PUB_ODTCR)
#define DDR0_PUB_DTCR (0x1000 + (0x2C << 2)) 	///../ucode/ddr3_reg.h:230
#define P_DDR0_PUB_DTCR 		MMC_REG_ADDR(DDR0_PUB_DTCR)
#define DDR0_PUB_DTAR0 (0x1000 + (0x2D << 2)) 	///../ucode/ddr3_reg.h:231
#define P_DDR0_PUB_DTAR0 		MMC_REG_ADDR(DDR0_PUB_DTAR0)
#define DDR0_PUB_DTAR1 (0x1000 + (0x2E << 2)) 	///../ucode/ddr3_reg.h:232
#define P_DDR0_PUB_DTAR1 		MMC_REG_ADDR(DDR0_PUB_DTAR1)
#define DDR0_PUB_DTAR2 (0x1000 + (0x2F << 2)) 	///../ucode/ddr3_reg.h:233
#define P_DDR0_PUB_DTAR2 		MMC_REG_ADDR(DDR0_PUB_DTAR2)
#define DDR0_PUB_DTAR3 (0x1000 + (0x30 << 2)) 	///../ucode/ddr3_reg.h:234
#define P_DDR0_PUB_DTAR3 		MMC_REG_ADDR(DDR0_PUB_DTAR3)
#define DDR0_PUB_DTDR0 (0x1000 + (0x31 << 2)) 	///../ucode/ddr3_reg.h:235
#define P_DDR0_PUB_DTDR0 		MMC_REG_ADDR(DDR0_PUB_DTDR0)
#define DDR0_PUB_DTDR1 (0x1000 + (0x32 << 2)) 	///../ucode/ddr3_reg.h:236
#define P_DDR0_PUB_DTDR1 		MMC_REG_ADDR(DDR0_PUB_DTDR1)
#define DDR0_PUB_DTEDR0 (0x1000 + (0x33 << 2)) 	///../ucode/ddr3_reg.h:237
#define P_DDR0_PUB_DTEDR0 		MMC_REG_ADDR(DDR0_PUB_DTEDR0)
#define DDR0_PUB_DTEDR1 (0x1000 + (0x34 << 2)) 	///../ucode/ddr3_reg.h:238
#define P_DDR0_PUB_DTEDR1 		MMC_REG_ADDR(DDR0_PUB_DTEDR1)
#define DDR0_PUB_RDIMMGCR0 (0x1000 + (0x35 << 2)) 	///../ucode/ddr3_reg.h:239
#define P_DDR0_PUB_RDIMMGCR0 		MMC_REG_ADDR(DDR0_PUB_RDIMMGCR0)
#define DDR0_PUB_RDIMMGCR1 (0x1000 + (0x36 << 2)) 	///../ucode/ddr3_reg.h:240
#define P_DDR0_PUB_RDIMMGCR1 		MMC_REG_ADDR(DDR0_PUB_RDIMMGCR1)
#define DDR0_PUB_RDIMMCR0 (0x1000 + (0x37 << 2)) 	///../ucode/ddr3_reg.h:241
#define P_DDR0_PUB_RDIMMCR0 		MMC_REG_ADDR(DDR0_PUB_RDIMMCR0)
#define DDR0_PUB_RDIMMCR1 (0x1000 + (0x38 << 2)) 	///../ucode/ddr3_reg.h:242
#define P_DDR0_PUB_RDIMMCR1 		MMC_REG_ADDR(DDR0_PUB_RDIMMCR1)
#define DDR0_PUB_GPR0 (0x1000 + (0x39 << 2)) 	///../ucode/ddr3_reg.h:243
#define P_DDR0_PUB_GPR0 		MMC_REG_ADDR(DDR0_PUB_GPR0)
#define DDR0_PUB_GPR1 (0x1000 + (0x3A << 2)) 	///../ucode/ddr3_reg.h:244
#define P_DDR0_PUB_GPR1 		MMC_REG_ADDR(DDR0_PUB_GPR1)
#define DDR0_PUB_CATR0 (0x1000 + (0x3B << 2)) 	///../ucode/ddr3_reg.h:245
#define P_DDR0_PUB_CATR0 		MMC_REG_ADDR(DDR0_PUB_CATR0)
#define DDR0_PUB_CATR1 (0x1000 + (0x3C << 2)) 	///../ucode/ddr3_reg.h:246
#define P_DDR0_PUB_CATR1 		MMC_REG_ADDR(DDR0_PUB_CATR1)
#define DDR0_PUB_DCUAR (0x1000 + (0x60 << 2)) 	///../ucode/ddr3_reg.h:248
#define P_DDR0_PUB_DCUAR 		MMC_REG_ADDR(DDR0_PUB_DCUAR)
#define DDR0_PUB_DCUDR (0x1000 + (0x61 << 2)) 	///../ucode/ddr3_reg.h:249
#define P_DDR0_PUB_DCUDR 		MMC_REG_ADDR(DDR0_PUB_DCUDR)
#define DDR0_PUB_DCURR (0x1000 + (0x62 << 2)) 	///../ucode/ddr3_reg.h:250
#define P_DDR0_PUB_DCURR 		MMC_REG_ADDR(DDR0_PUB_DCURR)
#define DDR0_PUB_DCULR (0x1000 + (0x63 << 2)) 	///../ucode/ddr3_reg.h:251
#define P_DDR0_PUB_DCULR 		MMC_REG_ADDR(DDR0_PUB_DCULR)
#define DDR0_PUB_DCUGCR (0x1000 + (0x64 << 2)) 	///../ucode/ddr3_reg.h:252
#define P_DDR0_PUB_DCUGCR 		MMC_REG_ADDR(DDR0_PUB_DCUGCR)
#define DDR0_PUB_DCUTPR (0x1000 + (0x65 << 2)) 	///../ucode/ddr3_reg.h:253
#define P_DDR0_PUB_DCUTPR 		MMC_REG_ADDR(DDR0_PUB_DCUTPR)
#define DDR0_PUB_DCUSR0 (0x1000 + (0x66 << 2)) 	///../ucode/ddr3_reg.h:254
#define P_DDR0_PUB_DCUSR0 		MMC_REG_ADDR(DDR0_PUB_DCUSR0)
#define DDR0_PUB_DCUSR1 (0x1000 + (0x67 << 2)) 	///../ucode/ddr3_reg.h:255
#define P_DDR0_PUB_DCUSR1 		MMC_REG_ADDR(DDR0_PUB_DCUSR1)
#define DDR0_PUB_BISTRR (0x1000 + (0x70 << 2)) 	///../ucode/ddr3_reg.h:257
#define P_DDR0_PUB_BISTRR 		MMC_REG_ADDR(DDR0_PUB_BISTRR)
#define DDR0_PUB_BISTWCR (0x1000 + (0x71 << 2)) 	///../ucode/ddr3_reg.h:258
#define P_DDR0_PUB_BISTWCR 		MMC_REG_ADDR(DDR0_PUB_BISTWCR)
#define DDR0_PUB_BISTMSKR0 (0x1000 + (0x72 << 2)) 	///../ucode/ddr3_reg.h:259
#define P_DDR0_PUB_BISTMSKR0 		MMC_REG_ADDR(DDR0_PUB_BISTMSKR0)
#define DDR0_PUB_BISTMSKR1 (0x1000 + (0x73 << 2)) 	///../ucode/ddr3_reg.h:260
#define P_DDR0_PUB_BISTMSKR1 		MMC_REG_ADDR(DDR0_PUB_BISTMSKR1)
#define DDR0_PUB_BISTMSKR2 (0x1000 + (0x74 << 2)) 	///../ucode/ddr3_reg.h:261
#define P_DDR0_PUB_BISTMSKR2 		MMC_REG_ADDR(DDR0_PUB_BISTMSKR2)
#define DDR0_PUB_BISTLSR (0x1000 + (0x75 << 2)) 	///../ucode/ddr3_reg.h:262
#define P_DDR0_PUB_BISTLSR 		MMC_REG_ADDR(DDR0_PUB_BISTLSR)
#define DDR0_PUB_BISTAR0 (0x1000 + (0x76 << 2)) 	///../ucode/ddr3_reg.h:263
#define P_DDR0_PUB_BISTAR0 		MMC_REG_ADDR(DDR0_PUB_BISTAR0)
#define DDR0_PUB_BISTAR1 (0x1000 + (0x77 << 2)) 	///../ucode/ddr3_reg.h:264
#define P_DDR0_PUB_BISTAR1 		MMC_REG_ADDR(DDR0_PUB_BISTAR1)
#define DDR0_PUB_BISTAR2 (0x1000 + (0x78 << 2)) 	///../ucode/ddr3_reg.h:265
#define P_DDR0_PUB_BISTAR2 		MMC_REG_ADDR(DDR0_PUB_BISTAR2)
#define DDR0_PUB_BISTUDPR (0x1000 + (0x79 << 2)) 	///../ucode/ddr3_reg.h:266
#define P_DDR0_PUB_BISTUDPR 		MMC_REG_ADDR(DDR0_PUB_BISTUDPR)
#define DDR0_PUB_BISTGSR (0x1000 + (0x7A << 2)) 	///../ucode/ddr3_reg.h:267
#define P_DDR0_PUB_BISTGSR 		MMC_REG_ADDR(DDR0_PUB_BISTGSR)
#define DDR0_PUB_BISTWER (0x1000 + (0x7B << 2)) 	///../ucode/ddr3_reg.h:268
#define P_DDR0_PUB_BISTWER 		MMC_REG_ADDR(DDR0_PUB_BISTWER)
#define DDR0_PUB_BISTBER0 (0x1000 + (0x7C << 2)) 	///../ucode/ddr3_reg.h:269
#define P_DDR0_PUB_BISTBER0 		MMC_REG_ADDR(DDR0_PUB_BISTBER0)
#define DDR0_PUB_BISTBER1 (0x1000 + (0x7D << 2)) 	///../ucode/ddr3_reg.h:270
#define P_DDR0_PUB_BISTBER1 		MMC_REG_ADDR(DDR0_PUB_BISTBER1)
#define DDR0_PUB_BISTBER2 (0x1000 + (0x7E << 2)) 	///../ucode/ddr3_reg.h:271
#define P_DDR0_PUB_BISTBER2 		MMC_REG_ADDR(DDR0_PUB_BISTBER2)
#define DDR0_PUB_BISTBER3 (0x1000 + (0x7F << 2)) 	///../ucode/ddr3_reg.h:272
#define P_DDR0_PUB_BISTBER3 		MMC_REG_ADDR(DDR0_PUB_BISTBER3)
#define DDR0_PUB_BISTWCSR (0x1000 + (0x80 << 2)) 	///../ucode/ddr3_reg.h:273
#define P_DDR0_PUB_BISTWCSR 		MMC_REG_ADDR(DDR0_PUB_BISTWCSR)
#define DDR0_PUB_BISTFWR0 (0x1000 + (0x81 << 2)) 	///../ucode/ddr3_reg.h:274
#define P_DDR0_PUB_BISTFWR0 		MMC_REG_ADDR(DDR0_PUB_BISTFWR0)
#define DDR0_PUB_BISTFWR1 (0x1000 + (0x82 << 2)) 	///../ucode/ddr3_reg.h:275
#define P_DDR0_PUB_BISTFWR1 		MMC_REG_ADDR(DDR0_PUB_BISTFWR1)
#define DDR0_PUB_BISTFWR2 (0x1000 + (0x83 << 2)) 	///../ucode/ddr3_reg.h:276
#define P_DDR0_PUB_BISTFWR2 		MMC_REG_ADDR(DDR0_PUB_BISTFWR2)
#define DDR0_PUB_IOVCR0 (0x1000 + (0x8E << 2)) 	///../ucode/ddr3_reg.h:278
#define P_DDR0_PUB_IOVCR0 		MMC_REG_ADDR(DDR0_PUB_IOVCR0)
#define DDR0_PUB_IOVCR1 (0x1000 + (0x8F << 2)) 	///../ucode/ddr3_reg.h:279
#define P_DDR0_PUB_IOVCR1 		MMC_REG_ADDR(DDR0_PUB_IOVCR1)
#define DDR0_PUB_ZQCR (0x1000 + (0x90 << 2)) 	///../ucode/ddr3_reg.h:280
#define P_DDR0_PUB_ZQCR 		MMC_REG_ADDR(DDR0_PUB_ZQCR)
#define DDR0_PUB_ZQ0PR (0x1000 + (0x91 << 2)) 	///../ucode/ddr3_reg.h:281
#define P_DDR0_PUB_ZQ0PR 		MMC_REG_ADDR(DDR0_PUB_ZQ0PR)
#define DDR0_PUB_ZQ0DR (0x1000 + (0x92 << 2)) 	///../ucode/ddr3_reg.h:282
#define P_DDR0_PUB_ZQ0DR 		MMC_REG_ADDR(DDR0_PUB_ZQ0DR)
#define DDR0_PUB_ZQ0SR (0x1000 + (0x93 << 2)) 	///../ucode/ddr3_reg.h:283
#define P_DDR0_PUB_ZQ0SR 		MMC_REG_ADDR(DDR0_PUB_ZQ0SR)
#define DDR0_PUB_ZQ1PR (0x1000 + (0x95 << 2)) 	///../ucode/ddr3_reg.h:285
#define P_DDR0_PUB_ZQ1PR 		MMC_REG_ADDR(DDR0_PUB_ZQ1PR)
#define DDR0_PUB_ZQ1DR (0x1000 + (0x96 << 2)) 	///../ucode/ddr3_reg.h:286
#define P_DDR0_PUB_ZQ1DR 		MMC_REG_ADDR(DDR0_PUB_ZQ1DR)
#define DDR0_PUB_ZQ1SR (0x1000 + (0x97 << 2)) 	///../ucode/ddr3_reg.h:287
#define P_DDR0_PUB_ZQ1SR 		MMC_REG_ADDR(DDR0_PUB_ZQ1SR)
#define DDR0_PUB_ZQ2PR (0x1000 + (0x99 << 2)) 	///../ucode/ddr3_reg.h:289
#define P_DDR0_PUB_ZQ2PR 		MMC_REG_ADDR(DDR0_PUB_ZQ2PR)
#define DDR0_PUB_ZQ2DR (0x1000 + (0x9A << 2)) 	///../ucode/ddr3_reg.h:290
#define P_DDR0_PUB_ZQ2DR 		MMC_REG_ADDR(DDR0_PUB_ZQ2DR)
#define DDR0_PUB_ZQ2SR (0x1000 + (0x9B << 2)) 	///../ucode/ddr3_reg.h:291
#define P_DDR0_PUB_ZQ2SR 		MMC_REG_ADDR(DDR0_PUB_ZQ2SR)
#define DDR0_PUB_ZQ3PR (0x1000 + (0x9D << 2)) 	///../ucode/ddr3_reg.h:293
#define P_DDR0_PUB_ZQ3PR 		MMC_REG_ADDR(DDR0_PUB_ZQ3PR)
#define DDR0_PUB_ZQ3DR (0x1000 + (0x9E << 2)) 	///../ucode/ddr3_reg.h:294
#define P_DDR0_PUB_ZQ3DR 		MMC_REG_ADDR(DDR0_PUB_ZQ3DR)
#define DDR0_PUB_ZQ3SR (0x1000 + (0x9F << 2)) 	///../ucode/ddr3_reg.h:295
#define P_DDR0_PUB_ZQ3SR 		MMC_REG_ADDR(DDR0_PUB_ZQ3SR)
#define DDR0_PUB_DX0GCR0 (0x1000 + (0xA0 << 2)) 	///../ucode/ddr3_reg.h:296
#define P_DDR0_PUB_DX0GCR0 		MMC_REG_ADDR(DDR0_PUB_DX0GCR0)
#define DDR0_PUB_DX0GCR1 (0x1000 + (0xA1 << 2)) 	///../ucode/ddr3_reg.h:297
#define P_DDR0_PUB_DX0GCR1 		MMC_REG_ADDR(DDR0_PUB_DX0GCR1)
#define DDR0_PUB_DX0GCR2 (0x1000 + (0xA2 << 2)) 	///../ucode/ddr3_reg.h:298
#define P_DDR0_PUB_DX0GCR2 		MMC_REG_ADDR(DDR0_PUB_DX0GCR2)
#define DDR0_PUB_DX0GCR3 (0x1000 + (0xA3 << 2)) 	///../ucode/ddr3_reg.h:299
#define P_DDR0_PUB_DX0GCR3 		MMC_REG_ADDR(DDR0_PUB_DX0GCR3)
#define DDR0_PUB_DX0GSR0 (0x1000 + (0xA4 << 2)) 	///../ucode/ddr3_reg.h:300
#define P_DDR0_PUB_DX0GSR0 		MMC_REG_ADDR(DDR0_PUB_DX0GSR0)
#define DDR0_PUB_DX0GSR1 (0x1000 + (0xA5 << 2)) 	///../ucode/ddr3_reg.h:301
#define P_DDR0_PUB_DX0GSR1 		MMC_REG_ADDR(DDR0_PUB_DX0GSR1)
#define DDR0_PUB_DX0GSR2 (0x1000 + (0xA6 << 2)) 	///../ucode/ddr3_reg.h:302
#define P_DDR0_PUB_DX0GSR2 		MMC_REG_ADDR(DDR0_PUB_DX0GSR2)
#define DDR0_PUB_DX0BDLR0 (0x1000 + (0xA7 << 2)) 	///../ucode/ddr3_reg.h:303
#define P_DDR0_PUB_DX0BDLR0 		MMC_REG_ADDR(DDR0_PUB_DX0BDLR0)
#define DDR0_PUB_DX0BDLR1 (0x1000 + (0xA8 << 2)) 	///../ucode/ddr3_reg.h:304
#define P_DDR0_PUB_DX0BDLR1 		MMC_REG_ADDR(DDR0_PUB_DX0BDLR1)
#define DDR0_PUB_DX0BDLR2 (0x1000 + (0xA9 << 2)) 	///../ucode/ddr3_reg.h:305
#define P_DDR0_PUB_DX0BDLR2 		MMC_REG_ADDR(DDR0_PUB_DX0BDLR2)
#define DDR0_PUB_DX0BDLR3 (0x1000 + (0xAA << 2)) 	///../ucode/ddr3_reg.h:306
#define P_DDR0_PUB_DX0BDLR3 		MMC_REG_ADDR(DDR0_PUB_DX0BDLR3)
#define DDR0_PUB_DX0BDLR4 (0x1000 + (0xAB << 2)) 	///../ucode/ddr3_reg.h:307
#define P_DDR0_PUB_DX0BDLR4 		MMC_REG_ADDR(DDR0_PUB_DX0BDLR4)
#define DDR0_PUB_DX0BDLR5 (0x1000 + (0xAC << 2)) 	///../ucode/ddr3_reg.h:308
#define P_DDR0_PUB_DX0BDLR5 		MMC_REG_ADDR(DDR0_PUB_DX0BDLR5)
#define DDR0_PUB_DX0BDLR6 (0x1000 + (0xAD << 2)) 	///../ucode/ddr3_reg.h:309
#define P_DDR0_PUB_DX0BDLR6 		MMC_REG_ADDR(DDR0_PUB_DX0BDLR6)
#define DDR0_PUB_DX0LCDLR0 (0x1000 + (0xAE << 2)) 	///../ucode/ddr3_reg.h:310
#define P_DDR0_PUB_DX0LCDLR0 		MMC_REG_ADDR(DDR0_PUB_DX0LCDLR0)
#define DDR0_PUB_DX0LCDLR1 (0x1000 + (0xAF << 2)) 	///../ucode/ddr3_reg.h:311
#define P_DDR0_PUB_DX0LCDLR1 		MMC_REG_ADDR(DDR0_PUB_DX0LCDLR1)
#define DDR0_PUB_DX0LCDLR2 (0x1000 + (0xB0 << 2)) 	///../ucode/ddr3_reg.h:312
#define P_DDR0_PUB_DX0LCDLR2 		MMC_REG_ADDR(DDR0_PUB_DX0LCDLR2)
#define DDR0_PUB_DX0MDLR (0x1000 + (0xB1 << 2)) 	///../ucode/ddr3_reg.h:313
#define P_DDR0_PUB_DX0MDLR 		MMC_REG_ADDR(DDR0_PUB_DX0MDLR)
#define DDR0_PUB_DX0GTR (0x1000 + (0xB2 << 2)) 	///../ucode/ddr3_reg.h:314
#define P_DDR0_PUB_DX0GTR 		MMC_REG_ADDR(DDR0_PUB_DX0GTR)
#define DDR0_PUB_DX1GCR0 (0x1000 + (0xC0 << 2)) 	///../ucode/ddr3_reg.h:316
#define P_DDR0_PUB_DX1GCR0 		MMC_REG_ADDR(DDR0_PUB_DX1GCR0)
#define DDR0_PUB_DX1GCR1 (0x1000 + (0xC1 << 2)) 	///../ucode/ddr3_reg.h:317
#define P_DDR0_PUB_DX1GCR1 		MMC_REG_ADDR(DDR0_PUB_DX1GCR1)
#define DDR0_PUB_DX1GCR2 (0x1000 + (0xC2 << 2)) 	///../ucode/ddr3_reg.h:318
#define P_DDR0_PUB_DX1GCR2 		MMC_REG_ADDR(DDR0_PUB_DX1GCR2)
#define DDR0_PUB_DX1GCR3 (0x1000 + (0xC3 << 2)) 	///../ucode/ddr3_reg.h:319
#define P_DDR0_PUB_DX1GCR3 		MMC_REG_ADDR(DDR0_PUB_DX1GCR3)
#define DDR0_PUB_DX1GSR0 (0x1000 + (0xC4 << 2)) 	///../ucode/ddr3_reg.h:320
#define P_DDR0_PUB_DX1GSR0 		MMC_REG_ADDR(DDR0_PUB_DX1GSR0)
#define DDR0_PUB_DX1GSR1 (0x1000 + (0xC5 << 2)) 	///../ucode/ddr3_reg.h:321
#define P_DDR0_PUB_DX1GSR1 		MMC_REG_ADDR(DDR0_PUB_DX1GSR1)
#define DDR0_PUB_DX1GSR2 (0x1000 + (0xC6 << 2)) 	///../ucode/ddr3_reg.h:322
#define P_DDR0_PUB_DX1GSR2 		MMC_REG_ADDR(DDR0_PUB_DX1GSR2)
#define DDR0_PUB_DX1BDLR0 (0x1000 + (0xC7 << 2)) 	///../ucode/ddr3_reg.h:323
#define P_DDR0_PUB_DX1BDLR0 		MMC_REG_ADDR(DDR0_PUB_DX1BDLR0)
#define DDR0_PUB_DX1BDLR1 (0x1000 + (0xC8 << 2)) 	///../ucode/ddr3_reg.h:324
#define P_DDR0_PUB_DX1BDLR1 		MMC_REG_ADDR(DDR0_PUB_DX1BDLR1)
#define DDR0_PUB_DX1BDLR2 (0x1000 + (0xC9 << 2)) 	///../ucode/ddr3_reg.h:325
#define P_DDR0_PUB_DX1BDLR2 		MMC_REG_ADDR(DDR0_PUB_DX1BDLR2)
#define DDR0_PUB_DX1BDLR3 (0x1000 + (0xCA << 2)) 	///../ucode/ddr3_reg.h:326
#define P_DDR0_PUB_DX1BDLR3 		MMC_REG_ADDR(DDR0_PUB_DX1BDLR3)
#define DDR0_PUB_DX1BDLR4 (0x1000 + (0xCB << 2)) 	///../ucode/ddr3_reg.h:327
#define P_DDR0_PUB_DX1BDLR4 		MMC_REG_ADDR(DDR0_PUB_DX1BDLR4)
#define DDR0_PUB_DX1BDLR5 (0x1000 + (0xCC << 2)) 	///../ucode/ddr3_reg.h:328
#define P_DDR0_PUB_DX1BDLR5 		MMC_REG_ADDR(DDR0_PUB_DX1BDLR5)
#define DDR0_PUB_DX1BDLR6 (0x1000 + (0xCD << 2)) 	///../ucode/ddr3_reg.h:329
#define P_DDR0_PUB_DX1BDLR6 		MMC_REG_ADDR(DDR0_PUB_DX1BDLR6)
#define DDR0_PUB_DX1LCDLR0 (0x1000 + (0xCE << 2)) 	///../ucode/ddr3_reg.h:330
#define P_DDR0_PUB_DX1LCDLR0 		MMC_REG_ADDR(DDR0_PUB_DX1LCDLR0)
#define DDR0_PUB_DX1LCDLR1 (0x1000 + (0xCF << 2)) 	///../ucode/ddr3_reg.h:331
#define P_DDR0_PUB_DX1LCDLR1 		MMC_REG_ADDR(DDR0_PUB_DX1LCDLR1)
#define DDR0_PUB_DX1LCDLR2 (0x1000 + (0xD0 << 2)) 	///../ucode/ddr3_reg.h:332
#define P_DDR0_PUB_DX1LCDLR2 		MMC_REG_ADDR(DDR0_PUB_DX1LCDLR2)
#define DDR0_PUB_DX1MDLR (0x1000 + (0xD1 << 2)) 	///../ucode/ddr3_reg.h:333
#define P_DDR0_PUB_DX1MDLR 		MMC_REG_ADDR(DDR0_PUB_DX1MDLR)
#define DDR0_PUB_DX1GTR (0x1000 + (0xD2 << 2)) 	///../ucode/ddr3_reg.h:334
#define P_DDR0_PUB_DX1GTR 		MMC_REG_ADDR(DDR0_PUB_DX1GTR)
#define DDR0_PUB_DX2GCR0 (0x1000 + (0xE0 << 2)) 	///../ucode/ddr3_reg.h:335
#define P_DDR0_PUB_DX2GCR0 		MMC_REG_ADDR(DDR0_PUB_DX2GCR0)
#define DDR0_PUB_DX2GCR1 (0x1000 + (0xE1 << 2)) 	///../ucode/ddr3_reg.h:336
#define P_DDR0_PUB_DX2GCR1 		MMC_REG_ADDR(DDR0_PUB_DX2GCR1)
#define DDR0_PUB_DX2GCR2 (0x1000 + (0xE2 << 2)) 	///../ucode/ddr3_reg.h:337
#define P_DDR0_PUB_DX2GCR2 		MMC_REG_ADDR(DDR0_PUB_DX2GCR2)
#define DDR0_PUB_DX2GCR3 (0x1000 + (0xE3 << 2)) 	///../ucode/ddr3_reg.h:338
#define P_DDR0_PUB_DX2GCR3 		MMC_REG_ADDR(DDR0_PUB_DX2GCR3)
#define DDR0_PUB_DX2GSR0 (0x1000 + (0xE4 << 2)) 	///../ucode/ddr3_reg.h:339
#define P_DDR0_PUB_DX2GSR0 		MMC_REG_ADDR(DDR0_PUB_DX2GSR0)
#define DDR0_PUB_DX2GSR1 (0x1000 + (0xE5 << 2)) 	///../ucode/ddr3_reg.h:340
#define P_DDR0_PUB_DX2GSR1 		MMC_REG_ADDR(DDR0_PUB_DX2GSR1)
#define DDR0_PUB_DX2GSR2 (0x1000 + (0xE6 << 2)) 	///../ucode/ddr3_reg.h:341
#define P_DDR0_PUB_DX2GSR2 		MMC_REG_ADDR(DDR0_PUB_DX2GSR2)
#define DDR0_PUB_DX2BDLR0 (0x1000 + (0xE7 << 2)) 	///../ucode/ddr3_reg.h:342
#define P_DDR0_PUB_DX2BDLR0 		MMC_REG_ADDR(DDR0_PUB_DX2BDLR0)
#define DDR0_PUB_DX2BDLR1 (0x1000 + (0xE8 << 2)) 	///../ucode/ddr3_reg.h:343
#define P_DDR0_PUB_DX2BDLR1 		MMC_REG_ADDR(DDR0_PUB_DX2BDLR1)
#define DDR0_PUB_DX2BDLR2 (0x1000 + (0xE9 << 2)) 	///../ucode/ddr3_reg.h:344
#define P_DDR0_PUB_DX2BDLR2 		MMC_REG_ADDR(DDR0_PUB_DX2BDLR2)
#define DDR0_PUB_DX2BDLR3 (0x1000 + (0xEA << 2)) 	///../ucode/ddr3_reg.h:345
#define P_DDR0_PUB_DX2BDLR3 		MMC_REG_ADDR(DDR0_PUB_DX2BDLR3)
#define DDR0_PUB_DX2BDLR4 (0x1000 + (0xEB << 2)) 	///../ucode/ddr3_reg.h:346
#define P_DDR0_PUB_DX2BDLR4 		MMC_REG_ADDR(DDR0_PUB_DX2BDLR4)
#define DDR0_PUB_DX2BDLR5 (0x1000 + (0xEC << 2)) 	///../ucode/ddr3_reg.h:347
#define P_DDR0_PUB_DX2BDLR5 		MMC_REG_ADDR(DDR0_PUB_DX2BDLR5)
#define DDR0_PUB_DX2BDLR6 (0x1000 + (0xED << 2)) 	///../ucode/ddr3_reg.h:348
#define P_DDR0_PUB_DX2BDLR6 		MMC_REG_ADDR(DDR0_PUB_DX2BDLR6)
#define DDR0_PUB_DX2LCDLR0 (0x1000 + (0xEE << 2)) 	///../ucode/ddr3_reg.h:349
#define P_DDR0_PUB_DX2LCDLR0 		MMC_REG_ADDR(DDR0_PUB_DX2LCDLR0)
#define DDR0_PUB_DX2LCDLR1 (0x1000 + (0xEF << 2)) 	///../ucode/ddr3_reg.h:350
#define P_DDR0_PUB_DX2LCDLR1 		MMC_REG_ADDR(DDR0_PUB_DX2LCDLR1)
#define DDR0_PUB_DX2LCDLR2 (0x1000 + (0xF0 << 2)) 	///../ucode/ddr3_reg.h:351
#define P_DDR0_PUB_DX2LCDLR2 		MMC_REG_ADDR(DDR0_PUB_DX2LCDLR2)
#define DDR0_PUB_DX2MDLR (0x1000 + (0xF1 << 2)) 	///../ucode/ddr3_reg.h:352
#define P_DDR0_PUB_DX2MDLR 		MMC_REG_ADDR(DDR0_PUB_DX2MDLR)
#define DDR0_PUB_DX2GTR (0x1000 + (0xF2 << 2)) 	///../ucode/ddr3_reg.h:353
#define P_DDR0_PUB_DX2GTR 		MMC_REG_ADDR(DDR0_PUB_DX2GTR)
#define DDR0_PUB_DX3GCR0 (0x1000 + (0x100 << 2)) 	///../ucode/ddr3_reg.h:354
#define P_DDR0_PUB_DX3GCR0 		MMC_REG_ADDR(DDR0_PUB_DX3GCR0)
#define DDR0_PUB_DX3GCR1 (0x1000 + (0x101 << 2)) 	///../ucode/ddr3_reg.h:355
#define P_DDR0_PUB_DX3GCR1 		MMC_REG_ADDR(DDR0_PUB_DX3GCR1)
#define DDR0_PUB_DX3GCR2 (0x1000 + (0x102 << 2)) 	///../ucode/ddr3_reg.h:356
#define P_DDR0_PUB_DX3GCR2 		MMC_REG_ADDR(DDR0_PUB_DX3GCR2)
#define DDR0_PUB_DX3GCR3 (0x1000 + (0x103 << 2)) 	///../ucode/ddr3_reg.h:357
#define P_DDR0_PUB_DX3GCR3 		MMC_REG_ADDR(DDR0_PUB_DX3GCR3)
#define DDR0_PUB_DX3GSR0 (0x1000 + (0x104 << 2)) 	///../ucode/ddr3_reg.h:358
#define P_DDR0_PUB_DX3GSR0 		MMC_REG_ADDR(DDR0_PUB_DX3GSR0)
#define DDR0_PUB_DX3GSR1 (0x1000 + (0x105 << 2)) 	///../ucode/ddr3_reg.h:359
#define P_DDR0_PUB_DX3GSR1 		MMC_REG_ADDR(DDR0_PUB_DX3GSR1)
#define DDR0_PUB_DX3GSR2 (0x1000 + (0x106 << 2)) 	///../ucode/ddr3_reg.h:360
#define P_DDR0_PUB_DX3GSR2 		MMC_REG_ADDR(DDR0_PUB_DX3GSR2)
#define DDR0_PUB_DX3BDLR0 (0x1000 + (0x107 << 2)) 	///../ucode/ddr3_reg.h:361
#define P_DDR0_PUB_DX3BDLR0 		MMC_REG_ADDR(DDR0_PUB_DX3BDLR0)
#define DDR0_PUB_DX3BDLR1 (0x1000 + (0x108 << 2)) 	///../ucode/ddr3_reg.h:362
#define P_DDR0_PUB_DX3BDLR1 		MMC_REG_ADDR(DDR0_PUB_DX3BDLR1)
#define DDR0_PUB_DX3BDLR2 (0x1000 + (0x109 << 2)) 	///../ucode/ddr3_reg.h:363
#define P_DDR0_PUB_DX3BDLR2 		MMC_REG_ADDR(DDR0_PUB_DX3BDLR2)
#define DDR0_PUB_DX3BDLR3 (0x1000 + (0x10A << 2)) 	///../ucode/ddr3_reg.h:364
#define P_DDR0_PUB_DX3BDLR3 		MMC_REG_ADDR(DDR0_PUB_DX3BDLR3)
#define DDR0_PUB_DX3BDLR4 (0x1000 + (0x10B << 2)) 	///../ucode/ddr3_reg.h:365
#define P_DDR0_PUB_DX3BDLR4 		MMC_REG_ADDR(DDR0_PUB_DX3BDLR4)
#define DDR0_PUB_DX3BDLR5 (0x1000 + (0x10C << 2)) 	///../ucode/ddr3_reg.h:366
#define P_DDR0_PUB_DX3BDLR5 		MMC_REG_ADDR(DDR0_PUB_DX3BDLR5)
#define DDR0_PUB_DX3BDLR6 (0x1000 + (0x10D << 2)) 	///../ucode/ddr3_reg.h:367
#define P_DDR0_PUB_DX3BDLR6 		MMC_REG_ADDR(DDR0_PUB_DX3BDLR6)
#define DDR0_PUB_DX3LCDLR0 (0x1000 + (0x10E << 2)) 	///../ucode/ddr3_reg.h:368
#define P_DDR0_PUB_DX3LCDLR0 		MMC_REG_ADDR(DDR0_PUB_DX3LCDLR0)
#define DDR0_PUB_DX3LCDLR1 (0x1000 + (0x10F << 2)) 	///../ucode/ddr3_reg.h:369
#define P_DDR0_PUB_DX3LCDLR1 		MMC_REG_ADDR(DDR0_PUB_DX3LCDLR1)
#define DDR0_PUB_DX3LCDLR2 (0x1000 + (0x110 << 2)) 	///../ucode/ddr3_reg.h:370
#define P_DDR0_PUB_DX3LCDLR2 		MMC_REG_ADDR(DDR0_PUB_DX3LCDLR2)
#define DDR0_PUB_DX3MDLR (0x1000 + (0x111 << 2)) 	///../ucode/ddr3_reg.h:371
#define P_DDR0_PUB_DX3MDLR 		MMC_REG_ADDR(DDR0_PUB_DX3MDLR)
#define DDR0_PUB_DX3GTR (0x1000 + (0x112 << 2)) 	///../ucode/ddr3_reg.h:372
#define P_DDR0_PUB_DX3GTR 		MMC_REG_ADDR(DDR0_PUB_DX3GTR)
#define DDR0_PUB_DX4GCR0 (0x1000 + (0x120 << 2)) 	///../ucode/ddr3_reg.h:373
#define P_DDR0_PUB_DX4GCR0 		MMC_REG_ADDR(DDR0_PUB_DX4GCR0)
#define DDR0_PUB_DX4GCR1 (0x1000 + (0x121 << 2)) 	///../ucode/ddr3_reg.h:374
#define P_DDR0_PUB_DX4GCR1 		MMC_REG_ADDR(DDR0_PUB_DX4GCR1)
#define DDR0_PUB_DX4GCR2 (0x1000 + (0x122 << 2)) 	///../ucode/ddr3_reg.h:375
#define P_DDR0_PUB_DX4GCR2 		MMC_REG_ADDR(DDR0_PUB_DX4GCR2)
#define DDR0_PUB_DX4GCR3 (0x1000 + (0x123 << 2)) 	///../ucode/ddr3_reg.h:376
#define P_DDR0_PUB_DX4GCR3 		MMC_REG_ADDR(DDR0_PUB_DX4GCR3)
#define DDR0_PUB_DX4GSR0 (0x1000 + (0x124 << 2)) 	///../ucode/ddr3_reg.h:377
#define P_DDR0_PUB_DX4GSR0 		MMC_REG_ADDR(DDR0_PUB_DX4GSR0)
#define DDR0_PUB_DX4GSR1 (0x1000 + (0x125 << 2)) 	///../ucode/ddr3_reg.h:378
#define P_DDR0_PUB_DX4GSR1 		MMC_REG_ADDR(DDR0_PUB_DX4GSR1)
#define DDR0_PUB_DX4GSR2 (0x1000 + (0x126 << 2)) 	///../ucode/ddr3_reg.h:379
#define P_DDR0_PUB_DX4GSR2 		MMC_REG_ADDR(DDR0_PUB_DX4GSR2)
#define DDR0_PUB_DX4BDLR0 (0x1000 + (0x127 << 2)) 	///../ucode/ddr3_reg.h:380
#define P_DDR0_PUB_DX4BDLR0 		MMC_REG_ADDR(DDR0_PUB_DX4BDLR0)
#define DDR0_PUB_DX4BDLR1 (0x1000 + (0x128 << 2)) 	///../ucode/ddr3_reg.h:381
#define P_DDR0_PUB_DX4BDLR1 		MMC_REG_ADDR(DDR0_PUB_DX4BDLR1)
#define DDR0_PUB_DX4BDLR2 (0x1000 + (0x129 << 2)) 	///../ucode/ddr3_reg.h:382
#define P_DDR0_PUB_DX4BDLR2 		MMC_REG_ADDR(DDR0_PUB_DX4BDLR2)
#define DDR0_PUB_DX4BDLR3 (0x1000 + (0x12A << 2)) 	///../ucode/ddr3_reg.h:383
#define P_DDR0_PUB_DX4BDLR3 		MMC_REG_ADDR(DDR0_PUB_DX4BDLR3)
#define DDR0_PUB_DX4BDLR4 (0x1000 + (0x12B << 2)) 	///../ucode/ddr3_reg.h:384
#define P_DDR0_PUB_DX4BDLR4 		MMC_REG_ADDR(DDR0_PUB_DX4BDLR4)
#define DDR0_PUB_DX4BDLR5 (0x1000 + (0x12C << 2)) 	///../ucode/ddr3_reg.h:385
#define P_DDR0_PUB_DX4BDLR5 		MMC_REG_ADDR(DDR0_PUB_DX4BDLR5)
#define DDR0_PUB_DX4BDLR6 (0x1000 + (0x12D << 2)) 	///../ucode/ddr3_reg.h:386
#define P_DDR0_PUB_DX4BDLR6 		MMC_REG_ADDR(DDR0_PUB_DX4BDLR6)
#define DDR0_PUB_DX4LCDLR0 (0x1000 + (0x12E << 2)) 	///../ucode/ddr3_reg.h:387
#define P_DDR0_PUB_DX4LCDLR0 		MMC_REG_ADDR(DDR0_PUB_DX4LCDLR0)
#define DDR0_PUB_DX4LCDLR1 (0x1000 + (0x12F << 2)) 	///../ucode/ddr3_reg.h:388
#define P_DDR0_PUB_DX4LCDLR1 		MMC_REG_ADDR(DDR0_PUB_DX4LCDLR1)
#define DDR0_PUB_DX4LCDLR2 (0x1000 + (0x130 << 2)) 	///../ucode/ddr3_reg.h:389
#define P_DDR0_PUB_DX4LCDLR2 		MMC_REG_ADDR(DDR0_PUB_DX4LCDLR2)
#define DDR0_PUB_DX4MDLR (0x1000 + (0x131 << 2)) 	///../ucode/ddr3_reg.h:390
#define P_DDR0_PUB_DX4MDLR 		MMC_REG_ADDR(DDR0_PUB_DX4MDLR)
#define DDR0_PUB_DX4GTR (0x1000 + (0x132 << 2)) 	///../ucode/ddr3_reg.h:391
#define P_DDR0_PUB_DX4GTR 		MMC_REG_ADDR(DDR0_PUB_DX4GTR)
#define DDR0_PUB_DX5GCR0 (0x1000 + (0x140 << 2)) 	///../ucode/ddr3_reg.h:392
#define P_DDR0_PUB_DX5GCR0 		MMC_REG_ADDR(DDR0_PUB_DX5GCR0)
#define DDR0_PUB_DX5GCR1 (0x1000 + (0x141 << 2)) 	///../ucode/ddr3_reg.h:393
#define P_DDR0_PUB_DX5GCR1 		MMC_REG_ADDR(DDR0_PUB_DX5GCR1)
#define DDR0_PUB_DX5GCR2 (0x1000 + (0x142 << 2)) 	///../ucode/ddr3_reg.h:394
#define P_DDR0_PUB_DX5GCR2 		MMC_REG_ADDR(DDR0_PUB_DX5GCR2)
#define DDR0_PUB_DX5GCR3 (0x1000 + (0x143 << 2)) 	///../ucode/ddr3_reg.h:395
#define P_DDR0_PUB_DX5GCR3 		MMC_REG_ADDR(DDR0_PUB_DX5GCR3)
#define DDR0_PUB_DX5GSR0 (0x1000 + (0x144 << 2)) 	///../ucode/ddr3_reg.h:396
#define P_DDR0_PUB_DX5GSR0 		MMC_REG_ADDR(DDR0_PUB_DX5GSR0)
#define DDR0_PUB_DX5GSR1 (0x1000 + (0x145 << 2)) 	///../ucode/ddr3_reg.h:397
#define P_DDR0_PUB_DX5GSR1 		MMC_REG_ADDR(DDR0_PUB_DX5GSR1)
#define DDR0_PUB_DX5GSR2 (0x1000 + (0x146 << 2)) 	///../ucode/ddr3_reg.h:398
#define P_DDR0_PUB_DX5GSR2 		MMC_REG_ADDR(DDR0_PUB_DX5GSR2)
#define DDR0_PUB_DX5BDLR0 (0x1000 + (0x147 << 2)) 	///../ucode/ddr3_reg.h:399
#define P_DDR0_PUB_DX5BDLR0 		MMC_REG_ADDR(DDR0_PUB_DX5BDLR0)
#define DDR0_PUB_DX5BDLR1 (0x1000 + (0x148 << 2)) 	///../ucode/ddr3_reg.h:400
#define P_DDR0_PUB_DX5BDLR1 		MMC_REG_ADDR(DDR0_PUB_DX5BDLR1)
#define DDR0_PUB_DX5BDLR2 (0x1000 + (0x149 << 2)) 	///../ucode/ddr3_reg.h:401
#define P_DDR0_PUB_DX5BDLR2 		MMC_REG_ADDR(DDR0_PUB_DX5BDLR2)
#define DDR0_PUB_DX5BDLR3 (0x1000 + (0x14A << 2)) 	///../ucode/ddr3_reg.h:402
#define P_DDR0_PUB_DX5BDLR3 		MMC_REG_ADDR(DDR0_PUB_DX5BDLR3)
#define DDR0_PUB_DX5BDLR4 (0x1000 + (0x14B << 2)) 	///../ucode/ddr3_reg.h:403
#define P_DDR0_PUB_DX5BDLR4 		MMC_REG_ADDR(DDR0_PUB_DX5BDLR4)
#define DDR0_PUB_DX5BDLR5 (0x1000 + (0x14C << 2)) 	///../ucode/ddr3_reg.h:404
#define P_DDR0_PUB_DX5BDLR5 		MMC_REG_ADDR(DDR0_PUB_DX5BDLR5)
#define DDR0_PUB_DX5BDLR6 (0x1000 + (0x14D << 2)) 	///../ucode/ddr3_reg.h:405
#define P_DDR0_PUB_DX5BDLR6 		MMC_REG_ADDR(DDR0_PUB_DX5BDLR6)
#define DDR0_PUB_DX5LCDLR0 (0x1000 + (0x14E << 2)) 	///../ucode/ddr3_reg.h:406
#define P_DDR0_PUB_DX5LCDLR0 		MMC_REG_ADDR(DDR0_PUB_DX5LCDLR0)
#define DDR0_PUB_DX5LCDLR1 (0x1000 + (0x14F << 2)) 	///../ucode/ddr3_reg.h:407
#define P_DDR0_PUB_DX5LCDLR1 		MMC_REG_ADDR(DDR0_PUB_DX5LCDLR1)
#define DDR0_PUB_DX5LCDLR2 (0x1000 + (0x150 << 2)) 	///../ucode/ddr3_reg.h:408
#define P_DDR0_PUB_DX5LCDLR2 		MMC_REG_ADDR(DDR0_PUB_DX5LCDLR2)
#define DDR0_PUB_DX5MDLR (0x1000 + (0x151 << 2)) 	///../ucode/ddr3_reg.h:409
#define P_DDR0_PUB_DX5MDLR 		MMC_REG_ADDR(DDR0_PUB_DX5MDLR)
#define DDR0_PUB_DX5GTR (0x1000 + (0x152 << 2)) 	///../ucode/ddr3_reg.h:410
#define P_DDR0_PUB_DX5GTR 		MMC_REG_ADDR(DDR0_PUB_DX5GTR)
#define DDR0_PUB_DX6GCR0 (0x1000 + (0x160 << 2)) 	///../ucode/ddr3_reg.h:411
#define P_DDR0_PUB_DX6GCR0 		MMC_REG_ADDR(DDR0_PUB_DX6GCR0)
#define DDR0_PUB_DX6GCR1 (0x1000 + (0x161 << 2)) 	///../ucode/ddr3_reg.h:412
#define P_DDR0_PUB_DX6GCR1 		MMC_REG_ADDR(DDR0_PUB_DX6GCR1)
#define DDR0_PUB_DX6GCR2 (0x1000 + (0x162 << 2)) 	///../ucode/ddr3_reg.h:413
#define P_DDR0_PUB_DX6GCR2 		MMC_REG_ADDR(DDR0_PUB_DX6GCR2)
#define DDR0_PUB_DX6GCR3 (0x1000 + (0x163 << 2)) 	///../ucode/ddr3_reg.h:414
#define P_DDR0_PUB_DX6GCR3 		MMC_REG_ADDR(DDR0_PUB_DX6GCR3)
#define DDR0_PUB_DX6GSR0 (0x1000 + (0x164 << 2)) 	///../ucode/ddr3_reg.h:415
#define P_DDR0_PUB_DX6GSR0 		MMC_REG_ADDR(DDR0_PUB_DX6GSR0)
#define DDR0_PUB_DX6GSR1 (0x1000 + (0x165 << 2)) 	///../ucode/ddr3_reg.h:416
#define P_DDR0_PUB_DX6GSR1 		MMC_REG_ADDR(DDR0_PUB_DX6GSR1)
#define DDR0_PUB_DX6GSR2 (0x1000 + (0x166 << 2)) 	///../ucode/ddr3_reg.h:417
#define P_DDR0_PUB_DX6GSR2 		MMC_REG_ADDR(DDR0_PUB_DX6GSR2)
#define DDR0_PUB_DX6BDLR0 (0x1000 + (0x167 << 2)) 	///../ucode/ddr3_reg.h:418
#define P_DDR0_PUB_DX6BDLR0 		MMC_REG_ADDR(DDR0_PUB_DX6BDLR0)
#define DDR0_PUB_DX6BDLR1 (0x1000 + (0x168 << 2)) 	///../ucode/ddr3_reg.h:419
#define P_DDR0_PUB_DX6BDLR1 		MMC_REG_ADDR(DDR0_PUB_DX6BDLR1)
#define DDR0_PUB_DX6BDLR2 (0x1000 + (0x169 << 2)) 	///../ucode/ddr3_reg.h:420
#define P_DDR0_PUB_DX6BDLR2 		MMC_REG_ADDR(DDR0_PUB_DX6BDLR2)
#define DDR0_PUB_DX6BDLR3 (0x1000 + (0x16A << 2)) 	///../ucode/ddr3_reg.h:421
#define P_DDR0_PUB_DX6BDLR3 		MMC_REG_ADDR(DDR0_PUB_DX6BDLR3)
#define DDR0_PUB_DX6BDLR4 (0x1000 + (0x16B << 2)) 	///../ucode/ddr3_reg.h:422
#define P_DDR0_PUB_DX6BDLR4 		MMC_REG_ADDR(DDR0_PUB_DX6BDLR4)
#define DDR0_PUB_DX6BDLR5 (0x1000 + (0x16C << 2)) 	///../ucode/ddr3_reg.h:423
#define P_DDR0_PUB_DX6BDLR5 		MMC_REG_ADDR(DDR0_PUB_DX6BDLR5)
#define DDR0_PUB_DX6BDLR6 (0x1000 + (0x16D << 2)) 	///../ucode/ddr3_reg.h:424
#define P_DDR0_PUB_DX6BDLR6 		MMC_REG_ADDR(DDR0_PUB_DX6BDLR6)
#define DDR0_PUB_DX6LCDLR0 (0x1000 + (0x16E << 2)) 	///../ucode/ddr3_reg.h:425
#define P_DDR0_PUB_DX6LCDLR0 		MMC_REG_ADDR(DDR0_PUB_DX6LCDLR0)
#define DDR0_PUB_DX6LCDLR1 (0x1000 + (0x16F << 2)) 	///../ucode/ddr3_reg.h:426
#define P_DDR0_PUB_DX6LCDLR1 		MMC_REG_ADDR(DDR0_PUB_DX6LCDLR1)
#define DDR0_PUB_DX6LCDLR2 (0x1000 + (0x170 << 2)) 	///../ucode/ddr3_reg.h:427
#define P_DDR0_PUB_DX6LCDLR2 		MMC_REG_ADDR(DDR0_PUB_DX6LCDLR2)
#define DDR0_PUB_DX6MDLR (0x1000 + (0x171 << 2)) 	///../ucode/ddr3_reg.h:428
#define P_DDR0_PUB_DX6MDLR 		MMC_REG_ADDR(DDR0_PUB_DX6MDLR)
#define DDR0_PUB_DX6GTR (0x1000 + (0x172 << 2)) 	///../ucode/ddr3_reg.h:429
#define P_DDR0_PUB_DX6GTR 		MMC_REG_ADDR(DDR0_PUB_DX6GTR)
#define DDR0_PUB_DX7GCR0 (0x1000 + (0x180 << 2)) 	///../ucode/ddr3_reg.h:430
#define P_DDR0_PUB_DX7GCR0 		MMC_REG_ADDR(DDR0_PUB_DX7GCR0)
#define DDR0_PUB_DX7GCR1 (0x1000 + (0x181 << 2)) 	///../ucode/ddr3_reg.h:431
#define P_DDR0_PUB_DX7GCR1 		MMC_REG_ADDR(DDR0_PUB_DX7GCR1)
#define DDR0_PUB_DX7GCR2 (0x1000 + (0x182 << 2)) 	///../ucode/ddr3_reg.h:432
#define P_DDR0_PUB_DX7GCR2 		MMC_REG_ADDR(DDR0_PUB_DX7GCR2)
#define DDR0_PUB_DX7GCR3 (0x1000 + (0x183 << 2)) 	///../ucode/ddr3_reg.h:433
#define P_DDR0_PUB_DX7GCR3 		MMC_REG_ADDR(DDR0_PUB_DX7GCR3)
#define DDR0_PUB_DX7GSR0 (0x1000 + (0x184 << 2)) 	///../ucode/ddr3_reg.h:434
#define P_DDR0_PUB_DX7GSR0 		MMC_REG_ADDR(DDR0_PUB_DX7GSR0)
#define DDR0_PUB_DX7GSR1 (0x1000 + (0x185 << 2)) 	///../ucode/ddr3_reg.h:435
#define P_DDR0_PUB_DX7GSR1 		MMC_REG_ADDR(DDR0_PUB_DX7GSR1)
#define DDR0_PUB_DX7GSR2 (0x1000 + (0x186 << 2)) 	///../ucode/ddr3_reg.h:436
#define P_DDR0_PUB_DX7GSR2 		MMC_REG_ADDR(DDR0_PUB_DX7GSR2)
#define DDR0_PUB_DX7BDLR0 (0x1000 + (0x187 << 2)) 	///../ucode/ddr3_reg.h:437
#define P_DDR0_PUB_DX7BDLR0 		MMC_REG_ADDR(DDR0_PUB_DX7BDLR0)
#define DDR0_PUB_DX7BDLR1 (0x1000 + (0x188 << 2)) 	///../ucode/ddr3_reg.h:438
#define P_DDR0_PUB_DX7BDLR1 		MMC_REG_ADDR(DDR0_PUB_DX7BDLR1)
#define DDR0_PUB_DX7BDLR2 (0x1000 + (0x189 << 2)) 	///../ucode/ddr3_reg.h:439
#define P_DDR0_PUB_DX7BDLR2 		MMC_REG_ADDR(DDR0_PUB_DX7BDLR2)
#define DDR0_PUB_DX7BDLR3 (0x1000 + (0x18A << 2)) 	///../ucode/ddr3_reg.h:440
#define P_DDR0_PUB_DX7BDLR3 		MMC_REG_ADDR(DDR0_PUB_DX7BDLR3)
#define DDR0_PUB_DX7BDLR4 (0x1000 + (0x18B << 2)) 	///../ucode/ddr3_reg.h:441
#define P_DDR0_PUB_DX7BDLR4 		MMC_REG_ADDR(DDR0_PUB_DX7BDLR4)
#define DDR0_PUB_DX7BDLR5 (0x1000 + (0x18C << 2)) 	///../ucode/ddr3_reg.h:442
#define P_DDR0_PUB_DX7BDLR5 		MMC_REG_ADDR(DDR0_PUB_DX7BDLR5)
#define DDR0_PUB_DX7BDLR6 (0x1000 + (0x18D << 2)) 	///../ucode/ddr3_reg.h:443
#define P_DDR0_PUB_DX7BDLR6 		MMC_REG_ADDR(DDR0_PUB_DX7BDLR6)
#define DDR0_PUB_DX7LCDLR0 (0x1000 + (0x18E << 2)) 	///../ucode/ddr3_reg.h:444
#define P_DDR0_PUB_DX7LCDLR0 		MMC_REG_ADDR(DDR0_PUB_DX7LCDLR0)
#define DDR0_PUB_DX7LCDLR1 (0x1000 + (0x18F << 2)) 	///../ucode/ddr3_reg.h:445
#define P_DDR0_PUB_DX7LCDLR1 		MMC_REG_ADDR(DDR0_PUB_DX7LCDLR1)
#define DDR0_PUB_DX7LCDLR2 (0x1000 + (0x190 << 2)) 	///../ucode/ddr3_reg.h:446
#define P_DDR0_PUB_DX7LCDLR2 		MMC_REG_ADDR(DDR0_PUB_DX7LCDLR2)
#define DDR0_PUB_DX7MDLR (0x1000 + (0x191 << 2)) 	///../ucode/ddr3_reg.h:447
#define P_DDR0_PUB_DX7MDLR 		MMC_REG_ADDR(DDR0_PUB_DX7MDLR)
#define DDR0_PUB_DX7GTR (0x1000 + (0x192 << 2)) 	///../ucode/ddr3_reg.h:448
#define P_DDR0_PUB_DX7GTR 		MMC_REG_ADDR(DDR0_PUB_DX7GTR)
#define DDR0_PUB_DX8GCR0 (0x1000 + (0x1A0 << 2)) 	///../ucode/ddr3_reg.h:449
#define P_DDR0_PUB_DX8GCR0 		MMC_REG_ADDR(DDR0_PUB_DX8GCR0)
#define DDR0_PUB_DX8GCR1 (0x1000 + (0x1A1 << 2)) 	///../ucode/ddr3_reg.h:450
#define P_DDR0_PUB_DX8GCR1 		MMC_REG_ADDR(DDR0_PUB_DX8GCR1)
#define DDR0_PUB_DX8GCR2 (0x1000 + (0x1A2 << 2)) 	///../ucode/ddr3_reg.h:451
#define P_DDR0_PUB_DX8GCR2 		MMC_REG_ADDR(DDR0_PUB_DX8GCR2)
#define DDR0_PUB_DX8GCR3 (0x1000 + (0x1A3 << 2)) 	///../ucode/ddr3_reg.h:452
#define P_DDR0_PUB_DX8GCR3 		MMC_REG_ADDR(DDR0_PUB_DX8GCR3)
#define DDR0_PUB_DX8GSR0 (0x1000 + (0x1A4 << 2)) 	///../ucode/ddr3_reg.h:453
#define P_DDR0_PUB_DX8GSR0 		MMC_REG_ADDR(DDR0_PUB_DX8GSR0)
#define DDR0_PUB_DX8GSR1 (0x1000 + (0x1A5 << 2)) 	///../ucode/ddr3_reg.h:454
#define P_DDR0_PUB_DX8GSR1 		MMC_REG_ADDR(DDR0_PUB_DX8GSR1)
#define DDR0_PUB_DX8GSR2 (0x1000 + (0x1A6 << 2)) 	///../ucode/ddr3_reg.h:455
#define P_DDR0_PUB_DX8GSR2 		MMC_REG_ADDR(DDR0_PUB_DX8GSR2)
#define DDR0_PUB_DX8BDLR0 (0x1000 + (0x1A7 << 2)) 	///../ucode/ddr3_reg.h:456
#define P_DDR0_PUB_DX8BDLR0 		MMC_REG_ADDR(DDR0_PUB_DX8BDLR0)
#define DDR0_PUB_DX8BDLR1 (0x1000 + (0x1A8 << 2)) 	///../ucode/ddr3_reg.h:457
#define P_DDR0_PUB_DX8BDLR1 		MMC_REG_ADDR(DDR0_PUB_DX8BDLR1)
#define DDR0_PUB_DX8BDLR2 (0x1000 + (0x1A9 << 2)) 	///../ucode/ddr3_reg.h:458
#define P_DDR0_PUB_DX8BDLR2 		MMC_REG_ADDR(DDR0_PUB_DX8BDLR2)
#define DDR0_PUB_DX8BDLR3 (0x1000 + (0x1AA << 2)) 	///../ucode/ddr3_reg.h:459
#define P_DDR0_PUB_DX8BDLR3 		MMC_REG_ADDR(DDR0_PUB_DX8BDLR3)
#define DDR0_PUB_DX8BDLR4 (0x1000 + (0x1AB << 2)) 	///../ucode/ddr3_reg.h:460
#define P_DDR0_PUB_DX8BDLR4 		MMC_REG_ADDR(DDR0_PUB_DX8BDLR4)
#define DDR0_PUB_DX8BDLR5 (0x1000 + (0x1AC << 2)) 	///../ucode/ddr3_reg.h:461
#define P_DDR0_PUB_DX8BDLR5 		MMC_REG_ADDR(DDR0_PUB_DX8BDLR5)
#define DDR0_PUB_DX8BDLR6 (0x1000 + (0x1AD << 2)) 	///../ucode/ddr3_reg.h:462
#define P_DDR0_PUB_DX8BDLR6 		MMC_REG_ADDR(DDR0_PUB_DX8BDLR6)
#define DDR0_PUB_DX8LCDLR0 (0x1000 + (0x1AE << 2)) 	///../ucode/ddr3_reg.h:463
#define P_DDR0_PUB_DX8LCDLR0 		MMC_REG_ADDR(DDR0_PUB_DX8LCDLR0)
#define DDR0_PUB_DX8LCDLR1 (0x1000 + (0x1AF << 2)) 	///../ucode/ddr3_reg.h:464
#define P_DDR0_PUB_DX8LCDLR1 		MMC_REG_ADDR(DDR0_PUB_DX8LCDLR1)
#define DDR0_PUB_DX8LCDLR2 (0x1000 + (0x1B0 << 2)) 	///../ucode/ddr3_reg.h:465
#define P_DDR0_PUB_DX8LCDLR2 		MMC_REG_ADDR(DDR0_PUB_DX8LCDLR2)
#define DDR0_PUB_DX8MDLR (0x1000 + (0x1B1 << 2)) 	///../ucode/ddr3_reg.h:466
#define P_DDR0_PUB_DX8MDLR 		MMC_REG_ADDR(DDR0_PUB_DX8MDLR)
#define DDR0_PUB_DX8GTR (0x1000 + (0x1B2 << 2)) 	///../ucode/ddr3_reg.h:467
#define P_DDR0_PUB_DX8GTR 		MMC_REG_ADDR(DDR0_PUB_DX8GTR)
#define DDR1_CLK_CTRL 0x2800 	///../ucode/ddr3_reg.h:471
#define P_DDR1_CLK_CTRL 		MMC_REG_ADDR(DDR1_CLK_CTRL)
#define DDR1_SOFT_RESET 0x2804 	///../ucode/ddr3_reg.h:472
#define P_DDR1_SOFT_RESET 		MMC_REG_ADDR(DDR1_SOFT_RESET)
#define DDR1_APD_CTRL 0x2808 	///../ucode/ddr3_reg.h:473
#define P_DDR1_APD_CTRL 		MMC_REG_ADDR(DDR1_APD_CTRL)
#define DDR1_PCTL_SCFG 0x2000 	///../ucode/ddr3_reg.h:475
#define P_DDR1_PCTL_SCFG 		MMC_REG_ADDR(DDR1_PCTL_SCFG)
#define DDR1_PCTL_SCTL 0x2004 	///../ucode/ddr3_reg.h:476
#define P_DDR1_PCTL_SCTL 		MMC_REG_ADDR(DDR1_PCTL_SCTL)
#define DDR1_PCTL_STAT 0x2008 	///../ucode/ddr3_reg.h:477
#define P_DDR1_PCTL_STAT 		MMC_REG_ADDR(DDR1_PCTL_STAT)
#define DDR1_PCTL_INTRSTAT 0x200c 	///../ucode/ddr3_reg.h:478
#define P_DDR1_PCTL_INTRSTAT 		MMC_REG_ADDR(DDR1_PCTL_INTRSTAT)
#define DDR1_PCTL_POWSTAT 0x2048 	///../ucode/ddr3_reg.h:479
#define P_DDR1_PCTL_POWSTAT 		MMC_REG_ADDR(DDR1_PCTL_POWSTAT)
#define DDR1_PCTL_MRRSTAT0 0x2064 	///../ucode/ddr3_reg.h:480
#define P_DDR1_PCTL_MRRSTAT0 		MMC_REG_ADDR(DDR1_PCTL_MRRSTAT0)
#define DDR1_PCTL_CMDTSTAT 0x204c 	///../ucode/ddr3_reg.h:481
#define P_DDR1_PCTL_CMDTSTAT 		MMC_REG_ADDR(DDR1_PCTL_CMDTSTAT)
#define DDR1_PCTL_MCMD 0x2040 	///../ucode/ddr3_reg.h:482
#define P_DDR1_PCTL_MCMD 		MMC_REG_ADDR(DDR1_PCTL_MCMD)
#define DDR1_PCTL_MRRSTAT1 0x2068 	///../ucode/ddr3_reg.h:483
#define P_DDR1_PCTL_MRRSTAT1 		MMC_REG_ADDR(DDR1_PCTL_MRRSTAT1)
#define DDR1_PCTL_MRRCFG0 0x2060 	///../ucode/ddr3_reg.h:484
#define P_DDR1_PCTL_MRRCFG0 		MMC_REG_ADDR(DDR1_PCTL_MRRCFG0)
#define DDR1_PCTL_CMDTSTATEN 0x2050 	///../ucode/ddr3_reg.h:485
#define P_DDR1_PCTL_CMDTSTATEN 		MMC_REG_ADDR(DDR1_PCTL_CMDTSTATEN)
#define DDR1_PCTL_POWCTL 0x2044 	///../ucode/ddr3_reg.h:486
#define P_DDR1_PCTL_POWCTL 		MMC_REG_ADDR(DDR1_PCTL_POWCTL)
#define DDR1_PCTL_PPCFG 0x2084 	///../ucode/ddr3_reg.h:487
#define P_DDR1_PCTL_PPCFG 		MMC_REG_ADDR(DDR1_PCTL_PPCFG)
#define DDR1_PCTL_LPDDR23ZQCFG 0x208c 	///../ucode/ddr3_reg.h:488
#define P_DDR1_PCTL_LPDDR23ZQCFG 		MMC_REG_ADDR(DDR1_PCTL_LPDDR23ZQCFG)
#define DDR1_PCTL_MCFG1 0x207c 	///../ucode/ddr3_reg.h:489
#define P_DDR1_PCTL_MCFG1 		MMC_REG_ADDR(DDR1_PCTL_MCFG1)
#define DDR1_PCTL_MSTAT 0x2088 	///../ucode/ddr3_reg.h:490
#define P_DDR1_PCTL_MSTAT 		MMC_REG_ADDR(DDR1_PCTL_MSTAT)
#define DDR1_PCTL_MCFG 0x2080 	///../ucode/ddr3_reg.h:491
#define P_DDR1_PCTL_MCFG 		MMC_REG_ADDR(DDR1_PCTL_MCFG)
#define DDR1_PCTL_DTUAWDT 0x20b0 	///../ucode/ddr3_reg.h:492
#define P_DDR1_PCTL_DTUAWDT 		MMC_REG_ADDR(DDR1_PCTL_DTUAWDT)
#define DDR1_PCTL_DTUPRD2 0x20a8 	///../ucode/ddr3_reg.h:493
#define P_DDR1_PCTL_DTUPRD2 		MMC_REG_ADDR(DDR1_PCTL_DTUPRD2)
#define DDR1_PCTL_DTUPRD3 0x20ac 	///../ucode/ddr3_reg.h:494
#define P_DDR1_PCTL_DTUPRD3 		MMC_REG_ADDR(DDR1_PCTL_DTUPRD3)
#define DDR1_PCTL_DTUNE 0x209c 	///../ucode/ddr3_reg.h:495
#define P_DDR1_PCTL_DTUNE 		MMC_REG_ADDR(DDR1_PCTL_DTUNE)
#define DDR1_PCTL_DTUPDES 0x2094 	///../ucode/ddr3_reg.h:496
#define P_DDR1_PCTL_DTUPDES 		MMC_REG_ADDR(DDR1_PCTL_DTUPDES)
#define DDR1_PCTL_DTUNA 0x2098 	///../ucode/ddr3_reg.h:497
#define P_DDR1_PCTL_DTUNA 		MMC_REG_ADDR(DDR1_PCTL_DTUNA)
#define DDR1_PCTL_DTUPRD0 0x20a0 	///../ucode/ddr3_reg.h:498
#define P_DDR1_PCTL_DTUPRD0 		MMC_REG_ADDR(DDR1_PCTL_DTUPRD0)
#define DDR1_PCTL_DTUPRD1 0x20a4 	///../ucode/ddr3_reg.h:499
#define P_DDR1_PCTL_DTUPRD1 		MMC_REG_ADDR(DDR1_PCTL_DTUPRD1)
#define DDR1_PCTL_TCKSRE 0x2124 	///../ucode/ddr3_reg.h:500
#define P_DDR1_PCTL_TCKSRE 		MMC_REG_ADDR(DDR1_PCTL_TCKSRE)
#define DDR1_PCTL_TZQCSI 0x211c 	///../ucode/ddr3_reg.h:501
#define P_DDR1_PCTL_TZQCSI 		MMC_REG_ADDR(DDR1_PCTL_TZQCSI)
#define DDR1_PCTL_TINIT 0x20c4 	///../ucode/ddr3_reg.h:502
#define P_DDR1_PCTL_TINIT 		MMC_REG_ADDR(DDR1_PCTL_TINIT)
#define DDR1_PCTL_TDPD 0x2144 	///../ucode/ddr3_reg.h:503
#define P_DDR1_PCTL_TDPD 		MMC_REG_ADDR(DDR1_PCTL_TDPD)
#define DDR1_PCTL_TOGCNT1U 0x20c0 	///../ucode/ddr3_reg.h:504
#define P_DDR1_PCTL_TOGCNT1U 		MMC_REG_ADDR(DDR1_PCTL_TOGCNT1U)
#define DDR1_PCTL_TCKE 0x212c 	///../ucode/ddr3_reg.h:505
#define P_DDR1_PCTL_TCKE 		MMC_REG_ADDR(DDR1_PCTL_TCKE)
#define DDR1_PCTL_TMOD 0x2130 	///../ucode/ddr3_reg.h:506
#define P_DDR1_PCTL_TMOD 		MMC_REG_ADDR(DDR1_PCTL_TMOD)
#define DDR1_PCTL_TEXSR 0x210c 	///../ucode/ddr3_reg.h:507
#define P_DDR1_PCTL_TEXSR 		MMC_REG_ADDR(DDR1_PCTL_TEXSR)
#define DDR1_PCTL_TAL 0x20e4 	///../ucode/ddr3_reg.h:508
#define P_DDR1_PCTL_TAL 		MMC_REG_ADDR(DDR1_PCTL_TAL)
#define DDR1_PCTL_TRTP 0x2100 	///../ucode/ddr3_reg.h:509
#define P_DDR1_PCTL_TRTP 		MMC_REG_ADDR(DDR1_PCTL_TRTP)
#define DDR1_PCTL_TCKSRX 0x2128 	///../ucode/ddr3_reg.h:510
#define P_DDR1_PCTL_TCKSRX 		MMC_REG_ADDR(DDR1_PCTL_TCKSRX)
#define DDR1_PCTL_TRTW 0x20e0 	///../ucode/ddr3_reg.h:511
#define P_DDR1_PCTL_TRTW 		MMC_REG_ADDR(DDR1_PCTL_TRTW)
#define DDR1_PCTL_TCWL 0x20ec 	///../ucode/ddr3_reg.h:512
#define P_DDR1_PCTL_TCWL 		MMC_REG_ADDR(DDR1_PCTL_TCWL)
#define DDR1_PCTL_TWR 0x2104 	///../ucode/ddr3_reg.h:513
#define P_DDR1_PCTL_TWR 		MMC_REG_ADDR(DDR1_PCTL_TWR)
#define DDR1_PCTL_TCL 0x20e8 	///../ucode/ddr3_reg.h:514
#define P_DDR1_PCTL_TCL 		MMC_REG_ADDR(DDR1_PCTL_TCL)
#define DDR1_PCTL_TDQS 0x2120 	///../ucode/ddr3_reg.h:515
#define P_DDR1_PCTL_TDQS 		MMC_REG_ADDR(DDR1_PCTL_TDQS)
#define DDR1_PCTL_TRSTH 0x20c8 	///../ucode/ddr3_reg.h:516
#define P_DDR1_PCTL_TRSTH 		MMC_REG_ADDR(DDR1_PCTL_TRSTH)
#define DDR1_PCTL_TRCD 0x20f8 	///../ucode/ddr3_reg.h:517
#define P_DDR1_PCTL_TRCD 		MMC_REG_ADDR(DDR1_PCTL_TRCD)
#define DDR1_PCTL_TXP 0x2110 	///../ucode/ddr3_reg.h:518
#define P_DDR1_PCTL_TXP 		MMC_REG_ADDR(DDR1_PCTL_TXP)
#define DDR1_PCTL_TOGCNT100N 0x20cc 	///../ucode/ddr3_reg.h:519
#define P_DDR1_PCTL_TOGCNT100N 		MMC_REG_ADDR(DDR1_PCTL_TOGCNT100N)
#define DDR1_PCTL_TMRD 0x20d4 	///../ucode/ddr3_reg.h:520
#define P_DDR1_PCTL_TMRD 		MMC_REG_ADDR(DDR1_PCTL_TMRD)
#define DDR1_PCTL_TRSTL 0x2134 	///../ucode/ddr3_reg.h:521
#define P_DDR1_PCTL_TRSTL 		MMC_REG_ADDR(DDR1_PCTL_TRSTL)
#define DDR1_PCTL_TREFI 0x20d0 	///../ucode/ddr3_reg.h:522
#define P_DDR1_PCTL_TREFI 		MMC_REG_ADDR(DDR1_PCTL_TREFI)
#define DDR1_PCTL_TRAS 0x20f0 	///../ucode/ddr3_reg.h:523
#define P_DDR1_PCTL_TRAS 		MMC_REG_ADDR(DDR1_PCTL_TRAS)
#define DDR1_PCTL_TREFI_MEM_DDR3 0x2148 	///../ucode/ddr3_reg.h:524
#define P_DDR1_PCTL_TREFI_MEM_DDR3 		MMC_REG_ADDR(DDR1_PCTL_TREFI_MEM_DDR3)
#define DDR1_PCTL_TWTR 0x2108 	///../ucode/ddr3_reg.h:525
#define P_DDR1_PCTL_TWTR 		MMC_REG_ADDR(DDR1_PCTL_TWTR)
#define DDR1_PCTL_TRC 0x20f4 	///../ucode/ddr3_reg.h:526
#define P_DDR1_PCTL_TRC 		MMC_REG_ADDR(DDR1_PCTL_TRC)
#define DDR1_PCTL_TRFC 0x20d8 	///../ucode/ddr3_reg.h:527
#define P_DDR1_PCTL_TRFC 		MMC_REG_ADDR(DDR1_PCTL_TRFC)
#define DDR1_PCTL_TMRR 0x213c 	///../ucode/ddr3_reg.h:528
#define P_DDR1_PCTL_TMRR 		MMC_REG_ADDR(DDR1_PCTL_TMRR)
#define DDR1_PCTL_TCKESR 0x2140 	///../ucode/ddr3_reg.h:529
#define P_DDR1_PCTL_TCKESR 		MMC_REG_ADDR(DDR1_PCTL_TCKESR)
#define DDR1_PCTL_TZQCL 0x2138 	///../ucode/ddr3_reg.h:530
#define P_DDR1_PCTL_TZQCL 		MMC_REG_ADDR(DDR1_PCTL_TZQCL)
#define DDR1_PCTL_TRRD 0x20fc 	///../ucode/ddr3_reg.h:531
#define P_DDR1_PCTL_TRRD 		MMC_REG_ADDR(DDR1_PCTL_TRRD)
#define DDR1_PCTL_TRP 0x20dc 	///../ucode/ddr3_reg.h:532
#define P_DDR1_PCTL_TRP 		MMC_REG_ADDR(DDR1_PCTL_TRP)
#define DDR1_PCTL_TZQCS 0x2118 	///../ucode/ddr3_reg.h:533
#define P_DDR1_PCTL_TZQCS 		MMC_REG_ADDR(DDR1_PCTL_TZQCS)
#define DDR1_PCTL_TXPDLL 0x2114 	///../ucode/ddr3_reg.h:534
#define P_DDR1_PCTL_TXPDLL 		MMC_REG_ADDR(DDR1_PCTL_TXPDLL)
#define DDR1_PCTL_ECCCFG 0x2180 	///../ucode/ddr3_reg.h:535
#define P_DDR1_PCTL_ECCCFG 		MMC_REG_ADDR(DDR1_PCTL_ECCCFG)
#define DDR1_PCTL_ECCLOG 0x218c 	///../ucode/ddr3_reg.h:536
#define P_DDR1_PCTL_ECCLOG 		MMC_REG_ADDR(DDR1_PCTL_ECCLOG)
#define DDR1_PCTL_ECCCLR 0x2188 	///../ucode/ddr3_reg.h:537
#define P_DDR1_PCTL_ECCCLR 		MMC_REG_ADDR(DDR1_PCTL_ECCCLR)
#define DDR1_PCTL_ECCTST 0x2184 	///../ucode/ddr3_reg.h:538
#define P_DDR1_PCTL_ECCTST 		MMC_REG_ADDR(DDR1_PCTL_ECCTST)
#define DDR1_PCTL_DTUWD0 0x2210 	///../ucode/ddr3_reg.h:539
#define P_DDR1_PCTL_DTUWD0 		MMC_REG_ADDR(DDR1_PCTL_DTUWD0)
#define DDR1_PCTL_DTUWD1 0x2214 	///../ucode/ddr3_reg.h:540
#define P_DDR1_PCTL_DTUWD1 		MMC_REG_ADDR(DDR1_PCTL_DTUWD1)
#define DDR1_PCTL_DTUWACTL 0x2200 	///../ucode/ddr3_reg.h:541
#define P_DDR1_PCTL_DTUWACTL 		MMC_REG_ADDR(DDR1_PCTL_DTUWACTL)
#define DDR1_PCTL_DTULFSRRD 0x2238 	///../ucode/ddr3_reg.h:542
#define P_DDR1_PCTL_DTULFSRRD 		MMC_REG_ADDR(DDR1_PCTL_DTULFSRRD)
#define DDR1_PCTL_DTUWD2 0x2218 	///../ucode/ddr3_reg.h:543
#define P_DDR1_PCTL_DTUWD2 		MMC_REG_ADDR(DDR1_PCTL_DTUWD2)
#define DDR1_PCTL_DTUWD3 0x221c 	///../ucode/ddr3_reg.h:544
#define P_DDR1_PCTL_DTUWD3 		MMC_REG_ADDR(DDR1_PCTL_DTUWD3)
#define DDR1_PCTL_DTULFSRWD 0x2234 	///../ucode/ddr3_reg.h:545
#define P_DDR1_PCTL_DTULFSRWD 		MMC_REG_ADDR(DDR1_PCTL_DTULFSRWD)
#define DDR1_PCTL_DTURACTL 0x2204 	///../ucode/ddr3_reg.h:546
#define P_DDR1_PCTL_DTURACTL 		MMC_REG_ADDR(DDR1_PCTL_DTURACTL)
#define DDR1_PCTL_DTUWDM 0x2220 	///../ucode/ddr3_reg.h:547
#define P_DDR1_PCTL_DTUWDM 		MMC_REG_ADDR(DDR1_PCTL_DTUWDM)
#define DDR1_PCTL_DTURD0 0x2224 	///../ucode/ddr3_reg.h:548
#define P_DDR1_PCTL_DTURD0 		MMC_REG_ADDR(DDR1_PCTL_DTURD0)
#define DDR1_PCTL_DTURD1 0x2228 	///../ucode/ddr3_reg.h:549
#define P_DDR1_PCTL_DTURD1 		MMC_REG_ADDR(DDR1_PCTL_DTURD1)
#define DDR1_PCTL_DTURD2 0x222c 	///../ucode/ddr3_reg.h:550
#define P_DDR1_PCTL_DTURD2 		MMC_REG_ADDR(DDR1_PCTL_DTURD2)
#define DDR1_PCTL_DTURD3 0x2230 	///../ucode/ddr3_reg.h:551
#define P_DDR1_PCTL_DTURD3 		MMC_REG_ADDR(DDR1_PCTL_DTURD3)
#define DDR1_PCTL_DTUCFG 0x2208 	///../ucode/ddr3_reg.h:552
#define P_DDR1_PCTL_DTUCFG 		MMC_REG_ADDR(DDR1_PCTL_DTUCFG)
#define DDR1_PCTL_DTUEAF 0x223c 	///../ucode/ddr3_reg.h:553
#define P_DDR1_PCTL_DTUEAF 		MMC_REG_ADDR(DDR1_PCTL_DTUEAF)
#define DDR1_PCTL_DTUECTL 0x220c 	///../ucode/ddr3_reg.h:554
#define P_DDR1_PCTL_DTUECTL 		MMC_REG_ADDR(DDR1_PCTL_DTUECTL)
#define DDR1_PCTL_DFIODTCFG1 0x2248 	///../ucode/ddr3_reg.h:555
#define P_DDR1_PCTL_DFIODTCFG1 		MMC_REG_ADDR(DDR1_PCTL_DFIODTCFG1)
#define DDR1_PCTL_DFITCTRLDELAY 0x2240 	///../ucode/ddr3_reg.h:556
#define P_DDR1_PCTL_DFITCTRLDELAY 		MMC_REG_ADDR(DDR1_PCTL_DFITCTRLDELAY)
#define DDR1_PCTL_DFIODTRANKMAP 0x224c 	///../ucode/ddr3_reg.h:557
#define P_DDR1_PCTL_DFIODTRANKMAP 		MMC_REG_ADDR(DDR1_PCTL_DFIODTRANKMAP)
#define DDR1_PCTL_DFIODTCFG 0x2244 	///../ucode/ddr3_reg.h:558
#define P_DDR1_PCTL_DFIODTCFG 		MMC_REG_ADDR(DDR1_PCTL_DFIODTCFG)
#define DDR1_PCTL_DFITPHYWRLAT 0x2254 	///../ucode/ddr3_reg.h:559
#define P_DDR1_PCTL_DFITPHYWRLAT 		MMC_REG_ADDR(DDR1_PCTL_DFITPHYWRLAT)
#define DDR1_PCTL_DFITPHYWRDATA 0x2250 	///../ucode/ddr3_reg.h:560
#define P_DDR1_PCTL_DFITPHYWRDATA 		MMC_REG_ADDR(DDR1_PCTL_DFITPHYWRDATA)
#define DDR1_PCTL_DFITRDDATAEN 0x2260 	///../ucode/ddr3_reg.h:561
#define P_DDR1_PCTL_DFITRDDATAEN 		MMC_REG_ADDR(DDR1_PCTL_DFITRDDATAEN)
#define DDR1_PCTL_DFITPHYRDLAT 0x2264 	///../ucode/ddr3_reg.h:562
#define P_DDR1_PCTL_DFITPHYRDLAT 		MMC_REG_ADDR(DDR1_PCTL_DFITPHYRDLAT)
#define DDR1_PCTL_DFITREFMSKI 0x2294 	///../ucode/ddr3_reg.h:563
#define P_DDR1_PCTL_DFITREFMSKI 		MMC_REG_ADDR(DDR1_PCTL_DFITREFMSKI)
#define DDR1_PCTL_DFITPHYUPDTYPE0 0x2270 	///../ucode/ddr3_reg.h:564
#define P_DDR1_PCTL_DFITPHYUPDTYPE0 		MMC_REG_ADDR(DDR1_PCTL_DFITPHYUPDTYPE0)
#define DDR1_PCTL_DFITPHYUPDTYPE1 0x2274 	///../ucode/ddr3_reg.h:565
#define P_DDR1_PCTL_DFITPHYUPDTYPE1 		MMC_REG_ADDR(DDR1_PCTL_DFITPHYUPDTYPE1)
#define DDR1_PCTL_DFITCTRLUPDDLY 0x2288 	///../ucode/ddr3_reg.h:566
#define P_DDR1_PCTL_DFITCTRLUPDDLY 		MMC_REG_ADDR(DDR1_PCTL_DFITCTRLUPDDLY)
#define DDR1_PCTL_DFITPHYUPDTYPE2 0x2278 	///../ucode/ddr3_reg.h:567
#define P_DDR1_PCTL_DFITPHYUPDTYPE2 		MMC_REG_ADDR(DDR1_PCTL_DFITPHYUPDTYPE2)
#define DDR1_PCTL_DFITCTRLUPDMIN 0x2280 	///../ucode/ddr3_reg.h:568
#define P_DDR1_PCTL_DFITCTRLUPDMIN 		MMC_REG_ADDR(DDR1_PCTL_DFITCTRLUPDMIN)
#define DDR1_PCTL_DFITPHYUPDTYPE3 0x227c 	///../ucode/ddr3_reg.h:569
#define P_DDR1_PCTL_DFITPHYUPDTYPE3 		MMC_REG_ADDR(DDR1_PCTL_DFITPHYUPDTYPE3)
#define DDR1_PCTL_DFIUPDCFG 0x2290 	///../ucode/ddr3_reg.h:570
#define P_DDR1_PCTL_DFIUPDCFG 		MMC_REG_ADDR(DDR1_PCTL_DFIUPDCFG)
#define DDR1_PCTL_DFITCTRLUPDMAX 0x2284 	///../ucode/ddr3_reg.h:571
#define P_DDR1_PCTL_DFITCTRLUPDMAX 		MMC_REG_ADDR(DDR1_PCTL_DFITCTRLUPDMAX)
#define DDR1_PCTL_DFITCTRLUPDI 0x2298 	///../ucode/ddr3_reg.h:572
#define P_DDR1_PCTL_DFITCTRLUPDI 		MMC_REG_ADDR(DDR1_PCTL_DFITCTRLUPDI)
#define DDR1_PCTL_DFITRRDLVLEN 0x22b8 	///../ucode/ddr3_reg.h:573
#define P_DDR1_PCTL_DFITRRDLVLEN 		MMC_REG_ADDR(DDR1_PCTL_DFITRRDLVLEN)
#define DDR1_PCTL_DFITRSTAT0 0x22b0 	///../ucode/ddr3_reg.h:574
#define P_DDR1_PCTL_DFITRSTAT0 		MMC_REG_ADDR(DDR1_PCTL_DFITRSTAT0)
#define DDR1_PCTL_DFITRWRLVLEN 0x22b4 	///../ucode/ddr3_reg.h:575
#define P_DDR1_PCTL_DFITRWRLVLEN 		MMC_REG_ADDR(DDR1_PCTL_DFITRWRLVLEN)
#define DDR1_PCTL_DFITRCFG0 0x22ac 	///../ucode/ddr3_reg.h:576
#define P_DDR1_PCTL_DFITRCFG0 		MMC_REG_ADDR(DDR1_PCTL_DFITRCFG0)
#define DDR1_PCTL_DFITRRDLVLGATEEN 0x22bc 	///../ucode/ddr3_reg.h:577
#define P_DDR1_PCTL_DFITRRDLVLGATEEN 		MMC_REG_ADDR(DDR1_PCTL_DFITRRDLVLGATEEN)
#define DDR1_PCTL_DFISTSTAT0 0x22c0 	///../ucode/ddr3_reg.h:578
#define P_DDR1_PCTL_DFISTSTAT0 		MMC_REG_ADDR(DDR1_PCTL_DFISTSTAT0)
#define DDR1_PCTL_DFISTPARLOG 0x22e0 	///../ucode/ddr3_reg.h:579
#define P_DDR1_PCTL_DFISTPARLOG 		MMC_REG_ADDR(DDR1_PCTL_DFISTPARLOG)
#define DDR1_PCTL_DFITDRAMCLKEN 0x22d0 	///../ucode/ddr3_reg.h:580
#define P_DDR1_PCTL_DFITDRAMCLKEN 		MMC_REG_ADDR(DDR1_PCTL_DFITDRAMCLKEN)
#define DDR1_PCTL_DFISTPARCLR 0x22dc 	///../ucode/ddr3_reg.h:581
#define P_DDR1_PCTL_DFISTPARCLR 		MMC_REG_ADDR(DDR1_PCTL_DFISTPARCLR)
#define DDR1_PCTL_DFISTCFG0 0x22c4 	///../ucode/ddr3_reg.h:582
#define P_DDR1_PCTL_DFISTCFG0 		MMC_REG_ADDR(DDR1_PCTL_DFISTCFG0)
#define DDR1_PCTL_DFISTCFG1 0x22c8 	///../ucode/ddr3_reg.h:583
#define P_DDR1_PCTL_DFISTCFG1 		MMC_REG_ADDR(DDR1_PCTL_DFISTCFG1)
#define DDR1_PCTL_DFISTCFG2 0x22d8 	///../ucode/ddr3_reg.h:584
#define P_DDR1_PCTL_DFISTCFG2 		MMC_REG_ADDR(DDR1_PCTL_DFISTCFG2)
#define DDR1_PCTL_DFITDRAMCLKDIS 0x22d4 	///../ucode/ddr3_reg.h:585
#define P_DDR1_PCTL_DFITDRAMCLKDIS 		MMC_REG_ADDR(DDR1_PCTL_DFITDRAMCLKDIS)
#define DDR1_PCTL_DFILPCFG0 0x22f0 	///../ucode/ddr3_reg.h:586
#define P_DDR1_PCTL_DFILPCFG0 		MMC_REG_ADDR(DDR1_PCTL_DFILPCFG0)
#define DDR1_PCTL_DFITRWRLVLDELAY0 0x2318 	///../ucode/ddr3_reg.h:587
#define P_DDR1_PCTL_DFITRWRLVLDELAY0 		MMC_REG_ADDR(DDR1_PCTL_DFITRWRLVLDELAY0)
#define DDR1_PCTL_DFITRWRLVLDELAY1 0x231c 	///../ucode/ddr3_reg.h:588
#define P_DDR1_PCTL_DFITRWRLVLDELAY1 		MMC_REG_ADDR(DDR1_PCTL_DFITRWRLVLDELAY1)
#define DDR1_PCTL_DFITRWRLVLDELAY2 0x2320 	///../ucode/ddr3_reg.h:589
#define P_DDR1_PCTL_DFITRWRLVLDELAY2 		MMC_REG_ADDR(DDR1_PCTL_DFITRWRLVLDELAY2)
#define DDR1_PCTL_DFITRRDLVLRESP0 0x230c 	///../ucode/ddr3_reg.h:590
#define P_DDR1_PCTL_DFITRRDLVLRESP0 		MMC_REG_ADDR(DDR1_PCTL_DFITRRDLVLRESP0)
#define DDR1_PCTL_DFITRRDLVLRESP1 0x2310 	///../ucode/ddr3_reg.h:591
#define P_DDR1_PCTL_DFITRRDLVLRESP1 		MMC_REG_ADDR(DDR1_PCTL_DFITRRDLVLRESP1)
#define DDR1_PCTL_DFITRRDLVLRESP2 0x2314 	///../ucode/ddr3_reg.h:592
#define P_DDR1_PCTL_DFITRRDLVLRESP2 		MMC_REG_ADDR(DDR1_PCTL_DFITRRDLVLRESP2)
#define DDR1_PCTL_DFITRWRLVLRESP0 0x2300 	///../ucode/ddr3_reg.h:593
#define P_DDR1_PCTL_DFITRWRLVLRESP0 		MMC_REG_ADDR(DDR1_PCTL_DFITRWRLVLRESP0)
#define DDR1_PCTL_DFITRRDLVLDELAY0 0x2324 	///../ucode/ddr3_reg.h:594
#define P_DDR1_PCTL_DFITRRDLVLDELAY0 		MMC_REG_ADDR(DDR1_PCTL_DFITRRDLVLDELAY0)
#define DDR1_PCTL_DFITRRDLVLDELAY1 0x2328 	///../ucode/ddr3_reg.h:595
#define P_DDR1_PCTL_DFITRRDLVLDELAY1 		MMC_REG_ADDR(DDR1_PCTL_DFITRRDLVLDELAY1)
#define DDR1_PCTL_DFITRWRLVLRESP1 0x2304 	///../ucode/ddr3_reg.h:596
#define P_DDR1_PCTL_DFITRWRLVLRESP1 		MMC_REG_ADDR(DDR1_PCTL_DFITRWRLVLRESP1)
#define DDR1_PCTL_DFITRRDLVLDELAY2 0x232c 	///../ucode/ddr3_reg.h:597
#define P_DDR1_PCTL_DFITRRDLVLDELAY2 		MMC_REG_ADDR(DDR1_PCTL_DFITRRDLVLDELAY2)
#define DDR1_PCTL_DFITRWRLVLRESP2 0x2308 	///../ucode/ddr3_reg.h:598
#define P_DDR1_PCTL_DFITRWRLVLRESP2 		MMC_REG_ADDR(DDR1_PCTL_DFITRWRLVLRESP2)
#define DDR1_PCTL_DFITRRDLVLGATEDELAY0 0x2330 	///../ucode/ddr3_reg.h:599
#define P_DDR1_PCTL_DFITRRDLVLGATEDELAY0 		MMC_REG_ADDR(DDR1_PCTL_DFITRRDLVLGATEDELAY0)
#define DDR1_PCTL_DFITRCMD 0x233c 	///../ucode/ddr3_reg.h:600
#define P_DDR1_PCTL_DFITRCMD 		MMC_REG_ADDR(DDR1_PCTL_DFITRCMD)
#define DDR1_PCTL_DFITRRDLVLGATEDELAY1 0x2334 	///../ucode/ddr3_reg.h:601
#define P_DDR1_PCTL_DFITRRDLVLGATEDELAY1 		MMC_REG_ADDR(DDR1_PCTL_DFITRRDLVLGATEDELAY1)
#define DDR1_PCTL_DFITRRDLVLGATEDELAY2 0x2338 	///../ucode/ddr3_reg.h:602
#define P_DDR1_PCTL_DFITRRDLVLGATEDELAY2 		MMC_REG_ADDR(DDR1_PCTL_DFITRRDLVLGATEDELAY2)
#define DDR1_PCTL_IPTR 0x23fc 	///../ucode/ddr3_reg.h:603
#define P_DDR1_PCTL_IPTR 		MMC_REG_ADDR(DDR1_PCTL_IPTR)
#define DDR1_PCTL_IPVR 0x23f8 	///../ucode/ddr3_reg.h:604
#define P_DDR1_PCTL_IPVR 		MMC_REG_ADDR(DDR1_PCTL_IPVR)
#define DDR1_PUB_RIDR (0x3000 + (0x00 << 2)) 	///../ucode/ddr3_reg.h:607
#define P_DDR1_PUB_RIDR 		MMC_REG_ADDR(DDR1_PUB_RIDR)
#define DDR1_PUB_PIR (0x3000 + (0x01 << 2)) 	///../ucode/ddr3_reg.h:608
#define P_DDR1_PUB_PIR 		MMC_REG_ADDR(DDR1_PUB_PIR)
#define DDR1_PUB_PGCR0 (0x3000 + (0x02 << 2)) 	///../ucode/ddr3_reg.h:609
#define P_DDR1_PUB_PGCR0 		MMC_REG_ADDR(DDR1_PUB_PGCR0)
#define DDR1_PUB_PGCR1 (0x3000 + (0x03 << 2)) 	///../ucode/ddr3_reg.h:610
#define P_DDR1_PUB_PGCR1 		MMC_REG_ADDR(DDR1_PUB_PGCR1)
#define DDR1_PUB_PGCR2 (0x3000 + (0x04 << 2)) 	///../ucode/ddr3_reg.h:611
#define P_DDR1_PUB_PGCR2 		MMC_REG_ADDR(DDR1_PUB_PGCR2)
#define DDR1_PUB_PGCR3 (0x3000 + (0x05 << 2)) 	///../ucode/ddr3_reg.h:612
#define P_DDR1_PUB_PGCR3 		MMC_REG_ADDR(DDR1_PUB_PGCR3)
#define DDR1_PUB_PGSR0 (0x3000 + (0x06 << 2)) 	///../ucode/ddr3_reg.h:613
#define P_DDR1_PUB_PGSR0 		MMC_REG_ADDR(DDR1_PUB_PGSR0)
#define DDR1_PUB_PGSR1 (0x3000 + (0x07 << 2)) 	///../ucode/ddr3_reg.h:614
#define P_DDR1_PUB_PGSR1 		MMC_REG_ADDR(DDR1_PUB_PGSR1)
#define DDR1_PUB_PLLCR (0x3000 + (0x08 << 2)) 	///../ucode/ddr3_reg.h:615
#define P_DDR1_PUB_PLLCR 		MMC_REG_ADDR(DDR1_PUB_PLLCR)
#define DDR1_PUB_PTR0 (0x3000 + (0x09 << 2)) 	///../ucode/ddr3_reg.h:616
#define P_DDR1_PUB_PTR0 		MMC_REG_ADDR(DDR1_PUB_PTR0)
#define DDR1_PUB_PTR1 (0x3000 + (0x0A << 2)) 	///../ucode/ddr3_reg.h:617
#define P_DDR1_PUB_PTR1 		MMC_REG_ADDR(DDR1_PUB_PTR1)
#define DDR1_PUB_PTR2 (0x3000 + (0x0B << 2)) 	///../ucode/ddr3_reg.h:618
#define P_DDR1_PUB_PTR2 		MMC_REG_ADDR(DDR1_PUB_PTR2)
#define DDR1_PUB_PTR3 (0x3000 + (0x0C << 2)) 	///../ucode/ddr3_reg.h:619
#define P_DDR1_PUB_PTR3 		MMC_REG_ADDR(DDR1_PUB_PTR3)
#define DDR1_PUB_PTR4 (0x3000 + (0x0D << 2)) 	///../ucode/ddr3_reg.h:620
#define P_DDR1_PUB_PTR4 		MMC_REG_ADDR(DDR1_PUB_PTR4)
#define DDR1_PUB_ACMDLR (0x3000 + (0x0E << 2)) 	///../ucode/ddr3_reg.h:621
#define P_DDR1_PUB_ACMDLR 		MMC_REG_ADDR(DDR1_PUB_ACMDLR)
#define DDR1_PUB_ACLCDLR (0x3000 + (0x0F << 2)) 	///../ucode/ddr3_reg.h:622
#define P_DDR1_PUB_ACLCDLR 		MMC_REG_ADDR(DDR1_PUB_ACLCDLR)
#define DDR1_PUB_ACBDLR0 (0x3000 + (0x10 << 2)) 	///../ucode/ddr3_reg.h:623
#define P_DDR1_PUB_ACBDLR0 		MMC_REG_ADDR(DDR1_PUB_ACBDLR0)
#define DDR1_PUB_ACBDLR1 (0x3000 + (0x11 << 2)) 	///../ucode/ddr3_reg.h:624
#define P_DDR1_PUB_ACBDLR1 		MMC_REG_ADDR(DDR1_PUB_ACBDLR1)
#define DDR1_PUB_ACBDLR2 (0x3000 + (0x12 << 2)) 	///../ucode/ddr3_reg.h:625
#define P_DDR1_PUB_ACBDLR2 		MMC_REG_ADDR(DDR1_PUB_ACBDLR2)
#define DDR1_PUB_ACBDLR3 (0x3000 + (0x13 << 2)) 	///../ucode/ddr3_reg.h:626
#define P_DDR1_PUB_ACBDLR3 		MMC_REG_ADDR(DDR1_PUB_ACBDLR3)
#define DDR1_PUB_ACBDLR4 (0x3000 + (0x14 << 2)) 	///../ucode/ddr3_reg.h:627
#define P_DDR1_PUB_ACBDLR4 		MMC_REG_ADDR(DDR1_PUB_ACBDLR4)
#define DDR1_PUB_ACBDLR5 (0x3000 + (0x15 << 2)) 	///../ucode/ddr3_reg.h:628
#define P_DDR1_PUB_ACBDLR5 		MMC_REG_ADDR(DDR1_PUB_ACBDLR5)
#define DDR1_PUB_ACBDLR6 (0x3000 + (0x16 << 2)) 	///../ucode/ddr3_reg.h:629
#define P_DDR1_PUB_ACBDLR6 		MMC_REG_ADDR(DDR1_PUB_ACBDLR6)
#define DDR1_PUB_ACBDLR7 (0x3000 + (0x17 << 2)) 	///../ucode/ddr3_reg.h:630
#define P_DDR1_PUB_ACBDLR7 		MMC_REG_ADDR(DDR1_PUB_ACBDLR7)
#define DDR1_PUB_ACBDLR8 (0x3000 + (0x18 << 2)) 	///../ucode/ddr3_reg.h:631
#define P_DDR1_PUB_ACBDLR8 		MMC_REG_ADDR(DDR1_PUB_ACBDLR8)
#define DDR1_PUB_ACBDLR9 (0x3000 + (0x19 << 2)) 	///../ucode/ddr3_reg.h:632
#define P_DDR1_PUB_ACBDLR9 		MMC_REG_ADDR(DDR1_PUB_ACBDLR9)
#define DDR1_PUB_ACIOCR0 (0x3000 + (0x1A << 2)) 	///../ucode/ddr3_reg.h:633
#define P_DDR1_PUB_ACIOCR0 		MMC_REG_ADDR(DDR1_PUB_ACIOCR0)
#define DDR1_PUB_ACIOCR1 (0x3000 + (0x1B << 2)) 	///../ucode/ddr3_reg.h:634
#define P_DDR1_PUB_ACIOCR1 		MMC_REG_ADDR(DDR1_PUB_ACIOCR1)
#define DDR1_PUB_ACIOCR2 (0x3000 + (0x1C << 2)) 	///../ucode/ddr3_reg.h:635
#define P_DDR1_PUB_ACIOCR2 		MMC_REG_ADDR(DDR1_PUB_ACIOCR2)
#define DDR1_PUB_ACIOCR3 (0x3000 + (0x1D << 2)) 	///../ucode/ddr3_reg.h:636
#define P_DDR1_PUB_ACIOCR3 		MMC_REG_ADDR(DDR1_PUB_ACIOCR3)
#define DDR1_PUB_ACIOCR4 (0x3000 + (0x1E << 2)) 	///../ucode/ddr3_reg.h:637
#define P_DDR1_PUB_ACIOCR4 		MMC_REG_ADDR(DDR1_PUB_ACIOCR4)
#define DDR1_PUB_ACIOCR5 (0x3000 + (0x1F << 2)) 	///../ucode/ddr3_reg.h:638
#define P_DDR1_PUB_ACIOCR5 		MMC_REG_ADDR(DDR1_PUB_ACIOCR5)
#define DDR1_PUB_DXCCR (0x3000 + (0x20 << 2)) 	///../ucode/ddr3_reg.h:639
#define P_DDR1_PUB_DXCCR 		MMC_REG_ADDR(DDR1_PUB_DXCCR)
#define DDR1_PUB_DSGCR (0x3000 + (0x21 << 2)) 	///../ucode/ddr3_reg.h:640
#define P_DDR1_PUB_DSGCR 		MMC_REG_ADDR(DDR1_PUB_DSGCR)
#define DDR1_PUB_DCR (0x3000 + (0x22 << 2)) 	///../ucode/ddr3_reg.h:641
#define P_DDR1_PUB_DCR 		MMC_REG_ADDR(DDR1_PUB_DCR)
#define DDR1_PUB_DTPR0 (0x3000 + (0x23 << 2)) 	///../ucode/ddr3_reg.h:642
#define P_DDR1_PUB_DTPR0 		MMC_REG_ADDR(DDR1_PUB_DTPR0)
#define DDR1_PUB_DTPR1 (0x3000 + (0x24 << 2)) 	///../ucode/ddr3_reg.h:643
#define P_DDR1_PUB_DTPR1 		MMC_REG_ADDR(DDR1_PUB_DTPR1)
#define DDR1_PUB_DTPR2 (0x3000 + (0x25 << 2)) 	///../ucode/ddr3_reg.h:644
#define P_DDR1_PUB_DTPR2 		MMC_REG_ADDR(DDR1_PUB_DTPR2)
#define DDR1_PUB_DTPR3 (0x3000 + (0x26 << 2)) 	///../ucode/ddr3_reg.h:645
#define P_DDR1_PUB_DTPR3 		MMC_REG_ADDR(DDR1_PUB_DTPR3)
#define DDR1_PUB_MR0 (0x3000 + (0x27 << 2)) 	///../ucode/ddr3_reg.h:646
#define P_DDR1_PUB_MR0 		MMC_REG_ADDR(DDR1_PUB_MR0)
#define DDR1_PUB_MR1 (0x3000 + (0x28 << 2)) 	///../ucode/ddr3_reg.h:647
#define P_DDR1_PUB_MR1 		MMC_REG_ADDR(DDR1_PUB_MR1)
#define DDR1_PUB_MR2 (0x3000 + (0x29 << 2)) 	///../ucode/ddr3_reg.h:648
#define P_DDR1_PUB_MR2 		MMC_REG_ADDR(DDR1_PUB_MR2)
#define DDR1_PUB_MR3 (0x3000 + (0x2A << 2)) 	///../ucode/ddr3_reg.h:649
#define P_DDR1_PUB_MR3 		MMC_REG_ADDR(DDR1_PUB_MR3)
#define DDR1_PUB_ODTCR (0x3000 + (0x2B << 2)) 	///../ucode/ddr3_reg.h:650
#define P_DDR1_PUB_ODTCR 		MMC_REG_ADDR(DDR1_PUB_ODTCR)
#define DDR1_PUB_DTCR (0x3000 + (0x2C << 2)) 	///../ucode/ddr3_reg.h:651
#define P_DDR1_PUB_DTCR 		MMC_REG_ADDR(DDR1_PUB_DTCR)
#define DDR1_PUB_DTAR0 (0x3000 + (0x2D << 2)) 	///../ucode/ddr3_reg.h:652
#define P_DDR1_PUB_DTAR0 		MMC_REG_ADDR(DDR1_PUB_DTAR0)
#define DDR1_PUB_DTAR1 (0x3000 + (0x2E << 2)) 	///../ucode/ddr3_reg.h:653
#define P_DDR1_PUB_DTAR1 		MMC_REG_ADDR(DDR1_PUB_DTAR1)
#define DDR1_PUB_DTAR2 (0x3000 + (0x2F << 2)) 	///../ucode/ddr3_reg.h:654
#define P_DDR1_PUB_DTAR2 		MMC_REG_ADDR(DDR1_PUB_DTAR2)
#define DDR1_PUB_DTAR3 (0x3000 + (0x30 << 2)) 	///../ucode/ddr3_reg.h:655
#define P_DDR1_PUB_DTAR3 		MMC_REG_ADDR(DDR1_PUB_DTAR3)
#define DDR1_PUB_DTDR0 (0x3000 + (0x31 << 2)) 	///../ucode/ddr3_reg.h:656
#define P_DDR1_PUB_DTDR0 		MMC_REG_ADDR(DDR1_PUB_DTDR0)
#define DDR1_PUB_DTDR1 (0x3000 + (0x32 << 2)) 	///../ucode/ddr3_reg.h:657
#define P_DDR1_PUB_DTDR1 		MMC_REG_ADDR(DDR1_PUB_DTDR1)
#define DDR1_PUB_DTEDR0 (0x3000 + (0x33 << 2)) 	///../ucode/ddr3_reg.h:658
#define P_DDR1_PUB_DTEDR0 		MMC_REG_ADDR(DDR1_PUB_DTEDR0)
#define DDR1_PUB_DTEDR1 (0x3000 + (0x34 << 2)) 	///../ucode/ddr3_reg.h:659
#define P_DDR1_PUB_DTEDR1 		MMC_REG_ADDR(DDR1_PUB_DTEDR1)
#define DDR1_PUB_RDIMMGCR0 (0x3000 + (0x35 << 2)) 	///../ucode/ddr3_reg.h:660
#define P_DDR1_PUB_RDIMMGCR0 		MMC_REG_ADDR(DDR1_PUB_RDIMMGCR0)
#define DDR1_PUB_RDIMMGCR1 (0x3000 + (0x36 << 2)) 	///../ucode/ddr3_reg.h:661
#define P_DDR1_PUB_RDIMMGCR1 		MMC_REG_ADDR(DDR1_PUB_RDIMMGCR1)
#define DDR1_PUB_RDIMMCR0 (0x3000 + (0x37 << 2)) 	///../ucode/ddr3_reg.h:662
#define P_DDR1_PUB_RDIMMCR0 		MMC_REG_ADDR(DDR1_PUB_RDIMMCR0)
#define DDR1_PUB_RDIMMCR1 (0x3000 + (0x38 << 2)) 	///../ucode/ddr3_reg.h:663
#define P_DDR1_PUB_RDIMMCR1 		MMC_REG_ADDR(DDR1_PUB_RDIMMCR1)
#define DDR1_PUB_GPR0 (0x3000 + (0x39 << 2)) 	///../ucode/ddr3_reg.h:664
#define P_DDR1_PUB_GPR0 		MMC_REG_ADDR(DDR1_PUB_GPR0)
#define DDR1_PUB_GPR1 (0x3000 + (0x3A << 2)) 	///../ucode/ddr3_reg.h:665
#define P_DDR1_PUB_GPR1 		MMC_REG_ADDR(DDR1_PUB_GPR1)
#define DDR1_PUB_CATR0 (0x3000 + (0x3B << 2)) 	///../ucode/ddr3_reg.h:666
#define P_DDR1_PUB_CATR0 		MMC_REG_ADDR(DDR1_PUB_CATR0)
#define DDR1_PUB_CATR1 (0x3000 + (0x3C << 2)) 	///../ucode/ddr3_reg.h:667
#define P_DDR1_PUB_CATR1 		MMC_REG_ADDR(DDR1_PUB_CATR1)
#define DDR1_PUB_DCUAR (0x3000 + (0x60 << 2)) 	///../ucode/ddr3_reg.h:668
#define P_DDR1_PUB_DCUAR 		MMC_REG_ADDR(DDR1_PUB_DCUAR)
#define DDR1_PUB_DCUDR (0x3000 + (0x61 << 2)) 	///../ucode/ddr3_reg.h:669
#define P_DDR1_PUB_DCUDR 		MMC_REG_ADDR(DDR1_PUB_DCUDR)
#define DDR1_PUB_DCURR (0x3000 + (0x62 << 2)) 	///../ucode/ddr3_reg.h:670
#define P_DDR1_PUB_DCURR 		MMC_REG_ADDR(DDR1_PUB_DCURR)
#define DDR1_PUB_DCULR (0x3000 + (0x63 << 2)) 	///../ucode/ddr3_reg.h:671
#define P_DDR1_PUB_DCULR 		MMC_REG_ADDR(DDR1_PUB_DCULR)
#define DDR1_PUB_DCUGCR (0x3000 + (0x64 << 2)) 	///../ucode/ddr3_reg.h:672
#define P_DDR1_PUB_DCUGCR 		MMC_REG_ADDR(DDR1_PUB_DCUGCR)
#define DDR1_PUB_DCUTPR (0x3000 + (0x65 << 2)) 	///../ucode/ddr3_reg.h:673
#define P_DDR1_PUB_DCUTPR 		MMC_REG_ADDR(DDR1_PUB_DCUTPR)
#define DDR1_PUB_DCUSR0 (0x3000 + (0x66 << 2)) 	///../ucode/ddr3_reg.h:674
#define P_DDR1_PUB_DCUSR0 		MMC_REG_ADDR(DDR1_PUB_DCUSR0)
#define DDR1_PUB_DCUSR1 (0x3000 + (0x67 << 2)) 	///../ucode/ddr3_reg.h:675
#define P_DDR1_PUB_DCUSR1 		MMC_REG_ADDR(DDR1_PUB_DCUSR1)
#define DDR1_PUB_BISTRR (0x3000 + (0x70 << 2)) 	///../ucode/ddr3_reg.h:676
#define P_DDR1_PUB_BISTRR 		MMC_REG_ADDR(DDR1_PUB_BISTRR)
#define DDR1_PUB_BISTWCR (0x3000 + (0x71 << 2)) 	///../ucode/ddr3_reg.h:677
#define P_DDR1_PUB_BISTWCR 		MMC_REG_ADDR(DDR1_PUB_BISTWCR)
#define DDR1_PUB_BISTMSKR0 (0x3000 + (0x72 << 2)) 	///../ucode/ddr3_reg.h:678
#define P_DDR1_PUB_BISTMSKR0 		MMC_REG_ADDR(DDR1_PUB_BISTMSKR0)
#define DDR1_PUB_BISTMSKR1 (0x3000 + (0x73 << 2)) 	///../ucode/ddr3_reg.h:679
#define P_DDR1_PUB_BISTMSKR1 		MMC_REG_ADDR(DDR1_PUB_BISTMSKR1)
#define DDR1_PUB_BISTMSKR2 (0x3000 + (0x74 << 2)) 	///../ucode/ddr3_reg.h:680
#define P_DDR1_PUB_BISTMSKR2 		MMC_REG_ADDR(DDR1_PUB_BISTMSKR2)
#define DDR1_PUB_BISTLSR (0x3000 + (0x75 << 2)) 	///../ucode/ddr3_reg.h:681
#define P_DDR1_PUB_BISTLSR 		MMC_REG_ADDR(DDR1_PUB_BISTLSR)
#define DDR1_PUB_BISTAR0 (0x3000 + (0x76 << 2)) 	///../ucode/ddr3_reg.h:682
#define P_DDR1_PUB_BISTAR0 		MMC_REG_ADDR(DDR1_PUB_BISTAR0)
#define DDR1_PUB_BISTAR1 (0x3000 + (0x77 << 2)) 	///../ucode/ddr3_reg.h:683
#define P_DDR1_PUB_BISTAR1 		MMC_REG_ADDR(DDR1_PUB_BISTAR1)
#define DDR1_PUB_BISTAR2 (0x3000 + (0x78 << 2)) 	///../ucode/ddr3_reg.h:684
#define P_DDR1_PUB_BISTAR2 		MMC_REG_ADDR(DDR1_PUB_BISTAR2)
#define DDR1_PUB_BISTUDPR (0x3000 + (0x79 << 2)) 	///../ucode/ddr3_reg.h:685
#define P_DDR1_PUB_BISTUDPR 		MMC_REG_ADDR(DDR1_PUB_BISTUDPR)
#define DDR1_PUB_BISTGSR (0x3000 + (0x7A << 2)) 	///../ucode/ddr3_reg.h:686
#define P_DDR1_PUB_BISTGSR 		MMC_REG_ADDR(DDR1_PUB_BISTGSR)
#define DDR1_PUB_BISTWER (0x3000 + (0x7B << 2)) 	///../ucode/ddr3_reg.h:687
#define P_DDR1_PUB_BISTWER 		MMC_REG_ADDR(DDR1_PUB_BISTWER)
#define DDR1_PUB_BISTBER0 (0x3000 + (0x7C << 2)) 	///../ucode/ddr3_reg.h:688
#define P_DDR1_PUB_BISTBER0 		MMC_REG_ADDR(DDR1_PUB_BISTBER0)
#define DDR1_PUB_BISTBER1 (0x3000 + (0x7D << 2)) 	///../ucode/ddr3_reg.h:689
#define P_DDR1_PUB_BISTBER1 		MMC_REG_ADDR(DDR1_PUB_BISTBER1)
#define DDR1_PUB_BISTBER2 (0x3000 + (0x7E << 2)) 	///../ucode/ddr3_reg.h:690
#define P_DDR1_PUB_BISTBER2 		MMC_REG_ADDR(DDR1_PUB_BISTBER2)
#define DDR1_PUB_BISTBER3 (0x3000 + (0x7F << 2)) 	///../ucode/ddr3_reg.h:691
#define P_DDR1_PUB_BISTBER3 		MMC_REG_ADDR(DDR1_PUB_BISTBER3)
#define DDR1_PUB_BISTWCSR (0x3000 + (0x80 << 2)) 	///../ucode/ddr3_reg.h:692
#define P_DDR1_PUB_BISTWCSR 		MMC_REG_ADDR(DDR1_PUB_BISTWCSR)
#define DDR1_PUB_BISTFWR0 (0x3000 + (0x81 << 2)) 	///../ucode/ddr3_reg.h:693
#define P_DDR1_PUB_BISTFWR0 		MMC_REG_ADDR(DDR1_PUB_BISTFWR0)
#define DDR1_PUB_BISTFWR1 (0x3000 + (0x82 << 2)) 	///../ucode/ddr3_reg.h:694
#define P_DDR1_PUB_BISTFWR1 		MMC_REG_ADDR(DDR1_PUB_BISTFWR1)
#define DDR1_PUB_BISTFWR2 (0x3000 + (0x83 << 2)) 	///../ucode/ddr3_reg.h:695
#define P_DDR1_PUB_BISTFWR2 		MMC_REG_ADDR(DDR1_PUB_BISTFWR2)
#define DDR1_PUB_IOVCR0 (0x3000 + (0x8E << 2)) 	///../ucode/ddr3_reg.h:696
#define P_DDR1_PUB_IOVCR0 		MMC_REG_ADDR(DDR1_PUB_IOVCR0)
#define DDR1_PUB_IOVCR1 (0x3000 + (0x8F << 2)) 	///../ucode/ddr3_reg.h:697
#define P_DDR1_PUB_IOVCR1 		MMC_REG_ADDR(DDR1_PUB_IOVCR1)
#define DDR1_PUB_ZQCR (0x3000 + (0x90 << 2)) 	///../ucode/ddr3_reg.h:698
#define P_DDR1_PUB_ZQCR 		MMC_REG_ADDR(DDR1_PUB_ZQCR)
#define DDR1_PUB_ZQ0PR (0x3000 + (0x91 << 2)) 	///../ucode/ddr3_reg.h:699
#define P_DDR1_PUB_ZQ0PR 		MMC_REG_ADDR(DDR1_PUB_ZQ0PR)
#define DDR1_PUB_ZQ0DR (0x3000 + (0x92 << 2)) 	///../ucode/ddr3_reg.h:700
#define P_DDR1_PUB_ZQ0DR 		MMC_REG_ADDR(DDR1_PUB_ZQ0DR)
#define DDR1_PUB_ZQ0SR (0x3000 + (0x93 << 2)) 	///../ucode/ddr3_reg.h:701
#define P_DDR1_PUB_ZQ0SR 		MMC_REG_ADDR(DDR1_PUB_ZQ0SR)
#define DDR1_PUB_ZQ1PR (0x3000 + (0x95 << 2)) 	///../ucode/ddr3_reg.h:702
#define P_DDR1_PUB_ZQ1PR 		MMC_REG_ADDR(DDR1_PUB_ZQ1PR)
#define DDR1_PUB_ZQ1DR (0x3000 + (0x96 << 2)) 	///../ucode/ddr3_reg.h:703
#define P_DDR1_PUB_ZQ1DR 		MMC_REG_ADDR(DDR1_PUB_ZQ1DR)
#define DDR1_PUB_ZQ1SR (0x3000 + (0x97 << 2)) 	///../ucode/ddr3_reg.h:704
#define P_DDR1_PUB_ZQ1SR 		MMC_REG_ADDR(DDR1_PUB_ZQ1SR)
#define DDR1_PUB_ZQ2PR (0x3000 + (0x99 << 2)) 	///../ucode/ddr3_reg.h:705
#define P_DDR1_PUB_ZQ2PR 		MMC_REG_ADDR(DDR1_PUB_ZQ2PR)
#define DDR1_PUB_ZQ2DR (0x3000 + (0x9A << 2)) 	///../ucode/ddr3_reg.h:706
#define P_DDR1_PUB_ZQ2DR 		MMC_REG_ADDR(DDR1_PUB_ZQ2DR)
#define DDR1_PUB_ZQ2SR (0x3000 + (0x9B << 2)) 	///../ucode/ddr3_reg.h:707
#define P_DDR1_PUB_ZQ2SR 		MMC_REG_ADDR(DDR1_PUB_ZQ2SR)
#define DDR1_PUB_ZQ3PR (0x3000 + (0x9D << 2)) 	///../ucode/ddr3_reg.h:708
#define P_DDR1_PUB_ZQ3PR 		MMC_REG_ADDR(DDR1_PUB_ZQ3PR)
#define DDR1_PUB_ZQ3DR (0x3000 + (0x9E << 2)) 	///../ucode/ddr3_reg.h:709
#define P_DDR1_PUB_ZQ3DR 		MMC_REG_ADDR(DDR1_PUB_ZQ3DR)
#define DDR1_PUB_ZQ3SR (0x3000 + (0x9F << 2)) 	///../ucode/ddr3_reg.h:710
#define P_DDR1_PUB_ZQ3SR 		MMC_REG_ADDR(DDR1_PUB_ZQ3SR)
#define DDR1_PUB_DX0GCR0 (0x3000 + (0xA0 << 2)) 	///../ucode/ddr3_reg.h:711
#define P_DDR1_PUB_DX0GCR0 		MMC_REG_ADDR(DDR1_PUB_DX0GCR0)
#define DDR1_PUB_DX0GCR1 (0x3000 + (0xA1 << 2)) 	///../ucode/ddr3_reg.h:712
#define P_DDR1_PUB_DX0GCR1 		MMC_REG_ADDR(DDR1_PUB_DX0GCR1)
#define DDR1_PUB_DX0GCR2 (0x3000 + (0xA2 << 2)) 	///../ucode/ddr3_reg.h:713
#define P_DDR1_PUB_DX0GCR2 		MMC_REG_ADDR(DDR1_PUB_DX0GCR2)
#define DDR1_PUB_DX0GCR3 (0x3000 + (0xA3 << 2)) 	///../ucode/ddr3_reg.h:714
#define P_DDR1_PUB_DX0GCR3 		MMC_REG_ADDR(DDR1_PUB_DX0GCR3)
#define DDR1_PUB_DX0GSR0 (0x3000 + (0xA4 << 2)) 	///../ucode/ddr3_reg.h:715
#define P_DDR1_PUB_DX0GSR0 		MMC_REG_ADDR(DDR1_PUB_DX0GSR0)
#define DDR1_PUB_DX0GSR1 (0x3000 + (0xA5 << 2)) 	///../ucode/ddr3_reg.h:716
#define P_DDR1_PUB_DX0GSR1 		MMC_REG_ADDR(DDR1_PUB_DX0GSR1)
#define DDR1_PUB_DX0GSR2 (0x3000 + (0xA6 << 2)) 	///../ucode/ddr3_reg.h:717
#define P_DDR1_PUB_DX0GSR2 		MMC_REG_ADDR(DDR1_PUB_DX0GSR2)
#define DDR1_PUB_DX0BDLR0 (0x3000 + (0xA7 << 2)) 	///../ucode/ddr3_reg.h:718
#define P_DDR1_PUB_DX0BDLR0 		MMC_REG_ADDR(DDR1_PUB_DX0BDLR0)
#define DDR1_PUB_DX0BDLR1 (0x3000 + (0xA8 << 2)) 	///../ucode/ddr3_reg.h:719
#define P_DDR1_PUB_DX0BDLR1 		MMC_REG_ADDR(DDR1_PUB_DX0BDLR1)
#define DDR1_PUB_DX0BDLR2 (0x3000 + (0xA9 << 2)) 	///../ucode/ddr3_reg.h:720
#define P_DDR1_PUB_DX0BDLR2 		MMC_REG_ADDR(DDR1_PUB_DX0BDLR2)
#define DDR1_PUB_DX0BDLR3 (0x3000 + (0xAA << 2)) 	///../ucode/ddr3_reg.h:721
#define P_DDR1_PUB_DX0BDLR3 		MMC_REG_ADDR(DDR1_PUB_DX0BDLR3)
#define DDR1_PUB_DX0BDLR4 (0x3000 + (0xAB << 2)) 	///../ucode/ddr3_reg.h:722
#define P_DDR1_PUB_DX0BDLR4 		MMC_REG_ADDR(DDR1_PUB_DX0BDLR4)
#define DDR1_PUB_DX0BDLR5 (0x3000 + (0xAC << 2)) 	///../ucode/ddr3_reg.h:723
#define P_DDR1_PUB_DX0BDLR5 		MMC_REG_ADDR(DDR1_PUB_DX0BDLR5)
#define DDR1_PUB_DX0BDLR6 (0x3000 + (0xAD << 2)) 	///../ucode/ddr3_reg.h:724
#define P_DDR1_PUB_DX0BDLR6 		MMC_REG_ADDR(DDR1_PUB_DX0BDLR6)
#define DDR1_PUB_DX0LCDLR0 (0x3000 + (0xAE << 2)) 	///../ucode/ddr3_reg.h:725
#define P_DDR1_PUB_DX0LCDLR0 		MMC_REG_ADDR(DDR1_PUB_DX0LCDLR0)
#define DDR1_PUB_DX0LCDLR1 (0x3000 + (0xAF << 2)) 	///../ucode/ddr3_reg.h:726
#define P_DDR1_PUB_DX0LCDLR1 		MMC_REG_ADDR(DDR1_PUB_DX0LCDLR1)
#define DDR1_PUB_DX0LCDLR2 (0x3000 + (0xB0 << 2)) 	///../ucode/ddr3_reg.h:727
#define P_DDR1_PUB_DX0LCDLR2 		MMC_REG_ADDR(DDR1_PUB_DX0LCDLR2)
#define DDR1_PUB_DX0MDLR (0x3000 + (0xB1 << 2)) 	///../ucode/ddr3_reg.h:728
#define P_DDR1_PUB_DX0MDLR 		MMC_REG_ADDR(DDR1_PUB_DX0MDLR)
#define DDR1_PUB_DX0GTR (0x3000 + (0xB2 << 2)) 	///../ucode/ddr3_reg.h:729
#define P_DDR1_PUB_DX0GTR 		MMC_REG_ADDR(DDR1_PUB_DX0GTR)
#define DDR1_PUB_DX1GCR0 (0x3000 + (0xC0 << 2)) 	///../ucode/ddr3_reg.h:730
#define P_DDR1_PUB_DX1GCR0 		MMC_REG_ADDR(DDR1_PUB_DX1GCR0)
#define DDR1_PUB_DX1GCR1 (0x3000 + (0xC1 << 2)) 	///../ucode/ddr3_reg.h:731
#define P_DDR1_PUB_DX1GCR1 		MMC_REG_ADDR(DDR1_PUB_DX1GCR1)
#define DDR1_PUB_DX1GCR2 (0x3000 + (0xC2 << 2)) 	///../ucode/ddr3_reg.h:732
#define P_DDR1_PUB_DX1GCR2 		MMC_REG_ADDR(DDR1_PUB_DX1GCR2)
#define DDR1_PUB_DX1GCR3 (0x3000 + (0xC3 << 2)) 	///../ucode/ddr3_reg.h:733
#define P_DDR1_PUB_DX1GCR3 		MMC_REG_ADDR(DDR1_PUB_DX1GCR3)
#define DDR1_PUB_DX1GSR0 (0x3000 + (0xC4 << 2)) 	///../ucode/ddr3_reg.h:734
#define P_DDR1_PUB_DX1GSR0 		MMC_REG_ADDR(DDR1_PUB_DX1GSR0)
#define DDR1_PUB_DX1GSR1 (0x3000 + (0xC5 << 2)) 	///../ucode/ddr3_reg.h:735
#define P_DDR1_PUB_DX1GSR1 		MMC_REG_ADDR(DDR1_PUB_DX1GSR1)
#define DDR1_PUB_DX1GSR2 (0x3000 + (0xC6 << 2)) 	///../ucode/ddr3_reg.h:736
#define P_DDR1_PUB_DX1GSR2 		MMC_REG_ADDR(DDR1_PUB_DX1GSR2)
#define DDR1_PUB_DX1BDLR0 (0x3000 + (0xC7 << 2)) 	///../ucode/ddr3_reg.h:737
#define P_DDR1_PUB_DX1BDLR0 		MMC_REG_ADDR(DDR1_PUB_DX1BDLR0)
#define DDR1_PUB_DX1BDLR1 (0x3000 + (0xC8 << 2)) 	///../ucode/ddr3_reg.h:738
#define P_DDR1_PUB_DX1BDLR1 		MMC_REG_ADDR(DDR1_PUB_DX1BDLR1)
#define DDR1_PUB_DX1BDLR2 (0x3000 + (0xC9 << 2)) 	///../ucode/ddr3_reg.h:739
#define P_DDR1_PUB_DX1BDLR2 		MMC_REG_ADDR(DDR1_PUB_DX1BDLR2)
#define DDR1_PUB_DX1BDLR3 (0x3000 + (0xCA << 2)) 	///../ucode/ddr3_reg.h:740
#define P_DDR1_PUB_DX1BDLR3 		MMC_REG_ADDR(DDR1_PUB_DX1BDLR3)
#define DDR1_PUB_DX1BDLR4 (0x3000 + (0xCB << 2)) 	///../ucode/ddr3_reg.h:741
#define P_DDR1_PUB_DX1BDLR4 		MMC_REG_ADDR(DDR1_PUB_DX1BDLR4)
#define DDR1_PUB_DX1BDLR5 (0x3000 + (0xCC << 2)) 	///../ucode/ddr3_reg.h:742
#define P_DDR1_PUB_DX1BDLR5 		MMC_REG_ADDR(DDR1_PUB_DX1BDLR5)
#define DDR1_PUB_DX1BDLR6 (0x3000 + (0xCD << 2)) 	///../ucode/ddr3_reg.h:743
#define P_DDR1_PUB_DX1BDLR6 		MMC_REG_ADDR(DDR1_PUB_DX1BDLR6)
#define DDR1_PUB_DX1LCDLR0 (0x3000 + (0xCE << 2)) 	///../ucode/ddr3_reg.h:744
#define P_DDR1_PUB_DX1LCDLR0 		MMC_REG_ADDR(DDR1_PUB_DX1LCDLR0)
#define DDR1_PUB_DX1LCDLR1 (0x3000 + (0xCF << 2)) 	///../ucode/ddr3_reg.h:745
#define P_DDR1_PUB_DX1LCDLR1 		MMC_REG_ADDR(DDR1_PUB_DX1LCDLR1)
#define DDR1_PUB_DX1LCDLR2 (0x3000 + (0xD0 << 2)) 	///../ucode/ddr3_reg.h:746
#define P_DDR1_PUB_DX1LCDLR2 		MMC_REG_ADDR(DDR1_PUB_DX1LCDLR2)
#define DDR1_PUB_DX1MDLR (0x3000 + (0xD1 << 2)) 	///../ucode/ddr3_reg.h:747
#define P_DDR1_PUB_DX1MDLR 		MMC_REG_ADDR(DDR1_PUB_DX1MDLR)
#define DDR1_PUB_DX1GTR (0x3000 + (0xD2 << 2)) 	///../ucode/ddr3_reg.h:748
#define P_DDR1_PUB_DX1GTR 		MMC_REG_ADDR(DDR1_PUB_DX1GTR)
#define DDR1_PUB_DX2GCR0 (0x3000 + (0xE0 << 2)) 	///../ucode/ddr3_reg.h:749
#define P_DDR1_PUB_DX2GCR0 		MMC_REG_ADDR(DDR1_PUB_DX2GCR0)
#define DDR1_PUB_DX2GCR1 (0x3000 + (0xE1 << 2)) 	///../ucode/ddr3_reg.h:750
#define P_DDR1_PUB_DX2GCR1 		MMC_REG_ADDR(DDR1_PUB_DX2GCR1)
#define DDR1_PUB_DX2GCR2 (0x3000 + (0xE2 << 2)) 	///../ucode/ddr3_reg.h:751
#define P_DDR1_PUB_DX2GCR2 		MMC_REG_ADDR(DDR1_PUB_DX2GCR2)
#define DDR1_PUB_DX2GCR3 (0x3000 + (0xE3 << 2)) 	///../ucode/ddr3_reg.h:752
#define P_DDR1_PUB_DX2GCR3 		MMC_REG_ADDR(DDR1_PUB_DX2GCR3)
#define DDR1_PUB_DX2GSR0 (0x3000 + (0xE4 << 2)) 	///../ucode/ddr3_reg.h:753
#define P_DDR1_PUB_DX2GSR0 		MMC_REG_ADDR(DDR1_PUB_DX2GSR0)
#define DDR1_PUB_DX2GSR1 (0x3000 + (0xE5 << 2)) 	///../ucode/ddr3_reg.h:754
#define P_DDR1_PUB_DX2GSR1 		MMC_REG_ADDR(DDR1_PUB_DX2GSR1)
#define DDR1_PUB_DX2GSR2 (0x3000 + (0xE6 << 2)) 	///../ucode/ddr3_reg.h:755
#define P_DDR1_PUB_DX2GSR2 		MMC_REG_ADDR(DDR1_PUB_DX2GSR2)
#define DDR1_PUB_DX2BDLR0 (0x3000 + (0xE7 << 2)) 	///../ucode/ddr3_reg.h:756
#define P_DDR1_PUB_DX2BDLR0 		MMC_REG_ADDR(DDR1_PUB_DX2BDLR0)
#define DDR1_PUB_DX2BDLR1 (0x3000 + (0xE8 << 2)) 	///../ucode/ddr3_reg.h:757
#define P_DDR1_PUB_DX2BDLR1 		MMC_REG_ADDR(DDR1_PUB_DX2BDLR1)
#define DDR1_PUB_DX2BDLR2 (0x3000 + (0xE9 << 2)) 	///../ucode/ddr3_reg.h:758
#define P_DDR1_PUB_DX2BDLR2 		MMC_REG_ADDR(DDR1_PUB_DX2BDLR2)
#define DDR1_PUB_DX2BDLR3 (0x3000 + (0xEA << 2)) 	///../ucode/ddr3_reg.h:759
#define P_DDR1_PUB_DX2BDLR3 		MMC_REG_ADDR(DDR1_PUB_DX2BDLR3)
#define DDR1_PUB_DX2BDLR4 (0x3000 + (0xEB << 2)) 	///../ucode/ddr3_reg.h:760
#define P_DDR1_PUB_DX2BDLR4 		MMC_REG_ADDR(DDR1_PUB_DX2BDLR4)
#define DDR1_PUB_DX2BDLR5 (0x3000 + (0xEC << 2)) 	///../ucode/ddr3_reg.h:761
#define P_DDR1_PUB_DX2BDLR5 		MMC_REG_ADDR(DDR1_PUB_DX2BDLR5)
#define DDR1_PUB_DX2BDLR6 (0x3000 + (0xED << 2)) 	///../ucode/ddr3_reg.h:762
#define P_DDR1_PUB_DX2BDLR6 		MMC_REG_ADDR(DDR1_PUB_DX2BDLR6)
#define DDR1_PUB_DX2LCDLR0 (0x3000 + (0xEE << 2)) 	///../ucode/ddr3_reg.h:763
#define P_DDR1_PUB_DX2LCDLR0 		MMC_REG_ADDR(DDR1_PUB_DX2LCDLR0)
#define DDR1_PUB_DX2LCDLR1 (0x3000 + (0xEF << 2)) 	///../ucode/ddr3_reg.h:764
#define P_DDR1_PUB_DX2LCDLR1 		MMC_REG_ADDR(DDR1_PUB_DX2LCDLR1)
#define DDR1_PUB_DX2LCDLR2 (0x3000 + (0xF0 << 2)) 	///../ucode/ddr3_reg.h:765
#define P_DDR1_PUB_DX2LCDLR2 		MMC_REG_ADDR(DDR1_PUB_DX2LCDLR2)
#define DDR1_PUB_DX2MDLR (0x3000 + (0xF1 << 2)) 	///../ucode/ddr3_reg.h:766
#define P_DDR1_PUB_DX2MDLR 		MMC_REG_ADDR(DDR1_PUB_DX2MDLR)
#define DDR1_PUB_DX2GTR (0x3000 + (0xF2 << 2)) 	///../ucode/ddr3_reg.h:767
#define P_DDR1_PUB_DX2GTR 		MMC_REG_ADDR(DDR1_PUB_DX2GTR)
#define DDR1_PUB_DX3GCR0 (0x3000 + (0x100 << 2)) 	///../ucode/ddr3_reg.h:768
#define P_DDR1_PUB_DX3GCR0 		MMC_REG_ADDR(DDR1_PUB_DX3GCR0)
#define DDR1_PUB_DX3GCR1 (0x3000 + (0x101 << 2)) 	///../ucode/ddr3_reg.h:769
#define P_DDR1_PUB_DX3GCR1 		MMC_REG_ADDR(DDR1_PUB_DX3GCR1)
#define DDR1_PUB_DX3GCR2 (0x3000 + (0x102 << 2)) 	///../ucode/ddr3_reg.h:770
#define P_DDR1_PUB_DX3GCR2 		MMC_REG_ADDR(DDR1_PUB_DX3GCR2)
#define DDR1_PUB_DX3GCR3 (0x3000 + (0x103 << 2)) 	///../ucode/ddr3_reg.h:771
#define P_DDR1_PUB_DX3GCR3 		MMC_REG_ADDR(DDR1_PUB_DX3GCR3)
#define DDR1_PUB_DX3GSR0 (0x3000 + (0x104 << 2)) 	///../ucode/ddr3_reg.h:772
#define P_DDR1_PUB_DX3GSR0 		MMC_REG_ADDR(DDR1_PUB_DX3GSR0)
#define DDR1_PUB_DX3GSR1 (0x3000 + (0x105 << 2)) 	///../ucode/ddr3_reg.h:773
#define P_DDR1_PUB_DX3GSR1 		MMC_REG_ADDR(DDR1_PUB_DX3GSR1)
#define DDR1_PUB_DX3GSR2 (0x3000 + (0x106 << 2)) 	///../ucode/ddr3_reg.h:774
#define P_DDR1_PUB_DX3GSR2 		MMC_REG_ADDR(DDR1_PUB_DX3GSR2)
#define DDR1_PUB_DX3BDLR0 (0x3000 + (0x107 << 2)) 	///../ucode/ddr3_reg.h:775
#define P_DDR1_PUB_DX3BDLR0 		MMC_REG_ADDR(DDR1_PUB_DX3BDLR0)
#define DDR1_PUB_DX3BDLR1 (0x3000 + (0x108 << 2)) 	///../ucode/ddr3_reg.h:776
#define P_DDR1_PUB_DX3BDLR1 		MMC_REG_ADDR(DDR1_PUB_DX3BDLR1)
#define DDR1_PUB_DX3BDLR2 (0x3000 + (0x109 << 2)) 	///../ucode/ddr3_reg.h:777
#define P_DDR1_PUB_DX3BDLR2 		MMC_REG_ADDR(DDR1_PUB_DX3BDLR2)
#define DDR1_PUB_DX3BDLR3 (0x3000 + (0x10A << 2)) 	///../ucode/ddr3_reg.h:778
#define P_DDR1_PUB_DX3BDLR3 		MMC_REG_ADDR(DDR1_PUB_DX3BDLR3)
#define DDR1_PUB_DX3BDLR4 (0x3000 + (0x10B << 2)) 	///../ucode/ddr3_reg.h:779
#define P_DDR1_PUB_DX3BDLR4 		MMC_REG_ADDR(DDR1_PUB_DX3BDLR4)
#define DDR1_PUB_DX3BDLR5 (0x3000 + (0x10C << 2)) 	///../ucode/ddr3_reg.h:780
#define P_DDR1_PUB_DX3BDLR5 		MMC_REG_ADDR(DDR1_PUB_DX3BDLR5)
#define DDR1_PUB_DX3BDLR6 (0x3000 + (0x10D << 2)) 	///../ucode/ddr3_reg.h:781
#define P_DDR1_PUB_DX3BDLR6 		MMC_REG_ADDR(DDR1_PUB_DX3BDLR6)
#define DDR1_PUB_DX3LCDLR0 (0x3000 + (0x10E << 2)) 	///../ucode/ddr3_reg.h:782
#define P_DDR1_PUB_DX3LCDLR0 		MMC_REG_ADDR(DDR1_PUB_DX3LCDLR0)
#define DDR1_PUB_DX3LCDLR1 (0x3000 + (0x10F << 2)) 	///../ucode/ddr3_reg.h:783
#define P_DDR1_PUB_DX3LCDLR1 		MMC_REG_ADDR(DDR1_PUB_DX3LCDLR1)
#define DDR1_PUB_DX3LCDLR2 (0x3000 + (0x110 << 2)) 	///../ucode/ddr3_reg.h:784
#define P_DDR1_PUB_DX3LCDLR2 		MMC_REG_ADDR(DDR1_PUB_DX3LCDLR2)
#define DDR1_PUB_DX3MDLR (0x3000 + (0x111 << 2)) 	///../ucode/ddr3_reg.h:785
#define P_DDR1_PUB_DX3MDLR 		MMC_REG_ADDR(DDR1_PUB_DX3MDLR)
#define DDR1_PUB_DX3GTR (0x3000 + (0x112 << 2)) 	///../ucode/ddr3_reg.h:786
#define P_DDR1_PUB_DX3GTR 		MMC_REG_ADDR(DDR1_PUB_DX3GTR)
#define DDR1_PUB_DX4GCR0 (0x3000 + (0x120 << 2)) 	///../ucode/ddr3_reg.h:787
#define P_DDR1_PUB_DX4GCR0 		MMC_REG_ADDR(DDR1_PUB_DX4GCR0)
#define DDR1_PUB_DX4GCR1 (0x3000 + (0x121 << 2)) 	///../ucode/ddr3_reg.h:788
#define P_DDR1_PUB_DX4GCR1 		MMC_REG_ADDR(DDR1_PUB_DX4GCR1)
#define DDR1_PUB_DX4GCR2 (0x3000 + (0x122 << 2)) 	///../ucode/ddr3_reg.h:789
#define P_DDR1_PUB_DX4GCR2 		MMC_REG_ADDR(DDR1_PUB_DX4GCR2)
#define DDR1_PUB_DX4GCR3 (0x3000 + (0x123 << 2)) 	///../ucode/ddr3_reg.h:790
#define P_DDR1_PUB_DX4GCR3 		MMC_REG_ADDR(DDR1_PUB_DX4GCR3)
#define DDR1_PUB_DX4GSR0 (0x3000 + (0x124 << 2)) 	///../ucode/ddr3_reg.h:791
#define P_DDR1_PUB_DX4GSR0 		MMC_REG_ADDR(DDR1_PUB_DX4GSR0)
#define DDR1_PUB_DX4GSR1 (0x3000 + (0x125 << 2)) 	///../ucode/ddr3_reg.h:792
#define P_DDR1_PUB_DX4GSR1 		MMC_REG_ADDR(DDR1_PUB_DX4GSR1)
#define DDR1_PUB_DX4GSR2 (0x3000 + (0x126 << 2)) 	///../ucode/ddr3_reg.h:793
#define P_DDR1_PUB_DX4GSR2 		MMC_REG_ADDR(DDR1_PUB_DX4GSR2)
#define DDR1_PUB_DX4BDLR0 (0x3000 + (0x127 << 2)) 	///../ucode/ddr3_reg.h:794
#define P_DDR1_PUB_DX4BDLR0 		MMC_REG_ADDR(DDR1_PUB_DX4BDLR0)
#define DDR1_PUB_DX4BDLR1 (0x3000 + (0x128 << 2)) 	///../ucode/ddr3_reg.h:795
#define P_DDR1_PUB_DX4BDLR1 		MMC_REG_ADDR(DDR1_PUB_DX4BDLR1)
#define DDR1_PUB_DX4BDLR2 (0x3000 + (0x129 << 2)) 	///../ucode/ddr3_reg.h:796
#define P_DDR1_PUB_DX4BDLR2 		MMC_REG_ADDR(DDR1_PUB_DX4BDLR2)
#define DDR1_PUB_DX4BDLR3 (0x3000 + (0x12A << 2)) 	///../ucode/ddr3_reg.h:797
#define P_DDR1_PUB_DX4BDLR3 		MMC_REG_ADDR(DDR1_PUB_DX4BDLR3)
#define DDR1_PUB_DX4BDLR4 (0x3000 + (0x12B << 2)) 	///../ucode/ddr3_reg.h:798
#define P_DDR1_PUB_DX4BDLR4 		MMC_REG_ADDR(DDR1_PUB_DX4BDLR4)
#define DDR1_PUB_DX4BDLR5 (0x3000 + (0x12C << 2)) 	///../ucode/ddr3_reg.h:799
#define P_DDR1_PUB_DX4BDLR5 		MMC_REG_ADDR(DDR1_PUB_DX4BDLR5)
#define DDR1_PUB_DX4BDLR6 (0x3000 + (0x12D << 2)) 	///../ucode/ddr3_reg.h:800
#define P_DDR1_PUB_DX4BDLR6 		MMC_REG_ADDR(DDR1_PUB_DX4BDLR6)
#define DDR1_PUB_DX4LCDLR0 (0x3000 + (0x12E << 2)) 	///../ucode/ddr3_reg.h:801
#define P_DDR1_PUB_DX4LCDLR0 		MMC_REG_ADDR(DDR1_PUB_DX4LCDLR0)
#define DDR1_PUB_DX4LCDLR1 (0x3000 + (0x12F << 2)) 	///../ucode/ddr3_reg.h:802
#define P_DDR1_PUB_DX4LCDLR1 		MMC_REG_ADDR(DDR1_PUB_DX4LCDLR1)
#define DDR1_PUB_DX4LCDLR2 (0x3000 + (0x130 << 2)) 	///../ucode/ddr3_reg.h:803
#define P_DDR1_PUB_DX4LCDLR2 		MMC_REG_ADDR(DDR1_PUB_DX4LCDLR2)
#define DDR1_PUB_DX4MDLR (0x3000 + (0x131 << 2)) 	///../ucode/ddr3_reg.h:804
#define P_DDR1_PUB_DX4MDLR 		MMC_REG_ADDR(DDR1_PUB_DX4MDLR)
#define DDR1_PUB_DX4GTR (0x3000 + (0x132 << 2)) 	///../ucode/ddr3_reg.h:805
#define P_DDR1_PUB_DX4GTR 		MMC_REG_ADDR(DDR1_PUB_DX4GTR)
#define DDR1_PUB_DX5GCR0 (0x3000 + (0x140 << 2)) 	///../ucode/ddr3_reg.h:806
#define P_DDR1_PUB_DX5GCR0 		MMC_REG_ADDR(DDR1_PUB_DX5GCR0)
#define DDR1_PUB_DX5GCR1 (0x3000 + (0x141 << 2)) 	///../ucode/ddr3_reg.h:807
#define P_DDR1_PUB_DX5GCR1 		MMC_REG_ADDR(DDR1_PUB_DX5GCR1)
#define DDR1_PUB_DX5GCR2 (0x3000 + (0x142 << 2)) 	///../ucode/ddr3_reg.h:808
#define P_DDR1_PUB_DX5GCR2 		MMC_REG_ADDR(DDR1_PUB_DX5GCR2)
#define DDR1_PUB_DX5GCR3 (0x3000 + (0x143 << 2)) 	///../ucode/ddr3_reg.h:809
#define P_DDR1_PUB_DX5GCR3 		MMC_REG_ADDR(DDR1_PUB_DX5GCR3)
#define DDR1_PUB_DX5GSR0 (0x3000 + (0x144 << 2)) 	///../ucode/ddr3_reg.h:810
#define P_DDR1_PUB_DX5GSR0 		MMC_REG_ADDR(DDR1_PUB_DX5GSR0)
#define DDR1_PUB_DX5GSR1 (0x3000 + (0x145 << 2)) 	///../ucode/ddr3_reg.h:811
#define P_DDR1_PUB_DX5GSR1 		MMC_REG_ADDR(DDR1_PUB_DX5GSR1)
#define DDR1_PUB_DX5GSR2 (0x3000 + (0x146 << 2)) 	///../ucode/ddr3_reg.h:812
#define P_DDR1_PUB_DX5GSR2 		MMC_REG_ADDR(DDR1_PUB_DX5GSR2)
#define DDR1_PUB_DX5BDLR0 (0x3000 + (0x147 << 2)) 	///../ucode/ddr3_reg.h:813
#define P_DDR1_PUB_DX5BDLR0 		MMC_REG_ADDR(DDR1_PUB_DX5BDLR0)
#define DDR1_PUB_DX5BDLR1 (0x3000 + (0x148 << 2)) 	///../ucode/ddr3_reg.h:814
#define P_DDR1_PUB_DX5BDLR1 		MMC_REG_ADDR(DDR1_PUB_DX5BDLR1)
#define DDR1_PUB_DX5BDLR2 (0x3000 + (0x149 << 2)) 	///../ucode/ddr3_reg.h:815
#define P_DDR1_PUB_DX5BDLR2 		MMC_REG_ADDR(DDR1_PUB_DX5BDLR2)
#define DDR1_PUB_DX5BDLR3 (0x3000 + (0x14A << 2)) 	///../ucode/ddr3_reg.h:816
#define P_DDR1_PUB_DX5BDLR3 		MMC_REG_ADDR(DDR1_PUB_DX5BDLR3)
#define DDR1_PUB_DX5BDLR4 (0x3000 + (0x14B << 2)) 	///../ucode/ddr3_reg.h:817
#define P_DDR1_PUB_DX5BDLR4 		MMC_REG_ADDR(DDR1_PUB_DX5BDLR4)
#define DDR1_PUB_DX5BDLR5 (0x3000 + (0x14C << 2)) 	///../ucode/ddr3_reg.h:818
#define P_DDR1_PUB_DX5BDLR5 		MMC_REG_ADDR(DDR1_PUB_DX5BDLR5)
#define DDR1_PUB_DX5BDLR6 (0x3000 + (0x14D << 2)) 	///../ucode/ddr3_reg.h:819
#define P_DDR1_PUB_DX5BDLR6 		MMC_REG_ADDR(DDR1_PUB_DX5BDLR6)
#define DDR1_PUB_DX5LCDLR0 (0x3000 + (0x14E << 2)) 	///../ucode/ddr3_reg.h:820
#define P_DDR1_PUB_DX5LCDLR0 		MMC_REG_ADDR(DDR1_PUB_DX5LCDLR0)
#define DDR1_PUB_DX5LCDLR1 (0x3000 + (0x14F << 2)) 	///../ucode/ddr3_reg.h:821
#define P_DDR1_PUB_DX5LCDLR1 		MMC_REG_ADDR(DDR1_PUB_DX5LCDLR1)
#define DDR1_PUB_DX5LCDLR2 (0x3000 + (0x150 << 2)) 	///../ucode/ddr3_reg.h:822
#define P_DDR1_PUB_DX5LCDLR2 		MMC_REG_ADDR(DDR1_PUB_DX5LCDLR2)
#define DDR1_PUB_DX5MDLR (0x3000 + (0x151 << 2)) 	///../ucode/ddr3_reg.h:823
#define P_DDR1_PUB_DX5MDLR 		MMC_REG_ADDR(DDR1_PUB_DX5MDLR)
#define DDR1_PUB_DX5GTR (0x3000 + (0x152 << 2)) 	///../ucode/ddr3_reg.h:824
#define P_DDR1_PUB_DX5GTR 		MMC_REG_ADDR(DDR1_PUB_DX5GTR)
#define DDR1_PUB_DX6GCR0 (0x3000 + (0x160 << 2)) 	///../ucode/ddr3_reg.h:825
#define P_DDR1_PUB_DX6GCR0 		MMC_REG_ADDR(DDR1_PUB_DX6GCR0)
#define DDR1_PUB_DX6GCR1 (0x3000 + (0x161 << 2)) 	///../ucode/ddr3_reg.h:826
#define P_DDR1_PUB_DX6GCR1 		MMC_REG_ADDR(DDR1_PUB_DX6GCR1)
#define DDR1_PUB_DX6GCR2 (0x3000 + (0x162 << 2)) 	///../ucode/ddr3_reg.h:827
#define P_DDR1_PUB_DX6GCR2 		MMC_REG_ADDR(DDR1_PUB_DX6GCR2)
#define DDR1_PUB_DX6GCR3 (0x3000 + (0x163 << 2)) 	///../ucode/ddr3_reg.h:828
#define P_DDR1_PUB_DX6GCR3 		MMC_REG_ADDR(DDR1_PUB_DX6GCR3)
#define DDR1_PUB_DX6GSR0 (0x3000 + (0x164 << 2)) 	///../ucode/ddr3_reg.h:829
#define P_DDR1_PUB_DX6GSR0 		MMC_REG_ADDR(DDR1_PUB_DX6GSR0)
#define DDR1_PUB_DX6GSR1 (0x3000 + (0x165 << 2)) 	///../ucode/ddr3_reg.h:830
#define P_DDR1_PUB_DX6GSR1 		MMC_REG_ADDR(DDR1_PUB_DX6GSR1)
#define DDR1_PUB_DX6GSR2 (0x3000 + (0x166 << 2)) 	///../ucode/ddr3_reg.h:831
#define P_DDR1_PUB_DX6GSR2 		MMC_REG_ADDR(DDR1_PUB_DX6GSR2)
#define DDR1_PUB_DX6BDLR0 (0x3000 + (0x167 << 2)) 	///../ucode/ddr3_reg.h:832
#define P_DDR1_PUB_DX6BDLR0 		MMC_REG_ADDR(DDR1_PUB_DX6BDLR0)
#define DDR1_PUB_DX6BDLR1 (0x3000 + (0x168 << 2)) 	///../ucode/ddr3_reg.h:833
#define P_DDR1_PUB_DX6BDLR1 		MMC_REG_ADDR(DDR1_PUB_DX6BDLR1)
#define DDR1_PUB_DX6BDLR2 (0x3000 + (0x169 << 2)) 	///../ucode/ddr3_reg.h:834
#define P_DDR1_PUB_DX6BDLR2 		MMC_REG_ADDR(DDR1_PUB_DX6BDLR2)
#define DDR1_PUB_DX6BDLR3 (0x3000 + (0x16A << 2)) 	///../ucode/ddr3_reg.h:835
#define P_DDR1_PUB_DX6BDLR3 		MMC_REG_ADDR(DDR1_PUB_DX6BDLR3)
#define DDR1_PUB_DX6BDLR4 (0x3000 + (0x16B << 2)) 	///../ucode/ddr3_reg.h:836
#define P_DDR1_PUB_DX6BDLR4 		MMC_REG_ADDR(DDR1_PUB_DX6BDLR4)
#define DDR1_PUB_DX6BDLR5 (0x3000 + (0x16C << 2)) 	///../ucode/ddr3_reg.h:837
#define P_DDR1_PUB_DX6BDLR5 		MMC_REG_ADDR(DDR1_PUB_DX6BDLR5)
#define DDR1_PUB_DX6BDLR6 (0x3000 + (0x16D << 2)) 	///../ucode/ddr3_reg.h:838
#define P_DDR1_PUB_DX6BDLR6 		MMC_REG_ADDR(DDR1_PUB_DX6BDLR6)
#define DDR1_PUB_DX6LCDLR0 (0x3000 + (0x16E << 2)) 	///../ucode/ddr3_reg.h:839
#define P_DDR1_PUB_DX6LCDLR0 		MMC_REG_ADDR(DDR1_PUB_DX6LCDLR0)
#define DDR1_PUB_DX6LCDLR1 (0x3000 + (0x16F << 2)) 	///../ucode/ddr3_reg.h:840
#define P_DDR1_PUB_DX6LCDLR1 		MMC_REG_ADDR(DDR1_PUB_DX6LCDLR1)
#define DDR1_PUB_DX6LCDLR2 (0x3000 + (0x170 << 2)) 	///../ucode/ddr3_reg.h:841
#define P_DDR1_PUB_DX6LCDLR2 		MMC_REG_ADDR(DDR1_PUB_DX6LCDLR2)
#define DDR1_PUB_DX6MDLR (0x3000 + (0x171 << 2)) 	///../ucode/ddr3_reg.h:842
#define P_DDR1_PUB_DX6MDLR 		MMC_REG_ADDR(DDR1_PUB_DX6MDLR)
#define DDR1_PUB_DX6GTR (0x3000 + (0x172 << 2)) 	///../ucode/ddr3_reg.h:843
#define P_DDR1_PUB_DX6GTR 		MMC_REG_ADDR(DDR1_PUB_DX6GTR)
#define DDR1_PUB_DX7GCR0 (0x3000 + (0x180 << 2)) 	///../ucode/ddr3_reg.h:844
#define P_DDR1_PUB_DX7GCR0 		MMC_REG_ADDR(DDR1_PUB_DX7GCR0)
#define DDR1_PUB_DX7GCR1 (0x3000 + (0x181 << 2)) 	///../ucode/ddr3_reg.h:845
#define P_DDR1_PUB_DX7GCR1 		MMC_REG_ADDR(DDR1_PUB_DX7GCR1)
#define DDR1_PUB_DX7GCR2 (0x3000 + (0x182 << 2)) 	///../ucode/ddr3_reg.h:846
#define P_DDR1_PUB_DX7GCR2 		MMC_REG_ADDR(DDR1_PUB_DX7GCR2)
#define DDR1_PUB_DX7GCR3 (0x3000 + (0x183 << 2)) 	///../ucode/ddr3_reg.h:847
#define P_DDR1_PUB_DX7GCR3 		MMC_REG_ADDR(DDR1_PUB_DX7GCR3)
#define DDR1_PUB_DX7GSR0 (0x3000 + (0x184 << 2)) 	///../ucode/ddr3_reg.h:848
#define P_DDR1_PUB_DX7GSR0 		MMC_REG_ADDR(DDR1_PUB_DX7GSR0)
#define DDR1_PUB_DX7GSR1 (0x3000 + (0x185 << 2)) 	///../ucode/ddr3_reg.h:849
#define P_DDR1_PUB_DX7GSR1 		MMC_REG_ADDR(DDR1_PUB_DX7GSR1)
#define DDR1_PUB_DX7GSR2 (0x3000 + (0x186 << 2)) 	///../ucode/ddr3_reg.h:850
#define P_DDR1_PUB_DX7GSR2 		MMC_REG_ADDR(DDR1_PUB_DX7GSR2)
#define DDR1_PUB_DX7BDLR0 (0x3000 + (0x187 << 2)) 	///../ucode/ddr3_reg.h:851
#define P_DDR1_PUB_DX7BDLR0 		MMC_REG_ADDR(DDR1_PUB_DX7BDLR0)
#define DDR1_PUB_DX7BDLR1 (0x3000 + (0x188 << 2)) 	///../ucode/ddr3_reg.h:852
#define P_DDR1_PUB_DX7BDLR1 		MMC_REG_ADDR(DDR1_PUB_DX7BDLR1)
#define DDR1_PUB_DX7BDLR2 (0x3000 + (0x189 << 2)) 	///../ucode/ddr3_reg.h:853
#define P_DDR1_PUB_DX7BDLR2 		MMC_REG_ADDR(DDR1_PUB_DX7BDLR2)
#define DDR1_PUB_DX7BDLR3 (0x3000 + (0x18A << 2)) 	///../ucode/ddr3_reg.h:854
#define P_DDR1_PUB_DX7BDLR3 		MMC_REG_ADDR(DDR1_PUB_DX7BDLR3)
#define DDR1_PUB_DX7BDLR4 (0x3000 + (0x18B << 2)) 	///../ucode/ddr3_reg.h:855
#define P_DDR1_PUB_DX7BDLR4 		MMC_REG_ADDR(DDR1_PUB_DX7BDLR4)
#define DDR1_PUB_DX7BDLR5 (0x3000 + (0x18C << 2)) 	///../ucode/ddr3_reg.h:856
#define P_DDR1_PUB_DX7BDLR5 		MMC_REG_ADDR(DDR1_PUB_DX7BDLR5)
#define DDR1_PUB_DX7BDLR6 (0x3000 + (0x18D << 2)) 	///../ucode/ddr3_reg.h:857
#define P_DDR1_PUB_DX7BDLR6 		MMC_REG_ADDR(DDR1_PUB_DX7BDLR6)
#define DDR1_PUB_DX7LCDLR0 (0x3000 + (0x18E << 2)) 	///../ucode/ddr3_reg.h:858
#define P_DDR1_PUB_DX7LCDLR0 		MMC_REG_ADDR(DDR1_PUB_DX7LCDLR0)
#define DDR1_PUB_DX7LCDLR1 (0x3000 + (0x18F << 2)) 	///../ucode/ddr3_reg.h:859
#define P_DDR1_PUB_DX7LCDLR1 		MMC_REG_ADDR(DDR1_PUB_DX7LCDLR1)
#define DDR1_PUB_DX7LCDLR2 (0x3000 + (0x190 << 2)) 	///../ucode/ddr3_reg.h:860
#define P_DDR1_PUB_DX7LCDLR2 		MMC_REG_ADDR(DDR1_PUB_DX7LCDLR2)
#define DDR1_PUB_DX7MDLR (0x3000 + (0x191 << 2)) 	///../ucode/ddr3_reg.h:861
#define P_DDR1_PUB_DX7MDLR 		MMC_REG_ADDR(DDR1_PUB_DX7MDLR)
#define DDR1_PUB_DX7GTR (0x3000 + (0x192 << 2)) 	///../ucode/ddr3_reg.h:862
#define P_DDR1_PUB_DX7GTR 		MMC_REG_ADDR(DDR1_PUB_DX7GTR)
#define DDR1_PUB_DX8GCR0 (0x3000 + (0x1A0 << 2)) 	///../ucode/ddr3_reg.h:863
#define P_DDR1_PUB_DX8GCR0 		MMC_REG_ADDR(DDR1_PUB_DX8GCR0)
#define DDR1_PUB_DX8GCR1 (0x3000 + (0x1A1 << 2)) 	///../ucode/ddr3_reg.h:864
#define P_DDR1_PUB_DX8GCR1 		MMC_REG_ADDR(DDR1_PUB_DX8GCR1)
#define DDR1_PUB_DX8GCR2 (0x3000 + (0x1A2 << 2)) 	///../ucode/ddr3_reg.h:865
#define P_DDR1_PUB_DX8GCR2 		MMC_REG_ADDR(DDR1_PUB_DX8GCR2)
#define DDR1_PUB_DX8GCR3 (0x3000 + (0x1A3 << 2)) 	///../ucode/ddr3_reg.h:866
#define P_DDR1_PUB_DX8GCR3 		MMC_REG_ADDR(DDR1_PUB_DX8GCR3)
#define DDR1_PUB_DX8GSR0 (0x3000 + (0x1A4 << 2)) 	///../ucode/ddr3_reg.h:867
#define P_DDR1_PUB_DX8GSR0 		MMC_REG_ADDR(DDR1_PUB_DX8GSR0)
#define DDR1_PUB_DX8GSR1 (0x3000 + (0x1A5 << 2)) 	///../ucode/ddr3_reg.h:868
#define P_DDR1_PUB_DX8GSR1 		MMC_REG_ADDR(DDR1_PUB_DX8GSR1)
#define DDR1_PUB_DX8GSR2 (0x3000 + (0x1A6 << 2)) 	///../ucode/ddr3_reg.h:869
#define P_DDR1_PUB_DX8GSR2 		MMC_REG_ADDR(DDR1_PUB_DX8GSR2)
#define DDR1_PUB_DX8BDLR0 (0x3000 + (0x1A7 << 2)) 	///../ucode/ddr3_reg.h:870
#define P_DDR1_PUB_DX8BDLR0 		MMC_REG_ADDR(DDR1_PUB_DX8BDLR0)
#define DDR1_PUB_DX8BDLR1 (0x3000 + (0x1A8 << 2)) 	///../ucode/ddr3_reg.h:871
#define P_DDR1_PUB_DX8BDLR1 		MMC_REG_ADDR(DDR1_PUB_DX8BDLR1)
#define DDR1_PUB_DX8BDLR2 (0x3000 + (0x1A9 << 2)) 	///../ucode/ddr3_reg.h:872
#define P_DDR1_PUB_DX8BDLR2 		MMC_REG_ADDR(DDR1_PUB_DX8BDLR2)
#define DDR1_PUB_DX8BDLR3 (0x3000 + (0x1AA << 2)) 	///../ucode/ddr3_reg.h:873
#define P_DDR1_PUB_DX8BDLR3 		MMC_REG_ADDR(DDR1_PUB_DX8BDLR3)
#define DDR1_PUB_DX8BDLR4 (0x3000 + (0x1AB << 2)) 	///../ucode/ddr3_reg.h:874
#define P_DDR1_PUB_DX8BDLR4 		MMC_REG_ADDR(DDR1_PUB_DX8BDLR4)
#define DDR1_PUB_DX8BDLR5 (0x3000 + (0x1AC << 2)) 	///../ucode/ddr3_reg.h:875
#define P_DDR1_PUB_DX8BDLR5 		MMC_REG_ADDR(DDR1_PUB_DX8BDLR5)
#define DDR1_PUB_DX8BDLR6 (0x3000 + (0x1AD << 2)) 	///../ucode/ddr3_reg.h:876
#define P_DDR1_PUB_DX8BDLR6 		MMC_REG_ADDR(DDR1_PUB_DX8BDLR6)
#define DDR1_PUB_DX8LCDLR0 (0x3000 + (0x1AE << 2)) 	///../ucode/ddr3_reg.h:877
#define P_DDR1_PUB_DX8LCDLR0 		MMC_REG_ADDR(DDR1_PUB_DX8LCDLR0)
#define DDR1_PUB_DX8LCDLR1 (0x3000 + (0x1AF << 2)) 	///../ucode/ddr3_reg.h:878
#define P_DDR1_PUB_DX8LCDLR1 		MMC_REG_ADDR(DDR1_PUB_DX8LCDLR1)
#define DDR1_PUB_DX8LCDLR2 (0x3000 + (0x1B0 << 2)) 	///../ucode/ddr3_reg.h:879
#define P_DDR1_PUB_DX8LCDLR2 		MMC_REG_ADDR(DDR1_PUB_DX8LCDLR2)
#define DDR1_PUB_DX8MDLR (0x3000 + (0x1B1 << 2)) 	///../ucode/ddr3_reg.h:880
#define P_DDR1_PUB_DX8MDLR 		MMC_REG_ADDR(DDR1_PUB_DX8MDLR)
#define DDR1_PUB_DX8GTR (0x3000 + (0x1B2 << 2)) 	///../ucode/ddr3_reg.h:881
#define P_DDR1_PUB_DX8GTR 		MMC_REG_ADDR(DDR1_PUB_DX8GTR)
#define S_DMC_REG_BASE 0x6000
#define DMC_REQ_CTRL (S_DMC_REG_BASE + (0x00 << 2)) 	///../ucode/dmc_reg.h:10
#define P_DMC_REQ_CTRL 		MMC_REG_ADDR(DMC_REQ_CTRL)
#define DMC_SOFT_RST (S_DMC_REG_BASE + (0x01 << 2)) 	///../ucode/dmc_reg.h:23
#define P_DMC_SOFT_RST 		MMC_REG_ADDR(DMC_SOFT_RST)
#define DMC_SOFT_RST1 (S_DMC_REG_BASE + (0x02 << 2)) 	///../ucode/dmc_reg.h:24
#define P_DMC_SOFT_RST1 		MMC_REG_ADDR(DMC_SOFT_RST1)
#define DMC_RST_STS (S_DMC_REG_BASE + (0x03 << 2)) 	///../ucode/dmc_reg.h:25
#define P_DMC_RST_STS 		MMC_REG_ADDR(DMC_RST_STS)
#define DMC_RST_STS1 (S_DMC_REG_BASE + (0x04 << 2)) 	///../ucode/dmc_reg.h:26
#define P_DMC_RST_STS1 		MMC_REG_ADDR(DMC_RST_STS1)
#define DMC_VERSION (S_DMC_REG_BASE + (0x05 << 2)) 	///../ucode/dmc_reg.h:27
#define P_DMC_VERSION 		MMC_REG_ADDR(DMC_VERSION)
#define DMC_DDR_CTRL (S_DMC_REG_BASE + (0x10 << 2)) 	///../ucode/dmc_reg.h:30
#define P_DMC_DDR_CTRL 		MMC_REG_ADDR(DMC_DDR_CTRL)
#define DMC_DDR_CTRL1 (S_DMC_REG_BASE + (0x11 << 2)) 	///../ucode/dmc_reg.h:55
#define P_DMC_DDR_CTRL1 		MMC_REG_ADDR(DMC_DDR_CTRL1)
#define DC_CAV_LUT_DATAL (S_DMC_REG_BASE + (0x12 << 2)) 	///../ucode/dmc_reg.h:57
#define P_DC_CAV_LUT_DATAL 		MMC_REG_ADDR(DC_CAV_LUT_DATAL)
#define DC_CAV_LUT_DATAH (S_DMC_REG_BASE + (0x13 << 2)) 	///../ucode/dmc_reg.h:59
#define P_DC_CAV_LUT_DATAH 		MMC_REG_ADDR(DC_CAV_LUT_DATAH)
#define DC_CAV_LUT_ADDR (S_DMC_REG_BASE + (0x14 << 2)) 	///../ucode/dmc_reg.h:61
#define P_DC_CAV_LUT_ADDR 		MMC_REG_ADDR(DC_CAV_LUT_ADDR)
#define DC_CAV_LUT_RDATAL (S_DMC_REG_BASE + (0x15 << 2)) 	///../ucode/dmc_reg.h:64
#define P_DC_CAV_LUT_RDATAL 		MMC_REG_ADDR(DC_CAV_LUT_RDATAL)
#define DC_CAV_LUT_RDATAH (S_DMC_REG_BASE + (0x16 << 2)) 	///../ucode/dmc_reg.h:65
#define P_DC_CAV_LUT_RDATAH 		MMC_REG_ADDR(DC_CAV_LUT_RDATAH)
#define DMC_2ARB_CTRL (S_DMC_REG_BASE + (0x20 << 2)) 	///../ucode/dmc_reg.h:66
#define P_DMC_2ARB_CTRL 		MMC_REG_ADDR(DMC_2ARB_CTRL)
#define DMC_REFR_CTRL1 (S_DMC_REG_BASE + (0x23 << 2)) 	///../ucode/dmc_reg.h:68
#define P_DMC_REFR_CTRL1 		MMC_REG_ADDR(DMC_REFR_CTRL1)
#define DMC_REFR_CTRL2 (S_DMC_REG_BASE + (0x24 << 2)) 	///../ucode/dmc_reg.h:79
#define P_DMC_REFR_CTRL2 		MMC_REG_ADDR(DMC_REFR_CTRL2)
#define DMC_PARB_CTRL (S_DMC_REG_BASE + (0x25 << 2)) 	///../ucode/dmc_reg.h:85
#define P_DMC_PARB_CTRL 		MMC_REG_ADDR(DMC_PARB_CTRL)
#define DMC_MON_CTRL2 (S_DMC_REG_BASE + (0x26 << 2)) 	///../ucode/dmc_reg.h:92
#define P_DMC_MON_CTRL2 		MMC_REG_ADDR(DMC_MON_CTRL2)
#define DMC_MON_CTRL3 (S_DMC_REG_BASE + (0x27 << 2)) 	///../ucode/dmc_reg.h:98
#define P_DMC_MON_CTRL3 		MMC_REG_ADDR(DMC_MON_CTRL3)
#define DMC_MON_ALL_REQ_CNT (S_DMC_REG_BASE + (0x28 << 2)) 	///../ucode/dmc_reg.h:102
#define P_DMC_MON_ALL_REQ_CNT 		MMC_REG_ADDR(DMC_MON_ALL_REQ_CNT)
#define DMC_MON_ALL_GRANT_CNT (S_DMC_REG_BASE + (0x29 << 2)) 	///../ucode/dmc_reg.h:104
#define P_DMC_MON_ALL_GRANT_CNT 		MMC_REG_ADDR(DMC_MON_ALL_GRANT_CNT)
#define DMC_MON_ONE_GRANT_CNT (S_DMC_REG_BASE + (0x2a << 2)) 	///../ucode/dmc_reg.h:106
#define P_DMC_MON_ONE_GRANT_CNT 		MMC_REG_ADDR(DMC_MON_ONE_GRANT_CNT)
#define DMC_CLKG_CTRL0 (S_DMC_REG_BASE + (0x30 << 2)) 	///../ucode/dmc_reg.h:109
#define P_DMC_CLKG_CTRL0 		MMC_REG_ADDR(DMC_CLKG_CTRL0)
#define DMC_CLKG_CTRL1 (S_DMC_REG_BASE + (0x31 << 2)) 	///../ucode/dmc_reg.h:139
#define P_DMC_CLKG_CTRL1 		MMC_REG_ADDR(DMC_CLKG_CTRL1)
#define DMC_CHAN_STS (S_DMC_REG_BASE + (0x32 << 2)) 	///../ucode/dmc_reg.h:170
#define P_DMC_CHAN_STS 		MMC_REG_ADDR(DMC_CHAN_STS)
#define DMC_CMD_FILTER_CTRL1 (S_DMC_REG_BASE + (0x40 << 2)) 	///../ucode/dmc_reg.h:172
#define P_DMC_CMD_FILTER_CTRL1 		MMC_REG_ADDR(DMC_CMD_FILTER_CTRL1)
#define DMC_CMD_FILTER_CTRL2 (S_DMC_REG_BASE + (0x41 << 2)) 	///../ucode/dmc_reg.h:177
#define P_DMC_CMD_FILTER_CTRL2 		MMC_REG_ADDR(DMC_CMD_FILTER_CTRL2)
#define DMC_CMD_FILTER_CTRL3 (S_DMC_REG_BASE + (0x42 << 2)) 	///../ucode/dmc_reg.h:182
#define P_DMC_CMD_FILTER_CTRL3 		MMC_REG_ADDR(DMC_CMD_FILTER_CTRL3)
#define DMC_CMD_FILTER_CTRL4 (S_DMC_REG_BASE + (0x43 << 2)) 	///../ucode/dmc_reg.h:191
#define P_DMC_CMD_FILTER_CTRL4 		MMC_REG_ADDR(DMC_CMD_FILTER_CTRL4)
#define DMC_CMD_BUFFER_CTRL (S_DMC_REG_BASE + (0x44 << 2)) 	///../ucode/dmc_reg.h:197
#define P_DMC_CMD_BUFFER_CTRL 		MMC_REG_ADDR(DMC_CMD_BUFFER_CTRL)
#define DMC_AM0_CHAN_CTRL (S_DMC_REG_BASE + (0x60 << 2)) 	///../ucode/dmc_reg.h:203
#define P_DMC_AM0_CHAN_CTRL 		MMC_REG_ADDR(DMC_AM0_CHAN_CTRL)
#define DMC_AM0_HOLD_CTRL (S_DMC_REG_BASE + (0x61 << 2)) 	///../ucode/dmc_reg.h:204
#define P_DMC_AM0_HOLD_CTRL 		MMC_REG_ADDR(DMC_AM0_HOLD_CTRL)
#define DMC_AM0_QOS_INC (S_DMC_REG_BASE + (0x62 << 2)) 	///../ucode/dmc_reg.h:205
#define P_DMC_AM0_QOS_INC 		MMC_REG_ADDR(DMC_AM0_QOS_INC)
#define DMC_AM0_QOS_INCBK (S_DMC_REG_BASE + (0x63 << 2)) 	///../ucode/dmc_reg.h:206
#define P_DMC_AM0_QOS_INCBK 		MMC_REG_ADDR(DMC_AM0_QOS_INCBK)
#define DMC_AM0_QOS_DEC (S_DMC_REG_BASE + (0x64 << 2)) 	///../ucode/dmc_reg.h:207
#define P_DMC_AM0_QOS_DEC 		MMC_REG_ADDR(DMC_AM0_QOS_DEC)
#define DMC_AM0_QOS_DECBK (S_DMC_REG_BASE + (0x65 << 2)) 	///../ucode/dmc_reg.h:208
#define P_DMC_AM0_QOS_DECBK 		MMC_REG_ADDR(DMC_AM0_QOS_DECBK)
#define DMC_AM0_QOS_DIS (S_DMC_REG_BASE + (0x66 << 2)) 	///../ucode/dmc_reg.h:209
#define P_DMC_AM0_QOS_DIS 		MMC_REG_ADDR(DMC_AM0_QOS_DIS)
#define DMC_AM0_QOS_DISBK (S_DMC_REG_BASE + (0x67 << 2)) 	///../ucode/dmc_reg.h:210
#define P_DMC_AM0_QOS_DISBK 		MMC_REG_ADDR(DMC_AM0_QOS_DISBK)
#define DMC_AM0_QOS_CTRL0 (S_DMC_REG_BASE + (0x68 << 2)) 	///../ucode/dmc_reg.h:211
#define P_DMC_AM0_QOS_CTRL0 		MMC_REG_ADDR(DMC_AM0_QOS_CTRL0)
#define DMC_AM0_QOS_CTRL1 (S_DMC_REG_BASE + (0x69 << 2)) 	///../ucode/dmc_reg.h:212
#define P_DMC_AM0_QOS_CTRL1 		MMC_REG_ADDR(DMC_AM0_QOS_CTRL1)
#define DMC_AM1_CHAN_CTRL (S_DMC_REG_BASE + (0x6a << 2)) 	///../ucode/dmc_reg.h:214
#define P_DMC_AM1_CHAN_CTRL 		MMC_REG_ADDR(DMC_AM1_CHAN_CTRL)
#define DMC_AM1_HOLD_CTRL (S_DMC_REG_BASE + (0x6b << 2)) 	///../ucode/dmc_reg.h:215
#define P_DMC_AM1_HOLD_CTRL 		MMC_REG_ADDR(DMC_AM1_HOLD_CTRL)
#define DMC_AM1_QOS_INC (S_DMC_REG_BASE + (0x6c << 2)) 	///../ucode/dmc_reg.h:216
#define P_DMC_AM1_QOS_INC 		MMC_REG_ADDR(DMC_AM1_QOS_INC)
#define DMC_AM1_QOS_INCBK (S_DMC_REG_BASE + (0x6d << 2)) 	///../ucode/dmc_reg.h:217
#define P_DMC_AM1_QOS_INCBK 		MMC_REG_ADDR(DMC_AM1_QOS_INCBK)
#define DMC_AM1_QOS_DEC (S_DMC_REG_BASE + (0x6e << 2)) 	///../ucode/dmc_reg.h:218
#define P_DMC_AM1_QOS_DEC 		MMC_REG_ADDR(DMC_AM1_QOS_DEC)
#define DMC_AM1_QOS_DECBK (S_DMC_REG_BASE + (0x6f << 2)) 	///../ucode/dmc_reg.h:219
#define P_DMC_AM1_QOS_DECBK 		MMC_REG_ADDR(DMC_AM1_QOS_DECBK)
#define DMC_AM1_QOS_DIS (S_DMC_REG_BASE + (0x70 << 2)) 	///../ucode/dmc_reg.h:220
#define P_DMC_AM1_QOS_DIS 		MMC_REG_ADDR(DMC_AM1_QOS_DIS)
#define DMC_AM1_QOS_DISBK (S_DMC_REG_BASE + (0x71 << 2)) 	///../ucode/dmc_reg.h:221
#define P_DMC_AM1_QOS_DISBK 		MMC_REG_ADDR(DMC_AM1_QOS_DISBK)
#define DMC_AM1_QOS_CTRL0 (S_DMC_REG_BASE + (0x72 << 2)) 	///../ucode/dmc_reg.h:222
#define P_DMC_AM1_QOS_CTRL0 		MMC_REG_ADDR(DMC_AM1_QOS_CTRL0)
#define DMC_AM1_QOS_CTRL1 (S_DMC_REG_BASE + (0x73 << 2)) 	///../ucode/dmc_reg.h:223
#define P_DMC_AM1_QOS_CTRL1 		MMC_REG_ADDR(DMC_AM1_QOS_CTRL1)
#define DMC_AM2_CHAN_CTRL (S_DMC_REG_BASE + (0x74 << 2)) 	///../ucode/dmc_reg.h:225
#define P_DMC_AM2_CHAN_CTRL 		MMC_REG_ADDR(DMC_AM2_CHAN_CTRL)
#define DMC_AM2_HOLD_CTRL (S_DMC_REG_BASE + (0x75 << 2)) 	///../ucode/dmc_reg.h:226
#define P_DMC_AM2_HOLD_CTRL 		MMC_REG_ADDR(DMC_AM2_HOLD_CTRL)
#define DMC_AM2_QOS_INC (S_DMC_REG_BASE + (0x76 << 2)) 	///../ucode/dmc_reg.h:227
#define P_DMC_AM2_QOS_INC 		MMC_REG_ADDR(DMC_AM2_QOS_INC)
#define DMC_AM2_QOS_INCBK (S_DMC_REG_BASE + (0x77 << 2)) 	///../ucode/dmc_reg.h:228
#define P_DMC_AM2_QOS_INCBK 		MMC_REG_ADDR(DMC_AM2_QOS_INCBK)
#define DMC_AM2_QOS_DEC (S_DMC_REG_BASE + (0x78 << 2)) 	///../ucode/dmc_reg.h:229
#define P_DMC_AM2_QOS_DEC 		MMC_REG_ADDR(DMC_AM2_QOS_DEC)
#define DMC_AM2_QOS_DECBK (S_DMC_REG_BASE + (0x79 << 2)) 	///../ucode/dmc_reg.h:230
#define P_DMC_AM2_QOS_DECBK 		MMC_REG_ADDR(DMC_AM2_QOS_DECBK)
#define DMC_AM2_QOS_DIS (S_DMC_REG_BASE + (0x7a << 2)) 	///../ucode/dmc_reg.h:231
#define P_DMC_AM2_QOS_DIS 		MMC_REG_ADDR(DMC_AM2_QOS_DIS)
#define DMC_AM2_QOS_DISBK (S_DMC_REG_BASE + (0x7b << 2)) 	///../ucode/dmc_reg.h:232
#define P_DMC_AM2_QOS_DISBK 		MMC_REG_ADDR(DMC_AM2_QOS_DISBK)
#define DMC_AM2_QOS_CTRL0 (S_DMC_REG_BASE + (0x7c << 2)) 	///../ucode/dmc_reg.h:233
#define P_DMC_AM2_QOS_CTRL0 		MMC_REG_ADDR(DMC_AM2_QOS_CTRL0)
#define DMC_AM2_QOS_CTRL1 (S_DMC_REG_BASE + (0x7d << 2)) 	///../ucode/dmc_reg.h:234
#define P_DMC_AM2_QOS_CTRL1 		MMC_REG_ADDR(DMC_AM2_QOS_CTRL1)
#define DMC_AM3_CHAN_CTRL (S_DMC_REG_BASE + (0x7e << 2)) 	///../ucode/dmc_reg.h:236
#define P_DMC_AM3_CHAN_CTRL 		MMC_REG_ADDR(DMC_AM3_CHAN_CTRL)
#define DMC_AM3_HOLD_CTRL (S_DMC_REG_BASE + (0x7f << 2)) 	///../ucode/dmc_reg.h:237
#define P_DMC_AM3_HOLD_CTRL 		MMC_REG_ADDR(DMC_AM3_HOLD_CTRL)
#define DMC_AM3_QOS_INC (S_DMC_REG_BASE + (0x80 << 2)) 	///../ucode/dmc_reg.h:238
#define P_DMC_AM3_QOS_INC 		MMC_REG_ADDR(DMC_AM3_QOS_INC)
#define DMC_AM3_QOS_INCBK (S_DMC_REG_BASE + (0x81 << 2)) 	///../ucode/dmc_reg.h:239
#define P_DMC_AM3_QOS_INCBK 		MMC_REG_ADDR(DMC_AM3_QOS_INCBK)
#define DMC_AM3_QOS_DEC (S_DMC_REG_BASE + (0x82 << 2)) 	///../ucode/dmc_reg.h:240
#define P_DMC_AM3_QOS_DEC 		MMC_REG_ADDR(DMC_AM3_QOS_DEC)
#define DMC_AM3_QOS_DECBK (S_DMC_REG_BASE + (0x83 << 2)) 	///../ucode/dmc_reg.h:241
#define P_DMC_AM3_QOS_DECBK 		MMC_REG_ADDR(DMC_AM3_QOS_DECBK)
#define DMC_AM3_QOS_DIS (S_DMC_REG_BASE + (0x84 << 2)) 	///../ucode/dmc_reg.h:242
#define P_DMC_AM3_QOS_DIS 		MMC_REG_ADDR(DMC_AM3_QOS_DIS)
#define DMC_AM3_QOS_DISBK (S_DMC_REG_BASE + (0x85 << 2)) 	///../ucode/dmc_reg.h:243
#define P_DMC_AM3_QOS_DISBK 		MMC_REG_ADDR(DMC_AM3_QOS_DISBK)
#define DMC_AM3_QOS_CTRL0 (S_DMC_REG_BASE + (0x86 << 2)) 	///../ucode/dmc_reg.h:244
#define P_DMC_AM3_QOS_CTRL0 		MMC_REG_ADDR(DMC_AM3_QOS_CTRL0)
#define DMC_AM3_QOS_CTRL1 (S_DMC_REG_BASE + (0x87 << 2)) 	///../ucode/dmc_reg.h:245
#define P_DMC_AM3_QOS_CTRL1 		MMC_REG_ADDR(DMC_AM3_QOS_CTRL1)
#define DMC_AM4_CHAN_CTRL (S_DMC_REG_BASE + (0x88 << 2)) 	///../ucode/dmc_reg.h:247
#define P_DMC_AM4_CHAN_CTRL 		MMC_REG_ADDR(DMC_AM4_CHAN_CTRL)
#define DMC_AM4_HOLD_CTRL (S_DMC_REG_BASE + (0x89 << 2)) 	///../ucode/dmc_reg.h:248
#define P_DMC_AM4_HOLD_CTRL 		MMC_REG_ADDR(DMC_AM4_HOLD_CTRL)
#define DMC_AM4_QOS_INC (S_DMC_REG_BASE + (0x8a << 2)) 	///../ucode/dmc_reg.h:249
#define P_DMC_AM4_QOS_INC 		MMC_REG_ADDR(DMC_AM4_QOS_INC)
#define DMC_AM4_QOS_INCBK (S_DMC_REG_BASE + (0x8b << 2)) 	///../ucode/dmc_reg.h:250
#define P_DMC_AM4_QOS_INCBK 		MMC_REG_ADDR(DMC_AM4_QOS_INCBK)
#define DMC_AM4_QOS_DEC (S_DMC_REG_BASE + (0x8c << 2)) 	///../ucode/dmc_reg.h:251
#define P_DMC_AM4_QOS_DEC 		MMC_REG_ADDR(DMC_AM4_QOS_DEC)
#define DMC_AM4_QOS_DECBK (S_DMC_REG_BASE + (0x8d << 2)) 	///../ucode/dmc_reg.h:252
#define P_DMC_AM4_QOS_DECBK 		MMC_REG_ADDR(DMC_AM4_QOS_DECBK)
#define DMC_AM4_QOS_DIS (S_DMC_REG_BASE + (0x8e << 2)) 	///../ucode/dmc_reg.h:253
#define P_DMC_AM4_QOS_DIS 		MMC_REG_ADDR(DMC_AM4_QOS_DIS)
#define DMC_AM4_QOS_DISBK (S_DMC_REG_BASE + (0x8f << 2)) 	///../ucode/dmc_reg.h:254
#define P_DMC_AM4_QOS_DISBK 		MMC_REG_ADDR(DMC_AM4_QOS_DISBK)
#define DMC_AM4_QOS_CTRL0 (S_DMC_REG_BASE + (0x90 << 2)) 	///../ucode/dmc_reg.h:255
#define P_DMC_AM4_QOS_CTRL0 		MMC_REG_ADDR(DMC_AM4_QOS_CTRL0)
#define DMC_AM4_QOS_CTRL1 (S_DMC_REG_BASE + (0x91 << 2)) 	///../ucode/dmc_reg.h:256
#define P_DMC_AM4_QOS_CTRL1 		MMC_REG_ADDR(DMC_AM4_QOS_CTRL1)
#define DMC_AM5_CHAN_CTRL (S_DMC_REG_BASE + (0x92 << 2)) 	///../ucode/dmc_reg.h:258
#define P_DMC_AM5_CHAN_CTRL 		MMC_REG_ADDR(DMC_AM5_CHAN_CTRL)
#define DMC_AM5_HOLD_CTRL (S_DMC_REG_BASE + (0x93 << 2)) 	///../ucode/dmc_reg.h:259
#define P_DMC_AM5_HOLD_CTRL 		MMC_REG_ADDR(DMC_AM5_HOLD_CTRL)
#define DMC_AM5_QOS_INC (S_DMC_REG_BASE + (0x94 << 2)) 	///../ucode/dmc_reg.h:260
#define P_DMC_AM5_QOS_INC 		MMC_REG_ADDR(DMC_AM5_QOS_INC)
#define DMC_AM5_QOS_INCBK (S_DMC_REG_BASE + (0x95 << 2)) 	///../ucode/dmc_reg.h:261
#define P_DMC_AM5_QOS_INCBK 		MMC_REG_ADDR(DMC_AM5_QOS_INCBK)
#define DMC_AM5_QOS_DEC (S_DMC_REG_BASE + (0x96 << 2)) 	///../ucode/dmc_reg.h:262
#define P_DMC_AM5_QOS_DEC 		MMC_REG_ADDR(DMC_AM5_QOS_DEC)
#define DMC_AM5_QOS_DECBK (S_DMC_REG_BASE + (0x97 << 2)) 	///../ucode/dmc_reg.h:263
#define P_DMC_AM5_QOS_DECBK 		MMC_REG_ADDR(DMC_AM5_QOS_DECBK)
#define DMC_AM5_QOS_DIS (S_DMC_REG_BASE + (0x98 << 2)) 	///../ucode/dmc_reg.h:264
#define P_DMC_AM5_QOS_DIS 		MMC_REG_ADDR(DMC_AM5_QOS_DIS)
#define DMC_AM5_QOS_DISBK (S_DMC_REG_BASE + (0x99 << 2)) 	///../ucode/dmc_reg.h:265
#define P_DMC_AM5_QOS_DISBK 		MMC_REG_ADDR(DMC_AM5_QOS_DISBK)
#define DMC_AM5_QOS_CTRL0 (S_DMC_REG_BASE + (0x9a << 2)) 	///../ucode/dmc_reg.h:266
#define P_DMC_AM5_QOS_CTRL0 		MMC_REG_ADDR(DMC_AM5_QOS_CTRL0)
#define DMC_AM5_QOS_CTRL1 (S_DMC_REG_BASE + (0x9b << 2)) 	///../ucode/dmc_reg.h:267
#define P_DMC_AM5_QOS_CTRL1 		MMC_REG_ADDR(DMC_AM5_QOS_CTRL1)
#define DMC_AM6_CHAN_CTRL (S_DMC_REG_BASE + (0x9c << 2)) 	///../ucode/dmc_reg.h:269
#define P_DMC_AM6_CHAN_CTRL 		MMC_REG_ADDR(DMC_AM6_CHAN_CTRL)
#define DMC_AM6_HOLD_CTRL (S_DMC_REG_BASE + (0x9d << 2)) 	///../ucode/dmc_reg.h:270
#define P_DMC_AM6_HOLD_CTRL 		MMC_REG_ADDR(DMC_AM6_HOLD_CTRL)
#define DMC_AM6_QOS_INC (S_DMC_REG_BASE + (0x9e << 2)) 	///../ucode/dmc_reg.h:271
#define P_DMC_AM6_QOS_INC 		MMC_REG_ADDR(DMC_AM6_QOS_INC)
#define DMC_AM6_QOS_INCBK (S_DMC_REG_BASE + (0x9f << 2)) 	///../ucode/dmc_reg.h:272
#define P_DMC_AM6_QOS_INCBK 		MMC_REG_ADDR(DMC_AM6_QOS_INCBK)
#define DMC_AM6_QOS_DEC (S_DMC_REG_BASE + (0xa0 << 2)) 	///../ucode/dmc_reg.h:273
#define P_DMC_AM6_QOS_DEC 		MMC_REG_ADDR(DMC_AM6_QOS_DEC)
#define DMC_AM6_QOS_DECBK (S_DMC_REG_BASE + (0xa1 << 2)) 	///../ucode/dmc_reg.h:274
#define P_DMC_AM6_QOS_DECBK 		MMC_REG_ADDR(DMC_AM6_QOS_DECBK)
#define DMC_AM6_QOS_DIS (S_DMC_REG_BASE + (0xa2 << 2)) 	///../ucode/dmc_reg.h:275
#define P_DMC_AM6_QOS_DIS 		MMC_REG_ADDR(DMC_AM6_QOS_DIS)
#define DMC_AM6_QOS_DISBK (S_DMC_REG_BASE + (0xa3 << 2)) 	///../ucode/dmc_reg.h:276
#define P_DMC_AM6_QOS_DISBK 		MMC_REG_ADDR(DMC_AM6_QOS_DISBK)
#define DMC_AM6_QOS_CTRL0 (S_DMC_REG_BASE + (0xa4 << 2)) 	///../ucode/dmc_reg.h:277
#define P_DMC_AM6_QOS_CTRL0 		MMC_REG_ADDR(DMC_AM6_QOS_CTRL0)
#define DMC_AM6_QOS_CTRL1 (S_DMC_REG_BASE + (0xa5 << 2)) 	///../ucode/dmc_reg.h:278
#define P_DMC_AM6_QOS_CTRL1 		MMC_REG_ADDR(DMC_AM6_QOS_CTRL1)
#define DMC_AM7_CHAN_CTRL (S_DMC_REG_BASE + (0xa6 << 2)) 	///../ucode/dmc_reg.h:280
#define P_DMC_AM7_CHAN_CTRL 		MMC_REG_ADDR(DMC_AM7_CHAN_CTRL)
#define DMC_AM7_HOLD_CTRL (S_DMC_REG_BASE + (0xa7 << 2)) 	///../ucode/dmc_reg.h:281
#define P_DMC_AM7_HOLD_CTRL 		MMC_REG_ADDR(DMC_AM7_HOLD_CTRL)
#define DMC_AM7_QOS_INC (S_DMC_REG_BASE + (0xa8 << 2)) 	///../ucode/dmc_reg.h:282
#define P_DMC_AM7_QOS_INC 		MMC_REG_ADDR(DMC_AM7_QOS_INC)
#define DMC_AM7_QOS_INCBK (S_DMC_REG_BASE + (0xa9 << 2)) 	///../ucode/dmc_reg.h:283
#define P_DMC_AM7_QOS_INCBK 		MMC_REG_ADDR(DMC_AM7_QOS_INCBK)
#define DMC_AM7_QOS_DEC (S_DMC_REG_BASE + (0xaa << 2)) 	///../ucode/dmc_reg.h:284
#define P_DMC_AM7_QOS_DEC 		MMC_REG_ADDR(DMC_AM7_QOS_DEC)
#define DMC_AM7_QOS_DECBK (S_DMC_REG_BASE + (0xab << 2)) 	///../ucode/dmc_reg.h:285
#define P_DMC_AM7_QOS_DECBK 		MMC_REG_ADDR(DMC_AM7_QOS_DECBK)
#define DMC_AM7_QOS_DIS (S_DMC_REG_BASE + (0xac << 2)) 	///../ucode/dmc_reg.h:286
#define P_DMC_AM7_QOS_DIS 		MMC_REG_ADDR(DMC_AM7_QOS_DIS)
#define DMC_AM7_QOS_DISBK (S_DMC_REG_BASE + (0xad << 2)) 	///../ucode/dmc_reg.h:287
#define P_DMC_AM7_QOS_DISBK 		MMC_REG_ADDR(DMC_AM7_QOS_DISBK)
#define DMC_AM7_QOS_CTRL0 (S_DMC_REG_BASE + (0xae << 2)) 	///../ucode/dmc_reg.h:288
#define P_DMC_AM7_QOS_CTRL0 		MMC_REG_ADDR(DMC_AM7_QOS_CTRL0)
#define DMC_AM7_QOS_CTRL1 (S_DMC_REG_BASE + (0xaf << 2)) 	///../ucode/dmc_reg.h:289
#define P_DMC_AM7_QOS_CTRL1 		MMC_REG_ADDR(DMC_AM7_QOS_CTRL1)
#define DMC_AXI0_CHAN_CTRL (S_DMC_REG_BASE + (0xb0 << 2)) 	///../ucode/dmc_reg.h:291
#define P_DMC_AXI0_CHAN_CTRL 		MMC_REG_ADDR(DMC_AXI0_CHAN_CTRL)
#define DMC_AXI0_HOLD_CTRL (S_DMC_REG_BASE + (0xb1 << 2)) 	///../ucode/dmc_reg.h:292
#define P_DMC_AXI0_HOLD_CTRL 		MMC_REG_ADDR(DMC_AXI0_HOLD_CTRL)
#define DMC_AXI0_QOS_INC (S_DMC_REG_BASE + (0xb2 << 2)) 	///../ucode/dmc_reg.h:293
#define P_DMC_AXI0_QOS_INC 		MMC_REG_ADDR(DMC_AXI0_QOS_INC)
#define DMC_AXI0_QOS_INCBK (S_DMC_REG_BASE + (0xb3 << 2)) 	///../ucode/dmc_reg.h:294
#define P_DMC_AXI0_QOS_INCBK 		MMC_REG_ADDR(DMC_AXI0_QOS_INCBK)
#define DMC_AXI0_QOS_DEC (S_DMC_REG_BASE + (0xb4 << 2)) 	///../ucode/dmc_reg.h:295
#define P_DMC_AXI0_QOS_DEC 		MMC_REG_ADDR(DMC_AXI0_QOS_DEC)
#define DMC_AXI0_QOS_DECBK (S_DMC_REG_BASE + (0xb5 << 2)) 	///../ucode/dmc_reg.h:296
#define P_DMC_AXI0_QOS_DECBK 		MMC_REG_ADDR(DMC_AXI0_QOS_DECBK)
#define DMC_AXI0_QOS_DIS (S_DMC_REG_BASE + (0xb6 << 2)) 	///../ucode/dmc_reg.h:297
#define P_DMC_AXI0_QOS_DIS 		MMC_REG_ADDR(DMC_AXI0_QOS_DIS)
#define DMC_AXI0_QOS_DISBK (S_DMC_REG_BASE + (0xb7 << 2)) 	///../ucode/dmc_reg.h:298
#define P_DMC_AXI0_QOS_DISBK 		MMC_REG_ADDR(DMC_AXI0_QOS_DISBK)
#define DMC_AXI0_QOS_CTRL0 (S_DMC_REG_BASE + (0xb8 << 2)) 	///../ucode/dmc_reg.h:299
#define P_DMC_AXI0_QOS_CTRL0 		MMC_REG_ADDR(DMC_AXI0_QOS_CTRL0)
#define DMC_AXI0_QOS_CTRL1 (S_DMC_REG_BASE + (0xb9 << 2)) 	///../ucode/dmc_reg.h:300
#define P_DMC_AXI0_QOS_CTRL1 		MMC_REG_ADDR(DMC_AXI0_QOS_CTRL1)
#define DMC_AXI1_CHAN_CTRL (S_DMC_REG_BASE + (0xba << 2)) 	///../ucode/dmc_reg.h:302
#define P_DMC_AXI1_CHAN_CTRL 		MMC_REG_ADDR(DMC_AXI1_CHAN_CTRL)
#define DMC_AXI1_HOLD_CTRL (S_DMC_REG_BASE + (0xbb << 2)) 	///../ucode/dmc_reg.h:303
#define P_DMC_AXI1_HOLD_CTRL 		MMC_REG_ADDR(DMC_AXI1_HOLD_CTRL)
#define DMC_AXI1_QOS_INC (S_DMC_REG_BASE + (0xbc << 2)) 	///../ucode/dmc_reg.h:304
#define P_DMC_AXI1_QOS_INC 		MMC_REG_ADDR(DMC_AXI1_QOS_INC)
#define DMC_AXI1_QOS_INCBK (S_DMC_REG_BASE + (0xbd << 2)) 	///../ucode/dmc_reg.h:305
#define P_DMC_AXI1_QOS_INCBK 		MMC_REG_ADDR(DMC_AXI1_QOS_INCBK)
#define DMC_AXI1_QOS_DEC (S_DMC_REG_BASE + (0xbe << 2)) 	///../ucode/dmc_reg.h:306
#define P_DMC_AXI1_QOS_DEC 		MMC_REG_ADDR(DMC_AXI1_QOS_DEC)
#define DMC_AXI1_QOS_DECBK (S_DMC_REG_BASE + (0xbf << 2)) 	///../ucode/dmc_reg.h:307
#define P_DMC_AXI1_QOS_DECBK 		MMC_REG_ADDR(DMC_AXI1_QOS_DECBK)
#define DMC_AXI1_QOS_DIS (S_DMC_REG_BASE + (0xc0 << 2)) 	///../ucode/dmc_reg.h:308
#define P_DMC_AXI1_QOS_DIS 		MMC_REG_ADDR(DMC_AXI1_QOS_DIS)
#define DMC_AXI1_QOS_DISBK (S_DMC_REG_BASE + (0xc1 << 2)) 	///../ucode/dmc_reg.h:309
#define P_DMC_AXI1_QOS_DISBK 		MMC_REG_ADDR(DMC_AXI1_QOS_DISBK)
#define DMC_AXI1_QOS_CTRL0 (S_DMC_REG_BASE + (0xc2 << 2)) 	///../ucode/dmc_reg.h:310
#define P_DMC_AXI1_QOS_CTRL0 		MMC_REG_ADDR(DMC_AXI1_QOS_CTRL0)
#define DMC_AXI1_QOS_CTRL1 (S_DMC_REG_BASE + (0xc3 << 2)) 	///../ucode/dmc_reg.h:311
#define P_DMC_AXI1_QOS_CTRL1 		MMC_REG_ADDR(DMC_AXI1_QOS_CTRL1)
#define DMC_AXI2_QOS_INC (S_DMC_REG_BASE + (0xc6 << 2)) 	///../ucode/dmc_reg.h:315
#define P_DMC_AXI2_QOS_INC 		MMC_REG_ADDR(DMC_AXI2_QOS_INC)
#define DMC_AXI2_QOS_INCBK (S_DMC_REG_BASE + (0xc7 << 2)) 	///../ucode/dmc_reg.h:316
#define P_DMC_AXI2_QOS_INCBK 		MMC_REG_ADDR(DMC_AXI2_QOS_INCBK)
#define DMC_AXI2_QOS_DEC (S_DMC_REG_BASE + (0xc8 << 2)) 	///../ucode/dmc_reg.h:317
#define P_DMC_AXI2_QOS_DEC 		MMC_REG_ADDR(DMC_AXI2_QOS_DEC)
#define DMC_AXI2_QOS_DECBK (S_DMC_REG_BASE + (0xc9 << 2)) 	///../ucode/dmc_reg.h:318
#define P_DMC_AXI2_QOS_DECBK 		MMC_REG_ADDR(DMC_AXI2_QOS_DECBK)
#define DMC_AXI2_QOS_DIS (S_DMC_REG_BASE + (0xca << 2)) 	///../ucode/dmc_reg.h:319
#define P_DMC_AXI2_QOS_DIS 		MMC_REG_ADDR(DMC_AXI2_QOS_DIS)
#define DMC_AXI2_QOS_DISBK (S_DMC_REG_BASE + (0xcb << 2)) 	///../ucode/dmc_reg.h:320
#define P_DMC_AXI2_QOS_DISBK 		MMC_REG_ADDR(DMC_AXI2_QOS_DISBK)
#define DMC_AXI2_QOS_CTRL0 (S_DMC_REG_BASE + (0xcc << 2)) 	///../ucode/dmc_reg.h:321
#define P_DMC_AXI2_QOS_CTRL0 		MMC_REG_ADDR(DMC_AXI2_QOS_CTRL0)
#define DMC_AXI2_QOS_CTRL1 (S_DMC_REG_BASE + (0xcd << 2)) 	///../ucode/dmc_reg.h:322
#define P_DMC_AXI2_QOS_CTRL1 		MMC_REG_ADDR(DMC_AXI2_QOS_CTRL1)
#define DMC_AXI3_CHAN_CTRL (S_DMC_REG_BASE + (0xce << 2)) 	///../ucode/dmc_reg.h:324
#define P_DMC_AXI3_CHAN_CTRL 		MMC_REG_ADDR(DMC_AXI3_CHAN_CTRL)
#define DMC_AXI3_HOLD_CTRL (S_DMC_REG_BASE + (0xcf << 2)) 	///../ucode/dmc_reg.h:325
#define P_DMC_AXI3_HOLD_CTRL 		MMC_REG_ADDR(DMC_AXI3_HOLD_CTRL)
#define DMC_AXI3_QOS_INC (S_DMC_REG_BASE + (0xd0 << 2)) 	///../ucode/dmc_reg.h:326
#define P_DMC_AXI3_QOS_INC 		MMC_REG_ADDR(DMC_AXI3_QOS_INC)
#define DMC_AXI3_QOS_INCBK (S_DMC_REG_BASE + (0xd1 << 2)) 	///../ucode/dmc_reg.h:327
#define P_DMC_AXI3_QOS_INCBK 		MMC_REG_ADDR(DMC_AXI3_QOS_INCBK)
#define DMC_AXI3_QOS_DEC (S_DMC_REG_BASE + (0xd2 << 2)) 	///../ucode/dmc_reg.h:328
#define P_DMC_AXI3_QOS_DEC 		MMC_REG_ADDR(DMC_AXI3_QOS_DEC)
#define DMC_AXI3_QOS_DECBK (S_DMC_REG_BASE + (0xd3 << 2)) 	///../ucode/dmc_reg.h:329
#define P_DMC_AXI3_QOS_DECBK 		MMC_REG_ADDR(DMC_AXI3_QOS_DECBK)
#define DMC_AXI3_QOS_DIS (S_DMC_REG_BASE + (0xd4 << 2)) 	///../ucode/dmc_reg.h:330
#define P_DMC_AXI3_QOS_DIS 		MMC_REG_ADDR(DMC_AXI3_QOS_DIS)
#define DMC_AXI3_QOS_DISBK (S_DMC_REG_BASE + (0xd5 << 2)) 	///../ucode/dmc_reg.h:331
#define P_DMC_AXI3_QOS_DISBK 		MMC_REG_ADDR(DMC_AXI3_QOS_DISBK)
#define DMC_AXI3_QOS_CTRL0 (S_DMC_REG_BASE + (0xd6 << 2)) 	///../ucode/dmc_reg.h:332
#define P_DMC_AXI3_QOS_CTRL0 		MMC_REG_ADDR(DMC_AXI3_QOS_CTRL0)
#define DMC_AXI3_QOS_CTRL1 (S_DMC_REG_BASE + (0xd7 << 2)) 	///../ucode/dmc_reg.h:333
#define P_DMC_AXI3_QOS_CTRL1 		MMC_REG_ADDR(DMC_AXI3_QOS_CTRL1)
#define DMC_AXI4_CHAN_CTRL (S_DMC_REG_BASE + (0xd8 << 2)) 	///../ucode/dmc_reg.h:335
#define P_DMC_AXI4_CHAN_CTRL 		MMC_REG_ADDR(DMC_AXI4_CHAN_CTRL)
#define DMC_AXI4_HOLD_CTRL (S_DMC_REG_BASE + (0xd9 << 2)) 	///../ucode/dmc_reg.h:336
#define P_DMC_AXI4_HOLD_CTRL 		MMC_REG_ADDR(DMC_AXI4_HOLD_CTRL)
#define DMC_AXI4_QOS_INC (S_DMC_REG_BASE + (0xda << 2)) 	///../ucode/dmc_reg.h:337
#define P_DMC_AXI4_QOS_INC 		MMC_REG_ADDR(DMC_AXI4_QOS_INC)
#define DMC_AXI4_QOS_INCBK (S_DMC_REG_BASE + (0xdb << 2)) 	///../ucode/dmc_reg.h:338
#define P_DMC_AXI4_QOS_INCBK 		MMC_REG_ADDR(DMC_AXI4_QOS_INCBK)
#define DMC_AXI4_QOS_DEC (S_DMC_REG_BASE + (0xdc << 2)) 	///../ucode/dmc_reg.h:339
#define P_DMC_AXI4_QOS_DEC 		MMC_REG_ADDR(DMC_AXI4_QOS_DEC)
#define DMC_AXI4_QOS_DECBK (S_DMC_REG_BASE + (0xdd << 2)) 	///../ucode/dmc_reg.h:340
#define P_DMC_AXI4_QOS_DECBK 		MMC_REG_ADDR(DMC_AXI4_QOS_DECBK)
#define DMC_AXI4_QOS_DIS (S_DMC_REG_BASE + (0xde << 2)) 	///../ucode/dmc_reg.h:341
#define P_DMC_AXI4_QOS_DIS 		MMC_REG_ADDR(DMC_AXI4_QOS_DIS)
#define DMC_AXI4_QOS_DISBK (S_DMC_REG_BASE + (0xdf << 2)) 	///../ucode/dmc_reg.h:342
#define P_DMC_AXI4_QOS_DISBK 		MMC_REG_ADDR(DMC_AXI4_QOS_DISBK)
#define DMC_AXI4_QOS_CTRL0 (S_DMC_REG_BASE + (0xe0 << 2)) 	///../ucode/dmc_reg.h:343
#define P_DMC_AXI4_QOS_CTRL0 		MMC_REG_ADDR(DMC_AXI4_QOS_CTRL0)
#define DMC_AXI4_QOS_CTRL1 (S_DMC_REG_BASE + (0xe1 << 2)) 	///../ucode/dmc_reg.h:344
#define P_DMC_AXI4_QOS_CTRL1 		MMC_REG_ADDR(DMC_AXI4_QOS_CTRL1)
#define DMC_AXI5_CHAN_CTRL (S_DMC_REG_BASE + (0xe2 << 2)) 	///../ucode/dmc_reg.h:346
#define P_DMC_AXI5_CHAN_CTRL 		MMC_REG_ADDR(DMC_AXI5_CHAN_CTRL)
#define DMC_AXI5_HOLD_CTRL (S_DMC_REG_BASE + (0xe3 << 2)) 	///../ucode/dmc_reg.h:347
#define P_DMC_AXI5_HOLD_CTRL 		MMC_REG_ADDR(DMC_AXI5_HOLD_CTRL)
#define DMC_AXI5_QOS_INC (S_DMC_REG_BASE + (0xe4 << 2)) 	///../ucode/dmc_reg.h:348
#define P_DMC_AXI5_QOS_INC 		MMC_REG_ADDR(DMC_AXI5_QOS_INC)
#define DMC_AXI5_QOS_INCBK (S_DMC_REG_BASE + (0xe5 << 2)) 	///../ucode/dmc_reg.h:349
#define P_DMC_AXI5_QOS_INCBK 		MMC_REG_ADDR(DMC_AXI5_QOS_INCBK)
#define DMC_AXI5_QOS_DEC (S_DMC_REG_BASE + (0xe6 << 2)) 	///../ucode/dmc_reg.h:350
#define P_DMC_AXI5_QOS_DEC 		MMC_REG_ADDR(DMC_AXI5_QOS_DEC)
#define DMC_AXI5_QOS_DECBK (S_DMC_REG_BASE + (0xe7 << 2)) 	///../ucode/dmc_reg.h:351
#define P_DMC_AXI5_QOS_DECBK 		MMC_REG_ADDR(DMC_AXI5_QOS_DECBK)
#define DMC_AXI5_QOS_DIS (S_DMC_REG_BASE + (0xe8 << 2)) 	///../ucode/dmc_reg.h:352
#define P_DMC_AXI5_QOS_DIS 		MMC_REG_ADDR(DMC_AXI5_QOS_DIS)
#define DMC_AXI5_QOS_DISBK (S_DMC_REG_BASE + (0xe9 << 2)) 	///../ucode/dmc_reg.h:353
#define P_DMC_AXI5_QOS_DISBK 		MMC_REG_ADDR(DMC_AXI5_QOS_DISBK)
#define DMC_AXI5_QOS_CTRL0 (S_DMC_REG_BASE + (0xea << 2)) 	///../ucode/dmc_reg.h:354
#define P_DMC_AXI5_QOS_CTRL0 		MMC_REG_ADDR(DMC_AXI5_QOS_CTRL0)
#define DMC_AXI5_QOS_CTRL1 (S_DMC_REG_BASE + (0xeb << 2)) 	///../ucode/dmc_reg.h:355
#define P_DMC_AXI5_QOS_CTRL1 		MMC_REG_ADDR(DMC_AXI5_QOS_CTRL1)
#define DMC_AXI6_CHAN_CTRL (S_DMC_REG_BASE + (0xec << 2)) 	///../ucode/dmc_reg.h:357
#define P_DMC_AXI6_CHAN_CTRL 		MMC_REG_ADDR(DMC_AXI6_CHAN_CTRL)
#define DMC_AXI6_HOLD_CTRL (S_DMC_REG_BASE + (0xed << 2)) 	///../ucode/dmc_reg.h:358
#define P_DMC_AXI6_HOLD_CTRL 		MMC_REG_ADDR(DMC_AXI6_HOLD_CTRL)
#define DMC_AXI6_QOS_INC (S_DMC_REG_BASE + (0xee << 2)) 	///../ucode/dmc_reg.h:359
#define P_DMC_AXI6_QOS_INC 		MMC_REG_ADDR(DMC_AXI6_QOS_INC)
#define DMC_AXI6_QOS_INCBK (S_DMC_REG_BASE + (0xef << 2)) 	///../ucode/dmc_reg.h:360
#define P_DMC_AXI6_QOS_INCBK 		MMC_REG_ADDR(DMC_AXI6_QOS_INCBK)
#define DMC_AXI6_QOS_DEC (S_DMC_REG_BASE + (0xf0 << 2)) 	///../ucode/dmc_reg.h:361
#define P_DMC_AXI6_QOS_DEC 		MMC_REG_ADDR(DMC_AXI6_QOS_DEC)
#define DMC_AXI6_QOS_DECBK (S_DMC_REG_BASE + (0xf1 << 2)) 	///../ucode/dmc_reg.h:362
#define P_DMC_AXI6_QOS_DECBK 		MMC_REG_ADDR(DMC_AXI6_QOS_DECBK)
#define DMC_AXI6_QOS_DIS (S_DMC_REG_BASE + (0xf2 << 2)) 	///../ucode/dmc_reg.h:363
#define P_DMC_AXI6_QOS_DIS 		MMC_REG_ADDR(DMC_AXI6_QOS_DIS)
#define DMC_AXI6_QOS_DISBK (S_DMC_REG_BASE + (0xf3 << 2)) 	///../ucode/dmc_reg.h:364
#define P_DMC_AXI6_QOS_DISBK 		MMC_REG_ADDR(DMC_AXI6_QOS_DISBK)
#define DMC_AXI6_QOS_CTRL0 (S_DMC_REG_BASE + (0xf4 << 2)) 	///../ucode/dmc_reg.h:365
#define P_DMC_AXI6_QOS_CTRL0 		MMC_REG_ADDR(DMC_AXI6_QOS_CTRL0)
#define DMC_AXI6_QOS_CTRL1 (S_DMC_REG_BASE + (0xf5 << 2)) 	///../ucode/dmc_reg.h:366
#define P_DMC_AXI6_QOS_CTRL1 		MMC_REG_ADDR(DMC_AXI6_QOS_CTRL1)
#define DMC_AXI7_CHAN_CTRL (S_DMC_REG_BASE + (0xf6 << 2)) 	///../ucode/dmc_reg.h:368
#define P_DMC_AXI7_CHAN_CTRL 		MMC_REG_ADDR(DMC_AXI7_CHAN_CTRL)
#define DMC_AXI7_HOLD_CTRL (S_DMC_REG_BASE + (0xf7 << 2)) 	///../ucode/dmc_reg.h:369
#define P_DMC_AXI7_HOLD_CTRL 		MMC_REG_ADDR(DMC_AXI7_HOLD_CTRL)
#define DMC_AXI7_QOS_INC (S_DMC_REG_BASE + (0xf8 << 2)) 	///../ucode/dmc_reg.h:370
#define P_DMC_AXI7_QOS_INC 		MMC_REG_ADDR(DMC_AXI7_QOS_INC)
#define DMC_AXI7_QOS_INCBK (S_DMC_REG_BASE + (0xf9 << 2)) 	///../ucode/dmc_reg.h:371
#define P_DMC_AXI7_QOS_INCBK 		MMC_REG_ADDR(DMC_AXI7_QOS_INCBK)
#define DMC_AXI7_QOS_DEC (S_DMC_REG_BASE + (0xfa << 2)) 	///../ucode/dmc_reg.h:372
#define P_DMC_AXI7_QOS_DEC 		MMC_REG_ADDR(DMC_AXI7_QOS_DEC)
#define DMC_AXI7_QOS_DECBK (S_DMC_REG_BASE + (0xfb << 2)) 	///../ucode/dmc_reg.h:373
#define P_DMC_AXI7_QOS_DECBK 		MMC_REG_ADDR(DMC_AXI7_QOS_DECBK)
#define DMC_AXI7_QOS_DIS (S_DMC_REG_BASE + (0xfc << 2)) 	///../ucode/dmc_reg.h:374
#define P_DMC_AXI7_QOS_DIS 		MMC_REG_ADDR(DMC_AXI7_QOS_DIS)
#define DMC_AXI7_QOS_DISBK (S_DMC_REG_BASE + (0xfd << 2)) 	///../ucode/dmc_reg.h:375
#define P_DMC_AXI7_QOS_DISBK 		MMC_REG_ADDR(DMC_AXI7_QOS_DISBK)
#define DMC_AXI7_QOS_CTRL0 (S_DMC_REG_BASE + (0xfe << 2)) 	///../ucode/dmc_reg.h:376
#define P_DMC_AXI7_QOS_CTRL0 		MMC_REG_ADDR(DMC_AXI7_QOS_CTRL0)
#define DMC_AXI7_QOS_CTRL1 (S_DMC_REG_BASE + (0xff << 2)) 	///../ucode/dmc_reg.h:377
#define P_DMC_AXI7_QOS_CTRL1 		MMC_REG_ADDR(DMC_AXI7_QOS_CTRL1)
#define STB_VERSION 0x1600 	///../ucode/c_stb_define.h:71
#define P_STB_VERSION 		CBUS_REG_ADDR(STB_VERSION)
#define STB_VERSION_2 0x1650 	///../ucode/c_stb_define.h:72
#define P_STB_VERSION_2 		CBUS_REG_ADDR(STB_VERSION_2)
#define STB_VERSION_3 0x16a0 	///../ucode/c_stb_define.h:73
#define P_STB_VERSION_3 		CBUS_REG_ADDR(STB_VERSION_3)
#define STB_TEST_REG 0x1601 	///../ucode/c_stb_define.h:74
#define P_STB_TEST_REG 		CBUS_REG_ADDR(STB_TEST_REG)
#define STB_TEST_REG_2 0x1651 	///../ucode/c_stb_define.h:75
#define P_STB_TEST_REG_2 		CBUS_REG_ADDR(STB_TEST_REG_2)
#define STB_TEST_REG_3 0x16a1 	///../ucode/c_stb_define.h:76
#define P_STB_TEST_REG_3 		CBUS_REG_ADDR(STB_TEST_REG_3)
#define FEC_INPUT_CONTROL 0x1602 	///../ucode/c_stb_define.h:84
#define P_FEC_INPUT_CONTROL 		CBUS_REG_ADDR(FEC_INPUT_CONTROL)
#define FEC_INPUT_CONTROL_2 0x1652 	///../ucode/c_stb_define.h:85
#define P_FEC_INPUT_CONTROL_2 		CBUS_REG_ADDR(FEC_INPUT_CONTROL_2)
#define FEC_INPUT_CONTROL_3 0x16a2 	///../ucode/c_stb_define.h:86
#define P_FEC_INPUT_CONTROL_3 		CBUS_REG_ADDR(FEC_INPUT_CONTROL_3)
#define FEC_INPUT_DATA 0x1603 	///../ucode/c_stb_define.h:87
#define P_FEC_INPUT_DATA 		CBUS_REG_ADDR(FEC_INPUT_DATA)
#define FEC_INPUT_DATA_2 0x1653 	///../ucode/c_stb_define.h:88
#define P_FEC_INPUT_DATA_2 		CBUS_REG_ADDR(FEC_INPUT_DATA_2)
#define FEC_INPUT_DATA_3 0x16a3 	///../ucode/c_stb_define.h:89
#define P_FEC_INPUT_DATA_3 		CBUS_REG_ADDR(FEC_INPUT_DATA_3)
#define DEMUX_CONTROL 0x1604 	///../ucode/c_stb_define.h:115
#define P_DEMUX_CONTROL 		CBUS_REG_ADDR(DEMUX_CONTROL)
#define DEMUX_CONTROL_2 0x1654 	///../ucode/c_stb_define.h:116
#define P_DEMUX_CONTROL_2 		CBUS_REG_ADDR(DEMUX_CONTROL_2)
#define DEMUX_CONTROL_3 0x16a4 	///../ucode/c_stb_define.h:117
#define P_DEMUX_CONTROL_3 		CBUS_REG_ADDR(DEMUX_CONTROL_3)
#define FEC_SYNC_BYTE 0x1605 	///../ucode/c_stb_define.h:120
#define P_FEC_SYNC_BYTE 		CBUS_REG_ADDR(FEC_SYNC_BYTE)
#define FEC_SYNC_BYTE_2 0x1655 	///../ucode/c_stb_define.h:121
#define P_FEC_SYNC_BYTE_2 		CBUS_REG_ADDR(FEC_SYNC_BYTE_2)
#define FEC_SYNC_BYTE_3 0x16a5 	///../ucode/c_stb_define.h:122
#define P_FEC_SYNC_BYTE_3 		CBUS_REG_ADDR(FEC_SYNC_BYTE_3)
#define FM_WR_DATA 0x1606 	///../ucode/c_stb_define.h:125
#define P_FM_WR_DATA 		CBUS_REG_ADDR(FM_WR_DATA)
#define FM_WR_DATA_2 0x1656 	///../ucode/c_stb_define.h:126
#define P_FM_WR_DATA_2 		CBUS_REG_ADDR(FM_WR_DATA_2)
#define FM_WR_DATA_3 0x16a6 	///../ucode/c_stb_define.h:127
#define P_FM_WR_DATA_3 		CBUS_REG_ADDR(FM_WR_DATA_3)
#define FM_WR_ADDR 0x1607 	///../ucode/c_stb_define.h:132
#define P_FM_WR_ADDR 		CBUS_REG_ADDR(FM_WR_ADDR)
#define FM_WR_ADDR_2 0x1657 	///../ucode/c_stb_define.h:133
#define P_FM_WR_ADDR_2 		CBUS_REG_ADDR(FM_WR_ADDR_2)
#define FM_WR_ADDR_3 0x16a7 	///../ucode/c_stb_define.h:134
#define P_FM_WR_ADDR_3 		CBUS_REG_ADDR(FM_WR_ADDR_3)
#define MAX_FM_COMP_ADDR 0x1608 	///../ucode/c_stb_define.h:138
#define P_MAX_FM_COMP_ADDR 		CBUS_REG_ADDR(MAX_FM_COMP_ADDR)
#define MAX_FM_COMP_ADDR_2 0x1658 	///../ucode/c_stb_define.h:139
#define P_MAX_FM_COMP_ADDR_2 		CBUS_REG_ADDR(MAX_FM_COMP_ADDR_2)
#define MAX_FM_COMP_ADDR_3 0x16a8 	///../ucode/c_stb_define.h:140
#define P_MAX_FM_COMP_ADDR_3 		CBUS_REG_ADDR(MAX_FM_COMP_ADDR_3)
#define TS_HEAD_0 0x1609 	///../ucode/c_stb_define.h:145
#define P_TS_HEAD_0 		CBUS_REG_ADDR(TS_HEAD_0)
#define TS_HEAD_0_2 0x1659 	///../ucode/c_stb_define.h:146
#define P_TS_HEAD_0_2 		CBUS_REG_ADDR(TS_HEAD_0_2)
#define TS_HEAD_0_3 0x16a9 	///../ucode/c_stb_define.h:147
#define P_TS_HEAD_0_3 		CBUS_REG_ADDR(TS_HEAD_0_3)
#define TS_HEAD_1 0x160a 	///../ucode/c_stb_define.h:151
#define P_TS_HEAD_1 		CBUS_REG_ADDR(TS_HEAD_1)
#define TS_HEAD_1_2 0x165a 	///../ucode/c_stb_define.h:152
#define P_TS_HEAD_1_2 		CBUS_REG_ADDR(TS_HEAD_1_2)
#define TS_HEAD_1_3 0x16aa 	///../ucode/c_stb_define.h:153
#define P_TS_HEAD_1_3 		CBUS_REG_ADDR(TS_HEAD_1_3)
#define OM_CMD_STATUS 0x160b 	///../ucode/c_stb_define.h:162
#define P_OM_CMD_STATUS 		CBUS_REG_ADDR(OM_CMD_STATUS)
#define OM_CMD_STATUS_2 0x165b 	///../ucode/c_stb_define.h:163
#define P_OM_CMD_STATUS_2 		CBUS_REG_ADDR(OM_CMD_STATUS_2)
#define OM_CMD_STATUS_3 0x16ab 	///../ucode/c_stb_define.h:164
#define P_OM_CMD_STATUS_3 		CBUS_REG_ADDR(OM_CMD_STATUS_3)
#define OM_CMD_DATA 0x160c 	///../ucode/c_stb_define.h:167
#define P_OM_CMD_DATA 		CBUS_REG_ADDR(OM_CMD_DATA)
#define OM_CMD_DATA_2 0x165c 	///../ucode/c_stb_define.h:168
#define P_OM_CMD_DATA_2 		CBUS_REG_ADDR(OM_CMD_DATA_2)
#define OM_CMD_DATA_3 0x16ac 	///../ucode/c_stb_define.h:169
#define P_OM_CMD_DATA_3 		CBUS_REG_ADDR(OM_CMD_DATA_3)
#define OM_CMD_DATA2 0x160d 	///../ucode/c_stb_define.h:171
#define P_OM_CMD_DATA2 		CBUS_REG_ADDR(OM_CMD_DATA2)
#define OM_CMD_DATA2_2 0x165d 	///../ucode/c_stb_define.h:172
#define P_OM_CMD_DATA2_2 		CBUS_REG_ADDR(OM_CMD_DATA2_2)
#define OM_CMD_DATA2_3 0x16ad 	///../ucode/c_stb_define.h:173
#define P_OM_CMD_DATA2_3 		CBUS_REG_ADDR(OM_CMD_DATA2_3)
#define SEC_BUFF_01_START 0x160e 	///../ucode/c_stb_define.h:176
#define P_SEC_BUFF_01_START 		CBUS_REG_ADDR(SEC_BUFF_01_START)
#define SEC_BUFF_01_START_2 0x165e 	///../ucode/c_stb_define.h:177
#define P_SEC_BUFF_01_START_2 		CBUS_REG_ADDR(SEC_BUFF_01_START_2)
#define SEC_BUFF_01_START_3 0x16ae 	///../ucode/c_stb_define.h:178
#define P_SEC_BUFF_01_START_3 		CBUS_REG_ADDR(SEC_BUFF_01_START_3)
#define SEC_BUFF_23_START 0x160f 	///../ucode/c_stb_define.h:181
#define P_SEC_BUFF_23_START 		CBUS_REG_ADDR(SEC_BUFF_23_START)
#define SEC_BUFF_23_START_2 0x165f 	///../ucode/c_stb_define.h:182
#define P_SEC_BUFF_23_START_2 		CBUS_REG_ADDR(SEC_BUFF_23_START_2)
#define SEC_BUFF_23_START_3 0x16af 	///../ucode/c_stb_define.h:183
#define P_SEC_BUFF_23_START_3 		CBUS_REG_ADDR(SEC_BUFF_23_START_3)
#define SEC_BUFF_SIZE 0x1610 	///../ucode/c_stb_define.h:188
#define P_SEC_BUFF_SIZE 		CBUS_REG_ADDR(SEC_BUFF_SIZE)
#define SEC_BUFF_SIZE_2 0x1660 	///../ucode/c_stb_define.h:189
#define P_SEC_BUFF_SIZE_2 		CBUS_REG_ADDR(SEC_BUFF_SIZE_2)
#define SEC_BUFF_SIZE_3 0x16b0 	///../ucode/c_stb_define.h:190
#define P_SEC_BUFF_SIZE_3 		CBUS_REG_ADDR(SEC_BUFF_SIZE_3)
#define SEC_BUFF_BUSY 0x1611 	///../ucode/c_stb_define.h:192
#define P_SEC_BUFF_BUSY 		CBUS_REG_ADDR(SEC_BUFF_BUSY)
#define SEC_BUFF_BUSY_2 0x1661 	///../ucode/c_stb_define.h:193
#define P_SEC_BUFF_BUSY_2 		CBUS_REG_ADDR(SEC_BUFF_BUSY_2)
#define SEC_BUFF_BUSY_3 0x16b1 	///../ucode/c_stb_define.h:194
#define P_SEC_BUFF_BUSY_3 		CBUS_REG_ADDR(SEC_BUFF_BUSY_3)
#define SEC_BUFF_READY 0x1612 	///../ucode/c_stb_define.h:197
#define P_SEC_BUFF_READY 		CBUS_REG_ADDR(SEC_BUFF_READY)
#define SEC_BUFF_READY_2 0x1662 	///../ucode/c_stb_define.h:198
#define P_SEC_BUFF_READY_2 		CBUS_REG_ADDR(SEC_BUFF_READY_2)
#define SEC_BUFF_READY_3 0x16b2 	///../ucode/c_stb_define.h:199
#define P_SEC_BUFF_READY_3 		CBUS_REG_ADDR(SEC_BUFF_READY_3)
#define SEC_BUFF_NUMBER 0x1613 	///../ucode/c_stb_define.h:204
#define P_SEC_BUFF_NUMBER 		CBUS_REG_ADDR(SEC_BUFF_NUMBER)
#define SEC_BUFF_NUMBER_2 0x1663 	///../ucode/c_stb_define.h:205
#define P_SEC_BUFF_NUMBER_2 		CBUS_REG_ADDR(SEC_BUFF_NUMBER_2)
#define SEC_BUFF_NUMBER_3 0x16b3 	///../ucode/c_stb_define.h:206
#define P_SEC_BUFF_NUMBER_3 		CBUS_REG_ADDR(SEC_BUFF_NUMBER_3)
#define ASSIGN_PID_NUMBER 0x1614 	///../ucode/c_stb_define.h:209
#define P_ASSIGN_PID_NUMBER 		CBUS_REG_ADDR(ASSIGN_PID_NUMBER)
#define ASSIGN_PID_NUMBER_2 0x1664 	///../ucode/c_stb_define.h:210
#define P_ASSIGN_PID_NUMBER_2 		CBUS_REG_ADDR(ASSIGN_PID_NUMBER_2)
#define ASSIGN_PID_NUMBER_3 0x16b4 	///../ucode/c_stb_define.h:211
#define P_ASSIGN_PID_NUMBER_3 		CBUS_REG_ADDR(ASSIGN_PID_NUMBER_3)
#define VIDEO_STREAM_ID 0x1615 	///../ucode/c_stb_define.h:214
#define P_VIDEO_STREAM_ID 		CBUS_REG_ADDR(VIDEO_STREAM_ID)
#define VIDEO_STREAM_ID_2 0x1665 	///../ucode/c_stb_define.h:215
#define P_VIDEO_STREAM_ID_2 		CBUS_REG_ADDR(VIDEO_STREAM_ID_2)
#define VIDEO_STREAM_ID_3 0x16b5 	///../ucode/c_stb_define.h:216
#define P_VIDEO_STREAM_ID_3 		CBUS_REG_ADDR(VIDEO_STREAM_ID_3)
#define AUDIO_STREAM_ID 0x1616 	///../ucode/c_stb_define.h:217
#define P_AUDIO_STREAM_ID 		CBUS_REG_ADDR(AUDIO_STREAM_ID)
#define AUDIO_STREAM_ID_2 0x1666 	///../ucode/c_stb_define.h:218
#define P_AUDIO_STREAM_ID_2 		CBUS_REG_ADDR(AUDIO_STREAM_ID_2)
#define AUDIO_STREAM_ID_3 0x16b6 	///../ucode/c_stb_define.h:219
#define P_AUDIO_STREAM_ID_3 		CBUS_REG_ADDR(AUDIO_STREAM_ID_3)
#define SUB_STREAM_ID 0x1617 	///../ucode/c_stb_define.h:220
#define P_SUB_STREAM_ID 		CBUS_REG_ADDR(SUB_STREAM_ID)
#define SUB_STREAM_ID_2 0x1667 	///../ucode/c_stb_define.h:221
#define P_SUB_STREAM_ID_2 		CBUS_REG_ADDR(SUB_STREAM_ID_2)
#define SUB_STREAM_ID_3 0x16b7 	///../ucode/c_stb_define.h:222
#define P_SUB_STREAM_ID_3 		CBUS_REG_ADDR(SUB_STREAM_ID_3)
#define OTHER_STREAM_ID 0x1618 	///../ucode/c_stb_define.h:223
#define P_OTHER_STREAM_ID 		CBUS_REG_ADDR(OTHER_STREAM_ID)
#define OTHER_STREAM_ID_2 0x1668 	///../ucode/c_stb_define.h:224
#define P_OTHER_STREAM_ID_2 		CBUS_REG_ADDR(OTHER_STREAM_ID_2)
#define OTHER_STREAM_ID_3 0x16b8 	///../ucode/c_stb_define.h:225
#define P_OTHER_STREAM_ID_3 		CBUS_REG_ADDR(OTHER_STREAM_ID_3)
#define PCR90K_CTL 0x1619 	///../ucode/c_stb_define.h:228
#define P_PCR90K_CTL 		CBUS_REG_ADDR(PCR90K_CTL)
#define PCR90K_CTL_2 0x1669 	///../ucode/c_stb_define.h:229
#define P_PCR90K_CTL_2 		CBUS_REG_ADDR(PCR90K_CTL_2)
#define PCR90K_CTL_3 0x16b9 	///../ucode/c_stb_define.h:230
#define P_PCR90K_CTL_3 		CBUS_REG_ADDR(PCR90K_CTL_3)
#define PCR_DEMUX 0x161a 	///../ucode/c_stb_define.h:232
#define P_PCR_DEMUX 		CBUS_REG_ADDR(PCR_DEMUX)
#define PCR_DEMUX_2 0x166a 	///../ucode/c_stb_define.h:233
#define P_PCR_DEMUX_2 		CBUS_REG_ADDR(PCR_DEMUX_2)
#define PCR_DEMUX_3 0x16ba 	///../ucode/c_stb_define.h:234
#define P_PCR_DEMUX_3 		CBUS_REG_ADDR(PCR_DEMUX_3)
#define VIDEO_PTS_DEMUX 0x161b 	///../ucode/c_stb_define.h:236
#define P_VIDEO_PTS_DEMUX 		CBUS_REG_ADDR(VIDEO_PTS_DEMUX)
#define VIDEO_PTS_DEMUX_2 0x166b 	///../ucode/c_stb_define.h:237
#define P_VIDEO_PTS_DEMUX_2 		CBUS_REG_ADDR(VIDEO_PTS_DEMUX_2)
#define VIDEO_PTS_DEMUX_3 0x16bb 	///../ucode/c_stb_define.h:238
#define P_VIDEO_PTS_DEMUX_3 		CBUS_REG_ADDR(VIDEO_PTS_DEMUX_3)
#define VIDEO_DTS_DEMUX 0x161c 	///../ucode/c_stb_define.h:240
#define P_VIDEO_DTS_DEMUX 		CBUS_REG_ADDR(VIDEO_DTS_DEMUX)
#define VIDEO_DTS_DEMUX_2 0x166c 	///../ucode/c_stb_define.h:241
#define P_VIDEO_DTS_DEMUX_2 		CBUS_REG_ADDR(VIDEO_DTS_DEMUX_2)
#define VIDEO_DTS_DEMUX_3 0x16bc 	///../ucode/c_stb_define.h:242
#define P_VIDEO_DTS_DEMUX_3 		CBUS_REG_ADDR(VIDEO_DTS_DEMUX_3)
#define AUDIO_PTS_DEMUX 0x161d 	///../ucode/c_stb_define.h:244
#define P_AUDIO_PTS_DEMUX 		CBUS_REG_ADDR(AUDIO_PTS_DEMUX)
#define AUDIO_PTS_DEMUX_2 0x166d 	///../ucode/c_stb_define.h:245
#define P_AUDIO_PTS_DEMUX_2 		CBUS_REG_ADDR(AUDIO_PTS_DEMUX_2)
#define AUDIO_PTS_DEMUX_3 0x16bd 	///../ucode/c_stb_define.h:246
#define P_AUDIO_PTS_DEMUX_3 		CBUS_REG_ADDR(AUDIO_PTS_DEMUX_3)
#define SUB_PTS_DEMUX 0x161e 	///../ucode/c_stb_define.h:248
#define P_SUB_PTS_DEMUX 		CBUS_REG_ADDR(SUB_PTS_DEMUX)
#define SUB_PTS_DEMUX_2 0x166e 	///../ucode/c_stb_define.h:249
#define P_SUB_PTS_DEMUX_2 		CBUS_REG_ADDR(SUB_PTS_DEMUX_2)
#define SUB_PTS_DEMUX_3 0x16be 	///../ucode/c_stb_define.h:250
#define P_SUB_PTS_DEMUX_3 		CBUS_REG_ADDR(SUB_PTS_DEMUX_3)
#define STB_PTS_DTS_STATUS 0x161f 	///../ucode/c_stb_define.h:260
#define P_STB_PTS_DTS_STATUS 		CBUS_REG_ADDR(STB_PTS_DTS_STATUS)
#define STB_PTS_DTS_STATUS_2 0x166f 	///../ucode/c_stb_define.h:261
#define P_STB_PTS_DTS_STATUS_2 		CBUS_REG_ADDR(STB_PTS_DTS_STATUS_2)
#define STB_PTS_DTS_STATUS_3 0x16bf 	///../ucode/c_stb_define.h:262
#define P_STB_PTS_DTS_STATUS_3 		CBUS_REG_ADDR(STB_PTS_DTS_STATUS_3)
#define STB_DEBUG_INDEX 0x1620 	///../ucode/c_stb_define.h:269
#define P_STB_DEBUG_INDEX 		CBUS_REG_ADDR(STB_DEBUG_INDEX)
#define STB_DEBUG_INDEX_2 0x1670 	///../ucode/c_stb_define.h:270
#define P_STB_DEBUG_INDEX_2 		CBUS_REG_ADDR(STB_DEBUG_INDEX_2)
#define STB_DEBUG_INDEX_3 0x16c0 	///../ucode/c_stb_define.h:271
#define P_STB_DEBUG_INDEX_3 		CBUS_REG_ADDR(STB_DEBUG_INDEX_3)
#define STB_DEBUG_DATAUT_O 0x1621 	///../ucode/c_stb_define.h:273
#define P_STB_DEBUG_DATAUT_O 		CBUS_REG_ADDR(STB_DEBUG_DATAUT_O)
#define STB_DEBUG_DATAUT_O_2 0x1671 	///../ucode/c_stb_define.h:274
#define P_STB_DEBUG_DATAUT_O_2 		CBUS_REG_ADDR(STB_DEBUG_DATAUT_O_2)
#define STB_DEBUG_DATAUT_O_3 0x16c1 	///../ucode/c_stb_define.h:275
#define P_STB_DEBUG_DATAUT_O_3 		CBUS_REG_ADDR(STB_DEBUG_DATAUT_O_3)
#define STBM_CTL_O 0x1622 	///../ucode/c_stb_define.h:279
#define P_STBM_CTL_O 		CBUS_REG_ADDR(STBM_CTL_O)
#define STBM_CTL_O_2 0x1672 	///../ucode/c_stb_define.h:280
#define P_STBM_CTL_O_2 		CBUS_REG_ADDR(STBM_CTL_O_2)
#define STBM_CTL_O_3 0x16c2 	///../ucode/c_stb_define.h:281
#define P_STBM_CTL_O_3 		CBUS_REG_ADDR(STBM_CTL_O_3)
#define STB_INT_STATUS 0x1623 	///../ucode/c_stb_define.h:293
#define P_STB_INT_STATUS 		CBUS_REG_ADDR(STB_INT_STATUS)
#define STB_INT_STATUS_2 0x1673 	///../ucode/c_stb_define.h:294
#define P_STB_INT_STATUS_2 		CBUS_REG_ADDR(STB_INT_STATUS_2)
#define STB_INT_STATUS_3 0x16c3 	///../ucode/c_stb_define.h:295
#define P_STB_INT_STATUS_3 		CBUS_REG_ADDR(STB_INT_STATUS_3)
#define DEMUX_ENDIAN 0x1624 	///../ucode/c_stb_define.h:307
#define P_DEMUX_ENDIAN 		CBUS_REG_ADDR(DEMUX_ENDIAN)
#define DEMUX_ENDIAN_2 0x1674 	///../ucode/c_stb_define.h:308
#define P_DEMUX_ENDIAN_2 		CBUS_REG_ADDR(DEMUX_ENDIAN_2)
#define DEMUX_ENDIAN_3 0x16c4 	///../ucode/c_stb_define.h:309
#define P_DEMUX_ENDIAN_3 		CBUS_REG_ADDR(DEMUX_ENDIAN_3)
#define TS_HIU_CTL 0x1625 	///../ucode/c_stb_define.h:315
#define P_TS_HIU_CTL 		CBUS_REG_ADDR(TS_HIU_CTL)
#define TS_HIU_CTL_2 0x1675 	///../ucode/c_stb_define.h:316
#define P_TS_HIU_CTL_2 		CBUS_REG_ADDR(TS_HIU_CTL_2)
#define TS_HIU_CTL_3 0x16c5 	///../ucode/c_stb_define.h:317
#define P_TS_HIU_CTL_3 		CBUS_REG_ADDR(TS_HIU_CTL_3)
#define SEC_BUFF_BASE 0x1626 	///../ucode/c_stb_define.h:319
#define P_SEC_BUFF_BASE 		CBUS_REG_ADDR(SEC_BUFF_BASE)
#define SEC_BUFF_BASE_2 0x1676 	///../ucode/c_stb_define.h:320
#define P_SEC_BUFF_BASE_2 		CBUS_REG_ADDR(SEC_BUFF_BASE_2)
#define SEC_BUFF_BASE_3 0x16c6 	///../ucode/c_stb_define.h:321
#define P_SEC_BUFF_BASE_3 		CBUS_REG_ADDR(SEC_BUFF_BASE_3)
#define DEMUX_MEM_REQ_EN 0x1627 	///../ucode/c_stb_define.h:328
#define P_DEMUX_MEM_REQ_EN 		CBUS_REG_ADDR(DEMUX_MEM_REQ_EN)
#define DEMUX_MEM_REQ_EN_2 0x1677 	///../ucode/c_stb_define.h:329
#define P_DEMUX_MEM_REQ_EN_2 		CBUS_REG_ADDR(DEMUX_MEM_REQ_EN_2)
#define DEMUX_MEM_REQ_EN_3 0x16c7 	///../ucode/c_stb_define.h:330
#define P_DEMUX_MEM_REQ_EN_3 		CBUS_REG_ADDR(DEMUX_MEM_REQ_EN_3)
#define VIDEO_PDTS_WR_PTR 0x1628 	///../ucode/c_stb_define.h:332
#define P_VIDEO_PDTS_WR_PTR 		CBUS_REG_ADDR(VIDEO_PDTS_WR_PTR)
#define VIDEO_PDTS_WR_PTR_2 0x1678 	///../ucode/c_stb_define.h:333
#define P_VIDEO_PDTS_WR_PTR_2 		CBUS_REG_ADDR(VIDEO_PDTS_WR_PTR_2)
#define VIDEO_PDTS_WR_PTR_3 0x16c8 	///../ucode/c_stb_define.h:334
#define P_VIDEO_PDTS_WR_PTR_3 		CBUS_REG_ADDR(VIDEO_PDTS_WR_PTR_3)
#define AUDIO_PDTS_WR_PTR 0x1629 	///../ucode/c_stb_define.h:336
#define P_AUDIO_PDTS_WR_PTR 		CBUS_REG_ADDR(AUDIO_PDTS_WR_PTR)
#define AUDIO_PDTS_WR_PTR_2 0x1679 	///../ucode/c_stb_define.h:337
#define P_AUDIO_PDTS_WR_PTR_2 		CBUS_REG_ADDR(AUDIO_PDTS_WR_PTR_2)
#define AUDIO_PDTS_WR_PTR_3 0x16c9 	///../ucode/c_stb_define.h:338
#define P_AUDIO_PDTS_WR_PTR_3 		CBUS_REG_ADDR(AUDIO_PDTS_WR_PTR_3)
#define SUB_WR_PTR 0x162a 	///../ucode/c_stb_define.h:340
#define P_SUB_WR_PTR 		CBUS_REG_ADDR(SUB_WR_PTR)
#define SUB_WR_PTR_2 0x167a 	///../ucode/c_stb_define.h:341
#define P_SUB_WR_PTR_2 		CBUS_REG_ADDR(SUB_WR_PTR_2)
#define SUB_WR_PTR_3 0x16ca 	///../ucode/c_stb_define.h:342
#define P_SUB_WR_PTR_3 		CBUS_REG_ADDR(SUB_WR_PTR_3)
#define SB_START 0x162b 	///../ucode/c_stb_define.h:344
#define P_SB_START 		CBUS_REG_ADDR(SB_START)
#define SB_START_2 0x167b 	///../ucode/c_stb_define.h:345
#define P_SB_START_2 		CBUS_REG_ADDR(SB_START_2)
#define SB_START_3 0x16cb 	///../ucode/c_stb_define.h:346
#define P_SB_START_3 		CBUS_REG_ADDR(SB_START_3)
#define SB_LAST_ADDR 0x162c 	///../ucode/c_stb_define.h:348
#define P_SB_LAST_ADDR 		CBUS_REG_ADDR(SB_LAST_ADDR)
#define SB_LAST_ADDR_2 0x167c 	///../ucode/c_stb_define.h:349
#define P_SB_LAST_ADDR_2 		CBUS_REG_ADDR(SB_LAST_ADDR_2)
#define SB_LAST_ADDR_3 0x16cc 	///../ucode/c_stb_define.h:350
#define P_SB_LAST_ADDR_3 		CBUS_REG_ADDR(SB_LAST_ADDR_3)
#define SB_PES_WR_PTR 0x162d 	///../ucode/c_stb_define.h:352
#define P_SB_PES_WR_PTR 		CBUS_REG_ADDR(SB_PES_WR_PTR)
#define SB_PES_WR_PTR_2 0x167d 	///../ucode/c_stb_define.h:353
#define P_SB_PES_WR_PTR_2 		CBUS_REG_ADDR(SB_PES_WR_PTR_2)
#define SB_PES_WR_PTR_3 0x16cd 	///../ucode/c_stb_define.h:354
#define P_SB_PES_WR_PTR_3 		CBUS_REG_ADDR(SB_PES_WR_PTR_3)
#define OTHER_WR_PTR 0x162e 	///../ucode/c_stb_define.h:357
#define P_OTHER_WR_PTR 		CBUS_REG_ADDR(OTHER_WR_PTR)
#define OTHER_WR_PTR_2 0x167e 	///../ucode/c_stb_define.h:358
#define P_OTHER_WR_PTR_2 		CBUS_REG_ADDR(OTHER_WR_PTR_2)
#define OTHER_WR_PTR_3 0x16ce 	///../ucode/c_stb_define.h:359
#define P_OTHER_WR_PTR_3 		CBUS_REG_ADDR(OTHER_WR_PTR_3)
#define OB_START 0x162f 	///../ucode/c_stb_define.h:361
#define P_OB_START 		CBUS_REG_ADDR(OB_START)
#define OB_START_2 0x167f 	///../ucode/c_stb_define.h:362
#define P_OB_START_2 		CBUS_REG_ADDR(OB_START_2)
#define OB_START_3 0x16cf 	///../ucode/c_stb_define.h:363
#define P_OB_START_3 		CBUS_REG_ADDR(OB_START_3)
#define OB_LAST_ADDR 0x1630 	///../ucode/c_stb_define.h:365
#define P_OB_LAST_ADDR 		CBUS_REG_ADDR(OB_LAST_ADDR)
#define OB_LAST_ADDR_2 0x1680 	///../ucode/c_stb_define.h:366
#define P_OB_LAST_ADDR_2 		CBUS_REG_ADDR(OB_LAST_ADDR_2)
#define OB_LAST_ADDR_3 0x16d0 	///../ucode/c_stb_define.h:367
#define P_OB_LAST_ADDR_3 		CBUS_REG_ADDR(OB_LAST_ADDR_3)
#define OB_PES_WR_PTR 0x1631 	///../ucode/c_stb_define.h:369
#define P_OB_PES_WR_PTR 		CBUS_REG_ADDR(OB_PES_WR_PTR)
#define OB_PES_WR_PTR_2 0x1681 	///../ucode/c_stb_define.h:370
#define P_OB_PES_WR_PTR_2 		CBUS_REG_ADDR(OB_PES_WR_PTR_2)
#define OB_PES_WR_PTR_3 0x16d1 	///../ucode/c_stb_define.h:371
#define P_OB_PES_WR_PTR_3 		CBUS_REG_ADDR(OB_PES_WR_PTR_3)
#define STB_INT_MASK 0x1632 	///../ucode/c_stb_define.h:383
#define P_STB_INT_MASK 		CBUS_REG_ADDR(STB_INT_MASK)
#define STB_INT_MASK_2 0x1682 	///../ucode/c_stb_define.h:384
#define P_STB_INT_MASK_2 		CBUS_REG_ADDR(STB_INT_MASK_2)
#define STB_INT_MASK_3 0x16d2 	///../ucode/c_stb_define.h:385
#define P_STB_INT_MASK_3 		CBUS_REG_ADDR(STB_INT_MASK_3)
#define VIDEO_SPLICING_CTL 0x1633 	///../ucode/c_stb_define.h:392
#define P_VIDEO_SPLICING_CTL 		CBUS_REG_ADDR(VIDEO_SPLICING_CTL)
#define VIDEO_SPLICING_CTL_2 0x1683 	///../ucode/c_stb_define.h:393
#define P_VIDEO_SPLICING_CTL_2 		CBUS_REG_ADDR(VIDEO_SPLICING_CTL_2)
#define VIDEO_SPLICING_CTL_3 0x16d3 	///../ucode/c_stb_define.h:394
#define P_VIDEO_SPLICING_CTL_3 		CBUS_REG_ADDR(VIDEO_SPLICING_CTL_3)
#define AUDIO_SPLICING_CTL 0x1634 	///../ucode/c_stb_define.h:401
#define P_AUDIO_SPLICING_CTL 		CBUS_REG_ADDR(AUDIO_SPLICING_CTL)
#define AUDIO_SPLICING_CTL_2 0x1684 	///../ucode/c_stb_define.h:402
#define P_AUDIO_SPLICING_CTL_2 		CBUS_REG_ADDR(AUDIO_SPLICING_CTL_2)
#define AUDIO_SPLICING_CTL_3 0x16d4 	///../ucode/c_stb_define.h:403
#define P_AUDIO_SPLICING_CTL_3 		CBUS_REG_ADDR(AUDIO_SPLICING_CTL_3)
#define TS_PACKAGE_BYTE_COUNT 0x1635 	///../ucode/c_stb_define.h:407
#define P_TS_PACKAGE_BYTE_COUNT 		CBUS_REG_ADDR(TS_PACKAGE_BYTE_COUNT)
#define TS_PACKAGE_BYTE_COUNT_2 0x1685 	///../ucode/c_stb_define.h:408
#define P_TS_PACKAGE_BYTE_COUNT_2 		CBUS_REG_ADDR(TS_PACKAGE_BYTE_COUNT_2)
#define TS_PACKAGE_BYTE_COUNT_3 0x16d5 	///../ucode/c_stb_define.h:409
#define P_TS_PACKAGE_BYTE_COUNT_3 		CBUS_REG_ADDR(TS_PACKAGE_BYTE_COUNT_3)
#define PES_STRONG_SYNC 0x1636 	///../ucode/c_stb_define.h:411
#define P_PES_STRONG_SYNC 		CBUS_REG_ADDR(PES_STRONG_SYNC)
#define PES_STRONG_SYNC_2 0x1686 	///../ucode/c_stb_define.h:412
#define P_PES_STRONG_SYNC_2 		CBUS_REG_ADDR(PES_STRONG_SYNC_2)
#define PES_STRONG_SYNC_3 0x16d6 	///../ucode/c_stb_define.h:413
#define P_PES_STRONG_SYNC_3 		CBUS_REG_ADDR(PES_STRONG_SYNC_3)
#define OM_DATA_RD_ADDR 0x1637 	///../ucode/c_stb_define.h:417
#define P_OM_DATA_RD_ADDR 		CBUS_REG_ADDR(OM_DATA_RD_ADDR)
#define OM_DATA_RD_ADDR_2 0x1687 	///../ucode/c_stb_define.h:418
#define P_OM_DATA_RD_ADDR_2 		CBUS_REG_ADDR(OM_DATA_RD_ADDR_2)
#define OM_DATA_RD_ADDR_3 0x16d7 	///../ucode/c_stb_define.h:419
#define P_OM_DATA_RD_ADDR_3 		CBUS_REG_ADDR(OM_DATA_RD_ADDR_3)
#define OM_DATA_RD 0x1638 	///../ucode/c_stb_define.h:421
#define P_OM_DATA_RD 		CBUS_REG_ADDR(OM_DATA_RD)
#define OM_DATA_RD_2 0x1688 	///../ucode/c_stb_define.h:422
#define P_OM_DATA_RD_2 		CBUS_REG_ADDR(OM_DATA_RD_2)
#define OM_DATA_RD_3 0x16d8 	///../ucode/c_stb_define.h:423
#define P_OM_DATA_RD_3 		CBUS_REG_ADDR(OM_DATA_RD_3)
#define SECTION_AUTO_STOP_3 0x1639 	///../ucode/c_stb_define.h:433
#define P_SECTION_AUTO_STOP_3 		CBUS_REG_ADDR(SECTION_AUTO_STOP_3)
#define SECTION_AUTO_STOP_3_2 0x1689 	///../ucode/c_stb_define.h:434
#define P_SECTION_AUTO_STOP_3_2 		CBUS_REG_ADDR(SECTION_AUTO_STOP_3_2)
#define SECTION_AUTO_STOP_3_3 0x16d9 	///../ucode/c_stb_define.h:435
#define P_SECTION_AUTO_STOP_3_3 		CBUS_REG_ADDR(SECTION_AUTO_STOP_3_3)
#define SECTION_AUTO_STOP_2 0x163a 	///../ucode/c_stb_define.h:437
#define P_SECTION_AUTO_STOP_2 		CBUS_REG_ADDR(SECTION_AUTO_STOP_2)
#define SECTION_AUTO_STOP_2_2 0x168a 	///../ucode/c_stb_define.h:438
#define P_SECTION_AUTO_STOP_2_2 		CBUS_REG_ADDR(SECTION_AUTO_STOP_2_2)
#define SECTION_AUTO_STOP_2_3 0x16da 	///../ucode/c_stb_define.h:439
#define P_SECTION_AUTO_STOP_2_3 		CBUS_REG_ADDR(SECTION_AUTO_STOP_2_3)
#define SECTION_AUTO_STOP_1 0x163b 	///../ucode/c_stb_define.h:441
#define P_SECTION_AUTO_STOP_1 		CBUS_REG_ADDR(SECTION_AUTO_STOP_1)
#define SECTION_AUTO_STOP_1_2 0x168b 	///../ucode/c_stb_define.h:442
#define P_SECTION_AUTO_STOP_1_2 		CBUS_REG_ADDR(SECTION_AUTO_STOP_1_2)
#define SECTION_AUTO_STOP_1_3 0x16db 	///../ucode/c_stb_define.h:443
#define P_SECTION_AUTO_STOP_1_3 		CBUS_REG_ADDR(SECTION_AUTO_STOP_1_3)
#define SECTION_AUTO_STOP_0 0x163c 	///../ucode/c_stb_define.h:445
#define P_SECTION_AUTO_STOP_0 		CBUS_REG_ADDR(SECTION_AUTO_STOP_0)
#define SECTION_AUTO_STOP_0_2 0x168c 	///../ucode/c_stb_define.h:446
#define P_SECTION_AUTO_STOP_0_2 		CBUS_REG_ADDR(SECTION_AUTO_STOP_0_2)
#define SECTION_AUTO_STOP_0_3 0x16dc 	///../ucode/c_stb_define.h:447
#define P_SECTION_AUTO_STOP_0_3 		CBUS_REG_ADDR(SECTION_AUTO_STOP_0_3)
#define DEMUX_CHANNEL_RESET 0x163d 	///../ucode/c_stb_define.h:450
#define P_DEMUX_CHANNEL_RESET 		CBUS_REG_ADDR(DEMUX_CHANNEL_RESET)
#define DEMUX_CHANNEL_RESET_2 0x168d 	///../ucode/c_stb_define.h:451
#define P_DEMUX_CHANNEL_RESET_2 		CBUS_REG_ADDR(DEMUX_CHANNEL_RESET_2)
#define DEMUX_CHANNEL_RESET_3 0x16dd 	///../ucode/c_stb_define.h:452
#define P_DEMUX_CHANNEL_RESET_3 		CBUS_REG_ADDR(DEMUX_CHANNEL_RESET_3)
#define DEMUX_SCRAMBLING_STATE 0x163e 	///../ucode/c_stb_define.h:453
#define P_DEMUX_SCRAMBLING_STATE 		CBUS_REG_ADDR(DEMUX_SCRAMBLING_STATE)
#define DEMUX_SCRAMBLING_STATE_2 0x168e 	///../ucode/c_stb_define.h:454
#define P_DEMUX_SCRAMBLING_STATE_2 		CBUS_REG_ADDR(DEMUX_SCRAMBLING_STATE_2)
#define DEMUX_SCRAMBLING_STATE_3 0x16de 	///../ucode/c_stb_define.h:455
#define P_DEMUX_SCRAMBLING_STATE_3 		CBUS_REG_ADDR(DEMUX_SCRAMBLING_STATE_3)
#define DEMUX_CHANNEL_ACTIVITY 0x163f 	///../ucode/c_stb_define.h:456
#define P_DEMUX_CHANNEL_ACTIVITY 		CBUS_REG_ADDR(DEMUX_CHANNEL_ACTIVITY)
#define DEMUX_CHANNEL_ACTIVITY_2 0x168f 	///../ucode/c_stb_define.h:457
#define P_DEMUX_CHANNEL_ACTIVITY_2 		CBUS_REG_ADDR(DEMUX_CHANNEL_ACTIVITY_2)
#define DEMUX_CHANNEL_ACTIVITY_3 0x16df 	///../ucode/c_stb_define.h:458
#define P_DEMUX_CHANNEL_ACTIVITY_3 		CBUS_REG_ADDR(DEMUX_CHANNEL_ACTIVITY_3)
#define DEMUX_STAMP_CTL 0x1640 	///../ucode/c_stb_define.h:464
#define P_DEMUX_STAMP_CTL 		CBUS_REG_ADDR(DEMUX_STAMP_CTL)
#define DEMUX_STAMP_CTL_2 0x1690 	///../ucode/c_stb_define.h:465
#define P_DEMUX_STAMP_CTL_2 		CBUS_REG_ADDR(DEMUX_STAMP_CTL_2)
#define DEMUX_STAMP_CTL_3 0x16e0 	///../ucode/c_stb_define.h:466
#define P_DEMUX_STAMP_CTL_3 		CBUS_REG_ADDR(DEMUX_STAMP_CTL_3)
#define DEMUX_VIDEO_STAMP_SYNC_0 0x1641 	///../ucode/c_stb_define.h:467
#define P_DEMUX_VIDEO_STAMP_SYNC_0 		CBUS_REG_ADDR(DEMUX_VIDEO_STAMP_SYNC_0)
#define DEMUX_VIDEO_STAMP_SYNC_0_2 0x1691 	///../ucode/c_stb_define.h:468
#define P_DEMUX_VIDEO_STAMP_SYNC_0_2 		CBUS_REG_ADDR(DEMUX_VIDEO_STAMP_SYNC_0_2)
#define DEMUX_VIDEO_STAMP_SYNC_0_3 0x16e1 	///../ucode/c_stb_define.h:469
#define P_DEMUX_VIDEO_STAMP_SYNC_0_3 		CBUS_REG_ADDR(DEMUX_VIDEO_STAMP_SYNC_0_3)
#define DEMUX_VIDEO_STAMP_SYNC_1 0x1642 	///../ucode/c_stb_define.h:470
#define P_DEMUX_VIDEO_STAMP_SYNC_1 		CBUS_REG_ADDR(DEMUX_VIDEO_STAMP_SYNC_1)
#define DEMUX_VIDEO_STAMP_SYNC_1_2 0x1692 	///../ucode/c_stb_define.h:471
#define P_DEMUX_VIDEO_STAMP_SYNC_1_2 		CBUS_REG_ADDR(DEMUX_VIDEO_STAMP_SYNC_1_2)
#define DEMUX_VIDEO_STAMP_SYNC_1_3 0x16e2 	///../ucode/c_stb_define.h:472
#define P_DEMUX_VIDEO_STAMP_SYNC_1_3 		CBUS_REG_ADDR(DEMUX_VIDEO_STAMP_SYNC_1_3)
#define DEMUX_AUDIO_STAMP_SYNC_0 0x1643 	///../ucode/c_stb_define.h:473
#define P_DEMUX_AUDIO_STAMP_SYNC_0 		CBUS_REG_ADDR(DEMUX_AUDIO_STAMP_SYNC_0)
#define DEMUX_AUDIO_STAMP_SYNC_0_2 0x1693 	///../ucode/c_stb_define.h:474
#define P_DEMUX_AUDIO_STAMP_SYNC_0_2 		CBUS_REG_ADDR(DEMUX_AUDIO_STAMP_SYNC_0_2)
#define DEMUX_AUDIO_STAMP_SYNC_0_3 0x16e3 	///../ucode/c_stb_define.h:475
#define P_DEMUX_AUDIO_STAMP_SYNC_0_3 		CBUS_REG_ADDR(DEMUX_AUDIO_STAMP_SYNC_0_3)
#define DEMUX_AUDIO_STAMP_SYNC_1 0x1644 	///../ucode/c_stb_define.h:476
#define P_DEMUX_AUDIO_STAMP_SYNC_1 		CBUS_REG_ADDR(DEMUX_AUDIO_STAMP_SYNC_1)
#define DEMUX_AUDIO_STAMP_SYNC_1_2 0x1694 	///../ucode/c_stb_define.h:477
#define P_DEMUX_AUDIO_STAMP_SYNC_1_2 		CBUS_REG_ADDR(DEMUX_AUDIO_STAMP_SYNC_1_2)
#define DEMUX_AUDIO_STAMP_SYNC_1_3 0x16e4 	///../ucode/c_stb_define.h:478
#define P_DEMUX_AUDIO_STAMP_SYNC_1_3 		CBUS_REG_ADDR(DEMUX_AUDIO_STAMP_SYNC_1_3)
#define DEMUX_SECTION_RESET 0x1645 	///../ucode/c_stb_define.h:483
#define P_DEMUX_SECTION_RESET 		CBUS_REG_ADDR(DEMUX_SECTION_RESET)
#define DEMUX_SECTION_RESET_2 0x1695 	///../ucode/c_stb_define.h:484
#define P_DEMUX_SECTION_RESET_2 		CBUS_REG_ADDR(DEMUX_SECTION_RESET_2)
#define DEMUX_SECTION_RESET_3 0x16e5 	///../ucode/c_stb_define.h:485
#define P_DEMUX_SECTION_RESET_3 		CBUS_REG_ADDR(DEMUX_SECTION_RESET_3)
#define EFUSE_CNTL0 0x0 	///../ucode/secure_apb.h:7
#define P_EFUSE_CNTL0 		SECBUS_REG_ADDR(EFUSE_CNTL0)
#define EFUSE_CNTL1 0x1 	///../ucode/secure_apb.h:8
#define P_EFUSE_CNTL1 		SECBUS_REG_ADDR(EFUSE_CNTL1)
#define EFUSE_CNTL2 0x2 	///../ucode/secure_apb.h:9
#define P_EFUSE_CNTL2 		SECBUS_REG_ADDR(EFUSE_CNTL2)
#define EFUSE_CNTL3 0x3 	///../ucode/secure_apb.h:10
#define P_EFUSE_CNTL3 		SECBUS_REG_ADDR(EFUSE_CNTL3)
#define EFUSE_CNTL4 0x4 	///../ucode/secure_apb.h:11
#define P_EFUSE_CNTL4 		SECBUS_REG_ADDR(EFUSE_CNTL4)
#define AO_SECURE_REG0 0x00 	///../ucode/secure_apb.h:19
#define P_AO_SECURE_REG0 		SECBUS2_REG_ADDR(AO_SECURE_REG0)
#define AO_SECURE_REG1 0x01 	///../ucode/secure_apb.h:20
#define P_AO_SECURE_REG1 		SECBUS2_REG_ADDR(AO_SECURE_REG1)
#define AO_SECURE_REG2 0x02 	///../ucode/secure_apb.h:21
#define P_AO_SECURE_REG2 		SECBUS2_REG_ADDR(AO_SECURE_REG2)
#define SEC_BLKMV_AES_REG0 0x00 	///../ucode/secure_apb.h:34
#define P_SEC_BLKMV_AES_REG0 		SECBUS3_REG_ADDR(SEC_BLKMV_AES_REG0)
#define SEC_BLKMV_AES_W0 0x01 	///../ucode/secure_apb.h:35
#define P_SEC_BLKMV_AES_W0 		SECBUS3_REG_ADDR(SEC_BLKMV_AES_W0)
#define SEC_BLKMV_AES_W1 0x02 	///../ucode/secure_apb.h:36
#define P_SEC_BLKMV_AES_W1 		SECBUS3_REG_ADDR(SEC_BLKMV_AES_W1)
#define SEC_BLKMV_AES_W2 0x03 	///../ucode/secure_apb.h:37
#define P_SEC_BLKMV_AES_W2 		SECBUS3_REG_ADDR(SEC_BLKMV_AES_W2)
#define SEC_BLKMV_AES_W3 0x04 	///../ucode/secure_apb.h:38
#define P_SEC_BLKMV_AES_W3 		SECBUS3_REG_ADDR(SEC_BLKMV_AES_W3)
#define SEC_BLKMV_AES_R0 0x05 	///../ucode/secure_apb.h:39
#define P_SEC_BLKMV_AES_R0 		SECBUS3_REG_ADDR(SEC_BLKMV_AES_R0)
#define SEC_BLKMV_AES_R1 0x06 	///../ucode/secure_apb.h:40
#define P_SEC_BLKMV_AES_R1 		SECBUS3_REG_ADDR(SEC_BLKMV_AES_R1)
#define SEC_BLKMV_AES_R2 0x07 	///../ucode/secure_apb.h:41
#define P_SEC_BLKMV_AES_R2 		SECBUS3_REG_ADDR(SEC_BLKMV_AES_R2)
#define SEC_BLKMV_AES_R3 0x08 	///../ucode/secure_apb.h:42
#define P_SEC_BLKMV_AES_R3 		SECBUS3_REG_ADDR(SEC_BLKMV_AES_R3)
#define SEC_BLKMV_TDES_LAST_IV_LO 0x09 	///../ucode/secure_apb.h:43
#define P_SEC_BLKMV_TDES_LAST_IV_LO 		SECBUS3_REG_ADDR(SEC_BLKMV_TDES_LAST_IV_LO)
#define SEC_BLKMV_TDES_LAST_IV_HI 0x0a 	///../ucode/secure_apb.h:44
#define P_SEC_BLKMV_TDES_LAST_IV_HI 		SECBUS3_REG_ADDR(SEC_BLKMV_TDES_LAST_IV_HI)
#define SEC_BLKMV_AES_IV_0 0x0b 	///../ucode/secure_apb.h:45
#define P_SEC_BLKMV_AES_IV_0 		SECBUS3_REG_ADDR(SEC_BLKMV_AES_IV_0)
#define SEC_BLKMV_AES_IV_1 0x0c 	///../ucode/secure_apb.h:46
#define P_SEC_BLKMV_AES_IV_1 		SECBUS3_REG_ADDR(SEC_BLKMV_AES_IV_1)
#define SEC_BLKMV_AES_IV_2 0x0d 	///../ucode/secure_apb.h:47
#define P_SEC_BLKMV_AES_IV_2 		SECBUS3_REG_ADDR(SEC_BLKMV_AES_IV_2)
#define SEC_BLKMV_AES_IV_3 0x0e 	///../ucode/secure_apb.h:48
#define P_SEC_BLKMV_AES_IV_3 		SECBUS3_REG_ADDR(SEC_BLKMV_AES_IV_3)
#define SEC_BLKMV_AES_KEY_0 0x10 	///../ucode/secure_apb.h:50
#define P_SEC_BLKMV_AES_KEY_0 		SECBUS3_REG_ADDR(SEC_BLKMV_AES_KEY_0)
#define SEC_BLKMV_AES_KEY_1 0x11 	///../ucode/secure_apb.h:51
#define P_SEC_BLKMV_AES_KEY_1 		SECBUS3_REG_ADDR(SEC_BLKMV_AES_KEY_1)
#define SEC_BLKMV_AES_KEY_2 0x12 	///../ucode/secure_apb.h:52
#define P_SEC_BLKMV_AES_KEY_2 		SECBUS3_REG_ADDR(SEC_BLKMV_AES_KEY_2)
#define SEC_BLKMV_AES_KEY_3 0x13 	///../ucode/secure_apb.h:53
#define P_SEC_BLKMV_AES_KEY_3 		SECBUS3_REG_ADDR(SEC_BLKMV_AES_KEY_3)
#define SEC_BLKMV_AES_KEY_4 0x14 	///../ucode/secure_apb.h:54
#define P_SEC_BLKMV_AES_KEY_4 		SECBUS3_REG_ADDR(SEC_BLKMV_AES_KEY_4)
#define SEC_BLKMV_AES_KEY_5 0x15 	///../ucode/secure_apb.h:55
#define P_SEC_BLKMV_AES_KEY_5 		SECBUS3_REG_ADDR(SEC_BLKMV_AES_KEY_5)
#define SEC_BLKMV_AES_KEY_6 0x16 	///../ucode/secure_apb.h:56
#define P_SEC_BLKMV_AES_KEY_6 		SECBUS3_REG_ADDR(SEC_BLKMV_AES_KEY_6)
#define SEC_BLKMV_AES_KEY_7 0x17 	///../ucode/secure_apb.h:57
#define P_SEC_BLKMV_AES_KEY_7 		SECBUS3_REG_ADDR(SEC_BLKMV_AES_KEY_7)
#define SEC_BLKMV_THREAD_TABLE_START0 0x18 	///../ucode/secure_apb.h:59
#define P_SEC_BLKMV_THREAD_TABLE_START0 		SECBUS3_REG_ADDR(SEC_BLKMV_THREAD_TABLE_START0)
#define SEC_BLKMV_THREAD_TABLE_CURR0 0x19 	///../ucode/secure_apb.h:60
#define P_SEC_BLKMV_THREAD_TABLE_CURR0 		SECBUS3_REG_ADDR(SEC_BLKMV_THREAD_TABLE_CURR0)
#define SEC_BLKMV_THREAD_TABLE_END0 0x1a 	///../ucode/secure_apb.h:61
#define P_SEC_BLKMV_THREAD_TABLE_END0 		SECBUS3_REG_ADDR(SEC_BLKMV_THREAD_TABLE_END0)
#define SEC_BLKMV_THREAD_TABLE_START1 0x1b 	///../ucode/secure_apb.h:63
#define P_SEC_BLKMV_THREAD_TABLE_START1 		SECBUS3_REG_ADDR(SEC_BLKMV_THREAD_TABLE_START1)
#define SEC_BLKMV_THREAD_TABLE_CURR1 0x1c 	///../ucode/secure_apb.h:64
#define P_SEC_BLKMV_THREAD_TABLE_CURR1 		SECBUS3_REG_ADDR(SEC_BLKMV_THREAD_TABLE_CURR1)
#define SEC_BLKMV_THREAD_TABLE_END1 0x1d 	///../ucode/secure_apb.h:65
#define P_SEC_BLKMV_THREAD_TABLE_END1 		SECBUS3_REG_ADDR(SEC_BLKMV_THREAD_TABLE_END1)
#define SEC_BLKMV_THREAD_TABLE_START2 0x1e 	///../ucode/secure_apb.h:67
#define P_SEC_BLKMV_THREAD_TABLE_START2 		SECBUS3_REG_ADDR(SEC_BLKMV_THREAD_TABLE_START2)
#define SEC_BLKMV_THREAD_TABLE_CURR2 0x1f 	///../ucode/secure_apb.h:68
#define P_SEC_BLKMV_THREAD_TABLE_CURR2 		SECBUS3_REG_ADDR(SEC_BLKMV_THREAD_TABLE_CURR2)
#define SEC_BLKMV_THREAD_TABLE_END2 0x20 	///../ucode/secure_apb.h:69
#define P_SEC_BLKMV_THREAD_TABLE_END2 		SECBUS3_REG_ADDR(SEC_BLKMV_THREAD_TABLE_END2)
#define SEC_BLKMV_THREAD_TABLE_START3 0x21 	///../ucode/secure_apb.h:71
#define P_SEC_BLKMV_THREAD_TABLE_START3 		SECBUS3_REG_ADDR(SEC_BLKMV_THREAD_TABLE_START3)
#define SEC_BLKMV_THREAD_TABLE_CURR3 0x22 	///../ucode/secure_apb.h:72
#define P_SEC_BLKMV_THREAD_TABLE_CURR3 		SECBUS3_REG_ADDR(SEC_BLKMV_THREAD_TABLE_CURR3)
#define SEC_BLKMV_THREAD_TABLE_END3 0x23 	///../ucode/secure_apb.h:73
#define P_SEC_BLKMV_THREAD_TABLE_END3 		SECBUS3_REG_ADDR(SEC_BLKMV_THREAD_TABLE_END3)
#define SEC_BLKMV_GEN_REG0 0x24 	///../ucode/secure_apb.h:75
#define P_SEC_BLKMV_GEN_REG0 		SECBUS3_REG_ADDR(SEC_BLKMV_GEN_REG0)
#define HDMI_ADDR_PORT 0x42000 	///../ucode/hdmi.h:4
#define P_HDMI_ADDR_PORT 		APB_REG_ADDR(HDMI_ADDR_PORT)
#define HDMI_DATA_PORT 0x42004 	///../ucode/hdmi.h:5
#define P_HDMI_DATA_PORT 		APB_REG_ADDR(HDMI_DATA_PORT)
#define HDMI_CTRL_PORT 0x42008 	///../ucode/hdmi.h:6
#define P_HDMI_CTRL_PORT 		APB_REG_ADDR(HDMI_CTRL_PORT)
#define MMC_CHAN_STS (S_DMC_REG_BASE + (0x32 << 2))		///../ucode/dmc_reg.h:170
#define P_MMC_CHAN_STS			MMC_REG_ADDR(MMC_CHAN_STS)
#endif
