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Whenever possible, you should use the general-purpose constraint letters
in asm arguments, since they will convey meaning more readily to
people reading your code. Failing that, use the constraint letters
that usually have very similar meanings across architectures. The most
commonly used constraints are ‘m’ and ‘r’ (for memory and
general-purpose registers respectively; see Simple Constraints), and
‘I’, usually the letter indicating the most common
immediate-constant format.
Each architecture defines additional constraints. These constraints
are used by the compiler itself for instruction generation, as well as
for asm statements; therefore, some of the constraints are not
particularly useful for asm. Here is a summary of some of the
machine-dependent constraints available on some particular machines;
it includes both constraints that are useful for asm and
constraints that aren’t. The compiler source file mentioned in the
table heading for each architecture is the definitive reference for
the meanings of that architecture’s constraints.
kThe stack pointer register (SP)
wFloating point or SIMD vector register
IInteger constant that is valid as an immediate operand in an ADD
instruction
JInteger constant that is valid as an immediate operand in a SUB
instruction (once negated)
KInteger constant that can be used with a 32-bit logical instruction
LInteger constant that can be used with a 64-bit logical instruction
MInteger constant that is valid as an immediate operand in a 32-bit MOV
pseudo instruction. The MOV may be assembled to one of several different
machine instructions depending on the value
NInteger constant that is valid as an immediate operand in a 64-bit MOV
pseudo instruction
SAn absolute symbolic address or a label reference
YFloating point constant zero
ZInteger constant zero
UshThe high part (bits 12 and upwards) of the pc-relative address of a symbol within 4GB of the instruction
QA memory address which uses a single base register with no offset
UmpA memory address suitable for a load/store pair instruction in SI, DI, SF and DF modes
qRegisters usable in ARCompact 16-bit instructions: r0-r3,
r12-r15. This constraint can only match when the -mq
option is in effect.
eRegisters usable as base-regs of memory addresses in ARCompact 16-bit memory
instructions: r0-r3, r12-r15, sp.
This constraint can only match when the -mq
option is in effect.
DARC FPX (dpfp) 64-bit registers. D0, D1.
IA signed 12-bit integer constant.
Calconstant for arithmetic/logical operations. This might be any constant that can be put into a long immediate by the assmbler or linker without involving a PIC relocation.
KA 3-bit unsigned integer constant.
LA 6-bit unsigned integer constant.
CnLOne’s complement of a 6-bit unsigned integer constant.
CmLTwo’s complement of a 6-bit unsigned integer constant.
MA 5-bit unsigned integer constant.
OA 7-bit unsigned integer constant.
PA 8-bit unsigned integer constant.
HAny const_double value.
hIn Thumb state, the core registers r8-r15.
kThe stack pointer register.
lIn Thumb State the core registers r0-r7. In ARM state this
is an alias for the r constraint.
tVFP floating-point registers s0-s31. Used for 32 bit values.
wVFP floating-point registers d0-d31 and the appropriate
subset d0-d15 based on command line options.
Used for 64 bit values only. Not valid for Thumb1.
yThe iWMMX co-processor registers.
zThe iWMMX GR registers.
GThe floating-point constant 0.0
IInteger that is valid as an immediate operand in a data processing instruction. That is, an integer in the range 0 to 255 rotated by a multiple of 2
JInteger in the range -4095 to 4095
KInteger that satisfies constraint ‘I’ when inverted (ones complement)
LInteger that satisfies constraint ‘I’ when negated (twos complement)
MInteger in the range 0 to 32
QA memory reference where the exact address is in a single register
(‘‘m’’ is preferable for asm statements)
RAn item in the constant pool
SA symbol in the text segment of the current file
UvA memory reference suitable for VFP load/store insns (reg+constant offset)
UyA memory reference suitable for iWMMXt load/store instructions.
UqA memory reference suitable for the ARMv4 ldrsb instruction.
lRegisters from r0 to r15
aRegisters from r16 to r23
dRegisters from r16 to r31
wRegisters from r24 to r31. These registers can be used in ‘adiw’ command
ePointer register (r26–r31)
bBase pointer register (r28–r31)
qStack pointer register (SPH:SPL)
tTemporary register r0
xRegister pair X (r27:r26)
yRegister pair Y (r29:r28)
zRegister pair Z (r31:r30)
IConstant greater than -1, less than 64
JConstant greater than -64, less than 1
KConstant integer 2
LConstant integer 0
MConstant that fits in 8 bits
NConstant integer -1
OConstant integer 8, 16, or 24
PConstant integer 1
GA floating point constant 0.0
QA memory address based on Y or Z pointer with displacement.
aP register
dD register
zA call clobbered P register.
qnA single register. If n is in the range 0 to 7, the corresponding D
register. If it is A, then the register P0.
DEven-numbered D register
WOdd-numbered D register
eAccumulator register.
AEven-numbered accumulator register.
BOdd-numbered accumulator register.
bI register
vB register
fM register
cRegisters used for circular buffering, i.e. I, B, or L registers.
CThe CC register.
tLT0 or LT1.
kLC0 or LC1.
uLB0 or LB1.
xAny D, P, B, M, I or L register.
yAdditional registers typically used only in prologues and epilogues: RETS, RETN, RETI, RETX, RETE, ASTAT, SEQSTAT and USP.
wAny register except accumulators or CC.
KshSigned 16 bit integer (in the range -32768 to 32767)
KuhUnsigned 16 bit integer (in the range 0 to 65535)
Ks7Signed 7 bit integer (in the range -64 to 63)
Ku7Unsigned 7 bit integer (in the range 0 to 127)
Ku5Unsigned 5 bit integer (in the range 0 to 31)
Ks4Signed 4 bit integer (in the range -8 to 7)
Ks3Signed 3 bit integer (in the range -3 to 4)
Ku3Unsigned 3 bit integer (in the range 0 to 7)
PnConstant n, where n is a single-digit constant in the range 0 to 4.
PAAn integer equal to one of the MACFLAG_XXX constants that is suitable for use with either accumulator.
PBAn integer equal to one of the MACFLAG_XXX constants that is suitable for use only with accumulator A1.
M1Constant 255.
M2Constant 65535.
JAn integer constant with exactly a single bit set.
LAn integer constant with all bits set except exactly one.
HQAny SYMBOL_REF.
bRegisters from r0 to r14 (registers without stack pointer)
tRegister from r0 to r11 (all 16-bit registers)
pRegister from r12 to r15 (all 32-bit registers)
ISigned constant that fits in 4 bits
JSigned constant that fits in 5 bits
KSigned constant that fits in 6 bits
LUnsigned constant that fits in 4 bits
MSigned constant that fits in 32 bits
NCheck for 64 bits wide constants for add/sub instructions
GFloating point constant that is legal for store immediate
U16An unsigned 16-bit constant.
KAn unsigned 5-bit constant.
LA signed 11-bit constant.
Cm1A signed 11-bit constant added to -1. Can only match when the -m1reg-reg option is active.
Cl1Left-shift of -1, i.e., a bit mask with a block of leading ones, the rest being a block of trailing zeroes. Can only match when the -m1reg-reg option is active.
Cr1Right-shift of -1, i.e., a bit mask with a trailing block of ones, the rest being zeroes. Or to put it another way, one less than a power of two. Can only match when the -m1reg-reg option is active.
CalConstant for arithmetic/logical operations.
This is like i, except that for position independent code,
no symbols / expressions needing relocations are allowed.
CsySymbolic constant for call/jump instruction.
RcsThe register class usable in short insns. This is a register class constraint, and can thus drive register allocation. This constraint won’t match unless -mprefer-short-insn-regs is in effect.
RscThe the register class of registers that can be used to hold a sibcall call address. I.e., a caller-saved register.
RctCore control register class.
RgsThe register group usable in short insns. This constraint does not use a register class, so that it only passively matches suitable registers, and doesn’t drive register allocation.
RraMatches the return address if it can be replaced with the link register.
RccMatches the integer condition code register.
SraMatches the return address if it is in a stack slot.
CfmMatches control register values to switch fp mode, which are encapsulated in
UNSPEC_FP_MODE.
aRegister in the class ACC_REGS (acc0 to acc7).
bRegister in the class EVEN_ACC_REGS (acc0 to acc7).
cRegister in the class CC_REGS (fcc0 to fcc3 and
icc0 to icc3).
dRegister in the class GPR_REGS (gr0 to gr63).
eRegister in the class EVEN_REGS (gr0 to gr63).
Odd registers are excluded not in the class but through the use of a machine
mode larger than 4 bytes.
fRegister in the class FPR_REGS (fr0 to fr63).
hRegister in the class FEVEN_REGS (fr0 to fr63).
Odd registers are excluded not in the class but through the use of a machine
mode larger than 4 bytes.
lRegister in the class LR_REG (the lr register).
qRegister in the class QUAD_REGS (gr2 to gr63).
Register numbers not divisible by 4 are excluded not in the class but through
the use of a machine mode larger than 8 bytes.
tRegister in the class ICC_REGS (icc0 to icc3).
uRegister in the class FCC_REGS (fcc0 to fcc3).
vRegister in the class ICR_REGS (cc4 to cc7).
wRegister in the class FCR_REGS (cc0 to cc3).
xRegister in the class QUAD_FPR_REGS (fr0 to fr63).
Register numbers not divisible by 4 are excluded not in the class but through
the use of a machine mode larger than 8 bytes.
zRegister in the class SPR_REGS (lcr and lr).
ARegister in the class QUAD_ACC_REGS (acc0 to acc7).
BRegister in the class ACCG_REGS (accg0 to accg7).
CRegister in the class CR_REGS (cc0 to cc7).
GFloating point constant zero
I6-bit signed integer constant
J10-bit signed integer constant
L16-bit signed integer constant
M16-bit unsigned integer constant
N12-bit signed integer constant that is negative—i.e. in the range of -2048 to -1
OConstant zero
P12-bit signed integer constant that is greater than zero—i.e. in the range of 1 to 2047.
AAn absolute address
BAn offset address
WA register indirect memory operand
eAn offset address.
fAn offset address.
OThe constant zero or one
IA 16-bit signed constant (-32768 … 32767)
wA bitfield mask suitable for bext or bins
xAn inverted bitfield mask suitable for bext or bins
LA 16-bit unsigned constant, multiple of 4 (0 … 65532)
SA 20-bit signed constant (-524288 … 524287)
bA constant for a bitfield width (1 … 16)
KAA 10-bit signed constant (-512 … 511)
aGeneral register 1
fFloating point register
qShift amount register
xFloating point register (deprecated)
yUpper floating point register (32-bit), floating point register (64-bit)
ZAny register
ISigned 11-bit integer constant
JSigned 14-bit integer constant
KInteger constant that can be deposited with a zdepi instruction
LSigned 5-bit integer constant
MInteger constant 0
NInteger constant that can be loaded with a ldil instruction
OInteger constant whose value plus one is a power of 2
PInteger constant that can be used for and operations in depi
and extru instructions
SInteger constant 31
UInteger constant 63
GFloating-point constant 0.0
AA lo_sum data-linkage-table memory operand
QA memory operand that can be used as the destination operand of an integer store instruction
RA scaled or unscaled indexed memory operand
TA memory operand for floating-point loads and stores
WA register indirect memory operand
aGeneral register r0 to r3 for addl instruction
bBranch register
cPredicate register (‘c’ as in “conditional”)
dApplication register residing in M-unit
eApplication register residing in I-unit
fFloating-point register
mMemory operand. If used together with ‘<’ or ‘>’, the operand can have postincrement and postdecrement which require printing with ‘%Pn’ on IA-64.
GFloating-point constant 0.0 or 1.0
I14-bit signed integer constant
J22-bit signed integer constant
K8-bit signed integer constant for logical instructions
L8-bit adjusted signed integer constant for compare pseudo-ops
M6-bit unsigned integer constant for shift counts
N9-bit signed integer constant for load and store postincrements
OThe constant zero
P0 or -1 for dep instruction
QNon-volatile memory for floating-point loads and stores
RInteger constant in the range 1 to 4 for shladd instruction
SMemory operand except postincrement and postdecrement. This is now roughly the same as ‘m’ when not used together with ‘<’ or ‘>’.
RspRfbRsb‘$sp’, ‘$fb’, ‘$sb’.
RcrAny control register, when they’re 16 bits wide (nothing if control registers are 24 bits wide)
RclAny control register, when they’re 24 bits wide.
R0wR1wR2wR3w$r0, $r1, $r2, $r3.
R02$r0 or $r2, or $r2r0 for 32 bit values.
R13$r1 or $r3, or $r3r1 for 32 bit values.
RdiA register that can hold a 64 bit value.
Rhl$r0 or $r1 (registers with addressable high/low bytes)
R23$r2 or $r3
RaaAddress registers
RawAddress registers when they’re 16 bits wide.
RalAddress registers when they’re 24 bits wide.
RqiRegisters that can hold QI values.
RadRegisters that can be used with displacements ($a0, $a1, $sb).
RsiRegisters that can hold 32 bit values.
RhiRegisters that can hold 16 bit values.
RhcRegisters chat can hold 16 bit values, including all control registers.
Rra$r0 through R1, plus $a0 and $a1.
RflThe flags register.
RmmThe memory-based pseudo-registers $mem0 through $mem15.
RpiRegisters that can hold pointers (16 bit registers for r8c, m16c; 24 bit registers for m32cm, m32c).
RpaMatches multiple registers in a PARALLEL to form a larger register. Used to match function return values.
Is3-8 … 7
IS1-128 … 127
IS2-32768 … 32767
IU20 … 65535
In4-8 … -1 or 1 … 8
In5-16 … -1 or 1 … 16
In6-32 … -1 or 1 … 32
IM2-65536 … -1
IlbAn 8 bit value with exactly one bit set.
IlwA 16 bit value with exactly one bit set.
SdThe common src/dest memory addressing modes.
SaMemory addressed using $a0 or $a1.
SiMemory addressed with immediate addresses.
SsMemory addressed using the stack pointer ($sp).
SfMemory addressed using the frame base register ($fb).
SsMemory addressed using the small base register ($sb).
S1$r1h
dA general register (r0 to r31).
zA status register (rmsr, $fcc1 to $fcc7).
dA general-purpose register. This is equivalent to r unless
generating MIPS16 code, in which case the MIPS16 register set is used.
fA floating-point register (if available).
hFormerly the hi register. This constraint is no longer supported.
lThe lo register. Use this register to store values that are
no bigger than a word.
xThe concatenated hi and lo registers. Use this register
to store doubleword values.
cA register suitable for use in an indirect jump. This will always be
$25 for -mabicalls.
vRegister $3. Do not use this constraint in new code;
it is retained only for compatibility with glibc.
yEquivalent to r; retained for backwards compatibility.
zA floating-point condition code register.
IA signed 16-bit constant (for arithmetic instructions).
JInteger zero.
KAn unsigned 16-bit constant (for logic instructions).
LA signed 32-bit constant in which the lower 16 bits are zero.
Such constants can be loaded using lui.
MA constant that cannot be loaded using lui, addiu
or ori.
NA constant in the range -65535 to -1 (inclusive).
OA signed 15-bit constant.
PA constant in the range 1 to 65535 (inclusive).
GFloating-point zero.
RAn address that can be used in a non-macro load or store.
ZCA memory operand whose address is formed by a base register and offset
that is suitable for use in instructions with the same addressing mode
as ll and sc.
ZDAn address suitable for a prefetch instruction, or for any other
instruction with the same addressing mode as prefetch.
aAddress register
dData register
f68881 floating-point register, if available
IInteger in the range 1 to 8
J16-bit signed number
KSigned number whose magnitude is greater than 0x80
LInteger in the range -8 to -1
MSigned number whose magnitude is greater than 0x100
NRange 24 to 31, rotatert:SI 8 to 1 expressed as rotate
O16 (for rotate using swap)
PRange 8 to 15, rotatert:HI 8 to 1 expressed as rotate
RNumbers that mov3q can handle
GFloating point constant that is not a 68881 constant
SOperands that satisfy ’m’ when -mpcrel is in effect
TOperands that satisfy ’s’ when -mpcrel is not in effect
QAddress register indirect addressing mode
URegister offset addressing
Wconst_call_operand
Cssymbol_ref or const
Ciconst_int
C0const_int 0
CjRange of signed numbers that don’t fit in 16 bits
CmvqIntegers valid for mvq
CapswIntegers valid for a moveq followed by a swap
CmvzIntegers valid for mvz
CmvsIntegers valid for mvs
Appush_operand
AcNon-register operands allowed in clr
AAn absolute address
BAn offset address
WA register indirect memory operand
IA constant in the range of 0 to 255.
NA constant in the range of 0 to -255.
R12Register R12.
R13Register R13.
KInteger constant 1.
LInteger constant -1^20..1^19.
MInteger constant 1-4.
YaMemory references which do not require an extended MOVX instruction.
YlMemory reference, labels only.
YsMemory reference, stack only.
wLOW register class $r0 to $r7 constraint for V3/V3M ISA.
lLOW register class $r0 to $r7.
dMIDDLE register class $r0 to $r11, $r16 to $r19.
hHIGH register class $r12 to $r14, $r20 to $r31.
tTemporary assist register $ta (i.e. $r15).
kStack register $sp.
Iu03Unsigned immediate 3-bit value.
In03Negative immediate 3-bit value in the range of -7–0.
Iu04Unsigned immediate 4-bit value.
Is05Signed immediate 5-bit value.
Iu05Unsigned immediate 5-bit value.
In05Negative immediate 5-bit value in the range of -31–0.
Ip05Unsigned immediate 5-bit value for movpi45 instruction with range 16–47.
Iu06Unsigned immediate 6-bit value constraint for addri36.sp instruction.
Iu08Unsigned immediate 8-bit value.
Iu09Unsigned immediate 9-bit value.
Is10Signed immediate 10-bit value.
Is11Signed immediate 11-bit value.
Is15Signed immediate 15-bit value.
Iu15Unsigned immediate 15-bit value.
Ic15A constant which is not in the range of imm15u but ok for bclr instruction.
Ie15A constant which is not in the range of imm15u but ok for bset instruction.
It15A constant which is not in the range of imm15u but ok for btgl instruction.
Ii15A constant whose compliment value is in the range of imm15u and ok for bitci instruction.
Is16Signed immediate 16-bit value.
Is17Signed immediate 17-bit value.
Is19Signed immediate 19-bit value.
Is20Signed immediate 20-bit value.
IhigThe immediate value that can be simply set high 20-bit.
IzebThe immediate value 0xff.
IzehThe immediate value 0xffff.
IxlsThe immediate value 0x01.
Ix11The immediate value 0x7ff.
IbmsThe immediate value with power of 2.
IfexThe immediate value with power of 2 minus 1.
U33Memory constraint for 333 format.
U45Memory constraint for 45 format.
U37Memory constraint for 37 format.
IInteger that is valid as an immediate operand in an instruction taking a signed 16-bit number. Range -32768 to 32767.
JInteger that is valid as an immediate operand in an instruction taking an unsigned 16-bit number. Range 0 to 65535.
KInteger that is valid as an immediate operand in an instruction taking only the upper 16-bits of a 32-bit number. Range 32-bit numbers with the lower 16-bits being 0.
LInteger that is valid as an immediate operand for a shift instruction. Range 0 to 31.
MInteger that is valid as an immediate operand for
only the value 0. Can be used in conjunction with
the format modifier z to use r0
instead of 0 in the assembly output.
NInteger that is valid as an immediate operand for a custom instruction opcode. Range 0 to 255.
PAn immediate operand for R2 andchi/andci instructions.
SMatches immediates which are addresses in the small
data section and therefore can be added to gp
as a 16-bit immediate to re-create their 32-bit value.
UMatches constants suitable as an operand for the rdprs and cache instructions.
vA memory operand suitable for Nios II R2 load/store exclusive instructions.
wA memory operand suitable for load/store IO and cache instructions.
aFloating point registers AC0 through AC3. These can be loaded from/to memory with a single instruction.
dOdd numbered general registers (R1, R3, R5). These are used for 16-bit multiply operations.
fAny of the floating point registers (AC0 through AC5).
GFloating point constant 0.
IAn integer constant that fits in 16 bits.
JAn integer constant whose low order 16 bits are zero.
KAn integer constant that does not meet the constraints for codes ‘I’ or ‘J’.
LThe integer constant 1.
MThe integer constant -1.
NThe integer constant 0.
OInteger constants -4 through -1 and 1 through 4; shifts by these amounts are handled as multiple single-bit shifts rather than a single variable-length shift.
QA memory reference which requires an additional word (address or offset) after the opcode.
RA memory reference that is encoded within the opcode.
bAddress base register
dFloating point register (containing 64-bit value)
fFloating point register (containing 32-bit value)
vAltivec vector register
waAny VSX register if the -mvsx option was used or NO_REGS.
When using any of the register constraints (wa, wd,
wf, wg, wh, wi, wj, wk,
wl, wm, wo, wp, wq, ws,
wt, wu, wv, ww, or wy)
that take VSX registers, you must use %x<n> in the template so
that the correct register is used. Otherwise the register number
output in the assembly file will be incorrect if an Altivec register
is an operand of a VSX instruction that expects VSX register
numbering.
asm ("xvadddp %x0,%x1,%x2"
: "=wa" (v1)
: "wa" (v2), "wa" (v3));
is correct, but:
asm ("xvadddp %0,%1,%2"
: "=wa" (v1)
: "wa" (v2), "wa" (v3));
is not correct.
If an instruction only takes Altivec registers, you do not want to use
%x<n>.
asm ("xsaddqp %0,%1,%2"
: "=v" (v1)
: "v" (v2), "v" (v3));
is correct because the xsaddqp instruction only takes Altivec
registers, while:
asm ("xsaddqp %x0,%x1,%x2"
: "=v" (v1)
: "v" (v2), "v" (v3));
is incorrect.
wbAltivec register if -mcpu=power9 is used or NO_REGS.
wdVSX vector register to hold vector double data or NO_REGS.
weVSX register if the -mcpu=power9 and -m64 options were used or NO_REGS.
wfVSX vector register to hold vector float data or NO_REGS.
wgIf -mmfpgpr was used, a floating point register or NO_REGS.
whFloating point register if direct moves are available, or NO_REGS.
wiFP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.
wjFP or VSX register to hold 64-bit integers for direct moves or NO_REGS.
wkFP or VSX register to hold 64-bit doubles for direct moves or NO_REGS.
wlFloating point register if the LFIWAX instruction is enabled or NO_REGS.
wmVSX register if direct move instructions are enabled, or NO_REGS.
wnNo register (NO_REGS).
woVSX register to use for ISA 3.0 vector instructions, or NO_REGS.
wpVSX register to use for IEEE 128-bit floating point TFmode, or NO_REGS.
wqVSX register to use for IEEE 128-bit floating point, or NO_REGS.
wrGeneral purpose register if 64-bit instructions are enabled or NO_REGS.
wsVSX vector register to hold scalar double values or NO_REGS.
wtVSX vector register to hold 128 bit integer or NO_REGS.
wuAltivec register to use for float/32-bit int loads/stores or NO_REGS.
wvAltivec register to use for double loads/stores or NO_REGS.
wwFP or VSX register to perform float operations under -mvsx or NO_REGS.
wxFloating point register if the STFIWX instruction is enabled or NO_REGS.
wyFP or VSX register to perform ISA 2.07 float ops or NO_REGS.
wzFloating point register if the LFIWZX instruction is enabled or NO_REGS.
wAAddress base register if 64-bit instructions are enabled or NO_REGS.
wBSigned 5-bit constant integer that can be loaded into an altivec register.
wDInt constant that is the element number of the 64-bit scalar in a vector.
wEVector constant that can be loaded with the XXSPLTIB instruction.
wFMemory operand suitable for power9 fusion load/stores.
wGMemory operand suitable for TOC fusion memory references.
wHAltivec register if -mvsx-small-integer.
wIFloating point register if -mvsx-small-integer.
wJFP register if -mvsx-small-integer and -mpower9-vector.
wKAltivec register if -mvsx-small-integer and -mpower9-vector.
wLInt constant that is the element number that the MFVSRLD instruction. targets.
wMMatch vector constant with all 1’s if the XXLORC instruction is available.
wOA memory operand suitable for the ISA 3.0 vector d-form instructions.
wQA memory address that will work with the lq and stq
instructions.
wSVector constant that can be loaded with XXSPLTIB & sign extension.
h‘MQ’, ‘CTR’, or ‘LINK’ register
c‘CTR’ register
l‘LINK’ register
x‘CR’ register (condition register) number 0
y‘CR’ register (condition register)
z‘XER[CA]’ carry bit (part of the XER register)
ISigned 16-bit constant
JUnsigned 16-bit constant shifted left 16 bits (use ‘L’ instead for
SImode constants)
KUnsigned 16-bit constant
LSigned 16-bit constant shifted left 16 bits
MConstant larger than 31
NExact power of 2
OZero
PConstant whose negation is a signed 16-bit constant
GFloating point constant that can be loaded into a register with one instruction per word
HInteger/Floating point constant that can be loaded into a register using three instructions
mMemory operand.
Normally, m does not allow addresses that update the base register.
If ‘<’ or ‘>’ constraint is also used, they are allowed and
therefore on PowerPC targets in that case it is only safe
to use ‘m<>’ in an asm statement if that asm statement
accesses the operand exactly once. The asm statement must also
use ‘%U<opno>’ as a placeholder for the “update” flag in the
corresponding load or store instruction. For example:
asm ("st%U0 %1,%0" : "=m<>" (mem) : "r" (val));
is correct but:
asm ("st %1,%0" : "=m<>" (mem) : "r" (val));
is not.
esA “stable” memory operand; that is, one which does not include any automodification of the base register. This used to be useful when ‘m’ allowed automodification of the base register, but as those are now only allowed when ‘<’ or ‘>’ is used, ‘es’ is basically the same as ‘m’ without ‘<’ and ‘>’.
QMemory operand that is an offset from a register (it is usually better
to use ‘m’ or ‘es’ in asm statements)
ZMemory operand that is an indexed or indirect from a register (it is
usually better to use ‘m’ or ‘es’ in asm statements)
RAIX TOC entry
aAddress operand that is an indexed or indirect from a register (‘p’ is
preferable for asm statements)
USystem V Release 4 small data area reference
WVector constant that does not require memory
jVector constant that is all zeros.
Int3An integer constant in the range 1 … 7.
Int8An integer constant in the range 0 … 255.
JAn integer constant in the range -255 … 0
KThe integer constant 1.
LThe integer constant -1.
MThe integer constant 0.
NThe integer constant 2.
OThe integer constant -2.
PAn integer constant in the range 1 … 15.
QbiThe built-in compare types–eq, ne, gtu, ltu, geu, and leu.
QscThe synthetic compare types–gt, lt, ge, and le.
WabA memory reference with an absolute address.
WbcA memory reference using BC as a base register, with an optional offset.
WcaA memory reference using AX, BC, DE, or HL for the address, for calls.
WcvA memory reference using any 16-bit register pair for the address, for calls.
Wd2A memory reference using DE as a base register, with an optional offset.
WdeA memory reference using DE as a base register, without any offset.
WfrAny memory reference to an address in the far address space.
Wh1A memory reference using HL as a base register, with an optional one-byte offset.
WhbA memory reference using HL as a base register, with B or C as the index register.
WhlA memory reference using HL as a base register, without any offset.
Ws1A memory reference using SP as a base register, with an optional one-byte offset.
YAny memory reference to an address in the near address space.
AThe AX register.
BThe BC register.
DThe DE register.
RA through L registers.
SThe SP register.
TThe HL register.
Z08WThe 16-bit R8 register.
Z10WThe 16-bit R10 register.
ZintThe registers reserved for interrupts (R24 to R31).
aThe A register.
bThe B register.
cThe C register.
dThe D register.
eThe E register.
hThe H register.
lThe L register.
vThe virtual registers.
wThe PSW register.
xThe X register.
fA floating-point register (if availiable).
IAn I-type 12-bit signed immediate.
JInteger zero.
KA 5-bit unsigned immediate for CSR access instructions.
AAn address that is held in a general-purpose register.
QAn address which does not involve register indirect addressing or pre/post increment/decrement addressing.
SymbolA symbol reference.
Int08A constant in the range -256 to 255, inclusive.
Sint08A constant in the range -128 to 127, inclusive.
Sint16A constant in the range -32768 to 32767, inclusive.
Sint24A constant in the range -8388608 to 8388607, inclusive.
Uint04A constant in the range 0 to 15, inclusive.
aAddress register (general purpose register except r0)
cCondition code register
dData register (arbitrary general purpose register)
fFloating-point register
IUnsigned 8-bit constant (0–255)
JUnsigned 12-bit constant (0–4095)
KSigned 16-bit constant (-32768–32767)
LValue appropriate as displacement.
(0..4095)for short displacement
(-524288..524287)for long displacement
MConstant integer with a value of 0x7fffffff.
NMultiple letter constraint followed by 4 parameter letters.
0..9:number of the part counting from most to least significant
H,Q:mode of the part
D,S,H:mode of the containing operand
0,F:value of the other parts (F—all bits set)
The constraint matches if the specified part of a constant has a value different from its other parts.
QMemory reference without index register and with short displacement.
RMemory reference with index register and short displacement.
SMemory reference without index register but with long displacement.
TMemory reference with index register and long displacement.
UPointer with short displacement.
WPointer with long displacement.
YShift count operand.
fFloating-point register on the SPARC-V8 architecture and lower floating-point register on the SPARC-V9 architecture.
eFloating-point register. It is equivalent to ‘f’ on the SPARC-V8 architecture and contains both lower and upper floating-point registers on the SPARC-V9 architecture.
cFloating-point condition code register.
dLower floating-point register. It is only valid on the SPARC-V9 architecture when the Visual Instruction Set is available.
bFloating-point register. It is only valid on the SPARC-V9 architecture when the Visual Instruction Set is available.
h64-bit global or out register for the SPARC-V8+ architecture.
CThe constant all-ones, for floating-point.
ASigned 5-bit constant
DA vector constant
ISigned 13-bit constant
JZero
K32-bit constant with the low 12 bits clear (a constant that can be
loaded with the sethi instruction)
LA constant in the range supported by movcc instructions (11-bit
signed immediate)
MA constant in the range supported by movrcc instructions (10-bit
signed immediate)
NSame as ‘K’, except that it verifies that bits that are not in the
lower 32-bit range are all zero. Must be used instead of ‘K’ for
modes wider than SImode
OThe constant 4096
GFloating-point zero
HSigned 13-bit constant, sign-extended to 32 or 64 bits
PThe constant -1
QFloating-point constant whose integral representation can be moved into an integer register using a single sethi instruction
RFloating-point constant whose integral representation can be moved into an integer register using a single mov instruction
SFloating-point constant whose integral representation can be moved into an integer register using a high/lo_sum instruction sequence
TMemory address aligned to an 8-byte boundary
UEven register
WMemory address for ‘e’ constraint registers
wMemory address with only a base register
YVector zero
aAn immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 64 bit value.
cAn immediate for and/xor/or instructions. const_int is treated as a 64 bit value.
dAn immediate for the iohl instruction. const_int is treated as a 64 bit value.
fAn immediate which can be loaded with fsmbi.
AAn immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 32 bit value.
BAn immediate for most arithmetic instructions. const_int is treated as a 32 bit value.
CAn immediate for and/xor/or instructions. const_int is treated as a 32 bit value.
DAn immediate for the iohl instruction. const_int is treated as a 32 bit value.
IA constant in the range [-64, 63] for shift/rotate instructions.
JAn unsigned 7-bit constant for conversion/nop/channel instructions.
KA signed 10-bit constant for most arithmetic instructions.
MA signed 16 bit immediate for stop.
NAn unsigned 16-bit constant for iohl and fsmbi.
OAn unsigned 7-bit constant whose 3 least significant bits are 0.
PAn unsigned 3-bit constant for 16-byte rotates and shifts
RCall operand, reg, for indirect calls
SCall operand, symbol, for relative calls.
TCall operand, const_int, for absolute calls.
UAn immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is sign extended to 128 bit.
WAn immediate for shift and rotate instructions. const_int is treated as a 32 bit value.
YAn immediate for and/xor/or instructions. const_int is sign extended as a 128 bit.
ZAn immediate for the iohl instruction. const_int is sign extended to 128 bit.
aRegister file A (A0–A31).
bRegister file B (B0–B31).
APredicate registers in register file A (A0–A2 on C64X and higher, A1 and A2 otherwise).
BPredicate registers in register file B (B0–B2).
CA call-used register in register file B (B0–B9, B16–B31).
DaRegister file A, excluding predicate registers (A3–A31, plus A0 if not C64X or higher).
DbRegister file B, excluding predicate registers (B3–B31).
Iu4Integer constant in the range 0 … 15.
Iu5Integer constant in the range 0 … 31.
In5Integer constant in the range -31 … 0.
Is5Integer constant in the range -16 … 15.
I5xInteger constant that can be the operand of an ADDA or a SUBA insn.
IuBInteger constant in the range 0 … 65535.
IsBInteger constant in the range -32768 … 32767.
IsCInteger constant in the range -2^{20} … 2^{20} - 1.
JcInteger constant that is a valid mask for the clr instruction.
JsInteger constant that is a valid mask for the set instruction.
QMemory location with A base register.
RMemory location with B base register.
ZRegister B14 (aka DP).
R00R01R02R03R04R05R06R07R08R09R10Each of these represents a register constraint for an individual register, from r0 to r10.
ISigned 8-bit integer constant.
JSigned 16-bit integer constant.
KUnsigned 16-bit integer constant.
LInteger constant that fits in one signed byte when incremented by one (-129 … 126).
mMemory operand. If used together with ‘<’ or ‘>’, the operand can have postincrement which requires printing with ‘%In’ and ‘%in’ on TILE-Gx. For example:
asm ("st_add %I0,%1,%i0" : "=m<>" (*mem) : "r" (val));
MA bit mask suitable for the BFINS instruction.
NInteger constant that is a byte tiled out eight times.
OThe integer zero constant.
PInteger constant that is a sign-extended byte tiled out as four shorts.
QInteger constant that fits in one signed byte when incremented (-129 … 126), but excluding -1.
SInteger constant that has all 1 bits consecutive and starting at bit 0.
TA 16-bit fragment of a got, tls, or pc-relative reference.
UMemory operand except postincrement. This is roughly the same as ‘m’ when not used together with ‘<’ or ‘>’.
WAn 8-element vector constant with identical elements.
YA 4-element vector constant with identical elements.
Z0The integer constant 0xffffffff.
Z1The integer constant 0xffffffff00000000.
R00R01R02R03R04R05R06R07R08R09R10Each of these represents a register constraint for an individual register, from r0 to r10.
ISigned 8-bit integer constant.
JSigned 16-bit integer constant.
KNonzero integer constant with low 16 bits zero.
LInteger constant that fits in one signed byte when incremented by one (-129 … 126).
mMemory operand. If used together with ‘<’ or ‘>’, the operand can have postincrement which requires printing with ‘%In’ and ‘%in’ on TILEPro. For example:
asm ("swadd %I0,%1,%i0" : "=m<>" (mem) : "r" (val));
MA bit mask suitable for the MM instruction.
NInteger constant that is a byte tiled out four times.
OThe integer zero constant.
PInteger constant that is a sign-extended byte tiled out as two shorts.
QInteger constant that fits in one signed byte when incremented (-129 … 126), but excluding -1.
TA symbolic operand, or a 16-bit fragment of a got, tls, or pc-relative reference.
UMemory operand except postincrement. This is roughly the same as ‘m’ when not used together with ‘<’ or ‘>’.
WA 4-element vector constant with identical elements.
YA 2-element vector constant with identical elements.
bEAM register mdb
cEAM register mdc
fFloating point register
lGeneral register, but not r29, r30 and r31
tRegister r1
uRegister r2
vRegister r3
GFloating-point constant 0.0
JInteger constant in the range 0 .. 65535 (16-bit immediate)
KInteger constant in the range 1 .. 31 (5-bit immediate)
LInteger constant in the range -65535 .. -1 (16-bit negative immediate)
MInteger constant -1
OInteger constant 0
PInteger constant 32
RLegacy register—the eight integer registers available on all
i386 processors (a, b, c, d,
si, di, bp, sp).
qAny register accessible as rl. In 32-bit mode, a,
b, c, and d; in 64-bit mode, any integer register.
QAny register accessible as rh: a, b,
c, and d.
aThe a register.
bThe b register.
cThe c register.
dThe d register.
SThe si register.
DThe di register.
AThe a and d registers. This class is used for instructions
that return double word results in the ax:dx register pair. Single
word values will be allocated either in ax or dx.
For example on i386 the following implements rdtsc:
unsigned long long rdtsc (void)
{
unsigned long long tick;
__asm__ __volatile__("rdtsc":"=A"(tick));
return tick;
}
This is not correct on x86-64 as it would allocate tick in either ax
or dx. You have to use the following variant instead:
unsigned long long rdtsc (void)
{
unsigned int tickl, tickh;
__asm__ __volatile__("rdtsc":"=a"(tickl),"=d"(tickh));
return ((unsigned long long)tickh << 32)|tickl;
}
fAny 80387 floating-point (stack) register.
tTop of 80387 floating-point stack (%st(0)).
uSecond from top of 80387 floating-point stack (%st(1)).
yAny MMX register.
xAny SSE register.
YzFirst SSE register (%xmm0).
IInteger constant in the range 0 … 31, for 32-bit shifts.
JInteger constant in the range 0 … 63, for 64-bit shifts.
KSigned 8-bit integer constant.
L0xFF or 0xFFFF, for andsi as a zero-extending move.
M0, 1, 2, or 3 (shifts for the lea instruction).
NUnsigned 8-bit integer constant (for in and out
instructions).
GStandard 80387 floating point constant.
CSSE constant zero operand.
e32-bit signed integer constant, or a symbolic reference known to fit that range (for immediate operands in sign-extending x86-64 instructions).
Z32-bit unsigned integer constant, or a symbolic reference known to fit that range (for immediate operands in zero-extending x86-64 instructions).
aRegister r0.
bRegister r1.
cRegister r2.
dRegister r8.
eRegisters r0 through r7.
tRegisters r0 and r1.
yThe carry register.
zRegisters r8 and r9.
IA constant between 0 and 3 inclusive.
JA constant that has exactly one bit set.
KA constant that has exactly one bit clear.
LA constant between 0 and 255 inclusive.
MA constant between -255 and 0 inclusive.
NA constant between -3 and 0 inclusive.
OA constant between 1 and 4 inclusive.
PA constant between -4 and -1 inclusive.
QA memory reference that is a stack push.
RA memory reference that is a stack pop.
SA memory reference that refers to a constant address of known value.
TThe register indicated by Rx (not implemented yet).
UA constant that is not between 2 and 15 inclusive.
ZThe constant 0.
aGeneral-purpose 32-bit register
bOne-bit boolean register
AMAC16 40-bit accumulator register
ISigned 12-bit integer constant, for use in MOVI instructions
JSigned 8-bit integer constant, for use in ADDI instructions
KInteger constant valid for BccI instructions
LUnsigned constant valid for BccUI instructions
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