config ARCH_ZYNQ
	bool "Xilinx Zynq ARM Cortex A9 Platform" if ARCH_MULTI_V7
	select ARCH_HAS_CPUFREQ
	select ARCH_HAS_OPP
	select ARCH_REQUIRE_GPIOLIB
	select ARCH_SUPPORTS_BIG_ENDIAN
	select ARM_AMBA
	select ARM_GIC
	select ARM_GLOBAL_TIMER if !CPU_FREQ
	select CACHE_L2X0
	select CADENCE_TTC_TIMER
	select GENERIC_ALLOCATOR
	select GENERIC_CLOCKEVENTS
	select HAVE_ARM_SCU if SMP
	select HAVE_ARM_TWD if SMP
	select HAVE_SMP
	select ICST
	select MFD_SYSCON
	select MIGHT_HAVE_CACHE_L2X0
	select MIGHT_HAVE_PCI
	help
	  Support for Xilinx Zynq ARM Cortex A9 Platform

if ARCH_ZYNQ

menu "Xilinx Specific Options"

config XILINX_PREFETCH
	bool "Cache Prefetch"
	default y
	help
	  This option turns on L1 & L2 cache prefetching to get the best performance
	  in many cases. This may not always be the best performance depending on
	  the usage.

config XILINX_AXIPCIE
	bool "Xilinx AXI PCIe host bridge support"
	select PCI
	select ARCH_SUPPORTS_MSI
	help
	  Say 'Y' here if you want kernel to support the Xilinx AXI PCIe
	  Host Bridge. This supports Message Signal Interrupts (MSI), if you
	  want to use this feature select CONFIG_PCI_MSI from 'Bus Support ->'.

endmenu

endif
