Llvm_target.TargetMachine

`sig type t val create : triple:string -> ?cpu:string -> ?features:string -> ?level:Llvm_target.CodeGenOptLevel.t -> ?reloc_mode:Llvm_target.RelocMode.t -> ?code_model:Llvm_target.CodeModel.t -> Llvm_target.Target.t -> Llvm_target.TargetMachine.t val target : Llvm_target.TargetMachine.t -> Llvm_target.Target.t val triple : Llvm_target.TargetMachine.t -> string val cpu : Llvm_target.TargetMachine.t -> string val features : Llvm_target.TargetMachine.t -> string val data_layout : Llvm_target.TargetMachine.t -> Llvm_target.DataLayout.t val add_analysis_passes : [< Llvm.PassManager.any ] Llvm.PassManager.t -> Llvm_target.TargetMachine.t -> unit val set_verbose_asm : bool -> Llvm_target.TargetMachine.t -> unit val emit_to_file : Llvm.llmodule -> Llvm_target.CodeGenFileType.t -> string -> Llvm_target.TargetMachine.t -> unit val emit_to_memory_buffer : Llvm.llmodule -> Llvm_target.CodeGenFileType.t -> Llvm_target.TargetMachine.t -> Llvm.llmemorybuffer end`