core::arch::arm - Rust
Description: API documentation for the Rust `arm` mod in crate `core`.
Keywords: rust, rustlang, rust-lang, arm

# [−][src]Module core::arch::arm

🔬 This is a nightly-only experimental API. (`stdsimd` #27731)
This is supported on ARM only.

Platform-specific intrinsics for the `arm` platform.

See the module documentation for more details.

## Structs

APSR | ExperimentalARM Application Program Status Register
ISH | ExperimentalARM Inner Shareable is the required shareability domain, reads and writes are the required access types
ISHST | ExperimentalARM Inner Shareable is the required shareability domain, writes are the required access type
NSH | ExperimentalARM Non-shareable is the required shareability domain, reads and writes are the required access types
NSHST | ExperimentalARM Non-shareable is the required shareability domain, writes are the required access type
OSH | ExperimentalARM Outer Shareable is the required shareability domain, reads and writes are the required access types
OSHST | ExperimentalARM Outer Shareable is the required shareability domain, writes are the required access type
ST | ExperimentalARM Full system is the required shareability domain, writes are the required access type
SY | ExperimentalARM Full system is the required shareability domain, reads and writes are the required access types
float32x2_t | ExperimentalARM ARM-specific 64-bit wide vector of two packed `f32`.
float32x4_t | ExperimentalARM ARM-specific 128-bit wide vector of four packed `f32`.
int16x2_t | ExperimentalARM ARM-specific 32-bit wide vector of two packed `i16`.
int16x4_t | ExperimentalARM ARM-specific 64-bit wide vector of four packed `i16`.
int16x8_t | ExperimentalARM ARM-specific 128-bit wide vector of eight packed `i16`.
int32x2_t | ExperimentalARM ARM-specific 64-bit wide vector of two packed `i32`.
int32x4_t | ExperimentalARM ARM-specific 128-bit wide vector of four packed `i32`.
int64x1_t | ExperimentalARM ARM-specific 64-bit wide vector of one packed `i64`.
int64x2_t | ExperimentalARM ARM-specific 128-bit wide vector of two packed `i64`.
int8x4_t | ExperimentalARM ARM-specific 32-bit wide vector of four packed `i8`.
int8x8_t | ExperimentalARM ARM-specific 64-bit wide vector of eight packed `i8`.
int8x16_t | ExperimentalARM ARM-specific 128-bit wide vector of sixteen packed `i8`.
int8x8x2_t | ExperimentalARM ARM-specific type containing two `int8x8_t` vectors.
int8x8x3_t | ExperimentalARM ARM-specific type containing three `int8x8_t` vectors.
int8x8x4_t | ExperimentalARM ARM-specific type containing four `int8x8_t` vectors.
poly16x4_t | ExperimentalARM ARM-specific 64-bit wide vector of four packed `u16`.
poly16x8_t | ExperimentalARM ARM-specific 128-bit wide vector of eight packed `u16`.
poly8x8_t | ExperimentalARM ARM-specific 64-bit wide polynomial vector of eight packed `u8`.
poly8x16_t | ExperimentalARM ARM-specific 128-bit wide vector of sixteen packed `u8`.
poly8x8x2_t | ExperimentalARM ARM-specific type containing two `poly8x8_t` vectors.
poly8x8x3_t | ExperimentalARM ARM-specific type containing three `poly8x8_t` vectors.
poly8x8x4_t | ExperimentalARM ARM-specific type containing four `poly8x8_t` vectors.
uint16x2_t | ExperimentalARM ARM-specific 32-bit wide vector of two packed `u16`.
uint16x4_t | ExperimentalARM ARM-specific 64-bit wide vector of four packed `u16`.
uint16x8_t | ExperimentalARM ARM-specific 128-bit wide vector of eight packed `u16`.
uint32x2_t | ExperimentalARM ARM-specific 64-bit wide vector of two packed `u32`.
uint32x4_t | ExperimentalARM ARM-specific 128-bit wide vector of four packed `u32`.
uint64x1_t | ExperimentalARM ARM-specific 64-bit wide vector of one packed `u64`.
uint64x2_t | ExperimentalARM ARM-specific 128-bit wide vector of two packed `u64`.
uint8x4_t | ExperimentalARM ARM-specific 32-bit wide vector of four packed `u8`.
uint8x8_t | ExperimentalARM ARM-specific 64-bit wide vector of eight packed `u8`.
uint8x16_t | ExperimentalARM ARM-specific 128-bit wide vector of sixteen packed `u8`.
uint8x8x2_t | ExperimentalARM ARM-specific type containing two `uint8x8_t` vectors.
uint8x8x3_t | ExperimentalARM ARM-specific type containing three `uint8x8_t` vectors.
uint8x8x4_t | ExperimentalARM ARM-specific type containing four `uint8x8_t` vectors.

## Functions

__breakpoint⚠ | ExperimentalARM Inserts a breakpoint instruction.
__clrex⚠ | ExperimentalARM Removes the exclusive lock created by LDREX
__dbg⚠ | ExperimentalARM Generates a DBG instruction.
__dmb⚠ | ExperimentalARM Generates a DMB (data memory barrier) instruction or equivalent CP15 instruction.
__dsb⚠ | ExperimentalARM Generates a DSB (data synchronization barrier) instruction or equivalent CP15 instruction.
__isb⚠ | ExperimentalARM Generates an ISB (instruction synchronization barrier) instruction or equivalent CP15 instruction.
__ldrex⚠ | ExperimentalARM Executes a exclusive LDR instruction for 32 bit value.
__ldrexb⚠ | ExperimentalARM Executes a exclusive LDR instruction for 8 bit value.
__ldrexh⚠ | ExperimentalARM Executes a exclusive LDR instruction for 16 bit value.
__nop⚠ | ExperimentalARM Generates an unspecified no-op instruction.
__qadd⚠ | ExperimentalARM Signed saturating addition
__qadd8⚠ | ExperimentalARM Saturating four 8-bit integer additions
__qadd16⚠ | ExperimentalARM Saturating two 16-bit integer additions
__qasx⚠ | ExperimentalARM Returns the 16-bit signed saturated equivalent of
__qdbl⚠ | ExperimentalARM Insert a QADD instruction
__qsax⚠ | ExperimentalARM Returns the 16-bit signed saturated equivalent of
__qsub⚠ | ExperimentalARM Signed saturating subtraction
__qsub8⚠ | ExperimentalARM Saturating two 8-bit integer subtraction
__qsub16⚠ | ExperimentalARM Saturating two 16-bit integer subtraction
__rsr⚠ | ExperimentalARM Reads a 32-bit system register
__rsrp⚠ | ExperimentalARM Reads a system register containing an address
__sadd8⚠ | ExperimentalARM Returns the 8-bit signed saturated equivalent of
__sadd16⚠ | ExperimentalARM Returns the 16-bit signed saturated equivalent of
__sasx⚠ | ExperimentalARM Returns the 16-bit signed equivalent of
__sel⚠ | ExperimentalARM Select bytes from each operand according to APSR GE flags
__sev⚠ | ExperimentalARM Generates a SEV (send a global event) hint instruction.
__shadd8⚠ | ExperimentalARM Signed halving parallel byte-wise addition.
__shadd16⚠ | ExperimentalARM Signed halving parallel halfword-wise addition.
__shsub8⚠ | ExperimentalARM Signed halving parallel byte-wise subtraction.
__shsub16⚠ | ExperimentalARM Signed halving parallel halfword-wise subtraction.
__smlabb⚠ | ExperimentalARM Insert a SMLABB instruction
__smlabt⚠ | ExperimentalARM Insert a SMLABT instruction
__smlad⚠ | ExperimentalARM Dual 16-bit Signed Multiply with Addition of products and 32-bit accumulation.
__smlatb⚠ | ExperimentalARM Insert a SMLATB instruction
__smlatt⚠ | ExperimentalARM Insert a SMLATT instruction
__smlawb⚠ | ExperimentalARM Insert a SMLAWB instruction
__smlawt⚠ | ExperimentalARM Insert a SMLAWT instruction
__smlsd⚠ | ExperimentalARM Dual 16-bit Signed Multiply with Subtraction of products and 32-bit accumulation and overflow detection.
__smuad⚠ | ExperimentalARM Signed Dual Multiply Add.
__smuadx⚠ | ExperimentalARM Signed Dual Multiply Add Reversed.
__smulbb⚠ | ExperimentalARM Insert a SMULBB instruction
__smulbt⚠ | ExperimentalARM Insert a SMULTB instruction
__smultb⚠ | ExperimentalARM Insert a SMULTB instruction
__smultt⚠ | ExperimentalARM Insert a SMULTT instruction
__smulwb⚠ | ExperimentalARM Insert a SMULWB instruction
__smulwt⚠ | ExperimentalARM Insert a SMULWT instruction
__smusd⚠ | ExperimentalARM Signed Dual Multiply Subtract.
__smusdx⚠ | ExperimentalARM Signed Dual Multiply Subtract Reversed.
__ssub8⚠ | ExperimentalARM Inserts a `SSUB8` instruction.
__strex⚠ | ExperimentalARM Executes a exclusive STR instruction for 32 bit values
__strexb⚠ | ExperimentalARM Executes a exclusive STR instruction for 8 bit values
__strexh⚠ | ExperimentalARM Executes a exclusive STR instruction for 16 bit values
__usad8⚠ | ExperimentalARM Sum of 8-bit absolute differences.
__usada8⚠ | ExperimentalARM Sum of 8-bit absolute differences and constant.
__usub8⚠ | ExperimentalARM Inserts a `USUB8` instruction.
__wfe⚠ | ExperimentalARM Generates a WFE (wait for event) hint instruction, or nothing.
__wfi⚠ | ExperimentalARM Generates a WFI (wait for interrupt) hint instruction, or nothing.
__wsr⚠ | ExperimentalARM Writes a 32-bit system register
__wsrp⚠ | ExperimentalARM Writes a system register containing an address
__yield⚠ | ExperimentalARM Generates a YIELD hint instruction.
_clz_u8⚠ | ExperimentalARM and `v7` Count Leading Zeros.
_clz_u16⚠ | ExperimentalARM and `v7` Count Leading Zeros.
_clz_u32⚠ | ExperimentalARM and `v7` Count Leading Zeros.
_rbit_u32⚠ | ExperimentalARM and `v7` Reverse the bit order.
_rev_u16⚠ | ExperimentalARM Reverse the order of the bytes.
_rev_u32⚠ | ExperimentalARM Reverse the order of the bytes.
udf⚠ | ExperimentalARM Generates the trap instruction `UDF`
vadd_f32⚠ | Experimental`neon` and `v7` and ARM Vector add.
vadd_s8⚠ | Experimental`neon` and `v7` and ARM Vector add.
vadd_s16⚠ | Experimental`neon` and `v7` and ARM Vector add.
vadd_s32⚠ | Experimental`neon` and `v7` and ARM Vector add.
vadd_u8⚠ | Experimental`neon` and `v7` and ARM Vector add.
vadd_u16⚠ | Experimental`neon` and `v7` and ARM Vector add.
vadd_u32⚠ | Experimental`neon` and `v7` and ARM Vector add.
vaddl_s8⚠ | Experimental`neon` and `v7` and ARM Vector long add.
vaddl_s16⚠ | Experimental`neon` and `v7` and ARM Vector long add.
vaddl_s32⚠ | Experimental`neon` and `v7` and ARM Vector long add.
vaddl_u8⚠ | Experimental`neon` and `v7` and ARM Vector long add.
vaddl_u16⚠ | Experimental`neon` and `v7` and ARM Vector long add.
vaddl_u32⚠ | Experimental`neon` and `v7` and ARM Vector long add.
vaddq_f32⚠ | Experimental`neon` and `v7` and ARM Vector add.
vaddq_s8⚠ | Experimental`neon` and `v7` and ARM Vector add.
vaddq_s16⚠ | Experimental`neon` and `v7` and ARM Vector add.
vaddq_s32⚠ | Experimental`neon` and `v7` and ARM Vector add.
vaddq_s64⚠ | Experimental`neon` and `v7` and ARM Vector add.
vaddq_u8⚠ | Experimental`neon` and `v7` and ARM Vector add.
vaddq_u16⚠ | Experimental`neon` and `v7` and ARM Vector add.
vaddq_u32⚠ | Experimental`neon` and `v7` and ARM Vector add.
vaddq_u64⚠ | Experimental`neon` and `v7` and ARM Vector add.
vmovl_s8⚠ | Experimental`neon` and `v7` and ARM Vector long move.
vmovl_s16⚠ | Experimental`neon` and `v7` and ARM Vector long move.
vmovl_s32⚠ | Experimental`neon` and `v7` and ARM Vector long move.
vmovl_u8⚠ | Experimental`neon` and `v7` and ARM Vector long move.
vmovl_u16⚠ | Experimental`neon` and `v7` and ARM Vector long move.
vmovl_u32⚠ | Experimental`neon` and `v7` and ARM Vector long move.
vmovn_s16⚠ | Experimental`neon` and `v7` and ARM Vector narrow integer.
vmovn_s32⚠ | Experimental`neon` and `v7` and ARM Vector narrow integer.
vmovn_s64⚠ | Experimental`neon` and `v7` and ARM Vector narrow integer.
vmovn_u16⚠ | Experimental`neon` and `v7` and ARM Vector narrow integer.
vmovn_u32⚠ | Experimental`neon` and `v7` and ARM Vector narrow integer.
vmovn_u64⚠ | Experimental`neon` and `v7` and ARM Vector narrow integer.
vpmax_f32⚠ | Experimental`neon` and `v7` and ARM Folding maximum of adjacent pairs
vpmax_s8⚠ | Experimental`neon` and `v7` and ARM Folding maximum of adjacent pairs
vpmax_s16⚠ | Experimental`neon` and `v7` and ARM Folding maximum of adjacent pairs
vpmax_s32⚠ | Experimental`neon` and `v7` and ARM Folding maximum of adjacent pairs
vpmax_u8⚠ | Experimental`neon` and `v7` and ARM Folding maximum of adjacent pairs
vpmax_u16⚠ | Experimental`neon` and `v7` and ARM Folding maximum of adjacent pairs
vpmax_u32⚠ | Experimental`neon` and `v7` and ARM Folding maximum of adjacent pairs
vpmin_f32⚠ | Experimental`neon` and `v7` and ARM Folding minimum of adjacent pairs
vpmin_s8⚠ | Experimental`neon` and `v7` and ARM Folding minimum of adjacent pairs
vpmin_s16⚠ | Experimental`neon` and `v7` and ARM Folding minimum of adjacent pairs
vpmin_s32⚠ | Experimental`neon` and `v7` and ARM Folding minimum of adjacent pairs
vpmin_u8⚠ | Experimental`neon` and `v7` and ARM Folding minimum of adjacent pairs
vpmin_u16⚠ | Experimental`neon` and `v7` and ARM Folding minimum of adjacent pairs
vpmin_u32⚠ | Experimental`neon` and `v7` and ARM Folding minimum of adjacent pairs
vrsqrte_f32⚠ | ExperimentalARM and `neon` Reciprocal square-root estimate.
vtbl1_p8⚠ | ExperimentalARM and `neon,v7` Table look-up
vtbl1_s8⚠ | ExperimentalARM and `neon,v7` Table look-up
vtbl1_u8⚠ | ExperimentalARM and `neon,v7` Table look-up
vtbl2_p8⚠ | ExperimentalARM and `neon,v7` Table look-up
vtbl2_s8⚠ | ExperimentalARM and `neon,v7` Table look-up
vtbl2_u8⚠ | ExperimentalARM and `neon,v7` Table look-up
vtbl3_p8⚠ | ExperimentalARM and `neon,v7` Table look-up
vtbl3_s8⚠ | ExperimentalARM and `neon,v7` Table look-up
vtbl3_u8⚠ | ExperimentalARM and `neon,v7` Table look-up
vtbl4_p8⚠ | ExperimentalARM and `neon,v7` Table look-up
vtbl4_s8⚠ | ExperimentalARM and `neon,v7` Table look-up
vtbl4_u8⚠ | ExperimentalARM and `neon,v7` Table look-up
vtbx1_p8⚠ | ExperimentalARM and `neon,v7` Extended table look-up
vtbx1_s8⚠ | ExperimentalARM and `neon,v7` Extended table look-up
vtbx1_u8⚠ | ExperimentalARM and `neon,v7` Extended table look-up
vtbx2_p8⚠ | ExperimentalARM and `neon,v7` Extended table look-up
vtbx2_s8⚠ | ExperimentalARM and `neon,v7` Extended table look-up
vtbx2_u8⚠ | ExperimentalARM and `neon,v7` Extended table look-up
vtbx3_p8⚠ | ExperimentalARM and `neon,v7` Extended table look-up
vtbx3_s8⚠ | ExperimentalARM and `neon,v7` Extended table look-up
vtbx3_u8⚠ | ExperimentalARM and `neon,v7` Extended table look-up
vtbx4_p8⚠ | ExperimentalARM and `neon,v7` Extended table look-up
vtbx4_s8⚠ | ExperimentalARM and `neon,v7` Extended table look-up
vtbx4_u8⚠ | ExperimentalARM and `neon,v7` Extended table look-up

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