core::arch::aarch64 - Rust
Description: API documentation for the Rust `aarch64` mod in crate `core`.
Keywords: rust, rustlang, rust-lang, aarch64

# [−][src]Module core::arch::aarch64

🔬 This is a nightly-only experimental API. (`stdsimd` #27731)
This is supported on AArch64 only.

Platform-specific intrinsics for the `aarch64` platform.

See the module documentation for more details.

## Structs

APSR | ExperimentalAArch64 Application Program Status Register
ISH | ExperimentalAArch64 Inner Shareable is the required shareability domain, reads and writes are the required access types
ISHST | ExperimentalAArch64 Inner Shareable is the required shareability domain, writes are the required access type
NSH | ExperimentalAArch64 Non-shareable is the required shareability domain, reads and writes are the required access types
NSHST | ExperimentalAArch64 Non-shareable is the required shareability domain, writes are the required access type
OSH | ExperimentalAArch64 Outer Shareable is the required shareability domain, reads and writes are the required access types
OSHST | ExperimentalAArch64 Outer Shareable is the required shareability domain, writes are the required access type
ST | ExperimentalAArch64 Full system is the required shareability domain, writes are the required access type
SY | ExperimentalAArch64 Full system is the required shareability domain, reads and writes are the required access types
float32x2_t | ExperimentalAArch64 ARM-specific 64-bit wide vector of two packed `f32`.
float32x4_t | ExperimentalAArch64 ARM-specific 128-bit wide vector of four packed `f32`.
float64x1_t | ExperimentalAArch64 ARM-specific 64-bit wide vector of one packed `f64`.
float64x2_t | ExperimentalAArch64 ARM-specific 128-bit wide vector of two packed `f64`.
int16x2_t | ExperimentalAArch64 ARM-specific 32-bit wide vector of two packed `i16`.
int16x4_t | ExperimentalAArch64 ARM-specific 64-bit wide vector of four packed `i16`.
int16x8_t | ExperimentalAArch64 ARM-specific 128-bit wide vector of eight packed `i16`.
int32x2_t | ExperimentalAArch64 ARM-specific 64-bit wide vector of two packed `i32`.
int32x4_t | ExperimentalAArch64 ARM-specific 128-bit wide vector of four packed `i32`.
int64x1_t | ExperimentalAArch64 ARM-specific 64-bit wide vector of one packed `i64`.
int64x2_t | ExperimentalAArch64 ARM-specific 128-bit wide vector of two packed `i64`.
int8x4_t | ExperimentalAArch64 ARM-specific 32-bit wide vector of four packed `i8`.
int8x8_t | ExperimentalAArch64 ARM-specific 64-bit wide vector of eight packed `i8`.
int8x16_t | ExperimentalAArch64 ARM-specific 128-bit wide vector of sixteen packed `i8`.
int8x16x2_t | ExperimentalAArch64 ARM-specific type containing two `int8x16_t` vectors.
int8x16x3_t | ExperimentalAArch64 ARM-specific type containing three `int8x16_t` vectors.
int8x16x4_t | ExperimentalAArch64 ARM-specific type containing four `int8x16_t` vectors.
int8x8x2_t | ExperimentalAArch64 ARM-specific type containing two `int8x8_t` vectors.
int8x8x3_t | ExperimentalAArch64 ARM-specific type containing three `int8x8_t` vectors.
int8x8x4_t | ExperimentalAArch64 ARM-specific type containing four `int8x8_t` vectors.
poly16x4_t | ExperimentalAArch64 ARM-specific 64-bit wide vector of four packed `u16`.
poly16x8_t | ExperimentalAArch64 ARM-specific 128-bit wide vector of eight packed `u16`.
poly64x1_t | ExperimentalAArch64 ARM-specific 64-bit wide vector of one packed `p64`.
poly64x2_t | ExperimentalAArch64 ARM-specific 64-bit wide vector of two packed `p64`.
poly8x8_t | ExperimentalAArch64 ARM-specific 64-bit wide polynomial vector of eight packed `u8`.
poly8x16_t | ExperimentalAArch64 ARM-specific 128-bit wide vector of sixteen packed `u8`.
poly8x16x2_t | ExperimentalAArch64 ARM-specific type containing two `poly8x16_t` vectors.
poly8x16x3_t | ExperimentalAArch64 ARM-specific type containing three `poly8x16_t` vectors.
poly8x16x4_t | ExperimentalAArch64 ARM-specific type containing four `poly8x16_t` vectors.
poly8x8x2_t | ExperimentalAArch64 ARM-specific type containing two `poly8x8_t` vectors.
poly8x8x3_t | ExperimentalAArch64 ARM-specific type containing three `poly8x8_t` vectors.
poly8x8x4_t | ExperimentalAArch64 ARM-specific type containing four `poly8x8_t` vectors.
uint16x2_t | ExperimentalAArch64 ARM-specific 32-bit wide vector of two packed `u16`.
uint16x4_t | ExperimentalAArch64 ARM-specific 64-bit wide vector of four packed `u16`.
uint16x8_t | ExperimentalAArch64 ARM-specific 128-bit wide vector of eight packed `u16`.
uint32x2_t | ExperimentalAArch64 ARM-specific 64-bit wide vector of two packed `u32`.
uint32x4_t | ExperimentalAArch64 ARM-specific 128-bit wide vector of four packed `u32`.
uint64x1_t | ExperimentalAArch64 ARM-specific 64-bit wide vector of one packed `u64`.
uint64x2_t | ExperimentalAArch64 ARM-specific 128-bit wide vector of two packed `u64`.
uint8x4_t | ExperimentalAArch64 ARM-specific 32-bit wide vector of four packed `u8`.
uint8x8_t | ExperimentalAArch64 ARM-specific 64-bit wide vector of eight packed `u8`.
uint8x16_t | ExperimentalAArch64 ARM-specific 128-bit wide vector of sixteen packed `u8`.
uint8x16x2_t | ExperimentalAArch64 ARM-specific type containing two `uint8x16_t` vectors.
uint8x16x3_t | ExperimentalAArch64 ARM-specific type containing three `uint8x16_t` vectors.
uint8x16x4_t | ExperimentalAArch64 ARM-specific type containing four `uint8x16_t` vectors.
uint8x8x2_t | ExperimentalAArch64 ARM-specific type containing two `uint8x8_t` vectors.
uint8x8x3_t | ExperimentalAArch64 ARM-specific type containing three `uint8x8_t` vectors.
uint8x8x4_t | ExperimentalAArch64 ARM-specific type containing four `uint8x8_t` vectors.

## Functions

__breakpoint⚠ | ExperimentalAArch64 Inserts a breakpoint instruction.
__clrex⚠ | ExperimentalAArch64 Removes the exclusive lock created by LDREX
__crc32b⚠ | ExperimentalAArch64 and `crc` CRC32 single round checksum for bytes (8 bits).
__crc32h⚠ | ExperimentalAArch64 and `crc` CRC32 single round checksum for half words (16 bits).
__crc32w⚠ | ExperimentalAArch64 and `crc` CRC32 single round checksum for words (32 bits).
__crc32d⚠ | ExperimentalAArch64 and `crc` CRC32 single round checksum for quad words (64 bits).
__crc32cb⚠ | ExperimentalAArch64 and `crc` CRC32-C single round checksum for bytes (8 bits).
__crc32ch⚠ | ExperimentalAArch64 and `crc` CRC32-C single round checksum for half words (16 bits).
__crc32cw⚠ | ExperimentalAArch64 and `crc` CRC32-C single round checksum for words (32 bits).
__crc32cd⚠ | ExperimentalAArch64 and `crc` CRC32-C single round checksum for quad words (64 bits).
__dbg⚠ | ExperimentalAArch64 Generates a DBG instruction.
__dmb⚠ | ExperimentalAArch64 Generates a DMB (data memory barrier) instruction or equivalent CP15 instruction.
__dsb⚠ | ExperimentalAArch64 Generates a DSB (data synchronization barrier) instruction or equivalent CP15 instruction.
__isb⚠ | ExperimentalAArch64 Generates an ISB (instruction synchronization barrier) instruction or equivalent CP15 instruction.
__ldrex⚠ | ExperimentalAArch64 Executes a exclusive LDR instruction for 32 bit value.
__ldrexb⚠ | ExperimentalAArch64 Executes a exclusive LDR instruction for 8 bit value.
__ldrexh⚠ | ExperimentalAArch64 Executes a exclusive LDR instruction for 16 bit value.
__nop⚠ | ExperimentalAArch64 Generates an unspecified no-op instruction.
__qadd⚠ | ExperimentalAArch64 Signed saturating addition
__qadd8⚠ | ExperimentalAArch64 Saturating four 8-bit integer additions
__qadd16⚠ | ExperimentalAArch64 Saturating two 16-bit integer additions
__qasx⚠ | ExperimentalAArch64 Returns the 16-bit signed saturated equivalent of
__qdbl⚠ | ExperimentalAArch64 Insert a QADD instruction
__qsax⚠ | ExperimentalAArch64 Returns the 16-bit signed saturated equivalent of
__qsub⚠ | ExperimentalAArch64 Signed saturating subtraction
__qsub8⚠ | ExperimentalAArch64 Saturating two 8-bit integer subtraction
__qsub16⚠ | ExperimentalAArch64 Saturating two 16-bit integer subtraction
__rsr⚠ | ExperimentalAArch64 Reads a 32-bit system register
__rsrp⚠ | ExperimentalAArch64 Reads a system register containing an address
__sadd8⚠ | ExperimentalAArch64 Returns the 8-bit signed saturated equivalent of
__sadd16⚠ | ExperimentalAArch64 Returns the 16-bit signed saturated equivalent of
__sasx⚠ | ExperimentalAArch64 Returns the 16-bit signed equivalent of
__sel⚠ | ExperimentalAArch64 Select bytes from each operand according to APSR GE flags
__sev⚠ | ExperimentalAArch64 Generates a SEV (send a global event) hint instruction.
__shadd8⚠ | ExperimentalAArch64 Signed halving parallel byte-wise addition.
__shadd16⚠ | ExperimentalAArch64 Signed halving parallel halfword-wise addition.
__shsub8⚠ | ExperimentalAArch64 Signed halving parallel byte-wise subtraction.
__shsub16⚠ | ExperimentalAArch64 Signed halving parallel halfword-wise subtraction.
__smlabb⚠ | ExperimentalAArch64 Insert a SMLABB instruction
__smlabt⚠ | ExperimentalAArch64 Insert a SMLABT instruction
__smlad⚠ | ExperimentalAArch64 Dual 16-bit Signed Multiply with Addition of products and 32-bit accumulation.
__smlatb⚠ | ExperimentalAArch64 Insert a SMLATB instruction
__smlatt⚠ | ExperimentalAArch64 Insert a SMLATT instruction
__smlawb⚠ | ExperimentalAArch64 Insert a SMLAWB instruction
__smlawt⚠ | ExperimentalAArch64 Insert a SMLAWT instruction
__smlsd⚠ | ExperimentalAArch64 Dual 16-bit Signed Multiply with Subtraction of products and 32-bit accumulation and overflow detection.
__smuad⚠ | ExperimentalAArch64 Signed Dual Multiply Add.
__smuadx⚠ | ExperimentalAArch64 Signed Dual Multiply Add Reversed.
__smulbb⚠ | ExperimentalAArch64 Insert a SMULBB instruction
__smulbt⚠ | ExperimentalAArch64 Insert a SMULTB instruction
__smultb⚠ | ExperimentalAArch64 Insert a SMULTB instruction
__smultt⚠ | ExperimentalAArch64 Insert a SMULTT instruction
__smulwb⚠ | ExperimentalAArch64 Insert a SMULWB instruction
__smulwt⚠ | ExperimentalAArch64 Insert a SMULWT instruction
__smusd⚠ | ExperimentalAArch64 Signed Dual Multiply Subtract.
__smusdx⚠ | ExperimentalAArch64 Signed Dual Multiply Subtract Reversed.
__ssub8⚠ | ExperimentalAArch64 Inserts a `SSUB8` instruction.
__strex⚠ | ExperimentalAArch64 Executes a exclusive STR instruction for 32 bit values
__strexb⚠ | ExperimentalAArch64 Executes a exclusive STR instruction for 8 bit values
__strexh⚠ | ExperimentalAArch64 Executes a exclusive STR instruction for 16 bit values
__usad8⚠ | ExperimentalAArch64 Sum of 8-bit absolute differences.
__usada8⚠ | ExperimentalAArch64 Sum of 8-bit absolute differences and constant.
__usub8⚠ | ExperimentalAArch64 Inserts a `USUB8` instruction.
__wfe⚠ | ExperimentalAArch64 Generates a WFE (wait for event) hint instruction, or nothing.
__wfi⚠ | ExperimentalAArch64 Generates a WFI (wait for interrupt) hint instruction, or nothing.
__wsr⚠ | ExperimentalAArch64 Writes a 32-bit system register
__wsrp⚠ | ExperimentalAArch64 Writes a system register containing an address
__yield⚠ | ExperimentalAArch64 Generates a YIELD hint instruction.
_cls_u32⚠ | ExperimentalAArch64 Counts the leading most significant bits set.
_cls_u64⚠ | ExperimentalAArch64 Counts the leading most significant bits set.
_clz_u8⚠ | ExperimentalAArch64 and `v7` Count Leading Zeros.
_clz_u16⚠ | ExperimentalAArch64 and `v7` Count Leading Zeros.
_clz_u32⚠ | ExperimentalAArch64 and `v7` Count Leading Zeros.
_clz_u64⚠ | ExperimentalAArch64 Count Leading Zeros.
_rbit_u32⚠ | ExperimentalAArch64 and `v7` Reverse the bit order.
_rbit_u64⚠ | ExperimentalAArch64 Reverse the bit order.
_rev_u16⚠ | ExperimentalAArch64 Reverse the order of the bytes.
_rev_u32⚠ | ExperimentalAArch64 Reverse the order of the bytes.
_rev_u64⚠ | ExperimentalAArch64 Reverse the order of the bytes.
brk⚠ | ExperimentalAArch64 Generates the trap instruction `BRK 1`
udf⚠ | ExperimentalAArch64 Generates the trap instruction `UDF`
vadd_f32⚠ | Experimental`neon` and `v7` and AArch64 Vector add.
vadd_f64⚠ | ExperimentalAArch64 and `neon` Vector add.
vadd_s8⚠ | Experimental`neon` and `v7` and AArch64 Vector add.
vadd_s16⚠ | Experimental`neon` and `v7` and AArch64 Vector add.
vadd_s32⚠ | Experimental`neon` and `v7` and AArch64 Vector add.
vadd_u8⚠ | Experimental`neon` and `v7` and AArch64 Vector add.
vadd_u16⚠ | Experimental`neon` and `v7` and AArch64 Vector add.
vadd_u32⚠ | Experimental`neon` and `v7` and AArch64 Vector add.
vaddd_s64⚠ | ExperimentalAArch64 and `neon` Vector add.
vaddd_u64⚠ | ExperimentalAArch64 and `neon` Vector add.
vaddl_s8⚠ | Experimental`neon` and `v7` and AArch64 Vector long add.
vaddl_s16⚠ | Experimental`neon` and `v7` and AArch64 Vector long add.
vaddl_s32⚠ | Experimental`neon` and `v7` and AArch64 Vector long add.
vaddl_u8⚠ | Experimental`neon` and `v7` and AArch64 Vector long add.
vaddl_u16⚠ | Experimental`neon` and `v7` and AArch64 Vector long add.
vaddl_u32⚠ | Experimental`neon` and `v7` and AArch64 Vector long add.
vaddq_f32⚠ | Experimental`neon` and `v7` and AArch64 Vector add.
vaddq_f64⚠ | ExperimentalAArch64 and `neon` Vector add.
vaddq_s8⚠ | Experimental`neon` and `v7` and AArch64 Vector add.
vaddq_s16⚠ | Experimental`neon` and `v7` and AArch64 Vector add.
vaddq_s32⚠ | Experimental`neon` and `v7` and AArch64 Vector add.
vaddq_s64⚠ | Experimental`neon` and `v7` and AArch64 Vector add.
vaddq_u8⚠ | Experimental`neon` and `v7` and AArch64 Vector add.
vaddq_u16⚠ | Experimental`neon` and `v7` and AArch64 Vector add.
vaddq_u32⚠ | Experimental`neon` and `v7` and AArch64 Vector add.
vaddq_u64⚠ | Experimental`neon` and `v7` and AArch64 Vector add.
vaesdq_u8⚠ | ExperimentalAArch64 and `crypto` AES single round decryption.
vaeseq_u8⚠ | ExperimentalAArch64 and `crypto` AES single round encryption.
vaesimcq_u8⚠ | ExperimentalAArch64 and `crypto` AES inverse mix columns.
vaesmcq_u8⚠ | ExperimentalAArch64 and `crypto` AES mix columns.
vcombine_f32⚠ | ExperimentalAArch64 and `neon` Vector combine
vcombine_f64⚠ | ExperimentalAArch64 and `neon` Vector combine
vcombine_p8⚠ | ExperimentalAArch64 and `neon` Vector combine
vcombine_p16⚠ | ExperimentalAArch64 and `neon` Vector combine
vcombine_p64⚠ | ExperimentalAArch64 and `neon` Vector combine
vcombine_s8⚠ | ExperimentalAArch64 and `neon` Vector combine
vcombine_s16⚠ | ExperimentalAArch64 and `neon` Vector combine
vcombine_s32⚠ | ExperimentalAArch64 and `neon` Vector combine
vcombine_s64⚠ | ExperimentalAArch64 and `neon` Vector combine
vcombine_u8⚠ | ExperimentalAArch64 and `neon` Vector combine
vcombine_u16⚠ | ExperimentalAArch64 and `neon` Vector combine
vcombine_u32⚠ | ExperimentalAArch64 and `neon` Vector combine
vcombine_u64⚠ | ExperimentalAArch64 and `neon` Vector combine
vmaxv_f32⚠ | ExperimentalAArch64 and `neon` Horizontal vector max.
vmaxv_s8⚠ | ExperimentalAArch64 and `neon` Horizontal vector max.
vmaxv_s16⚠ | ExperimentalAArch64 and `neon` Horizontal vector max.
vmaxv_s32⚠ | ExperimentalAArch64 and `neon` Horizontal vector max.
vmaxv_u8⚠ | ExperimentalAArch64 and `neon` Horizontal vector max.
vmaxv_u16⚠ | ExperimentalAArch64 and `neon` Horizontal vector max.
vmaxv_u32⚠ | ExperimentalAArch64 and `neon` Horizontal vector max.
vmaxvq_f32⚠ | ExperimentalAArch64 and `neon` Horizontal vector max.
vmaxvq_f64⚠ | ExperimentalAArch64 and `neon` Horizontal vector max.
vmaxvq_s8⚠ | ExperimentalAArch64 and `neon` Horizontal vector max.
vmaxvq_s16⚠ | ExperimentalAArch64 and `neon` Horizontal vector max.
vmaxvq_s32⚠ | ExperimentalAArch64 and `neon` Horizontal vector max.
vmaxvq_u8⚠ | ExperimentalAArch64 and `neon` Horizontal vector max.
vmaxvq_u16⚠ | ExperimentalAArch64 and `neon` Horizontal vector max.
vmaxvq_u32⚠ | ExperimentalAArch64 and `neon` Horizontal vector max.
vminv_f32⚠ | ExperimentalAArch64 and `neon` Horizontal vector min.
vminv_s8⚠ | ExperimentalAArch64 and `neon` Horizontal vector min.
vminv_s16⚠ | ExperimentalAArch64 and `neon` Horizontal vector min.
vminv_s32⚠ | ExperimentalAArch64 and `neon` Horizontal vector min.
vminv_u8⚠ | ExperimentalAArch64 and `neon` Horizontal vector min.
vminv_u16⚠ | ExperimentalAArch64 and `neon` Horizontal vector min.
vminv_u32⚠ | ExperimentalAArch64 and `neon` Horizontal vector min.
vminvq_f32⚠ | ExperimentalAArch64 and `neon` Horizontal vector min.
vminvq_f64⚠ | ExperimentalAArch64 and `neon` Horizontal vector min.
vminvq_s8⚠ | ExperimentalAArch64 and `neon` Horizontal vector min.
vminvq_s16⚠ | ExperimentalAArch64 and `neon` Horizontal vector min.
vminvq_s32⚠ | ExperimentalAArch64 and `neon` Horizontal vector min.
vminvq_u8⚠ | ExperimentalAArch64 and `neon` Horizontal vector min.
vminvq_u16⚠ | ExperimentalAArch64 and `neon` Horizontal vector min.
vminvq_u32⚠ | ExperimentalAArch64 and `neon` Horizontal vector min.
vmovl_s8⚠ | Experimental`neon` and `v7` and AArch64 Vector long move.
vmovl_s16⚠ | Experimental`neon` and `v7` and AArch64 Vector long move.
vmovl_s32⚠ | Experimental`neon` and `v7` and AArch64 Vector long move.
vmovl_u8⚠ | Experimental`neon` and `v7` and AArch64 Vector long move.
vmovl_u16⚠ | Experimental`neon` and `v7` and AArch64 Vector long move.
vmovl_u32⚠ | Experimental`neon` and `v7` and AArch64 Vector long move.
vmovn_s16⚠ | Experimental`neon` and `v7` and AArch64 Vector narrow integer.
vmovn_s32⚠ | Experimental`neon` and `v7` and AArch64 Vector narrow integer.
vmovn_s64⚠ | Experimental`neon` and `v7` and AArch64 Vector narrow integer.
vmovn_u16⚠ | Experimental`neon` and `v7` and AArch64 Vector narrow integer.
vmovn_u32⚠ | Experimental`neon` and `v7` and AArch64 Vector narrow integer.
vmovn_u64⚠ | Experimental`neon` and `v7` and AArch64 Vector narrow integer.
vmvn_p8⚠ | Experimental`neon` and `v7` and AArch64 Vector bitwise not.
vmvn_s8⚠ | Experimental`neon` and `v7` and AArch64 Vector bitwise not.
vmvn_s16⚠ | Experimental`neon` and `v7` and AArch64 Vector bitwise not.
vmvn_s32⚠ | Experimental`neon` and `v7` and AArch64 Vector bitwise not.
vmvn_u8⚠ | Experimental`neon` and `v7` and AArch64 Vector bitwise not.
vmvn_u16⚠ | Experimental`neon` and `v7` and AArch64 Vector bitwise not.
vmvn_u32⚠ | Experimental`neon` and `v7` and AArch64 Vector bitwise not.
vmvnq_p8⚠ | Experimental`neon` and `v7` and AArch64 Vector bitwise not.
vmvnq_s8⚠ | Experimental`neon` and `v7` and AArch64 Vector bitwise not.
vmvnq_s16⚠ | Experimental`neon` and `v7` and AArch64 Vector bitwise not.
vmvnq_s32⚠ | Experimental`neon` and `v7` and AArch64 Vector bitwise not.
vmvnq_u8⚠ | Experimental`neon` and `v7` and AArch64 Vector bitwise not.
vmvnq_u16⚠ | Experimental`neon` and `v7` and AArch64 Vector bitwise not.
vmvnq_u32⚠ | Experimental`neon` and `v7` and AArch64 Vector bitwise not.
vpmax_f32⚠ | Experimental`neon` and `v7` and AArch64 Folding maximum of adjacent pairs
vpmax_s8⚠ | Experimental`neon` and `v7` and AArch64 Folding maximum of adjacent pairs
vpmax_s16⚠ | Experimental`neon` and `v7` and AArch64 Folding maximum of adjacent pairs
vpmax_s32⚠ | Experimental`neon` and `v7` and AArch64 Folding maximum of adjacent pairs
vpmax_u8⚠ | Experimental`neon` and `v7` and AArch64 Folding maximum of adjacent pairs
vpmax_u16⚠ | Experimental`neon` and `v7` and AArch64 Folding maximum of adjacent pairs
vpmax_u32⚠ | Experimental`neon` and `v7` and AArch64 Folding maximum of adjacent pairs
vpmaxq_f32⚠ | ExperimentalAArch64 and `neon` Folding maximum of adjacent pairs
vpmaxq_f64⚠ | ExperimentalAArch64 and `neon` Folding maximum of adjacent pairs
vpmaxq_s8⚠ | ExperimentalAArch64 and `neon` Folding maximum of adjacent pairs
vpmaxq_s16⚠ | ExperimentalAArch64 and `neon` Folding maximum of adjacent pairs
vpmaxq_s32⚠ | ExperimentalAArch64 and `neon` Folding maximum of adjacent pairs
vpmaxq_u8⚠ | ExperimentalAArch64 and `neon` Folding maximum of adjacent pairs
vpmaxq_u16⚠ | ExperimentalAArch64 and `neon` Folding maximum of adjacent pairs
vpmaxq_u32⚠ | ExperimentalAArch64 and `neon` Folding maximum of adjacent pairs
vpmin_f32⚠ | Experimental`neon` and `v7` and AArch64 Folding minimum of adjacent pairs
vpmin_s8⚠ | Experimental`neon` and `v7` and AArch64 Folding minimum of adjacent pairs
vpmin_s16⚠ | Experimental`neon` and `v7` and AArch64 Folding minimum of adjacent pairs
vpmin_s32⚠ | Experimental`neon` and `v7` and AArch64 Folding minimum of adjacent pairs
vpmin_u8⚠ | Experimental`neon` and `v7` and AArch64 Folding minimum of adjacent pairs
vpmin_u16⚠ | Experimental`neon` and `v7` and AArch64 Folding minimum of adjacent pairs
vpmin_u32⚠ | Experimental`neon` and `v7` and AArch64 Folding minimum of adjacent pairs
vpminq_f32⚠ | ExperimentalAArch64 and `neon` Folding minimum of adjacent pairs
vpminq_f64⚠ | ExperimentalAArch64 and `neon` Folding minimum of adjacent pairs
vpminq_s8⚠ | ExperimentalAArch64 and `neon` Folding minimum of adjacent pairs
vpminq_s16⚠ | ExperimentalAArch64 and `neon` Folding minimum of adjacent pairs
vpminq_s32⚠ | ExperimentalAArch64 and `neon` Folding minimum of adjacent pairs
vpminq_u8⚠ | ExperimentalAArch64 and `neon` Folding minimum of adjacent pairs
vpminq_u16⚠ | ExperimentalAArch64 and `neon` Folding minimum of adjacent pairs
vpminq_u32⚠ | ExperimentalAArch64 and `neon` Folding minimum of adjacent pairs
vqtbl1_p8⚠ | ExperimentalAArch64 and `neon` Table look-up
vqtbl1_s8⚠ | ExperimentalAArch64 and `neon` Table look-up
vqtbl1_u8⚠ | ExperimentalAArch64 and `neon` Table look-up
vqtbl1q_p8⚠ | ExperimentalAArch64 and `neon` Table look-up
vqtbl1q_s8⚠ | ExperimentalAArch64 and `neon` Table look-up
vqtbl1q_u8⚠ | ExperimentalAArch64 and `neon` Table look-up
vqtbl2_p8⚠ | ExperimentalAArch64 and `neon` Table look-up
vqtbl2_s8⚠ | ExperimentalAArch64 and `neon` Table look-up
vqtbl2_u8⚠ | ExperimentalAArch64 and `neon` Table look-up
vqtbl2q_p8⚠ | ExperimentalAArch64 and `neon` Table look-up
vqtbl2q_s8⚠ | ExperimentalAArch64 and `neon` Table look-up
vqtbl2q_u8⚠ | ExperimentalAArch64 and `neon` Table look-up
vqtbl3_p8⚠ | ExperimentalAArch64 and `neon` Table look-up
vqtbl3_s8⚠ | ExperimentalAArch64 and `neon` Table look-up
vqtbl3_u8⚠ | ExperimentalAArch64 and `neon` Table look-up
vqtbl3q_p8⚠ | ExperimentalAArch64 and `neon` Table look-up
vqtbl3q_s8⚠ | ExperimentalAArch64 and `neon` Table look-up
vqtbl3q_u8⚠ | ExperimentalAArch64 and `neon` Table look-up
vqtbl4_p8⚠ | ExperimentalAArch64 and `neon` Table look-up
vqtbl4_s8⚠ | ExperimentalAArch64 and `neon` Table look-up
vqtbl4_u8⚠ | ExperimentalAArch64 and `neon` Table look-up
vqtbl4q_p8⚠ | ExperimentalAArch64 and `neon` Table look-up
vqtbl4q_s8⚠ | ExperimentalAArch64 and `neon` Table look-up
vqtbl4q_u8⚠ | ExperimentalAArch64 and `neon` Table look-up
vqtbx1_p8⚠ | ExperimentalAArch64 and `neon` Extended table look-up
vqtbx1_s8⚠ | ExperimentalAArch64 and `neon` Extended table look-up
vqtbx1_u8⚠ | ExperimentalAArch64 and `neon` Extended table look-up
vqtbx1q_p8⚠ | ExperimentalAArch64 and `neon` Extended table look-up
vqtbx1q_s8⚠ | ExperimentalAArch64 and `neon` Extended table look-up
vqtbx1q_u8⚠ | ExperimentalAArch64 and `neon` Extended table look-up
vqtbx2_p8⚠ | ExperimentalAArch64 and `neon` Extended table look-up
vqtbx2_s8⚠ | ExperimentalAArch64 and `neon` Extended table look-up
vqtbx2_u8⚠ | ExperimentalAArch64 and `neon` Extended table look-up
vqtbx2q_p8⚠ | ExperimentalAArch64 and `neon` Extended table look-up
vqtbx2q_s8⚠ | ExperimentalAArch64 and `neon` Extended table look-up
vqtbx2q_u8⚠ | ExperimentalAArch64 and `neon` Extended table look-up
vqtbx3_p8⚠ | ExperimentalAArch64 and `neon` Extended table look-up
vqtbx3_s8⚠ | ExperimentalAArch64 and `neon` Extended table look-up
vqtbx3_u8⚠ | ExperimentalAArch64 and `neon` Extended table look-up
vqtbx3q_p8⚠ | ExperimentalAArch64 and `neon` Extended table look-up
vqtbx3q_s8⚠ | ExperimentalAArch64 and `neon` Extended table look-up
vqtbx3q_u8⚠ | ExperimentalAArch64 and `neon` Extended table look-up
vqtbx4_p8⚠ | ExperimentalAArch64 and `neon` Extended table look-up
vqtbx4_s8⚠ | ExperimentalAArch64 and `neon` Extended table look-up
vqtbx4_u8⚠ | ExperimentalAArch64 and `neon` Extended table look-up
vqtbx4q_p8⚠ | ExperimentalAArch64 and `neon` Extended table look-up
vqtbx4q_s8⚠ | ExperimentalAArch64 and `neon` Extended table look-up
vqtbx4q_u8⚠ | ExperimentalAArch64 and `neon` Extended table look-up
vrsqrte_f32⚠ | ExperimentalAArch64 and `neon` Reciprocal square-root estimate.
vsha1cq_u32⚠ | ExperimentalAArch64 and `crypto` SHA1 hash update accelerator, choose.
vsha1h_u32⚠ | ExperimentalAArch64 and `crypto` SHA1 fixed rotate.
vsha1mq_u32⚠ | ExperimentalAArch64 and `crypto` SHA1 hash update accelerator, majority.
vsha1pq_u32⚠ | ExperimentalAArch64 and `crypto` SHA1 hash update accelerator, parity.
vsha1su0q_u32⚠ | ExperimentalAArch64 and `crypto` SHA1 schedule update accelerator, first part.
vsha1su1q_u32⚠ | ExperimentalAArch64 and `crypto` SHA1 schedule update accelerator, second part.
vsha256h2q_u32⚠ | ExperimentalAArch64 and `crypto` SHA256 hash update accelerator, upper part.
vsha256hq_u32⚠ | ExperimentalAArch64 and `crypto` SHA256 hash update accelerator.
vsha256su0q_u32⚠ | ExperimentalAArch64 and `crypto` SHA256 schedule update accelerator, first part.
vsha256su1q_u32⚠ | ExperimentalAArch64 and `crypto` SHA256 schedule update accelerator, second part.
vtbl1_p8⚠ | ExperimentalAArch64 and `neon,v7` Table look-up
vtbl1_s8⚠ | ExperimentalAArch64 and `neon,v7` Table look-up
vtbl1_u8⚠ | ExperimentalAArch64 and `neon,v7` Table look-up
vtbl2_p8⚠ | ExperimentalAArch64 and `neon,v7` Table look-up
vtbl2_s8⚠ | ExperimentalAArch64 and `neon,v7` Table look-up
vtbl2_u8⚠ | ExperimentalAArch64 and `neon,v7` Table look-up
vtbl3_p8⚠ | ExperimentalAArch64 and `neon,v7` Table look-up
vtbl3_s8⚠ | ExperimentalAArch64 and `neon,v7` Table look-up
vtbl3_u8⚠ | ExperimentalAArch64 and `neon,v7` Table look-up
vtbl4_p8⚠ | ExperimentalAArch64 and `neon,v7` Table look-up
vtbl4_s8⚠ | ExperimentalAArch64 and `neon,v7` Table look-up
vtbl4_u8⚠ | ExperimentalAArch64 and `neon,v7` Table look-up
vtbx1_p8⚠ | ExperimentalAArch64 and `neon,v7` Extended table look-up
vtbx1_s8⚠ | ExperimentalAArch64 and `neon,v7` Extended table look-up
vtbx1_u8⚠ | ExperimentalAArch64 and `neon,v7` Extended table look-up
vtbx2_p8⚠ | ExperimentalAArch64 and `neon,v7` Extended table look-up
vtbx2_s8⚠ | ExperimentalAArch64 and `neon,v7` Extended table look-up
vtbx2_u8⚠ | ExperimentalAArch64 and `neon,v7` Extended table look-up
vtbx3_p8⚠ | ExperimentalAArch64 and `neon,v7` Extended table look-up
vtbx3_s8⚠ | ExperimentalAArch64 and `neon,v7` Extended table look-up
vtbx3_u8⚠ | ExperimentalAArch64 and `neon,v7` Extended table look-up
vtbx4_p8⚠ | ExperimentalAArch64 and `neon,v7` Extended table look-up
vtbx4_s8⚠ | ExperimentalAArch64 and `neon,v7` Extended table look-up
vtbx4_u8⚠ | ExperimentalAArch64 and `neon,v7` Extended table look-up