# gnetlist-legacy

NAME
SYNOPSIS
DESCRIPTION
GENERAL OPTIONS
BACKENDS
EXAMPLES
ENVIRONMENT
AUTHORS
COPYRIGHT
SEE ALSO

## NAME

gnetlist-legacy - gEDA/gaf Netlist Extraction and Generation

## SYNOPSIS

gnetlist-legacy [OPTION ...] [-g BACKEND] [--] FILE ...

## DESCRIPTION

gnetlist-legacy is a netlist extraction and generation tool, and is part of the gEDA (GPL Electronic Design Automation) toolset. It takes one or electronic schematics as input, and outputs a netlist. A netlist is a machine-interpretable description of the way that components in an electronic circuit are connected together, and is commonly used as the input to a PCB layout program such as pcb(1) or to a simulator such as gnucap(1).

A normal gnetlist-legacy run is carried out in two steps. First, the gnetlist-legacy frontend loads the specified human-readable schematic FILEs, and compiles them to an in-memory netlist description. Next, a ’backend’ is used to export the connection and component data to one of many supported netlist formats.

gnetlist-legacy is extensible, using the Scheme programming language.

## GENERAL OPTIONS

| -q |  | Quiet mode. Turns off all warnings/notes/messages.

-v, --verbose

Verbose mode. Output all diagnostic information.

-L DIRECTORY

Prepend DIRECTORY to the list of directories to be searched for Scheme files.

-g BACKEND

Specify the netlist backend to be used.

-O STRING

Pass an option string to the backend.

--list-backends

Print a list of available netlist backends.

| -o FILE |  | Specify the filename for the generated netlist. By default, output is directed to ’output.net’. If ’-’ is given instead of a filename, the output is directed to the standard output.
| -l FILE |  | Specify a Scheme file to be loaded before the backend is loaded or executed. This option can be specified multiple times.
| -m FILE |  | Specify a Scheme file to be loaded between loading the backend and executing it. This option can be specified multiple times.
| -c EXPR |  | Specify a Scheme expression to be executed during gnetlist-legacy startup. This option can be specified multiple times.
| -i |  | After the schematic files have been loaded and compiled, and after all Scheme files have been loaded, but before running the backend, enter a Scheme read-eval-print loop.

-h, --help

Print a help message.

-V, --version

Print gnetlist-legacy version information.

| -- |  | Treat all remaining arguments as schematic filenames. Use this if you have a schematic filename which begins with ’-’.

## BACKENDS

Currently, gnetlist-legacy includes the following backends:

| allegro |  | Allegro netlist format. |
| bae |  | Bartels Autoengineer netlist format. |

bom, bom2

Bill of materials generation.

| calay |  | Calay netlist format. |
| cascade |  | RF Cascade netlist format |

drc, drc2

Design rule checkers (drc2 is recommended).

| eagle |  | Eagle netlist format.
| ewnet |  | Netlist format for National Instruments ULTIboard layout tool.

futurenet2

Futurenet2 netlist format.

| geda |  | Native gEDA netlist format (mainly used for testing and diagnostics).
| gossip |  | Gossip netlist format.

gsch2pcb

Backend used for pcb(1) file layout generation by gsch2pcb(1). It is not recommended to use this backend directly.

liquidpcb

LiquidPCB netlist format.

mathematica

Netlister for analytical circuit solving using Mathematica.

maxascii

MAXASCII netlist format.

| osmond |  | Osmond netlist format. |
| pads |  | PADS netlist format. |

partslist1, partslist2, partslist3

Bill of materials generation backends (alternatives to bom and bom2).

| PCB |  | pcb(1) netlist format.
| pcbpins |  | Generates a pcb(1) action file for forward annotating pin/pad names from schematic to layout.

protelII

Protel II netlist format.

| redac |  | RACAL-REDAC netlist format. |

spice, spice-sdb

SPICE-compatible netlist format (spice-sdb is recommended). Suitable for use with gnucap(1).

| switcap |  | SWITCAP switched capacitor simulator netlist format.
| systemc |  | Structural SystemC code generation.
| tango |  | Tango netlist format.
| vams |  | VHDL-AMS code generation.
| verilog |  | Verilog code generation.
| vhdl |  | VHDL code generation.
| vipec |  | ViPEC Network Analyser netlist format.

## EXAMPLES

These examples assume that you have a ’stack_1.sch’ in the current directory.

gnetlist-legacy requires that at least one schematic to be specified on the command line:

./gnetlist-legacy stack_1.sch

This is not very useful since it does not direct gnetlist-legacy to do
anything.

Specify a backend name with ’-g’ to get gnetlist-legacy to output a
netlist:

| ./gnetlist-legacy -g geda stack_1.sch

The netlist output will be written to a file called ’output.net’
in the current working directory.

You can specify the output filename by using the ’-o’ option:

| ./gnetlist-legacy -g geda stack_1.sch -o /tmp/stack.netlist

Output will now be directed to ’/tmp/stack.netlist’.

You could run (for example) the ’spice-sdb’ backend against the
schematic if you specified ’-g spice-sdb’, or you could generate a
bill of materials for the schematic using ’-g partslist1’.

To obtain a Scheme prompt to run Scheme expressions directly, you can
use the ’-i’ option.

| ./gnetlist-legacy -i stack_1.sch

gnetlist-legacy will load ’stack_1.sh’, and then enter an interactive
Scheme read-eval-print loop.

## ENVIRONMENT

GEDADATA

specifies the search directory for Scheme and rc files. The default is ’${prefix}/share/gEDA’.

GEDADATARC

specifies the search directory for rc files. The default is ’$GEDADATA’.

| GEDALOG |  | specifies the directory to which to write log files. The default is ’~/.gEDA/logs’.

## AUTHORS

See the ’AUTHORS’ file included with this program.

## COPYRIGHT

Copyright © 1999-2019 gEDA Contributors. License GPLv2+: GNU GPL
version 2 or later. Please see the ’COPYING’ file included with this
program for full details.

This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law.

## SEE ALSO

gschem(1), gsymcheck(1), pcb(1), gnucap(1)