%FILENAME%
verilator-4.030-1-armv7h.pkg.tar.xz

%NAME%
verilator

%BASE%
verilator

%VERSION%
4.030-1

%DESC%
The fastest free Verilog HDL simulator

%CSIZE%
3144516

%ISIZE%
15424643

%MD5SUM%
c0dceadaf878ca589c9ddc9377a7c0e5

%SHA256SUM%
48c5fc8b652f8b830b0beb9c0b240b6a2d16c317ffa6bc70eb8265e73006697d

%PGPSIG%
iQIzBAABCAAdFiEEaLNTfzmjE7PldNBndxk/FSvb5qYFAl5+tOYACgkQdxk/FSvb5qac0RAAwhDVctwFlgh4IKKcDqFXZLSNFZtBiwrypgmC084bK3dtU1I6EOA0R2CUysc5mTGtvFuxbAs17aSMWDglU77CQyRyubUwoWoIKDNeGZ+tBNNXiFWrgPQz+pOAMFy+Bgs4TnVle8yzVGh+GHO+ZEB3fbDy02AZnAbHmRftOt4ZBNCx5mZRQZSwklLgsiteybH8Y2SlRPtf5xZA4ZcogvJsxPMFHOK/yRKoIT7wW+GN77yfcNId4xtBkymZmlZ/bCihdxY2zFKtKYDqaJo1TNwGJ6CDrOIVGfpy35/mcXvBcpIyoldWWoGlGQsE8z1SrrC8oZyZGWXXCMvx7IL6Mf0dByvASe2qHwaETcLz0rbgEXsj/BoZEbKMb1W3J3L+NaJBlUmX00U7ikxlwowyUjUE+7WV/Rib0IGdX37FBa7m6IQvMHs7zKKbC57M4FrEsxtFzosxi27ULgR3Wwn9lKvQrZO/Uw9JNzfejwERrGKpU6aDFIW516TEPjwpj6hnnCdMoYEJMzmZ2LLMxTyGxZJgrfkN5sIE/3CMHRc/xit4lKj8htBgqnZBJB/kb4AJtq+UboqXiRXAtNVtqvbFCugjLFLfhpIsAC/z3EQhZd7fbwxszBI1gyOEp3khhuN3N9XmHjJJrDSEsGKBhi2hdN5xZqBhWx9HbAD4McPZQpyv3eo=

%URL%
https://www.veripool.org/projects/verilator/wiki/Intro

%LICENSE%
LGPL

%ARCH%
armv7h

%BUILDDATE%
1585361827

%PACKAGER%
Arch Linux ARM Build System <builder+xu6@archlinuxarm.org>

