PIC16F1459
Author: Molnár Károly

All Enhanced Extended Regular 12 bits 14 bits 16 bits RAM
size ROM
size EEPROM
size Common
SFRs
Features Configuration Bits RAM map SFR map

PIC16F1459
CONFIG1 (address:0x8007, mask:0x3EFF, default:0x3EFF)
FOSC -- Oscillator Selection Bits (bitmask:0x0007)
FOSC = LP | 0x3FF8 | LP Oscillator, Low-power crystal connected between OSC1 and OSC2 pins.
FOSC = XT | 0x3FF9 | XT Oscillator, Crystal/resonator connected between OSC1 and OSC2 pins.
FOSC = HS | 0x3FFA | HS Oscillator, High-speed crystal/resonator connected between OSC1 and OSC2 pins.
FOSC = EXTRC | 0x3FFB | EXTRC oscillator: External RC circuit connected to CLKIN pin.
FOSC = INTOSC | 0x3FFC | INTOSC oscillator: I/O function on CLKIN pin.
FOSC = ECL | 0x3FFD | ECL, External Clock, Low Power Mode (0-0.5 MHz): device clock supplied to CLKIN pins.
FOSC = ECM | 0x3FFE | ECM, External Clock, Medium Power Mode (0.5-4 MHz): device clock supplied to CLKIN pins.
FOSC = ECH | 0x3FFF | ECH, External Clock, High Power Mode (4-20 MHz): device clock supplied to CLKIN pins.
WDTE -- Watchdog Timer Enable (bitmask:0x0018)
WDTE = OFF | 0x3FE7 | WDT disabled.
WDTE = SWDTEN | 0x3FEF | WDT controlled by the SWDTEN bit in the WDTCON register.
WDTE = NSLEEP | 0x3FF7 | WDT enabled while running and disabled in Sleep.
WDTE = ON | 0x3FFF | WDT enabled.
PWRTE -- Power-up Timer Enable (bitmask:0x0020)
PWRTE = ON | 0x3FDF | PWRT enabled.
PWRTE = OFF | 0x3FFF | PWRT disabled.
MCLRE -- MCLR Pin Function Select (bitmask:0x0040)
MCLRE = OFF | 0x3FBF | MCLR/VPP pin function is digital input.
MCLRE = ON | 0x3FFF | MCLR/VPP pin function is MCLR.
CP -- Flash Program Memory Code Protection (bitmask:0x0080)
CP = ON | 0x3F7F | Program memory code protection is enabled.
CP = OFF | 0x3FFF | Program memory code protection is disabled.
BOREN -- Brown-out Reset Enable (bitmask:0x0600)
BOREN = OFF | 0x39FF | Brown-out Reset disabled.
BOREN = SBODEN | 0x3BFF | Brown-out Reset controlled by the SBOREN bit in the BORCON register.
BOREN = NSLEEP | 0x3DFF | Brown-out Reset enabled while running and disabled in Sleep.
BOREN = ON | 0x3FFF | Brown-out Reset enabled.
CLKOUTEN -- Clock Out Enable (bitmask:0x0800)
CLKOUTEN = ON | 0x37FF | CLKOUT function is enabled on the CLKOUT pin.
CLKOUTEN = OFF | 0x3FFF | CLKOUT function is disabled. I/O or oscillator function on the CLKOUT pin.
IESO -- Internal/External Switchover Mode (bitmask:0x1000)
IESO = OFF | 0x2FFF | Internal/External Switchover Mode is disabled.
IESO = ON | 0x3FFF | Internal/External Switchover Mode is enabled.
FCMEN -- Fail-Safe Clock Monitor Enable (bitmask:0x2000)
FCMEN = OFF | 0x1FFF | Fail-Safe Clock Monitor is disabled.
FCMEN = ON | 0x3FFF | Fail-Safe Clock Monitor is enabled.
CONFIG2 (address:0x8008, mask:0x3FF3, default:0x3FF3)
WRT -- Flash Memory Self-Write Protection (bitmask:0x0003)
WRT = ALL | 0x3FFC | 000h to 1FFFh write protected, no addresses may be modified by PMCON control.
WRT = HALF | 0x3FFD | 000h to 0FFFh write protected, 1000h to 1FFFh may be modified by PMCON control.
WRT = BOOT | 0x3FFE | 000h to 1FFh write protected, 200h to 1FFFh may be modified by PMCON control.
WRT = OFF | 0x3FFF | Write protection off.
CPUDIV -- CPU System Clock Selection Bit (bitmask:0x0030)
CPUDIV = NOCLKDIV | 0x3FCF | NO CPU system divide.
CPUDIV = CLKDIV2 | 0x3FDF | CPU system clock divided by 2.
CPUDIV = CLKDIV3 | 0x3FEF | CPU system clock divided by 3.
CPUDIV = CLKDIV6 | 0x3FFF | CPU system clock divided by 6.
USBLSCLK -- USB Low SPeed Clock Selection bit (bitmask:0x0040)
USBLSCLK = 24MHz | 0x3FBF | System clock expects 24 MHz, FS/LS USB CLKENs divide-by is set to 4.
USBLSCLK = 48MHz | 0x3FFF | System clock expects 48 MHz, FS/LS USB CLKENs divide-by is set to 8.
PLLMULT -- PLL Multipler Selection Bit (bitmask:0x0080)
PLLMULT = 4x | 0x3F7F | 4x Output Frequency Selected.
PLLMULT = 3x | 0x3FFF | 3x Output Frequency Selected.
PLLEN -- PLL Enable Bit (bitmask:0x0100)
PLLEN = DISABLED | 0x3EFF | 3x or 4x PLL Disabled.
PLLEN = ENABLED | 0x3FFF | 3x or 4x PLL Enabled.
STVREN -- Stack Overflow/Underflow Reset Enable (bitmask:0x0200)
STVREN = OFF | 0x3DFF | Stack Overflow or Underflow will not cause a Reset.
STVREN = ON | 0x3FFF | Stack Overflow or Underflow will cause a Reset.
BORV -- Brown-out Reset Voltage Selection (bitmask:0x0400)
BORV = HI | 0x3BFF | Brown-out Reset Voltage (Vbor), high trip point selected.
BORV = LO | 0x3FFF | Brown-out Reset Voltage (Vbor), low trip point selected.
LPBOR -- Low-Power Brown Out Reset (bitmask:0x0800)
LPBOR = ON | 0x37FF | Low-Power BOR is enabled.
LPBOR = OFF | 0x3FFF | Low-Power BOR is disabled.
DEBUG -- Debugger enable bit (bitmask:0x1000)
DEBUG = ON | 0x2FFF | Background debugger enabled.
DEBUG = OFF | 0x3FFF | Background debugger disabled.
LVP -- Low-Voltage Programming Enable (bitmask:0x2000)
LVP = OFF | 0x1FFF | High-voltage on MCLR/VPP must be used for programming.
LVP = ON | 0x3FFF | Low-voltage programming enabled.

This page generated automatically by the device-help.pl program (2016-09-12 18:02:33 UTC) from the 8bit_device.info file (rev: 1.31) of mpasmx and from the gputils source package (rev: svn Unversioned directory). The mpasmx is included in the MPLAB X.