MANIFEST.in
README.md
setup.py
pythondata_cpu_mor1kx/__init__.py
pythondata_cpu_mor1kx.egg-info/PKG-INFO
pythondata_cpu_mor1kx.egg-info/SOURCES.txt
pythondata_cpu_mor1kx.egg-info/dependency_links.txt
pythondata_cpu_mor1kx.egg-info/not-zip-safe
pythondata_cpu_mor1kx.egg-info/top_level.txt
pythondata_cpu_mor1kx/verilog/.gitignore
pythondata_cpu_mor1kx/verilog/.travis.yml
pythondata_cpu_mor1kx/verilog/Jenkinsfile
pythondata_cpu_mor1kx/verilog/LICENSE
pythondata_cpu_mor1kx/verilog/README.md
pythondata_cpu_mor1kx/verilog/mor1kx.core
pythondata_cpu_mor1kx/verilog/.travis/run-or1k-tests.sh
pythondata_cpu_mor1kx/verilog/.travis/run-verilator.sh
pythondata_cpu_mor1kx/verilog/.travis/test.sh
pythondata_cpu_mor1kx/verilog/bench/verilog/mor1kx_monitor.v
pythondata_cpu_mor1kx/verilog/bench/verilog/mor1kx_traceport_monitor.v
pythondata_cpu_mor1kx/verilog/doc/Makefile
pythondata_cpu_mor1kx/verilog/doc/docbook-xsl.css
pythondata_cpu_mor1kx/verilog/doc/docbook.xsl
pythondata_cpu_mor1kx/verilog/doc/gen-docinfo.pl
pythondata_cpu_mor1kx/verilog/doc/mor1kx.asciidoc
pythondata_cpu_mor1kx/verilog/rtl/verilog/mor1kx-defines.v
pythondata_cpu_mor1kx/verilog/rtl/verilog/mor1kx-sprs.v
pythondata_cpu_mor1kx/verilog/rtl/verilog/mor1kx.v
pythondata_cpu_mor1kx/verilog/rtl/verilog/mor1kx_branch_prediction.v
pythondata_cpu_mor1kx/verilog/rtl/verilog/mor1kx_branch_predictor_gshare.v
pythondata_cpu_mor1kx/verilog/rtl/verilog/mor1kx_branch_predictor_saturation_counter.v
pythondata_cpu_mor1kx/verilog/rtl/verilog/mor1kx_branch_predictor_simple.v
pythondata_cpu_mor1kx/verilog/rtl/verilog/mor1kx_bus_if_wb32.v
pythondata_cpu_mor1kx/verilog/rtl/verilog/mor1kx_cache_lru.v
pythondata_cpu_mor1kx/verilog/rtl/verilog/mor1kx_cfgrs.v
pythondata_cpu_mor1kx/verilog/rtl/verilog/mor1kx_cpu.v
pythondata_cpu_mor1kx/verilog/rtl/verilog/mor1kx_cpu_cappuccino.v
pythondata_cpu_mor1kx/verilog/rtl/verilog/mor1kx_cpu_espresso.v
pythondata_cpu_mor1kx/verilog/rtl/verilog/mor1kx_cpu_prontoespresso.v
pythondata_cpu_mor1kx/verilog/rtl/verilog/mor1kx_ctrl_cappuccino.v
pythondata_cpu_mor1kx/verilog/rtl/verilog/mor1kx_ctrl_espresso.v
pythondata_cpu_mor1kx/verilog/rtl/verilog/mor1kx_ctrl_prontoespresso.v
pythondata_cpu_mor1kx/verilog/rtl/verilog/mor1kx_dcache.v
pythondata_cpu_mor1kx/verilog/rtl/verilog/mor1kx_decode.v
pythondata_cpu_mor1kx/verilog/rtl/verilog/mor1kx_decode_execute_cappuccino.v
pythondata_cpu_mor1kx/verilog/rtl/verilog/mor1kx_dmmu.v
pythondata_cpu_mor1kx/verilog/rtl/verilog/mor1kx_execute_alu.v
pythondata_cpu_mor1kx/verilog/rtl/verilog/mor1kx_execute_ctrl_cappuccino.v
pythondata_cpu_mor1kx/verilog/rtl/verilog/mor1kx_fetch_cappuccino.v
pythondata_cpu_mor1kx/verilog/rtl/verilog/mor1kx_fetch_espresso.v
pythondata_cpu_mor1kx/verilog/rtl/verilog/mor1kx_fetch_prontoespresso.v
pythondata_cpu_mor1kx/verilog/rtl/verilog/mor1kx_fetch_tcm_prontoespresso.v
pythondata_cpu_mor1kx/verilog/rtl/verilog/mor1kx_icache.v
pythondata_cpu_mor1kx/verilog/rtl/verilog/mor1kx_immu.v
pythondata_cpu_mor1kx/verilog/rtl/verilog/mor1kx_lsu_cappuccino.v
pythondata_cpu_mor1kx/verilog/rtl/verilog/mor1kx_lsu_espresso.v
pythondata_cpu_mor1kx/verilog/rtl/verilog/mor1kx_pcu.v
pythondata_cpu_mor1kx/verilog/rtl/verilog/mor1kx_pic.v
pythondata_cpu_mor1kx/verilog/rtl/verilog/mor1kx_rf_cappuccino.v
pythondata_cpu_mor1kx/verilog/rtl/verilog/mor1kx_rf_espresso.v
pythondata_cpu_mor1kx/verilog/rtl/verilog/mor1kx_simple_dpram_sclk.v
pythondata_cpu_mor1kx/verilog/rtl/verilog/mor1kx_store_buffer.v
pythondata_cpu_mor1kx/verilog/rtl/verilog/mor1kx_ticktimer.v
pythondata_cpu_mor1kx/verilog/rtl/verilog/mor1kx_true_dpram_sclk.v
pythondata_cpu_mor1kx/verilog/rtl/verilog/mor1kx_utils.vh
pythondata_cpu_mor1kx/verilog/rtl/verilog/mor1kx_wb_mux_cappuccino.v
pythondata_cpu_mor1kx/verilog/rtl/verilog/mor1kx_wb_mux_espresso.v
pythondata_cpu_mor1kx/verilog/rtl/verilog/pfpu32/pfpu32_addsub.v
pythondata_cpu_mor1kx/verilog/rtl/verilog/pfpu32/pfpu32_cmp.v
pythondata_cpu_mor1kx/verilog/rtl/verilog/pfpu32/pfpu32_f2i.v
pythondata_cpu_mor1kx/verilog/rtl/verilog/pfpu32/pfpu32_i2f.v
pythondata_cpu_mor1kx/verilog/rtl/verilog/pfpu32/pfpu32_muldiv.v
pythondata_cpu_mor1kx/verilog/rtl/verilog/pfpu32/pfpu32_rnd.v
pythondata_cpu_mor1kx/verilog/rtl/verilog/pfpu32/pfpu32_top.v