MANIFEST.in
README.md
setup.py
litex/__init__.py
litex.egg-info/PKG-INFO
litex.egg-info/SOURCES.txt
litex.egg-info/dependency_links.txt
litex.egg-info/entry_points.txt
litex.egg-info/requires.txt
litex.egg-info/top_level.txt
litex/boards/__init__.py
litex/boards/platforms/__init__.py
litex/boards/platforms/arty.py
litex/boards/platforms/avalanche.py
litex/boards/platforms/de0nano.py
litex/boards/platforms/genesys2.py
litex/boards/platforms/icebreaker.py
litex/boards/platforms/kc705.py
litex/boards/platforms/kcu105.py
litex/boards/platforms/machxo3.py
litex/boards/platforms/minispartan6.py
litex/boards/platforms/netv2.py
litex/boards/platforms/nexys4ddr.py
litex/boards/platforms/nexys_video.py
litex/boards/platforms/pcie_screamer.py
litex/boards/platforms/tinyfpga_bx.py
litex/boards/platforms/ulx3s.py
litex/boards/platforms/versa_ecp5.py
litex/boards/targets/__init__.py
litex/boards/targets/arty.py
litex/boards/targets/de0nano.py
litex/boards/targets/genesys2.py
litex/boards/targets/icebreaker.py
litex/boards/targets/kc705.py
litex/boards/targets/kcu105.py
litex/boards/targets/minispartan6.py
litex/boards/targets/netv2.py
litex/boards/targets/nexys4ddr.py
litex/boards/targets/nexys_video.py
litex/boards/targets/pcie_screamer.py
litex/boards/targets/simple.py
litex/boards/targets/ulx3s.py
litex/boards/targets/versa_ecp5.py
litex/build/__init__.py
litex/build/generic_platform.py
litex/build/generic_programmer.py
litex/build/io.py
litex/build/openocd.py
litex/build/tools.py
litex/build/altera/__init__.py
litex/build/altera/common.py
litex/build/altera/platform.py
litex/build/altera/programmer.py
litex/build/altera/quartus.py
litex/build/lattice/__init__.py
litex/build/lattice/common.py
litex/build/lattice/diamond.py
litex/build/lattice/icestorm.py
litex/build/lattice/platform.py
litex/build/lattice/programmer.py
litex/build/lattice/trellis.py
litex/build/microsemi/__init__.py
litex/build/microsemi/common.py
litex/build/microsemi/libero_soc.py
litex/build/microsemi/platform.py
litex/build/sim/README
litex/build/sim/__init__.py
litex/build/sim/common.py
litex/build/sim/config.py
litex/build/sim/platform.py
litex/build/sim/verilator.py
litex/build/sim/core/Makefile
litex/build/sim/core/error.h
litex/build/sim/core/libdylib.c
litex/build/sim/core/libdylib.h
litex/build/sim/core/modules.c
litex/build/sim/core/modules.h
litex/build/sim/core/pads.c
litex/build/sim/core/pads.h
litex/build/sim/core/parse.c
litex/build/sim/core/sim.c
litex/build/sim/core/tinydir.h
litex/build/sim/core/veril.cpp
litex/build/sim/core/veril.h
litex/build/sim/core/modules/Makefile
litex/build/sim/core/modules/rules.mak
litex/build/sim/core/modules/clocker/Makefile
litex/build/sim/core/modules/clocker/clocker.c
litex/build/sim/core/modules/ethernet/Makefile
litex/build/sim/core/modules/ethernet/ethernet.c
litex/build/sim/core/modules/jtagremote/Makefile
litex/build/sim/core/modules/jtagremote/jtagremote.c
litex/build/sim/core/modules/serial2console/Makefile
litex/build/sim/core/modules/serial2console/serial2console.c
litex/build/sim/core/modules/serial2tcp/Makefile
litex/build/sim/core/modules/serial2tcp/serial2tcp.c
litex/build/sim/core/modules/xgmii_ethernet/Makefile
litex/build/sim/core/modules/xgmii_ethernet/xgmii_ethernet.c
litex/build/xilinx/__init__.py
litex/build/xilinx/common.py
litex/build/xilinx/ise.py
litex/build/xilinx/platform.py
litex/build/xilinx/programmer.py
litex/build/xilinx/vivado.py
litex/gen/__init__.py
litex/gen/common.py
litex/gen/io.py
litex/gen/fhdl/__init__.py
litex/gen/fhdl/verilog.py
litex/gen/sim/__init__.py
litex/gen/sim/core.py
litex/gen/sim/vcd.py
litex/soc/__init__.py
litex/soc/cores/__init__.py
litex/soc/cores/bitbang.py
litex/soc/cores/clock.py
litex/soc/cores/code_8b10b.py
litex/soc/cores/dna.py
litex/soc/cores/ecc.py
litex/soc/cores/emif.py
litex/soc/cores/freqmeter.py
litex/soc/cores/gpio.py
litex/soc/cores/hyperbus.py
litex/soc/cores/i2s.py
litex/soc/cores/icap.py
litex/soc/cores/identifier.py
litex/soc/cores/jtag.py
litex/soc/cores/prbs.py
litex/soc/cores/pwm.py
litex/soc/cores/spi.py
litex/soc/cores/spi_flash.py
litex/soc/cores/spi_opi.py
litex/soc/cores/timer.py
litex/soc/cores/uart.py
litex/soc/cores/up5kspram.py
litex/soc/cores/usb_fifo.py
litex/soc/cores/xadc.py
litex/soc/cores/cpu/__init__.py
litex/soc/cores/cpu/blackparrot/__init__.py
litex/soc/cores/cpu/blackparrot/core.py
litex/soc/cores/cpu/lm32/__init__.py
litex/soc/cores/cpu/lm32/core.py
litex/soc/cores/cpu/microwatt/__init__.py
litex/soc/cores/cpu/microwatt/core.py
litex/soc/cores/cpu/minerva/__init__.py
litex/soc/cores/cpu/minerva/core.py
litex/soc/cores/cpu/mor1kx/__init__.py
litex/soc/cores/cpu/mor1kx/core.py
litex/soc/cores/cpu/picorv32/__init__.py
litex/soc/cores/cpu/picorv32/core.py
litex/soc/cores/cpu/rocket/__init__.py
litex/soc/cores/cpu/rocket/core.py
litex/soc/cores/cpu/serv/__init__.py
litex/soc/cores/cpu/serv/core.py
litex/soc/cores/cpu/vexriscv/__init__.py
litex/soc/cores/cpu/vexriscv/core.py
litex/soc/doc/__init__.py
litex/soc/doc/csr.py
litex/soc/doc/module.py
litex/soc/doc/rst.py
litex/soc/integration/__init__.py
litex/soc/integration/builder.py
litex/soc/integration/common.py
litex/soc/integration/doc.py
litex/soc/integration/export.py
litex/soc/integration/soc.py
litex/soc/integration/soc_core.py
litex/soc/integration/soc_sdram.py
litex/soc/integration/soc_zynq.py
litex/soc/interconnect/__init__.py
litex/soc/interconnect/avalon.py
litex/soc/interconnect/axi.py
litex/soc/interconnect/csr.py
litex/soc/interconnect/csr_bus.py
litex/soc/interconnect/csr_eventmanager.py
litex/soc/interconnect/packet.py
litex/soc/interconnect/stream.py
litex/soc/interconnect/stream_sim.py
litex/soc/interconnect/wishbone.py
litex/soc/interconnect/wishbone2csr.py
litex/soc/interconnect/wishbonebridge.py
litex/tools/__init__.py
litex/tools/litex_client.py
litex/tools/litex_gen.py
litex/tools/litex_read_verilog.py
litex/tools/litex_server.py
litex/tools/litex_sim.py
litex/tools/litex_term.py
litex/tools/remote/__init__.py
litex/tools/remote/comm_pcie.py
litex/tools/remote/comm_uart.py
litex/tools/remote/comm_udp.py
litex/tools/remote/comm_usb.py
litex/tools/remote/csr_builder.py
litex/tools/remote/etherbone.py
test/test_axi.py
test/test_bitbang.py
test/test_clock.py
test/test_code_8b10b.py
test/test_csr.py
test/test_ecc.py
test/test_emif.py
test/test_gearbox.py
test/test_hyperbus.py
test/test_i2s.py
test/test_icap.py
test/test_packet.py
test/test_prbs.py
test/test_spi.py
test/test_spi_opi.py
test/test_stream.py
test/test_targets.py