// Hand created file. DO NOT DELETE.
// atsamd51x bitfield definitions that are not auto-generated by gen-device-svd.go

// +build sam,atsamd51

// These are the supported pchctrl function numberings on the atsamd51x
// See http://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf
// table 14-9

package sam

const (
	PCHCTRL_GCLK_OSCCTRL_DFLL48     = 0 // DFLL48 input clock source
	PCHCTRL_GCLK_OSCCTRL_FDPLL0     = 1 // Reference clock for FDPLL0
	PCHCTRL_GCLK_OSCCTRL_FDPLL1     = 2 // Reference clock for FDPLL1
	PCHCTRL_GCLK_OSCCTRL_FDPLL0_32K = 3 // FDPLL0 = 3 // 32KHz clock for internal lock timer
	PCHCTRL_GCLK_OSCCTRL_FDPLL1_32K = 3 // FDPLL1 = 3 // 32KHz clock for internal lock timer
	PCHCTRL_GCLK_SDHC0_SLOW         = 3 // SDHC0 = 3 // Slow
	PCHCTRL_GCLK_SDHC1_SLOW         = 3 // SDHC1 = 3 // Slow
	PCHCTRL_GCLK_SERCOMX_SLOW       = 3 // GCLK_SERCOM[0..7]_SLOW = 3
	PCHCTRL_GCLK_EIC                = 4
	PCHCTRL_GCLK_FREQM_MSR          = 5 // FREQM Measure
	PCHCTRL_GCLK_FREQM_REF          = 6 // FREQM Reference
	PCHCTRL_GCLK_SERCOM0_CORE       = 7 // SERCOM0 Core
	PCHCTRL_GCLK_SERCOM1_CORE       = 8 // SERCOM1 Core
	PCHCTRL_GCLK_TC0                = 9
	PCHCTRL_GCLK_TC1                = 9  // TC0, TC1
	PCHCTRL_GCLK_USB                = 10 // USB
	PCHCTRL_GCLK_EVSYS0             = 11
	PCHCTRL_GCLK_EVSYS1             = 12
	PCHCTRL_GCLK_EVSYS2             = 13
	PCHCTRL_GCLK_EVSYS3             = 14
	PCHCTRL_GCLK_EVSYS4             = 15
	PCHCTRL_GCLK_EVSYS5             = 16
	PCHCTRL_GCLK_EVSYS6             = 17
	PCHCTRL_GCLK_EVSYS7             = 18
	PCHCTRL_GCLK_EVSYS8             = 19
	PCHCTRL_GCLK_EVSYS9             = 20
	PCHCTRL_GCLK_EVSYS10            = 21
	PCHCTRL_GCLK_EVSYS11            = 22
	PCHCTRL_GCLK_SERCOM2_CORE       = 23 // SERCOM2 Core
	PCHCTRL_GCLK_SERCOM3_CORE       = 24 // SERCOM3 Core
	PCHCTRL_GCLK_TCC0               = 25
	PCHCTRL_GCLK_TCC1               = 25 // TCC0, TCC1
	PCHCTRL_GCLK_TC2                = 26
	PCHCTRL_GCLK_TC3                = 26 // TC2, TC3
	PCHCTRL_GCLK_CAN0               = 27 // CAN0
	PCHCTRL_GCLK_CAN1               = 28 // CAN1
	PCHCTRL_GCLK_TCC2               = 29
	PCHCTRL_GCLK_TCC3               = 29 // TCC2, TCC3
	PCHCTRL_GCLK_TC4                = 30
	PCHCTRL_GCLK_TC5                = 30 // TC4, TC5
	PCHCTRL_GCLK_PDEC               = 31 // PDEC
	PCHCTRL_GCLK_AC                 = 32 // AC
	PCHCTRL_GCLK_CCL                = 33 // CCL
	PCHCTRL_GCLK_SERCOM4_CORE       = 34 // SERCOM4 Core
	PCHCTRL_GCLK_SERCOM5_CORE       = 35 // SERCOM5 Core
	PCHCTRL_GCLK_SERCOM6_CORE       = 36 // SERCOM6 Core
	PCHCTRL_GCLK_SERCOM7_CORE       = 37 // SERCOM7 Core
	PCHCTRL_GCLK_TCC4               = 38 // TCC4
	PCHCTRL_GCLK_TC6                = 39
	PCHCTRL_GCLK_TC7                = 39 // TC6, TC7
	PCHCTRL_GCLK_ADC0               = 40 // ADC0
	PCHCTRL_GCLK_ADC1               = 41 // ADC1
	PCHCTRL_GCLK_DAC                = 42 // DAC
	PCHCTRL_GCLK_I2S0               = 43
	PCHCTRL_GCLK_I2S1               = 44
	PCHCTRL_GCLK_SDHC0              = 45 // SDHC0
	PCHCTRL_GCLK_SDHC1              = 46 // SDHC1
	PCHCTRL_GCLK_CM4_TRACE          = 47 // CM4 Trace
)
