// Automatically generated file. DO NOT EDIT.
// Generated by gen-device-avr.go from AT90CAN128.atdf, see http://packs.download.atmel.com/

// +build avr,at90can128

// Device information for the AT90CAN128.
package avr

import (
	"runtime/interrupt"
	"runtime/volatile"
	"unsafe"
)

// Some information about this device.
const (
	DEVICE = "AT90CAN128"
	ARCH   = "AVR8"
	FAMILY = "megaAVR"
)

// Interrupts
const (
	IRQ_RESET        = 0  // External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset and JTAG AVR Reset
	IRQ_INT0         = 1  // External Interrupt Request 0
	IRQ_INT1         = 2  // External Interrupt Request 1
	IRQ_INT2         = 3  // External Interrupt Request 2
	IRQ_INT3         = 4  // External Interrupt Request 3
	IRQ_INT4         = 5  // External Interrupt Request 4
	IRQ_INT5         = 6  // External Interrupt Request 5
	IRQ_INT6         = 7  // External Interrupt Request 6
	IRQ_INT7         = 8  // External Interrupt Request 7
	IRQ_TIMER2_COMP  = 9  // Timer/Counter2 Compare Match
	IRQ_TIMER2_OVF   = 10 // Timer/Counter2 Overflow
	IRQ_TIMER1_CAPT  = 11 // Timer/Counter1 Capture Event
	IRQ_TIMER1_COMPA = 12 // Timer/Counter1 Compare Match A
	IRQ_TIMER1_COMPB = 13 // Timer/Counter Compare Match B
	IRQ_TIMER1_COMPC = 14 // Timer/Counter1 Compare Match C
	IRQ_TIMER1_OVF   = 15 // Timer/Counter1 Overflow
	IRQ_TIMER0_COMP  = 16 // Timer/Counter0 Compare Match
	IRQ_TIMER0_OVF   = 17 // Timer/Counter0 Overflow
	IRQ_CANIT        = 18 // CAN Transfer Complete or Error
	IRQ_OVRIT        = 19 // CAN Timer Overrun
	IRQ_SPI_STC      = 20 // SPI Serial Transfer Complete
	IRQ_USART0_RX    = 21 // USART0, Rx Complete
	IRQ_USART0_UDRE  = 22 // USART0 Data Register Empty
	IRQ_USART0_TX    = 23 // USART0, Tx Complete
	IRQ_ANALOG_COMP  = 24 // Analog Comparator
	IRQ_ADC          = 25 // ADC Conversion Complete
	IRQ_EE_READY     = 26 // EEPROM Ready
	IRQ_TIMER3_CAPT  = 27 // Timer/Counter3 Capture Event
	IRQ_TIMER3_COMPA = 28 // Timer/Counter3 Compare Match A
	IRQ_TIMER3_COMPB = 29 // Timer/Counter3 Compare Match B
	IRQ_TIMER3_COMPC = 30 // Timer/Counter3 Compare Match C
	IRQ_TIMER3_OVF   = 31 // Timer/Counter3 Overflow
	IRQ_USART1_RX    = 32 // USART1, Rx Complete
	IRQ_USART1_UDRE  = 33 // USART1, Data Register Empty
	IRQ_USART1_TX    = 34 // USART1, Tx Complete
	IRQ_TWI          = 35 // 2-wire Serial Interface
	IRQ_SPM_READY    = 36 // Store Program Memory Read
	IRQ_max          = 36 // Highest interrupt number on this device.
)

// Map interrupt numbers to function names.
// These aren't real calls, they're removed by the compiler.
var (
	_ = interrupt.Register(IRQ_RESET, "__vector_RESET")
	_ = interrupt.Register(IRQ_INT0, "__vector_INT0")
	_ = interrupt.Register(IRQ_INT1, "__vector_INT1")
	_ = interrupt.Register(IRQ_INT2, "__vector_INT2")
	_ = interrupt.Register(IRQ_INT3, "__vector_INT3")
	_ = interrupt.Register(IRQ_INT4, "__vector_INT4")
	_ = interrupt.Register(IRQ_INT5, "__vector_INT5")
	_ = interrupt.Register(IRQ_INT6, "__vector_INT6")
	_ = interrupt.Register(IRQ_INT7, "__vector_INT7")
	_ = interrupt.Register(IRQ_TIMER2_COMP, "__vector_TIMER2_COMP")
	_ = interrupt.Register(IRQ_TIMER2_OVF, "__vector_TIMER2_OVF")
	_ = interrupt.Register(IRQ_TIMER1_CAPT, "__vector_TIMER1_CAPT")
	_ = interrupt.Register(IRQ_TIMER1_COMPA, "__vector_TIMER1_COMPA")
	_ = interrupt.Register(IRQ_TIMER1_COMPB, "__vector_TIMER1_COMPB")
	_ = interrupt.Register(IRQ_TIMER1_COMPC, "__vector_TIMER1_COMPC")
	_ = interrupt.Register(IRQ_TIMER1_OVF, "__vector_TIMER1_OVF")
	_ = interrupt.Register(IRQ_TIMER0_COMP, "__vector_TIMER0_COMP")
	_ = interrupt.Register(IRQ_TIMER0_OVF, "__vector_TIMER0_OVF")
	_ = interrupt.Register(IRQ_CANIT, "__vector_CANIT")
	_ = interrupt.Register(IRQ_OVRIT, "__vector_OVRIT")
	_ = interrupt.Register(IRQ_SPI_STC, "__vector_SPI_STC")
	_ = interrupt.Register(IRQ_USART0_RX, "__vector_USART0_RX")
	_ = interrupt.Register(IRQ_USART0_UDRE, "__vector_USART0_UDRE")
	_ = interrupt.Register(IRQ_USART0_TX, "__vector_USART0_TX")
	_ = interrupt.Register(IRQ_ANALOG_COMP, "__vector_ANALOG_COMP")
	_ = interrupt.Register(IRQ_ADC, "__vector_ADC")
	_ = interrupt.Register(IRQ_EE_READY, "__vector_EE_READY")
	_ = interrupt.Register(IRQ_TIMER3_CAPT, "__vector_TIMER3_CAPT")
	_ = interrupt.Register(IRQ_TIMER3_COMPA, "__vector_TIMER3_COMPA")
	_ = interrupt.Register(IRQ_TIMER3_COMPB, "__vector_TIMER3_COMPB")
	_ = interrupt.Register(IRQ_TIMER3_COMPC, "__vector_TIMER3_COMPC")
	_ = interrupt.Register(IRQ_TIMER3_OVF, "__vector_TIMER3_OVF")
	_ = interrupt.Register(IRQ_USART1_RX, "__vector_USART1_RX")
	_ = interrupt.Register(IRQ_USART1_UDRE, "__vector_USART1_UDRE")
	_ = interrupt.Register(IRQ_USART1_TX, "__vector_USART1_TX")
	_ = interrupt.Register(IRQ_TWI, "__vector_TWI")
	_ = interrupt.Register(IRQ_SPM_READY, "__vector_SPM_READY")
)

// Peripherals.
var (
	// Fuses
	EXTENDED = (*volatile.Register8)(unsafe.Pointer(uintptr(0x2)))
	HIGH     = (*volatile.Register8)(unsafe.Pointer(uintptr(0x1)))
	LOW      = (*volatile.Register8)(unsafe.Pointer(uintptr(0x0)))

	// Lockbits
	LOCKBIT = (*volatile.Register8)(unsafe.Pointer(uintptr(0x0)))

	// I/O Port
	PORTA = (*volatile.Register8)(unsafe.Pointer(uintptr(0x22)))
	DDRA  = (*volatile.Register8)(unsafe.Pointer(uintptr(0x21)))
	PINA  = (*volatile.Register8)(unsafe.Pointer(uintptr(0x20)))
	PORTB = (*volatile.Register8)(unsafe.Pointer(uintptr(0x25)))
	DDRB  = (*volatile.Register8)(unsafe.Pointer(uintptr(0x24)))
	PINB  = (*volatile.Register8)(unsafe.Pointer(uintptr(0x23)))
	PORTC = (*volatile.Register8)(unsafe.Pointer(uintptr(0x28)))
	DDRC  = (*volatile.Register8)(unsafe.Pointer(uintptr(0x27)))
	PINC  = (*volatile.Register8)(unsafe.Pointer(uintptr(0x26)))
	PORTD = (*volatile.Register8)(unsafe.Pointer(uintptr(0x2b)))
	DDRD  = (*volatile.Register8)(unsafe.Pointer(uintptr(0x2a)))
	PIND  = (*volatile.Register8)(unsafe.Pointer(uintptr(0x29)))
	PORTE = (*volatile.Register8)(unsafe.Pointer(uintptr(0x2e)))
	DDRE  = (*volatile.Register8)(unsafe.Pointer(uintptr(0x2d)))
	PINE  = (*volatile.Register8)(unsafe.Pointer(uintptr(0x2c)))
	PORTF = (*volatile.Register8)(unsafe.Pointer(uintptr(0x31)))
	DDRF  = (*volatile.Register8)(unsafe.Pointer(uintptr(0x30)))
	PINF  = (*volatile.Register8)(unsafe.Pointer(uintptr(0x2f)))
	PORTG = (*volatile.Register8)(unsafe.Pointer(uintptr(0x34)))
	DDRG  = (*volatile.Register8)(unsafe.Pointer(uintptr(0x33)))
	PING  = (*volatile.Register8)(unsafe.Pointer(uintptr(0x32)))

	// JTAG Interface
	OCDR = (*volatile.Register8)(unsafe.Pointer(uintptr(0x51)))

	// Serial Peripheral Interface
	SPCR = (*volatile.Register8)(unsafe.Pointer(uintptr(0x4c)))
	SPSR = (*volatile.Register8)(unsafe.Pointer(uintptr(0x4d)))
	SPDR = (*volatile.Register8)(unsafe.Pointer(uintptr(0x4e)))

	// Two Wire Serial Interface
	TWBR = (*volatile.Register8)(unsafe.Pointer(uintptr(0xb8)))
	TWCR = (*volatile.Register8)(unsafe.Pointer(uintptr(0xbc)))
	TWSR = (*volatile.Register8)(unsafe.Pointer(uintptr(0xb9)))
	TWDR = (*volatile.Register8)(unsafe.Pointer(uintptr(0xbb)))
	TWAR = (*volatile.Register8)(unsafe.Pointer(uintptr(0xba)))

	// USART
	UDR0   = (*volatile.Register8)(unsafe.Pointer(uintptr(0xc6)))
	UCSR0A = (*volatile.Register8)(unsafe.Pointer(uintptr(0xc0)))
	UCSR0B = (*volatile.Register8)(unsafe.Pointer(uintptr(0xc1)))
	UCSR0C = (*volatile.Register8)(unsafe.Pointer(uintptr(0xc2)))
	UBRR0L = (*volatile.Register8)(unsafe.Pointer(uintptr(0xc4)))
	UBRR0H = (*volatile.Register8)(unsafe.Pointer(uintptr(0xc5)))
	UDR1   = (*volatile.Register8)(unsafe.Pointer(uintptr(0xce)))
	UCSR1A = (*volatile.Register8)(unsafe.Pointer(uintptr(0xc8)))
	UCSR1B = (*volatile.Register8)(unsafe.Pointer(uintptr(0xc9)))
	UCSR1C = (*volatile.Register8)(unsafe.Pointer(uintptr(0xca)))
	UBRR1L = (*volatile.Register8)(unsafe.Pointer(uintptr(0xcc)))
	UBRR1H = (*volatile.Register8)(unsafe.Pointer(uintptr(0xcd)))

	// CPU Registers
	SREG   = (*volatile.Register8)(unsafe.Pointer(uintptr(0x5f)))
	SPL    = (*volatile.Register8)(unsafe.Pointer(uintptr(0x5d)))
	SPH    = (*volatile.Register8)(unsafe.Pointer(uintptr(0x5e)))
	XMCRA  = (*volatile.Register8)(unsafe.Pointer(uintptr(0x74)))
	XMCRB  = (*volatile.Register8)(unsafe.Pointer(uintptr(0x75)))
	OSCCAL = (*volatile.Register8)(unsafe.Pointer(uintptr(0x66)))
	CLKPR  = (*volatile.Register8)(unsafe.Pointer(uintptr(0x61)))
	SMCR   = (*volatile.Register8)(unsafe.Pointer(uintptr(0x53)))
	RAMPZ  = (*volatile.Register8)(unsafe.Pointer(uintptr(0x5b)))
	GPIOR2 = (*volatile.Register8)(unsafe.Pointer(uintptr(0x4b)))
	GPIOR1 = (*volatile.Register8)(unsafe.Pointer(uintptr(0x4a)))
	GPIOR0 = (*volatile.Register8)(unsafe.Pointer(uintptr(0x3e)))

	// Bootloader
	SPMCSR = (*volatile.Register8)(unsafe.Pointer(uintptr(0x57)))

	// External Interrupts
	EICRA = (*volatile.Register8)(unsafe.Pointer(uintptr(0x69)))
	EICRB = (*volatile.Register8)(unsafe.Pointer(uintptr(0x6a)))
	EIMSK = (*volatile.Register8)(unsafe.Pointer(uintptr(0x3d)))
	EIFR  = (*volatile.Register8)(unsafe.Pointer(uintptr(0x3c)))

	// EEPROM
	EEARL = (*volatile.Register8)(unsafe.Pointer(uintptr(0x41)))
	EEARH = (*volatile.Register8)(unsafe.Pointer(uintptr(0x42)))
	EEDR  = (*volatile.Register8)(unsafe.Pointer(uintptr(0x40)))
	EECR  = (*volatile.Register8)(unsafe.Pointer(uintptr(0x3f)))

	// Timer/Counter, 8-bit
	TCCR0A = (*volatile.Register8)(unsafe.Pointer(uintptr(0x44)))
	TCNT0  = (*volatile.Register8)(unsafe.Pointer(uintptr(0x46)))
	OCR0A  = (*volatile.Register8)(unsafe.Pointer(uintptr(0x47)))
	TIMSK0 = (*volatile.Register8)(unsafe.Pointer(uintptr(0x6e)))
	TIFR0  = (*volatile.Register8)(unsafe.Pointer(uintptr(0x35)))

	// Timer/Counter, 16-bit
	TCCR1A = (*volatile.Register8)(unsafe.Pointer(uintptr(0x80)))
	TCCR1B = (*volatile.Register8)(unsafe.Pointer(uintptr(0x81)))
	TCCR1C = (*volatile.Register8)(unsafe.Pointer(uintptr(0x82)))
	TCNT1L = (*volatile.Register8)(unsafe.Pointer(uintptr(0x84)))
	TCNT1H = (*volatile.Register8)(unsafe.Pointer(uintptr(0x85)))
	OCR1AL = (*volatile.Register8)(unsafe.Pointer(uintptr(0x88)))
	OCR1AH = (*volatile.Register8)(unsafe.Pointer(uintptr(0x89)))
	OCR1BL = (*volatile.Register8)(unsafe.Pointer(uintptr(0x8a)))
	OCR1BH = (*volatile.Register8)(unsafe.Pointer(uintptr(0x8b)))
	OCR1CL = (*volatile.Register8)(unsafe.Pointer(uintptr(0x8c)))
	OCR1CH = (*volatile.Register8)(unsafe.Pointer(uintptr(0x8d)))
	ICR1L  = (*volatile.Register8)(unsafe.Pointer(uintptr(0x86)))
	ICR1H  = (*volatile.Register8)(unsafe.Pointer(uintptr(0x87)))
	TIMSK1 = (*volatile.Register8)(unsafe.Pointer(uintptr(0x6f)))
	TIFR1  = (*volatile.Register8)(unsafe.Pointer(uintptr(0x36)))
	TCCR3A = (*volatile.Register8)(unsafe.Pointer(uintptr(0x90)))
	TCCR3B = (*volatile.Register8)(unsafe.Pointer(uintptr(0x91)))
	TCCR3C = (*volatile.Register8)(unsafe.Pointer(uintptr(0x92)))
	TCNT3L = (*volatile.Register8)(unsafe.Pointer(uintptr(0x94)))
	TCNT3H = (*volatile.Register8)(unsafe.Pointer(uintptr(0x95)))
	OCR3AL = (*volatile.Register8)(unsafe.Pointer(uintptr(0x98)))
	OCR3AH = (*volatile.Register8)(unsafe.Pointer(uintptr(0x99)))
	OCR3BL = (*volatile.Register8)(unsafe.Pointer(uintptr(0x9a)))
	OCR3BH = (*volatile.Register8)(unsafe.Pointer(uintptr(0x9b)))
	OCR3CL = (*volatile.Register8)(unsafe.Pointer(uintptr(0x9c)))
	OCR3CH = (*volatile.Register8)(unsafe.Pointer(uintptr(0x9d)))
	ICR3L  = (*volatile.Register8)(unsafe.Pointer(uintptr(0x96)))
	ICR3H  = (*volatile.Register8)(unsafe.Pointer(uintptr(0x97)))
	TIMSK3 = (*volatile.Register8)(unsafe.Pointer(uintptr(0x71)))
	TIFR3  = (*volatile.Register8)(unsafe.Pointer(uintptr(0x38)))

	// Timer/Counter, 8-bit Async
	TCCR2A = (*volatile.Register8)(unsafe.Pointer(uintptr(0xb0)))
	TCNT2  = (*volatile.Register8)(unsafe.Pointer(uintptr(0xb2)))
	OCR2A  = (*volatile.Register8)(unsafe.Pointer(uintptr(0xb3)))
	TIMSK2 = (*volatile.Register8)(unsafe.Pointer(uintptr(0x70)))
	TIFR2  = (*volatile.Register8)(unsafe.Pointer(uintptr(0x37)))
	ASSR   = (*volatile.Register8)(unsafe.Pointer(uintptr(0xb6)))

	// Watchdog Timer
	WDTCR = (*volatile.Register8)(unsafe.Pointer(uintptr(0x60)))

	// Analog-to-Digital Converter
	ADMUX  = (*volatile.Register8)(unsafe.Pointer(uintptr(0x7c)))
	ADCSRA = (*volatile.Register8)(unsafe.Pointer(uintptr(0x7a)))
	ADCL   = (*volatile.Register8)(unsafe.Pointer(uintptr(0x78)))
	ADCH   = (*volatile.Register8)(unsafe.Pointer(uintptr(0x79)))
	DIDR0  = (*volatile.Register8)(unsafe.Pointer(uintptr(0x7e)))

	// Analog Comparator
	ACSR  = (*volatile.Register8)(unsafe.Pointer(uintptr(0x50)))
	DIDR1 = (*volatile.Register8)(unsafe.Pointer(uintptr(0x7f)))

	// Controller Area Network
	CANGCON  = (*volatile.Register8)(unsafe.Pointer(uintptr(0xd8)))
	CANGSTA  = (*volatile.Register8)(unsafe.Pointer(uintptr(0xd9)))
	CANGIT   = (*volatile.Register8)(unsafe.Pointer(uintptr(0xda)))
	CANGIE   = (*volatile.Register8)(unsafe.Pointer(uintptr(0xdb)))
	CANEN2   = (*volatile.Register8)(unsafe.Pointer(uintptr(0xdc)))
	CANEN1   = (*volatile.Register8)(unsafe.Pointer(uintptr(0xdd)))
	CANIE2   = (*volatile.Register8)(unsafe.Pointer(uintptr(0xde)))
	CANIE1   = (*volatile.Register8)(unsafe.Pointer(uintptr(0xdf)))
	CANSIT2  = (*volatile.Register8)(unsafe.Pointer(uintptr(0xe0)))
	CANSIT1  = (*volatile.Register8)(unsafe.Pointer(uintptr(0xe1)))
	CANBT1   = (*volatile.Register8)(unsafe.Pointer(uintptr(0xe2)))
	CANBT2   = (*volatile.Register8)(unsafe.Pointer(uintptr(0xe3)))
	CANBT3   = (*volatile.Register8)(unsafe.Pointer(uintptr(0xe4)))
	CANTCON  = (*volatile.Register8)(unsafe.Pointer(uintptr(0xe5)))
	CANTIML  = (*volatile.Register8)(unsafe.Pointer(uintptr(0xe6)))
	CANTIMH  = (*volatile.Register8)(unsafe.Pointer(uintptr(0xe7)))
	CANTTCL  = (*volatile.Register8)(unsafe.Pointer(uintptr(0xe8)))
	CANTTCH  = (*volatile.Register8)(unsafe.Pointer(uintptr(0xe9)))
	CANTEC   = (*volatile.Register8)(unsafe.Pointer(uintptr(0xea)))
	CANREC   = (*volatile.Register8)(unsafe.Pointer(uintptr(0xeb)))
	CANHPMOB = (*volatile.Register8)(unsafe.Pointer(uintptr(0xec)))
	CANPAGE  = (*volatile.Register8)(unsafe.Pointer(uintptr(0xed)))
	CANSTMOB = (*volatile.Register8)(unsafe.Pointer(uintptr(0xee)))
	CANCDMOB = (*volatile.Register8)(unsafe.Pointer(uintptr(0xef)))
	CANIDT4  = (*volatile.Register8)(unsafe.Pointer(uintptr(0xf0)))
	CANIDT3  = (*volatile.Register8)(unsafe.Pointer(uintptr(0xf1)))
	CANIDT2  = (*volatile.Register8)(unsafe.Pointer(uintptr(0xf2)))
	CANIDT1  = (*volatile.Register8)(unsafe.Pointer(uintptr(0xf3)))
	CANIDM4  = (*volatile.Register8)(unsafe.Pointer(uintptr(0xf4)))
	CANIDM3  = (*volatile.Register8)(unsafe.Pointer(uintptr(0xf5)))
	CANIDM2  = (*volatile.Register8)(unsafe.Pointer(uintptr(0xf6)))
	CANIDM1  = (*volatile.Register8)(unsafe.Pointer(uintptr(0xf7)))
	CANSTML  = (*volatile.Register8)(unsafe.Pointer(uintptr(0xf8)))
	CANSTMH  = (*volatile.Register8)(unsafe.Pointer(uintptr(0xf9)))
	CANMSG   = (*volatile.Register8)(unsafe.Pointer(uintptr(0xfa)))
)

// Bitfields for FUSE: Fuses
const (
	// EXTENDED
	EXTENDED_BODLEVEL0 = 0x2 // Brown-out Detector trigger level
	EXTENDED_BODLEVEL1 = 0x4 // Brown-out Detector trigger level
	EXTENDED_BODLEVEL2 = 0x8 // Brown-out Detector trigger level
	EXTENDED_TA0SEL    = 0x1 // Reserved for factory tests

	// HIGH
	HIGH_OCDEN   = 0x80 // On-Chip Debug Enabled
	HIGH_JTAGEN  = 0x40 // JTAG Interface Enabled
	HIGH_SPIEN   = 0x20 // Serial program downloading (SPI) enabled
	HIGH_WDTON   = 0x10 // Watchdog timer always on
	HIGH_EESAVE  = 0x8  // Preserve EEPROM through the Chip Erase cycle
	HIGH_BOOTSZ0 = 0x2  // Select Boot Size
	HIGH_BOOTSZ1 = 0x4  // Select Boot Size
	HIGH_BOOTRST = 0x1  // Boot Reset vector Enabled

	// LOW
	LOW_CKDIV8     = 0x80 // Divide clock by 8 internally; [CKDIV8=0]
	LOW_CKOUT      = 0x40 // Clock output on PORTC7; [CKOUT=0]
	LOW_SUT_CKSEL0 = 0x1  // Select Clock Source
	LOW_SUT_CKSEL1 = 0x2  // Select Clock Source
	LOW_SUT_CKSEL2 = 0x4  // Select Clock Source
	LOW_SUT_CKSEL3 = 0x8  // Select Clock Source
	LOW_SUT_CKSEL4 = 0x10 // Select Clock Source
	LOW_SUT_CKSEL5 = 0x20 // Select Clock Source
)

// Bitfields for LOCKBIT: Lockbits
const (
	// LOCKBIT
	LOCKBIT_LB0   = 0x1  // Memory Lock
	LOCKBIT_LB1   = 0x2  // Memory Lock
	LOCKBIT_BLB00 = 0x4  // Boot Loader Protection Mode
	LOCKBIT_BLB01 = 0x8  // Boot Loader Protection Mode
	LOCKBIT_BLB10 = 0x10 // Boot Loader Protection Mode
	LOCKBIT_BLB11 = 0x20 // Boot Loader Protection Mode
)

// Bitfields for SPI: Serial Peripheral Interface
const (
	// SPCR: SPI Control Register
	SPCR_SPIE = 0x80 // SPI Interrupt Enable
	SPCR_SPE  = 0x40 // SPI Enable
	SPCR_DORD = 0x20 // Data Order
	SPCR_MSTR = 0x10 // Master/Slave Select
	SPCR_CPOL = 0x8  // Clock polarity
	SPCR_CPHA = 0x4  // Clock Phase
	SPCR_SPR0 = 0x1  // SPI Clock Rate Selects
	SPCR_SPR1 = 0x2  // SPI Clock Rate Selects

	// SPSR: SPI Status Register
	SPSR_SPIF  = 0x80 // SPI Interrupt Flag
	SPSR_WCOL  = 0x40 // Write Collision Flag
	SPSR_SPI2X = 0x1  // Double SPI Speed Bit

	// SPDR: SPI Data Register
	SPDR_SPD0 = 0x1  // SPI Data Register
	SPDR_SPD1 = 0x2  // SPI Data Register
	SPDR_SPD2 = 0x4  // SPI Data Register
	SPDR_SPD3 = 0x8  // SPI Data Register
	SPDR_SPD4 = 0x10 // SPI Data Register
	SPDR_SPD5 = 0x20 // SPI Data Register
	SPDR_SPD6 = 0x40 // SPI Data Register
	SPDR_SPD7 = 0x80 // SPI Data Register
)

// Bitfields for TWI: Two Wire Serial Interface
const (
	// TWCR: TWI Control Register
	TWCR_TWINT = 0x80 // TWI Interrupt Flag
	TWCR_TWEA  = 0x40 // TWI Enable Acknowledge Bit
	TWCR_TWSTA = 0x20 // TWI Start Condition Bit
	TWCR_TWSTO = 0x10 // TWI Stop Condition Bit
	TWCR_TWWC  = 0x8  // TWI Write Collition Flag
	TWCR_TWEN  = 0x4  // TWI Enable Bit
	TWCR_TWIE  = 0x1  // TWI Interrupt Enable

	// TWSR: TWI Status Register
	TWSR_TWS0  = 0x8  // TWI Status
	TWSR_TWS1  = 0x10 // TWI Status
	TWSR_TWS2  = 0x20 // TWI Status
	TWSR_TWS3  = 0x40 // TWI Status
	TWSR_TWS4  = 0x80 // TWI Status
	TWSR_TWPS0 = 0x1  // TWI Prescaler
	TWSR_TWPS1 = 0x2  // TWI Prescaler

	// TWAR: TWI (Slave) Address register
	TWAR_TWA0  = 0x2  // TWI (Slave) Address register Bits
	TWAR_TWA1  = 0x4  // TWI (Slave) Address register Bits
	TWAR_TWA2  = 0x8  // TWI (Slave) Address register Bits
	TWAR_TWA3  = 0x10 // TWI (Slave) Address register Bits
	TWAR_TWA4  = 0x20 // TWI (Slave) Address register Bits
	TWAR_TWA5  = 0x40 // TWI (Slave) Address register Bits
	TWAR_TWA6  = 0x80 // TWI (Slave) Address register Bits
	TWAR_TWGCE = 0x1  // TWI General Call Recognition Enable Bit
)

// Bitfields for USART: USART
const (
	// UCSR0A: USART Control and Status Register A
	UCSR0A_RXC0  = 0x80 // USART Receive Complete
	UCSR0A_TXC0  = 0x40 // USART Transmitt Complete
	UCSR0A_UDRE0 = 0x20 // USART Data Register Empty
	UCSR0A_FE0   = 0x10 // Framing Error
	UCSR0A_DOR0  = 0x8  // Data overRun
	UCSR0A_UPE0  = 0x4  // Parity Error
	UCSR0A_U2X0  = 0x2  // Double the USART transmission speed
	UCSR0A_MPCM0 = 0x1  // Multi-processor Communication Mode

	// UCSR0B: USART Control and Status Register B
	UCSR0B_RXCIE0 = 0x80 // RX Complete Interrupt Enable
	UCSR0B_TXCIE0 = 0x40 // TX Complete Interrupt Enable
	UCSR0B_UDRIE0 = 0x20 // USART Data register Empty Interrupt Enable
	UCSR0B_RXEN0  = 0x10 // Receiver Enable
	UCSR0B_TXEN0  = 0x8  // Transmitter Enable
	UCSR0B_UCSZ02 = 0x4  // Character Size
	UCSR0B_RXB80  = 0x2  // Receive Data Bit 8
	UCSR0B_TXB80  = 0x1  // Transmit Data Bit 8

	// UCSR0C: USART Control and Status Register C
	UCSR0C_UMSEL0 = 0x40 // USART Mode Select
	UCSR0C_UPM00  = 0x10 // Parity Mode Bits
	UCSR0C_UPM01  = 0x20 // Parity Mode Bits
	UCSR0C_USBS0  = 0x8  // Stop Bit Select
	UCSR0C_UCSZ00 = 0x2  // Character Size
	UCSR0C_UCSZ01 = 0x4  // Character Size
	UCSR0C_UCPOL0 = 0x1  // Clock Polarity

	// UCSR1A: USART Control and Status Register A
	UCSR1A_RXC1  = 0x80 // USART Receive Complete
	UCSR1A_TXC1  = 0x40 // USART Transmitt Complete
	UCSR1A_UDRE1 = 0x20 // USART Data Register Empty
	UCSR1A_FE1   = 0x10 // Framing Error
	UCSR1A_DOR1  = 0x8  // Data overRun
	UCSR1A_UPE1  = 0x4  // Parity Error
	UCSR1A_U2X1  = 0x2  // Double the USART transmission speed
	UCSR1A_MPCM1 = 0x1  // Multi-processor Communication Mode

	// UCSR1B: USART Control and Status Register B
	UCSR1B_RXCIE1 = 0x80 // RX Complete Interrupt Enable
	UCSR1B_TXCIE1 = 0x40 // TX Complete Interrupt Enable
	UCSR1B_UDRIE1 = 0x20 // USART Data register Empty Interrupt Enable
	UCSR1B_RXEN1  = 0x10 // Receiver Enable
	UCSR1B_TXEN1  = 0x8  // Transmitter Enable
	UCSR1B_UCSZ12 = 0x4  // Character Size
	UCSR1B_RXB81  = 0x2  // Receive Data Bit 8
	UCSR1B_TXB81  = 0x1  // Transmit Data Bit 8

	// UCSR1C: USART Control and Status Register C
	UCSR1C_UMSEL1 = 0x40 // USART Mode Select
	UCSR1C_UPM10  = 0x10 // Parity Mode Bits
	UCSR1C_UPM11  = 0x20 // Parity Mode Bits
	UCSR1C_USBS1  = 0x8  // Stop Bit Select
	UCSR1C_UCSZ10 = 0x2  // Character Size
	UCSR1C_UCSZ11 = 0x4  // Character Size
	UCSR1C_UCPOL1 = 0x1  // Clock Polarity
)

// Bitfields for CPU: CPU Registers
const (
	// SREG: Status Register
	SREG_I = 0x80 // Global Interrupt Enable
	SREG_T = 0x40 // Bit Copy Storage
	SREG_H = 0x20 // Half Carry Flag
	SREG_S = 0x10 // Sign Bit
	SREG_V = 0x8  // Two's Complement Overflow Flag
	SREG_N = 0x4  // Negative Flag
	SREG_Z = 0x2  // Zero Flag
	SREG_C = 0x1  // Carry Flag

	// XMCRA: External Memory Control Register A
	XMCRA_SRE   = 0x80 // External SRAM Enable
	XMCRA_SRL0  = 0x10 // Wait state page limit
	XMCRA_SRL1  = 0x20 // Wait state page limit
	XMCRA_SRL2  = 0x40 // Wait state page limit
	XMCRA_SRW10 = 0x4  // Wait state select bit upper page
	XMCRA_SRW11 = 0x8  // Wait state select bit upper page
	XMCRA_SRW00 = 0x1  // Wait state select bit lower page
	XMCRA_SRW01 = 0x2  // Wait state select bit lower page

	// XMCRB: External Memory Control Register B
	XMCRB_XMBK = 0x80 // External Memory Bus Keeper Enable
	XMCRB_XMM0 = 0x1  // External Memory High Mask
	XMCRB_XMM1 = 0x2  // External Memory High Mask
	XMCRB_XMM2 = 0x4  // External Memory High Mask

	// OSCCAL: Oscillator Calibration Value
	OSCCAL_OSCCAL0 = 0x1  // Oscillator Calibration
	OSCCAL_OSCCAL1 = 0x2  // Oscillator Calibration
	OSCCAL_OSCCAL2 = 0x4  // Oscillator Calibration
	OSCCAL_OSCCAL3 = 0x8  // Oscillator Calibration
	OSCCAL_OSCCAL4 = 0x10 // Oscillator Calibration
	OSCCAL_OSCCAL5 = 0x20 // Oscillator Calibration
	OSCCAL_OSCCAL6 = 0x40 // Oscillator Calibration
	OSCCAL_OSCCAL7 = 0x80 // Oscillator Calibration

	// CLKPR: Clock Prescale Register
	CLKPR_CLKPCE = 0x80
	CLKPR_CLKPS0 = 0x1
	CLKPR_CLKPS1 = 0x2
	CLKPR_CLKPS2 = 0x4
	CLKPR_CLKPS3 = 0x8

	// SMCR: Sleep Mode Control Register
	SMCR_SM0 = 0x2 // Sleep Mode Select bits
	SMCR_SM1 = 0x4 // Sleep Mode Select bits
	SMCR_SM2 = 0x8 // Sleep Mode Select bits
	SMCR_SE  = 0x1 // Sleep Enable

	// RAMPZ: RAM Page Z Select Register
	RAMPZ_RAMPZ0 = 0x1 // RAM Page Z Select Register Bit 0

	// GPIOR2: General Purpose IO Register 2
	GPIOR2_GPIOR0 = 0x1  // General Purpose IO Register 2 bis
	GPIOR2_GPIOR1 = 0x2  // General Purpose IO Register 2 bis
	GPIOR2_GPIOR2 = 0x4  // General Purpose IO Register 2 bis
	GPIOR2_GPIOR3 = 0x8  // General Purpose IO Register 2 bis
	GPIOR2_GPIOR4 = 0x10 // General Purpose IO Register 2 bis
	GPIOR2_GPIOR5 = 0x20 // General Purpose IO Register 2 bis
	GPIOR2_GPIOR6 = 0x40 // General Purpose IO Register 2 bis
	GPIOR2_GPIOR7 = 0x80 // General Purpose IO Register 2 bis

	// GPIOR1: General Purpose IO Register 1
	GPIOR1_GPIOR0 = 0x1  // General Purpose IO Register 1 bis
	GPIOR1_GPIOR1 = 0x2  // General Purpose IO Register 1 bis
	GPIOR1_GPIOR2 = 0x4  // General Purpose IO Register 1 bis
	GPIOR1_GPIOR3 = 0x8  // General Purpose IO Register 1 bis
	GPIOR1_GPIOR4 = 0x10 // General Purpose IO Register 1 bis
	GPIOR1_GPIOR5 = 0x20 // General Purpose IO Register 1 bis
	GPIOR1_GPIOR6 = 0x40 // General Purpose IO Register 1 bis
	GPIOR1_GPIOR7 = 0x80 // General Purpose IO Register 1 bis

	// GPIOR0: General Purpose IO Register 0
	GPIOR0_GPIOR07 = 0x80 // General Purpose IO Register 0 bit 7
	GPIOR0_GPIOR06 = 0x40 // General Purpose IO Register 0 bit 6
	GPIOR0_GPIOR05 = 0x20 // General Purpose IO Register 0 bit 5
	GPIOR0_GPIOR04 = 0x10 // General Purpose IO Register 0 bit 4
	GPIOR0_GPIOR03 = 0x8  // General Purpose IO Register 0 bit 3
	GPIOR0_GPIOR02 = 0x4  // General Purpose IO Register 0 bit 2
	GPIOR0_GPIOR01 = 0x2  // General Purpose IO Register 0 bit 1
	GPIOR0_GPIOR00 = 0x1  // General Purpose IO Register 0 bit 0
)

// Bitfields for BOOT_LOAD: Bootloader
const (
	// SPMCSR: Store Program Memory Control Register
	SPMCSR_SPMIE  = 0x80 // SPM Interrupt Enable
	SPMCSR_RWWSB  = 0x40 // Read While Write Section Busy
	SPMCSR_RWWSRE = 0x10 // Read While Write section read enable
	SPMCSR_BLBSET = 0x8  // Boot Lock Bit Set
	SPMCSR_PGWRT  = 0x4  // Page Write
	SPMCSR_PGERS  = 0x2  // Page Erase
	SPMCSR_SPMEN  = 0x1  // Store Program Memory Enable
)

// Bitfields for EXINT: External Interrupts
const (
	// EICRA: External Interrupt Control Register A
	EICRA_ISC30 = 0x40 // External Interrupt Sense Control Bit
	EICRA_ISC31 = 0x80 // External Interrupt Sense Control Bit
	EICRA_ISC20 = 0x10 // External Interrupt Sense Control Bit
	EICRA_ISC21 = 0x20 // External Interrupt Sense Control Bit
	EICRA_ISC10 = 0x4  // External Interrupt Sense Control Bit
	EICRA_ISC11 = 0x8  // External Interrupt Sense Control Bit
	EICRA_ISC00 = 0x1  // External Interrupt Sense Control Bit
	EICRA_ISC01 = 0x2  // External Interrupt Sense Control Bit

	// EICRB: External Interrupt Control Register B
	EICRB_ISC70 = 0x40 // External Interrupt 7-4 Sense Control Bit
	EICRB_ISC71 = 0x80 // External Interrupt 7-4 Sense Control Bit
	EICRB_ISC60 = 0x10 // External Interrupt 7-4 Sense Control Bit
	EICRB_ISC61 = 0x20 // External Interrupt 7-4 Sense Control Bit
	EICRB_ISC50 = 0x4  // External Interrupt 7-4 Sense Control Bit
	EICRB_ISC51 = 0x8  // External Interrupt 7-4 Sense Control Bit
	EICRB_ISC40 = 0x1  // External Interrupt 7-4 Sense Control Bit
	EICRB_ISC41 = 0x2  // External Interrupt 7-4 Sense Control Bit

	// EIMSK: External Interrupt Mask Register
	EIMSK_INT0 = 0x1  // External Interrupt Request 7 Enable
	EIMSK_INT1 = 0x2  // External Interrupt Request 7 Enable
	EIMSK_INT2 = 0x4  // External Interrupt Request 7 Enable
	EIMSK_INT3 = 0x8  // External Interrupt Request 7 Enable
	EIMSK_INT4 = 0x10 // External Interrupt Request 7 Enable
	EIMSK_INT5 = 0x20 // External Interrupt Request 7 Enable
	EIMSK_INT6 = 0x40 // External Interrupt Request 7 Enable
	EIMSK_INT7 = 0x80 // External Interrupt Request 7 Enable

	// EIFR: External Interrupt Flag Register
	EIFR_INTF0 = 0x1  // External Interrupt Flags
	EIFR_INTF1 = 0x2  // External Interrupt Flags
	EIFR_INTF2 = 0x4  // External Interrupt Flags
	EIFR_INTF3 = 0x8  // External Interrupt Flags
	EIFR_INTF4 = 0x10 // External Interrupt Flags
	EIFR_INTF5 = 0x20 // External Interrupt Flags
	EIFR_INTF6 = 0x40 // External Interrupt Flags
	EIFR_INTF7 = 0x80 // External Interrupt Flags
)

// Bitfields for EEPROM: EEPROM
const (
	// EEARL: EEPROM Read/Write Access Bytes

	// EEARH: EEPROM Read/Write Access Bytes
	EEAR_EEAR0 = 0x1  // EEPROM Address bits
	EEAR_EEAR1 = 0x2  // EEPROM Address bits
	EEAR_EEAR2 = 0x4  // EEPROM Address bits
	EEAR_EEAR3 = 0x8  // EEPROM Address bits
	EEAR_EEAR4 = 0x10 // EEPROM Address bits
	EEAR_EEAR5 = 0x20 // EEPROM Address bits
	EEAR_EEAR6 = 0x40 // EEPROM Address bits
	EEAR_EEAR7 = 0x80 // EEPROM Address bits

	// EEDR: EEPROM Data Register
	EEDR_EEDR0 = 0x1  // EEPROM Data bits
	EEDR_EEDR1 = 0x2  // EEPROM Data bits
	EEDR_EEDR2 = 0x4  // EEPROM Data bits
	EEDR_EEDR3 = 0x8  // EEPROM Data bits
	EEDR_EEDR4 = 0x10 // EEPROM Data bits
	EEDR_EEDR5 = 0x20 // EEPROM Data bits
	EEDR_EEDR6 = 0x40 // EEPROM Data bits
	EEDR_EEDR7 = 0x80 // EEPROM Data bits

	// EECR: EEPROM Control Register
	EECR_EERIE = 0x8 // EEPROM Ready Interrupt Enable
	EECR_EEMWE = 0x4 // EEPROM Master Write Enable
	EECR_EEWE  = 0x2 // EEPROM Write Enable
	EECR_EERE  = 0x1 // EEPROM Read Enable
)

// Bitfields for TC8: Timer/Counter, 8-bit
const (
	// TCCR0A: Timer/Counter0 Control Register
	TCCR0A_FOC0A  = 0x80 // Force Output Compare
	TCCR0A_WGM00  = 0x40 // Waveform Generation Mode 0
	TCCR0A_COM0A0 = 0x10 // Compare Match Output Modes
	TCCR0A_COM0A1 = 0x20 // Compare Match Output Modes
	TCCR0A_WGM01  = 0x8  // Waveform Generation Mode 1
	TCCR0A_CS00   = 0x1  // Clock Selects
	TCCR0A_CS01   = 0x2  // Clock Selects
	TCCR0A_CS02   = 0x4  // Clock Selects

	// OCR0A: Timer/Counter0 Output Compare Register
	OCR0A_OCR0A0 = 0x1  // Output Compare A bits
	OCR0A_OCR0A1 = 0x2  // Output Compare A bits
	OCR0A_OCR0A2 = 0x4  // Output Compare A bits
	OCR0A_OCR0A3 = 0x8  // Output Compare A bits
	OCR0A_OCR0A4 = 0x10 // Output Compare A bits
	OCR0A_OCR0A5 = 0x20 // Output Compare A bits
	OCR0A_OCR0A6 = 0x40 // Output Compare A bits
	OCR0A_OCR0A7 = 0x80 // Output Compare A bits

	// TIMSK0: Timer/Counter0 Interrupt Mask Register
	TIMSK0_OCIE0A = 0x2 // Timer/Counter0 Output Compare Match Interrupt Enable
	TIMSK0_TOIE0  = 0x1 // Timer/Counter0 Overflow Interrupt Enable

	// TIFR0: Timer/Counter0 Interrupt Flag register
	TIFR0_OCF0A = 0x2 // Timer/Counter0 Output Compare Flag 0
	TIFR0_TOV0  = 0x1 // Timer/Counter0 Overflow Flag
)

// Bitfields for TC16: Timer/Counter, 16-bit
const (
	// TCCR1A: Timer/Counter1 Control Register A
	TCCR1A_COM1A0 = 0x40 // Compare Output Mode 1A, bits
	TCCR1A_COM1A1 = 0x80 // Compare Output Mode 1A, bits
	TCCR1A_COM1B0 = 0x10 // Compare Output Mode 1B, bits
	TCCR1A_COM1B1 = 0x20 // Compare Output Mode 1B, bits
	TCCR1A_COM1C0 = 0x4  // Compare Output Mode 1C, bits
	TCCR1A_COM1C1 = 0x8  // Compare Output Mode 1C, bits
	TCCR1A_WGM10  = 0x1  // Waveform Generation Mode
	TCCR1A_WGM11  = 0x2  // Waveform Generation Mode

	// TCCR1B: Timer/Counter1 Control Register B
	TCCR1B_ICNC1 = 0x80 // Input Capture 1 Noise Canceler
	TCCR1B_ICES1 = 0x40 // Input Capture 1 Edge Select
	TCCR1B_WGM10 = 0x8  // Waveform Generation Mode
	TCCR1B_WGM11 = 0x10 // Waveform Generation Mode
	TCCR1B_CS10  = 0x1  // Prescaler source of Timer/Counter 1
	TCCR1B_CS11  = 0x2  // Prescaler source of Timer/Counter 1
	TCCR1B_CS12  = 0x4  // Prescaler source of Timer/Counter 1

	// TCCR1C: Timer/Counter 1 Control Register C
	TCCR1C_FOC1A = 0x80 // Force Output Compare 1A
	TCCR1C_FOC1B = 0x40 // Force Output Compare 1B
	TCCR1C_FOC1C = 0x20 // Force Output Compare 1C

	// TIMSK1: Timer/Counter Interrupt Mask Register
	TIMSK1_ICIE1  = 0x20 // Timer/Counter1 Input Capture Interrupt Enable
	TIMSK1_OCIE1C = 0x8  // Timer/Counter1 Output CompareC Match Interrupt Enable
	TIMSK1_OCIE1B = 0x4  // Timer/Counter1 Output CompareB Match Interrupt Enable
	TIMSK1_OCIE1A = 0x2  // Timer/Counter1 Output CompareA Match Interrupt Enable
	TIMSK1_TOIE1  = 0x1  // Timer/Counter1 Overflow Interrupt Enable

	// TIFR1: Timer/Counter Interrupt Flag register
	TIFR1_ICF1  = 0x20 // Input Capture Flag 1
	TIFR1_OCF1C = 0x8  // Output Compare Flag 1C
	TIFR1_OCF1B = 0x4  // Output Compare Flag 1B
	TIFR1_OCF1A = 0x2  // Output Compare Flag 1A
	TIFR1_TOV1  = 0x1  // Timer/Counter1 Overflow Flag

	// TCCR3A: Timer/Counter3 Control Register A
	TCCR3A_COM3A0 = 0x40 // Compare Output Mode 3A, bits
	TCCR3A_COM3A1 = 0x80 // Compare Output Mode 3A, bits
	TCCR3A_COM3B0 = 0x10 // Compare Output Mode 3B, bits
	TCCR3A_COM3B1 = 0x20 // Compare Output Mode 3B, bits
	TCCR3A_COM3C0 = 0x4  // Compare Output Mode 3C, bits
	TCCR3A_COM3C1 = 0x8  // Compare Output Mode 3C, bits
	TCCR3A_WGM30  = 0x1  // Waveform Generation Mode
	TCCR3A_WGM31  = 0x2  // Waveform Generation Mode

	// TCCR3B: Timer/Counter3 Control Register B
	TCCR3B_ICNC3 = 0x80 // Input Capture 3 Noise Canceler
	TCCR3B_ICES3 = 0x40 // Input Capture 3 Edge Select
	TCCR3B_WGM30 = 0x8  // Waveform Generation Mode
	TCCR3B_WGM31 = 0x10 // Waveform Generation Mode
	TCCR3B_CS30  = 0x1  // Prescaler source of Timer/Counter 3
	TCCR3B_CS31  = 0x2  // Prescaler source of Timer/Counter 3
	TCCR3B_CS32  = 0x4  // Prescaler source of Timer/Counter 3

	// TCCR3C: Timer/Counter 3 Control Register C
	TCCR3C_FOC3A = 0x80 // Force Output Compare 3A
	TCCR3C_FOC3B = 0x40 // Force Output Compare 3B
	TCCR3C_FOC3C = 0x20 // Force Output Compare 3C

	// TIMSK3: Timer/Counter Interrupt Mask Register
	TIMSK3_ICIE3  = 0x20 // Timer/Counter3 Input Capture Interrupt Enable
	TIMSK3_OCIE3C = 0x8  // Timer/Counter3 Output CompareC Match Interrupt Enable
	TIMSK3_OCIE3B = 0x4  // Timer/Counter3 Output CompareB Match Interrupt Enable
	TIMSK3_OCIE3A = 0x2  // Timer/Counter3 Output CompareA Match Interrupt Enable
	TIMSK3_TOIE3  = 0x1  // Timer/Counter3 Overflow Interrupt Enable

	// TIFR3: Timer/Counter Interrupt Flag register
	TIFR3_ICF3  = 0x20 // Input Capture Flag 3
	TIFR3_OCF3C = 0x8  // Output Compare Flag 3C
	TIFR3_OCF3B = 0x4  // Output Compare Flag 3B
	TIFR3_OCF3A = 0x2  // Output Compare Flag 3A
	TIFR3_TOV3  = 0x1  // Timer/Counter3 Overflow Flag
)

// Bitfields for TC8_ASYNC: Timer/Counter, 8-bit Async
const (
	// TCCR2A: Timer/Counter2 Control Register
	TCCR2A_FOC2A  = 0x80 // Force Output Compare
	TCCR2A_WGM20  = 0x40 // Waveform Genration Mode
	TCCR2A_COM2A0 = 0x10 // Compare Output Mode bits
	TCCR2A_COM2A1 = 0x20 // Compare Output Mode bits
	TCCR2A_WGM21  = 0x8  // Waveform Generation Mode
	TCCR2A_CS20   = 0x1  // Clock Select bits
	TCCR2A_CS21   = 0x2  // Clock Select bits
	TCCR2A_CS22   = 0x4  // Clock Select bits

	// TIMSK2: Timer/Counter Interrupt Mask register
	TIMSK2_OCIE2A = 0x2 // Timer/Counter2 Output Compare Match Interrupt Enable
	TIMSK2_TOIE2  = 0x1 // Timer/Counter2 Overflow Interrupt Enable

	// TIFR2: Timer/Counter Interrupt Flag Register
	TIFR2_OCF2A = 0x2 // Output Compare Flag 2
	TIFR2_TOV2  = 0x1 // Timer/Counter2 Overflow Flag

	// ASSR: Asynchronous Status Register
	ASSR_EXCLK  = 0x10 // Enable External Clock Interrupt
	ASSR_AS2    = 0x8  // AS2: Asynchronous Timer/Counter2
	ASSR_TCN2UB = 0x4  // TCN2UB: Timer/Counter2 Update Busy
	ASSR_OCR2UB = 0x2  // Output Compare Register2 Update Busy
	ASSR_TCR2UB = 0x1  // TCR2UB: Timer/Counter Control Register2 Update Busy
)

// Bitfields for WDT: Watchdog Timer
const (
	// WDTCR: Watchdog Timer Control Register
	WDTCR_WDCE = 0x10 // Watchdog Change Enable
	WDTCR_WDE  = 0x8  // Watch Dog Enable
	WDTCR_WDP0 = 0x1  // Watch Dog Timer Prescaler bits
	WDTCR_WDP1 = 0x2  // Watch Dog Timer Prescaler bits
	WDTCR_WDP2 = 0x4  // Watch Dog Timer Prescaler bits
)

// Bitfields for ADC: Analog-to-Digital Converter
const (
	// ADMUX: The ADC multiplexer Selection Register
	ADMUX_REFS0 = 0x40 // Reference Selection Bits
	ADMUX_REFS1 = 0x80 // Reference Selection Bits
	ADMUX_ADLAR = 0x20 // Left Adjust Result
	ADMUX_MUX0  = 0x1  // Analog Channel and Gain Selection Bits
	ADMUX_MUX1  = 0x2  // Analog Channel and Gain Selection Bits
	ADMUX_MUX2  = 0x4  // Analog Channel and Gain Selection Bits
	ADMUX_MUX3  = 0x8  // Analog Channel and Gain Selection Bits
	ADMUX_MUX4  = 0x10 // Analog Channel and Gain Selection Bits

	// ADCSRA: The ADC Control and Status register
	ADCSRA_ADEN  = 0x80 // ADC Enable
	ADCSRA_ADSC  = 0x40 // ADC Start Conversion
	ADCSRA_ADATE = 0x20 // ADC Auto Trigger Enable
	ADCSRA_ADIF  = 0x10 // ADC Interrupt Flag
	ADCSRA_ADIE  = 0x8  // ADC Interrupt Enable
	ADCSRA_ADPS0 = 0x1  // ADC  Prescaler Select Bits
	ADCSRA_ADPS1 = 0x2  // ADC  Prescaler Select Bits
	ADCSRA_ADPS2 = 0x4  // ADC  Prescaler Select Bits

	// DIDR0: Digital Input Disable Register 1
	DIDR0_ADC7D = 0x80 // ADC7 Digital input Disable
	DIDR0_ADC6D = 0x40 // ADC6 Digital input Disable
	DIDR0_ADC5D = 0x20 // ADC5 Digital input Disable
	DIDR0_ADC4D = 0x10 // ADC4 Digital input Disable
	DIDR0_ADC3D = 0x8  // ADC3 Digital input Disable
	DIDR0_ADC2D = 0x4  // ADC2 Digital input Disable
	DIDR0_ADC1D = 0x2  // ADC1 Digital input Disable
	DIDR0_ADC0D = 0x1  // ADC0 Digital input Disable
)

// Bitfields for AC: Analog Comparator
const (
	// ACSR: Analog Comparator Control And Status Register
	ACSR_ACD   = 0x80 // Analog Comparator Disable
	ACSR_ACBG  = 0x40 // Analog Comparator Bandgap Select
	ACSR_ACO   = 0x20 // Analog Compare Output
	ACSR_ACI   = 0x10 // Analog Comparator Interrupt Flag
	ACSR_ACIE  = 0x8  // Analog Comparator Interrupt Enable
	ACSR_ACIC  = 0x4  // Analog Comparator Input Capture Enable
	ACSR_ACIS0 = 0x1  // Analog Comparator Interrupt Mode Select bits
	ACSR_ACIS1 = 0x2  // Analog Comparator Interrupt Mode Select bits

	// DIDR1
	DIDR1_AIN1D = 0x2 // AIN1 Digital Input Disable
	DIDR1_AIN0D = 0x1 // AIN0 Digital Input Disable
)

// Bitfields for CAN: Controller Area Network
const (
	// CANGCON: CAN General Control Register
	CANGCON_ABRQ   = 0x80 // Abort Request
	CANGCON_OVRQ   = 0x40 // Overload Frame Request
	CANGCON_TTC    = 0x20 // Time Trigger Communication
	CANGCON_SYNTTC = 0x10 // Synchronization of TTC
	CANGCON_LISTEN = 0x8  // Listening Mode
	CANGCON_TEST   = 0x4  // Test Mode
	CANGCON_ENASTB = 0x2  // Enable / Standby
	CANGCON_SWRES  = 0x1  // Software Reset Request

	// CANGSTA: CAN General Status Register
	CANGSTA_OVRG  = 0x40 // Overload Frame Flag
	CANGSTA_TXBSY = 0x10 // Transmitter Busy
	CANGSTA_RXBSY = 0x8  // Receiver Busy
	CANGSTA_ENFG  = 0x4  // Enable Flag
	CANGSTA_BOFF  = 0x2  // Bus Off Mode
	CANGSTA_ERRP  = 0x1  // Error Passive Mode

	// CANGIT: CAN General Interrupt Register
	CANGIT_CANIT  = 0x80 // General Interrupt Flag
	CANGIT_BOFFIT = 0x40 // Bus Off Interrupt Flag
	CANGIT_OVRTIM = 0x20 // Overrun CAN Timer
	CANGIT_BXOK   = 0x10 // Burst Receive Interrupt
	CANGIT_SERG   = 0x8  // Stuff Error General
	CANGIT_CERG   = 0x4  // CRC Error General
	CANGIT_FERG   = 0x2  // Form Error General
	CANGIT_AERG   = 0x1  // Ackknowledgement Error General

	// CANGIE: CAN General Interrupt Enable Register
	CANGIE_ENIT   = 0x80 // Enable all Interrupts
	CANGIE_ENBOFF = 0x40 // Enable Bus Off INterrupt
	CANGIE_ENRX   = 0x20 // Enable Receive Interrupt
	CANGIE_ENTX   = 0x10 // Enable Transmitt Interrupt
	CANGIE_ENERR  = 0x8  // Enable MOb Error Interrupt
	CANGIE_ENBX   = 0x4  // Enable Burst Receive Interrupt
	CANGIE_ENERG  = 0x2  // Enable General Error Interrupt
	CANGIE_ENOVRT = 0x1  // Enable CAN Timer Overrun Interrupt

	// CANEN2: Enable MOb Register
	CANEN2_ENMOB0 = 0x1  // Enable MOb
	CANEN2_ENMOB1 = 0x2  // Enable MOb
	CANEN2_ENMOB2 = 0x4  // Enable MOb
	CANEN2_ENMOB3 = 0x8  // Enable MOb
	CANEN2_ENMOB4 = 0x10 // Enable MOb
	CANEN2_ENMOB5 = 0x20 // Enable MOb
	CANEN2_ENMOB6 = 0x40 // Enable MOb
	CANEN2_ENMOB7 = 0x80 // Enable MOb

	// CANEN1: Enable MOb Register
	CANEN1_ENMOB0 = 0x1  // Enable MOb
	CANEN1_ENMOB1 = 0x2  // Enable MOb
	CANEN1_ENMOB2 = 0x4  // Enable MOb
	CANEN1_ENMOB3 = 0x8  // Enable MOb
	CANEN1_ENMOB4 = 0x10 // Enable MOb
	CANEN1_ENMOB5 = 0x20 // Enable MOb
	CANEN1_ENMOB6 = 0x40 // Enable MOb

	// CANIE2: Enable Interrupt MOb Register
	CANIE2_IEMOB0 = 0x1  // Interrupt Enable by MOb
	CANIE2_IEMOB1 = 0x2  // Interrupt Enable by MOb
	CANIE2_IEMOB2 = 0x4  // Interrupt Enable by MOb
	CANIE2_IEMOB3 = 0x8  // Interrupt Enable by MOb
	CANIE2_IEMOB4 = 0x10 // Interrupt Enable by MOb
	CANIE2_IEMOB5 = 0x20 // Interrupt Enable by MOb
	CANIE2_IEMOB6 = 0x40 // Interrupt Enable by MOb
	CANIE2_IEMOB7 = 0x80 // Interrupt Enable by MOb

	// CANIE1: Enable Interrupt MOb Register
	CANIE1_IEMOB0 = 0x1  // Interrupt Enable by MOb
	CANIE1_IEMOB1 = 0x2  // Interrupt Enable by MOb
	CANIE1_IEMOB2 = 0x4  // Interrupt Enable by MOb
	CANIE1_IEMOB3 = 0x8  // Interrupt Enable by MOb
	CANIE1_IEMOB4 = 0x10 // Interrupt Enable by MOb
	CANIE1_IEMOB5 = 0x20 // Interrupt Enable by MOb
	CANIE1_IEMOB6 = 0x40 // Interrupt Enable by MOb

	// CANSIT2: CAN Status Interrupt MOb Register
	CANSIT2_SIT0 = 0x1  // Status of Interrupt by MOb
	CANSIT2_SIT1 = 0x2  // Status of Interrupt by MOb
	CANSIT2_SIT2 = 0x4  // Status of Interrupt by MOb
	CANSIT2_SIT3 = 0x8  // Status of Interrupt by MOb
	CANSIT2_SIT4 = 0x10 // Status of Interrupt by MOb
	CANSIT2_SIT5 = 0x20 // Status of Interrupt by MOb
	CANSIT2_SIT6 = 0x40 // Status of Interrupt by MOb
	CANSIT2_SIT7 = 0x80 // Status of Interrupt by MOb

	// CANSIT1: CAN Status Interrupt MOb Register
	CANSIT1_SIT0 = 0x1  // Status of Interrupt by MOb
	CANSIT1_SIT1 = 0x2  // Status of Interrupt by MOb
	CANSIT1_SIT2 = 0x4  // Status of Interrupt by MOb
	CANSIT1_SIT3 = 0x8  // Status of Interrupt by MOb
	CANSIT1_SIT4 = 0x10 // Status of Interrupt by MOb
	CANSIT1_SIT5 = 0x20 // Status of Interrupt by MOb
	CANSIT1_SIT6 = 0x40 // Status of Interrupt by MOb

	// CANBT1: Bit Timing Register 1
	CANBT1_BRP0 = 0x2  // Baud Rate Prescaler bits
	CANBT1_BRP1 = 0x4  // Baud Rate Prescaler bits
	CANBT1_BRP2 = 0x8  // Baud Rate Prescaler bits
	CANBT1_BRP3 = 0x10 // Baud Rate Prescaler bits
	CANBT1_BRP4 = 0x20 // Baud Rate Prescaler bits
	CANBT1_BRP5 = 0x40 // Baud Rate Prescaler bits

	// CANBT2: Bit Timing Register 2
	CANBT2_SJW0 = 0x20 // Re-Sync Jump Width
	CANBT2_SJW1 = 0x40 // Re-Sync Jump Width
	CANBT2_PRS0 = 0x2  // Propagation Time Segment
	CANBT2_PRS1 = 0x4  // Propagation Time Segment
	CANBT2_PRS2 = 0x8  // Propagation Time Segment

	// CANBT3: Bit Timing Register 3
	CANBT3_PHS20 = 0x10 // Phase Segments
	CANBT3_PHS21 = 0x20 // Phase Segments
	CANBT3_PHS22 = 0x40 // Phase Segments
	CANBT3_PHS10 = 0x2  // Phase Segment 1
	CANBT3_PHS11 = 0x4  // Phase Segment 1
	CANBT3_PHS12 = 0x8  // Phase Segment 1
	CANBT3_SMP   = 0x1  // Sample Type

	// CANTCON: Timer Control Register
	CANTCON_TPRSC0 = 0x1  // CAN Timer Prescaler
	CANTCON_TPRSC1 = 0x2  // CAN Timer Prescaler
	CANTCON_TPRSC2 = 0x4  // CAN Timer Prescaler
	CANTCON_TPRSC3 = 0x8  // CAN Timer Prescaler
	CANTCON_TPRSC4 = 0x10 // CAN Timer Prescaler
	CANTCON_TPRSC5 = 0x20 // CAN Timer Prescaler
	CANTCON_TPRSC6 = 0x40 // CAN Timer Prescaler
	CANTCON_TPRSC7 = 0x80 // CAN Timer Prescaler

	// CANTIML: Timer Register

	// CANTIMH: Timer Register
	CANTIM_CANTIM0 = 0x1  // CAN Timer Count
	CANTIM_CANTIM1 = 0x2  // CAN Timer Count
	CANTIM_CANTIM2 = 0x4  // CAN Timer Count
	CANTIM_CANTIM3 = 0x8  // CAN Timer Count
	CANTIM_CANTIM4 = 0x10 // CAN Timer Count
	CANTIM_CANTIM5 = 0x20 // CAN Timer Count
	CANTIM_CANTIM6 = 0x40 // CAN Timer Count
	CANTIM_CANTIM7 = 0x80 // CAN Timer Count

	// CANTTCL: TTC Timer Register

	// CANTTCH: TTC Timer Register
	CANTTC_TIMTTC0 = 0x1  // TTC Timer Count
	CANTTC_TIMTTC1 = 0x2  // TTC Timer Count
	CANTTC_TIMTTC2 = 0x4  // TTC Timer Count
	CANTTC_TIMTTC3 = 0x8  // TTC Timer Count
	CANTTC_TIMTTC4 = 0x10 // TTC Timer Count
	CANTTC_TIMTTC5 = 0x20 // TTC Timer Count
	CANTTC_TIMTTC6 = 0x40 // TTC Timer Count
	CANTTC_TIMTTC7 = 0x80 // TTC Timer Count

	// CANTEC: Transmit Error Counter Register
	CANTEC_TEC0 = 0x1  // Trasnmit Error Count
	CANTEC_TEC1 = 0x2  // Trasnmit Error Count
	CANTEC_TEC2 = 0x4  // Trasnmit Error Count
	CANTEC_TEC3 = 0x8  // Trasnmit Error Count
	CANTEC_TEC4 = 0x10 // Trasnmit Error Count
	CANTEC_TEC5 = 0x20 // Trasnmit Error Count
	CANTEC_TEC6 = 0x40 // Trasnmit Error Count
	CANTEC_TEC7 = 0x80 // Trasnmit Error Count

	// CANREC: Receive Error Counter Register
	CANREC_REC0 = 0x1  // Receive Error Count
	CANREC_REC1 = 0x2  // Receive Error Count
	CANREC_REC2 = 0x4  // Receive Error Count
	CANREC_REC3 = 0x8  // Receive Error Count
	CANREC_REC4 = 0x10 // Receive Error Count
	CANREC_REC5 = 0x20 // Receive Error Count
	CANREC_REC6 = 0x40 // Receive Error Count
	CANREC_REC7 = 0x80 // Receive Error Count

	// CANHPMOB: Highest Priority MOb Register
	CANHPMOB_HPMOB0 = 0x10 // Highest Priority MOb number
	CANHPMOB_HPMOB1 = 0x20 // Highest Priority MOb number
	CANHPMOB_HPMOB2 = 0x40 // Highest Priority MOb number
	CANHPMOB_HPMOB3 = 0x80 // Highest Priority MOb number
	CANHPMOB_CGP0   = 0x1  // CAN General purpose bits
	CANHPMOB_CGP1   = 0x2  // CAN General purpose bits
	CANHPMOB_CGP2   = 0x4  // CAN General purpose bits
	CANHPMOB_CGP3   = 0x8  // CAN General purpose bits

	// CANPAGE: Page MOb Register
	CANPAGE_MOBNB0 = 0x10 // MOb Number Bits
	CANPAGE_MOBNB1 = 0x20 // MOb Number Bits
	CANPAGE_MOBNB2 = 0x40 // MOb Number Bits
	CANPAGE_MOBNB3 = 0x80 // MOb Number Bits
	CANPAGE_AINC   = 0x8  // MOb Data Buffer Auto Increment
	CANPAGE_INDX0  = 0x1  // Data Buffer Index Bits
	CANPAGE_INDX1  = 0x2  // Data Buffer Index Bits
	CANPAGE_INDX2  = 0x4  // Data Buffer Index Bits

	// CANSTMOB: MOb Status Register
	CANSTMOB_DLCW = 0x80 // Data Length Code Warning
	CANSTMOB_TXOK = 0x40 // Transmit OK
	CANSTMOB_RXOK = 0x20 // Receive OK
	CANSTMOB_BERR = 0x10 // Bit Error
	CANSTMOB_SERR = 0x8  // Stuff Error
	CANSTMOB_CERR = 0x4  // CRC Error
	CANSTMOB_FERR = 0x2  // Form Error
	CANSTMOB_AERR = 0x1  // Ackknowledgement Error

	// CANCDMOB: MOb Control and DLC Register
	CANCDMOB_CONMOB0 = 0x40 // MOb Config Bits
	CANCDMOB_CONMOB1 = 0x80 // MOb Config Bits
	CANCDMOB_RPLV    = 0x20 // Reply Valid
	CANCDMOB_IDE     = 0x10 // Identifier Extension
	CANCDMOB_DLC0    = 0x1  // Data Length Code Bits
	CANCDMOB_DLC1    = 0x2  // Data Length Code Bits
	CANCDMOB_DLC2    = 0x4  // Data Length Code Bits
	CANCDMOB_DLC3    = 0x8  // Data Length Code Bits

	// CANIDT4: Identifier Tag Register 4
	CANIDT4_IDT0   = 0x8  // Identifier Tag
	CANIDT4_IDT1   = 0x10 // Identifier Tag
	CANIDT4_IDT2   = 0x20 // Identifier Tag
	CANIDT4_IDT3   = 0x40 // Identifier Tag
	CANIDT4_IDT4   = 0x80 // Identifier Tag
	CANIDT4_RTRTAG = 0x4  // Remote Trasnmission Request Tag
	CANIDT4_RB1TAG = 0x2  // Reserved Bit 1 Tag
	CANIDT4_RB0TAG = 0x1  // Reserved Bit 0 Tag

	// CANIDT3: Identifier Tag Register 3
	CANIDT3_IDT0 = 0x1  // Identifier Tag
	CANIDT3_IDT1 = 0x2  // Identifier Tag
	CANIDT3_IDT2 = 0x4  // Identifier Tag
	CANIDT3_IDT3 = 0x8  // Identifier Tag
	CANIDT3_IDT4 = 0x10 // Identifier Tag
	CANIDT3_IDT5 = 0x20 // Identifier Tag
	CANIDT3_IDT6 = 0x40 // Identifier Tag
	CANIDT3_IDT7 = 0x80 // Identifier Tag

	// CANIDT2: Identifier Tag Register 2
	CANIDT2_IDT0 = 0x1  // Identifier Tag
	CANIDT2_IDT1 = 0x2  // Identifier Tag
	CANIDT2_IDT2 = 0x4  // Identifier Tag
	CANIDT2_IDT3 = 0x8  // Identifier Tag
	CANIDT2_IDT4 = 0x10 // Identifier Tag
	CANIDT2_IDT5 = 0x20 // Identifier Tag
	CANIDT2_IDT6 = 0x40 // Identifier Tag
	CANIDT2_IDT7 = 0x80 // Identifier Tag

	// CANIDT1: Identifier Tag Register 1
	CANIDT1_IDT0 = 0x1  // Identifier Tag
	CANIDT1_IDT1 = 0x2  // Identifier Tag
	CANIDT1_IDT2 = 0x4  // Identifier Tag
	CANIDT1_IDT3 = 0x8  // Identifier Tag
	CANIDT1_IDT4 = 0x10 // Identifier Tag
	CANIDT1_IDT5 = 0x20 // Identifier Tag
	CANIDT1_IDT6 = 0x40 // Identifier Tag
	CANIDT1_IDT7 = 0x80 // Identifier Tag

	// CANIDM4: Identifier Mask Register 4
	CANIDM4_IDMSK0 = 0x8  // Identifier Mask
	CANIDM4_IDMSK1 = 0x10 // Identifier Mask
	CANIDM4_IDMSK2 = 0x20 // Identifier Mask
	CANIDM4_IDMSK3 = 0x40 // Identifier Mask
	CANIDM4_IDMSK4 = 0x80 // Identifier Mask
	CANIDM4_RTRMSK = 0x4  // Remote Transmission Request Mask
	CANIDM4_IDEMSK = 0x1  // Identifier Extension Mask

	// CANIDM3: Identifier Mask Register 3
	CANIDM3_IDMSK0 = 0x1  // Identifier Mask
	CANIDM3_IDMSK1 = 0x2  // Identifier Mask
	CANIDM3_IDMSK2 = 0x4  // Identifier Mask
	CANIDM3_IDMSK3 = 0x8  // Identifier Mask
	CANIDM3_IDMSK4 = 0x10 // Identifier Mask
	CANIDM3_IDMSK5 = 0x20 // Identifier Mask
	CANIDM3_IDMSK6 = 0x40 // Identifier Mask
	CANIDM3_IDMSK7 = 0x80 // Identifier Mask

	// CANIDM2: Identifier Mask Register 2
	CANIDM2_IDMSK0 = 0x1  // Identifier Mask
	CANIDM2_IDMSK1 = 0x2  // Identifier Mask
	CANIDM2_IDMSK2 = 0x4  // Identifier Mask
	CANIDM2_IDMSK3 = 0x8  // Identifier Mask
	CANIDM2_IDMSK4 = 0x10 // Identifier Mask
	CANIDM2_IDMSK5 = 0x20 // Identifier Mask
	CANIDM2_IDMSK6 = 0x40 // Identifier Mask
	CANIDM2_IDMSK7 = 0x80 // Identifier Mask

	// CANIDM1: Identifier Mask Register 1
	CANIDM1_IDMSK0 = 0x1  // Identifier Mask
	CANIDM1_IDMSK1 = 0x2  // Identifier Mask
	CANIDM1_IDMSK2 = 0x4  // Identifier Mask
	CANIDM1_IDMSK3 = 0x8  // Identifier Mask
	CANIDM1_IDMSK4 = 0x10 // Identifier Mask
	CANIDM1_IDMSK5 = 0x20 // Identifier Mask
	CANIDM1_IDMSK6 = 0x40 // Identifier Mask
	CANIDM1_IDMSK7 = 0x80 // Identifier Mask

	// CANSTML: Time Stamp Register

	// CANSTMH: Time Stamp Register
	CANSTM_TIMSTM0 = 0x1  // Time Stamp Count
	CANSTM_TIMSTM1 = 0x2  // Time Stamp Count
	CANSTM_TIMSTM2 = 0x4  // Time Stamp Count
	CANSTM_TIMSTM3 = 0x8  // Time Stamp Count
	CANSTM_TIMSTM4 = 0x10 // Time Stamp Count
	CANSTM_TIMSTM5 = 0x20 // Time Stamp Count
	CANSTM_TIMSTM6 = 0x40 // Time Stamp Count
	CANSTM_TIMSTM7 = 0x80 // Time Stamp Count

	// CANMSG: Message Data Register
	CANMSG_MSG0 = 0x1  // Message Data
	CANMSG_MSG1 = 0x2  // Message Data
	CANMSG_MSG2 = 0x4  // Message Data
	CANMSG_MSG3 = 0x8  // Message Data
	CANMSG_MSG4 = 0x10 // Message Data
	CANMSG_MSG5 = 0x20 // Message Data
	CANMSG_MSG6 = 0x40 // Message Data
	CANMSG_MSG7 = 0x80 // Message Data
)
