// Automatically generated file. DO NOT EDIT.
// Generated by gen-device-svd.go from STM32G473xx.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/STMicro

// +build stm32,stm32g473xx

// STM32G473xx
//

package stm32

import (
	"runtime/interrupt"
	"runtime/volatile"
	"unsafe"
)

// Some information about this device.
const (
	DEVICE = "STM32G473xx"
)

// Interrupt numbers.
const (
	IRQ_WWDG             = 0   //
	IRQ_PVD_PVM          = 1   // External interrupt/event controller
	IRQ_RTC_TAMP_CSS_LSE = 2   // Real-time clock
	IRQ_RTC_WKUP         = 3   // Real-time clock
	IRQ_FLASH            = 4   // Flash
	IRQ_RCC              = 5   // Reset and clock control
	IRQ_EXTI0            = 6   // External interrupt/event controller
	IRQ_EXTI1            = 7   // External interrupt/event controller
	IRQ_EXTI2            = 8   // External interrupt/event controller
	IRQ_EXTI3            = 9   // External interrupt/event controller
	IRQ_EXTI4            = 10  // External interrupt/event controller
	IRQ_DMA1_CH1         = 11  // DMA controller
	IRQ_DMA1_CH2         = 12  // DMA controller
	IRQ_DMA1_CH3         = 13  // DMA controller
	IRQ_DMA1_CH4         = 14  // DMA controller
	IRQ_DMA1_CH5         = 15  // DMA controller
	IRQ_DMA1_CH6         = 16  // DMA controller
	IRQ_DMA1_CH7         = 17  //
	IRQ_ADC1_2           = 18  // Analog-to-Digital Converter
	IRQ_USB_HP           = 19  // External interrupt/event controller
	IRQ_USB_LP           = 20  // External interrupt/event controller
	IRQ_fdcan1_intr1_it  = 21  // External interrupt/event controller
	IRQ_fdcan1_intr0_it  = 22  // External interrupt/event controller
	IRQ_EXTI9_5          = 23  // External interrupt/event controller
	IRQ_TIM1_BRK_TIM15   = 24  // Advanced-timers
	IRQ_TIM1_UP_TIM16    = 25  // Advanced-timers
	IRQ_TIM1_TRG_COM     = 26  // Advanced-timers
	IRQ_TIM1_CC          = 27  // Advanced-timers
	IRQ_TIM2             = 28  // Advanced-timers
	IRQ_TIM3             = 29  //
	IRQ_TIM4             = 30  //
	IRQ_I2C1_EV          = 31  // Inter-integrated circuit
	IRQ_I2C1_ER          = 32  // Inter-integrated circuit
	IRQ_I2C2_EV          = 33  //
	IRQ_I2C2_ER          = 34  //
	IRQ_SPI1             = 35  // Serial peripheral interface/Inter-IC sound
	IRQ_SPI2             = 36  //
	IRQ_USART1           = 37  // Universal synchronous asynchronous receiver transmitter
	IRQ_USART2           = 38  //
	IRQ_USART3           = 39  //
	IRQ_EXTI15_10        = 40  // External interrupt/event controller
	IRQ_RTC_ALARM        = 41  // Real-time clock
	IRQ_USBWakeUP        = 42  // External interrupt/event controller
	IRQ_TIM8_BRK         = 43  //
	IRQ_TIM8_UP          = 44  //
	IRQ_TIM8_TRG_COM     = 45  //
	IRQ_TIM8_CC          = 46  // Advanced-timers
	IRQ_ADC3             = 47  // Analog-to-Digital Converter
	IRQ_FMC              = 48  // Flexible memory controller
	IRQ_LPTIM1           = 49  // Universal synchronous asynchronous receiver transmitter
	IRQ_TIM5             = 50  //
	IRQ_SPI3             = 51  //
	IRQ_UART4            = 52  // Universal synchronous asynchronous receiver transmitter
	IRQ_UART5            = 53  //
	IRQ_TIM6_DACUNDER    = 54  // Basic-timers
	IRQ_TIM7             = 55  //
	IRQ_DMA2_CH1         = 56  //
	IRQ_DMA2_CH2         = 57  //
	IRQ_DMA2_CH3         = 58  //
	IRQ_DMA2_CH4         = 59  //
	IRQ_DMA2_CH5         = 60  //
	IRQ_ADC4             = 61  //
	IRQ_ADC5             = 62  //
	IRQ_UCPD1            = 63  // UCPD1
	IRQ_COMP1_2_3        = 64  // Comparator control and status register
	IRQ_COMP4_5_6        = 65  // Comparator control and status register
	IRQ_COMP7            = 66  // Comparator control and status register
	IRQ_CRS              = 75  // External interrupt/event controller
	IRQ_SAI              = 76  // Serial audio interface
	IRQ_TIM20_BRK        = 77  //
	IRQ_TIM20_UP         = 78  //
	IRQ_TIM20_TRG_COM    = 79  //
	IRQ_TIM20_CC         = 80  //
	IRQ_FPU              = 81  // Floting point unit
	IRQ_I2C4_EV          = 82  //
	IRQ_I2C4_ER          = 83  //
	IRQ_SPI4             = 84  // Serial peripheral interface/Inter-IC sound
	IRQ_AES              = 85  // Advanced encryption standard hardware accelerator
	IRQ_FDCAN2_intr0     = 86  // FDCAN //
	IRQ_FDCAN2_intr1     = 87  // FDCAN //
	IRQ_FDCAN3_intr0     = 88  // FDCAN //
	IRQ_FDCAN3_intr1     = 89  // FDCAN //
	IRQ_RNG              = 90  // Random number generator
	IRQ_LPUART           = 91  // Universal synchronous asynchronous receiver transmitter
	IRQ_I2C3_EV          = 92  //
	IRQ_I2C3_ER          = 93  //
	IRQ_DMAMUX_OVR       = 94  // DMAMUX
	IRQ_QUADSPI          = 95  // QuadSPI interface
	IRQ_DMA1_CH8         = 96  // DMA controller
	IRQ_DMA2_CH6         = 97  //
	IRQ_DMA2_CH7         = 98  //
	IRQ_DMA2_CH8         = 99  //
	IRQ_Cordic           = 100 // CORDIC Co-processor
	IRQ_FMAC             = 101 // Filter Math Accelerator
	IRQ_max              = 101 // Highest interrupt number on this device.
)

// Map interrupt numbers to function names.
// These aren't real calls, they're removed by the compiler.
var (
	_ = interrupt.Register(IRQ_WWDG, "WWDG_IRQHandler")
	_ = interrupt.Register(IRQ_PVD_PVM, "PVD_PVM_IRQHandler")
	_ = interrupt.Register(IRQ_RTC_TAMP_CSS_LSE, "RTC_TAMP_CSS_LSE_IRQHandler")
	_ = interrupt.Register(IRQ_RTC_WKUP, "RTC_WKUP_IRQHandler")
	_ = interrupt.Register(IRQ_FLASH, "FLASH_IRQHandler")
	_ = interrupt.Register(IRQ_RCC, "RCC_IRQHandler")
	_ = interrupt.Register(IRQ_EXTI0, "EXTI0_IRQHandler")
	_ = interrupt.Register(IRQ_EXTI1, "EXTI1_IRQHandler")
	_ = interrupt.Register(IRQ_EXTI2, "EXTI2_IRQHandler")
	_ = interrupt.Register(IRQ_EXTI3, "EXTI3_IRQHandler")
	_ = interrupt.Register(IRQ_EXTI4, "EXTI4_IRQHandler")
	_ = interrupt.Register(IRQ_DMA1_CH1, "DMA1_CH1_IRQHandler")
	_ = interrupt.Register(IRQ_DMA1_CH2, "DMA1_CH2_IRQHandler")
	_ = interrupt.Register(IRQ_DMA1_CH3, "DMA1_CH3_IRQHandler")
	_ = interrupt.Register(IRQ_DMA1_CH4, "DMA1_CH4_IRQHandler")
	_ = interrupt.Register(IRQ_DMA1_CH5, "DMA1_CH5_IRQHandler")
	_ = interrupt.Register(IRQ_DMA1_CH6, "DMA1_CH6_IRQHandler")
	_ = interrupt.Register(IRQ_DMA1_CH7, "DMA1_CH7_IRQHandler")
	_ = interrupt.Register(IRQ_ADC1_2, "ADC1_2_IRQHandler")
	_ = interrupt.Register(IRQ_USB_HP, "USB_HP_IRQHandler")
	_ = interrupt.Register(IRQ_USB_LP, "USB_LP_IRQHandler")
	_ = interrupt.Register(IRQ_fdcan1_intr1_it, "fdcan1_intr1_it_IRQHandler")
	_ = interrupt.Register(IRQ_fdcan1_intr0_it, "fdcan1_intr0_it_IRQHandler")
	_ = interrupt.Register(IRQ_EXTI9_5, "EXTI9_5_IRQHandler")
	_ = interrupt.Register(IRQ_TIM1_BRK_TIM15, "TIM1_BRK_TIM15_IRQHandler")
	_ = interrupt.Register(IRQ_TIM1_UP_TIM16, "TIM1_UP_TIM16_IRQHandler")
	_ = interrupt.Register(IRQ_TIM1_TRG_COM, "TIM1_TRG_COM_IRQHandler")
	_ = interrupt.Register(IRQ_TIM1_CC, "TIM1_CC_IRQHandler")
	_ = interrupt.Register(IRQ_TIM2, "TIM2_IRQHandler")
	_ = interrupt.Register(IRQ_TIM3, "TIM3_IRQHandler")
	_ = interrupt.Register(IRQ_TIM4, "TIM4_IRQHandler")
	_ = interrupt.Register(IRQ_I2C1_EV, "I2C1_EV_IRQHandler")
	_ = interrupt.Register(IRQ_I2C1_ER, "I2C1_ER_IRQHandler")
	_ = interrupt.Register(IRQ_I2C2_EV, "I2C2_EV_IRQHandler")
	_ = interrupt.Register(IRQ_I2C2_ER, "I2C2_ER_IRQHandler")
	_ = interrupt.Register(IRQ_SPI1, "SPI1_IRQHandler")
	_ = interrupt.Register(IRQ_SPI2, "SPI2_IRQHandler")
	_ = interrupt.Register(IRQ_USART1, "USART1_IRQHandler")
	_ = interrupt.Register(IRQ_USART2, "USART2_IRQHandler")
	_ = interrupt.Register(IRQ_USART3, "USART3_IRQHandler")
	_ = interrupt.Register(IRQ_EXTI15_10, "EXTI15_10_IRQHandler")
	_ = interrupt.Register(IRQ_RTC_ALARM, "RTC_ALARM_IRQHandler")
	_ = interrupt.Register(IRQ_USBWakeUP, "USBWakeUP_IRQHandler")
	_ = interrupt.Register(IRQ_TIM8_BRK, "TIM8_BRK_IRQHandler")
	_ = interrupt.Register(IRQ_TIM8_UP, "TIM8_UP_IRQHandler")
	_ = interrupt.Register(IRQ_TIM8_TRG_COM, "TIM8_TRG_COM_IRQHandler")
	_ = interrupt.Register(IRQ_TIM8_CC, "TIM8_CC_IRQHandler")
	_ = interrupt.Register(IRQ_ADC3, "ADC3_IRQHandler")
	_ = interrupt.Register(IRQ_FMC, "FMC_IRQHandler")
	_ = interrupt.Register(IRQ_LPTIM1, "LPTIM1_IRQHandler")
	_ = interrupt.Register(IRQ_TIM5, "TIM5_IRQHandler")
	_ = interrupt.Register(IRQ_SPI3, "SPI3_IRQHandler")
	_ = interrupt.Register(IRQ_UART4, "UART4_IRQHandler")
	_ = interrupt.Register(IRQ_UART5, "UART5_IRQHandler")
	_ = interrupt.Register(IRQ_TIM6_DACUNDER, "TIM6_DACUNDER_IRQHandler")
	_ = interrupt.Register(IRQ_TIM7, "TIM7_IRQHandler")
	_ = interrupt.Register(IRQ_DMA2_CH1, "DMA2_CH1_IRQHandler")
	_ = interrupt.Register(IRQ_DMA2_CH2, "DMA2_CH2_IRQHandler")
	_ = interrupt.Register(IRQ_DMA2_CH3, "DMA2_CH3_IRQHandler")
	_ = interrupt.Register(IRQ_DMA2_CH4, "DMA2_CH4_IRQHandler")
	_ = interrupt.Register(IRQ_DMA2_CH5, "DMA2_CH5_IRQHandler")
	_ = interrupt.Register(IRQ_ADC4, "ADC4_IRQHandler")
	_ = interrupt.Register(IRQ_ADC5, "ADC5_IRQHandler")
	_ = interrupt.Register(IRQ_UCPD1, "UCPD1_IRQHandler")
	_ = interrupt.Register(IRQ_COMP1_2_3, "COMP1_2_3_IRQHandler")
	_ = interrupt.Register(IRQ_COMP4_5_6, "COMP4_5_6_IRQHandler")
	_ = interrupt.Register(IRQ_COMP7, "COMP7_IRQHandler")
	_ = interrupt.Register(IRQ_CRS, "CRS_IRQHandler")
	_ = interrupt.Register(IRQ_SAI, "SAI_IRQHandler")
	_ = interrupt.Register(IRQ_TIM20_BRK, "TIM20_BRK_IRQHandler")
	_ = interrupt.Register(IRQ_TIM20_UP, "TIM20_UP_IRQHandler")
	_ = interrupt.Register(IRQ_TIM20_TRG_COM, "TIM20_TRG_COM_IRQHandler")
	_ = interrupt.Register(IRQ_TIM20_CC, "TIM20_CC_IRQHandler")
	_ = interrupt.Register(IRQ_FPU, "FPU_IRQHandler")
	_ = interrupt.Register(IRQ_I2C4_EV, "I2C4_EV_IRQHandler")
	_ = interrupt.Register(IRQ_I2C4_ER, "I2C4_ER_IRQHandler")
	_ = interrupt.Register(IRQ_SPI4, "SPI4_IRQHandler")
	_ = interrupt.Register(IRQ_AES, "AES_IRQHandler")
	_ = interrupt.Register(IRQ_FDCAN2_intr0, "FDCAN2_intr0_IRQHandler")
	_ = interrupt.Register(IRQ_FDCAN2_intr1, "FDCAN2_intr1_IRQHandler")
	_ = interrupt.Register(IRQ_FDCAN3_intr0, "FDCAN3_intr0_IRQHandler")
	_ = interrupt.Register(IRQ_FDCAN3_intr1, "FDCAN3_intr1_IRQHandler")
	_ = interrupt.Register(IRQ_RNG, "RNG_IRQHandler")
	_ = interrupt.Register(IRQ_LPUART, "LPUART_IRQHandler")
	_ = interrupt.Register(IRQ_I2C3_EV, "I2C3_EV_IRQHandler")
	_ = interrupt.Register(IRQ_I2C3_ER, "I2C3_ER_IRQHandler")
	_ = interrupt.Register(IRQ_DMAMUX_OVR, "DMAMUX_OVR_IRQHandler")
	_ = interrupt.Register(IRQ_QUADSPI, "QUADSPI_IRQHandler")
	_ = interrupt.Register(IRQ_DMA1_CH8, "DMA1_CH8_IRQHandler")
	_ = interrupt.Register(IRQ_DMA2_CH6, "DMA2_CH6_IRQHandler")
	_ = interrupt.Register(IRQ_DMA2_CH7, "DMA2_CH7_IRQHandler")
	_ = interrupt.Register(IRQ_DMA2_CH8, "DMA2_CH8_IRQHandler")
	_ = interrupt.Register(IRQ_Cordic, "Cordic_IRQHandler")
	_ = interrupt.Register(IRQ_FMAC, "FMAC_IRQHandler")
)

// Peripherals.
var (
	CRC           = (*CRC_Type)(unsafe.Pointer(uintptr(0x40023000)))     // Cyclic redundancy check calculation unit
	WWDG          = (*IWDG_Type)(unsafe.Pointer(uintptr(0x40002c00)))    // WinWATCHDOG
	IWDG          = (*WWDG_Type)(unsafe.Pointer(uintptr(0x40003000)))    // System window watchdog
	I2C1          = (*I2C_Type)(unsafe.Pointer(uintptr(0x40005400)))     // Inter-integrated circuit
	FLASH         = (*Flash_Type)(unsafe.Pointer(uintptr(0x40022000)))   // Flash
	DBGMCU        = (*DBGMCU_Type)(unsafe.Pointer(uintptr(0xe0042000)))  // Debug support
	RCC           = (*RCC_Type)(unsafe.Pointer(uintptr(0x40021000)))     // Reset and clock control
	PWR           = (*PWR_Type)(unsafe.Pointer(uintptr(0x40007000)))     // Power control
	RNG           = (*RNG_Type)(unsafe.Pointer(uintptr(0x50060800)))     // Random number generator
	AES           = (*AES_Type)(unsafe.Pointer(uintptr(0x50060000)))     // Advanced encryption standard hardware accelerator
	GPIOA         = (*GPIO_Type)(unsafe.Pointer(uintptr(0x48000000)))    // General-purpose I/Os
	GPIOB         = (*GPIO_Type)(unsafe.Pointer(uintptr(0x48000400)))    // General-purpose I/Os
	GPIOC         = (*GPIO_Type)(unsafe.Pointer(uintptr(0x48000800)))    // General-purpose I/Os
	TIM15         = (*TIM_Type)(unsafe.Pointer(uintptr(0x40014000)))     // General purpose timers
	TIM16         = (*TIM_Type)(unsafe.Pointer(uintptr(0x40014400)))     // General purpose timers
	TIM1          = (*TIM_Type)(unsafe.Pointer(uintptr(0x40012c00)))     // Advanced-timers
	TIM2          = (*TIM_Type)(unsafe.Pointer(uintptr(0x40000000)))     // Advanced-timers
	TIM6          = (*TIM_Type)(unsafe.Pointer(uintptr(0x40001000)))     // Basic-timers
	LPTIMER1      = (*LPTIM_Type)(unsafe.Pointer(uintptr(0x40007c00)))   // Low power timer
	USART1        = (*USART_Type)(unsafe.Pointer(uintptr(0x40013800)))   // Universal synchronous asynchronous receiver transmitter
	UART4         = (*USART_Type)(unsafe.Pointer(uintptr(0x40004c00)))   // Universal synchronous asynchronous receiver transmitter
	LPUART1       = (*USART_Type)(unsafe.Pointer(uintptr(0x40008000)))   // Universal synchronous asynchronous receiver transmitter
	SPI1          = (*SPI_Type)(unsafe.Pointer(uintptr(0x40013000)))     // Serial peripheral interface/Inter-IC sound
	SPI4          = (*SPI_Type)(unsafe.Pointer(uintptr(0x40013c00)))     // Serial peripheral interface/Inter-IC sound
	EXTI          = (*EXTI_Type)(unsafe.Pointer(uintptr(0x40010400)))    // External interrupt/event controller
	RTC           = (*RTC_Type)(unsafe.Pointer(uintptr(0x40002800)))     // Real-time clock
	FMC           = (*FMC_Type)(unsafe.Pointer(uintptr(0xa0000000)))     // Flexible memory controller
	DMA1          = (*DMA_Type)(unsafe.Pointer(uintptr(0x40020000)))     // DMA controller
	DMAMUX        = (*DMAMUX_Type)(unsafe.Pointer(uintptr(0x40020800)))  // DMAMUX
	SYSCFG        = (*SYSCFG_Type)(unsafe.Pointer(uintptr(0x40010000)))  // System configuration controller
	VREFBUF       = (*VREFBUF_Type)(unsafe.Pointer(uintptr(0x40010030))) // Voltage reference buffer
	COMP          = (*COMP_Type)(unsafe.Pointer(uintptr(0x40010200)))    // Comparator control and status register
	OPAMP         = (*OPAMP_Type)(unsafe.Pointer(uintptr(0x40010300)))   // Operational amplifiers
	QUADSPI       = (*QUADSPI_Type)(unsafe.Pointer(uintptr(0xa0001000))) // QuadSPI interface
	DAC1          = (*DAC_Type)(unsafe.Pointer(uintptr(0x50000800)))     // Digital-to-analog converter
	ADC1          = (*ADC_Type)(unsafe.Pointer(uintptr(0x50000000)))     // Analog-to-Digital Converter
	ADC3          = (*ADC_Type)(unsafe.Pointer(uintptr(0x50000400)))     // Analog-to-Digital Converter
	ADC12_Common  = (*ADC_Type)(unsafe.Pointer(uintptr(0x50000200)))     // Analog-to-Digital Converter
	FMAC          = (*FMAC_Type)(unsafe.Pointer(uintptr(0x40021400)))    // Filter Math Accelerator
	CORDIC        = (*CORDIC_Type)(unsafe.Pointer(uintptr(0x40020c00)))  // CORDIC Co-processor
	SAI           = (*SAI_Type)(unsafe.Pointer(uintptr(0x40015400)))     // Serial audio interface
	TAMP          = (*TAMP_Type)(unsafe.Pointer(uintptr(0x40002400)))    // Tamper and backup registers
	FPU           = (*FPU_Type)(unsafe.Pointer(uintptr(0xe000ef34)))     // Floting point unit
	MPU           = (*MPU_Type)(unsafe.Pointer(uintptr(0xe000e084)))     // Memory protection unit
	STK           = (*STK_Type)(unsafe.Pointer(uintptr(0xe000e010)))     // SysTick timer
	SCB           = (*SCB_Type)(unsafe.Pointer(uintptr(0xe000e040)))     // System control block
	NVIC          = (*NVIC_Type)(unsafe.Pointer(uintptr(0xe000e100)))    // Nested Vectored Interrupt Controller
	FPU_CPACR     = (*FPU_Type)(unsafe.Pointer(uintptr(0xe000ef08)))     // Floating point unit CPACR
	SCB_ACTRL     = (*SCB_Type)(unsafe.Pointer(uintptr(0xe000e008)))     // System control block ACTLR
	FDCAN         = (*FDCAN_Type)(unsafe.Pointer(uintptr(0x4000a400)))   // FDCAN
	FDCAN1        = (*FDCAN_Type)(unsafe.Pointer(uintptr(0x40006400)))   // FDCAN
	FDCAN2        = (*FDCAN_Type)(unsafe.Pointer(uintptr(0x40006800)))   // FDCAN
	FDCAN3        = (*FDCAN_Type)(unsafe.Pointer(uintptr(0x40006c00)))   // FDCAN
	UCPD1         = (*UCPD_Type)(unsafe.Pointer(uintptr(0x4000a000)))    // UCPD1
	USB_FS_device = (*USB_Type)(unsafe.Pointer(uintptr(0x40005c00)))     // USB_FS_device
	CRS           = (*CRS_Type)(unsafe.Pointer(uintptr(0x40002000)))     // CRS
	I2C2          = (*I2C_Type)(unsafe.Pointer(uintptr(0x40005800)))     // Inter-integrated circuit
	I2C3          = (*I2C_Type)(unsafe.Pointer(uintptr(0x40007800)))     // Inter-integrated circuit
	I2C4          = (*I2C_Type)(unsafe.Pointer(uintptr(0x40008400)))     // Inter-integrated circuit
	GPIOD         = (*GPIO_Type)(unsafe.Pointer(uintptr(0x48000c00)))    // General-purpose I/Os
	GPIOE         = (*GPIO_Type)(unsafe.Pointer(uintptr(0x48001000)))    // General-purpose I/Os
	GPIOF         = (*GPIO_Type)(unsafe.Pointer(uintptr(0x48001400)))    // General-purpose I/Os
	GPIOG         = (*GPIO_Type)(unsafe.Pointer(uintptr(0x48001800)))    // General-purpose I/Os
	TIM17         = (*TIM_Type)(unsafe.Pointer(uintptr(0x40014800)))     // General purpose timers
	TIM20         = (*TIM_Type)(unsafe.Pointer(uintptr(0x40015000)))     // Advanced-timers
	TIM8          = (*TIM_Type)(unsafe.Pointer(uintptr(0x40013400)))     // Advanced-timers
	TIM3          = (*TIM_Type)(unsafe.Pointer(uintptr(0x40000400)))     // Advanced-timers
	TIM4          = (*TIM_Type)(unsafe.Pointer(uintptr(0x40000800)))     // Advanced-timers
	TIM5          = (*TIM_Type)(unsafe.Pointer(uintptr(0x40000c00)))     // Advanced-timers
	TIM7          = (*TIM_Type)(unsafe.Pointer(uintptr(0x40001400)))     // Basic-timers
	USART2        = (*USART_Type)(unsafe.Pointer(uintptr(0x40004400)))   // Universal synchronous asynchronous receiver transmitter
	USART3        = (*USART_Type)(unsafe.Pointer(uintptr(0x40004800)))   // Universal synchronous asynchronous receiver transmitter
	UART5         = (*USART_Type)(unsafe.Pointer(uintptr(0x40005000)))   // Universal synchronous asynchronous receiver transmitter
	SPI3          = (*SPI_Type)(unsafe.Pointer(uintptr(0x40003c00)))     // Serial peripheral interface/Inter-IC sound
	SPI2          = (*SPI_Type)(unsafe.Pointer(uintptr(0x40003800)))     // Serial peripheral interface/Inter-IC sound
	DMA2          = (*DMA_Type)(unsafe.Pointer(uintptr(0x40020400)))     // DMA controller
	DAC2          = (*DAC_Type)(unsafe.Pointer(uintptr(0x50000c00)))     // Digital-to-analog converter
	DAC3          = (*DAC_Type)(unsafe.Pointer(uintptr(0x50001000)))     // Digital-to-analog converter
	DAC4          = (*DAC_Type)(unsafe.Pointer(uintptr(0x50001400)))     // Digital-to-analog converter
	ADC2          = (*ADC_Type)(unsafe.Pointer(uintptr(0x50000100)))     // Analog-to-Digital Converter
	ADC4          = (*ADC_Type)(unsafe.Pointer(uintptr(0x50000500)))     // Analog-to-Digital Converter
	ADC5          = (*ADC_Type)(unsafe.Pointer(uintptr(0x50000600)))     // Analog-to-Digital Converter
	ADC345_Common = (*ADC_Type)(unsafe.Pointer(uintptr(0x50000700)))     // Analog-to-Digital Converter
)

// Cyclic redundancy check calculation unit
type CRC_Type struct {
	DR   volatile.Register32 // 0x0
	IDR  volatile.Register32 // 0x4
	CR   volatile.Register32 // 0x8
	_    [4]byte
	INIT volatile.Register32 // 0x10
	POL  volatile.Register32 // 0x14
}

// WinWATCHDOG
type IWDG_Type struct {
	KR   volatile.Register32 // 0x0
	PR   volatile.Register32 // 0x4
	RLR  volatile.Register32 // 0x8
	SR   volatile.Register32 // 0xC
	WINR volatile.Register32 // 0x10
}

// System window watchdog
type WWDG_Type struct {
	CR  volatile.Register32 // 0x0
	CFR volatile.Register32 // 0x4
	SR  volatile.Register32 // 0x8
}

// Inter-integrated circuit
type I2C_Type struct {
	CR1      volatile.Register32 // 0x0
	CR2      volatile.Register32 // 0x4
	OAR1     volatile.Register32 // 0x8
	OAR2     volatile.Register32 // 0xC
	TIMINGR  volatile.Register32 // 0x10
	TIMEOUTR volatile.Register32 // 0x14
	ISR      volatile.Register32 // 0x18
	ICR      volatile.Register32 // 0x1C
	PECR     volatile.Register32 // 0x20
	RXDR     volatile.Register32 // 0x24
	TXDR     volatile.Register32 // 0x28
}

// Flash
type Flash_Type struct {
	ACR      volatile.Register32 // 0x0
	PDKEYR   volatile.Register32 // 0x4
	KEYR     volatile.Register32 // 0x8
	OPTKEYR  volatile.Register32 // 0xC
	SR       volatile.Register32 // 0x10
	CR       volatile.Register32 // 0x14
	ECCR     volatile.Register32 // 0x18
	_        [4]byte
	OPTR     volatile.Register32 // 0x20
	PCROP1SR volatile.Register32 // 0x24
	PCROP1ER volatile.Register32 // 0x28
	WRP1AR   volatile.Register32 // 0x2C
	WRP1BR   volatile.Register32 // 0x30
	_        [60]byte
	SEC1R    volatile.Register32 // 0x70
}

// Debug support
type DBGMCU_Type struct {
	IDCODE   volatile.Register32 // 0x0
	CR       volatile.Register32 // 0x4
	APB1L_FZ volatile.Register32 // 0x8
	APB1H_FZ volatile.Register32 // 0xC
	APB2_FZ  volatile.Register32 // 0x10
}

// Reset and clock control
type RCC_Type struct {
	CR         volatile.Register32 // 0x0
	ICSCR      volatile.Register32 // 0x4
	CFGR       volatile.Register32 // 0x8
	PLLSYSCFGR volatile.Register32 // 0xC
	_          [8]byte
	CIER       volatile.Register32 // 0x18
	CIFR       volatile.Register32 // 0x1C
	CICR       volatile.Register32 // 0x20
	_          [4]byte
	AHB1RSTR   volatile.Register32 // 0x28
	AHB2RSTR   volatile.Register32 // 0x2C
	AHB3RSTR   volatile.Register32 // 0x30
	_          [4]byte
	APB1RSTR1  volatile.Register32 // 0x38
	APB1RSTR2  volatile.Register32 // 0x3C
	APB2RSTR   volatile.Register32 // 0x40
	_          [4]byte
	AHB1ENR    volatile.Register32 // 0x48
	AHB2ENR    volatile.Register32 // 0x4C
	AHB3ENR    volatile.Register32 // 0x50
	_          [4]byte
	APB1ENR1   volatile.Register32 // 0x58
	APB1ENR2   volatile.Register32 // 0x5C
	APB2ENR    volatile.Register32 // 0x60
	_          [4]byte
	AHB1SMENR  volatile.Register32 // 0x68
	AHB2SMENR  volatile.Register32 // 0x6C
	AHB3SMENR  volatile.Register32 // 0x70
	_          [4]byte
	APB1SMENR1 volatile.Register32 // 0x78
	APB1SMENR2 volatile.Register32 // 0x7C
	APB2SMENR  volatile.Register32 // 0x80
	_          [4]byte
	CCIPR1     volatile.Register32 // 0x88
	_          [4]byte
	BDCR       volatile.Register32 // 0x90
	CSR        volatile.Register32 // 0x94
	CRRCR      volatile.Register32 // 0x98
	CCIPR2     volatile.Register32 // 0x9C
}

// Power control
type PWR_Type struct {
	CR1   volatile.Register32 // 0x0
	CR2   volatile.Register32 // 0x4
	CR3   volatile.Register32 // 0x8
	CR4   volatile.Register32 // 0xC
	SR1   volatile.Register32 // 0x10
	SR2   volatile.Register32 // 0x14
	SCR   volatile.Register32 // 0x18
	_     [4]byte
	PUCRA volatile.Register32 // 0x20
	PDCRA volatile.Register32 // 0x24
	PUCRB volatile.Register32 // 0x28
	PDCRB volatile.Register32 // 0x2C
	PUCRC volatile.Register32 // 0x30
	PDCRC volatile.Register32 // 0x34
	PUCRD volatile.Register32 // 0x38
	PDCRD volatile.Register32 // 0x3C
	PUCRE volatile.Register32 // 0x40
	PDCRE volatile.Register32 // 0x44
	PUCRF volatile.Register32 // 0x48
	PDCRF volatile.Register32 // 0x4C
	PUCRG volatile.Register32 // 0x50
	PDCRG volatile.Register32 // 0x54
	_     [40]byte
	CR5   volatile.Register32 // 0x80
}

// Random number generator
type RNG_Type struct {
	CR volatile.Register32 // 0x0
	SR volatile.Register32 // 0x4
	DR volatile.Register32 // 0x8
}

// Advanced encryption standard hardware accelerator
type AES_Type struct {
	CR     volatile.Register32 // 0x0
	SR     volatile.Register32 // 0x4
	DINR   volatile.Register32 // 0x8
	DOUTR  volatile.Register32 // 0xC
	KEYR0  volatile.Register32 // 0x10
	KEYR1  volatile.Register32 // 0x14
	KEYR2  volatile.Register32 // 0x18
	KEYR3  volatile.Register32 // 0x1C
	IVR0   volatile.Register32 // 0x20
	IVR1   volatile.Register32 // 0x24
	IVR2   volatile.Register32 // 0x28
	IVR3   volatile.Register32 // 0x2C
	KEYR4  volatile.Register32 // 0x30
	KEYR5  volatile.Register32 // 0x34
	KEYR6  volatile.Register32 // 0x38
	KEYR7  volatile.Register32 // 0x3C
	SUSP0R volatile.Register32 // 0x40
	SUSP1R volatile.Register32 // 0x44
	SUSP2R volatile.Register32 // 0x48
	SUSP3R volatile.Register32 // 0x4C
	SUSP4R volatile.Register32 // 0x50
	SUSP5R volatile.Register32 // 0x54
	SUSP6R volatile.Register32 // 0x58
	SUSP7R volatile.Register32 // 0x5C
}

// General-purpose I/Os
type GPIO_Type struct {
	MODER   volatile.Register32 // 0x0
	OTYPER  volatile.Register32 // 0x4
	OSPEEDR volatile.Register32 // 0x8
	PUPDR   volatile.Register32 // 0xC
	IDR     volatile.Register32 // 0x10
	ODR     volatile.Register32 // 0x14
	BSRR    volatile.Register32 // 0x18
	LCKR    volatile.Register32 // 0x1C
	AFRL    volatile.Register32 // 0x20
	AFRH    volatile.Register32 // 0x24
	BRR     volatile.Register32 // 0x28
}

// General purpose timers
type TIM_Type struct {
	CR1          volatile.Register32 // 0x0
	CR2          volatile.Register32 // 0x4
	SMCR         volatile.Register32 // 0x8
	DIER         volatile.Register32 // 0xC
	SR           volatile.Register32 // 0x10
	EGR          volatile.Register32 // 0x14
	CCMR1_Output volatile.Register32 // 0x18
	_            [4]byte
	CCER         volatile.Register32 // 0x20
	CNT          volatile.Register32 // 0x24
	PSC          volatile.Register32 // 0x28
	ARR          volatile.Register32 // 0x2C
	RCR          volatile.Register32 // 0x30
	CCR1         volatile.Register32 // 0x34
	CCR2         volatile.Register32 // 0x38
	_            [8]byte
	BDTR         volatile.Register32 // 0x44
	_            [12]byte
	DTR2         volatile.Register32 // 0x54
	_            [4]byte
	TISEL        volatile.Register32 // 0x5C
	AF1          volatile.Register32 // 0x60
	AF2          volatile.Register32 // 0x64
	_            [884]byte
	DCR          volatile.Register32 // 0x3DC
	DMAR         volatile.Register32 // 0x3E0
}

// Low power timer
type LPTIM_Type struct {
	ISR  volatile.Register32 // 0x0
	ICR  volatile.Register32 // 0x4
	IER  volatile.Register32 // 0x8
	CFGR volatile.Register32 // 0xC
	CR   volatile.Register32 // 0x10
	CMP  volatile.Register32 // 0x14
	ARR  volatile.Register32 // 0x18
	CNT  volatile.Register32 // 0x1C
	OR   volatile.Register32 // 0x20
}

// Universal synchronous asynchronous receiver transmitter
type USART_Type struct {
	CR1   volatile.Register32 // 0x0
	CR2   volatile.Register32 // 0x4
	CR3   volatile.Register32 // 0x8
	BRR   volatile.Register32 // 0xC
	GTPR  volatile.Register32 // 0x10
	RTOR  volatile.Register32 // 0x14
	RQR   volatile.Register32 // 0x18
	ISR   volatile.Register32 // 0x1C
	ICR   volatile.Register32 // 0x20
	RDR   volatile.Register32 // 0x24
	TDR   volatile.Register32 // 0x28
	PRESC volatile.Register32 // 0x2C
}

// Serial peripheral interface/Inter-IC sound
type SPI_Type struct {
	CR1     volatile.Register32 // 0x0
	CR2     volatile.Register32 // 0x4
	SR      volatile.Register32 // 0x8
	DR      volatile.Register32 // 0xC
	CRCPR   volatile.Register32 // 0x10
	RXCRCR  volatile.Register32 // 0x14
	TXCRCR  volatile.Register32 // 0x18
	I2SCFGR volatile.Register32 // 0x1C
	I2SPR   volatile.Register32 // 0x20
}

// External interrupt/event controller
type EXTI_Type struct {
	IMR1   volatile.Register32 // 0x0
	EMR1   volatile.Register32 // 0x4
	RTSR1  volatile.Register32 // 0x8
	FTSR1  volatile.Register32 // 0xC
	SWIER1 volatile.Register32 // 0x10
	PR1    volatile.Register32 // 0x14
	_      [8]byte
	IMR2   volatile.Register32 // 0x20
	EMR2   volatile.Register32 // 0x24
	RTSR2  volatile.Register32 // 0x28
	FTSR2  volatile.Register32 // 0x2C
	SWIER2 volatile.Register32 // 0x30
	PR2    volatile.Register32 // 0x34
}

// Real-time clock
type RTC_Type struct {
	TR       volatile.Register32 // 0x0
	DR       volatile.Register32 // 0x4
	SSR      volatile.Register32 // 0x8
	ICSR     volatile.Register32 // 0xC
	PRER     volatile.Register32 // 0x10
	WUTR     volatile.Register32 // 0x14
	CR       volatile.Register32 // 0x18
	_        [8]byte
	WPR      volatile.Register32 // 0x24
	CALR     volatile.Register32 // 0x28
	SHIFTR   volatile.Register32 // 0x2C
	TSTR     volatile.Register32 // 0x30
	TSDR     volatile.Register32 // 0x34
	TSSSR    volatile.Register32 // 0x38
	_        [4]byte
	ALRMAR   volatile.Register32 // 0x40
	ALRMASSR volatile.Register32 // 0x44
	ALRMBR   volatile.Register32 // 0x48
	ALRMBSSR volatile.Register32 // 0x4C
	SR       volatile.Register32 // 0x50
	MISR     volatile.Register32 // 0x54
	_        [4]byte
	SCR      volatile.Register32 // 0x5C
}

// Flexible memory controller
type FMC_Type struct {
	BCR1    volatile.Register32 // 0x0
	BTR1    volatile.Register32 // 0x4
	BCR2    volatile.Register32 // 0x8
	BTR2    volatile.Register32 // 0xC
	BCR3    volatile.Register32 // 0x10
	BTR3    volatile.Register32 // 0x14
	BCR4    volatile.Register32 // 0x18
	BTR4    volatile.Register32 // 0x1C
	PCSCNTR volatile.Register32 // 0x20
	_       [92]byte
	PCR     volatile.Register32 // 0x80
	SR      volatile.Register32 // 0x84
	PMEM    volatile.Register32 // 0x88
	PATT    volatile.Register32 // 0x8C
	_       [4]byte
	ECCR    volatile.Register32 // 0x94
	_       [108]byte
	BWTR1   volatile.Register32 // 0x104
	_       [4]byte
	BWTR2   volatile.Register32 // 0x10C
	_       [4]byte
	BWTR3   volatile.Register32 // 0x114
	_       [4]byte
	BWTR4   volatile.Register32 // 0x11C
}

// DMA controller
type DMA_Type struct {
	ISR    volatile.Register32 // 0x0
	IFCR   volatile.Register32 // 0x4
	CCR1   volatile.Register32 // 0x8
	CNDTR1 volatile.Register32 // 0xC
	CPAR1  volatile.Register32 // 0x10
	CMAR1  volatile.Register32 // 0x14
	_      [4]byte
	CCR2   volatile.Register32 // 0x1C
	CNDTR2 volatile.Register32 // 0x20
	CPAR2  volatile.Register32 // 0x24
	CMAR2  volatile.Register32 // 0x28
	_      [4]byte
	CCR3   volatile.Register32 // 0x30
	CNDTR3 volatile.Register32 // 0x34
	CPAR3  volatile.Register32 // 0x38
	CMAR3  volatile.Register32 // 0x3C
	_      [4]byte
	CCR4   volatile.Register32 // 0x44
	CNDTR4 volatile.Register32 // 0x48
	CPAR4  volatile.Register32 // 0x4C
	CMAR4  volatile.Register32 // 0x50
	_      [4]byte
	CCR5   volatile.Register32 // 0x58
	CNDTR5 volatile.Register32 // 0x5C
	CPAR5  volatile.Register32 // 0x60
	CMAR5  volatile.Register32 // 0x64
	_      [4]byte
	CCR6   volatile.Register32 // 0x6C
	CNDTR6 volatile.Register32 // 0x70
	CPAR6  volatile.Register32 // 0x74
	CMAR6  volatile.Register32 // 0x78
	_      [4]byte
	CCR7   volatile.Register32 // 0x80
	CNDTR7 volatile.Register32 // 0x84
	CPAR7  volatile.Register32 // 0x88
	CMAR7  volatile.Register32 // 0x8C
	_      [4]byte
	CCR8   volatile.Register32 // 0x94
	CNDTR8 volatile.Register32 // 0x98
	CPAR8  volatile.Register32 // 0x9C
	CMAR8  volatile.Register32 // 0xA0
}

// DMAMUX
type DMAMUX_Type struct {
	C0CR  volatile.Register32 // 0x0
	C1CR  volatile.Register32 // 0x4
	C2CR  volatile.Register32 // 0x8
	C3CR  volatile.Register32 // 0xC
	C4CR  volatile.Register32 // 0x10
	C5CR  volatile.Register32 // 0x14
	C6CR  volatile.Register32 // 0x18
	C7CR  volatile.Register32 // 0x1C
	C8CR  volatile.Register32 // 0x20
	C9CR  volatile.Register32 // 0x24
	C10CR volatile.Register32 // 0x28
	C11CR volatile.Register32 // 0x2C
	C12CR volatile.Register32 // 0x30
	C13CR volatile.Register32 // 0x34
	C14CR volatile.Register32 // 0x38
	C15CR volatile.Register32 // 0x3C
	_     [64]byte
	CSR   volatile.Register32 // 0x80
	CFR   volatile.Register32 // 0x84
	_     [120]byte
	RG0CR volatile.Register32 // 0x100
	RG1CR volatile.Register32 // 0x104
	RG2CR volatile.Register32 // 0x108
	RG3CR volatile.Register32 // 0x10C
	_     [48]byte
	RGSR  volatile.Register32 // 0x140
	RGCFR volatile.Register32 // 0x144
}

// System configuration controller
type SYSCFG_Type struct {
	MEMRMP  volatile.Register32 // 0x0
	CFGR1   volatile.Register32 // 0x4
	EXTICR1 volatile.Register32 // 0x8
	EXTICR2 volatile.Register32 // 0xC
	EXTICR3 volatile.Register32 // 0x10
	EXTICR4 volatile.Register32 // 0x14
	SCSR    volatile.Register32 // 0x18
	CFGR2   volatile.Register32 // 0x1C
	SWPR    volatile.Register32 // 0x20
	SKR     volatile.Register32 // 0x24
}

// Voltage reference buffer
type VREFBUF_Type struct {
	VREFBUF_CSR volatile.Register32 // 0x0
	VREFBUF_CCR volatile.Register32 // 0x4
}

// Comparator control and status register
type COMP_Type struct {
	COMP_C1CSR volatile.Register32 // 0x0
	COMP_C2CSR volatile.Register32 // 0x4
	COMP_C3CSR volatile.Register32 // 0x8
	_          [6]byte
	COMP_C4CSR volatile.Register32 // 0x12
	COMP_C5CSR volatile.Register32 // 0x16
	_          [6]byte
	COMP_C6CSR volatile.Register32 // 0x20
	COMP_C7CSR volatile.Register32 // 0x24
}

// Operational amplifiers
type OPAMP_Type struct {
	OPAMP1_CSR  volatile.Register32 // 0x0
	OPAMP2_CSR  volatile.Register32 // 0x4
	OPAMP3_CSR  volatile.Register32 // 0x8
	OPAMP4_CSR  volatile.Register32 // 0xC
	OPAMP5_CSR  volatile.Register32 // 0x10
	OPAMP6_CSR  volatile.Register32 // 0x14
	OPAMP1_TCMR volatile.Register32 // 0x18
	OPAMP2_TCMR volatile.Register32 // 0x1C
	OPAMP3_TCMR volatile.Register32 // 0x20
	OPAMP4_TCMR volatile.Register32 // 0x24
	OPAMP5_TCMR volatile.Register32 // 0x28
	OPAMP6_TCMR volatile.Register32 // 0x2C
}

// QuadSPI interface
type QUADSPI_Type struct {
	CR    volatile.Register32 // 0x0
	DCR   volatile.Register32 // 0x4
	SR    volatile.Register32 // 0x8
	FCR   volatile.Register32 // 0xC
	DLR   volatile.Register32 // 0x10
	CCR   volatile.Register32 // 0x14
	AR    volatile.Register32 // 0x18
	ABR   volatile.Register32 // 0x1C
	DR    volatile.Register32 // 0x20
	PSMKR volatile.Register32 // 0x24
	PSMAR volatile.Register32 // 0x28
	PIR   volatile.Register32 // 0x2C
	LPTR  volatile.Register32 // 0x30
}

// Digital-to-analog converter
type DAC_Type struct {
	DAC_CR      volatile.Register32 // 0x0
	DAC_SWTRGR  volatile.Register32 // 0x4
	DAC_DHR12R1 volatile.Register32 // 0x8
	DAC_DHR12L1 volatile.Register32 // 0xC
	DAC_DHR8R1  volatile.Register32 // 0x10
	DAC_DHR12R2 volatile.Register32 // 0x14
	DAC_DHR12L2 volatile.Register32 // 0x18
	DAC_DHR8R2  volatile.Register32 // 0x1C
	DAC_DHR12RD volatile.Register32 // 0x20
	DAC_DHR12LD volatile.Register32 // 0x24
	DAC_DHR8RD  volatile.Register32 // 0x28
	DAC_DOR1    volatile.Register32 // 0x2C
	DAC_DOR2    volatile.Register32 // 0x30
	DAC_SR      volatile.Register32 // 0x34
	DAC_CCR     volatile.Register32 // 0x38
	DAC_MCR     volatile.Register32 // 0x3C
	DAC_SHSR1   volatile.Register32 // 0x40
	DAC_SHSR2   volatile.Register32 // 0x44
	DAC_SHHR    volatile.Register32 // 0x48
	DAC_SHRR    volatile.Register32 // 0x4C
	_           [8]byte
	DAC_STR1    volatile.Register32 // 0x58
	DAC_STR2    volatile.Register32 // 0x5C
	DAC_STMODR  volatile.Register32 // 0x60
}

// Analog-to-Digital Converter
type ADC_Type struct {
	ISR     volatile.Register32 // 0x0
	IER     volatile.Register32 // 0x4
	CR      volatile.Register32 // 0x8
	CFGR    volatile.Register32 // 0xC
	CFGR2   volatile.Register32 // 0x10
	SMPR1   volatile.Register32 // 0x14
	SMPR2   volatile.Register32 // 0x18
	_       [4]byte
	TR1     volatile.Register32 // 0x20
	TR2     volatile.Register32 // 0x24
	TR3     volatile.Register32 // 0x28
	_       [4]byte
	SQR1    volatile.Register32 // 0x30
	SQR2    volatile.Register32 // 0x34
	SQR3    volatile.Register32 // 0x38
	SQR4    volatile.Register32 // 0x3C
	DR      volatile.Register32 // 0x40
	_       [8]byte
	JSQR    volatile.Register32 // 0x4C
	_       [16]byte
	OFR1    volatile.Register32 // 0x60
	OFR2    volatile.Register32 // 0x64
	OFR3    volatile.Register32 // 0x68
	OFR4    volatile.Register32 // 0x6C
	_       [16]byte
	JDR1    volatile.Register32 // 0x80
	JDR2    volatile.Register32 // 0x84
	JDR3    volatile.Register32 // 0x88
	JDR4    volatile.Register32 // 0x8C
	_       [16]byte
	AWD2CR  volatile.Register32 // 0xA0
	AWD3CR  volatile.Register32 // 0xA4
	_       [8]byte
	DIFSEL  volatile.Register32 // 0xB0
	CALFACT volatile.Register32 // 0xB4
	_       [8]byte
	GCOMP   volatile.Register32 // 0xC0
}

// Filter Math Accelerator
type FMAC_Type struct {
	X1BUFCFG volatile.Register32 // 0x0
	X2BUFCFG volatile.Register32 // 0x4
	YBUFCFG  volatile.Register32 // 0x8
	PARAM    volatile.Register32 // 0xC
	CR       volatile.Register32 // 0x10
	SR       volatile.Register32 // 0x14
	WDATA    volatile.Register32 // 0x18
	RDATA    volatile.Register32 // 0x1C
}

// CORDIC Co-processor
type CORDIC_Type struct {
	CSR   volatile.Register32 // 0x0
	WDATA volatile.Register32 // 0x4
	RDATA volatile.Register32 // 0x8
}

// Serial audio interface
type SAI_Type struct {
	_      [4]byte
	ACR1   volatile.Register32 // 0x4
	ACR2   volatile.Register32 // 0x8
	AFRCR  volatile.Register32 // 0xC
	ASLOTR volatile.Register32 // 0x10
	AIM    volatile.Register32 // 0x14
	ASR    volatile.Register32 // 0x18
	ACLRFR volatile.Register32 // 0x1C
	ADR    volatile.Register32 // 0x20
	BCR1   volatile.Register32 // 0x24
	BCR2   volatile.Register32 // 0x28
	BFRCR  volatile.Register32 // 0x2C
	BSLOTR volatile.Register32 // 0x30
	BIM    volatile.Register32 // 0x34
	BSR    volatile.Register32 // 0x38
	BCLRFR volatile.Register32 // 0x3C
	BDR    volatile.Register32 // 0x40
	PDMCR  volatile.Register32 // 0x44
	PDMDLY volatile.Register32 // 0x48
}

// Tamper and backup registers
type TAMP_Type struct {
	CR1    volatile.Register32 // 0x0
	CR2    volatile.Register32 // 0x4
	_      [4]byte
	FLTCR  volatile.Register32 // 0xC
	_      [28]byte
	IER    volatile.Register32 // 0x2C
	SR     volatile.Register32 // 0x30
	MISR   volatile.Register32 // 0x34
	_      [4]byte
	SCR    volatile.Register32 // 0x3C
	_      [192]byte
	BKP0R  volatile.Register32 // 0x100
	BKP1R  volatile.Register32 // 0x104
	BKP2R  volatile.Register32 // 0x108
	BKP3R  volatile.Register32 // 0x10C
	BKP4R  volatile.Register32 // 0x110
	BKP5R  volatile.Register32 // 0x114
	BKP6R  volatile.Register32 // 0x118
	BKP7R  volatile.Register32 // 0x11C
	BKP8R  volatile.Register32 // 0x120
	BKP9R  volatile.Register32 // 0x124
	BKP10R volatile.Register32 // 0x128
	BKP11R volatile.Register32 // 0x12C
	BKP12R volatile.Register32 // 0x130
	BKP13R volatile.Register32 // 0x134
	BKP14R volatile.Register32 // 0x138
	BKP15R volatile.Register32 // 0x13C
	BKP16R volatile.Register32 // 0x140
	BKP17R volatile.Register32 // 0x144
	BKP18R volatile.Register32 // 0x148
	BKP19R volatile.Register32 // 0x14C
	BKP20R volatile.Register32 // 0x150
	BKP21R volatile.Register32 // 0x154
	BKP22R volatile.Register32 // 0x158
	BKP23R volatile.Register32 // 0x15C
	BKP24R volatile.Register32 // 0x160
	BKP25R volatile.Register32 // 0x164
	BKP26R volatile.Register32 // 0x168
	BKP27R volatile.Register32 // 0x16C
	BKP28R volatile.Register32 // 0x170
	BKP29R volatile.Register32 // 0x174
	BKP30R volatile.Register32 // 0x178
	BKP31R volatile.Register32 // 0x17C
}

// Floting point unit
type FPU_Type struct {
	FPCCR volatile.Register32 // 0x0
	FPCAR volatile.Register32 // 0x4
	FPSCR volatile.Register32 // 0x8
}

// Memory protection unit
type MPU_Type struct {
	TYPER volatile.Register32 // 0x0
	CTRL  volatile.Register32 // 0x4
	RNR   volatile.Register32 // 0x8
	RBAR  volatile.Register32 // 0xC
	RASR  volatile.Register32 // 0x10
}

// SysTick timer
type STK_Type struct {
	CTRL  volatile.Register32 // 0x0
	LOAD  volatile.Register32 // 0x4
	VAL   volatile.Register32 // 0x8
	CALIB volatile.Register32 // 0xC
}

// System control block
type SCB_Type struct {
	CPUID                volatile.Register32 // 0x0
	ICSR                 volatile.Register32 // 0x4
	VTOR                 volatile.Register32 // 0x8
	AIRCR                volatile.Register32 // 0xC
	SCR                  volatile.Register32 // 0x10
	CCR                  volatile.Register32 // 0x14
	SHPR1                volatile.Register32 // 0x18
	SHPR2                volatile.Register32 // 0x1C
	SHPR3                volatile.Register32 // 0x20
	SHCRS                volatile.Register32 // 0x24
	CFSR_UFSR_BFSR_MMFSR volatile.Register32 // 0x28
	HFSR                 volatile.Register32 // 0x2C
	_                    [4]byte
	MMFAR                volatile.Register32 // 0x34
	BFAR                 volatile.Register32 // 0x38
	AFSR                 volatile.Register32 // 0x3C
}

// Nested Vectored Interrupt Controller
type NVIC_Type struct {
	ISER0 volatile.Register32 // 0x0
	ISER1 volatile.Register32 // 0x4
	ISER2 volatile.Register32 // 0x8
	ISER3 volatile.Register32 // 0xC
	_     [112]byte
	ICER0 volatile.Register32 // 0x80
	ICER1 volatile.Register32 // 0x84
	ICER2 volatile.Register32 // 0x88
	ICER3 volatile.Register32 // 0x8C
	_     [112]byte
	ISPR0 volatile.Register32 // 0x100
	ISPR1 volatile.Register32 // 0x104
	ISPR2 volatile.Register32 // 0x108
	ISPR3 volatile.Register32 // 0x10C
	_     [112]byte
	ICPR0 volatile.Register32 // 0x180
	ICPR1 volatile.Register32 // 0x184
	ICPR2 volatile.Register32 // 0x188
	ICPR3 volatile.Register32 // 0x18C
	_     [112]byte
	IABR0 volatile.Register32 // 0x200
	IABR1 volatile.Register32 // 0x204
	IABR2 volatile.Register32 // 0x208
	IABR3 volatile.Register32 // 0x20C
	_     [240]byte
	IPR0  volatile.Register32 // 0x300
	IPR1  volatile.Register32 // 0x304
	IPR2  volatile.Register32 // 0x308
	IPR3  volatile.Register32 // 0x30C
	IPR4  volatile.Register32 // 0x310
	IPR5  volatile.Register32 // 0x314
	IPR6  volatile.Register32 // 0x318
	IPR7  volatile.Register32 // 0x31C
	IPR8  volatile.Register32 // 0x320
	IPR9  volatile.Register32 // 0x324
	IPR10 volatile.Register32 // 0x328
	IPR11 volatile.Register32 // 0x32C
	IPR12 volatile.Register32 // 0x330
	IPR13 volatile.Register32 // 0x334
	IPR14 volatile.Register32 // 0x338
	IPR15 volatile.Register32 // 0x33C
	IPR16 volatile.Register32 // 0x340
	IPR17 volatile.Register32 // 0x344
	IPR18 volatile.Register32 // 0x348
	IPR19 volatile.Register32 // 0x34C
	IPR20 volatile.Register32 // 0x350
	IPR21 volatile.Register32 // 0x354
	IPR22 volatile.Register32 // 0x358
	IPR23 volatile.Register32 // 0x35C
	IPR24 volatile.Register32 // 0x360
	IPR25 volatile.Register32 // 0x364
	_     [2712]byte
	STIR  volatile.Register32 // 0xE00
}

// FDCAN
type FDCAN_Type struct {
	CREL   volatile.Register32 // 0x0
	ENDN   volatile.Register32 // 0x4
	_      [4]byte
	DBTP   volatile.Register32 // 0xC
	TEST   volatile.Register32 // 0x10
	RWD    volatile.Register32 // 0x14
	CCCR   volatile.Register32 // 0x18
	NBTP   volatile.Register32 // 0x1C
	TSCC   volatile.Register32 // 0x20
	TSCV   volatile.Register32 // 0x24
	TOCC   volatile.Register32 // 0x28
	TOCV   volatile.Register32 // 0x2C
	_      [16]byte
	ECR    volatile.Register32 // 0x40
	PSR    volatile.Register32 // 0x44
	TDCR   volatile.Register32 // 0x48
	_      [4]byte
	IR     volatile.Register32 // 0x50
	IE     volatile.Register32 // 0x54
	ILS    volatile.Register32 // 0x58
	ILE    volatile.Register32 // 0x5C
	_      [32]byte
	RXGFC  volatile.Register32 // 0x80
	XIDAM  volatile.Register32 // 0x84
	HPMS   volatile.Register32 // 0x88
	_      [4]byte
	RXF0S  volatile.Register32 // 0x90
	RXF0A  volatile.Register32 // 0x94
	RXF1S  volatile.Register32 // 0x98
	RXF1A  volatile.Register32 // 0x9C
	_      [32]byte
	TXBC   volatile.Register32 // 0xC0
	TXFQS  volatile.Register32 // 0xC4
	TXBRP  volatile.Register32 // 0xC8
	TXBAR  volatile.Register32 // 0xCC
	TXBCR  volatile.Register32 // 0xD0
	TXBTO  volatile.Register32 // 0xD4
	TXBCF  volatile.Register32 // 0xD8
	TXBTIE volatile.Register32 // 0xDC
	TXBCIE volatile.Register32 // 0xE0
	TXEFS  volatile.Register32 // 0xE4
	TXEFA  volatile.Register32 // 0xE8
	_      [20]byte
	CKDIV  volatile.Register32 // 0x100
}

// UCPD1
type UCPD_Type struct {
	CFG1       volatile.Register32 // 0x0
	CFG2       volatile.Register32 // 0x4
	_          [4]byte
	CR         volatile.Register32 // 0xC
	IMR        volatile.Register32 // 0x10
	SR         volatile.Register32 // 0x14
	ICR        volatile.Register32 // 0x18
	TX_ORDSET  volatile.Register32 // 0x1C
	TX_PAYSZ   volatile.Register32 // 0x20
	TXDR       volatile.Register32 // 0x24
	RX_ORDSET  volatile.Register32 // 0x28
	RX_PAYSZ   volatile.Register32 // 0x2C
	RXDR       volatile.Register32 // 0x30
	RX_ORDEXT1 volatile.Register32 // 0x34
	RX_ORDEXT2 volatile.Register32 // 0x38
}

// USB_FS_device
type USB_Type struct {
	EP0R   volatile.Register32 // 0x0
	EP1R   volatile.Register32 // 0x4
	EP2R   volatile.Register32 // 0x8
	EP3R   volatile.Register32 // 0xC
	EP4R   volatile.Register32 // 0x10
	EP5R   volatile.Register32 // 0x14
	EP6R   volatile.Register32 // 0x18
	EP7R   volatile.Register32 // 0x1C
	_      [32]byte
	CNTR   volatile.Register32 // 0x40
	ISTR   volatile.Register32 // 0x44
	FNR    volatile.Register32 // 0x48
	DADDR  volatile.Register32 // 0x4C
	BTABLE volatile.Register32 // 0x50
}

// CRS
type CRS_Type struct {
	CR   volatile.Register32 // 0x0
	CFGR volatile.Register32 // 0x4
	ISR  volatile.Register32 // 0x8
	ICR  volatile.Register32 // 0xC
}

// Bitfields for CRC: Cyclic redundancy check calculation unit
const (
	// DR: Data register
	CRC_DR_DR_Pos = 0x0        // Position of DR field.
	CRC_DR_DR_Msk = 0xffffffff // Bit mask of DR field.

	// IDR: Independent data register
	CRC_IDR_IDR_Pos = 0x0        // Position of IDR field.
	CRC_IDR_IDR_Msk = 0xffffffff // Bit mask of IDR field.

	// CR: Control register
	CRC_CR_REV_OUT_Pos  = 0x7  // Position of REV_OUT field.
	CRC_CR_REV_OUT_Msk  = 0x80 // Bit mask of REV_OUT field.
	CRC_CR_REV_OUT      = 0x80 // Bit REV_OUT.
	CRC_CR_REV_IN_Pos   = 0x5  // Position of REV_IN field.
	CRC_CR_REV_IN_Msk   = 0x60 // Bit mask of REV_IN field.
	CRC_CR_POLYSIZE_Pos = 0x3  // Position of POLYSIZE field.
	CRC_CR_POLYSIZE_Msk = 0x18 // Bit mask of POLYSIZE field.
	CRC_CR_RESET_Pos    = 0x0  // Position of RESET field.
	CRC_CR_RESET_Msk    = 0x1  // Bit mask of RESET field.
	CRC_CR_RESET        = 0x1  // Bit RESET.

	// INIT: Initial CRC value
	CRC_INIT_CRC_INIT_Pos = 0x0        // Position of CRC_INIT field.
	CRC_INIT_CRC_INIT_Msk = 0xffffffff // Bit mask of CRC_INIT field.

	// POL: polynomial
	CRC_POL_POL_Pos = 0x0        // Position of POL field.
	CRC_POL_POL_Msk = 0xffffffff // Bit mask of POL field.
)

// Bitfields for WWDG: WinWATCHDOG
const (
	// KR: Key register
	IWDG_KR_KEY_Pos = 0x0    // Position of KEY field.
	IWDG_KR_KEY_Msk = 0xffff // Bit mask of KEY field.

	// PR: Prescaler register
	IWDG_PR_PR_Pos = 0x0 // Position of PR field.
	IWDG_PR_PR_Msk = 0x7 // Bit mask of PR field.

	// RLR: Reload register
	IWDG_RLR_RL_Pos = 0x0   // Position of RL field.
	IWDG_RLR_RL_Msk = 0xfff // Bit mask of RL field.

	// SR: Status register
	IWDG_SR_WVU_Pos = 0x2 // Position of WVU field.
	IWDG_SR_WVU_Msk = 0x4 // Bit mask of WVU field.
	IWDG_SR_WVU     = 0x4 // Bit WVU.
	IWDG_SR_RVU_Pos = 0x1 // Position of RVU field.
	IWDG_SR_RVU_Msk = 0x2 // Bit mask of RVU field.
	IWDG_SR_RVU     = 0x2 // Bit RVU.
	IWDG_SR_PVU_Pos = 0x0 // Position of PVU field.
	IWDG_SR_PVU_Msk = 0x1 // Bit mask of PVU field.
	IWDG_SR_PVU     = 0x1 // Bit PVU.

	// WINR: Window register
	IWDG_WINR_WIN_Pos = 0x0   // Position of WIN field.
	IWDG_WINR_WIN_Msk = 0xfff // Bit mask of WIN field.
)

// Bitfields for IWDG: System window watchdog
const (
	// CR: Control register
	WWDG_CR_WDGA_Pos = 0x7  // Position of WDGA field.
	WWDG_CR_WDGA_Msk = 0x80 // Bit mask of WDGA field.
	WWDG_CR_WDGA     = 0x80 // Bit WDGA.
	WWDG_CR_T_Pos    = 0x0  // Position of T field.
	WWDG_CR_T_Msk    = 0x7f // Bit mask of T field.

	// CFR: Configuration register
	WWDG_CFR_WDGTB_Pos = 0xb    // Position of WDGTB field.
	WWDG_CFR_WDGTB_Msk = 0x3800 // Bit mask of WDGTB field.
	WWDG_CFR_EWI_Pos   = 0x9    // Position of EWI field.
	WWDG_CFR_EWI_Msk   = 0x200  // Bit mask of EWI field.
	WWDG_CFR_EWI       = 0x200  // Bit EWI.
	WWDG_CFR_W_Pos     = 0x0    // Position of W field.
	WWDG_CFR_W_Msk     = 0x7f   // Bit mask of W field.

	// SR: Status register
	WWDG_SR_EWIF_Pos = 0x0 // Position of EWIF field.
	WWDG_SR_EWIF_Msk = 0x1 // Bit mask of EWIF field.
	WWDG_SR_EWIF     = 0x1 // Bit EWIF.
)

// Bitfields for I2C1: Inter-integrated circuit
const (
	// CR1: Control register 1
	I2C_CR1_PE_Pos        = 0x0      // Position of PE field.
	I2C_CR1_PE_Msk        = 0x1      // Bit mask of PE field.
	I2C_CR1_PE            = 0x1      // Bit PE.
	I2C_CR1_TXIE_Pos      = 0x1      // Position of TXIE field.
	I2C_CR1_TXIE_Msk      = 0x2      // Bit mask of TXIE field.
	I2C_CR1_TXIE          = 0x2      // Bit TXIE.
	I2C_CR1_RXIE_Pos      = 0x2      // Position of RXIE field.
	I2C_CR1_RXIE_Msk      = 0x4      // Bit mask of RXIE field.
	I2C_CR1_RXIE          = 0x4      // Bit RXIE.
	I2C_CR1_ADDRIE_Pos    = 0x3      // Position of ADDRIE field.
	I2C_CR1_ADDRIE_Msk    = 0x8      // Bit mask of ADDRIE field.
	I2C_CR1_ADDRIE        = 0x8      // Bit ADDRIE.
	I2C_CR1_NACKIE_Pos    = 0x4      // Position of NACKIE field.
	I2C_CR1_NACKIE_Msk    = 0x10     // Bit mask of NACKIE field.
	I2C_CR1_NACKIE        = 0x10     // Bit NACKIE.
	I2C_CR1_STOPIE_Pos    = 0x5      // Position of STOPIE field.
	I2C_CR1_STOPIE_Msk    = 0x20     // Bit mask of STOPIE field.
	I2C_CR1_STOPIE        = 0x20     // Bit STOPIE.
	I2C_CR1_TCIE_Pos      = 0x6      // Position of TCIE field.
	I2C_CR1_TCIE_Msk      = 0x40     // Bit mask of TCIE field.
	I2C_CR1_TCIE          = 0x40     // Bit TCIE.
	I2C_CR1_ERRIE_Pos     = 0x7      // Position of ERRIE field.
	I2C_CR1_ERRIE_Msk     = 0x80     // Bit mask of ERRIE field.
	I2C_CR1_ERRIE         = 0x80     // Bit ERRIE.
	I2C_CR1_DNF_Pos       = 0x8      // Position of DNF field.
	I2C_CR1_DNF_Msk       = 0xf00    // Bit mask of DNF field.
	I2C_CR1_ANFOFF_Pos    = 0xc      // Position of ANFOFF field.
	I2C_CR1_ANFOFF_Msk    = 0x1000   // Bit mask of ANFOFF field.
	I2C_CR1_ANFOFF        = 0x1000   // Bit ANFOFF.
	I2C_CR1_TXDMAEN_Pos   = 0xe      // Position of TXDMAEN field.
	I2C_CR1_TXDMAEN_Msk   = 0x4000   // Bit mask of TXDMAEN field.
	I2C_CR1_TXDMAEN       = 0x4000   // Bit TXDMAEN.
	I2C_CR1_RXDMAEN_Pos   = 0xf      // Position of RXDMAEN field.
	I2C_CR1_RXDMAEN_Msk   = 0x8000   // Bit mask of RXDMAEN field.
	I2C_CR1_RXDMAEN       = 0x8000   // Bit RXDMAEN.
	I2C_CR1_SBC_Pos       = 0x10     // Position of SBC field.
	I2C_CR1_SBC_Msk       = 0x10000  // Bit mask of SBC field.
	I2C_CR1_SBC           = 0x10000  // Bit SBC.
	I2C_CR1_NOSTRETCH_Pos = 0x11     // Position of NOSTRETCH field.
	I2C_CR1_NOSTRETCH_Msk = 0x20000  // Bit mask of NOSTRETCH field.
	I2C_CR1_NOSTRETCH     = 0x20000  // Bit NOSTRETCH.
	I2C_CR1_WUPEN_Pos     = 0x12     // Position of WUPEN field.
	I2C_CR1_WUPEN_Msk     = 0x40000  // Bit mask of WUPEN field.
	I2C_CR1_WUPEN         = 0x40000  // Bit WUPEN.
	I2C_CR1_GCEN_Pos      = 0x13     // Position of GCEN field.
	I2C_CR1_GCEN_Msk      = 0x80000  // Bit mask of GCEN field.
	I2C_CR1_GCEN          = 0x80000  // Bit GCEN.
	I2C_CR1_SMBHEN_Pos    = 0x14     // Position of SMBHEN field.
	I2C_CR1_SMBHEN_Msk    = 0x100000 // Bit mask of SMBHEN field.
	I2C_CR1_SMBHEN        = 0x100000 // Bit SMBHEN.
	I2C_CR1_SMBDEN_Pos    = 0x15     // Position of SMBDEN field.
	I2C_CR1_SMBDEN_Msk    = 0x200000 // Bit mask of SMBDEN field.
	I2C_CR1_SMBDEN        = 0x200000 // Bit SMBDEN.
	I2C_CR1_ALERTEN_Pos   = 0x16     // Position of ALERTEN field.
	I2C_CR1_ALERTEN_Msk   = 0x400000 // Bit mask of ALERTEN field.
	I2C_CR1_ALERTEN       = 0x400000 // Bit ALERTEN.
	I2C_CR1_PECEN_Pos     = 0x17     // Position of PECEN field.
	I2C_CR1_PECEN_Msk     = 0x800000 // Bit mask of PECEN field.
	I2C_CR1_PECEN         = 0x800000 // Bit PECEN.

	// CR2: Control register 2
	I2C_CR2_PECBYTE_Pos = 0x1a      // Position of PECBYTE field.
	I2C_CR2_PECBYTE_Msk = 0x4000000 // Bit mask of PECBYTE field.
	I2C_CR2_PECBYTE     = 0x4000000 // Bit PECBYTE.
	I2C_CR2_AUTOEND_Pos = 0x19      // Position of AUTOEND field.
	I2C_CR2_AUTOEND_Msk = 0x2000000 // Bit mask of AUTOEND field.
	I2C_CR2_AUTOEND     = 0x2000000 // Bit AUTOEND.
	I2C_CR2_RELOAD_Pos  = 0x18      // Position of RELOAD field.
	I2C_CR2_RELOAD_Msk  = 0x1000000 // Bit mask of RELOAD field.
	I2C_CR2_RELOAD      = 0x1000000 // Bit RELOAD.
	I2C_CR2_NBYTES_Pos  = 0x10      // Position of NBYTES field.
	I2C_CR2_NBYTES_Msk  = 0xff0000  // Bit mask of NBYTES field.
	I2C_CR2_NACK_Pos    = 0xf       // Position of NACK field.
	I2C_CR2_NACK_Msk    = 0x8000    // Bit mask of NACK field.
	I2C_CR2_NACK        = 0x8000    // Bit NACK.
	I2C_CR2_STOP_Pos    = 0xe       // Position of STOP field.
	I2C_CR2_STOP_Msk    = 0x4000    // Bit mask of STOP field.
	I2C_CR2_STOP        = 0x4000    // Bit STOP.
	I2C_CR2_START_Pos   = 0xd       // Position of START field.
	I2C_CR2_START_Msk   = 0x2000    // Bit mask of START field.
	I2C_CR2_START       = 0x2000    // Bit START.
	I2C_CR2_HEAD10R_Pos = 0xc       // Position of HEAD10R field.
	I2C_CR2_HEAD10R_Msk = 0x1000    // Bit mask of HEAD10R field.
	I2C_CR2_HEAD10R     = 0x1000    // Bit HEAD10R.
	I2C_CR2_ADD10_Pos   = 0xb       // Position of ADD10 field.
	I2C_CR2_ADD10_Msk   = 0x800     // Bit mask of ADD10 field.
	I2C_CR2_ADD10       = 0x800     // Bit ADD10.
	I2C_CR2_RD_WRN_Pos  = 0xa       // Position of RD_WRN field.
	I2C_CR2_RD_WRN_Msk  = 0x400     // Bit mask of RD_WRN field.
	I2C_CR2_RD_WRN      = 0x400     // Bit RD_WRN.
	I2C_CR2_SADD_Pos    = 0x0       // Position of SADD field.
	I2C_CR2_SADD_Msk    = 0x3ff     // Bit mask of SADD field.

	// OAR1: Own address register 1
	I2C_OAR1_OA1_Pos     = 0x0    // Position of OA1 field.
	I2C_OAR1_OA1_Msk     = 0x3ff  // Bit mask of OA1 field.
	I2C_OAR1_OA1MODE_Pos = 0xa    // Position of OA1MODE field.
	I2C_OAR1_OA1MODE_Msk = 0x400  // Bit mask of OA1MODE field.
	I2C_OAR1_OA1MODE     = 0x400  // Bit OA1MODE.
	I2C_OAR1_OA1EN_Pos   = 0xf    // Position of OA1EN field.
	I2C_OAR1_OA1EN_Msk   = 0x8000 // Bit mask of OA1EN field.
	I2C_OAR1_OA1EN       = 0x8000 // Bit OA1EN.

	// OAR2: Own address register 2
	I2C_OAR2_OA2_Pos    = 0x1    // Position of OA2 field.
	I2C_OAR2_OA2_Msk    = 0xfe   // Bit mask of OA2 field.
	I2C_OAR2_OA2MSK_Pos = 0x8    // Position of OA2MSK field.
	I2C_OAR2_OA2MSK_Msk = 0x700  // Bit mask of OA2MSK field.
	I2C_OAR2_OA2EN_Pos  = 0xf    // Position of OA2EN field.
	I2C_OAR2_OA2EN_Msk  = 0x8000 // Bit mask of OA2EN field.
	I2C_OAR2_OA2EN      = 0x8000 // Bit OA2EN.

	// TIMINGR: Timing register
	I2C_TIMINGR_SCLL_Pos   = 0x0        // Position of SCLL field.
	I2C_TIMINGR_SCLL_Msk   = 0xff       // Bit mask of SCLL field.
	I2C_TIMINGR_SCLH_Pos   = 0x8        // Position of SCLH field.
	I2C_TIMINGR_SCLH_Msk   = 0xff00     // Bit mask of SCLH field.
	I2C_TIMINGR_SDADEL_Pos = 0x10       // Position of SDADEL field.
	I2C_TIMINGR_SDADEL_Msk = 0xf0000    // Bit mask of SDADEL field.
	I2C_TIMINGR_SCLDEL_Pos = 0x14       // Position of SCLDEL field.
	I2C_TIMINGR_SCLDEL_Msk = 0xf00000   // Bit mask of SCLDEL field.
	I2C_TIMINGR_PRESC_Pos  = 0x1c       // Position of PRESC field.
	I2C_TIMINGR_PRESC_Msk  = 0xf0000000 // Bit mask of PRESC field.

	// TIMEOUTR: Status register 1
	I2C_TIMEOUTR_TIMEOUTA_Pos = 0x0        // Position of TIMEOUTA field.
	I2C_TIMEOUTR_TIMEOUTA_Msk = 0xfff      // Bit mask of TIMEOUTA field.
	I2C_TIMEOUTR_TIDLE_Pos    = 0xc        // Position of TIDLE field.
	I2C_TIMEOUTR_TIDLE_Msk    = 0x1000     // Bit mask of TIDLE field.
	I2C_TIMEOUTR_TIDLE        = 0x1000     // Bit TIDLE.
	I2C_TIMEOUTR_TIMOUTEN_Pos = 0xf        // Position of TIMOUTEN field.
	I2C_TIMEOUTR_TIMOUTEN_Msk = 0x8000     // Bit mask of TIMOUTEN field.
	I2C_TIMEOUTR_TIMOUTEN     = 0x8000     // Bit TIMOUTEN.
	I2C_TIMEOUTR_TIMEOUTB_Pos = 0x10       // Position of TIMEOUTB field.
	I2C_TIMEOUTR_TIMEOUTB_Msk = 0xfff0000  // Bit mask of TIMEOUTB field.
	I2C_TIMEOUTR_TEXTEN_Pos   = 0x1f       // Position of TEXTEN field.
	I2C_TIMEOUTR_TEXTEN_Msk   = 0x80000000 // Bit mask of TEXTEN field.
	I2C_TIMEOUTR_TEXTEN       = 0x80000000 // Bit TEXTEN.

	// ISR: Interrupt and Status register
	I2C_ISR_ADDCODE_Pos = 0x11     // Position of ADDCODE field.
	I2C_ISR_ADDCODE_Msk = 0xfe0000 // Bit mask of ADDCODE field.
	I2C_ISR_DIR_Pos     = 0x10     // Position of DIR field.
	I2C_ISR_DIR_Msk     = 0x10000  // Bit mask of DIR field.
	I2C_ISR_DIR         = 0x10000  // Bit DIR.
	I2C_ISR_BUSY_Pos    = 0xf      // Position of BUSY field.
	I2C_ISR_BUSY_Msk    = 0x8000   // Bit mask of BUSY field.
	I2C_ISR_BUSY        = 0x8000   // Bit BUSY.
	I2C_ISR_ALERT_Pos   = 0xd      // Position of ALERT field.
	I2C_ISR_ALERT_Msk   = 0x2000   // Bit mask of ALERT field.
	I2C_ISR_ALERT       = 0x2000   // Bit ALERT.
	I2C_ISR_TIMEOUT_Pos = 0xc      // Position of TIMEOUT field.
	I2C_ISR_TIMEOUT_Msk = 0x1000   // Bit mask of TIMEOUT field.
	I2C_ISR_TIMEOUT     = 0x1000   // Bit TIMEOUT.
	I2C_ISR_PECERR_Pos  = 0xb      // Position of PECERR field.
	I2C_ISR_PECERR_Msk  = 0x800    // Bit mask of PECERR field.
	I2C_ISR_PECERR      = 0x800    // Bit PECERR.
	I2C_ISR_OVR_Pos     = 0xa      // Position of OVR field.
	I2C_ISR_OVR_Msk     = 0x400    // Bit mask of OVR field.
	I2C_ISR_OVR         = 0x400    // Bit OVR.
	I2C_ISR_ARLO_Pos    = 0x9      // Position of ARLO field.
	I2C_ISR_ARLO_Msk    = 0x200    // Bit mask of ARLO field.
	I2C_ISR_ARLO        = 0x200    // Bit ARLO.
	I2C_ISR_BERR_Pos    = 0x8      // Position of BERR field.
	I2C_ISR_BERR_Msk    = 0x100    // Bit mask of BERR field.
	I2C_ISR_BERR        = 0x100    // Bit BERR.
	I2C_ISR_TCR_Pos     = 0x7      // Position of TCR field.
	I2C_ISR_TCR_Msk     = 0x80     // Bit mask of TCR field.
	I2C_ISR_TCR         = 0x80     // Bit TCR.
	I2C_ISR_TC_Pos      = 0x6      // Position of TC field.
	I2C_ISR_TC_Msk      = 0x40     // Bit mask of TC field.
	I2C_ISR_TC          = 0x40     // Bit TC.
	I2C_ISR_STOPF_Pos   = 0x5      // Position of STOPF field.
	I2C_ISR_STOPF_Msk   = 0x20     // Bit mask of STOPF field.
	I2C_ISR_STOPF       = 0x20     // Bit STOPF.
	I2C_ISR_NACKF_Pos   = 0x4      // Position of NACKF field.
	I2C_ISR_NACKF_Msk   = 0x10     // Bit mask of NACKF field.
	I2C_ISR_NACKF       = 0x10     // Bit NACKF.
	I2C_ISR_ADDR_Pos    = 0x3      // Position of ADDR field.
	I2C_ISR_ADDR_Msk    = 0x8      // Bit mask of ADDR field.
	I2C_ISR_ADDR        = 0x8      // Bit ADDR.
	I2C_ISR_RXNE_Pos    = 0x2      // Position of RXNE field.
	I2C_ISR_RXNE_Msk    = 0x4      // Bit mask of RXNE field.
	I2C_ISR_RXNE        = 0x4      // Bit RXNE.
	I2C_ISR_TXIS_Pos    = 0x1      // Position of TXIS field.
	I2C_ISR_TXIS_Msk    = 0x2      // Bit mask of TXIS field.
	I2C_ISR_TXIS        = 0x2      // Bit TXIS.
	I2C_ISR_TXE_Pos     = 0x0      // Position of TXE field.
	I2C_ISR_TXE_Msk     = 0x1      // Bit mask of TXE field.
	I2C_ISR_TXE         = 0x1      // Bit TXE.

	// ICR: Interrupt clear register
	I2C_ICR_ALERTCF_Pos  = 0xd    // Position of ALERTCF field.
	I2C_ICR_ALERTCF_Msk  = 0x2000 // Bit mask of ALERTCF field.
	I2C_ICR_ALERTCF      = 0x2000 // Bit ALERTCF.
	I2C_ICR_TIMOUTCF_Pos = 0xc    // Position of TIMOUTCF field.
	I2C_ICR_TIMOUTCF_Msk = 0x1000 // Bit mask of TIMOUTCF field.
	I2C_ICR_TIMOUTCF     = 0x1000 // Bit TIMOUTCF.
	I2C_ICR_PECCF_Pos    = 0xb    // Position of PECCF field.
	I2C_ICR_PECCF_Msk    = 0x800  // Bit mask of PECCF field.
	I2C_ICR_PECCF        = 0x800  // Bit PECCF.
	I2C_ICR_OVRCF_Pos    = 0xa    // Position of OVRCF field.
	I2C_ICR_OVRCF_Msk    = 0x400  // Bit mask of OVRCF field.
	I2C_ICR_OVRCF        = 0x400  // Bit OVRCF.
	I2C_ICR_ARLOCF_Pos   = 0x9    // Position of ARLOCF field.
	I2C_ICR_ARLOCF_Msk   = 0x200  // Bit mask of ARLOCF field.
	I2C_ICR_ARLOCF       = 0x200  // Bit ARLOCF.
	I2C_ICR_BERRCF_Pos   = 0x8    // Position of BERRCF field.
	I2C_ICR_BERRCF_Msk   = 0x100  // Bit mask of BERRCF field.
	I2C_ICR_BERRCF       = 0x100  // Bit BERRCF.
	I2C_ICR_STOPCF_Pos   = 0x5    // Position of STOPCF field.
	I2C_ICR_STOPCF_Msk   = 0x20   // Bit mask of STOPCF field.
	I2C_ICR_STOPCF       = 0x20   // Bit STOPCF.
	I2C_ICR_NACKCF_Pos   = 0x4    // Position of NACKCF field.
	I2C_ICR_NACKCF_Msk   = 0x10   // Bit mask of NACKCF field.
	I2C_ICR_NACKCF       = 0x10   // Bit NACKCF.
	I2C_ICR_ADDRCF_Pos   = 0x3    // Position of ADDRCF field.
	I2C_ICR_ADDRCF_Msk   = 0x8    // Bit mask of ADDRCF field.
	I2C_ICR_ADDRCF       = 0x8    // Bit ADDRCF.

	// PECR: PEC register
	I2C_PECR_PEC_Pos = 0x0  // Position of PEC field.
	I2C_PECR_PEC_Msk = 0xff // Bit mask of PEC field.

	// RXDR: Receive data register
	I2C_RXDR_RXDATA_Pos = 0x0  // Position of RXDATA field.
	I2C_RXDR_RXDATA_Msk = 0xff // Bit mask of RXDATA field.

	// TXDR: Transmit data register
	I2C_TXDR_TXDATA_Pos = 0x0  // Position of TXDATA field.
	I2C_TXDR_TXDATA_Msk = 0xff // Bit mask of TXDATA field.
)

// Bitfields for FLASH: Flash
const (
	// ACR: Access control register
	Flash_ACR_LATENCY_Pos  = 0x0     // Position of LATENCY field.
	Flash_ACR_LATENCY_Msk  = 0xf     // Bit mask of LATENCY field.
	Flash_ACR_PRFTEN_Pos   = 0x8     // Position of PRFTEN field.
	Flash_ACR_PRFTEN_Msk   = 0x100   // Bit mask of PRFTEN field.
	Flash_ACR_PRFTEN       = 0x100   // Bit PRFTEN.
	Flash_ACR_ICEN_Pos     = 0x9     // Position of ICEN field.
	Flash_ACR_ICEN_Msk     = 0x200   // Bit mask of ICEN field.
	Flash_ACR_ICEN         = 0x200   // Bit ICEN.
	Flash_ACR_DCEN_Pos     = 0xa     // Position of DCEN field.
	Flash_ACR_DCEN_Msk     = 0x400   // Bit mask of DCEN field.
	Flash_ACR_DCEN         = 0x400   // Bit DCEN.
	Flash_ACR_ICRST_Pos    = 0xb     // Position of ICRST field.
	Flash_ACR_ICRST_Msk    = 0x800   // Bit mask of ICRST field.
	Flash_ACR_ICRST        = 0x800   // Bit ICRST.
	Flash_ACR_DCRST_Pos    = 0xc     // Position of DCRST field.
	Flash_ACR_DCRST_Msk    = 0x1000  // Bit mask of DCRST field.
	Flash_ACR_DCRST        = 0x1000  // Bit DCRST.
	Flash_ACR_RUN_PD_Pos   = 0xd     // Position of RUN_PD field.
	Flash_ACR_RUN_PD_Msk   = 0x2000  // Bit mask of RUN_PD field.
	Flash_ACR_RUN_PD       = 0x2000  // Bit RUN_PD.
	Flash_ACR_SLEEP_PD_Pos = 0xe     // Position of SLEEP_PD field.
	Flash_ACR_SLEEP_PD_Msk = 0x4000  // Bit mask of SLEEP_PD field.
	Flash_ACR_SLEEP_PD     = 0x4000  // Bit SLEEP_PD.
	Flash_ACR_DBG_SWEN_Pos = 0x12    // Position of DBG_SWEN field.
	Flash_ACR_DBG_SWEN_Msk = 0x40000 // Bit mask of DBG_SWEN field.
	Flash_ACR_DBG_SWEN     = 0x40000 // Bit DBG_SWEN.

	// PDKEYR: Power down key register
	Flash_PDKEYR_PDKEYR_Pos = 0x0        // Position of PDKEYR field.
	Flash_PDKEYR_PDKEYR_Msk = 0xffffffff // Bit mask of PDKEYR field.

	// KEYR: Flash key register
	Flash_KEYR_KEYR_Pos = 0x0        // Position of KEYR field.
	Flash_KEYR_KEYR_Msk = 0xffffffff // Bit mask of KEYR field.

	// OPTKEYR: Option byte key register
	Flash_OPTKEYR_OPTKEYR_Pos = 0x0        // Position of OPTKEYR field.
	Flash_OPTKEYR_OPTKEYR_Msk = 0xffffffff // Bit mask of OPTKEYR field.

	// SR: Status register
	Flash_SR_EOP_Pos     = 0x0     // Position of EOP field.
	Flash_SR_EOP_Msk     = 0x1     // Bit mask of EOP field.
	Flash_SR_EOP         = 0x1     // Bit EOP.
	Flash_SR_OPERR_Pos   = 0x1     // Position of OPERR field.
	Flash_SR_OPERR_Msk   = 0x2     // Bit mask of OPERR field.
	Flash_SR_OPERR       = 0x2     // Bit OPERR.
	Flash_SR_PROGERR_Pos = 0x3     // Position of PROGERR field.
	Flash_SR_PROGERR_Msk = 0x8     // Bit mask of PROGERR field.
	Flash_SR_PROGERR     = 0x8     // Bit PROGERR.
	Flash_SR_WRPERR_Pos  = 0x4     // Position of WRPERR field.
	Flash_SR_WRPERR_Msk  = 0x10    // Bit mask of WRPERR field.
	Flash_SR_WRPERR      = 0x10    // Bit WRPERR.
	Flash_SR_PGAERR_Pos  = 0x5     // Position of PGAERR field.
	Flash_SR_PGAERR_Msk  = 0x20    // Bit mask of PGAERR field.
	Flash_SR_PGAERR      = 0x20    // Bit PGAERR.
	Flash_SR_SIZERR_Pos  = 0x6     // Position of SIZERR field.
	Flash_SR_SIZERR_Msk  = 0x40    // Bit mask of SIZERR field.
	Flash_SR_SIZERR      = 0x40    // Bit SIZERR.
	Flash_SR_PGSERR_Pos  = 0x7     // Position of PGSERR field.
	Flash_SR_PGSERR_Msk  = 0x80    // Bit mask of PGSERR field.
	Flash_SR_PGSERR      = 0x80    // Bit PGSERR.
	Flash_SR_MISERR_Pos  = 0x8     // Position of MISERR field.
	Flash_SR_MISERR_Msk  = 0x100   // Bit mask of MISERR field.
	Flash_SR_MISERR      = 0x100   // Bit MISERR.
	Flash_SR_FASTERR_Pos = 0x9     // Position of FASTERR field.
	Flash_SR_FASTERR_Msk = 0x200   // Bit mask of FASTERR field.
	Flash_SR_FASTERR     = 0x200   // Bit FASTERR.
	Flash_SR_RDERR_Pos   = 0xe     // Position of RDERR field.
	Flash_SR_RDERR_Msk   = 0x4000  // Bit mask of RDERR field.
	Flash_SR_RDERR       = 0x4000  // Bit RDERR.
	Flash_SR_OPTVERR_Pos = 0xf     // Position of OPTVERR field.
	Flash_SR_OPTVERR_Msk = 0x8000  // Bit mask of OPTVERR field.
	Flash_SR_OPTVERR     = 0x8000  // Bit OPTVERR.
	Flash_SR_BSY_Pos     = 0x10    // Position of BSY field.
	Flash_SR_BSY_Msk     = 0x10000 // Bit mask of BSY field.
	Flash_SR_BSY         = 0x10000 // Bit BSY.

	// CR: Flash control register
	Flash_CR_PG_Pos         = 0x0        // Position of PG field.
	Flash_CR_PG_Msk         = 0x1        // Bit mask of PG field.
	Flash_CR_PG             = 0x1        // Bit PG.
	Flash_CR_PER_Pos        = 0x1        // Position of PER field.
	Flash_CR_PER_Msk        = 0x2        // Bit mask of PER field.
	Flash_CR_PER            = 0x2        // Bit PER.
	Flash_CR_MER1_Pos       = 0x2        // Position of MER1 field.
	Flash_CR_MER1_Msk       = 0x4        // Bit mask of MER1 field.
	Flash_CR_MER1           = 0x4        // Bit MER1.
	Flash_CR_PNB_Pos        = 0x3        // Position of PNB field.
	Flash_CR_PNB_Msk        = 0x3f8      // Bit mask of PNB field.
	Flash_CR_STRT_Pos       = 0x10       // Position of STRT field.
	Flash_CR_STRT_Msk       = 0x10000    // Bit mask of STRT field.
	Flash_CR_STRT           = 0x10000    // Bit STRT.
	Flash_CR_OPTSTRT_Pos    = 0x11       // Position of OPTSTRT field.
	Flash_CR_OPTSTRT_Msk    = 0x20000    // Bit mask of OPTSTRT field.
	Flash_CR_OPTSTRT        = 0x20000    // Bit OPTSTRT.
	Flash_CR_FSTPG_Pos      = 0x12       // Position of FSTPG field.
	Flash_CR_FSTPG_Msk      = 0x40000    // Bit mask of FSTPG field.
	Flash_CR_FSTPG          = 0x40000    // Bit FSTPG.
	Flash_CR_EOPIE_Pos      = 0x18       // Position of EOPIE field.
	Flash_CR_EOPIE_Msk      = 0x1000000  // Bit mask of EOPIE field.
	Flash_CR_EOPIE          = 0x1000000  // Bit EOPIE.
	Flash_CR_ERRIE_Pos      = 0x19       // Position of ERRIE field.
	Flash_CR_ERRIE_Msk      = 0x2000000  // Bit mask of ERRIE field.
	Flash_CR_ERRIE          = 0x2000000  // Bit ERRIE.
	Flash_CR_RDERRIE_Pos    = 0x1a       // Position of RDERRIE field.
	Flash_CR_RDERRIE_Msk    = 0x4000000  // Bit mask of RDERRIE field.
	Flash_CR_RDERRIE        = 0x4000000  // Bit RDERRIE.
	Flash_CR_OBL_LAUNCH_Pos = 0x1b       // Position of OBL_LAUNCH field.
	Flash_CR_OBL_LAUNCH_Msk = 0x8000000  // Bit mask of OBL_LAUNCH field.
	Flash_CR_OBL_LAUNCH     = 0x8000000  // Bit OBL_LAUNCH.
	Flash_CR_SEC_PROT1_Pos  = 0x1c       // Position of SEC_PROT1 field.
	Flash_CR_SEC_PROT1_Msk  = 0x10000000 // Bit mask of SEC_PROT1 field.
	Flash_CR_SEC_PROT1      = 0x10000000 // Bit SEC_PROT1.
	Flash_CR_OPTLOCK_Pos    = 0x1e       // Position of OPTLOCK field.
	Flash_CR_OPTLOCK_Msk    = 0x40000000 // Bit mask of OPTLOCK field.
	Flash_CR_OPTLOCK        = 0x40000000 // Bit OPTLOCK.
	Flash_CR_LOCK_Pos       = 0x1f       // Position of LOCK field.
	Flash_CR_LOCK_Msk       = 0x80000000 // Bit mask of LOCK field.
	Flash_CR_LOCK           = 0x80000000 // Bit LOCK.

	// ECCR: Flash ECC register
	Flash_ECCR_ADDR_ECC_Pos = 0x0        // Position of ADDR_ECC field.
	Flash_ECCR_ADDR_ECC_Msk = 0x7ffff    // Bit mask of ADDR_ECC field.
	Flash_ECCR_BK_ECC_Pos   = 0x15       // Position of BK_ECC field.
	Flash_ECCR_BK_ECC_Msk   = 0x200000   // Bit mask of BK_ECC field.
	Flash_ECCR_BK_ECC       = 0x200000   // Bit BK_ECC.
	Flash_ECCR_SYSF_ECC_Pos = 0x16       // Position of SYSF_ECC field.
	Flash_ECCR_SYSF_ECC_Msk = 0x400000   // Bit mask of SYSF_ECC field.
	Flash_ECCR_SYSF_ECC     = 0x400000   // Bit SYSF_ECC.
	Flash_ECCR_ECCIE_Pos    = 0x18       // Position of ECCIE field.
	Flash_ECCR_ECCIE_Msk    = 0x1000000  // Bit mask of ECCIE field.
	Flash_ECCR_ECCIE        = 0x1000000  // Bit ECCIE.
	Flash_ECCR_ECCC2_Pos    = 0x1c       // Position of ECCC2 field.
	Flash_ECCR_ECCC2_Msk    = 0x10000000 // Bit mask of ECCC2 field.
	Flash_ECCR_ECCC2        = 0x10000000 // Bit ECCC2.
	Flash_ECCR_ECCD2_Pos    = 0x1d       // Position of ECCD2 field.
	Flash_ECCR_ECCD2_Msk    = 0x20000000 // Bit mask of ECCD2 field.
	Flash_ECCR_ECCD2        = 0x20000000 // Bit ECCD2.
	Flash_ECCR_ECCC_Pos     = 0x1e       // Position of ECCC field.
	Flash_ECCR_ECCC_Msk     = 0x40000000 // Bit mask of ECCC field.
	Flash_ECCR_ECCC         = 0x40000000 // Bit ECCC.
	Flash_ECCR_ECCD_Pos     = 0x1f       // Position of ECCD field.
	Flash_ECCR_ECCD_Msk     = 0x80000000 // Bit mask of ECCD field.
	Flash_ECCR_ECCD         = 0x80000000 // Bit ECCD.

	// OPTR: Flash option register
	Flash_OPTR_RDP_Pos        = 0x0        // Position of RDP field.
	Flash_OPTR_RDP_Msk        = 0xff       // Bit mask of RDP field.
	Flash_OPTR_BOR_LEV_Pos    = 0x8        // Position of BOR_LEV field.
	Flash_OPTR_BOR_LEV_Msk    = 0x700      // Bit mask of BOR_LEV field.
	Flash_OPTR_NRST_STOP_Pos  = 0xc        // Position of NRST_STOP field.
	Flash_OPTR_NRST_STOP_Msk  = 0x1000     // Bit mask of NRST_STOP field.
	Flash_OPTR_NRST_STOP      = 0x1000     // Bit NRST_STOP.
	Flash_OPTR_NRST_STDBY_Pos = 0xd        // Position of NRST_STDBY field.
	Flash_OPTR_NRST_STDBY_Msk = 0x2000     // Bit mask of NRST_STDBY field.
	Flash_OPTR_NRST_STDBY     = 0x2000     // Bit NRST_STDBY.
	Flash_OPTR_NRST_SHDW_Pos  = 0xe        // Position of NRST_SHDW field.
	Flash_OPTR_NRST_SHDW_Msk  = 0x4000     // Bit mask of NRST_SHDW field.
	Flash_OPTR_NRST_SHDW      = 0x4000     // Bit NRST_SHDW.
	Flash_OPTR_IDWG_SW_Pos    = 0x10       // Position of IDWG_SW field.
	Flash_OPTR_IDWG_SW_Msk    = 0x10000    // Bit mask of IDWG_SW field.
	Flash_OPTR_IDWG_SW        = 0x10000    // Bit IDWG_SW.
	Flash_OPTR_IWDG_STOP_Pos  = 0x11       // Position of IWDG_STOP field.
	Flash_OPTR_IWDG_STOP_Msk  = 0x20000    // Bit mask of IWDG_STOP field.
	Flash_OPTR_IWDG_STOP      = 0x20000    // Bit IWDG_STOP.
	Flash_OPTR_IWDG_STDBY_Pos = 0x12       // Position of IWDG_STDBY field.
	Flash_OPTR_IWDG_STDBY_Msk = 0x40000    // Bit mask of IWDG_STDBY field.
	Flash_OPTR_IWDG_STDBY     = 0x40000    // Bit IWDG_STDBY.
	Flash_OPTR_WWDG_SW_Pos    = 0x13       // Position of WWDG_SW field.
	Flash_OPTR_WWDG_SW_Msk    = 0x80000    // Bit mask of WWDG_SW field.
	Flash_OPTR_WWDG_SW        = 0x80000    // Bit WWDG_SW.
	Flash_OPTR_NBOOT1_Pos     = 0x17       // Position of NBOOT1 field.
	Flash_OPTR_NBOOT1_Msk     = 0x800000   // Bit mask of NBOOT1 field.
	Flash_OPTR_NBOOT1         = 0x800000   // Bit NBOOT1.
	Flash_OPTR_SRAM2_PE_Pos   = 0x18       // Position of SRAM2_PE field.
	Flash_OPTR_SRAM2_PE_Msk   = 0x1000000  // Bit mask of SRAM2_PE field.
	Flash_OPTR_SRAM2_PE       = 0x1000000  // Bit SRAM2_PE.
	Flash_OPTR_SRAM2_RST_Pos  = 0x19       // Position of SRAM2_RST field.
	Flash_OPTR_SRAM2_RST_Msk  = 0x2000000  // Bit mask of SRAM2_RST field.
	Flash_OPTR_SRAM2_RST      = 0x2000000  // Bit SRAM2_RST.
	Flash_OPTR_NSWBOOT0_Pos   = 0x1a       // Position of NSWBOOT0 field.
	Flash_OPTR_NSWBOOT0_Msk   = 0x4000000  // Bit mask of NSWBOOT0 field.
	Flash_OPTR_NSWBOOT0       = 0x4000000  // Bit NSWBOOT0.
	Flash_OPTR_NBOOT0_Pos     = 0x1b       // Position of NBOOT0 field.
	Flash_OPTR_NBOOT0_Msk     = 0x8000000  // Bit mask of NBOOT0 field.
	Flash_OPTR_NBOOT0         = 0x8000000  // Bit NBOOT0.
	Flash_OPTR_NRST_MODE_Pos  = 0x1c       // Position of NRST_MODE field.
	Flash_OPTR_NRST_MODE_Msk  = 0x30000000 // Bit mask of NRST_MODE field.
	Flash_OPTR_IRHEN_Pos      = 0x1e       // Position of IRHEN field.
	Flash_OPTR_IRHEN_Msk      = 0x40000000 // Bit mask of IRHEN field.
	Flash_OPTR_IRHEN          = 0x40000000 // Bit IRHEN.

	// PCROP1SR: Flash Bank 1 PCROP Start address           register
	Flash_PCROP1SR_PCROP1_STRT_Pos = 0x0    // Position of PCROP1_STRT field.
	Flash_PCROP1SR_PCROP1_STRT_Msk = 0x7fff // Bit mask of PCROP1_STRT field.

	// PCROP1ER: Flash Bank 1 PCROP End address           register
	Flash_PCROP1ER_PCROP1_END_Pos = 0x0        // Position of PCROP1_END field.
	Flash_PCROP1ER_PCROP1_END_Msk = 0x7fff     // Bit mask of PCROP1_END field.
	Flash_PCROP1ER_PCROP_RDP_Pos  = 0x1f       // Position of PCROP_RDP field.
	Flash_PCROP1ER_PCROP_RDP_Msk  = 0x80000000 // Bit mask of PCROP_RDP field.
	Flash_PCROP1ER_PCROP_RDP      = 0x80000000 // Bit PCROP_RDP.

	// WRP1AR: Flash Bank 1 WRP area A address           register
	Flash_WRP1AR_WRP1A_STRT_Pos = 0x0      // Position of WRP1A_STRT field.
	Flash_WRP1AR_WRP1A_STRT_Msk = 0x7f     // Bit mask of WRP1A_STRT field.
	Flash_WRP1AR_WRP1A_END_Pos  = 0x10     // Position of WRP1A_END field.
	Flash_WRP1AR_WRP1A_END_Msk  = 0x7f0000 // Bit mask of WRP1A_END field.

	// WRP1BR: Flash Bank 1 WRP area B address           register
	Flash_WRP1BR_WRP1B_STRT_Pos = 0x0      // Position of WRP1B_STRT field.
	Flash_WRP1BR_WRP1B_STRT_Msk = 0x7f     // Bit mask of WRP1B_STRT field.
	Flash_WRP1BR_WRP1B_END_Pos  = 0x10     // Position of WRP1B_END field.
	Flash_WRP1BR_WRP1B_END_Msk  = 0x7f0000 // Bit mask of WRP1B_END field.

	// SEC1R: securable area bank1 register
	Flash_SEC1R_BOOT_LOCK_Pos = 0x10    // Position of BOOT_LOCK field.
	Flash_SEC1R_BOOT_LOCK_Msk = 0x10000 // Bit mask of BOOT_LOCK field.
	Flash_SEC1R_BOOT_LOCK     = 0x10000 // Bit BOOT_LOCK.
	Flash_SEC1R_SEC_SIZE1_Pos = 0x0     // Position of SEC_SIZE1 field.
	Flash_SEC1R_SEC_SIZE1_Msk = 0xff    // Bit mask of SEC_SIZE1 field.
)

// Bitfields for DBGMCU: Debug support
const (
	// IDCODE: MCU Device ID Code Register
	DBGMCU_IDCODE_DEV_ID_Pos = 0x0        // Position of DEV_ID field.
	DBGMCU_IDCODE_DEV_ID_Msk = 0xffff     // Bit mask of DEV_ID field.
	DBGMCU_IDCODE_REV_ID_Pos = 0x10       // Position of REV_ID field.
	DBGMCU_IDCODE_REV_ID_Msk = 0xffff0000 // Bit mask of REV_ID field.

	// CR: Debug MCU Configuration           Register
	DBGMCU_CR_DBG_SLEEP_Pos   = 0x0  // Position of DBG_SLEEP field.
	DBGMCU_CR_DBG_SLEEP_Msk   = 0x1  // Bit mask of DBG_SLEEP field.
	DBGMCU_CR_DBG_SLEEP       = 0x1  // Bit DBG_SLEEP.
	DBGMCU_CR_DBG_STOP_Pos    = 0x1  // Position of DBG_STOP field.
	DBGMCU_CR_DBG_STOP_Msk    = 0x2  // Bit mask of DBG_STOP field.
	DBGMCU_CR_DBG_STOP        = 0x2  // Bit DBG_STOP.
	DBGMCU_CR_DBG_STANDBY_Pos = 0x2  // Position of DBG_STANDBY field.
	DBGMCU_CR_DBG_STANDBY_Msk = 0x4  // Bit mask of DBG_STANDBY field.
	DBGMCU_CR_DBG_STANDBY     = 0x4  // Bit DBG_STANDBY.
	DBGMCU_CR_TRACE_IOEN_Pos  = 0x5  // Position of TRACE_IOEN field.
	DBGMCU_CR_TRACE_IOEN_Msk  = 0x20 // Bit mask of TRACE_IOEN field.
	DBGMCU_CR_TRACE_IOEN      = 0x20 // Bit TRACE_IOEN.
	DBGMCU_CR_TRACE_MODE_Pos  = 0x6  // Position of TRACE_MODE field.
	DBGMCU_CR_TRACE_MODE_Msk  = 0xc0 // Bit mask of TRACE_MODE field.

	// APB1L_FZ: APB Low Freeze Register 1
	DBGMCU_APB1L_FZ_DBG_TIMER2_STOP_Pos  = 0x0        // Position of DBG_TIMER2_STOP field.
	DBGMCU_APB1L_FZ_DBG_TIMER2_STOP_Msk  = 0x1        // Bit mask of DBG_TIMER2_STOP field.
	DBGMCU_APB1L_FZ_DBG_TIMER2_STOP      = 0x1        // Bit DBG_TIMER2_STOP.
	DBGMCU_APB1L_FZ_DBG_TIM3_STOP_Pos    = 0x1        // Position of DBG_TIM3_STOP field.
	DBGMCU_APB1L_FZ_DBG_TIM3_STOP_Msk    = 0x2        // Bit mask of DBG_TIM3_STOP field.
	DBGMCU_APB1L_FZ_DBG_TIM3_STOP        = 0x2        // Bit DBG_TIM3_STOP.
	DBGMCU_APB1L_FZ_DBG_TIM4_STOP_Pos    = 0x2        // Position of DBG_TIM4_STOP field.
	DBGMCU_APB1L_FZ_DBG_TIM4_STOP_Msk    = 0x4        // Bit mask of DBG_TIM4_STOP field.
	DBGMCU_APB1L_FZ_DBG_TIM4_STOP        = 0x4        // Bit DBG_TIM4_STOP.
	DBGMCU_APB1L_FZ_DBG_TIM5_STOP_Pos    = 0x3        // Position of DBG_TIM5_STOP field.
	DBGMCU_APB1L_FZ_DBG_TIM5_STOP_Msk    = 0x8        // Bit mask of DBG_TIM5_STOP field.
	DBGMCU_APB1L_FZ_DBG_TIM5_STOP        = 0x8        // Bit DBG_TIM5_STOP.
	DBGMCU_APB1L_FZ_DBG_TIMER6_STOP_Pos  = 0x4        // Position of DBG_TIMER6_STOP field.
	DBGMCU_APB1L_FZ_DBG_TIMER6_STOP_Msk  = 0x10       // Bit mask of DBG_TIMER6_STOP field.
	DBGMCU_APB1L_FZ_DBG_TIMER6_STOP      = 0x10       // Bit DBG_TIMER6_STOP.
	DBGMCU_APB1L_FZ_DBG_TIM7_STOP_Pos    = 0x5        // Position of DBG_TIM7_STOP field.
	DBGMCU_APB1L_FZ_DBG_TIM7_STOP_Msk    = 0x20       // Bit mask of DBG_TIM7_STOP field.
	DBGMCU_APB1L_FZ_DBG_TIM7_STOP        = 0x20       // Bit DBG_TIM7_STOP.
	DBGMCU_APB1L_FZ_DBG_RTC_STOP_Pos     = 0xa        // Position of DBG_RTC_STOP field.
	DBGMCU_APB1L_FZ_DBG_RTC_STOP_Msk     = 0x400      // Bit mask of DBG_RTC_STOP field.
	DBGMCU_APB1L_FZ_DBG_RTC_STOP         = 0x400      // Bit DBG_RTC_STOP.
	DBGMCU_APB1L_FZ_DBG_WWDG_STOP_Pos    = 0xb        // Position of DBG_WWDG_STOP field.
	DBGMCU_APB1L_FZ_DBG_WWDG_STOP_Msk    = 0x800      // Bit mask of DBG_WWDG_STOP field.
	DBGMCU_APB1L_FZ_DBG_WWDG_STOP        = 0x800      // Bit DBG_WWDG_STOP.
	DBGMCU_APB1L_FZ_DBG_IWDG_STOP_Pos    = 0xc        // Position of DBG_IWDG_STOP field.
	DBGMCU_APB1L_FZ_DBG_IWDG_STOP_Msk    = 0x1000     // Bit mask of DBG_IWDG_STOP field.
	DBGMCU_APB1L_FZ_DBG_IWDG_STOP        = 0x1000     // Bit DBG_IWDG_STOP.
	DBGMCU_APB1L_FZ_DBG_I2C1_STOP_Pos    = 0x15       // Position of DBG_I2C1_STOP field.
	DBGMCU_APB1L_FZ_DBG_I2C1_STOP_Msk    = 0x200000   // Bit mask of DBG_I2C1_STOP field.
	DBGMCU_APB1L_FZ_DBG_I2C1_STOP        = 0x200000   // Bit DBG_I2C1_STOP.
	DBGMCU_APB1L_FZ_DBG_I2C2_STOP_Pos    = 0x16       // Position of DBG_I2C2_STOP field.
	DBGMCU_APB1L_FZ_DBG_I2C2_STOP_Msk    = 0x400000   // Bit mask of DBG_I2C2_STOP field.
	DBGMCU_APB1L_FZ_DBG_I2C2_STOP        = 0x400000   // Bit DBG_I2C2_STOP.
	DBGMCU_APB1L_FZ_DBG_I2C3_STOP_Pos    = 0x1e       // Position of DBG_I2C3_STOP field.
	DBGMCU_APB1L_FZ_DBG_I2C3_STOP_Msk    = 0x40000000 // Bit mask of DBG_I2C3_STOP field.
	DBGMCU_APB1L_FZ_DBG_I2C3_STOP        = 0x40000000 // Bit DBG_I2C3_STOP.
	DBGMCU_APB1L_FZ_DBG_LPTIMER_STOP_Pos = 0x1f       // Position of DBG_LPTIMER_STOP field.
	DBGMCU_APB1L_FZ_DBG_LPTIMER_STOP_Msk = 0x80000000 // Bit mask of DBG_LPTIMER_STOP field.
	DBGMCU_APB1L_FZ_DBG_LPTIMER_STOP     = 0x80000000 // Bit DBG_LPTIMER_STOP.

	// APB1H_FZ: APB Low Freeze Register 2
	DBGMCU_APB1H_FZ_DBG_I2C4_STOP_Pos = 0x1 // Position of DBG_I2C4_STOP field.
	DBGMCU_APB1H_FZ_DBG_I2C4_STOP_Msk = 0x2 // Bit mask of DBG_I2C4_STOP field.
	DBGMCU_APB1H_FZ_DBG_I2C4_STOP     = 0x2 // Bit DBG_I2C4_STOP.

	// APB2_FZ: APB High Freeze Register
	DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos   = 0xb        // Position of DBG_TIM1_STOP field.
	DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk   = 0x800      // Bit mask of DBG_TIM1_STOP field.
	DBGMCU_APB2_FZ_DBG_TIM1_STOP       = 0x800      // Bit DBG_TIM1_STOP.
	DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos   = 0xd        // Position of DBG_TIM8_STOP field.
	DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk   = 0x2000     // Bit mask of DBG_TIM8_STOP field.
	DBGMCU_APB2_FZ_DBG_TIM8_STOP       = 0x2000     // Bit DBG_TIM8_STOP.
	DBGMCU_APB2_FZ_DBG_TIM15_STOP_Pos  = 0x10       // Position of DBG_TIM15_STOP field.
	DBGMCU_APB2_FZ_DBG_TIM15_STOP_Msk  = 0x10000    // Bit mask of DBG_TIM15_STOP field.
	DBGMCU_APB2_FZ_DBG_TIM15_STOP      = 0x10000    // Bit DBG_TIM15_STOP.
	DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos  = 0x11       // Position of DBG_TIM16_STOP field.
	DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk  = 0x20000    // Bit mask of DBG_TIM16_STOP field.
	DBGMCU_APB2_FZ_DBG_TIM16_STOP      = 0x20000    // Bit DBG_TIM16_STOP.
	DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos  = 0x12       // Position of DBG_TIM17_STOP field.
	DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk  = 0x40000    // Bit mask of DBG_TIM17_STOP field.
	DBGMCU_APB2_FZ_DBG_TIM17_STOP      = 0x40000    // Bit DBG_TIM17_STOP.
	DBGMCU_APB2_FZ_DBG_TIM20_STOP_Pos  = 0x14       // Position of DBG_TIM20_STOP field.
	DBGMCU_APB2_FZ_DBG_TIM20_STOP_Msk  = 0x100000   // Bit mask of DBG_TIM20_STOP field.
	DBGMCU_APB2_FZ_DBG_TIM20_STOP      = 0x100000   // Bit DBG_TIM20_STOP.
	DBGMCU_APB2_FZ_DBG_HRTIM0_STOP_Pos = 0x1a       // Position of DBG_HRTIM0_STOP field.
	DBGMCU_APB2_FZ_DBG_HRTIM0_STOP_Msk = 0x4000000  // Bit mask of DBG_HRTIM0_STOP field.
	DBGMCU_APB2_FZ_DBG_HRTIM0_STOP     = 0x4000000  // Bit DBG_HRTIM0_STOP.
	DBGMCU_APB2_FZ_DBG_HRTIM1_STOP_Pos = 0x1b       // Position of DBG_HRTIM1_STOP field.
	DBGMCU_APB2_FZ_DBG_HRTIM1_STOP_Msk = 0x8000000  // Bit mask of DBG_HRTIM1_STOP field.
	DBGMCU_APB2_FZ_DBG_HRTIM1_STOP     = 0x8000000  // Bit DBG_HRTIM1_STOP.
	DBGMCU_APB2_FZ_DBG_HRTIM2_STOP_Pos = 0x1c       // Position of DBG_HRTIM2_STOP field.
	DBGMCU_APB2_FZ_DBG_HRTIM2_STOP_Msk = 0x10000000 // Bit mask of DBG_HRTIM2_STOP field.
	DBGMCU_APB2_FZ_DBG_HRTIM2_STOP     = 0x10000000 // Bit DBG_HRTIM2_STOP.
	DBGMCU_APB2_FZ_DBG_HRTIM3_STOP_Pos = 0x1d       // Position of DBG_HRTIM3_STOP field.
	DBGMCU_APB2_FZ_DBG_HRTIM3_STOP_Msk = 0x20000000 // Bit mask of DBG_HRTIM3_STOP field.
	DBGMCU_APB2_FZ_DBG_HRTIM3_STOP     = 0x20000000 // Bit DBG_HRTIM3_STOP.
)

// Bitfields for RCC: Reset and clock control
const (
	// CR: Clock control register
	RCC_CR_PLLSYSRDY_Pos = 0x19      // Position of PLLSYSRDY field.
	RCC_CR_PLLSYSRDY_Msk = 0x2000000 // Bit mask of PLLSYSRDY field.
	RCC_CR_PLLSYSRDY     = 0x2000000 // Bit PLLSYSRDY.
	RCC_CR_PLLSYSON_Pos  = 0x18      // Position of PLLSYSON field.
	RCC_CR_PLLSYSON_Msk  = 0x1000000 // Bit mask of PLLSYSON field.
	RCC_CR_PLLSYSON      = 0x1000000 // Bit PLLSYSON.
	RCC_CR_HSECSSON_Pos  = 0x13      // Position of HSECSSON field.
	RCC_CR_HSECSSON_Msk  = 0x80000   // Bit mask of HSECSSON field.
	RCC_CR_HSECSSON      = 0x80000   // Bit HSECSSON.
	RCC_CR_HSEBYP_Pos    = 0x12      // Position of HSEBYP field.
	RCC_CR_HSEBYP_Msk    = 0x40000   // Bit mask of HSEBYP field.
	RCC_CR_HSEBYP        = 0x40000   // Bit HSEBYP.
	RCC_CR_HSERDY_Pos    = 0x11      // Position of HSERDY field.
	RCC_CR_HSERDY_Msk    = 0x20000   // Bit mask of HSERDY field.
	RCC_CR_HSERDY        = 0x20000   // Bit HSERDY.
	RCC_CR_HSEON_Pos     = 0x10      // Position of HSEON field.
	RCC_CR_HSEON_Msk     = 0x10000   // Bit mask of HSEON field.
	RCC_CR_HSEON         = 0x10000   // Bit HSEON.
	RCC_CR_HSIRDY_Pos    = 0xa       // Position of HSIRDY field.
	RCC_CR_HSIRDY_Msk    = 0x400     // Bit mask of HSIRDY field.
	RCC_CR_HSIRDY        = 0x400     // Bit HSIRDY.
	RCC_CR_HSIKERON_Pos  = 0x9       // Position of HSIKERON field.
	RCC_CR_HSIKERON_Msk  = 0x200     // Bit mask of HSIKERON field.
	RCC_CR_HSIKERON      = 0x200     // Bit HSIKERON.
	RCC_CR_HSION_Pos     = 0x8       // Position of HSION field.
	RCC_CR_HSION_Msk     = 0x100     // Bit mask of HSION field.
	RCC_CR_HSION         = 0x100     // Bit HSION.

	// ICSCR: Internal clock sources calibration           register
	RCC_ICSCR_HSICAL0_Pos = 0x10       // Position of HSICAL0 field.
	RCC_ICSCR_HSICAL0_Msk = 0xff0000   // Bit mask of HSICAL0 field.
	RCC_ICSCR_HSITRIM_Pos = 0x18       // Position of HSITRIM field.
	RCC_ICSCR_HSITRIM_Msk = 0x7f000000 // Bit mask of HSITRIM field.

	// CFGR: Clock configuration register
	RCC_CFGR_MCOPRE_Pos = 0x1c       // Position of MCOPRE field.
	RCC_CFGR_MCOPRE_Msk = 0x70000000 // Bit mask of MCOPRE field.
	RCC_CFGR_MCOSEL_Pos = 0x18       // Position of MCOSEL field.
	RCC_CFGR_MCOSEL_Msk = 0xf000000  // Bit mask of MCOSEL field.
	RCC_CFGR_PPRE2_Pos  = 0xb        // Position of PPRE2 field.
	RCC_CFGR_PPRE2_Msk  = 0x3800     // Bit mask of PPRE2 field.
	RCC_CFGR_PPRE1_Pos  = 0x8        // Position of PPRE1 field.
	RCC_CFGR_PPRE1_Msk  = 0x700      // Bit mask of PPRE1 field.
	RCC_CFGR_HPRE_Pos   = 0x4        // Position of HPRE field.
	RCC_CFGR_HPRE_Msk   = 0xf0       // Bit mask of HPRE field.
	RCC_CFGR_SWS_Pos    = 0x2        // Position of SWS field.
	RCC_CFGR_SWS_Msk    = 0xc        // Bit mask of SWS field.
	RCC_CFGR_SW_Pos     = 0x0        // Position of SW field.
	RCC_CFGR_SW_Msk     = 0x3        // Bit mask of SW field.

	// PLLSYSCFGR: PLL configuration register
	RCC_PLLSYSCFGR_PLLSYSPDIV_Pos = 0x1b       // Position of PLLSYSPDIV field.
	RCC_PLLSYSCFGR_PLLSYSPDIV_Msk = 0xf8000000 // Bit mask of PLLSYSPDIV field.
	RCC_PLLSYSCFGR_PLLSYSR_Pos    = 0x19       // Position of PLLSYSR field.
	RCC_PLLSYSCFGR_PLLSYSR_Msk    = 0x6000000  // Bit mask of PLLSYSR field.
	RCC_PLLSYSCFGR_PLLSYSREN_Pos  = 0x18       // Position of PLLSYSREN field.
	RCC_PLLSYSCFGR_PLLSYSREN_Msk  = 0x1000000  // Bit mask of PLLSYSREN field.
	RCC_PLLSYSCFGR_PLLSYSREN      = 0x1000000  // Bit PLLSYSREN.
	RCC_PLLSYSCFGR_PLLSYSQ_Pos    = 0x15       // Position of PLLSYSQ field.
	RCC_PLLSYSCFGR_PLLSYSQ_Msk    = 0x600000   // Bit mask of PLLSYSQ field.
	RCC_PLLSYSCFGR_PLLSYSQEN_Pos  = 0x14       // Position of PLLSYSQEN field.
	RCC_PLLSYSCFGR_PLLSYSQEN_Msk  = 0x100000   // Bit mask of PLLSYSQEN field.
	RCC_PLLSYSCFGR_PLLSYSQEN      = 0x100000   // Bit PLLSYSQEN.
	RCC_PLLSYSCFGR_PLLSYSP_Pos    = 0x11       // Position of PLLSYSP field.
	RCC_PLLSYSCFGR_PLLSYSP_Msk    = 0x20000    // Bit mask of PLLSYSP field.
	RCC_PLLSYSCFGR_PLLSYSP        = 0x20000    // Bit PLLSYSP.
	RCC_PLLSYSCFGR_PLLPEN_Pos     = 0x10       // Position of PLLPEN field.
	RCC_PLLSYSCFGR_PLLPEN_Msk     = 0x10000    // Bit mask of PLLPEN field.
	RCC_PLLSYSCFGR_PLLPEN         = 0x10000    // Bit PLLPEN.
	RCC_PLLSYSCFGR_PLLSYSN_Pos    = 0x8        // Position of PLLSYSN field.
	RCC_PLLSYSCFGR_PLLSYSN_Msk    = 0x7f00     // Bit mask of PLLSYSN field.
	RCC_PLLSYSCFGR_PLLSYSM_Pos    = 0x4        // Position of PLLSYSM field.
	RCC_PLLSYSCFGR_PLLSYSM_Msk    = 0xf0       // Bit mask of PLLSYSM field.
	RCC_PLLSYSCFGR_PLLSRC_Pos     = 0x0        // Position of PLLSRC field.
	RCC_PLLSYSCFGR_PLLSRC_Msk     = 0x3        // Bit mask of PLLSRC field.

	// CIER: Clock interrupt enable           register
	RCC_CIER_LSIRDYIE_Pos    = 0x0   // Position of LSIRDYIE field.
	RCC_CIER_LSIRDYIE_Msk    = 0x1   // Bit mask of LSIRDYIE field.
	RCC_CIER_LSIRDYIE        = 0x1   // Bit LSIRDYIE.
	RCC_CIER_LSERDYIE_Pos    = 0x1   // Position of LSERDYIE field.
	RCC_CIER_LSERDYIE_Msk    = 0x2   // Bit mask of LSERDYIE field.
	RCC_CIER_LSERDYIE        = 0x2   // Bit LSERDYIE.
	RCC_CIER_HSIRDYIE_Pos    = 0x3   // Position of HSIRDYIE field.
	RCC_CIER_HSIRDYIE_Msk    = 0x8   // Bit mask of HSIRDYIE field.
	RCC_CIER_HSIRDYIE        = 0x8   // Bit HSIRDYIE.
	RCC_CIER_HSERDYIE_Pos    = 0x4   // Position of HSERDYIE field.
	RCC_CIER_HSERDYIE_Msk    = 0x10  // Bit mask of HSERDYIE field.
	RCC_CIER_HSERDYIE        = 0x10  // Bit HSERDYIE.
	RCC_CIER_PLLSYSRDYIE_Pos = 0x5   // Position of PLLSYSRDYIE field.
	RCC_CIER_PLLSYSRDYIE_Msk = 0x20  // Bit mask of PLLSYSRDYIE field.
	RCC_CIER_PLLSYSRDYIE     = 0x20  // Bit PLLSYSRDYIE.
	RCC_CIER_LSECSSIE_Pos    = 0x9   // Position of LSECSSIE field.
	RCC_CIER_LSECSSIE_Msk    = 0x200 // Bit mask of LSECSSIE field.
	RCC_CIER_LSECSSIE        = 0x200 // Bit LSECSSIE.
	RCC_CIER_RC48RDYIE_Pos   = 0xa   // Position of RC48RDYIE field.
	RCC_CIER_RC48RDYIE_Msk   = 0x400 // Bit mask of RC48RDYIE field.
	RCC_CIER_RC48RDYIE       = 0x400 // Bit RC48RDYIE.

	// CIFR: Clock interrupt flag register
	RCC_CIFR_LSIRDYF_Pos    = 0x0   // Position of LSIRDYF field.
	RCC_CIFR_LSIRDYF_Msk    = 0x1   // Bit mask of LSIRDYF field.
	RCC_CIFR_LSIRDYF        = 0x1   // Bit LSIRDYF.
	RCC_CIFR_LSERDYF_Pos    = 0x1   // Position of LSERDYF field.
	RCC_CIFR_LSERDYF_Msk    = 0x2   // Bit mask of LSERDYF field.
	RCC_CIFR_LSERDYF        = 0x2   // Bit LSERDYF.
	RCC_CIFR_HSIRDYF_Pos    = 0x3   // Position of HSIRDYF field.
	RCC_CIFR_HSIRDYF_Msk    = 0x8   // Bit mask of HSIRDYF field.
	RCC_CIFR_HSIRDYF        = 0x8   // Bit HSIRDYF.
	RCC_CIFR_HSERDYF_Pos    = 0x4   // Position of HSERDYF field.
	RCC_CIFR_HSERDYF_Msk    = 0x10  // Bit mask of HSERDYF field.
	RCC_CIFR_HSERDYF        = 0x10  // Bit HSERDYF.
	RCC_CIFR_PLLSYSRDYF_Pos = 0x5   // Position of PLLSYSRDYF field.
	RCC_CIFR_PLLSYSRDYF_Msk = 0x20  // Bit mask of PLLSYSRDYF field.
	RCC_CIFR_PLLSYSRDYF     = 0x20  // Bit PLLSYSRDYF.
	RCC_CIFR_HSECSSF_Pos    = 0x8   // Position of HSECSSF field.
	RCC_CIFR_HSECSSF_Msk    = 0x100 // Bit mask of HSECSSF field.
	RCC_CIFR_HSECSSF        = 0x100 // Bit HSECSSF.
	RCC_CIFR_LSECSSF_Pos    = 0x9   // Position of LSECSSF field.
	RCC_CIFR_LSECSSF_Msk    = 0x200 // Bit mask of LSECSSF field.
	RCC_CIFR_LSECSSF        = 0x200 // Bit LSECSSF.
	RCC_CIFR_RC48RDYF_Pos   = 0xa   // Position of RC48RDYF field.
	RCC_CIFR_RC48RDYF_Msk   = 0x400 // Bit mask of RC48RDYF field.
	RCC_CIFR_RC48RDYF       = 0x400 // Bit RC48RDYF.

	// CICR: Clock interrupt clear register
	RCC_CICR_LSIRDYC_Pos    = 0x0   // Position of LSIRDYC field.
	RCC_CICR_LSIRDYC_Msk    = 0x1   // Bit mask of LSIRDYC field.
	RCC_CICR_LSIRDYC        = 0x1   // Bit LSIRDYC.
	RCC_CICR_LSERDYC_Pos    = 0x1   // Position of LSERDYC field.
	RCC_CICR_LSERDYC_Msk    = 0x2   // Bit mask of LSERDYC field.
	RCC_CICR_LSERDYC        = 0x2   // Bit LSERDYC.
	RCC_CICR_HSIRDYC_Pos    = 0x3   // Position of HSIRDYC field.
	RCC_CICR_HSIRDYC_Msk    = 0x8   // Bit mask of HSIRDYC field.
	RCC_CICR_HSIRDYC        = 0x8   // Bit HSIRDYC.
	RCC_CICR_HSERDYC_Pos    = 0x4   // Position of HSERDYC field.
	RCC_CICR_HSERDYC_Msk    = 0x10  // Bit mask of HSERDYC field.
	RCC_CICR_HSERDYC        = 0x10  // Bit HSERDYC.
	RCC_CICR_PLLSYSRDYC_Pos = 0x5   // Position of PLLSYSRDYC field.
	RCC_CICR_PLLSYSRDYC_Msk = 0x20  // Bit mask of PLLSYSRDYC field.
	RCC_CICR_PLLSYSRDYC     = 0x20  // Bit PLLSYSRDYC.
	RCC_CICR_HSECSSC_Pos    = 0x8   // Position of HSECSSC field.
	RCC_CICR_HSECSSC_Msk    = 0x100 // Bit mask of HSECSSC field.
	RCC_CICR_HSECSSC        = 0x100 // Bit HSECSSC.
	RCC_CICR_LSECSSC_Pos    = 0x9   // Position of LSECSSC field.
	RCC_CICR_LSECSSC_Msk    = 0x200 // Bit mask of LSECSSC field.
	RCC_CICR_LSECSSC        = 0x200 // Bit LSECSSC.
	RCC_CICR_RC48RDYC_Pos   = 0xa   // Position of RC48RDYC field.
	RCC_CICR_RC48RDYC_Msk   = 0x400 // Bit mask of RC48RDYC field.
	RCC_CICR_RC48RDYC       = 0x400 // Bit RC48RDYC.

	// AHB1RSTR: AHB1 peripheral reset register
	RCC_AHB1RSTR_DMA1RST_Pos    = 0x0    // Position of DMA1RST field.
	RCC_AHB1RSTR_DMA1RST_Msk    = 0x1    // Bit mask of DMA1RST field.
	RCC_AHB1RSTR_DMA1RST        = 0x1    // Bit DMA1RST.
	RCC_AHB1RSTR_DMA2RST_Pos    = 0x1    // Position of DMA2RST field.
	RCC_AHB1RSTR_DMA2RST_Msk    = 0x2    // Bit mask of DMA2RST field.
	RCC_AHB1RSTR_DMA2RST        = 0x2    // Bit DMA2RST.
	RCC_AHB1RSTR_DMAMUX1RST_Pos = 0x2    // Position of DMAMUX1RST field.
	RCC_AHB1RSTR_DMAMUX1RST_Msk = 0x4    // Bit mask of DMAMUX1RST field.
	RCC_AHB1RSTR_DMAMUX1RST     = 0x4    // Bit DMAMUX1RST.
	RCC_AHB1RSTR_CORDICRST_Pos  = 0x3    // Position of CORDICRST field.
	RCC_AHB1RSTR_CORDICRST_Msk  = 0x8    // Bit mask of CORDICRST field.
	RCC_AHB1RSTR_CORDICRST      = 0x8    // Bit CORDICRST.
	RCC_AHB1RSTR_MATRIXRST_Pos  = 0x4    // Position of MATRIXRST field.
	RCC_AHB1RSTR_MATRIXRST_Msk  = 0x10   // Bit mask of MATRIXRST field.
	RCC_AHB1RSTR_MATRIXRST      = 0x10   // Bit MATRIXRST.
	RCC_AHB1RSTR_FLITFRST__Pos  = 0x8    // Position of FLITFRST_ field.
	RCC_AHB1RSTR_FLITFRST__Msk  = 0x100  // Bit mask of FLITFRST_ field.
	RCC_AHB1RSTR_FLITFRST_      = 0x100  // Bit FLITFRST_.
	RCC_AHB1RSTR_CRCRST_Pos     = 0xc    // Position of CRCRST field.
	RCC_AHB1RSTR_CRCRST_Msk     = 0x1000 // Bit mask of CRCRST field.
	RCC_AHB1RSTR_CRCRST         = 0x1000 // Bit CRCRST.

	// AHB2RSTR: AHB2 peripheral reset register
	RCC_AHB2RSTR_GPIOARST_Pos   = 0x0       // Position of GPIOARST field.
	RCC_AHB2RSTR_GPIOARST_Msk   = 0x1       // Bit mask of GPIOARST field.
	RCC_AHB2RSTR_GPIOARST       = 0x1       // Bit GPIOARST.
	RCC_AHB2RSTR_GPIOBRST_Pos   = 0x1       // Position of GPIOBRST field.
	RCC_AHB2RSTR_GPIOBRST_Msk   = 0x2       // Bit mask of GPIOBRST field.
	RCC_AHB2RSTR_GPIOBRST       = 0x2       // Bit GPIOBRST.
	RCC_AHB2RSTR_GPIOCRST_Pos   = 0x2       // Position of GPIOCRST field.
	RCC_AHB2RSTR_GPIOCRST_Msk   = 0x4       // Bit mask of GPIOCRST field.
	RCC_AHB2RSTR_GPIOCRST       = 0x4       // Bit GPIOCRST.
	RCC_AHB2RSTR_GPIODRST_Pos   = 0x3       // Position of GPIODRST field.
	RCC_AHB2RSTR_GPIODRST_Msk   = 0x8       // Bit mask of GPIODRST field.
	RCC_AHB2RSTR_GPIODRST       = 0x8       // Bit GPIODRST.
	RCC_AHB2RSTR_GPIOERST_Pos   = 0x4       // Position of GPIOERST field.
	RCC_AHB2RSTR_GPIOERST_Msk   = 0x10      // Bit mask of GPIOERST field.
	RCC_AHB2RSTR_GPIOERST       = 0x10      // Bit GPIOERST.
	RCC_AHB2RSTR_GPIOFRST_Pos   = 0x5       // Position of GPIOFRST field.
	RCC_AHB2RSTR_GPIOFRST_Msk   = 0x20      // Bit mask of GPIOFRST field.
	RCC_AHB2RSTR_GPIOFRST       = 0x20      // Bit GPIOFRST.
	RCC_AHB2RSTR_GPIOGRST_Pos   = 0x6       // Position of GPIOGRST field.
	RCC_AHB2RSTR_GPIOGRST_Msk   = 0x40      // Bit mask of GPIOGRST field.
	RCC_AHB2RSTR_GPIOGRST       = 0x40      // Bit GPIOGRST.
	RCC_AHB2RSTR_ADC12RST_Pos   = 0xd       // Position of ADC12RST field.
	RCC_AHB2RSTR_ADC12RST_Msk   = 0x2000    // Bit mask of ADC12RST field.
	RCC_AHB2RSTR_ADC12RST       = 0x2000    // Bit ADC12RST.
	RCC_AHB2RSTR_ADC345RST__Pos = 0xe       // Position of ADC345RST_ field.
	RCC_AHB2RSTR_ADC345RST__Msk = 0x4000    // Bit mask of ADC345RST_ field.
	RCC_AHB2RSTR_ADC345RST_     = 0x4000    // Bit ADC345RST_.
	RCC_AHB2RSTR_DAC1RST__Pos   = 0x10      // Position of DAC1RST_ field.
	RCC_AHB2RSTR_DAC1RST__Msk   = 0x10000   // Bit mask of DAC1RST_ field.
	RCC_AHB2RSTR_DAC1RST_       = 0x10000   // Bit DAC1RST_.
	RCC_AHB2RSTR_DAC2RST_Pos    = 0x11      // Position of DAC2RST field.
	RCC_AHB2RSTR_DAC2RST_Msk    = 0x20000   // Bit mask of DAC2RST field.
	RCC_AHB2RSTR_DAC2RST        = 0x20000   // Bit DAC2RST.
	RCC_AHB2RSTR_DAC3RST_Pos    = 0x12      // Position of DAC3RST field.
	RCC_AHB2RSTR_DAC3RST_Msk    = 0x40000   // Bit mask of DAC3RST field.
	RCC_AHB2RSTR_DAC3RST        = 0x40000   // Bit DAC3RST.
	RCC_AHB2RSTR_DAC4RST_Pos    = 0x13      // Position of DAC4RST field.
	RCC_AHB2RSTR_DAC4RST_Msk    = 0x80000   // Bit mask of DAC4RST field.
	RCC_AHB2RSTR_DAC4RST        = 0x80000   // Bit DAC4RST.
	RCC_AHB2RSTR_CRYPTRST_Pos   = 0x18      // Position of CRYPTRST field.
	RCC_AHB2RSTR_CRYPTRST_Msk   = 0x1000000 // Bit mask of CRYPTRST field.
	RCC_AHB2RSTR_CRYPTRST       = 0x1000000 // Bit CRYPTRST.
	RCC_AHB2RSTR_RNGRST_Pos     = 0x1a      // Position of RNGRST field.
	RCC_AHB2RSTR_RNGRST_Msk     = 0x4000000 // Bit mask of RNGRST field.
	RCC_AHB2RSTR_RNGRST         = 0x4000000 // Bit RNGRST.

	// AHB3RSTR: AHB3 peripheral reset register
	RCC_AHB3RSTR_FMCRST_Pos      = 0x0   // Position of FMCRST field.
	RCC_AHB3RSTR_FMCRST_Msk      = 0x1   // Bit mask of FMCRST field.
	RCC_AHB3RSTR_FMCRST          = 0x1   // Bit FMCRST.
	RCC_AHB3RSTR_QUADSPI1RST_Pos = 0x8   // Position of QUADSPI1RST field.
	RCC_AHB3RSTR_QUADSPI1RST_Msk = 0x100 // Bit mask of QUADSPI1RST field.
	RCC_AHB3RSTR_QUADSPI1RST     = 0x100 // Bit QUADSPI1RST.

	// APB1RSTR1: APB1 peripheral reset register           1
	RCC_APB1RSTR1_LPTIM1RST_Pos = 0x1f       // Position of LPTIM1RST field.
	RCC_APB1RSTR1_LPTIM1RST_Msk = 0x80000000 // Bit mask of LPTIM1RST field.
	RCC_APB1RSTR1_LPTIM1RST     = 0x80000000 // Bit LPTIM1RST.
	RCC_APB1RSTR1_I2C3_Pos      = 0x1e       // Position of I2C3 field.
	RCC_APB1RSTR1_I2C3_Msk      = 0x40000000 // Bit mask of I2C3 field.
	RCC_APB1RSTR1_I2C3          = 0x40000000 // Bit I2C3.
	RCC_APB1RSTR1_PWRRST_Pos    = 0x1c       // Position of PWRRST field.
	RCC_APB1RSTR1_PWRRST_Msk    = 0x10000000 // Bit mask of PWRRST field.
	RCC_APB1RSTR1_PWRRST        = 0x10000000 // Bit PWRRST.
	RCC_APB1RSTR1_FDCANRST_Pos  = 0x19       // Position of FDCANRST field.
	RCC_APB1RSTR1_FDCANRST_Msk  = 0x2000000  // Bit mask of FDCANRST field.
	RCC_APB1RSTR1_FDCANRST      = 0x2000000  // Bit FDCANRST.
	RCC_APB1RSTR1_USBDRST_Pos   = 0x17       // Position of USBDRST field.
	RCC_APB1RSTR1_USBDRST_Msk   = 0x800000   // Bit mask of USBDRST field.
	RCC_APB1RSTR1_USBDRST       = 0x800000   // Bit USBDRST.
	RCC_APB1RSTR1_I2C2RST_Pos   = 0x16       // Position of I2C2RST field.
	RCC_APB1RSTR1_I2C2RST_Msk   = 0x400000   // Bit mask of I2C2RST field.
	RCC_APB1RSTR1_I2C2RST       = 0x400000   // Bit I2C2RST.
	RCC_APB1RSTR1_I2C1RST_Pos   = 0x15       // Position of I2C1RST field.
	RCC_APB1RSTR1_I2C1RST_Msk   = 0x200000   // Bit mask of I2C1RST field.
	RCC_APB1RSTR1_I2C1RST       = 0x200000   // Bit I2C1RST.
	RCC_APB1RSTR1_UART5RST_Pos  = 0x14       // Position of UART5RST field.
	RCC_APB1RSTR1_UART5RST_Msk  = 0x100000   // Bit mask of UART5RST field.
	RCC_APB1RSTR1_UART5RST      = 0x100000   // Bit UART5RST.
	RCC_APB1RSTR1_UART4RST_Pos  = 0x13       // Position of UART4RST field.
	RCC_APB1RSTR1_UART4RST_Msk  = 0x80000    // Bit mask of UART4RST field.
	RCC_APB1RSTR1_UART4RST      = 0x80000    // Bit UART4RST.
	RCC_APB1RSTR1_USART3RST_Pos = 0x12       // Position of USART3RST field.
	RCC_APB1RSTR1_USART3RST_Msk = 0x40000    // Bit mask of USART3RST field.
	RCC_APB1RSTR1_USART3RST     = 0x40000    // Bit USART3RST.
	RCC_APB1RSTR1_USART2RST_Pos = 0x11       // Position of USART2RST field.
	RCC_APB1RSTR1_USART2RST_Msk = 0x20000    // Bit mask of USART2RST field.
	RCC_APB1RSTR1_USART2RST     = 0x20000    // Bit USART2RST.
	RCC_APB1RSTR1_SPI3RST_Pos   = 0xf        // Position of SPI3RST field.
	RCC_APB1RSTR1_SPI3RST_Msk   = 0x8000     // Bit mask of SPI3RST field.
	RCC_APB1RSTR1_SPI3RST       = 0x8000     // Bit SPI3RST.
	RCC_APB1RSTR1_SPI2RST_Pos   = 0xe        // Position of SPI2RST field.
	RCC_APB1RSTR1_SPI2RST_Msk   = 0x4000     // Bit mask of SPI2RST field.
	RCC_APB1RSTR1_SPI2RST       = 0x4000     // Bit SPI2RST.
	RCC_APB1RSTR1_CRSRST_Pos    = 0x8        // Position of CRSRST field.
	RCC_APB1RSTR1_CRSRST_Msk    = 0x100      // Bit mask of CRSRST field.
	RCC_APB1RSTR1_CRSRST        = 0x100      // Bit CRSRST.
	RCC_APB1RSTR1_TIM7RST_Pos   = 0x5        // Position of TIM7RST field.
	RCC_APB1RSTR1_TIM7RST_Msk   = 0x20       // Bit mask of TIM7RST field.
	RCC_APB1RSTR1_TIM7RST       = 0x20       // Bit TIM7RST.
	RCC_APB1RSTR1_TIM6RST_Pos   = 0x4        // Position of TIM6RST field.
	RCC_APB1RSTR1_TIM6RST_Msk   = 0x10       // Bit mask of TIM6RST field.
	RCC_APB1RSTR1_TIM6RST       = 0x10       // Bit TIM6RST.
	RCC_APB1RSTR1_TIM5RST_Pos   = 0x3        // Position of TIM5RST field.
	RCC_APB1RSTR1_TIM5RST_Msk   = 0x8        // Bit mask of TIM5RST field.
	RCC_APB1RSTR1_TIM5RST       = 0x8        // Bit TIM5RST.
	RCC_APB1RSTR1_TIM4RST_Pos   = 0x2        // Position of TIM4RST field.
	RCC_APB1RSTR1_TIM4RST_Msk   = 0x4        // Bit mask of TIM4RST field.
	RCC_APB1RSTR1_TIM4RST       = 0x4        // Bit TIM4RST.
	RCC_APB1RSTR1_TIM3RST_Pos   = 0x1        // Position of TIM3RST field.
	RCC_APB1RSTR1_TIM3RST_Msk   = 0x2        // Bit mask of TIM3RST field.
	RCC_APB1RSTR1_TIM3RST       = 0x2        // Bit TIM3RST.
	RCC_APB1RSTR1_TIM2RST_Pos   = 0x0        // Position of TIM2RST field.
	RCC_APB1RSTR1_TIM2RST_Msk   = 0x1        // Bit mask of TIM2RST field.
	RCC_APB1RSTR1_TIM2RST       = 0x1        // Bit TIM2RST.

	// APB1RSTR2: APB1 peripheral reset register           2
	RCC_APB1RSTR2_LPUART1RST_Pos = 0x0   // Position of LPUART1RST field.
	RCC_APB1RSTR2_LPUART1RST_Msk = 0x1   // Bit mask of LPUART1RST field.
	RCC_APB1RSTR2_LPUART1RST     = 0x1   // Bit LPUART1RST.
	RCC_APB1RSTR2_I2C4RST_Pos    = 0x1   // Position of I2C4RST field.
	RCC_APB1RSTR2_I2C4RST_Msk    = 0x2   // Bit mask of I2C4RST field.
	RCC_APB1RSTR2_I2C4RST        = 0x2   // Bit I2C4RST.
	RCC_APB1RSTR2_USBPDRST_Pos   = 0x8   // Position of USBPDRST field.
	RCC_APB1RSTR2_USBPDRST_Msk   = 0x100 // Bit mask of USBPDRST field.
	RCC_APB1RSTR2_USBPDRST       = 0x100 // Bit USBPDRST.

	// APB2RSTR: APB2 peripheral reset register
	RCC_APB2RSTR_SYSCFGRST_Pos = 0x0       // Position of SYSCFGRST field.
	RCC_APB2RSTR_SYSCFGRST_Msk = 0x1       // Bit mask of SYSCFGRST field.
	RCC_APB2RSTR_SYSCFGRST     = 0x1       // Bit SYSCFGRST.
	RCC_APB2RSTR_TIM1RST_Pos   = 0xb       // Position of TIM1RST field.
	RCC_APB2RSTR_TIM1RST_Msk   = 0x800     // Bit mask of TIM1RST field.
	RCC_APB2RSTR_TIM1RST       = 0x800     // Bit TIM1RST.
	RCC_APB2RSTR_SPI1RST_Pos   = 0xc       // Position of SPI1RST field.
	RCC_APB2RSTR_SPI1RST_Msk   = 0x1000    // Bit mask of SPI1RST field.
	RCC_APB2RSTR_SPI1RST       = 0x1000    // Bit SPI1RST.
	RCC_APB2RSTR_TIM8RST_Pos   = 0xd       // Position of TIM8RST field.
	RCC_APB2RSTR_TIM8RST_Msk   = 0x2000    // Bit mask of TIM8RST field.
	RCC_APB2RSTR_TIM8RST       = 0x2000    // Bit TIM8RST.
	RCC_APB2RSTR_USART1RST_Pos = 0xe       // Position of USART1RST field.
	RCC_APB2RSTR_USART1RST_Msk = 0x4000    // Bit mask of USART1RST field.
	RCC_APB2RSTR_USART1RST     = 0x4000    // Bit USART1RST.
	RCC_APB2RSTR_SPI4RST_Pos   = 0xf       // Position of SPI4RST field.
	RCC_APB2RSTR_SPI4RST_Msk   = 0x8000    // Bit mask of SPI4RST field.
	RCC_APB2RSTR_SPI4RST       = 0x8000    // Bit SPI4RST.
	RCC_APB2RSTR_TIM15RST_Pos  = 0x10      // Position of TIM15RST field.
	RCC_APB2RSTR_TIM15RST_Msk  = 0x10000   // Bit mask of TIM15RST field.
	RCC_APB2RSTR_TIM15RST      = 0x10000   // Bit TIM15RST.
	RCC_APB2RSTR_TIM16RST_Pos  = 0x11      // Position of TIM16RST field.
	RCC_APB2RSTR_TIM16RST_Msk  = 0x20000   // Bit mask of TIM16RST field.
	RCC_APB2RSTR_TIM16RST      = 0x20000   // Bit TIM16RST.
	RCC_APB2RSTR_TIM17RST_Pos  = 0x12      // Position of TIM17RST field.
	RCC_APB2RSTR_TIM17RST_Msk  = 0x40000   // Bit mask of TIM17RST field.
	RCC_APB2RSTR_TIM17RST      = 0x40000   // Bit TIM17RST.
	RCC_APB2RSTR_TIM20RST_Pos  = 0x14      // Position of TIM20RST field.
	RCC_APB2RSTR_TIM20RST_Msk  = 0x100000  // Bit mask of TIM20RST field.
	RCC_APB2RSTR_TIM20RST      = 0x100000  // Bit TIM20RST.
	RCC_APB2RSTR_SAI1RST_Pos   = 0x15      // Position of SAI1RST field.
	RCC_APB2RSTR_SAI1RST_Msk   = 0x200000  // Bit mask of SAI1RST field.
	RCC_APB2RSTR_SAI1RST       = 0x200000  // Bit SAI1RST.
	RCC_APB2RSTR_HRTIM1RST_Pos = 0x1a      // Position of HRTIM1RST field.
	RCC_APB2RSTR_HRTIM1RST_Msk = 0x4000000 // Bit mask of HRTIM1RST field.
	RCC_APB2RSTR_HRTIM1RST     = 0x4000000 // Bit HRTIM1RST.

	// AHB1ENR: AHB1 peripheral clock enable           register
	RCC_AHB1ENR_DMA1EN_Pos   = 0x0    // Position of DMA1EN field.
	RCC_AHB1ENR_DMA1EN_Msk   = 0x1    // Bit mask of DMA1EN field.
	RCC_AHB1ENR_DMA1EN       = 0x1    // Bit DMA1EN.
	RCC_AHB1ENR_DMA2EN_Pos   = 0x1    // Position of DMA2EN field.
	RCC_AHB1ENR_DMA2EN_Msk   = 0x2    // Bit mask of DMA2EN field.
	RCC_AHB1ENR_DMA2EN       = 0x2    // Bit DMA2EN.
	RCC_AHB1ENR_DMAMUXEN_Pos = 0x2    // Position of DMAMUXEN field.
	RCC_AHB1ENR_DMAMUXEN_Msk = 0x4    // Bit mask of DMAMUXEN field.
	RCC_AHB1ENR_DMAMUXEN     = 0x4    // Bit DMAMUXEN.
	RCC_AHB1ENR_CORDICEN_Pos = 0x3    // Position of CORDICEN field.
	RCC_AHB1ENR_CORDICEN_Msk = 0x8    // Bit mask of CORDICEN field.
	RCC_AHB1ENR_CORDICEN     = 0x8    // Bit CORDICEN.
	RCC_AHB1ENR_FMACEN_Pos   = 0x4    // Position of FMACEN field.
	RCC_AHB1ENR_FMACEN_Msk   = 0x10   // Bit mask of FMACEN field.
	RCC_AHB1ENR_FMACEN       = 0x10   // Bit FMACEN.
	RCC_AHB1ENR_FLITFEN_Pos  = 0x8    // Position of FLITFEN field.
	RCC_AHB1ENR_FLITFEN_Msk  = 0x100  // Bit mask of FLITFEN field.
	RCC_AHB1ENR_FLITFEN      = 0x100  // Bit FLITFEN.
	RCC_AHB1ENR_CRCEN_Pos    = 0xc    // Position of CRCEN field.
	RCC_AHB1ENR_CRCEN_Msk    = 0x1000 // Bit mask of CRCEN field.
	RCC_AHB1ENR_CRCEN        = 0x1000 // Bit CRCEN.

	// AHB2ENR: AHB2 peripheral clock enable           register
	RCC_AHB2ENR_GPIOAEN_Pos  = 0x0       // Position of GPIOAEN field.
	RCC_AHB2ENR_GPIOAEN_Msk  = 0x1       // Bit mask of GPIOAEN field.
	RCC_AHB2ENR_GPIOAEN      = 0x1       // Bit GPIOAEN.
	RCC_AHB2ENR_GPIOBEN_Pos  = 0x1       // Position of GPIOBEN field.
	RCC_AHB2ENR_GPIOBEN_Msk  = 0x2       // Bit mask of GPIOBEN field.
	RCC_AHB2ENR_GPIOBEN      = 0x2       // Bit GPIOBEN.
	RCC_AHB2ENR_GPIOCEN_Pos  = 0x2       // Position of GPIOCEN field.
	RCC_AHB2ENR_GPIOCEN_Msk  = 0x4       // Bit mask of GPIOCEN field.
	RCC_AHB2ENR_GPIOCEN      = 0x4       // Bit GPIOCEN.
	RCC_AHB2ENR_GPIODEN_Pos  = 0x3       // Position of GPIODEN field.
	RCC_AHB2ENR_GPIODEN_Msk  = 0x8       // Bit mask of GPIODEN field.
	RCC_AHB2ENR_GPIODEN      = 0x8       // Bit GPIODEN.
	RCC_AHB2ENR_GPIOEEN_Pos  = 0x4       // Position of GPIOEEN field.
	RCC_AHB2ENR_GPIOEEN_Msk  = 0x10      // Bit mask of GPIOEEN field.
	RCC_AHB2ENR_GPIOEEN      = 0x10      // Bit GPIOEEN.
	RCC_AHB2ENR_GPIOFEN_Pos  = 0x5       // Position of GPIOFEN field.
	RCC_AHB2ENR_GPIOFEN_Msk  = 0x20      // Bit mask of GPIOFEN field.
	RCC_AHB2ENR_GPIOFEN      = 0x20      // Bit GPIOFEN.
	RCC_AHB2ENR_GPIOGEN_Pos  = 0x6       // Position of GPIOGEN field.
	RCC_AHB2ENR_GPIOGEN_Msk  = 0x40      // Bit mask of GPIOGEN field.
	RCC_AHB2ENR_GPIOGEN      = 0x40      // Bit GPIOGEN.
	RCC_AHB2ENR_ADC12EN_Pos  = 0xd       // Position of ADC12EN field.
	RCC_AHB2ENR_ADC12EN_Msk  = 0x2000    // Bit mask of ADC12EN field.
	RCC_AHB2ENR_ADC12EN      = 0x2000    // Bit ADC12EN.
	RCC_AHB2ENR_ADC345EN_Pos = 0xe       // Position of ADC345EN field.
	RCC_AHB2ENR_ADC345EN_Msk = 0x4000    // Bit mask of ADC345EN field.
	RCC_AHB2ENR_ADC345EN     = 0x4000    // Bit ADC345EN.
	RCC_AHB2ENR_DAC1_Pos     = 0x10      // Position of DAC1 field.
	RCC_AHB2ENR_DAC1_Msk     = 0x10000   // Bit mask of DAC1 field.
	RCC_AHB2ENR_DAC1         = 0x10000   // Bit DAC1.
	RCC_AHB2ENR_DAC2_Pos     = 0x11      // Position of DAC2 field.
	RCC_AHB2ENR_DAC2_Msk     = 0x20000   // Bit mask of DAC2 field.
	RCC_AHB2ENR_DAC2         = 0x20000   // Bit DAC2.
	RCC_AHB2ENR_DAC3_Pos     = 0x12      // Position of DAC3 field.
	RCC_AHB2ENR_DAC3_Msk     = 0x40000   // Bit mask of DAC3 field.
	RCC_AHB2ENR_DAC3         = 0x40000   // Bit DAC3.
	RCC_AHB2ENR_DAC4_Pos     = 0x13      // Position of DAC4 field.
	RCC_AHB2ENR_DAC4_Msk     = 0x80000   // Bit mask of DAC4 field.
	RCC_AHB2ENR_DAC4         = 0x80000   // Bit DAC4.
	RCC_AHB2ENR_CRYPTEN_Pos  = 0x18      // Position of CRYPTEN field.
	RCC_AHB2ENR_CRYPTEN_Msk  = 0x1000000 // Bit mask of CRYPTEN field.
	RCC_AHB2ENR_CRYPTEN      = 0x1000000 // Bit CRYPTEN.
	RCC_AHB2ENR_RNGEN_Pos    = 0x1a      // Position of RNGEN field.
	RCC_AHB2ENR_RNGEN_Msk    = 0x4000000 // Bit mask of RNGEN field.
	RCC_AHB2ENR_RNGEN        = 0x4000000 // Bit RNGEN.

	// AHB3ENR: AHB3 peripheral clock enable           register
	RCC_AHB3ENR_FMCEN_Pos      = 0x0   // Position of FMCEN field.
	RCC_AHB3ENR_FMCEN_Msk      = 0x1   // Bit mask of FMCEN field.
	RCC_AHB3ENR_FMCEN          = 0x1   // Bit FMCEN.
	RCC_AHB3ENR_QUADSPI1EN_Pos = 0x8   // Position of QUADSPI1EN field.
	RCC_AHB3ENR_QUADSPI1EN_Msk = 0x100 // Bit mask of QUADSPI1EN field.
	RCC_AHB3ENR_QUADSPI1EN     = 0x100 // Bit QUADSPI1EN.

	// APB1ENR1: APB1ENR1
	RCC_APB1ENR1_TIM2EN_Pos   = 0x0        // Position of TIM2EN field.
	RCC_APB1ENR1_TIM2EN_Msk   = 0x1        // Bit mask of TIM2EN field.
	RCC_APB1ENR1_TIM2EN       = 0x1        // Bit TIM2EN.
	RCC_APB1ENR1_TIM3EN_Pos   = 0x1        // Position of TIM3EN field.
	RCC_APB1ENR1_TIM3EN_Msk   = 0x2        // Bit mask of TIM3EN field.
	RCC_APB1ENR1_TIM3EN       = 0x2        // Bit TIM3EN.
	RCC_APB1ENR1_TIM4EN_Pos   = 0x2        // Position of TIM4EN field.
	RCC_APB1ENR1_TIM4EN_Msk   = 0x4        // Bit mask of TIM4EN field.
	RCC_APB1ENR1_TIM4EN       = 0x4        // Bit TIM4EN.
	RCC_APB1ENR1_TIM5EN_Pos   = 0x3        // Position of TIM5EN field.
	RCC_APB1ENR1_TIM5EN_Msk   = 0x8        // Bit mask of TIM5EN field.
	RCC_APB1ENR1_TIM5EN       = 0x8        // Bit TIM5EN.
	RCC_APB1ENR1_TIM6EN_Pos   = 0x4        // Position of TIM6EN field.
	RCC_APB1ENR1_TIM6EN_Msk   = 0x10       // Bit mask of TIM6EN field.
	RCC_APB1ENR1_TIM6EN       = 0x10       // Bit TIM6EN.
	RCC_APB1ENR1_TIM7EN_Pos   = 0x5        // Position of TIM7EN field.
	RCC_APB1ENR1_TIM7EN_Msk   = 0x20       // Bit mask of TIM7EN field.
	RCC_APB1ENR1_TIM7EN       = 0x20       // Bit TIM7EN.
	RCC_APB1ENR1_CRSEN_Pos    = 0x8        // Position of CRSEN field.
	RCC_APB1ENR1_CRSEN_Msk    = 0x100      // Bit mask of CRSEN field.
	RCC_APB1ENR1_CRSEN        = 0x100      // Bit CRSEN.
	RCC_APB1ENR1_RTCAPBEN_Pos = 0xa        // Position of RTCAPBEN field.
	RCC_APB1ENR1_RTCAPBEN_Msk = 0x400      // Bit mask of RTCAPBEN field.
	RCC_APB1ENR1_RTCAPBEN     = 0x400      // Bit RTCAPBEN.
	RCC_APB1ENR1_WWDGEN_Pos   = 0xb        // Position of WWDGEN field.
	RCC_APB1ENR1_WWDGEN_Msk   = 0x800      // Bit mask of WWDGEN field.
	RCC_APB1ENR1_WWDGEN       = 0x800      // Bit WWDGEN.
	RCC_APB1ENR1_SPI2EN_Pos   = 0xe        // Position of SPI2EN field.
	RCC_APB1ENR1_SPI2EN_Msk   = 0x4000     // Bit mask of SPI2EN field.
	RCC_APB1ENR1_SPI2EN       = 0x4000     // Bit SPI2EN.
	RCC_APB1ENR1_SP3EN_Pos    = 0xf        // Position of SP3EN field.
	RCC_APB1ENR1_SP3EN_Msk    = 0x8000     // Bit mask of SP3EN field.
	RCC_APB1ENR1_SP3EN        = 0x8000     // Bit SP3EN.
	RCC_APB1ENR1_USART2EN_Pos = 0x11       // Position of USART2EN field.
	RCC_APB1ENR1_USART2EN_Msk = 0x20000    // Bit mask of USART2EN field.
	RCC_APB1ENR1_USART2EN     = 0x20000    // Bit USART2EN.
	RCC_APB1ENR1_USART3EN_Pos = 0x12       // Position of USART3EN field.
	RCC_APB1ENR1_USART3EN_Msk = 0x40000    // Bit mask of USART3EN field.
	RCC_APB1ENR1_USART3EN     = 0x40000    // Bit USART3EN.
	RCC_APB1ENR1_UART4EN_Pos  = 0x13       // Position of UART4EN field.
	RCC_APB1ENR1_UART4EN_Msk  = 0x80000    // Bit mask of UART4EN field.
	RCC_APB1ENR1_UART4EN      = 0x80000    // Bit UART4EN.
	RCC_APB1ENR1_UART5EN_Pos  = 0x14       // Position of UART5EN field.
	RCC_APB1ENR1_UART5EN_Msk  = 0x100000   // Bit mask of UART5EN field.
	RCC_APB1ENR1_UART5EN      = 0x100000   // Bit UART5EN.
	RCC_APB1ENR1_I2C1EN_Pos   = 0x15       // Position of I2C1EN field.
	RCC_APB1ENR1_I2C1EN_Msk   = 0x200000   // Bit mask of I2C1EN field.
	RCC_APB1ENR1_I2C1EN       = 0x200000   // Bit I2C1EN.
	RCC_APB1ENR1_I2C2EN_Pos   = 0x16       // Position of I2C2EN field.
	RCC_APB1ENR1_I2C2EN_Msk   = 0x400000   // Bit mask of I2C2EN field.
	RCC_APB1ENR1_I2C2EN       = 0x400000   // Bit I2C2EN.
	RCC_APB1ENR1_USBDEN_Pos   = 0x17       // Position of USBDEN field.
	RCC_APB1ENR1_USBDEN_Msk   = 0x800000   // Bit mask of USBDEN field.
	RCC_APB1ENR1_USBDEN       = 0x800000   // Bit USBDEN.
	RCC_APB1ENR1_FDCANEN_Pos  = 0x19       // Position of FDCANEN field.
	RCC_APB1ENR1_FDCANEN_Msk  = 0x2000000  // Bit mask of FDCANEN field.
	RCC_APB1ENR1_FDCANEN      = 0x2000000  // Bit FDCANEN.
	RCC_APB1ENR1_PWREN_Pos    = 0x1c       // Position of PWREN field.
	RCC_APB1ENR1_PWREN_Msk    = 0x10000000 // Bit mask of PWREN field.
	RCC_APB1ENR1_PWREN        = 0x10000000 // Bit PWREN.
	RCC_APB1ENR1_I2C3_Pos     = 0x1e       // Position of I2C3 field.
	RCC_APB1ENR1_I2C3_Msk     = 0x40000000 // Bit mask of I2C3 field.
	RCC_APB1ENR1_I2C3         = 0x40000000 // Bit I2C3.
	RCC_APB1ENR1_LPTIM1EN_Pos = 0x1f       // Position of LPTIM1EN field.
	RCC_APB1ENR1_LPTIM1EN_Msk = 0x80000000 // Bit mask of LPTIM1EN field.
	RCC_APB1ENR1_LPTIM1EN     = 0x80000000 // Bit LPTIM1EN.

	// APB1ENR2: APB1 peripheral clock enable register           2
	RCC_APB1ENR2_LPUART1EN_Pos = 0x0   // Position of LPUART1EN field.
	RCC_APB1ENR2_LPUART1EN_Msk = 0x1   // Bit mask of LPUART1EN field.
	RCC_APB1ENR2_LPUART1EN     = 0x1   // Bit LPUART1EN.
	RCC_APB1ENR2_I2C4EN_Pos    = 0x1   // Position of I2C4EN field.
	RCC_APB1ENR2_I2C4EN_Msk    = 0x2   // Bit mask of I2C4EN field.
	RCC_APB1ENR2_I2C4EN        = 0x2   // Bit I2C4EN.
	RCC_APB1ENR2_USBPDEN_Pos   = 0x8   // Position of USBPDEN field.
	RCC_APB1ENR2_USBPDEN_Msk   = 0x100 // Bit mask of USBPDEN field.
	RCC_APB1ENR2_USBPDEN       = 0x100 // Bit USBPDEN.

	// APB2ENR: APB2ENR
	RCC_APB2ENR_SYSCFGEN_Pos  = 0x0       // Position of SYSCFGEN field.
	RCC_APB2ENR_SYSCFGEN_Msk  = 0x1       // Bit mask of SYSCFGEN field.
	RCC_APB2ENR_SYSCFGEN      = 0x1       // Bit SYSCFGEN.
	RCC_APB2ENR_TIM1EN_Pos    = 0xb       // Position of TIM1EN field.
	RCC_APB2ENR_TIM1EN_Msk    = 0x800     // Bit mask of TIM1EN field.
	RCC_APB2ENR_TIM1EN        = 0x800     // Bit TIM1EN.
	RCC_APB2ENR_SPI1EN_Pos    = 0xc       // Position of SPI1EN field.
	RCC_APB2ENR_SPI1EN_Msk    = 0x1000    // Bit mask of SPI1EN field.
	RCC_APB2ENR_SPI1EN        = 0x1000    // Bit SPI1EN.
	RCC_APB2ENR_TIM8EN_Pos    = 0xd       // Position of TIM8EN field.
	RCC_APB2ENR_TIM8EN_Msk    = 0x2000    // Bit mask of TIM8EN field.
	RCC_APB2ENR_TIM8EN        = 0x2000    // Bit TIM8EN.
	RCC_APB2ENR_USART1EN_Pos  = 0xe       // Position of USART1EN field.
	RCC_APB2ENR_USART1EN_Msk  = 0x4000    // Bit mask of USART1EN field.
	RCC_APB2ENR_USART1EN      = 0x4000    // Bit USART1EN.
	RCC_APB2ENR_SPI4EN_Pos    = 0xf       // Position of SPI4EN field.
	RCC_APB2ENR_SPI4EN_Msk    = 0x8000    // Bit mask of SPI4EN field.
	RCC_APB2ENR_SPI4EN        = 0x8000    // Bit SPI4EN.
	RCC_APB2ENR_TIM15EN_Pos   = 0x10      // Position of TIM15EN field.
	RCC_APB2ENR_TIM15EN_Msk   = 0x10000   // Bit mask of TIM15EN field.
	RCC_APB2ENR_TIM15EN       = 0x10000   // Bit TIM15EN.
	RCC_APB2ENR_TIM16EN_Pos   = 0x11      // Position of TIM16EN field.
	RCC_APB2ENR_TIM16EN_Msk   = 0x20000   // Bit mask of TIM16EN field.
	RCC_APB2ENR_TIM16EN       = 0x20000   // Bit TIM16EN.
	RCC_APB2ENR_TIM17EN_Pos   = 0x12      // Position of TIM17EN field.
	RCC_APB2ENR_TIM17EN_Msk   = 0x40000   // Bit mask of TIM17EN field.
	RCC_APB2ENR_TIM17EN       = 0x40000   // Bit TIM17EN.
	RCC_APB2ENR_TIM20EN_Pos   = 0x14      // Position of TIM20EN field.
	RCC_APB2ENR_TIM20EN_Msk   = 0x100000  // Bit mask of TIM20EN field.
	RCC_APB2ENR_TIM20EN       = 0x100000  // Bit TIM20EN.
	RCC_APB2ENR_SAI1EN_Pos    = 0x15      // Position of SAI1EN field.
	RCC_APB2ENR_SAI1EN_Msk    = 0x200000  // Bit mask of SAI1EN field.
	RCC_APB2ENR_SAI1EN        = 0x200000  // Bit SAI1EN.
	RCC_APB2ENR_HRTIMEREN_Pos = 0x1a      // Position of HRTIMEREN field.
	RCC_APB2ENR_HRTIMEREN_Msk = 0x4000000 // Bit mask of HRTIMEREN field.
	RCC_APB2ENR_HRTIMEREN     = 0x4000000 // Bit HRTIMEREN.

	// AHB1SMENR: AHB1 peripheral clocks enable in Sleep and           Stop modes register
	RCC_AHB1SMENR_DMA1SMEN_Pos    = 0x0    // Position of DMA1SMEN field.
	RCC_AHB1SMENR_DMA1SMEN_Msk    = 0x1    // Bit mask of DMA1SMEN field.
	RCC_AHB1SMENR_DMA1SMEN        = 0x1    // Bit DMA1SMEN.
	RCC_AHB1SMENR_DMA2SMEN_Pos    = 0x1    // Position of DMA2SMEN field.
	RCC_AHB1SMENR_DMA2SMEN_Msk    = 0x2    // Bit mask of DMA2SMEN field.
	RCC_AHB1SMENR_DMA2SMEN        = 0x2    // Bit DMA2SMEN.
	RCC_AHB1SMENR_DMAMUX1SMEN_Pos = 0x2    // Position of DMAMUX1SMEN field.
	RCC_AHB1SMENR_DMAMUX1SMEN_Msk = 0x4    // Bit mask of DMAMUX1SMEN field.
	RCC_AHB1SMENR_DMAMUX1SMEN     = 0x4    // Bit DMAMUX1SMEN.
	RCC_AHB1SMENR_CORDICSMEN_Pos  = 0x3    // Position of CORDICSMEN field.
	RCC_AHB1SMENR_CORDICSMEN_Msk  = 0x8    // Bit mask of CORDICSMEN field.
	RCC_AHB1SMENR_CORDICSMEN      = 0x8    // Bit CORDICSMEN.
	RCC_AHB1SMENR_FLASHSMEN_Pos   = 0x8    // Position of FLASHSMEN field.
	RCC_AHB1SMENR_FLASHSMEN_Msk   = 0x100  // Bit mask of FLASHSMEN field.
	RCC_AHB1SMENR_FLASHSMEN       = 0x100  // Bit FLASHSMEN.
	RCC_AHB1SMENR_SRAM1SMEN_Pos   = 0x9    // Position of SRAM1SMEN field.
	RCC_AHB1SMENR_SRAM1SMEN_Msk   = 0x200  // Bit mask of SRAM1SMEN field.
	RCC_AHB1SMENR_SRAM1SMEN       = 0x200  // Bit SRAM1SMEN.
	RCC_AHB1SMENR_CRCSMEN_Pos     = 0xc    // Position of CRCSMEN field.
	RCC_AHB1SMENR_CRCSMEN_Msk     = 0x1000 // Bit mask of CRCSMEN field.
	RCC_AHB1SMENR_CRCSMEN         = 0x1000 // Bit CRCSMEN.
	RCC_AHB1SMENR_FMACSMEN_Pos    = 0x4    // Position of FMACSMEN field.
	RCC_AHB1SMENR_FMACSMEN_Msk    = 0x10   // Bit mask of FMACSMEN field.
	RCC_AHB1SMENR_FMACSMEN        = 0x10   // Bit FMACSMEN.

	// AHB2SMENR: AHB2 peripheral clocks enable in Sleep and           Stop modes register
	RCC_AHB2SMENR_GPIOASMEN_Pos  = 0x0       // Position of GPIOASMEN field.
	RCC_AHB2SMENR_GPIOASMEN_Msk  = 0x1       // Bit mask of GPIOASMEN field.
	RCC_AHB2SMENR_GPIOASMEN      = 0x1       // Bit GPIOASMEN.
	RCC_AHB2SMENR_GPIOBSMEN_Pos  = 0x1       // Position of GPIOBSMEN field.
	RCC_AHB2SMENR_GPIOBSMEN_Msk  = 0x2       // Bit mask of GPIOBSMEN field.
	RCC_AHB2SMENR_GPIOBSMEN      = 0x2       // Bit GPIOBSMEN.
	RCC_AHB2SMENR_GPIOCSMEN_Pos  = 0x2       // Position of GPIOCSMEN field.
	RCC_AHB2SMENR_GPIOCSMEN_Msk  = 0x4       // Bit mask of GPIOCSMEN field.
	RCC_AHB2SMENR_GPIOCSMEN      = 0x4       // Bit GPIOCSMEN.
	RCC_AHB2SMENR_GPIODSMEN_Pos  = 0x3       // Position of GPIODSMEN field.
	RCC_AHB2SMENR_GPIODSMEN_Msk  = 0x8       // Bit mask of GPIODSMEN field.
	RCC_AHB2SMENR_GPIODSMEN      = 0x8       // Bit GPIODSMEN.
	RCC_AHB2SMENR_GPIOESMEN_Pos  = 0x4       // Position of GPIOESMEN field.
	RCC_AHB2SMENR_GPIOESMEN_Msk  = 0x10      // Bit mask of GPIOESMEN field.
	RCC_AHB2SMENR_GPIOESMEN      = 0x10      // Bit GPIOESMEN.
	RCC_AHB2SMENR_GPIOFSMEN_Pos  = 0x5       // Position of GPIOFSMEN field.
	RCC_AHB2SMENR_GPIOFSMEN_Msk  = 0x20      // Bit mask of GPIOFSMEN field.
	RCC_AHB2SMENR_GPIOFSMEN      = 0x20      // Bit GPIOFSMEN.
	RCC_AHB2SMENR_GPIOGSMEN_Pos  = 0x6       // Position of GPIOGSMEN field.
	RCC_AHB2SMENR_GPIOGSMEN_Msk  = 0x40      // Bit mask of GPIOGSMEN field.
	RCC_AHB2SMENR_GPIOGSMEN      = 0x40      // Bit GPIOGSMEN.
	RCC_AHB2SMENR_SRAM2SMEN_Pos  = 0x9       // Position of SRAM2SMEN field.
	RCC_AHB2SMENR_SRAM2SMEN_Msk  = 0x200     // Bit mask of SRAM2SMEN field.
	RCC_AHB2SMENR_SRAM2SMEN      = 0x200     // Bit SRAM2SMEN.
	RCC_AHB2SMENR_SRAM3SMEN_Pos  = 0xa       // Position of SRAM3SMEN field.
	RCC_AHB2SMENR_SRAM3SMEN_Msk  = 0x400     // Bit mask of SRAM3SMEN field.
	RCC_AHB2SMENR_SRAM3SMEN      = 0x400     // Bit SRAM3SMEN.
	RCC_AHB2SMENR_AD12CSMEN_Pos  = 0xd       // Position of AD12CSMEN field.
	RCC_AHB2SMENR_AD12CSMEN_Msk  = 0x2000    // Bit mask of AD12CSMEN field.
	RCC_AHB2SMENR_AD12CSMEN      = 0x2000    // Bit AD12CSMEN.
	RCC_AHB2SMENR_ADC345SMEN_Pos = 0xe       // Position of ADC345SMEN field.
	RCC_AHB2SMENR_ADC345SMEN_Msk = 0x4000    // Bit mask of ADC345SMEN field.
	RCC_AHB2SMENR_ADC345SMEN     = 0x4000    // Bit ADC345SMEN.
	RCC_AHB2SMENR_DAC1SMEN_Pos   = 0x10      // Position of DAC1SMEN field.
	RCC_AHB2SMENR_DAC1SMEN_Msk   = 0x10000   // Bit mask of DAC1SMEN field.
	RCC_AHB2SMENR_DAC1SMEN       = 0x10000   // Bit DAC1SMEN.
	RCC_AHB2SMENR_DAC2SMEN_Pos   = 0x11      // Position of DAC2SMEN field.
	RCC_AHB2SMENR_DAC2SMEN_Msk   = 0x20000   // Bit mask of DAC2SMEN field.
	RCC_AHB2SMENR_DAC2SMEN       = 0x20000   // Bit DAC2SMEN.
	RCC_AHB2SMENR_DAC3SMEN_Pos   = 0x12      // Position of DAC3SMEN field.
	RCC_AHB2SMENR_DAC3SMEN_Msk   = 0x40000   // Bit mask of DAC3SMEN field.
	RCC_AHB2SMENR_DAC3SMEN       = 0x40000   // Bit DAC3SMEN.
	RCC_AHB2SMENR_DAC4SMEN_Pos   = 0x13      // Position of DAC4SMEN field.
	RCC_AHB2SMENR_DAC4SMEN_Msk   = 0x80000   // Bit mask of DAC4SMEN field.
	RCC_AHB2SMENR_DAC4SMEN       = 0x80000   // Bit DAC4SMEN.
	RCC_AHB2SMENR_CRYPTSMEN_Pos  = 0x18      // Position of CRYPTSMEN field.
	RCC_AHB2SMENR_CRYPTSMEN_Msk  = 0x1000000 // Bit mask of CRYPTSMEN field.
	RCC_AHB2SMENR_CRYPTSMEN      = 0x1000000 // Bit CRYPTSMEN.
	RCC_AHB2SMENR_RNGSMEN_Pos    = 0x1a      // Position of RNGSMEN field.
	RCC_AHB2SMENR_RNGSMEN_Msk    = 0x4000000 // Bit mask of RNGSMEN field.
	RCC_AHB2SMENR_RNGSMEN        = 0x4000000 // Bit RNGSMEN.

	// AHB3SMENR: AHB3 peripheral clocks enable in Sleep and           Stop modes register
	RCC_AHB3SMENR_FMCSMEN_Pos      = 0x0   // Position of FMCSMEN field.
	RCC_AHB3SMENR_FMCSMEN_Msk      = 0x1   // Bit mask of FMCSMEN field.
	RCC_AHB3SMENR_FMCSMEN          = 0x1   // Bit FMCSMEN.
	RCC_AHB3SMENR_QUADSPI1SMEN_Pos = 0x8   // Position of QUADSPI1SMEN field.
	RCC_AHB3SMENR_QUADSPI1SMEN_Msk = 0x100 // Bit mask of QUADSPI1SMEN field.
	RCC_AHB3SMENR_QUADSPI1SMEN     = 0x100 // Bit QUADSPI1SMEN.

	// APB1SMENR1: APB1SMENR1
	RCC_APB1SMENR1_TIM2SMEN_Pos   = 0x0        // Position of TIM2SMEN field.
	RCC_APB1SMENR1_TIM2SMEN_Msk   = 0x1        // Bit mask of TIM2SMEN field.
	RCC_APB1SMENR1_TIM2SMEN       = 0x1        // Bit TIM2SMEN.
	RCC_APB1SMENR1_TIM3SMEN_Pos   = 0x1        // Position of TIM3SMEN field.
	RCC_APB1SMENR1_TIM3SMEN_Msk   = 0x2        // Bit mask of TIM3SMEN field.
	RCC_APB1SMENR1_TIM3SMEN       = 0x2        // Bit TIM3SMEN.
	RCC_APB1SMENR1_TIM4SMEN_Pos   = 0x2        // Position of TIM4SMEN field.
	RCC_APB1SMENR1_TIM4SMEN_Msk   = 0x4        // Bit mask of TIM4SMEN field.
	RCC_APB1SMENR1_TIM4SMEN       = 0x4        // Bit TIM4SMEN.
	RCC_APB1SMENR1_TIM5SMEN_Pos   = 0x3        // Position of TIM5SMEN field.
	RCC_APB1SMENR1_TIM5SMEN_Msk   = 0x8        // Bit mask of TIM5SMEN field.
	RCC_APB1SMENR1_TIM5SMEN       = 0x8        // Bit TIM5SMEN.
	RCC_APB1SMENR1_TIM6SMEN_Pos   = 0x4        // Position of TIM6SMEN field.
	RCC_APB1SMENR1_TIM6SMEN_Msk   = 0x10       // Bit mask of TIM6SMEN field.
	RCC_APB1SMENR1_TIM6SMEN       = 0x10       // Bit TIM6SMEN.
	RCC_APB1SMENR1_TIM7SMEN_Pos   = 0x5        // Position of TIM7SMEN field.
	RCC_APB1SMENR1_TIM7SMEN_Msk   = 0x20       // Bit mask of TIM7SMEN field.
	RCC_APB1SMENR1_TIM7SMEN       = 0x20       // Bit TIM7SMEN.
	RCC_APB1SMENR1_CRSSMEN_Pos    = 0x8        // Position of CRSSMEN field.
	RCC_APB1SMENR1_CRSSMEN_Msk    = 0x100      // Bit mask of CRSSMEN field.
	RCC_APB1SMENR1_CRSSMEN        = 0x100      // Bit CRSSMEN.
	RCC_APB1SMENR1_RTCAPBSMEN_Pos = 0xa        // Position of RTCAPBSMEN field.
	RCC_APB1SMENR1_RTCAPBSMEN_Msk = 0x400      // Bit mask of RTCAPBSMEN field.
	RCC_APB1SMENR1_RTCAPBSMEN     = 0x400      // Bit RTCAPBSMEN.
	RCC_APB1SMENR1_WWDGSMEN_Pos   = 0xb        // Position of WWDGSMEN field.
	RCC_APB1SMENR1_WWDGSMEN_Msk   = 0x800      // Bit mask of WWDGSMEN field.
	RCC_APB1SMENR1_WWDGSMEN       = 0x800      // Bit WWDGSMEN.
	RCC_APB1SMENR1_SPI2SMEN_Pos   = 0xe        // Position of SPI2SMEN field.
	RCC_APB1SMENR1_SPI2SMEN_Msk   = 0x4000     // Bit mask of SPI2SMEN field.
	RCC_APB1SMENR1_SPI2SMEN       = 0x4000     // Bit SPI2SMEN.
	RCC_APB1SMENR1_SP3SMEN_Pos    = 0xf        // Position of SP3SMEN field.
	RCC_APB1SMENR1_SP3SMEN_Msk    = 0x8000     // Bit mask of SP3SMEN field.
	RCC_APB1SMENR1_SP3SMEN        = 0x8000     // Bit SP3SMEN.
	RCC_APB1SMENR1_USART2SMEN_Pos = 0x11       // Position of USART2SMEN field.
	RCC_APB1SMENR1_USART2SMEN_Msk = 0x20000    // Bit mask of USART2SMEN field.
	RCC_APB1SMENR1_USART2SMEN     = 0x20000    // Bit USART2SMEN.
	RCC_APB1SMENR1_USART3SMEN_Pos = 0x12       // Position of USART3SMEN field.
	RCC_APB1SMENR1_USART3SMEN_Msk = 0x40000    // Bit mask of USART3SMEN field.
	RCC_APB1SMENR1_USART3SMEN     = 0x40000    // Bit USART3SMEN.
	RCC_APB1SMENR1_UART4SMEN_Pos  = 0x13       // Position of UART4SMEN field.
	RCC_APB1SMENR1_UART4SMEN_Msk  = 0x80000    // Bit mask of UART4SMEN field.
	RCC_APB1SMENR1_UART4SMEN      = 0x80000    // Bit UART4SMEN.
	RCC_APB1SMENR1_UART5SMEN_Pos  = 0x14       // Position of UART5SMEN field.
	RCC_APB1SMENR1_UART5SMEN_Msk  = 0x100000   // Bit mask of UART5SMEN field.
	RCC_APB1SMENR1_UART5SMEN      = 0x100000   // Bit UART5SMEN.
	RCC_APB1SMENR1_I2C1SMEN_Pos   = 0x15       // Position of I2C1SMEN field.
	RCC_APB1SMENR1_I2C1SMEN_Msk   = 0x200000   // Bit mask of I2C1SMEN field.
	RCC_APB1SMENR1_I2C1SMEN       = 0x200000   // Bit I2C1SMEN.
	RCC_APB1SMENR1_I2C2SMEN_Pos   = 0x16       // Position of I2C2SMEN field.
	RCC_APB1SMENR1_I2C2SMEN_Msk   = 0x400000   // Bit mask of I2C2SMEN field.
	RCC_APB1SMENR1_I2C2SMEN       = 0x400000   // Bit I2C2SMEN.
	RCC_APB1SMENR1_I2C3SMEN_Pos   = 0x17       // Position of I2C3SMEN field.
	RCC_APB1SMENR1_I2C3SMEN_Msk   = 0x800000   // Bit mask of I2C3SMEN field.
	RCC_APB1SMENR1_I2C3SMEN       = 0x800000   // Bit I2C3SMEN.
	RCC_APB1SMENR1_FDCANSMEN_Pos  = 0x19       // Position of FDCANSMEN field.
	RCC_APB1SMENR1_FDCANSMEN_Msk  = 0x2000000  // Bit mask of FDCANSMEN field.
	RCC_APB1SMENR1_FDCANSMEN      = 0x2000000  // Bit FDCANSMEN.
	RCC_APB1SMENR1_PWRSMEN_Pos    = 0x1c       // Position of PWRSMEN field.
	RCC_APB1SMENR1_PWRSMEN_Msk    = 0x10000000 // Bit mask of PWRSMEN field.
	RCC_APB1SMENR1_PWRSMEN        = 0x10000000 // Bit PWRSMEN.
	RCC_APB1SMENR1_I2C3SMEN_3_Pos = 0x1e       // Position of I2C3SMEN_3 field.
	RCC_APB1SMENR1_I2C3SMEN_3_Msk = 0x40000000 // Bit mask of I2C3SMEN_3 field.
	RCC_APB1SMENR1_I2C3SMEN_3     = 0x40000000 // Bit I2C3SMEN_3.
	RCC_APB1SMENR1_LPTIM1SMEN_Pos = 0x1f       // Position of LPTIM1SMEN field.
	RCC_APB1SMENR1_LPTIM1SMEN_Msk = 0x80000000 // Bit mask of LPTIM1SMEN field.
	RCC_APB1SMENR1_LPTIM1SMEN     = 0x80000000 // Bit LPTIM1SMEN.

	// APB1SMENR2: APB1 peripheral clocks enable in Sleep and           Stop modes register 2
	RCC_APB1SMENR2_LPUART1SMEN_Pos = 0x0   // Position of LPUART1SMEN field.
	RCC_APB1SMENR2_LPUART1SMEN_Msk = 0x1   // Bit mask of LPUART1SMEN field.
	RCC_APB1SMENR2_LPUART1SMEN     = 0x1   // Bit LPUART1SMEN.
	RCC_APB1SMENR2_I2C4SMEN_Pos    = 0x1   // Position of I2C4SMEN field.
	RCC_APB1SMENR2_I2C4SMEN_Msk    = 0x2   // Bit mask of I2C4SMEN field.
	RCC_APB1SMENR2_I2C4SMEN        = 0x2   // Bit I2C4SMEN.
	RCC_APB1SMENR2_USBPDSMEN_Pos   = 0x8   // Position of USBPDSMEN field.
	RCC_APB1SMENR2_USBPDSMEN_Msk   = 0x100 // Bit mask of USBPDSMEN field.
	RCC_APB1SMENR2_USBPDSMEN       = 0x100 // Bit USBPDSMEN.

	// APB2SMENR: APB2SMENR
	RCC_APB2SMENR_SYSCFGSMEN_Pos  = 0x0       // Position of SYSCFGSMEN field.
	RCC_APB2SMENR_SYSCFGSMEN_Msk  = 0x1       // Bit mask of SYSCFGSMEN field.
	RCC_APB2SMENR_SYSCFGSMEN      = 0x1       // Bit SYSCFGSMEN.
	RCC_APB2SMENR_TIM1SMEN_Pos    = 0xb       // Position of TIM1SMEN field.
	RCC_APB2SMENR_TIM1SMEN_Msk    = 0x800     // Bit mask of TIM1SMEN field.
	RCC_APB2SMENR_TIM1SMEN        = 0x800     // Bit TIM1SMEN.
	RCC_APB2SMENR_SPI1SMEN_Pos    = 0xc       // Position of SPI1SMEN field.
	RCC_APB2SMENR_SPI1SMEN_Msk    = 0x1000    // Bit mask of SPI1SMEN field.
	RCC_APB2SMENR_SPI1SMEN        = 0x1000    // Bit SPI1SMEN.
	RCC_APB2SMENR_TIM8SMEN_Pos    = 0xd       // Position of TIM8SMEN field.
	RCC_APB2SMENR_TIM8SMEN_Msk    = 0x2000    // Bit mask of TIM8SMEN field.
	RCC_APB2SMENR_TIM8SMEN        = 0x2000    // Bit TIM8SMEN.
	RCC_APB2SMENR_USART1SMEN_Pos  = 0xe       // Position of USART1SMEN field.
	RCC_APB2SMENR_USART1SMEN_Msk  = 0x4000    // Bit mask of USART1SMEN field.
	RCC_APB2SMENR_USART1SMEN      = 0x4000    // Bit USART1SMEN.
	RCC_APB2SMENR_SPI4SMEN_Pos    = 0xf       // Position of SPI4SMEN field.
	RCC_APB2SMENR_SPI4SMEN_Msk    = 0x8000    // Bit mask of SPI4SMEN field.
	RCC_APB2SMENR_SPI4SMEN        = 0x8000    // Bit SPI4SMEN.
	RCC_APB2SMENR_TIM15SMEN_Pos   = 0x10      // Position of TIM15SMEN field.
	RCC_APB2SMENR_TIM15SMEN_Msk   = 0x10000   // Bit mask of TIM15SMEN field.
	RCC_APB2SMENR_TIM15SMEN       = 0x10000   // Bit TIM15SMEN.
	RCC_APB2SMENR_TIM16SMEN_Pos   = 0x11      // Position of TIM16SMEN field.
	RCC_APB2SMENR_TIM16SMEN_Msk   = 0x20000   // Bit mask of TIM16SMEN field.
	RCC_APB2SMENR_TIM16SMEN       = 0x20000   // Bit TIM16SMEN.
	RCC_APB2SMENR_TIM17SMEN_Pos   = 0x12      // Position of TIM17SMEN field.
	RCC_APB2SMENR_TIM17SMEN_Msk   = 0x40000   // Bit mask of TIM17SMEN field.
	RCC_APB2SMENR_TIM17SMEN       = 0x40000   // Bit TIM17SMEN.
	RCC_APB2SMENR_TIM20SMEN_Pos   = 0x14      // Position of TIM20SMEN field.
	RCC_APB2SMENR_TIM20SMEN_Msk   = 0x100000  // Bit mask of TIM20SMEN field.
	RCC_APB2SMENR_TIM20SMEN       = 0x100000  // Bit TIM20SMEN.
	RCC_APB2SMENR_SAI1SMEN_Pos    = 0x15      // Position of SAI1SMEN field.
	RCC_APB2SMENR_SAI1SMEN_Msk    = 0x200000  // Bit mask of SAI1SMEN field.
	RCC_APB2SMENR_SAI1SMEN        = 0x200000  // Bit SAI1SMEN.
	RCC_APB2SMENR_HRTIMERSMEN_Pos = 0x1a      // Position of HRTIMERSMEN field.
	RCC_APB2SMENR_HRTIMERSMEN_Msk = 0x4000000 // Bit mask of HRTIMERSMEN field.
	RCC_APB2SMENR_HRTIMERSMEN     = 0x4000000 // Bit HRTIMERSMEN.

	// CCIPR1: CCIPR
	RCC_CCIPR1_ADC345SEL_Pos  = 0x1e       // Position of ADC345SEL field.
	RCC_CCIPR1_ADC345SEL_Msk  = 0xc0000000 // Bit mask of ADC345SEL field.
	RCC_CCIPR1_ADCSEL_Pos     = 0x1c       // Position of ADCSEL field.
	RCC_CCIPR1_ADCSEL_Msk     = 0x30000000 // Bit mask of ADCSEL field.
	RCC_CCIPR1_CLK48SEL_Pos   = 0x1a       // Position of CLK48SEL field.
	RCC_CCIPR1_CLK48SEL_Msk   = 0xc000000  // Bit mask of CLK48SEL field.
	RCC_CCIPR1_FDCANSEL_Pos   = 0x18       // Position of FDCANSEL field.
	RCC_CCIPR1_FDCANSEL_Msk   = 0x3000000  // Bit mask of FDCANSEL field.
	RCC_CCIPR1_SPISEL__Pos    = 0x16       // Position of SPISEL_ field.
	RCC_CCIPR1_SPISEL__Msk    = 0xc00000   // Bit mask of SPISEL_ field.
	RCC_CCIPR1_SAISEL_Pos     = 0x14       // Position of SAISEL field.
	RCC_CCIPR1_SAISEL_Msk     = 0x300000   // Bit mask of SAISEL field.
	RCC_CCIPR1_LPTIM1SEL_Pos  = 0x12       // Position of LPTIM1SEL field.
	RCC_CCIPR1_LPTIM1SEL_Msk  = 0xc0000    // Bit mask of LPTIM1SEL field.
	RCC_CCIPR1_I2C3SEL_Pos    = 0x10       // Position of I2C3SEL field.
	RCC_CCIPR1_I2C3SEL_Msk    = 0x30000    // Bit mask of I2C3SEL field.
	RCC_CCIPR1_I2C2SEL_Pos    = 0xe        // Position of I2C2SEL field.
	RCC_CCIPR1_I2C2SEL_Msk    = 0xc000     // Bit mask of I2C2SEL field.
	RCC_CCIPR1_I2C1SEL_Pos    = 0xc        // Position of I2C1SEL field.
	RCC_CCIPR1_I2C1SEL_Msk    = 0x3000     // Bit mask of I2C1SEL field.
	RCC_CCIPR1_LPUART1SEL_Pos = 0xa        // Position of LPUART1SEL field.
	RCC_CCIPR1_LPUART1SEL_Msk = 0xc00      // Bit mask of LPUART1SEL field.
	RCC_CCIPR1_UART5SEL_Pos   = 0x8        // Position of UART5SEL field.
	RCC_CCIPR1_UART5SEL_Msk   = 0x300      // Bit mask of UART5SEL field.
	RCC_CCIPR1_UART4SEL_Pos   = 0x6        // Position of UART4SEL field.
	RCC_CCIPR1_UART4SEL_Msk   = 0xc0       // Bit mask of UART4SEL field.
	RCC_CCIPR1_USART3SEL_Pos  = 0x4        // Position of USART3SEL field.
	RCC_CCIPR1_USART3SEL_Msk  = 0x30       // Bit mask of USART3SEL field.
	RCC_CCIPR1_USART2SEL_Pos  = 0x2        // Position of USART2SEL field.
	RCC_CCIPR1_USART2SEL_Msk  = 0xc        // Bit mask of USART2SEL field.
	RCC_CCIPR1_USART1SEL_Pos  = 0x0        // Position of USART1SEL field.
	RCC_CCIPR1_USART1SEL_Msk  = 0x3        // Bit mask of USART1SEL field.

	// BDCR: BDCR
	RCC_BDCR_LSCOSEL_Pos  = 0x19      // Position of LSCOSEL field.
	RCC_BDCR_LSCOSEL_Msk  = 0x2000000 // Bit mask of LSCOSEL field.
	RCC_BDCR_LSCOSEL      = 0x2000000 // Bit LSCOSEL.
	RCC_BDCR_LSCCOEN_Pos  = 0x18      // Position of LSCCOEN field.
	RCC_BDCR_LSCCOEN_Msk  = 0x1000000 // Bit mask of LSCCOEN field.
	RCC_BDCR_LSCCOEN      = 0x1000000 // Bit LSCCOEN.
	RCC_BDCR_VSWRST_Pos   = 0x10      // Position of VSWRST field.
	RCC_BDCR_VSWRST_Msk   = 0x10000   // Bit mask of VSWRST field.
	RCC_BDCR_VSWRST       = 0x10000   // Bit VSWRST.
	RCC_BDCR_RTCEN_Pos    = 0xf       // Position of RTCEN field.
	RCC_BDCR_RTCEN_Msk    = 0x8000    // Bit mask of RTCEN field.
	RCC_BDCR_RTCEN        = 0x8000    // Bit RTCEN.
	RCC_BDCR_RTCSEL_Pos   = 0x8       // Position of RTCSEL field.
	RCC_BDCR_RTCSEL_Msk   = 0x300     // Bit mask of RTCSEL field.
	RCC_BDCR_LSECSSD_Pos  = 0x6       // Position of LSECSSD field.
	RCC_BDCR_LSECSSD_Msk  = 0x40      // Bit mask of LSECSSD field.
	RCC_BDCR_LSECSSD      = 0x40      // Bit LSECSSD.
	RCC_BDCR_LSECSSON_Pos = 0x5       // Position of LSECSSON field.
	RCC_BDCR_LSECSSON_Msk = 0x20      // Bit mask of LSECSSON field.
	RCC_BDCR_LSECSSON     = 0x20      // Bit LSECSSON.
	RCC_BDCR_LSEDRV_Pos   = 0x3       // Position of LSEDRV field.
	RCC_BDCR_LSEDRV_Msk   = 0x18      // Bit mask of LSEDRV field.
	RCC_BDCR_LSEBYP_Pos   = 0x2       // Position of LSEBYP field.
	RCC_BDCR_LSEBYP_Msk   = 0x4       // Bit mask of LSEBYP field.
	RCC_BDCR_LSEBYP       = 0x4       // Bit LSEBYP.
	RCC_BDCR_LSERDY_Pos   = 0x1       // Position of LSERDY field.
	RCC_BDCR_LSERDY_Msk   = 0x2       // Bit mask of LSERDY field.
	RCC_BDCR_LSERDY       = 0x2       // Bit LSERDY.
	RCC_BDCR_LSEON_Pos    = 0x0       // Position of LSEON field.
	RCC_BDCR_LSEON_Msk    = 0x1       // Bit mask of LSEON field.
	RCC_BDCR_LSEON        = 0x1       // Bit LSEON.

	// CSR: CSR
	RCC_CSR_LPWRSTF_Pos  = 0x1f       // Position of LPWRSTF field.
	RCC_CSR_LPWRSTF_Msk  = 0x80000000 // Bit mask of LPWRSTF field.
	RCC_CSR_LPWRSTF      = 0x80000000 // Bit LPWRSTF.
	RCC_CSR_WWDGRSTF_Pos = 0x1e       // Position of WWDGRSTF field.
	RCC_CSR_WWDGRSTF_Msk = 0x40000000 // Bit mask of WWDGRSTF field.
	RCC_CSR_WWDGRSTF     = 0x40000000 // Bit WWDGRSTF.
	RCC_CSR_WDGRSTF_Pos  = 0x1d       // Position of WDGRSTF field.
	RCC_CSR_WDGRSTF_Msk  = 0x20000000 // Bit mask of WDGRSTF field.
	RCC_CSR_WDGRSTF      = 0x20000000 // Bit WDGRSTF.
	RCC_CSR_SFTRSTF_Pos  = 0x1c       // Position of SFTRSTF field.
	RCC_CSR_SFTRSTF_Msk  = 0x10000000 // Bit mask of SFTRSTF field.
	RCC_CSR_SFTRSTF      = 0x10000000 // Bit SFTRSTF.
	RCC_CSR_BORRSTF_Pos  = 0x1b       // Position of BORRSTF field.
	RCC_CSR_BORRSTF_Msk  = 0x8000000  // Bit mask of BORRSTF field.
	RCC_CSR_BORRSTF      = 0x8000000  // Bit BORRSTF.
	RCC_CSR_PADRSTF_Pos  = 0x1a       // Position of PADRSTF field.
	RCC_CSR_PADRSTF_Msk  = 0x4000000  // Bit mask of PADRSTF field.
	RCC_CSR_PADRSTF      = 0x4000000  // Bit PADRSTF.
	RCC_CSR_OBLRSTF_Pos  = 0x19       // Position of OBLRSTF field.
	RCC_CSR_OBLRSTF_Msk  = 0x2000000  // Bit mask of OBLRSTF field.
	RCC_CSR_OBLRSTF      = 0x2000000  // Bit OBLRSTF.
	RCC_CSR_RMVF_Pos     = 0x17       // Position of RMVF field.
	RCC_CSR_RMVF_Msk     = 0x800000   // Bit mask of RMVF field.
	RCC_CSR_RMVF         = 0x800000   // Bit RMVF.
	RCC_CSR_LSIRDY_Pos   = 0x1        // Position of LSIRDY field.
	RCC_CSR_LSIRDY_Msk   = 0x2        // Bit mask of LSIRDY field.
	RCC_CSR_LSIRDY       = 0x2        // Bit LSIRDY.
	RCC_CSR_LSION_Pos    = 0x0        // Position of LSION field.
	RCC_CSR_LSION_Msk    = 0x1        // Bit mask of LSION field.
	RCC_CSR_LSION        = 0x1        // Bit LSION.

	// CRRCR: Clock recovery RC register
	RCC_CRRCR_RC48ON_Pos  = 0x0    // Position of RC48ON field.
	RCC_CRRCR_RC48ON_Msk  = 0x1    // Bit mask of RC48ON field.
	RCC_CRRCR_RC48ON      = 0x1    // Bit RC48ON.
	RCC_CRRCR_RC48RDY_Pos = 0x1    // Position of RC48RDY field.
	RCC_CRRCR_RC48RDY_Msk = 0x2    // Bit mask of RC48RDY field.
	RCC_CRRCR_RC48RDY     = 0x2    // Bit RC48RDY.
	RCC_CRRCR_RC48CAL_Pos = 0x7    // Position of RC48CAL field.
	RCC_CRRCR_RC48CAL_Msk = 0xff80 // Bit mask of RC48CAL field.

	// CCIPR2: Peripherals independent clock configuration           register
	RCC_CCIPR2_I2C4SEL_Pos    = 0x0      // Position of I2C4SEL field.
	RCC_CCIPR2_I2C4SEL_Msk    = 0x3      // Bit mask of I2C4SEL field.
	RCC_CCIPR2_QUADSPISEL_Pos = 0x14     // Position of QUADSPISEL field.
	RCC_CCIPR2_QUADSPISEL_Msk = 0x300000 // Bit mask of QUADSPISEL field.
)

// Bitfields for PWR: Power control
const (
	// CR1: Power control register 1
	PWR_CR1_LPR_Pos  = 0xe    // Position of LPR field.
	PWR_CR1_LPR_Msk  = 0x4000 // Bit mask of LPR field.
	PWR_CR1_LPR      = 0x4000 // Bit LPR.
	PWR_CR1_VOS_Pos  = 0x9    // Position of VOS field.
	PWR_CR1_VOS_Msk  = 0x600  // Bit mask of VOS field.
	PWR_CR1_DBP_Pos  = 0x8    // Position of DBP field.
	PWR_CR1_DBP_Msk  = 0x100  // Bit mask of DBP field.
	PWR_CR1_DBP      = 0x100  // Bit DBP.
	PWR_CR1_LPMS_Pos = 0x0    // Position of LPMS field.
	PWR_CR1_LPMS_Msk = 0x7    // Bit mask of LPMS field.

	// CR2: Power control register 2
	PWR_CR2_PVMEN1_Pos = 0x4  // Position of PVMEN1 field.
	PWR_CR2_PVMEN1_Msk = 0x10 // Bit mask of PVMEN1 field.
	PWR_CR2_PVMEN1     = 0x10 // Bit PVMEN1.
	PWR_CR2_PLS_Pos    = 0x1  // Position of PLS field.
	PWR_CR2_PLS_Msk    = 0xe  // Bit mask of PLS field.
	PWR_CR2_PVDE_Pos   = 0x0  // Position of PVDE field.
	PWR_CR2_PVDE_Msk   = 0x1  // Bit mask of PVDE field.
	PWR_CR2_PVDE       = 0x1  // Bit PVDE.
	PWR_CR2_PVMEN2_Pos = 0x5  // Position of PVMEN2 field.
	PWR_CR2_PVMEN2_Msk = 0x20 // Bit mask of PVMEN2 field.
	PWR_CR2_PVMEN2     = 0x20 // Bit PVMEN2.
	PWR_CR2_PVMEN3_Pos = 0x6  // Position of PVMEN3 field.
	PWR_CR2_PVMEN3_Msk = 0x40 // Bit mask of PVMEN3 field.
	PWR_CR2_PVMEN3     = 0x40 // Bit PVMEN3.
	PWR_CR2_PVMEN4_Pos = 0x7  // Position of PVMEN4 field.
	PWR_CR2_PVMEN4_Msk = 0x80 // Bit mask of PVMEN4 field.
	PWR_CR2_PVMEN4     = 0x80 // Bit PVMEN4.

	// CR3: Power control register 3
	PWR_CR3_EWUP1_Pos       = 0x0    // Position of EWUP1 field.
	PWR_CR3_EWUP1_Msk       = 0x1    // Bit mask of EWUP1 field.
	PWR_CR3_EWUP1           = 0x1    // Bit EWUP1.
	PWR_CR3_EWUP2_Pos       = 0x1    // Position of EWUP2 field.
	PWR_CR3_EWUP2_Msk       = 0x2    // Bit mask of EWUP2 field.
	PWR_CR3_EWUP2           = 0x2    // Bit EWUP2.
	PWR_CR3_EWUP3_Pos       = 0x2    // Position of EWUP3 field.
	PWR_CR3_EWUP3_Msk       = 0x4    // Bit mask of EWUP3 field.
	PWR_CR3_EWUP3           = 0x4    // Bit EWUP3.
	PWR_CR3_EWUP4_Pos       = 0x3    // Position of EWUP4 field.
	PWR_CR3_EWUP4_Msk       = 0x8    // Bit mask of EWUP4 field.
	PWR_CR3_EWUP4           = 0x8    // Bit EWUP4.
	PWR_CR3_EWUP5_Pos       = 0x4    // Position of EWUP5 field.
	PWR_CR3_EWUP5_Msk       = 0x10   // Bit mask of EWUP5 field.
	PWR_CR3_EWUP5           = 0x10   // Bit EWUP5.
	PWR_CR3_RRS_Pos         = 0x8    // Position of RRS field.
	PWR_CR3_RRS_Msk         = 0x100  // Bit mask of RRS field.
	PWR_CR3_RRS             = 0x100  // Bit RRS.
	PWR_CR3_APC_Pos         = 0xa    // Position of APC field.
	PWR_CR3_APC_Msk         = 0x400  // Bit mask of APC field.
	PWR_CR3_APC             = 0x400  // Bit APC.
	PWR_CR3_UCPD1_STDBY_Pos = 0xd    // Position of UCPD1_STDBY field.
	PWR_CR3_UCPD1_STDBY_Msk = 0x2000 // Bit mask of UCPD1_STDBY field.
	PWR_CR3_UCPD1_STDBY     = 0x2000 // Bit UCPD1_STDBY.
	PWR_CR3_UCPD1_DBDIS_Pos = 0xe    // Position of UCPD1_DBDIS field.
	PWR_CR3_UCPD1_DBDIS_Msk = 0x4000 // Bit mask of UCPD1_DBDIS field.
	PWR_CR3_UCPD1_DBDIS     = 0x4000 // Bit UCPD1_DBDIS.
	PWR_CR3_EIWUL_Pos       = 0xf    // Position of EIWUL field.
	PWR_CR3_EIWUL_Msk       = 0x8000 // Bit mask of EIWUL field.
	PWR_CR3_EIWUL           = 0x8000 // Bit EIWUL.

	// CR4: Power control register 4
	PWR_CR4_VBRS_Pos = 0x9   // Position of VBRS field.
	PWR_CR4_VBRS_Msk = 0x200 // Bit mask of VBRS field.
	PWR_CR4_VBRS     = 0x200 // Bit VBRS.
	PWR_CR4_VBE_Pos  = 0x8   // Position of VBE field.
	PWR_CR4_VBE_Msk  = 0x100 // Bit mask of VBE field.
	PWR_CR4_VBE      = 0x100 // Bit VBE.
	PWR_CR4_WP5_Pos  = 0x4   // Position of WP5 field.
	PWR_CR4_WP5_Msk  = 0x10  // Bit mask of WP5 field.
	PWR_CR4_WP5      = 0x10  // Bit WP5.
	PWR_CR4_WP4_Pos  = 0x3   // Position of WP4 field.
	PWR_CR4_WP4_Msk  = 0x8   // Bit mask of WP4 field.
	PWR_CR4_WP4      = 0x8   // Bit WP4.
	PWR_CR4_WP3_Pos  = 0x2   // Position of WP3 field.
	PWR_CR4_WP3_Msk  = 0x4   // Bit mask of WP3 field.
	PWR_CR4_WP3      = 0x4   // Bit WP3.
	PWR_CR4_WP2_Pos  = 0x1   // Position of WP2 field.
	PWR_CR4_WP2_Msk  = 0x2   // Bit mask of WP2 field.
	PWR_CR4_WP2      = 0x2   // Bit WP2.
	PWR_CR4_WP1_Pos  = 0x0   // Position of WP1 field.
	PWR_CR4_WP1_Msk  = 0x1   // Bit mask of WP1 field.
	PWR_CR4_WP1      = 0x1   // Bit WP1.

	// SR1: Power status register 1
	PWR_SR1_WUFI_Pos = 0xf    // Position of WUFI field.
	PWR_SR1_WUFI_Msk = 0x8000 // Bit mask of WUFI field.
	PWR_SR1_WUFI     = 0x8000 // Bit WUFI.
	PWR_SR1_SBF_Pos  = 0x8    // Position of SBF field.
	PWR_SR1_SBF_Msk  = 0x100  // Bit mask of SBF field.
	PWR_SR1_SBF      = 0x100  // Bit SBF.
	PWR_SR1_WUF5_Pos = 0x4    // Position of WUF5 field.
	PWR_SR1_WUF5_Msk = 0x10   // Bit mask of WUF5 field.
	PWR_SR1_WUF5     = 0x10   // Bit WUF5.
	PWR_SR1_WUF4_Pos = 0x3    // Position of WUF4 field.
	PWR_SR1_WUF4_Msk = 0x8    // Bit mask of WUF4 field.
	PWR_SR1_WUF4     = 0x8    // Bit WUF4.
	PWR_SR1_WUF3_Pos = 0x2    // Position of WUF3 field.
	PWR_SR1_WUF3_Msk = 0x4    // Bit mask of WUF3 field.
	PWR_SR1_WUF3     = 0x4    // Bit WUF3.
	PWR_SR1_WUF2_Pos = 0x1    // Position of WUF2 field.
	PWR_SR1_WUF2_Msk = 0x2    // Bit mask of WUF2 field.
	PWR_SR1_WUF2     = 0x2    // Bit WUF2.
	PWR_SR1_WUF1_Pos = 0x0    // Position of WUF1 field.
	PWR_SR1_WUF1_Msk = 0x1    // Bit mask of WUF1 field.
	PWR_SR1_WUF1     = 0x1    // Bit WUF1.

	// SR2: Power status register 2
	PWR_SR2_PVMO4_Pos  = 0xf    // Position of PVMO4 field.
	PWR_SR2_PVMO4_Msk  = 0x8000 // Bit mask of PVMO4 field.
	PWR_SR2_PVMO4      = 0x8000 // Bit PVMO4.
	PWR_SR2_PVMO3_Pos  = 0xe    // Position of PVMO3 field.
	PWR_SR2_PVMO3_Msk  = 0x4000 // Bit mask of PVMO3 field.
	PWR_SR2_PVMO3      = 0x4000 // Bit PVMO3.
	PWR_SR2_PVMO2_Pos  = 0xd    // Position of PVMO2 field.
	PWR_SR2_PVMO2_Msk  = 0x2000 // Bit mask of PVMO2 field.
	PWR_SR2_PVMO2      = 0x2000 // Bit PVMO2.
	PWR_SR2_PVMO1_Pos  = 0xc    // Position of PVMO1 field.
	PWR_SR2_PVMO1_Msk  = 0x1000 // Bit mask of PVMO1 field.
	PWR_SR2_PVMO1      = 0x1000 // Bit PVMO1.
	PWR_SR2_PVDO_Pos   = 0xb    // Position of PVDO field.
	PWR_SR2_PVDO_Msk   = 0x800  // Bit mask of PVDO field.
	PWR_SR2_PVDO       = 0x800  // Bit PVDO.
	PWR_SR2_VOSF_Pos   = 0xa    // Position of VOSF field.
	PWR_SR2_VOSF_Msk   = 0x400  // Bit mask of VOSF field.
	PWR_SR2_VOSF       = 0x400  // Bit VOSF.
	PWR_SR2_REGLPF_Pos = 0x9    // Position of REGLPF field.
	PWR_SR2_REGLPF_Msk = 0x200  // Bit mask of REGLPF field.
	PWR_SR2_REGLPF     = 0x200  // Bit REGLPF.
	PWR_SR2_REGLPS_Pos = 0x8    // Position of REGLPS field.
	PWR_SR2_REGLPS_Msk = 0x100  // Bit mask of REGLPS field.
	PWR_SR2_REGLPS     = 0x100  // Bit REGLPS.

	// SCR: Power status clear register
	PWR_SCR_CSBF_Pos  = 0x8   // Position of CSBF field.
	PWR_SCR_CSBF_Msk  = 0x100 // Bit mask of CSBF field.
	PWR_SCR_CSBF      = 0x100 // Bit CSBF.
	PWR_SCR_CWUF5_Pos = 0x4   // Position of CWUF5 field.
	PWR_SCR_CWUF5_Msk = 0x10  // Bit mask of CWUF5 field.
	PWR_SCR_CWUF5     = 0x10  // Bit CWUF5.
	PWR_SCR_CWUF4_Pos = 0x3   // Position of CWUF4 field.
	PWR_SCR_CWUF4_Msk = 0x8   // Bit mask of CWUF4 field.
	PWR_SCR_CWUF4     = 0x8   // Bit CWUF4.
	PWR_SCR_CWUF3_Pos = 0x2   // Position of CWUF3 field.
	PWR_SCR_CWUF3_Msk = 0x4   // Bit mask of CWUF3 field.
	PWR_SCR_CWUF3     = 0x4   // Bit CWUF3.
	PWR_SCR_CWUF2_Pos = 0x1   // Position of CWUF2 field.
	PWR_SCR_CWUF2_Msk = 0x2   // Bit mask of CWUF2 field.
	PWR_SCR_CWUF2     = 0x2   // Bit CWUF2.
	PWR_SCR_CWUF1_Pos = 0x0   // Position of CWUF1 field.
	PWR_SCR_CWUF1_Msk = 0x1   // Bit mask of CWUF1 field.
	PWR_SCR_CWUF1     = 0x1   // Bit CWUF1.

	// PUCRA: Power Port A pull-up control           register
	PWR_PUCRA_PU15_Pos = 0xf    // Position of PU15 field.
	PWR_PUCRA_PU15_Msk = 0x8000 // Bit mask of PU15 field.
	PWR_PUCRA_PU15     = 0x8000 // Bit PU15.
	PWR_PUCRA_PU13_Pos = 0xd    // Position of PU13 field.
	PWR_PUCRA_PU13_Msk = 0x2000 // Bit mask of PU13 field.
	PWR_PUCRA_PU13     = 0x2000 // Bit PU13.
	PWR_PUCRA_PU12_Pos = 0xc    // Position of PU12 field.
	PWR_PUCRA_PU12_Msk = 0x1000 // Bit mask of PU12 field.
	PWR_PUCRA_PU12     = 0x1000 // Bit PU12.
	PWR_PUCRA_PU11_Pos = 0xb    // Position of PU11 field.
	PWR_PUCRA_PU11_Msk = 0x800  // Bit mask of PU11 field.
	PWR_PUCRA_PU11     = 0x800  // Bit PU11.
	PWR_PUCRA_PU10_Pos = 0xa    // Position of PU10 field.
	PWR_PUCRA_PU10_Msk = 0x400  // Bit mask of PU10 field.
	PWR_PUCRA_PU10     = 0x400  // Bit PU10.
	PWR_PUCRA_PU9_Pos  = 0x9    // Position of PU9 field.
	PWR_PUCRA_PU9_Msk  = 0x200  // Bit mask of PU9 field.
	PWR_PUCRA_PU9      = 0x200  // Bit PU9.
	PWR_PUCRA_PU8_Pos  = 0x8    // Position of PU8 field.
	PWR_PUCRA_PU8_Msk  = 0x100  // Bit mask of PU8 field.
	PWR_PUCRA_PU8      = 0x100  // Bit PU8.
	PWR_PUCRA_PU7_Pos  = 0x7    // Position of PU7 field.
	PWR_PUCRA_PU7_Msk  = 0x80   // Bit mask of PU7 field.
	PWR_PUCRA_PU7      = 0x80   // Bit PU7.
	PWR_PUCRA_PU6_Pos  = 0x6    // Position of PU6 field.
	PWR_PUCRA_PU6_Msk  = 0x40   // Bit mask of PU6 field.
	PWR_PUCRA_PU6      = 0x40   // Bit PU6.
	PWR_PUCRA_PU5_Pos  = 0x5    // Position of PU5 field.
	PWR_PUCRA_PU5_Msk  = 0x20   // Bit mask of PU5 field.
	PWR_PUCRA_PU5      = 0x20   // Bit PU5.
	PWR_PUCRA_PU4_Pos  = 0x4    // Position of PU4 field.
	PWR_PUCRA_PU4_Msk  = 0x10   // Bit mask of PU4 field.
	PWR_PUCRA_PU4      = 0x10   // Bit PU4.
	PWR_PUCRA_PU3_Pos  = 0x3    // Position of PU3 field.
	PWR_PUCRA_PU3_Msk  = 0x8    // Bit mask of PU3 field.
	PWR_PUCRA_PU3      = 0x8    // Bit PU3.
	PWR_PUCRA_PU2_Pos  = 0x2    // Position of PU2 field.
	PWR_PUCRA_PU2_Msk  = 0x4    // Bit mask of PU2 field.
	PWR_PUCRA_PU2      = 0x4    // Bit PU2.
	PWR_PUCRA_PU1_Pos  = 0x1    // Position of PU1 field.
	PWR_PUCRA_PU1_Msk  = 0x2    // Bit mask of PU1 field.
	PWR_PUCRA_PU1      = 0x2    // Bit PU1.
	PWR_PUCRA_PU0_Pos  = 0x0    // Position of PU0 field.
	PWR_PUCRA_PU0_Msk  = 0x1    // Bit mask of PU0 field.
	PWR_PUCRA_PU0      = 0x1    // Bit PU0.

	// PDCRA: Power Port A pull-down control           register
	PWR_PDCRA_PD14_Pos = 0xe    // Position of PD14 field.
	PWR_PDCRA_PD14_Msk = 0x4000 // Bit mask of PD14 field.
	PWR_PDCRA_PD14     = 0x4000 // Bit PD14.
	PWR_PDCRA_PD12_Pos = 0xc    // Position of PD12 field.
	PWR_PDCRA_PD12_Msk = 0x1000 // Bit mask of PD12 field.
	PWR_PDCRA_PD12     = 0x1000 // Bit PD12.
	PWR_PDCRA_PD11_Pos = 0xb    // Position of PD11 field.
	PWR_PDCRA_PD11_Msk = 0x800  // Bit mask of PD11 field.
	PWR_PDCRA_PD11     = 0x800  // Bit PD11.
	PWR_PDCRA_PD10_Pos = 0xa    // Position of PD10 field.
	PWR_PDCRA_PD10_Msk = 0x400  // Bit mask of PD10 field.
	PWR_PDCRA_PD10     = 0x400  // Bit PD10.
	PWR_PDCRA_PD9_Pos  = 0x9    // Position of PD9 field.
	PWR_PDCRA_PD9_Msk  = 0x200  // Bit mask of PD9 field.
	PWR_PDCRA_PD9      = 0x200  // Bit PD9.
	PWR_PDCRA_PD8_Pos  = 0x8    // Position of PD8 field.
	PWR_PDCRA_PD8_Msk  = 0x100  // Bit mask of PD8 field.
	PWR_PDCRA_PD8      = 0x100  // Bit PD8.
	PWR_PDCRA_PD7_Pos  = 0x7    // Position of PD7 field.
	PWR_PDCRA_PD7_Msk  = 0x80   // Bit mask of PD7 field.
	PWR_PDCRA_PD7      = 0x80   // Bit PD7.
	PWR_PDCRA_PD6_Pos  = 0x6    // Position of PD6 field.
	PWR_PDCRA_PD6_Msk  = 0x40   // Bit mask of PD6 field.
	PWR_PDCRA_PD6      = 0x40   // Bit PD6.
	PWR_PDCRA_PD5_Pos  = 0x5    // Position of PD5 field.
	PWR_PDCRA_PD5_Msk  = 0x20   // Bit mask of PD5 field.
	PWR_PDCRA_PD5      = 0x20   // Bit PD5.
	PWR_PDCRA_PD4_Pos  = 0x4    // Position of PD4 field.
	PWR_PDCRA_PD4_Msk  = 0x10   // Bit mask of PD4 field.
	PWR_PDCRA_PD4      = 0x10   // Bit PD4.
	PWR_PDCRA_PD3_Pos  = 0x3    // Position of PD3 field.
	PWR_PDCRA_PD3_Msk  = 0x8    // Bit mask of PD3 field.
	PWR_PDCRA_PD3      = 0x8    // Bit PD3.
	PWR_PDCRA_PD2_Pos  = 0x2    // Position of PD2 field.
	PWR_PDCRA_PD2_Msk  = 0x4    // Bit mask of PD2 field.
	PWR_PDCRA_PD2      = 0x4    // Bit PD2.
	PWR_PDCRA_PD1_Pos  = 0x1    // Position of PD1 field.
	PWR_PDCRA_PD1_Msk  = 0x2    // Bit mask of PD1 field.
	PWR_PDCRA_PD1      = 0x2    // Bit PD1.
	PWR_PDCRA_PD0_Pos  = 0x0    // Position of PD0 field.
	PWR_PDCRA_PD0_Msk  = 0x1    // Bit mask of PD0 field.
	PWR_PDCRA_PD0      = 0x1    // Bit PD0.

	// PUCRB: Power Port B pull-up control           register
	PWR_PUCRB_PU15_Pos = 0xf    // Position of PU15 field.
	PWR_PUCRB_PU15_Msk = 0x8000 // Bit mask of PU15 field.
	PWR_PUCRB_PU15     = 0x8000 // Bit PU15.
	PWR_PUCRB_PU14_Pos = 0xe    // Position of PU14 field.
	PWR_PUCRB_PU14_Msk = 0x4000 // Bit mask of PU14 field.
	PWR_PUCRB_PU14     = 0x4000 // Bit PU14.
	PWR_PUCRB_PU13_Pos = 0xd    // Position of PU13 field.
	PWR_PUCRB_PU13_Msk = 0x2000 // Bit mask of PU13 field.
	PWR_PUCRB_PU13     = 0x2000 // Bit PU13.
	PWR_PUCRB_PU12_Pos = 0xc    // Position of PU12 field.
	PWR_PUCRB_PU12_Msk = 0x1000 // Bit mask of PU12 field.
	PWR_PUCRB_PU12     = 0x1000 // Bit PU12.
	PWR_PUCRB_PU11_Pos = 0xb    // Position of PU11 field.
	PWR_PUCRB_PU11_Msk = 0x800  // Bit mask of PU11 field.
	PWR_PUCRB_PU11     = 0x800  // Bit PU11.
	PWR_PUCRB_PU10_Pos = 0xa    // Position of PU10 field.
	PWR_PUCRB_PU10_Msk = 0x400  // Bit mask of PU10 field.
	PWR_PUCRB_PU10     = 0x400  // Bit PU10.
	PWR_PUCRB_PU9_Pos  = 0x9    // Position of PU9 field.
	PWR_PUCRB_PU9_Msk  = 0x200  // Bit mask of PU9 field.
	PWR_PUCRB_PU9      = 0x200  // Bit PU9.
	PWR_PUCRB_PU8_Pos  = 0x8    // Position of PU8 field.
	PWR_PUCRB_PU8_Msk  = 0x100  // Bit mask of PU8 field.
	PWR_PUCRB_PU8      = 0x100  // Bit PU8.
	PWR_PUCRB_PU7_Pos  = 0x7    // Position of PU7 field.
	PWR_PUCRB_PU7_Msk  = 0x80   // Bit mask of PU7 field.
	PWR_PUCRB_PU7      = 0x80   // Bit PU7.
	PWR_PUCRB_PU6_Pos  = 0x6    // Position of PU6 field.
	PWR_PUCRB_PU6_Msk  = 0x40   // Bit mask of PU6 field.
	PWR_PUCRB_PU6      = 0x40   // Bit PU6.
	PWR_PUCRB_PU5_Pos  = 0x5    // Position of PU5 field.
	PWR_PUCRB_PU5_Msk  = 0x20   // Bit mask of PU5 field.
	PWR_PUCRB_PU5      = 0x20   // Bit PU5.
	PWR_PUCRB_PU4_Pos  = 0x4    // Position of PU4 field.
	PWR_PUCRB_PU4_Msk  = 0x10   // Bit mask of PU4 field.
	PWR_PUCRB_PU4      = 0x10   // Bit PU4.
	PWR_PUCRB_PU3_Pos  = 0x3    // Position of PU3 field.
	PWR_PUCRB_PU3_Msk  = 0x8    // Bit mask of PU3 field.
	PWR_PUCRB_PU3      = 0x8    // Bit PU3.
	PWR_PUCRB_PU2_Pos  = 0x2    // Position of PU2 field.
	PWR_PUCRB_PU2_Msk  = 0x4    // Bit mask of PU2 field.
	PWR_PUCRB_PU2      = 0x4    // Bit PU2.
	PWR_PUCRB_PU1_Pos  = 0x1    // Position of PU1 field.
	PWR_PUCRB_PU1_Msk  = 0x2    // Bit mask of PU1 field.
	PWR_PUCRB_PU1      = 0x2    // Bit PU1.
	PWR_PUCRB_PU0_Pos  = 0x0    // Position of PU0 field.
	PWR_PUCRB_PU0_Msk  = 0x1    // Bit mask of PU0 field.
	PWR_PUCRB_PU0      = 0x1    // Bit PU0.

	// PDCRB: Power Port B pull-down control           register
	PWR_PDCRB_PD15_Pos = 0xf    // Position of PD15 field.
	PWR_PDCRB_PD15_Msk = 0x8000 // Bit mask of PD15 field.
	PWR_PDCRB_PD15     = 0x8000 // Bit PD15.
	PWR_PDCRB_PD14_Pos = 0xe    // Position of PD14 field.
	PWR_PDCRB_PD14_Msk = 0x4000 // Bit mask of PD14 field.
	PWR_PDCRB_PD14     = 0x4000 // Bit PD14.
	PWR_PDCRB_PD13_Pos = 0xd    // Position of PD13 field.
	PWR_PDCRB_PD13_Msk = 0x2000 // Bit mask of PD13 field.
	PWR_PDCRB_PD13     = 0x2000 // Bit PD13.
	PWR_PDCRB_PD12_Pos = 0xc    // Position of PD12 field.
	PWR_PDCRB_PD12_Msk = 0x1000 // Bit mask of PD12 field.
	PWR_PDCRB_PD12     = 0x1000 // Bit PD12.
	PWR_PDCRB_PD11_Pos = 0xb    // Position of PD11 field.
	PWR_PDCRB_PD11_Msk = 0x800  // Bit mask of PD11 field.
	PWR_PDCRB_PD11     = 0x800  // Bit PD11.
	PWR_PDCRB_PD10_Pos = 0xa    // Position of PD10 field.
	PWR_PDCRB_PD10_Msk = 0x400  // Bit mask of PD10 field.
	PWR_PDCRB_PD10     = 0x400  // Bit PD10.
	PWR_PDCRB_PD9_Pos  = 0x9    // Position of PD9 field.
	PWR_PDCRB_PD9_Msk  = 0x200  // Bit mask of PD9 field.
	PWR_PDCRB_PD9      = 0x200  // Bit PD9.
	PWR_PDCRB_PD8_Pos  = 0x8    // Position of PD8 field.
	PWR_PDCRB_PD8_Msk  = 0x100  // Bit mask of PD8 field.
	PWR_PDCRB_PD8      = 0x100  // Bit PD8.
	PWR_PDCRB_PD7_Pos  = 0x7    // Position of PD7 field.
	PWR_PDCRB_PD7_Msk  = 0x80   // Bit mask of PD7 field.
	PWR_PDCRB_PD7      = 0x80   // Bit PD7.
	PWR_PDCRB_PD6_Pos  = 0x6    // Position of PD6 field.
	PWR_PDCRB_PD6_Msk  = 0x40   // Bit mask of PD6 field.
	PWR_PDCRB_PD6      = 0x40   // Bit PD6.
	PWR_PDCRB_PD5_Pos  = 0x5    // Position of PD5 field.
	PWR_PDCRB_PD5_Msk  = 0x20   // Bit mask of PD5 field.
	PWR_PDCRB_PD5      = 0x20   // Bit PD5.
	PWR_PDCRB_PD3_Pos  = 0x3    // Position of PD3 field.
	PWR_PDCRB_PD3_Msk  = 0x8    // Bit mask of PD3 field.
	PWR_PDCRB_PD3      = 0x8    // Bit PD3.
	PWR_PDCRB_PD2_Pos  = 0x2    // Position of PD2 field.
	PWR_PDCRB_PD2_Msk  = 0x4    // Bit mask of PD2 field.
	PWR_PDCRB_PD2      = 0x4    // Bit PD2.
	PWR_PDCRB_PD1_Pos  = 0x1    // Position of PD1 field.
	PWR_PDCRB_PD1_Msk  = 0x2    // Bit mask of PD1 field.
	PWR_PDCRB_PD1      = 0x2    // Bit PD1.
	PWR_PDCRB_PD0_Pos  = 0x0    // Position of PD0 field.
	PWR_PDCRB_PD0_Msk  = 0x1    // Bit mask of PD0 field.
	PWR_PDCRB_PD0      = 0x1    // Bit PD0.

	// PUCRC: Power Port C pull-up control           register
	PWR_PUCRC_PU15_Pos = 0xf    // Position of PU15 field.
	PWR_PUCRC_PU15_Msk = 0x8000 // Bit mask of PU15 field.
	PWR_PUCRC_PU15     = 0x8000 // Bit PU15.
	PWR_PUCRC_PU14_Pos = 0xe    // Position of PU14 field.
	PWR_PUCRC_PU14_Msk = 0x4000 // Bit mask of PU14 field.
	PWR_PUCRC_PU14     = 0x4000 // Bit PU14.
	PWR_PUCRC_PU13_Pos = 0xd    // Position of PU13 field.
	PWR_PUCRC_PU13_Msk = 0x2000 // Bit mask of PU13 field.
	PWR_PUCRC_PU13     = 0x2000 // Bit PU13.
	PWR_PUCRC_PU12_Pos = 0xc    // Position of PU12 field.
	PWR_PUCRC_PU12_Msk = 0x1000 // Bit mask of PU12 field.
	PWR_PUCRC_PU12     = 0x1000 // Bit PU12.
	PWR_PUCRC_PU11_Pos = 0xb    // Position of PU11 field.
	PWR_PUCRC_PU11_Msk = 0x800  // Bit mask of PU11 field.
	PWR_PUCRC_PU11     = 0x800  // Bit PU11.
	PWR_PUCRC_PU10_Pos = 0xa    // Position of PU10 field.
	PWR_PUCRC_PU10_Msk = 0x400  // Bit mask of PU10 field.
	PWR_PUCRC_PU10     = 0x400  // Bit PU10.
	PWR_PUCRC_PU9_Pos  = 0x9    // Position of PU9 field.
	PWR_PUCRC_PU9_Msk  = 0x200  // Bit mask of PU9 field.
	PWR_PUCRC_PU9      = 0x200  // Bit PU9.
	PWR_PUCRC_PU8_Pos  = 0x8    // Position of PU8 field.
	PWR_PUCRC_PU8_Msk  = 0x100  // Bit mask of PU8 field.
	PWR_PUCRC_PU8      = 0x100  // Bit PU8.
	PWR_PUCRC_PU7_Pos  = 0x7    // Position of PU7 field.
	PWR_PUCRC_PU7_Msk  = 0x80   // Bit mask of PU7 field.
	PWR_PUCRC_PU7      = 0x80   // Bit PU7.
	PWR_PUCRC_PU6_Pos  = 0x6    // Position of PU6 field.
	PWR_PUCRC_PU6_Msk  = 0x40   // Bit mask of PU6 field.
	PWR_PUCRC_PU6      = 0x40   // Bit PU6.
	PWR_PUCRC_PU5_Pos  = 0x5    // Position of PU5 field.
	PWR_PUCRC_PU5_Msk  = 0x20   // Bit mask of PU5 field.
	PWR_PUCRC_PU5      = 0x20   // Bit PU5.
	PWR_PUCRC_PU4_Pos  = 0x4    // Position of PU4 field.
	PWR_PUCRC_PU4_Msk  = 0x10   // Bit mask of PU4 field.
	PWR_PUCRC_PU4      = 0x10   // Bit PU4.
	PWR_PUCRC_PU3_Pos  = 0x3    // Position of PU3 field.
	PWR_PUCRC_PU3_Msk  = 0x8    // Bit mask of PU3 field.
	PWR_PUCRC_PU3      = 0x8    // Bit PU3.
	PWR_PUCRC_PU2_Pos  = 0x2    // Position of PU2 field.
	PWR_PUCRC_PU2_Msk  = 0x4    // Bit mask of PU2 field.
	PWR_PUCRC_PU2      = 0x4    // Bit PU2.
	PWR_PUCRC_PU1_Pos  = 0x1    // Position of PU1 field.
	PWR_PUCRC_PU1_Msk  = 0x2    // Bit mask of PU1 field.
	PWR_PUCRC_PU1      = 0x2    // Bit PU1.
	PWR_PUCRC_PU0_Pos  = 0x0    // Position of PU0 field.
	PWR_PUCRC_PU0_Msk  = 0x1    // Bit mask of PU0 field.
	PWR_PUCRC_PU0      = 0x1    // Bit PU0.

	// PDCRC: Power Port C pull-down control           register
	PWR_PDCRC_PD15_Pos = 0xf    // Position of PD15 field.
	PWR_PDCRC_PD15_Msk = 0x8000 // Bit mask of PD15 field.
	PWR_PDCRC_PD15     = 0x8000 // Bit PD15.
	PWR_PDCRC_PD14_Pos = 0xe    // Position of PD14 field.
	PWR_PDCRC_PD14_Msk = 0x4000 // Bit mask of PD14 field.
	PWR_PDCRC_PD14     = 0x4000 // Bit PD14.
	PWR_PDCRC_PD13_Pos = 0xd    // Position of PD13 field.
	PWR_PDCRC_PD13_Msk = 0x2000 // Bit mask of PD13 field.
	PWR_PDCRC_PD13     = 0x2000 // Bit PD13.
	PWR_PDCRC_PD12_Pos = 0xc    // Position of PD12 field.
	PWR_PDCRC_PD12_Msk = 0x1000 // Bit mask of PD12 field.
	PWR_PDCRC_PD12     = 0x1000 // Bit PD12.
	PWR_PDCRC_PD11_Pos = 0xb    // Position of PD11 field.
	PWR_PDCRC_PD11_Msk = 0x800  // Bit mask of PD11 field.
	PWR_PDCRC_PD11     = 0x800  // Bit PD11.
	PWR_PDCRC_PD10_Pos = 0xa    // Position of PD10 field.
	PWR_PDCRC_PD10_Msk = 0x400  // Bit mask of PD10 field.
	PWR_PDCRC_PD10     = 0x400  // Bit PD10.
	PWR_PDCRC_PD9_Pos  = 0x9    // Position of PD9 field.
	PWR_PDCRC_PD9_Msk  = 0x200  // Bit mask of PD9 field.
	PWR_PDCRC_PD9      = 0x200  // Bit PD9.
	PWR_PDCRC_PD8_Pos  = 0x8    // Position of PD8 field.
	PWR_PDCRC_PD8_Msk  = 0x100  // Bit mask of PD8 field.
	PWR_PDCRC_PD8      = 0x100  // Bit PD8.
	PWR_PDCRC_PD7_Pos  = 0x7    // Position of PD7 field.
	PWR_PDCRC_PD7_Msk  = 0x80   // Bit mask of PD7 field.
	PWR_PDCRC_PD7      = 0x80   // Bit PD7.
	PWR_PDCRC_PD6_Pos  = 0x6    // Position of PD6 field.
	PWR_PDCRC_PD6_Msk  = 0x40   // Bit mask of PD6 field.
	PWR_PDCRC_PD6      = 0x40   // Bit PD6.
	PWR_PDCRC_PD5_Pos  = 0x5    // Position of PD5 field.
	PWR_PDCRC_PD5_Msk  = 0x20   // Bit mask of PD5 field.
	PWR_PDCRC_PD5      = 0x20   // Bit PD5.
	PWR_PDCRC_PD4_Pos  = 0x4    // Position of PD4 field.
	PWR_PDCRC_PD4_Msk  = 0x10   // Bit mask of PD4 field.
	PWR_PDCRC_PD4      = 0x10   // Bit PD4.
	PWR_PDCRC_PD3_Pos  = 0x3    // Position of PD3 field.
	PWR_PDCRC_PD3_Msk  = 0x8    // Bit mask of PD3 field.
	PWR_PDCRC_PD3      = 0x8    // Bit PD3.
	PWR_PDCRC_PD2_Pos  = 0x2    // Position of PD2 field.
	PWR_PDCRC_PD2_Msk  = 0x4    // Bit mask of PD2 field.
	PWR_PDCRC_PD2      = 0x4    // Bit PD2.
	PWR_PDCRC_PD1_Pos  = 0x1    // Position of PD1 field.
	PWR_PDCRC_PD1_Msk  = 0x2    // Bit mask of PD1 field.
	PWR_PDCRC_PD1      = 0x2    // Bit PD1.
	PWR_PDCRC_PD0_Pos  = 0x0    // Position of PD0 field.
	PWR_PDCRC_PD0_Msk  = 0x1    // Bit mask of PD0 field.
	PWR_PDCRC_PD0      = 0x1    // Bit PD0.

	// PUCRD: Power Port D pull-up control           register
	PWR_PUCRD_PU15_Pos = 0xf    // Position of PU15 field.
	PWR_PUCRD_PU15_Msk = 0x8000 // Bit mask of PU15 field.
	PWR_PUCRD_PU15     = 0x8000 // Bit PU15.
	PWR_PUCRD_PU14_Pos = 0xe    // Position of PU14 field.
	PWR_PUCRD_PU14_Msk = 0x4000 // Bit mask of PU14 field.
	PWR_PUCRD_PU14     = 0x4000 // Bit PU14.
	PWR_PUCRD_PU13_Pos = 0xd    // Position of PU13 field.
	PWR_PUCRD_PU13_Msk = 0x2000 // Bit mask of PU13 field.
	PWR_PUCRD_PU13     = 0x2000 // Bit PU13.
	PWR_PUCRD_PU12_Pos = 0xc    // Position of PU12 field.
	PWR_PUCRD_PU12_Msk = 0x1000 // Bit mask of PU12 field.
	PWR_PUCRD_PU12     = 0x1000 // Bit PU12.
	PWR_PUCRD_PU11_Pos = 0xb    // Position of PU11 field.
	PWR_PUCRD_PU11_Msk = 0x800  // Bit mask of PU11 field.
	PWR_PUCRD_PU11     = 0x800  // Bit PU11.
	PWR_PUCRD_PU10_Pos = 0xa    // Position of PU10 field.
	PWR_PUCRD_PU10_Msk = 0x400  // Bit mask of PU10 field.
	PWR_PUCRD_PU10     = 0x400  // Bit PU10.
	PWR_PUCRD_PU9_Pos  = 0x9    // Position of PU9 field.
	PWR_PUCRD_PU9_Msk  = 0x200  // Bit mask of PU9 field.
	PWR_PUCRD_PU9      = 0x200  // Bit PU9.
	PWR_PUCRD_PU8_Pos  = 0x8    // Position of PU8 field.
	PWR_PUCRD_PU8_Msk  = 0x100  // Bit mask of PU8 field.
	PWR_PUCRD_PU8      = 0x100  // Bit PU8.
	PWR_PUCRD_PU7_Pos  = 0x7    // Position of PU7 field.
	PWR_PUCRD_PU7_Msk  = 0x80   // Bit mask of PU7 field.
	PWR_PUCRD_PU7      = 0x80   // Bit PU7.
	PWR_PUCRD_PU6_Pos  = 0x6    // Position of PU6 field.
	PWR_PUCRD_PU6_Msk  = 0x40   // Bit mask of PU6 field.
	PWR_PUCRD_PU6      = 0x40   // Bit PU6.
	PWR_PUCRD_PU5_Pos  = 0x5    // Position of PU5 field.
	PWR_PUCRD_PU5_Msk  = 0x20   // Bit mask of PU5 field.
	PWR_PUCRD_PU5      = 0x20   // Bit PU5.
	PWR_PUCRD_PU4_Pos  = 0x4    // Position of PU4 field.
	PWR_PUCRD_PU4_Msk  = 0x10   // Bit mask of PU4 field.
	PWR_PUCRD_PU4      = 0x10   // Bit PU4.
	PWR_PUCRD_PU3_Pos  = 0x3    // Position of PU3 field.
	PWR_PUCRD_PU3_Msk  = 0x8    // Bit mask of PU3 field.
	PWR_PUCRD_PU3      = 0x8    // Bit PU3.
	PWR_PUCRD_PU2_Pos  = 0x2    // Position of PU2 field.
	PWR_PUCRD_PU2_Msk  = 0x4    // Bit mask of PU2 field.
	PWR_PUCRD_PU2      = 0x4    // Bit PU2.
	PWR_PUCRD_PU1_Pos  = 0x1    // Position of PU1 field.
	PWR_PUCRD_PU1_Msk  = 0x2    // Bit mask of PU1 field.
	PWR_PUCRD_PU1      = 0x2    // Bit PU1.
	PWR_PUCRD_PU0_Pos  = 0x0    // Position of PU0 field.
	PWR_PUCRD_PU0_Msk  = 0x1    // Bit mask of PU0 field.
	PWR_PUCRD_PU0      = 0x1    // Bit PU0.

	// PDCRD: Power Port D pull-down control           register
	PWR_PDCRD_PD15_Pos = 0xf    // Position of PD15 field.
	PWR_PDCRD_PD15_Msk = 0x8000 // Bit mask of PD15 field.
	PWR_PDCRD_PD15     = 0x8000 // Bit PD15.
	PWR_PDCRD_PD14_Pos = 0xe    // Position of PD14 field.
	PWR_PDCRD_PD14_Msk = 0x4000 // Bit mask of PD14 field.
	PWR_PDCRD_PD14     = 0x4000 // Bit PD14.
	PWR_PDCRD_PD13_Pos = 0xd    // Position of PD13 field.
	PWR_PDCRD_PD13_Msk = 0x2000 // Bit mask of PD13 field.
	PWR_PDCRD_PD13     = 0x2000 // Bit PD13.
	PWR_PDCRD_PD12_Pos = 0xc    // Position of PD12 field.
	PWR_PDCRD_PD12_Msk = 0x1000 // Bit mask of PD12 field.
	PWR_PDCRD_PD12     = 0x1000 // Bit PD12.
	PWR_PDCRD_PD11_Pos = 0xb    // Position of PD11 field.
	PWR_PDCRD_PD11_Msk = 0x800  // Bit mask of PD11 field.
	PWR_PDCRD_PD11     = 0x800  // Bit PD11.
	PWR_PDCRD_PD10_Pos = 0xa    // Position of PD10 field.
	PWR_PDCRD_PD10_Msk = 0x400  // Bit mask of PD10 field.
	PWR_PDCRD_PD10     = 0x400  // Bit PD10.
	PWR_PDCRD_PD9_Pos  = 0x9    // Position of PD9 field.
	PWR_PDCRD_PD9_Msk  = 0x200  // Bit mask of PD9 field.
	PWR_PDCRD_PD9      = 0x200  // Bit PD9.
	PWR_PDCRD_PD8_Pos  = 0x8    // Position of PD8 field.
	PWR_PDCRD_PD8_Msk  = 0x100  // Bit mask of PD8 field.
	PWR_PDCRD_PD8      = 0x100  // Bit PD8.
	PWR_PDCRD_PD7_Pos  = 0x7    // Position of PD7 field.
	PWR_PDCRD_PD7_Msk  = 0x80   // Bit mask of PD7 field.
	PWR_PDCRD_PD7      = 0x80   // Bit PD7.
	PWR_PDCRD_PD6_Pos  = 0x6    // Position of PD6 field.
	PWR_PDCRD_PD6_Msk  = 0x40   // Bit mask of PD6 field.
	PWR_PDCRD_PD6      = 0x40   // Bit PD6.
	PWR_PDCRD_PD5_Pos  = 0x5    // Position of PD5 field.
	PWR_PDCRD_PD5_Msk  = 0x20   // Bit mask of PD5 field.
	PWR_PDCRD_PD5      = 0x20   // Bit PD5.
	PWR_PDCRD_PD4_Pos  = 0x4    // Position of PD4 field.
	PWR_PDCRD_PD4_Msk  = 0x10   // Bit mask of PD4 field.
	PWR_PDCRD_PD4      = 0x10   // Bit PD4.
	PWR_PDCRD_PD3_Pos  = 0x3    // Position of PD3 field.
	PWR_PDCRD_PD3_Msk  = 0x8    // Bit mask of PD3 field.
	PWR_PDCRD_PD3      = 0x8    // Bit PD3.
	PWR_PDCRD_PD2_Pos  = 0x2    // Position of PD2 field.
	PWR_PDCRD_PD2_Msk  = 0x4    // Bit mask of PD2 field.
	PWR_PDCRD_PD2      = 0x4    // Bit PD2.
	PWR_PDCRD_PD1_Pos  = 0x1    // Position of PD1 field.
	PWR_PDCRD_PD1_Msk  = 0x2    // Bit mask of PD1 field.
	PWR_PDCRD_PD1      = 0x2    // Bit PD1.
	PWR_PDCRD_PD0_Pos  = 0x0    // Position of PD0 field.
	PWR_PDCRD_PD0_Msk  = 0x1    // Bit mask of PD0 field.
	PWR_PDCRD_PD0      = 0x1    // Bit PD0.

	// PUCRE: Power Port E pull-up control           register
	PWR_PUCRE_PU15_Pos = 0xf    // Position of PU15 field.
	PWR_PUCRE_PU15_Msk = 0x8000 // Bit mask of PU15 field.
	PWR_PUCRE_PU15     = 0x8000 // Bit PU15.
	PWR_PUCRE_PU14_Pos = 0xe    // Position of PU14 field.
	PWR_PUCRE_PU14_Msk = 0x4000 // Bit mask of PU14 field.
	PWR_PUCRE_PU14     = 0x4000 // Bit PU14.
	PWR_PUCRE_PU13_Pos = 0xd    // Position of PU13 field.
	PWR_PUCRE_PU13_Msk = 0x2000 // Bit mask of PU13 field.
	PWR_PUCRE_PU13     = 0x2000 // Bit PU13.
	PWR_PUCRE_PU12_Pos = 0xc    // Position of PU12 field.
	PWR_PUCRE_PU12_Msk = 0x1000 // Bit mask of PU12 field.
	PWR_PUCRE_PU12     = 0x1000 // Bit PU12.
	PWR_PUCRE_PU11_Pos = 0xb    // Position of PU11 field.
	PWR_PUCRE_PU11_Msk = 0x800  // Bit mask of PU11 field.
	PWR_PUCRE_PU11     = 0x800  // Bit PU11.
	PWR_PUCRE_PU10_Pos = 0xa    // Position of PU10 field.
	PWR_PUCRE_PU10_Msk = 0x400  // Bit mask of PU10 field.
	PWR_PUCRE_PU10     = 0x400  // Bit PU10.
	PWR_PUCRE_PU9_Pos  = 0x9    // Position of PU9 field.
	PWR_PUCRE_PU9_Msk  = 0x200  // Bit mask of PU9 field.
	PWR_PUCRE_PU9      = 0x200  // Bit PU9.
	PWR_PUCRE_PU8_Pos  = 0x8    // Position of PU8 field.
	PWR_PUCRE_PU8_Msk  = 0x100  // Bit mask of PU8 field.
	PWR_PUCRE_PU8      = 0x100  // Bit PU8.
	PWR_PUCRE_PU7_Pos  = 0x7    // Position of PU7 field.
	PWR_PUCRE_PU7_Msk  = 0x80   // Bit mask of PU7 field.
	PWR_PUCRE_PU7      = 0x80   // Bit PU7.
	PWR_PUCRE_PU6_Pos  = 0x6    // Position of PU6 field.
	PWR_PUCRE_PU6_Msk  = 0x40   // Bit mask of PU6 field.
	PWR_PUCRE_PU6      = 0x40   // Bit PU6.
	PWR_PUCRE_PU5_Pos  = 0x5    // Position of PU5 field.
	PWR_PUCRE_PU5_Msk  = 0x20   // Bit mask of PU5 field.
	PWR_PUCRE_PU5      = 0x20   // Bit PU5.
	PWR_PUCRE_PU4_Pos  = 0x4    // Position of PU4 field.
	PWR_PUCRE_PU4_Msk  = 0x10   // Bit mask of PU4 field.
	PWR_PUCRE_PU4      = 0x10   // Bit PU4.
	PWR_PUCRE_PU3_Pos  = 0x3    // Position of PU3 field.
	PWR_PUCRE_PU3_Msk  = 0x8    // Bit mask of PU3 field.
	PWR_PUCRE_PU3      = 0x8    // Bit PU3.
	PWR_PUCRE_PU2_Pos  = 0x2    // Position of PU2 field.
	PWR_PUCRE_PU2_Msk  = 0x4    // Bit mask of PU2 field.
	PWR_PUCRE_PU2      = 0x4    // Bit PU2.
	PWR_PUCRE_PU1_Pos  = 0x1    // Position of PU1 field.
	PWR_PUCRE_PU1_Msk  = 0x2    // Bit mask of PU1 field.
	PWR_PUCRE_PU1      = 0x2    // Bit PU1.
	PWR_PUCRE_PU0_Pos  = 0x0    // Position of PU0 field.
	PWR_PUCRE_PU0_Msk  = 0x1    // Bit mask of PU0 field.
	PWR_PUCRE_PU0      = 0x1    // Bit PU0.

	// PDCRE: Power Port E pull-down control           register
	PWR_PDCRE_PD15_Pos = 0xf    // Position of PD15 field.
	PWR_PDCRE_PD15_Msk = 0x8000 // Bit mask of PD15 field.
	PWR_PDCRE_PD15     = 0x8000 // Bit PD15.
	PWR_PDCRE_PD14_Pos = 0xe    // Position of PD14 field.
	PWR_PDCRE_PD14_Msk = 0x4000 // Bit mask of PD14 field.
	PWR_PDCRE_PD14     = 0x4000 // Bit PD14.
	PWR_PDCRE_PD13_Pos = 0xd    // Position of PD13 field.
	PWR_PDCRE_PD13_Msk = 0x2000 // Bit mask of PD13 field.
	PWR_PDCRE_PD13     = 0x2000 // Bit PD13.
	PWR_PDCRE_PD12_Pos = 0xc    // Position of PD12 field.
	PWR_PDCRE_PD12_Msk = 0x1000 // Bit mask of PD12 field.
	PWR_PDCRE_PD12     = 0x1000 // Bit PD12.
	PWR_PDCRE_PD11_Pos = 0xb    // Position of PD11 field.
	PWR_PDCRE_PD11_Msk = 0x800  // Bit mask of PD11 field.
	PWR_PDCRE_PD11     = 0x800  // Bit PD11.
	PWR_PDCRE_PD10_Pos = 0xa    // Position of PD10 field.
	PWR_PDCRE_PD10_Msk = 0x400  // Bit mask of PD10 field.
	PWR_PDCRE_PD10     = 0x400  // Bit PD10.
	PWR_PDCRE_PD9_Pos  = 0x9    // Position of PD9 field.
	PWR_PDCRE_PD9_Msk  = 0x200  // Bit mask of PD9 field.
	PWR_PDCRE_PD9      = 0x200  // Bit PD9.
	PWR_PDCRE_PD8_Pos  = 0x8    // Position of PD8 field.
	PWR_PDCRE_PD8_Msk  = 0x100  // Bit mask of PD8 field.
	PWR_PDCRE_PD8      = 0x100  // Bit PD8.
	PWR_PDCRE_PD7_Pos  = 0x7    // Position of PD7 field.
	PWR_PDCRE_PD7_Msk  = 0x80   // Bit mask of PD7 field.
	PWR_PDCRE_PD7      = 0x80   // Bit PD7.
	PWR_PDCRE_PD6_Pos  = 0x6    // Position of PD6 field.
	PWR_PDCRE_PD6_Msk  = 0x40   // Bit mask of PD6 field.
	PWR_PDCRE_PD6      = 0x40   // Bit PD6.
	PWR_PDCRE_PD5_Pos  = 0x5    // Position of PD5 field.
	PWR_PDCRE_PD5_Msk  = 0x20   // Bit mask of PD5 field.
	PWR_PDCRE_PD5      = 0x20   // Bit PD5.
	PWR_PDCRE_PD4_Pos  = 0x4    // Position of PD4 field.
	PWR_PDCRE_PD4_Msk  = 0x10   // Bit mask of PD4 field.
	PWR_PDCRE_PD4      = 0x10   // Bit PD4.
	PWR_PDCRE_PD3_Pos  = 0x3    // Position of PD3 field.
	PWR_PDCRE_PD3_Msk  = 0x8    // Bit mask of PD3 field.
	PWR_PDCRE_PD3      = 0x8    // Bit PD3.
	PWR_PDCRE_PD2_Pos  = 0x2    // Position of PD2 field.
	PWR_PDCRE_PD2_Msk  = 0x4    // Bit mask of PD2 field.
	PWR_PDCRE_PD2      = 0x4    // Bit PD2.
	PWR_PDCRE_PD1_Pos  = 0x1    // Position of PD1 field.
	PWR_PDCRE_PD1_Msk  = 0x2    // Bit mask of PD1 field.
	PWR_PDCRE_PD1      = 0x2    // Bit PD1.
	PWR_PDCRE_PD0_Pos  = 0x0    // Position of PD0 field.
	PWR_PDCRE_PD0_Msk  = 0x1    // Bit mask of PD0 field.
	PWR_PDCRE_PD0      = 0x1    // Bit PD0.

	// PUCRF: Power Port F pull-up control           register
	PWR_PUCRF_PU15_Pos = 0xf    // Position of PU15 field.
	PWR_PUCRF_PU15_Msk = 0x8000 // Bit mask of PU15 field.
	PWR_PUCRF_PU15     = 0x8000 // Bit PU15.
	PWR_PUCRF_PU14_Pos = 0xe    // Position of PU14 field.
	PWR_PUCRF_PU14_Msk = 0x4000 // Bit mask of PU14 field.
	PWR_PUCRF_PU14     = 0x4000 // Bit PU14.
	PWR_PUCRF_PU13_Pos = 0xd    // Position of PU13 field.
	PWR_PUCRF_PU13_Msk = 0x2000 // Bit mask of PU13 field.
	PWR_PUCRF_PU13     = 0x2000 // Bit PU13.
	PWR_PUCRF_PU12_Pos = 0xc    // Position of PU12 field.
	PWR_PUCRF_PU12_Msk = 0x1000 // Bit mask of PU12 field.
	PWR_PUCRF_PU12     = 0x1000 // Bit PU12.
	PWR_PUCRF_PU11_Pos = 0xb    // Position of PU11 field.
	PWR_PUCRF_PU11_Msk = 0x800  // Bit mask of PU11 field.
	PWR_PUCRF_PU11     = 0x800  // Bit PU11.
	PWR_PUCRF_PU10_Pos = 0xa    // Position of PU10 field.
	PWR_PUCRF_PU10_Msk = 0x400  // Bit mask of PU10 field.
	PWR_PUCRF_PU10     = 0x400  // Bit PU10.
	PWR_PUCRF_PU9_Pos  = 0x9    // Position of PU9 field.
	PWR_PUCRF_PU9_Msk  = 0x200  // Bit mask of PU9 field.
	PWR_PUCRF_PU9      = 0x200  // Bit PU9.
	PWR_PUCRF_PU8_Pos  = 0x8    // Position of PU8 field.
	PWR_PUCRF_PU8_Msk  = 0x100  // Bit mask of PU8 field.
	PWR_PUCRF_PU8      = 0x100  // Bit PU8.
	PWR_PUCRF_PU7_Pos  = 0x7    // Position of PU7 field.
	PWR_PUCRF_PU7_Msk  = 0x80   // Bit mask of PU7 field.
	PWR_PUCRF_PU7      = 0x80   // Bit PU7.
	PWR_PUCRF_PU6_Pos  = 0x6    // Position of PU6 field.
	PWR_PUCRF_PU6_Msk  = 0x40   // Bit mask of PU6 field.
	PWR_PUCRF_PU6      = 0x40   // Bit PU6.
	PWR_PUCRF_PU5_Pos  = 0x5    // Position of PU5 field.
	PWR_PUCRF_PU5_Msk  = 0x20   // Bit mask of PU5 field.
	PWR_PUCRF_PU5      = 0x20   // Bit PU5.
	PWR_PUCRF_PU4_Pos  = 0x4    // Position of PU4 field.
	PWR_PUCRF_PU4_Msk  = 0x10   // Bit mask of PU4 field.
	PWR_PUCRF_PU4      = 0x10   // Bit PU4.
	PWR_PUCRF_PU3_Pos  = 0x3    // Position of PU3 field.
	PWR_PUCRF_PU3_Msk  = 0x8    // Bit mask of PU3 field.
	PWR_PUCRF_PU3      = 0x8    // Bit PU3.
	PWR_PUCRF_PU2_Pos  = 0x2    // Position of PU2 field.
	PWR_PUCRF_PU2_Msk  = 0x4    // Bit mask of PU2 field.
	PWR_PUCRF_PU2      = 0x4    // Bit PU2.
	PWR_PUCRF_PU1_Pos  = 0x1    // Position of PU1 field.
	PWR_PUCRF_PU1_Msk  = 0x2    // Bit mask of PU1 field.
	PWR_PUCRF_PU1      = 0x2    // Bit PU1.
	PWR_PUCRF_PU0_Pos  = 0x0    // Position of PU0 field.
	PWR_PUCRF_PU0_Msk  = 0x1    // Bit mask of PU0 field.
	PWR_PUCRF_PU0      = 0x1    // Bit PU0.

	// PDCRF: Power Port F pull-down control           register
	PWR_PDCRF_PD15_Pos = 0xf    // Position of PD15 field.
	PWR_PDCRF_PD15_Msk = 0x8000 // Bit mask of PD15 field.
	PWR_PDCRF_PD15     = 0x8000 // Bit PD15.
	PWR_PDCRF_PD14_Pos = 0xe    // Position of PD14 field.
	PWR_PDCRF_PD14_Msk = 0x4000 // Bit mask of PD14 field.
	PWR_PDCRF_PD14     = 0x4000 // Bit PD14.
	PWR_PDCRF_PD13_Pos = 0xd    // Position of PD13 field.
	PWR_PDCRF_PD13_Msk = 0x2000 // Bit mask of PD13 field.
	PWR_PDCRF_PD13     = 0x2000 // Bit PD13.
	PWR_PDCRF_PD12_Pos = 0xc    // Position of PD12 field.
	PWR_PDCRF_PD12_Msk = 0x1000 // Bit mask of PD12 field.
	PWR_PDCRF_PD12     = 0x1000 // Bit PD12.
	PWR_PDCRF_PD11_Pos = 0xb    // Position of PD11 field.
	PWR_PDCRF_PD11_Msk = 0x800  // Bit mask of PD11 field.
	PWR_PDCRF_PD11     = 0x800  // Bit PD11.
	PWR_PDCRF_PD10_Pos = 0xa    // Position of PD10 field.
	PWR_PDCRF_PD10_Msk = 0x400  // Bit mask of PD10 field.
	PWR_PDCRF_PD10     = 0x400  // Bit PD10.
	PWR_PDCRF_PD9_Pos  = 0x9    // Position of PD9 field.
	PWR_PDCRF_PD9_Msk  = 0x200  // Bit mask of PD9 field.
	PWR_PDCRF_PD9      = 0x200  // Bit PD9.
	PWR_PDCRF_PD8_Pos  = 0x8    // Position of PD8 field.
	PWR_PDCRF_PD8_Msk  = 0x100  // Bit mask of PD8 field.
	PWR_PDCRF_PD8      = 0x100  // Bit PD8.
	PWR_PDCRF_PD7_Pos  = 0x7    // Position of PD7 field.
	PWR_PDCRF_PD7_Msk  = 0x80   // Bit mask of PD7 field.
	PWR_PDCRF_PD7      = 0x80   // Bit PD7.
	PWR_PDCRF_PD6_Pos  = 0x6    // Position of PD6 field.
	PWR_PDCRF_PD6_Msk  = 0x40   // Bit mask of PD6 field.
	PWR_PDCRF_PD6      = 0x40   // Bit PD6.
	PWR_PDCRF_PD5_Pos  = 0x5    // Position of PD5 field.
	PWR_PDCRF_PD5_Msk  = 0x20   // Bit mask of PD5 field.
	PWR_PDCRF_PD5      = 0x20   // Bit PD5.
	PWR_PDCRF_PD4_Pos  = 0x4    // Position of PD4 field.
	PWR_PDCRF_PD4_Msk  = 0x10   // Bit mask of PD4 field.
	PWR_PDCRF_PD4      = 0x10   // Bit PD4.
	PWR_PDCRF_PD3_Pos  = 0x3    // Position of PD3 field.
	PWR_PDCRF_PD3_Msk  = 0x8    // Bit mask of PD3 field.
	PWR_PDCRF_PD3      = 0x8    // Bit PD3.
	PWR_PDCRF_PD2_Pos  = 0x2    // Position of PD2 field.
	PWR_PDCRF_PD2_Msk  = 0x4    // Bit mask of PD2 field.
	PWR_PDCRF_PD2      = 0x4    // Bit PD2.
	PWR_PDCRF_PD1_Pos  = 0x1    // Position of PD1 field.
	PWR_PDCRF_PD1_Msk  = 0x2    // Bit mask of PD1 field.
	PWR_PDCRF_PD1      = 0x2    // Bit PD1.
	PWR_PDCRF_PD0_Pos  = 0x0    // Position of PD0 field.
	PWR_PDCRF_PD0_Msk  = 0x1    // Bit mask of PD0 field.
	PWR_PDCRF_PD0      = 0x1    // Bit PD0.

	// PUCRG: Power Port G pull-up control           register
	PWR_PUCRG_PU10_Pos = 0xa   // Position of PU10 field.
	PWR_PUCRG_PU10_Msk = 0x400 // Bit mask of PU10 field.
	PWR_PUCRG_PU10     = 0x400 // Bit PU10.
	PWR_PUCRG_PU9_Pos  = 0x9   // Position of PU9 field.
	PWR_PUCRG_PU9_Msk  = 0x200 // Bit mask of PU9 field.
	PWR_PUCRG_PU9      = 0x200 // Bit PU9.
	PWR_PUCRG_PU8_Pos  = 0x8   // Position of PU8 field.
	PWR_PUCRG_PU8_Msk  = 0x100 // Bit mask of PU8 field.
	PWR_PUCRG_PU8      = 0x100 // Bit PU8.
	PWR_PUCRG_PU7_Pos  = 0x7   // Position of PU7 field.
	PWR_PUCRG_PU7_Msk  = 0x80  // Bit mask of PU7 field.
	PWR_PUCRG_PU7      = 0x80  // Bit PU7.
	PWR_PUCRG_PU6_Pos  = 0x6   // Position of PU6 field.
	PWR_PUCRG_PU6_Msk  = 0x40  // Bit mask of PU6 field.
	PWR_PUCRG_PU6      = 0x40  // Bit PU6.
	PWR_PUCRG_PU5_Pos  = 0x5   // Position of PU5 field.
	PWR_PUCRG_PU5_Msk  = 0x20  // Bit mask of PU5 field.
	PWR_PUCRG_PU5      = 0x20  // Bit PU5.
	PWR_PUCRG_PU4_Pos  = 0x4   // Position of PU4 field.
	PWR_PUCRG_PU4_Msk  = 0x10  // Bit mask of PU4 field.
	PWR_PUCRG_PU4      = 0x10  // Bit PU4.
	PWR_PUCRG_PU3_Pos  = 0x3   // Position of PU3 field.
	PWR_PUCRG_PU3_Msk  = 0x8   // Bit mask of PU3 field.
	PWR_PUCRG_PU3      = 0x8   // Bit PU3.
	PWR_PUCRG_PU2_Pos  = 0x2   // Position of PU2 field.
	PWR_PUCRG_PU2_Msk  = 0x4   // Bit mask of PU2 field.
	PWR_PUCRG_PU2      = 0x4   // Bit PU2.
	PWR_PUCRG_PU1_Pos  = 0x1   // Position of PU1 field.
	PWR_PUCRG_PU1_Msk  = 0x2   // Bit mask of PU1 field.
	PWR_PUCRG_PU1      = 0x2   // Bit PU1.
	PWR_PUCRG_PU0_Pos  = 0x0   // Position of PU0 field.
	PWR_PUCRG_PU0_Msk  = 0x1   // Bit mask of PU0 field.
	PWR_PUCRG_PU0      = 0x1   // Bit PU0.

	// PDCRG: Power Port G pull-down control           register
	PWR_PDCRG_PD10_Pos = 0xa   // Position of PD10 field.
	PWR_PDCRG_PD10_Msk = 0x400 // Bit mask of PD10 field.
	PWR_PDCRG_PD10     = 0x400 // Bit PD10.
	PWR_PDCRG_PD9_Pos  = 0x9   // Position of PD9 field.
	PWR_PDCRG_PD9_Msk  = 0x200 // Bit mask of PD9 field.
	PWR_PDCRG_PD9      = 0x200 // Bit PD9.
	PWR_PDCRG_PD8_Pos  = 0x8   // Position of PD8 field.
	PWR_PDCRG_PD8_Msk  = 0x100 // Bit mask of PD8 field.
	PWR_PDCRG_PD8      = 0x100 // Bit PD8.
	PWR_PDCRG_PD7_Pos  = 0x7   // Position of PD7 field.
	PWR_PDCRG_PD7_Msk  = 0x80  // Bit mask of PD7 field.
	PWR_PDCRG_PD7      = 0x80  // Bit PD7.
	PWR_PDCRG_PD6_Pos  = 0x6   // Position of PD6 field.
	PWR_PDCRG_PD6_Msk  = 0x40  // Bit mask of PD6 field.
	PWR_PDCRG_PD6      = 0x40  // Bit PD6.
	PWR_PDCRG_PD5_Pos  = 0x5   // Position of PD5 field.
	PWR_PDCRG_PD5_Msk  = 0x20  // Bit mask of PD5 field.
	PWR_PDCRG_PD5      = 0x20  // Bit PD5.
	PWR_PDCRG_PD4_Pos  = 0x4   // Position of PD4 field.
	PWR_PDCRG_PD4_Msk  = 0x10  // Bit mask of PD4 field.
	PWR_PDCRG_PD4      = 0x10  // Bit PD4.
	PWR_PDCRG_PD3_Pos  = 0x3   // Position of PD3 field.
	PWR_PDCRG_PD3_Msk  = 0x8   // Bit mask of PD3 field.
	PWR_PDCRG_PD3      = 0x8   // Bit PD3.
	PWR_PDCRG_PD2_Pos  = 0x2   // Position of PD2 field.
	PWR_PDCRG_PD2_Msk  = 0x4   // Bit mask of PD2 field.
	PWR_PDCRG_PD2      = 0x4   // Bit PD2.
	PWR_PDCRG_PD1_Pos  = 0x1   // Position of PD1 field.
	PWR_PDCRG_PD1_Msk  = 0x2   // Bit mask of PD1 field.
	PWR_PDCRG_PD1      = 0x2   // Bit PD1.
	PWR_PDCRG_PD0_Pos  = 0x0   // Position of PD0 field.
	PWR_PDCRG_PD0_Msk  = 0x1   // Bit mask of PD0 field.
	PWR_PDCRG_PD0      = 0x1   // Bit PD0.

	// CR5: Power control register 5
	PWR_CR5_R1MODE_Pos = 0x0 // Position of R1MODE field.
	PWR_CR5_R1MODE_Msk = 0x1 // Bit mask of R1MODE field.
	PWR_CR5_R1MODE     = 0x1 // Bit R1MODE.
)

// Bitfields for RNG: Random number generator
const (
	// CR: control register
	RNG_CR_CED_Pos   = 0x5  // Position of CED field.
	RNG_CR_CED_Msk   = 0x20 // Bit mask of CED field.
	RNG_CR_CED       = 0x20 // Bit CED.
	RNG_CR_IE_Pos    = 0x3  // Position of IE field.
	RNG_CR_IE_Msk    = 0x8  // Bit mask of IE field.
	RNG_CR_IE        = 0x8  // Bit IE.
	RNG_CR_RNGEN_Pos = 0x2  // Position of RNGEN field.
	RNG_CR_RNGEN_Msk = 0x4  // Bit mask of RNGEN field.
	RNG_CR_RNGEN     = 0x4  // Bit RNGEN.

	// SR: status register
	RNG_SR_SEIS_Pos = 0x6  // Position of SEIS field.
	RNG_SR_SEIS_Msk = 0x40 // Bit mask of SEIS field.
	RNG_SR_SEIS     = 0x40 // Bit SEIS.
	RNG_SR_CEIS_Pos = 0x5  // Position of CEIS field.
	RNG_SR_CEIS_Msk = 0x20 // Bit mask of CEIS field.
	RNG_SR_CEIS     = 0x20 // Bit CEIS.
	RNG_SR_SECS_Pos = 0x2  // Position of SECS field.
	RNG_SR_SECS_Msk = 0x4  // Bit mask of SECS field.
	RNG_SR_SECS     = 0x4  // Bit SECS.
	RNG_SR_CECS_Pos = 0x1  // Position of CECS field.
	RNG_SR_CECS_Msk = 0x2  // Bit mask of CECS field.
	RNG_SR_CECS     = 0x2  // Bit CECS.
	RNG_SR_DRDY_Pos = 0x0  // Position of DRDY field.
	RNG_SR_DRDY_Msk = 0x1  // Bit mask of DRDY field.
	RNG_SR_DRDY     = 0x1  // Bit DRDY.

	// DR: data register
	RNG_DR_RNDATA_Pos = 0x0        // Position of RNDATA field.
	RNG_DR_RNDATA_Msk = 0xffffffff // Bit mask of RNDATA field.
)

// Bitfields for AES: Advanced encryption standard hardware accelerator
const (
	// CR: control register
	AES_CR_NPBLB_Pos    = 0x14     // Position of NPBLB field.
	AES_CR_NPBLB_Msk    = 0xf00000 // Bit mask of NPBLB field.
	AES_CR_KEYSIZE_Pos  = 0x12     // Position of KEYSIZE field.
	AES_CR_KEYSIZE_Msk  = 0x40000  // Bit mask of KEYSIZE field.
	AES_CR_KEYSIZE      = 0x40000  // Bit KEYSIZE.
	AES_CR_CHMOD_2_Pos  = 0x10     // Position of CHMOD_2 field.
	AES_CR_CHMOD_2_Msk  = 0x10000  // Bit mask of CHMOD_2 field.
	AES_CR_CHMOD_2      = 0x10000  // Bit CHMOD_2.
	AES_CR_GCMPH_Pos    = 0xd      // Position of GCMPH field.
	AES_CR_GCMPH_Msk    = 0x6000   // Bit mask of GCMPH field.
	AES_CR_DMAOUTEN_Pos = 0xc      // Position of DMAOUTEN field.
	AES_CR_DMAOUTEN_Msk = 0x1000   // Bit mask of DMAOUTEN field.
	AES_CR_DMAOUTEN     = 0x1000   // Bit DMAOUTEN.
	AES_CR_DMAINEN_Pos  = 0xb      // Position of DMAINEN field.
	AES_CR_DMAINEN_Msk  = 0x800    // Bit mask of DMAINEN field.
	AES_CR_DMAINEN      = 0x800    // Bit DMAINEN.
	AES_CR_ERRIE_Pos    = 0xa      // Position of ERRIE field.
	AES_CR_ERRIE_Msk    = 0x400    // Bit mask of ERRIE field.
	AES_CR_ERRIE        = 0x400    // Bit ERRIE.
	AES_CR_CCFIE_Pos    = 0x9      // Position of CCFIE field.
	AES_CR_CCFIE_Msk    = 0x200    // Bit mask of CCFIE field.
	AES_CR_CCFIE        = 0x200    // Bit CCFIE.
	AES_CR_ERRC_Pos     = 0x8      // Position of ERRC field.
	AES_CR_ERRC_Msk     = 0x100    // Bit mask of ERRC field.
	AES_CR_ERRC         = 0x100    // Bit ERRC.
	AES_CR_CCFC_Pos     = 0x7      // Position of CCFC field.
	AES_CR_CCFC_Msk     = 0x80     // Bit mask of CCFC field.
	AES_CR_CCFC         = 0x80     // Bit CCFC.
	AES_CR_CHMOD_Pos    = 0x5      // Position of CHMOD field.
	AES_CR_CHMOD_Msk    = 0x60     // Bit mask of CHMOD field.
	AES_CR_MODE_Pos     = 0x3      // Position of MODE field.
	AES_CR_MODE_Msk     = 0x18     // Bit mask of MODE field.
	AES_CR_DATATYPE_Pos = 0x1      // Position of DATATYPE field.
	AES_CR_DATATYPE_Msk = 0x6      // Bit mask of DATATYPE field.
	AES_CR_EN_Pos       = 0x0      // Position of EN field.
	AES_CR_EN_Msk       = 0x1      // Bit mask of EN field.
	AES_CR_EN           = 0x1      // Bit EN.

	// SR: status register
	AES_SR_BUSY_Pos  = 0x3 // Position of BUSY field.
	AES_SR_BUSY_Msk  = 0x8 // Bit mask of BUSY field.
	AES_SR_BUSY      = 0x8 // Bit BUSY.
	AES_SR_WRERR_Pos = 0x2 // Position of WRERR field.
	AES_SR_WRERR_Msk = 0x4 // Bit mask of WRERR field.
	AES_SR_WRERR     = 0x4 // Bit WRERR.
	AES_SR_RDERR_Pos = 0x1 // Position of RDERR field.
	AES_SR_RDERR_Msk = 0x2 // Bit mask of RDERR field.
	AES_SR_RDERR     = 0x2 // Bit RDERR.
	AES_SR_CCF_Pos   = 0x0 // Position of CCF field.
	AES_SR_CCF_Msk   = 0x1 // Bit mask of CCF field.
	AES_SR_CCF       = 0x1 // Bit CCF.

	// DINR: data input register
	AES_DINR_AES_DINR_Pos = 0x0        // Position of AES_DINR field.
	AES_DINR_AES_DINR_Msk = 0xffffffff // Bit mask of AES_DINR field.

	// DOUTR: data output register
	AES_DOUTR_AES_DOUTR_Pos = 0x0        // Position of AES_DOUTR field.
	AES_DOUTR_AES_DOUTR_Msk = 0xffffffff // Bit mask of AES_DOUTR field.

	// KEYR0: key register 0
	AES_KEYR0_AES_KEYR0_Pos = 0x0        // Position of AES_KEYR0 field.
	AES_KEYR0_AES_KEYR0_Msk = 0xffffffff // Bit mask of AES_KEYR0 field.

	// KEYR1: key register 1
	AES_KEYR1_AES_KEYR1_Pos = 0x0        // Position of AES_KEYR1 field.
	AES_KEYR1_AES_KEYR1_Msk = 0xffffffff // Bit mask of AES_KEYR1 field.

	// KEYR2: key register 2
	AES_KEYR2_AES_KEYR2_Pos = 0x0        // Position of AES_KEYR2 field.
	AES_KEYR2_AES_KEYR2_Msk = 0xffffffff // Bit mask of AES_KEYR2 field.

	// KEYR3: key register 3
	AES_KEYR3_AES_KEYR3_Pos = 0x0        // Position of AES_KEYR3 field.
	AES_KEYR3_AES_KEYR3_Msk = 0xffffffff // Bit mask of AES_KEYR3 field.

	// IVR0: initialization vector register           0
	AES_IVR0_AES_IVR0_Pos = 0x0        // Position of AES_IVR0 field.
	AES_IVR0_AES_IVR0_Msk = 0xffffffff // Bit mask of AES_IVR0 field.

	// IVR1: initialization vector register           1
	AES_IVR1_AES_IVR1_Pos = 0x0        // Position of AES_IVR1 field.
	AES_IVR1_AES_IVR1_Msk = 0xffffffff // Bit mask of AES_IVR1 field.

	// IVR2: initialization vector register           2
	AES_IVR2_AES_IVR2_Pos = 0x0        // Position of AES_IVR2 field.
	AES_IVR2_AES_IVR2_Msk = 0xffffffff // Bit mask of AES_IVR2 field.

	// IVR3: initialization vector register           3
	AES_IVR3_AES_IVR3_Pos = 0x0        // Position of AES_IVR3 field.
	AES_IVR3_AES_IVR3_Msk = 0xffffffff // Bit mask of AES_IVR3 field.

	// KEYR4: key register 4
	AES_KEYR4_KEY_Pos = 0x0        // Position of KEY field.
	AES_KEYR4_KEY_Msk = 0xffffffff // Bit mask of KEY field.

	// KEYR5: key register 5
	AES_KEYR5_KEY_Pos = 0x0        // Position of KEY field.
	AES_KEYR5_KEY_Msk = 0xffffffff // Bit mask of KEY field.

	// KEYR6: key register 6
	AES_KEYR6_KEY_Pos = 0x0        // Position of KEY field.
	AES_KEYR6_KEY_Msk = 0xffffffff // Bit mask of KEY field.

	// KEYR7: key register 7
	AES_KEYR7_KEY_Pos = 0x0        // Position of KEY field.
	AES_KEYR7_KEY_Msk = 0xffffffff // Bit mask of KEY field.

	// SUSP0R: suspend registers
	AES_SUSP0R_SUSP_Pos = 0x0        // Position of SUSP field.
	AES_SUSP0R_SUSP_Msk = 0xffffffff // Bit mask of SUSP field.

	// SUSP1R: suspend registers
	AES_SUSP1R_SUSP_Pos = 0x0        // Position of SUSP field.
	AES_SUSP1R_SUSP_Msk = 0xffffffff // Bit mask of SUSP field.

	// SUSP2R: suspend registers
	AES_SUSP2R_SUSP_Pos = 0x0        // Position of SUSP field.
	AES_SUSP2R_SUSP_Msk = 0xffffffff // Bit mask of SUSP field.

	// SUSP3R: suspend registers
	AES_SUSP3R_SUSP_Pos = 0x0        // Position of SUSP field.
	AES_SUSP3R_SUSP_Msk = 0xffffffff // Bit mask of SUSP field.

	// SUSP4R: suspend registers
	AES_SUSP4R_SUSP_Pos = 0x0        // Position of SUSP field.
	AES_SUSP4R_SUSP_Msk = 0xffffffff // Bit mask of SUSP field.

	// SUSP5R: suspend registers
	AES_SUSP5R_SUSP_Pos = 0x0        // Position of SUSP field.
	AES_SUSP5R_SUSP_Msk = 0xffffffff // Bit mask of SUSP field.

	// SUSP6R: suspend registers
	AES_SUSP6R_SUSP_Pos = 0x0        // Position of SUSP field.
	AES_SUSP6R_SUSP_Msk = 0xffffffff // Bit mask of SUSP field.

	// SUSP7R: suspend registers
	AES_SUSP7R_SUSP_Pos = 0x0        // Position of SUSP field.
	AES_SUSP7R_SUSP_Msk = 0xffffffff // Bit mask of SUSP field.
)

// Bitfields for GPIOA: General-purpose I/Os
const (
	// MODER: GPIO port mode register
	GPIO_MODER_MODER15_Pos = 0x1e       // Position of MODER15 field.
	GPIO_MODER_MODER15_Msk = 0xc0000000 // Bit mask of MODER15 field.
	GPIO_MODER_MODER14_Pos = 0x1c       // Position of MODER14 field.
	GPIO_MODER_MODER14_Msk = 0x30000000 // Bit mask of MODER14 field.
	GPIO_MODER_MODER13_Pos = 0x1a       // Position of MODER13 field.
	GPIO_MODER_MODER13_Msk = 0xc000000  // Bit mask of MODER13 field.
	GPIO_MODER_MODER12_Pos = 0x18       // Position of MODER12 field.
	GPIO_MODER_MODER12_Msk = 0x3000000  // Bit mask of MODER12 field.
	GPIO_MODER_MODER11_Pos = 0x16       // Position of MODER11 field.
	GPIO_MODER_MODER11_Msk = 0xc00000   // Bit mask of MODER11 field.
	GPIO_MODER_MODER10_Pos = 0x14       // Position of MODER10 field.
	GPIO_MODER_MODER10_Msk = 0x300000   // Bit mask of MODER10 field.
	GPIO_MODER_MODER9_Pos  = 0x12       // Position of MODER9 field.
	GPIO_MODER_MODER9_Msk  = 0xc0000    // Bit mask of MODER9 field.
	GPIO_MODER_MODER8_Pos  = 0x10       // Position of MODER8 field.
	GPIO_MODER_MODER8_Msk  = 0x30000    // Bit mask of MODER8 field.
	GPIO_MODER_MODER7_Pos  = 0xe        // Position of MODER7 field.
	GPIO_MODER_MODER7_Msk  = 0xc000     // Bit mask of MODER7 field.
	GPIO_MODER_MODER6_Pos  = 0xc        // Position of MODER6 field.
	GPIO_MODER_MODER6_Msk  = 0x3000     // Bit mask of MODER6 field.
	GPIO_MODER_MODER5_Pos  = 0xa        // Position of MODER5 field.
	GPIO_MODER_MODER5_Msk  = 0xc00      // Bit mask of MODER5 field.
	GPIO_MODER_MODER4_Pos  = 0x8        // Position of MODER4 field.
	GPIO_MODER_MODER4_Msk  = 0x300      // Bit mask of MODER4 field.
	GPIO_MODER_MODER3_Pos  = 0x6        // Position of MODER3 field.
	GPIO_MODER_MODER3_Msk  = 0xc0       // Bit mask of MODER3 field.
	GPIO_MODER_MODER2_Pos  = 0x4        // Position of MODER2 field.
	GPIO_MODER_MODER2_Msk  = 0x30       // Bit mask of MODER2 field.
	GPIO_MODER_MODER1_Pos  = 0x2        // Position of MODER1 field.
	GPIO_MODER_MODER1_Msk  = 0xc        // Bit mask of MODER1 field.
	GPIO_MODER_MODER0_Pos  = 0x0        // Position of MODER0 field.
	GPIO_MODER_MODER0_Msk  = 0x3        // Bit mask of MODER0 field.

	// OTYPER: GPIO port output type register
	GPIO_OTYPER_OT15_Pos = 0xf    // Position of OT15 field.
	GPIO_OTYPER_OT15_Msk = 0x8000 // Bit mask of OT15 field.
	GPIO_OTYPER_OT15     = 0x8000 // Bit OT15.
	GPIO_OTYPER_OT14_Pos = 0xe    // Position of OT14 field.
	GPIO_OTYPER_OT14_Msk = 0x4000 // Bit mask of OT14 field.
	GPIO_OTYPER_OT14     = 0x4000 // Bit OT14.
	GPIO_OTYPER_OT13_Pos = 0xd    // Position of OT13 field.
	GPIO_OTYPER_OT13_Msk = 0x2000 // Bit mask of OT13 field.
	GPIO_OTYPER_OT13     = 0x2000 // Bit OT13.
	GPIO_OTYPER_OT12_Pos = 0xc    // Position of OT12 field.
	GPIO_OTYPER_OT12_Msk = 0x1000 // Bit mask of OT12 field.
	GPIO_OTYPER_OT12     = 0x1000 // Bit OT12.
	GPIO_OTYPER_OT11_Pos = 0xb    // Position of OT11 field.
	GPIO_OTYPER_OT11_Msk = 0x800  // Bit mask of OT11 field.
	GPIO_OTYPER_OT11     = 0x800  // Bit OT11.
	GPIO_OTYPER_OT10_Pos = 0xa    // Position of OT10 field.
	GPIO_OTYPER_OT10_Msk = 0x400  // Bit mask of OT10 field.
	GPIO_OTYPER_OT10     = 0x400  // Bit OT10.
	GPIO_OTYPER_OT9_Pos  = 0x9    // Position of OT9 field.
	GPIO_OTYPER_OT9_Msk  = 0x200  // Bit mask of OT9 field.
	GPIO_OTYPER_OT9      = 0x200  // Bit OT9.
	GPIO_OTYPER_OT8_Pos  = 0x8    // Position of OT8 field.
	GPIO_OTYPER_OT8_Msk  = 0x100  // Bit mask of OT8 field.
	GPIO_OTYPER_OT8      = 0x100  // Bit OT8.
	GPIO_OTYPER_OT7_Pos  = 0x7    // Position of OT7 field.
	GPIO_OTYPER_OT7_Msk  = 0x80   // Bit mask of OT7 field.
	GPIO_OTYPER_OT7      = 0x80   // Bit OT7.
	GPIO_OTYPER_OT6_Pos  = 0x6    // Position of OT6 field.
	GPIO_OTYPER_OT6_Msk  = 0x40   // Bit mask of OT6 field.
	GPIO_OTYPER_OT6      = 0x40   // Bit OT6.
	GPIO_OTYPER_OT5_Pos  = 0x5    // Position of OT5 field.
	GPIO_OTYPER_OT5_Msk  = 0x20   // Bit mask of OT5 field.
	GPIO_OTYPER_OT5      = 0x20   // Bit OT5.
	GPIO_OTYPER_OT4_Pos  = 0x4    // Position of OT4 field.
	GPIO_OTYPER_OT4_Msk  = 0x10   // Bit mask of OT4 field.
	GPIO_OTYPER_OT4      = 0x10   // Bit OT4.
	GPIO_OTYPER_OT3_Pos  = 0x3    // Position of OT3 field.
	GPIO_OTYPER_OT3_Msk  = 0x8    // Bit mask of OT3 field.
	GPIO_OTYPER_OT3      = 0x8    // Bit OT3.
	GPIO_OTYPER_OT2_Pos  = 0x2    // Position of OT2 field.
	GPIO_OTYPER_OT2_Msk  = 0x4    // Bit mask of OT2 field.
	GPIO_OTYPER_OT2      = 0x4    // Bit OT2.
	GPIO_OTYPER_OT1_Pos  = 0x1    // Position of OT1 field.
	GPIO_OTYPER_OT1_Msk  = 0x2    // Bit mask of OT1 field.
	GPIO_OTYPER_OT1      = 0x2    // Bit OT1.
	GPIO_OTYPER_OT0_Pos  = 0x0    // Position of OT0 field.
	GPIO_OTYPER_OT0_Msk  = 0x1    // Bit mask of OT0 field.
	GPIO_OTYPER_OT0      = 0x1    // Bit OT0.

	// OSPEEDR: GPIO port output speed           register
	GPIO_OSPEEDR_OSPEEDR15_Pos = 0x1e       // Position of OSPEEDR15 field.
	GPIO_OSPEEDR_OSPEEDR15_Msk = 0xc0000000 // Bit mask of OSPEEDR15 field.
	GPIO_OSPEEDR_OSPEEDR14_Pos = 0x1c       // Position of OSPEEDR14 field.
	GPIO_OSPEEDR_OSPEEDR14_Msk = 0x30000000 // Bit mask of OSPEEDR14 field.
	GPIO_OSPEEDR_OSPEEDR13_Pos = 0x1a       // Position of OSPEEDR13 field.
	GPIO_OSPEEDR_OSPEEDR13_Msk = 0xc000000  // Bit mask of OSPEEDR13 field.
	GPIO_OSPEEDR_OSPEEDR12_Pos = 0x18       // Position of OSPEEDR12 field.
	GPIO_OSPEEDR_OSPEEDR12_Msk = 0x3000000  // Bit mask of OSPEEDR12 field.
	GPIO_OSPEEDR_OSPEEDR11_Pos = 0x16       // Position of OSPEEDR11 field.
	GPIO_OSPEEDR_OSPEEDR11_Msk = 0xc00000   // Bit mask of OSPEEDR11 field.
	GPIO_OSPEEDR_OSPEEDR10_Pos = 0x14       // Position of OSPEEDR10 field.
	GPIO_OSPEEDR_OSPEEDR10_Msk = 0x300000   // Bit mask of OSPEEDR10 field.
	GPIO_OSPEEDR_OSPEEDR9_Pos  = 0x12       // Position of OSPEEDR9 field.
	GPIO_OSPEEDR_OSPEEDR9_Msk  = 0xc0000    // Bit mask of OSPEEDR9 field.
	GPIO_OSPEEDR_OSPEEDR8_Pos  = 0x10       // Position of OSPEEDR8 field.
	GPIO_OSPEEDR_OSPEEDR8_Msk  = 0x30000    // Bit mask of OSPEEDR8 field.
	GPIO_OSPEEDR_OSPEEDR7_Pos  = 0xe        // Position of OSPEEDR7 field.
	GPIO_OSPEEDR_OSPEEDR7_Msk  = 0xc000     // Bit mask of OSPEEDR7 field.
	GPIO_OSPEEDR_OSPEEDR6_Pos  = 0xc        // Position of OSPEEDR6 field.
	GPIO_OSPEEDR_OSPEEDR6_Msk  = 0x3000     // Bit mask of OSPEEDR6 field.
	GPIO_OSPEEDR_OSPEEDR5_Pos  = 0xa        // Position of OSPEEDR5 field.
	GPIO_OSPEEDR_OSPEEDR5_Msk  = 0xc00      // Bit mask of OSPEEDR5 field.
	GPIO_OSPEEDR_OSPEEDR4_Pos  = 0x8        // Position of OSPEEDR4 field.
	GPIO_OSPEEDR_OSPEEDR4_Msk  = 0x300      // Bit mask of OSPEEDR4 field.
	GPIO_OSPEEDR_OSPEEDR3_Pos  = 0x6        // Position of OSPEEDR3 field.
	GPIO_OSPEEDR_OSPEEDR3_Msk  = 0xc0       // Bit mask of OSPEEDR3 field.
	GPIO_OSPEEDR_OSPEEDR2_Pos  = 0x4        // Position of OSPEEDR2 field.
	GPIO_OSPEEDR_OSPEEDR2_Msk  = 0x30       // Bit mask of OSPEEDR2 field.
	GPIO_OSPEEDR_OSPEEDR1_Pos  = 0x2        // Position of OSPEEDR1 field.
	GPIO_OSPEEDR_OSPEEDR1_Msk  = 0xc        // Bit mask of OSPEEDR1 field.
	GPIO_OSPEEDR_OSPEEDR0_Pos  = 0x0        // Position of OSPEEDR0 field.
	GPIO_OSPEEDR_OSPEEDR0_Msk  = 0x3        // Bit mask of OSPEEDR0 field.

	// PUPDR: GPIO port pull-up/pull-down           register
	GPIO_PUPDR_PUPDR15_Pos = 0x1e       // Position of PUPDR15 field.
	GPIO_PUPDR_PUPDR15_Msk = 0xc0000000 // Bit mask of PUPDR15 field.
	GPIO_PUPDR_PUPDR14_Pos = 0x1c       // Position of PUPDR14 field.
	GPIO_PUPDR_PUPDR14_Msk = 0x30000000 // Bit mask of PUPDR14 field.
	GPIO_PUPDR_PUPDR13_Pos = 0x1a       // Position of PUPDR13 field.
	GPIO_PUPDR_PUPDR13_Msk = 0xc000000  // Bit mask of PUPDR13 field.
	GPIO_PUPDR_PUPDR12_Pos = 0x18       // Position of PUPDR12 field.
	GPIO_PUPDR_PUPDR12_Msk = 0x3000000  // Bit mask of PUPDR12 field.
	GPIO_PUPDR_PUPDR11_Pos = 0x16       // Position of PUPDR11 field.
	GPIO_PUPDR_PUPDR11_Msk = 0xc00000   // Bit mask of PUPDR11 field.
	GPIO_PUPDR_PUPDR10_Pos = 0x14       // Position of PUPDR10 field.
	GPIO_PUPDR_PUPDR10_Msk = 0x300000   // Bit mask of PUPDR10 field.
	GPIO_PUPDR_PUPDR9_Pos  = 0x12       // Position of PUPDR9 field.
	GPIO_PUPDR_PUPDR9_Msk  = 0xc0000    // Bit mask of PUPDR9 field.
	GPIO_PUPDR_PUPDR8_Pos  = 0x10       // Position of PUPDR8 field.
	GPIO_PUPDR_PUPDR8_Msk  = 0x30000    // Bit mask of PUPDR8 field.
	GPIO_PUPDR_PUPDR7_Pos  = 0xe        // Position of PUPDR7 field.
	GPIO_PUPDR_PUPDR7_Msk  = 0xc000     // Bit mask of PUPDR7 field.
	GPIO_PUPDR_PUPDR6_Pos  = 0xc        // Position of PUPDR6 field.
	GPIO_PUPDR_PUPDR6_Msk  = 0x3000     // Bit mask of PUPDR6 field.
	GPIO_PUPDR_PUPDR5_Pos  = 0xa        // Position of PUPDR5 field.
	GPIO_PUPDR_PUPDR5_Msk  = 0xc00      // Bit mask of PUPDR5 field.
	GPIO_PUPDR_PUPDR4_Pos  = 0x8        // Position of PUPDR4 field.
	GPIO_PUPDR_PUPDR4_Msk  = 0x300      // Bit mask of PUPDR4 field.
	GPIO_PUPDR_PUPDR3_Pos  = 0x6        // Position of PUPDR3 field.
	GPIO_PUPDR_PUPDR3_Msk  = 0xc0       // Bit mask of PUPDR3 field.
	GPIO_PUPDR_PUPDR2_Pos  = 0x4        // Position of PUPDR2 field.
	GPIO_PUPDR_PUPDR2_Msk  = 0x30       // Bit mask of PUPDR2 field.
	GPIO_PUPDR_PUPDR1_Pos  = 0x2        // Position of PUPDR1 field.
	GPIO_PUPDR_PUPDR1_Msk  = 0xc        // Bit mask of PUPDR1 field.
	GPIO_PUPDR_PUPDR0_Pos  = 0x0        // Position of PUPDR0 field.
	GPIO_PUPDR_PUPDR0_Msk  = 0x3        // Bit mask of PUPDR0 field.

	// IDR: GPIO port input data register
	GPIO_IDR_IDR15_Pos = 0xf    // Position of IDR15 field.
	GPIO_IDR_IDR15_Msk = 0x8000 // Bit mask of IDR15 field.
	GPIO_IDR_IDR15     = 0x8000 // Bit IDR15.
	GPIO_IDR_IDR14_Pos = 0xe    // Position of IDR14 field.
	GPIO_IDR_IDR14_Msk = 0x4000 // Bit mask of IDR14 field.
	GPIO_IDR_IDR14     = 0x4000 // Bit IDR14.
	GPIO_IDR_IDR13_Pos = 0xd    // Position of IDR13 field.
	GPIO_IDR_IDR13_Msk = 0x2000 // Bit mask of IDR13 field.
	GPIO_IDR_IDR13     = 0x2000 // Bit IDR13.
	GPIO_IDR_IDR12_Pos = 0xc    // Position of IDR12 field.
	GPIO_IDR_IDR12_Msk = 0x1000 // Bit mask of IDR12 field.
	GPIO_IDR_IDR12     = 0x1000 // Bit IDR12.
	GPIO_IDR_IDR11_Pos = 0xb    // Position of IDR11 field.
	GPIO_IDR_IDR11_Msk = 0x800  // Bit mask of IDR11 field.
	GPIO_IDR_IDR11     = 0x800  // Bit IDR11.
	GPIO_IDR_IDR10_Pos = 0xa    // Position of IDR10 field.
	GPIO_IDR_IDR10_Msk = 0x400  // Bit mask of IDR10 field.
	GPIO_IDR_IDR10     = 0x400  // Bit IDR10.
	GPIO_IDR_IDR9_Pos  = 0x9    // Position of IDR9 field.
	GPIO_IDR_IDR9_Msk  = 0x200  // Bit mask of IDR9 field.
	GPIO_IDR_IDR9      = 0x200  // Bit IDR9.
	GPIO_IDR_IDR8_Pos  = 0x8    // Position of IDR8 field.
	GPIO_IDR_IDR8_Msk  = 0x100  // Bit mask of IDR8 field.
	GPIO_IDR_IDR8      = 0x100  // Bit IDR8.
	GPIO_IDR_IDR7_Pos  = 0x7    // Position of IDR7 field.
	GPIO_IDR_IDR7_Msk  = 0x80   // Bit mask of IDR7 field.
	GPIO_IDR_IDR7      = 0x80   // Bit IDR7.
	GPIO_IDR_IDR6_Pos  = 0x6    // Position of IDR6 field.
	GPIO_IDR_IDR6_Msk  = 0x40   // Bit mask of IDR6 field.
	GPIO_IDR_IDR6      = 0x40   // Bit IDR6.
	GPIO_IDR_IDR5_Pos  = 0x5    // Position of IDR5 field.
	GPIO_IDR_IDR5_Msk  = 0x20   // Bit mask of IDR5 field.
	GPIO_IDR_IDR5      = 0x20   // Bit IDR5.
	GPIO_IDR_IDR4_Pos  = 0x4    // Position of IDR4 field.
	GPIO_IDR_IDR4_Msk  = 0x10   // Bit mask of IDR4 field.
	GPIO_IDR_IDR4      = 0x10   // Bit IDR4.
	GPIO_IDR_IDR3_Pos  = 0x3    // Position of IDR3 field.
	GPIO_IDR_IDR3_Msk  = 0x8    // Bit mask of IDR3 field.
	GPIO_IDR_IDR3      = 0x8    // Bit IDR3.
	GPIO_IDR_IDR2_Pos  = 0x2    // Position of IDR2 field.
	GPIO_IDR_IDR2_Msk  = 0x4    // Bit mask of IDR2 field.
	GPIO_IDR_IDR2      = 0x4    // Bit IDR2.
	GPIO_IDR_IDR1_Pos  = 0x1    // Position of IDR1 field.
	GPIO_IDR_IDR1_Msk  = 0x2    // Bit mask of IDR1 field.
	GPIO_IDR_IDR1      = 0x2    // Bit IDR1.
	GPIO_IDR_IDR0_Pos  = 0x0    // Position of IDR0 field.
	GPIO_IDR_IDR0_Msk  = 0x1    // Bit mask of IDR0 field.
	GPIO_IDR_IDR0      = 0x1    // Bit IDR0.

	// ODR: GPIO port output data register
	GPIO_ODR_ODR15_Pos = 0xf    // Position of ODR15 field.
	GPIO_ODR_ODR15_Msk = 0x8000 // Bit mask of ODR15 field.
	GPIO_ODR_ODR15     = 0x8000 // Bit ODR15.
	GPIO_ODR_ODR14_Pos = 0xe    // Position of ODR14 field.
	GPIO_ODR_ODR14_Msk = 0x4000 // Bit mask of ODR14 field.
	GPIO_ODR_ODR14     = 0x4000 // Bit ODR14.
	GPIO_ODR_ODR13_Pos = 0xd    // Position of ODR13 field.
	GPIO_ODR_ODR13_Msk = 0x2000 // Bit mask of ODR13 field.
	GPIO_ODR_ODR13     = 0x2000 // Bit ODR13.
	GPIO_ODR_ODR12_Pos = 0xc    // Position of ODR12 field.
	GPIO_ODR_ODR12_Msk = 0x1000 // Bit mask of ODR12 field.
	GPIO_ODR_ODR12     = 0x1000 // Bit ODR12.
	GPIO_ODR_ODR11_Pos = 0xb    // Position of ODR11 field.
	GPIO_ODR_ODR11_Msk = 0x800  // Bit mask of ODR11 field.
	GPIO_ODR_ODR11     = 0x800  // Bit ODR11.
	GPIO_ODR_ODR10_Pos = 0xa    // Position of ODR10 field.
	GPIO_ODR_ODR10_Msk = 0x400  // Bit mask of ODR10 field.
	GPIO_ODR_ODR10     = 0x400  // Bit ODR10.
	GPIO_ODR_ODR9_Pos  = 0x9    // Position of ODR9 field.
	GPIO_ODR_ODR9_Msk  = 0x200  // Bit mask of ODR9 field.
	GPIO_ODR_ODR9      = 0x200  // Bit ODR9.
	GPIO_ODR_ODR8_Pos  = 0x8    // Position of ODR8 field.
	GPIO_ODR_ODR8_Msk  = 0x100  // Bit mask of ODR8 field.
	GPIO_ODR_ODR8      = 0x100  // Bit ODR8.
	GPIO_ODR_ODR7_Pos  = 0x7    // Position of ODR7 field.
	GPIO_ODR_ODR7_Msk  = 0x80   // Bit mask of ODR7 field.
	GPIO_ODR_ODR7      = 0x80   // Bit ODR7.
	GPIO_ODR_ODR6_Pos  = 0x6    // Position of ODR6 field.
	GPIO_ODR_ODR6_Msk  = 0x40   // Bit mask of ODR6 field.
	GPIO_ODR_ODR6      = 0x40   // Bit ODR6.
	GPIO_ODR_ODR5_Pos  = 0x5    // Position of ODR5 field.
	GPIO_ODR_ODR5_Msk  = 0x20   // Bit mask of ODR5 field.
	GPIO_ODR_ODR5      = 0x20   // Bit ODR5.
	GPIO_ODR_ODR4_Pos  = 0x4    // Position of ODR4 field.
	GPIO_ODR_ODR4_Msk  = 0x10   // Bit mask of ODR4 field.
	GPIO_ODR_ODR4      = 0x10   // Bit ODR4.
	GPIO_ODR_ODR3_Pos  = 0x3    // Position of ODR3 field.
	GPIO_ODR_ODR3_Msk  = 0x8    // Bit mask of ODR3 field.
	GPIO_ODR_ODR3      = 0x8    // Bit ODR3.
	GPIO_ODR_ODR2_Pos  = 0x2    // Position of ODR2 field.
	GPIO_ODR_ODR2_Msk  = 0x4    // Bit mask of ODR2 field.
	GPIO_ODR_ODR2      = 0x4    // Bit ODR2.
	GPIO_ODR_ODR1_Pos  = 0x1    // Position of ODR1 field.
	GPIO_ODR_ODR1_Msk  = 0x2    // Bit mask of ODR1 field.
	GPIO_ODR_ODR1      = 0x2    // Bit ODR1.
	GPIO_ODR_ODR0_Pos  = 0x0    // Position of ODR0 field.
	GPIO_ODR_ODR0_Msk  = 0x1    // Bit mask of ODR0 field.
	GPIO_ODR_ODR0      = 0x1    // Bit ODR0.

	// BSRR: GPIO port bit set/reset           register
	GPIO_BSRR_BR15_Pos = 0x1f       // Position of BR15 field.
	GPIO_BSRR_BR15_Msk = 0x80000000 // Bit mask of BR15 field.
	GPIO_BSRR_BR15     = 0x80000000 // Bit BR15.
	GPIO_BSRR_BR14_Pos = 0x1e       // Position of BR14 field.
	GPIO_BSRR_BR14_Msk = 0x40000000 // Bit mask of BR14 field.
	GPIO_BSRR_BR14     = 0x40000000 // Bit BR14.
	GPIO_BSRR_BR13_Pos = 0x1d       // Position of BR13 field.
	GPIO_BSRR_BR13_Msk = 0x20000000 // Bit mask of BR13 field.
	GPIO_BSRR_BR13     = 0x20000000 // Bit BR13.
	GPIO_BSRR_BR12_Pos = 0x1c       // Position of BR12 field.
	GPIO_BSRR_BR12_Msk = 0x10000000 // Bit mask of BR12 field.
	GPIO_BSRR_BR12     = 0x10000000 // Bit BR12.
	GPIO_BSRR_BR11_Pos = 0x1b       // Position of BR11 field.
	GPIO_BSRR_BR11_Msk = 0x8000000  // Bit mask of BR11 field.
	GPIO_BSRR_BR11     = 0x8000000  // Bit BR11.
	GPIO_BSRR_BR10_Pos = 0x1a       // Position of BR10 field.
	GPIO_BSRR_BR10_Msk = 0x4000000  // Bit mask of BR10 field.
	GPIO_BSRR_BR10     = 0x4000000  // Bit BR10.
	GPIO_BSRR_BR9_Pos  = 0x19       // Position of BR9 field.
	GPIO_BSRR_BR9_Msk  = 0x2000000  // Bit mask of BR9 field.
	GPIO_BSRR_BR9      = 0x2000000  // Bit BR9.
	GPIO_BSRR_BR8_Pos  = 0x18       // Position of BR8 field.
	GPIO_BSRR_BR8_Msk  = 0x1000000  // Bit mask of BR8 field.
	GPIO_BSRR_BR8      = 0x1000000  // Bit BR8.
	GPIO_BSRR_BR7_Pos  = 0x17       // Position of BR7 field.
	GPIO_BSRR_BR7_Msk  = 0x800000   // Bit mask of BR7 field.
	GPIO_BSRR_BR7      = 0x800000   // Bit BR7.
	GPIO_BSRR_BR6_Pos  = 0x16       // Position of BR6 field.
	GPIO_BSRR_BR6_Msk  = 0x400000   // Bit mask of BR6 field.
	GPIO_BSRR_BR6      = 0x400000   // Bit BR6.
	GPIO_BSRR_BR5_Pos  = 0x15       // Position of BR5 field.
	GPIO_BSRR_BR5_Msk  = 0x200000   // Bit mask of BR5 field.
	GPIO_BSRR_BR5      = 0x200000   // Bit BR5.
	GPIO_BSRR_BR4_Pos  = 0x14       // Position of BR4 field.
	GPIO_BSRR_BR4_Msk  = 0x100000   // Bit mask of BR4 field.
	GPIO_BSRR_BR4      = 0x100000   // Bit BR4.
	GPIO_BSRR_BR3_Pos  = 0x13       // Position of BR3 field.
	GPIO_BSRR_BR3_Msk  = 0x80000    // Bit mask of BR3 field.
	GPIO_BSRR_BR3      = 0x80000    // Bit BR3.
	GPIO_BSRR_BR2_Pos  = 0x12       // Position of BR2 field.
	GPIO_BSRR_BR2_Msk  = 0x40000    // Bit mask of BR2 field.
	GPIO_BSRR_BR2      = 0x40000    // Bit BR2.
	GPIO_BSRR_BR1_Pos  = 0x11       // Position of BR1 field.
	GPIO_BSRR_BR1_Msk  = 0x20000    // Bit mask of BR1 field.
	GPIO_BSRR_BR1      = 0x20000    // Bit BR1.
	GPIO_BSRR_BR0_Pos  = 0x10       // Position of BR0 field.
	GPIO_BSRR_BR0_Msk  = 0x10000    // Bit mask of BR0 field.
	GPIO_BSRR_BR0      = 0x10000    // Bit BR0.
	GPIO_BSRR_BS15_Pos = 0xf        // Position of BS15 field.
	GPIO_BSRR_BS15_Msk = 0x8000     // Bit mask of BS15 field.
	GPIO_BSRR_BS15     = 0x8000     // Bit BS15.
	GPIO_BSRR_BS14_Pos = 0xe        // Position of BS14 field.
	GPIO_BSRR_BS14_Msk = 0x4000     // Bit mask of BS14 field.
	GPIO_BSRR_BS14     = 0x4000     // Bit BS14.
	GPIO_BSRR_BS13_Pos = 0xd        // Position of BS13 field.
	GPIO_BSRR_BS13_Msk = 0x2000     // Bit mask of BS13 field.
	GPIO_BSRR_BS13     = 0x2000     // Bit BS13.
	GPIO_BSRR_BS12_Pos = 0xc        // Position of BS12 field.
	GPIO_BSRR_BS12_Msk = 0x1000     // Bit mask of BS12 field.
	GPIO_BSRR_BS12     = 0x1000     // Bit BS12.
	GPIO_BSRR_BS11_Pos = 0xb        // Position of BS11 field.
	GPIO_BSRR_BS11_Msk = 0x800      // Bit mask of BS11 field.
	GPIO_BSRR_BS11     = 0x800      // Bit BS11.
	GPIO_BSRR_BS10_Pos = 0xa        // Position of BS10 field.
	GPIO_BSRR_BS10_Msk = 0x400      // Bit mask of BS10 field.
	GPIO_BSRR_BS10     = 0x400      // Bit BS10.
	GPIO_BSRR_BS9_Pos  = 0x9        // Position of BS9 field.
	GPIO_BSRR_BS9_Msk  = 0x200      // Bit mask of BS9 field.
	GPIO_BSRR_BS9      = 0x200      // Bit BS9.
	GPIO_BSRR_BS8_Pos  = 0x8        // Position of BS8 field.
	GPIO_BSRR_BS8_Msk  = 0x100      // Bit mask of BS8 field.
	GPIO_BSRR_BS8      = 0x100      // Bit BS8.
	GPIO_BSRR_BS7_Pos  = 0x7        // Position of BS7 field.
	GPIO_BSRR_BS7_Msk  = 0x80       // Bit mask of BS7 field.
	GPIO_BSRR_BS7      = 0x80       // Bit BS7.
	GPIO_BSRR_BS6_Pos  = 0x6        // Position of BS6 field.
	GPIO_BSRR_BS6_Msk  = 0x40       // Bit mask of BS6 field.
	GPIO_BSRR_BS6      = 0x40       // Bit BS6.
	GPIO_BSRR_BS5_Pos  = 0x5        // Position of BS5 field.
	GPIO_BSRR_BS5_Msk  = 0x20       // Bit mask of BS5 field.
	GPIO_BSRR_BS5      = 0x20       // Bit BS5.
	GPIO_BSRR_BS4_Pos  = 0x4        // Position of BS4 field.
	GPIO_BSRR_BS4_Msk  = 0x10       // Bit mask of BS4 field.
	GPIO_BSRR_BS4      = 0x10       // Bit BS4.
	GPIO_BSRR_BS3_Pos  = 0x3        // Position of BS3 field.
	GPIO_BSRR_BS3_Msk  = 0x8        // Bit mask of BS3 field.
	GPIO_BSRR_BS3      = 0x8        // Bit BS3.
	GPIO_BSRR_BS2_Pos  = 0x2        // Position of BS2 field.
	GPIO_BSRR_BS2_Msk  = 0x4        // Bit mask of BS2 field.
	GPIO_BSRR_BS2      = 0x4        // Bit BS2.
	GPIO_BSRR_BS1_Pos  = 0x1        // Position of BS1 field.
	GPIO_BSRR_BS1_Msk  = 0x2        // Bit mask of BS1 field.
	GPIO_BSRR_BS1      = 0x2        // Bit BS1.
	GPIO_BSRR_BS0_Pos  = 0x0        // Position of BS0 field.
	GPIO_BSRR_BS0_Msk  = 0x1        // Bit mask of BS0 field.
	GPIO_BSRR_BS0      = 0x1        // Bit BS0.

	// LCKR: GPIO port configuration lock           register
	GPIO_LCKR_LCKK_Pos  = 0x10    // Position of LCKK field.
	GPIO_LCKR_LCKK_Msk  = 0x10000 // Bit mask of LCKK field.
	GPIO_LCKR_LCKK      = 0x10000 // Bit LCKK.
	GPIO_LCKR_LCK15_Pos = 0xf     // Position of LCK15 field.
	GPIO_LCKR_LCK15_Msk = 0x8000  // Bit mask of LCK15 field.
	GPIO_LCKR_LCK15     = 0x8000  // Bit LCK15.
	GPIO_LCKR_LCK14_Pos = 0xe     // Position of LCK14 field.
	GPIO_LCKR_LCK14_Msk = 0x4000  // Bit mask of LCK14 field.
	GPIO_LCKR_LCK14     = 0x4000  // Bit LCK14.
	GPIO_LCKR_LCK13_Pos = 0xd     // Position of LCK13 field.
	GPIO_LCKR_LCK13_Msk = 0x2000  // Bit mask of LCK13 field.
	GPIO_LCKR_LCK13     = 0x2000  // Bit LCK13.
	GPIO_LCKR_LCK12_Pos = 0xc     // Position of LCK12 field.
	GPIO_LCKR_LCK12_Msk = 0x1000  // Bit mask of LCK12 field.
	GPIO_LCKR_LCK12     = 0x1000  // Bit LCK12.
	GPIO_LCKR_LCK11_Pos = 0xb     // Position of LCK11 field.
	GPIO_LCKR_LCK11_Msk = 0x800   // Bit mask of LCK11 field.
	GPIO_LCKR_LCK11     = 0x800   // Bit LCK11.
	GPIO_LCKR_LCK10_Pos = 0xa     // Position of LCK10 field.
	GPIO_LCKR_LCK10_Msk = 0x400   // Bit mask of LCK10 field.
	GPIO_LCKR_LCK10     = 0x400   // Bit LCK10.
	GPIO_LCKR_LCK9_Pos  = 0x9     // Position of LCK9 field.
	GPIO_LCKR_LCK9_Msk  = 0x200   // Bit mask of LCK9 field.
	GPIO_LCKR_LCK9      = 0x200   // Bit LCK9.
	GPIO_LCKR_LCK8_Pos  = 0x8     // Position of LCK8 field.
	GPIO_LCKR_LCK8_Msk  = 0x100   // Bit mask of LCK8 field.
	GPIO_LCKR_LCK8      = 0x100   // Bit LCK8.
	GPIO_LCKR_LCK7_Pos  = 0x7     // Position of LCK7 field.
	GPIO_LCKR_LCK7_Msk  = 0x80    // Bit mask of LCK7 field.
	GPIO_LCKR_LCK7      = 0x80    // Bit LCK7.
	GPIO_LCKR_LCK6_Pos  = 0x6     // Position of LCK6 field.
	GPIO_LCKR_LCK6_Msk  = 0x40    // Bit mask of LCK6 field.
	GPIO_LCKR_LCK6      = 0x40    // Bit LCK6.
	GPIO_LCKR_LCK5_Pos  = 0x5     // Position of LCK5 field.
	GPIO_LCKR_LCK5_Msk  = 0x20    // Bit mask of LCK5 field.
	GPIO_LCKR_LCK5      = 0x20    // Bit LCK5.
	GPIO_LCKR_LCK4_Pos  = 0x4     // Position of LCK4 field.
	GPIO_LCKR_LCK4_Msk  = 0x10    // Bit mask of LCK4 field.
	GPIO_LCKR_LCK4      = 0x10    // Bit LCK4.
	GPIO_LCKR_LCK3_Pos  = 0x3     // Position of LCK3 field.
	GPIO_LCKR_LCK3_Msk  = 0x8     // Bit mask of LCK3 field.
	GPIO_LCKR_LCK3      = 0x8     // Bit LCK3.
	GPIO_LCKR_LCK2_Pos  = 0x2     // Position of LCK2 field.
	GPIO_LCKR_LCK2_Msk  = 0x4     // Bit mask of LCK2 field.
	GPIO_LCKR_LCK2      = 0x4     // Bit LCK2.
	GPIO_LCKR_LCK1_Pos  = 0x1     // Position of LCK1 field.
	GPIO_LCKR_LCK1_Msk  = 0x2     // Bit mask of LCK1 field.
	GPIO_LCKR_LCK1      = 0x2     // Bit LCK1.
	GPIO_LCKR_LCK0_Pos  = 0x0     // Position of LCK0 field.
	GPIO_LCKR_LCK0_Msk  = 0x1     // Bit mask of LCK0 field.
	GPIO_LCKR_LCK0      = 0x1     // Bit LCK0.

	// AFRL: GPIO alternate function low           register
	GPIO_AFRL_AFRL7_Pos = 0x1c       // Position of AFRL7 field.
	GPIO_AFRL_AFRL7_Msk = 0xf0000000 // Bit mask of AFRL7 field.
	GPIO_AFRL_AFRL6_Pos = 0x18       // Position of AFRL6 field.
	GPIO_AFRL_AFRL6_Msk = 0xf000000  // Bit mask of AFRL6 field.
	GPIO_AFRL_AFRL5_Pos = 0x14       // Position of AFRL5 field.
	GPIO_AFRL_AFRL5_Msk = 0xf00000   // Bit mask of AFRL5 field.
	GPIO_AFRL_AFRL4_Pos = 0x10       // Position of AFRL4 field.
	GPIO_AFRL_AFRL4_Msk = 0xf0000    // Bit mask of AFRL4 field.
	GPIO_AFRL_AFRL3_Pos = 0xc        // Position of AFRL3 field.
	GPIO_AFRL_AFRL3_Msk = 0xf000     // Bit mask of AFRL3 field.
	GPIO_AFRL_AFRL2_Pos = 0x8        // Position of AFRL2 field.
	GPIO_AFRL_AFRL2_Msk = 0xf00      // Bit mask of AFRL2 field.
	GPIO_AFRL_AFRL1_Pos = 0x4        // Position of AFRL1 field.
	GPIO_AFRL_AFRL1_Msk = 0xf0       // Bit mask of AFRL1 field.
	GPIO_AFRL_AFRL0_Pos = 0x0        // Position of AFRL0 field.
	GPIO_AFRL_AFRL0_Msk = 0xf        // Bit mask of AFRL0 field.

	// AFRH: GPIO alternate function high           register
	GPIO_AFRH_AFRH15_Pos = 0x1c       // Position of AFRH15 field.
	GPIO_AFRH_AFRH15_Msk = 0xf0000000 // Bit mask of AFRH15 field.
	GPIO_AFRH_AFRH14_Pos = 0x18       // Position of AFRH14 field.
	GPIO_AFRH_AFRH14_Msk = 0xf000000  // Bit mask of AFRH14 field.
	GPIO_AFRH_AFRH13_Pos = 0x14       // Position of AFRH13 field.
	GPIO_AFRH_AFRH13_Msk = 0xf00000   // Bit mask of AFRH13 field.
	GPIO_AFRH_AFRH12_Pos = 0x10       // Position of AFRH12 field.
	GPIO_AFRH_AFRH12_Msk = 0xf0000    // Bit mask of AFRH12 field.
	GPIO_AFRH_AFRH11_Pos = 0xc        // Position of AFRH11 field.
	GPIO_AFRH_AFRH11_Msk = 0xf000     // Bit mask of AFRH11 field.
	GPIO_AFRH_AFRH10_Pos = 0x8        // Position of AFRH10 field.
	GPIO_AFRH_AFRH10_Msk = 0xf00      // Bit mask of AFRH10 field.
	GPIO_AFRH_AFRH9_Pos  = 0x4        // Position of AFRH9 field.
	GPIO_AFRH_AFRH9_Msk  = 0xf0       // Bit mask of AFRH9 field.
	GPIO_AFRH_AFRH8_Pos  = 0x0        // Position of AFRH8 field.
	GPIO_AFRH_AFRH8_Msk  = 0xf        // Bit mask of AFRH8 field.

	// BRR: GPIO port bit reset register
	GPIO_BRR_BR0_Pos  = 0x0    // Position of BR0 field.
	GPIO_BRR_BR0_Msk  = 0x1    // Bit mask of BR0 field.
	GPIO_BRR_BR0      = 0x1    // Bit BR0.
	GPIO_BRR_BR1_Pos  = 0x1    // Position of BR1 field.
	GPIO_BRR_BR1_Msk  = 0x2    // Bit mask of BR1 field.
	GPIO_BRR_BR1      = 0x2    // Bit BR1.
	GPIO_BRR_BR2_Pos  = 0x2    // Position of BR2 field.
	GPIO_BRR_BR2_Msk  = 0x4    // Bit mask of BR2 field.
	GPIO_BRR_BR2      = 0x4    // Bit BR2.
	GPIO_BRR_BR3_Pos  = 0x3    // Position of BR3 field.
	GPIO_BRR_BR3_Msk  = 0x8    // Bit mask of BR3 field.
	GPIO_BRR_BR3      = 0x8    // Bit BR3.
	GPIO_BRR_BR4_Pos  = 0x4    // Position of BR4 field.
	GPIO_BRR_BR4_Msk  = 0x10   // Bit mask of BR4 field.
	GPIO_BRR_BR4      = 0x10   // Bit BR4.
	GPIO_BRR_BR5_Pos  = 0x5    // Position of BR5 field.
	GPIO_BRR_BR5_Msk  = 0x20   // Bit mask of BR5 field.
	GPIO_BRR_BR5      = 0x20   // Bit BR5.
	GPIO_BRR_BR6_Pos  = 0x6    // Position of BR6 field.
	GPIO_BRR_BR6_Msk  = 0x40   // Bit mask of BR6 field.
	GPIO_BRR_BR6      = 0x40   // Bit BR6.
	GPIO_BRR_BR7_Pos  = 0x7    // Position of BR7 field.
	GPIO_BRR_BR7_Msk  = 0x80   // Bit mask of BR7 field.
	GPIO_BRR_BR7      = 0x80   // Bit BR7.
	GPIO_BRR_BR8_Pos  = 0x8    // Position of BR8 field.
	GPIO_BRR_BR8_Msk  = 0x100  // Bit mask of BR8 field.
	GPIO_BRR_BR8      = 0x100  // Bit BR8.
	GPIO_BRR_BR9_Pos  = 0x9    // Position of BR9 field.
	GPIO_BRR_BR9_Msk  = 0x200  // Bit mask of BR9 field.
	GPIO_BRR_BR9      = 0x200  // Bit BR9.
	GPIO_BRR_BR10_Pos = 0xa    // Position of BR10 field.
	GPIO_BRR_BR10_Msk = 0x400  // Bit mask of BR10 field.
	GPIO_BRR_BR10     = 0x400  // Bit BR10.
	GPIO_BRR_BR11_Pos = 0xb    // Position of BR11 field.
	GPIO_BRR_BR11_Msk = 0x800  // Bit mask of BR11 field.
	GPIO_BRR_BR11     = 0x800  // Bit BR11.
	GPIO_BRR_BR12_Pos = 0xc    // Position of BR12 field.
	GPIO_BRR_BR12_Msk = 0x1000 // Bit mask of BR12 field.
	GPIO_BRR_BR12     = 0x1000 // Bit BR12.
	GPIO_BRR_BR13_Pos = 0xd    // Position of BR13 field.
	GPIO_BRR_BR13_Msk = 0x2000 // Bit mask of BR13 field.
	GPIO_BRR_BR13     = 0x2000 // Bit BR13.
	GPIO_BRR_BR14_Pos = 0xe    // Position of BR14 field.
	GPIO_BRR_BR14_Msk = 0x4000 // Bit mask of BR14 field.
	GPIO_BRR_BR14     = 0x4000 // Bit BR14.
	GPIO_BRR_BR15_Pos = 0xf    // Position of BR15 field.
	GPIO_BRR_BR15_Msk = 0x8000 // Bit mask of BR15 field.
	GPIO_BRR_BR15     = 0x8000 // Bit BR15.
)

// Bitfields for TIM15: General purpose timers
const (
	// CR1: control register 1
	TIM_CR1_CEN_Pos      = 0x0    // Position of CEN field.
	TIM_CR1_CEN_Msk      = 0x1    // Bit mask of CEN field.
	TIM_CR1_CEN          = 0x1    // Bit CEN.
	TIM_CR1_UDIS_Pos     = 0x1    // Position of UDIS field.
	TIM_CR1_UDIS_Msk     = 0x2    // Bit mask of UDIS field.
	TIM_CR1_UDIS         = 0x2    // Bit UDIS.
	TIM_CR1_URS_Pos      = 0x2    // Position of URS field.
	TIM_CR1_URS_Msk      = 0x4    // Bit mask of URS field.
	TIM_CR1_URS          = 0x4    // Bit URS.
	TIM_CR1_OPM_Pos      = 0x3    // Position of OPM field.
	TIM_CR1_OPM_Msk      = 0x8    // Bit mask of OPM field.
	TIM_CR1_OPM          = 0x8    // Bit OPM.
	TIM_CR1_ARPE_Pos     = 0x7    // Position of ARPE field.
	TIM_CR1_ARPE_Msk     = 0x80   // Bit mask of ARPE field.
	TIM_CR1_ARPE         = 0x80   // Bit ARPE.
	TIM_CR1_CKD_Pos      = 0x8    // Position of CKD field.
	TIM_CR1_CKD_Msk      = 0x300  // Bit mask of CKD field.
	TIM_CR1_UIFREMAP_Pos = 0xb    // Position of UIFREMAP field.
	TIM_CR1_UIFREMAP_Msk = 0x800  // Bit mask of UIFREMAP field.
	TIM_CR1_UIFREMAP     = 0x800  // Bit UIFREMAP.
	TIM_CR1_DITHEN_Pos   = 0xc    // Position of DITHEN field.
	TIM_CR1_DITHEN_Msk   = 0x1000 // Bit mask of DITHEN field.
	TIM_CR1_DITHEN       = 0x1000 // Bit DITHEN.

	// CR2: control register 2
	TIM_CR2_OIS2_Pos  = 0xa   // Position of OIS2 field.
	TIM_CR2_OIS2_Msk  = 0x400 // Bit mask of OIS2 field.
	TIM_CR2_OIS2      = 0x400 // Bit OIS2.
	TIM_CR2_OIS1N_Pos = 0x9   // Position of OIS1N field.
	TIM_CR2_OIS1N_Msk = 0x200 // Bit mask of OIS1N field.
	TIM_CR2_OIS1N     = 0x200 // Bit OIS1N.
	TIM_CR2_OIS1_Pos  = 0x8   // Position of OIS1 field.
	TIM_CR2_OIS1_Msk  = 0x100 // Bit mask of OIS1 field.
	TIM_CR2_OIS1      = 0x100 // Bit OIS1.
	TIM_CR2_TI1S_Pos  = 0x7   // Position of TI1S field.
	TIM_CR2_TI1S_Msk  = 0x80  // Bit mask of TI1S field.
	TIM_CR2_TI1S      = 0x80  // Bit TI1S.
	TIM_CR2_MMS_Pos   = 0x4   // Position of MMS field.
	TIM_CR2_MMS_Msk   = 0x70  // Bit mask of MMS field.
	TIM_CR2_CCDS_Pos  = 0x3   // Position of CCDS field.
	TIM_CR2_CCDS_Msk  = 0x8   // Bit mask of CCDS field.
	TIM_CR2_CCDS      = 0x8   // Bit CCDS.
	TIM_CR2_CCUS_Pos  = 0x2   // Position of CCUS field.
	TIM_CR2_CCUS_Msk  = 0x4   // Bit mask of CCUS field.
	TIM_CR2_CCUS      = 0x4   // Bit CCUS.
	TIM_CR2_CCPC_Pos  = 0x0   // Position of CCPC field.
	TIM_CR2_CCPC_Msk  = 0x1   // Bit mask of CCPC field.
	TIM_CR2_CCPC      = 0x1   // Bit CCPC.

	// SMCR: slave mode control register
	TIM_SMCR_TS_4_3_Pos = 0x14     // Position of TS_4_3 field.
	TIM_SMCR_TS_4_3_Msk = 0x300000 // Bit mask of TS_4_3 field.
	TIM_SMCR_SMS_3_Pos  = 0x10     // Position of SMS_3 field.
	TIM_SMCR_SMS_3_Msk  = 0x10000  // Bit mask of SMS_3 field.
	TIM_SMCR_SMS_3      = 0x10000  // Bit SMS_3.
	TIM_SMCR_MSM_Pos    = 0x7      // Position of MSM field.
	TIM_SMCR_MSM_Msk    = 0x80     // Bit mask of MSM field.
	TIM_SMCR_MSM        = 0x80     // Bit MSM.
	TIM_SMCR_TS_Pos     = 0x4      // Position of TS field.
	TIM_SMCR_TS_Msk     = 0x70     // Bit mask of TS field.
	TIM_SMCR_SMS_Pos    = 0x0      // Position of SMS field.
	TIM_SMCR_SMS_Msk    = 0x7      // Bit mask of SMS field.

	// DIER: DMA/Interrupt enable register
	TIM_DIER_TDE_Pos   = 0xe    // Position of TDE field.
	TIM_DIER_TDE_Msk   = 0x4000 // Bit mask of TDE field.
	TIM_DIER_TDE       = 0x4000 // Bit TDE.
	TIM_DIER_COMDE_Pos = 0xd    // Position of COMDE field.
	TIM_DIER_COMDE_Msk = 0x2000 // Bit mask of COMDE field.
	TIM_DIER_COMDE     = 0x2000 // Bit COMDE.
	TIM_DIER_CC2DE_Pos = 0xa    // Position of CC2DE field.
	TIM_DIER_CC2DE_Msk = 0x400  // Bit mask of CC2DE field.
	TIM_DIER_CC2DE     = 0x400  // Bit CC2DE.
	TIM_DIER_CC1DE_Pos = 0x9    // Position of CC1DE field.
	TIM_DIER_CC1DE_Msk = 0x200  // Bit mask of CC1DE field.
	TIM_DIER_CC1DE     = 0x200  // Bit CC1DE.
	TIM_DIER_UDE_Pos   = 0x8    // Position of UDE field.
	TIM_DIER_UDE_Msk   = 0x100  // Bit mask of UDE field.
	TIM_DIER_UDE       = 0x100  // Bit UDE.
	TIM_DIER_BIE_Pos   = 0x7    // Position of BIE field.
	TIM_DIER_BIE_Msk   = 0x80   // Bit mask of BIE field.
	TIM_DIER_BIE       = 0x80   // Bit BIE.
	TIM_DIER_TIE_Pos   = 0x6    // Position of TIE field.
	TIM_DIER_TIE_Msk   = 0x40   // Bit mask of TIE field.
	TIM_DIER_TIE       = 0x40   // Bit TIE.
	TIM_DIER_COMIE_Pos = 0x5    // Position of COMIE field.
	TIM_DIER_COMIE_Msk = 0x20   // Bit mask of COMIE field.
	TIM_DIER_COMIE     = 0x20   // Bit COMIE.
	TIM_DIER_CC2IE_Pos = 0x2    // Position of CC2IE field.
	TIM_DIER_CC2IE_Msk = 0x4    // Bit mask of CC2IE field.
	TIM_DIER_CC2IE     = 0x4    // Bit CC2IE.
	TIM_DIER_CC1IE_Pos = 0x1    // Position of CC1IE field.
	TIM_DIER_CC1IE_Msk = 0x2    // Bit mask of CC1IE field.
	TIM_DIER_CC1IE     = 0x2    // Bit CC1IE.
	TIM_DIER_UIE_Pos   = 0x0    // Position of UIE field.
	TIM_DIER_UIE_Msk   = 0x1    // Bit mask of UIE field.
	TIM_DIER_UIE       = 0x1    // Bit UIE.

	// SR: status register
	TIM_SR_CC2OF_Pos = 0xa   // Position of CC2OF field.
	TIM_SR_CC2OF_Msk = 0x400 // Bit mask of CC2OF field.
	TIM_SR_CC2OF     = 0x400 // Bit CC2OF.
	TIM_SR_CC1OF_Pos = 0x9   // Position of CC1OF field.
	TIM_SR_CC1OF_Msk = 0x200 // Bit mask of CC1OF field.
	TIM_SR_CC1OF     = 0x200 // Bit CC1OF.
	TIM_SR_BIF_Pos   = 0x7   // Position of BIF field.
	TIM_SR_BIF_Msk   = 0x80  // Bit mask of BIF field.
	TIM_SR_BIF       = 0x80  // Bit BIF.
	TIM_SR_TIF_Pos   = 0x6   // Position of TIF field.
	TIM_SR_TIF_Msk   = 0x40  // Bit mask of TIF field.
	TIM_SR_TIF       = 0x40  // Bit TIF.
	TIM_SR_COMIF_Pos = 0x5   // Position of COMIF field.
	TIM_SR_COMIF_Msk = 0x20  // Bit mask of COMIF field.
	TIM_SR_COMIF     = 0x20  // Bit COMIF.
	TIM_SR_CC2IF_Pos = 0x2   // Position of CC2IF field.
	TIM_SR_CC2IF_Msk = 0x4   // Bit mask of CC2IF field.
	TIM_SR_CC2IF     = 0x4   // Bit CC2IF.
	TIM_SR_CC1IF_Pos = 0x1   // Position of CC1IF field.
	TIM_SR_CC1IF_Msk = 0x2   // Bit mask of CC1IF field.
	TIM_SR_CC1IF     = 0x2   // Bit CC1IF.
	TIM_SR_UIF_Pos   = 0x0   // Position of UIF field.
	TIM_SR_UIF_Msk   = 0x1   // Bit mask of UIF field.
	TIM_SR_UIF       = 0x1   // Bit UIF.

	// EGR: event generation register
	TIM_EGR_BG_Pos   = 0x7  // Position of BG field.
	TIM_EGR_BG_Msk   = 0x80 // Bit mask of BG field.
	TIM_EGR_BG       = 0x80 // Bit BG.
	TIM_EGR_TG_Pos   = 0x6  // Position of TG field.
	TIM_EGR_TG_Msk   = 0x40 // Bit mask of TG field.
	TIM_EGR_TG       = 0x40 // Bit TG.
	TIM_EGR_COMG_Pos = 0x5  // Position of COMG field.
	TIM_EGR_COMG_Msk = 0x20 // Bit mask of COMG field.
	TIM_EGR_COMG     = 0x20 // Bit COMG.
	TIM_EGR_CC2G_Pos = 0x2  // Position of CC2G field.
	TIM_EGR_CC2G_Msk = 0x4  // Bit mask of CC2G field.
	TIM_EGR_CC2G     = 0x4  // Bit CC2G.
	TIM_EGR_CC1G_Pos = 0x1  // Position of CC1G field.
	TIM_EGR_CC1G_Msk = 0x2  // Bit mask of CC1G field.
	TIM_EGR_CC1G     = 0x2  // Bit CC1G.
	TIM_EGR_UG_Pos   = 0x0  // Position of UG field.
	TIM_EGR_UG_Msk   = 0x1  // Bit mask of UG field.
	TIM_EGR_UG       = 0x1  // Bit UG.

	// CCMR1_Output: capture/compare mode register (output           mode)
	TIM_CCMR1_Output_OC2M_3_Pos = 0x18      // Position of OC2M_3 field.
	TIM_CCMR1_Output_OC2M_3_Msk = 0x1000000 // Bit mask of OC2M_3 field.
	TIM_CCMR1_Output_OC2M_3     = 0x1000000 // Bit OC2M_3.
	TIM_CCMR1_Output_OC1M_3_Pos = 0x10      // Position of OC1M_3 field.
	TIM_CCMR1_Output_OC1M_3_Msk = 0x10000   // Bit mask of OC1M_3 field.
	TIM_CCMR1_Output_OC1M_3     = 0x10000   // Bit OC1M_3.
	TIM_CCMR1_Output_OC2M_Pos   = 0xc       // Position of OC2M field.
	TIM_CCMR1_Output_OC2M_Msk   = 0x7000    // Bit mask of OC2M field.
	TIM_CCMR1_Output_OC2PE_Pos  = 0xb       // Position of OC2PE field.
	TIM_CCMR1_Output_OC2PE_Msk  = 0x800     // Bit mask of OC2PE field.
	TIM_CCMR1_Output_OC2PE      = 0x800     // Bit OC2PE.
	TIM_CCMR1_Output_OC2FE_Pos  = 0xa       // Position of OC2FE field.
	TIM_CCMR1_Output_OC2FE_Msk  = 0x400     // Bit mask of OC2FE field.
	TIM_CCMR1_Output_OC2FE      = 0x400     // Bit OC2FE.
	TIM_CCMR1_Output_CC2S_Pos   = 0x8       // Position of CC2S field.
	TIM_CCMR1_Output_CC2S_Msk   = 0x300     // Bit mask of CC2S field.
	TIM_CCMR1_Output_OC1CE_Pos  = 0x7       // Position of OC1CE field.
	TIM_CCMR1_Output_OC1CE_Msk  = 0x80      // Bit mask of OC1CE field.
	TIM_CCMR1_Output_OC1CE      = 0x80      // Bit OC1CE.
	TIM_CCMR1_Output_OC1M_Pos   = 0x4       // Position of OC1M field.
	TIM_CCMR1_Output_OC1M_Msk   = 0x70      // Bit mask of OC1M field.
	TIM_CCMR1_Output_OC1PE_Pos  = 0x3       // Position of OC1PE field.
	TIM_CCMR1_Output_OC1PE_Msk  = 0x8       // Bit mask of OC1PE field.
	TIM_CCMR1_Output_OC1PE      = 0x8       // Bit OC1PE.
	TIM_CCMR1_Output_OC1FE_Pos  = 0x2       // Position of OC1FE field.
	TIM_CCMR1_Output_OC1FE_Msk  = 0x4       // Bit mask of OC1FE field.
	TIM_CCMR1_Output_OC1FE      = 0x4       // Bit OC1FE.
	TIM_CCMR1_Output_CC1S_Pos   = 0x0       // Position of CC1S field.
	TIM_CCMR1_Output_CC1S_Msk   = 0x3       // Bit mask of CC1S field.

	// CCMR1_Input: capture/compare mode register 1 (input           mode)
	TIM_CCMR1_Input_IC2F_Pos   = 0xc    // Position of IC2F field.
	TIM_CCMR1_Input_IC2F_Msk   = 0xf000 // Bit mask of IC2F field.
	TIM_CCMR1_Input_IC2PSC_Pos = 0xa    // Position of IC2PSC field.
	TIM_CCMR1_Input_IC2PSC_Msk = 0xc00  // Bit mask of IC2PSC field.
	TIM_CCMR1_Input_CC2S_Pos   = 0x8    // Position of CC2S field.
	TIM_CCMR1_Input_CC2S_Msk   = 0x300  // Bit mask of CC2S field.
	TIM_CCMR1_Input_IC1F_Pos   = 0x4    // Position of IC1F field.
	TIM_CCMR1_Input_IC1F_Msk   = 0xf0   // Bit mask of IC1F field.
	TIM_CCMR1_Input_IC1PSC_Pos = 0x2    // Position of IC1PSC field.
	TIM_CCMR1_Input_IC1PSC_Msk = 0xc    // Bit mask of IC1PSC field.
	TIM_CCMR1_Input_CC1S_Pos   = 0x0    // Position of CC1S field.
	TIM_CCMR1_Input_CC1S_Msk   = 0x3    // Bit mask of CC1S field.

	// CCER: capture/compare enable           register
	TIM_CCER_CC2NP_Pos = 0x7  // Position of CC2NP field.
	TIM_CCER_CC2NP_Msk = 0x80 // Bit mask of CC2NP field.
	TIM_CCER_CC2NP     = 0x80 // Bit CC2NP.
	TIM_CCER_CC2P_Pos  = 0x5  // Position of CC2P field.
	TIM_CCER_CC2P_Msk  = 0x20 // Bit mask of CC2P field.
	TIM_CCER_CC2P      = 0x20 // Bit CC2P.
	TIM_CCER_CC2E_Pos  = 0x4  // Position of CC2E field.
	TIM_CCER_CC2E_Msk  = 0x10 // Bit mask of CC2E field.
	TIM_CCER_CC2E      = 0x10 // Bit CC2E.
	TIM_CCER_CC1NP_Pos = 0x3  // Position of CC1NP field.
	TIM_CCER_CC1NP_Msk = 0x8  // Bit mask of CC1NP field.
	TIM_CCER_CC1NP     = 0x8  // Bit CC1NP.
	TIM_CCER_CC1NE_Pos = 0x2  // Position of CC1NE field.
	TIM_CCER_CC1NE_Msk = 0x4  // Bit mask of CC1NE field.
	TIM_CCER_CC1NE     = 0x4  // Bit CC1NE.
	TIM_CCER_CC1P_Pos  = 0x1  // Position of CC1P field.
	TIM_CCER_CC1P_Msk  = 0x2  // Bit mask of CC1P field.
	TIM_CCER_CC1P      = 0x2  // Bit CC1P.
	TIM_CCER_CC1E_Pos  = 0x0  // Position of CC1E field.
	TIM_CCER_CC1E_Msk  = 0x1  // Bit mask of CC1E field.
	TIM_CCER_CC1E      = 0x1  // Bit CC1E.

	// CNT: counter
	TIM_CNT_CNT_Pos    = 0x0        // Position of CNT field.
	TIM_CNT_CNT_Msk    = 0xffff     // Bit mask of CNT field.
	TIM_CNT_UIFCPY_Pos = 0x1f       // Position of UIFCPY field.
	TIM_CNT_UIFCPY_Msk = 0x80000000 // Bit mask of UIFCPY field.
	TIM_CNT_UIFCPY     = 0x80000000 // Bit UIFCPY.

	// PSC: prescaler
	TIM_PSC_PSC_Pos = 0x0    // Position of PSC field.
	TIM_PSC_PSC_Msk = 0xffff // Bit mask of PSC field.

	// ARR: auto-reload register
	TIM_ARR_ARR_Pos = 0x0    // Position of ARR field.
	TIM_ARR_ARR_Msk = 0xffff // Bit mask of ARR field.

	// RCR: repetition counter register
	TIM_RCR_REP_Pos = 0x0  // Position of REP field.
	TIM_RCR_REP_Msk = 0xff // Bit mask of REP field.

	// CCR1: capture/compare register 1
	TIM_CCR1_CCR1_Pos = 0x0    // Position of CCR1 field.
	TIM_CCR1_CCR1_Msk = 0xffff // Bit mask of CCR1 field.

	// CCR2: capture/compare register 2
	TIM_CCR2_CCR2_Pos = 0x0    // Position of CCR2 field.
	TIM_CCR2_CCR2_Msk = 0xffff // Bit mask of CCR2 field.

	// BDTR: break and dead-time register
	TIM_BDTR_DTG_Pos    = 0x0        // Position of DTG field.
	TIM_BDTR_DTG_Msk    = 0xff       // Bit mask of DTG field.
	TIM_BDTR_LOCK_Pos   = 0x8        // Position of LOCK field.
	TIM_BDTR_LOCK_Msk   = 0x300      // Bit mask of LOCK field.
	TIM_BDTR_OSSI_Pos   = 0xa        // Position of OSSI field.
	TIM_BDTR_OSSI_Msk   = 0x400      // Bit mask of OSSI field.
	TIM_BDTR_OSSI       = 0x400      // Bit OSSI.
	TIM_BDTR_OSSR_Pos   = 0xb        // Position of OSSR field.
	TIM_BDTR_OSSR_Msk   = 0x800      // Bit mask of OSSR field.
	TIM_BDTR_OSSR       = 0x800      // Bit OSSR.
	TIM_BDTR_BKE_Pos    = 0xc        // Position of BKE field.
	TIM_BDTR_BKE_Msk    = 0x1000     // Bit mask of BKE field.
	TIM_BDTR_BKE        = 0x1000     // Bit BKE.
	TIM_BDTR_BKP_Pos    = 0xd        // Position of BKP field.
	TIM_BDTR_BKP_Msk    = 0x2000     // Bit mask of BKP field.
	TIM_BDTR_BKP        = 0x2000     // Bit BKP.
	TIM_BDTR_AOE_Pos    = 0xe        // Position of AOE field.
	TIM_BDTR_AOE_Msk    = 0x4000     // Bit mask of AOE field.
	TIM_BDTR_AOE        = 0x4000     // Bit AOE.
	TIM_BDTR_MOE_Pos    = 0xf        // Position of MOE field.
	TIM_BDTR_MOE_Msk    = 0x8000     // Bit mask of MOE field.
	TIM_BDTR_MOE        = 0x8000     // Bit MOE.
	TIM_BDTR_BKF_Pos    = 0x10       // Position of BKF field.
	TIM_BDTR_BKF_Msk    = 0xf0000    // Bit mask of BKF field.
	TIM_BDTR_BKDSRM_Pos = 0x1a       // Position of BKDSRM field.
	TIM_BDTR_BKDSRM_Msk = 0x4000000  // Bit mask of BKDSRM field.
	TIM_BDTR_BKDSRM     = 0x4000000  // Bit BKDSRM.
	TIM_BDTR_BKBID_Pos  = 0x1c       // Position of BKBID field.
	TIM_BDTR_BKBID_Msk  = 0x10000000 // Bit mask of BKBID field.
	TIM_BDTR_BKBID      = 0x10000000 // Bit BKBID.

	// DTR2: timer Deadtime Register 2
	TIM_DTR2_DTGF_Pos = 0x0     // Position of DTGF field.
	TIM_DTR2_DTGF_Msk = 0xff    // Bit mask of DTGF field.
	TIM_DTR2_DTAE_Pos = 0x10    // Position of DTAE field.
	TIM_DTR2_DTAE_Msk = 0x10000 // Bit mask of DTAE field.
	TIM_DTR2_DTAE     = 0x10000 // Bit DTAE.
	TIM_DTR2_DTPE_Pos = 0x11    // Position of DTPE field.
	TIM_DTR2_DTPE_Msk = 0x20000 // Bit mask of DTPE field.
	TIM_DTR2_DTPE     = 0x20000 // Bit DTPE.

	// TISEL: TIM timer input selection           register
	TIM_TISEL_TI1SEL_Pos = 0x0   // Position of TI1SEL field.
	TIM_TISEL_TI1SEL_Msk = 0xf   // Bit mask of TI1SEL field.
	TIM_TISEL_TI2SEL_Pos = 0x8   // Position of TI2SEL field.
	TIM_TISEL_TI2SEL_Msk = 0xf00 // Bit mask of TI2SEL field.

	// AF1: TIM alternate function option register           1
	TIM_AF1_BKCMP4P_Pos = 0xd    // Position of BKCMP4P field.
	TIM_AF1_BKCMP4P_Msk = 0x2000 // Bit mask of BKCMP4P field.
	TIM_AF1_BKCMP4P     = 0x2000 // Bit BKCMP4P.
	TIM_AF1_BKCMP3P_Pos = 0xc    // Position of BKCMP3P field.
	TIM_AF1_BKCMP3P_Msk = 0x1000 // Bit mask of BKCMP3P field.
	TIM_AF1_BKCMP3P     = 0x1000 // Bit BKCMP3P.
	TIM_AF1_BKCMP2P_Pos = 0xb    // Position of BKCMP2P field.
	TIM_AF1_BKCMP2P_Msk = 0x800  // Bit mask of BKCMP2P field.
	TIM_AF1_BKCMP2P     = 0x800  // Bit BKCMP2P.
	TIM_AF1_BKCMP1P_Pos = 0xa    // Position of BKCMP1P field.
	TIM_AF1_BKCMP1P_Msk = 0x400  // Bit mask of BKCMP1P field.
	TIM_AF1_BKCMP1P     = 0x400  // Bit BKCMP1P.
	TIM_AF1_BKINP_Pos   = 0x9    // Position of BKINP field.
	TIM_AF1_BKINP_Msk   = 0x200  // Bit mask of BKINP field.
	TIM_AF1_BKINP       = 0x200  // Bit BKINP.
	TIM_AF1_BKCMP7E_Pos = 0x7    // Position of BKCMP7E field.
	TIM_AF1_BKCMP7E_Msk = 0x80   // Bit mask of BKCMP7E field.
	TIM_AF1_BKCMP7E     = 0x80   // Bit BKCMP7E.
	TIM_AF1_BKCMP6E_Pos = 0x6    // Position of BKCMP6E field.
	TIM_AF1_BKCMP6E_Msk = 0x40   // Bit mask of BKCMP6E field.
	TIM_AF1_BKCMP6E     = 0x40   // Bit BKCMP6E.
	TIM_AF1_BKCMP5E_Pos = 0x5    // Position of BKCMP5E field.
	TIM_AF1_BKCMP5E_Msk = 0x20   // Bit mask of BKCMP5E field.
	TIM_AF1_BKCMP5E     = 0x20   // Bit BKCMP5E.
	TIM_AF1_BKCMP4E_Pos = 0x4    // Position of BKCMP4E field.
	TIM_AF1_BKCMP4E_Msk = 0x10   // Bit mask of BKCMP4E field.
	TIM_AF1_BKCMP4E     = 0x10   // Bit BKCMP4E.
	TIM_AF1_BKCMP3E_Pos = 0x3    // Position of BKCMP3E field.
	TIM_AF1_BKCMP3E_Msk = 0x8    // Bit mask of BKCMP3E field.
	TIM_AF1_BKCMP3E     = 0x8    // Bit BKCMP3E.
	TIM_AF1_BKCMP2E_Pos = 0x2    // Position of BKCMP2E field.
	TIM_AF1_BKCMP2E_Msk = 0x4    // Bit mask of BKCMP2E field.
	TIM_AF1_BKCMP2E     = 0x4    // Bit BKCMP2E.
	TIM_AF1_BKCMP1E_Pos = 0x1    // Position of BKCMP1E field.
	TIM_AF1_BKCMP1E_Msk = 0x2    // Bit mask of BKCMP1E field.
	TIM_AF1_BKCMP1E     = 0x2    // Bit BKCMP1E.
	TIM_AF1_BKINE_Pos   = 0x0    // Position of BKINE field.
	TIM_AF1_BKINE_Msk   = 0x1    // Bit mask of BKINE field.
	TIM_AF1_BKINE       = 0x1    // Bit BKINE.

	// AF2: TIM alternate function option register           2
	TIM_AF2_OCRSEL_Pos = 0x10    // Position of OCRSEL field.
	TIM_AF2_OCRSEL_Msk = 0x70000 // Bit mask of OCRSEL field.

	// DCR: DMA control register
	TIM_DCR_DBL_Pos = 0x8    // Position of DBL field.
	TIM_DCR_DBL_Msk = 0x1f00 // Bit mask of DBL field.
	TIM_DCR_DBA_Pos = 0x0    // Position of DBA field.
	TIM_DCR_DBA_Msk = 0x1f   // Bit mask of DBA field.

	// DMAR: DMA address for full transfer
	TIM_DMAR_DMAB_Pos = 0x0        // Position of DMAB field.
	TIM_DMAR_DMAB_Msk = 0xffffffff // Bit mask of DMAB field.
)

// Bitfields for LPTIMER1: Low power timer
const (
	// ISR: Interrupt and Status Register
	LPTIM_ISR_DOWN_Pos    = 0x6  // Position of DOWN field.
	LPTIM_ISR_DOWN_Msk    = 0x40 // Bit mask of DOWN field.
	LPTIM_ISR_DOWN        = 0x40 // Bit DOWN.
	LPTIM_ISR_UP_Pos      = 0x5  // Position of UP field.
	LPTIM_ISR_UP_Msk      = 0x20 // Bit mask of UP field.
	LPTIM_ISR_UP          = 0x20 // Bit UP.
	LPTIM_ISR_ARROK_Pos   = 0x4  // Position of ARROK field.
	LPTIM_ISR_ARROK_Msk   = 0x10 // Bit mask of ARROK field.
	LPTIM_ISR_ARROK       = 0x10 // Bit ARROK.
	LPTIM_ISR_CMPOK_Pos   = 0x3  // Position of CMPOK field.
	LPTIM_ISR_CMPOK_Msk   = 0x8  // Bit mask of CMPOK field.
	LPTIM_ISR_CMPOK       = 0x8  // Bit CMPOK.
	LPTIM_ISR_EXTTRIG_Pos = 0x2  // Position of EXTTRIG field.
	LPTIM_ISR_EXTTRIG_Msk = 0x4  // Bit mask of EXTTRIG field.
	LPTIM_ISR_EXTTRIG     = 0x4  // Bit EXTTRIG.
	LPTIM_ISR_ARRM_Pos    = 0x1  // Position of ARRM field.
	LPTIM_ISR_ARRM_Msk    = 0x2  // Bit mask of ARRM field.
	LPTIM_ISR_ARRM        = 0x2  // Bit ARRM.
	LPTIM_ISR_CMPM_Pos    = 0x0  // Position of CMPM field.
	LPTIM_ISR_CMPM_Msk    = 0x1  // Bit mask of CMPM field.
	LPTIM_ISR_CMPM        = 0x1  // Bit CMPM.

	// ICR: Interrupt Clear Register
	LPTIM_ICR_DOWNCF_Pos    = 0x6  // Position of DOWNCF field.
	LPTIM_ICR_DOWNCF_Msk    = 0x40 // Bit mask of DOWNCF field.
	LPTIM_ICR_DOWNCF        = 0x40 // Bit DOWNCF.
	LPTIM_ICR_UPCF_Pos      = 0x5  // Position of UPCF field.
	LPTIM_ICR_UPCF_Msk      = 0x20 // Bit mask of UPCF field.
	LPTIM_ICR_UPCF          = 0x20 // Bit UPCF.
	LPTIM_ICR_ARROKCF_Pos   = 0x4  // Position of ARROKCF field.
	LPTIM_ICR_ARROKCF_Msk   = 0x10 // Bit mask of ARROKCF field.
	LPTIM_ICR_ARROKCF       = 0x10 // Bit ARROKCF.
	LPTIM_ICR_CMPOKCF_Pos   = 0x3  // Position of CMPOKCF field.
	LPTIM_ICR_CMPOKCF_Msk   = 0x8  // Bit mask of CMPOKCF field.
	LPTIM_ICR_CMPOKCF       = 0x8  // Bit CMPOKCF.
	LPTIM_ICR_EXTTRIGCF_Pos = 0x2  // Position of EXTTRIGCF field.
	LPTIM_ICR_EXTTRIGCF_Msk = 0x4  // Bit mask of EXTTRIGCF field.
	LPTIM_ICR_EXTTRIGCF     = 0x4  // Bit EXTTRIGCF.
	LPTIM_ICR_ARRMCF_Pos    = 0x1  // Position of ARRMCF field.
	LPTIM_ICR_ARRMCF_Msk    = 0x2  // Bit mask of ARRMCF field.
	LPTIM_ICR_ARRMCF        = 0x2  // Bit ARRMCF.
	LPTIM_ICR_CMPMCF_Pos    = 0x0  // Position of CMPMCF field.
	LPTIM_ICR_CMPMCF_Msk    = 0x1  // Bit mask of CMPMCF field.
	LPTIM_ICR_CMPMCF        = 0x1  // Bit CMPMCF.

	// IER: Interrupt Enable Register
	LPTIM_IER_DOWNIE_Pos    = 0x6  // Position of DOWNIE field.
	LPTIM_IER_DOWNIE_Msk    = 0x40 // Bit mask of DOWNIE field.
	LPTIM_IER_DOWNIE        = 0x40 // Bit DOWNIE.
	LPTIM_IER_UPIE_Pos      = 0x5  // Position of UPIE field.
	LPTIM_IER_UPIE_Msk      = 0x20 // Bit mask of UPIE field.
	LPTIM_IER_UPIE          = 0x20 // Bit UPIE.
	LPTIM_IER_ARROKIE_Pos   = 0x4  // Position of ARROKIE field.
	LPTIM_IER_ARROKIE_Msk   = 0x10 // Bit mask of ARROKIE field.
	LPTIM_IER_ARROKIE       = 0x10 // Bit ARROKIE.
	LPTIM_IER_CMPOKIE_Pos   = 0x3  // Position of CMPOKIE field.
	LPTIM_IER_CMPOKIE_Msk   = 0x8  // Bit mask of CMPOKIE field.
	LPTIM_IER_CMPOKIE       = 0x8  // Bit CMPOKIE.
	LPTIM_IER_EXTTRIGIE_Pos = 0x2  // Position of EXTTRIGIE field.
	LPTIM_IER_EXTTRIGIE_Msk = 0x4  // Bit mask of EXTTRIGIE field.
	LPTIM_IER_EXTTRIGIE     = 0x4  // Bit EXTTRIGIE.
	LPTIM_IER_ARRMIE_Pos    = 0x1  // Position of ARRMIE field.
	LPTIM_IER_ARRMIE_Msk    = 0x2  // Bit mask of ARRMIE field.
	LPTIM_IER_ARRMIE        = 0x2  // Bit ARRMIE.
	LPTIM_IER_CMPMIE_Pos    = 0x0  // Position of CMPMIE field.
	LPTIM_IER_CMPMIE_Msk    = 0x1  // Bit mask of CMPMIE field.
	LPTIM_IER_CMPMIE        = 0x1  // Bit CMPMIE.

	// CFGR: Configuration Register
	LPTIM_CFGR_ENC_Pos       = 0x18      // Position of ENC field.
	LPTIM_CFGR_ENC_Msk       = 0x1000000 // Bit mask of ENC field.
	LPTIM_CFGR_ENC           = 0x1000000 // Bit ENC.
	LPTIM_CFGR_COUNTMODE_Pos = 0x17      // Position of COUNTMODE field.
	LPTIM_CFGR_COUNTMODE_Msk = 0x800000  // Bit mask of COUNTMODE field.
	LPTIM_CFGR_COUNTMODE     = 0x800000  // Bit COUNTMODE.
	LPTIM_CFGR_PRELOAD_Pos   = 0x16      // Position of PRELOAD field.
	LPTIM_CFGR_PRELOAD_Msk   = 0x400000  // Bit mask of PRELOAD field.
	LPTIM_CFGR_PRELOAD       = 0x400000  // Bit PRELOAD.
	LPTIM_CFGR_WAVPOL_Pos    = 0x15      // Position of WAVPOL field.
	LPTIM_CFGR_WAVPOL_Msk    = 0x200000  // Bit mask of WAVPOL field.
	LPTIM_CFGR_WAVPOL        = 0x200000  // Bit WAVPOL.
	LPTIM_CFGR_WAVE_Pos      = 0x14      // Position of WAVE field.
	LPTIM_CFGR_WAVE_Msk      = 0x100000  // Bit mask of WAVE field.
	LPTIM_CFGR_WAVE          = 0x100000  // Bit WAVE.
	LPTIM_CFGR_TIMOUT_Pos    = 0x13      // Position of TIMOUT field.
	LPTIM_CFGR_TIMOUT_Msk    = 0x80000   // Bit mask of TIMOUT field.
	LPTIM_CFGR_TIMOUT        = 0x80000   // Bit TIMOUT.
	LPTIM_CFGR_TRIGEN_Pos    = 0x11      // Position of TRIGEN field.
	LPTIM_CFGR_TRIGEN_Msk    = 0x60000   // Bit mask of TRIGEN field.
	LPTIM_CFGR_TRIGSEL_Pos   = 0xd       // Position of TRIGSEL field.
	LPTIM_CFGR_TRIGSEL_Msk   = 0x1e000   // Bit mask of TRIGSEL field.
	LPTIM_CFGR_PRESC_Pos     = 0x9       // Position of PRESC field.
	LPTIM_CFGR_PRESC_Msk     = 0xe00     // Bit mask of PRESC field.
	LPTIM_CFGR_TRGFLT_Pos    = 0x6       // Position of TRGFLT field.
	LPTIM_CFGR_TRGFLT_Msk    = 0xc0      // Bit mask of TRGFLT field.
	LPTIM_CFGR_CKFLT_Pos     = 0x3       // Position of CKFLT field.
	LPTIM_CFGR_CKFLT_Msk     = 0x18      // Bit mask of CKFLT field.
	LPTIM_CFGR_CKPOL_Pos     = 0x1       // Position of CKPOL field.
	LPTIM_CFGR_CKPOL_Msk     = 0x6       // Bit mask of CKPOL field.
	LPTIM_CFGR_CKSEL_Pos     = 0x0       // Position of CKSEL field.
	LPTIM_CFGR_CKSEL_Msk     = 0x1       // Bit mask of CKSEL field.
	LPTIM_CFGR_CKSEL         = 0x1       // Bit CKSEL.

	// CR: Control Register
	LPTIM_CR_RSTARE_Pos   = 0x4  // Position of RSTARE field.
	LPTIM_CR_RSTARE_Msk   = 0x10 // Bit mask of RSTARE field.
	LPTIM_CR_RSTARE       = 0x10 // Bit RSTARE.
	LPTIM_CR_COUNTRST_Pos = 0x3  // Position of COUNTRST field.
	LPTIM_CR_COUNTRST_Msk = 0x8  // Bit mask of COUNTRST field.
	LPTIM_CR_COUNTRST     = 0x8  // Bit COUNTRST.
	LPTIM_CR_CNTSTRT_Pos  = 0x2  // Position of CNTSTRT field.
	LPTIM_CR_CNTSTRT_Msk  = 0x4  // Bit mask of CNTSTRT field.
	LPTIM_CR_CNTSTRT      = 0x4  // Bit CNTSTRT.
	LPTIM_CR_SNGSTRT_Pos  = 0x1  // Position of SNGSTRT field.
	LPTIM_CR_SNGSTRT_Msk  = 0x2  // Bit mask of SNGSTRT field.
	LPTIM_CR_SNGSTRT      = 0x2  // Bit SNGSTRT.
	LPTIM_CR_ENABLE_Pos   = 0x0  // Position of ENABLE field.
	LPTIM_CR_ENABLE_Msk   = 0x1  // Bit mask of ENABLE field.
	LPTIM_CR_ENABLE       = 0x1  // Bit ENABLE.

	// CMP: Compare Register
	LPTIM_CMP_CMP_Pos = 0x0    // Position of CMP field.
	LPTIM_CMP_CMP_Msk = 0xffff // Bit mask of CMP field.

	// ARR: Autoreload Register
	LPTIM_ARR_ARR_Pos = 0x0    // Position of ARR field.
	LPTIM_ARR_ARR_Msk = 0xffff // Bit mask of ARR field.

	// CNT: Counter Register
	LPTIM_CNT_CNT_Pos = 0x0    // Position of CNT field.
	LPTIM_CNT_CNT_Msk = 0xffff // Bit mask of CNT field.

	// OR: option register
	LPTIM_OR_IN1_Pos     = 0x0  // Position of IN1 field.
	LPTIM_OR_IN1_Msk     = 0x1  // Bit mask of IN1 field.
	LPTIM_OR_IN1         = 0x1  // Bit IN1.
	LPTIM_OR_IN2_Pos     = 0x1  // Position of IN2 field.
	LPTIM_OR_IN2_Msk     = 0x2  // Bit mask of IN2 field.
	LPTIM_OR_IN2         = 0x2  // Bit IN2.
	LPTIM_OR_IN1_2_1_Pos = 0x2  // Position of IN1_2_1 field.
	LPTIM_OR_IN1_2_1_Msk = 0xc  // Bit mask of IN1_2_1 field.
	LPTIM_OR_IN2_2_1_Pos = 0x4  // Position of IN2_2_1 field.
	LPTIM_OR_IN2_2_1_Msk = 0x30 // Bit mask of IN2_2_1 field.
)

// Bitfields for USART1: Universal synchronous asynchronous receiver transmitter
const (
	// CR1: Control register 1
	USART_CR1_RXFFIE_Pos = 0x1f       // Position of RXFFIE field.
	USART_CR1_RXFFIE_Msk = 0x80000000 // Bit mask of RXFFIE field.
	USART_CR1_RXFFIE     = 0x80000000 // Bit RXFFIE.
	USART_CR1_TXFEIE_Pos = 0x1e       // Position of TXFEIE field.
	USART_CR1_TXFEIE_Msk = 0x40000000 // Bit mask of TXFEIE field.
	USART_CR1_TXFEIE     = 0x40000000 // Bit TXFEIE.
	USART_CR1_FIFOEN_Pos = 0x1d       // Position of FIFOEN field.
	USART_CR1_FIFOEN_Msk = 0x20000000 // Bit mask of FIFOEN field.
	USART_CR1_FIFOEN     = 0x20000000 // Bit FIFOEN.
	USART_CR1_M1_Pos     = 0x1c       // Position of M1 field.
	USART_CR1_M1_Msk     = 0x10000000 // Bit mask of M1 field.
	USART_CR1_M1         = 0x10000000 // Bit M1.
	USART_CR1_EOBIE_Pos  = 0x1b       // Position of EOBIE field.
	USART_CR1_EOBIE_Msk  = 0x8000000  // Bit mask of EOBIE field.
	USART_CR1_EOBIE      = 0x8000000  // Bit EOBIE.
	USART_CR1_RTOIE_Pos  = 0x1a       // Position of RTOIE field.
	USART_CR1_RTOIE_Msk  = 0x4000000  // Bit mask of RTOIE field.
	USART_CR1_RTOIE      = 0x4000000  // Bit RTOIE.
	USART_CR1_DEAT4_Pos  = 0x19       // Position of DEAT4 field.
	USART_CR1_DEAT4_Msk  = 0x2000000  // Bit mask of DEAT4 field.
	USART_CR1_DEAT4      = 0x2000000  // Bit DEAT4.
	USART_CR1_DEAT3_Pos  = 0x18       // Position of DEAT3 field.
	USART_CR1_DEAT3_Msk  = 0x1000000  // Bit mask of DEAT3 field.
	USART_CR1_DEAT3      = 0x1000000  // Bit DEAT3.
	USART_CR1_DEAT2_Pos  = 0x17       // Position of DEAT2 field.
	USART_CR1_DEAT2_Msk  = 0x800000   // Bit mask of DEAT2 field.
	USART_CR1_DEAT2      = 0x800000   // Bit DEAT2.
	USART_CR1_DEAT1_Pos  = 0x16       // Position of DEAT1 field.
	USART_CR1_DEAT1_Msk  = 0x400000   // Bit mask of DEAT1 field.
	USART_CR1_DEAT1      = 0x400000   // Bit DEAT1.
	USART_CR1_DEAT0_Pos  = 0x15       // Position of DEAT0 field.
	USART_CR1_DEAT0_Msk  = 0x200000   // Bit mask of DEAT0 field.
	USART_CR1_DEAT0      = 0x200000   // Bit DEAT0.
	USART_CR1_DEDT4_Pos  = 0x14       // Position of DEDT4 field.
	USART_CR1_DEDT4_Msk  = 0x100000   // Bit mask of DEDT4 field.
	USART_CR1_DEDT4      = 0x100000   // Bit DEDT4.
	USART_CR1_DEDT3_Pos  = 0x13       // Position of DEDT3 field.
	USART_CR1_DEDT3_Msk  = 0x80000    // Bit mask of DEDT3 field.
	USART_CR1_DEDT3      = 0x80000    // Bit DEDT3.
	USART_CR1_DEDT2_Pos  = 0x12       // Position of DEDT2 field.
	USART_CR1_DEDT2_Msk  = 0x40000    // Bit mask of DEDT2 field.
	USART_CR1_DEDT2      = 0x40000    // Bit DEDT2.
	USART_CR1_DEDT1_Pos  = 0x11       // Position of DEDT1 field.
	USART_CR1_DEDT1_Msk  = 0x20000    // Bit mask of DEDT1 field.
	USART_CR1_DEDT1      = 0x20000    // Bit DEDT1.
	USART_CR1_DEDT0_Pos  = 0x10       // Position of DEDT0 field.
	USART_CR1_DEDT0_Msk  = 0x10000    // Bit mask of DEDT0 field.
	USART_CR1_DEDT0      = 0x10000    // Bit DEDT0.
	USART_CR1_OVER8_Pos  = 0xf        // Position of OVER8 field.
	USART_CR1_OVER8_Msk  = 0x8000     // Bit mask of OVER8 field.
	USART_CR1_OVER8      = 0x8000     // Bit OVER8.
	USART_CR1_CMIE_Pos   = 0xe        // Position of CMIE field.
	USART_CR1_CMIE_Msk   = 0x4000     // Bit mask of CMIE field.
	USART_CR1_CMIE       = 0x4000     // Bit CMIE.
	USART_CR1_MME_Pos    = 0xd        // Position of MME field.
	USART_CR1_MME_Msk    = 0x2000     // Bit mask of MME field.
	USART_CR1_MME        = 0x2000     // Bit MME.
	USART_CR1_M0_Pos     = 0xc        // Position of M0 field.
	USART_CR1_M0_Msk     = 0x1000     // Bit mask of M0 field.
	USART_CR1_M0         = 0x1000     // Bit M0.
	USART_CR1_WAKE_Pos   = 0xb        // Position of WAKE field.
	USART_CR1_WAKE_Msk   = 0x800      // Bit mask of WAKE field.
	USART_CR1_WAKE       = 0x800      // Bit WAKE.
	USART_CR1_PCE_Pos    = 0xa        // Position of PCE field.
	USART_CR1_PCE_Msk    = 0x400      // Bit mask of PCE field.
	USART_CR1_PCE        = 0x400      // Bit PCE.
	USART_CR1_PS_Pos     = 0x9        // Position of PS field.
	USART_CR1_PS_Msk     = 0x200      // Bit mask of PS field.
	USART_CR1_PS         = 0x200      // Bit PS.
	USART_CR1_PEIE_Pos   = 0x8        // Position of PEIE field.
	USART_CR1_PEIE_Msk   = 0x100      // Bit mask of PEIE field.
	USART_CR1_PEIE       = 0x100      // Bit PEIE.
	USART_CR1_TXEIE_Pos  = 0x7        // Position of TXEIE field.
	USART_CR1_TXEIE_Msk  = 0x80       // Bit mask of TXEIE field.
	USART_CR1_TXEIE      = 0x80       // Bit TXEIE.
	USART_CR1_TCIE_Pos   = 0x6        // Position of TCIE field.
	USART_CR1_TCIE_Msk   = 0x40       // Bit mask of TCIE field.
	USART_CR1_TCIE       = 0x40       // Bit TCIE.
	USART_CR1_RXNEIE_Pos = 0x5        // Position of RXNEIE field.
	USART_CR1_RXNEIE_Msk = 0x20       // Bit mask of RXNEIE field.
	USART_CR1_RXNEIE     = 0x20       // Bit RXNEIE.
	USART_CR1_IDLEIE_Pos = 0x4        // Position of IDLEIE field.
	USART_CR1_IDLEIE_Msk = 0x10       // Bit mask of IDLEIE field.
	USART_CR1_IDLEIE     = 0x10       // Bit IDLEIE.
	USART_CR1_TE_Pos     = 0x3        // Position of TE field.
	USART_CR1_TE_Msk     = 0x8        // Bit mask of TE field.
	USART_CR1_TE         = 0x8        // Bit TE.
	USART_CR1_RE_Pos     = 0x2        // Position of RE field.
	USART_CR1_RE_Msk     = 0x4        // Bit mask of RE field.
	USART_CR1_RE         = 0x4        // Bit RE.
	USART_CR1_UESM_Pos   = 0x1        // Position of UESM field.
	USART_CR1_UESM_Msk   = 0x2        // Bit mask of UESM field.
	USART_CR1_UESM       = 0x2        // Bit UESM.
	USART_CR1_UE_Pos     = 0x0        // Position of UE field.
	USART_CR1_UE_Msk     = 0x1        // Bit mask of UE field.
	USART_CR1_UE         = 0x1        // Bit UE.

	// CR2: Control register 2
	USART_CR2_ADD4_7_Pos   = 0x1c       // Position of ADD4_7 field.
	USART_CR2_ADD4_7_Msk   = 0xf0000000 // Bit mask of ADD4_7 field.
	USART_CR2_ADD0_3_Pos   = 0x18       // Position of ADD0_3 field.
	USART_CR2_ADD0_3_Msk   = 0xf000000  // Bit mask of ADD0_3 field.
	USART_CR2_RTOEN_Pos    = 0x17       // Position of RTOEN field.
	USART_CR2_RTOEN_Msk    = 0x800000   // Bit mask of RTOEN field.
	USART_CR2_RTOEN        = 0x800000   // Bit RTOEN.
	USART_CR2_ABRMOD1_Pos  = 0x16       // Position of ABRMOD1 field.
	USART_CR2_ABRMOD1_Msk  = 0x400000   // Bit mask of ABRMOD1 field.
	USART_CR2_ABRMOD1      = 0x400000   // Bit ABRMOD1.
	USART_CR2_ABRMOD0_Pos  = 0x15       // Position of ABRMOD0 field.
	USART_CR2_ABRMOD0_Msk  = 0x200000   // Bit mask of ABRMOD0 field.
	USART_CR2_ABRMOD0      = 0x200000   // Bit ABRMOD0.
	USART_CR2_ABREN_Pos    = 0x14       // Position of ABREN field.
	USART_CR2_ABREN_Msk    = 0x100000   // Bit mask of ABREN field.
	USART_CR2_ABREN        = 0x100000   // Bit ABREN.
	USART_CR2_MSBFIRST_Pos = 0x13       // Position of MSBFIRST field.
	USART_CR2_MSBFIRST_Msk = 0x80000    // Bit mask of MSBFIRST field.
	USART_CR2_MSBFIRST     = 0x80000    // Bit MSBFIRST.
	USART_CR2_TAINV_Pos    = 0x12       // Position of TAINV field.
	USART_CR2_TAINV_Msk    = 0x40000    // Bit mask of TAINV field.
	USART_CR2_TAINV        = 0x40000    // Bit TAINV.
	USART_CR2_TXINV_Pos    = 0x11       // Position of TXINV field.
	USART_CR2_TXINV_Msk    = 0x20000    // Bit mask of TXINV field.
	USART_CR2_TXINV        = 0x20000    // Bit TXINV.
	USART_CR2_RXINV_Pos    = 0x10       // Position of RXINV field.
	USART_CR2_RXINV_Msk    = 0x10000    // Bit mask of RXINV field.
	USART_CR2_RXINV        = 0x10000    // Bit RXINV.
	USART_CR2_SWAP_Pos     = 0xf        // Position of SWAP field.
	USART_CR2_SWAP_Msk     = 0x8000     // Bit mask of SWAP field.
	USART_CR2_SWAP         = 0x8000     // Bit SWAP.
	USART_CR2_LINEN_Pos    = 0xe        // Position of LINEN field.
	USART_CR2_LINEN_Msk    = 0x4000     // Bit mask of LINEN field.
	USART_CR2_LINEN        = 0x4000     // Bit LINEN.
	USART_CR2_STOP_Pos     = 0xc        // Position of STOP field.
	USART_CR2_STOP_Msk     = 0x3000     // Bit mask of STOP field.
	USART_CR2_CLKEN_Pos    = 0xb        // Position of CLKEN field.
	USART_CR2_CLKEN_Msk    = 0x800      // Bit mask of CLKEN field.
	USART_CR2_CLKEN        = 0x800      // Bit CLKEN.
	USART_CR2_CPOL_Pos     = 0xa        // Position of CPOL field.
	USART_CR2_CPOL_Msk     = 0x400      // Bit mask of CPOL field.
	USART_CR2_CPOL         = 0x400      // Bit CPOL.
	USART_CR2_CPHA_Pos     = 0x9        // Position of CPHA field.
	USART_CR2_CPHA_Msk     = 0x200      // Bit mask of CPHA field.
	USART_CR2_CPHA         = 0x200      // Bit CPHA.
	USART_CR2_LBCL_Pos     = 0x8        // Position of LBCL field.
	USART_CR2_LBCL_Msk     = 0x100      // Bit mask of LBCL field.
	USART_CR2_LBCL         = 0x100      // Bit LBCL.
	USART_CR2_LBDIE_Pos    = 0x6        // Position of LBDIE field.
	USART_CR2_LBDIE_Msk    = 0x40       // Bit mask of LBDIE field.
	USART_CR2_LBDIE        = 0x40       // Bit LBDIE.
	USART_CR2_LBDL_Pos     = 0x5        // Position of LBDL field.
	USART_CR2_LBDL_Msk     = 0x20       // Bit mask of LBDL field.
	USART_CR2_LBDL         = 0x20       // Bit LBDL.
	USART_CR2_ADDM7_Pos    = 0x4        // Position of ADDM7 field.
	USART_CR2_ADDM7_Msk    = 0x10       // Bit mask of ADDM7 field.
	USART_CR2_ADDM7        = 0x10       // Bit ADDM7.
	USART_CR2_DIS_NSS_Pos  = 0x3        // Position of DIS_NSS field.
	USART_CR2_DIS_NSS_Msk  = 0x8        // Bit mask of DIS_NSS field.
	USART_CR2_DIS_NSS      = 0x8        // Bit DIS_NSS.
	USART_CR2_SLVEN_Pos    = 0x0        // Position of SLVEN field.
	USART_CR2_SLVEN_Msk    = 0x1        // Bit mask of SLVEN field.
	USART_CR2_SLVEN        = 0x1        // Bit SLVEN.

	// CR3: Control register 3
	USART_CR3_TXFTCFG_Pos = 0x1d       // Position of TXFTCFG field.
	USART_CR3_TXFTCFG_Msk = 0xe0000000 // Bit mask of TXFTCFG field.
	USART_CR3_RXFTIE_Pos  = 0x1c       // Position of RXFTIE field.
	USART_CR3_RXFTIE_Msk  = 0x10000000 // Bit mask of RXFTIE field.
	USART_CR3_RXFTIE      = 0x10000000 // Bit RXFTIE.
	USART_CR3_RXFTCFG_Pos = 0x19       // Position of RXFTCFG field.
	USART_CR3_RXFTCFG_Msk = 0xe000000  // Bit mask of RXFTCFG field.
	USART_CR3_TCBGTIE_Pos = 0x18       // Position of TCBGTIE field.
	USART_CR3_TCBGTIE_Msk = 0x1000000  // Bit mask of TCBGTIE field.
	USART_CR3_TCBGTIE     = 0x1000000  // Bit TCBGTIE.
	USART_CR3_TXFTIE_Pos  = 0x17       // Position of TXFTIE field.
	USART_CR3_TXFTIE_Msk  = 0x800000   // Bit mask of TXFTIE field.
	USART_CR3_TXFTIE      = 0x800000   // Bit TXFTIE.
	USART_CR3_WUFIE_Pos   = 0x16       // Position of WUFIE field.
	USART_CR3_WUFIE_Msk   = 0x400000   // Bit mask of WUFIE field.
	USART_CR3_WUFIE       = 0x400000   // Bit WUFIE.
	USART_CR3_WUS_Pos     = 0x14       // Position of WUS field.
	USART_CR3_WUS_Msk     = 0x300000   // Bit mask of WUS field.
	USART_CR3_SCARCNT_Pos = 0x11       // Position of SCARCNT field.
	USART_CR3_SCARCNT_Msk = 0xe0000    // Bit mask of SCARCNT field.
	USART_CR3_DEP_Pos     = 0xf        // Position of DEP field.
	USART_CR3_DEP_Msk     = 0x8000     // Bit mask of DEP field.
	USART_CR3_DEP         = 0x8000     // Bit DEP.
	USART_CR3_DEM_Pos     = 0xe        // Position of DEM field.
	USART_CR3_DEM_Msk     = 0x4000     // Bit mask of DEM field.
	USART_CR3_DEM         = 0x4000     // Bit DEM.
	USART_CR3_DDRE_Pos    = 0xd        // Position of DDRE field.
	USART_CR3_DDRE_Msk    = 0x2000     // Bit mask of DDRE field.
	USART_CR3_DDRE        = 0x2000     // Bit DDRE.
	USART_CR3_OVRDIS_Pos  = 0xc        // Position of OVRDIS field.
	USART_CR3_OVRDIS_Msk  = 0x1000     // Bit mask of OVRDIS field.
	USART_CR3_OVRDIS      = 0x1000     // Bit OVRDIS.
	USART_CR3_ONEBIT_Pos  = 0xb        // Position of ONEBIT field.
	USART_CR3_ONEBIT_Msk  = 0x800      // Bit mask of ONEBIT field.
	USART_CR3_ONEBIT      = 0x800      // Bit ONEBIT.
	USART_CR3_CTSIE_Pos   = 0xa        // Position of CTSIE field.
	USART_CR3_CTSIE_Msk   = 0x400      // Bit mask of CTSIE field.
	USART_CR3_CTSIE       = 0x400      // Bit CTSIE.
	USART_CR3_CTSE_Pos    = 0x9        // Position of CTSE field.
	USART_CR3_CTSE_Msk    = 0x200      // Bit mask of CTSE field.
	USART_CR3_CTSE        = 0x200      // Bit CTSE.
	USART_CR3_RTSE_Pos    = 0x8        // Position of RTSE field.
	USART_CR3_RTSE_Msk    = 0x100      // Bit mask of RTSE field.
	USART_CR3_RTSE        = 0x100      // Bit RTSE.
	USART_CR3_DMAT_Pos    = 0x7        // Position of DMAT field.
	USART_CR3_DMAT_Msk    = 0x80       // Bit mask of DMAT field.
	USART_CR3_DMAT        = 0x80       // Bit DMAT.
	USART_CR3_DMAR_Pos    = 0x6        // Position of DMAR field.
	USART_CR3_DMAR_Msk    = 0x40       // Bit mask of DMAR field.
	USART_CR3_DMAR        = 0x40       // Bit DMAR.
	USART_CR3_SCEN_Pos    = 0x5        // Position of SCEN field.
	USART_CR3_SCEN_Msk    = 0x20       // Bit mask of SCEN field.
	USART_CR3_SCEN        = 0x20       // Bit SCEN.
	USART_CR3_NACK_Pos    = 0x4        // Position of NACK field.
	USART_CR3_NACK_Msk    = 0x10       // Bit mask of NACK field.
	USART_CR3_NACK        = 0x10       // Bit NACK.
	USART_CR3_HDSEL_Pos   = 0x3        // Position of HDSEL field.
	USART_CR3_HDSEL_Msk   = 0x8        // Bit mask of HDSEL field.
	USART_CR3_HDSEL       = 0x8        // Bit HDSEL.
	USART_CR3_IRLP_Pos    = 0x2        // Position of IRLP field.
	USART_CR3_IRLP_Msk    = 0x4        // Bit mask of IRLP field.
	USART_CR3_IRLP        = 0x4        // Bit IRLP.
	USART_CR3_IREN_Pos    = 0x1        // Position of IREN field.
	USART_CR3_IREN_Msk    = 0x2        // Bit mask of IREN field.
	USART_CR3_IREN        = 0x2        // Bit IREN.
	USART_CR3_EIE_Pos     = 0x0        // Position of EIE field.
	USART_CR3_EIE_Msk     = 0x1        // Bit mask of EIE field.
	USART_CR3_EIE         = 0x1        // Bit EIE.

	// BRR: Baud rate register
	USART_BRR_DIV_Mantissa_Pos = 0x4    // Position of DIV_Mantissa field.
	USART_BRR_DIV_Mantissa_Msk = 0xfff0 // Bit mask of DIV_Mantissa field.
	USART_BRR_DIV_Fraction_Pos = 0x0    // Position of DIV_Fraction field.
	USART_BRR_DIV_Fraction_Msk = 0xf    // Bit mask of DIV_Fraction field.

	// GTPR: Guard time and prescaler           register
	USART_GTPR_GT_Pos  = 0x8    // Position of GT field.
	USART_GTPR_GT_Msk  = 0xff00 // Bit mask of GT field.
	USART_GTPR_PSC_Pos = 0x0    // Position of PSC field.
	USART_GTPR_PSC_Msk = 0xff   // Bit mask of PSC field.

	// RTOR: Receiver timeout register
	USART_RTOR_BLEN_Pos = 0x18       // Position of BLEN field.
	USART_RTOR_BLEN_Msk = 0xff000000 // Bit mask of BLEN field.
	USART_RTOR_RTO_Pos  = 0x0        // Position of RTO field.
	USART_RTOR_RTO_Msk  = 0xffffff   // Bit mask of RTO field.

	// RQR: Request register
	USART_RQR_TXFRQ_Pos = 0x4  // Position of TXFRQ field.
	USART_RQR_TXFRQ_Msk = 0x10 // Bit mask of TXFRQ field.
	USART_RQR_TXFRQ     = 0x10 // Bit TXFRQ.
	USART_RQR_RXFRQ_Pos = 0x3  // Position of RXFRQ field.
	USART_RQR_RXFRQ_Msk = 0x8  // Bit mask of RXFRQ field.
	USART_RQR_RXFRQ     = 0x8  // Bit RXFRQ.
	USART_RQR_MMRQ_Pos  = 0x2  // Position of MMRQ field.
	USART_RQR_MMRQ_Msk  = 0x4  // Bit mask of MMRQ field.
	USART_RQR_MMRQ      = 0x4  // Bit MMRQ.
	USART_RQR_SBKRQ_Pos = 0x1  // Position of SBKRQ field.
	USART_RQR_SBKRQ_Msk = 0x2  // Bit mask of SBKRQ field.
	USART_RQR_SBKRQ     = 0x2  // Bit SBKRQ.
	USART_RQR_ABRRQ_Pos = 0x0  // Position of ABRRQ field.
	USART_RQR_ABRRQ_Msk = 0x1  // Bit mask of ABRRQ field.
	USART_RQR_ABRRQ     = 0x1  // Bit ABRRQ.

	// ISR: Interrupt & status           register
	USART_ISR_TXFT_Pos  = 0x1b      // Position of TXFT field.
	USART_ISR_TXFT_Msk  = 0x8000000 // Bit mask of TXFT field.
	USART_ISR_TXFT      = 0x8000000 // Bit TXFT.
	USART_ISR_RXFT_Pos  = 0x1a      // Position of RXFT field.
	USART_ISR_RXFT_Msk  = 0x4000000 // Bit mask of RXFT field.
	USART_ISR_RXFT      = 0x4000000 // Bit RXFT.
	USART_ISR_TCBGT_Pos = 0x19      // Position of TCBGT field.
	USART_ISR_TCBGT_Msk = 0x2000000 // Bit mask of TCBGT field.
	USART_ISR_TCBGT     = 0x2000000 // Bit TCBGT.
	USART_ISR_RXFF_Pos  = 0x18      // Position of RXFF field.
	USART_ISR_RXFF_Msk  = 0x1000000 // Bit mask of RXFF field.
	USART_ISR_RXFF      = 0x1000000 // Bit RXFF.
	USART_ISR_TXFE_Pos  = 0x17      // Position of TXFE field.
	USART_ISR_TXFE_Msk  = 0x800000  // Bit mask of TXFE field.
	USART_ISR_TXFE      = 0x800000  // Bit TXFE.
	USART_ISR_REACK_Pos = 0x16      // Position of REACK field.
	USART_ISR_REACK_Msk = 0x400000  // Bit mask of REACK field.
	USART_ISR_REACK     = 0x400000  // Bit REACK.
	USART_ISR_TEACK_Pos = 0x15      // Position of TEACK field.
	USART_ISR_TEACK_Msk = 0x200000  // Bit mask of TEACK field.
	USART_ISR_TEACK     = 0x200000  // Bit TEACK.
	USART_ISR_WUF_Pos   = 0x14      // Position of WUF field.
	USART_ISR_WUF_Msk   = 0x100000  // Bit mask of WUF field.
	USART_ISR_WUF       = 0x100000  // Bit WUF.
	USART_ISR_RWU_Pos   = 0x13      // Position of RWU field.
	USART_ISR_RWU_Msk   = 0x80000   // Bit mask of RWU field.
	USART_ISR_RWU       = 0x80000   // Bit RWU.
	USART_ISR_SBKF_Pos  = 0x12      // Position of SBKF field.
	USART_ISR_SBKF_Msk  = 0x40000   // Bit mask of SBKF field.
	USART_ISR_SBKF      = 0x40000   // Bit SBKF.
	USART_ISR_CMF_Pos   = 0x11      // Position of CMF field.
	USART_ISR_CMF_Msk   = 0x20000   // Bit mask of CMF field.
	USART_ISR_CMF       = 0x20000   // Bit CMF.
	USART_ISR_BUSY_Pos  = 0x10      // Position of BUSY field.
	USART_ISR_BUSY_Msk  = 0x10000   // Bit mask of BUSY field.
	USART_ISR_BUSY      = 0x10000   // Bit BUSY.
	USART_ISR_ABRF_Pos  = 0xf       // Position of ABRF field.
	USART_ISR_ABRF_Msk  = 0x8000    // Bit mask of ABRF field.
	USART_ISR_ABRF      = 0x8000    // Bit ABRF.
	USART_ISR_ABRE_Pos  = 0xe       // Position of ABRE field.
	USART_ISR_ABRE_Msk  = 0x4000    // Bit mask of ABRE field.
	USART_ISR_ABRE      = 0x4000    // Bit ABRE.
	USART_ISR_UDR_Pos   = 0xd       // Position of UDR field.
	USART_ISR_UDR_Msk   = 0x2000    // Bit mask of UDR field.
	USART_ISR_UDR       = 0x2000    // Bit UDR.
	USART_ISR_EOBF_Pos  = 0xc       // Position of EOBF field.
	USART_ISR_EOBF_Msk  = 0x1000    // Bit mask of EOBF field.
	USART_ISR_EOBF      = 0x1000    // Bit EOBF.
	USART_ISR_RTOF_Pos  = 0xb       // Position of RTOF field.
	USART_ISR_RTOF_Msk  = 0x800     // Bit mask of RTOF field.
	USART_ISR_RTOF      = 0x800     // Bit RTOF.
	USART_ISR_CTS_Pos   = 0xa       // Position of CTS field.
	USART_ISR_CTS_Msk   = 0x400     // Bit mask of CTS field.
	USART_ISR_CTS       = 0x400     // Bit CTS.
	USART_ISR_CTSIF_Pos = 0x9       // Position of CTSIF field.
	USART_ISR_CTSIF_Msk = 0x200     // Bit mask of CTSIF field.
	USART_ISR_CTSIF     = 0x200     // Bit CTSIF.
	USART_ISR_LBDF_Pos  = 0x8       // Position of LBDF field.
	USART_ISR_LBDF_Msk  = 0x100     // Bit mask of LBDF field.
	USART_ISR_LBDF      = 0x100     // Bit LBDF.
	USART_ISR_TXE_Pos   = 0x7       // Position of TXE field.
	USART_ISR_TXE_Msk   = 0x80      // Bit mask of TXE field.
	USART_ISR_TXE       = 0x80      // Bit TXE.
	USART_ISR_TC_Pos    = 0x6       // Position of TC field.
	USART_ISR_TC_Msk    = 0x40      // Bit mask of TC field.
	USART_ISR_TC        = 0x40      // Bit TC.
	USART_ISR_RXNE_Pos  = 0x5       // Position of RXNE field.
	USART_ISR_RXNE_Msk  = 0x20      // Bit mask of RXNE field.
	USART_ISR_RXNE      = 0x20      // Bit RXNE.
	USART_ISR_IDLE_Pos  = 0x4       // Position of IDLE field.
	USART_ISR_IDLE_Msk  = 0x10      // Bit mask of IDLE field.
	USART_ISR_IDLE      = 0x10      // Bit IDLE.
	USART_ISR_ORE_Pos   = 0x3       // Position of ORE field.
	USART_ISR_ORE_Msk   = 0x8       // Bit mask of ORE field.
	USART_ISR_ORE       = 0x8       // Bit ORE.
	USART_ISR_NF_Pos    = 0x2       // Position of NF field.
	USART_ISR_NF_Msk    = 0x4       // Bit mask of NF field.
	USART_ISR_NF        = 0x4       // Bit NF.
	USART_ISR_FE_Pos    = 0x1       // Position of FE field.
	USART_ISR_FE_Msk    = 0x2       // Bit mask of FE field.
	USART_ISR_FE        = 0x2       // Bit FE.
	USART_ISR_PE_Pos    = 0x0       // Position of PE field.
	USART_ISR_PE_Msk    = 0x1       // Bit mask of PE field.
	USART_ISR_PE        = 0x1       // Bit PE.

	// ICR: Interrupt flag clear register
	USART_ICR_WUCF_Pos    = 0x14     // Position of WUCF field.
	USART_ICR_WUCF_Msk    = 0x100000 // Bit mask of WUCF field.
	USART_ICR_WUCF        = 0x100000 // Bit WUCF.
	USART_ICR_CMCF_Pos    = 0x11     // Position of CMCF field.
	USART_ICR_CMCF_Msk    = 0x20000  // Bit mask of CMCF field.
	USART_ICR_CMCF        = 0x20000  // Bit CMCF.
	USART_ICR_UDRCF_Pos   = 0xd      // Position of UDRCF field.
	USART_ICR_UDRCF_Msk   = 0x2000   // Bit mask of UDRCF field.
	USART_ICR_UDRCF       = 0x2000   // Bit UDRCF.
	USART_ICR_EOBCF_Pos   = 0xc      // Position of EOBCF field.
	USART_ICR_EOBCF_Msk   = 0x1000   // Bit mask of EOBCF field.
	USART_ICR_EOBCF       = 0x1000   // Bit EOBCF.
	USART_ICR_RTOCF_Pos   = 0xb      // Position of RTOCF field.
	USART_ICR_RTOCF_Msk   = 0x800    // Bit mask of RTOCF field.
	USART_ICR_RTOCF       = 0x800    // Bit RTOCF.
	USART_ICR_CTSCF_Pos   = 0x9      // Position of CTSCF field.
	USART_ICR_CTSCF_Msk   = 0x200    // Bit mask of CTSCF field.
	USART_ICR_CTSCF       = 0x200    // Bit CTSCF.
	USART_ICR_LBDCF_Pos   = 0x8      // Position of LBDCF field.
	USART_ICR_LBDCF_Msk   = 0x100    // Bit mask of LBDCF field.
	USART_ICR_LBDCF       = 0x100    // Bit LBDCF.
	USART_ICR_TCBGTCF_Pos = 0x7      // Position of TCBGTCF field.
	USART_ICR_TCBGTCF_Msk = 0x80     // Bit mask of TCBGTCF field.
	USART_ICR_TCBGTCF     = 0x80     // Bit TCBGTCF.
	USART_ICR_TCCF_Pos    = 0x6      // Position of TCCF field.
	USART_ICR_TCCF_Msk    = 0x40     // Bit mask of TCCF field.
	USART_ICR_TCCF        = 0x40     // Bit TCCF.
	USART_ICR_TXFECF_Pos  = 0x5      // Position of TXFECF field.
	USART_ICR_TXFECF_Msk  = 0x20     // Bit mask of TXFECF field.
	USART_ICR_TXFECF      = 0x20     // Bit TXFECF.
	USART_ICR_IDLECF_Pos  = 0x4      // Position of IDLECF field.
	USART_ICR_IDLECF_Msk  = 0x10     // Bit mask of IDLECF field.
	USART_ICR_IDLECF      = 0x10     // Bit IDLECF.
	USART_ICR_ORECF_Pos   = 0x3      // Position of ORECF field.
	USART_ICR_ORECF_Msk   = 0x8      // Bit mask of ORECF field.
	USART_ICR_ORECF       = 0x8      // Bit ORECF.
	USART_ICR_NCF_Pos     = 0x2      // Position of NCF field.
	USART_ICR_NCF_Msk     = 0x4      // Bit mask of NCF field.
	USART_ICR_NCF         = 0x4      // Bit NCF.
	USART_ICR_FECF_Pos    = 0x1      // Position of FECF field.
	USART_ICR_FECF_Msk    = 0x2      // Bit mask of FECF field.
	USART_ICR_FECF        = 0x2      // Bit FECF.
	USART_ICR_PECF_Pos    = 0x0      // Position of PECF field.
	USART_ICR_PECF_Msk    = 0x1      // Bit mask of PECF field.
	USART_ICR_PECF        = 0x1      // Bit PECF.

	// RDR: Receive data register
	USART_RDR_RDR_Pos = 0x0   // Position of RDR field.
	USART_RDR_RDR_Msk = 0x1ff // Bit mask of RDR field.

	// TDR: Transmit data register
	USART_TDR_TDR_Pos = 0x0   // Position of TDR field.
	USART_TDR_TDR_Msk = 0x1ff // Bit mask of TDR field.

	// PRESC: USART prescaler register
	USART_PRESC_PRESCALER_Pos = 0x0 // Position of PRESCALER field.
	USART_PRESC_PRESCALER_Msk = 0xf // Bit mask of PRESCALER field.
)

// Bitfields for SPI1: Serial peripheral interface/Inter-IC sound
const (
	// CR1: control register 1
	SPI_CR1_BIDIMODE_Pos = 0xf    // Position of BIDIMODE field.
	SPI_CR1_BIDIMODE_Msk = 0x8000 // Bit mask of BIDIMODE field.
	SPI_CR1_BIDIMODE     = 0x8000 // Bit BIDIMODE.
	SPI_CR1_BIDIOE_Pos   = 0xe    // Position of BIDIOE field.
	SPI_CR1_BIDIOE_Msk   = 0x4000 // Bit mask of BIDIOE field.
	SPI_CR1_BIDIOE       = 0x4000 // Bit BIDIOE.
	SPI_CR1_CRCEN_Pos    = 0xd    // Position of CRCEN field.
	SPI_CR1_CRCEN_Msk    = 0x2000 // Bit mask of CRCEN field.
	SPI_CR1_CRCEN        = 0x2000 // Bit CRCEN.
	SPI_CR1_CRCNEXT_Pos  = 0xc    // Position of CRCNEXT field.
	SPI_CR1_CRCNEXT_Msk  = 0x1000 // Bit mask of CRCNEXT field.
	SPI_CR1_CRCNEXT      = 0x1000 // Bit CRCNEXT.
	SPI_CR1_DFF_Pos      = 0xb    // Position of DFF field.
	SPI_CR1_DFF_Msk      = 0x800  // Bit mask of DFF field.
	SPI_CR1_DFF          = 0x800  // Bit DFF.
	SPI_CR1_RXONLY_Pos   = 0xa    // Position of RXONLY field.
	SPI_CR1_RXONLY_Msk   = 0x400  // Bit mask of RXONLY field.
	SPI_CR1_RXONLY       = 0x400  // Bit RXONLY.
	SPI_CR1_SSM_Pos      = 0x9    // Position of SSM field.
	SPI_CR1_SSM_Msk      = 0x200  // Bit mask of SSM field.
	SPI_CR1_SSM          = 0x200  // Bit SSM.
	SPI_CR1_SSI_Pos      = 0x8    // Position of SSI field.
	SPI_CR1_SSI_Msk      = 0x100  // Bit mask of SSI field.
	SPI_CR1_SSI          = 0x100  // Bit SSI.
	SPI_CR1_LSBFIRST_Pos = 0x7    // Position of LSBFIRST field.
	SPI_CR1_LSBFIRST_Msk = 0x80   // Bit mask of LSBFIRST field.
	SPI_CR1_LSBFIRST     = 0x80   // Bit LSBFIRST.
	SPI_CR1_SPE_Pos      = 0x6    // Position of SPE field.
	SPI_CR1_SPE_Msk      = 0x40   // Bit mask of SPE field.
	SPI_CR1_SPE          = 0x40   // Bit SPE.
	SPI_CR1_BR_Pos       = 0x3    // Position of BR field.
	SPI_CR1_BR_Msk       = 0x38   // Bit mask of BR field.
	SPI_CR1_MSTR_Pos     = 0x2    // Position of MSTR field.
	SPI_CR1_MSTR_Msk     = 0x4    // Bit mask of MSTR field.
	SPI_CR1_MSTR         = 0x4    // Bit MSTR.
	SPI_CR1_CPOL_Pos     = 0x1    // Position of CPOL field.
	SPI_CR1_CPOL_Msk     = 0x2    // Bit mask of CPOL field.
	SPI_CR1_CPOL         = 0x2    // Bit CPOL.
	SPI_CR1_CPHA_Pos     = 0x0    // Position of CPHA field.
	SPI_CR1_CPHA_Msk     = 0x1    // Bit mask of CPHA field.
	SPI_CR1_CPHA         = 0x1    // Bit CPHA.

	// CR2: control register 2
	SPI_CR2_RXDMAEN_Pos = 0x0    // Position of RXDMAEN field.
	SPI_CR2_RXDMAEN_Msk = 0x1    // Bit mask of RXDMAEN field.
	SPI_CR2_RXDMAEN     = 0x1    // Bit RXDMAEN.
	SPI_CR2_TXDMAEN_Pos = 0x1    // Position of TXDMAEN field.
	SPI_CR2_TXDMAEN_Msk = 0x2    // Bit mask of TXDMAEN field.
	SPI_CR2_TXDMAEN     = 0x2    // Bit TXDMAEN.
	SPI_CR2_SSOE_Pos    = 0x2    // Position of SSOE field.
	SPI_CR2_SSOE_Msk    = 0x4    // Bit mask of SSOE field.
	SPI_CR2_SSOE        = 0x4    // Bit SSOE.
	SPI_CR2_NSSP_Pos    = 0x3    // Position of NSSP field.
	SPI_CR2_NSSP_Msk    = 0x8    // Bit mask of NSSP field.
	SPI_CR2_NSSP        = 0x8    // Bit NSSP.
	SPI_CR2_FRF_Pos     = 0x4    // Position of FRF field.
	SPI_CR2_FRF_Msk     = 0x10   // Bit mask of FRF field.
	SPI_CR2_FRF         = 0x10   // Bit FRF.
	SPI_CR2_ERRIE_Pos   = 0x5    // Position of ERRIE field.
	SPI_CR2_ERRIE_Msk   = 0x20   // Bit mask of ERRIE field.
	SPI_CR2_ERRIE       = 0x20   // Bit ERRIE.
	SPI_CR2_RXNEIE_Pos  = 0x6    // Position of RXNEIE field.
	SPI_CR2_RXNEIE_Msk  = 0x40   // Bit mask of RXNEIE field.
	SPI_CR2_RXNEIE      = 0x40   // Bit RXNEIE.
	SPI_CR2_TXEIE_Pos   = 0x7    // Position of TXEIE field.
	SPI_CR2_TXEIE_Msk   = 0x80   // Bit mask of TXEIE field.
	SPI_CR2_TXEIE       = 0x80   // Bit TXEIE.
	SPI_CR2_DS_Pos      = 0x8    // Position of DS field.
	SPI_CR2_DS_Msk      = 0xf00  // Bit mask of DS field.
	SPI_CR2_FRXTH_Pos   = 0xc    // Position of FRXTH field.
	SPI_CR2_FRXTH_Msk   = 0x1000 // Bit mask of FRXTH field.
	SPI_CR2_FRXTH       = 0x1000 // Bit FRXTH.
	SPI_CR2_LDMA_RX_Pos = 0xd    // Position of LDMA_RX field.
	SPI_CR2_LDMA_RX_Msk = 0x2000 // Bit mask of LDMA_RX field.
	SPI_CR2_LDMA_RX     = 0x2000 // Bit LDMA_RX.
	SPI_CR2_LDMA_TX_Pos = 0xe    // Position of LDMA_TX field.
	SPI_CR2_LDMA_TX_Msk = 0x4000 // Bit mask of LDMA_TX field.
	SPI_CR2_LDMA_TX     = 0x4000 // Bit LDMA_TX.

	// SR: status register
	SPI_SR_RXNE_Pos   = 0x0    // Position of RXNE field.
	SPI_SR_RXNE_Msk   = 0x1    // Bit mask of RXNE field.
	SPI_SR_RXNE       = 0x1    // Bit RXNE.
	SPI_SR_TXE_Pos    = 0x1    // Position of TXE field.
	SPI_SR_TXE_Msk    = 0x2    // Bit mask of TXE field.
	SPI_SR_TXE        = 0x2    // Bit TXE.
	SPI_SR_CRCERR_Pos = 0x4    // Position of CRCERR field.
	SPI_SR_CRCERR_Msk = 0x10   // Bit mask of CRCERR field.
	SPI_SR_CRCERR     = 0x10   // Bit CRCERR.
	SPI_SR_MODF_Pos   = 0x5    // Position of MODF field.
	SPI_SR_MODF_Msk   = 0x20   // Bit mask of MODF field.
	SPI_SR_MODF       = 0x20   // Bit MODF.
	SPI_SR_OVR_Pos    = 0x6    // Position of OVR field.
	SPI_SR_OVR_Msk    = 0x40   // Bit mask of OVR field.
	SPI_SR_OVR        = 0x40   // Bit OVR.
	SPI_SR_BSY_Pos    = 0x7    // Position of BSY field.
	SPI_SR_BSY_Msk    = 0x80   // Bit mask of BSY field.
	SPI_SR_BSY        = 0x80   // Bit BSY.
	SPI_SR_TIFRFE_Pos = 0x8    // Position of TIFRFE field.
	SPI_SR_TIFRFE_Msk = 0x100  // Bit mask of TIFRFE field.
	SPI_SR_TIFRFE     = 0x100  // Bit TIFRFE.
	SPI_SR_FRLVL_Pos  = 0x9    // Position of FRLVL field.
	SPI_SR_FRLVL_Msk  = 0x600  // Bit mask of FRLVL field.
	SPI_SR_FTLVL_Pos  = 0xb    // Position of FTLVL field.
	SPI_SR_FTLVL_Msk  = 0x1800 // Bit mask of FTLVL field.

	// DR: data register
	SPI_DR_DR_Pos = 0x0    // Position of DR field.
	SPI_DR_DR_Msk = 0xffff // Bit mask of DR field.

	// CRCPR: CRC polynomial register
	SPI_CRCPR_CRCPOLY_Pos = 0x0    // Position of CRCPOLY field.
	SPI_CRCPR_CRCPOLY_Msk = 0xffff // Bit mask of CRCPOLY field.

	// RXCRCR: RX CRC register
	SPI_RXCRCR_RxCRC_Pos = 0x0    // Position of RxCRC field.
	SPI_RXCRCR_RxCRC_Msk = 0xffff // Bit mask of RxCRC field.

	// TXCRCR: TX CRC register
	SPI_TXCRCR_TxCRC_Pos = 0x0    // Position of TxCRC field.
	SPI_TXCRCR_TxCRC_Msk = 0xffff // Bit mask of TxCRC field.

	// I2SCFGR: configuration register
	SPI_I2SCFGR_CHLEN_Pos   = 0x0   // Position of CHLEN field.
	SPI_I2SCFGR_CHLEN_Msk   = 0x1   // Bit mask of CHLEN field.
	SPI_I2SCFGR_CHLEN       = 0x1   // Bit CHLEN.
	SPI_I2SCFGR_DATLEN_Pos  = 0x1   // Position of DATLEN field.
	SPI_I2SCFGR_DATLEN_Msk  = 0x6   // Bit mask of DATLEN field.
	SPI_I2SCFGR_CKPOL_Pos   = 0x3   // Position of CKPOL field.
	SPI_I2SCFGR_CKPOL_Msk   = 0x8   // Bit mask of CKPOL field.
	SPI_I2SCFGR_CKPOL       = 0x8   // Bit CKPOL.
	SPI_I2SCFGR_I2SSTD_Pos  = 0x4   // Position of I2SSTD field.
	SPI_I2SCFGR_I2SSTD_Msk  = 0x30  // Bit mask of I2SSTD field.
	SPI_I2SCFGR_PCMSYNC_Pos = 0x7   // Position of PCMSYNC field.
	SPI_I2SCFGR_PCMSYNC_Msk = 0x80  // Bit mask of PCMSYNC field.
	SPI_I2SCFGR_PCMSYNC     = 0x80  // Bit PCMSYNC.
	SPI_I2SCFGR_I2SCFG_Pos  = 0x8   // Position of I2SCFG field.
	SPI_I2SCFGR_I2SCFG_Msk  = 0x300 // Bit mask of I2SCFG field.
	SPI_I2SCFGR_I2SE_Pos    = 0xa   // Position of I2SE field.
	SPI_I2SCFGR_I2SE_Msk    = 0x400 // Bit mask of I2SE field.
	SPI_I2SCFGR_I2SE        = 0x400 // Bit I2SE.
	SPI_I2SCFGR_I2SMOD_Pos  = 0xb   // Position of I2SMOD field.
	SPI_I2SCFGR_I2SMOD_Msk  = 0x800 // Bit mask of I2SMOD field.
	SPI_I2SCFGR_I2SMOD      = 0x800 // Bit I2SMOD.

	// I2SPR: prescaler register
	SPI_I2SPR_I2SDIV_Pos = 0x0   // Position of I2SDIV field.
	SPI_I2SPR_I2SDIV_Msk = 0xff  // Bit mask of I2SDIV field.
	SPI_I2SPR_ODD_Pos    = 0x8   // Position of ODD field.
	SPI_I2SPR_ODD_Msk    = 0x100 // Bit mask of ODD field.
	SPI_I2SPR_ODD        = 0x100 // Bit ODD.
	SPI_I2SPR_MCKOE_Pos  = 0x9   // Position of MCKOE field.
	SPI_I2SPR_MCKOE_Msk  = 0x200 // Bit mask of MCKOE field.
	SPI_I2SPR_MCKOE      = 0x200 // Bit MCKOE.
)

// Bitfields for EXTI: External interrupt/event controller
const (
	// IMR1: Interrupt mask register
	EXTI_IMR1_IM0_Pos  = 0x0        // Position of IM0 field.
	EXTI_IMR1_IM0_Msk  = 0x1        // Bit mask of IM0 field.
	EXTI_IMR1_IM0      = 0x1        // Bit IM0.
	EXTI_IMR1_IM1_Pos  = 0x1        // Position of IM1 field.
	EXTI_IMR1_IM1_Msk  = 0x2        // Bit mask of IM1 field.
	EXTI_IMR1_IM1      = 0x2        // Bit IM1.
	EXTI_IMR1_IM2_Pos  = 0x2        // Position of IM2 field.
	EXTI_IMR1_IM2_Msk  = 0x4        // Bit mask of IM2 field.
	EXTI_IMR1_IM2      = 0x4        // Bit IM2.
	EXTI_IMR1_IM3_Pos  = 0x3        // Position of IM3 field.
	EXTI_IMR1_IM3_Msk  = 0x8        // Bit mask of IM3 field.
	EXTI_IMR1_IM3      = 0x8        // Bit IM3.
	EXTI_IMR1_IM4_Pos  = 0x4        // Position of IM4 field.
	EXTI_IMR1_IM4_Msk  = 0x10       // Bit mask of IM4 field.
	EXTI_IMR1_IM4      = 0x10       // Bit IM4.
	EXTI_IMR1_IM5_Pos  = 0x5        // Position of IM5 field.
	EXTI_IMR1_IM5_Msk  = 0x20       // Bit mask of IM5 field.
	EXTI_IMR1_IM5      = 0x20       // Bit IM5.
	EXTI_IMR1_IM6_Pos  = 0x6        // Position of IM6 field.
	EXTI_IMR1_IM6_Msk  = 0x40       // Bit mask of IM6 field.
	EXTI_IMR1_IM6      = 0x40       // Bit IM6.
	EXTI_IMR1_IM7_Pos  = 0x7        // Position of IM7 field.
	EXTI_IMR1_IM7_Msk  = 0x80       // Bit mask of IM7 field.
	EXTI_IMR1_IM7      = 0x80       // Bit IM7.
	EXTI_IMR1_IM8_Pos  = 0x8        // Position of IM8 field.
	EXTI_IMR1_IM8_Msk  = 0x100      // Bit mask of IM8 field.
	EXTI_IMR1_IM8      = 0x100      // Bit IM8.
	EXTI_IMR1_IM9_Pos  = 0x9        // Position of IM9 field.
	EXTI_IMR1_IM9_Msk  = 0x200      // Bit mask of IM9 field.
	EXTI_IMR1_IM9      = 0x200      // Bit IM9.
	EXTI_IMR1_IM10_Pos = 0xa        // Position of IM10 field.
	EXTI_IMR1_IM10_Msk = 0x400      // Bit mask of IM10 field.
	EXTI_IMR1_IM10     = 0x400      // Bit IM10.
	EXTI_IMR1_IM11_Pos = 0xb        // Position of IM11 field.
	EXTI_IMR1_IM11_Msk = 0x800      // Bit mask of IM11 field.
	EXTI_IMR1_IM11     = 0x800      // Bit IM11.
	EXTI_IMR1_IM12_Pos = 0xc        // Position of IM12 field.
	EXTI_IMR1_IM12_Msk = 0x1000     // Bit mask of IM12 field.
	EXTI_IMR1_IM12     = 0x1000     // Bit IM12.
	EXTI_IMR1_IM13_Pos = 0xd        // Position of IM13 field.
	EXTI_IMR1_IM13_Msk = 0x2000     // Bit mask of IM13 field.
	EXTI_IMR1_IM13     = 0x2000     // Bit IM13.
	EXTI_IMR1_IM14_Pos = 0xe        // Position of IM14 field.
	EXTI_IMR1_IM14_Msk = 0x4000     // Bit mask of IM14 field.
	EXTI_IMR1_IM14     = 0x4000     // Bit IM14.
	EXTI_IMR1_IM15_Pos = 0xf        // Position of IM15 field.
	EXTI_IMR1_IM15_Msk = 0x8000     // Bit mask of IM15 field.
	EXTI_IMR1_IM15     = 0x8000     // Bit IM15.
	EXTI_IMR1_IM16_Pos = 0x10       // Position of IM16 field.
	EXTI_IMR1_IM16_Msk = 0x10000    // Bit mask of IM16 field.
	EXTI_IMR1_IM16     = 0x10000    // Bit IM16.
	EXTI_IMR1_IM17_Pos = 0x11       // Position of IM17 field.
	EXTI_IMR1_IM17_Msk = 0x20000    // Bit mask of IM17 field.
	EXTI_IMR1_IM17     = 0x20000    // Bit IM17.
	EXTI_IMR1_IM18_Pos = 0x12       // Position of IM18 field.
	EXTI_IMR1_IM18_Msk = 0x40000    // Bit mask of IM18 field.
	EXTI_IMR1_IM18     = 0x40000    // Bit IM18.
	EXTI_IMR1_IM19_Pos = 0x13       // Position of IM19 field.
	EXTI_IMR1_IM19_Msk = 0x80000    // Bit mask of IM19 field.
	EXTI_IMR1_IM19     = 0x80000    // Bit IM19.
	EXTI_IMR1_IM20_Pos = 0x14       // Position of IM20 field.
	EXTI_IMR1_IM20_Msk = 0x100000   // Bit mask of IM20 field.
	EXTI_IMR1_IM20     = 0x100000   // Bit IM20.
	EXTI_IMR1_IM21_Pos = 0x15       // Position of IM21 field.
	EXTI_IMR1_IM21_Msk = 0x200000   // Bit mask of IM21 field.
	EXTI_IMR1_IM21     = 0x200000   // Bit IM21.
	EXTI_IMR1_IM22_Pos = 0x16       // Position of IM22 field.
	EXTI_IMR1_IM22_Msk = 0x400000   // Bit mask of IM22 field.
	EXTI_IMR1_IM22     = 0x400000   // Bit IM22.
	EXTI_IMR1_IM23_Pos = 0x17       // Position of IM23 field.
	EXTI_IMR1_IM23_Msk = 0x800000   // Bit mask of IM23 field.
	EXTI_IMR1_IM23     = 0x800000   // Bit IM23.
	EXTI_IMR1_IM24_Pos = 0x18       // Position of IM24 field.
	EXTI_IMR1_IM24_Msk = 0x1000000  // Bit mask of IM24 field.
	EXTI_IMR1_IM24     = 0x1000000  // Bit IM24.
	EXTI_IMR1_IM25_Pos = 0x19       // Position of IM25 field.
	EXTI_IMR1_IM25_Msk = 0x2000000  // Bit mask of IM25 field.
	EXTI_IMR1_IM25     = 0x2000000  // Bit IM25.
	EXTI_IMR1_IM26_Pos = 0x1a       // Position of IM26 field.
	EXTI_IMR1_IM26_Msk = 0x4000000  // Bit mask of IM26 field.
	EXTI_IMR1_IM26     = 0x4000000  // Bit IM26.
	EXTI_IMR1_IM27_Pos = 0x1b       // Position of IM27 field.
	EXTI_IMR1_IM27_Msk = 0x8000000  // Bit mask of IM27 field.
	EXTI_IMR1_IM27     = 0x8000000  // Bit IM27.
	EXTI_IMR1_IM28_Pos = 0x1c       // Position of IM28 field.
	EXTI_IMR1_IM28_Msk = 0x10000000 // Bit mask of IM28 field.
	EXTI_IMR1_IM28     = 0x10000000 // Bit IM28.
	EXTI_IMR1_IM29_Pos = 0x1d       // Position of IM29 field.
	EXTI_IMR1_IM29_Msk = 0x20000000 // Bit mask of IM29 field.
	EXTI_IMR1_IM29     = 0x20000000 // Bit IM29.
	EXTI_IMR1_IM30_Pos = 0x1e       // Position of IM30 field.
	EXTI_IMR1_IM30_Msk = 0x40000000 // Bit mask of IM30 field.
	EXTI_IMR1_IM30     = 0x40000000 // Bit IM30.
	EXTI_IMR1_IM31_Pos = 0x1f       // Position of IM31 field.
	EXTI_IMR1_IM31_Msk = 0x80000000 // Bit mask of IM31 field.
	EXTI_IMR1_IM31     = 0x80000000 // Bit IM31.

	// EMR1: Event mask register
	EXTI_EMR1_EM0_Pos  = 0x0        // Position of EM0 field.
	EXTI_EMR1_EM0_Msk  = 0x1        // Bit mask of EM0 field.
	EXTI_EMR1_EM0      = 0x1        // Bit EM0.
	EXTI_EMR1_EM1_Pos  = 0x1        // Position of EM1 field.
	EXTI_EMR1_EM1_Msk  = 0x2        // Bit mask of EM1 field.
	EXTI_EMR1_EM1      = 0x2        // Bit EM1.
	EXTI_EMR1_EM2_Pos  = 0x2        // Position of EM2 field.
	EXTI_EMR1_EM2_Msk  = 0x4        // Bit mask of EM2 field.
	EXTI_EMR1_EM2      = 0x4        // Bit EM2.
	EXTI_EMR1_EM3_Pos  = 0x3        // Position of EM3 field.
	EXTI_EMR1_EM3_Msk  = 0x8        // Bit mask of EM3 field.
	EXTI_EMR1_EM3      = 0x8        // Bit EM3.
	EXTI_EMR1_EM4_Pos  = 0x4        // Position of EM4 field.
	EXTI_EMR1_EM4_Msk  = 0x10       // Bit mask of EM4 field.
	EXTI_EMR1_EM4      = 0x10       // Bit EM4.
	EXTI_EMR1_EM5_Pos  = 0x5        // Position of EM5 field.
	EXTI_EMR1_EM5_Msk  = 0x20       // Bit mask of EM5 field.
	EXTI_EMR1_EM5      = 0x20       // Bit EM5.
	EXTI_EMR1_EM6_Pos  = 0x6        // Position of EM6 field.
	EXTI_EMR1_EM6_Msk  = 0x40       // Bit mask of EM6 field.
	EXTI_EMR1_EM6      = 0x40       // Bit EM6.
	EXTI_EMR1_EM7_Pos  = 0x7        // Position of EM7 field.
	EXTI_EMR1_EM7_Msk  = 0x80       // Bit mask of EM7 field.
	EXTI_EMR1_EM7      = 0x80       // Bit EM7.
	EXTI_EMR1_EM8_Pos  = 0x8        // Position of EM8 field.
	EXTI_EMR1_EM8_Msk  = 0x100      // Bit mask of EM8 field.
	EXTI_EMR1_EM8      = 0x100      // Bit EM8.
	EXTI_EMR1_EM9_Pos  = 0x9        // Position of EM9 field.
	EXTI_EMR1_EM9_Msk  = 0x200      // Bit mask of EM9 field.
	EXTI_EMR1_EM9      = 0x200      // Bit EM9.
	EXTI_EMR1_EM10_Pos = 0xa        // Position of EM10 field.
	EXTI_EMR1_EM10_Msk = 0x400      // Bit mask of EM10 field.
	EXTI_EMR1_EM10     = 0x400      // Bit EM10.
	EXTI_EMR1_EM11_Pos = 0xb        // Position of EM11 field.
	EXTI_EMR1_EM11_Msk = 0x800      // Bit mask of EM11 field.
	EXTI_EMR1_EM11     = 0x800      // Bit EM11.
	EXTI_EMR1_EM12_Pos = 0xc        // Position of EM12 field.
	EXTI_EMR1_EM12_Msk = 0x1000     // Bit mask of EM12 field.
	EXTI_EMR1_EM12     = 0x1000     // Bit EM12.
	EXTI_EMR1_EM13_Pos = 0xd        // Position of EM13 field.
	EXTI_EMR1_EM13_Msk = 0x2000     // Bit mask of EM13 field.
	EXTI_EMR1_EM13     = 0x2000     // Bit EM13.
	EXTI_EMR1_EM14_Pos = 0xe        // Position of EM14 field.
	EXTI_EMR1_EM14_Msk = 0x4000     // Bit mask of EM14 field.
	EXTI_EMR1_EM14     = 0x4000     // Bit EM14.
	EXTI_EMR1_EM15_Pos = 0xf        // Position of EM15 field.
	EXTI_EMR1_EM15_Msk = 0x8000     // Bit mask of EM15 field.
	EXTI_EMR1_EM15     = 0x8000     // Bit EM15.
	EXTI_EMR1_EM16_Pos = 0x10       // Position of EM16 field.
	EXTI_EMR1_EM16_Msk = 0x10000    // Bit mask of EM16 field.
	EXTI_EMR1_EM16     = 0x10000    // Bit EM16.
	EXTI_EMR1_EM17_Pos = 0x11       // Position of EM17 field.
	EXTI_EMR1_EM17_Msk = 0x20000    // Bit mask of EM17 field.
	EXTI_EMR1_EM17     = 0x20000    // Bit EM17.
	EXTI_EMR1_EM18_Pos = 0x12       // Position of EM18 field.
	EXTI_EMR1_EM18_Msk = 0x40000    // Bit mask of EM18 field.
	EXTI_EMR1_EM18     = 0x40000    // Bit EM18.
	EXTI_EMR1_EM19_Pos = 0x13       // Position of EM19 field.
	EXTI_EMR1_EM19_Msk = 0x80000    // Bit mask of EM19 field.
	EXTI_EMR1_EM19     = 0x80000    // Bit EM19.
	EXTI_EMR1_EM20_Pos = 0x14       // Position of EM20 field.
	EXTI_EMR1_EM20_Msk = 0x100000   // Bit mask of EM20 field.
	EXTI_EMR1_EM20     = 0x100000   // Bit EM20.
	EXTI_EMR1_EM21_Pos = 0x15       // Position of EM21 field.
	EXTI_EMR1_EM21_Msk = 0x200000   // Bit mask of EM21 field.
	EXTI_EMR1_EM21     = 0x200000   // Bit EM21.
	EXTI_EMR1_EM22_Pos = 0x16       // Position of EM22 field.
	EXTI_EMR1_EM22_Msk = 0x400000   // Bit mask of EM22 field.
	EXTI_EMR1_EM22     = 0x400000   // Bit EM22.
	EXTI_EMR1_EM23_Pos = 0x17       // Position of EM23 field.
	EXTI_EMR1_EM23_Msk = 0x800000   // Bit mask of EM23 field.
	EXTI_EMR1_EM23     = 0x800000   // Bit EM23.
	EXTI_EMR1_EM24_Pos = 0x18       // Position of EM24 field.
	EXTI_EMR1_EM24_Msk = 0x1000000  // Bit mask of EM24 field.
	EXTI_EMR1_EM24     = 0x1000000  // Bit EM24.
	EXTI_EMR1_EM25_Pos = 0x19       // Position of EM25 field.
	EXTI_EMR1_EM25_Msk = 0x2000000  // Bit mask of EM25 field.
	EXTI_EMR1_EM25     = 0x2000000  // Bit EM25.
	EXTI_EMR1_EM26_Pos = 0x1a       // Position of EM26 field.
	EXTI_EMR1_EM26_Msk = 0x4000000  // Bit mask of EM26 field.
	EXTI_EMR1_EM26     = 0x4000000  // Bit EM26.
	EXTI_EMR1_EM27_Pos = 0x1b       // Position of EM27 field.
	EXTI_EMR1_EM27_Msk = 0x8000000  // Bit mask of EM27 field.
	EXTI_EMR1_EM27     = 0x8000000  // Bit EM27.
	EXTI_EMR1_EM28_Pos = 0x1c       // Position of EM28 field.
	EXTI_EMR1_EM28_Msk = 0x10000000 // Bit mask of EM28 field.
	EXTI_EMR1_EM28     = 0x10000000 // Bit EM28.
	EXTI_EMR1_EM29_Pos = 0x1d       // Position of EM29 field.
	EXTI_EMR1_EM29_Msk = 0x20000000 // Bit mask of EM29 field.
	EXTI_EMR1_EM29     = 0x20000000 // Bit EM29.
	EXTI_EMR1_EM30_Pos = 0x1e       // Position of EM30 field.
	EXTI_EMR1_EM30_Msk = 0x40000000 // Bit mask of EM30 field.
	EXTI_EMR1_EM30     = 0x40000000 // Bit EM30.
	EXTI_EMR1_EM31_Pos = 0x1f       // Position of EM31 field.
	EXTI_EMR1_EM31_Msk = 0x80000000 // Bit mask of EM31 field.
	EXTI_EMR1_EM31     = 0x80000000 // Bit EM31.

	// RTSR1: Rising Trigger selection           register
	EXTI_RTSR1_RT0_Pos  = 0x0        // Position of RT0 field.
	EXTI_RTSR1_RT0_Msk  = 0x1        // Bit mask of RT0 field.
	EXTI_RTSR1_RT0      = 0x1        // Bit RT0.
	EXTI_RTSR1_RT1_Pos  = 0x1        // Position of RT1 field.
	EXTI_RTSR1_RT1_Msk  = 0x2        // Bit mask of RT1 field.
	EXTI_RTSR1_RT1      = 0x2        // Bit RT1.
	EXTI_RTSR1_RT2_Pos  = 0x2        // Position of RT2 field.
	EXTI_RTSR1_RT2_Msk  = 0x4        // Bit mask of RT2 field.
	EXTI_RTSR1_RT2      = 0x4        // Bit RT2.
	EXTI_RTSR1_RT3_Pos  = 0x3        // Position of RT3 field.
	EXTI_RTSR1_RT3_Msk  = 0x8        // Bit mask of RT3 field.
	EXTI_RTSR1_RT3      = 0x8        // Bit RT3.
	EXTI_RTSR1_RT4_Pos  = 0x4        // Position of RT4 field.
	EXTI_RTSR1_RT4_Msk  = 0x10       // Bit mask of RT4 field.
	EXTI_RTSR1_RT4      = 0x10       // Bit RT4.
	EXTI_RTSR1_RT5_Pos  = 0x5        // Position of RT5 field.
	EXTI_RTSR1_RT5_Msk  = 0x20       // Bit mask of RT5 field.
	EXTI_RTSR1_RT5      = 0x20       // Bit RT5.
	EXTI_RTSR1_RT6_Pos  = 0x6        // Position of RT6 field.
	EXTI_RTSR1_RT6_Msk  = 0x40       // Bit mask of RT6 field.
	EXTI_RTSR1_RT6      = 0x40       // Bit RT6.
	EXTI_RTSR1_RT7_Pos  = 0x7        // Position of RT7 field.
	EXTI_RTSR1_RT7_Msk  = 0x80       // Bit mask of RT7 field.
	EXTI_RTSR1_RT7      = 0x80       // Bit RT7.
	EXTI_RTSR1_RT8_Pos  = 0x8        // Position of RT8 field.
	EXTI_RTSR1_RT8_Msk  = 0x100      // Bit mask of RT8 field.
	EXTI_RTSR1_RT8      = 0x100      // Bit RT8.
	EXTI_RTSR1_RT9_Pos  = 0x9        // Position of RT9 field.
	EXTI_RTSR1_RT9_Msk  = 0x200      // Bit mask of RT9 field.
	EXTI_RTSR1_RT9      = 0x200      // Bit RT9.
	EXTI_RTSR1_RT10_Pos = 0xa        // Position of RT10 field.
	EXTI_RTSR1_RT10_Msk = 0x400      // Bit mask of RT10 field.
	EXTI_RTSR1_RT10     = 0x400      // Bit RT10.
	EXTI_RTSR1_RT11_Pos = 0xb        // Position of RT11 field.
	EXTI_RTSR1_RT11_Msk = 0x800      // Bit mask of RT11 field.
	EXTI_RTSR1_RT11     = 0x800      // Bit RT11.
	EXTI_RTSR1_RT12_Pos = 0xc        // Position of RT12 field.
	EXTI_RTSR1_RT12_Msk = 0x1000     // Bit mask of RT12 field.
	EXTI_RTSR1_RT12     = 0x1000     // Bit RT12.
	EXTI_RTSR1_RT13_Pos = 0xd        // Position of RT13 field.
	EXTI_RTSR1_RT13_Msk = 0x2000     // Bit mask of RT13 field.
	EXTI_RTSR1_RT13     = 0x2000     // Bit RT13.
	EXTI_RTSR1_RT14_Pos = 0xe        // Position of RT14 field.
	EXTI_RTSR1_RT14_Msk = 0x4000     // Bit mask of RT14 field.
	EXTI_RTSR1_RT14     = 0x4000     // Bit RT14.
	EXTI_RTSR1_RT15_Pos = 0xf        // Position of RT15 field.
	EXTI_RTSR1_RT15_Msk = 0x8000     // Bit mask of RT15 field.
	EXTI_RTSR1_RT15     = 0x8000     // Bit RT15.
	EXTI_RTSR1_RT16_Pos = 0x10       // Position of RT16 field.
	EXTI_RTSR1_RT16_Msk = 0x10000    // Bit mask of RT16 field.
	EXTI_RTSR1_RT16     = 0x10000    // Bit RT16.
	EXTI_RTSR1_RT18_Pos = 0x12       // Position of RT18 field.
	EXTI_RTSR1_RT18_Msk = 0x40000    // Bit mask of RT18 field.
	EXTI_RTSR1_RT18     = 0x40000    // Bit RT18.
	EXTI_RTSR1_RT19_Pos = 0x13       // Position of RT19 field.
	EXTI_RTSR1_RT19_Msk = 0x80000    // Bit mask of RT19 field.
	EXTI_RTSR1_RT19     = 0x80000    // Bit RT19.
	EXTI_RTSR1_RT20_Pos = 0x14       // Position of RT20 field.
	EXTI_RTSR1_RT20_Msk = 0x100000   // Bit mask of RT20 field.
	EXTI_RTSR1_RT20     = 0x100000   // Bit RT20.
	EXTI_RTSR1_RT21_Pos = 0x15       // Position of RT21 field.
	EXTI_RTSR1_RT21_Msk = 0x200000   // Bit mask of RT21 field.
	EXTI_RTSR1_RT21     = 0x200000   // Bit RT21.
	EXTI_RTSR1_RT22_Pos = 0x16       // Position of RT22 field.
	EXTI_RTSR1_RT22_Msk = 0x400000   // Bit mask of RT22 field.
	EXTI_RTSR1_RT22     = 0x400000   // Bit RT22.
	EXTI_RTSR1_RT_Pos   = 0x1d       // Position of RT field.
	EXTI_RTSR1_RT_Msk   = 0xe0000000 // Bit mask of RT field.

	// FTSR1: Falling Trigger selection           register
	EXTI_FTSR1_FT0_Pos  = 0x0      // Position of FT0 field.
	EXTI_FTSR1_FT0_Msk  = 0x1      // Bit mask of FT0 field.
	EXTI_FTSR1_FT0      = 0x1      // Bit FT0.
	EXTI_FTSR1_FT1_Pos  = 0x1      // Position of FT1 field.
	EXTI_FTSR1_FT1_Msk  = 0x2      // Bit mask of FT1 field.
	EXTI_FTSR1_FT1      = 0x2      // Bit FT1.
	EXTI_FTSR1_FT2_Pos  = 0x2      // Position of FT2 field.
	EXTI_FTSR1_FT2_Msk  = 0x4      // Bit mask of FT2 field.
	EXTI_FTSR1_FT2      = 0x4      // Bit FT2.
	EXTI_FTSR1_FT3_Pos  = 0x3      // Position of FT3 field.
	EXTI_FTSR1_FT3_Msk  = 0x8      // Bit mask of FT3 field.
	EXTI_FTSR1_FT3      = 0x8      // Bit FT3.
	EXTI_FTSR1_FT4_Pos  = 0x4      // Position of FT4 field.
	EXTI_FTSR1_FT4_Msk  = 0x10     // Bit mask of FT4 field.
	EXTI_FTSR1_FT4      = 0x10     // Bit FT4.
	EXTI_FTSR1_FT5_Pos  = 0x5      // Position of FT5 field.
	EXTI_FTSR1_FT5_Msk  = 0x20     // Bit mask of FT5 field.
	EXTI_FTSR1_FT5      = 0x20     // Bit FT5.
	EXTI_FTSR1_FT6_Pos  = 0x6      // Position of FT6 field.
	EXTI_FTSR1_FT6_Msk  = 0x40     // Bit mask of FT6 field.
	EXTI_FTSR1_FT6      = 0x40     // Bit FT6.
	EXTI_FTSR1_FT7_Pos  = 0x7      // Position of FT7 field.
	EXTI_FTSR1_FT7_Msk  = 0x80     // Bit mask of FT7 field.
	EXTI_FTSR1_FT7      = 0x80     // Bit FT7.
	EXTI_FTSR1_FT8_Pos  = 0x8      // Position of FT8 field.
	EXTI_FTSR1_FT8_Msk  = 0x100    // Bit mask of FT8 field.
	EXTI_FTSR1_FT8      = 0x100    // Bit FT8.
	EXTI_FTSR1_FT9_Pos  = 0x9      // Position of FT9 field.
	EXTI_FTSR1_FT9_Msk  = 0x200    // Bit mask of FT9 field.
	EXTI_FTSR1_FT9      = 0x200    // Bit FT9.
	EXTI_FTSR1_FT10_Pos = 0xa      // Position of FT10 field.
	EXTI_FTSR1_FT10_Msk = 0x400    // Bit mask of FT10 field.
	EXTI_FTSR1_FT10     = 0x400    // Bit FT10.
	EXTI_FTSR1_FT11_Pos = 0xb      // Position of FT11 field.
	EXTI_FTSR1_FT11_Msk = 0x800    // Bit mask of FT11 field.
	EXTI_FTSR1_FT11     = 0x800    // Bit FT11.
	EXTI_FTSR1_FT12_Pos = 0xc      // Position of FT12 field.
	EXTI_FTSR1_FT12_Msk = 0x1000   // Bit mask of FT12 field.
	EXTI_FTSR1_FT12     = 0x1000   // Bit FT12.
	EXTI_FTSR1_FT13_Pos = 0xd      // Position of FT13 field.
	EXTI_FTSR1_FT13_Msk = 0x2000   // Bit mask of FT13 field.
	EXTI_FTSR1_FT13     = 0x2000   // Bit FT13.
	EXTI_FTSR1_FT14_Pos = 0xe      // Position of FT14 field.
	EXTI_FTSR1_FT14_Msk = 0x4000   // Bit mask of FT14 field.
	EXTI_FTSR1_FT14     = 0x4000   // Bit FT14.
	EXTI_FTSR1_FT15_Pos = 0xf      // Position of FT15 field.
	EXTI_FTSR1_FT15_Msk = 0x8000   // Bit mask of FT15 field.
	EXTI_FTSR1_FT15     = 0x8000   // Bit FT15.
	EXTI_FTSR1_FT16_Pos = 0x10     // Position of FT16 field.
	EXTI_FTSR1_FT16_Msk = 0x10000  // Bit mask of FT16 field.
	EXTI_FTSR1_FT16     = 0x10000  // Bit FT16.
	EXTI_FTSR1_FT18_Pos = 0x12     // Position of FT18 field.
	EXTI_FTSR1_FT18_Msk = 0x40000  // Bit mask of FT18 field.
	EXTI_FTSR1_FT18     = 0x40000  // Bit FT18.
	EXTI_FTSR1_FT19_Pos = 0x13     // Position of FT19 field.
	EXTI_FTSR1_FT19_Msk = 0x80000  // Bit mask of FT19 field.
	EXTI_FTSR1_FT19     = 0x80000  // Bit FT19.
	EXTI_FTSR1_FT20_Pos = 0x14     // Position of FT20 field.
	EXTI_FTSR1_FT20_Msk = 0x100000 // Bit mask of FT20 field.
	EXTI_FTSR1_FT20     = 0x100000 // Bit FT20.
	EXTI_FTSR1_FT21_Pos = 0x15     // Position of FT21 field.
	EXTI_FTSR1_FT21_Msk = 0x200000 // Bit mask of FT21 field.
	EXTI_FTSR1_FT21     = 0x200000 // Bit FT21.
	EXTI_FTSR1_FT22_Pos = 0x16     // Position of FT22 field.
	EXTI_FTSR1_FT22_Msk = 0x400000 // Bit mask of FT22 field.
	EXTI_FTSR1_FT22     = 0x400000 // Bit FT22.

	// SWIER1: Software interrupt event           register
	EXTI_SWIER1_SWI0_Pos  = 0x0      // Position of SWI0 field.
	EXTI_SWIER1_SWI0_Msk  = 0x1      // Bit mask of SWI0 field.
	EXTI_SWIER1_SWI0      = 0x1      // Bit SWI0.
	EXTI_SWIER1_SWI1_Pos  = 0x1      // Position of SWI1 field.
	EXTI_SWIER1_SWI1_Msk  = 0x2      // Bit mask of SWI1 field.
	EXTI_SWIER1_SWI1      = 0x2      // Bit SWI1.
	EXTI_SWIER1_SWI2_Pos  = 0x2      // Position of SWI2 field.
	EXTI_SWIER1_SWI2_Msk  = 0x4      // Bit mask of SWI2 field.
	EXTI_SWIER1_SWI2      = 0x4      // Bit SWI2.
	EXTI_SWIER1_SWI3_Pos  = 0x3      // Position of SWI3 field.
	EXTI_SWIER1_SWI3_Msk  = 0x8      // Bit mask of SWI3 field.
	EXTI_SWIER1_SWI3      = 0x8      // Bit SWI3.
	EXTI_SWIER1_SWI4_Pos  = 0x4      // Position of SWI4 field.
	EXTI_SWIER1_SWI4_Msk  = 0x10     // Bit mask of SWI4 field.
	EXTI_SWIER1_SWI4      = 0x10     // Bit SWI4.
	EXTI_SWIER1_SWI5_Pos  = 0x5      // Position of SWI5 field.
	EXTI_SWIER1_SWI5_Msk  = 0x20     // Bit mask of SWI5 field.
	EXTI_SWIER1_SWI5      = 0x20     // Bit SWI5.
	EXTI_SWIER1_SWI6_Pos  = 0x6      // Position of SWI6 field.
	EXTI_SWIER1_SWI6_Msk  = 0x40     // Bit mask of SWI6 field.
	EXTI_SWIER1_SWI6      = 0x40     // Bit SWI6.
	EXTI_SWIER1_SWI7_Pos  = 0x7      // Position of SWI7 field.
	EXTI_SWIER1_SWI7_Msk  = 0x80     // Bit mask of SWI7 field.
	EXTI_SWIER1_SWI7      = 0x80     // Bit SWI7.
	EXTI_SWIER1_SWI8_Pos  = 0x8      // Position of SWI8 field.
	EXTI_SWIER1_SWI8_Msk  = 0x100    // Bit mask of SWI8 field.
	EXTI_SWIER1_SWI8      = 0x100    // Bit SWI8.
	EXTI_SWIER1_SWI9_Pos  = 0x9      // Position of SWI9 field.
	EXTI_SWIER1_SWI9_Msk  = 0x200    // Bit mask of SWI9 field.
	EXTI_SWIER1_SWI9      = 0x200    // Bit SWI9.
	EXTI_SWIER1_SWI10_Pos = 0xa      // Position of SWI10 field.
	EXTI_SWIER1_SWI10_Msk = 0x400    // Bit mask of SWI10 field.
	EXTI_SWIER1_SWI10     = 0x400    // Bit SWI10.
	EXTI_SWIER1_SWI11_Pos = 0xb      // Position of SWI11 field.
	EXTI_SWIER1_SWI11_Msk = 0x800    // Bit mask of SWI11 field.
	EXTI_SWIER1_SWI11     = 0x800    // Bit SWI11.
	EXTI_SWIER1_SWI12_Pos = 0xc      // Position of SWI12 field.
	EXTI_SWIER1_SWI12_Msk = 0x1000   // Bit mask of SWI12 field.
	EXTI_SWIER1_SWI12     = 0x1000   // Bit SWI12.
	EXTI_SWIER1_SWI13_Pos = 0xd      // Position of SWI13 field.
	EXTI_SWIER1_SWI13_Msk = 0x2000   // Bit mask of SWI13 field.
	EXTI_SWIER1_SWI13     = 0x2000   // Bit SWI13.
	EXTI_SWIER1_SWI14_Pos = 0xe      // Position of SWI14 field.
	EXTI_SWIER1_SWI14_Msk = 0x4000   // Bit mask of SWI14 field.
	EXTI_SWIER1_SWI14     = 0x4000   // Bit SWI14.
	EXTI_SWIER1_SWI15_Pos = 0xf      // Position of SWI15 field.
	EXTI_SWIER1_SWI15_Msk = 0x8000   // Bit mask of SWI15 field.
	EXTI_SWIER1_SWI15     = 0x8000   // Bit SWI15.
	EXTI_SWIER1_SWI16_Pos = 0x10     // Position of SWI16 field.
	EXTI_SWIER1_SWI16_Msk = 0x10000  // Bit mask of SWI16 field.
	EXTI_SWIER1_SWI16     = 0x10000  // Bit SWI16.
	EXTI_SWIER1_SWI18_Pos = 0x12     // Position of SWI18 field.
	EXTI_SWIER1_SWI18_Msk = 0x40000  // Bit mask of SWI18 field.
	EXTI_SWIER1_SWI18     = 0x40000  // Bit SWI18.
	EXTI_SWIER1_SWI19_Pos = 0x13     // Position of SWI19 field.
	EXTI_SWIER1_SWI19_Msk = 0x80000  // Bit mask of SWI19 field.
	EXTI_SWIER1_SWI19     = 0x80000  // Bit SWI19.
	EXTI_SWIER1_SWI20_Pos = 0x14     // Position of SWI20 field.
	EXTI_SWIER1_SWI20_Msk = 0x100000 // Bit mask of SWI20 field.
	EXTI_SWIER1_SWI20     = 0x100000 // Bit SWI20.
	EXTI_SWIER1_SWI21_Pos = 0x15     // Position of SWI21 field.
	EXTI_SWIER1_SWI21_Msk = 0x200000 // Bit mask of SWI21 field.
	EXTI_SWIER1_SWI21     = 0x200000 // Bit SWI21.
	EXTI_SWIER1_SWI22_Pos = 0x16     // Position of SWI22 field.
	EXTI_SWIER1_SWI22_Msk = 0x400000 // Bit mask of SWI22 field.
	EXTI_SWIER1_SWI22     = 0x400000 // Bit SWI22.

	// PR1: Pending register
	EXTI_PR1_PIF0_Pos  = 0x0      // Position of PIF0 field.
	EXTI_PR1_PIF0_Msk  = 0x1      // Bit mask of PIF0 field.
	EXTI_PR1_PIF0      = 0x1      // Bit PIF0.
	EXTI_PR1_PIF1_Pos  = 0x1      // Position of PIF1 field.
	EXTI_PR1_PIF1_Msk  = 0x2      // Bit mask of PIF1 field.
	EXTI_PR1_PIF1      = 0x2      // Bit PIF1.
	EXTI_PR1_PIF2_Pos  = 0x2      // Position of PIF2 field.
	EXTI_PR1_PIF2_Msk  = 0x4      // Bit mask of PIF2 field.
	EXTI_PR1_PIF2      = 0x4      // Bit PIF2.
	EXTI_PR1_PIF3_Pos  = 0x3      // Position of PIF3 field.
	EXTI_PR1_PIF3_Msk  = 0x8      // Bit mask of PIF3 field.
	EXTI_PR1_PIF3      = 0x8      // Bit PIF3.
	EXTI_PR1_PIF4_Pos  = 0x4      // Position of PIF4 field.
	EXTI_PR1_PIF4_Msk  = 0x10     // Bit mask of PIF4 field.
	EXTI_PR1_PIF4      = 0x10     // Bit PIF4.
	EXTI_PR1_PIF5_Pos  = 0x5      // Position of PIF5 field.
	EXTI_PR1_PIF5_Msk  = 0x20     // Bit mask of PIF5 field.
	EXTI_PR1_PIF5      = 0x20     // Bit PIF5.
	EXTI_PR1_PIF6_Pos  = 0x6      // Position of PIF6 field.
	EXTI_PR1_PIF6_Msk  = 0x40     // Bit mask of PIF6 field.
	EXTI_PR1_PIF6      = 0x40     // Bit PIF6.
	EXTI_PR1_PIF7_Pos  = 0x7      // Position of PIF7 field.
	EXTI_PR1_PIF7_Msk  = 0x80     // Bit mask of PIF7 field.
	EXTI_PR1_PIF7      = 0x80     // Bit PIF7.
	EXTI_PR1_PIF8_Pos  = 0x8      // Position of PIF8 field.
	EXTI_PR1_PIF8_Msk  = 0x100    // Bit mask of PIF8 field.
	EXTI_PR1_PIF8      = 0x100    // Bit PIF8.
	EXTI_PR1_PIF9_Pos  = 0x9      // Position of PIF9 field.
	EXTI_PR1_PIF9_Msk  = 0x200    // Bit mask of PIF9 field.
	EXTI_PR1_PIF9      = 0x200    // Bit PIF9.
	EXTI_PR1_PIF10_Pos = 0xa      // Position of PIF10 field.
	EXTI_PR1_PIF10_Msk = 0x400    // Bit mask of PIF10 field.
	EXTI_PR1_PIF10     = 0x400    // Bit PIF10.
	EXTI_PR1_PIF11_Pos = 0xb      // Position of PIF11 field.
	EXTI_PR1_PIF11_Msk = 0x800    // Bit mask of PIF11 field.
	EXTI_PR1_PIF11     = 0x800    // Bit PIF11.
	EXTI_PR1_PIF12_Pos = 0xc      // Position of PIF12 field.
	EXTI_PR1_PIF12_Msk = 0x1000   // Bit mask of PIF12 field.
	EXTI_PR1_PIF12     = 0x1000   // Bit PIF12.
	EXTI_PR1_PIF13_Pos = 0xd      // Position of PIF13 field.
	EXTI_PR1_PIF13_Msk = 0x2000   // Bit mask of PIF13 field.
	EXTI_PR1_PIF13     = 0x2000   // Bit PIF13.
	EXTI_PR1_PIF14_Pos = 0xe      // Position of PIF14 field.
	EXTI_PR1_PIF14_Msk = 0x4000   // Bit mask of PIF14 field.
	EXTI_PR1_PIF14     = 0x4000   // Bit PIF14.
	EXTI_PR1_PIF15_Pos = 0xf      // Position of PIF15 field.
	EXTI_PR1_PIF15_Msk = 0x8000   // Bit mask of PIF15 field.
	EXTI_PR1_PIF15     = 0x8000   // Bit PIF15.
	EXTI_PR1_PIF16_Pos = 0x10     // Position of PIF16 field.
	EXTI_PR1_PIF16_Msk = 0x10000  // Bit mask of PIF16 field.
	EXTI_PR1_PIF16     = 0x10000  // Bit PIF16.
	EXTI_PR1_PIF18_Pos = 0x12     // Position of PIF18 field.
	EXTI_PR1_PIF18_Msk = 0x40000  // Bit mask of PIF18 field.
	EXTI_PR1_PIF18     = 0x40000  // Bit PIF18.
	EXTI_PR1_PIF19_Pos = 0x13     // Position of PIF19 field.
	EXTI_PR1_PIF19_Msk = 0x80000  // Bit mask of PIF19 field.
	EXTI_PR1_PIF19     = 0x80000  // Bit PIF19.
	EXTI_PR1_PIF20_Pos = 0x14     // Position of PIF20 field.
	EXTI_PR1_PIF20_Msk = 0x100000 // Bit mask of PIF20 field.
	EXTI_PR1_PIF20     = 0x100000 // Bit PIF20.
	EXTI_PR1_PIF21_Pos = 0x15     // Position of PIF21 field.
	EXTI_PR1_PIF21_Msk = 0x200000 // Bit mask of PIF21 field.
	EXTI_PR1_PIF21     = 0x200000 // Bit PIF21.
	EXTI_PR1_PIF22_Pos = 0x16     // Position of PIF22 field.
	EXTI_PR1_PIF22_Msk = 0x400000 // Bit mask of PIF22 field.
	EXTI_PR1_PIF22     = 0x400000 // Bit PIF22.

	// IMR2: Interrupt mask register
	EXTI_IMR2_IM32_Pos = 0x0   // Position of IM32 field.
	EXTI_IMR2_IM32_Msk = 0x1   // Bit mask of IM32 field.
	EXTI_IMR2_IM32     = 0x1   // Bit IM32.
	EXTI_IMR2_IM33_Pos = 0x1   // Position of IM33 field.
	EXTI_IMR2_IM33_Msk = 0x2   // Bit mask of IM33 field.
	EXTI_IMR2_IM33     = 0x2   // Bit IM33.
	EXTI_IMR2_IM34_Pos = 0x2   // Position of IM34 field.
	EXTI_IMR2_IM34_Msk = 0x4   // Bit mask of IM34 field.
	EXTI_IMR2_IM34     = 0x4   // Bit IM34.
	EXTI_IMR2_IM35_Pos = 0x3   // Position of IM35 field.
	EXTI_IMR2_IM35_Msk = 0x8   // Bit mask of IM35 field.
	EXTI_IMR2_IM35     = 0x8   // Bit IM35.
	EXTI_IMR2_IM36_Pos = 0x4   // Position of IM36 field.
	EXTI_IMR2_IM36_Msk = 0x10  // Bit mask of IM36 field.
	EXTI_IMR2_IM36     = 0x10  // Bit IM36.
	EXTI_IMR2_IM37_Pos = 0x5   // Position of IM37 field.
	EXTI_IMR2_IM37_Msk = 0x20  // Bit mask of IM37 field.
	EXTI_IMR2_IM37     = 0x20  // Bit IM37.
	EXTI_IMR2_IM38_Pos = 0x6   // Position of IM38 field.
	EXTI_IMR2_IM38_Msk = 0x40  // Bit mask of IM38 field.
	EXTI_IMR2_IM38     = 0x40  // Bit IM38.
	EXTI_IMR2_IM39_Pos = 0x7   // Position of IM39 field.
	EXTI_IMR2_IM39_Msk = 0x80  // Bit mask of IM39 field.
	EXTI_IMR2_IM39     = 0x80  // Bit IM39.
	EXTI_IMR2_IM40_Pos = 0x8   // Position of IM40 field.
	EXTI_IMR2_IM40_Msk = 0x100 // Bit mask of IM40 field.
	EXTI_IMR2_IM40     = 0x100 // Bit IM40.
	EXTI_IMR2_IM41_Pos = 0x9   // Position of IM41 field.
	EXTI_IMR2_IM41_Msk = 0x200 // Bit mask of IM41 field.
	EXTI_IMR2_IM41     = 0x200 // Bit IM41.
	EXTI_IMR2_IM42_Pos = 0xa   // Position of IM42 field.
	EXTI_IMR2_IM42_Msk = 0x400 // Bit mask of IM42 field.
	EXTI_IMR2_IM42     = 0x400 // Bit IM42.
	EXTI_IMR2_IM43_Pos = 0xb   // Position of IM43 field.
	EXTI_IMR2_IM43_Msk = 0x800 // Bit mask of IM43 field.
	EXTI_IMR2_IM43     = 0x800 // Bit IM43.

	// EMR2: Event mask register
	EXTI_EMR2_EM32_Pos = 0x0   // Position of EM32 field.
	EXTI_EMR2_EM32_Msk = 0x1   // Bit mask of EM32 field.
	EXTI_EMR2_EM32     = 0x1   // Bit EM32.
	EXTI_EMR2_EM33_Pos = 0x1   // Position of EM33 field.
	EXTI_EMR2_EM33_Msk = 0x2   // Bit mask of EM33 field.
	EXTI_EMR2_EM33     = 0x2   // Bit EM33.
	EXTI_EMR2_EM34_Pos = 0x2   // Position of EM34 field.
	EXTI_EMR2_EM34_Msk = 0x4   // Bit mask of EM34 field.
	EXTI_EMR2_EM34     = 0x4   // Bit EM34.
	EXTI_EMR2_EM35_Pos = 0x3   // Position of EM35 field.
	EXTI_EMR2_EM35_Msk = 0x8   // Bit mask of EM35 field.
	EXTI_EMR2_EM35     = 0x8   // Bit EM35.
	EXTI_EMR2_EM36_Pos = 0x4   // Position of EM36 field.
	EXTI_EMR2_EM36_Msk = 0x10  // Bit mask of EM36 field.
	EXTI_EMR2_EM36     = 0x10  // Bit EM36.
	EXTI_EMR2_EM37_Pos = 0x5   // Position of EM37 field.
	EXTI_EMR2_EM37_Msk = 0x20  // Bit mask of EM37 field.
	EXTI_EMR2_EM37     = 0x20  // Bit EM37.
	EXTI_EMR2_EM38_Pos = 0x6   // Position of EM38 field.
	EXTI_EMR2_EM38_Msk = 0x40  // Bit mask of EM38 field.
	EXTI_EMR2_EM38     = 0x40  // Bit EM38.
	EXTI_EMR2_EM39_Pos = 0x7   // Position of EM39 field.
	EXTI_EMR2_EM39_Msk = 0x80  // Bit mask of EM39 field.
	EXTI_EMR2_EM39     = 0x80  // Bit EM39.
	EXTI_EMR2_EM40_Pos = 0x8   // Position of EM40 field.
	EXTI_EMR2_EM40_Msk = 0x100 // Bit mask of EM40 field.
	EXTI_EMR2_EM40     = 0x100 // Bit EM40.

	// RTSR2: Rising Trigger selection           register
	EXTI_RTSR2_RT32_Pos = 0x0   // Position of RT32 field.
	EXTI_RTSR2_RT32_Msk = 0x1   // Bit mask of RT32 field.
	EXTI_RTSR2_RT32     = 0x1   // Bit RT32.
	EXTI_RTSR2_RT33_Pos = 0x1   // Position of RT33 field.
	EXTI_RTSR2_RT33_Msk = 0x2   // Bit mask of RT33 field.
	EXTI_RTSR2_RT33     = 0x2   // Bit RT33.
	EXTI_RTSR2_RT38_Pos = 0x6   // Position of RT38 field.
	EXTI_RTSR2_RT38_Msk = 0x40  // Bit mask of RT38 field.
	EXTI_RTSR2_RT38     = 0x40  // Bit RT38.
	EXTI_RTSR2_RT39_Pos = 0x7   // Position of RT39 field.
	EXTI_RTSR2_RT39_Msk = 0x80  // Bit mask of RT39 field.
	EXTI_RTSR2_RT39     = 0x80  // Bit RT39.
	EXTI_RTSR2_RT40_Pos = 0x8   // Position of RT40 field.
	EXTI_RTSR2_RT40_Msk = 0x100 // Bit mask of RT40 field.
	EXTI_RTSR2_RT40     = 0x100 // Bit RT40.
	EXTI_RTSR2_RT41_Pos = 0x9   // Position of RT41 field.
	EXTI_RTSR2_RT41_Msk = 0x200 // Bit mask of RT41 field.
	EXTI_RTSR2_RT41     = 0x200 // Bit RT41.

	// FTSR2: Falling Trigger selection           register
	EXTI_FTSR2_FT35_Pos = 0x3  // Position of FT35 field.
	EXTI_FTSR2_FT35_Msk = 0x8  // Bit mask of FT35 field.
	EXTI_FTSR2_FT35     = 0x8  // Bit FT35.
	EXTI_FTSR2_FT36_Pos = 0x4  // Position of FT36 field.
	EXTI_FTSR2_FT36_Msk = 0x10 // Bit mask of FT36 field.
	EXTI_FTSR2_FT36     = 0x10 // Bit FT36.
	EXTI_FTSR2_FT37_Pos = 0x5  // Position of FT37 field.
	EXTI_FTSR2_FT37_Msk = 0x20 // Bit mask of FT37 field.
	EXTI_FTSR2_FT37     = 0x20 // Bit FT37.
	EXTI_FTSR2_FT38_Pos = 0x6  // Position of FT38 field.
	EXTI_FTSR2_FT38_Msk = 0x40 // Bit mask of FT38 field.
	EXTI_FTSR2_FT38     = 0x40 // Bit FT38.

	// SWIER2: Software interrupt event           register
	EXTI_SWIER2_SWI35_Pos = 0x3  // Position of SWI35 field.
	EXTI_SWIER2_SWI35_Msk = 0x8  // Bit mask of SWI35 field.
	EXTI_SWIER2_SWI35     = 0x8  // Bit SWI35.
	EXTI_SWIER2_SWI36_Pos = 0x4  // Position of SWI36 field.
	EXTI_SWIER2_SWI36_Msk = 0x10 // Bit mask of SWI36 field.
	EXTI_SWIER2_SWI36     = 0x10 // Bit SWI36.
	EXTI_SWIER2_SWI37_Pos = 0x5  // Position of SWI37 field.
	EXTI_SWIER2_SWI37_Msk = 0x20 // Bit mask of SWI37 field.
	EXTI_SWIER2_SWI37     = 0x20 // Bit SWI37.
	EXTI_SWIER2_SWI38_Pos = 0x6  // Position of SWI38 field.
	EXTI_SWIER2_SWI38_Msk = 0x40 // Bit mask of SWI38 field.
	EXTI_SWIER2_SWI38     = 0x40 // Bit SWI38.

	// PR2: Pending register
	EXTI_PR2_PIF35_Pos = 0x3  // Position of PIF35 field.
	EXTI_PR2_PIF35_Msk = 0x8  // Bit mask of PIF35 field.
	EXTI_PR2_PIF35     = 0x8  // Bit PIF35.
	EXTI_PR2_PIF36_Pos = 0x4  // Position of PIF36 field.
	EXTI_PR2_PIF36_Msk = 0x10 // Bit mask of PIF36 field.
	EXTI_PR2_PIF36     = 0x10 // Bit PIF36.
	EXTI_PR2_PIF37_Pos = 0x5  // Position of PIF37 field.
	EXTI_PR2_PIF37_Msk = 0x20 // Bit mask of PIF37 field.
	EXTI_PR2_PIF37     = 0x20 // Bit PIF37.
	EXTI_PR2_PIF38_Pos = 0x6  // Position of PIF38 field.
	EXTI_PR2_PIF38_Msk = 0x40 // Bit mask of PIF38 field.
	EXTI_PR2_PIF38     = 0x40 // Bit PIF38.
)

// Bitfields for RTC: Real-time clock
const (
	// TR: time register
	RTC_TR_PM_Pos  = 0x16     // Position of PM field.
	RTC_TR_PM_Msk  = 0x400000 // Bit mask of PM field.
	RTC_TR_PM      = 0x400000 // Bit PM.
	RTC_TR_HT_Pos  = 0x14     // Position of HT field.
	RTC_TR_HT_Msk  = 0x300000 // Bit mask of HT field.
	RTC_TR_HU_Pos  = 0x10     // Position of HU field.
	RTC_TR_HU_Msk  = 0xf0000  // Bit mask of HU field.
	RTC_TR_MNT_Pos = 0xc      // Position of MNT field.
	RTC_TR_MNT_Msk = 0x7000   // Bit mask of MNT field.
	RTC_TR_MNU_Pos = 0x8      // Position of MNU field.
	RTC_TR_MNU_Msk = 0xf00    // Bit mask of MNU field.
	RTC_TR_ST_Pos  = 0x4      // Position of ST field.
	RTC_TR_ST_Msk  = 0x70     // Bit mask of ST field.
	RTC_TR_SU_Pos  = 0x0      // Position of SU field.
	RTC_TR_SU_Msk  = 0xf      // Bit mask of SU field.

	// DR: date register
	RTC_DR_YT_Pos  = 0x14     // Position of YT field.
	RTC_DR_YT_Msk  = 0xf00000 // Bit mask of YT field.
	RTC_DR_YU_Pos  = 0x10     // Position of YU field.
	RTC_DR_YU_Msk  = 0xf0000  // Bit mask of YU field.
	RTC_DR_WDU_Pos = 0xd      // Position of WDU field.
	RTC_DR_WDU_Msk = 0xe000   // Bit mask of WDU field.
	RTC_DR_MT_Pos  = 0xc      // Position of MT field.
	RTC_DR_MT_Msk  = 0x1000   // Bit mask of MT field.
	RTC_DR_MT      = 0x1000   // Bit MT.
	RTC_DR_MU_Pos  = 0x8      // Position of MU field.
	RTC_DR_MU_Msk  = 0xf00    // Bit mask of MU field.
	RTC_DR_DT_Pos  = 0x4      // Position of DT field.
	RTC_DR_DT_Msk  = 0x30     // Bit mask of DT field.
	RTC_DR_DU_Pos  = 0x0      // Position of DU field.
	RTC_DR_DU_Msk  = 0xf      // Bit mask of DU field.

	// SSR: sub second register
	RTC_SSR_SS_Pos = 0x0    // Position of SS field.
	RTC_SSR_SS_Msk = 0xffff // Bit mask of SS field.

	// ICSR: initialization and status           register
	RTC_ICSR_ALRAWF_Pos  = 0x0     // Position of ALRAWF field.
	RTC_ICSR_ALRAWF_Msk  = 0x1     // Bit mask of ALRAWF field.
	RTC_ICSR_ALRAWF      = 0x1     // Bit ALRAWF.
	RTC_ICSR_ALRBWF_Pos  = 0x1     // Position of ALRBWF field.
	RTC_ICSR_ALRBWF_Msk  = 0x2     // Bit mask of ALRBWF field.
	RTC_ICSR_ALRBWF      = 0x2     // Bit ALRBWF.
	RTC_ICSR_WUTWF_Pos   = 0x2     // Position of WUTWF field.
	RTC_ICSR_WUTWF_Msk   = 0x4     // Bit mask of WUTWF field.
	RTC_ICSR_WUTWF       = 0x4     // Bit WUTWF.
	RTC_ICSR_SHPF_Pos    = 0x3     // Position of SHPF field.
	RTC_ICSR_SHPF_Msk    = 0x8     // Bit mask of SHPF field.
	RTC_ICSR_SHPF        = 0x8     // Bit SHPF.
	RTC_ICSR_INITS_Pos   = 0x4     // Position of INITS field.
	RTC_ICSR_INITS_Msk   = 0x10    // Bit mask of INITS field.
	RTC_ICSR_INITS       = 0x10    // Bit INITS.
	RTC_ICSR_RSF_Pos     = 0x5     // Position of RSF field.
	RTC_ICSR_RSF_Msk     = 0x20    // Bit mask of RSF field.
	RTC_ICSR_RSF         = 0x20    // Bit RSF.
	RTC_ICSR_INITF_Pos   = 0x6     // Position of INITF field.
	RTC_ICSR_INITF_Msk   = 0x40    // Bit mask of INITF field.
	RTC_ICSR_INITF       = 0x40    // Bit INITF.
	RTC_ICSR_INIT_Pos    = 0x7     // Position of INIT field.
	RTC_ICSR_INIT_Msk    = 0x80    // Bit mask of INIT field.
	RTC_ICSR_INIT        = 0x80    // Bit INIT.
	RTC_ICSR_RECALPF_Pos = 0x10    // Position of RECALPF field.
	RTC_ICSR_RECALPF_Msk = 0x10000 // Bit mask of RECALPF field.
	RTC_ICSR_RECALPF     = 0x10000 // Bit RECALPF.

	// PRER: prescaler register
	RTC_PRER_PREDIV_A_Pos = 0x10     // Position of PREDIV_A field.
	RTC_PRER_PREDIV_A_Msk = 0x7f0000 // Bit mask of PREDIV_A field.
	RTC_PRER_PREDIV_S_Pos = 0x0      // Position of PREDIV_S field.
	RTC_PRER_PREDIV_S_Msk = 0x7fff   // Bit mask of PREDIV_S field.

	// WUTR: wakeup timer register
	RTC_WUTR_WUT_Pos = 0x0    // Position of WUT field.
	RTC_WUTR_WUT_Msk = 0xffff // Bit mask of WUT field.

	// CR: control register
	RTC_CR_WCKSEL_Pos        = 0x0        // Position of WCKSEL field.
	RTC_CR_WCKSEL_Msk        = 0x7        // Bit mask of WCKSEL field.
	RTC_CR_TSEDGE_Pos        = 0x3        // Position of TSEDGE field.
	RTC_CR_TSEDGE_Msk        = 0x8        // Bit mask of TSEDGE field.
	RTC_CR_TSEDGE            = 0x8        // Bit TSEDGE.
	RTC_CR_REFCKON_Pos       = 0x4        // Position of REFCKON field.
	RTC_CR_REFCKON_Msk       = 0x10       // Bit mask of REFCKON field.
	RTC_CR_REFCKON           = 0x10       // Bit REFCKON.
	RTC_CR_BYPSHAD_Pos       = 0x5        // Position of BYPSHAD field.
	RTC_CR_BYPSHAD_Msk       = 0x20       // Bit mask of BYPSHAD field.
	RTC_CR_BYPSHAD           = 0x20       // Bit BYPSHAD.
	RTC_CR_FMT_Pos           = 0x6        // Position of FMT field.
	RTC_CR_FMT_Msk           = 0x40       // Bit mask of FMT field.
	RTC_CR_FMT               = 0x40       // Bit FMT.
	RTC_CR_ALRAE_Pos         = 0x8        // Position of ALRAE field.
	RTC_CR_ALRAE_Msk         = 0x100      // Bit mask of ALRAE field.
	RTC_CR_ALRAE             = 0x100      // Bit ALRAE.
	RTC_CR_ALRBE_Pos         = 0x9        // Position of ALRBE field.
	RTC_CR_ALRBE_Msk         = 0x200      // Bit mask of ALRBE field.
	RTC_CR_ALRBE             = 0x200      // Bit ALRBE.
	RTC_CR_WUTE_Pos          = 0xa        // Position of WUTE field.
	RTC_CR_WUTE_Msk          = 0x400      // Bit mask of WUTE field.
	RTC_CR_WUTE              = 0x400      // Bit WUTE.
	RTC_CR_TSE_Pos           = 0xb        // Position of TSE field.
	RTC_CR_TSE_Msk           = 0x800      // Bit mask of TSE field.
	RTC_CR_TSE               = 0x800      // Bit TSE.
	RTC_CR_ALRAIE_Pos        = 0xc        // Position of ALRAIE field.
	RTC_CR_ALRAIE_Msk        = 0x1000     // Bit mask of ALRAIE field.
	RTC_CR_ALRAIE            = 0x1000     // Bit ALRAIE.
	RTC_CR_ALRBIE_Pos        = 0xd        // Position of ALRBIE field.
	RTC_CR_ALRBIE_Msk        = 0x2000     // Bit mask of ALRBIE field.
	RTC_CR_ALRBIE            = 0x2000     // Bit ALRBIE.
	RTC_CR_WUTIE_Pos         = 0xe        // Position of WUTIE field.
	RTC_CR_WUTIE_Msk         = 0x4000     // Bit mask of WUTIE field.
	RTC_CR_WUTIE             = 0x4000     // Bit WUTIE.
	RTC_CR_TSIE_Pos          = 0xf        // Position of TSIE field.
	RTC_CR_TSIE_Msk          = 0x8000     // Bit mask of TSIE field.
	RTC_CR_TSIE              = 0x8000     // Bit TSIE.
	RTC_CR_ADD1H_Pos         = 0x10       // Position of ADD1H field.
	RTC_CR_ADD1H_Msk         = 0x10000    // Bit mask of ADD1H field.
	RTC_CR_ADD1H             = 0x10000    // Bit ADD1H.
	RTC_CR_SUB1H_Pos         = 0x11       // Position of SUB1H field.
	RTC_CR_SUB1H_Msk         = 0x20000    // Bit mask of SUB1H field.
	RTC_CR_SUB1H             = 0x20000    // Bit SUB1H.
	RTC_CR_BKP_Pos           = 0x12       // Position of BKP field.
	RTC_CR_BKP_Msk           = 0x40000    // Bit mask of BKP field.
	RTC_CR_BKP               = 0x40000    // Bit BKP.
	RTC_CR_COSEL_Pos         = 0x13       // Position of COSEL field.
	RTC_CR_COSEL_Msk         = 0x80000    // Bit mask of COSEL field.
	RTC_CR_COSEL             = 0x80000    // Bit COSEL.
	RTC_CR_POL_Pos           = 0x14       // Position of POL field.
	RTC_CR_POL_Msk           = 0x100000   // Bit mask of POL field.
	RTC_CR_POL               = 0x100000   // Bit POL.
	RTC_CR_OSEL_Pos          = 0x15       // Position of OSEL field.
	RTC_CR_OSEL_Msk          = 0x600000   // Bit mask of OSEL field.
	RTC_CR_COE_Pos           = 0x17       // Position of COE field.
	RTC_CR_COE_Msk           = 0x800000   // Bit mask of COE field.
	RTC_CR_COE               = 0x800000   // Bit COE.
	RTC_CR_ITSE_Pos          = 0x18       // Position of ITSE field.
	RTC_CR_ITSE_Msk          = 0x1000000  // Bit mask of ITSE field.
	RTC_CR_ITSE              = 0x1000000  // Bit ITSE.
	RTC_CR_TAMPTS_Pos        = 0x19       // Position of TAMPTS field.
	RTC_CR_TAMPTS_Msk        = 0x2000000  // Bit mask of TAMPTS field.
	RTC_CR_TAMPTS            = 0x2000000  // Bit TAMPTS.
	RTC_CR_TAMPOE_Pos        = 0x1a       // Position of TAMPOE field.
	RTC_CR_TAMPOE_Msk        = 0x4000000  // Bit mask of TAMPOE field.
	RTC_CR_TAMPOE            = 0x4000000  // Bit TAMPOE.
	RTC_CR_TAMPALRM_PU_Pos   = 0x1d       // Position of TAMPALRM_PU field.
	RTC_CR_TAMPALRM_PU_Msk   = 0x20000000 // Bit mask of TAMPALRM_PU field.
	RTC_CR_TAMPALRM_PU       = 0x20000000 // Bit TAMPALRM_PU.
	RTC_CR_TAMPALRM_TYPE_Pos = 0x1e       // Position of TAMPALRM_TYPE field.
	RTC_CR_TAMPALRM_TYPE_Msk = 0x40000000 // Bit mask of TAMPALRM_TYPE field.
	RTC_CR_TAMPALRM_TYPE     = 0x40000000 // Bit TAMPALRM_TYPE.
	RTC_CR_OUT2EN_Pos        = 0x1f       // Position of OUT2EN field.
	RTC_CR_OUT2EN_Msk        = 0x80000000 // Bit mask of OUT2EN field.
	RTC_CR_OUT2EN            = 0x80000000 // Bit OUT2EN.

	// WPR: write protection register
	RTC_WPR_KEY_Pos = 0x0  // Position of KEY field.
	RTC_WPR_KEY_Msk = 0xff // Bit mask of KEY field.

	// CALR: calibration register
	RTC_CALR_CALP_Pos   = 0xf    // Position of CALP field.
	RTC_CALR_CALP_Msk   = 0x8000 // Bit mask of CALP field.
	RTC_CALR_CALP       = 0x8000 // Bit CALP.
	RTC_CALR_CALW8_Pos  = 0xe    // Position of CALW8 field.
	RTC_CALR_CALW8_Msk  = 0x4000 // Bit mask of CALW8 field.
	RTC_CALR_CALW8      = 0x4000 // Bit CALW8.
	RTC_CALR_CALW16_Pos = 0xd    // Position of CALW16 field.
	RTC_CALR_CALW16_Msk = 0x2000 // Bit mask of CALW16 field.
	RTC_CALR_CALW16     = 0x2000 // Bit CALW16.
	RTC_CALR_CALM_Pos   = 0x0    // Position of CALM field.
	RTC_CALR_CALM_Msk   = 0x1ff  // Bit mask of CALM field.

	// SHIFTR: shift control register
	RTC_SHIFTR_ADD1S_Pos = 0x1f       // Position of ADD1S field.
	RTC_SHIFTR_ADD1S_Msk = 0x80000000 // Bit mask of ADD1S field.
	RTC_SHIFTR_ADD1S     = 0x80000000 // Bit ADD1S.
	RTC_SHIFTR_SUBFS_Pos = 0x0        // Position of SUBFS field.
	RTC_SHIFTR_SUBFS_Msk = 0x7fff     // Bit mask of SUBFS field.

	// TSTR: time stamp time register
	RTC_TSTR_SU_Pos  = 0x0      // Position of SU field.
	RTC_TSTR_SU_Msk  = 0xf      // Bit mask of SU field.
	RTC_TSTR_ST_Pos  = 0x4      // Position of ST field.
	RTC_TSTR_ST_Msk  = 0x70     // Bit mask of ST field.
	RTC_TSTR_MNU_Pos = 0x8      // Position of MNU field.
	RTC_TSTR_MNU_Msk = 0xf00    // Bit mask of MNU field.
	RTC_TSTR_MNT_Pos = 0xc      // Position of MNT field.
	RTC_TSTR_MNT_Msk = 0x7000   // Bit mask of MNT field.
	RTC_TSTR_HU_Pos  = 0x10     // Position of HU field.
	RTC_TSTR_HU_Msk  = 0xf0000  // Bit mask of HU field.
	RTC_TSTR_HT_Pos  = 0x14     // Position of HT field.
	RTC_TSTR_HT_Msk  = 0x300000 // Bit mask of HT field.
	RTC_TSTR_PM_Pos  = 0x16     // Position of PM field.
	RTC_TSTR_PM_Msk  = 0x400000 // Bit mask of PM field.
	RTC_TSTR_PM      = 0x400000 // Bit PM.

	// TSDR: time stamp date register
	RTC_TSDR_WDU_Pos = 0xd    // Position of WDU field.
	RTC_TSDR_WDU_Msk = 0xe000 // Bit mask of WDU field.
	RTC_TSDR_MT_Pos  = 0xc    // Position of MT field.
	RTC_TSDR_MT_Msk  = 0x1000 // Bit mask of MT field.
	RTC_TSDR_MT      = 0x1000 // Bit MT.
	RTC_TSDR_MU_Pos  = 0x8    // Position of MU field.
	RTC_TSDR_MU_Msk  = 0xf00  // Bit mask of MU field.
	RTC_TSDR_DT_Pos  = 0x4    // Position of DT field.
	RTC_TSDR_DT_Msk  = 0x30   // Bit mask of DT field.
	RTC_TSDR_DU_Pos  = 0x0    // Position of DU field.
	RTC_TSDR_DU_Msk  = 0xf    // Bit mask of DU field.

	// TSSSR: timestamp sub second register
	RTC_TSSSR_SS_Pos = 0x0    // Position of SS field.
	RTC_TSSSR_SS_Msk = 0xffff // Bit mask of SS field.

	// ALRMAR: alarm A register
	RTC_ALRMAR_MSK4_Pos  = 0x1f       // Position of MSK4 field.
	RTC_ALRMAR_MSK4_Msk  = 0x80000000 // Bit mask of MSK4 field.
	RTC_ALRMAR_MSK4      = 0x80000000 // Bit MSK4.
	RTC_ALRMAR_WDSEL_Pos = 0x1e       // Position of WDSEL field.
	RTC_ALRMAR_WDSEL_Msk = 0x40000000 // Bit mask of WDSEL field.
	RTC_ALRMAR_WDSEL     = 0x40000000 // Bit WDSEL.
	RTC_ALRMAR_DT_Pos    = 0x1c       // Position of DT field.
	RTC_ALRMAR_DT_Msk    = 0x30000000 // Bit mask of DT field.
	RTC_ALRMAR_DU_Pos    = 0x18       // Position of DU field.
	RTC_ALRMAR_DU_Msk    = 0xf000000  // Bit mask of DU field.
	RTC_ALRMAR_MSK3_Pos  = 0x17       // Position of MSK3 field.
	RTC_ALRMAR_MSK3_Msk  = 0x800000   // Bit mask of MSK3 field.
	RTC_ALRMAR_MSK3      = 0x800000   // Bit MSK3.
	RTC_ALRMAR_PM_Pos    = 0x16       // Position of PM field.
	RTC_ALRMAR_PM_Msk    = 0x400000   // Bit mask of PM field.
	RTC_ALRMAR_PM        = 0x400000   // Bit PM.
	RTC_ALRMAR_HT_Pos    = 0x14       // Position of HT field.
	RTC_ALRMAR_HT_Msk    = 0x300000   // Bit mask of HT field.
	RTC_ALRMAR_HU_Pos    = 0x10       // Position of HU field.
	RTC_ALRMAR_HU_Msk    = 0xf0000    // Bit mask of HU field.
	RTC_ALRMAR_MSK2_Pos  = 0xf        // Position of MSK2 field.
	RTC_ALRMAR_MSK2_Msk  = 0x8000     // Bit mask of MSK2 field.
	RTC_ALRMAR_MSK2      = 0x8000     // Bit MSK2.
	RTC_ALRMAR_MNT_Pos   = 0xc        // Position of MNT field.
	RTC_ALRMAR_MNT_Msk   = 0x7000     // Bit mask of MNT field.
	RTC_ALRMAR_MNU_Pos   = 0x8        // Position of MNU field.
	RTC_ALRMAR_MNU_Msk   = 0xf00      // Bit mask of MNU field.
	RTC_ALRMAR_MSK1_Pos  = 0x7        // Position of MSK1 field.
	RTC_ALRMAR_MSK1_Msk  = 0x80       // Bit mask of MSK1 field.
	RTC_ALRMAR_MSK1      = 0x80       // Bit MSK1.
	RTC_ALRMAR_ST_Pos    = 0x4        // Position of ST field.
	RTC_ALRMAR_ST_Msk    = 0x70       // Bit mask of ST field.
	RTC_ALRMAR_SU_Pos    = 0x0        // Position of SU field.
	RTC_ALRMAR_SU_Msk    = 0xf        // Bit mask of SU field.

	// ALRMASSR: alarm A sub second register
	RTC_ALRMASSR_MASKSS_Pos = 0x18      // Position of MASKSS field.
	RTC_ALRMASSR_MASKSS_Msk = 0xf000000 // Bit mask of MASKSS field.
	RTC_ALRMASSR_SS_Pos     = 0x0       // Position of SS field.
	RTC_ALRMASSR_SS_Msk     = 0x7fff    // Bit mask of SS field.

	// ALRMBR: alarm B register
	RTC_ALRMBR_MSK4_Pos  = 0x1f       // Position of MSK4 field.
	RTC_ALRMBR_MSK4_Msk  = 0x80000000 // Bit mask of MSK4 field.
	RTC_ALRMBR_MSK4      = 0x80000000 // Bit MSK4.
	RTC_ALRMBR_WDSEL_Pos = 0x1e       // Position of WDSEL field.
	RTC_ALRMBR_WDSEL_Msk = 0x40000000 // Bit mask of WDSEL field.
	RTC_ALRMBR_WDSEL     = 0x40000000 // Bit WDSEL.
	RTC_ALRMBR_DT_Pos    = 0x1c       // Position of DT field.
	RTC_ALRMBR_DT_Msk    = 0x30000000 // Bit mask of DT field.
	RTC_ALRMBR_DU_Pos    = 0x18       // Position of DU field.
	RTC_ALRMBR_DU_Msk    = 0xf000000  // Bit mask of DU field.
	RTC_ALRMBR_MSK3_Pos  = 0x17       // Position of MSK3 field.
	RTC_ALRMBR_MSK3_Msk  = 0x800000   // Bit mask of MSK3 field.
	RTC_ALRMBR_MSK3      = 0x800000   // Bit MSK3.
	RTC_ALRMBR_PM_Pos    = 0x16       // Position of PM field.
	RTC_ALRMBR_PM_Msk    = 0x400000   // Bit mask of PM field.
	RTC_ALRMBR_PM        = 0x400000   // Bit PM.
	RTC_ALRMBR_HT_Pos    = 0x14       // Position of HT field.
	RTC_ALRMBR_HT_Msk    = 0x300000   // Bit mask of HT field.
	RTC_ALRMBR_HU_Pos    = 0x10       // Position of HU field.
	RTC_ALRMBR_HU_Msk    = 0xf0000    // Bit mask of HU field.
	RTC_ALRMBR_MSK2_Pos  = 0xf        // Position of MSK2 field.
	RTC_ALRMBR_MSK2_Msk  = 0x8000     // Bit mask of MSK2 field.
	RTC_ALRMBR_MSK2      = 0x8000     // Bit MSK2.
	RTC_ALRMBR_MNT_Pos   = 0xc        // Position of MNT field.
	RTC_ALRMBR_MNT_Msk   = 0x7000     // Bit mask of MNT field.
	RTC_ALRMBR_MNU_Pos   = 0x8        // Position of MNU field.
	RTC_ALRMBR_MNU_Msk   = 0xf00      // Bit mask of MNU field.
	RTC_ALRMBR_MSK1_Pos  = 0x7        // Position of MSK1 field.
	RTC_ALRMBR_MSK1_Msk  = 0x80       // Bit mask of MSK1 field.
	RTC_ALRMBR_MSK1      = 0x80       // Bit MSK1.
	RTC_ALRMBR_ST_Pos    = 0x4        // Position of ST field.
	RTC_ALRMBR_ST_Msk    = 0x70       // Bit mask of ST field.
	RTC_ALRMBR_SU_Pos    = 0x0        // Position of SU field.
	RTC_ALRMBR_SU_Msk    = 0xf        // Bit mask of SU field.

	// ALRMBSSR: alarm B sub second register
	RTC_ALRMBSSR_MASKSS_Pos = 0x18      // Position of MASKSS field.
	RTC_ALRMBSSR_MASKSS_Msk = 0xf000000 // Bit mask of MASKSS field.
	RTC_ALRMBSSR_SS_Pos     = 0x0       // Position of SS field.
	RTC_ALRMBSSR_SS_Msk     = 0x7fff    // Bit mask of SS field.

	// SR: status register
	RTC_SR_ALRAF_Pos = 0x0  // Position of ALRAF field.
	RTC_SR_ALRAF_Msk = 0x1  // Bit mask of ALRAF field.
	RTC_SR_ALRAF     = 0x1  // Bit ALRAF.
	RTC_SR_ALRBF_Pos = 0x1  // Position of ALRBF field.
	RTC_SR_ALRBF_Msk = 0x2  // Bit mask of ALRBF field.
	RTC_SR_ALRBF     = 0x2  // Bit ALRBF.
	RTC_SR_WUTF_Pos  = 0x2  // Position of WUTF field.
	RTC_SR_WUTF_Msk  = 0x4  // Bit mask of WUTF field.
	RTC_SR_WUTF      = 0x4  // Bit WUTF.
	RTC_SR_TSF_Pos   = 0x3  // Position of TSF field.
	RTC_SR_TSF_Msk   = 0x8  // Bit mask of TSF field.
	RTC_SR_TSF       = 0x8  // Bit TSF.
	RTC_SR_TSOVF_Pos = 0x4  // Position of TSOVF field.
	RTC_SR_TSOVF_Msk = 0x10 // Bit mask of TSOVF field.
	RTC_SR_TSOVF     = 0x10 // Bit TSOVF.
	RTC_SR_ITSF_Pos  = 0x5  // Position of ITSF field.
	RTC_SR_ITSF_Msk  = 0x20 // Bit mask of ITSF field.
	RTC_SR_ITSF      = 0x20 // Bit ITSF.

	// MISR: status register
	RTC_MISR_ALRAMF_Pos = 0x0  // Position of ALRAMF field.
	RTC_MISR_ALRAMF_Msk = 0x1  // Bit mask of ALRAMF field.
	RTC_MISR_ALRAMF     = 0x1  // Bit ALRAMF.
	RTC_MISR_ALRBMF_Pos = 0x1  // Position of ALRBMF field.
	RTC_MISR_ALRBMF_Msk = 0x2  // Bit mask of ALRBMF field.
	RTC_MISR_ALRBMF     = 0x2  // Bit ALRBMF.
	RTC_MISR_WUTMF_Pos  = 0x2  // Position of WUTMF field.
	RTC_MISR_WUTMF_Msk  = 0x4  // Bit mask of WUTMF field.
	RTC_MISR_WUTMF      = 0x4  // Bit WUTMF.
	RTC_MISR_TSMF_Pos   = 0x3  // Position of TSMF field.
	RTC_MISR_TSMF_Msk   = 0x8  // Bit mask of TSMF field.
	RTC_MISR_TSMF       = 0x8  // Bit TSMF.
	RTC_MISR_TSOVMF_Pos = 0x4  // Position of TSOVMF field.
	RTC_MISR_TSOVMF_Msk = 0x10 // Bit mask of TSOVMF field.
	RTC_MISR_TSOVMF     = 0x10 // Bit TSOVMF.
	RTC_MISR_ITSMF_Pos  = 0x5  // Position of ITSMF field.
	RTC_MISR_ITSMF_Msk  = 0x20 // Bit mask of ITSMF field.
	RTC_MISR_ITSMF      = 0x20 // Bit ITSMF.

	// SCR: status register
	RTC_SCR_CALRAF_Pos = 0x0  // Position of CALRAF field.
	RTC_SCR_CALRAF_Msk = 0x1  // Bit mask of CALRAF field.
	RTC_SCR_CALRAF     = 0x1  // Bit CALRAF.
	RTC_SCR_CALRBF_Pos = 0x1  // Position of CALRBF field.
	RTC_SCR_CALRBF_Msk = 0x2  // Bit mask of CALRBF field.
	RTC_SCR_CALRBF     = 0x2  // Bit CALRBF.
	RTC_SCR_CWUTF_Pos  = 0x2  // Position of CWUTF field.
	RTC_SCR_CWUTF_Msk  = 0x4  // Bit mask of CWUTF field.
	RTC_SCR_CWUTF      = 0x4  // Bit CWUTF.
	RTC_SCR_CTSF_Pos   = 0x3  // Position of CTSF field.
	RTC_SCR_CTSF_Msk   = 0x8  // Bit mask of CTSF field.
	RTC_SCR_CTSF       = 0x8  // Bit CTSF.
	RTC_SCR_CTSOVF_Pos = 0x4  // Position of CTSOVF field.
	RTC_SCR_CTSOVF_Msk = 0x10 // Bit mask of CTSOVF field.
	RTC_SCR_CTSOVF     = 0x10 // Bit CTSOVF.
	RTC_SCR_CITSF_Pos  = 0x5  // Position of CITSF field.
	RTC_SCR_CITSF_Msk  = 0x20 // Bit mask of CITSF field.
	RTC_SCR_CITSF      = 0x20 // Bit CITSF.
)

// Bitfields for FMC: Flexible memory controller
const (
	// BCR1: SRAM/NOR-Flash chip-select control register           1
	FMC_BCR1_MBKEN_Pos     = 0x0      // Position of MBKEN field.
	FMC_BCR1_MBKEN_Msk     = 0x1      // Bit mask of MBKEN field.
	FMC_BCR1_MBKEN         = 0x1      // Bit MBKEN.
	FMC_BCR1_MUXEN_Pos     = 0x1      // Position of MUXEN field.
	FMC_BCR1_MUXEN_Msk     = 0x2      // Bit mask of MUXEN field.
	FMC_BCR1_MUXEN         = 0x2      // Bit MUXEN.
	FMC_BCR1_MTYP_Pos      = 0x2      // Position of MTYP field.
	FMC_BCR1_MTYP_Msk      = 0xc      // Bit mask of MTYP field.
	FMC_BCR1_MWID_Pos      = 0x4      // Position of MWID field.
	FMC_BCR1_MWID_Msk      = 0x30     // Bit mask of MWID field.
	FMC_BCR1_FACCEN_Pos    = 0x6      // Position of FACCEN field.
	FMC_BCR1_FACCEN_Msk    = 0x40     // Bit mask of FACCEN field.
	FMC_BCR1_FACCEN        = 0x40     // Bit FACCEN.
	FMC_BCR1_BURSTEN_Pos   = 0x8      // Position of BURSTEN field.
	FMC_BCR1_BURSTEN_Msk   = 0x100    // Bit mask of BURSTEN field.
	FMC_BCR1_BURSTEN       = 0x100    // Bit BURSTEN.
	FMC_BCR1_WAITPOL_Pos   = 0x9      // Position of WAITPOL field.
	FMC_BCR1_WAITPOL_Msk   = 0x200    // Bit mask of WAITPOL field.
	FMC_BCR1_WAITPOL       = 0x200    // Bit WAITPOL.
	FMC_BCR1_WAITCFG_Pos   = 0xb      // Position of WAITCFG field.
	FMC_BCR1_WAITCFG_Msk   = 0x800    // Bit mask of WAITCFG field.
	FMC_BCR1_WAITCFG       = 0x800    // Bit WAITCFG.
	FMC_BCR1_WREN_Pos      = 0xc      // Position of WREN field.
	FMC_BCR1_WREN_Msk      = 0x1000   // Bit mask of WREN field.
	FMC_BCR1_WREN          = 0x1000   // Bit WREN.
	FMC_BCR1_WAITEN_Pos    = 0xd      // Position of WAITEN field.
	FMC_BCR1_WAITEN_Msk    = 0x2000   // Bit mask of WAITEN field.
	FMC_BCR1_WAITEN        = 0x2000   // Bit WAITEN.
	FMC_BCR1_EXTMOD_Pos    = 0xe      // Position of EXTMOD field.
	FMC_BCR1_EXTMOD_Msk    = 0x4000   // Bit mask of EXTMOD field.
	FMC_BCR1_EXTMOD        = 0x4000   // Bit EXTMOD.
	FMC_BCR1_ASYNCWAIT_Pos = 0xf      // Position of ASYNCWAIT field.
	FMC_BCR1_ASYNCWAIT_Msk = 0x8000   // Bit mask of ASYNCWAIT field.
	FMC_BCR1_ASYNCWAIT     = 0x8000   // Bit ASYNCWAIT.
	FMC_BCR1_CPSIZE_Pos    = 0x10     // Position of CPSIZE field.
	FMC_BCR1_CPSIZE_Msk    = 0x70000  // Bit mask of CPSIZE field.
	FMC_BCR1_CBURSTRW_Pos  = 0x13     // Position of CBURSTRW field.
	FMC_BCR1_CBURSTRW_Msk  = 0x80000  // Bit mask of CBURSTRW field.
	FMC_BCR1_CBURSTRW      = 0x80000  // Bit CBURSTRW.
	FMC_BCR1_CCLKEN_Pos    = 0x14     // Position of CCLKEN field.
	FMC_BCR1_CCLKEN_Msk    = 0x100000 // Bit mask of CCLKEN field.
	FMC_BCR1_CCLKEN        = 0x100000 // Bit CCLKEN.
	FMC_BCR1_WFDIS_Pos     = 0x15     // Position of WFDIS field.
	FMC_BCR1_WFDIS_Msk     = 0x200000 // Bit mask of WFDIS field.
	FMC_BCR1_WFDIS         = 0x200000 // Bit WFDIS.
	FMC_BCR1_NBLSET_Pos    = 0x16     // Position of NBLSET field.
	FMC_BCR1_NBLSET_Msk    = 0xc00000 // Bit mask of NBLSET field.

	// BTR1: SRAM/NOR-Flash chip-select timing register           1
	FMC_BTR1_DATAHLD_Pos = 0x1e       // Position of DATAHLD field.
	FMC_BTR1_DATAHLD_Msk = 0xc0000000 // Bit mask of DATAHLD field.
	FMC_BTR1_ACCMOD_Pos  = 0x1c       // Position of ACCMOD field.
	FMC_BTR1_ACCMOD_Msk  = 0x30000000 // Bit mask of ACCMOD field.
	FMC_BTR1_DATLAT_Pos  = 0x18       // Position of DATLAT field.
	FMC_BTR1_DATLAT_Msk  = 0xf000000  // Bit mask of DATLAT field.
	FMC_BTR1_CLKDIV_Pos  = 0x14       // Position of CLKDIV field.
	FMC_BTR1_CLKDIV_Msk  = 0xf00000   // Bit mask of CLKDIV field.
	FMC_BTR1_BUSTURN_Pos = 0x10       // Position of BUSTURN field.
	FMC_BTR1_BUSTURN_Msk = 0xf0000    // Bit mask of BUSTURN field.
	FMC_BTR1_DATAST_Pos  = 0x8        // Position of DATAST field.
	FMC_BTR1_DATAST_Msk  = 0xff00     // Bit mask of DATAST field.
	FMC_BTR1_ADDHLD_Pos  = 0x4        // Position of ADDHLD field.
	FMC_BTR1_ADDHLD_Msk  = 0xf0       // Bit mask of ADDHLD field.
	FMC_BTR1_ADDSET_Pos  = 0x0        // Position of ADDSET field.
	FMC_BTR1_ADDSET_Msk  = 0xf        // Bit mask of ADDSET field.

	// BCR2: SRAM/NOR-Flash chip-select control register           2
	FMC_BCR2_MBKEN_Pos     = 0x0      // Position of MBKEN field.
	FMC_BCR2_MBKEN_Msk     = 0x1      // Bit mask of MBKEN field.
	FMC_BCR2_MBKEN         = 0x1      // Bit MBKEN.
	FMC_BCR2_MUXEN_Pos     = 0x1      // Position of MUXEN field.
	FMC_BCR2_MUXEN_Msk     = 0x2      // Bit mask of MUXEN field.
	FMC_BCR2_MUXEN         = 0x2      // Bit MUXEN.
	FMC_BCR2_MTYP_Pos      = 0x2      // Position of MTYP field.
	FMC_BCR2_MTYP_Msk      = 0xc      // Bit mask of MTYP field.
	FMC_BCR2_MWID_Pos      = 0x4      // Position of MWID field.
	FMC_BCR2_MWID_Msk      = 0x30     // Bit mask of MWID field.
	FMC_BCR2_FACCEN_Pos    = 0x6      // Position of FACCEN field.
	FMC_BCR2_FACCEN_Msk    = 0x40     // Bit mask of FACCEN field.
	FMC_BCR2_FACCEN        = 0x40     // Bit FACCEN.
	FMC_BCR2_BURSTEN_Pos   = 0x8      // Position of BURSTEN field.
	FMC_BCR2_BURSTEN_Msk   = 0x100    // Bit mask of BURSTEN field.
	FMC_BCR2_BURSTEN       = 0x100    // Bit BURSTEN.
	FMC_BCR2_WAITPOL_Pos   = 0x9      // Position of WAITPOL field.
	FMC_BCR2_WAITPOL_Msk   = 0x200    // Bit mask of WAITPOL field.
	FMC_BCR2_WAITPOL       = 0x200    // Bit WAITPOL.
	FMC_BCR2_WAITCFG_Pos   = 0xb      // Position of WAITCFG field.
	FMC_BCR2_WAITCFG_Msk   = 0x800    // Bit mask of WAITCFG field.
	FMC_BCR2_WAITCFG       = 0x800    // Bit WAITCFG.
	FMC_BCR2_WREN_Pos      = 0xc      // Position of WREN field.
	FMC_BCR2_WREN_Msk      = 0x1000   // Bit mask of WREN field.
	FMC_BCR2_WREN          = 0x1000   // Bit WREN.
	FMC_BCR2_WAITEN_Pos    = 0xd      // Position of WAITEN field.
	FMC_BCR2_WAITEN_Msk    = 0x2000   // Bit mask of WAITEN field.
	FMC_BCR2_WAITEN        = 0x2000   // Bit WAITEN.
	FMC_BCR2_EXTMOD_Pos    = 0xe      // Position of EXTMOD field.
	FMC_BCR2_EXTMOD_Msk    = 0x4000   // Bit mask of EXTMOD field.
	FMC_BCR2_EXTMOD        = 0x4000   // Bit EXTMOD.
	FMC_BCR2_ASYNCWAIT_Pos = 0xf      // Position of ASYNCWAIT field.
	FMC_BCR2_ASYNCWAIT_Msk = 0x8000   // Bit mask of ASYNCWAIT field.
	FMC_BCR2_ASYNCWAIT     = 0x8000   // Bit ASYNCWAIT.
	FMC_BCR2_CPSIZE_Pos    = 0x10     // Position of CPSIZE field.
	FMC_BCR2_CPSIZE_Msk    = 0x70000  // Bit mask of CPSIZE field.
	FMC_BCR2_CBURSTRW_Pos  = 0x13     // Position of CBURSTRW field.
	FMC_BCR2_CBURSTRW_Msk  = 0x80000  // Bit mask of CBURSTRW field.
	FMC_BCR2_CBURSTRW      = 0x80000  // Bit CBURSTRW.
	FMC_BCR2_CCLKEN_Pos    = 0x14     // Position of CCLKEN field.
	FMC_BCR2_CCLKEN_Msk    = 0x100000 // Bit mask of CCLKEN field.
	FMC_BCR2_CCLKEN        = 0x100000 // Bit CCLKEN.
	FMC_BCR2_WFDIS_Pos     = 0x15     // Position of WFDIS field.
	FMC_BCR2_WFDIS_Msk     = 0x200000 // Bit mask of WFDIS field.
	FMC_BCR2_WFDIS         = 0x200000 // Bit WFDIS.
	FMC_BCR2_NBLSET_Pos    = 0x16     // Position of NBLSET field.
	FMC_BCR2_NBLSET_Msk    = 0xc00000 // Bit mask of NBLSET field.

	// BTR2: SRAM/NOR-Flash chip-select timing register           2
	FMC_BTR2_DATAHLD_Pos = 0x1e       // Position of DATAHLD field.
	FMC_BTR2_DATAHLD_Msk = 0xc0000000 // Bit mask of DATAHLD field.
	FMC_BTR2_ACCMOD_Pos  = 0x1c       // Position of ACCMOD field.
	FMC_BTR2_ACCMOD_Msk  = 0x30000000 // Bit mask of ACCMOD field.
	FMC_BTR2_DATLAT_Pos  = 0x18       // Position of DATLAT field.
	FMC_BTR2_DATLAT_Msk  = 0xf000000  // Bit mask of DATLAT field.
	FMC_BTR2_CLKDIV_Pos  = 0x14       // Position of CLKDIV field.
	FMC_BTR2_CLKDIV_Msk  = 0xf00000   // Bit mask of CLKDIV field.
	FMC_BTR2_BUSTURN_Pos = 0x10       // Position of BUSTURN field.
	FMC_BTR2_BUSTURN_Msk = 0xf0000    // Bit mask of BUSTURN field.
	FMC_BTR2_DATAST_Pos  = 0x8        // Position of DATAST field.
	FMC_BTR2_DATAST_Msk  = 0xff00     // Bit mask of DATAST field.
	FMC_BTR2_ADDHLD_Pos  = 0x4        // Position of ADDHLD field.
	FMC_BTR2_ADDHLD_Msk  = 0xf0       // Bit mask of ADDHLD field.
	FMC_BTR2_ADDSET_Pos  = 0x0        // Position of ADDSET field.
	FMC_BTR2_ADDSET_Msk  = 0xf        // Bit mask of ADDSET field.

	// BCR3: SRAM/NOR-Flash chip-select control register           3
	FMC_BCR3_MBKEN_Pos     = 0x0      // Position of MBKEN field.
	FMC_BCR3_MBKEN_Msk     = 0x1      // Bit mask of MBKEN field.
	FMC_BCR3_MBKEN         = 0x1      // Bit MBKEN.
	FMC_BCR3_MUXEN_Pos     = 0x1      // Position of MUXEN field.
	FMC_BCR3_MUXEN_Msk     = 0x2      // Bit mask of MUXEN field.
	FMC_BCR3_MUXEN         = 0x2      // Bit MUXEN.
	FMC_BCR3_MTYP_Pos      = 0x2      // Position of MTYP field.
	FMC_BCR3_MTYP_Msk      = 0xc      // Bit mask of MTYP field.
	FMC_BCR3_MWID_Pos      = 0x4      // Position of MWID field.
	FMC_BCR3_MWID_Msk      = 0x30     // Bit mask of MWID field.
	FMC_BCR3_FACCEN_Pos    = 0x6      // Position of FACCEN field.
	FMC_BCR3_FACCEN_Msk    = 0x40     // Bit mask of FACCEN field.
	FMC_BCR3_FACCEN        = 0x40     // Bit FACCEN.
	FMC_BCR3_BURSTEN_Pos   = 0x8      // Position of BURSTEN field.
	FMC_BCR3_BURSTEN_Msk   = 0x100    // Bit mask of BURSTEN field.
	FMC_BCR3_BURSTEN       = 0x100    // Bit BURSTEN.
	FMC_BCR3_WAITPOL_Pos   = 0x9      // Position of WAITPOL field.
	FMC_BCR3_WAITPOL_Msk   = 0x200    // Bit mask of WAITPOL field.
	FMC_BCR3_WAITPOL       = 0x200    // Bit WAITPOL.
	FMC_BCR3_WAITCFG_Pos   = 0xb      // Position of WAITCFG field.
	FMC_BCR3_WAITCFG_Msk   = 0x800    // Bit mask of WAITCFG field.
	FMC_BCR3_WAITCFG       = 0x800    // Bit WAITCFG.
	FMC_BCR3_WREN_Pos      = 0xc      // Position of WREN field.
	FMC_BCR3_WREN_Msk      = 0x1000   // Bit mask of WREN field.
	FMC_BCR3_WREN          = 0x1000   // Bit WREN.
	FMC_BCR3_WAITEN_Pos    = 0xd      // Position of WAITEN field.
	FMC_BCR3_WAITEN_Msk    = 0x2000   // Bit mask of WAITEN field.
	FMC_BCR3_WAITEN        = 0x2000   // Bit WAITEN.
	FMC_BCR3_EXTMOD_Pos    = 0xe      // Position of EXTMOD field.
	FMC_BCR3_EXTMOD_Msk    = 0x4000   // Bit mask of EXTMOD field.
	FMC_BCR3_EXTMOD        = 0x4000   // Bit EXTMOD.
	FMC_BCR3_ASYNCWAIT_Pos = 0xf      // Position of ASYNCWAIT field.
	FMC_BCR3_ASYNCWAIT_Msk = 0x8000   // Bit mask of ASYNCWAIT field.
	FMC_BCR3_ASYNCWAIT     = 0x8000   // Bit ASYNCWAIT.
	FMC_BCR3_CPSIZE_Pos    = 0x10     // Position of CPSIZE field.
	FMC_BCR3_CPSIZE_Msk    = 0x70000  // Bit mask of CPSIZE field.
	FMC_BCR3_CBURSTRW_Pos  = 0x13     // Position of CBURSTRW field.
	FMC_BCR3_CBURSTRW_Msk  = 0x80000  // Bit mask of CBURSTRW field.
	FMC_BCR3_CBURSTRW      = 0x80000  // Bit CBURSTRW.
	FMC_BCR3_CCLKEN_Pos    = 0x14     // Position of CCLKEN field.
	FMC_BCR3_CCLKEN_Msk    = 0x100000 // Bit mask of CCLKEN field.
	FMC_BCR3_CCLKEN        = 0x100000 // Bit CCLKEN.
	FMC_BCR3_WFDIS_Pos     = 0x15     // Position of WFDIS field.
	FMC_BCR3_WFDIS_Msk     = 0x200000 // Bit mask of WFDIS field.
	FMC_BCR3_WFDIS         = 0x200000 // Bit WFDIS.
	FMC_BCR3_NBLSET_Pos    = 0x16     // Position of NBLSET field.
	FMC_BCR3_NBLSET_Msk    = 0xc00000 // Bit mask of NBLSET field.

	// BTR3: SRAM/NOR-Flash chip-select timing register           3
	FMC_BTR3_DATAHLD_Pos = 0x1e       // Position of DATAHLD field.
	FMC_BTR3_DATAHLD_Msk = 0xc0000000 // Bit mask of DATAHLD field.
	FMC_BTR3_ACCMOD_Pos  = 0x1c       // Position of ACCMOD field.
	FMC_BTR3_ACCMOD_Msk  = 0x30000000 // Bit mask of ACCMOD field.
	FMC_BTR3_DATLAT_Pos  = 0x18       // Position of DATLAT field.
	FMC_BTR3_DATLAT_Msk  = 0xf000000  // Bit mask of DATLAT field.
	FMC_BTR3_CLKDIV_Pos  = 0x14       // Position of CLKDIV field.
	FMC_BTR3_CLKDIV_Msk  = 0xf00000   // Bit mask of CLKDIV field.
	FMC_BTR3_BUSTURN_Pos = 0x10       // Position of BUSTURN field.
	FMC_BTR3_BUSTURN_Msk = 0xf0000    // Bit mask of BUSTURN field.
	FMC_BTR3_DATAST_Pos  = 0x8        // Position of DATAST field.
	FMC_BTR3_DATAST_Msk  = 0xff00     // Bit mask of DATAST field.
	FMC_BTR3_ADDHLD_Pos  = 0x4        // Position of ADDHLD field.
	FMC_BTR3_ADDHLD_Msk  = 0xf0       // Bit mask of ADDHLD field.
	FMC_BTR3_ADDSET_Pos  = 0x0        // Position of ADDSET field.
	FMC_BTR3_ADDSET_Msk  = 0xf        // Bit mask of ADDSET field.

	// BCR4: SRAM/NOR-Flash chip-select control register           4
	FMC_BCR4_MBKEN_Pos     = 0x0      // Position of MBKEN field.
	FMC_BCR4_MBKEN_Msk     = 0x1      // Bit mask of MBKEN field.
	FMC_BCR4_MBKEN         = 0x1      // Bit MBKEN.
	FMC_BCR4_MUXEN_Pos     = 0x1      // Position of MUXEN field.
	FMC_BCR4_MUXEN_Msk     = 0x2      // Bit mask of MUXEN field.
	FMC_BCR4_MUXEN         = 0x2      // Bit MUXEN.
	FMC_BCR4_MTYP_Pos      = 0x2      // Position of MTYP field.
	FMC_BCR4_MTYP_Msk      = 0xc      // Bit mask of MTYP field.
	FMC_BCR4_MWID_Pos      = 0x4      // Position of MWID field.
	FMC_BCR4_MWID_Msk      = 0x30     // Bit mask of MWID field.
	FMC_BCR4_FACCEN_Pos    = 0x6      // Position of FACCEN field.
	FMC_BCR4_FACCEN_Msk    = 0x40     // Bit mask of FACCEN field.
	FMC_BCR4_FACCEN        = 0x40     // Bit FACCEN.
	FMC_BCR4_BURSTEN_Pos   = 0x8      // Position of BURSTEN field.
	FMC_BCR4_BURSTEN_Msk   = 0x100    // Bit mask of BURSTEN field.
	FMC_BCR4_BURSTEN       = 0x100    // Bit BURSTEN.
	FMC_BCR4_WAITPOL_Pos   = 0x9      // Position of WAITPOL field.
	FMC_BCR4_WAITPOL_Msk   = 0x200    // Bit mask of WAITPOL field.
	FMC_BCR4_WAITPOL       = 0x200    // Bit WAITPOL.
	FMC_BCR4_WAITCFG_Pos   = 0xb      // Position of WAITCFG field.
	FMC_BCR4_WAITCFG_Msk   = 0x800    // Bit mask of WAITCFG field.
	FMC_BCR4_WAITCFG       = 0x800    // Bit WAITCFG.
	FMC_BCR4_WREN_Pos      = 0xc      // Position of WREN field.
	FMC_BCR4_WREN_Msk      = 0x1000   // Bit mask of WREN field.
	FMC_BCR4_WREN          = 0x1000   // Bit WREN.
	FMC_BCR4_WAITEN_Pos    = 0xd      // Position of WAITEN field.
	FMC_BCR4_WAITEN_Msk    = 0x2000   // Bit mask of WAITEN field.
	FMC_BCR4_WAITEN        = 0x2000   // Bit WAITEN.
	FMC_BCR4_EXTMOD_Pos    = 0xe      // Position of EXTMOD field.
	FMC_BCR4_EXTMOD_Msk    = 0x4000   // Bit mask of EXTMOD field.
	FMC_BCR4_EXTMOD        = 0x4000   // Bit EXTMOD.
	FMC_BCR4_ASYNCWAIT_Pos = 0xf      // Position of ASYNCWAIT field.
	FMC_BCR4_ASYNCWAIT_Msk = 0x8000   // Bit mask of ASYNCWAIT field.
	FMC_BCR4_ASYNCWAIT     = 0x8000   // Bit ASYNCWAIT.
	FMC_BCR4_CPSIZE_Pos    = 0x10     // Position of CPSIZE field.
	FMC_BCR4_CPSIZE_Msk    = 0x70000  // Bit mask of CPSIZE field.
	FMC_BCR4_CBURSTRW_Pos  = 0x13     // Position of CBURSTRW field.
	FMC_BCR4_CBURSTRW_Msk  = 0x80000  // Bit mask of CBURSTRW field.
	FMC_BCR4_CBURSTRW      = 0x80000  // Bit CBURSTRW.
	FMC_BCR4_CCLKEN_Pos    = 0x14     // Position of CCLKEN field.
	FMC_BCR4_CCLKEN_Msk    = 0x100000 // Bit mask of CCLKEN field.
	FMC_BCR4_CCLKEN        = 0x100000 // Bit CCLKEN.
	FMC_BCR4_WFDIS_Pos     = 0x15     // Position of WFDIS field.
	FMC_BCR4_WFDIS_Msk     = 0x200000 // Bit mask of WFDIS field.
	FMC_BCR4_WFDIS         = 0x200000 // Bit WFDIS.
	FMC_BCR4_NBLSET_Pos    = 0x16     // Position of NBLSET field.
	FMC_BCR4_NBLSET_Msk    = 0xc00000 // Bit mask of NBLSET field.

	// BTR4: SRAM/NOR-Flash chip-select timing register           4
	FMC_BTR4_DATAHLD_Pos = 0x1e       // Position of DATAHLD field.
	FMC_BTR4_DATAHLD_Msk = 0xc0000000 // Bit mask of DATAHLD field.
	FMC_BTR4_ACCMOD_Pos  = 0x1c       // Position of ACCMOD field.
	FMC_BTR4_ACCMOD_Msk  = 0x30000000 // Bit mask of ACCMOD field.
	FMC_BTR4_DATLAT_Pos  = 0x18       // Position of DATLAT field.
	FMC_BTR4_DATLAT_Msk  = 0xf000000  // Bit mask of DATLAT field.
	FMC_BTR4_CLKDIV_Pos  = 0x14       // Position of CLKDIV field.
	FMC_BTR4_CLKDIV_Msk  = 0xf00000   // Bit mask of CLKDIV field.
	FMC_BTR4_BUSTURN_Pos = 0x10       // Position of BUSTURN field.
	FMC_BTR4_BUSTURN_Msk = 0xf0000    // Bit mask of BUSTURN field.
	FMC_BTR4_DATAST_Pos  = 0x8        // Position of DATAST field.
	FMC_BTR4_DATAST_Msk  = 0xff00     // Bit mask of DATAST field.
	FMC_BTR4_ADDHLD_Pos  = 0x4        // Position of ADDHLD field.
	FMC_BTR4_ADDHLD_Msk  = 0xf0       // Bit mask of ADDHLD field.
	FMC_BTR4_ADDSET_Pos  = 0x0        // Position of ADDSET field.
	FMC_BTR4_ADDSET_Msk  = 0xf        // Bit mask of ADDSET field.

	// PCSCNTR: PSRAM chip select counter           register
	FMC_PCSCNTR_CSCOUNT_Pos = 0x0     // Position of CSCOUNT field.
	FMC_PCSCNTR_CSCOUNT_Msk = 0xffff  // Bit mask of CSCOUNT field.
	FMC_PCSCNTR_CNTB1EN_Pos = 0x10    // Position of CNTB1EN field.
	FMC_PCSCNTR_CNTB1EN_Msk = 0x10000 // Bit mask of CNTB1EN field.
	FMC_PCSCNTR_CNTB1EN     = 0x10000 // Bit CNTB1EN.
	FMC_PCSCNTR_CNTB2EN_Pos = 0x11    // Position of CNTB2EN field.
	FMC_PCSCNTR_CNTB2EN_Msk = 0x20000 // Bit mask of CNTB2EN field.
	FMC_PCSCNTR_CNTB2EN     = 0x20000 // Bit CNTB2EN.
	FMC_PCSCNTR_CNTB3EN_Pos = 0x12    // Position of CNTB3EN field.
	FMC_PCSCNTR_CNTB3EN_Msk = 0x40000 // Bit mask of CNTB3EN field.
	FMC_PCSCNTR_CNTB3EN     = 0x40000 // Bit CNTB3EN.
	FMC_PCSCNTR_CNTB4EN_Pos = 0x13    // Position of CNTB4EN field.
	FMC_PCSCNTR_CNTB4EN_Msk = 0x80000 // Bit mask of CNTB4EN field.
	FMC_PCSCNTR_CNTB4EN     = 0x80000 // Bit CNTB4EN.

	// PCR: PC Card/NAND Flash control register           3
	FMC_PCR_ECCPS_Pos   = 0x11    // Position of ECCPS field.
	FMC_PCR_ECCPS_Msk   = 0xe0000 // Bit mask of ECCPS field.
	FMC_PCR_TAR_Pos     = 0xd     // Position of TAR field.
	FMC_PCR_TAR_Msk     = 0x1e000 // Bit mask of TAR field.
	FMC_PCR_TCLR_Pos    = 0x9     // Position of TCLR field.
	FMC_PCR_TCLR_Msk    = 0x1e00  // Bit mask of TCLR field.
	FMC_PCR_ECCEN_Pos   = 0x6     // Position of ECCEN field.
	FMC_PCR_ECCEN_Msk   = 0x40    // Bit mask of ECCEN field.
	FMC_PCR_ECCEN       = 0x40    // Bit ECCEN.
	FMC_PCR_PWID_Pos    = 0x4     // Position of PWID field.
	FMC_PCR_PWID_Msk    = 0x30    // Bit mask of PWID field.
	FMC_PCR_PTYP_Pos    = 0x3     // Position of PTYP field.
	FMC_PCR_PTYP_Msk    = 0x8     // Bit mask of PTYP field.
	FMC_PCR_PTYP        = 0x8     // Bit PTYP.
	FMC_PCR_PBKEN_Pos   = 0x2     // Position of PBKEN field.
	FMC_PCR_PBKEN_Msk   = 0x4     // Bit mask of PBKEN field.
	FMC_PCR_PBKEN       = 0x4     // Bit PBKEN.
	FMC_PCR_PWAITEN_Pos = 0x1     // Position of PWAITEN field.
	FMC_PCR_PWAITEN_Msk = 0x2     // Bit mask of PWAITEN field.
	FMC_PCR_PWAITEN     = 0x2     // Bit PWAITEN.

	// SR: FIFO status and interrupt register           3
	FMC_SR_FEMPT_Pos = 0x6  // Position of FEMPT field.
	FMC_SR_FEMPT_Msk = 0x40 // Bit mask of FEMPT field.
	FMC_SR_FEMPT     = 0x40 // Bit FEMPT.
	FMC_SR_IFEN_Pos  = 0x5  // Position of IFEN field.
	FMC_SR_IFEN_Msk  = 0x20 // Bit mask of IFEN field.
	FMC_SR_IFEN      = 0x20 // Bit IFEN.
	FMC_SR_ILEN_Pos  = 0x4  // Position of ILEN field.
	FMC_SR_ILEN_Msk  = 0x10 // Bit mask of ILEN field.
	FMC_SR_ILEN      = 0x10 // Bit ILEN.
	FMC_SR_IREN_Pos  = 0x3  // Position of IREN field.
	FMC_SR_IREN_Msk  = 0x8  // Bit mask of IREN field.
	FMC_SR_IREN      = 0x8  // Bit IREN.
	FMC_SR_IFS_Pos   = 0x2  // Position of IFS field.
	FMC_SR_IFS_Msk   = 0x4  // Bit mask of IFS field.
	FMC_SR_IFS       = 0x4  // Bit IFS.
	FMC_SR_ILS_Pos   = 0x1  // Position of ILS field.
	FMC_SR_ILS_Msk   = 0x2  // Bit mask of ILS field.
	FMC_SR_ILS       = 0x2  // Bit ILS.
	FMC_SR_IRS_Pos   = 0x0  // Position of IRS field.
	FMC_SR_IRS_Msk   = 0x1  // Bit mask of IRS field.
	FMC_SR_IRS       = 0x1  // Bit IRS.

	// PMEM: Common memory space timing register           3
	FMC_PMEM_MEMHIZx_Pos  = 0x18       // Position of MEMHIZx field.
	FMC_PMEM_MEMHIZx_Msk  = 0xff000000 // Bit mask of MEMHIZx field.
	FMC_PMEM_MEMHOLDx_Pos = 0x10       // Position of MEMHOLDx field.
	FMC_PMEM_MEMHOLDx_Msk = 0xff0000   // Bit mask of MEMHOLDx field.
	FMC_PMEM_MEMWAITx_Pos = 0x8        // Position of MEMWAITx field.
	FMC_PMEM_MEMWAITx_Msk = 0xff00     // Bit mask of MEMWAITx field.
	FMC_PMEM_MEMSETx_Pos  = 0x0        // Position of MEMSETx field.
	FMC_PMEM_MEMSETx_Msk  = 0xff       // Bit mask of MEMSETx field.

	// PATT: Attribute memory space timing register           3
	FMC_PATT_ATTHIZx_Pos  = 0x18       // Position of ATTHIZx field.
	FMC_PATT_ATTHIZx_Msk  = 0xff000000 // Bit mask of ATTHIZx field.
	FMC_PATT_ATTHOLDx_Pos = 0x10       // Position of ATTHOLDx field.
	FMC_PATT_ATTHOLDx_Msk = 0xff0000   // Bit mask of ATTHOLDx field.
	FMC_PATT_ATTWAITx_Pos = 0x8        // Position of ATTWAITx field.
	FMC_PATT_ATTWAITx_Msk = 0xff00     // Bit mask of ATTWAITx field.
	FMC_PATT_ATTSETx_Pos  = 0x0        // Position of ATTSETx field.
	FMC_PATT_ATTSETx_Msk  = 0xff       // Bit mask of ATTSETx field.

	// ECCR: ECC result register 3
	FMC_ECCR_ECCx_Pos = 0x0        // Position of ECCx field.
	FMC_ECCR_ECCx_Msk = 0xffffffff // Bit mask of ECCx field.

	// BWTR1: SRAM/NOR-Flash write timing registers           1
	FMC_BWTR1_DATAHLD_Pos = 0x1e       // Position of DATAHLD field.
	FMC_BWTR1_DATAHLD_Msk = 0xc0000000 // Bit mask of DATAHLD field.
	FMC_BWTR1_ACCMOD_Pos  = 0x1c       // Position of ACCMOD field.
	FMC_BWTR1_ACCMOD_Msk  = 0x30000000 // Bit mask of ACCMOD field.
	FMC_BWTR1_BUSTURN_Pos = 0x10       // Position of BUSTURN field.
	FMC_BWTR1_BUSTURN_Msk = 0xf0000    // Bit mask of BUSTURN field.
	FMC_BWTR1_DATAST_Pos  = 0x8        // Position of DATAST field.
	FMC_BWTR1_DATAST_Msk  = 0xff00     // Bit mask of DATAST field.
	FMC_BWTR1_ADDHLD_Pos  = 0x4        // Position of ADDHLD field.
	FMC_BWTR1_ADDHLD_Msk  = 0xf0       // Bit mask of ADDHLD field.
	FMC_BWTR1_ADDSET_Pos  = 0x0        // Position of ADDSET field.
	FMC_BWTR1_ADDSET_Msk  = 0xf        // Bit mask of ADDSET field.

	// BWTR2: SRAM/NOR-Flash write timing registers           2
	FMC_BWTR2_DATAHLD_Pos = 0x1e       // Position of DATAHLD field.
	FMC_BWTR2_DATAHLD_Msk = 0xc0000000 // Bit mask of DATAHLD field.
	FMC_BWTR2_ACCMOD_Pos  = 0x1c       // Position of ACCMOD field.
	FMC_BWTR2_ACCMOD_Msk  = 0x30000000 // Bit mask of ACCMOD field.
	FMC_BWTR2_BUSTURN_Pos = 0x10       // Position of BUSTURN field.
	FMC_BWTR2_BUSTURN_Msk = 0xf0000    // Bit mask of BUSTURN field.
	FMC_BWTR2_DATAST_Pos  = 0x8        // Position of DATAST field.
	FMC_BWTR2_DATAST_Msk  = 0xff00     // Bit mask of DATAST field.
	FMC_BWTR2_ADDHLD_Pos  = 0x4        // Position of ADDHLD field.
	FMC_BWTR2_ADDHLD_Msk  = 0xf0       // Bit mask of ADDHLD field.
	FMC_BWTR2_ADDSET_Pos  = 0x0        // Position of ADDSET field.
	FMC_BWTR2_ADDSET_Msk  = 0xf        // Bit mask of ADDSET field.

	// BWTR3: SRAM/NOR-Flash write timing registers           3
	FMC_BWTR3_DATAHLD_Pos = 0x1e       // Position of DATAHLD field.
	FMC_BWTR3_DATAHLD_Msk = 0xc0000000 // Bit mask of DATAHLD field.
	FMC_BWTR3_ACCMOD_Pos  = 0x1c       // Position of ACCMOD field.
	FMC_BWTR3_ACCMOD_Msk  = 0x30000000 // Bit mask of ACCMOD field.
	FMC_BWTR3_BUSTURN_Pos = 0x10       // Position of BUSTURN field.
	FMC_BWTR3_BUSTURN_Msk = 0xf0000    // Bit mask of BUSTURN field.
	FMC_BWTR3_DATAST_Pos  = 0x8        // Position of DATAST field.
	FMC_BWTR3_DATAST_Msk  = 0xff00     // Bit mask of DATAST field.
	FMC_BWTR3_ADDHLD_Pos  = 0x4        // Position of ADDHLD field.
	FMC_BWTR3_ADDHLD_Msk  = 0xf0       // Bit mask of ADDHLD field.
	FMC_BWTR3_ADDSET_Pos  = 0x0        // Position of ADDSET field.
	FMC_BWTR3_ADDSET_Msk  = 0xf        // Bit mask of ADDSET field.

	// BWTR4: SRAM/NOR-Flash write timing registers           4
	FMC_BWTR4_DATAHLD_Pos = 0x1e       // Position of DATAHLD field.
	FMC_BWTR4_DATAHLD_Msk = 0xc0000000 // Bit mask of DATAHLD field.
	FMC_BWTR4_ACCMOD_Pos  = 0x1c       // Position of ACCMOD field.
	FMC_BWTR4_ACCMOD_Msk  = 0x30000000 // Bit mask of ACCMOD field.
	FMC_BWTR4_BUSTURN_Pos = 0x10       // Position of BUSTURN field.
	FMC_BWTR4_BUSTURN_Msk = 0xf0000    // Bit mask of BUSTURN field.
	FMC_BWTR4_DATAST_Pos  = 0x8        // Position of DATAST field.
	FMC_BWTR4_DATAST_Msk  = 0xff00     // Bit mask of DATAST field.
	FMC_BWTR4_ADDHLD_Pos  = 0x4        // Position of ADDHLD field.
	FMC_BWTR4_ADDHLD_Msk  = 0xf0       // Bit mask of ADDHLD field.
	FMC_BWTR4_ADDSET_Pos  = 0x0        // Position of ADDSET field.
	FMC_BWTR4_ADDSET_Msk  = 0xf        // Bit mask of ADDSET field.
)

// Bitfields for DMA1: DMA controller
const (
	// ISR: interrupt status register
	DMA_ISR_TEIF8_Pos = 0x1f       // Position of TEIF8 field.
	DMA_ISR_TEIF8_Msk = 0x80000000 // Bit mask of TEIF8 field.
	DMA_ISR_TEIF8     = 0x80000000 // Bit TEIF8.
	DMA_ISR_HTIF8_Pos = 0x1e       // Position of HTIF8 field.
	DMA_ISR_HTIF8_Msk = 0x40000000 // Bit mask of HTIF8 field.
	DMA_ISR_HTIF8     = 0x40000000 // Bit HTIF8.
	DMA_ISR_TCIF8_Pos = 0x1d       // Position of TCIF8 field.
	DMA_ISR_TCIF8_Msk = 0x20000000 // Bit mask of TCIF8 field.
	DMA_ISR_TCIF8     = 0x20000000 // Bit TCIF8.
	DMA_ISR_GIF8_Pos  = 0x1c       // Position of GIF8 field.
	DMA_ISR_GIF8_Msk  = 0x10000000 // Bit mask of GIF8 field.
	DMA_ISR_GIF8      = 0x10000000 // Bit GIF8.
	DMA_ISR_TEIF7_Pos = 0x1b       // Position of TEIF7 field.
	DMA_ISR_TEIF7_Msk = 0x8000000  // Bit mask of TEIF7 field.
	DMA_ISR_TEIF7     = 0x8000000  // Bit TEIF7.
	DMA_ISR_HTIF7_Pos = 0x1a       // Position of HTIF7 field.
	DMA_ISR_HTIF7_Msk = 0x4000000  // Bit mask of HTIF7 field.
	DMA_ISR_HTIF7     = 0x4000000  // Bit HTIF7.
	DMA_ISR_TCIF7_Pos = 0x19       // Position of TCIF7 field.
	DMA_ISR_TCIF7_Msk = 0x2000000  // Bit mask of TCIF7 field.
	DMA_ISR_TCIF7     = 0x2000000  // Bit TCIF7.
	DMA_ISR_GIF7_Pos  = 0x18       // Position of GIF7 field.
	DMA_ISR_GIF7_Msk  = 0x1000000  // Bit mask of GIF7 field.
	DMA_ISR_GIF7      = 0x1000000  // Bit GIF7.
	DMA_ISR_TEIF6_Pos = 0x17       // Position of TEIF6 field.
	DMA_ISR_TEIF6_Msk = 0x800000   // Bit mask of TEIF6 field.
	DMA_ISR_TEIF6     = 0x800000   // Bit TEIF6.
	DMA_ISR_HTIF6_Pos = 0x16       // Position of HTIF6 field.
	DMA_ISR_HTIF6_Msk = 0x400000   // Bit mask of HTIF6 field.
	DMA_ISR_HTIF6     = 0x400000   // Bit HTIF6.
	DMA_ISR_TCIF6_Pos = 0x15       // Position of TCIF6 field.
	DMA_ISR_TCIF6_Msk = 0x200000   // Bit mask of TCIF6 field.
	DMA_ISR_TCIF6     = 0x200000   // Bit TCIF6.
	DMA_ISR_GIF6_Pos  = 0x14       // Position of GIF6 field.
	DMA_ISR_GIF6_Msk  = 0x100000   // Bit mask of GIF6 field.
	DMA_ISR_GIF6      = 0x100000   // Bit GIF6.
	DMA_ISR_TEIF5_Pos = 0x13       // Position of TEIF5 field.
	DMA_ISR_TEIF5_Msk = 0x80000    // Bit mask of TEIF5 field.
	DMA_ISR_TEIF5     = 0x80000    // Bit TEIF5.
	DMA_ISR_HTIF5_Pos = 0x12       // Position of HTIF5 field.
	DMA_ISR_HTIF5_Msk = 0x40000    // Bit mask of HTIF5 field.
	DMA_ISR_HTIF5     = 0x40000    // Bit HTIF5.
	DMA_ISR_TCIF5_Pos = 0x11       // Position of TCIF5 field.
	DMA_ISR_TCIF5_Msk = 0x20000    // Bit mask of TCIF5 field.
	DMA_ISR_TCIF5     = 0x20000    // Bit TCIF5.
	DMA_ISR_GIF5_Pos  = 0x10       // Position of GIF5 field.
	DMA_ISR_GIF5_Msk  = 0x10000    // Bit mask of GIF5 field.
	DMA_ISR_GIF5      = 0x10000    // Bit GIF5.
	DMA_ISR_TEIF4_Pos = 0xf        // Position of TEIF4 field.
	DMA_ISR_TEIF4_Msk = 0x8000     // Bit mask of TEIF4 field.
	DMA_ISR_TEIF4     = 0x8000     // Bit TEIF4.
	DMA_ISR_HTIF4_Pos = 0xe        // Position of HTIF4 field.
	DMA_ISR_HTIF4_Msk = 0x4000     // Bit mask of HTIF4 field.
	DMA_ISR_HTIF4     = 0x4000     // Bit HTIF4.
	DMA_ISR_TCIF4_Pos = 0xd        // Position of TCIF4 field.
	DMA_ISR_TCIF4_Msk = 0x2000     // Bit mask of TCIF4 field.
	DMA_ISR_TCIF4     = 0x2000     // Bit TCIF4.
	DMA_ISR_GIF4_Pos  = 0xc        // Position of GIF4 field.
	DMA_ISR_GIF4_Msk  = 0x1000     // Bit mask of GIF4 field.
	DMA_ISR_GIF4      = 0x1000     // Bit GIF4.
	DMA_ISR_TEIF3_Pos = 0xb        // Position of TEIF3 field.
	DMA_ISR_TEIF3_Msk = 0x800      // Bit mask of TEIF3 field.
	DMA_ISR_TEIF3     = 0x800      // Bit TEIF3.
	DMA_ISR_HTIF3_Pos = 0xa        // Position of HTIF3 field.
	DMA_ISR_HTIF3_Msk = 0x400      // Bit mask of HTIF3 field.
	DMA_ISR_HTIF3     = 0x400      // Bit HTIF3.
	DMA_ISR_TCIF3_Pos = 0x9        // Position of TCIF3 field.
	DMA_ISR_TCIF3_Msk = 0x200      // Bit mask of TCIF3 field.
	DMA_ISR_TCIF3     = 0x200      // Bit TCIF3.
	DMA_ISR_GIF3_Pos  = 0x8        // Position of GIF3 field.
	DMA_ISR_GIF3_Msk  = 0x100      // Bit mask of GIF3 field.
	DMA_ISR_GIF3      = 0x100      // Bit GIF3.
	DMA_ISR_TEIF2_Pos = 0x7        // Position of TEIF2 field.
	DMA_ISR_TEIF2_Msk = 0x80       // Bit mask of TEIF2 field.
	DMA_ISR_TEIF2     = 0x80       // Bit TEIF2.
	DMA_ISR_HTIF2_Pos = 0x6        // Position of HTIF2 field.
	DMA_ISR_HTIF2_Msk = 0x40       // Bit mask of HTIF2 field.
	DMA_ISR_HTIF2     = 0x40       // Bit HTIF2.
	DMA_ISR_TCIF2_Pos = 0x5        // Position of TCIF2 field.
	DMA_ISR_TCIF2_Msk = 0x20       // Bit mask of TCIF2 field.
	DMA_ISR_TCIF2     = 0x20       // Bit TCIF2.
	DMA_ISR_GIF2_Pos  = 0x4        // Position of GIF2 field.
	DMA_ISR_GIF2_Msk  = 0x10       // Bit mask of GIF2 field.
	DMA_ISR_GIF2      = 0x10       // Bit GIF2.
	DMA_ISR_TEIF1_Pos = 0x3        // Position of TEIF1 field.
	DMA_ISR_TEIF1_Msk = 0x8        // Bit mask of TEIF1 field.
	DMA_ISR_TEIF1     = 0x8        // Bit TEIF1.
	DMA_ISR_HTIF1_Pos = 0x2        // Position of HTIF1 field.
	DMA_ISR_HTIF1_Msk = 0x4        // Bit mask of HTIF1 field.
	DMA_ISR_HTIF1     = 0x4        // Bit HTIF1.
	DMA_ISR_TCIF1_Pos = 0x1        // Position of TCIF1 field.
	DMA_ISR_TCIF1_Msk = 0x2        // Bit mask of TCIF1 field.
	DMA_ISR_TCIF1     = 0x2        // Bit TCIF1.
	DMA_ISR_GIF1_Pos  = 0x0        // Position of GIF1 field.
	DMA_ISR_GIF1_Msk  = 0x1        // Bit mask of GIF1 field.
	DMA_ISR_GIF1      = 0x1        // Bit GIF1.

	// IFCR: DMA interrupt flag clear           register
	DMA_IFCR_TEIF8_Pos = 0x1f       // Position of TEIF8 field.
	DMA_IFCR_TEIF8_Msk = 0x80000000 // Bit mask of TEIF8 field.
	DMA_IFCR_TEIF8     = 0x80000000 // Bit TEIF8.
	DMA_IFCR_HTIF8_Pos = 0x1e       // Position of HTIF8 field.
	DMA_IFCR_HTIF8_Msk = 0x40000000 // Bit mask of HTIF8 field.
	DMA_IFCR_HTIF8     = 0x40000000 // Bit HTIF8.
	DMA_IFCR_TCIF8_Pos = 0x1d       // Position of TCIF8 field.
	DMA_IFCR_TCIF8_Msk = 0x20000000 // Bit mask of TCIF8 field.
	DMA_IFCR_TCIF8     = 0x20000000 // Bit TCIF8.
	DMA_IFCR_GIF8_Pos  = 0x1c       // Position of GIF8 field.
	DMA_IFCR_GIF8_Msk  = 0x10000000 // Bit mask of GIF8 field.
	DMA_IFCR_GIF8      = 0x10000000 // Bit GIF8.
	DMA_IFCR_TEIF7_Pos = 0x1b       // Position of TEIF7 field.
	DMA_IFCR_TEIF7_Msk = 0x8000000  // Bit mask of TEIF7 field.
	DMA_IFCR_TEIF7     = 0x8000000  // Bit TEIF7.
	DMA_IFCR_HTIF7_Pos = 0x1a       // Position of HTIF7 field.
	DMA_IFCR_HTIF7_Msk = 0x4000000  // Bit mask of HTIF7 field.
	DMA_IFCR_HTIF7     = 0x4000000  // Bit HTIF7.
	DMA_IFCR_TCIF7_Pos = 0x19       // Position of TCIF7 field.
	DMA_IFCR_TCIF7_Msk = 0x2000000  // Bit mask of TCIF7 field.
	DMA_IFCR_TCIF7     = 0x2000000  // Bit TCIF7.
	DMA_IFCR_GIF7_Pos  = 0x18       // Position of GIF7 field.
	DMA_IFCR_GIF7_Msk  = 0x1000000  // Bit mask of GIF7 field.
	DMA_IFCR_GIF7      = 0x1000000  // Bit GIF7.
	DMA_IFCR_TEIF6_Pos = 0x17       // Position of TEIF6 field.
	DMA_IFCR_TEIF6_Msk = 0x800000   // Bit mask of TEIF6 field.
	DMA_IFCR_TEIF6     = 0x800000   // Bit TEIF6.
	DMA_IFCR_HTIF6_Pos = 0x16       // Position of HTIF6 field.
	DMA_IFCR_HTIF6_Msk = 0x400000   // Bit mask of HTIF6 field.
	DMA_IFCR_HTIF6     = 0x400000   // Bit HTIF6.
	DMA_IFCR_TCIF6_Pos = 0x15       // Position of TCIF6 field.
	DMA_IFCR_TCIF6_Msk = 0x200000   // Bit mask of TCIF6 field.
	DMA_IFCR_TCIF6     = 0x200000   // Bit TCIF6.
	DMA_IFCR_GIF6_Pos  = 0x14       // Position of GIF6 field.
	DMA_IFCR_GIF6_Msk  = 0x100000   // Bit mask of GIF6 field.
	DMA_IFCR_GIF6      = 0x100000   // Bit GIF6.
	DMA_IFCR_TEIF5_Pos = 0x13       // Position of TEIF5 field.
	DMA_IFCR_TEIF5_Msk = 0x80000    // Bit mask of TEIF5 field.
	DMA_IFCR_TEIF5     = 0x80000    // Bit TEIF5.
	DMA_IFCR_HTIF5_Pos = 0x12       // Position of HTIF5 field.
	DMA_IFCR_HTIF5_Msk = 0x40000    // Bit mask of HTIF5 field.
	DMA_IFCR_HTIF5     = 0x40000    // Bit HTIF5.
	DMA_IFCR_TCIF5_Pos = 0x11       // Position of TCIF5 field.
	DMA_IFCR_TCIF5_Msk = 0x20000    // Bit mask of TCIF5 field.
	DMA_IFCR_TCIF5     = 0x20000    // Bit TCIF5.
	DMA_IFCR_GIF5_Pos  = 0x10       // Position of GIF5 field.
	DMA_IFCR_GIF5_Msk  = 0x10000    // Bit mask of GIF5 field.
	DMA_IFCR_GIF5      = 0x10000    // Bit GIF5.
	DMA_IFCR_TEIF4_Pos = 0xf        // Position of TEIF4 field.
	DMA_IFCR_TEIF4_Msk = 0x8000     // Bit mask of TEIF4 field.
	DMA_IFCR_TEIF4     = 0x8000     // Bit TEIF4.
	DMA_IFCR_HTIF4_Pos = 0xe        // Position of HTIF4 field.
	DMA_IFCR_HTIF4_Msk = 0x4000     // Bit mask of HTIF4 field.
	DMA_IFCR_HTIF4     = 0x4000     // Bit HTIF4.
	DMA_IFCR_TCIF4_Pos = 0xd        // Position of TCIF4 field.
	DMA_IFCR_TCIF4_Msk = 0x2000     // Bit mask of TCIF4 field.
	DMA_IFCR_TCIF4     = 0x2000     // Bit TCIF4.
	DMA_IFCR_GIF4_Pos  = 0xc        // Position of GIF4 field.
	DMA_IFCR_GIF4_Msk  = 0x1000     // Bit mask of GIF4 field.
	DMA_IFCR_GIF4      = 0x1000     // Bit GIF4.
	DMA_IFCR_TEIF3_Pos = 0xb        // Position of TEIF3 field.
	DMA_IFCR_TEIF3_Msk = 0x800      // Bit mask of TEIF3 field.
	DMA_IFCR_TEIF3     = 0x800      // Bit TEIF3.
	DMA_IFCR_HTIF3_Pos = 0xa        // Position of HTIF3 field.
	DMA_IFCR_HTIF3_Msk = 0x400      // Bit mask of HTIF3 field.
	DMA_IFCR_HTIF3     = 0x400      // Bit HTIF3.
	DMA_IFCR_TCIF3_Pos = 0x9        // Position of TCIF3 field.
	DMA_IFCR_TCIF3_Msk = 0x200      // Bit mask of TCIF3 field.
	DMA_IFCR_TCIF3     = 0x200      // Bit TCIF3.
	DMA_IFCR_GIF3_Pos  = 0x8        // Position of GIF3 field.
	DMA_IFCR_GIF3_Msk  = 0x100      // Bit mask of GIF3 field.
	DMA_IFCR_GIF3      = 0x100      // Bit GIF3.
	DMA_IFCR_TEIF2_Pos = 0x7        // Position of TEIF2 field.
	DMA_IFCR_TEIF2_Msk = 0x80       // Bit mask of TEIF2 field.
	DMA_IFCR_TEIF2     = 0x80       // Bit TEIF2.
	DMA_IFCR_HTIF2_Pos = 0x6        // Position of HTIF2 field.
	DMA_IFCR_HTIF2_Msk = 0x40       // Bit mask of HTIF2 field.
	DMA_IFCR_HTIF2     = 0x40       // Bit HTIF2.
	DMA_IFCR_TCIF2_Pos = 0x5        // Position of TCIF2 field.
	DMA_IFCR_TCIF2_Msk = 0x20       // Bit mask of TCIF2 field.
	DMA_IFCR_TCIF2     = 0x20       // Bit TCIF2.
	DMA_IFCR_GIF2_Pos  = 0x4        // Position of GIF2 field.
	DMA_IFCR_GIF2_Msk  = 0x10       // Bit mask of GIF2 field.
	DMA_IFCR_GIF2      = 0x10       // Bit GIF2.
	DMA_IFCR_TEIF1_Pos = 0x3        // Position of TEIF1 field.
	DMA_IFCR_TEIF1_Msk = 0x8        // Bit mask of TEIF1 field.
	DMA_IFCR_TEIF1     = 0x8        // Bit TEIF1.
	DMA_IFCR_HTIF1_Pos = 0x2        // Position of HTIF1 field.
	DMA_IFCR_HTIF1_Msk = 0x4        // Bit mask of HTIF1 field.
	DMA_IFCR_HTIF1     = 0x4        // Bit HTIF1.
	DMA_IFCR_TCIF1_Pos = 0x1        // Position of TCIF1 field.
	DMA_IFCR_TCIF1_Msk = 0x2        // Bit mask of TCIF1 field.
	DMA_IFCR_TCIF1     = 0x2        // Bit TCIF1.
	DMA_IFCR_GIF1_Pos  = 0x0        // Position of GIF1 field.
	DMA_IFCR_GIF1_Msk  = 0x1        // Bit mask of GIF1 field.
	DMA_IFCR_GIF1      = 0x1        // Bit GIF1.

	// CCR1: DMA channel 1 configuration           register
	DMA_CCR1_EN_Pos      = 0x0    // Position of EN field.
	DMA_CCR1_EN_Msk      = 0x1    // Bit mask of EN field.
	DMA_CCR1_EN          = 0x1    // Bit EN.
	DMA_CCR1_TCIE_Pos    = 0x1    // Position of TCIE field.
	DMA_CCR1_TCIE_Msk    = 0x2    // Bit mask of TCIE field.
	DMA_CCR1_TCIE        = 0x2    // Bit TCIE.
	DMA_CCR1_HTIE_Pos    = 0x2    // Position of HTIE field.
	DMA_CCR1_HTIE_Msk    = 0x4    // Bit mask of HTIE field.
	DMA_CCR1_HTIE        = 0x4    // Bit HTIE.
	DMA_CCR1_TEIE_Pos    = 0x3    // Position of TEIE field.
	DMA_CCR1_TEIE_Msk    = 0x8    // Bit mask of TEIE field.
	DMA_CCR1_TEIE        = 0x8    // Bit TEIE.
	DMA_CCR1_DIR_Pos     = 0x4    // Position of DIR field.
	DMA_CCR1_DIR_Msk     = 0x10   // Bit mask of DIR field.
	DMA_CCR1_DIR         = 0x10   // Bit DIR.
	DMA_CCR1_CIRC_Pos    = 0x5    // Position of CIRC field.
	DMA_CCR1_CIRC_Msk    = 0x20   // Bit mask of CIRC field.
	DMA_CCR1_CIRC        = 0x20   // Bit CIRC.
	DMA_CCR1_PINC_Pos    = 0x6    // Position of PINC field.
	DMA_CCR1_PINC_Msk    = 0x40   // Bit mask of PINC field.
	DMA_CCR1_PINC        = 0x40   // Bit PINC.
	DMA_CCR1_MINC_Pos    = 0x7    // Position of MINC field.
	DMA_CCR1_MINC_Msk    = 0x80   // Bit mask of MINC field.
	DMA_CCR1_MINC        = 0x80   // Bit MINC.
	DMA_CCR1_PSIZE_Pos   = 0x8    // Position of PSIZE field.
	DMA_CCR1_PSIZE_Msk   = 0x300  // Bit mask of PSIZE field.
	DMA_CCR1_MSIZE_Pos   = 0xa    // Position of MSIZE field.
	DMA_CCR1_MSIZE_Msk   = 0xc00  // Bit mask of MSIZE field.
	DMA_CCR1_PL_Pos      = 0xc    // Position of PL field.
	DMA_CCR1_PL_Msk      = 0x3000 // Bit mask of PL field.
	DMA_CCR1_MEM2MEM_Pos = 0xe    // Position of MEM2MEM field.
	DMA_CCR1_MEM2MEM_Msk = 0x4000 // Bit mask of MEM2MEM field.
	DMA_CCR1_MEM2MEM     = 0x4000 // Bit MEM2MEM.

	// CNDTR1: channel x number of data to transfer           register
	DMA_CNDTR1_NDT_Pos = 0x0    // Position of NDT field.
	DMA_CNDTR1_NDT_Msk = 0xffff // Bit mask of NDT field.

	// CPAR1: DMA channel x peripheral address           register
	DMA_CPAR1_PA_Pos = 0x0        // Position of PA field.
	DMA_CPAR1_PA_Msk = 0xffffffff // Bit mask of PA field.

	// CMAR1: DMA channel x memory address           register
	DMA_CMAR1_MA_Pos = 0x0        // Position of MA field.
	DMA_CMAR1_MA_Msk = 0xffffffff // Bit mask of MA field.

	// CCR2: DMA channel 2 configuration           register
	DMA_CCR2_EN_Pos      = 0x0    // Position of EN field.
	DMA_CCR2_EN_Msk      = 0x1    // Bit mask of EN field.
	DMA_CCR2_EN          = 0x1    // Bit EN.
	DMA_CCR2_TCIE_Pos    = 0x1    // Position of TCIE field.
	DMA_CCR2_TCIE_Msk    = 0x2    // Bit mask of TCIE field.
	DMA_CCR2_TCIE        = 0x2    // Bit TCIE.
	DMA_CCR2_HTIE_Pos    = 0x2    // Position of HTIE field.
	DMA_CCR2_HTIE_Msk    = 0x4    // Bit mask of HTIE field.
	DMA_CCR2_HTIE        = 0x4    // Bit HTIE.
	DMA_CCR2_TEIE_Pos    = 0x3    // Position of TEIE field.
	DMA_CCR2_TEIE_Msk    = 0x8    // Bit mask of TEIE field.
	DMA_CCR2_TEIE        = 0x8    // Bit TEIE.
	DMA_CCR2_DIR_Pos     = 0x4    // Position of DIR field.
	DMA_CCR2_DIR_Msk     = 0x10   // Bit mask of DIR field.
	DMA_CCR2_DIR         = 0x10   // Bit DIR.
	DMA_CCR2_CIRC_Pos    = 0x5    // Position of CIRC field.
	DMA_CCR2_CIRC_Msk    = 0x20   // Bit mask of CIRC field.
	DMA_CCR2_CIRC        = 0x20   // Bit CIRC.
	DMA_CCR2_PINC_Pos    = 0x6    // Position of PINC field.
	DMA_CCR2_PINC_Msk    = 0x40   // Bit mask of PINC field.
	DMA_CCR2_PINC        = 0x40   // Bit PINC.
	DMA_CCR2_MINC_Pos    = 0x7    // Position of MINC field.
	DMA_CCR2_MINC_Msk    = 0x80   // Bit mask of MINC field.
	DMA_CCR2_MINC        = 0x80   // Bit MINC.
	DMA_CCR2_PSIZE_Pos   = 0x8    // Position of PSIZE field.
	DMA_CCR2_PSIZE_Msk   = 0x300  // Bit mask of PSIZE field.
	DMA_CCR2_MSIZE_Pos   = 0xa    // Position of MSIZE field.
	DMA_CCR2_MSIZE_Msk   = 0xc00  // Bit mask of MSIZE field.
	DMA_CCR2_PL_Pos      = 0xc    // Position of PL field.
	DMA_CCR2_PL_Msk      = 0x3000 // Bit mask of PL field.
	DMA_CCR2_MEM2MEM_Pos = 0xe    // Position of MEM2MEM field.
	DMA_CCR2_MEM2MEM_Msk = 0x4000 // Bit mask of MEM2MEM field.
	DMA_CCR2_MEM2MEM     = 0x4000 // Bit MEM2MEM.

	// CNDTR2: channel x number of data to transfer           register
	DMA_CNDTR2_NDT_Pos = 0x0    // Position of NDT field.
	DMA_CNDTR2_NDT_Msk = 0xffff // Bit mask of NDT field.

	// CPAR2: DMA channel x peripheral address           register
	DMA_CPAR2_PA_Pos = 0x0        // Position of PA field.
	DMA_CPAR2_PA_Msk = 0xffffffff // Bit mask of PA field.

	// CMAR2: DMA channel x memory address           register
	DMA_CMAR2_MA_Pos = 0x0        // Position of MA field.
	DMA_CMAR2_MA_Msk = 0xffffffff // Bit mask of MA field.

	// CCR3: DMA channel 3 configuration           register
	DMA_CCR3_EN_Pos      = 0x0    // Position of EN field.
	DMA_CCR3_EN_Msk      = 0x1    // Bit mask of EN field.
	DMA_CCR3_EN          = 0x1    // Bit EN.
	DMA_CCR3_TCIE_Pos    = 0x1    // Position of TCIE field.
	DMA_CCR3_TCIE_Msk    = 0x2    // Bit mask of TCIE field.
	DMA_CCR3_TCIE        = 0x2    // Bit TCIE.
	DMA_CCR3_HTIE_Pos    = 0x2    // Position of HTIE field.
	DMA_CCR3_HTIE_Msk    = 0x4    // Bit mask of HTIE field.
	DMA_CCR3_HTIE        = 0x4    // Bit HTIE.
	DMA_CCR3_TEIE_Pos    = 0x3    // Position of TEIE field.
	DMA_CCR3_TEIE_Msk    = 0x8    // Bit mask of TEIE field.
	DMA_CCR3_TEIE        = 0x8    // Bit TEIE.
	DMA_CCR3_DIR_Pos     = 0x4    // Position of DIR field.
	DMA_CCR3_DIR_Msk     = 0x10   // Bit mask of DIR field.
	DMA_CCR3_DIR         = 0x10   // Bit DIR.
	DMA_CCR3_CIRC_Pos    = 0x5    // Position of CIRC field.
	DMA_CCR3_CIRC_Msk    = 0x20   // Bit mask of CIRC field.
	DMA_CCR3_CIRC        = 0x20   // Bit CIRC.
	DMA_CCR3_PINC_Pos    = 0x6    // Position of PINC field.
	DMA_CCR3_PINC_Msk    = 0x40   // Bit mask of PINC field.
	DMA_CCR3_PINC        = 0x40   // Bit PINC.
	DMA_CCR3_MINC_Pos    = 0x7    // Position of MINC field.
	DMA_CCR3_MINC_Msk    = 0x80   // Bit mask of MINC field.
	DMA_CCR3_MINC        = 0x80   // Bit MINC.
	DMA_CCR3_PSIZE_Pos   = 0x8    // Position of PSIZE field.
	DMA_CCR3_PSIZE_Msk   = 0x300  // Bit mask of PSIZE field.
	DMA_CCR3_MSIZE_Pos   = 0xa    // Position of MSIZE field.
	DMA_CCR3_MSIZE_Msk   = 0xc00  // Bit mask of MSIZE field.
	DMA_CCR3_PL_Pos      = 0xc    // Position of PL field.
	DMA_CCR3_PL_Msk      = 0x3000 // Bit mask of PL field.
	DMA_CCR3_MEM2MEM_Pos = 0xe    // Position of MEM2MEM field.
	DMA_CCR3_MEM2MEM_Msk = 0x4000 // Bit mask of MEM2MEM field.
	DMA_CCR3_MEM2MEM     = 0x4000 // Bit MEM2MEM.

	// CNDTR3: channel x number of data to transfer           register
	DMA_CNDTR3_NDT_Pos = 0x0    // Position of NDT field.
	DMA_CNDTR3_NDT_Msk = 0xffff // Bit mask of NDT field.

	// CPAR3: DMA channel x peripheral address           register
	DMA_CPAR3_PA_Pos = 0x0        // Position of PA field.
	DMA_CPAR3_PA_Msk = 0xffffffff // Bit mask of PA field.

	// CMAR3: DMA channel x memory address           register
	DMA_CMAR3_MA_Pos = 0x0        // Position of MA field.
	DMA_CMAR3_MA_Msk = 0xffffffff // Bit mask of MA field.

	// CCR4: DMA channel 3 configuration           register
	DMA_CCR4_EN_Pos      = 0x0    // Position of EN field.
	DMA_CCR4_EN_Msk      = 0x1    // Bit mask of EN field.
	DMA_CCR4_EN          = 0x1    // Bit EN.
	DMA_CCR4_TCIE_Pos    = 0x1    // Position of TCIE field.
	DMA_CCR4_TCIE_Msk    = 0x2    // Bit mask of TCIE field.
	DMA_CCR4_TCIE        = 0x2    // Bit TCIE.
	DMA_CCR4_HTIE_Pos    = 0x2    // Position of HTIE field.
	DMA_CCR4_HTIE_Msk    = 0x4    // Bit mask of HTIE field.
	DMA_CCR4_HTIE        = 0x4    // Bit HTIE.
	DMA_CCR4_TEIE_Pos    = 0x3    // Position of TEIE field.
	DMA_CCR4_TEIE_Msk    = 0x8    // Bit mask of TEIE field.
	DMA_CCR4_TEIE        = 0x8    // Bit TEIE.
	DMA_CCR4_DIR_Pos     = 0x4    // Position of DIR field.
	DMA_CCR4_DIR_Msk     = 0x10   // Bit mask of DIR field.
	DMA_CCR4_DIR         = 0x10   // Bit DIR.
	DMA_CCR4_CIRC_Pos    = 0x5    // Position of CIRC field.
	DMA_CCR4_CIRC_Msk    = 0x20   // Bit mask of CIRC field.
	DMA_CCR4_CIRC        = 0x20   // Bit CIRC.
	DMA_CCR4_PINC_Pos    = 0x6    // Position of PINC field.
	DMA_CCR4_PINC_Msk    = 0x40   // Bit mask of PINC field.
	DMA_CCR4_PINC        = 0x40   // Bit PINC.
	DMA_CCR4_MINC_Pos    = 0x7    // Position of MINC field.
	DMA_CCR4_MINC_Msk    = 0x80   // Bit mask of MINC field.
	DMA_CCR4_MINC        = 0x80   // Bit MINC.
	DMA_CCR4_PSIZE_Pos   = 0x8    // Position of PSIZE field.
	DMA_CCR4_PSIZE_Msk   = 0x300  // Bit mask of PSIZE field.
	DMA_CCR4_MSIZE_Pos   = 0xa    // Position of MSIZE field.
	DMA_CCR4_MSIZE_Msk   = 0xc00  // Bit mask of MSIZE field.
	DMA_CCR4_PL_Pos      = 0xc    // Position of PL field.
	DMA_CCR4_PL_Msk      = 0x3000 // Bit mask of PL field.
	DMA_CCR4_MEM2MEM_Pos = 0xe    // Position of MEM2MEM field.
	DMA_CCR4_MEM2MEM_Msk = 0x4000 // Bit mask of MEM2MEM field.
	DMA_CCR4_MEM2MEM     = 0x4000 // Bit MEM2MEM.

	// CNDTR4: channel x number of data to transfer           register
	DMA_CNDTR4_NDT_Pos = 0x0    // Position of NDT field.
	DMA_CNDTR4_NDT_Msk = 0xffff // Bit mask of NDT field.

	// CPAR4: DMA channel x peripheral address           register
	DMA_CPAR4_PA_Pos = 0x0        // Position of PA field.
	DMA_CPAR4_PA_Msk = 0xffffffff // Bit mask of PA field.

	// CMAR4: DMA channel x memory address           register
	DMA_CMAR4_MA_Pos = 0x0        // Position of MA field.
	DMA_CMAR4_MA_Msk = 0xffffffff // Bit mask of MA field.

	// CCR5: DMA channel 4 configuration           register
	DMA_CCR5_EN_Pos      = 0x0    // Position of EN field.
	DMA_CCR5_EN_Msk      = 0x1    // Bit mask of EN field.
	DMA_CCR5_EN          = 0x1    // Bit EN.
	DMA_CCR5_TCIE_Pos    = 0x1    // Position of TCIE field.
	DMA_CCR5_TCIE_Msk    = 0x2    // Bit mask of TCIE field.
	DMA_CCR5_TCIE        = 0x2    // Bit TCIE.
	DMA_CCR5_HTIE_Pos    = 0x2    // Position of HTIE field.
	DMA_CCR5_HTIE_Msk    = 0x4    // Bit mask of HTIE field.
	DMA_CCR5_HTIE        = 0x4    // Bit HTIE.
	DMA_CCR5_TEIE_Pos    = 0x3    // Position of TEIE field.
	DMA_CCR5_TEIE_Msk    = 0x8    // Bit mask of TEIE field.
	DMA_CCR5_TEIE        = 0x8    // Bit TEIE.
	DMA_CCR5_DIR_Pos     = 0x4    // Position of DIR field.
	DMA_CCR5_DIR_Msk     = 0x10   // Bit mask of DIR field.
	DMA_CCR5_DIR         = 0x10   // Bit DIR.
	DMA_CCR5_CIRC_Pos    = 0x5    // Position of CIRC field.
	DMA_CCR5_CIRC_Msk    = 0x20   // Bit mask of CIRC field.
	DMA_CCR5_CIRC        = 0x20   // Bit CIRC.
	DMA_CCR5_PINC_Pos    = 0x6    // Position of PINC field.
	DMA_CCR5_PINC_Msk    = 0x40   // Bit mask of PINC field.
	DMA_CCR5_PINC        = 0x40   // Bit PINC.
	DMA_CCR5_MINC_Pos    = 0x7    // Position of MINC field.
	DMA_CCR5_MINC_Msk    = 0x80   // Bit mask of MINC field.
	DMA_CCR5_MINC        = 0x80   // Bit MINC.
	DMA_CCR5_PSIZE_Pos   = 0x8    // Position of PSIZE field.
	DMA_CCR5_PSIZE_Msk   = 0x300  // Bit mask of PSIZE field.
	DMA_CCR5_MSIZE_Pos   = 0xa    // Position of MSIZE field.
	DMA_CCR5_MSIZE_Msk   = 0xc00  // Bit mask of MSIZE field.
	DMA_CCR5_PL_Pos      = 0xc    // Position of PL field.
	DMA_CCR5_PL_Msk      = 0x3000 // Bit mask of PL field.
	DMA_CCR5_MEM2MEM_Pos = 0xe    // Position of MEM2MEM field.
	DMA_CCR5_MEM2MEM_Msk = 0x4000 // Bit mask of MEM2MEM field.
	DMA_CCR5_MEM2MEM     = 0x4000 // Bit MEM2MEM.

	// CNDTR5: channel x number of data to transfer           register
	DMA_CNDTR5_NDT_Pos = 0x0    // Position of NDT field.
	DMA_CNDTR5_NDT_Msk = 0xffff // Bit mask of NDT field.

	// CPAR5: DMA channel x peripheral address           register
	DMA_CPAR5_PA_Pos = 0x0        // Position of PA field.
	DMA_CPAR5_PA_Msk = 0xffffffff // Bit mask of PA field.

	// CMAR5: DMA channel x memory address           register
	DMA_CMAR5_MA_Pos = 0x0        // Position of MA field.
	DMA_CMAR5_MA_Msk = 0xffffffff // Bit mask of MA field.

	// CCR6: DMA channel 5 configuration           register
	DMA_CCR6_EN_Pos      = 0x0    // Position of EN field.
	DMA_CCR6_EN_Msk      = 0x1    // Bit mask of EN field.
	DMA_CCR6_EN          = 0x1    // Bit EN.
	DMA_CCR6_TCIE_Pos    = 0x1    // Position of TCIE field.
	DMA_CCR6_TCIE_Msk    = 0x2    // Bit mask of TCIE field.
	DMA_CCR6_TCIE        = 0x2    // Bit TCIE.
	DMA_CCR6_HTIE_Pos    = 0x2    // Position of HTIE field.
	DMA_CCR6_HTIE_Msk    = 0x4    // Bit mask of HTIE field.
	DMA_CCR6_HTIE        = 0x4    // Bit HTIE.
	DMA_CCR6_TEIE_Pos    = 0x3    // Position of TEIE field.
	DMA_CCR6_TEIE_Msk    = 0x8    // Bit mask of TEIE field.
	DMA_CCR6_TEIE        = 0x8    // Bit TEIE.
	DMA_CCR6_DIR_Pos     = 0x4    // Position of DIR field.
	DMA_CCR6_DIR_Msk     = 0x10   // Bit mask of DIR field.
	DMA_CCR6_DIR         = 0x10   // Bit DIR.
	DMA_CCR6_CIRC_Pos    = 0x5    // Position of CIRC field.
	DMA_CCR6_CIRC_Msk    = 0x20   // Bit mask of CIRC field.
	DMA_CCR6_CIRC        = 0x20   // Bit CIRC.
	DMA_CCR6_PINC_Pos    = 0x6    // Position of PINC field.
	DMA_CCR6_PINC_Msk    = 0x40   // Bit mask of PINC field.
	DMA_CCR6_PINC        = 0x40   // Bit PINC.
	DMA_CCR6_MINC_Pos    = 0x7    // Position of MINC field.
	DMA_CCR6_MINC_Msk    = 0x80   // Bit mask of MINC field.
	DMA_CCR6_MINC        = 0x80   // Bit MINC.
	DMA_CCR6_PSIZE_Pos   = 0x8    // Position of PSIZE field.
	DMA_CCR6_PSIZE_Msk   = 0x300  // Bit mask of PSIZE field.
	DMA_CCR6_MSIZE_Pos   = 0xa    // Position of MSIZE field.
	DMA_CCR6_MSIZE_Msk   = 0xc00  // Bit mask of MSIZE field.
	DMA_CCR6_PL_Pos      = 0xc    // Position of PL field.
	DMA_CCR6_PL_Msk      = 0x3000 // Bit mask of PL field.
	DMA_CCR6_MEM2MEM_Pos = 0xe    // Position of MEM2MEM field.
	DMA_CCR6_MEM2MEM_Msk = 0x4000 // Bit mask of MEM2MEM field.
	DMA_CCR6_MEM2MEM     = 0x4000 // Bit MEM2MEM.

	// CNDTR6: channel x number of data to transfer           register
	DMA_CNDTR6_NDT_Pos = 0x0    // Position of NDT field.
	DMA_CNDTR6_NDT_Msk = 0xffff // Bit mask of NDT field.

	// CPAR6: DMA channel x peripheral address           register
	DMA_CPAR6_PA_Pos = 0x0        // Position of PA field.
	DMA_CPAR6_PA_Msk = 0xffffffff // Bit mask of PA field.

	// CMAR6: DMA channel x memory address           register
	DMA_CMAR6_MA_Pos = 0x0        // Position of MA field.
	DMA_CMAR6_MA_Msk = 0xffffffff // Bit mask of MA field.

	// CCR7: DMA channel 6 configuration           register
	DMA_CCR7_EN_Pos      = 0x0    // Position of EN field.
	DMA_CCR7_EN_Msk      = 0x1    // Bit mask of EN field.
	DMA_CCR7_EN          = 0x1    // Bit EN.
	DMA_CCR7_TCIE_Pos    = 0x1    // Position of TCIE field.
	DMA_CCR7_TCIE_Msk    = 0x2    // Bit mask of TCIE field.
	DMA_CCR7_TCIE        = 0x2    // Bit TCIE.
	DMA_CCR7_HTIE_Pos    = 0x2    // Position of HTIE field.
	DMA_CCR7_HTIE_Msk    = 0x4    // Bit mask of HTIE field.
	DMA_CCR7_HTIE        = 0x4    // Bit HTIE.
	DMA_CCR7_TEIE_Pos    = 0x3    // Position of TEIE field.
	DMA_CCR7_TEIE_Msk    = 0x8    // Bit mask of TEIE field.
	DMA_CCR7_TEIE        = 0x8    // Bit TEIE.
	DMA_CCR7_DIR_Pos     = 0x4    // Position of DIR field.
	DMA_CCR7_DIR_Msk     = 0x10   // Bit mask of DIR field.
	DMA_CCR7_DIR         = 0x10   // Bit DIR.
	DMA_CCR7_CIRC_Pos    = 0x5    // Position of CIRC field.
	DMA_CCR7_CIRC_Msk    = 0x20   // Bit mask of CIRC field.
	DMA_CCR7_CIRC        = 0x20   // Bit CIRC.
	DMA_CCR7_PINC_Pos    = 0x6    // Position of PINC field.
	DMA_CCR7_PINC_Msk    = 0x40   // Bit mask of PINC field.
	DMA_CCR7_PINC        = 0x40   // Bit PINC.
	DMA_CCR7_MINC_Pos    = 0x7    // Position of MINC field.
	DMA_CCR7_MINC_Msk    = 0x80   // Bit mask of MINC field.
	DMA_CCR7_MINC        = 0x80   // Bit MINC.
	DMA_CCR7_PSIZE_Pos   = 0x8    // Position of PSIZE field.
	DMA_CCR7_PSIZE_Msk   = 0x300  // Bit mask of PSIZE field.
	DMA_CCR7_MSIZE_Pos   = 0xa    // Position of MSIZE field.
	DMA_CCR7_MSIZE_Msk   = 0xc00  // Bit mask of MSIZE field.
	DMA_CCR7_PL_Pos      = 0xc    // Position of PL field.
	DMA_CCR7_PL_Msk      = 0x3000 // Bit mask of PL field.
	DMA_CCR7_MEM2MEM_Pos = 0xe    // Position of MEM2MEM field.
	DMA_CCR7_MEM2MEM_Msk = 0x4000 // Bit mask of MEM2MEM field.
	DMA_CCR7_MEM2MEM     = 0x4000 // Bit MEM2MEM.

	// CNDTR7: channel x number of data to transfer           register
	DMA_CNDTR7_NDT_Pos = 0x0    // Position of NDT field.
	DMA_CNDTR7_NDT_Msk = 0xffff // Bit mask of NDT field.

	// CPAR7: DMA channel x peripheral address           register
	DMA_CPAR7_PA_Pos = 0x0        // Position of PA field.
	DMA_CPAR7_PA_Msk = 0xffffffff // Bit mask of PA field.

	// CMAR7: DMA channel x memory address           register
	DMA_CMAR7_MA_Pos = 0x0        // Position of MA field.
	DMA_CMAR7_MA_Msk = 0xffffffff // Bit mask of MA field.

	// CCR8: DMA channel 7 configuration           register
	DMA_CCR8_EN_Pos      = 0x0    // Position of EN field.
	DMA_CCR8_EN_Msk      = 0x1    // Bit mask of EN field.
	DMA_CCR8_EN          = 0x1    // Bit EN.
	DMA_CCR8_TCIE_Pos    = 0x1    // Position of TCIE field.
	DMA_CCR8_TCIE_Msk    = 0x2    // Bit mask of TCIE field.
	DMA_CCR8_TCIE        = 0x2    // Bit TCIE.
	DMA_CCR8_HTIE_Pos    = 0x2    // Position of HTIE field.
	DMA_CCR8_HTIE_Msk    = 0x4    // Bit mask of HTIE field.
	DMA_CCR8_HTIE        = 0x4    // Bit HTIE.
	DMA_CCR8_TEIE_Pos    = 0x3    // Position of TEIE field.
	DMA_CCR8_TEIE_Msk    = 0x8    // Bit mask of TEIE field.
	DMA_CCR8_TEIE        = 0x8    // Bit TEIE.
	DMA_CCR8_DIR_Pos     = 0x4    // Position of DIR field.
	DMA_CCR8_DIR_Msk     = 0x10   // Bit mask of DIR field.
	DMA_CCR8_DIR         = 0x10   // Bit DIR.
	DMA_CCR8_CIRC_Pos    = 0x5    // Position of CIRC field.
	DMA_CCR8_CIRC_Msk    = 0x20   // Bit mask of CIRC field.
	DMA_CCR8_CIRC        = 0x20   // Bit CIRC.
	DMA_CCR8_PINC_Pos    = 0x6    // Position of PINC field.
	DMA_CCR8_PINC_Msk    = 0x40   // Bit mask of PINC field.
	DMA_CCR8_PINC        = 0x40   // Bit PINC.
	DMA_CCR8_MINC_Pos    = 0x7    // Position of MINC field.
	DMA_CCR8_MINC_Msk    = 0x80   // Bit mask of MINC field.
	DMA_CCR8_MINC        = 0x80   // Bit MINC.
	DMA_CCR8_PSIZE_Pos   = 0x8    // Position of PSIZE field.
	DMA_CCR8_PSIZE_Msk   = 0x300  // Bit mask of PSIZE field.
	DMA_CCR8_MSIZE_Pos   = 0xa    // Position of MSIZE field.
	DMA_CCR8_MSIZE_Msk   = 0xc00  // Bit mask of MSIZE field.
	DMA_CCR8_PL_Pos      = 0xc    // Position of PL field.
	DMA_CCR8_PL_Msk      = 0x3000 // Bit mask of PL field.
	DMA_CCR8_MEM2MEM_Pos = 0xe    // Position of MEM2MEM field.
	DMA_CCR8_MEM2MEM_Msk = 0x4000 // Bit mask of MEM2MEM field.
	DMA_CCR8_MEM2MEM     = 0x4000 // Bit MEM2MEM.

	// CNDTR8: channel x number of data to transfer           register
	DMA_CNDTR8_NDT_Pos = 0x0    // Position of NDT field.
	DMA_CNDTR8_NDT_Msk = 0xffff // Bit mask of NDT field.

	// CPAR8: DMA channel x peripheral address           register
	DMA_CPAR8_PA_Pos = 0x0        // Position of PA field.
	DMA_CPAR8_PA_Msk = 0xffffffff // Bit mask of PA field.

	// CMAR8: DMA channel x memory address           register
	DMA_CMAR8_MA_Pos = 0x0        // Position of MA field.
	DMA_CMAR8_MA_Msk = 0xffffffff // Bit mask of MA field.
)

// Bitfields for DMAMUX: DMAMUX
const (
	// C0CR: DMAMux - DMA request line multiplexer           channel x control register
	DMAMUX_C0CR_DMAREQ_ID_Pos = 0x0        // Position of DMAREQ_ID field.
	DMAMUX_C0CR_DMAREQ_ID_Msk = 0x7f       // Bit mask of DMAREQ_ID field.
	DMAMUX_C0CR_SOIE_Pos      = 0x8        // Position of SOIE field.
	DMAMUX_C0CR_SOIE_Msk      = 0x100      // Bit mask of SOIE field.
	DMAMUX_C0CR_SOIE          = 0x100      // Bit SOIE.
	DMAMUX_C0CR_EGE_Pos       = 0x9        // Position of EGE field.
	DMAMUX_C0CR_EGE_Msk       = 0x200      // Bit mask of EGE field.
	DMAMUX_C0CR_EGE           = 0x200      // Bit EGE.
	DMAMUX_C0CR_SE_Pos        = 0x10       // Position of SE field.
	DMAMUX_C0CR_SE_Msk        = 0x10000    // Bit mask of SE field.
	DMAMUX_C0CR_SE            = 0x10000    // Bit SE.
	DMAMUX_C0CR_SPOL_Pos      = 0x11       // Position of SPOL field.
	DMAMUX_C0CR_SPOL_Msk      = 0x60000    // Bit mask of SPOL field.
	DMAMUX_C0CR_NBREQ_Pos     = 0x13       // Position of NBREQ field.
	DMAMUX_C0CR_NBREQ_Msk     = 0xf80000   // Bit mask of NBREQ field.
	DMAMUX_C0CR_SYNC_ID_Pos   = 0x18       // Position of SYNC_ID field.
	DMAMUX_C0CR_SYNC_ID_Msk   = 0x1f000000 // Bit mask of SYNC_ID field.

	// C1CR: DMAMux - DMA request line multiplexer           channel x control register
	DMAMUX_C1CR_DMAREQ_ID_Pos = 0x0        // Position of DMAREQ_ID field.
	DMAMUX_C1CR_DMAREQ_ID_Msk = 0x7f       // Bit mask of DMAREQ_ID field.
	DMAMUX_C1CR_SOIE_Pos      = 0x8        // Position of SOIE field.
	DMAMUX_C1CR_SOIE_Msk      = 0x100      // Bit mask of SOIE field.
	DMAMUX_C1CR_SOIE          = 0x100      // Bit SOIE.
	DMAMUX_C1CR_EGE_Pos       = 0x9        // Position of EGE field.
	DMAMUX_C1CR_EGE_Msk       = 0x200      // Bit mask of EGE field.
	DMAMUX_C1CR_EGE           = 0x200      // Bit EGE.
	DMAMUX_C1CR_SE_Pos        = 0x10       // Position of SE field.
	DMAMUX_C1CR_SE_Msk        = 0x10000    // Bit mask of SE field.
	DMAMUX_C1CR_SE            = 0x10000    // Bit SE.
	DMAMUX_C1CR_SPOL_Pos      = 0x11       // Position of SPOL field.
	DMAMUX_C1CR_SPOL_Msk      = 0x60000    // Bit mask of SPOL field.
	DMAMUX_C1CR_NBREQ_Pos     = 0x13       // Position of NBREQ field.
	DMAMUX_C1CR_NBREQ_Msk     = 0xf80000   // Bit mask of NBREQ field.
	DMAMUX_C1CR_SYNC_ID_Pos   = 0x18       // Position of SYNC_ID field.
	DMAMUX_C1CR_SYNC_ID_Msk   = 0x1f000000 // Bit mask of SYNC_ID field.

	// C2CR: DMAMux - DMA request line multiplexer           channel x control register
	DMAMUX_C2CR_DMAREQ_ID_Pos = 0x0        // Position of DMAREQ_ID field.
	DMAMUX_C2CR_DMAREQ_ID_Msk = 0x7f       // Bit mask of DMAREQ_ID field.
	DMAMUX_C2CR_SOIE_Pos      = 0x8        // Position of SOIE field.
	DMAMUX_C2CR_SOIE_Msk      = 0x100      // Bit mask of SOIE field.
	DMAMUX_C2CR_SOIE          = 0x100      // Bit SOIE.
	DMAMUX_C2CR_EGE_Pos       = 0x9        // Position of EGE field.
	DMAMUX_C2CR_EGE_Msk       = 0x200      // Bit mask of EGE field.
	DMAMUX_C2CR_EGE           = 0x200      // Bit EGE.
	DMAMUX_C2CR_SE_Pos        = 0x10       // Position of SE field.
	DMAMUX_C2CR_SE_Msk        = 0x10000    // Bit mask of SE field.
	DMAMUX_C2CR_SE            = 0x10000    // Bit SE.
	DMAMUX_C2CR_SPOL_Pos      = 0x11       // Position of SPOL field.
	DMAMUX_C2CR_SPOL_Msk      = 0x60000    // Bit mask of SPOL field.
	DMAMUX_C2CR_NBREQ_Pos     = 0x13       // Position of NBREQ field.
	DMAMUX_C2CR_NBREQ_Msk     = 0xf80000   // Bit mask of NBREQ field.
	DMAMUX_C2CR_SYNC_ID_Pos   = 0x18       // Position of SYNC_ID field.
	DMAMUX_C2CR_SYNC_ID_Msk   = 0x1f000000 // Bit mask of SYNC_ID field.

	// C3CR: DMAMux - DMA request line multiplexer           channel x control register
	DMAMUX_C3CR_DMAREQ_ID_Pos = 0x0        // Position of DMAREQ_ID field.
	DMAMUX_C3CR_DMAREQ_ID_Msk = 0x7f       // Bit mask of DMAREQ_ID field.
	DMAMUX_C3CR_SOIE_Pos      = 0x8        // Position of SOIE field.
	DMAMUX_C3CR_SOIE_Msk      = 0x100      // Bit mask of SOIE field.
	DMAMUX_C3CR_SOIE          = 0x100      // Bit SOIE.
	DMAMUX_C3CR_EGE_Pos       = 0x9        // Position of EGE field.
	DMAMUX_C3CR_EGE_Msk       = 0x200      // Bit mask of EGE field.
	DMAMUX_C3CR_EGE           = 0x200      // Bit EGE.
	DMAMUX_C3CR_SE_Pos        = 0x10       // Position of SE field.
	DMAMUX_C3CR_SE_Msk        = 0x10000    // Bit mask of SE field.
	DMAMUX_C3CR_SE            = 0x10000    // Bit SE.
	DMAMUX_C3CR_SPOL_Pos      = 0x11       // Position of SPOL field.
	DMAMUX_C3CR_SPOL_Msk      = 0x60000    // Bit mask of SPOL field.
	DMAMUX_C3CR_NBREQ_Pos     = 0x13       // Position of NBREQ field.
	DMAMUX_C3CR_NBREQ_Msk     = 0xf80000   // Bit mask of NBREQ field.
	DMAMUX_C3CR_SYNC_ID_Pos   = 0x18       // Position of SYNC_ID field.
	DMAMUX_C3CR_SYNC_ID_Msk   = 0x1f000000 // Bit mask of SYNC_ID field.

	// C4CR: DMAMux - DMA request line multiplexer           channel x control register
	DMAMUX_C4CR_DMAREQ_ID_Pos = 0x0        // Position of DMAREQ_ID field.
	DMAMUX_C4CR_DMAREQ_ID_Msk = 0x7f       // Bit mask of DMAREQ_ID field.
	DMAMUX_C4CR_SOIE_Pos      = 0x8        // Position of SOIE field.
	DMAMUX_C4CR_SOIE_Msk      = 0x100      // Bit mask of SOIE field.
	DMAMUX_C4CR_SOIE          = 0x100      // Bit SOIE.
	DMAMUX_C4CR_EGE_Pos       = 0x9        // Position of EGE field.
	DMAMUX_C4CR_EGE_Msk       = 0x200      // Bit mask of EGE field.
	DMAMUX_C4CR_EGE           = 0x200      // Bit EGE.
	DMAMUX_C4CR_SE_Pos        = 0x10       // Position of SE field.
	DMAMUX_C4CR_SE_Msk        = 0x10000    // Bit mask of SE field.
	DMAMUX_C4CR_SE            = 0x10000    // Bit SE.
	DMAMUX_C4CR_SPOL_Pos      = 0x11       // Position of SPOL field.
	DMAMUX_C4CR_SPOL_Msk      = 0x60000    // Bit mask of SPOL field.
	DMAMUX_C4CR_NBREQ_Pos     = 0x13       // Position of NBREQ field.
	DMAMUX_C4CR_NBREQ_Msk     = 0xf80000   // Bit mask of NBREQ field.
	DMAMUX_C4CR_SYNC_ID_Pos   = 0x18       // Position of SYNC_ID field.
	DMAMUX_C4CR_SYNC_ID_Msk   = 0x1f000000 // Bit mask of SYNC_ID field.

	// C5CR: DMAMux - DMA request line multiplexer           channel x control register
	DMAMUX_C5CR_DMAREQ_ID_Pos = 0x0        // Position of DMAREQ_ID field.
	DMAMUX_C5CR_DMAREQ_ID_Msk = 0x7f       // Bit mask of DMAREQ_ID field.
	DMAMUX_C5CR_SOIE_Pos      = 0x8        // Position of SOIE field.
	DMAMUX_C5CR_SOIE_Msk      = 0x100      // Bit mask of SOIE field.
	DMAMUX_C5CR_SOIE          = 0x100      // Bit SOIE.
	DMAMUX_C5CR_EGE_Pos       = 0x9        // Position of EGE field.
	DMAMUX_C5CR_EGE_Msk       = 0x200      // Bit mask of EGE field.
	DMAMUX_C5CR_EGE           = 0x200      // Bit EGE.
	DMAMUX_C5CR_SE_Pos        = 0x10       // Position of SE field.
	DMAMUX_C5CR_SE_Msk        = 0x10000    // Bit mask of SE field.
	DMAMUX_C5CR_SE            = 0x10000    // Bit SE.
	DMAMUX_C5CR_SPOL_Pos      = 0x11       // Position of SPOL field.
	DMAMUX_C5CR_SPOL_Msk      = 0x60000    // Bit mask of SPOL field.
	DMAMUX_C5CR_NBREQ_Pos     = 0x13       // Position of NBREQ field.
	DMAMUX_C5CR_NBREQ_Msk     = 0xf80000   // Bit mask of NBREQ field.
	DMAMUX_C5CR_SYNC_ID_Pos   = 0x18       // Position of SYNC_ID field.
	DMAMUX_C5CR_SYNC_ID_Msk   = 0x1f000000 // Bit mask of SYNC_ID field.

	// C6CR: DMAMux - DMA request line multiplexer           channel x control register
	DMAMUX_C6CR_DMAREQ_ID_Pos = 0x0        // Position of DMAREQ_ID field.
	DMAMUX_C6CR_DMAREQ_ID_Msk = 0x7f       // Bit mask of DMAREQ_ID field.
	DMAMUX_C6CR_SOIE_Pos      = 0x8        // Position of SOIE field.
	DMAMUX_C6CR_SOIE_Msk      = 0x100      // Bit mask of SOIE field.
	DMAMUX_C6CR_SOIE          = 0x100      // Bit SOIE.
	DMAMUX_C6CR_EGE_Pos       = 0x9        // Position of EGE field.
	DMAMUX_C6CR_EGE_Msk       = 0x200      // Bit mask of EGE field.
	DMAMUX_C6CR_EGE           = 0x200      // Bit EGE.
	DMAMUX_C6CR_SE_Pos        = 0x10       // Position of SE field.
	DMAMUX_C6CR_SE_Msk        = 0x10000    // Bit mask of SE field.
	DMAMUX_C6CR_SE            = 0x10000    // Bit SE.
	DMAMUX_C6CR_SPOL_Pos      = 0x11       // Position of SPOL field.
	DMAMUX_C6CR_SPOL_Msk      = 0x60000    // Bit mask of SPOL field.
	DMAMUX_C6CR_NBREQ_Pos     = 0x13       // Position of NBREQ field.
	DMAMUX_C6CR_NBREQ_Msk     = 0xf80000   // Bit mask of NBREQ field.
	DMAMUX_C6CR_SYNC_ID_Pos   = 0x18       // Position of SYNC_ID field.
	DMAMUX_C6CR_SYNC_ID_Msk   = 0x1f000000 // Bit mask of SYNC_ID field.

	// C7CR: DMAMux - DMA request line multiplexer           channel x control register
	DMAMUX_C7CR_DMAREQ_ID_Pos = 0x0        // Position of DMAREQ_ID field.
	DMAMUX_C7CR_DMAREQ_ID_Msk = 0x7f       // Bit mask of DMAREQ_ID field.
	DMAMUX_C7CR_SOIE_Pos      = 0x8        // Position of SOIE field.
	DMAMUX_C7CR_SOIE_Msk      = 0x100      // Bit mask of SOIE field.
	DMAMUX_C7CR_SOIE          = 0x100      // Bit SOIE.
	DMAMUX_C7CR_EGE_Pos       = 0x9        // Position of EGE field.
	DMAMUX_C7CR_EGE_Msk       = 0x200      // Bit mask of EGE field.
	DMAMUX_C7CR_EGE           = 0x200      // Bit EGE.
	DMAMUX_C7CR_SE_Pos        = 0x10       // Position of SE field.
	DMAMUX_C7CR_SE_Msk        = 0x10000    // Bit mask of SE field.
	DMAMUX_C7CR_SE            = 0x10000    // Bit SE.
	DMAMUX_C7CR_SPOL_Pos      = 0x11       // Position of SPOL field.
	DMAMUX_C7CR_SPOL_Msk      = 0x60000    // Bit mask of SPOL field.
	DMAMUX_C7CR_NBREQ_Pos     = 0x13       // Position of NBREQ field.
	DMAMUX_C7CR_NBREQ_Msk     = 0xf80000   // Bit mask of NBREQ field.
	DMAMUX_C7CR_SYNC_ID_Pos   = 0x18       // Position of SYNC_ID field.
	DMAMUX_C7CR_SYNC_ID_Msk   = 0x1f000000 // Bit mask of SYNC_ID field.

	// C8CR: DMAMux - DMA request line multiplexer           channel x control register
	DMAMUX_C8CR_DMAREQ_ID_Pos = 0x0        // Position of DMAREQ_ID field.
	DMAMUX_C8CR_DMAREQ_ID_Msk = 0x7f       // Bit mask of DMAREQ_ID field.
	DMAMUX_C8CR_SOIE_Pos      = 0x8        // Position of SOIE field.
	DMAMUX_C8CR_SOIE_Msk      = 0x100      // Bit mask of SOIE field.
	DMAMUX_C8CR_SOIE          = 0x100      // Bit SOIE.
	DMAMUX_C8CR_EGE_Pos       = 0x9        // Position of EGE field.
	DMAMUX_C8CR_EGE_Msk       = 0x200      // Bit mask of EGE field.
	DMAMUX_C8CR_EGE           = 0x200      // Bit EGE.
	DMAMUX_C8CR_SE_Pos        = 0x10       // Position of SE field.
	DMAMUX_C8CR_SE_Msk        = 0x10000    // Bit mask of SE field.
	DMAMUX_C8CR_SE            = 0x10000    // Bit SE.
	DMAMUX_C8CR_SPOL_Pos      = 0x11       // Position of SPOL field.
	DMAMUX_C8CR_SPOL_Msk      = 0x60000    // Bit mask of SPOL field.
	DMAMUX_C8CR_NBREQ_Pos     = 0x13       // Position of NBREQ field.
	DMAMUX_C8CR_NBREQ_Msk     = 0xf80000   // Bit mask of NBREQ field.
	DMAMUX_C8CR_SYNC_ID_Pos   = 0x18       // Position of SYNC_ID field.
	DMAMUX_C8CR_SYNC_ID_Msk   = 0x1f000000 // Bit mask of SYNC_ID field.

	// C9CR: DMAMux - DMA request line multiplexer           channel x control register
	DMAMUX_C9CR_DMAREQ_ID_Pos = 0x0        // Position of DMAREQ_ID field.
	DMAMUX_C9CR_DMAREQ_ID_Msk = 0x7f       // Bit mask of DMAREQ_ID field.
	DMAMUX_C9CR_SOIE_Pos      = 0x8        // Position of SOIE field.
	DMAMUX_C9CR_SOIE_Msk      = 0x100      // Bit mask of SOIE field.
	DMAMUX_C9CR_SOIE          = 0x100      // Bit SOIE.
	DMAMUX_C9CR_EGE_Pos       = 0x9        // Position of EGE field.
	DMAMUX_C9CR_EGE_Msk       = 0x200      // Bit mask of EGE field.
	DMAMUX_C9CR_EGE           = 0x200      // Bit EGE.
	DMAMUX_C9CR_SE_Pos        = 0x10       // Position of SE field.
	DMAMUX_C9CR_SE_Msk        = 0x10000    // Bit mask of SE field.
	DMAMUX_C9CR_SE            = 0x10000    // Bit SE.
	DMAMUX_C9CR_SPOL_Pos      = 0x11       // Position of SPOL field.
	DMAMUX_C9CR_SPOL_Msk      = 0x60000    // Bit mask of SPOL field.
	DMAMUX_C9CR_NBREQ_Pos     = 0x13       // Position of NBREQ field.
	DMAMUX_C9CR_NBREQ_Msk     = 0xf80000   // Bit mask of NBREQ field.
	DMAMUX_C9CR_SYNC_ID_Pos   = 0x18       // Position of SYNC_ID field.
	DMAMUX_C9CR_SYNC_ID_Msk   = 0x1f000000 // Bit mask of SYNC_ID field.

	// C10CR: DMAMux - DMA request line multiplexer           channel x control register
	DMAMUX_C10CR_DMAREQ_ID_Pos = 0x0        // Position of DMAREQ_ID field.
	DMAMUX_C10CR_DMAREQ_ID_Msk = 0x7f       // Bit mask of DMAREQ_ID field.
	DMAMUX_C10CR_SOIE_Pos      = 0x8        // Position of SOIE field.
	DMAMUX_C10CR_SOIE_Msk      = 0x100      // Bit mask of SOIE field.
	DMAMUX_C10CR_SOIE          = 0x100      // Bit SOIE.
	DMAMUX_C10CR_EGE_Pos       = 0x9        // Position of EGE field.
	DMAMUX_C10CR_EGE_Msk       = 0x200      // Bit mask of EGE field.
	DMAMUX_C10CR_EGE           = 0x200      // Bit EGE.
	DMAMUX_C10CR_SE_Pos        = 0x10       // Position of SE field.
	DMAMUX_C10CR_SE_Msk        = 0x10000    // Bit mask of SE field.
	DMAMUX_C10CR_SE            = 0x10000    // Bit SE.
	DMAMUX_C10CR_SPOL_Pos      = 0x11       // Position of SPOL field.
	DMAMUX_C10CR_SPOL_Msk      = 0x60000    // Bit mask of SPOL field.
	DMAMUX_C10CR_NBREQ_Pos     = 0x13       // Position of NBREQ field.
	DMAMUX_C10CR_NBREQ_Msk     = 0xf80000   // Bit mask of NBREQ field.
	DMAMUX_C10CR_SYNC_ID_Pos   = 0x18       // Position of SYNC_ID field.
	DMAMUX_C10CR_SYNC_ID_Msk   = 0x1f000000 // Bit mask of SYNC_ID field.

	// C11CR: DMAMux - DMA request line multiplexer           channel x control register
	DMAMUX_C11CR_DMAREQ_ID_Pos = 0x0        // Position of DMAREQ_ID field.
	DMAMUX_C11CR_DMAREQ_ID_Msk = 0x7f       // Bit mask of DMAREQ_ID field.
	DMAMUX_C11CR_SOIE_Pos      = 0x8        // Position of SOIE field.
	DMAMUX_C11CR_SOIE_Msk      = 0x100      // Bit mask of SOIE field.
	DMAMUX_C11CR_SOIE          = 0x100      // Bit SOIE.
	DMAMUX_C11CR_EGE_Pos       = 0x9        // Position of EGE field.
	DMAMUX_C11CR_EGE_Msk       = 0x200      // Bit mask of EGE field.
	DMAMUX_C11CR_EGE           = 0x200      // Bit EGE.
	DMAMUX_C11CR_SE_Pos        = 0x10       // Position of SE field.
	DMAMUX_C11CR_SE_Msk        = 0x10000    // Bit mask of SE field.
	DMAMUX_C11CR_SE            = 0x10000    // Bit SE.
	DMAMUX_C11CR_SPOL_Pos      = 0x11       // Position of SPOL field.
	DMAMUX_C11CR_SPOL_Msk      = 0x60000    // Bit mask of SPOL field.
	DMAMUX_C11CR_NBREQ_Pos     = 0x13       // Position of NBREQ field.
	DMAMUX_C11CR_NBREQ_Msk     = 0xf80000   // Bit mask of NBREQ field.
	DMAMUX_C11CR_SYNC_ID_Pos   = 0x18       // Position of SYNC_ID field.
	DMAMUX_C11CR_SYNC_ID_Msk   = 0x1f000000 // Bit mask of SYNC_ID field.

	// C12CR: DMAMux - DMA request line multiplexer           channel x control register
	DMAMUX_C12CR_DMAREQ_ID_Pos = 0x0        // Position of DMAREQ_ID field.
	DMAMUX_C12CR_DMAREQ_ID_Msk = 0x7f       // Bit mask of DMAREQ_ID field.
	DMAMUX_C12CR_SOIE_Pos      = 0x8        // Position of SOIE field.
	DMAMUX_C12CR_SOIE_Msk      = 0x100      // Bit mask of SOIE field.
	DMAMUX_C12CR_SOIE          = 0x100      // Bit SOIE.
	DMAMUX_C12CR_EGE_Pos       = 0x9        // Position of EGE field.
	DMAMUX_C12CR_EGE_Msk       = 0x200      // Bit mask of EGE field.
	DMAMUX_C12CR_EGE           = 0x200      // Bit EGE.
	DMAMUX_C12CR_SE_Pos        = 0x10       // Position of SE field.
	DMAMUX_C12CR_SE_Msk        = 0x10000    // Bit mask of SE field.
	DMAMUX_C12CR_SE            = 0x10000    // Bit SE.
	DMAMUX_C12CR_SPOL_Pos      = 0x11       // Position of SPOL field.
	DMAMUX_C12CR_SPOL_Msk      = 0x60000    // Bit mask of SPOL field.
	DMAMUX_C12CR_NBREQ_Pos     = 0x13       // Position of NBREQ field.
	DMAMUX_C12CR_NBREQ_Msk     = 0xf80000   // Bit mask of NBREQ field.
	DMAMUX_C12CR_SYNC_ID_Pos   = 0x18       // Position of SYNC_ID field.
	DMAMUX_C12CR_SYNC_ID_Msk   = 0x1f000000 // Bit mask of SYNC_ID field.

	// C13CR: DMAMux - DMA request line multiplexer           channel x control register
	DMAMUX_C13CR_DMAREQ_ID_Pos = 0x0        // Position of DMAREQ_ID field.
	DMAMUX_C13CR_DMAREQ_ID_Msk = 0x7f       // Bit mask of DMAREQ_ID field.
	DMAMUX_C13CR_SOIE_Pos      = 0x8        // Position of SOIE field.
	DMAMUX_C13CR_SOIE_Msk      = 0x100      // Bit mask of SOIE field.
	DMAMUX_C13CR_SOIE          = 0x100      // Bit SOIE.
	DMAMUX_C13CR_EGE_Pos       = 0x9        // Position of EGE field.
	DMAMUX_C13CR_EGE_Msk       = 0x200      // Bit mask of EGE field.
	DMAMUX_C13CR_EGE           = 0x200      // Bit EGE.
	DMAMUX_C13CR_SE_Pos        = 0x10       // Position of SE field.
	DMAMUX_C13CR_SE_Msk        = 0x10000    // Bit mask of SE field.
	DMAMUX_C13CR_SE            = 0x10000    // Bit SE.
	DMAMUX_C13CR_SPOL_Pos      = 0x11       // Position of SPOL field.
	DMAMUX_C13CR_SPOL_Msk      = 0x60000    // Bit mask of SPOL field.
	DMAMUX_C13CR_NBREQ_Pos     = 0x13       // Position of NBREQ field.
	DMAMUX_C13CR_NBREQ_Msk     = 0xf80000   // Bit mask of NBREQ field.
	DMAMUX_C13CR_SYNC_ID_Pos   = 0x18       // Position of SYNC_ID field.
	DMAMUX_C13CR_SYNC_ID_Msk   = 0x1f000000 // Bit mask of SYNC_ID field.

	// C14CR: DMAMux - DMA request line multiplexer           channel x control register
	DMAMUX_C14CR_DMAREQ_ID_Pos = 0x0        // Position of DMAREQ_ID field.
	DMAMUX_C14CR_DMAREQ_ID_Msk = 0x7f       // Bit mask of DMAREQ_ID field.
	DMAMUX_C14CR_SOIE_Pos      = 0x8        // Position of SOIE field.
	DMAMUX_C14CR_SOIE_Msk      = 0x100      // Bit mask of SOIE field.
	DMAMUX_C14CR_SOIE          = 0x100      // Bit SOIE.
	DMAMUX_C14CR_EGE_Pos       = 0x9        // Position of EGE field.
	DMAMUX_C14CR_EGE_Msk       = 0x200      // Bit mask of EGE field.
	DMAMUX_C14CR_EGE           = 0x200      // Bit EGE.
	DMAMUX_C14CR_SE_Pos        = 0x10       // Position of SE field.
	DMAMUX_C14CR_SE_Msk        = 0x10000    // Bit mask of SE field.
	DMAMUX_C14CR_SE            = 0x10000    // Bit SE.
	DMAMUX_C14CR_SPOL_Pos      = 0x11       // Position of SPOL field.
	DMAMUX_C14CR_SPOL_Msk      = 0x60000    // Bit mask of SPOL field.
	DMAMUX_C14CR_NBREQ_Pos     = 0x13       // Position of NBREQ field.
	DMAMUX_C14CR_NBREQ_Msk     = 0xf80000   // Bit mask of NBREQ field.
	DMAMUX_C14CR_SYNC_ID_Pos   = 0x18       // Position of SYNC_ID field.
	DMAMUX_C14CR_SYNC_ID_Msk   = 0x1f000000 // Bit mask of SYNC_ID field.

	// C15CR: DMAMux - DMA request line multiplexer           channel x control register
	DMAMUX_C15CR_DMAREQ_ID_Pos = 0x0        // Position of DMAREQ_ID field.
	DMAMUX_C15CR_DMAREQ_ID_Msk = 0x7f       // Bit mask of DMAREQ_ID field.
	DMAMUX_C15CR_SOIE_Pos      = 0x8        // Position of SOIE field.
	DMAMUX_C15CR_SOIE_Msk      = 0x100      // Bit mask of SOIE field.
	DMAMUX_C15CR_SOIE          = 0x100      // Bit SOIE.
	DMAMUX_C15CR_EGE_Pos       = 0x9        // Position of EGE field.
	DMAMUX_C15CR_EGE_Msk       = 0x200      // Bit mask of EGE field.
	DMAMUX_C15CR_EGE           = 0x200      // Bit EGE.
	DMAMUX_C15CR_SE_Pos        = 0x10       // Position of SE field.
	DMAMUX_C15CR_SE_Msk        = 0x10000    // Bit mask of SE field.
	DMAMUX_C15CR_SE            = 0x10000    // Bit SE.
	DMAMUX_C15CR_SPOL_Pos      = 0x11       // Position of SPOL field.
	DMAMUX_C15CR_SPOL_Msk      = 0x60000    // Bit mask of SPOL field.
	DMAMUX_C15CR_NBREQ_Pos     = 0x13       // Position of NBREQ field.
	DMAMUX_C15CR_NBREQ_Msk     = 0xf80000   // Bit mask of NBREQ field.
	DMAMUX_C15CR_SYNC_ID_Pos   = 0x18       // Position of SYNC_ID field.
	DMAMUX_C15CR_SYNC_ID_Msk   = 0x1f000000 // Bit mask of SYNC_ID field.

	// CSR: DMAMUX request line multiplexer interrupt           channel status register
	DMAMUX_CSR_SOF_Pos = 0x0    // Position of SOF field.
	DMAMUX_CSR_SOF_Msk = 0xffff // Bit mask of SOF field.

	// CFR: DMAMUX request line multiplexer interrupt           clear flag register
	DMAMUX_CFR_CSOF_Pos = 0x0    // Position of CSOF field.
	DMAMUX_CFR_CSOF_Msk = 0xffff // Bit mask of CSOF field.

	// RG0CR: DMAMux - DMA request generator channel x           control register
	DMAMUX_RG0CR_SIG_ID_Pos = 0x0      // Position of SIG_ID field.
	DMAMUX_RG0CR_SIG_ID_Msk = 0x1f     // Bit mask of SIG_ID field.
	DMAMUX_RG0CR_OIE_Pos    = 0x8      // Position of OIE field.
	DMAMUX_RG0CR_OIE_Msk    = 0x100    // Bit mask of OIE field.
	DMAMUX_RG0CR_OIE        = 0x100    // Bit OIE.
	DMAMUX_RG0CR_GE_Pos     = 0x10     // Position of GE field.
	DMAMUX_RG0CR_GE_Msk     = 0x10000  // Bit mask of GE field.
	DMAMUX_RG0CR_GE         = 0x10000  // Bit GE.
	DMAMUX_RG0CR_GPOL_Pos   = 0x11     // Position of GPOL field.
	DMAMUX_RG0CR_GPOL_Msk   = 0x60000  // Bit mask of GPOL field.
	DMAMUX_RG0CR_GNBREQ_Pos = 0x13     // Position of GNBREQ field.
	DMAMUX_RG0CR_GNBREQ_Msk = 0xf80000 // Bit mask of GNBREQ field.

	// RG1CR: DMAMux - DMA request generator channel x           control register
	DMAMUX_RG1CR_SIG_ID_Pos = 0x0      // Position of SIG_ID field.
	DMAMUX_RG1CR_SIG_ID_Msk = 0x1f     // Bit mask of SIG_ID field.
	DMAMUX_RG1CR_OIE_Pos    = 0x8      // Position of OIE field.
	DMAMUX_RG1CR_OIE_Msk    = 0x100    // Bit mask of OIE field.
	DMAMUX_RG1CR_OIE        = 0x100    // Bit OIE.
	DMAMUX_RG1CR_GE_Pos     = 0x10     // Position of GE field.
	DMAMUX_RG1CR_GE_Msk     = 0x10000  // Bit mask of GE field.
	DMAMUX_RG1CR_GE         = 0x10000  // Bit GE.
	DMAMUX_RG1CR_GPOL_Pos   = 0x11     // Position of GPOL field.
	DMAMUX_RG1CR_GPOL_Msk   = 0x60000  // Bit mask of GPOL field.
	DMAMUX_RG1CR_GNBREQ_Pos = 0x13     // Position of GNBREQ field.
	DMAMUX_RG1CR_GNBREQ_Msk = 0xf80000 // Bit mask of GNBREQ field.

	// RG2CR: DMAMux - DMA request generator channel x           control register
	DMAMUX_RG2CR_SIG_ID_Pos = 0x0      // Position of SIG_ID field.
	DMAMUX_RG2CR_SIG_ID_Msk = 0x1f     // Bit mask of SIG_ID field.
	DMAMUX_RG2CR_OIE_Pos    = 0x8      // Position of OIE field.
	DMAMUX_RG2CR_OIE_Msk    = 0x100    // Bit mask of OIE field.
	DMAMUX_RG2CR_OIE        = 0x100    // Bit OIE.
	DMAMUX_RG2CR_GE_Pos     = 0x10     // Position of GE field.
	DMAMUX_RG2CR_GE_Msk     = 0x10000  // Bit mask of GE field.
	DMAMUX_RG2CR_GE         = 0x10000  // Bit GE.
	DMAMUX_RG2CR_GPOL_Pos   = 0x11     // Position of GPOL field.
	DMAMUX_RG2CR_GPOL_Msk   = 0x60000  // Bit mask of GPOL field.
	DMAMUX_RG2CR_GNBREQ_Pos = 0x13     // Position of GNBREQ field.
	DMAMUX_RG2CR_GNBREQ_Msk = 0xf80000 // Bit mask of GNBREQ field.

	// RG3CR: DMAMux - DMA request generator channel x           control register
	DMAMUX_RG3CR_SIG_ID_Pos = 0x0      // Position of SIG_ID field.
	DMAMUX_RG3CR_SIG_ID_Msk = 0x1f     // Bit mask of SIG_ID field.
	DMAMUX_RG3CR_OIE_Pos    = 0x8      // Position of OIE field.
	DMAMUX_RG3CR_OIE_Msk    = 0x100    // Bit mask of OIE field.
	DMAMUX_RG3CR_OIE        = 0x100    // Bit OIE.
	DMAMUX_RG3CR_GE_Pos     = 0x10     // Position of GE field.
	DMAMUX_RG3CR_GE_Msk     = 0x10000  // Bit mask of GE field.
	DMAMUX_RG3CR_GE         = 0x10000  // Bit GE.
	DMAMUX_RG3CR_GPOL_Pos   = 0x11     // Position of GPOL field.
	DMAMUX_RG3CR_GPOL_Msk   = 0x60000  // Bit mask of GPOL field.
	DMAMUX_RG3CR_GNBREQ_Pos = 0x13     // Position of GNBREQ field.
	DMAMUX_RG3CR_GNBREQ_Msk = 0xf80000 // Bit mask of GNBREQ field.

	// RGSR: DMAMux - DMA request generator status           register
	DMAMUX_RGSR_OF_Pos = 0x0 // Position of OF field.
	DMAMUX_RGSR_OF_Msk = 0xf // Bit mask of OF field.

	// RGCFR: DMAMux - DMA request generator clear flag           register
	DMAMUX_RGCFR_COF_Pos = 0x0 // Position of COF field.
	DMAMUX_RGCFR_COF_Msk = 0xf // Bit mask of COF field.
)

// Bitfields for SYSCFG: System configuration controller
const (
	// MEMRMP: Remap Memory register
	SYSCFG_MEMRMP_MEM_MODE_Pos = 0x0   // Position of MEM_MODE field.
	SYSCFG_MEMRMP_MEM_MODE_Msk = 0x7   // Bit mask of MEM_MODE field.
	SYSCFG_MEMRMP_FB_mode_Pos  = 0x8   // Position of FB_mode field.
	SYSCFG_MEMRMP_FB_mode_Msk  = 0x100 // Bit mask of FB_mode field.
	SYSCFG_MEMRMP_FB_mode      = 0x100 // Bit FB_mode.

	// CFGR1: peripheral mode configuration           register
	SYSCFG_CFGR1_BOOSTEN_Pos     = 0x8        // Position of BOOSTEN field.
	SYSCFG_CFGR1_BOOSTEN_Msk     = 0x100      // Bit mask of BOOSTEN field.
	SYSCFG_CFGR1_BOOSTEN         = 0x100      // Bit BOOSTEN.
	SYSCFG_CFGR1_ANASWVDD_Pos    = 0x9        // Position of ANASWVDD field.
	SYSCFG_CFGR1_ANASWVDD_Msk    = 0x200      // Bit mask of ANASWVDD field.
	SYSCFG_CFGR1_ANASWVDD        = 0x200      // Bit ANASWVDD.
	SYSCFG_CFGR1_I2C_PB6_FMP_Pos = 0x10       // Position of I2C_PB6_FMP field.
	SYSCFG_CFGR1_I2C_PB6_FMP_Msk = 0x10000    // Bit mask of I2C_PB6_FMP field.
	SYSCFG_CFGR1_I2C_PB6_FMP     = 0x10000    // Bit I2C_PB6_FMP.
	SYSCFG_CFGR1_I2C_PB7_FMP_Pos = 0x11       // Position of I2C_PB7_FMP field.
	SYSCFG_CFGR1_I2C_PB7_FMP_Msk = 0x20000    // Bit mask of I2C_PB7_FMP field.
	SYSCFG_CFGR1_I2C_PB7_FMP     = 0x20000    // Bit I2C_PB7_FMP.
	SYSCFG_CFGR1_I2C_PB8_FMP_Pos = 0x12       // Position of I2C_PB8_FMP field.
	SYSCFG_CFGR1_I2C_PB8_FMP_Msk = 0x40000    // Bit mask of I2C_PB8_FMP field.
	SYSCFG_CFGR1_I2C_PB8_FMP     = 0x40000    // Bit I2C_PB8_FMP.
	SYSCFG_CFGR1_I2C_PB9_FMP_Pos = 0x13       // Position of I2C_PB9_FMP field.
	SYSCFG_CFGR1_I2C_PB9_FMP_Msk = 0x80000    // Bit mask of I2C_PB9_FMP field.
	SYSCFG_CFGR1_I2C_PB9_FMP     = 0x80000    // Bit I2C_PB9_FMP.
	SYSCFG_CFGR1_I2C1_FMP_Pos    = 0x14       // Position of I2C1_FMP field.
	SYSCFG_CFGR1_I2C1_FMP_Msk    = 0x100000   // Bit mask of I2C1_FMP field.
	SYSCFG_CFGR1_I2C1_FMP        = 0x100000   // Bit I2C1_FMP.
	SYSCFG_CFGR1_I2C2_FMP_Pos    = 0x15       // Position of I2C2_FMP field.
	SYSCFG_CFGR1_I2C2_FMP_Msk    = 0x200000   // Bit mask of I2C2_FMP field.
	SYSCFG_CFGR1_I2C2_FMP        = 0x200000   // Bit I2C2_FMP.
	SYSCFG_CFGR1_I2C3_FMP_Pos    = 0x16       // Position of I2C3_FMP field.
	SYSCFG_CFGR1_I2C3_FMP_Msk    = 0x400000   // Bit mask of I2C3_FMP field.
	SYSCFG_CFGR1_I2C3_FMP        = 0x400000   // Bit I2C3_FMP.
	SYSCFG_CFGR1_I2C4_FMP_Pos    = 0x17       // Position of I2C4_FMP field.
	SYSCFG_CFGR1_I2C4_FMP_Msk    = 0x800000   // Bit mask of I2C4_FMP field.
	SYSCFG_CFGR1_I2C4_FMP        = 0x800000   // Bit I2C4_FMP.
	SYSCFG_CFGR1_FPU_IE_Pos      = 0x1a       // Position of FPU_IE field.
	SYSCFG_CFGR1_FPU_IE_Msk      = 0xfc000000 // Bit mask of FPU_IE field.

	// EXTICR1: external interrupt configuration register           1
	SYSCFG_EXTICR1_EXTI3_Pos = 0xc    // Position of EXTI3 field.
	SYSCFG_EXTICR1_EXTI3_Msk = 0xf000 // Bit mask of EXTI3 field.
	SYSCFG_EXTICR1_EXTI2_Pos = 0x8    // Position of EXTI2 field.
	SYSCFG_EXTICR1_EXTI2_Msk = 0xf00  // Bit mask of EXTI2 field.
	SYSCFG_EXTICR1_EXTI1_Pos = 0x4    // Position of EXTI1 field.
	SYSCFG_EXTICR1_EXTI1_Msk = 0xf0   // Bit mask of EXTI1 field.
	SYSCFG_EXTICR1_EXTI0_Pos = 0x0    // Position of EXTI0 field.
	SYSCFG_EXTICR1_EXTI0_Msk = 0xf    // Bit mask of EXTI0 field.

	// EXTICR2: external interrupt configuration register           2
	SYSCFG_EXTICR2_EXTI7_Pos = 0xc    // Position of EXTI7 field.
	SYSCFG_EXTICR2_EXTI7_Msk = 0xf000 // Bit mask of EXTI7 field.
	SYSCFG_EXTICR2_EXTI6_Pos = 0x8    // Position of EXTI6 field.
	SYSCFG_EXTICR2_EXTI6_Msk = 0xf00  // Bit mask of EXTI6 field.
	SYSCFG_EXTICR2_EXTI5_Pos = 0x4    // Position of EXTI5 field.
	SYSCFG_EXTICR2_EXTI5_Msk = 0xf0   // Bit mask of EXTI5 field.
	SYSCFG_EXTICR2_EXTI4_Pos = 0x0    // Position of EXTI4 field.
	SYSCFG_EXTICR2_EXTI4_Msk = 0xf    // Bit mask of EXTI4 field.

	// EXTICR3: external interrupt configuration register           3
	SYSCFG_EXTICR3_EXTI11_Pos = 0xc    // Position of EXTI11 field.
	SYSCFG_EXTICR3_EXTI11_Msk = 0xf000 // Bit mask of EXTI11 field.
	SYSCFG_EXTICR3_EXTI10_Pos = 0x8    // Position of EXTI10 field.
	SYSCFG_EXTICR3_EXTI10_Msk = 0xf00  // Bit mask of EXTI10 field.
	SYSCFG_EXTICR3_EXTI9_Pos  = 0x4    // Position of EXTI9 field.
	SYSCFG_EXTICR3_EXTI9_Msk  = 0xf0   // Bit mask of EXTI9 field.
	SYSCFG_EXTICR3_EXTI8_Pos  = 0x0    // Position of EXTI8 field.
	SYSCFG_EXTICR3_EXTI8_Msk  = 0xf    // Bit mask of EXTI8 field.

	// EXTICR4: external interrupt configuration register           4
	SYSCFG_EXTICR4_EXTI15_Pos = 0xc    // Position of EXTI15 field.
	SYSCFG_EXTICR4_EXTI15_Msk = 0xf000 // Bit mask of EXTI15 field.
	SYSCFG_EXTICR4_EXTI14_Pos = 0x8    // Position of EXTI14 field.
	SYSCFG_EXTICR4_EXTI14_Msk = 0xf00  // Bit mask of EXTI14 field.
	SYSCFG_EXTICR4_EXTI13_Pos = 0x4    // Position of EXTI13 field.
	SYSCFG_EXTICR4_EXTI13_Msk = 0xf0   // Bit mask of EXTI13 field.
	SYSCFG_EXTICR4_EXTI12_Pos = 0x0    // Position of EXTI12 field.
	SYSCFG_EXTICR4_EXTI12_Msk = 0xf    // Bit mask of EXTI12 field.

	// SCSR: CCM SRAM control and status           register
	SYSCFG_SCSR_CCMER_Pos  = 0x0 // Position of CCMER field.
	SYSCFG_SCSR_CCMER_Msk  = 0x1 // Bit mask of CCMER field.
	SYSCFG_SCSR_CCMER      = 0x1 // Bit CCMER.
	SYSCFG_SCSR_CCMBSY_Pos = 0x1 // Position of CCMBSY field.
	SYSCFG_SCSR_CCMBSY_Msk = 0x2 // Bit mask of CCMBSY field.
	SYSCFG_SCSR_CCMBSY     = 0x2 // Bit CCMBSY.

	// CFGR2: configuration register 2
	SYSCFG_CFGR2_CLL_Pos  = 0x0   // Position of CLL field.
	SYSCFG_CFGR2_CLL_Msk  = 0x1   // Bit mask of CLL field.
	SYSCFG_CFGR2_CLL      = 0x1   // Bit CLL.
	SYSCFG_CFGR2_SPL_Pos  = 0x1   // Position of SPL field.
	SYSCFG_CFGR2_SPL_Msk  = 0x2   // Bit mask of SPL field.
	SYSCFG_CFGR2_SPL      = 0x2   // Bit SPL.
	SYSCFG_CFGR2_PVDL_Pos = 0x2   // Position of PVDL field.
	SYSCFG_CFGR2_PVDL_Msk = 0x4   // Bit mask of PVDL field.
	SYSCFG_CFGR2_PVDL     = 0x4   // Bit PVDL.
	SYSCFG_CFGR2_ECCL_Pos = 0x3   // Position of ECCL field.
	SYSCFG_CFGR2_ECCL_Msk = 0x8   // Bit mask of ECCL field.
	SYSCFG_CFGR2_ECCL     = 0x8   // Bit ECCL.
	SYSCFG_CFGR2_SPF_Pos  = 0x8   // Position of SPF field.
	SYSCFG_CFGR2_SPF_Msk  = 0x100 // Bit mask of SPF field.
	SYSCFG_CFGR2_SPF      = 0x100 // Bit SPF.

	// SWPR: SRAM Write protection register           1
	SYSCFG_SWPR_Page0_WP_Pos  = 0x0        // Position of Page0_WP field.
	SYSCFG_SWPR_Page0_WP_Msk  = 0x1        // Bit mask of Page0_WP field.
	SYSCFG_SWPR_Page0_WP      = 0x1        // Bit Page0_WP.
	SYSCFG_SWPR_Page1_WP_Pos  = 0x1        // Position of Page1_WP field.
	SYSCFG_SWPR_Page1_WP_Msk  = 0x2        // Bit mask of Page1_WP field.
	SYSCFG_SWPR_Page1_WP      = 0x2        // Bit Page1_WP.
	SYSCFG_SWPR_Page2_WP_Pos  = 0x2        // Position of Page2_WP field.
	SYSCFG_SWPR_Page2_WP_Msk  = 0x4        // Bit mask of Page2_WP field.
	SYSCFG_SWPR_Page2_WP      = 0x4        // Bit Page2_WP.
	SYSCFG_SWPR_Page3_WP_Pos  = 0x3        // Position of Page3_WP field.
	SYSCFG_SWPR_Page3_WP_Msk  = 0x8        // Bit mask of Page3_WP field.
	SYSCFG_SWPR_Page3_WP      = 0x8        // Bit Page3_WP.
	SYSCFG_SWPR_Page4_WP_Pos  = 0x4        // Position of Page4_WP field.
	SYSCFG_SWPR_Page4_WP_Msk  = 0x10       // Bit mask of Page4_WP field.
	SYSCFG_SWPR_Page4_WP      = 0x10       // Bit Page4_WP.
	SYSCFG_SWPR_Page5_WP_Pos  = 0x5        // Position of Page5_WP field.
	SYSCFG_SWPR_Page5_WP_Msk  = 0x20       // Bit mask of Page5_WP field.
	SYSCFG_SWPR_Page5_WP      = 0x20       // Bit Page5_WP.
	SYSCFG_SWPR_Page6_WP_Pos  = 0x6        // Position of Page6_WP field.
	SYSCFG_SWPR_Page6_WP_Msk  = 0x40       // Bit mask of Page6_WP field.
	SYSCFG_SWPR_Page6_WP      = 0x40       // Bit Page6_WP.
	SYSCFG_SWPR_Page7_WP_Pos  = 0x7        // Position of Page7_WP field.
	SYSCFG_SWPR_Page7_WP_Msk  = 0x80       // Bit mask of Page7_WP field.
	SYSCFG_SWPR_Page7_WP      = 0x80       // Bit Page7_WP.
	SYSCFG_SWPR_Page8_WP_Pos  = 0x8        // Position of Page8_WP field.
	SYSCFG_SWPR_Page8_WP_Msk  = 0x100      // Bit mask of Page8_WP field.
	SYSCFG_SWPR_Page8_WP      = 0x100      // Bit Page8_WP.
	SYSCFG_SWPR_Page9_WP_Pos  = 0x9        // Position of Page9_WP field.
	SYSCFG_SWPR_Page9_WP_Msk  = 0x200      // Bit mask of Page9_WP field.
	SYSCFG_SWPR_Page9_WP      = 0x200      // Bit Page9_WP.
	SYSCFG_SWPR_Page10_WP_Pos = 0xa        // Position of Page10_WP field.
	SYSCFG_SWPR_Page10_WP_Msk = 0x400      // Bit mask of Page10_WP field.
	SYSCFG_SWPR_Page10_WP     = 0x400      // Bit Page10_WP.
	SYSCFG_SWPR_Page11_WP_Pos = 0xb        // Position of Page11_WP field.
	SYSCFG_SWPR_Page11_WP_Msk = 0x800      // Bit mask of Page11_WP field.
	SYSCFG_SWPR_Page11_WP     = 0x800      // Bit Page11_WP.
	SYSCFG_SWPR_Page12_WP_Pos = 0xc        // Position of Page12_WP field.
	SYSCFG_SWPR_Page12_WP_Msk = 0x1000     // Bit mask of Page12_WP field.
	SYSCFG_SWPR_Page12_WP     = 0x1000     // Bit Page12_WP.
	SYSCFG_SWPR_Page13_WP_Pos = 0xd        // Position of Page13_WP field.
	SYSCFG_SWPR_Page13_WP_Msk = 0x2000     // Bit mask of Page13_WP field.
	SYSCFG_SWPR_Page13_WP     = 0x2000     // Bit Page13_WP.
	SYSCFG_SWPR_Page14_WP_Pos = 0xe        // Position of Page14_WP field.
	SYSCFG_SWPR_Page14_WP_Msk = 0x4000     // Bit mask of Page14_WP field.
	SYSCFG_SWPR_Page14_WP     = 0x4000     // Bit Page14_WP.
	SYSCFG_SWPR_Page15_WP_Pos = 0xf        // Position of Page15_WP field.
	SYSCFG_SWPR_Page15_WP_Msk = 0x8000     // Bit mask of Page15_WP field.
	SYSCFG_SWPR_Page15_WP     = 0x8000     // Bit Page15_WP.
	SYSCFG_SWPR_Page16_WP_Pos = 0x10       // Position of Page16_WP field.
	SYSCFG_SWPR_Page16_WP_Msk = 0x10000    // Bit mask of Page16_WP field.
	SYSCFG_SWPR_Page16_WP     = 0x10000    // Bit Page16_WP.
	SYSCFG_SWPR_Page17_WP_Pos = 0x11       // Position of Page17_WP field.
	SYSCFG_SWPR_Page17_WP_Msk = 0x20000    // Bit mask of Page17_WP field.
	SYSCFG_SWPR_Page17_WP     = 0x20000    // Bit Page17_WP.
	SYSCFG_SWPR_Page18_WP_Pos = 0x12       // Position of Page18_WP field.
	SYSCFG_SWPR_Page18_WP_Msk = 0x40000    // Bit mask of Page18_WP field.
	SYSCFG_SWPR_Page18_WP     = 0x40000    // Bit Page18_WP.
	SYSCFG_SWPR_Page19_WP_Pos = 0x13       // Position of Page19_WP field.
	SYSCFG_SWPR_Page19_WP_Msk = 0x80000    // Bit mask of Page19_WP field.
	SYSCFG_SWPR_Page19_WP     = 0x80000    // Bit Page19_WP.
	SYSCFG_SWPR_Page20_WP_Pos = 0x14       // Position of Page20_WP field.
	SYSCFG_SWPR_Page20_WP_Msk = 0x100000   // Bit mask of Page20_WP field.
	SYSCFG_SWPR_Page20_WP     = 0x100000   // Bit Page20_WP.
	SYSCFG_SWPR_Page21_WP_Pos = 0x15       // Position of Page21_WP field.
	SYSCFG_SWPR_Page21_WP_Msk = 0x200000   // Bit mask of Page21_WP field.
	SYSCFG_SWPR_Page21_WP     = 0x200000   // Bit Page21_WP.
	SYSCFG_SWPR_Page22_WP_Pos = 0x16       // Position of Page22_WP field.
	SYSCFG_SWPR_Page22_WP_Msk = 0x400000   // Bit mask of Page22_WP field.
	SYSCFG_SWPR_Page22_WP     = 0x400000   // Bit Page22_WP.
	SYSCFG_SWPR_Page23_WP_Pos = 0x17       // Position of Page23_WP field.
	SYSCFG_SWPR_Page23_WP_Msk = 0x800000   // Bit mask of Page23_WP field.
	SYSCFG_SWPR_Page23_WP     = 0x800000   // Bit Page23_WP.
	SYSCFG_SWPR_Page24_WP_Pos = 0x18       // Position of Page24_WP field.
	SYSCFG_SWPR_Page24_WP_Msk = 0x1000000  // Bit mask of Page24_WP field.
	SYSCFG_SWPR_Page24_WP     = 0x1000000  // Bit Page24_WP.
	SYSCFG_SWPR_Page25_WP_Pos = 0x19       // Position of Page25_WP field.
	SYSCFG_SWPR_Page25_WP_Msk = 0x2000000  // Bit mask of Page25_WP field.
	SYSCFG_SWPR_Page25_WP     = 0x2000000  // Bit Page25_WP.
	SYSCFG_SWPR_Page26_WP_Pos = 0x1a       // Position of Page26_WP field.
	SYSCFG_SWPR_Page26_WP_Msk = 0x4000000  // Bit mask of Page26_WP field.
	SYSCFG_SWPR_Page26_WP     = 0x4000000  // Bit Page26_WP.
	SYSCFG_SWPR_Page27_WP_Pos = 0x1b       // Position of Page27_WP field.
	SYSCFG_SWPR_Page27_WP_Msk = 0x8000000  // Bit mask of Page27_WP field.
	SYSCFG_SWPR_Page27_WP     = 0x8000000  // Bit Page27_WP.
	SYSCFG_SWPR_Page28_WP_Pos = 0x1c       // Position of Page28_WP field.
	SYSCFG_SWPR_Page28_WP_Msk = 0x10000000 // Bit mask of Page28_WP field.
	SYSCFG_SWPR_Page28_WP     = 0x10000000 // Bit Page28_WP.
	SYSCFG_SWPR_Page29_WP_Pos = 0x1d       // Position of Page29_WP field.
	SYSCFG_SWPR_Page29_WP_Msk = 0x20000000 // Bit mask of Page29_WP field.
	SYSCFG_SWPR_Page29_WP     = 0x20000000 // Bit Page29_WP.
	SYSCFG_SWPR_Page30_WP_Pos = 0x1e       // Position of Page30_WP field.
	SYSCFG_SWPR_Page30_WP_Msk = 0x40000000 // Bit mask of Page30_WP field.
	SYSCFG_SWPR_Page30_WP     = 0x40000000 // Bit Page30_WP.
	SYSCFG_SWPR_Page31_WP_Pos = 0x1f       // Position of Page31_WP field.
	SYSCFG_SWPR_Page31_WP_Msk = 0x80000000 // Bit mask of Page31_WP field.
	SYSCFG_SWPR_Page31_WP     = 0x80000000 // Bit Page31_WP.

	// SKR: SRAM2 Key Register
	SYSCFG_SKR_KEY_Pos = 0x0  // Position of KEY field.
	SYSCFG_SKR_KEY_Msk = 0xff // Bit mask of KEY field.
)

// Bitfields for VREFBUF: Voltage reference buffer
const (
	// VREFBUF_CSR: VREF_BUF Control and Status           Register
	VREFBUF_VREFBUF_CSR_ENVR_Pos = 0x0  // Position of ENVR field.
	VREFBUF_VREFBUF_CSR_ENVR_Msk = 0x1  // Bit mask of ENVR field.
	VREFBUF_VREFBUF_CSR_ENVR     = 0x1  // Bit ENVR.
	VREFBUF_VREFBUF_CSR_HIZ_Pos  = 0x1  // Position of HIZ field.
	VREFBUF_VREFBUF_CSR_HIZ_Msk  = 0x2  // Bit mask of HIZ field.
	VREFBUF_VREFBUF_CSR_HIZ      = 0x2  // Bit HIZ.
	VREFBUF_VREFBUF_CSR_VRR_Pos  = 0x3  // Position of VRR field.
	VREFBUF_VREFBUF_CSR_VRR_Msk  = 0x8  // Bit mask of VRR field.
	VREFBUF_VREFBUF_CSR_VRR      = 0x8  // Bit VRR.
	VREFBUF_VREFBUF_CSR_VRS_Pos  = 0x4  // Position of VRS field.
	VREFBUF_VREFBUF_CSR_VRS_Msk  = 0x30 // Bit mask of VRS field.

	// VREFBUF_CCR: VREF_BUF Calibration Control           Register
	VREFBUF_VREFBUF_CCR_TRIM_Pos = 0x0  // Position of TRIM field.
	VREFBUF_VREFBUF_CCR_TRIM_Msk = 0x3f // Bit mask of TRIM field.
)

// Bitfields for COMP: Comparator control and status register
const (
	// COMP_C1CSR: Comparator control/status           register
	COMP_COMP_C1CSR_EN_Pos               = 0x0        // Position of EN field.
	COMP_COMP_C1CSR_EN_Msk               = 0x1        // Bit mask of EN field.
	COMP_COMP_C1CSR_EN                   = 0x1        // Bit EN.
	COMP_COMP_C1CSR_COMP_DEGLITCH_EN_Pos = 0x1        // Position of COMP_DEGLITCH_EN field.
	COMP_COMP_C1CSR_COMP_DEGLITCH_EN_Msk = 0x2        // Bit mask of COMP_DEGLITCH_EN field.
	COMP_COMP_C1CSR_COMP_DEGLITCH_EN     = 0x2        // Bit COMP_DEGLITCH_EN.
	COMP_COMP_C1CSR_INMSEL_Pos           = 0x4        // Position of INMSEL field.
	COMP_COMP_C1CSR_INMSEL_Msk           = 0x70       // Bit mask of INMSEL field.
	COMP_COMP_C1CSR_INPSEL_Pos           = 0x8        // Position of INPSEL field.
	COMP_COMP_C1CSR_INPSEL_Msk           = 0x100      // Bit mask of INPSEL field.
	COMP_COMP_C1CSR_INPSEL               = 0x100      // Bit INPSEL.
	COMP_COMP_C1CSR_POL_Pos              = 0xf        // Position of POL field.
	COMP_COMP_C1CSR_POL_Msk              = 0x8000     // Bit mask of POL field.
	COMP_COMP_C1CSR_POL                  = 0x8000     // Bit POL.
	COMP_COMP_C1CSR_HYST_Pos             = 0x10       // Position of HYST field.
	COMP_COMP_C1CSR_HYST_Msk             = 0x70000    // Bit mask of HYST field.
	COMP_COMP_C1CSR_BLANKSEL_Pos         = 0x13       // Position of BLANKSEL field.
	COMP_COMP_C1CSR_BLANKSEL_Msk         = 0x380000   // Bit mask of BLANKSEL field.
	COMP_COMP_C1CSR_BRGEN_Pos            = 0x16       // Position of BRGEN field.
	COMP_COMP_C1CSR_BRGEN_Msk            = 0x400000   // Bit mask of BRGEN field.
	COMP_COMP_C1CSR_BRGEN                = 0x400000   // Bit BRGEN.
	COMP_COMP_C1CSR_SCALEN_Pos           = 0x17       // Position of SCALEN field.
	COMP_COMP_C1CSR_SCALEN_Msk           = 0x800000   // Bit mask of SCALEN field.
	COMP_COMP_C1CSR_SCALEN               = 0x800000   // Bit SCALEN.
	COMP_COMP_C1CSR_VALUE_Pos            = 0x1e       // Position of VALUE field.
	COMP_COMP_C1CSR_VALUE_Msk            = 0x40000000 // Bit mask of VALUE field.
	COMP_COMP_C1CSR_VALUE                = 0x40000000 // Bit VALUE.
	COMP_COMP_C1CSR_LOCK_Pos             = 0x1f       // Position of LOCK field.
	COMP_COMP_C1CSR_LOCK_Msk             = 0x80000000 // Bit mask of LOCK field.
	COMP_COMP_C1CSR_LOCK                 = 0x80000000 // Bit LOCK.

	// COMP_C2CSR: Comparator control/status           register
	COMP_COMP_C2CSR_EN_Pos               = 0x0        // Position of EN field.
	COMP_COMP_C2CSR_EN_Msk               = 0x1        // Bit mask of EN field.
	COMP_COMP_C2CSR_EN                   = 0x1        // Bit EN.
	COMP_COMP_C2CSR_COMP_DEGLITCH_EN_Pos = 0x1        // Position of COMP_DEGLITCH_EN field.
	COMP_COMP_C2CSR_COMP_DEGLITCH_EN_Msk = 0x2        // Bit mask of COMP_DEGLITCH_EN field.
	COMP_COMP_C2CSR_COMP_DEGLITCH_EN     = 0x2        // Bit COMP_DEGLITCH_EN.
	COMP_COMP_C2CSR_INMSEL_Pos           = 0x4        // Position of INMSEL field.
	COMP_COMP_C2CSR_INMSEL_Msk           = 0x70       // Bit mask of INMSEL field.
	COMP_COMP_C2CSR_INPSEL_Pos           = 0x8        // Position of INPSEL field.
	COMP_COMP_C2CSR_INPSEL_Msk           = 0x100      // Bit mask of INPSEL field.
	COMP_COMP_C2CSR_INPSEL               = 0x100      // Bit INPSEL.
	COMP_COMP_C2CSR_POL_Pos              = 0xf        // Position of POL field.
	COMP_COMP_C2CSR_POL_Msk              = 0x8000     // Bit mask of POL field.
	COMP_COMP_C2CSR_POL                  = 0x8000     // Bit POL.
	COMP_COMP_C2CSR_HYST_Pos             = 0x10       // Position of HYST field.
	COMP_COMP_C2CSR_HYST_Msk             = 0x70000    // Bit mask of HYST field.
	COMP_COMP_C2CSR_BLANKSEL_Pos         = 0x13       // Position of BLANKSEL field.
	COMP_COMP_C2CSR_BLANKSEL_Msk         = 0x380000   // Bit mask of BLANKSEL field.
	COMP_COMP_C2CSR_BRGEN_Pos            = 0x16       // Position of BRGEN field.
	COMP_COMP_C2CSR_BRGEN_Msk            = 0x400000   // Bit mask of BRGEN field.
	COMP_COMP_C2CSR_BRGEN                = 0x400000   // Bit BRGEN.
	COMP_COMP_C2CSR_SCALEN_Pos           = 0x17       // Position of SCALEN field.
	COMP_COMP_C2CSR_SCALEN_Msk           = 0x800000   // Bit mask of SCALEN field.
	COMP_COMP_C2CSR_SCALEN               = 0x800000   // Bit SCALEN.
	COMP_COMP_C2CSR_VALUE_Pos            = 0x1e       // Position of VALUE field.
	COMP_COMP_C2CSR_VALUE_Msk            = 0x40000000 // Bit mask of VALUE field.
	COMP_COMP_C2CSR_VALUE                = 0x40000000 // Bit VALUE.
	COMP_COMP_C2CSR_LOCK_Pos             = 0x1f       // Position of LOCK field.
	COMP_COMP_C2CSR_LOCK_Msk             = 0x80000000 // Bit mask of LOCK field.
	COMP_COMP_C2CSR_LOCK                 = 0x80000000 // Bit LOCK.

	// COMP_C3CSR: Comparator control/status           register
	COMP_COMP_C3CSR_EN_Pos               = 0x0        // Position of EN field.
	COMP_COMP_C3CSR_EN_Msk               = 0x1        // Bit mask of EN field.
	COMP_COMP_C3CSR_EN                   = 0x1        // Bit EN.
	COMP_COMP_C3CSR_COMP_DEGLITCH_EN_Pos = 0x1        // Position of COMP_DEGLITCH_EN field.
	COMP_COMP_C3CSR_COMP_DEGLITCH_EN_Msk = 0x2        // Bit mask of COMP_DEGLITCH_EN field.
	COMP_COMP_C3CSR_COMP_DEGLITCH_EN     = 0x2        // Bit COMP_DEGLITCH_EN.
	COMP_COMP_C3CSR_INMSEL_Pos           = 0x4        // Position of INMSEL field.
	COMP_COMP_C3CSR_INMSEL_Msk           = 0x70       // Bit mask of INMSEL field.
	COMP_COMP_C3CSR_INPSEL_Pos           = 0x8        // Position of INPSEL field.
	COMP_COMP_C3CSR_INPSEL_Msk           = 0x100      // Bit mask of INPSEL field.
	COMP_COMP_C3CSR_INPSEL               = 0x100      // Bit INPSEL.
	COMP_COMP_C3CSR_POL_Pos              = 0xf        // Position of POL field.
	COMP_COMP_C3CSR_POL_Msk              = 0x8000     // Bit mask of POL field.
	COMP_COMP_C3CSR_POL                  = 0x8000     // Bit POL.
	COMP_COMP_C3CSR_HYST_Pos             = 0x10       // Position of HYST field.
	COMP_COMP_C3CSR_HYST_Msk             = 0x70000    // Bit mask of HYST field.
	COMP_COMP_C3CSR_BLANKSEL_Pos         = 0x13       // Position of BLANKSEL field.
	COMP_COMP_C3CSR_BLANKSEL_Msk         = 0x380000   // Bit mask of BLANKSEL field.
	COMP_COMP_C3CSR_BRGEN_Pos            = 0x16       // Position of BRGEN field.
	COMP_COMP_C3CSR_BRGEN_Msk            = 0x400000   // Bit mask of BRGEN field.
	COMP_COMP_C3CSR_BRGEN                = 0x400000   // Bit BRGEN.
	COMP_COMP_C3CSR_SCALEN_Pos           = 0x17       // Position of SCALEN field.
	COMP_COMP_C3CSR_SCALEN_Msk           = 0x800000   // Bit mask of SCALEN field.
	COMP_COMP_C3CSR_SCALEN               = 0x800000   // Bit SCALEN.
	COMP_COMP_C3CSR_VALUE_Pos            = 0x1e       // Position of VALUE field.
	COMP_COMP_C3CSR_VALUE_Msk            = 0x40000000 // Bit mask of VALUE field.
	COMP_COMP_C3CSR_VALUE                = 0x40000000 // Bit VALUE.
	COMP_COMP_C3CSR_LOCK_Pos             = 0x1f       // Position of LOCK field.
	COMP_COMP_C3CSR_LOCK_Msk             = 0x80000000 // Bit mask of LOCK field.
	COMP_COMP_C3CSR_LOCK                 = 0x80000000 // Bit LOCK.

	// COMP_C4CSR: Comparator control/status           register
	COMP_COMP_C4CSR_EN_Pos               = 0x0        // Position of EN field.
	COMP_COMP_C4CSR_EN_Msk               = 0x1        // Bit mask of EN field.
	COMP_COMP_C4CSR_EN                   = 0x1        // Bit EN.
	COMP_COMP_C4CSR_COMP_DEGLITCH_EN_Pos = 0x1        // Position of COMP_DEGLITCH_EN field.
	COMP_COMP_C4CSR_COMP_DEGLITCH_EN_Msk = 0x2        // Bit mask of COMP_DEGLITCH_EN field.
	COMP_COMP_C4CSR_COMP_DEGLITCH_EN     = 0x2        // Bit COMP_DEGLITCH_EN.
	COMP_COMP_C4CSR_INMSEL_Pos           = 0x4        // Position of INMSEL field.
	COMP_COMP_C4CSR_INMSEL_Msk           = 0x70       // Bit mask of INMSEL field.
	COMP_COMP_C4CSR_INPSEL_Pos           = 0x8        // Position of INPSEL field.
	COMP_COMP_C4CSR_INPSEL_Msk           = 0x100      // Bit mask of INPSEL field.
	COMP_COMP_C4CSR_INPSEL               = 0x100      // Bit INPSEL.
	COMP_COMP_C4CSR_POL_Pos              = 0xf        // Position of POL field.
	COMP_COMP_C4CSR_POL_Msk              = 0x8000     // Bit mask of POL field.
	COMP_COMP_C4CSR_POL                  = 0x8000     // Bit POL.
	COMP_COMP_C4CSR_HYST_Pos             = 0x10       // Position of HYST field.
	COMP_COMP_C4CSR_HYST_Msk             = 0x70000    // Bit mask of HYST field.
	COMP_COMP_C4CSR_BLANKSEL_Pos         = 0x13       // Position of BLANKSEL field.
	COMP_COMP_C4CSR_BLANKSEL_Msk         = 0x380000   // Bit mask of BLANKSEL field.
	COMP_COMP_C4CSR_BRGEN_Pos            = 0x16       // Position of BRGEN field.
	COMP_COMP_C4CSR_BRGEN_Msk            = 0x400000   // Bit mask of BRGEN field.
	COMP_COMP_C4CSR_BRGEN                = 0x400000   // Bit BRGEN.
	COMP_COMP_C4CSR_SCALEN_Pos           = 0x17       // Position of SCALEN field.
	COMP_COMP_C4CSR_SCALEN_Msk           = 0x800000   // Bit mask of SCALEN field.
	COMP_COMP_C4CSR_SCALEN               = 0x800000   // Bit SCALEN.
	COMP_COMP_C4CSR_VALUE_Pos            = 0x1e       // Position of VALUE field.
	COMP_COMP_C4CSR_VALUE_Msk            = 0x40000000 // Bit mask of VALUE field.
	COMP_COMP_C4CSR_VALUE                = 0x40000000 // Bit VALUE.
	COMP_COMP_C4CSR_LOCK_Pos             = 0x1f       // Position of LOCK field.
	COMP_COMP_C4CSR_LOCK_Msk             = 0x80000000 // Bit mask of LOCK field.
	COMP_COMP_C4CSR_LOCK                 = 0x80000000 // Bit LOCK.

	// COMP_C5CSR: Comparator control/status           register
	COMP_COMP_C5CSR_EN_Pos               = 0x0        // Position of EN field.
	COMP_COMP_C5CSR_EN_Msk               = 0x1        // Bit mask of EN field.
	COMP_COMP_C5CSR_EN                   = 0x1        // Bit EN.
	COMP_COMP_C5CSR_COMP_DEGLITCH_EN_Pos = 0x1        // Position of COMP_DEGLITCH_EN field.
	COMP_COMP_C5CSR_COMP_DEGLITCH_EN_Msk = 0x2        // Bit mask of COMP_DEGLITCH_EN field.
	COMP_COMP_C5CSR_COMP_DEGLITCH_EN     = 0x2        // Bit COMP_DEGLITCH_EN.
	COMP_COMP_C5CSR_INMSEL_Pos           = 0x4        // Position of INMSEL field.
	COMP_COMP_C5CSR_INMSEL_Msk           = 0x70       // Bit mask of INMSEL field.
	COMP_COMP_C5CSR_INPSEL_Pos           = 0x8        // Position of INPSEL field.
	COMP_COMP_C5CSR_INPSEL_Msk           = 0x100      // Bit mask of INPSEL field.
	COMP_COMP_C5CSR_INPSEL               = 0x100      // Bit INPSEL.
	COMP_COMP_C5CSR_POL_Pos              = 0xf        // Position of POL field.
	COMP_COMP_C5CSR_POL_Msk              = 0x8000     // Bit mask of POL field.
	COMP_COMP_C5CSR_POL                  = 0x8000     // Bit POL.
	COMP_COMP_C5CSR_HYST_Pos             = 0x10       // Position of HYST field.
	COMP_COMP_C5CSR_HYST_Msk             = 0x70000    // Bit mask of HYST field.
	COMP_COMP_C5CSR_BLANKSEL_Pos         = 0x13       // Position of BLANKSEL field.
	COMP_COMP_C5CSR_BLANKSEL_Msk         = 0x380000   // Bit mask of BLANKSEL field.
	COMP_COMP_C5CSR_BRGEN_Pos            = 0x16       // Position of BRGEN field.
	COMP_COMP_C5CSR_BRGEN_Msk            = 0x400000   // Bit mask of BRGEN field.
	COMP_COMP_C5CSR_BRGEN                = 0x400000   // Bit BRGEN.
	COMP_COMP_C5CSR_SCALEN_Pos           = 0x17       // Position of SCALEN field.
	COMP_COMP_C5CSR_SCALEN_Msk           = 0x800000   // Bit mask of SCALEN field.
	COMP_COMP_C5CSR_SCALEN               = 0x800000   // Bit SCALEN.
	COMP_COMP_C5CSR_VALUE_Pos            = 0x1e       // Position of VALUE field.
	COMP_COMP_C5CSR_VALUE_Msk            = 0x40000000 // Bit mask of VALUE field.
	COMP_COMP_C5CSR_VALUE                = 0x40000000 // Bit VALUE.
	COMP_COMP_C5CSR_LOCK_Pos             = 0x1f       // Position of LOCK field.
	COMP_COMP_C5CSR_LOCK_Msk             = 0x80000000 // Bit mask of LOCK field.
	COMP_COMP_C5CSR_LOCK                 = 0x80000000 // Bit LOCK.

	// COMP_C6CSR: Comparator control/status           register
	COMP_COMP_C6CSR_EN_Pos               = 0x0        // Position of EN field.
	COMP_COMP_C6CSR_EN_Msk               = 0x1        // Bit mask of EN field.
	COMP_COMP_C6CSR_EN                   = 0x1        // Bit EN.
	COMP_COMP_C6CSR_COMP_DEGLITCH_EN_Pos = 0x1        // Position of COMP_DEGLITCH_EN field.
	COMP_COMP_C6CSR_COMP_DEGLITCH_EN_Msk = 0x2        // Bit mask of COMP_DEGLITCH_EN field.
	COMP_COMP_C6CSR_COMP_DEGLITCH_EN     = 0x2        // Bit COMP_DEGLITCH_EN.
	COMP_COMP_C6CSR_INMSEL_Pos           = 0x4        // Position of INMSEL field.
	COMP_COMP_C6CSR_INMSEL_Msk           = 0x70       // Bit mask of INMSEL field.
	COMP_COMP_C6CSR_INPSEL_Pos           = 0x8        // Position of INPSEL field.
	COMP_COMP_C6CSR_INPSEL_Msk           = 0x100      // Bit mask of INPSEL field.
	COMP_COMP_C6CSR_INPSEL               = 0x100      // Bit INPSEL.
	COMP_COMP_C6CSR_POL_Pos              = 0xf        // Position of POL field.
	COMP_COMP_C6CSR_POL_Msk              = 0x8000     // Bit mask of POL field.
	COMP_COMP_C6CSR_POL                  = 0x8000     // Bit POL.
	COMP_COMP_C6CSR_HYST_Pos             = 0x10       // Position of HYST field.
	COMP_COMP_C6CSR_HYST_Msk             = 0x70000    // Bit mask of HYST field.
	COMP_COMP_C6CSR_BLANKSEL_Pos         = 0x13       // Position of BLANKSEL field.
	COMP_COMP_C6CSR_BLANKSEL_Msk         = 0x380000   // Bit mask of BLANKSEL field.
	COMP_COMP_C6CSR_BRGEN_Pos            = 0x16       // Position of BRGEN field.
	COMP_COMP_C6CSR_BRGEN_Msk            = 0x400000   // Bit mask of BRGEN field.
	COMP_COMP_C6CSR_BRGEN                = 0x400000   // Bit BRGEN.
	COMP_COMP_C6CSR_SCALEN_Pos           = 0x17       // Position of SCALEN field.
	COMP_COMP_C6CSR_SCALEN_Msk           = 0x800000   // Bit mask of SCALEN field.
	COMP_COMP_C6CSR_SCALEN               = 0x800000   // Bit SCALEN.
	COMP_COMP_C6CSR_VALUE_Pos            = 0x1e       // Position of VALUE field.
	COMP_COMP_C6CSR_VALUE_Msk            = 0x40000000 // Bit mask of VALUE field.
	COMP_COMP_C6CSR_VALUE                = 0x40000000 // Bit VALUE.
	COMP_COMP_C6CSR_LOCK_Pos             = 0x1f       // Position of LOCK field.
	COMP_COMP_C6CSR_LOCK_Msk             = 0x80000000 // Bit mask of LOCK field.
	COMP_COMP_C6CSR_LOCK                 = 0x80000000 // Bit LOCK.

	// COMP_C7CSR: Comparator control/status           register
	COMP_COMP_C7CSR_EN_Pos               = 0x0        // Position of EN field.
	COMP_COMP_C7CSR_EN_Msk               = 0x1        // Bit mask of EN field.
	COMP_COMP_C7CSR_EN                   = 0x1        // Bit EN.
	COMP_COMP_C7CSR_COMP_DEGLITCH_EN_Pos = 0x1        // Position of COMP_DEGLITCH_EN field.
	COMP_COMP_C7CSR_COMP_DEGLITCH_EN_Msk = 0x2        // Bit mask of COMP_DEGLITCH_EN field.
	COMP_COMP_C7CSR_COMP_DEGLITCH_EN     = 0x2        // Bit COMP_DEGLITCH_EN.
	COMP_COMP_C7CSR_INMSEL_Pos           = 0x4        // Position of INMSEL field.
	COMP_COMP_C7CSR_INMSEL_Msk           = 0x70       // Bit mask of INMSEL field.
	COMP_COMP_C7CSR_INPSEL_Pos           = 0x8        // Position of INPSEL field.
	COMP_COMP_C7CSR_INPSEL_Msk           = 0x100      // Bit mask of INPSEL field.
	COMP_COMP_C7CSR_INPSEL               = 0x100      // Bit INPSEL.
	COMP_COMP_C7CSR_POL_Pos              = 0xf        // Position of POL field.
	COMP_COMP_C7CSR_POL_Msk              = 0x8000     // Bit mask of POL field.
	COMP_COMP_C7CSR_POL                  = 0x8000     // Bit POL.
	COMP_COMP_C7CSR_HYST_Pos             = 0x10       // Position of HYST field.
	COMP_COMP_C7CSR_HYST_Msk             = 0x70000    // Bit mask of HYST field.
	COMP_COMP_C7CSR_BLANKSEL_Pos         = 0x13       // Position of BLANKSEL field.
	COMP_COMP_C7CSR_BLANKSEL_Msk         = 0x380000   // Bit mask of BLANKSEL field.
	COMP_COMP_C7CSR_BRGEN_Pos            = 0x16       // Position of BRGEN field.
	COMP_COMP_C7CSR_BRGEN_Msk            = 0x400000   // Bit mask of BRGEN field.
	COMP_COMP_C7CSR_BRGEN                = 0x400000   // Bit BRGEN.
	COMP_COMP_C7CSR_SCALEN_Pos           = 0x17       // Position of SCALEN field.
	COMP_COMP_C7CSR_SCALEN_Msk           = 0x800000   // Bit mask of SCALEN field.
	COMP_COMP_C7CSR_SCALEN               = 0x800000   // Bit SCALEN.
	COMP_COMP_C7CSR_VALUE_Pos            = 0x1e       // Position of VALUE field.
	COMP_COMP_C7CSR_VALUE_Msk            = 0x40000000 // Bit mask of VALUE field.
	COMP_COMP_C7CSR_VALUE                = 0x40000000 // Bit VALUE.
	COMP_COMP_C7CSR_LOCK_Pos             = 0x1f       // Position of LOCK field.
	COMP_COMP_C7CSR_LOCK_Msk             = 0x80000000 // Bit mask of LOCK field.
	COMP_COMP_C7CSR_LOCK                 = 0x80000000 // Bit LOCK.
)

// Bitfields for OPAMP: Operational amplifiers
const (
	// OPAMP1_CSR: OPAMP1 control/status register
	OPAMP_OPAMP1_CSR_OPAEN_Pos       = 0x0        // Position of OPAEN field.
	OPAMP_OPAMP1_CSR_OPAEN_Msk       = 0x1        // Bit mask of OPAEN field.
	OPAMP_OPAMP1_CSR_OPAEN           = 0x1        // Bit OPAEN.
	OPAMP_OPAMP1_CSR_FORCE_VP_Pos    = 0x1        // Position of FORCE_VP field.
	OPAMP_OPAMP1_CSR_FORCE_VP_Msk    = 0x2        // Bit mask of FORCE_VP field.
	OPAMP_OPAMP1_CSR_FORCE_VP        = 0x2        // Bit FORCE_VP.
	OPAMP_OPAMP1_CSR_VP_SEL_Pos      = 0x2        // Position of VP_SEL field.
	OPAMP_OPAMP1_CSR_VP_SEL_Msk      = 0xc        // Bit mask of VP_SEL field.
	OPAMP_OPAMP1_CSR_USERTRIM_Pos    = 0x4        // Position of USERTRIM field.
	OPAMP_OPAMP1_CSR_USERTRIM_Msk    = 0x10       // Bit mask of USERTRIM field.
	OPAMP_OPAMP1_CSR_USERTRIM        = 0x10       // Bit USERTRIM.
	OPAMP_OPAMP1_CSR_VM_SEL_Pos      = 0x5        // Position of VM_SEL field.
	OPAMP_OPAMP1_CSR_VM_SEL_Msk      = 0x60       // Bit mask of VM_SEL field.
	OPAMP_OPAMP1_CSR_OPAHSM_Pos      = 0x7        // Position of OPAHSM field.
	OPAMP_OPAMP1_CSR_OPAHSM_Msk      = 0x80       // Bit mask of OPAHSM field.
	OPAMP_OPAMP1_CSR_OPAHSM          = 0x80       // Bit OPAHSM.
	OPAMP_OPAMP1_CSR_OPAINTOEN_Pos   = 0x8        // Position of OPAINTOEN field.
	OPAMP_OPAMP1_CSR_OPAINTOEN_Msk   = 0x100      // Bit mask of OPAINTOEN field.
	OPAMP_OPAMP1_CSR_OPAINTOEN       = 0x100      // Bit OPAINTOEN.
	OPAMP_OPAMP1_CSR_CALON_Pos       = 0xb        // Position of CALON field.
	OPAMP_OPAMP1_CSR_CALON_Msk       = 0x800      // Bit mask of CALON field.
	OPAMP_OPAMP1_CSR_CALON           = 0x800      // Bit CALON.
	OPAMP_OPAMP1_CSR_CALSEL_Pos      = 0xc        // Position of CALSEL field.
	OPAMP_OPAMP1_CSR_CALSEL_Msk      = 0x3000     // Bit mask of CALSEL field.
	OPAMP_OPAMP1_CSR_PGA_GAIN_Pos    = 0xe        // Position of PGA_GAIN field.
	OPAMP_OPAMP1_CSR_PGA_GAIN_Msk    = 0x7c000    // Bit mask of PGA_GAIN field.
	OPAMP_OPAMP1_CSR_TRIMOFFSETP_Pos = 0x13       // Position of TRIMOFFSETP field.
	OPAMP_OPAMP1_CSR_TRIMOFFSETP_Msk = 0xf80000   // Bit mask of TRIMOFFSETP field.
	OPAMP_OPAMP1_CSR_TRIMOFFSETN_Pos = 0x18       // Position of TRIMOFFSETN field.
	OPAMP_OPAMP1_CSR_TRIMOFFSETN_Msk = 0x1f000000 // Bit mask of TRIMOFFSETN field.
	OPAMP_OPAMP1_CSR_CALOUT_Pos      = 0x1e       // Position of CALOUT field.
	OPAMP_OPAMP1_CSR_CALOUT_Msk      = 0x40000000 // Bit mask of CALOUT field.
	OPAMP_OPAMP1_CSR_CALOUT          = 0x40000000 // Bit CALOUT.
	OPAMP_OPAMP1_CSR_LOCK_Pos        = 0x1f       // Position of LOCK field.
	OPAMP_OPAMP1_CSR_LOCK_Msk        = 0x80000000 // Bit mask of LOCK field.
	OPAMP_OPAMP1_CSR_LOCK            = 0x80000000 // Bit LOCK.

	// OPAMP2_CSR: OPAMP2 control/status register
	OPAMP_OPAMP2_CSR_OPAEN_Pos       = 0x0        // Position of OPAEN field.
	OPAMP_OPAMP2_CSR_OPAEN_Msk       = 0x1        // Bit mask of OPAEN field.
	OPAMP_OPAMP2_CSR_OPAEN           = 0x1        // Bit OPAEN.
	OPAMP_OPAMP2_CSR_FORCE_VP_Pos    = 0x1        // Position of FORCE_VP field.
	OPAMP_OPAMP2_CSR_FORCE_VP_Msk    = 0x2        // Bit mask of FORCE_VP field.
	OPAMP_OPAMP2_CSR_FORCE_VP        = 0x2        // Bit FORCE_VP.
	OPAMP_OPAMP2_CSR_VP_SEL_Pos      = 0x2        // Position of VP_SEL field.
	OPAMP_OPAMP2_CSR_VP_SEL_Msk      = 0xc        // Bit mask of VP_SEL field.
	OPAMP_OPAMP2_CSR_USERTRIM_Pos    = 0x4        // Position of USERTRIM field.
	OPAMP_OPAMP2_CSR_USERTRIM_Msk    = 0x10       // Bit mask of USERTRIM field.
	OPAMP_OPAMP2_CSR_USERTRIM        = 0x10       // Bit USERTRIM.
	OPAMP_OPAMP2_CSR_VM_SEL_Pos      = 0x5        // Position of VM_SEL field.
	OPAMP_OPAMP2_CSR_VM_SEL_Msk      = 0x60       // Bit mask of VM_SEL field.
	OPAMP_OPAMP2_CSR_OPAHSM_Pos      = 0x7        // Position of OPAHSM field.
	OPAMP_OPAMP2_CSR_OPAHSM_Msk      = 0x80       // Bit mask of OPAHSM field.
	OPAMP_OPAMP2_CSR_OPAHSM          = 0x80       // Bit OPAHSM.
	OPAMP_OPAMP2_CSR_OPAINTOEN_Pos   = 0x8        // Position of OPAINTOEN field.
	OPAMP_OPAMP2_CSR_OPAINTOEN_Msk   = 0x100      // Bit mask of OPAINTOEN field.
	OPAMP_OPAMP2_CSR_OPAINTOEN       = 0x100      // Bit OPAINTOEN.
	OPAMP_OPAMP2_CSR_CALON_Pos       = 0xb        // Position of CALON field.
	OPAMP_OPAMP2_CSR_CALON_Msk       = 0x800      // Bit mask of CALON field.
	OPAMP_OPAMP2_CSR_CALON           = 0x800      // Bit CALON.
	OPAMP_OPAMP2_CSR_CALSEL_Pos      = 0xc        // Position of CALSEL field.
	OPAMP_OPAMP2_CSR_CALSEL_Msk      = 0x3000     // Bit mask of CALSEL field.
	OPAMP_OPAMP2_CSR_PGA_GAIN_Pos    = 0xe        // Position of PGA_GAIN field.
	OPAMP_OPAMP2_CSR_PGA_GAIN_Msk    = 0x7c000    // Bit mask of PGA_GAIN field.
	OPAMP_OPAMP2_CSR_TRIMOFFSETP_Pos = 0x13       // Position of TRIMOFFSETP field.
	OPAMP_OPAMP2_CSR_TRIMOFFSETP_Msk = 0xf80000   // Bit mask of TRIMOFFSETP field.
	OPAMP_OPAMP2_CSR_TRIMOFFSETN_Pos = 0x18       // Position of TRIMOFFSETN field.
	OPAMP_OPAMP2_CSR_TRIMOFFSETN_Msk = 0x1f000000 // Bit mask of TRIMOFFSETN field.
	OPAMP_OPAMP2_CSR_CALOUT_Pos      = 0x1e       // Position of CALOUT field.
	OPAMP_OPAMP2_CSR_CALOUT_Msk      = 0x40000000 // Bit mask of CALOUT field.
	OPAMP_OPAMP2_CSR_CALOUT          = 0x40000000 // Bit CALOUT.
	OPAMP_OPAMP2_CSR_LOCK_Pos        = 0x1f       // Position of LOCK field.
	OPAMP_OPAMP2_CSR_LOCK_Msk        = 0x80000000 // Bit mask of LOCK field.
	OPAMP_OPAMP2_CSR_LOCK            = 0x80000000 // Bit LOCK.

	// OPAMP3_CSR: OPAMP3 control/status register
	OPAMP_OPAMP3_CSR_OPAEN_Pos       = 0x0        // Position of OPAEN field.
	OPAMP_OPAMP3_CSR_OPAEN_Msk       = 0x1        // Bit mask of OPAEN field.
	OPAMP_OPAMP3_CSR_OPAEN           = 0x1        // Bit OPAEN.
	OPAMP_OPAMP3_CSR_FORCE_VP_Pos    = 0x1        // Position of FORCE_VP field.
	OPAMP_OPAMP3_CSR_FORCE_VP_Msk    = 0x2        // Bit mask of FORCE_VP field.
	OPAMP_OPAMP3_CSR_FORCE_VP        = 0x2        // Bit FORCE_VP.
	OPAMP_OPAMP3_CSR_VP_SEL_Pos      = 0x2        // Position of VP_SEL field.
	OPAMP_OPAMP3_CSR_VP_SEL_Msk      = 0xc        // Bit mask of VP_SEL field.
	OPAMP_OPAMP3_CSR_USERTRIM_Pos    = 0x4        // Position of USERTRIM field.
	OPAMP_OPAMP3_CSR_USERTRIM_Msk    = 0x10       // Bit mask of USERTRIM field.
	OPAMP_OPAMP3_CSR_USERTRIM        = 0x10       // Bit USERTRIM.
	OPAMP_OPAMP3_CSR_VM_SEL_Pos      = 0x5        // Position of VM_SEL field.
	OPAMP_OPAMP3_CSR_VM_SEL_Msk      = 0x60       // Bit mask of VM_SEL field.
	OPAMP_OPAMP3_CSR_OPAHSM_Pos      = 0x7        // Position of OPAHSM field.
	OPAMP_OPAMP3_CSR_OPAHSM_Msk      = 0x80       // Bit mask of OPAHSM field.
	OPAMP_OPAMP3_CSR_OPAHSM          = 0x80       // Bit OPAHSM.
	OPAMP_OPAMP3_CSR_OPAINTOEN_Pos   = 0x8        // Position of OPAINTOEN field.
	OPAMP_OPAMP3_CSR_OPAINTOEN_Msk   = 0x100      // Bit mask of OPAINTOEN field.
	OPAMP_OPAMP3_CSR_OPAINTOEN       = 0x100      // Bit OPAINTOEN.
	OPAMP_OPAMP3_CSR_CALON_Pos       = 0xb        // Position of CALON field.
	OPAMP_OPAMP3_CSR_CALON_Msk       = 0x800      // Bit mask of CALON field.
	OPAMP_OPAMP3_CSR_CALON           = 0x800      // Bit CALON.
	OPAMP_OPAMP3_CSR_CALSEL_Pos      = 0xc        // Position of CALSEL field.
	OPAMP_OPAMP3_CSR_CALSEL_Msk      = 0x3000     // Bit mask of CALSEL field.
	OPAMP_OPAMP3_CSR_PGA_GAIN_Pos    = 0xe        // Position of PGA_GAIN field.
	OPAMP_OPAMP3_CSR_PGA_GAIN_Msk    = 0x7c000    // Bit mask of PGA_GAIN field.
	OPAMP_OPAMP3_CSR_TRIMOFFSETP_Pos = 0x13       // Position of TRIMOFFSETP field.
	OPAMP_OPAMP3_CSR_TRIMOFFSETP_Msk = 0xf80000   // Bit mask of TRIMOFFSETP field.
	OPAMP_OPAMP3_CSR_TRIMOFFSETN_Pos = 0x18       // Position of TRIMOFFSETN field.
	OPAMP_OPAMP3_CSR_TRIMOFFSETN_Msk = 0x1f000000 // Bit mask of TRIMOFFSETN field.
	OPAMP_OPAMP3_CSR_CALOUT_Pos      = 0x1e       // Position of CALOUT field.
	OPAMP_OPAMP3_CSR_CALOUT_Msk      = 0x40000000 // Bit mask of CALOUT field.
	OPAMP_OPAMP3_CSR_CALOUT          = 0x40000000 // Bit CALOUT.
	OPAMP_OPAMP3_CSR_LOCK_Pos        = 0x1f       // Position of LOCK field.
	OPAMP_OPAMP3_CSR_LOCK_Msk        = 0x80000000 // Bit mask of LOCK field.
	OPAMP_OPAMP3_CSR_LOCK            = 0x80000000 // Bit LOCK.

	// OPAMP4_CSR: OPAMP4 control/status register
	OPAMP_OPAMP4_CSR_OPAEN_Pos       = 0x0        // Position of OPAEN field.
	OPAMP_OPAMP4_CSR_OPAEN_Msk       = 0x1        // Bit mask of OPAEN field.
	OPAMP_OPAMP4_CSR_OPAEN           = 0x1        // Bit OPAEN.
	OPAMP_OPAMP4_CSR_FORCE_VP_Pos    = 0x1        // Position of FORCE_VP field.
	OPAMP_OPAMP4_CSR_FORCE_VP_Msk    = 0x2        // Bit mask of FORCE_VP field.
	OPAMP_OPAMP4_CSR_FORCE_VP        = 0x2        // Bit FORCE_VP.
	OPAMP_OPAMP4_CSR_VP_SEL_Pos      = 0x2        // Position of VP_SEL field.
	OPAMP_OPAMP4_CSR_VP_SEL_Msk      = 0xc        // Bit mask of VP_SEL field.
	OPAMP_OPAMP4_CSR_USERTRIM_Pos    = 0x4        // Position of USERTRIM field.
	OPAMP_OPAMP4_CSR_USERTRIM_Msk    = 0x10       // Bit mask of USERTRIM field.
	OPAMP_OPAMP4_CSR_USERTRIM        = 0x10       // Bit USERTRIM.
	OPAMP_OPAMP4_CSR_VM_SEL_Pos      = 0x5        // Position of VM_SEL field.
	OPAMP_OPAMP4_CSR_VM_SEL_Msk      = 0x60       // Bit mask of VM_SEL field.
	OPAMP_OPAMP4_CSR_OPAHSM_Pos      = 0x7        // Position of OPAHSM field.
	OPAMP_OPAMP4_CSR_OPAHSM_Msk      = 0x80       // Bit mask of OPAHSM field.
	OPAMP_OPAMP4_CSR_OPAHSM          = 0x80       // Bit OPAHSM.
	OPAMP_OPAMP4_CSR_OPAINTOEN_Pos   = 0x8        // Position of OPAINTOEN field.
	OPAMP_OPAMP4_CSR_OPAINTOEN_Msk   = 0x100      // Bit mask of OPAINTOEN field.
	OPAMP_OPAMP4_CSR_OPAINTOEN       = 0x100      // Bit OPAINTOEN.
	OPAMP_OPAMP4_CSR_CALON_Pos       = 0xb        // Position of CALON field.
	OPAMP_OPAMP4_CSR_CALON_Msk       = 0x800      // Bit mask of CALON field.
	OPAMP_OPAMP4_CSR_CALON           = 0x800      // Bit CALON.
	OPAMP_OPAMP4_CSR_CALSEL_Pos      = 0xc        // Position of CALSEL field.
	OPAMP_OPAMP4_CSR_CALSEL_Msk      = 0x3000     // Bit mask of CALSEL field.
	OPAMP_OPAMP4_CSR_PGA_GAIN_Pos    = 0xe        // Position of PGA_GAIN field.
	OPAMP_OPAMP4_CSR_PGA_GAIN_Msk    = 0x7c000    // Bit mask of PGA_GAIN field.
	OPAMP_OPAMP4_CSR_TRIMOFFSETP_Pos = 0x13       // Position of TRIMOFFSETP field.
	OPAMP_OPAMP4_CSR_TRIMOFFSETP_Msk = 0xf80000   // Bit mask of TRIMOFFSETP field.
	OPAMP_OPAMP4_CSR_TRIMOFFSETN_Pos = 0x18       // Position of TRIMOFFSETN field.
	OPAMP_OPAMP4_CSR_TRIMOFFSETN_Msk = 0x1f000000 // Bit mask of TRIMOFFSETN field.
	OPAMP_OPAMP4_CSR_CALOUT_Pos      = 0x1e       // Position of CALOUT field.
	OPAMP_OPAMP4_CSR_CALOUT_Msk      = 0x40000000 // Bit mask of CALOUT field.
	OPAMP_OPAMP4_CSR_CALOUT          = 0x40000000 // Bit CALOUT.
	OPAMP_OPAMP4_CSR_LOCK_Pos        = 0x1f       // Position of LOCK field.
	OPAMP_OPAMP4_CSR_LOCK_Msk        = 0x80000000 // Bit mask of LOCK field.
	OPAMP_OPAMP4_CSR_LOCK            = 0x80000000 // Bit LOCK.

	// OPAMP5_CSR: OPAMP5 control/status register
	OPAMP_OPAMP5_CSR_OPAEN_Pos       = 0x0        // Position of OPAEN field.
	OPAMP_OPAMP5_CSR_OPAEN_Msk       = 0x1        // Bit mask of OPAEN field.
	OPAMP_OPAMP5_CSR_OPAEN           = 0x1        // Bit OPAEN.
	OPAMP_OPAMP5_CSR_FORCE_VP_Pos    = 0x1        // Position of FORCE_VP field.
	OPAMP_OPAMP5_CSR_FORCE_VP_Msk    = 0x2        // Bit mask of FORCE_VP field.
	OPAMP_OPAMP5_CSR_FORCE_VP        = 0x2        // Bit FORCE_VP.
	OPAMP_OPAMP5_CSR_VP_SEL_Pos      = 0x2        // Position of VP_SEL field.
	OPAMP_OPAMP5_CSR_VP_SEL_Msk      = 0xc        // Bit mask of VP_SEL field.
	OPAMP_OPAMP5_CSR_USERTRIM_Pos    = 0x4        // Position of USERTRIM field.
	OPAMP_OPAMP5_CSR_USERTRIM_Msk    = 0x10       // Bit mask of USERTRIM field.
	OPAMP_OPAMP5_CSR_USERTRIM        = 0x10       // Bit USERTRIM.
	OPAMP_OPAMP5_CSR_VM_SEL_Pos      = 0x5        // Position of VM_SEL field.
	OPAMP_OPAMP5_CSR_VM_SEL_Msk      = 0x60       // Bit mask of VM_SEL field.
	OPAMP_OPAMP5_CSR_OPAHSM_Pos      = 0x7        // Position of OPAHSM field.
	OPAMP_OPAMP5_CSR_OPAHSM_Msk      = 0x80       // Bit mask of OPAHSM field.
	OPAMP_OPAMP5_CSR_OPAHSM          = 0x80       // Bit OPAHSM.
	OPAMP_OPAMP5_CSR_OPAINTOEN_Pos   = 0x8        // Position of OPAINTOEN field.
	OPAMP_OPAMP5_CSR_OPAINTOEN_Msk   = 0x100      // Bit mask of OPAINTOEN field.
	OPAMP_OPAMP5_CSR_OPAINTOEN       = 0x100      // Bit OPAINTOEN.
	OPAMP_OPAMP5_CSR_CALON_Pos       = 0xb        // Position of CALON field.
	OPAMP_OPAMP5_CSR_CALON_Msk       = 0x800      // Bit mask of CALON field.
	OPAMP_OPAMP5_CSR_CALON           = 0x800      // Bit CALON.
	OPAMP_OPAMP5_CSR_CALSEL_Pos      = 0xc        // Position of CALSEL field.
	OPAMP_OPAMP5_CSR_CALSEL_Msk      = 0x3000     // Bit mask of CALSEL field.
	OPAMP_OPAMP5_CSR_PGA_GAIN_Pos    = 0xe        // Position of PGA_GAIN field.
	OPAMP_OPAMP5_CSR_PGA_GAIN_Msk    = 0x7c000    // Bit mask of PGA_GAIN field.
	OPAMP_OPAMP5_CSR_TRIMOFFSETP_Pos = 0x13       // Position of TRIMOFFSETP field.
	OPAMP_OPAMP5_CSR_TRIMOFFSETP_Msk = 0xf80000   // Bit mask of TRIMOFFSETP field.
	OPAMP_OPAMP5_CSR_TRIMOFFSETN_Pos = 0x18       // Position of TRIMOFFSETN field.
	OPAMP_OPAMP5_CSR_TRIMOFFSETN_Msk = 0x1f000000 // Bit mask of TRIMOFFSETN field.
	OPAMP_OPAMP5_CSR_CALOUT_Pos      = 0x1e       // Position of CALOUT field.
	OPAMP_OPAMP5_CSR_CALOUT_Msk      = 0x40000000 // Bit mask of CALOUT field.
	OPAMP_OPAMP5_CSR_CALOUT          = 0x40000000 // Bit CALOUT.
	OPAMP_OPAMP5_CSR_LOCK_Pos        = 0x1f       // Position of LOCK field.
	OPAMP_OPAMP5_CSR_LOCK_Msk        = 0x80000000 // Bit mask of LOCK field.
	OPAMP_OPAMP5_CSR_LOCK            = 0x80000000 // Bit LOCK.

	// OPAMP6_CSR: OPAMP6 control/status register
	OPAMP_OPAMP6_CSR_OPAEN_Pos       = 0x0        // Position of OPAEN field.
	OPAMP_OPAMP6_CSR_OPAEN_Msk       = 0x1        // Bit mask of OPAEN field.
	OPAMP_OPAMP6_CSR_OPAEN           = 0x1        // Bit OPAEN.
	OPAMP_OPAMP6_CSR_FORCE_VP_Pos    = 0x1        // Position of FORCE_VP field.
	OPAMP_OPAMP6_CSR_FORCE_VP_Msk    = 0x2        // Bit mask of FORCE_VP field.
	OPAMP_OPAMP6_CSR_FORCE_VP        = 0x2        // Bit FORCE_VP.
	OPAMP_OPAMP6_CSR_VP_SEL_Pos      = 0x2        // Position of VP_SEL field.
	OPAMP_OPAMP6_CSR_VP_SEL_Msk      = 0xc        // Bit mask of VP_SEL field.
	OPAMP_OPAMP6_CSR_USERTRIM_Pos    = 0x4        // Position of USERTRIM field.
	OPAMP_OPAMP6_CSR_USERTRIM_Msk    = 0x10       // Bit mask of USERTRIM field.
	OPAMP_OPAMP6_CSR_USERTRIM        = 0x10       // Bit USERTRIM.
	OPAMP_OPAMP6_CSR_VM_SEL_Pos      = 0x5        // Position of VM_SEL field.
	OPAMP_OPAMP6_CSR_VM_SEL_Msk      = 0x60       // Bit mask of VM_SEL field.
	OPAMP_OPAMP6_CSR_OPAHSM_Pos      = 0x7        // Position of OPAHSM field.
	OPAMP_OPAMP6_CSR_OPAHSM_Msk      = 0x80       // Bit mask of OPAHSM field.
	OPAMP_OPAMP6_CSR_OPAHSM          = 0x80       // Bit OPAHSM.
	OPAMP_OPAMP6_CSR_OPAINTOEN_Pos   = 0x8        // Position of OPAINTOEN field.
	OPAMP_OPAMP6_CSR_OPAINTOEN_Msk   = 0x100      // Bit mask of OPAINTOEN field.
	OPAMP_OPAMP6_CSR_OPAINTOEN       = 0x100      // Bit OPAINTOEN.
	OPAMP_OPAMP6_CSR_CALON_Pos       = 0xb        // Position of CALON field.
	OPAMP_OPAMP6_CSR_CALON_Msk       = 0x800      // Bit mask of CALON field.
	OPAMP_OPAMP6_CSR_CALON           = 0x800      // Bit CALON.
	OPAMP_OPAMP6_CSR_CALSEL_Pos      = 0xc        // Position of CALSEL field.
	OPAMP_OPAMP6_CSR_CALSEL_Msk      = 0x3000     // Bit mask of CALSEL field.
	OPAMP_OPAMP6_CSR_PGA_GAIN_Pos    = 0xe        // Position of PGA_GAIN field.
	OPAMP_OPAMP6_CSR_PGA_GAIN_Msk    = 0x7c000    // Bit mask of PGA_GAIN field.
	OPAMP_OPAMP6_CSR_TRIMOFFSETP_Pos = 0x13       // Position of TRIMOFFSETP field.
	OPAMP_OPAMP6_CSR_TRIMOFFSETP_Msk = 0xf80000   // Bit mask of TRIMOFFSETP field.
	OPAMP_OPAMP6_CSR_TRIMOFFSETN_Pos = 0x18       // Position of TRIMOFFSETN field.
	OPAMP_OPAMP6_CSR_TRIMOFFSETN_Msk = 0x1f000000 // Bit mask of TRIMOFFSETN field.
	OPAMP_OPAMP6_CSR_CALOUT_Pos      = 0x1e       // Position of CALOUT field.
	OPAMP_OPAMP6_CSR_CALOUT_Msk      = 0x40000000 // Bit mask of CALOUT field.
	OPAMP_OPAMP6_CSR_CALOUT          = 0x40000000 // Bit CALOUT.
	OPAMP_OPAMP6_CSR_LOCK_Pos        = 0x1f       // Position of LOCK field.
	OPAMP_OPAMP6_CSR_LOCK_Msk        = 0x80000000 // Bit mask of LOCK field.
	OPAMP_OPAMP6_CSR_LOCK            = 0x80000000 // Bit LOCK.

	// OPAMP1_TCMR: OPAMP1 control/status register
	OPAMP_OPAMP1_TCMR_VMS_SEL_Pos  = 0x0        // Position of VMS_SEL field.
	OPAMP_OPAMP1_TCMR_VMS_SEL_Msk  = 0x1        // Bit mask of VMS_SEL field.
	OPAMP_OPAMP1_TCMR_VMS_SEL      = 0x1        // Bit VMS_SEL.
	OPAMP_OPAMP1_TCMR_VPS_SEL_Pos  = 0x1        // Position of VPS_SEL field.
	OPAMP_OPAMP1_TCMR_VPS_SEL_Msk  = 0x6        // Bit mask of VPS_SEL field.
	OPAMP_OPAMP1_TCMR_T1CM_EN_Pos  = 0x3        // Position of T1CM_EN field.
	OPAMP_OPAMP1_TCMR_T1CM_EN_Msk  = 0x8        // Bit mask of T1CM_EN field.
	OPAMP_OPAMP1_TCMR_T1CM_EN      = 0x8        // Bit T1CM_EN.
	OPAMP_OPAMP1_TCMR_T8CM_EN_Pos  = 0x4        // Position of T8CM_EN field.
	OPAMP_OPAMP1_TCMR_T8CM_EN_Msk  = 0x10       // Bit mask of T8CM_EN field.
	OPAMP_OPAMP1_TCMR_T8CM_EN      = 0x10       // Bit T8CM_EN.
	OPAMP_OPAMP1_TCMR_T20CM_EN_Pos = 0x5        // Position of T20CM_EN field.
	OPAMP_OPAMP1_TCMR_T20CM_EN_Msk = 0x20       // Bit mask of T20CM_EN field.
	OPAMP_OPAMP1_TCMR_T20CM_EN     = 0x20       // Bit T20CM_EN.
	OPAMP_OPAMP1_TCMR_LOCK_Pos     = 0x1f       // Position of LOCK field.
	OPAMP_OPAMP1_TCMR_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	OPAMP_OPAMP1_TCMR_LOCK         = 0x80000000 // Bit LOCK.

	// OPAMP2_TCMR: OPAMP2 control/status register
	OPAMP_OPAMP2_TCMR_VMS_SEL_Pos  = 0x0        // Position of VMS_SEL field.
	OPAMP_OPAMP2_TCMR_VMS_SEL_Msk  = 0x1        // Bit mask of VMS_SEL field.
	OPAMP_OPAMP2_TCMR_VMS_SEL      = 0x1        // Bit VMS_SEL.
	OPAMP_OPAMP2_TCMR_VPS_SEL_Pos  = 0x1        // Position of VPS_SEL field.
	OPAMP_OPAMP2_TCMR_VPS_SEL_Msk  = 0x6        // Bit mask of VPS_SEL field.
	OPAMP_OPAMP2_TCMR_T1CM_EN_Pos  = 0x3        // Position of T1CM_EN field.
	OPAMP_OPAMP2_TCMR_T1CM_EN_Msk  = 0x8        // Bit mask of T1CM_EN field.
	OPAMP_OPAMP2_TCMR_T1CM_EN      = 0x8        // Bit T1CM_EN.
	OPAMP_OPAMP2_TCMR_T8CM_EN_Pos  = 0x4        // Position of T8CM_EN field.
	OPAMP_OPAMP2_TCMR_T8CM_EN_Msk  = 0x10       // Bit mask of T8CM_EN field.
	OPAMP_OPAMP2_TCMR_T8CM_EN      = 0x10       // Bit T8CM_EN.
	OPAMP_OPAMP2_TCMR_T20CM_EN_Pos = 0x5        // Position of T20CM_EN field.
	OPAMP_OPAMP2_TCMR_T20CM_EN_Msk = 0x20       // Bit mask of T20CM_EN field.
	OPAMP_OPAMP2_TCMR_T20CM_EN     = 0x20       // Bit T20CM_EN.
	OPAMP_OPAMP2_TCMR_LOCK_Pos     = 0x1f       // Position of LOCK field.
	OPAMP_OPAMP2_TCMR_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	OPAMP_OPAMP2_TCMR_LOCK         = 0x80000000 // Bit LOCK.

	// OPAMP3_TCMR: OPAMP3 control/status register
	OPAMP_OPAMP3_TCMR_VMS_SEL_Pos  = 0x0        // Position of VMS_SEL field.
	OPAMP_OPAMP3_TCMR_VMS_SEL_Msk  = 0x1        // Bit mask of VMS_SEL field.
	OPAMP_OPAMP3_TCMR_VMS_SEL      = 0x1        // Bit VMS_SEL.
	OPAMP_OPAMP3_TCMR_VPS_SEL_Pos  = 0x1        // Position of VPS_SEL field.
	OPAMP_OPAMP3_TCMR_VPS_SEL_Msk  = 0x6        // Bit mask of VPS_SEL field.
	OPAMP_OPAMP3_TCMR_T1CM_EN_Pos  = 0x3        // Position of T1CM_EN field.
	OPAMP_OPAMP3_TCMR_T1CM_EN_Msk  = 0x8        // Bit mask of T1CM_EN field.
	OPAMP_OPAMP3_TCMR_T1CM_EN      = 0x8        // Bit T1CM_EN.
	OPAMP_OPAMP3_TCMR_T8CM_EN_Pos  = 0x4        // Position of T8CM_EN field.
	OPAMP_OPAMP3_TCMR_T8CM_EN_Msk  = 0x10       // Bit mask of T8CM_EN field.
	OPAMP_OPAMP3_TCMR_T8CM_EN      = 0x10       // Bit T8CM_EN.
	OPAMP_OPAMP3_TCMR_T20CM_EN_Pos = 0x5        // Position of T20CM_EN field.
	OPAMP_OPAMP3_TCMR_T20CM_EN_Msk = 0x20       // Bit mask of T20CM_EN field.
	OPAMP_OPAMP3_TCMR_T20CM_EN     = 0x20       // Bit T20CM_EN.
	OPAMP_OPAMP3_TCMR_LOCK_Pos     = 0x1f       // Position of LOCK field.
	OPAMP_OPAMP3_TCMR_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	OPAMP_OPAMP3_TCMR_LOCK         = 0x80000000 // Bit LOCK.

	// OPAMP4_TCMR: OPAMP4 control/status register
	OPAMP_OPAMP4_TCMR_VMS_SEL_Pos  = 0x0        // Position of VMS_SEL field.
	OPAMP_OPAMP4_TCMR_VMS_SEL_Msk  = 0x1        // Bit mask of VMS_SEL field.
	OPAMP_OPAMP4_TCMR_VMS_SEL      = 0x1        // Bit VMS_SEL.
	OPAMP_OPAMP4_TCMR_VPS_SEL_Pos  = 0x1        // Position of VPS_SEL field.
	OPAMP_OPAMP4_TCMR_VPS_SEL_Msk  = 0x6        // Bit mask of VPS_SEL field.
	OPAMP_OPAMP4_TCMR_T1CM_EN_Pos  = 0x3        // Position of T1CM_EN field.
	OPAMP_OPAMP4_TCMR_T1CM_EN_Msk  = 0x8        // Bit mask of T1CM_EN field.
	OPAMP_OPAMP4_TCMR_T1CM_EN      = 0x8        // Bit T1CM_EN.
	OPAMP_OPAMP4_TCMR_T8CM_EN_Pos  = 0x4        // Position of T8CM_EN field.
	OPAMP_OPAMP4_TCMR_T8CM_EN_Msk  = 0x10       // Bit mask of T8CM_EN field.
	OPAMP_OPAMP4_TCMR_T8CM_EN      = 0x10       // Bit T8CM_EN.
	OPAMP_OPAMP4_TCMR_T20CM_EN_Pos = 0x5        // Position of T20CM_EN field.
	OPAMP_OPAMP4_TCMR_T20CM_EN_Msk = 0x20       // Bit mask of T20CM_EN field.
	OPAMP_OPAMP4_TCMR_T20CM_EN     = 0x20       // Bit T20CM_EN.
	OPAMP_OPAMP4_TCMR_LOCK_Pos     = 0x1f       // Position of LOCK field.
	OPAMP_OPAMP4_TCMR_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	OPAMP_OPAMP4_TCMR_LOCK         = 0x80000000 // Bit LOCK.

	// OPAMP5_TCMR: OPAMP5 control/status register
	OPAMP_OPAMP5_TCMR_VMS_SEL_Pos  = 0x0        // Position of VMS_SEL field.
	OPAMP_OPAMP5_TCMR_VMS_SEL_Msk  = 0x1        // Bit mask of VMS_SEL field.
	OPAMP_OPAMP5_TCMR_VMS_SEL      = 0x1        // Bit VMS_SEL.
	OPAMP_OPAMP5_TCMR_VPS_SEL_Pos  = 0x1        // Position of VPS_SEL field.
	OPAMP_OPAMP5_TCMR_VPS_SEL_Msk  = 0x6        // Bit mask of VPS_SEL field.
	OPAMP_OPAMP5_TCMR_T1CM_EN_Pos  = 0x3        // Position of T1CM_EN field.
	OPAMP_OPAMP5_TCMR_T1CM_EN_Msk  = 0x8        // Bit mask of T1CM_EN field.
	OPAMP_OPAMP5_TCMR_T1CM_EN      = 0x8        // Bit T1CM_EN.
	OPAMP_OPAMP5_TCMR_T8CM_EN_Pos  = 0x4        // Position of T8CM_EN field.
	OPAMP_OPAMP5_TCMR_T8CM_EN_Msk  = 0x10       // Bit mask of T8CM_EN field.
	OPAMP_OPAMP5_TCMR_T8CM_EN      = 0x10       // Bit T8CM_EN.
	OPAMP_OPAMP5_TCMR_T20CM_EN_Pos = 0x5        // Position of T20CM_EN field.
	OPAMP_OPAMP5_TCMR_T20CM_EN_Msk = 0x20       // Bit mask of T20CM_EN field.
	OPAMP_OPAMP5_TCMR_T20CM_EN     = 0x20       // Bit T20CM_EN.
	OPAMP_OPAMP5_TCMR_LOCK_Pos     = 0x1f       // Position of LOCK field.
	OPAMP_OPAMP5_TCMR_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	OPAMP_OPAMP5_TCMR_LOCK         = 0x80000000 // Bit LOCK.

	// OPAMP6_TCMR: OPAMP6 control/status register
	OPAMP_OPAMP6_TCMR_VMS_SEL_Pos  = 0x0        // Position of VMS_SEL field.
	OPAMP_OPAMP6_TCMR_VMS_SEL_Msk  = 0x1        // Bit mask of VMS_SEL field.
	OPAMP_OPAMP6_TCMR_VMS_SEL      = 0x1        // Bit VMS_SEL.
	OPAMP_OPAMP6_TCMR_VPS_SEL_Pos  = 0x1        // Position of VPS_SEL field.
	OPAMP_OPAMP6_TCMR_VPS_SEL_Msk  = 0x6        // Bit mask of VPS_SEL field.
	OPAMP_OPAMP6_TCMR_T1CM_EN_Pos  = 0x3        // Position of T1CM_EN field.
	OPAMP_OPAMP6_TCMR_T1CM_EN_Msk  = 0x8        // Bit mask of T1CM_EN field.
	OPAMP_OPAMP6_TCMR_T1CM_EN      = 0x8        // Bit T1CM_EN.
	OPAMP_OPAMP6_TCMR_T8CM_EN_Pos  = 0x4        // Position of T8CM_EN field.
	OPAMP_OPAMP6_TCMR_T8CM_EN_Msk  = 0x10       // Bit mask of T8CM_EN field.
	OPAMP_OPAMP6_TCMR_T8CM_EN      = 0x10       // Bit T8CM_EN.
	OPAMP_OPAMP6_TCMR_T20CM_EN_Pos = 0x5        // Position of T20CM_EN field.
	OPAMP_OPAMP6_TCMR_T20CM_EN_Msk = 0x20       // Bit mask of T20CM_EN field.
	OPAMP_OPAMP6_TCMR_T20CM_EN     = 0x20       // Bit T20CM_EN.
	OPAMP_OPAMP6_TCMR_LOCK_Pos     = 0x1f       // Position of LOCK field.
	OPAMP_OPAMP6_TCMR_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	OPAMP_OPAMP6_TCMR_LOCK         = 0x80000000 // Bit LOCK.
)

// Bitfields for QUADSPI: QuadSPI interface
const (
	// CR: control register
	QUADSPI_CR_PRESCALER_Pos = 0x18       // Position of PRESCALER field.
	QUADSPI_CR_PRESCALER_Msk = 0xff000000 // Bit mask of PRESCALER field.
	QUADSPI_CR_PMM_Pos       = 0x17       // Position of PMM field.
	QUADSPI_CR_PMM_Msk       = 0x800000   // Bit mask of PMM field.
	QUADSPI_CR_PMM           = 0x800000   // Bit PMM.
	QUADSPI_CR_APMS_Pos      = 0x16       // Position of APMS field.
	QUADSPI_CR_APMS_Msk      = 0x400000   // Bit mask of APMS field.
	QUADSPI_CR_APMS          = 0x400000   // Bit APMS.
	QUADSPI_CR_TOIE_Pos      = 0x14       // Position of TOIE field.
	QUADSPI_CR_TOIE_Msk      = 0x100000   // Bit mask of TOIE field.
	QUADSPI_CR_TOIE          = 0x100000   // Bit TOIE.
	QUADSPI_CR_SMIE_Pos      = 0x13       // Position of SMIE field.
	QUADSPI_CR_SMIE_Msk      = 0x80000    // Bit mask of SMIE field.
	QUADSPI_CR_SMIE          = 0x80000    // Bit SMIE.
	QUADSPI_CR_FTIE_Pos      = 0x12       // Position of FTIE field.
	QUADSPI_CR_FTIE_Msk      = 0x40000    // Bit mask of FTIE field.
	QUADSPI_CR_FTIE          = 0x40000    // Bit FTIE.
	QUADSPI_CR_TCIE_Pos      = 0x11       // Position of TCIE field.
	QUADSPI_CR_TCIE_Msk      = 0x20000    // Bit mask of TCIE field.
	QUADSPI_CR_TCIE          = 0x20000    // Bit TCIE.
	QUADSPI_CR_TEIE_Pos      = 0x10       // Position of TEIE field.
	QUADSPI_CR_TEIE_Msk      = 0x10000    // Bit mask of TEIE field.
	QUADSPI_CR_TEIE          = 0x10000    // Bit TEIE.
	QUADSPI_CR_FTHRES_Pos    = 0x8        // Position of FTHRES field.
	QUADSPI_CR_FTHRES_Msk    = 0x1f00     // Bit mask of FTHRES field.
	QUADSPI_CR_FSEL_Pos      = 0x7        // Position of FSEL field.
	QUADSPI_CR_FSEL_Msk      = 0x80       // Bit mask of FSEL field.
	QUADSPI_CR_FSEL          = 0x80       // Bit FSEL.
	QUADSPI_CR_DFM_Pos       = 0x6        // Position of DFM field.
	QUADSPI_CR_DFM_Msk       = 0x40       // Bit mask of DFM field.
	QUADSPI_CR_DFM           = 0x40       // Bit DFM.
	QUADSPI_CR_SSHIFT_Pos    = 0x4        // Position of SSHIFT field.
	QUADSPI_CR_SSHIFT_Msk    = 0x10       // Bit mask of SSHIFT field.
	QUADSPI_CR_SSHIFT        = 0x10       // Bit SSHIFT.
	QUADSPI_CR_TCEN_Pos      = 0x3        // Position of TCEN field.
	QUADSPI_CR_TCEN_Msk      = 0x8        // Bit mask of TCEN field.
	QUADSPI_CR_TCEN          = 0x8        // Bit TCEN.
	QUADSPI_CR_DMAEN_Pos     = 0x2        // Position of DMAEN field.
	QUADSPI_CR_DMAEN_Msk     = 0x4        // Bit mask of DMAEN field.
	QUADSPI_CR_DMAEN         = 0x4        // Bit DMAEN.
	QUADSPI_CR_ABORT_Pos     = 0x1        // Position of ABORT field.
	QUADSPI_CR_ABORT_Msk     = 0x2        // Bit mask of ABORT field.
	QUADSPI_CR_ABORT         = 0x2        // Bit ABORT.
	QUADSPI_CR_EN_Pos        = 0x0        // Position of EN field.
	QUADSPI_CR_EN_Msk        = 0x1        // Bit mask of EN field.
	QUADSPI_CR_EN            = 0x1        // Bit EN.

	// DCR: device configuration register
	QUADSPI_DCR_FSIZE_Pos  = 0x10     // Position of FSIZE field.
	QUADSPI_DCR_FSIZE_Msk  = 0x1f0000 // Bit mask of FSIZE field.
	QUADSPI_DCR_CSHT_Pos   = 0x8      // Position of CSHT field.
	QUADSPI_DCR_CSHT_Msk   = 0x700    // Bit mask of CSHT field.
	QUADSPI_DCR_CKMODE_Pos = 0x0      // Position of CKMODE field.
	QUADSPI_DCR_CKMODE_Msk = 0x1      // Bit mask of CKMODE field.
	QUADSPI_DCR_CKMODE     = 0x1      // Bit CKMODE.

	// SR: status register
	QUADSPI_SR_FLEVEL_Pos = 0x8    // Position of FLEVEL field.
	QUADSPI_SR_FLEVEL_Msk = 0x1f00 // Bit mask of FLEVEL field.
	QUADSPI_SR_BUSY_Pos   = 0x5    // Position of BUSY field.
	QUADSPI_SR_BUSY_Msk   = 0x20   // Bit mask of BUSY field.
	QUADSPI_SR_BUSY       = 0x20   // Bit BUSY.
	QUADSPI_SR_TOF_Pos    = 0x4    // Position of TOF field.
	QUADSPI_SR_TOF_Msk    = 0x10   // Bit mask of TOF field.
	QUADSPI_SR_TOF        = 0x10   // Bit TOF.
	QUADSPI_SR_SMF_Pos    = 0x3    // Position of SMF field.
	QUADSPI_SR_SMF_Msk    = 0x8    // Bit mask of SMF field.
	QUADSPI_SR_SMF        = 0x8    // Bit SMF.
	QUADSPI_SR_FTF_Pos    = 0x2    // Position of FTF field.
	QUADSPI_SR_FTF_Msk    = 0x4    // Bit mask of FTF field.
	QUADSPI_SR_FTF        = 0x4    // Bit FTF.
	QUADSPI_SR_TCF_Pos    = 0x1    // Position of TCF field.
	QUADSPI_SR_TCF_Msk    = 0x2    // Bit mask of TCF field.
	QUADSPI_SR_TCF        = 0x2    // Bit TCF.
	QUADSPI_SR_TEF_Pos    = 0x0    // Position of TEF field.
	QUADSPI_SR_TEF_Msk    = 0x1    // Bit mask of TEF field.
	QUADSPI_SR_TEF        = 0x1    // Bit TEF.

	// FCR: flag clear register
	QUADSPI_FCR_CTOF_Pos = 0x4  // Position of CTOF field.
	QUADSPI_FCR_CTOF_Msk = 0x10 // Bit mask of CTOF field.
	QUADSPI_FCR_CTOF     = 0x10 // Bit CTOF.
	QUADSPI_FCR_CSMF_Pos = 0x3  // Position of CSMF field.
	QUADSPI_FCR_CSMF_Msk = 0x8  // Bit mask of CSMF field.
	QUADSPI_FCR_CSMF     = 0x8  // Bit CSMF.
	QUADSPI_FCR_CTCF_Pos = 0x1  // Position of CTCF field.
	QUADSPI_FCR_CTCF_Msk = 0x2  // Bit mask of CTCF field.
	QUADSPI_FCR_CTCF     = 0x2  // Bit CTCF.
	QUADSPI_FCR_CTEF_Pos = 0x0  // Position of CTEF field.
	QUADSPI_FCR_CTEF_Msk = 0x1  // Bit mask of CTEF field.
	QUADSPI_FCR_CTEF     = 0x1  // Bit CTEF.

	// DLR: data length register
	QUADSPI_DLR_DL_Pos = 0x0        // Position of DL field.
	QUADSPI_DLR_DL_Msk = 0xffffffff // Bit mask of DL field.

	// CCR: communication configuration           register
	QUADSPI_CCR_DDRM_Pos        = 0x1f       // Position of DDRM field.
	QUADSPI_CCR_DDRM_Msk        = 0x80000000 // Bit mask of DDRM field.
	QUADSPI_CCR_DDRM            = 0x80000000 // Bit DDRM.
	QUADSPI_CCR_SIOO_Pos        = 0x1c       // Position of SIOO field.
	QUADSPI_CCR_SIOO_Msk        = 0x10000000 // Bit mask of SIOO field.
	QUADSPI_CCR_SIOO            = 0x10000000 // Bit SIOO.
	QUADSPI_CCR_FMODE_Pos       = 0x1a       // Position of FMODE field.
	QUADSPI_CCR_FMODE_Msk       = 0xc000000  // Bit mask of FMODE field.
	QUADSPI_CCR_DMODE_Pos       = 0x18       // Position of DMODE field.
	QUADSPI_CCR_DMODE_Msk       = 0x3000000  // Bit mask of DMODE field.
	QUADSPI_CCR_DCYC_Pos        = 0x12       // Position of DCYC field.
	QUADSPI_CCR_DCYC_Msk        = 0x7c0000   // Bit mask of DCYC field.
	QUADSPI_CCR_ABSIZE_Pos      = 0x10       // Position of ABSIZE field.
	QUADSPI_CCR_ABSIZE_Msk      = 0x30000    // Bit mask of ABSIZE field.
	QUADSPI_CCR_ABMODE_Pos      = 0xe        // Position of ABMODE field.
	QUADSPI_CCR_ABMODE_Msk      = 0xc000     // Bit mask of ABMODE field.
	QUADSPI_CCR_ADSIZE_Pos      = 0xc        // Position of ADSIZE field.
	QUADSPI_CCR_ADSIZE_Msk      = 0x3000     // Bit mask of ADSIZE field.
	QUADSPI_CCR_ADMODE_Pos      = 0xa        // Position of ADMODE field.
	QUADSPI_CCR_ADMODE_Msk      = 0xc00      // Bit mask of ADMODE field.
	QUADSPI_CCR_IMODE_Pos       = 0x8        // Position of IMODE field.
	QUADSPI_CCR_IMODE_Msk       = 0x300      // Bit mask of IMODE field.
	QUADSPI_CCR_INSTRUCTION_Pos = 0x0        // Position of INSTRUCTION field.
	QUADSPI_CCR_INSTRUCTION_Msk = 0xff       // Bit mask of INSTRUCTION field.

	// AR: address register
	QUADSPI_AR_ADDRESS_Pos = 0x0        // Position of ADDRESS field.
	QUADSPI_AR_ADDRESS_Msk = 0xffffffff // Bit mask of ADDRESS field.

	// ABR: ABR
	QUADSPI_ABR_ALTERNATE_Pos = 0x0        // Position of ALTERNATE field.
	QUADSPI_ABR_ALTERNATE_Msk = 0xffffffff // Bit mask of ALTERNATE field.

	// DR: data register
	QUADSPI_DR_DATA_Pos = 0x0        // Position of DATA field.
	QUADSPI_DR_DATA_Msk = 0xffffffff // Bit mask of DATA field.

	// PSMKR: polling status mask register
	QUADSPI_PSMKR_MASK_Pos = 0x0        // Position of MASK field.
	QUADSPI_PSMKR_MASK_Msk = 0xffffffff // Bit mask of MASK field.

	// PSMAR: polling status match register
	QUADSPI_PSMAR_MATCH_Pos = 0x0        // Position of MATCH field.
	QUADSPI_PSMAR_MATCH_Msk = 0xffffffff // Bit mask of MATCH field.

	// PIR: polling interval register
	QUADSPI_PIR_INTERVAL_Pos = 0x0    // Position of INTERVAL field.
	QUADSPI_PIR_INTERVAL_Msk = 0xffff // Bit mask of INTERVAL field.

	// LPTR: low-power timeout register
	QUADSPI_LPTR_TIMEOUT_Pos = 0x0    // Position of TIMEOUT field.
	QUADSPI_LPTR_TIMEOUT_Msk = 0xffff // Bit mask of TIMEOUT field.
)

// Bitfields for DAC1: Digital-to-analog converter
const (
	// DAC_CR: DAC control register
	DAC_DAC_CR_EN1_Pos       = 0x0        // Position of EN1 field.
	DAC_DAC_CR_EN1_Msk       = 0x1        // Bit mask of EN1 field.
	DAC_DAC_CR_EN1           = 0x1        // Bit EN1.
	DAC_DAC_CR_TEN1_Pos      = 0x1        // Position of TEN1 field.
	DAC_DAC_CR_TEN1_Msk      = 0x2        // Bit mask of TEN1 field.
	DAC_DAC_CR_TEN1          = 0x2        // Bit TEN1.
	DAC_DAC_CR_TSEL1_Pos     = 0x2        // Position of TSEL1 field.
	DAC_DAC_CR_TSEL1_Msk     = 0x3c       // Bit mask of TSEL1 field.
	DAC_DAC_CR_WAVE1_Pos     = 0x6        // Position of WAVE1 field.
	DAC_DAC_CR_WAVE1_Msk     = 0xc0       // Bit mask of WAVE1 field.
	DAC_DAC_CR_MAMP1_Pos     = 0x8        // Position of MAMP1 field.
	DAC_DAC_CR_MAMP1_Msk     = 0xf00      // Bit mask of MAMP1 field.
	DAC_DAC_CR_DMAEN1_Pos    = 0xc        // Position of DMAEN1 field.
	DAC_DAC_CR_DMAEN1_Msk    = 0x1000     // Bit mask of DMAEN1 field.
	DAC_DAC_CR_DMAEN1        = 0x1000     // Bit DMAEN1.
	DAC_DAC_CR_DMAUDRIE1_Pos = 0xd        // Position of DMAUDRIE1 field.
	DAC_DAC_CR_DMAUDRIE1_Msk = 0x2000     // Bit mask of DMAUDRIE1 field.
	DAC_DAC_CR_DMAUDRIE1     = 0x2000     // Bit DMAUDRIE1.
	DAC_DAC_CR_CEN1_Pos      = 0xe        // Position of CEN1 field.
	DAC_DAC_CR_CEN1_Msk      = 0x4000     // Bit mask of CEN1 field.
	DAC_DAC_CR_CEN1          = 0x4000     // Bit CEN1.
	DAC_DAC_CR_EN2_Pos       = 0x10       // Position of EN2 field.
	DAC_DAC_CR_EN2_Msk       = 0x10000    // Bit mask of EN2 field.
	DAC_DAC_CR_EN2           = 0x10000    // Bit EN2.
	DAC_DAC_CR_TEN2_Pos      = 0x11       // Position of TEN2 field.
	DAC_DAC_CR_TEN2_Msk      = 0x20000    // Bit mask of TEN2 field.
	DAC_DAC_CR_TEN2          = 0x20000    // Bit TEN2.
	DAC_DAC_CR_TSEL2_Pos     = 0x12       // Position of TSEL2 field.
	DAC_DAC_CR_TSEL2_Msk     = 0x3c0000   // Bit mask of TSEL2 field.
	DAC_DAC_CR_WAVE2_Pos     = 0x16       // Position of WAVE2 field.
	DAC_DAC_CR_WAVE2_Msk     = 0xc00000   // Bit mask of WAVE2 field.
	DAC_DAC_CR_MAMP2_Pos     = 0x18       // Position of MAMP2 field.
	DAC_DAC_CR_MAMP2_Msk     = 0xf000000  // Bit mask of MAMP2 field.
	DAC_DAC_CR_DMAEN2_Pos    = 0x1c       // Position of DMAEN2 field.
	DAC_DAC_CR_DMAEN2_Msk    = 0x10000000 // Bit mask of DMAEN2 field.
	DAC_DAC_CR_DMAEN2        = 0x10000000 // Bit DMAEN2.
	DAC_DAC_CR_DMAUDRIE2_Pos = 0x1d       // Position of DMAUDRIE2 field.
	DAC_DAC_CR_DMAUDRIE2_Msk = 0x20000000 // Bit mask of DMAUDRIE2 field.
	DAC_DAC_CR_DMAUDRIE2     = 0x20000000 // Bit DMAUDRIE2.
	DAC_DAC_CR_CEN2_Pos      = 0x1e       // Position of CEN2 field.
	DAC_DAC_CR_CEN2_Msk      = 0x40000000 // Bit mask of CEN2 field.
	DAC_DAC_CR_CEN2          = 0x40000000 // Bit CEN2.

	// DAC_SWTRGR: DAC software trigger register
	DAC_DAC_SWTRGR_SWTRIG1_Pos  = 0x0     // Position of SWTRIG1 field.
	DAC_DAC_SWTRGR_SWTRIG1_Msk  = 0x1     // Bit mask of SWTRIG1 field.
	DAC_DAC_SWTRGR_SWTRIG1      = 0x1     // Bit SWTRIG1.
	DAC_DAC_SWTRGR_SWTRIG2_Pos  = 0x1     // Position of SWTRIG2 field.
	DAC_DAC_SWTRGR_SWTRIG2_Msk  = 0x2     // Bit mask of SWTRIG2 field.
	DAC_DAC_SWTRGR_SWTRIG2      = 0x2     // Bit SWTRIG2.
	DAC_DAC_SWTRGR_SWTRIGB1_Pos = 0x10    // Position of SWTRIGB1 field.
	DAC_DAC_SWTRGR_SWTRIGB1_Msk = 0x10000 // Bit mask of SWTRIGB1 field.
	DAC_DAC_SWTRGR_SWTRIGB1     = 0x10000 // Bit SWTRIGB1.
	DAC_DAC_SWTRGR_SWTRIGB2_Pos = 0x11    // Position of SWTRIGB2 field.
	DAC_DAC_SWTRGR_SWTRIGB2_Msk = 0x20000 // Bit mask of SWTRIGB2 field.
	DAC_DAC_SWTRGR_SWTRIGB2     = 0x20000 // Bit SWTRIGB2.

	// DAC_DHR12R1: DAC channel1 12-bit right-aligned data           holding register
	DAC_DAC_DHR12R1_DACC1DHR_Pos  = 0x0       // Position of DACC1DHR field.
	DAC_DAC_DHR12R1_DACC1DHR_Msk  = 0xfff     // Bit mask of DACC1DHR field.
	DAC_DAC_DHR12R1_DACC1DHRB_Pos = 0x10      // Position of DACC1DHRB field.
	DAC_DAC_DHR12R1_DACC1DHRB_Msk = 0xfff0000 // Bit mask of DACC1DHRB field.

	// DAC_DHR12L1: DAC channel1 12-bit left aligned data           holding register
	DAC_DAC_DHR12L1_DACC1DHR_Pos  = 0x4        // Position of DACC1DHR field.
	DAC_DAC_DHR12L1_DACC1DHR_Msk  = 0xfff0     // Bit mask of DACC1DHR field.
	DAC_DAC_DHR12L1_DACC1DHRB_Pos = 0x14       // Position of DACC1DHRB field.
	DAC_DAC_DHR12L1_DACC1DHRB_Msk = 0xfff00000 // Bit mask of DACC1DHRB field.

	// DAC_DHR8R1: DAC channel1 8-bit right aligned data           holding register
	DAC_DAC_DHR8R1_DACC1DHR_Pos  = 0x0    // Position of DACC1DHR field.
	DAC_DAC_DHR8R1_DACC1DHR_Msk  = 0xff   // Bit mask of DACC1DHR field.
	DAC_DAC_DHR8R1_DACC1DHRB_Pos = 0x8    // Position of DACC1DHRB field.
	DAC_DAC_DHR8R1_DACC1DHRB_Msk = 0xff00 // Bit mask of DACC1DHRB field.

	// DAC_DHR12R2: DAC channel2 12-bit right aligned data           holding register
	DAC_DAC_DHR12R2_DACC2DHR_Pos  = 0x0       // Position of DACC2DHR field.
	DAC_DAC_DHR12R2_DACC2DHR_Msk  = 0xfff     // Bit mask of DACC2DHR field.
	DAC_DAC_DHR12R2_DACC2DHRB_Pos = 0x10      // Position of DACC2DHRB field.
	DAC_DAC_DHR12R2_DACC2DHRB_Msk = 0xfff0000 // Bit mask of DACC2DHRB field.

	// DAC_DHR12L2: DAC channel2 12-bit left aligned data           holding register
	DAC_DAC_DHR12L2_DACC2DHR_Pos  = 0x4        // Position of DACC2DHR field.
	DAC_DAC_DHR12L2_DACC2DHR_Msk  = 0xfff0     // Bit mask of DACC2DHR field.
	DAC_DAC_DHR12L2_DACC2DHRB_Pos = 0x14       // Position of DACC2DHRB field.
	DAC_DAC_DHR12L2_DACC2DHRB_Msk = 0xfff00000 // Bit mask of DACC2DHRB field.

	// DAC_DHR8R2: DAC channel2 8-bit right-aligned data           holding register
	DAC_DAC_DHR8R2_DACC2DHR_Pos  = 0x0    // Position of DACC2DHR field.
	DAC_DAC_DHR8R2_DACC2DHR_Msk  = 0xff   // Bit mask of DACC2DHR field.
	DAC_DAC_DHR8R2_DACC2DHRB_Pos = 0x8    // Position of DACC2DHRB field.
	DAC_DAC_DHR8R2_DACC2DHRB_Msk = 0xff00 // Bit mask of DACC2DHRB field.

	// DAC_DHR12RD: Dual DAC 12-bit right-aligned data holding           register
	DAC_DAC_DHR12RD_DACC1DHR_Pos = 0x0       // Position of DACC1DHR field.
	DAC_DAC_DHR12RD_DACC1DHR_Msk = 0xfff     // Bit mask of DACC1DHR field.
	DAC_DAC_DHR12RD_DACC2DHR_Pos = 0x10      // Position of DACC2DHR field.
	DAC_DAC_DHR12RD_DACC2DHR_Msk = 0xfff0000 // Bit mask of DACC2DHR field.

	// DAC_DHR12LD: DUAL DAC 12-bit left aligned data holding           register
	DAC_DAC_DHR12LD_DACC1DHR_Pos = 0x4        // Position of DACC1DHR field.
	DAC_DAC_DHR12LD_DACC1DHR_Msk = 0xfff0     // Bit mask of DACC1DHR field.
	DAC_DAC_DHR12LD_DACC2DHR_Pos = 0x14       // Position of DACC2DHR field.
	DAC_DAC_DHR12LD_DACC2DHR_Msk = 0xfff00000 // Bit mask of DACC2DHR field.

	// DAC_DHR8RD: DUAL DAC 8-bit right aligned data holding           register
	DAC_DAC_DHR8RD_DACC1DHR_Pos = 0x0    // Position of DACC1DHR field.
	DAC_DAC_DHR8RD_DACC1DHR_Msk = 0xff   // Bit mask of DACC1DHR field.
	DAC_DAC_DHR8RD_DACC2DHR_Pos = 0x8    // Position of DACC2DHR field.
	DAC_DAC_DHR8RD_DACC2DHR_Msk = 0xff00 // Bit mask of DACC2DHR field.

	// DAC_DOR1: DAC channel1 data output           register
	DAC_DAC_DOR1_DACC1DOR_Pos  = 0x0       // Position of DACC1DOR field.
	DAC_DAC_DOR1_DACC1DOR_Msk  = 0xfff     // Bit mask of DACC1DOR field.
	DAC_DAC_DOR1_DACC1DORB_Pos = 0x10      // Position of DACC1DORB field.
	DAC_DAC_DOR1_DACC1DORB_Msk = 0xfff0000 // Bit mask of DACC1DORB field.

	// DAC_DOR2: DAC channel2 data output           register
	DAC_DAC_DOR2_DACC2DOR_Pos  = 0x0       // Position of DACC2DOR field.
	DAC_DAC_DOR2_DACC2DOR_Msk  = 0xfff     // Bit mask of DACC2DOR field.
	DAC_DAC_DOR2_DACC2DORB_Pos = 0x10      // Position of DACC2DORB field.
	DAC_DAC_DOR2_DACC2DORB_Msk = 0xfff0000 // Bit mask of DACC2DORB field.

	// DAC_SR: DAC status register
	DAC_DAC_SR_DAC1RDY_Pos   = 0xb        // Position of DAC1RDY field.
	DAC_DAC_SR_DAC1RDY_Msk   = 0x800      // Bit mask of DAC1RDY field.
	DAC_DAC_SR_DAC1RDY       = 0x800      // Bit DAC1RDY.
	DAC_DAC_SR_DORSTAT1_Pos  = 0xc        // Position of DORSTAT1 field.
	DAC_DAC_SR_DORSTAT1_Msk  = 0x1000     // Bit mask of DORSTAT1 field.
	DAC_DAC_SR_DORSTAT1      = 0x1000     // Bit DORSTAT1.
	DAC_DAC_SR_DMAUDR1_Pos   = 0xd        // Position of DMAUDR1 field.
	DAC_DAC_SR_DMAUDR1_Msk   = 0x2000     // Bit mask of DMAUDR1 field.
	DAC_DAC_SR_DMAUDR1       = 0x2000     // Bit DMAUDR1.
	DAC_DAC_SR_CAL_FLAG1_Pos = 0xe        // Position of CAL_FLAG1 field.
	DAC_DAC_SR_CAL_FLAG1_Msk = 0x4000     // Bit mask of CAL_FLAG1 field.
	DAC_DAC_SR_CAL_FLAG1     = 0x4000     // Bit CAL_FLAG1.
	DAC_DAC_SR_BWST1_Pos     = 0xf        // Position of BWST1 field.
	DAC_DAC_SR_BWST1_Msk     = 0x8000     // Bit mask of BWST1 field.
	DAC_DAC_SR_BWST1         = 0x8000     // Bit BWST1.
	DAC_DAC_SR_DAC2RDY_Pos   = 0x1b       // Position of DAC2RDY field.
	DAC_DAC_SR_DAC2RDY_Msk   = 0x8000000  // Bit mask of DAC2RDY field.
	DAC_DAC_SR_DAC2RDY       = 0x8000000  // Bit DAC2RDY.
	DAC_DAC_SR_DORSTAT2_Pos  = 0x1c       // Position of DORSTAT2 field.
	DAC_DAC_SR_DORSTAT2_Msk  = 0x10000000 // Bit mask of DORSTAT2 field.
	DAC_DAC_SR_DORSTAT2      = 0x10000000 // Bit DORSTAT2.
	DAC_DAC_SR_DMAUDR2_Pos   = 0x1d       // Position of DMAUDR2 field.
	DAC_DAC_SR_DMAUDR2_Msk   = 0x20000000 // Bit mask of DMAUDR2 field.
	DAC_DAC_SR_DMAUDR2       = 0x20000000 // Bit DMAUDR2.
	DAC_DAC_SR_CAL_FLAG2_Pos = 0x1e       // Position of CAL_FLAG2 field.
	DAC_DAC_SR_CAL_FLAG2_Msk = 0x40000000 // Bit mask of CAL_FLAG2 field.
	DAC_DAC_SR_CAL_FLAG2     = 0x40000000 // Bit CAL_FLAG2.
	DAC_DAC_SR_BWST2_Pos     = 0x1f       // Position of BWST2 field.
	DAC_DAC_SR_BWST2_Msk     = 0x80000000 // Bit mask of BWST2 field.
	DAC_DAC_SR_BWST2         = 0x80000000 // Bit BWST2.

	// DAC_CCR: DAC calibration control           register
	DAC_DAC_CCR_OTRIM1_Pos = 0x0      // Position of OTRIM1 field.
	DAC_DAC_CCR_OTRIM1_Msk = 0x1f     // Bit mask of OTRIM1 field.
	DAC_DAC_CCR_OTRIM2_Pos = 0x10     // Position of OTRIM2 field.
	DAC_DAC_CCR_OTRIM2_Msk = 0x1f0000 // Bit mask of OTRIM2 field.

	// DAC_MCR: DAC mode control register
	DAC_DAC_MCR_MODE1_Pos      = 0x0       // Position of MODE1 field.
	DAC_DAC_MCR_MODE1_Msk      = 0x7       // Bit mask of MODE1 field.
	DAC_DAC_MCR_DMADOUBLE1_Pos = 0x8       // Position of DMADOUBLE1 field.
	DAC_DAC_MCR_DMADOUBLE1_Msk = 0x100     // Bit mask of DMADOUBLE1 field.
	DAC_DAC_MCR_DMADOUBLE1     = 0x100     // Bit DMADOUBLE1.
	DAC_DAC_MCR_SINFORMAT1_Pos = 0x9       // Position of SINFORMAT1 field.
	DAC_DAC_MCR_SINFORMAT1_Msk = 0x200     // Bit mask of SINFORMAT1 field.
	DAC_DAC_MCR_SINFORMAT1     = 0x200     // Bit SINFORMAT1.
	DAC_DAC_MCR_HFSEL_Pos      = 0xe       // Position of HFSEL field.
	DAC_DAC_MCR_HFSEL_Msk      = 0xc000    // Bit mask of HFSEL field.
	DAC_DAC_MCR_MODE2_Pos      = 0x10      // Position of MODE2 field.
	DAC_DAC_MCR_MODE2_Msk      = 0x70000   // Bit mask of MODE2 field.
	DAC_DAC_MCR_DMADOUBLE2_Pos = 0x18      // Position of DMADOUBLE2 field.
	DAC_DAC_MCR_DMADOUBLE2_Msk = 0x1000000 // Bit mask of DMADOUBLE2 field.
	DAC_DAC_MCR_DMADOUBLE2     = 0x1000000 // Bit DMADOUBLE2.
	DAC_DAC_MCR_SINFORMAT2_Pos = 0x19      // Position of SINFORMAT2 field.
	DAC_DAC_MCR_SINFORMAT2_Msk = 0x2000000 // Bit mask of SINFORMAT2 field.
	DAC_DAC_MCR_SINFORMAT2     = 0x2000000 // Bit SINFORMAT2.

	// DAC_SHSR1: DAC Sample and Hold sample time register           1
	DAC_DAC_SHSR1_TSAMPLE1_Pos = 0x0   // Position of TSAMPLE1 field.
	DAC_DAC_SHSR1_TSAMPLE1_Msk = 0x3ff // Bit mask of TSAMPLE1 field.

	// DAC_SHSR2: DAC Sample and Hold sample time register           2
	DAC_DAC_SHSR2_TSAMPLE2_Pos = 0x0   // Position of TSAMPLE2 field.
	DAC_DAC_SHSR2_TSAMPLE2_Msk = 0x3ff // Bit mask of TSAMPLE2 field.

	// DAC_SHHR: DAC Sample and Hold hold time           register
	DAC_DAC_SHHR_THOLD1_Pos = 0x0       // Position of THOLD1 field.
	DAC_DAC_SHHR_THOLD1_Msk = 0x3ff     // Bit mask of THOLD1 field.
	DAC_DAC_SHHR_THOLD2_Pos = 0x10      // Position of THOLD2 field.
	DAC_DAC_SHHR_THOLD2_Msk = 0x3ff0000 // Bit mask of THOLD2 field.

	// DAC_SHRR: DAC Sample and Hold refresh time           register
	DAC_DAC_SHRR_TREFRESH1_Pos = 0x0      // Position of TREFRESH1 field.
	DAC_DAC_SHRR_TREFRESH1_Msk = 0xff     // Bit mask of TREFRESH1 field.
	DAC_DAC_SHRR_TREFRESH2_Pos = 0x10     // Position of TREFRESH2 field.
	DAC_DAC_SHRR_TREFRESH2_Msk = 0xff0000 // Bit mask of TREFRESH2 field.

	// DAC_STR1: Sawtooth register
	DAC_DAC_STR1_STRSTDATA1_Pos = 0x0        // Position of STRSTDATA1 field.
	DAC_DAC_STR1_STRSTDATA1_Msk = 0xfff      // Bit mask of STRSTDATA1 field.
	DAC_DAC_STR1_STDIR1_Pos     = 0xc        // Position of STDIR1 field.
	DAC_DAC_STR1_STDIR1_Msk     = 0x1000     // Bit mask of STDIR1 field.
	DAC_DAC_STR1_STDIR1         = 0x1000     // Bit STDIR1.
	DAC_DAC_STR1_STINCDATA1_Pos = 0x10       // Position of STINCDATA1 field.
	DAC_DAC_STR1_STINCDATA1_Msk = 0xffff0000 // Bit mask of STINCDATA1 field.

	// DAC_STR2: Sawtooth register
	DAC_DAC_STR2_STRSTDATA2_Pos = 0x0        // Position of STRSTDATA2 field.
	DAC_DAC_STR2_STRSTDATA2_Msk = 0xfff      // Bit mask of STRSTDATA2 field.
	DAC_DAC_STR2_STDIR2_Pos     = 0xc        // Position of STDIR2 field.
	DAC_DAC_STR2_STDIR2_Msk     = 0x1000     // Bit mask of STDIR2 field.
	DAC_DAC_STR2_STDIR2         = 0x1000     // Bit STDIR2.
	DAC_DAC_STR2_STINCDATA2_Pos = 0x10       // Position of STINCDATA2 field.
	DAC_DAC_STR2_STINCDATA2_Msk = 0xffff0000 // Bit mask of STINCDATA2 field.

	// DAC_STMODR: Sawtooth Mode register
	DAC_DAC_STMODR_STRSTTRIGSEL1_Pos = 0x0       // Position of STRSTTRIGSEL1 field.
	DAC_DAC_STMODR_STRSTTRIGSEL1_Msk = 0xf       // Bit mask of STRSTTRIGSEL1 field.
	DAC_DAC_STMODR_STINCTRIGSEL1_Pos = 0x8       // Position of STINCTRIGSEL1 field.
	DAC_DAC_STMODR_STINCTRIGSEL1_Msk = 0xf00     // Bit mask of STINCTRIGSEL1 field.
	DAC_DAC_STMODR_STRSTTRIGSEL2_Pos = 0x10      // Position of STRSTTRIGSEL2 field.
	DAC_DAC_STMODR_STRSTTRIGSEL2_Msk = 0xf0000   // Bit mask of STRSTTRIGSEL2 field.
	DAC_DAC_STMODR_STINCTRIGSEL2_Pos = 0x18      // Position of STINCTRIGSEL2 field.
	DAC_DAC_STMODR_STINCTRIGSEL2_Msk = 0xf000000 // Bit mask of STINCTRIGSEL2 field.
)

// Bitfields for ADC1: Analog-to-Digital Converter
const (
	// ISR: interrupt and status register
	ADC_ISR_JQOVF_Pos = 0xa   // Position of JQOVF field.
	ADC_ISR_JQOVF_Msk = 0x400 // Bit mask of JQOVF field.
	ADC_ISR_JQOVF     = 0x400 // Bit JQOVF.
	ADC_ISR_AWD3_Pos  = 0x9   // Position of AWD3 field.
	ADC_ISR_AWD3_Msk  = 0x200 // Bit mask of AWD3 field.
	ADC_ISR_AWD3      = 0x200 // Bit AWD3.
	ADC_ISR_AWD2_Pos  = 0x8   // Position of AWD2 field.
	ADC_ISR_AWD2_Msk  = 0x100 // Bit mask of AWD2 field.
	ADC_ISR_AWD2      = 0x100 // Bit AWD2.
	ADC_ISR_AWD1_Pos  = 0x7   // Position of AWD1 field.
	ADC_ISR_AWD1_Msk  = 0x80  // Bit mask of AWD1 field.
	ADC_ISR_AWD1      = 0x80  // Bit AWD1.
	ADC_ISR_JEOS_Pos  = 0x6   // Position of JEOS field.
	ADC_ISR_JEOS_Msk  = 0x40  // Bit mask of JEOS field.
	ADC_ISR_JEOS      = 0x40  // Bit JEOS.
	ADC_ISR_JEOC_Pos  = 0x5   // Position of JEOC field.
	ADC_ISR_JEOC_Msk  = 0x20  // Bit mask of JEOC field.
	ADC_ISR_JEOC      = 0x20  // Bit JEOC.
	ADC_ISR_OVR_Pos   = 0x4   // Position of OVR field.
	ADC_ISR_OVR_Msk   = 0x10  // Bit mask of OVR field.
	ADC_ISR_OVR       = 0x10  // Bit OVR.
	ADC_ISR_EOS_Pos   = 0x3   // Position of EOS field.
	ADC_ISR_EOS_Msk   = 0x8   // Bit mask of EOS field.
	ADC_ISR_EOS       = 0x8   // Bit EOS.
	ADC_ISR_EOC_Pos   = 0x2   // Position of EOC field.
	ADC_ISR_EOC_Msk   = 0x4   // Bit mask of EOC field.
	ADC_ISR_EOC       = 0x4   // Bit EOC.
	ADC_ISR_EOSMP_Pos = 0x1   // Position of EOSMP field.
	ADC_ISR_EOSMP_Msk = 0x2   // Bit mask of EOSMP field.
	ADC_ISR_EOSMP     = 0x2   // Bit EOSMP.
	ADC_ISR_ADRDY_Pos = 0x0   // Position of ADRDY field.
	ADC_ISR_ADRDY_Msk = 0x1   // Bit mask of ADRDY field.
	ADC_ISR_ADRDY     = 0x1   // Bit ADRDY.

	// IER: interrupt enable register
	ADC_IER_JQOVFIE_Pos = 0xa   // Position of JQOVFIE field.
	ADC_IER_JQOVFIE_Msk = 0x400 // Bit mask of JQOVFIE field.
	ADC_IER_JQOVFIE     = 0x400 // Bit JQOVFIE.
	ADC_IER_AWD3IE_Pos  = 0x9   // Position of AWD3IE field.
	ADC_IER_AWD3IE_Msk  = 0x200 // Bit mask of AWD3IE field.
	ADC_IER_AWD3IE      = 0x200 // Bit AWD3IE.
	ADC_IER_AWD2IE_Pos  = 0x8   // Position of AWD2IE field.
	ADC_IER_AWD2IE_Msk  = 0x100 // Bit mask of AWD2IE field.
	ADC_IER_AWD2IE      = 0x100 // Bit AWD2IE.
	ADC_IER_AWD1IE_Pos  = 0x7   // Position of AWD1IE field.
	ADC_IER_AWD1IE_Msk  = 0x80  // Bit mask of AWD1IE field.
	ADC_IER_AWD1IE      = 0x80  // Bit AWD1IE.
	ADC_IER_JEOSIE_Pos  = 0x6   // Position of JEOSIE field.
	ADC_IER_JEOSIE_Msk  = 0x40  // Bit mask of JEOSIE field.
	ADC_IER_JEOSIE      = 0x40  // Bit JEOSIE.
	ADC_IER_JEOCIE_Pos  = 0x5   // Position of JEOCIE field.
	ADC_IER_JEOCIE_Msk  = 0x20  // Bit mask of JEOCIE field.
	ADC_IER_JEOCIE      = 0x20  // Bit JEOCIE.
	ADC_IER_OVRIE_Pos   = 0x4   // Position of OVRIE field.
	ADC_IER_OVRIE_Msk   = 0x10  // Bit mask of OVRIE field.
	ADC_IER_OVRIE       = 0x10  // Bit OVRIE.
	ADC_IER_EOSIE_Pos   = 0x3   // Position of EOSIE field.
	ADC_IER_EOSIE_Msk   = 0x8   // Bit mask of EOSIE field.
	ADC_IER_EOSIE       = 0x8   // Bit EOSIE.
	ADC_IER_EOCIE_Pos   = 0x2   // Position of EOCIE field.
	ADC_IER_EOCIE_Msk   = 0x4   // Bit mask of EOCIE field.
	ADC_IER_EOCIE       = 0x4   // Bit EOCIE.
	ADC_IER_EOSMPIE_Pos = 0x1   // Position of EOSMPIE field.
	ADC_IER_EOSMPIE_Msk = 0x2   // Bit mask of EOSMPIE field.
	ADC_IER_EOSMPIE     = 0x2   // Bit EOSMPIE.
	ADC_IER_ADRDYIE_Pos = 0x0   // Position of ADRDYIE field.
	ADC_IER_ADRDYIE_Msk = 0x1   // Bit mask of ADRDYIE field.
	ADC_IER_ADRDYIE     = 0x1   // Bit ADRDYIE.

	// CR: control register
	ADC_CR_ADCAL_Pos    = 0x1f       // Position of ADCAL field.
	ADC_CR_ADCAL_Msk    = 0x80000000 // Bit mask of ADCAL field.
	ADC_CR_ADCAL        = 0x80000000 // Bit ADCAL.
	ADC_CR_ADCALDIF_Pos = 0x1e       // Position of ADCALDIF field.
	ADC_CR_ADCALDIF_Msk = 0x40000000 // Bit mask of ADCALDIF field.
	ADC_CR_ADCALDIF     = 0x40000000 // Bit ADCALDIF.
	ADC_CR_DEEPPWD_Pos  = 0x1d       // Position of DEEPPWD field.
	ADC_CR_DEEPPWD_Msk  = 0x20000000 // Bit mask of DEEPPWD field.
	ADC_CR_DEEPPWD      = 0x20000000 // Bit DEEPPWD.
	ADC_CR_ADVREGEN_Pos = 0x1c       // Position of ADVREGEN field.
	ADC_CR_ADVREGEN_Msk = 0x10000000 // Bit mask of ADVREGEN field.
	ADC_CR_ADVREGEN     = 0x10000000 // Bit ADVREGEN.
	ADC_CR_JADSTP_Pos   = 0x5        // Position of JADSTP field.
	ADC_CR_JADSTP_Msk   = 0x20       // Bit mask of JADSTP field.
	ADC_CR_JADSTP       = 0x20       // Bit JADSTP.
	ADC_CR_ADSTP_Pos    = 0x4        // Position of ADSTP field.
	ADC_CR_ADSTP_Msk    = 0x10       // Bit mask of ADSTP field.
	ADC_CR_ADSTP        = 0x10       // Bit ADSTP.
	ADC_CR_JADSTART_Pos = 0x3        // Position of JADSTART field.
	ADC_CR_JADSTART_Msk = 0x8        // Bit mask of JADSTART field.
	ADC_CR_JADSTART     = 0x8        // Bit JADSTART.
	ADC_CR_ADSTART_Pos  = 0x2        // Position of ADSTART field.
	ADC_CR_ADSTART_Msk  = 0x4        // Bit mask of ADSTART field.
	ADC_CR_ADSTART      = 0x4        // Bit ADSTART.
	ADC_CR_ADDIS_Pos    = 0x1        // Position of ADDIS field.
	ADC_CR_ADDIS_Msk    = 0x2        // Bit mask of ADDIS field.
	ADC_CR_ADDIS        = 0x2        // Bit ADDIS.
	ADC_CR_ADEN_Pos     = 0x0        // Position of ADEN field.
	ADC_CR_ADEN_Msk     = 0x1        // Bit mask of ADEN field.
	ADC_CR_ADEN         = 0x1        // Bit ADEN.

	// CFGR: configuration register
	ADC_CFGR_JQDIS_Pos    = 0x1f       // Position of JQDIS field.
	ADC_CFGR_JQDIS_Msk    = 0x80000000 // Bit mask of JQDIS field.
	ADC_CFGR_JQDIS        = 0x80000000 // Bit JQDIS.
	ADC_CFGR_AWDCH1CH_Pos = 0x1a       // Position of AWDCH1CH field.
	ADC_CFGR_AWDCH1CH_Msk = 0x7c000000 // Bit mask of AWDCH1CH field.
	ADC_CFGR_JAUTO_Pos    = 0x19       // Position of JAUTO field.
	ADC_CFGR_JAUTO_Msk    = 0x2000000  // Bit mask of JAUTO field.
	ADC_CFGR_JAUTO        = 0x2000000  // Bit JAUTO.
	ADC_CFGR_JAWD1EN_Pos  = 0x18       // Position of JAWD1EN field.
	ADC_CFGR_JAWD1EN_Msk  = 0x1000000  // Bit mask of JAWD1EN field.
	ADC_CFGR_JAWD1EN      = 0x1000000  // Bit JAWD1EN.
	ADC_CFGR_AWD1EN_Pos   = 0x17       // Position of AWD1EN field.
	ADC_CFGR_AWD1EN_Msk   = 0x800000   // Bit mask of AWD1EN field.
	ADC_CFGR_AWD1EN       = 0x800000   // Bit AWD1EN.
	ADC_CFGR_AWD1SGL_Pos  = 0x16       // Position of AWD1SGL field.
	ADC_CFGR_AWD1SGL_Msk  = 0x400000   // Bit mask of AWD1SGL field.
	ADC_CFGR_AWD1SGL      = 0x400000   // Bit AWD1SGL.
	ADC_CFGR_JQM_Pos      = 0x15       // Position of JQM field.
	ADC_CFGR_JQM_Msk      = 0x200000   // Bit mask of JQM field.
	ADC_CFGR_JQM          = 0x200000   // Bit JQM.
	ADC_CFGR_JDISCEN_Pos  = 0x14       // Position of JDISCEN field.
	ADC_CFGR_JDISCEN_Msk  = 0x100000   // Bit mask of JDISCEN field.
	ADC_CFGR_JDISCEN      = 0x100000   // Bit JDISCEN.
	ADC_CFGR_DISCNUM_Pos  = 0x11       // Position of DISCNUM field.
	ADC_CFGR_DISCNUM_Msk  = 0xe0000    // Bit mask of DISCNUM field.
	ADC_CFGR_DISCEN_Pos   = 0x10       // Position of DISCEN field.
	ADC_CFGR_DISCEN_Msk   = 0x10000    // Bit mask of DISCEN field.
	ADC_CFGR_DISCEN       = 0x10000    // Bit DISCEN.
	ADC_CFGR_ALIGN_Pos    = 0xf        // Position of ALIGN field.
	ADC_CFGR_ALIGN_Msk    = 0x8000     // Bit mask of ALIGN field.
	ADC_CFGR_ALIGN        = 0x8000     // Bit ALIGN.
	ADC_CFGR_AUTDLY_Pos   = 0xe        // Position of AUTDLY field.
	ADC_CFGR_AUTDLY_Msk   = 0x4000     // Bit mask of AUTDLY field.
	ADC_CFGR_AUTDLY       = 0x4000     // Bit AUTDLY.
	ADC_CFGR_CONT_Pos     = 0xd        // Position of CONT field.
	ADC_CFGR_CONT_Msk     = 0x2000     // Bit mask of CONT field.
	ADC_CFGR_CONT         = 0x2000     // Bit CONT.
	ADC_CFGR_OVRMOD_Pos   = 0xc        // Position of OVRMOD field.
	ADC_CFGR_OVRMOD_Msk   = 0x1000     // Bit mask of OVRMOD field.
	ADC_CFGR_OVRMOD       = 0x1000     // Bit OVRMOD.
	ADC_CFGR_EXTEN_Pos    = 0xa        // Position of EXTEN field.
	ADC_CFGR_EXTEN_Msk    = 0xc00      // Bit mask of EXTEN field.
	ADC_CFGR_EXTSEL_Pos   = 0x6        // Position of EXTSEL field.
	ADC_CFGR_EXTSEL_Msk   = 0x3c0      // Bit mask of EXTSEL field.
	ADC_CFGR_ALIGN_5_Pos  = 0x5        // Position of ALIGN_5 field.
	ADC_CFGR_ALIGN_5_Msk  = 0x20       // Bit mask of ALIGN_5 field.
	ADC_CFGR_ALIGN_5      = 0x20       // Bit ALIGN_5.
	ADC_CFGR_RES_Pos      = 0x3        // Position of RES field.
	ADC_CFGR_RES_Msk      = 0x18       // Bit mask of RES field.
	ADC_CFGR_DMACFG_Pos   = 0x1        // Position of DMACFG field.
	ADC_CFGR_DMACFG_Msk   = 0x2        // Bit mask of DMACFG field.
	ADC_CFGR_DMACFG       = 0x2        // Bit DMACFG.
	ADC_CFGR_DMAEN_Pos    = 0x0        // Position of DMAEN field.
	ADC_CFGR_DMAEN_Msk    = 0x1        // Bit mask of DMAEN field.
	ADC_CFGR_DMAEN        = 0x1        // Bit DMAEN.

	// CFGR2: configuration register
	ADC_CFGR2_SMPTRIG_Pos = 0x1b      // Position of SMPTRIG field.
	ADC_CFGR2_SMPTRIG_Msk = 0x8000000 // Bit mask of SMPTRIG field.
	ADC_CFGR2_SMPTRIG     = 0x8000000 // Bit SMPTRIG.
	ADC_CFGR2_BULB_Pos    = 0x1a      // Position of BULB field.
	ADC_CFGR2_BULB_Msk    = 0x4000000 // Bit mask of BULB field.
	ADC_CFGR2_BULB        = 0x4000000 // Bit BULB.
	ADC_CFGR2_SWTRIG_Pos  = 0x19      // Position of SWTRIG field.
	ADC_CFGR2_SWTRIG_Msk  = 0x2000000 // Bit mask of SWTRIG field.
	ADC_CFGR2_SWTRIG      = 0x2000000 // Bit SWTRIG.
	ADC_CFGR2_GCOMP_Pos   = 0x10      // Position of GCOMP field.
	ADC_CFGR2_GCOMP_Msk   = 0x10000   // Bit mask of GCOMP field.
	ADC_CFGR2_GCOMP       = 0x10000   // Bit GCOMP.
	ADC_CFGR2_ROVSM_Pos   = 0xa       // Position of ROVSM field.
	ADC_CFGR2_ROVSM_Msk   = 0x400     // Bit mask of ROVSM field.
	ADC_CFGR2_ROVSM       = 0x400     // Bit ROVSM.
	ADC_CFGR2_TROVS_Pos   = 0x9       // Position of TROVS field.
	ADC_CFGR2_TROVS_Msk   = 0x200     // Bit mask of TROVS field.
	ADC_CFGR2_TROVS       = 0x200     // Bit TROVS.
	ADC_CFGR2_OVSS_Pos    = 0x5       // Position of OVSS field.
	ADC_CFGR2_OVSS_Msk    = 0x1e0     // Bit mask of OVSS field.
	ADC_CFGR2_OVSR_Pos    = 0x2       // Position of OVSR field.
	ADC_CFGR2_OVSR_Msk    = 0x1c      // Bit mask of OVSR field.
	ADC_CFGR2_JOVSE_Pos   = 0x1       // Position of JOVSE field.
	ADC_CFGR2_JOVSE_Msk   = 0x2       // Bit mask of JOVSE field.
	ADC_CFGR2_JOVSE       = 0x2       // Bit JOVSE.
	ADC_CFGR2_ROVSE_Pos   = 0x0       // Position of ROVSE field.
	ADC_CFGR2_ROVSE_Msk   = 0x1       // Bit mask of ROVSE field.
	ADC_CFGR2_ROVSE       = 0x1       // Bit ROVSE.

	// SMPR1: sample time register 1
	ADC_SMPR1_SMP9_Pos    = 0x1b       // Position of SMP9 field.
	ADC_SMPR1_SMP9_Msk    = 0x38000000 // Bit mask of SMP9 field.
	ADC_SMPR1_SMP8_Pos    = 0x18       // Position of SMP8 field.
	ADC_SMPR1_SMP8_Msk    = 0x7000000  // Bit mask of SMP8 field.
	ADC_SMPR1_SMP7_Pos    = 0x15       // Position of SMP7 field.
	ADC_SMPR1_SMP7_Msk    = 0xe00000   // Bit mask of SMP7 field.
	ADC_SMPR1_SMP6_Pos    = 0x12       // Position of SMP6 field.
	ADC_SMPR1_SMP6_Msk    = 0x1c0000   // Bit mask of SMP6 field.
	ADC_SMPR1_SMP5_Pos    = 0xf        // Position of SMP5 field.
	ADC_SMPR1_SMP5_Msk    = 0x38000    // Bit mask of SMP5 field.
	ADC_SMPR1_SMP4_Pos    = 0xc        // Position of SMP4 field.
	ADC_SMPR1_SMP4_Msk    = 0x7000     // Bit mask of SMP4 field.
	ADC_SMPR1_SMP3_Pos    = 0x9        // Position of SMP3 field.
	ADC_SMPR1_SMP3_Msk    = 0xe00      // Bit mask of SMP3 field.
	ADC_SMPR1_SMP2_Pos    = 0x6        // Position of SMP2 field.
	ADC_SMPR1_SMP2_Msk    = 0x1c0      // Bit mask of SMP2 field.
	ADC_SMPR1_SMP1_Pos    = 0x3        // Position of SMP1 field.
	ADC_SMPR1_SMP1_Msk    = 0x38       // Bit mask of SMP1 field.
	ADC_SMPR1_SMPPLUS_Pos = 0x1f       // Position of SMPPLUS field.
	ADC_SMPR1_SMPPLUS_Msk = 0x80000000 // Bit mask of SMPPLUS field.
	ADC_SMPR1_SMPPLUS     = 0x80000000 // Bit SMPPLUS.
	ADC_SMPR1_SMP0_Pos    = 0x0        // Position of SMP0 field.
	ADC_SMPR1_SMP0_Msk    = 0x7        // Bit mask of SMP0 field.

	// SMPR2: sample time register 2
	ADC_SMPR2_SMP18_Pos = 0x18      // Position of SMP18 field.
	ADC_SMPR2_SMP18_Msk = 0x7000000 // Bit mask of SMP18 field.
	ADC_SMPR2_SMP17_Pos = 0x15      // Position of SMP17 field.
	ADC_SMPR2_SMP17_Msk = 0xe00000  // Bit mask of SMP17 field.
	ADC_SMPR2_SMP16_Pos = 0x12      // Position of SMP16 field.
	ADC_SMPR2_SMP16_Msk = 0x1c0000  // Bit mask of SMP16 field.
	ADC_SMPR2_SMP15_Pos = 0xf       // Position of SMP15 field.
	ADC_SMPR2_SMP15_Msk = 0x38000   // Bit mask of SMP15 field.
	ADC_SMPR2_SMP14_Pos = 0xc       // Position of SMP14 field.
	ADC_SMPR2_SMP14_Msk = 0x7000    // Bit mask of SMP14 field.
	ADC_SMPR2_SMP13_Pos = 0x9       // Position of SMP13 field.
	ADC_SMPR2_SMP13_Msk = 0xe00     // Bit mask of SMP13 field.
	ADC_SMPR2_SMP12_Pos = 0x6       // Position of SMP12 field.
	ADC_SMPR2_SMP12_Msk = 0x1c0     // Bit mask of SMP12 field.
	ADC_SMPR2_SMP11_Pos = 0x3       // Position of SMP11 field.
	ADC_SMPR2_SMP11_Msk = 0x38      // Bit mask of SMP11 field.
	ADC_SMPR2_SMP10_Pos = 0x0       // Position of SMP10 field.
	ADC_SMPR2_SMP10_Msk = 0x7       // Bit mask of SMP10 field.

	// TR1: watchdog threshold register 1
	ADC_TR1_HT1_Pos     = 0x10      // Position of HT1 field.
	ADC_TR1_HT1_Msk     = 0xfff0000 // Bit mask of HT1 field.
	ADC_TR1_AWDFILT_Pos = 0xc       // Position of AWDFILT field.
	ADC_TR1_AWDFILT_Msk = 0x7000    // Bit mask of AWDFILT field.
	ADC_TR1_LT1_Pos     = 0x0       // Position of LT1 field.
	ADC_TR1_LT1_Msk     = 0xfff     // Bit mask of LT1 field.

	// TR2: watchdog threshold register
	ADC_TR2_HT2_Pos = 0x10     // Position of HT2 field.
	ADC_TR2_HT2_Msk = 0xff0000 // Bit mask of HT2 field.
	ADC_TR2_LT2_Pos = 0x0      // Position of LT2 field.
	ADC_TR2_LT2_Msk = 0xff     // Bit mask of LT2 field.

	// TR3: watchdog threshold register 3
	ADC_TR3_HT3_Pos = 0x10     // Position of HT3 field.
	ADC_TR3_HT3_Msk = 0xff0000 // Bit mask of HT3 field.
	ADC_TR3_LT3_Pos = 0x0      // Position of LT3 field.
	ADC_TR3_LT3_Msk = 0xff     // Bit mask of LT3 field.

	// SQR1: regular sequence register 1
	ADC_SQR1_SQ4_Pos = 0x18       // Position of SQ4 field.
	ADC_SQR1_SQ4_Msk = 0x1f000000 // Bit mask of SQ4 field.
	ADC_SQR1_SQ3_Pos = 0x12       // Position of SQ3 field.
	ADC_SQR1_SQ3_Msk = 0x7c0000   // Bit mask of SQ3 field.
	ADC_SQR1_SQ2_Pos = 0xc        // Position of SQ2 field.
	ADC_SQR1_SQ2_Msk = 0x1f000    // Bit mask of SQ2 field.
	ADC_SQR1_SQ1_Pos = 0x6        // Position of SQ1 field.
	ADC_SQR1_SQ1_Msk = 0x7c0      // Bit mask of SQ1 field.
	ADC_SQR1_L_Pos   = 0x0        // Position of L field.
	ADC_SQR1_L_Msk   = 0xf        // Bit mask of L field.

	// SQR2: regular sequence register 2
	ADC_SQR2_SQ9_Pos = 0x18       // Position of SQ9 field.
	ADC_SQR2_SQ9_Msk = 0x1f000000 // Bit mask of SQ9 field.
	ADC_SQR2_SQ8_Pos = 0x12       // Position of SQ8 field.
	ADC_SQR2_SQ8_Msk = 0x7c0000   // Bit mask of SQ8 field.
	ADC_SQR2_SQ7_Pos = 0xc        // Position of SQ7 field.
	ADC_SQR2_SQ7_Msk = 0x1f000    // Bit mask of SQ7 field.
	ADC_SQR2_SQ6_Pos = 0x6        // Position of SQ6 field.
	ADC_SQR2_SQ6_Msk = 0x7c0      // Bit mask of SQ6 field.
	ADC_SQR2_SQ5_Pos = 0x0        // Position of SQ5 field.
	ADC_SQR2_SQ5_Msk = 0x1f       // Bit mask of SQ5 field.

	// SQR3: regular sequence register 3
	ADC_SQR3_SQ14_Pos = 0x18       // Position of SQ14 field.
	ADC_SQR3_SQ14_Msk = 0x1f000000 // Bit mask of SQ14 field.
	ADC_SQR3_SQ13_Pos = 0x12       // Position of SQ13 field.
	ADC_SQR3_SQ13_Msk = 0x7c0000   // Bit mask of SQ13 field.
	ADC_SQR3_SQ12_Pos = 0xc        // Position of SQ12 field.
	ADC_SQR3_SQ12_Msk = 0x1f000    // Bit mask of SQ12 field.
	ADC_SQR3_SQ11_Pos = 0x6        // Position of SQ11 field.
	ADC_SQR3_SQ11_Msk = 0x7c0      // Bit mask of SQ11 field.
	ADC_SQR3_SQ10_Pos = 0x0        // Position of SQ10 field.
	ADC_SQR3_SQ10_Msk = 0x1f       // Bit mask of SQ10 field.

	// SQR4: regular sequence register 4
	ADC_SQR4_SQ16_Pos = 0x6   // Position of SQ16 field.
	ADC_SQR4_SQ16_Msk = 0x7c0 // Bit mask of SQ16 field.
	ADC_SQR4_SQ15_Pos = 0x0   // Position of SQ15 field.
	ADC_SQR4_SQ15_Msk = 0x1f  // Bit mask of SQ15 field.

	// DR: regular Data Register
	ADC_DR_RDATA_Pos = 0x0    // Position of RDATA field.
	ADC_DR_RDATA_Msk = 0xffff // Bit mask of RDATA field.

	// JSQR: injected sequence register
	ADC_JSQR_JSQ4_Pos    = 0x1b       // Position of JSQ4 field.
	ADC_JSQR_JSQ4_Msk    = 0xf8000000 // Bit mask of JSQ4 field.
	ADC_JSQR_JSQ3_Pos    = 0x15       // Position of JSQ3 field.
	ADC_JSQR_JSQ3_Msk    = 0x3e00000  // Bit mask of JSQ3 field.
	ADC_JSQR_JSQ2_Pos    = 0xf        // Position of JSQ2 field.
	ADC_JSQR_JSQ2_Msk    = 0xf8000    // Bit mask of JSQ2 field.
	ADC_JSQR_JSQ1_Pos    = 0x9        // Position of JSQ1 field.
	ADC_JSQR_JSQ1_Msk    = 0x3e00     // Bit mask of JSQ1 field.
	ADC_JSQR_JEXTEN_Pos  = 0x7        // Position of JEXTEN field.
	ADC_JSQR_JEXTEN_Msk  = 0x180      // Bit mask of JEXTEN field.
	ADC_JSQR_JEXTSEL_Pos = 0x2        // Position of JEXTSEL field.
	ADC_JSQR_JEXTSEL_Msk = 0x7c       // Bit mask of JEXTSEL field.
	ADC_JSQR_JL_Pos      = 0x0        // Position of JL field.
	ADC_JSQR_JL_Msk      = 0x3        // Bit mask of JL field.

	// OFR1: offset register 1
	ADC_OFR1_OFFSET1_EN_Pos = 0x1f       // Position of OFFSET1_EN field.
	ADC_OFR1_OFFSET1_EN_Msk = 0x80000000 // Bit mask of OFFSET1_EN field.
	ADC_OFR1_OFFSET1_EN     = 0x80000000 // Bit OFFSET1_EN.
	ADC_OFR1_OFFSET1_CH_Pos = 0x1a       // Position of OFFSET1_CH field.
	ADC_OFR1_OFFSET1_CH_Msk = 0x7c000000 // Bit mask of OFFSET1_CH field.
	ADC_OFR1_SATEN_Pos      = 0x19       // Position of SATEN field.
	ADC_OFR1_SATEN_Msk      = 0x2000000  // Bit mask of SATEN field.
	ADC_OFR1_SATEN          = 0x2000000  // Bit SATEN.
	ADC_OFR1_OFFSETPOS_Pos  = 0x18       // Position of OFFSETPOS field.
	ADC_OFR1_OFFSETPOS_Msk  = 0x1000000  // Bit mask of OFFSETPOS field.
	ADC_OFR1_OFFSETPOS      = 0x1000000  // Bit OFFSETPOS.
	ADC_OFR1_OFFSET1_Pos    = 0x0        // Position of OFFSET1 field.
	ADC_OFR1_OFFSET1_Msk    = 0xfff      // Bit mask of OFFSET1 field.

	// OFR2: offset register 2
	ADC_OFR2_OFFSET1_EN_Pos = 0x1f       // Position of OFFSET1_EN field.
	ADC_OFR2_OFFSET1_EN_Msk = 0x80000000 // Bit mask of OFFSET1_EN field.
	ADC_OFR2_OFFSET1_EN     = 0x80000000 // Bit OFFSET1_EN.
	ADC_OFR2_OFFSET1_CH_Pos = 0x1a       // Position of OFFSET1_CH field.
	ADC_OFR2_OFFSET1_CH_Msk = 0x7c000000 // Bit mask of OFFSET1_CH field.
	ADC_OFR2_SATEN_Pos      = 0x19       // Position of SATEN field.
	ADC_OFR2_SATEN_Msk      = 0x2000000  // Bit mask of SATEN field.
	ADC_OFR2_SATEN          = 0x2000000  // Bit SATEN.
	ADC_OFR2_OFFSETPOS_Pos  = 0x18       // Position of OFFSETPOS field.
	ADC_OFR2_OFFSETPOS_Msk  = 0x1000000  // Bit mask of OFFSETPOS field.
	ADC_OFR2_OFFSETPOS      = 0x1000000  // Bit OFFSETPOS.
	ADC_OFR2_OFFSET1_Pos    = 0x0        // Position of OFFSET1 field.
	ADC_OFR2_OFFSET1_Msk    = 0xfff      // Bit mask of OFFSET1 field.

	// OFR3: offset register 3
	ADC_OFR3_OFFSET1_EN_Pos = 0x1f       // Position of OFFSET1_EN field.
	ADC_OFR3_OFFSET1_EN_Msk = 0x80000000 // Bit mask of OFFSET1_EN field.
	ADC_OFR3_OFFSET1_EN     = 0x80000000 // Bit OFFSET1_EN.
	ADC_OFR3_OFFSET1_CH_Pos = 0x1a       // Position of OFFSET1_CH field.
	ADC_OFR3_OFFSET1_CH_Msk = 0x7c000000 // Bit mask of OFFSET1_CH field.
	ADC_OFR3_SATEN_Pos      = 0x19       // Position of SATEN field.
	ADC_OFR3_SATEN_Msk      = 0x2000000  // Bit mask of SATEN field.
	ADC_OFR3_SATEN          = 0x2000000  // Bit SATEN.
	ADC_OFR3_OFFSETPOS_Pos  = 0x18       // Position of OFFSETPOS field.
	ADC_OFR3_OFFSETPOS_Msk  = 0x1000000  // Bit mask of OFFSETPOS field.
	ADC_OFR3_OFFSETPOS      = 0x1000000  // Bit OFFSETPOS.
	ADC_OFR3_OFFSET1_Pos    = 0x0        // Position of OFFSET1 field.
	ADC_OFR3_OFFSET1_Msk    = 0xfff      // Bit mask of OFFSET1 field.

	// OFR4: offset register 4
	ADC_OFR4_OFFSET1_EN_Pos = 0x1f       // Position of OFFSET1_EN field.
	ADC_OFR4_OFFSET1_EN_Msk = 0x80000000 // Bit mask of OFFSET1_EN field.
	ADC_OFR4_OFFSET1_EN     = 0x80000000 // Bit OFFSET1_EN.
	ADC_OFR4_OFFSET1_CH_Pos = 0x1a       // Position of OFFSET1_CH field.
	ADC_OFR4_OFFSET1_CH_Msk = 0x7c000000 // Bit mask of OFFSET1_CH field.
	ADC_OFR4_SATEN_Pos      = 0x19       // Position of SATEN field.
	ADC_OFR4_SATEN_Msk      = 0x2000000  // Bit mask of SATEN field.
	ADC_OFR4_SATEN          = 0x2000000  // Bit SATEN.
	ADC_OFR4_OFFSETPOS_Pos  = 0x18       // Position of OFFSETPOS field.
	ADC_OFR4_OFFSETPOS_Msk  = 0x1000000  // Bit mask of OFFSETPOS field.
	ADC_OFR4_OFFSETPOS      = 0x1000000  // Bit OFFSETPOS.
	ADC_OFR4_OFFSET1_Pos    = 0x0        // Position of OFFSET1 field.
	ADC_OFR4_OFFSET1_Msk    = 0xfff      // Bit mask of OFFSET1 field.

	// JDR1: injected data register 1
	ADC_JDR1_JDATA1_Pos = 0x0    // Position of JDATA1 field.
	ADC_JDR1_JDATA1_Msk = 0xffff // Bit mask of JDATA1 field.

	// JDR2: injected data register 2
	ADC_JDR2_JDATA2_Pos = 0x0    // Position of JDATA2 field.
	ADC_JDR2_JDATA2_Msk = 0xffff // Bit mask of JDATA2 field.

	// JDR3: injected data register 3
	ADC_JDR3_JDATA3_Pos = 0x0    // Position of JDATA3 field.
	ADC_JDR3_JDATA3_Msk = 0xffff // Bit mask of JDATA3 field.

	// JDR4: injected data register 4
	ADC_JDR4_JDATA4_Pos = 0x0    // Position of JDATA4 field.
	ADC_JDR4_JDATA4_Msk = 0xffff // Bit mask of JDATA4 field.

	// AWD2CR: Analog Watchdog 2 Configuration           Register
	ADC_AWD2CR_AWD2CH_Pos = 0x0     // Position of AWD2CH field.
	ADC_AWD2CR_AWD2CH_Msk = 0x7ffff // Bit mask of AWD2CH field.

	// AWD3CR: Analog Watchdog 3 Configuration           Register
	ADC_AWD3CR_AWD3CH_Pos = 0x0     // Position of AWD3CH field.
	ADC_AWD3CR_AWD3CH_Msk = 0x7ffff // Bit mask of AWD3CH field.

	// DIFSEL: Differential Mode Selection Register           2
	ADC_DIFSEL_DIFSEL_0_Pos    = 0x0     // Position of DIFSEL_0 field.
	ADC_DIFSEL_DIFSEL_0_Msk    = 0x1     // Bit mask of DIFSEL_0 field.
	ADC_DIFSEL_DIFSEL_0        = 0x1     // Bit DIFSEL_0.
	ADC_DIFSEL_DIFSEL_1_18_Pos = 0x1     // Position of DIFSEL_1_18 field.
	ADC_DIFSEL_DIFSEL_1_18_Msk = 0x7fffe // Bit mask of DIFSEL_1_18 field.

	// CALFACT: Calibration Factors
	ADC_CALFACT_CALFACT_D_Pos = 0x10     // Position of CALFACT_D field.
	ADC_CALFACT_CALFACT_D_Msk = 0x7f0000 // Bit mask of CALFACT_D field.
	ADC_CALFACT_CALFACT_S_Pos = 0x0      // Position of CALFACT_S field.
	ADC_CALFACT_CALFACT_S_Msk = 0x7f     // Bit mask of CALFACT_S field.

	// GCOMP: Gain compensation Register
	ADC_GCOMP_GCOMPCOEFF_Pos = 0x0    // Position of GCOMPCOEFF field.
	ADC_GCOMP_GCOMPCOEFF_Msk = 0x3fff // Bit mask of GCOMPCOEFF field.
)

// Bitfields for FMAC: Filter Math Accelerator
const (
	// X1BUFCFG: FMAC X1 Buffer Configuration           register
	FMAC_X1BUFCFG_X1_BASE_Pos     = 0x0       // Position of X1_BASE field.
	FMAC_X1BUFCFG_X1_BASE_Msk     = 0xff      // Bit mask of X1_BASE field.
	FMAC_X1BUFCFG_X1_BUF_SIZE_Pos = 0x8       // Position of X1_BUF_SIZE field.
	FMAC_X1BUFCFG_X1_BUF_SIZE_Msk = 0xff00    // Bit mask of X1_BUF_SIZE field.
	FMAC_X1BUFCFG_FULL_WM_Pos     = 0x18      // Position of FULL_WM field.
	FMAC_X1BUFCFG_FULL_WM_Msk     = 0x3000000 // Bit mask of FULL_WM field.

	// X2BUFCFG: FMAC X2 Buffer Configuration           register
	FMAC_X2BUFCFG_X2_BASE_Pos     = 0x0    // Position of X2_BASE field.
	FMAC_X2BUFCFG_X2_BASE_Msk     = 0xff   // Bit mask of X2_BASE field.
	FMAC_X2BUFCFG_X2_BUF_SIZE_Pos = 0x8    // Position of X2_BUF_SIZE field.
	FMAC_X2BUFCFG_X2_BUF_SIZE_Msk = 0xff00 // Bit mask of X2_BUF_SIZE field.

	// YBUFCFG: FMAC Y Buffer Configuration           register
	FMAC_YBUFCFG_Y_BASE_Pos     = 0x0       // Position of Y_BASE field.
	FMAC_YBUFCFG_Y_BASE_Msk     = 0xff      // Bit mask of Y_BASE field.
	FMAC_YBUFCFG_Y_BUF_SIZE_Pos = 0x8       // Position of Y_BUF_SIZE field.
	FMAC_YBUFCFG_Y_BUF_SIZE_Msk = 0xff00    // Bit mask of Y_BUF_SIZE field.
	FMAC_YBUFCFG_EMPTY_WM_Pos   = 0x18      // Position of EMPTY_WM field.
	FMAC_YBUFCFG_EMPTY_WM_Msk   = 0x3000000 // Bit mask of EMPTY_WM field.

	// PARAM: FMAC Parameter register
	FMAC_PARAM_START_Pos = 0x1f       // Position of START field.
	FMAC_PARAM_START_Msk = 0x80000000 // Bit mask of START field.
	FMAC_PARAM_START     = 0x80000000 // Bit START.
	FMAC_PARAM_FUNC_Pos  = 0x18       // Position of FUNC field.
	FMAC_PARAM_FUNC_Msk  = 0x7f000000 // Bit mask of FUNC field.
	FMAC_PARAM_R_Pos     = 0x10       // Position of R field.
	FMAC_PARAM_R_Msk     = 0xff0000   // Bit mask of R field.
	FMAC_PARAM_Q_Pos     = 0x8        // Position of Q field.
	FMAC_PARAM_Q_Msk     = 0xff00     // Bit mask of Q field.
	FMAC_PARAM_P_Pos     = 0x0        // Position of P field.
	FMAC_PARAM_P_Msk     = 0xff       // Bit mask of P field.

	// CR: FMAC Control register
	FMAC_CR_RESET_Pos   = 0x10    // Position of RESET field.
	FMAC_CR_RESET_Msk   = 0x10000 // Bit mask of RESET field.
	FMAC_CR_RESET       = 0x10000 // Bit RESET.
	FMAC_CR_CLIPEN_Pos  = 0xf     // Position of CLIPEN field.
	FMAC_CR_CLIPEN_Msk  = 0x8000  // Bit mask of CLIPEN field.
	FMAC_CR_CLIPEN      = 0x8000  // Bit CLIPEN.
	FMAC_CR_DMAWEN_Pos  = 0x9     // Position of DMAWEN field.
	FMAC_CR_DMAWEN_Msk  = 0x200   // Bit mask of DMAWEN field.
	FMAC_CR_DMAWEN      = 0x200   // Bit DMAWEN.
	FMAC_CR_DMAREN_Pos  = 0x8     // Position of DMAREN field.
	FMAC_CR_DMAREN_Msk  = 0x100   // Bit mask of DMAREN field.
	FMAC_CR_DMAREN      = 0x100   // Bit DMAREN.
	FMAC_CR_SATIEN_Pos  = 0x4     // Position of SATIEN field.
	FMAC_CR_SATIEN_Msk  = 0x10    // Bit mask of SATIEN field.
	FMAC_CR_SATIEN      = 0x10    // Bit SATIEN.
	FMAC_CR_UNFLIEN_Pos = 0x3     // Position of UNFLIEN field.
	FMAC_CR_UNFLIEN_Msk = 0x8     // Bit mask of UNFLIEN field.
	FMAC_CR_UNFLIEN     = 0x8     // Bit UNFLIEN.
	FMAC_CR_OVFLIEN_Pos = 0x2     // Position of OVFLIEN field.
	FMAC_CR_OVFLIEN_Msk = 0x4     // Bit mask of OVFLIEN field.
	FMAC_CR_OVFLIEN     = 0x4     // Bit OVFLIEN.
	FMAC_CR_WIEN_Pos    = 0x1     // Position of WIEN field.
	FMAC_CR_WIEN_Msk    = 0x2     // Bit mask of WIEN field.
	FMAC_CR_WIEN        = 0x2     // Bit WIEN.
	FMAC_CR_RIEN_Pos    = 0x0     // Position of RIEN field.
	FMAC_CR_RIEN_Msk    = 0x1     // Bit mask of RIEN field.
	FMAC_CR_RIEN        = 0x1     // Bit RIEN.

	// SR: FMAC Status register
	FMAC_SR_YEMPTY_Pos = 0x0   // Position of YEMPTY field.
	FMAC_SR_YEMPTY_Msk = 0x1   // Bit mask of YEMPTY field.
	FMAC_SR_YEMPTY     = 0x1   // Bit YEMPTY.
	FMAC_SR_X1FULL_Pos = 0x1   // Position of X1FULL field.
	FMAC_SR_X1FULL_Msk = 0x2   // Bit mask of X1FULL field.
	FMAC_SR_X1FULL     = 0x2   // Bit X1FULL.
	FMAC_SR_OVFL_Pos   = 0x8   // Position of OVFL field.
	FMAC_SR_OVFL_Msk   = 0x100 // Bit mask of OVFL field.
	FMAC_SR_OVFL       = 0x100 // Bit OVFL.
	FMAC_SR_UNFL_Pos   = 0x9   // Position of UNFL field.
	FMAC_SR_UNFL_Msk   = 0x200 // Bit mask of UNFL field.
	FMAC_SR_UNFL       = 0x200 // Bit UNFL.
	FMAC_SR_SAT_Pos    = 0xa   // Position of SAT field.
	FMAC_SR_SAT_Msk    = 0x400 // Bit mask of SAT field.
	FMAC_SR_SAT        = 0x400 // Bit SAT.

	// WDATA: FMAC Write Data register
	FMAC_WDATA_WDATA_Pos = 0x0    // Position of WDATA field.
	FMAC_WDATA_WDATA_Msk = 0xffff // Bit mask of WDATA field.

	// RDATA: FMAC Read Data register
	FMAC_RDATA_RDATA_Pos = 0x0    // Position of RDATA field.
	FMAC_RDATA_RDATA_Msk = 0xffff // Bit mask of RDATA field.
)

// Bitfields for CORDIC: CORDIC Co-processor
const (
	// CSR: CORDIC Control Status register
	CORDIC_CSR_FUNC_Pos      = 0x0        // Position of FUNC field.
	CORDIC_CSR_FUNC_Msk      = 0xf        // Bit mask of FUNC field.
	CORDIC_CSR_PRECISION_Pos = 0x4        // Position of PRECISION field.
	CORDIC_CSR_PRECISION_Msk = 0xf0       // Bit mask of PRECISION field.
	CORDIC_CSR_SCALE_Pos     = 0x8        // Position of SCALE field.
	CORDIC_CSR_SCALE_Msk     = 0x700      // Bit mask of SCALE field.
	CORDIC_CSR_IEN_Pos       = 0x10       // Position of IEN field.
	CORDIC_CSR_IEN_Msk       = 0x10000    // Bit mask of IEN field.
	CORDIC_CSR_IEN           = 0x10000    // Bit IEN.
	CORDIC_CSR_DMAREN_Pos    = 0x11       // Position of DMAREN field.
	CORDIC_CSR_DMAREN_Msk    = 0x20000    // Bit mask of DMAREN field.
	CORDIC_CSR_DMAREN        = 0x20000    // Bit DMAREN.
	CORDIC_CSR_DMAWEN_Pos    = 0x12       // Position of DMAWEN field.
	CORDIC_CSR_DMAWEN_Msk    = 0x40000    // Bit mask of DMAWEN field.
	CORDIC_CSR_DMAWEN        = 0x40000    // Bit DMAWEN.
	CORDIC_CSR_NRES_Pos      = 0x13       // Position of NRES field.
	CORDIC_CSR_NRES_Msk      = 0x80000    // Bit mask of NRES field.
	CORDIC_CSR_NRES          = 0x80000    // Bit NRES.
	CORDIC_CSR_NARGS_Pos     = 0x14       // Position of NARGS field.
	CORDIC_CSR_NARGS_Msk     = 0x100000   // Bit mask of NARGS field.
	CORDIC_CSR_NARGS         = 0x100000   // Bit NARGS.
	CORDIC_CSR_RESSIZE_Pos   = 0x15       // Position of RESSIZE field.
	CORDIC_CSR_RESSIZE_Msk   = 0x200000   // Bit mask of RESSIZE field.
	CORDIC_CSR_RESSIZE       = 0x200000   // Bit RESSIZE.
	CORDIC_CSR_ARGSIZE_Pos   = 0x16       // Position of ARGSIZE field.
	CORDIC_CSR_ARGSIZE_Msk   = 0x400000   // Bit mask of ARGSIZE field.
	CORDIC_CSR_ARGSIZE       = 0x400000   // Bit ARGSIZE.
	CORDIC_CSR_RRDY_Pos      = 0x1f       // Position of RRDY field.
	CORDIC_CSR_RRDY_Msk      = 0x80000000 // Bit mask of RRDY field.
	CORDIC_CSR_RRDY          = 0x80000000 // Bit RRDY.

	// WDATA: FMAC Write Data register
	CORDIC_WDATA_ARG_Pos = 0x0        // Position of ARG field.
	CORDIC_WDATA_ARG_Msk = 0xffffffff // Bit mask of ARG field.

	// RDATA: FMAC Read Data register
	CORDIC_RDATA_RES_Pos = 0x0        // Position of RES field.
	CORDIC_RDATA_RES_Msk = 0xffffffff // Bit mask of RES field.
)

// Bitfields for SAI: Serial audio interface
const (
	// ACR1: AConfiguration register 1
	SAI_ACR1_MCKEN_Pos    = 0x1b      // Position of MCKEN field.
	SAI_ACR1_MCKEN_Msk    = 0x8000000 // Bit mask of MCKEN field.
	SAI_ACR1_MCKEN        = 0x8000000 // Bit MCKEN.
	SAI_ACR1_OSR_Pos      = 0x1a      // Position of OSR field.
	SAI_ACR1_OSR_Msk      = 0x4000000 // Bit mask of OSR field.
	SAI_ACR1_OSR          = 0x4000000 // Bit OSR.
	SAI_ACR1_MCJDIV_Pos   = 0x14      // Position of MCJDIV field.
	SAI_ACR1_MCJDIV_Msk   = 0x3f00000 // Bit mask of MCJDIV field.
	SAI_ACR1_NODIV_Pos    = 0x13      // Position of NODIV field.
	SAI_ACR1_NODIV_Msk    = 0x80000   // Bit mask of NODIV field.
	SAI_ACR1_NODIV        = 0x80000   // Bit NODIV.
	SAI_ACR1_DMAEN_Pos    = 0x11      // Position of DMAEN field.
	SAI_ACR1_DMAEN_Msk    = 0x20000   // Bit mask of DMAEN field.
	SAI_ACR1_DMAEN        = 0x20000   // Bit DMAEN.
	SAI_ACR1_SAIAEN_Pos   = 0x10      // Position of SAIAEN field.
	SAI_ACR1_SAIAEN_Msk   = 0x10000   // Bit mask of SAIAEN field.
	SAI_ACR1_SAIAEN       = 0x10000   // Bit SAIAEN.
	SAI_ACR1_OutDri_Pos   = 0xd       // Position of OutDri field.
	SAI_ACR1_OutDri_Msk   = 0x2000    // Bit mask of OutDri field.
	SAI_ACR1_OutDri       = 0x2000    // Bit OutDri.
	SAI_ACR1_MONO_Pos     = 0xc       // Position of MONO field.
	SAI_ACR1_MONO_Msk     = 0x1000    // Bit mask of MONO field.
	SAI_ACR1_MONO         = 0x1000    // Bit MONO.
	SAI_ACR1_SYNCEN_Pos   = 0xa       // Position of SYNCEN field.
	SAI_ACR1_SYNCEN_Msk   = 0xc00     // Bit mask of SYNCEN field.
	SAI_ACR1_CKSTR_Pos    = 0x9       // Position of CKSTR field.
	SAI_ACR1_CKSTR_Msk    = 0x200     // Bit mask of CKSTR field.
	SAI_ACR1_CKSTR        = 0x200     // Bit CKSTR.
	SAI_ACR1_LSBFIRST_Pos = 0x8       // Position of LSBFIRST field.
	SAI_ACR1_LSBFIRST_Msk = 0x100     // Bit mask of LSBFIRST field.
	SAI_ACR1_LSBFIRST     = 0x100     // Bit LSBFIRST.
	SAI_ACR1_DS_Pos       = 0x5       // Position of DS field.
	SAI_ACR1_DS_Msk       = 0xe0      // Bit mask of DS field.
	SAI_ACR1_PRTCFG_Pos   = 0x2       // Position of PRTCFG field.
	SAI_ACR1_PRTCFG_Msk   = 0xc       // Bit mask of PRTCFG field.
	SAI_ACR1_MODE_Pos     = 0x0       // Position of MODE field.
	SAI_ACR1_MODE_Msk     = 0x3       // Bit mask of MODE field.

	// ACR2: AConfiguration register 2
	SAI_ACR2_COMP_Pos    = 0xe    // Position of COMP field.
	SAI_ACR2_COMP_Msk    = 0xc000 // Bit mask of COMP field.
	SAI_ACR2_CPL_Pos     = 0xd    // Position of CPL field.
	SAI_ACR2_CPL_Msk     = 0x2000 // Bit mask of CPL field.
	SAI_ACR2_CPL         = 0x2000 // Bit CPL.
	SAI_ACR2_MUTECN_Pos  = 0x7    // Position of MUTECN field.
	SAI_ACR2_MUTECN_Msk  = 0x1f80 // Bit mask of MUTECN field.
	SAI_ACR2_MUTEVAL_Pos = 0x6    // Position of MUTEVAL field.
	SAI_ACR2_MUTEVAL_Msk = 0x40   // Bit mask of MUTEVAL field.
	SAI_ACR2_MUTEVAL     = 0x40   // Bit MUTEVAL.
	SAI_ACR2_MUTE_Pos    = 0x5    // Position of MUTE field.
	SAI_ACR2_MUTE_Msk    = 0x20   // Bit mask of MUTE field.
	SAI_ACR2_MUTE        = 0x20   // Bit MUTE.
	SAI_ACR2_TRIS_Pos    = 0x4    // Position of TRIS field.
	SAI_ACR2_TRIS_Msk    = 0x10   // Bit mask of TRIS field.
	SAI_ACR2_TRIS        = 0x10   // Bit TRIS.
	SAI_ACR2_FFLUS_Pos   = 0x3    // Position of FFLUS field.
	SAI_ACR2_FFLUS_Msk   = 0x8    // Bit mask of FFLUS field.
	SAI_ACR2_FFLUS       = 0x8    // Bit FFLUS.
	SAI_ACR2_FTH_Pos     = 0x0    // Position of FTH field.
	SAI_ACR2_FTH_Msk     = 0x7    // Bit mask of FTH field.

	// AFRCR: AFRCR
	SAI_AFRCR_FSOFF_Pos = 0x12    // Position of FSOFF field.
	SAI_AFRCR_FSOFF_Msk = 0x40000 // Bit mask of FSOFF field.
	SAI_AFRCR_FSOFF     = 0x40000 // Bit FSOFF.
	SAI_AFRCR_FSPOL_Pos = 0x11    // Position of FSPOL field.
	SAI_AFRCR_FSPOL_Msk = 0x20000 // Bit mask of FSPOL field.
	SAI_AFRCR_FSPOL     = 0x20000 // Bit FSPOL.
	SAI_AFRCR_FSDEF_Pos = 0x10    // Position of FSDEF field.
	SAI_AFRCR_FSDEF_Msk = 0x10000 // Bit mask of FSDEF field.
	SAI_AFRCR_FSDEF     = 0x10000 // Bit FSDEF.
	SAI_AFRCR_FSALL_Pos = 0x8     // Position of FSALL field.
	SAI_AFRCR_FSALL_Msk = 0x7f00  // Bit mask of FSALL field.
	SAI_AFRCR_FRL_Pos   = 0x0     // Position of FRL field.
	SAI_AFRCR_FRL_Msk   = 0xff    // Bit mask of FRL field.

	// ASLOTR: ASlot register
	SAI_ASLOTR_SLOTEN_Pos = 0x10       // Position of SLOTEN field.
	SAI_ASLOTR_SLOTEN_Msk = 0xffff0000 // Bit mask of SLOTEN field.
	SAI_ASLOTR_NBSLOT_Pos = 0x8        // Position of NBSLOT field.
	SAI_ASLOTR_NBSLOT_Msk = 0xf00      // Bit mask of NBSLOT field.
	SAI_ASLOTR_SLOTSZ_Pos = 0x6        // Position of SLOTSZ field.
	SAI_ASLOTR_SLOTSZ_Msk = 0xc0       // Bit mask of SLOTSZ field.
	SAI_ASLOTR_FBOFF_Pos  = 0x0        // Position of FBOFF field.
	SAI_ASLOTR_FBOFF_Msk  = 0x1f       // Bit mask of FBOFF field.

	// AIM: AInterrupt mask register2
	SAI_AIM_LFSDET_Pos   = 0x6  // Position of LFSDET field.
	SAI_AIM_LFSDET_Msk   = 0x40 // Bit mask of LFSDET field.
	SAI_AIM_LFSDET       = 0x40 // Bit LFSDET.
	SAI_AIM_AFSDETIE_Pos = 0x5  // Position of AFSDETIE field.
	SAI_AIM_AFSDETIE_Msk = 0x20 // Bit mask of AFSDETIE field.
	SAI_AIM_AFSDETIE     = 0x20 // Bit AFSDETIE.
	SAI_AIM_CNRDYIE_Pos  = 0x4  // Position of CNRDYIE field.
	SAI_AIM_CNRDYIE_Msk  = 0x10 // Bit mask of CNRDYIE field.
	SAI_AIM_CNRDYIE      = 0x10 // Bit CNRDYIE.
	SAI_AIM_FREQIE_Pos   = 0x3  // Position of FREQIE field.
	SAI_AIM_FREQIE_Msk   = 0x8  // Bit mask of FREQIE field.
	SAI_AIM_FREQIE       = 0x8  // Bit FREQIE.
	SAI_AIM_WCKCFG_Pos   = 0x2  // Position of WCKCFG field.
	SAI_AIM_WCKCFG_Msk   = 0x4  // Bit mask of WCKCFG field.
	SAI_AIM_WCKCFG       = 0x4  // Bit WCKCFG.
	SAI_AIM_MUTEDET_Pos  = 0x1  // Position of MUTEDET field.
	SAI_AIM_MUTEDET_Msk  = 0x2  // Bit mask of MUTEDET field.
	SAI_AIM_MUTEDET      = 0x2  // Bit MUTEDET.
	SAI_AIM_OVRUDRIE_Pos = 0x0  // Position of OVRUDRIE field.
	SAI_AIM_OVRUDRIE_Msk = 0x1  // Bit mask of OVRUDRIE field.
	SAI_AIM_OVRUDRIE     = 0x1  // Bit OVRUDRIE.

	// ASR: AStatus register
	SAI_ASR_FLVL_Pos    = 0x10    // Position of FLVL field.
	SAI_ASR_FLVL_Msk    = 0x70000 // Bit mask of FLVL field.
	SAI_ASR_LFSDET_Pos  = 0x6     // Position of LFSDET field.
	SAI_ASR_LFSDET_Msk  = 0x40    // Bit mask of LFSDET field.
	SAI_ASR_LFSDET      = 0x40    // Bit LFSDET.
	SAI_ASR_AFSDET_Pos  = 0x5     // Position of AFSDET field.
	SAI_ASR_AFSDET_Msk  = 0x20    // Bit mask of AFSDET field.
	SAI_ASR_AFSDET      = 0x20    // Bit AFSDET.
	SAI_ASR_CNRDY_Pos   = 0x4     // Position of CNRDY field.
	SAI_ASR_CNRDY_Msk   = 0x10    // Bit mask of CNRDY field.
	SAI_ASR_CNRDY       = 0x10    // Bit CNRDY.
	SAI_ASR_FREQ_Pos    = 0x3     // Position of FREQ field.
	SAI_ASR_FREQ_Msk    = 0x8     // Bit mask of FREQ field.
	SAI_ASR_FREQ        = 0x8     // Bit FREQ.
	SAI_ASR_WCKCFG_Pos  = 0x2     // Position of WCKCFG field.
	SAI_ASR_WCKCFG_Msk  = 0x4     // Bit mask of WCKCFG field.
	SAI_ASR_WCKCFG      = 0x4     // Bit WCKCFG.
	SAI_ASR_MUTEDET_Pos = 0x1     // Position of MUTEDET field.
	SAI_ASR_MUTEDET_Msk = 0x2     // Bit mask of MUTEDET field.
	SAI_ASR_MUTEDET     = 0x2     // Bit MUTEDET.
	SAI_ASR_OVRUDR_Pos  = 0x0     // Position of OVRUDR field.
	SAI_ASR_OVRUDR_Msk  = 0x1     // Bit mask of OVRUDR field.
	SAI_ASR_OVRUDR      = 0x1     // Bit OVRUDR.

	// ACLRFR: AClear flag register
	SAI_ACLRFR_LFSDET_Pos  = 0x6  // Position of LFSDET field.
	SAI_ACLRFR_LFSDET_Msk  = 0x40 // Bit mask of LFSDET field.
	SAI_ACLRFR_LFSDET      = 0x40 // Bit LFSDET.
	SAI_ACLRFR_CAFSDET_Pos = 0x5  // Position of CAFSDET field.
	SAI_ACLRFR_CAFSDET_Msk = 0x20 // Bit mask of CAFSDET field.
	SAI_ACLRFR_CAFSDET     = 0x20 // Bit CAFSDET.
	SAI_ACLRFR_CNRDY_Pos   = 0x4  // Position of CNRDY field.
	SAI_ACLRFR_CNRDY_Msk   = 0x10 // Bit mask of CNRDY field.
	SAI_ACLRFR_CNRDY       = 0x10 // Bit CNRDY.
	SAI_ACLRFR_WCKCFG_Pos  = 0x2  // Position of WCKCFG field.
	SAI_ACLRFR_WCKCFG_Msk  = 0x4  // Bit mask of WCKCFG field.
	SAI_ACLRFR_WCKCFG      = 0x4  // Bit WCKCFG.
	SAI_ACLRFR_MUTEDET_Pos = 0x1  // Position of MUTEDET field.
	SAI_ACLRFR_MUTEDET_Msk = 0x2  // Bit mask of MUTEDET field.
	SAI_ACLRFR_MUTEDET     = 0x2  // Bit MUTEDET.
	SAI_ACLRFR_OVRUDR_Pos  = 0x0  // Position of OVRUDR field.
	SAI_ACLRFR_OVRUDR_Msk  = 0x1  // Bit mask of OVRUDR field.
	SAI_ACLRFR_OVRUDR      = 0x1  // Bit OVRUDR.

	// ADR: AData register
	SAI_ADR_DATA_Pos = 0x0        // Position of DATA field.
	SAI_ADR_DATA_Msk = 0xffffffff // Bit mask of DATA field.

	// BCR1: BConfiguration register 1
	SAI_BCR1_MCKEN_Pos    = 0x1b      // Position of MCKEN field.
	SAI_BCR1_MCKEN_Msk    = 0x8000000 // Bit mask of MCKEN field.
	SAI_BCR1_MCKEN        = 0x8000000 // Bit MCKEN.
	SAI_BCR1_OSR_Pos      = 0x1a      // Position of OSR field.
	SAI_BCR1_OSR_Msk      = 0x4000000 // Bit mask of OSR field.
	SAI_BCR1_OSR          = 0x4000000 // Bit OSR.
	SAI_BCR1_MCJDIV_Pos   = 0x14      // Position of MCJDIV field.
	SAI_BCR1_MCJDIV_Msk   = 0x3f00000 // Bit mask of MCJDIV field.
	SAI_BCR1_NODIV_Pos    = 0x13      // Position of NODIV field.
	SAI_BCR1_NODIV_Msk    = 0x80000   // Bit mask of NODIV field.
	SAI_BCR1_NODIV        = 0x80000   // Bit NODIV.
	SAI_BCR1_DMAEN_Pos    = 0x11      // Position of DMAEN field.
	SAI_BCR1_DMAEN_Msk    = 0x20000   // Bit mask of DMAEN field.
	SAI_BCR1_DMAEN        = 0x20000   // Bit DMAEN.
	SAI_BCR1_SAIBEN_Pos   = 0x10      // Position of SAIBEN field.
	SAI_BCR1_SAIBEN_Msk   = 0x10000   // Bit mask of SAIBEN field.
	SAI_BCR1_SAIBEN       = 0x10000   // Bit SAIBEN.
	SAI_BCR1_OutDri_Pos   = 0xd       // Position of OutDri field.
	SAI_BCR1_OutDri_Msk   = 0x2000    // Bit mask of OutDri field.
	SAI_BCR1_OutDri       = 0x2000    // Bit OutDri.
	SAI_BCR1_MONO_Pos     = 0xc       // Position of MONO field.
	SAI_BCR1_MONO_Msk     = 0x1000    // Bit mask of MONO field.
	SAI_BCR1_MONO         = 0x1000    // Bit MONO.
	SAI_BCR1_SYNCEN_Pos   = 0xa       // Position of SYNCEN field.
	SAI_BCR1_SYNCEN_Msk   = 0xc00     // Bit mask of SYNCEN field.
	SAI_BCR1_CKSTR_Pos    = 0x9       // Position of CKSTR field.
	SAI_BCR1_CKSTR_Msk    = 0x200     // Bit mask of CKSTR field.
	SAI_BCR1_CKSTR        = 0x200     // Bit CKSTR.
	SAI_BCR1_LSBFIRST_Pos = 0x8       // Position of LSBFIRST field.
	SAI_BCR1_LSBFIRST_Msk = 0x100     // Bit mask of LSBFIRST field.
	SAI_BCR1_LSBFIRST     = 0x100     // Bit LSBFIRST.
	SAI_BCR1_DS_Pos       = 0x5       // Position of DS field.
	SAI_BCR1_DS_Msk       = 0xe0      // Bit mask of DS field.
	SAI_BCR1_PRTCFG_Pos   = 0x2       // Position of PRTCFG field.
	SAI_BCR1_PRTCFG_Msk   = 0xc       // Bit mask of PRTCFG field.
	SAI_BCR1_MODE_Pos     = 0x0       // Position of MODE field.
	SAI_BCR1_MODE_Msk     = 0x3       // Bit mask of MODE field.

	// BCR2: BConfiguration register 2
	SAI_BCR2_COMP_Pos    = 0xe    // Position of COMP field.
	SAI_BCR2_COMP_Msk    = 0xc000 // Bit mask of COMP field.
	SAI_BCR2_CPL_Pos     = 0xd    // Position of CPL field.
	SAI_BCR2_CPL_Msk     = 0x2000 // Bit mask of CPL field.
	SAI_BCR2_CPL         = 0x2000 // Bit CPL.
	SAI_BCR2_MUTECN_Pos  = 0x7    // Position of MUTECN field.
	SAI_BCR2_MUTECN_Msk  = 0x1f80 // Bit mask of MUTECN field.
	SAI_BCR2_MUTEVAL_Pos = 0x6    // Position of MUTEVAL field.
	SAI_BCR2_MUTEVAL_Msk = 0x40   // Bit mask of MUTEVAL field.
	SAI_BCR2_MUTEVAL     = 0x40   // Bit MUTEVAL.
	SAI_BCR2_MUTE_Pos    = 0x5    // Position of MUTE field.
	SAI_BCR2_MUTE_Msk    = 0x20   // Bit mask of MUTE field.
	SAI_BCR2_MUTE        = 0x20   // Bit MUTE.
	SAI_BCR2_TRIS_Pos    = 0x4    // Position of TRIS field.
	SAI_BCR2_TRIS_Msk    = 0x10   // Bit mask of TRIS field.
	SAI_BCR2_TRIS        = 0x10   // Bit TRIS.
	SAI_BCR2_FFLUS_Pos   = 0x3    // Position of FFLUS field.
	SAI_BCR2_FFLUS_Msk   = 0x8    // Bit mask of FFLUS field.
	SAI_BCR2_FFLUS       = 0x8    // Bit FFLUS.
	SAI_BCR2_FTH_Pos     = 0x0    // Position of FTH field.
	SAI_BCR2_FTH_Msk     = 0x7    // Bit mask of FTH field.

	// BFRCR: BFRCR
	SAI_BFRCR_FSOFF_Pos = 0x12    // Position of FSOFF field.
	SAI_BFRCR_FSOFF_Msk = 0x40000 // Bit mask of FSOFF field.
	SAI_BFRCR_FSOFF     = 0x40000 // Bit FSOFF.
	SAI_BFRCR_FSPOL_Pos = 0x11    // Position of FSPOL field.
	SAI_BFRCR_FSPOL_Msk = 0x20000 // Bit mask of FSPOL field.
	SAI_BFRCR_FSPOL     = 0x20000 // Bit FSPOL.
	SAI_BFRCR_FSDEF_Pos = 0x10    // Position of FSDEF field.
	SAI_BFRCR_FSDEF_Msk = 0x10000 // Bit mask of FSDEF field.
	SAI_BFRCR_FSDEF     = 0x10000 // Bit FSDEF.
	SAI_BFRCR_FSALL_Pos = 0x8     // Position of FSALL field.
	SAI_BFRCR_FSALL_Msk = 0x7f00  // Bit mask of FSALL field.
	SAI_BFRCR_FRL_Pos   = 0x0     // Position of FRL field.
	SAI_BFRCR_FRL_Msk   = 0xff    // Bit mask of FRL field.

	// BSLOTR: BSlot register
	SAI_BSLOTR_SLOTEN_Pos = 0x10       // Position of SLOTEN field.
	SAI_BSLOTR_SLOTEN_Msk = 0xffff0000 // Bit mask of SLOTEN field.
	SAI_BSLOTR_NBSLOT_Pos = 0x8        // Position of NBSLOT field.
	SAI_BSLOTR_NBSLOT_Msk = 0xf00      // Bit mask of NBSLOT field.
	SAI_BSLOTR_SLOTSZ_Pos = 0x6        // Position of SLOTSZ field.
	SAI_BSLOTR_SLOTSZ_Msk = 0xc0       // Bit mask of SLOTSZ field.
	SAI_BSLOTR_FBOFF_Pos  = 0x0        // Position of FBOFF field.
	SAI_BSLOTR_FBOFF_Msk  = 0x1f       // Bit mask of FBOFF field.

	// BIM: BInterrupt mask register2
	SAI_BIM_LFSDETIE_Pos = 0x6  // Position of LFSDETIE field.
	SAI_BIM_LFSDETIE_Msk = 0x40 // Bit mask of LFSDETIE field.
	SAI_BIM_LFSDETIE     = 0x40 // Bit LFSDETIE.
	SAI_BIM_AFSDETIE_Pos = 0x5  // Position of AFSDETIE field.
	SAI_BIM_AFSDETIE_Msk = 0x20 // Bit mask of AFSDETIE field.
	SAI_BIM_AFSDETIE     = 0x20 // Bit AFSDETIE.
	SAI_BIM_CNRDYIE_Pos  = 0x4  // Position of CNRDYIE field.
	SAI_BIM_CNRDYIE_Msk  = 0x10 // Bit mask of CNRDYIE field.
	SAI_BIM_CNRDYIE      = 0x10 // Bit CNRDYIE.
	SAI_BIM_FREQIE_Pos   = 0x3  // Position of FREQIE field.
	SAI_BIM_FREQIE_Msk   = 0x8  // Bit mask of FREQIE field.
	SAI_BIM_FREQIE       = 0x8  // Bit FREQIE.
	SAI_BIM_WCKCFG_Pos   = 0x2  // Position of WCKCFG field.
	SAI_BIM_WCKCFG_Msk   = 0x4  // Bit mask of WCKCFG field.
	SAI_BIM_WCKCFG       = 0x4  // Bit WCKCFG.
	SAI_BIM_MUTEDET_Pos  = 0x1  // Position of MUTEDET field.
	SAI_BIM_MUTEDET_Msk  = 0x2  // Bit mask of MUTEDET field.
	SAI_BIM_MUTEDET      = 0x2  // Bit MUTEDET.
	SAI_BIM_OVRUDRIE_Pos = 0x0  // Position of OVRUDRIE field.
	SAI_BIM_OVRUDRIE_Msk = 0x1  // Bit mask of OVRUDRIE field.
	SAI_BIM_OVRUDRIE     = 0x1  // Bit OVRUDRIE.

	// BSR: BStatus register
	SAI_BSR_FLVL_Pos    = 0x10    // Position of FLVL field.
	SAI_BSR_FLVL_Msk    = 0x70000 // Bit mask of FLVL field.
	SAI_BSR_LFSDET_Pos  = 0x6     // Position of LFSDET field.
	SAI_BSR_LFSDET_Msk  = 0x40    // Bit mask of LFSDET field.
	SAI_BSR_LFSDET      = 0x40    // Bit LFSDET.
	SAI_BSR_AFSDET_Pos  = 0x5     // Position of AFSDET field.
	SAI_BSR_AFSDET_Msk  = 0x20    // Bit mask of AFSDET field.
	SAI_BSR_AFSDET      = 0x20    // Bit AFSDET.
	SAI_BSR_CNRDY_Pos   = 0x4     // Position of CNRDY field.
	SAI_BSR_CNRDY_Msk   = 0x10    // Bit mask of CNRDY field.
	SAI_BSR_CNRDY       = 0x10    // Bit CNRDY.
	SAI_BSR_FREQ_Pos    = 0x3     // Position of FREQ field.
	SAI_BSR_FREQ_Msk    = 0x8     // Bit mask of FREQ field.
	SAI_BSR_FREQ        = 0x8     // Bit FREQ.
	SAI_BSR_WCKCFG_Pos  = 0x2     // Position of WCKCFG field.
	SAI_BSR_WCKCFG_Msk  = 0x4     // Bit mask of WCKCFG field.
	SAI_BSR_WCKCFG      = 0x4     // Bit WCKCFG.
	SAI_BSR_MUTEDET_Pos = 0x1     // Position of MUTEDET field.
	SAI_BSR_MUTEDET_Msk = 0x2     // Bit mask of MUTEDET field.
	SAI_BSR_MUTEDET     = 0x2     // Bit MUTEDET.
	SAI_BSR_OVRUDR_Pos  = 0x0     // Position of OVRUDR field.
	SAI_BSR_OVRUDR_Msk  = 0x1     // Bit mask of OVRUDR field.
	SAI_BSR_OVRUDR      = 0x1     // Bit OVRUDR.

	// BCLRFR: BClear flag register
	SAI_BCLRFR_LFSDET_Pos  = 0x6  // Position of LFSDET field.
	SAI_BCLRFR_LFSDET_Msk  = 0x40 // Bit mask of LFSDET field.
	SAI_BCLRFR_LFSDET      = 0x40 // Bit LFSDET.
	SAI_BCLRFR_CAFSDET_Pos = 0x5  // Position of CAFSDET field.
	SAI_BCLRFR_CAFSDET_Msk = 0x20 // Bit mask of CAFSDET field.
	SAI_BCLRFR_CAFSDET     = 0x20 // Bit CAFSDET.
	SAI_BCLRFR_CNRDY_Pos   = 0x4  // Position of CNRDY field.
	SAI_BCLRFR_CNRDY_Msk   = 0x10 // Bit mask of CNRDY field.
	SAI_BCLRFR_CNRDY       = 0x10 // Bit CNRDY.
	SAI_BCLRFR_WCKCFG_Pos  = 0x2  // Position of WCKCFG field.
	SAI_BCLRFR_WCKCFG_Msk  = 0x4  // Bit mask of WCKCFG field.
	SAI_BCLRFR_WCKCFG      = 0x4  // Bit WCKCFG.
	SAI_BCLRFR_MUTEDET_Pos = 0x1  // Position of MUTEDET field.
	SAI_BCLRFR_MUTEDET_Msk = 0x2  // Bit mask of MUTEDET field.
	SAI_BCLRFR_MUTEDET     = 0x2  // Bit MUTEDET.
	SAI_BCLRFR_OVRUDR_Pos  = 0x0  // Position of OVRUDR field.
	SAI_BCLRFR_OVRUDR_Msk  = 0x1  // Bit mask of OVRUDR field.
	SAI_BCLRFR_OVRUDR      = 0x1  // Bit OVRUDR.

	// BDR: BData register
	SAI_BDR_DATA_Pos = 0x0        // Position of DATA field.
	SAI_BDR_DATA_Msk = 0xffffffff // Bit mask of DATA field.

	// PDMCR: PDM control register
	SAI_PDMCR_PDMEN_Pos  = 0x0   // Position of PDMEN field.
	SAI_PDMCR_PDMEN_Msk  = 0x1   // Bit mask of PDMEN field.
	SAI_PDMCR_PDMEN      = 0x1   // Bit PDMEN.
	SAI_PDMCR_MICNBR_Pos = 0x4   // Position of MICNBR field.
	SAI_PDMCR_MICNBR_Msk = 0x30  // Bit mask of MICNBR field.
	SAI_PDMCR_CKEN1_Pos  = 0x8   // Position of CKEN1 field.
	SAI_PDMCR_CKEN1_Msk  = 0x100 // Bit mask of CKEN1 field.
	SAI_PDMCR_CKEN1      = 0x100 // Bit CKEN1.
	SAI_PDMCR_CKEN2_Pos  = 0x9   // Position of CKEN2 field.
	SAI_PDMCR_CKEN2_Msk  = 0x200 // Bit mask of CKEN2 field.
	SAI_PDMCR_CKEN2      = 0x200 // Bit CKEN2.
	SAI_PDMCR_CKEN3_Pos  = 0xa   // Position of CKEN3 field.
	SAI_PDMCR_CKEN3_Msk  = 0x400 // Bit mask of CKEN3 field.
	SAI_PDMCR_CKEN3      = 0x400 // Bit CKEN3.
	SAI_PDMCR_CKEN4_Pos  = 0xb   // Position of CKEN4 field.
	SAI_PDMCR_CKEN4_Msk  = 0x800 // Bit mask of CKEN4 field.
	SAI_PDMCR_CKEN4      = 0x800 // Bit CKEN4.

	// PDMDLY: PDM delay register
	SAI_PDMDLY_DLYM1L_Pos = 0x0        // Position of DLYM1L field.
	SAI_PDMDLY_DLYM1L_Msk = 0x7        // Bit mask of DLYM1L field.
	SAI_PDMDLY_DLYM1R_Pos = 0x4        // Position of DLYM1R field.
	SAI_PDMDLY_DLYM1R_Msk = 0x70       // Bit mask of DLYM1R field.
	SAI_PDMDLY_DLYM2L_Pos = 0x8        // Position of DLYM2L field.
	SAI_PDMDLY_DLYM2L_Msk = 0x700      // Bit mask of DLYM2L field.
	SAI_PDMDLY_DLYM2R_Pos = 0xc        // Position of DLYM2R field.
	SAI_PDMDLY_DLYM2R_Msk = 0x7000     // Bit mask of DLYM2R field.
	SAI_PDMDLY_DLYM3L_Pos = 0x10       // Position of DLYM3L field.
	SAI_PDMDLY_DLYM3L_Msk = 0x70000    // Bit mask of DLYM3L field.
	SAI_PDMDLY_DLYM3R_Pos = 0x14       // Position of DLYM3R field.
	SAI_PDMDLY_DLYM3R_Msk = 0x700000   // Bit mask of DLYM3R field.
	SAI_PDMDLY_DLYM4L_Pos = 0x18       // Position of DLYM4L field.
	SAI_PDMDLY_DLYM4L_Msk = 0x7000000  // Bit mask of DLYM4L field.
	SAI_PDMDLY_DLYM4R_Pos = 0x1c       // Position of DLYM4R field.
	SAI_PDMDLY_DLYM4R_Msk = 0x70000000 // Bit mask of DLYM4R field.
)

// Bitfields for TAMP: Tamper and backup registers
const (
	// CR1: control register 1
	TAMP_CR1_TAMP1E_Pos  = 0x0      // Position of TAMP1E field.
	TAMP_CR1_TAMP1E_Msk  = 0x1      // Bit mask of TAMP1E field.
	TAMP_CR1_TAMP1E      = 0x1      // Bit TAMP1E.
	TAMP_CR1_TAMP2E_Pos  = 0x1      // Position of TAMP2E field.
	TAMP_CR1_TAMP2E_Msk  = 0x2      // Bit mask of TAMP2E field.
	TAMP_CR1_TAMP2E      = 0x2      // Bit TAMP2E.
	TAMP_CR1_TAMP3E_Pos  = 0x2      // Position of TAMP3E field.
	TAMP_CR1_TAMP3E_Msk  = 0x4      // Bit mask of TAMP3E field.
	TAMP_CR1_TAMP3E      = 0x4      // Bit TAMP3E.
	TAMP_CR1_ITAMP3E_Pos = 0x12     // Position of ITAMP3E field.
	TAMP_CR1_ITAMP3E_Msk = 0x40000  // Bit mask of ITAMP3E field.
	TAMP_CR1_ITAMP3E     = 0x40000  // Bit ITAMP3E.
	TAMP_CR1_ITAMP4E_Pos = 0x13     // Position of ITAMP4E field.
	TAMP_CR1_ITAMP4E_Msk = 0x80000  // Bit mask of ITAMP4E field.
	TAMP_CR1_ITAMP4E     = 0x80000  // Bit ITAMP4E.
	TAMP_CR1_ITAMP5E_Pos = 0x14     // Position of ITAMP5E field.
	TAMP_CR1_ITAMP5E_Msk = 0x100000 // Bit mask of ITAMP5E field.
	TAMP_CR1_ITAMP5E     = 0x100000 // Bit ITAMP5E.
	TAMP_CR1_ITAMP6E_Pos = 0x15     // Position of ITAMP6E field.
	TAMP_CR1_ITAMP6E_Msk = 0x200000 // Bit mask of ITAMP6E field.
	TAMP_CR1_ITAMP6E     = 0x200000 // Bit ITAMP6E.

	// CR2: control register 2
	TAMP_CR2_TAMP1NOER_Pos = 0x0       // Position of TAMP1NOER field.
	TAMP_CR2_TAMP1NOER_Msk = 0x1       // Bit mask of TAMP1NOER field.
	TAMP_CR2_TAMP1NOER     = 0x1       // Bit TAMP1NOER.
	TAMP_CR2_TAMP2NOER_Pos = 0x1       // Position of TAMP2NOER field.
	TAMP_CR2_TAMP2NOER_Msk = 0x2       // Bit mask of TAMP2NOER field.
	TAMP_CR2_TAMP2NOER     = 0x2       // Bit TAMP2NOER.
	TAMP_CR2_TAMP3NOER_Pos = 0x2       // Position of TAMP3NOER field.
	TAMP_CR2_TAMP3NOER_Msk = 0x4       // Bit mask of TAMP3NOER field.
	TAMP_CR2_TAMP3NOER     = 0x4       // Bit TAMP3NOER.
	TAMP_CR2_TAMP1MSK_Pos  = 0x10      // Position of TAMP1MSK field.
	TAMP_CR2_TAMP1MSK_Msk  = 0x10000   // Bit mask of TAMP1MSK field.
	TAMP_CR2_TAMP1MSK      = 0x10000   // Bit TAMP1MSK.
	TAMP_CR2_TAMP2MSK_Pos  = 0x11      // Position of TAMP2MSK field.
	TAMP_CR2_TAMP2MSK_Msk  = 0x20000   // Bit mask of TAMP2MSK field.
	TAMP_CR2_TAMP2MSK      = 0x20000   // Bit TAMP2MSK.
	TAMP_CR2_TAMP3MSK_Pos  = 0x12      // Position of TAMP3MSK field.
	TAMP_CR2_TAMP3MSK_Msk  = 0x40000   // Bit mask of TAMP3MSK field.
	TAMP_CR2_TAMP3MSK      = 0x40000   // Bit TAMP3MSK.
	TAMP_CR2_TAMP1TRG_Pos  = 0x18      // Position of TAMP1TRG field.
	TAMP_CR2_TAMP1TRG_Msk  = 0x1000000 // Bit mask of TAMP1TRG field.
	TAMP_CR2_TAMP1TRG      = 0x1000000 // Bit TAMP1TRG.
	TAMP_CR2_TAMP2TRG_Pos  = 0x19      // Position of TAMP2TRG field.
	TAMP_CR2_TAMP2TRG_Msk  = 0x2000000 // Bit mask of TAMP2TRG field.
	TAMP_CR2_TAMP2TRG      = 0x2000000 // Bit TAMP2TRG.
	TAMP_CR2_TAMP3TRG_Pos  = 0x1a      // Position of TAMP3TRG field.
	TAMP_CR2_TAMP3TRG_Msk  = 0x4000000 // Bit mask of TAMP3TRG field.
	TAMP_CR2_TAMP3TRG      = 0x4000000 // Bit TAMP3TRG.

	// FLTCR: TAMP filter control register
	TAMP_FLTCR_TAMPFREQ_Pos  = 0x0  // Position of TAMPFREQ field.
	TAMP_FLTCR_TAMPFREQ_Msk  = 0x7  // Bit mask of TAMPFREQ field.
	TAMP_FLTCR_TAMPFLT_Pos   = 0x3  // Position of TAMPFLT field.
	TAMP_FLTCR_TAMPFLT_Msk   = 0x18 // Bit mask of TAMPFLT field.
	TAMP_FLTCR_TAMPPRCH_Pos  = 0x5  // Position of TAMPPRCH field.
	TAMP_FLTCR_TAMPPRCH_Msk  = 0x60 // Bit mask of TAMPPRCH field.
	TAMP_FLTCR_TAMPPUDIS_Pos = 0x7  // Position of TAMPPUDIS field.
	TAMP_FLTCR_TAMPPUDIS_Msk = 0x80 // Bit mask of TAMPPUDIS field.
	TAMP_FLTCR_TAMPPUDIS     = 0x80 // Bit TAMPPUDIS.

	// IER: TAMP interrupt enable register
	TAMP_IER_TAMP1IE_Pos  = 0x0      // Position of TAMP1IE field.
	TAMP_IER_TAMP1IE_Msk  = 0x1      // Bit mask of TAMP1IE field.
	TAMP_IER_TAMP1IE      = 0x1      // Bit TAMP1IE.
	TAMP_IER_TAMP2IE_Pos  = 0x1      // Position of TAMP2IE field.
	TAMP_IER_TAMP2IE_Msk  = 0x2      // Bit mask of TAMP2IE field.
	TAMP_IER_TAMP2IE      = 0x2      // Bit TAMP2IE.
	TAMP_IER_TAMP3IE_Pos  = 0x2      // Position of TAMP3IE field.
	TAMP_IER_TAMP3IE_Msk  = 0x4      // Bit mask of TAMP3IE field.
	TAMP_IER_TAMP3IE      = 0x4      // Bit TAMP3IE.
	TAMP_IER_ITAMP3IE_Pos = 0x12     // Position of ITAMP3IE field.
	TAMP_IER_ITAMP3IE_Msk = 0x40000  // Bit mask of ITAMP3IE field.
	TAMP_IER_ITAMP3IE     = 0x40000  // Bit ITAMP3IE.
	TAMP_IER_ITAMP4IE_Pos = 0x13     // Position of ITAMP4IE field.
	TAMP_IER_ITAMP4IE_Msk = 0x80000  // Bit mask of ITAMP4IE field.
	TAMP_IER_ITAMP4IE     = 0x80000  // Bit ITAMP4IE.
	TAMP_IER_ITAMP5IE_Pos = 0x14     // Position of ITAMP5IE field.
	TAMP_IER_ITAMP5IE_Msk = 0x100000 // Bit mask of ITAMP5IE field.
	TAMP_IER_ITAMP5IE     = 0x100000 // Bit ITAMP5IE.
	TAMP_IER_ITAMP6IE_Pos = 0x15     // Position of ITAMP6IE field.
	TAMP_IER_ITAMP6IE_Msk = 0x200000 // Bit mask of ITAMP6IE field.
	TAMP_IER_ITAMP6IE     = 0x200000 // Bit ITAMP6IE.

	// SR: TAMP status register
	TAMP_SR_TAMP1F_Pos  = 0x0      // Position of TAMP1F field.
	TAMP_SR_TAMP1F_Msk  = 0x1      // Bit mask of TAMP1F field.
	TAMP_SR_TAMP1F      = 0x1      // Bit TAMP1F.
	TAMP_SR_TAMP2F_Pos  = 0x1      // Position of TAMP2F field.
	TAMP_SR_TAMP2F_Msk  = 0x2      // Bit mask of TAMP2F field.
	TAMP_SR_TAMP2F      = 0x2      // Bit TAMP2F.
	TAMP_SR_TAMP3F_Pos  = 0x2      // Position of TAMP3F field.
	TAMP_SR_TAMP3F_Msk  = 0x4      // Bit mask of TAMP3F field.
	TAMP_SR_TAMP3F      = 0x4      // Bit TAMP3F.
	TAMP_SR_ITAMP3F_Pos = 0x12     // Position of ITAMP3F field.
	TAMP_SR_ITAMP3F_Msk = 0x40000  // Bit mask of ITAMP3F field.
	TAMP_SR_ITAMP3F     = 0x40000  // Bit ITAMP3F.
	TAMP_SR_ITAMP4F_Pos = 0x13     // Position of ITAMP4F field.
	TAMP_SR_ITAMP4F_Msk = 0x80000  // Bit mask of ITAMP4F field.
	TAMP_SR_ITAMP4F     = 0x80000  // Bit ITAMP4F.
	TAMP_SR_ITAMP5F_Pos = 0x14     // Position of ITAMP5F field.
	TAMP_SR_ITAMP5F_Msk = 0x100000 // Bit mask of ITAMP5F field.
	TAMP_SR_ITAMP5F     = 0x100000 // Bit ITAMP5F.
	TAMP_SR_ITAMP6F_Pos = 0x15     // Position of ITAMP6F field.
	TAMP_SR_ITAMP6F_Msk = 0x200000 // Bit mask of ITAMP6F field.
	TAMP_SR_ITAMP6F     = 0x200000 // Bit ITAMP6F.

	// MISR: TAMP masked interrupt status           register
	TAMP_MISR_TAMP1MF_Pos  = 0x0      // Position of TAMP1MF field.
	TAMP_MISR_TAMP1MF_Msk  = 0x1      // Bit mask of TAMP1MF field.
	TAMP_MISR_TAMP1MF      = 0x1      // Bit TAMP1MF.
	TAMP_MISR_TAMP2MF_Pos  = 0x1      // Position of TAMP2MF field.
	TAMP_MISR_TAMP2MF_Msk  = 0x2      // Bit mask of TAMP2MF field.
	TAMP_MISR_TAMP2MF      = 0x2      // Bit TAMP2MF.
	TAMP_MISR_TAMP3MF_Pos  = 0x2      // Position of TAMP3MF field.
	TAMP_MISR_TAMP3MF_Msk  = 0x4      // Bit mask of TAMP3MF field.
	TAMP_MISR_TAMP3MF      = 0x4      // Bit TAMP3MF.
	TAMP_MISR_ITAMP3MF_Pos = 0x12     // Position of ITAMP3MF field.
	TAMP_MISR_ITAMP3MF_Msk = 0x40000  // Bit mask of ITAMP3MF field.
	TAMP_MISR_ITAMP3MF     = 0x40000  // Bit ITAMP3MF.
	TAMP_MISR_ITAMP4MF_Pos = 0x13     // Position of ITAMP4MF field.
	TAMP_MISR_ITAMP4MF_Msk = 0x80000  // Bit mask of ITAMP4MF field.
	TAMP_MISR_ITAMP4MF     = 0x80000  // Bit ITAMP4MF.
	TAMP_MISR_ITAMP5MF_Pos = 0x14     // Position of ITAMP5MF field.
	TAMP_MISR_ITAMP5MF_Msk = 0x100000 // Bit mask of ITAMP5MF field.
	TAMP_MISR_ITAMP5MF     = 0x100000 // Bit ITAMP5MF.
	TAMP_MISR_ITAMP6MF_Pos = 0x15     // Position of ITAMP6MF field.
	TAMP_MISR_ITAMP6MF_Msk = 0x200000 // Bit mask of ITAMP6MF field.
	TAMP_MISR_ITAMP6MF     = 0x200000 // Bit ITAMP6MF.

	// SCR: TAMP status clear register
	TAMP_SCR_CTAMP1F_Pos  = 0x0      // Position of CTAMP1F field.
	TAMP_SCR_CTAMP1F_Msk  = 0x1      // Bit mask of CTAMP1F field.
	TAMP_SCR_CTAMP1F      = 0x1      // Bit CTAMP1F.
	TAMP_SCR_CTAMP2F_Pos  = 0x1      // Position of CTAMP2F field.
	TAMP_SCR_CTAMP2F_Msk  = 0x2      // Bit mask of CTAMP2F field.
	TAMP_SCR_CTAMP2F      = 0x2      // Bit CTAMP2F.
	TAMP_SCR_CTAMP3F_Pos  = 0x2      // Position of CTAMP3F field.
	TAMP_SCR_CTAMP3F_Msk  = 0x4      // Bit mask of CTAMP3F field.
	TAMP_SCR_CTAMP3F      = 0x4      // Bit CTAMP3F.
	TAMP_SCR_CITAMP3F_Pos = 0x12     // Position of CITAMP3F field.
	TAMP_SCR_CITAMP3F_Msk = 0x40000  // Bit mask of CITAMP3F field.
	TAMP_SCR_CITAMP3F     = 0x40000  // Bit CITAMP3F.
	TAMP_SCR_CITAMP4F_Pos = 0x13     // Position of CITAMP4F field.
	TAMP_SCR_CITAMP4F_Msk = 0x80000  // Bit mask of CITAMP4F field.
	TAMP_SCR_CITAMP4F     = 0x80000  // Bit CITAMP4F.
	TAMP_SCR_CITAMP5F_Pos = 0x14     // Position of CITAMP5F field.
	TAMP_SCR_CITAMP5F_Msk = 0x100000 // Bit mask of CITAMP5F field.
	TAMP_SCR_CITAMP5F     = 0x100000 // Bit CITAMP5F.
	TAMP_SCR_CITAMP6F_Pos = 0x15     // Position of CITAMP6F field.
	TAMP_SCR_CITAMP6F_Msk = 0x200000 // Bit mask of CITAMP6F field.
	TAMP_SCR_CITAMP6F     = 0x200000 // Bit CITAMP6F.

	// BKP0R: TAMP backup register
	TAMP_BKP0R_BKP_Pos = 0x0        // Position of BKP field.
	TAMP_BKP0R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// BKP1R: TAMP backup register
	TAMP_BKP1R_BKP_Pos = 0x0        // Position of BKP field.
	TAMP_BKP1R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// BKP2R: TAMP backup register
	TAMP_BKP2R_BKP_Pos = 0x0        // Position of BKP field.
	TAMP_BKP2R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// BKP3R: TAMP backup register
	TAMP_BKP3R_BKP_Pos = 0x0        // Position of BKP field.
	TAMP_BKP3R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// BKP4R: TAMP backup register
	TAMP_BKP4R_BKP_Pos = 0x0        // Position of BKP field.
	TAMP_BKP4R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// BKP5R: TAMP backup register
	TAMP_BKP5R_BKP_Pos = 0x0        // Position of BKP field.
	TAMP_BKP5R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// BKP6R: TAMP backup register
	TAMP_BKP6R_BKP_Pos = 0x0        // Position of BKP field.
	TAMP_BKP6R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// BKP7R: TAMP backup register
	TAMP_BKP7R_BKP_Pos = 0x0        // Position of BKP field.
	TAMP_BKP7R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// BKP8R: TAMP backup register
	TAMP_BKP8R_BKP_Pos = 0x0        // Position of BKP field.
	TAMP_BKP8R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// BKP9R: TAMP backup register
	TAMP_BKP9R_BKP_Pos = 0x0        // Position of BKP field.
	TAMP_BKP9R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// BKP10R: TAMP backup register
	TAMP_BKP10R_BKP_Pos = 0x0        // Position of BKP field.
	TAMP_BKP10R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// BKP11R: TAMP backup register
	TAMP_BKP11R_BKP_Pos = 0x0        // Position of BKP field.
	TAMP_BKP11R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// BKP12R: TAMP backup register
	TAMP_BKP12R_BKP_Pos = 0x0        // Position of BKP field.
	TAMP_BKP12R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// BKP13R: TAMP backup register
	TAMP_BKP13R_BKP_Pos = 0x0        // Position of BKP field.
	TAMP_BKP13R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// BKP14R: TAMP backup register
	TAMP_BKP14R_BKP_Pos = 0x0        // Position of BKP field.
	TAMP_BKP14R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// BKP15R: TAMP backup register
	TAMP_BKP15R_BKP_Pos = 0x0        // Position of BKP field.
	TAMP_BKP15R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// BKP16R: TAMP backup register
	TAMP_BKP16R_BKP_Pos = 0x0        // Position of BKP field.
	TAMP_BKP16R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// BKP17R: TAMP backup register
	TAMP_BKP17R_BKP_Pos = 0x0        // Position of BKP field.
	TAMP_BKP17R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// BKP18R: TAMP backup register
	TAMP_BKP18R_BKP_Pos = 0x0        // Position of BKP field.
	TAMP_BKP18R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// BKP19R: TAMP backup register
	TAMP_BKP19R_BKP_Pos = 0x0        // Position of BKP field.
	TAMP_BKP19R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// BKP20R: TAMP backup register
	TAMP_BKP20R_BKP_Pos = 0x0        // Position of BKP field.
	TAMP_BKP20R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// BKP21R: TAMP backup register
	TAMP_BKP21R_BKP_Pos = 0x0        // Position of BKP field.
	TAMP_BKP21R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// BKP22R: TAMP backup register
	TAMP_BKP22R_BKP_Pos = 0x0        // Position of BKP field.
	TAMP_BKP22R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// BKP23R: TAMP backup register
	TAMP_BKP23R_BKP_Pos = 0x0        // Position of BKP field.
	TAMP_BKP23R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// BKP24R: TAMP backup register
	TAMP_BKP24R_BKP_Pos = 0x0        // Position of BKP field.
	TAMP_BKP24R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// BKP25R: TAMP backup register
	TAMP_BKP25R_BKP_Pos = 0x0        // Position of BKP field.
	TAMP_BKP25R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// BKP26R: TAMP backup register
	TAMP_BKP26R_BKP_Pos = 0x0        // Position of BKP field.
	TAMP_BKP26R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// BKP27R: TAMP backup register
	TAMP_BKP27R_BKP_Pos = 0x0        // Position of BKP field.
	TAMP_BKP27R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// BKP28R: TAMP backup register
	TAMP_BKP28R_BKP_Pos = 0x0        // Position of BKP field.
	TAMP_BKP28R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// BKP29R: TAMP backup register
	TAMP_BKP29R_BKP_Pos = 0x0        // Position of BKP field.
	TAMP_BKP29R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// BKP30R: TAMP backup register
	TAMP_BKP30R_BKP_Pos = 0x0        // Position of BKP field.
	TAMP_BKP30R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// BKP31R: TAMP backup register
	TAMP_BKP31R_BKP_Pos = 0x0        // Position of BKP field.
	TAMP_BKP31R_BKP_Msk = 0xffffffff // Bit mask of BKP field.
)

// Bitfields for FPU: Floting point unit
const (
	// FPCCR: Floating-point context control           register
	FPU_FPCCR_LSPACT_Pos = 0x0        // Position of LSPACT field.
	FPU_FPCCR_LSPACT_Msk = 0x1        // Bit mask of LSPACT field.
	FPU_FPCCR_LSPACT     = 0x1        // Bit LSPACT.
	FPU_FPCCR_USER_Pos   = 0x1        // Position of USER field.
	FPU_FPCCR_USER_Msk   = 0x2        // Bit mask of USER field.
	FPU_FPCCR_USER       = 0x2        // Bit USER.
	FPU_FPCCR_THREAD_Pos = 0x3        // Position of THREAD field.
	FPU_FPCCR_THREAD_Msk = 0x8        // Bit mask of THREAD field.
	FPU_FPCCR_THREAD     = 0x8        // Bit THREAD.
	FPU_FPCCR_HFRDY_Pos  = 0x4        // Position of HFRDY field.
	FPU_FPCCR_HFRDY_Msk  = 0x10       // Bit mask of HFRDY field.
	FPU_FPCCR_HFRDY      = 0x10       // Bit HFRDY.
	FPU_FPCCR_MMRDY_Pos  = 0x5        // Position of MMRDY field.
	FPU_FPCCR_MMRDY_Msk  = 0x20       // Bit mask of MMRDY field.
	FPU_FPCCR_MMRDY      = 0x20       // Bit MMRDY.
	FPU_FPCCR_BFRDY_Pos  = 0x6        // Position of BFRDY field.
	FPU_FPCCR_BFRDY_Msk  = 0x40       // Bit mask of BFRDY field.
	FPU_FPCCR_BFRDY      = 0x40       // Bit BFRDY.
	FPU_FPCCR_MONRDY_Pos = 0x8        // Position of MONRDY field.
	FPU_FPCCR_MONRDY_Msk = 0x100      // Bit mask of MONRDY field.
	FPU_FPCCR_MONRDY     = 0x100      // Bit MONRDY.
	FPU_FPCCR_LSPEN_Pos  = 0x1e       // Position of LSPEN field.
	FPU_FPCCR_LSPEN_Msk  = 0x40000000 // Bit mask of LSPEN field.
	FPU_FPCCR_LSPEN      = 0x40000000 // Bit LSPEN.
	FPU_FPCCR_ASPEN_Pos  = 0x1f       // Position of ASPEN field.
	FPU_FPCCR_ASPEN_Msk  = 0x80000000 // Bit mask of ASPEN field.
	FPU_FPCCR_ASPEN      = 0x80000000 // Bit ASPEN.

	// FPCAR: Floating-point context address           register
	FPU_FPCAR_ADDRESS_Pos = 0x3        // Position of ADDRESS field.
	FPU_FPCAR_ADDRESS_Msk = 0xfffffff8 // Bit mask of ADDRESS field.

	// FPSCR: Floating-point status control           register
	FPU_FPSCR_IOC_Pos   = 0x0        // Position of IOC field.
	FPU_FPSCR_IOC_Msk   = 0x1        // Bit mask of IOC field.
	FPU_FPSCR_IOC       = 0x1        // Bit IOC.
	FPU_FPSCR_DZC_Pos   = 0x1        // Position of DZC field.
	FPU_FPSCR_DZC_Msk   = 0x2        // Bit mask of DZC field.
	FPU_FPSCR_DZC       = 0x2        // Bit DZC.
	FPU_FPSCR_OFC_Pos   = 0x2        // Position of OFC field.
	FPU_FPSCR_OFC_Msk   = 0x4        // Bit mask of OFC field.
	FPU_FPSCR_OFC       = 0x4        // Bit OFC.
	FPU_FPSCR_UFC_Pos   = 0x3        // Position of UFC field.
	FPU_FPSCR_UFC_Msk   = 0x8        // Bit mask of UFC field.
	FPU_FPSCR_UFC       = 0x8        // Bit UFC.
	FPU_FPSCR_IXC_Pos   = 0x4        // Position of IXC field.
	FPU_FPSCR_IXC_Msk   = 0x10       // Bit mask of IXC field.
	FPU_FPSCR_IXC       = 0x10       // Bit IXC.
	FPU_FPSCR_IDC_Pos   = 0x7        // Position of IDC field.
	FPU_FPSCR_IDC_Msk   = 0x80       // Bit mask of IDC field.
	FPU_FPSCR_IDC       = 0x80       // Bit IDC.
	FPU_FPSCR_RMode_Pos = 0x16       // Position of RMode field.
	FPU_FPSCR_RMode_Msk = 0xc00000   // Bit mask of RMode field.
	FPU_FPSCR_FZ_Pos    = 0x18       // Position of FZ field.
	FPU_FPSCR_FZ_Msk    = 0x1000000  // Bit mask of FZ field.
	FPU_FPSCR_FZ        = 0x1000000  // Bit FZ.
	FPU_FPSCR_DN_Pos    = 0x19       // Position of DN field.
	FPU_FPSCR_DN_Msk    = 0x2000000  // Bit mask of DN field.
	FPU_FPSCR_DN        = 0x2000000  // Bit DN.
	FPU_FPSCR_AHP_Pos   = 0x1a       // Position of AHP field.
	FPU_FPSCR_AHP_Msk   = 0x4000000  // Bit mask of AHP field.
	FPU_FPSCR_AHP       = 0x4000000  // Bit AHP.
	FPU_FPSCR_V_Pos     = 0x1c       // Position of V field.
	FPU_FPSCR_V_Msk     = 0x10000000 // Bit mask of V field.
	FPU_FPSCR_V         = 0x10000000 // Bit V.
	FPU_FPSCR_C_Pos     = 0x1d       // Position of C field.
	FPU_FPSCR_C_Msk     = 0x20000000 // Bit mask of C field.
	FPU_FPSCR_C         = 0x20000000 // Bit C.
	FPU_FPSCR_Z_Pos     = 0x1e       // Position of Z field.
	FPU_FPSCR_Z_Msk     = 0x40000000 // Bit mask of Z field.
	FPU_FPSCR_Z         = 0x40000000 // Bit Z.
	FPU_FPSCR_N_Pos     = 0x1f       // Position of N field.
	FPU_FPSCR_N_Msk     = 0x80000000 // Bit mask of N field.
	FPU_FPSCR_N         = 0x80000000 // Bit N.
)

// Bitfields for MPU: Memory protection unit
const (
	// TYPER: MPU type register
	MPU_TYPER_SEPARATE_Pos = 0x0      // Position of SEPARATE field.
	MPU_TYPER_SEPARATE_Msk = 0x1      // Bit mask of SEPARATE field.
	MPU_TYPER_SEPARATE     = 0x1      // Bit SEPARATE.
	MPU_TYPER_DREGION_Pos  = 0x8      // Position of DREGION field.
	MPU_TYPER_DREGION_Msk  = 0xff00   // Bit mask of DREGION field.
	MPU_TYPER_IREGION_Pos  = 0x10     // Position of IREGION field.
	MPU_TYPER_IREGION_Msk  = 0xff0000 // Bit mask of IREGION field.

	// CTRL: MPU control register
	MPU_CTRL_ENABLE_Pos     = 0x0 // Position of ENABLE field.
	MPU_CTRL_ENABLE_Msk     = 0x1 // Bit mask of ENABLE field.
	MPU_CTRL_ENABLE         = 0x1 // Bit ENABLE.
	MPU_CTRL_HFNMIENA_Pos   = 0x1 // Position of HFNMIENA field.
	MPU_CTRL_HFNMIENA_Msk   = 0x2 // Bit mask of HFNMIENA field.
	MPU_CTRL_HFNMIENA       = 0x2 // Bit HFNMIENA.
	MPU_CTRL_PRIVDEFENA_Pos = 0x2 // Position of PRIVDEFENA field.
	MPU_CTRL_PRIVDEFENA_Msk = 0x4 // Bit mask of PRIVDEFENA field.
	MPU_CTRL_PRIVDEFENA     = 0x4 // Bit PRIVDEFENA.

	// RNR: MPU region number register
	MPU_RNR_REGION_Pos = 0x0  // Position of REGION field.
	MPU_RNR_REGION_Msk = 0xff // Bit mask of REGION field.

	// RBAR: MPU region base address           register
	MPU_RBAR_REGION_Pos = 0x0        // Position of REGION field.
	MPU_RBAR_REGION_Msk = 0xf        // Bit mask of REGION field.
	MPU_RBAR_VALID_Pos  = 0x4        // Position of VALID field.
	MPU_RBAR_VALID_Msk  = 0x10       // Bit mask of VALID field.
	MPU_RBAR_VALID      = 0x10       // Bit VALID.
	MPU_RBAR_ADDR_Pos   = 0x5        // Position of ADDR field.
	MPU_RBAR_ADDR_Msk   = 0xffffffe0 // Bit mask of ADDR field.

	// RASR: MPU region attribute and size           register
	MPU_RASR_ENABLE_Pos = 0x0        // Position of ENABLE field.
	MPU_RASR_ENABLE_Msk = 0x1        // Bit mask of ENABLE field.
	MPU_RASR_ENABLE     = 0x1        // Bit ENABLE.
	MPU_RASR_SIZE_Pos   = 0x1        // Position of SIZE field.
	MPU_RASR_SIZE_Msk   = 0x3e       // Bit mask of SIZE field.
	MPU_RASR_SRD_Pos    = 0x8        // Position of SRD field.
	MPU_RASR_SRD_Msk    = 0xff00     // Bit mask of SRD field.
	MPU_RASR_B_Pos      = 0x10       // Position of B field.
	MPU_RASR_B_Msk      = 0x10000    // Bit mask of B field.
	MPU_RASR_B          = 0x10000    // Bit B.
	MPU_RASR_C_Pos      = 0x11       // Position of C field.
	MPU_RASR_C_Msk      = 0x20000    // Bit mask of C field.
	MPU_RASR_C          = 0x20000    // Bit C.
	MPU_RASR_S_Pos      = 0x12       // Position of S field.
	MPU_RASR_S_Msk      = 0x40000    // Bit mask of S field.
	MPU_RASR_S          = 0x40000    // Bit S.
	MPU_RASR_TEX_Pos    = 0x13       // Position of TEX field.
	MPU_RASR_TEX_Msk    = 0x380000   // Bit mask of TEX field.
	MPU_RASR_AP_Pos     = 0x18       // Position of AP field.
	MPU_RASR_AP_Msk     = 0x7000000  // Bit mask of AP field.
	MPU_RASR_XN_Pos     = 0x1c       // Position of XN field.
	MPU_RASR_XN_Msk     = 0x10000000 // Bit mask of XN field.
	MPU_RASR_XN         = 0x10000000 // Bit XN.
)

// Bitfields for STK: SysTick timer
const (
	// CTRL: SysTick control and status           register
	STK_CTRL_ENABLE_Pos    = 0x0     // Position of ENABLE field.
	STK_CTRL_ENABLE_Msk    = 0x1     // Bit mask of ENABLE field.
	STK_CTRL_ENABLE        = 0x1     // Bit ENABLE.
	STK_CTRL_TICKINT_Pos   = 0x1     // Position of TICKINT field.
	STK_CTRL_TICKINT_Msk   = 0x2     // Bit mask of TICKINT field.
	STK_CTRL_TICKINT       = 0x2     // Bit TICKINT.
	STK_CTRL_CLKSOURCE_Pos = 0x2     // Position of CLKSOURCE field.
	STK_CTRL_CLKSOURCE_Msk = 0x4     // Bit mask of CLKSOURCE field.
	STK_CTRL_CLKSOURCE     = 0x4     // Bit CLKSOURCE.
	STK_CTRL_COUNTFLAG_Pos = 0x10    // Position of COUNTFLAG field.
	STK_CTRL_COUNTFLAG_Msk = 0x10000 // Bit mask of COUNTFLAG field.
	STK_CTRL_COUNTFLAG     = 0x10000 // Bit COUNTFLAG.

	// LOAD: SysTick reload value register
	STK_LOAD_RELOAD_Pos = 0x0      // Position of RELOAD field.
	STK_LOAD_RELOAD_Msk = 0xffffff // Bit mask of RELOAD field.

	// VAL: SysTick current value register
	STK_VAL_CURRENT_Pos = 0x0      // Position of CURRENT field.
	STK_VAL_CURRENT_Msk = 0xffffff // Bit mask of CURRENT field.

	// CALIB: SysTick calibration value           register
	STK_CALIB_TENMS_Pos = 0x0        // Position of TENMS field.
	STK_CALIB_TENMS_Msk = 0xffffff   // Bit mask of TENMS field.
	STK_CALIB_SKEW_Pos  = 0x1e       // Position of SKEW field.
	STK_CALIB_SKEW_Msk  = 0x40000000 // Bit mask of SKEW field.
	STK_CALIB_SKEW      = 0x40000000 // Bit SKEW.
	STK_CALIB_NOREF_Pos = 0x1f       // Position of NOREF field.
	STK_CALIB_NOREF_Msk = 0x80000000 // Bit mask of NOREF field.
	STK_CALIB_NOREF     = 0x80000000 // Bit NOREF.
)

// Bitfields for SCB: System control block
const (
	// CPUID: CPUID base register
	SCB_CPUID_Revision_Pos    = 0x0        // Position of Revision field.
	SCB_CPUID_Revision_Msk    = 0xf        // Bit mask of Revision field.
	SCB_CPUID_PartNo_Pos      = 0x4        // Position of PartNo field.
	SCB_CPUID_PartNo_Msk      = 0xfff0     // Bit mask of PartNo field.
	SCB_CPUID_Constant_Pos    = 0x10       // Position of Constant field.
	SCB_CPUID_Constant_Msk    = 0xf0000    // Bit mask of Constant field.
	SCB_CPUID_Variant_Pos     = 0x14       // Position of Variant field.
	SCB_CPUID_Variant_Msk     = 0xf00000   // Bit mask of Variant field.
	SCB_CPUID_Implementer_Pos = 0x18       // Position of Implementer field.
	SCB_CPUID_Implementer_Msk = 0xff000000 // Bit mask of Implementer field.

	// ICSR: Interrupt control and state           register
	SCB_ICSR_VECTACTIVE_Pos  = 0x0        // Position of VECTACTIVE field.
	SCB_ICSR_VECTACTIVE_Msk  = 0x1ff      // Bit mask of VECTACTIVE field.
	SCB_ICSR_RETTOBASE_Pos   = 0xb        // Position of RETTOBASE field.
	SCB_ICSR_RETTOBASE_Msk   = 0x800      // Bit mask of RETTOBASE field.
	SCB_ICSR_RETTOBASE       = 0x800      // Bit RETTOBASE.
	SCB_ICSR_VECTPENDING_Pos = 0xc        // Position of VECTPENDING field.
	SCB_ICSR_VECTPENDING_Msk = 0x7f000    // Bit mask of VECTPENDING field.
	SCB_ICSR_ISRPENDING_Pos  = 0x16       // Position of ISRPENDING field.
	SCB_ICSR_ISRPENDING_Msk  = 0x400000   // Bit mask of ISRPENDING field.
	SCB_ICSR_ISRPENDING      = 0x400000   // Bit ISRPENDING.
	SCB_ICSR_PENDSTCLR_Pos   = 0x19       // Position of PENDSTCLR field.
	SCB_ICSR_PENDSTCLR_Msk   = 0x2000000  // Bit mask of PENDSTCLR field.
	SCB_ICSR_PENDSTCLR       = 0x2000000  // Bit PENDSTCLR.
	SCB_ICSR_PENDSTSET_Pos   = 0x1a       // Position of PENDSTSET field.
	SCB_ICSR_PENDSTSET_Msk   = 0x4000000  // Bit mask of PENDSTSET field.
	SCB_ICSR_PENDSTSET       = 0x4000000  // Bit PENDSTSET.
	SCB_ICSR_PENDSVCLR_Pos   = 0x1b       // Position of PENDSVCLR field.
	SCB_ICSR_PENDSVCLR_Msk   = 0x8000000  // Bit mask of PENDSVCLR field.
	SCB_ICSR_PENDSVCLR       = 0x8000000  // Bit PENDSVCLR.
	SCB_ICSR_PENDSVSET_Pos   = 0x1c       // Position of PENDSVSET field.
	SCB_ICSR_PENDSVSET_Msk   = 0x10000000 // Bit mask of PENDSVSET field.
	SCB_ICSR_PENDSVSET       = 0x10000000 // Bit PENDSVSET.
	SCB_ICSR_NMIPENDSET_Pos  = 0x1f       // Position of NMIPENDSET field.
	SCB_ICSR_NMIPENDSET_Msk  = 0x80000000 // Bit mask of NMIPENDSET field.
	SCB_ICSR_NMIPENDSET      = 0x80000000 // Bit NMIPENDSET.

	// VTOR: Vector table offset register
	SCB_VTOR_TBLOFF_Pos = 0x9        // Position of TBLOFF field.
	SCB_VTOR_TBLOFF_Msk = 0x3ffffe00 // Bit mask of TBLOFF field.

	// AIRCR: Application interrupt and reset control           register
	SCB_AIRCR_VECTRESET_Pos     = 0x0        // Position of VECTRESET field.
	SCB_AIRCR_VECTRESET_Msk     = 0x1        // Bit mask of VECTRESET field.
	SCB_AIRCR_VECTRESET         = 0x1        // Bit VECTRESET.
	SCB_AIRCR_VECTCLRACTIVE_Pos = 0x1        // Position of VECTCLRACTIVE field.
	SCB_AIRCR_VECTCLRACTIVE_Msk = 0x2        // Bit mask of VECTCLRACTIVE field.
	SCB_AIRCR_VECTCLRACTIVE     = 0x2        // Bit VECTCLRACTIVE.
	SCB_AIRCR_SYSRESETREQ_Pos   = 0x2        // Position of SYSRESETREQ field.
	SCB_AIRCR_SYSRESETREQ_Msk   = 0x4        // Bit mask of SYSRESETREQ field.
	SCB_AIRCR_SYSRESETREQ       = 0x4        // Bit SYSRESETREQ.
	SCB_AIRCR_PRIGROUP_Pos      = 0x8        // Position of PRIGROUP field.
	SCB_AIRCR_PRIGROUP_Msk      = 0x700      // Bit mask of PRIGROUP field.
	SCB_AIRCR_ENDIANESS_Pos     = 0xf        // Position of ENDIANESS field.
	SCB_AIRCR_ENDIANESS_Msk     = 0x8000     // Bit mask of ENDIANESS field.
	SCB_AIRCR_ENDIANESS         = 0x8000     // Bit ENDIANESS.
	SCB_AIRCR_VECTKEYSTAT_Pos   = 0x10       // Position of VECTKEYSTAT field.
	SCB_AIRCR_VECTKEYSTAT_Msk   = 0xffff0000 // Bit mask of VECTKEYSTAT field.

	// SCR: System control register
	SCB_SCR_SLEEPONEXIT_Pos = 0x1  // Position of SLEEPONEXIT field.
	SCB_SCR_SLEEPONEXIT_Msk = 0x2  // Bit mask of SLEEPONEXIT field.
	SCB_SCR_SLEEPONEXIT     = 0x2  // Bit SLEEPONEXIT.
	SCB_SCR_SLEEPDEEP_Pos   = 0x2  // Position of SLEEPDEEP field.
	SCB_SCR_SLEEPDEEP_Msk   = 0x4  // Bit mask of SLEEPDEEP field.
	SCB_SCR_SLEEPDEEP       = 0x4  // Bit SLEEPDEEP.
	SCB_SCR_SEVEONPEND_Pos  = 0x4  // Position of SEVEONPEND field.
	SCB_SCR_SEVEONPEND_Msk  = 0x10 // Bit mask of SEVEONPEND field.
	SCB_SCR_SEVEONPEND      = 0x10 // Bit SEVEONPEND.

	// CCR: Configuration and control           register
	SCB_CCR_NONBASETHRDENA_Pos = 0x0   // Position of NONBASETHRDENA field.
	SCB_CCR_NONBASETHRDENA_Msk = 0x1   // Bit mask of NONBASETHRDENA field.
	SCB_CCR_NONBASETHRDENA     = 0x1   // Bit NONBASETHRDENA.
	SCB_CCR_USERSETMPEND_Pos   = 0x1   // Position of USERSETMPEND field.
	SCB_CCR_USERSETMPEND_Msk   = 0x2   // Bit mask of USERSETMPEND field.
	SCB_CCR_USERSETMPEND       = 0x2   // Bit USERSETMPEND.
	SCB_CCR_UNALIGN__TRP_Pos   = 0x3   // Position of UNALIGN__TRP field.
	SCB_CCR_UNALIGN__TRP_Msk   = 0x8   // Bit mask of UNALIGN__TRP field.
	SCB_CCR_UNALIGN__TRP       = 0x8   // Bit UNALIGN__TRP.
	SCB_CCR_DIV_0_TRP_Pos      = 0x4   // Position of DIV_0_TRP field.
	SCB_CCR_DIV_0_TRP_Msk      = 0x10  // Bit mask of DIV_0_TRP field.
	SCB_CCR_DIV_0_TRP          = 0x10  // Bit DIV_0_TRP.
	SCB_CCR_BFHFNMIGN_Pos      = 0x8   // Position of BFHFNMIGN field.
	SCB_CCR_BFHFNMIGN_Msk      = 0x100 // Bit mask of BFHFNMIGN field.
	SCB_CCR_BFHFNMIGN          = 0x100 // Bit BFHFNMIGN.
	SCB_CCR_STKALIGN_Pos       = 0x9   // Position of STKALIGN field.
	SCB_CCR_STKALIGN_Msk       = 0x200 // Bit mask of STKALIGN field.
	SCB_CCR_STKALIGN           = 0x200 // Bit STKALIGN.

	// SHPR1: System handler priority           registers
	SCB_SHPR1_PRI_4_Pos = 0x0      // Position of PRI_4 field.
	SCB_SHPR1_PRI_4_Msk = 0xff     // Bit mask of PRI_4 field.
	SCB_SHPR1_PRI_5_Pos = 0x8      // Position of PRI_5 field.
	SCB_SHPR1_PRI_5_Msk = 0xff00   // Bit mask of PRI_5 field.
	SCB_SHPR1_PRI_6_Pos = 0x10     // Position of PRI_6 field.
	SCB_SHPR1_PRI_6_Msk = 0xff0000 // Bit mask of PRI_6 field.

	// SHPR2: System handler priority           registers
	SCB_SHPR2_PRI_11_Pos = 0x18       // Position of PRI_11 field.
	SCB_SHPR2_PRI_11_Msk = 0xff000000 // Bit mask of PRI_11 field.

	// SHPR3: System handler priority           registers
	SCB_SHPR3_PRI_14_Pos = 0x10       // Position of PRI_14 field.
	SCB_SHPR3_PRI_14_Msk = 0xff0000   // Bit mask of PRI_14 field.
	SCB_SHPR3_PRI_15_Pos = 0x18       // Position of PRI_15 field.
	SCB_SHPR3_PRI_15_Msk = 0xff000000 // Bit mask of PRI_15 field.

	// SHCRS: System handler control and state           register
	SCB_SHCRS_MEMFAULTACT_Pos    = 0x0     // Position of MEMFAULTACT field.
	SCB_SHCRS_MEMFAULTACT_Msk    = 0x1     // Bit mask of MEMFAULTACT field.
	SCB_SHCRS_MEMFAULTACT        = 0x1     // Bit MEMFAULTACT.
	SCB_SHCRS_BUSFAULTACT_Pos    = 0x1     // Position of BUSFAULTACT field.
	SCB_SHCRS_BUSFAULTACT_Msk    = 0x2     // Bit mask of BUSFAULTACT field.
	SCB_SHCRS_BUSFAULTACT        = 0x2     // Bit BUSFAULTACT.
	SCB_SHCRS_USGFAULTACT_Pos    = 0x3     // Position of USGFAULTACT field.
	SCB_SHCRS_USGFAULTACT_Msk    = 0x8     // Bit mask of USGFAULTACT field.
	SCB_SHCRS_USGFAULTACT        = 0x8     // Bit USGFAULTACT.
	SCB_SHCRS_SVCALLACT_Pos      = 0x7     // Position of SVCALLACT field.
	SCB_SHCRS_SVCALLACT_Msk      = 0x80    // Bit mask of SVCALLACT field.
	SCB_SHCRS_SVCALLACT          = 0x80    // Bit SVCALLACT.
	SCB_SHCRS_MONITORACT_Pos     = 0x8     // Position of MONITORACT field.
	SCB_SHCRS_MONITORACT_Msk     = 0x100   // Bit mask of MONITORACT field.
	SCB_SHCRS_MONITORACT         = 0x100   // Bit MONITORACT.
	SCB_SHCRS_PENDSVACT_Pos      = 0xa     // Position of PENDSVACT field.
	SCB_SHCRS_PENDSVACT_Msk      = 0x400   // Bit mask of PENDSVACT field.
	SCB_SHCRS_PENDSVACT          = 0x400   // Bit PENDSVACT.
	SCB_SHCRS_SYSTICKACT_Pos     = 0xb     // Position of SYSTICKACT field.
	SCB_SHCRS_SYSTICKACT_Msk     = 0x800   // Bit mask of SYSTICKACT field.
	SCB_SHCRS_SYSTICKACT         = 0x800   // Bit SYSTICKACT.
	SCB_SHCRS_USGFAULTPENDED_Pos = 0xc     // Position of USGFAULTPENDED field.
	SCB_SHCRS_USGFAULTPENDED_Msk = 0x1000  // Bit mask of USGFAULTPENDED field.
	SCB_SHCRS_USGFAULTPENDED     = 0x1000  // Bit USGFAULTPENDED.
	SCB_SHCRS_MEMFAULTPENDED_Pos = 0xd     // Position of MEMFAULTPENDED field.
	SCB_SHCRS_MEMFAULTPENDED_Msk = 0x2000  // Bit mask of MEMFAULTPENDED field.
	SCB_SHCRS_MEMFAULTPENDED     = 0x2000  // Bit MEMFAULTPENDED.
	SCB_SHCRS_BUSFAULTPENDED_Pos = 0xe     // Position of BUSFAULTPENDED field.
	SCB_SHCRS_BUSFAULTPENDED_Msk = 0x4000  // Bit mask of BUSFAULTPENDED field.
	SCB_SHCRS_BUSFAULTPENDED     = 0x4000  // Bit BUSFAULTPENDED.
	SCB_SHCRS_SVCALLPENDED_Pos   = 0xf     // Position of SVCALLPENDED field.
	SCB_SHCRS_SVCALLPENDED_Msk   = 0x8000  // Bit mask of SVCALLPENDED field.
	SCB_SHCRS_SVCALLPENDED       = 0x8000  // Bit SVCALLPENDED.
	SCB_SHCRS_MEMFAULTENA_Pos    = 0x10    // Position of MEMFAULTENA field.
	SCB_SHCRS_MEMFAULTENA_Msk    = 0x10000 // Bit mask of MEMFAULTENA field.
	SCB_SHCRS_MEMFAULTENA        = 0x10000 // Bit MEMFAULTENA.
	SCB_SHCRS_BUSFAULTENA_Pos    = 0x11    // Position of BUSFAULTENA field.
	SCB_SHCRS_BUSFAULTENA_Msk    = 0x20000 // Bit mask of BUSFAULTENA field.
	SCB_SHCRS_BUSFAULTENA        = 0x20000 // Bit BUSFAULTENA.
	SCB_SHCRS_USGFAULTENA_Pos    = 0x12    // Position of USGFAULTENA field.
	SCB_SHCRS_USGFAULTENA_Msk    = 0x40000 // Bit mask of USGFAULTENA field.
	SCB_SHCRS_USGFAULTENA        = 0x40000 // Bit USGFAULTENA.

	// CFSR_UFSR_BFSR_MMFSR: Configurable fault status           register
	SCB_CFSR_UFSR_BFSR_MMFSR_IACCVIOL_Pos    = 0x1       // Position of IACCVIOL field.
	SCB_CFSR_UFSR_BFSR_MMFSR_IACCVIOL_Msk    = 0x2       // Bit mask of IACCVIOL field.
	SCB_CFSR_UFSR_BFSR_MMFSR_IACCVIOL        = 0x2       // Bit IACCVIOL.
	SCB_CFSR_UFSR_BFSR_MMFSR_MUNSTKERR_Pos   = 0x3       // Position of MUNSTKERR field.
	SCB_CFSR_UFSR_BFSR_MMFSR_MUNSTKERR_Msk   = 0x8       // Bit mask of MUNSTKERR field.
	SCB_CFSR_UFSR_BFSR_MMFSR_MUNSTKERR       = 0x8       // Bit MUNSTKERR.
	SCB_CFSR_UFSR_BFSR_MMFSR_MSTKERR_Pos     = 0x4       // Position of MSTKERR field.
	SCB_CFSR_UFSR_BFSR_MMFSR_MSTKERR_Msk     = 0x10      // Bit mask of MSTKERR field.
	SCB_CFSR_UFSR_BFSR_MMFSR_MSTKERR         = 0x10      // Bit MSTKERR.
	SCB_CFSR_UFSR_BFSR_MMFSR_MLSPERR_Pos     = 0x5       // Position of MLSPERR field.
	SCB_CFSR_UFSR_BFSR_MMFSR_MLSPERR_Msk     = 0x20      // Bit mask of MLSPERR field.
	SCB_CFSR_UFSR_BFSR_MMFSR_MLSPERR         = 0x20      // Bit MLSPERR.
	SCB_CFSR_UFSR_BFSR_MMFSR_MMARVALID_Pos   = 0x7       // Position of MMARVALID field.
	SCB_CFSR_UFSR_BFSR_MMFSR_MMARVALID_Msk   = 0x80      // Bit mask of MMARVALID field.
	SCB_CFSR_UFSR_BFSR_MMFSR_MMARVALID       = 0x80      // Bit MMARVALID.
	SCB_CFSR_UFSR_BFSR_MMFSR_IBUSERR_Pos     = 0x8       // Position of IBUSERR field.
	SCB_CFSR_UFSR_BFSR_MMFSR_IBUSERR_Msk     = 0x100     // Bit mask of IBUSERR field.
	SCB_CFSR_UFSR_BFSR_MMFSR_IBUSERR         = 0x100     // Bit IBUSERR.
	SCB_CFSR_UFSR_BFSR_MMFSR_PRECISERR_Pos   = 0x9       // Position of PRECISERR field.
	SCB_CFSR_UFSR_BFSR_MMFSR_PRECISERR_Msk   = 0x200     // Bit mask of PRECISERR field.
	SCB_CFSR_UFSR_BFSR_MMFSR_PRECISERR       = 0x200     // Bit PRECISERR.
	SCB_CFSR_UFSR_BFSR_MMFSR_IMPRECISERR_Pos = 0xa       // Position of IMPRECISERR field.
	SCB_CFSR_UFSR_BFSR_MMFSR_IMPRECISERR_Msk = 0x400     // Bit mask of IMPRECISERR field.
	SCB_CFSR_UFSR_BFSR_MMFSR_IMPRECISERR     = 0x400     // Bit IMPRECISERR.
	SCB_CFSR_UFSR_BFSR_MMFSR_UNSTKERR_Pos    = 0xb       // Position of UNSTKERR field.
	SCB_CFSR_UFSR_BFSR_MMFSR_UNSTKERR_Msk    = 0x800     // Bit mask of UNSTKERR field.
	SCB_CFSR_UFSR_BFSR_MMFSR_UNSTKERR        = 0x800     // Bit UNSTKERR.
	SCB_CFSR_UFSR_BFSR_MMFSR_STKERR_Pos      = 0xc       // Position of STKERR field.
	SCB_CFSR_UFSR_BFSR_MMFSR_STKERR_Msk      = 0x1000    // Bit mask of STKERR field.
	SCB_CFSR_UFSR_BFSR_MMFSR_STKERR          = 0x1000    // Bit STKERR.
	SCB_CFSR_UFSR_BFSR_MMFSR_LSPERR_Pos      = 0xd       // Position of LSPERR field.
	SCB_CFSR_UFSR_BFSR_MMFSR_LSPERR_Msk      = 0x2000    // Bit mask of LSPERR field.
	SCB_CFSR_UFSR_BFSR_MMFSR_LSPERR          = 0x2000    // Bit LSPERR.
	SCB_CFSR_UFSR_BFSR_MMFSR_BFARVALID_Pos   = 0xf       // Position of BFARVALID field.
	SCB_CFSR_UFSR_BFSR_MMFSR_BFARVALID_Msk   = 0x8000    // Bit mask of BFARVALID field.
	SCB_CFSR_UFSR_BFSR_MMFSR_BFARVALID       = 0x8000    // Bit BFARVALID.
	SCB_CFSR_UFSR_BFSR_MMFSR_UNDEFINSTR_Pos  = 0x10      // Position of UNDEFINSTR field.
	SCB_CFSR_UFSR_BFSR_MMFSR_UNDEFINSTR_Msk  = 0x10000   // Bit mask of UNDEFINSTR field.
	SCB_CFSR_UFSR_BFSR_MMFSR_UNDEFINSTR      = 0x10000   // Bit UNDEFINSTR.
	SCB_CFSR_UFSR_BFSR_MMFSR_INVSTATE_Pos    = 0x11      // Position of INVSTATE field.
	SCB_CFSR_UFSR_BFSR_MMFSR_INVSTATE_Msk    = 0x20000   // Bit mask of INVSTATE field.
	SCB_CFSR_UFSR_BFSR_MMFSR_INVSTATE        = 0x20000   // Bit INVSTATE.
	SCB_CFSR_UFSR_BFSR_MMFSR_INVPC_Pos       = 0x12      // Position of INVPC field.
	SCB_CFSR_UFSR_BFSR_MMFSR_INVPC_Msk       = 0x40000   // Bit mask of INVPC field.
	SCB_CFSR_UFSR_BFSR_MMFSR_INVPC           = 0x40000   // Bit INVPC.
	SCB_CFSR_UFSR_BFSR_MMFSR_NOCP_Pos        = 0x13      // Position of NOCP field.
	SCB_CFSR_UFSR_BFSR_MMFSR_NOCP_Msk        = 0x80000   // Bit mask of NOCP field.
	SCB_CFSR_UFSR_BFSR_MMFSR_NOCP            = 0x80000   // Bit NOCP.
	SCB_CFSR_UFSR_BFSR_MMFSR_UNALIGNED_Pos   = 0x18      // Position of UNALIGNED field.
	SCB_CFSR_UFSR_BFSR_MMFSR_UNALIGNED_Msk   = 0x1000000 // Bit mask of UNALIGNED field.
	SCB_CFSR_UFSR_BFSR_MMFSR_UNALIGNED       = 0x1000000 // Bit UNALIGNED.
	SCB_CFSR_UFSR_BFSR_MMFSR_DIVBYZERO_Pos   = 0x19      // Position of DIVBYZERO field.
	SCB_CFSR_UFSR_BFSR_MMFSR_DIVBYZERO_Msk   = 0x2000000 // Bit mask of DIVBYZERO field.
	SCB_CFSR_UFSR_BFSR_MMFSR_DIVBYZERO       = 0x2000000 // Bit DIVBYZERO.

	// HFSR: Hard fault status register
	SCB_HFSR_VECTTBL_Pos  = 0x1        // Position of VECTTBL field.
	SCB_HFSR_VECTTBL_Msk  = 0x2        // Bit mask of VECTTBL field.
	SCB_HFSR_VECTTBL      = 0x2        // Bit VECTTBL.
	SCB_HFSR_FORCED_Pos   = 0x1e       // Position of FORCED field.
	SCB_HFSR_FORCED_Msk   = 0x40000000 // Bit mask of FORCED field.
	SCB_HFSR_FORCED       = 0x40000000 // Bit FORCED.
	SCB_HFSR_DEBUG_VT_Pos = 0x1f       // Position of DEBUG_VT field.
	SCB_HFSR_DEBUG_VT_Msk = 0x80000000 // Bit mask of DEBUG_VT field.
	SCB_HFSR_DEBUG_VT     = 0x80000000 // Bit DEBUG_VT.

	// MMFAR: Memory management fault address           register
	SCB_MMFAR_MMFAR_Pos = 0x0        // Position of MMFAR field.
	SCB_MMFAR_MMFAR_Msk = 0xffffffff // Bit mask of MMFAR field.

	// BFAR: Bus fault address register
	SCB_BFAR_BFAR_Pos = 0x0        // Position of BFAR field.
	SCB_BFAR_BFAR_Msk = 0xffffffff // Bit mask of BFAR field.

	// AFSR: Auxiliary fault status           register
	SCB_AFSR_IMPDEF_Pos = 0x0        // Position of IMPDEF field.
	SCB_AFSR_IMPDEF_Msk = 0xffffffff // Bit mask of IMPDEF field.
)

// Bitfields for NVIC: Nested Vectored Interrupt Controller
const (
	// ISER0: Interrupt Set-Enable Register
	NVIC_ISER0_SETENA_Pos = 0x0        // Position of SETENA field.
	NVIC_ISER0_SETENA_Msk = 0xffffffff // Bit mask of SETENA field.

	// ISER1: Interrupt Set-Enable Register
	NVIC_ISER1_SETENA_Pos = 0x0        // Position of SETENA field.
	NVIC_ISER1_SETENA_Msk = 0xffffffff // Bit mask of SETENA field.

	// ISER2: Interrupt Set-Enable Register
	NVIC_ISER2_SETENA_Pos = 0x0        // Position of SETENA field.
	NVIC_ISER2_SETENA_Msk = 0xffffffff // Bit mask of SETENA field.

	// ISER3: Interrupt Set-Enable Register
	NVIC_ISER3_SETENA_Pos = 0x0        // Position of SETENA field.
	NVIC_ISER3_SETENA_Msk = 0xffffffff // Bit mask of SETENA field.

	// ICER0: Interrupt Clear-Enable           Register
	NVIC_ICER0_CLRENA_Pos = 0x0        // Position of CLRENA field.
	NVIC_ICER0_CLRENA_Msk = 0xffffffff // Bit mask of CLRENA field.

	// ICER1: Interrupt Clear-Enable           Register
	NVIC_ICER1_CLRENA_Pos = 0x0        // Position of CLRENA field.
	NVIC_ICER1_CLRENA_Msk = 0xffffffff // Bit mask of CLRENA field.

	// ICER2: Interrupt Clear-Enable           Register
	NVIC_ICER2_CLRENA_Pos = 0x0        // Position of CLRENA field.
	NVIC_ICER2_CLRENA_Msk = 0xffffffff // Bit mask of CLRENA field.

	// ICER3: Interrupt Clear-Enable   Register
	NVIC_ICER3_CLRENA_Pos = 0x0        // Position of CLRENA field.
	NVIC_ICER3_CLRENA_Msk = 0xffffffff // Bit mask of CLRENA field.

	// ISPR0: Interrupt Set-Pending Register
	NVIC_ISPR0_SETPEND_Pos = 0x0        // Position of SETPEND field.
	NVIC_ISPR0_SETPEND_Msk = 0xffffffff // Bit mask of SETPEND field.

	// ISPR1: Interrupt Set-Pending Register
	NVIC_ISPR1_SETPEND_Pos = 0x0        // Position of SETPEND field.
	NVIC_ISPR1_SETPEND_Msk = 0xffffffff // Bit mask of SETPEND field.

	// ISPR2: Interrupt Set-Pending Register
	NVIC_ISPR2_SETPEND_Pos = 0x0        // Position of SETPEND field.
	NVIC_ISPR2_SETPEND_Msk = 0xffffffff // Bit mask of SETPEND field.

	// ISPR3: Interrupt Set-Pending Register
	NVIC_ISPR3_SETPEND_Pos = 0x0        // Position of SETPEND field.
	NVIC_ISPR3_SETPEND_Msk = 0xffffffff // Bit mask of SETPEND field.

	// ICPR0: Interrupt Clear-Pending           Register
	NVIC_ICPR0_CLRPEND_Pos = 0x0        // Position of CLRPEND field.
	NVIC_ICPR0_CLRPEND_Msk = 0xffffffff // Bit mask of CLRPEND field.

	// ICPR1: Interrupt Clear-Pending           Register
	NVIC_ICPR1_CLRPEND_Pos = 0x0        // Position of CLRPEND field.
	NVIC_ICPR1_CLRPEND_Msk = 0xffffffff // Bit mask of CLRPEND field.

	// ICPR2: Interrupt Clear-Pending           Register
	NVIC_ICPR2_CLRPEND_Pos = 0x0        // Position of CLRPEND field.
	NVIC_ICPR2_CLRPEND_Msk = 0xffffffff // Bit mask of CLRPEND field.

	// ICPR3: Interrupt Clear-Pending           Register
	NVIC_ICPR3_CLRPEND_Pos = 0x0        // Position of CLRPEND field.
	NVIC_ICPR3_CLRPEND_Msk = 0xffffffff // Bit mask of CLRPEND field.

	// IABR0: Interrupt Active Bit Register
	NVIC_IABR0_ACTIVE_Pos = 0x0        // Position of ACTIVE field.
	NVIC_IABR0_ACTIVE_Msk = 0xffffffff // Bit mask of ACTIVE field.

	// IABR1: Interrupt Active Bit Register
	NVIC_IABR1_ACTIVE_Pos = 0x0        // Position of ACTIVE field.
	NVIC_IABR1_ACTIVE_Msk = 0xffffffff // Bit mask of ACTIVE field.

	// IABR2: Interrupt Active Bit Register
	NVIC_IABR2_ACTIVE_Pos = 0x0        // Position of ACTIVE field.
	NVIC_IABR2_ACTIVE_Msk = 0xffffffff // Bit mask of ACTIVE field.

	// IABR3: Interrupt Active Bit Register
	NVIC_IABR3_ACTIVE_Pos = 0x0        // Position of ACTIVE field.
	NVIC_IABR3_ACTIVE_Msk = 0xffffffff // Bit mask of ACTIVE field.

	// IPR0: Interrupt Priority Register
	NVIC_IPR0_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR0_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR0_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR0_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR0_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR0_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR0_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR0_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR1: Interrupt Priority Register
	NVIC_IPR1_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR1_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR1_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR1_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR1_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR1_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR1_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR1_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR2: Interrupt Priority Register
	NVIC_IPR2_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR2_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR2_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR2_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR2_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR2_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR2_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR2_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR3: Interrupt Priority Register
	NVIC_IPR3_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR3_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR3_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR3_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR3_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR3_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR3_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR3_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR4: Interrupt Priority Register
	NVIC_IPR4_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR4_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR4_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR4_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR4_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR4_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR4_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR4_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR5: Interrupt Priority Register
	NVIC_IPR5_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR5_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR5_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR5_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR5_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR5_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR5_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR5_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR6: Interrupt Priority Register
	NVIC_IPR6_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR6_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR6_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR6_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR6_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR6_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR6_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR6_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR7: Interrupt Priority Register
	NVIC_IPR7_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR7_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR7_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR7_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR7_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR7_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR7_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR7_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR8: Interrupt Priority Register
	NVIC_IPR8_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR8_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR8_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR8_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR8_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR8_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR8_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR8_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR9: Interrupt Priority Register
	NVIC_IPR9_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR9_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR9_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR9_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR9_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR9_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR9_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR9_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR10: Interrupt Priority Register
	NVIC_IPR10_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR10_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR10_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR10_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR10_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR10_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR10_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR10_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR11: Interrupt Priority Register
	NVIC_IPR11_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR11_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR11_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR11_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR11_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR11_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR11_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR11_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR12: Interrupt Priority Register
	NVIC_IPR12_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR12_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR12_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR12_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR12_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR12_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR12_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR12_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR13: Interrupt Priority Register
	NVIC_IPR13_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR13_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR13_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR13_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR13_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR13_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR13_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR13_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR14: Interrupt Priority Register
	NVIC_IPR14_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR14_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR14_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR14_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR14_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR14_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR14_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR14_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR15: Interrupt Priority Register
	NVIC_IPR15_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR15_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR15_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR15_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR15_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR15_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR15_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR15_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR16: Interrupt Priority Register
	NVIC_IPR16_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR16_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR16_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR16_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR16_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR16_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR16_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR16_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR17: Interrupt Priority Register
	NVIC_IPR17_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR17_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR17_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR17_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR17_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR17_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR17_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR17_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR18: Interrupt Priority Register
	NVIC_IPR18_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR18_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR18_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR18_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR18_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR18_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR18_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR18_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR19: Interrupt Priority Register
	NVIC_IPR19_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR19_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR19_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR19_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR19_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR19_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR19_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR19_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR20: Interrupt Priority Register
	NVIC_IPR20_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR20_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR20_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR20_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR20_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR20_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR20_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR20_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// STIR: Software trigger interrupt register
	NVIC_STIR_INTID_Pos = 0x0   // Position of INTID field.
	NVIC_STIR_INTID_Msk = 0x1ff // Bit mask of INTID field.
)

// Bitfields for FDCAN: FDCAN
const (
	// CREL: FDCAN Core Release Register
	FDCAN_CREL_DAY_Pos     = 0x0        // Position of DAY field.
	FDCAN_CREL_DAY_Msk     = 0xff       // Bit mask of DAY field.
	FDCAN_CREL_MON_Pos     = 0x8        // Position of MON field.
	FDCAN_CREL_MON_Msk     = 0xff00     // Bit mask of MON field.
	FDCAN_CREL_YEAR_Pos    = 0x10       // Position of YEAR field.
	FDCAN_CREL_YEAR_Msk    = 0xf0000    // Bit mask of YEAR field.
	FDCAN_CREL_SUBSTEP_Pos = 0x14       // Position of SUBSTEP field.
	FDCAN_CREL_SUBSTEP_Msk = 0xf00000   // Bit mask of SUBSTEP field.
	FDCAN_CREL_STEP_Pos    = 0x18       // Position of STEP field.
	FDCAN_CREL_STEP_Msk    = 0xf000000  // Bit mask of STEP field.
	FDCAN_CREL_REL_Pos     = 0x1c       // Position of REL field.
	FDCAN_CREL_REL_Msk     = 0xf0000000 // Bit mask of REL field.

	// ENDN: FDCAN Core Release Register
	FDCAN_ENDN_ETV_Pos = 0x0        // Position of ETV field.
	FDCAN_ENDN_ETV_Msk = 0xffffffff // Bit mask of ETV field.

	// DBTP: This register is only writable if bits           CCCR.CCE and CCCR.INIT are set. The CAN bit time may be           programed in the range of 4 to 25 time quanta. The CAN           time quantum may be programmed in the range of 1 to 1024           FDCAN clock periods. tq = (DBRP + 1) FDCAN clock period.           DTSEG1 is the sum of Prop_Seg and Phase_Seg1. DTSEG2 is           Phase_Seg2. Therefore the length of the bit time is           (programmed values) [DTSEG1 + DTSEG2 + 3] tq or           (functional values) [Sync_Seg + Prop_Seg + Phase_Seg1 +           Phase_Seg2] tq. The Information Processing Time (IPT) is           zero, meaning the data for the next bit is available at           the first clock edge after the sample           point.
	FDCAN_DBTP_DSJW_Pos   = 0x0      // Position of DSJW field.
	FDCAN_DBTP_DSJW_Msk   = 0xf      // Bit mask of DSJW field.
	FDCAN_DBTP_DTSEG2_Pos = 0x4      // Position of DTSEG2 field.
	FDCAN_DBTP_DTSEG2_Msk = 0xf0     // Bit mask of DTSEG2 field.
	FDCAN_DBTP_DTSEG1_Pos = 0x8      // Position of DTSEG1 field.
	FDCAN_DBTP_DTSEG1_Msk = 0x1f00   // Bit mask of DTSEG1 field.
	FDCAN_DBTP_DBRP_Pos   = 0x10     // Position of DBRP field.
	FDCAN_DBTP_DBRP_Msk   = 0x1f0000 // Bit mask of DBRP field.
	FDCAN_DBTP_TDC_Pos    = 0x17     // Position of TDC field.
	FDCAN_DBTP_TDC_Msk    = 0x800000 // Bit mask of TDC field.
	FDCAN_DBTP_TDC        = 0x800000 // Bit TDC.

	// TEST: Write access to the Test Register has to be           enabled by setting bit CCCR[TEST] to 1 . All Test           Register functions are set to their reset values when bit           CCCR[TEST] is reset. Loop Back mode and software control           of Tx pin FDCANx_TX are hardware test modes. Programming           TX differently from 00 may disturb the message transfer           on the CAN bus.
	FDCAN_TEST_LBCK_Pos = 0x4  // Position of LBCK field.
	FDCAN_TEST_LBCK_Msk = 0x10 // Bit mask of LBCK field.
	FDCAN_TEST_LBCK     = 0x10 // Bit LBCK.
	FDCAN_TEST_TX_Pos   = 0x5  // Position of TX field.
	FDCAN_TEST_TX_Msk   = 0x60 // Bit mask of TX field.
	FDCAN_TEST_RX_Pos   = 0x7  // Position of RX field.
	FDCAN_TEST_RX_Msk   = 0x80 // Bit mask of RX field.
	FDCAN_TEST_RX       = 0x80 // Bit RX.

	// RWD: The RAM Watchdog monitors the READY output           of the Message RAM. A Message RAM access starts the           Message RAM Watchdog Counter with the value configured by           the RWD[WDC] bits. The counter is reloaded with RWD[WDC]           bits when the Message RAM signals successful completion           by activating its READY output. In case there is no           response from the Message RAM until the counter has           counted down to 0, the counter stops and interrupt flag           IR[WDI] bit is set. The RAM Watchdog Counter is clocked           by the fdcan_pclk clock.
	FDCAN_RWD_WDC_Pos = 0x0    // Position of WDC field.
	FDCAN_RWD_WDC_Msk = 0xff   // Bit mask of WDC field.
	FDCAN_RWD_WDV_Pos = 0x8    // Position of WDV field.
	FDCAN_RWD_WDV_Msk = 0xff00 // Bit mask of WDV field.

	// CCCR: For details about setting and resetting of           single bits see Software initialization.
	FDCAN_CCCR_INIT_Pos = 0x0    // Position of INIT field.
	FDCAN_CCCR_INIT_Msk = 0x1    // Bit mask of INIT field.
	FDCAN_CCCR_INIT     = 0x1    // Bit INIT.
	FDCAN_CCCR_CCE_Pos  = 0x1    // Position of CCE field.
	FDCAN_CCCR_CCE_Msk  = 0x2    // Bit mask of CCE field.
	FDCAN_CCCR_CCE      = 0x2    // Bit CCE.
	FDCAN_CCCR_ASM_Pos  = 0x2    // Position of ASM field.
	FDCAN_CCCR_ASM_Msk  = 0x4    // Bit mask of ASM field.
	FDCAN_CCCR_ASM      = 0x4    // Bit ASM.
	FDCAN_CCCR_CSA_Pos  = 0x3    // Position of CSA field.
	FDCAN_CCCR_CSA_Msk  = 0x8    // Bit mask of CSA field.
	FDCAN_CCCR_CSA      = 0x8    // Bit CSA.
	FDCAN_CCCR_CSR_Pos  = 0x4    // Position of CSR field.
	FDCAN_CCCR_CSR_Msk  = 0x10   // Bit mask of CSR field.
	FDCAN_CCCR_CSR      = 0x10   // Bit CSR.
	FDCAN_CCCR_MON_Pos  = 0x5    // Position of MON field.
	FDCAN_CCCR_MON_Msk  = 0x20   // Bit mask of MON field.
	FDCAN_CCCR_MON      = 0x20   // Bit MON.
	FDCAN_CCCR_DAR_Pos  = 0x6    // Position of DAR field.
	FDCAN_CCCR_DAR_Msk  = 0x40   // Bit mask of DAR field.
	FDCAN_CCCR_DAR      = 0x40   // Bit DAR.
	FDCAN_CCCR_TEST_Pos = 0x7    // Position of TEST field.
	FDCAN_CCCR_TEST_Msk = 0x80   // Bit mask of TEST field.
	FDCAN_CCCR_TEST     = 0x80   // Bit TEST.
	FDCAN_CCCR_FDOE_Pos = 0x8    // Position of FDOE field.
	FDCAN_CCCR_FDOE_Msk = 0x100  // Bit mask of FDOE field.
	FDCAN_CCCR_FDOE     = 0x100  // Bit FDOE.
	FDCAN_CCCR_BRSE_Pos = 0x9    // Position of BRSE field.
	FDCAN_CCCR_BRSE_Msk = 0x200  // Bit mask of BRSE field.
	FDCAN_CCCR_BRSE     = 0x200  // Bit BRSE.
	FDCAN_CCCR_PXHD_Pos = 0xc    // Position of PXHD field.
	FDCAN_CCCR_PXHD_Msk = 0x1000 // Bit mask of PXHD field.
	FDCAN_CCCR_PXHD     = 0x1000 // Bit PXHD.
	FDCAN_CCCR_EFBI_Pos = 0xd    // Position of EFBI field.
	FDCAN_CCCR_EFBI_Msk = 0x2000 // Bit mask of EFBI field.
	FDCAN_CCCR_EFBI     = 0x2000 // Bit EFBI.
	FDCAN_CCCR_TXP_Pos  = 0xe    // Position of TXP field.
	FDCAN_CCCR_TXP_Msk  = 0x4000 // Bit mask of TXP field.
	FDCAN_CCCR_TXP      = 0x4000 // Bit TXP.
	FDCAN_CCCR_NISO_Pos = 0xf    // Position of NISO field.
	FDCAN_CCCR_NISO_Msk = 0x8000 // Bit mask of NISO field.
	FDCAN_CCCR_NISO     = 0x8000 // Bit NISO.

	// NBTP: FDCAN_NBTP
	FDCAN_NBTP_TSEG2_Pos  = 0x0        // Position of TSEG2 field.
	FDCAN_NBTP_TSEG2_Msk  = 0x7f       // Bit mask of TSEG2 field.
	FDCAN_NBTP_NTSEG1_Pos = 0x8        // Position of NTSEG1 field.
	FDCAN_NBTP_NTSEG1_Msk = 0xff00     // Bit mask of NTSEG1 field.
	FDCAN_NBTP_NBRP_Pos   = 0x10       // Position of NBRP field.
	FDCAN_NBTP_NBRP_Msk   = 0x1ff0000  // Bit mask of NBRP field.
	FDCAN_NBTP_NSJW_Pos   = 0x19       // Position of NSJW field.
	FDCAN_NBTP_NSJW_Msk   = 0xfe000000 // Bit mask of NSJW field.

	// TSCC: FDCAN Timestamp Counter Configuration           Register
	FDCAN_TSCC_TSS_Pos = 0x0     // Position of TSS field.
	FDCAN_TSCC_TSS_Msk = 0x3     // Bit mask of TSS field.
	FDCAN_TSCC_TCP_Pos = 0x10    // Position of TCP field.
	FDCAN_TSCC_TCP_Msk = 0xf0000 // Bit mask of TCP field.

	// TSCV: FDCAN Timestamp Counter Value           Register
	FDCAN_TSCV_TSC_Pos = 0x0    // Position of TSC field.
	FDCAN_TSCV_TSC_Msk = 0xffff // Bit mask of TSC field.

	// TOCC: FDCAN Timeout Counter Configuration           Register
	FDCAN_TOCC_ETOC_Pos = 0x0        // Position of ETOC field.
	FDCAN_TOCC_ETOC_Msk = 0x1        // Bit mask of ETOC field.
	FDCAN_TOCC_ETOC     = 0x1        // Bit ETOC.
	FDCAN_TOCC_TOS_Pos  = 0x1        // Position of TOS field.
	FDCAN_TOCC_TOS_Msk  = 0x6        // Bit mask of TOS field.
	FDCAN_TOCC_TOP_Pos  = 0x10       // Position of TOP field.
	FDCAN_TOCC_TOP_Msk  = 0xffff0000 // Bit mask of TOP field.

	// TOCV: FDCAN Timeout Counter Value           Register
	FDCAN_TOCV_TOC_Pos = 0x0    // Position of TOC field.
	FDCAN_TOCV_TOC_Msk = 0xffff // Bit mask of TOC field.

	// ECR: FDCAN Error Counter Register
	FDCAN_ECR_TEC_Pos  = 0x0      // Position of TEC field.
	FDCAN_ECR_TEC_Msk  = 0xff     // Bit mask of TEC field.
	FDCAN_ECR_TREC_Pos = 0x8      // Position of TREC field.
	FDCAN_ECR_TREC_Msk = 0x7f00   // Bit mask of TREC field.
	FDCAN_ECR_RP_Pos   = 0xf      // Position of RP field.
	FDCAN_ECR_RP_Msk   = 0x8000   // Bit mask of RP field.
	FDCAN_ECR_RP       = 0x8000   // Bit RP.
	FDCAN_ECR_CEL_Pos  = 0x10     // Position of CEL field.
	FDCAN_ECR_CEL_Msk  = 0xff0000 // Bit mask of CEL field.

	// PSR: FDCAN Protocol Status Register
	FDCAN_PSR_LEC_Pos  = 0x0      // Position of LEC field.
	FDCAN_PSR_LEC_Msk  = 0x7      // Bit mask of LEC field.
	FDCAN_PSR_ACT_Pos  = 0x3      // Position of ACT field.
	FDCAN_PSR_ACT_Msk  = 0x18     // Bit mask of ACT field.
	FDCAN_PSR_EP_Pos   = 0x5      // Position of EP field.
	FDCAN_PSR_EP_Msk   = 0x20     // Bit mask of EP field.
	FDCAN_PSR_EP       = 0x20     // Bit EP.
	FDCAN_PSR_EW_Pos   = 0x6      // Position of EW field.
	FDCAN_PSR_EW_Msk   = 0x40     // Bit mask of EW field.
	FDCAN_PSR_EW       = 0x40     // Bit EW.
	FDCAN_PSR_BO_Pos   = 0x7      // Position of BO field.
	FDCAN_PSR_BO_Msk   = 0x80     // Bit mask of BO field.
	FDCAN_PSR_BO       = 0x80     // Bit BO.
	FDCAN_PSR_DLEC_Pos = 0x8      // Position of DLEC field.
	FDCAN_PSR_DLEC_Msk = 0x700    // Bit mask of DLEC field.
	FDCAN_PSR_RESI_Pos = 0xb      // Position of RESI field.
	FDCAN_PSR_RESI_Msk = 0x800    // Bit mask of RESI field.
	FDCAN_PSR_RESI     = 0x800    // Bit RESI.
	FDCAN_PSR_RBRS_Pos = 0xc      // Position of RBRS field.
	FDCAN_PSR_RBRS_Msk = 0x1000   // Bit mask of RBRS field.
	FDCAN_PSR_RBRS     = 0x1000   // Bit RBRS.
	FDCAN_PSR_REDL_Pos = 0xd      // Position of REDL field.
	FDCAN_PSR_REDL_Msk = 0x2000   // Bit mask of REDL field.
	FDCAN_PSR_REDL     = 0x2000   // Bit REDL.
	FDCAN_PSR_PXE_Pos  = 0xe      // Position of PXE field.
	FDCAN_PSR_PXE_Msk  = 0x4000   // Bit mask of PXE field.
	FDCAN_PSR_PXE      = 0x4000   // Bit PXE.
	FDCAN_PSR_TDCV_Pos = 0x10     // Position of TDCV field.
	FDCAN_PSR_TDCV_Msk = 0x7f0000 // Bit mask of TDCV field.

	// TDCR: FDCAN Transmitter Delay Compensation           Register
	FDCAN_TDCR_TDCF_Pos = 0x0    // Position of TDCF field.
	FDCAN_TDCR_TDCF_Msk = 0x7f   // Bit mask of TDCF field.
	FDCAN_TDCR_TDCO_Pos = 0x8    // Position of TDCO field.
	FDCAN_TDCR_TDCO_Msk = 0x7f00 // Bit mask of TDCO field.

	// IR: The flags are set when one of the listed           conditions is detected (edge-sensitive). The flags remain           set until the Host clears them. A flag is cleared by           writing a 1 to the corresponding bit position. Writing a           0 has no effect. A hard reset will clear the register.           The configuration of IE controls whether an interrupt is           generated. The configuration of ILS controls on which           interrupt line an interrupt is signaled.
	FDCAN_IR_RF0N_Pos = 0x0        // Position of RF0N field.
	FDCAN_IR_RF0N_Msk = 0x1        // Bit mask of RF0N field.
	FDCAN_IR_RF0N     = 0x1        // Bit RF0N.
	FDCAN_IR_RF0W_Pos = 0x1        // Position of RF0W field.
	FDCAN_IR_RF0W_Msk = 0x2        // Bit mask of RF0W field.
	FDCAN_IR_RF0W     = 0x2        // Bit RF0W.
	FDCAN_IR_RF0F_Pos = 0x2        // Position of RF0F field.
	FDCAN_IR_RF0F_Msk = 0x4        // Bit mask of RF0F field.
	FDCAN_IR_RF0F     = 0x4        // Bit RF0F.
	FDCAN_IR_RF0L_Pos = 0x3        // Position of RF0L field.
	FDCAN_IR_RF0L_Msk = 0x8        // Bit mask of RF0L field.
	FDCAN_IR_RF0L     = 0x8        // Bit RF0L.
	FDCAN_IR_RF1N_Pos = 0x4        // Position of RF1N field.
	FDCAN_IR_RF1N_Msk = 0x10       // Bit mask of RF1N field.
	FDCAN_IR_RF1N     = 0x10       // Bit RF1N.
	FDCAN_IR_RF1W_Pos = 0x5        // Position of RF1W field.
	FDCAN_IR_RF1W_Msk = 0x20       // Bit mask of RF1W field.
	FDCAN_IR_RF1W     = 0x20       // Bit RF1W.
	FDCAN_IR_RF1F_Pos = 0x6        // Position of RF1F field.
	FDCAN_IR_RF1F_Msk = 0x40       // Bit mask of RF1F field.
	FDCAN_IR_RF1F     = 0x40       // Bit RF1F.
	FDCAN_IR_RF1L_Pos = 0x7        // Position of RF1L field.
	FDCAN_IR_RF1L_Msk = 0x80       // Bit mask of RF1L field.
	FDCAN_IR_RF1L     = 0x80       // Bit RF1L.
	FDCAN_IR_HPM_Pos  = 0x8        // Position of HPM field.
	FDCAN_IR_HPM_Msk  = 0x100      // Bit mask of HPM field.
	FDCAN_IR_HPM      = 0x100      // Bit HPM.
	FDCAN_IR_TC_Pos   = 0x9        // Position of TC field.
	FDCAN_IR_TC_Msk   = 0x200      // Bit mask of TC field.
	FDCAN_IR_TC       = 0x200      // Bit TC.
	FDCAN_IR_TCF_Pos  = 0xa        // Position of TCF field.
	FDCAN_IR_TCF_Msk  = 0x400      // Bit mask of TCF field.
	FDCAN_IR_TCF      = 0x400      // Bit TCF.
	FDCAN_IR_TFE_Pos  = 0xb        // Position of TFE field.
	FDCAN_IR_TFE_Msk  = 0x800      // Bit mask of TFE field.
	FDCAN_IR_TFE      = 0x800      // Bit TFE.
	FDCAN_IR_TEFN_Pos = 0xc        // Position of TEFN field.
	FDCAN_IR_TEFN_Msk = 0x1000     // Bit mask of TEFN field.
	FDCAN_IR_TEFN     = 0x1000     // Bit TEFN.
	FDCAN_IR_TEFW_Pos = 0xd        // Position of TEFW field.
	FDCAN_IR_TEFW_Msk = 0x2000     // Bit mask of TEFW field.
	FDCAN_IR_TEFW     = 0x2000     // Bit TEFW.
	FDCAN_IR_TEFF_Pos = 0xe        // Position of TEFF field.
	FDCAN_IR_TEFF_Msk = 0x4000     // Bit mask of TEFF field.
	FDCAN_IR_TEFF     = 0x4000     // Bit TEFF.
	FDCAN_IR_TEFL_Pos = 0xf        // Position of TEFL field.
	FDCAN_IR_TEFL_Msk = 0x8000     // Bit mask of TEFL field.
	FDCAN_IR_TEFL     = 0x8000     // Bit TEFL.
	FDCAN_IR_TSW_Pos  = 0x10       // Position of TSW field.
	FDCAN_IR_TSW_Msk  = 0x10000    // Bit mask of TSW field.
	FDCAN_IR_TSW      = 0x10000    // Bit TSW.
	FDCAN_IR_MRAF_Pos = 0x11       // Position of MRAF field.
	FDCAN_IR_MRAF_Msk = 0x20000    // Bit mask of MRAF field.
	FDCAN_IR_MRAF     = 0x20000    // Bit MRAF.
	FDCAN_IR_TOO_Pos  = 0x12       // Position of TOO field.
	FDCAN_IR_TOO_Msk  = 0x40000    // Bit mask of TOO field.
	FDCAN_IR_TOO      = 0x40000    // Bit TOO.
	FDCAN_IR_DRX_Pos  = 0x13       // Position of DRX field.
	FDCAN_IR_DRX_Msk  = 0x80000    // Bit mask of DRX field.
	FDCAN_IR_DRX      = 0x80000    // Bit DRX.
	FDCAN_IR_ELO_Pos  = 0x16       // Position of ELO field.
	FDCAN_IR_ELO_Msk  = 0x400000   // Bit mask of ELO field.
	FDCAN_IR_ELO      = 0x400000   // Bit ELO.
	FDCAN_IR_EP_Pos   = 0x17       // Position of EP field.
	FDCAN_IR_EP_Msk   = 0x800000   // Bit mask of EP field.
	FDCAN_IR_EP       = 0x800000   // Bit EP.
	FDCAN_IR_EW_Pos   = 0x18       // Position of EW field.
	FDCAN_IR_EW_Msk   = 0x1000000  // Bit mask of EW field.
	FDCAN_IR_EW       = 0x1000000  // Bit EW.
	FDCAN_IR_BO_Pos   = 0x19       // Position of BO field.
	FDCAN_IR_BO_Msk   = 0x2000000  // Bit mask of BO field.
	FDCAN_IR_BO       = 0x2000000  // Bit BO.
	FDCAN_IR_WDI_Pos  = 0x1a       // Position of WDI field.
	FDCAN_IR_WDI_Msk  = 0x4000000  // Bit mask of WDI field.
	FDCAN_IR_WDI      = 0x4000000  // Bit WDI.
	FDCAN_IR_PEA_Pos  = 0x1b       // Position of PEA field.
	FDCAN_IR_PEA_Msk  = 0x8000000  // Bit mask of PEA field.
	FDCAN_IR_PEA      = 0x8000000  // Bit PEA.
	FDCAN_IR_PED_Pos  = 0x1c       // Position of PED field.
	FDCAN_IR_PED_Msk  = 0x10000000 // Bit mask of PED field.
	FDCAN_IR_PED      = 0x10000000 // Bit PED.
	FDCAN_IR_ARA_Pos  = 0x1d       // Position of ARA field.
	FDCAN_IR_ARA_Msk  = 0x20000000 // Bit mask of ARA field.
	FDCAN_IR_ARA      = 0x20000000 // Bit ARA.

	// IE: The settings in the Interrupt Enable           register determine which status changes in the Interrupt           Register will be signaled on an interrupt           line.
	FDCAN_IE_RF0NE_Pos = 0x0        // Position of RF0NE field.
	FDCAN_IE_RF0NE_Msk = 0x1        // Bit mask of RF0NE field.
	FDCAN_IE_RF0NE     = 0x1        // Bit RF0NE.
	FDCAN_IE_RF0WE_Pos = 0x1        // Position of RF0WE field.
	FDCAN_IE_RF0WE_Msk = 0x2        // Bit mask of RF0WE field.
	FDCAN_IE_RF0WE     = 0x2        // Bit RF0WE.
	FDCAN_IE_RF0FE_Pos = 0x2        // Position of RF0FE field.
	FDCAN_IE_RF0FE_Msk = 0x4        // Bit mask of RF0FE field.
	FDCAN_IE_RF0FE     = 0x4        // Bit RF0FE.
	FDCAN_IE_RF0LE_Pos = 0x3        // Position of RF0LE field.
	FDCAN_IE_RF0LE_Msk = 0x8        // Bit mask of RF0LE field.
	FDCAN_IE_RF0LE     = 0x8        // Bit RF0LE.
	FDCAN_IE_RF1NE_Pos = 0x4        // Position of RF1NE field.
	FDCAN_IE_RF1NE_Msk = 0x10       // Bit mask of RF1NE field.
	FDCAN_IE_RF1NE     = 0x10       // Bit RF1NE.
	FDCAN_IE_RF1WE_Pos = 0x5        // Position of RF1WE field.
	FDCAN_IE_RF1WE_Msk = 0x20       // Bit mask of RF1WE field.
	FDCAN_IE_RF1WE     = 0x20       // Bit RF1WE.
	FDCAN_IE_RF1FE_Pos = 0x6        // Position of RF1FE field.
	FDCAN_IE_RF1FE_Msk = 0x40       // Bit mask of RF1FE field.
	FDCAN_IE_RF1FE     = 0x40       // Bit RF1FE.
	FDCAN_IE_RF1LE_Pos = 0x7        // Position of RF1LE field.
	FDCAN_IE_RF1LE_Msk = 0x80       // Bit mask of RF1LE field.
	FDCAN_IE_RF1LE     = 0x80       // Bit RF1LE.
	FDCAN_IE_HPME_Pos  = 0x8        // Position of HPME field.
	FDCAN_IE_HPME_Msk  = 0x100      // Bit mask of HPME field.
	FDCAN_IE_HPME      = 0x100      // Bit HPME.
	FDCAN_IE_TCE_Pos   = 0x9        // Position of TCE field.
	FDCAN_IE_TCE_Msk   = 0x200      // Bit mask of TCE field.
	FDCAN_IE_TCE       = 0x200      // Bit TCE.
	FDCAN_IE_TCFE_Pos  = 0xa        // Position of TCFE field.
	FDCAN_IE_TCFE_Msk  = 0x400      // Bit mask of TCFE field.
	FDCAN_IE_TCFE      = 0x400      // Bit TCFE.
	FDCAN_IE_TFEE_Pos  = 0xb        // Position of TFEE field.
	FDCAN_IE_TFEE_Msk  = 0x800      // Bit mask of TFEE field.
	FDCAN_IE_TFEE      = 0x800      // Bit TFEE.
	FDCAN_IE_TEFNE_Pos = 0xc        // Position of TEFNE field.
	FDCAN_IE_TEFNE_Msk = 0x1000     // Bit mask of TEFNE field.
	FDCAN_IE_TEFNE     = 0x1000     // Bit TEFNE.
	FDCAN_IE_TEFWE_Pos = 0xd        // Position of TEFWE field.
	FDCAN_IE_TEFWE_Msk = 0x2000     // Bit mask of TEFWE field.
	FDCAN_IE_TEFWE     = 0x2000     // Bit TEFWE.
	FDCAN_IE_TEFFE_Pos = 0xe        // Position of TEFFE field.
	FDCAN_IE_TEFFE_Msk = 0x4000     // Bit mask of TEFFE field.
	FDCAN_IE_TEFFE     = 0x4000     // Bit TEFFE.
	FDCAN_IE_TEFLE_Pos = 0xf        // Position of TEFLE field.
	FDCAN_IE_TEFLE_Msk = 0x8000     // Bit mask of TEFLE field.
	FDCAN_IE_TEFLE     = 0x8000     // Bit TEFLE.
	FDCAN_IE_TSWE_Pos  = 0x10       // Position of TSWE field.
	FDCAN_IE_TSWE_Msk  = 0x10000    // Bit mask of TSWE field.
	FDCAN_IE_TSWE      = 0x10000    // Bit TSWE.
	FDCAN_IE_MRAFE_Pos = 0x11       // Position of MRAFE field.
	FDCAN_IE_MRAFE_Msk = 0x20000    // Bit mask of MRAFE field.
	FDCAN_IE_MRAFE     = 0x20000    // Bit MRAFE.
	FDCAN_IE_TOOE_Pos  = 0x12       // Position of TOOE field.
	FDCAN_IE_TOOE_Msk  = 0x40000    // Bit mask of TOOE field.
	FDCAN_IE_TOOE      = 0x40000    // Bit TOOE.
	FDCAN_IE_DRX_Pos   = 0x13       // Position of DRX field.
	FDCAN_IE_DRX_Msk   = 0x80000    // Bit mask of DRX field.
	FDCAN_IE_DRX       = 0x80000    // Bit DRX.
	FDCAN_IE_BECE_Pos  = 0x14       // Position of BECE field.
	FDCAN_IE_BECE_Msk  = 0x100000   // Bit mask of BECE field.
	FDCAN_IE_BECE      = 0x100000   // Bit BECE.
	FDCAN_IE_BEUE_Pos  = 0x15       // Position of BEUE field.
	FDCAN_IE_BEUE_Msk  = 0x200000   // Bit mask of BEUE field.
	FDCAN_IE_BEUE      = 0x200000   // Bit BEUE.
	FDCAN_IE_ELOE_Pos  = 0x16       // Position of ELOE field.
	FDCAN_IE_ELOE_Msk  = 0x400000   // Bit mask of ELOE field.
	FDCAN_IE_ELOE      = 0x400000   // Bit ELOE.
	FDCAN_IE_EPE_Pos   = 0x17       // Position of EPE field.
	FDCAN_IE_EPE_Msk   = 0x800000   // Bit mask of EPE field.
	FDCAN_IE_EPE       = 0x800000   // Bit EPE.
	FDCAN_IE_EWE_Pos   = 0x18       // Position of EWE field.
	FDCAN_IE_EWE_Msk   = 0x1000000  // Bit mask of EWE field.
	FDCAN_IE_EWE       = 0x1000000  // Bit EWE.
	FDCAN_IE_BOE_Pos   = 0x19       // Position of BOE field.
	FDCAN_IE_BOE_Msk   = 0x2000000  // Bit mask of BOE field.
	FDCAN_IE_BOE       = 0x2000000  // Bit BOE.
	FDCAN_IE_WDIE_Pos  = 0x1a       // Position of WDIE field.
	FDCAN_IE_WDIE_Msk  = 0x4000000  // Bit mask of WDIE field.
	FDCAN_IE_WDIE      = 0x4000000  // Bit WDIE.
	FDCAN_IE_PEAE_Pos  = 0x1b       // Position of PEAE field.
	FDCAN_IE_PEAE_Msk  = 0x8000000  // Bit mask of PEAE field.
	FDCAN_IE_PEAE      = 0x8000000  // Bit PEAE.
	FDCAN_IE_PEDE_Pos  = 0x1c       // Position of PEDE field.
	FDCAN_IE_PEDE_Msk  = 0x10000000 // Bit mask of PEDE field.
	FDCAN_IE_PEDE      = 0x10000000 // Bit PEDE.
	FDCAN_IE_ARAE_Pos  = 0x1d       // Position of ARAE field.
	FDCAN_IE_ARAE_Msk  = 0x20000000 // Bit mask of ARAE field.
	FDCAN_IE_ARAE      = 0x20000000 // Bit ARAE.

	// ILS: The Interrupt Line Select register assigns           an interrupt generated by a specific interrupt flag from           the Interrupt Register to one of the two module interrupt           lines. For interrupt generation the respective interrupt           line has to be enabled via ILE[EINT0] and           ILE[EINT1].
	FDCAN_ILS_RF0NL_Pos = 0x0        // Position of RF0NL field.
	FDCAN_ILS_RF0NL_Msk = 0x1        // Bit mask of RF0NL field.
	FDCAN_ILS_RF0NL     = 0x1        // Bit RF0NL.
	FDCAN_ILS_RF0WL_Pos = 0x1        // Position of RF0WL field.
	FDCAN_ILS_RF0WL_Msk = 0x2        // Bit mask of RF0WL field.
	FDCAN_ILS_RF0WL     = 0x2        // Bit RF0WL.
	FDCAN_ILS_RF0FL_Pos = 0x2        // Position of RF0FL field.
	FDCAN_ILS_RF0FL_Msk = 0x4        // Bit mask of RF0FL field.
	FDCAN_ILS_RF0FL     = 0x4        // Bit RF0FL.
	FDCAN_ILS_RF0LL_Pos = 0x3        // Position of RF0LL field.
	FDCAN_ILS_RF0LL_Msk = 0x8        // Bit mask of RF0LL field.
	FDCAN_ILS_RF0LL     = 0x8        // Bit RF0LL.
	FDCAN_ILS_RF1NL_Pos = 0x4        // Position of RF1NL field.
	FDCAN_ILS_RF1NL_Msk = 0x10       // Bit mask of RF1NL field.
	FDCAN_ILS_RF1NL     = 0x10       // Bit RF1NL.
	FDCAN_ILS_RF1WL_Pos = 0x5        // Position of RF1WL field.
	FDCAN_ILS_RF1WL_Msk = 0x20       // Bit mask of RF1WL field.
	FDCAN_ILS_RF1WL     = 0x20       // Bit RF1WL.
	FDCAN_ILS_RF1FL_Pos = 0x6        // Position of RF1FL field.
	FDCAN_ILS_RF1FL_Msk = 0x40       // Bit mask of RF1FL field.
	FDCAN_ILS_RF1FL     = 0x40       // Bit RF1FL.
	FDCAN_ILS_RF1LL_Pos = 0x7        // Position of RF1LL field.
	FDCAN_ILS_RF1LL_Msk = 0x80       // Bit mask of RF1LL field.
	FDCAN_ILS_RF1LL     = 0x80       // Bit RF1LL.
	FDCAN_ILS_HPML_Pos  = 0x8        // Position of HPML field.
	FDCAN_ILS_HPML_Msk  = 0x100      // Bit mask of HPML field.
	FDCAN_ILS_HPML      = 0x100      // Bit HPML.
	FDCAN_ILS_TCL_Pos   = 0x9        // Position of TCL field.
	FDCAN_ILS_TCL_Msk   = 0x200      // Bit mask of TCL field.
	FDCAN_ILS_TCL       = 0x200      // Bit TCL.
	FDCAN_ILS_TCFL_Pos  = 0xa        // Position of TCFL field.
	FDCAN_ILS_TCFL_Msk  = 0x400      // Bit mask of TCFL field.
	FDCAN_ILS_TCFL      = 0x400      // Bit TCFL.
	FDCAN_ILS_TFEL_Pos  = 0xb        // Position of TFEL field.
	FDCAN_ILS_TFEL_Msk  = 0x800      // Bit mask of TFEL field.
	FDCAN_ILS_TFEL      = 0x800      // Bit TFEL.
	FDCAN_ILS_TEFNL_Pos = 0xc        // Position of TEFNL field.
	FDCAN_ILS_TEFNL_Msk = 0x1000     // Bit mask of TEFNL field.
	FDCAN_ILS_TEFNL     = 0x1000     // Bit TEFNL.
	FDCAN_ILS_TEFWL_Pos = 0xd        // Position of TEFWL field.
	FDCAN_ILS_TEFWL_Msk = 0x2000     // Bit mask of TEFWL field.
	FDCAN_ILS_TEFWL     = 0x2000     // Bit TEFWL.
	FDCAN_ILS_TEFFL_Pos = 0xe        // Position of TEFFL field.
	FDCAN_ILS_TEFFL_Msk = 0x4000     // Bit mask of TEFFL field.
	FDCAN_ILS_TEFFL     = 0x4000     // Bit TEFFL.
	FDCAN_ILS_TEFLL_Pos = 0xf        // Position of TEFLL field.
	FDCAN_ILS_TEFLL_Msk = 0x8000     // Bit mask of TEFLL field.
	FDCAN_ILS_TEFLL     = 0x8000     // Bit TEFLL.
	FDCAN_ILS_TSWL_Pos  = 0x10       // Position of TSWL field.
	FDCAN_ILS_TSWL_Msk  = 0x10000    // Bit mask of TSWL field.
	FDCAN_ILS_TSWL      = 0x10000    // Bit TSWL.
	FDCAN_ILS_MRAFL_Pos = 0x11       // Position of MRAFL field.
	FDCAN_ILS_MRAFL_Msk = 0x20000    // Bit mask of MRAFL field.
	FDCAN_ILS_MRAFL     = 0x20000    // Bit MRAFL.
	FDCAN_ILS_TOOL_Pos  = 0x12       // Position of TOOL field.
	FDCAN_ILS_TOOL_Msk  = 0x40000    // Bit mask of TOOL field.
	FDCAN_ILS_TOOL      = 0x40000    // Bit TOOL.
	FDCAN_ILS_DRXL_Pos  = 0x13       // Position of DRXL field.
	FDCAN_ILS_DRXL_Msk  = 0x80000    // Bit mask of DRXL field.
	FDCAN_ILS_DRXL      = 0x80000    // Bit DRXL.
	FDCAN_ILS_BECL_Pos  = 0x14       // Position of BECL field.
	FDCAN_ILS_BECL_Msk  = 0x100000   // Bit mask of BECL field.
	FDCAN_ILS_BECL      = 0x100000   // Bit BECL.
	FDCAN_ILS_BEUL_Pos  = 0x15       // Position of BEUL field.
	FDCAN_ILS_BEUL_Msk  = 0x200000   // Bit mask of BEUL field.
	FDCAN_ILS_BEUL      = 0x200000   // Bit BEUL.
	FDCAN_ILS_ELOL_Pos  = 0x16       // Position of ELOL field.
	FDCAN_ILS_ELOL_Msk  = 0x400000   // Bit mask of ELOL field.
	FDCAN_ILS_ELOL      = 0x400000   // Bit ELOL.
	FDCAN_ILS_EPL_Pos   = 0x17       // Position of EPL field.
	FDCAN_ILS_EPL_Msk   = 0x800000   // Bit mask of EPL field.
	FDCAN_ILS_EPL       = 0x800000   // Bit EPL.
	FDCAN_ILS_EWL_Pos   = 0x18       // Position of EWL field.
	FDCAN_ILS_EWL_Msk   = 0x1000000  // Bit mask of EWL field.
	FDCAN_ILS_EWL       = 0x1000000  // Bit EWL.
	FDCAN_ILS_BOL_Pos   = 0x19       // Position of BOL field.
	FDCAN_ILS_BOL_Msk   = 0x2000000  // Bit mask of BOL field.
	FDCAN_ILS_BOL       = 0x2000000  // Bit BOL.
	FDCAN_ILS_WDIL_Pos  = 0x1a       // Position of WDIL field.
	FDCAN_ILS_WDIL_Msk  = 0x4000000  // Bit mask of WDIL field.
	FDCAN_ILS_WDIL      = 0x4000000  // Bit WDIL.
	FDCAN_ILS_PEAL_Pos  = 0x1b       // Position of PEAL field.
	FDCAN_ILS_PEAL_Msk  = 0x8000000  // Bit mask of PEAL field.
	FDCAN_ILS_PEAL      = 0x8000000  // Bit PEAL.
	FDCAN_ILS_PEDL_Pos  = 0x1c       // Position of PEDL field.
	FDCAN_ILS_PEDL_Msk  = 0x10000000 // Bit mask of PEDL field.
	FDCAN_ILS_PEDL      = 0x10000000 // Bit PEDL.
	FDCAN_ILS_ARAL_Pos  = 0x1d       // Position of ARAL field.
	FDCAN_ILS_ARAL_Msk  = 0x20000000 // Bit mask of ARAL field.
	FDCAN_ILS_ARAL      = 0x20000000 // Bit ARAL.

	// ILE: Each of the two interrupt lines to the CPU           can be enabled/disabled separately by programming bits           EINT0 and EINT1.
	FDCAN_ILE_EINT0_Pos = 0x0 // Position of EINT0 field.
	FDCAN_ILE_EINT0_Msk = 0x1 // Bit mask of EINT0 field.
	FDCAN_ILE_EINT0     = 0x1 // Bit EINT0.
	FDCAN_ILE_EINT1_Pos = 0x1 // Position of EINT1 field.
	FDCAN_ILE_EINT1_Msk = 0x2 // Bit mask of EINT1 field.
	FDCAN_ILE_EINT1     = 0x2 // Bit EINT1.

	// RXGFC: Global settings for Message ID filtering.           The Global Filter Configuration controls the filter path           for standard and extended messages as described in           Figure706: Standard Message ID filter path and Figure707:           Extended Message ID filter path.
	FDCAN_RXGFC_RRFE_Pos = 0x0  // Position of RRFE field.
	FDCAN_RXGFC_RRFE_Msk = 0x1  // Bit mask of RRFE field.
	FDCAN_RXGFC_RRFE     = 0x1  // Bit RRFE.
	FDCAN_RXGFC_RRFS_Pos = 0x1  // Position of RRFS field.
	FDCAN_RXGFC_RRFS_Msk = 0x2  // Bit mask of RRFS field.
	FDCAN_RXGFC_RRFS     = 0x2  // Bit RRFS.
	FDCAN_RXGFC_ANFE_Pos = 0x2  // Position of ANFE field.
	FDCAN_RXGFC_ANFE_Msk = 0xc  // Bit mask of ANFE field.
	FDCAN_RXGFC_ANFS_Pos = 0x4  // Position of ANFS field.
	FDCAN_RXGFC_ANFS_Msk = 0x30 // Bit mask of ANFS field.

	// XIDAM: FDCAN Extended ID and Mask   Register
	FDCAN_XIDAM_EIDM_Pos = 0x0        // Position of EIDM field.
	FDCAN_XIDAM_EIDM_Msk = 0x1fffffff // Bit mask of EIDM field.

	// HPMS: This register is updated every time a    Message ID filter element configured to generate a    priority event match. This can be used to monitor the    status of incoming high priority messages and to enable           fast access to these messages.
	FDCAN_HPMS_BIDX_Pos = 0x0    // Position of BIDX field.
	FDCAN_HPMS_BIDX_Msk = 0x3f   // Bit mask of BIDX field.
	FDCAN_HPMS_MSI_Pos  = 0x6    // Position of MSI field.
	FDCAN_HPMS_MSI_Msk  = 0xc0   // Bit mask of MSI field.
	FDCAN_HPMS_FIDX_Pos = 0x8    // Position of FIDX field.
	FDCAN_HPMS_FIDX_Msk = 0x7f00 // Bit mask of FIDX field.
	FDCAN_HPMS_FLST_Pos = 0xf    // Position of FLST field.
	FDCAN_HPMS_FLST_Msk = 0x8000 // Bit mask of FLST field.
	FDCAN_HPMS_FLST     = 0x8000 // Bit FLST.

	// RXF0S: FDCAN Rx FIFO 0 Status Register
	FDCAN_RXF0S_F0FL_Pos = 0x0       // Position of F0FL field.
	FDCAN_RXF0S_F0FL_Msk = 0x7f      // Bit mask of F0FL field.
	FDCAN_RXF0S_F0GI_Pos = 0x8       // Position of F0GI field.
	FDCAN_RXF0S_F0GI_Msk = 0x3f00    // Bit mask of F0GI field.
	FDCAN_RXF0S_F0PI_Pos = 0x10      // Position of F0PI field.
	FDCAN_RXF0S_F0PI_Msk = 0x3f0000  // Bit mask of F0PI field.
	FDCAN_RXF0S_F0F_Pos  = 0x18      // Position of F0F field.
	FDCAN_RXF0S_F0F_Msk  = 0x1000000 // Bit mask of F0F field.
	FDCAN_RXF0S_F0F      = 0x1000000 // Bit F0F.
	FDCAN_RXF0S_RF0L_Pos = 0x19      // Position of RF0L field.
	FDCAN_RXF0S_RF0L_Msk = 0x2000000 // Bit mask of RF0L field.
	FDCAN_RXF0S_RF0L     = 0x2000000 // Bit RF0L.

	// RXF0A: CAN Rx FIFO 0 Acknowledge Register
	FDCAN_RXF0A_F0AI_Pos = 0x0  // Position of F0AI field.
	FDCAN_RXF0A_F0AI_Msk = 0x3f // Bit mask of F0AI field.

	// RXF1S: FDCAN Rx FIFO 1 Status  Register
	FDCAN_RXF1S_F1FL_Pos = 0x0        // Position of F1FL field.
	FDCAN_RXF1S_F1FL_Msk = 0x7f       // Bit mask of F1FL field.
	FDCAN_RXF1S_F1GI_Pos = 0x8        // Position of F1GI field.
	FDCAN_RXF1S_F1GI_Msk = 0x3f00     // Bit mask of F1GI field.
	FDCAN_RXF1S_F1PI_Pos = 0x10       // Position of F1PI field.
	FDCAN_RXF1S_F1PI_Msk = 0x3f0000   // Bit mask of F1PI field.
	FDCAN_RXF1S_F1F_Pos  = 0x18       // Position of F1F field.
	FDCAN_RXF1S_F1F_Msk  = 0x1000000  // Bit mask of F1F field.
	FDCAN_RXF1S_F1F      = 0x1000000  // Bit F1F.
	FDCAN_RXF1S_RF1L_Pos = 0x19       // Position of RF1L field.
	FDCAN_RXF1S_RF1L_Msk = 0x2000000  // Bit mask of RF1L field.
	FDCAN_RXF1S_RF1L     = 0x2000000  // Bit RF1L.
	FDCAN_RXF1S_DMS_Pos  = 0x1e       // Position of DMS field.
	FDCAN_RXF1S_DMS_Msk  = 0xc0000000 // Bit mask of DMS field.

	// RXF1A: FDCAN Rx FIFO 1 Acknowledge Register
	FDCAN_RXF1A_F1AI_Pos = 0x0  // Position of F1AI field.
	FDCAN_RXF1A_F1AI_Msk = 0x3f // Bit mask of F1AI field.

	// TXBC: FDCAN Tx Buffer Configuration  Register
	FDCAN_TXBC_TBSA_Pos = 0x2        // Position of TBSA field.
	FDCAN_TXBC_TBSA_Msk = 0xfffc     // Bit mask of TBSA field.
	FDCAN_TXBC_NDTB_Pos = 0x10       // Position of NDTB field.
	FDCAN_TXBC_NDTB_Msk = 0x3f0000   // Bit mask of NDTB field.
	FDCAN_TXBC_TFQS_Pos = 0x18       // Position of TFQS field.
	FDCAN_TXBC_TFQS_Msk = 0x3f000000 // Bit mask of TFQS field.
	FDCAN_TXBC_TFQM_Pos = 0x1e       // Position of TFQM field.
	FDCAN_TXBC_TFQM_Msk = 0x40000000 // Bit mask of TFQM field.
	FDCAN_TXBC_TFQM     = 0x40000000 // Bit TFQM.

	// TXFQS: The Tx FIFO/Queue status is related to the    pending Tx requests listed in register TXBRP. Therefore     the effect of Add/Cancellation requests may be delayed   due to a running Tx scan (TXBRP not yet           updated).
	FDCAN_TXFQS_TFFL_Pos  = 0x0      // Position of TFFL field.
	FDCAN_TXFQS_TFFL_Msk  = 0x3f     // Bit mask of TFFL field.
	FDCAN_TXFQS_TFGI_Pos  = 0x8      // Position of TFGI field.
	FDCAN_TXFQS_TFGI_Msk  = 0x1f00   // Bit mask of TFGI field.
	FDCAN_TXFQS_TFQPI_Pos = 0x10     // Position of TFQPI field.
	FDCAN_TXFQS_TFQPI_Msk = 0x1f0000 // Bit mask of TFQPI field.
	FDCAN_TXFQS_TFQF_Pos  = 0x15     // Position of TFQF field.
	FDCAN_TXFQS_TFQF_Msk  = 0x200000 // Bit mask of TFQF field.
	FDCAN_TXFQS_TFQF      = 0x200000 // Bit TFQF.

	// TXBRP: FDCAN Tx Buffer Request Pending           Register
	FDCAN_TXBRP_TRP_Pos = 0x0        // Position of TRP field.
	FDCAN_TXBRP_TRP_Msk = 0xffffffff // Bit mask of TRP field.

	// TXBAR: FDCAN Tx Buffer Add Request           Register
	FDCAN_TXBAR_AR_Pos = 0x0        // Position of AR field.
	FDCAN_TXBAR_AR_Msk = 0xffffffff // Bit mask of AR field.

	// TXBCR: FDCAN Tx Buffer Cancellation Request           Register
	FDCAN_TXBCR_CR_Pos = 0x0        // Position of CR field.
	FDCAN_TXBCR_CR_Msk = 0xffffffff // Bit mask of CR field.

	// TXBTO: FDCAN Tx Buffer Transmission Occurred           Register
	FDCAN_TXBTO_TO_Pos = 0x0        // Position of TO field.
	FDCAN_TXBTO_TO_Msk = 0xffffffff // Bit mask of TO field.

	// TXBCF: FDCAN Tx Buffer Cancellation Finished           Register
	FDCAN_TXBCF_CF_Pos = 0x0        // Position of CF field.
	FDCAN_TXBCF_CF_Msk = 0xffffffff // Bit mask of CF field.

	// TXBTIE: FDCAN Tx Buffer Transmission Interrupt           Enable Register
	FDCAN_TXBTIE_TIE_Pos = 0x0        // Position of TIE field.
	FDCAN_TXBTIE_TIE_Msk = 0xffffffff // Bit mask of TIE field.

	// TXBCIE: FDCAN Tx Buffer Cancellation Finished           Interrupt Enable Register
	FDCAN_TXBCIE_CFIE_Pos = 0x0        // Position of CFIE field.
	FDCAN_TXBCIE_CFIE_Msk = 0xffffffff // Bit mask of CFIE field.

	// TXEFS: FDCAN Tx Event FIFO Status           Register
	FDCAN_TXEFS_EFFL_Pos = 0x0       // Position of EFFL field.
	FDCAN_TXEFS_EFFL_Msk = 0x3f      // Bit mask of EFFL field.
	FDCAN_TXEFS_EFGI_Pos = 0x8       // Position of EFGI field.
	FDCAN_TXEFS_EFGI_Msk = 0x1f00    // Bit mask of EFGI field.
	FDCAN_TXEFS_EFPI_Pos = 0x10      // Position of EFPI field.
	FDCAN_TXEFS_EFPI_Msk = 0x1f0000  // Bit mask of EFPI field.
	FDCAN_TXEFS_EFF_Pos  = 0x18      // Position of EFF field.
	FDCAN_TXEFS_EFF_Msk  = 0x1000000 // Bit mask of EFF field.
	FDCAN_TXEFS_EFF      = 0x1000000 // Bit EFF.
	FDCAN_TXEFS_TEFL_Pos = 0x19      // Position of TEFL field.
	FDCAN_TXEFS_TEFL_Msk = 0x2000000 // Bit mask of TEFL field.
	FDCAN_TXEFS_TEFL     = 0x2000000 // Bit TEFL.

	// TXEFA: FDCAN Tx Event FIFO Acknowledge           Register
	FDCAN_TXEFA_EFAI_Pos = 0x0  // Position of EFAI field.
	FDCAN_TXEFA_EFAI_Msk = 0x1f // Bit mask of EFAI field.

	// CKDIV: FDCAN CFG clock divider           register
	FDCAN_CKDIV_PDIV_Pos = 0x0 // Position of PDIV field.
	FDCAN_CKDIV_PDIV_Msk = 0xf // Bit mask of PDIV field.
)

// Bitfields for UCPD1: UCPD1
const (
	// CFG1: UCPD configuration register 1
	UCPD_CFG1_HBITCLKDIV_Pos   = 0x0        // Position of HBITCLKDIV field.
	UCPD_CFG1_HBITCLKDIV_Msk   = 0x3f       // Bit mask of HBITCLKDIV field.
	UCPD_CFG1_IFRGAP_Pos       = 0x6        // Position of IFRGAP field.
	UCPD_CFG1_IFRGAP_Msk       = 0x7c0      // Bit mask of IFRGAP field.
	UCPD_CFG1_TRANSWIN_Pos     = 0xb        // Position of TRANSWIN field.
	UCPD_CFG1_TRANSWIN_Msk     = 0xf800     // Bit mask of TRANSWIN field.
	UCPD_CFG1_PSC_USBPDCLK_Pos = 0x11       // Position of PSC_USBPDCLK field.
	UCPD_CFG1_PSC_USBPDCLK_Msk = 0xe0000    // Bit mask of PSC_USBPDCLK field.
	UCPD_CFG1_RXORDSETEN_Pos   = 0x14       // Position of RXORDSETEN field.
	UCPD_CFG1_RXORDSETEN_Msk   = 0x1ff00000 // Bit mask of RXORDSETEN field.
	UCPD_CFG1_TXDMAEN_Pos      = 0x1d       // Position of TXDMAEN field.
	UCPD_CFG1_TXDMAEN_Msk      = 0x20000000 // Bit mask of TXDMAEN field.
	UCPD_CFG1_TXDMAEN          = 0x20000000 // Bit TXDMAEN.
	UCPD_CFG1_RXDMAEN_Pos      = 0x1e       // Position of RXDMAEN field.
	UCPD_CFG1_RXDMAEN_Msk      = 0x40000000 // Bit mask of RXDMAEN field.
	UCPD_CFG1_RXDMAEN          = 0x40000000 // Bit RXDMAEN.
	UCPD_CFG1_UCPDEN_Pos       = 0x1f       // Position of UCPDEN field.
	UCPD_CFG1_UCPDEN_Msk       = 0x80000000 // Bit mask of UCPDEN field.
	UCPD_CFG1_UCPDEN           = 0x80000000 // Bit UCPDEN.

	// CFG2: UCPD configuration register 2
	UCPD_CFG2_RXFILTDIS_Pos = 0x0 // Position of RXFILTDIS field.
	UCPD_CFG2_RXFILTDIS_Msk = 0x1 // Bit mask of RXFILTDIS field.
	UCPD_CFG2_RXFILTDIS     = 0x1 // Bit RXFILTDIS.
	UCPD_CFG2_RXFILT2N3_Pos = 0x1 // Position of RXFILT2N3 field.
	UCPD_CFG2_RXFILT2N3_Msk = 0x2 // Bit mask of RXFILT2N3 field.
	UCPD_CFG2_RXFILT2N3     = 0x2 // Bit RXFILT2N3.
	UCPD_CFG2_FORCECLK_Pos  = 0x2 // Position of FORCECLK field.
	UCPD_CFG2_FORCECLK_Msk  = 0x4 // Bit mask of FORCECLK field.
	UCPD_CFG2_FORCECLK      = 0x4 // Bit FORCECLK.
	UCPD_CFG2_WUPEN_Pos     = 0x3 // Position of WUPEN field.
	UCPD_CFG2_WUPEN_Msk     = 0x8 // Bit mask of WUPEN field.
	UCPD_CFG2_WUPEN         = 0x8 // Bit WUPEN.

	// CR: UCPD configuration register 2
	UCPD_CR_TXMODE_Pos     = 0x0      // Position of TXMODE field.
	UCPD_CR_TXMODE_Msk     = 0x3      // Bit mask of TXMODE field.
	UCPD_CR_TXSEND_Pos     = 0x2      // Position of TXSEND field.
	UCPD_CR_TXSEND_Msk     = 0x4      // Bit mask of TXSEND field.
	UCPD_CR_TXSEND         = 0x4      // Bit TXSEND.
	UCPD_CR_TXHRST_Pos     = 0x3      // Position of TXHRST field.
	UCPD_CR_TXHRST_Msk     = 0x8      // Bit mask of TXHRST field.
	UCPD_CR_TXHRST         = 0x8      // Bit TXHRST.
	UCPD_CR_RXMODE_Pos     = 0x4      // Position of RXMODE field.
	UCPD_CR_RXMODE_Msk     = 0x10     // Bit mask of RXMODE field.
	UCPD_CR_RXMODE         = 0x10     // Bit RXMODE.
	UCPD_CR_PHYRXEN_Pos    = 0x5      // Position of PHYRXEN field.
	UCPD_CR_PHYRXEN_Msk    = 0x20     // Bit mask of PHYRXEN field.
	UCPD_CR_PHYRXEN        = 0x20     // Bit PHYRXEN.
	UCPD_CR_PHYCCSEL_Pos   = 0x6      // Position of PHYCCSEL field.
	UCPD_CR_PHYCCSEL_Msk   = 0x40     // Bit mask of PHYCCSEL field.
	UCPD_CR_PHYCCSEL       = 0x40     // Bit PHYCCSEL.
	UCPD_CR_ANASUBMODE_Pos = 0x7      // Position of ANASUBMODE field.
	UCPD_CR_ANASUBMODE_Msk = 0x180    // Bit mask of ANASUBMODE field.
	UCPD_CR_ANAMODE_Pos    = 0x9      // Position of ANAMODE field.
	UCPD_CR_ANAMODE_Msk    = 0x200    // Bit mask of ANAMODE field.
	UCPD_CR_ANAMODE        = 0x200    // Bit ANAMODE.
	UCPD_CR_CCENABLE_Pos   = 0xa      // Position of CCENABLE field.
	UCPD_CR_CCENABLE_Msk   = 0xc00    // Bit mask of CCENABLE field.
	UCPD_CR_FRSRXEN_Pos    = 0x10     // Position of FRSRXEN field.
	UCPD_CR_FRSRXEN_Msk    = 0x10000  // Bit mask of FRSRXEN field.
	UCPD_CR_FRSRXEN        = 0x10000  // Bit FRSRXEN.
	UCPD_CR_FRSTX_Pos      = 0x11     // Position of FRSTX field.
	UCPD_CR_FRSTX_Msk      = 0x20000  // Bit mask of FRSTX field.
	UCPD_CR_FRSTX          = 0x20000  // Bit FRSTX.
	UCPD_CR_RDCH_Pos       = 0x12     // Position of RDCH field.
	UCPD_CR_RDCH_Msk       = 0x40000  // Bit mask of RDCH field.
	UCPD_CR_RDCH           = 0x40000  // Bit RDCH.
	UCPD_CR_CC1TCDIS_Pos   = 0x14     // Position of CC1TCDIS field.
	UCPD_CR_CC1TCDIS_Msk   = 0x100000 // Bit mask of CC1TCDIS field.
	UCPD_CR_CC1TCDIS       = 0x100000 // Bit CC1TCDIS.
	UCPD_CR_CC2TCDIS_Pos   = 0x15     // Position of CC2TCDIS field.
	UCPD_CR_CC2TCDIS_Msk   = 0x200000 // Bit mask of CC2TCDIS field.
	UCPD_CR_CC2TCDIS       = 0x200000 // Bit CC2TCDIS.

	// IMR: UCPD Interrupt Mask Register
	UCPD_IMR_TXISIE_Pos      = 0x0      // Position of TXISIE field.
	UCPD_IMR_TXISIE_Msk      = 0x1      // Bit mask of TXISIE field.
	UCPD_IMR_TXISIE          = 0x1      // Bit TXISIE.
	UCPD_IMR_TXMSGDISCIE_Pos = 0x1      // Position of TXMSGDISCIE field.
	UCPD_IMR_TXMSGDISCIE_Msk = 0x2      // Bit mask of TXMSGDISCIE field.
	UCPD_IMR_TXMSGDISCIE     = 0x2      // Bit TXMSGDISCIE.
	UCPD_IMR_TXMSGSENTIE_Pos = 0x2      // Position of TXMSGSENTIE field.
	UCPD_IMR_TXMSGSENTIE_Msk = 0x4      // Bit mask of TXMSGSENTIE field.
	UCPD_IMR_TXMSGSENTIE     = 0x4      // Bit TXMSGSENTIE.
	UCPD_IMR_TXMSGABTIE_Pos  = 0x3      // Position of TXMSGABTIE field.
	UCPD_IMR_TXMSGABTIE_Msk  = 0x8      // Bit mask of TXMSGABTIE field.
	UCPD_IMR_TXMSGABTIE      = 0x8      // Bit TXMSGABTIE.
	UCPD_IMR_HRSTDISCIE_Pos  = 0x4      // Position of HRSTDISCIE field.
	UCPD_IMR_HRSTDISCIE_Msk  = 0x10     // Bit mask of HRSTDISCIE field.
	UCPD_IMR_HRSTDISCIE      = 0x10     // Bit HRSTDISCIE.
	UCPD_IMR_HRSTSENTIE_Pos  = 0x5      // Position of HRSTSENTIE field.
	UCPD_IMR_HRSTSENTIE_Msk  = 0x20     // Bit mask of HRSTSENTIE field.
	UCPD_IMR_HRSTSENTIE      = 0x20     // Bit HRSTSENTIE.
	UCPD_IMR_TXUNDIE_Pos     = 0x6      // Position of TXUNDIE field.
	UCPD_IMR_TXUNDIE_Msk     = 0x40     // Bit mask of TXUNDIE field.
	UCPD_IMR_TXUNDIE         = 0x40     // Bit TXUNDIE.
	UCPD_IMR_RXNEIE_Pos      = 0x8      // Position of RXNEIE field.
	UCPD_IMR_RXNEIE_Msk      = 0x100    // Bit mask of RXNEIE field.
	UCPD_IMR_RXNEIE          = 0x100    // Bit RXNEIE.
	UCPD_IMR_RXORDDETIE_Pos  = 0x9      // Position of RXORDDETIE field.
	UCPD_IMR_RXORDDETIE_Msk  = 0x200    // Bit mask of RXORDDETIE field.
	UCPD_IMR_RXORDDETIE      = 0x200    // Bit RXORDDETIE.
	UCPD_IMR_RXHRSTDETIE_Pos = 0xa      // Position of RXHRSTDETIE field.
	UCPD_IMR_RXHRSTDETIE_Msk = 0x400    // Bit mask of RXHRSTDETIE field.
	UCPD_IMR_RXHRSTDETIE     = 0x400    // Bit RXHRSTDETIE.
	UCPD_IMR_RXOVRIE_Pos     = 0xb      // Position of RXOVRIE field.
	UCPD_IMR_RXOVRIE_Msk     = 0x800    // Bit mask of RXOVRIE field.
	UCPD_IMR_RXOVRIE         = 0x800    // Bit RXOVRIE.
	UCPD_IMR_RXMSGENDIE_Pos  = 0xc      // Position of RXMSGENDIE field.
	UCPD_IMR_RXMSGENDIE_Msk  = 0x1000   // Bit mask of RXMSGENDIE field.
	UCPD_IMR_RXMSGENDIE      = 0x1000   // Bit RXMSGENDIE.
	UCPD_IMR_TYPECEVT1IE_Pos = 0xe      // Position of TYPECEVT1IE field.
	UCPD_IMR_TYPECEVT1IE_Msk = 0x4000   // Bit mask of TYPECEVT1IE field.
	UCPD_IMR_TYPECEVT1IE     = 0x4000   // Bit TYPECEVT1IE.
	UCPD_IMR_TYPECEVT2IE_Pos = 0xf      // Position of TYPECEVT2IE field.
	UCPD_IMR_TYPECEVT2IE_Msk = 0x8000   // Bit mask of TYPECEVT2IE field.
	UCPD_IMR_TYPECEVT2IE     = 0x8000   // Bit TYPECEVT2IE.
	UCPD_IMR_FRSEVTIE_Pos    = 0x14     // Position of FRSEVTIE field.
	UCPD_IMR_FRSEVTIE_Msk    = 0x100000 // Bit mask of FRSEVTIE field.
	UCPD_IMR_FRSEVTIE        = 0x100000 // Bit FRSEVTIE.

	// SR: UCPD Status Register
	UCPD_SR_TXIS_Pos             = 0x0      // Position of TXIS field.
	UCPD_SR_TXIS_Msk             = 0x1      // Bit mask of TXIS field.
	UCPD_SR_TXIS                 = 0x1      // Bit TXIS.
	UCPD_SR_TXMSGDISC_Pos        = 0x1      // Position of TXMSGDISC field.
	UCPD_SR_TXMSGDISC_Msk        = 0x2      // Bit mask of TXMSGDISC field.
	UCPD_SR_TXMSGDISC            = 0x2      // Bit TXMSGDISC.
	UCPD_SR_TXMSGSENT_Pos        = 0x2      // Position of TXMSGSENT field.
	UCPD_SR_TXMSGSENT_Msk        = 0x4      // Bit mask of TXMSGSENT field.
	UCPD_SR_TXMSGSENT            = 0x4      // Bit TXMSGSENT.
	UCPD_SR_TXMSGABT_Pos         = 0x3      // Position of TXMSGABT field.
	UCPD_SR_TXMSGABT_Msk         = 0x8      // Bit mask of TXMSGABT field.
	UCPD_SR_TXMSGABT             = 0x8      // Bit TXMSGABT.
	UCPD_SR_HRSTDISC_Pos         = 0x4      // Position of HRSTDISC field.
	UCPD_SR_HRSTDISC_Msk         = 0x10     // Bit mask of HRSTDISC field.
	UCPD_SR_HRSTDISC             = 0x10     // Bit HRSTDISC.
	UCPD_SR_HRSTSENT_Pos         = 0x5      // Position of HRSTSENT field.
	UCPD_SR_HRSTSENT_Msk         = 0x20     // Bit mask of HRSTSENT field.
	UCPD_SR_HRSTSENT             = 0x20     // Bit HRSTSENT.
	UCPD_SR_TXUND_Pos            = 0x6      // Position of TXUND field.
	UCPD_SR_TXUND_Msk            = 0x40     // Bit mask of TXUND field.
	UCPD_SR_TXUND                = 0x40     // Bit TXUND.
	UCPD_SR_RXNE_Pos             = 0x8      // Position of RXNE field.
	UCPD_SR_RXNE_Msk             = 0x100    // Bit mask of RXNE field.
	UCPD_SR_RXNE                 = 0x100    // Bit RXNE.
	UCPD_SR_RXORDDET_Pos         = 0x9      // Position of RXORDDET field.
	UCPD_SR_RXORDDET_Msk         = 0x200    // Bit mask of RXORDDET field.
	UCPD_SR_RXORDDET             = 0x200    // Bit RXORDDET.
	UCPD_SR_RXHRSTDET_Pos        = 0xa      // Position of RXHRSTDET field.
	UCPD_SR_RXHRSTDET_Msk        = 0x400    // Bit mask of RXHRSTDET field.
	UCPD_SR_RXHRSTDET            = 0x400    // Bit RXHRSTDET.
	UCPD_SR_RXOVR_Pos            = 0xb      // Position of RXOVR field.
	UCPD_SR_RXOVR_Msk            = 0x800    // Bit mask of RXOVR field.
	UCPD_SR_RXOVR                = 0x800    // Bit RXOVR.
	UCPD_SR_RXMSGEND_Pos         = 0xc      // Position of RXMSGEND field.
	UCPD_SR_RXMSGEND_Msk         = 0x1000   // Bit mask of RXMSGEND field.
	UCPD_SR_RXMSGEND             = 0x1000   // Bit RXMSGEND.
	UCPD_SR_RXERR_Pos            = 0xd      // Position of RXERR field.
	UCPD_SR_RXERR_Msk            = 0x2000   // Bit mask of RXERR field.
	UCPD_SR_RXERR                = 0x2000   // Bit RXERR.
	UCPD_SR_TYPECEVT1_Pos        = 0xe      // Position of TYPECEVT1 field.
	UCPD_SR_TYPECEVT1_Msk        = 0x4000   // Bit mask of TYPECEVT1 field.
	UCPD_SR_TYPECEVT1            = 0x4000   // Bit TYPECEVT1.
	UCPD_SR_TYPECEVT2_Pos        = 0xf      // Position of TYPECEVT2 field.
	UCPD_SR_TYPECEVT2_Msk        = 0x8000   // Bit mask of TYPECEVT2 field.
	UCPD_SR_TYPECEVT2            = 0x8000   // Bit TYPECEVT2.
	UCPD_SR_TYPEC_VSTATE_CC1_Pos = 0x10     // Position of TYPEC_VSTATE_CC1 field.
	UCPD_SR_TYPEC_VSTATE_CC1_Msk = 0x30000  // Bit mask of TYPEC_VSTATE_CC1 field.
	UCPD_SR_TYPEC_VSTATE_CC2_Pos = 0x12     // Position of TYPEC_VSTATE_CC2 field.
	UCPD_SR_TYPEC_VSTATE_CC2_Msk = 0xc0000  // Bit mask of TYPEC_VSTATE_CC2 field.
	UCPD_SR_FRSEVT_Pos           = 0x14     // Position of FRSEVT field.
	UCPD_SR_FRSEVT_Msk           = 0x100000 // Bit mask of FRSEVT field.
	UCPD_SR_FRSEVT               = 0x100000 // Bit FRSEVT.

	// ICR: UCPD Interrupt Clear Register
	UCPD_ICR_TXMSGDISCCF_Pos = 0x1      // Position of TXMSGDISCCF field.
	UCPD_ICR_TXMSGDISCCF_Msk = 0x2      // Bit mask of TXMSGDISCCF field.
	UCPD_ICR_TXMSGDISCCF     = 0x2      // Bit TXMSGDISCCF.
	UCPD_ICR_TXMSGSENTCF_Pos = 0x2      // Position of TXMSGSENTCF field.
	UCPD_ICR_TXMSGSENTCF_Msk = 0x4      // Bit mask of TXMSGSENTCF field.
	UCPD_ICR_TXMSGSENTCF     = 0x4      // Bit TXMSGSENTCF.
	UCPD_ICR_TXMSGABTCF_Pos  = 0x3      // Position of TXMSGABTCF field.
	UCPD_ICR_TXMSGABTCF_Msk  = 0x8      // Bit mask of TXMSGABTCF field.
	UCPD_ICR_TXMSGABTCF      = 0x8      // Bit TXMSGABTCF.
	UCPD_ICR_HRSTDISCCF_Pos  = 0x4      // Position of HRSTDISCCF field.
	UCPD_ICR_HRSTDISCCF_Msk  = 0x10     // Bit mask of HRSTDISCCF field.
	UCPD_ICR_HRSTDISCCF      = 0x10     // Bit HRSTDISCCF.
	UCPD_ICR_HRSTSENTCF_Pos  = 0x5      // Position of HRSTSENTCF field.
	UCPD_ICR_HRSTSENTCF_Msk  = 0x20     // Bit mask of HRSTSENTCF field.
	UCPD_ICR_HRSTSENTCF      = 0x20     // Bit HRSTSENTCF.
	UCPD_ICR_TXUNDCF_Pos     = 0x6      // Position of TXUNDCF field.
	UCPD_ICR_TXUNDCF_Msk     = 0x40     // Bit mask of TXUNDCF field.
	UCPD_ICR_TXUNDCF         = 0x40     // Bit TXUNDCF.
	UCPD_ICR_RXORDDETCF_Pos  = 0x9      // Position of RXORDDETCF field.
	UCPD_ICR_RXORDDETCF_Msk  = 0x200    // Bit mask of RXORDDETCF field.
	UCPD_ICR_RXORDDETCF      = 0x200    // Bit RXORDDETCF.
	UCPD_ICR_RXHRSTDETCF_Pos = 0xa      // Position of RXHRSTDETCF field.
	UCPD_ICR_RXHRSTDETCF_Msk = 0x400    // Bit mask of RXHRSTDETCF field.
	UCPD_ICR_RXHRSTDETCF     = 0x400    // Bit RXHRSTDETCF.
	UCPD_ICR_RXOVRCF_Pos     = 0xb      // Position of RXOVRCF field.
	UCPD_ICR_RXOVRCF_Msk     = 0x800    // Bit mask of RXOVRCF field.
	UCPD_ICR_RXOVRCF         = 0x800    // Bit RXOVRCF.
	UCPD_ICR_RXMSGENDCF_Pos  = 0xc      // Position of RXMSGENDCF field.
	UCPD_ICR_RXMSGENDCF_Msk  = 0x1000   // Bit mask of RXMSGENDCF field.
	UCPD_ICR_RXMSGENDCF      = 0x1000   // Bit RXMSGENDCF.
	UCPD_ICR_TYPECEVT1CF_Pos = 0xe      // Position of TYPECEVT1CF field.
	UCPD_ICR_TYPECEVT1CF_Msk = 0x4000   // Bit mask of TYPECEVT1CF field.
	UCPD_ICR_TYPECEVT1CF     = 0x4000   // Bit TYPECEVT1CF.
	UCPD_ICR_TYPECEVT2CF_Pos = 0xf      // Position of TYPECEVT2CF field.
	UCPD_ICR_TYPECEVT2CF_Msk = 0x8000   // Bit mask of TYPECEVT2CF field.
	UCPD_ICR_TYPECEVT2CF     = 0x8000   // Bit TYPECEVT2CF.
	UCPD_ICR_FRSEVTCF_Pos    = 0x14     // Position of FRSEVTCF field.
	UCPD_ICR_FRSEVTCF_Msk    = 0x100000 // Bit mask of FRSEVTCF field.
	UCPD_ICR_FRSEVTCF        = 0x100000 // Bit FRSEVTCF.

	// TX_ORDSET: UCPD Tx Ordered Set Type           Register
	UCPD_TX_ORDSET_TXORDSET_Pos = 0x0     // Position of TXORDSET field.
	UCPD_TX_ORDSET_TXORDSET_Msk = 0xfffff // Bit mask of TXORDSET field.

	// TX_PAYSZ: UCPD Tx Paysize Register
	UCPD_TX_PAYSZ_TXPAYSZ_Pos = 0x0   // Position of TXPAYSZ field.
	UCPD_TX_PAYSZ_TXPAYSZ_Msk = 0x3ff // Bit mask of TXPAYSZ field.

	// TXDR: UCPD Tx Data Register
	UCPD_TXDR_TXDATA_Pos = 0x0  // Position of TXDATA field.
	UCPD_TXDR_TXDATA_Msk = 0xff // Bit mask of TXDATA field.

	// RX_ORDSET: UCPD Rx Ordered Set Register
	UCPD_RX_ORDSET_RXORDSET_Pos      = 0x0  // Position of RXORDSET field.
	UCPD_RX_ORDSET_RXORDSET_Msk      = 0x7  // Bit mask of RXORDSET field.
	UCPD_RX_ORDSET_RXSOP3OF4_Pos     = 0x3  // Position of RXSOP3OF4 field.
	UCPD_RX_ORDSET_RXSOP3OF4_Msk     = 0x8  // Bit mask of RXSOP3OF4 field.
	UCPD_RX_ORDSET_RXSOP3OF4         = 0x8  // Bit RXSOP3OF4.
	UCPD_RX_ORDSET_RXSOPKINVALID_Pos = 0x4  // Position of RXSOPKINVALID field.
	UCPD_RX_ORDSET_RXSOPKINVALID_Msk = 0x70 // Bit mask of RXSOPKINVALID field.

	// RX_PAYSZ: UCPD Rx Paysize Register
	UCPD_RX_PAYSZ_RXPAYSZ_Pos = 0x0   // Position of RXPAYSZ field.
	UCPD_RX_PAYSZ_RXPAYSZ_Msk = 0x3ff // Bit mask of RXPAYSZ field.

	// RXDR: UCPD Rx Data Register
	UCPD_RXDR_RXDATA_Pos = 0x0  // Position of RXDATA field.
	UCPD_RXDR_RXDATA_Msk = 0xff // Bit mask of RXDATA field.

	// RX_ORDEXT1: UCPD Rx Ordered Set Extension Register           1
	UCPD_RX_ORDEXT1_RXSOPX1_Pos = 0x0     // Position of RXSOPX1 field.
	UCPD_RX_ORDEXT1_RXSOPX1_Msk = 0xfffff // Bit mask of RXSOPX1 field.

	// RX_ORDEXT2: UCPD Rx Ordered Set Extension Register           2
	UCPD_RX_ORDEXT2_RXSOPX2_Pos = 0x0     // Position of RXSOPX2 field.
	UCPD_RX_ORDEXT2_RXSOPX2_Msk = 0xfffff // Bit mask of RXSOPX2 field.
)

// Bitfields for USB_FS_device: USB_FS_device
const (
	// EP0R: USB endpoint n register
	USB_EP0R_EA_Pos      = 0x0    // Position of EA field.
	USB_EP0R_EA_Msk      = 0xf    // Bit mask of EA field.
	USB_EP0R_STAT_TX_Pos = 0x4    // Position of STAT_TX field.
	USB_EP0R_STAT_TX_Msk = 0x30   // Bit mask of STAT_TX field.
	USB_EP0R_DTOG_TX_Pos = 0x6    // Position of DTOG_TX field.
	USB_EP0R_DTOG_TX_Msk = 0x40   // Bit mask of DTOG_TX field.
	USB_EP0R_DTOG_TX     = 0x40   // Bit DTOG_TX.
	USB_EP0R_CTR_TX_Pos  = 0x7    // Position of CTR_TX field.
	USB_EP0R_CTR_TX_Msk  = 0x80   // Bit mask of CTR_TX field.
	USB_EP0R_CTR_TX      = 0x80   // Bit CTR_TX.
	USB_EP0R_EP_KIND_Pos = 0x8    // Position of EP_KIND field.
	USB_EP0R_EP_KIND_Msk = 0x100  // Bit mask of EP_KIND field.
	USB_EP0R_EP_KIND     = 0x100  // Bit EP_KIND.
	USB_EP0R_EP_TYPE_Pos = 0x9    // Position of EP_TYPE field.
	USB_EP0R_EP_TYPE_Msk = 0x600  // Bit mask of EP_TYPE field.
	USB_EP0R_SETUP_Pos   = 0xb    // Position of SETUP field.
	USB_EP0R_SETUP_Msk   = 0x800  // Bit mask of SETUP field.
	USB_EP0R_SETUP       = 0x800  // Bit SETUP.
	USB_EP0R_STAT_RX_Pos = 0xc    // Position of STAT_RX field.
	USB_EP0R_STAT_RX_Msk = 0x3000 // Bit mask of STAT_RX field.
	USB_EP0R_DTOG_RX_Pos = 0xe    // Position of DTOG_RX field.
	USB_EP0R_DTOG_RX_Msk = 0x4000 // Bit mask of DTOG_RX field.
	USB_EP0R_DTOG_RX     = 0x4000 // Bit DTOG_RX.
	USB_EP0R_CTR_RX_Pos  = 0xf    // Position of CTR_RX field.
	USB_EP0R_CTR_RX_Msk  = 0x8000 // Bit mask of CTR_RX field.
	USB_EP0R_CTR_RX      = 0x8000 // Bit CTR_RX.

	// EP1R: USB endpoint n register
	USB_EP1R_EA_Pos      = 0x0    // Position of EA field.
	USB_EP1R_EA_Msk      = 0xf    // Bit mask of EA field.
	USB_EP1R_STAT_TX_Pos = 0x4    // Position of STAT_TX field.
	USB_EP1R_STAT_TX_Msk = 0x30   // Bit mask of STAT_TX field.
	USB_EP1R_DTOG_TX_Pos = 0x6    // Position of DTOG_TX field.
	USB_EP1R_DTOG_TX_Msk = 0x40   // Bit mask of DTOG_TX field.
	USB_EP1R_DTOG_TX     = 0x40   // Bit DTOG_TX.
	USB_EP1R_CTR_TX_Pos  = 0x7    // Position of CTR_TX field.
	USB_EP1R_CTR_TX_Msk  = 0x80   // Bit mask of CTR_TX field.
	USB_EP1R_CTR_TX      = 0x80   // Bit CTR_TX.
	USB_EP1R_EP_KIND_Pos = 0x8    // Position of EP_KIND field.
	USB_EP1R_EP_KIND_Msk = 0x100  // Bit mask of EP_KIND field.
	USB_EP1R_EP_KIND     = 0x100  // Bit EP_KIND.
	USB_EP1R_EP_TYPE_Pos = 0x9    // Position of EP_TYPE field.
	USB_EP1R_EP_TYPE_Msk = 0x600  // Bit mask of EP_TYPE field.
	USB_EP1R_SETUP_Pos   = 0xb    // Position of SETUP field.
	USB_EP1R_SETUP_Msk   = 0x800  // Bit mask of SETUP field.
	USB_EP1R_SETUP       = 0x800  // Bit SETUP.
	USB_EP1R_STAT_RX_Pos = 0xc    // Position of STAT_RX field.
	USB_EP1R_STAT_RX_Msk = 0x3000 // Bit mask of STAT_RX field.
	USB_EP1R_DTOG_RX_Pos = 0xe    // Position of DTOG_RX field.
	USB_EP1R_DTOG_RX_Msk = 0x4000 // Bit mask of DTOG_RX field.
	USB_EP1R_DTOG_RX     = 0x4000 // Bit DTOG_RX.
	USB_EP1R_CTR_RX_Pos  = 0xf    // Position of CTR_RX field.
	USB_EP1R_CTR_RX_Msk  = 0x8000 // Bit mask of CTR_RX field.
	USB_EP1R_CTR_RX      = 0x8000 // Bit CTR_RX.

	// EP2R: USB endpoint n register
	USB_EP2R_EA_Pos      = 0x0    // Position of EA field.
	USB_EP2R_EA_Msk      = 0xf    // Bit mask of EA field.
	USB_EP2R_STAT_TX_Pos = 0x4    // Position of STAT_TX field.
	USB_EP2R_STAT_TX_Msk = 0x30   // Bit mask of STAT_TX field.
	USB_EP2R_DTOG_TX_Pos = 0x6    // Position of DTOG_TX field.
	USB_EP2R_DTOG_TX_Msk = 0x40   // Bit mask of DTOG_TX field.
	USB_EP2R_DTOG_TX     = 0x40   // Bit DTOG_TX.
	USB_EP2R_CTR_TX_Pos  = 0x7    // Position of CTR_TX field.
	USB_EP2R_CTR_TX_Msk  = 0x80   // Bit mask of CTR_TX field.
	USB_EP2R_CTR_TX      = 0x80   // Bit CTR_TX.
	USB_EP2R_EP_KIND_Pos = 0x8    // Position of EP_KIND field.
	USB_EP2R_EP_KIND_Msk = 0x100  // Bit mask of EP_KIND field.
	USB_EP2R_EP_KIND     = 0x100  // Bit EP_KIND.
	USB_EP2R_EP_TYPE_Pos = 0x9    // Position of EP_TYPE field.
	USB_EP2R_EP_TYPE_Msk = 0x600  // Bit mask of EP_TYPE field.
	USB_EP2R_SETUP_Pos   = 0xb    // Position of SETUP field.
	USB_EP2R_SETUP_Msk   = 0x800  // Bit mask of SETUP field.
	USB_EP2R_SETUP       = 0x800  // Bit SETUP.
	USB_EP2R_STAT_RX_Pos = 0xc    // Position of STAT_RX field.
	USB_EP2R_STAT_RX_Msk = 0x3000 // Bit mask of STAT_RX field.
	USB_EP2R_DTOG_RX_Pos = 0xe    // Position of DTOG_RX field.
	USB_EP2R_DTOG_RX_Msk = 0x4000 // Bit mask of DTOG_RX field.
	USB_EP2R_DTOG_RX     = 0x4000 // Bit DTOG_RX.
	USB_EP2R_CTR_RX_Pos  = 0xf    // Position of CTR_RX field.
	USB_EP2R_CTR_RX_Msk  = 0x8000 // Bit mask of CTR_RX field.
	USB_EP2R_CTR_RX      = 0x8000 // Bit CTR_RX.

	// EP3R: USB endpoint n register
	USB_EP3R_EA_Pos      = 0x0    // Position of EA field.
	USB_EP3R_EA_Msk      = 0xf    // Bit mask of EA field.
	USB_EP3R_STAT_TX_Pos = 0x4    // Position of STAT_TX field.
	USB_EP3R_STAT_TX_Msk = 0x30   // Bit mask of STAT_TX field.
	USB_EP3R_DTOG_TX_Pos = 0x6    // Position of DTOG_TX field.
	USB_EP3R_DTOG_TX_Msk = 0x40   // Bit mask of DTOG_TX field.
	USB_EP3R_DTOG_TX     = 0x40   // Bit DTOG_TX.
	USB_EP3R_CTR_TX_Pos  = 0x7    // Position of CTR_TX field.
	USB_EP3R_CTR_TX_Msk  = 0x80   // Bit mask of CTR_TX field.
	USB_EP3R_CTR_TX      = 0x80   // Bit CTR_TX.
	USB_EP3R_EP_KIND_Pos = 0x8    // Position of EP_KIND field.
	USB_EP3R_EP_KIND_Msk = 0x100  // Bit mask of EP_KIND field.
	USB_EP3R_EP_KIND     = 0x100  // Bit EP_KIND.
	USB_EP3R_EP_TYPE_Pos = 0x9    // Position of EP_TYPE field.
	USB_EP3R_EP_TYPE_Msk = 0x600  // Bit mask of EP_TYPE field.
	USB_EP3R_SETUP_Pos   = 0xb    // Position of SETUP field.
	USB_EP3R_SETUP_Msk   = 0x800  // Bit mask of SETUP field.
	USB_EP3R_SETUP       = 0x800  // Bit SETUP.
	USB_EP3R_STAT_RX_Pos = 0xc    // Position of STAT_RX field.
	USB_EP3R_STAT_RX_Msk = 0x3000 // Bit mask of STAT_RX field.
	USB_EP3R_DTOG_RX_Pos = 0xe    // Position of DTOG_RX field.
	USB_EP3R_DTOG_RX_Msk = 0x4000 // Bit mask of DTOG_RX field.
	USB_EP3R_DTOG_RX     = 0x4000 // Bit DTOG_RX.
	USB_EP3R_CTR_RX_Pos  = 0xf    // Position of CTR_RX field.
	USB_EP3R_CTR_RX_Msk  = 0x8000 // Bit mask of CTR_RX field.
	USB_EP3R_CTR_RX      = 0x8000 // Bit CTR_RX.

	// EP4R: USB endpoint n register
	USB_EP4R_EA_Pos      = 0x0    // Position of EA field.
	USB_EP4R_EA_Msk      = 0xf    // Bit mask of EA field.
	USB_EP4R_STAT_TX_Pos = 0x4    // Position of STAT_TX field.
	USB_EP4R_STAT_TX_Msk = 0x30   // Bit mask of STAT_TX field.
	USB_EP4R_DTOG_TX_Pos = 0x6    // Position of DTOG_TX field.
	USB_EP4R_DTOG_TX_Msk = 0x40   // Bit mask of DTOG_TX field.
	USB_EP4R_DTOG_TX     = 0x40   // Bit DTOG_TX.
	USB_EP4R_CTR_TX_Pos  = 0x7    // Position of CTR_TX field.
	USB_EP4R_CTR_TX_Msk  = 0x80   // Bit mask of CTR_TX field.
	USB_EP4R_CTR_TX      = 0x80   // Bit CTR_TX.
	USB_EP4R_EP_KIND_Pos = 0x8    // Position of EP_KIND field.
	USB_EP4R_EP_KIND_Msk = 0x100  // Bit mask of EP_KIND field.
	USB_EP4R_EP_KIND     = 0x100  // Bit EP_KIND.
	USB_EP4R_EP_TYPE_Pos = 0x9    // Position of EP_TYPE field.
	USB_EP4R_EP_TYPE_Msk = 0x600  // Bit mask of EP_TYPE field.
	USB_EP4R_SETUP_Pos   = 0xb    // Position of SETUP field.
	USB_EP4R_SETUP_Msk   = 0x800  // Bit mask of SETUP field.
	USB_EP4R_SETUP       = 0x800  // Bit SETUP.
	USB_EP4R_STAT_RX_Pos = 0xc    // Position of STAT_RX field.
	USB_EP4R_STAT_RX_Msk = 0x3000 // Bit mask of STAT_RX field.
	USB_EP4R_DTOG_RX_Pos = 0xe    // Position of DTOG_RX field.
	USB_EP4R_DTOG_RX_Msk = 0x4000 // Bit mask of DTOG_RX field.
	USB_EP4R_DTOG_RX     = 0x4000 // Bit DTOG_RX.
	USB_EP4R_CTR_RX_Pos  = 0xf    // Position of CTR_RX field.
	USB_EP4R_CTR_RX_Msk  = 0x8000 // Bit mask of CTR_RX field.
	USB_EP4R_CTR_RX      = 0x8000 // Bit CTR_RX.

	// EP5R: USB endpoint n register
	USB_EP5R_EA_Pos      = 0x0    // Position of EA field.
	USB_EP5R_EA_Msk      = 0xf    // Bit mask of EA field.
	USB_EP5R_STAT_TX_Pos = 0x4    // Position of STAT_TX field.
	USB_EP5R_STAT_TX_Msk = 0x30   // Bit mask of STAT_TX field.
	USB_EP5R_DTOG_TX_Pos = 0x6    // Position of DTOG_TX field.
	USB_EP5R_DTOG_TX_Msk = 0x40   // Bit mask of DTOG_TX field.
	USB_EP5R_DTOG_TX     = 0x40   // Bit DTOG_TX.
	USB_EP5R_CTR_TX_Pos  = 0x7    // Position of CTR_TX field.
	USB_EP5R_CTR_TX_Msk  = 0x80   // Bit mask of CTR_TX field.
	USB_EP5R_CTR_TX      = 0x80   // Bit CTR_TX.
	USB_EP5R_EP_KIND_Pos = 0x8    // Position of EP_KIND field.
	USB_EP5R_EP_KIND_Msk = 0x100  // Bit mask of EP_KIND field.
	USB_EP5R_EP_KIND     = 0x100  // Bit EP_KIND.
	USB_EP5R_EP_TYPE_Pos = 0x9    // Position of EP_TYPE field.
	USB_EP5R_EP_TYPE_Msk = 0x600  // Bit mask of EP_TYPE field.
	USB_EP5R_SETUP_Pos   = 0xb    // Position of SETUP field.
	USB_EP5R_SETUP_Msk   = 0x800  // Bit mask of SETUP field.
	USB_EP5R_SETUP       = 0x800  // Bit SETUP.
	USB_EP5R_STAT_RX_Pos = 0xc    // Position of STAT_RX field.
	USB_EP5R_STAT_RX_Msk = 0x3000 // Bit mask of STAT_RX field.
	USB_EP5R_DTOG_RX_Pos = 0xe    // Position of DTOG_RX field.
	USB_EP5R_DTOG_RX_Msk = 0x4000 // Bit mask of DTOG_RX field.
	USB_EP5R_DTOG_RX     = 0x4000 // Bit DTOG_RX.
	USB_EP5R_CTR_RX_Pos  = 0xf    // Position of CTR_RX field.
	USB_EP5R_CTR_RX_Msk  = 0x8000 // Bit mask of CTR_RX field.
	USB_EP5R_CTR_RX      = 0x8000 // Bit CTR_RX.

	// EP6R: USB endpoint n register
	USB_EP6R_EA_Pos      = 0x0    // Position of EA field.
	USB_EP6R_EA_Msk      = 0xf    // Bit mask of EA field.
	USB_EP6R_STAT_TX_Pos = 0x4    // Position of STAT_TX field.
	USB_EP6R_STAT_TX_Msk = 0x30   // Bit mask of STAT_TX field.
	USB_EP6R_DTOG_TX_Pos = 0x6    // Position of DTOG_TX field.
	USB_EP6R_DTOG_TX_Msk = 0x40   // Bit mask of DTOG_TX field.
	USB_EP6R_DTOG_TX     = 0x40   // Bit DTOG_TX.
	USB_EP6R_CTR_TX_Pos  = 0x7    // Position of CTR_TX field.
	USB_EP6R_CTR_TX_Msk  = 0x80   // Bit mask of CTR_TX field.
	USB_EP6R_CTR_TX      = 0x80   // Bit CTR_TX.
	USB_EP6R_EP_KIND_Pos = 0x8    // Position of EP_KIND field.
	USB_EP6R_EP_KIND_Msk = 0x100  // Bit mask of EP_KIND field.
	USB_EP6R_EP_KIND     = 0x100  // Bit EP_KIND.
	USB_EP6R_EP_TYPE_Pos = 0x9    // Position of EP_TYPE field.
	USB_EP6R_EP_TYPE_Msk = 0x600  // Bit mask of EP_TYPE field.
	USB_EP6R_SETUP_Pos   = 0xb    // Position of SETUP field.
	USB_EP6R_SETUP_Msk   = 0x800  // Bit mask of SETUP field.
	USB_EP6R_SETUP       = 0x800  // Bit SETUP.
	USB_EP6R_STAT_RX_Pos = 0xc    // Position of STAT_RX field.
	USB_EP6R_STAT_RX_Msk = 0x3000 // Bit mask of STAT_RX field.
	USB_EP6R_DTOG_RX_Pos = 0xe    // Position of DTOG_RX field.
	USB_EP6R_DTOG_RX_Msk = 0x4000 // Bit mask of DTOG_RX field.
	USB_EP6R_DTOG_RX     = 0x4000 // Bit DTOG_RX.
	USB_EP6R_CTR_RX_Pos  = 0xf    // Position of CTR_RX field.
	USB_EP6R_CTR_RX_Msk  = 0x8000 // Bit mask of CTR_RX field.
	USB_EP6R_CTR_RX      = 0x8000 // Bit CTR_RX.

	// EP7R: USB endpoint n register
	USB_EP7R_EA_Pos      = 0x0    // Position of EA field.
	USB_EP7R_EA_Msk      = 0xf    // Bit mask of EA field.
	USB_EP7R_STAT_TX_Pos = 0x4    // Position of STAT_TX field.
	USB_EP7R_STAT_TX_Msk = 0x30   // Bit mask of STAT_TX field.
	USB_EP7R_DTOG_TX_Pos = 0x6    // Position of DTOG_TX field.
	USB_EP7R_DTOG_TX_Msk = 0x40   // Bit mask of DTOG_TX field.
	USB_EP7R_DTOG_TX     = 0x40   // Bit DTOG_TX.
	USB_EP7R_CTR_TX_Pos  = 0x7    // Position of CTR_TX field.
	USB_EP7R_CTR_TX_Msk  = 0x80   // Bit mask of CTR_TX field.
	USB_EP7R_CTR_TX      = 0x80   // Bit CTR_TX.
	USB_EP7R_EP_KIND_Pos = 0x8    // Position of EP_KIND field.
	USB_EP7R_EP_KIND_Msk = 0x100  // Bit mask of EP_KIND field.
	USB_EP7R_EP_KIND     = 0x100  // Bit EP_KIND.
	USB_EP7R_EP_TYPE_Pos = 0x9    // Position of EP_TYPE field.
	USB_EP7R_EP_TYPE_Msk = 0x600  // Bit mask of EP_TYPE field.
	USB_EP7R_SETUP_Pos   = 0xb    // Position of SETUP field.
	USB_EP7R_SETUP_Msk   = 0x800  // Bit mask of SETUP field.
	USB_EP7R_SETUP       = 0x800  // Bit SETUP.
	USB_EP7R_STAT_RX_Pos = 0xc    // Position of STAT_RX field.
	USB_EP7R_STAT_RX_Msk = 0x3000 // Bit mask of STAT_RX field.
	USB_EP7R_DTOG_RX_Pos = 0xe    // Position of DTOG_RX field.
	USB_EP7R_DTOG_RX_Msk = 0x4000 // Bit mask of DTOG_RX field.
	USB_EP7R_DTOG_RX     = 0x4000 // Bit DTOG_RX.
	USB_EP7R_CTR_RX_Pos  = 0xf    // Position of CTR_RX field.
	USB_EP7R_CTR_RX_Msk  = 0x8000 // Bit mask of CTR_RX field.
	USB_EP7R_CTR_RX      = 0x8000 // Bit CTR_RX.

	// CNTR: USB control register
	USB_CNTR_FRES_Pos     = 0x0    // Position of FRES field.
	USB_CNTR_FRES_Msk     = 0x1    // Bit mask of FRES field.
	USB_CNTR_FRES         = 0x1    // Bit FRES.
	USB_CNTR_PDWN_Pos     = 0x1    // Position of PDWN field.
	USB_CNTR_PDWN_Msk     = 0x2    // Bit mask of PDWN field.
	USB_CNTR_PDWN         = 0x2    // Bit PDWN.
	USB_CNTR_LP_MODE_Pos  = 0x2    // Position of LP_MODE field.
	USB_CNTR_LP_MODE_Msk  = 0x4    // Bit mask of LP_MODE field.
	USB_CNTR_LP_MODE      = 0x4    // Bit LP_MODE.
	USB_CNTR_FSUSP_Pos    = 0x3    // Position of FSUSP field.
	USB_CNTR_FSUSP_Msk    = 0x8    // Bit mask of FSUSP field.
	USB_CNTR_FSUSP        = 0x8    // Bit FSUSP.
	USB_CNTR_RESUME_Pos   = 0x4    // Position of RESUME field.
	USB_CNTR_RESUME_Msk   = 0x10   // Bit mask of RESUME field.
	USB_CNTR_RESUME       = 0x10   // Bit RESUME.
	USB_CNTR_L1RESUME_Pos = 0x5    // Position of L1RESUME field.
	USB_CNTR_L1RESUME_Msk = 0x20   // Bit mask of L1RESUME field.
	USB_CNTR_L1RESUME     = 0x20   // Bit L1RESUME.
	USB_CNTR_L1REQM_Pos   = 0x7    // Position of L1REQM field.
	USB_CNTR_L1REQM_Msk   = 0x80   // Bit mask of L1REQM field.
	USB_CNTR_L1REQM       = 0x80   // Bit L1REQM.
	USB_CNTR_ESOFM_Pos    = 0x8    // Position of ESOFM field.
	USB_CNTR_ESOFM_Msk    = 0x100  // Bit mask of ESOFM field.
	USB_CNTR_ESOFM        = 0x100  // Bit ESOFM.
	USB_CNTR_SOFM_Pos     = 0x9    // Position of SOFM field.
	USB_CNTR_SOFM_Msk     = 0x200  // Bit mask of SOFM field.
	USB_CNTR_SOFM         = 0x200  // Bit SOFM.
	USB_CNTR_RESETM_Pos   = 0xa    // Position of RESETM field.
	USB_CNTR_RESETM_Msk   = 0x400  // Bit mask of RESETM field.
	USB_CNTR_RESETM       = 0x400  // Bit RESETM.
	USB_CNTR_SUSPM_Pos    = 0xb    // Position of SUSPM field.
	USB_CNTR_SUSPM_Msk    = 0x800  // Bit mask of SUSPM field.
	USB_CNTR_SUSPM        = 0x800  // Bit SUSPM.
	USB_CNTR_WKUPM_Pos    = 0xc    // Position of WKUPM field.
	USB_CNTR_WKUPM_Msk    = 0x1000 // Bit mask of WKUPM field.
	USB_CNTR_WKUPM        = 0x1000 // Bit WKUPM.
	USB_CNTR_ERRM_Pos     = 0xd    // Position of ERRM field.
	USB_CNTR_ERRM_Msk     = 0x2000 // Bit mask of ERRM field.
	USB_CNTR_ERRM         = 0x2000 // Bit ERRM.
	USB_CNTR_PMAOVRM_Pos  = 0xe    // Position of PMAOVRM field.
	USB_CNTR_PMAOVRM_Msk  = 0x4000 // Bit mask of PMAOVRM field.
	USB_CNTR_PMAOVRM      = 0x4000 // Bit PMAOVRM.
	USB_CNTR_CTRM_Pos     = 0xf    // Position of CTRM field.
	USB_CNTR_CTRM_Msk     = 0x8000 // Bit mask of CTRM field.
	USB_CNTR_CTRM         = 0x8000 // Bit CTRM.

	// ISTR: USB interrupt status register
	USB_ISTR_EP_ID_Pos  = 0x0    // Position of EP_ID field.
	USB_ISTR_EP_ID_Msk  = 0xf    // Bit mask of EP_ID field.
	USB_ISTR_DIR_Pos    = 0x4    // Position of DIR field.
	USB_ISTR_DIR_Msk    = 0x10   // Bit mask of DIR field.
	USB_ISTR_DIR        = 0x10   // Bit DIR.
	USB_ISTR_L1REQ_Pos  = 0x7    // Position of L1REQ field.
	USB_ISTR_L1REQ_Msk  = 0x80   // Bit mask of L1REQ field.
	USB_ISTR_L1REQ      = 0x80   // Bit L1REQ.
	USB_ISTR_ESOF_Pos   = 0x8    // Position of ESOF field.
	USB_ISTR_ESOF_Msk   = 0x100  // Bit mask of ESOF field.
	USB_ISTR_ESOF       = 0x100  // Bit ESOF.
	USB_ISTR_SOF_Pos    = 0x9    // Position of SOF field.
	USB_ISTR_SOF_Msk    = 0x200  // Bit mask of SOF field.
	USB_ISTR_SOF        = 0x200  // Bit SOF.
	USB_ISTR_RESET_Pos  = 0xa    // Position of RESET field.
	USB_ISTR_RESET_Msk  = 0x400  // Bit mask of RESET field.
	USB_ISTR_RESET      = 0x400  // Bit RESET.
	USB_ISTR_SUSP_Pos   = 0xb    // Position of SUSP field.
	USB_ISTR_SUSP_Msk   = 0x800  // Bit mask of SUSP field.
	USB_ISTR_SUSP       = 0x800  // Bit SUSP.
	USB_ISTR_WKUP_Pos   = 0xc    // Position of WKUP field.
	USB_ISTR_WKUP_Msk   = 0x1000 // Bit mask of WKUP field.
	USB_ISTR_WKUP       = 0x1000 // Bit WKUP.
	USB_ISTR_ERR_Pos    = 0xd    // Position of ERR field.
	USB_ISTR_ERR_Msk    = 0x2000 // Bit mask of ERR field.
	USB_ISTR_ERR        = 0x2000 // Bit ERR.
	USB_ISTR_PMAOVR_Pos = 0xe    // Position of PMAOVR field.
	USB_ISTR_PMAOVR_Msk = 0x4000 // Bit mask of PMAOVR field.
	USB_ISTR_PMAOVR     = 0x4000 // Bit PMAOVR.
	USB_ISTR_CTR_Pos    = 0xf    // Position of CTR field.
	USB_ISTR_CTR_Msk    = 0x8000 // Bit mask of CTR field.
	USB_ISTR_CTR        = 0x8000 // Bit CTR.

	// FNR: USB frame number register
	USB_FNR_FN_Pos   = 0x0    // Position of FN field.
	USB_FNR_FN_Msk   = 0x7ff  // Bit mask of FN field.
	USB_FNR_LSOF_Pos = 0xb    // Position of LSOF field.
	USB_FNR_LSOF_Msk = 0x1800 // Bit mask of LSOF field.
	USB_FNR_LCK_Pos  = 0xd    // Position of LCK field.
	USB_FNR_LCK_Msk  = 0x2000 // Bit mask of LCK field.
	USB_FNR_LCK      = 0x2000 // Bit LCK.
	USB_FNR_RXDM_Pos = 0xe    // Position of RXDM field.
	USB_FNR_RXDM_Msk = 0x4000 // Bit mask of RXDM field.
	USB_FNR_RXDM     = 0x4000 // Bit RXDM.
	USB_FNR_RXDP_Pos = 0xf    // Position of RXDP field.
	USB_FNR_RXDP_Msk = 0x8000 // Bit mask of RXDP field.
	USB_FNR_RXDP     = 0x8000 // Bit RXDP.

	// DADDR: USB device address
	USB_DADDR_ADD_Pos = 0x0  // Position of ADD field.
	USB_DADDR_ADD_Msk = 0x7f // Bit mask of ADD field.
	USB_DADDR_EF_Pos  = 0x7  // Position of EF field.
	USB_DADDR_EF_Msk  = 0x80 // Bit mask of EF field.
	USB_DADDR_EF      = 0x80 // Bit EF.

	// BTABLE: Buffer table address
	USB_BTABLE_BTABLE_Pos = 0x3    // Position of BTABLE field.
	USB_BTABLE_BTABLE_Msk = 0xfff8 // Bit mask of BTABLE field.
)

// Bitfields for CRS: CRS
const (
	// CR: CRS control register
	CRS_CR_SYNCOKIE_Pos   = 0x0    // Position of SYNCOKIE field.
	CRS_CR_SYNCOKIE_Msk   = 0x1    // Bit mask of SYNCOKIE field.
	CRS_CR_SYNCOKIE       = 0x1    // Bit SYNCOKIE.
	CRS_CR_SYNCWARNIE_Pos = 0x1    // Position of SYNCWARNIE field.
	CRS_CR_SYNCWARNIE_Msk = 0x2    // Bit mask of SYNCWARNIE field.
	CRS_CR_SYNCWARNIE     = 0x2    // Bit SYNCWARNIE.
	CRS_CR_ERRIE_Pos      = 0x2    // Position of ERRIE field.
	CRS_CR_ERRIE_Msk      = 0x4    // Bit mask of ERRIE field.
	CRS_CR_ERRIE          = 0x4    // Bit ERRIE.
	CRS_CR_ESYNCIE_Pos    = 0x3    // Position of ESYNCIE field.
	CRS_CR_ESYNCIE_Msk    = 0x8    // Bit mask of ESYNCIE field.
	CRS_CR_ESYNCIE        = 0x8    // Bit ESYNCIE.
	CRS_CR_CEN_Pos        = 0x5    // Position of CEN field.
	CRS_CR_CEN_Msk        = 0x20   // Bit mask of CEN field.
	CRS_CR_CEN            = 0x20   // Bit CEN.
	CRS_CR_AUTOTRIMEN_Pos = 0x6    // Position of AUTOTRIMEN field.
	CRS_CR_AUTOTRIMEN_Msk = 0x40   // Bit mask of AUTOTRIMEN field.
	CRS_CR_AUTOTRIMEN     = 0x40   // Bit AUTOTRIMEN.
	CRS_CR_SWSYNC_Pos     = 0x7    // Position of SWSYNC field.
	CRS_CR_SWSYNC_Msk     = 0x80   // Bit mask of SWSYNC field.
	CRS_CR_SWSYNC         = 0x80   // Bit SWSYNC.
	CRS_CR_TRIM_Pos       = 0x8    // Position of TRIM field.
	CRS_CR_TRIM_Msk       = 0x7f00 // Bit mask of TRIM field.

	// CFGR: This register can be written only when the           frequency error counter is disabled (CEN bit is cleared           in CRS_CR). When the counter is enabled, this register is           write-protected.
	CRS_CFGR_RELOAD_Pos  = 0x0        // Position of RELOAD field.
	CRS_CFGR_RELOAD_Msk  = 0xffff     // Bit mask of RELOAD field.
	CRS_CFGR_FELIM_Pos   = 0x10       // Position of FELIM field.
	CRS_CFGR_FELIM_Msk   = 0xff0000   // Bit mask of FELIM field.
	CRS_CFGR_SYNCDIV_Pos = 0x18       // Position of SYNCDIV field.
	CRS_CFGR_SYNCDIV_Msk = 0x7000000  // Bit mask of SYNCDIV field.
	CRS_CFGR_SYNCSRC_Pos = 0x1c       // Position of SYNCSRC field.
	CRS_CFGR_SYNCSRC_Msk = 0x30000000 // Bit mask of SYNCSRC field.
	CRS_CFGR_SYNCPOL_Pos = 0x1f       // Position of SYNCPOL field.
	CRS_CFGR_SYNCPOL_Msk = 0x80000000 // Bit mask of SYNCPOL field.
	CRS_CFGR_SYNCPOL     = 0x80000000 // Bit SYNCPOL.

	// ISR: CRS interrupt and status    register
	CRS_ISR_SYNCOKF_Pos   = 0x0        // Position of SYNCOKF field.
	CRS_ISR_SYNCOKF_Msk   = 0x1        // Bit mask of SYNCOKF field.
	CRS_ISR_SYNCOKF       = 0x1        // Bit SYNCOKF.
	CRS_ISR_SYNCWARNF_Pos = 0x1        // Position of SYNCWARNF field.
	CRS_ISR_SYNCWARNF_Msk = 0x2        // Bit mask of SYNCWARNF field.
	CRS_ISR_SYNCWARNF     = 0x2        // Bit SYNCWARNF.
	CRS_ISR_ERRF_Pos      = 0x2        // Position of ERRF field.
	CRS_ISR_ERRF_Msk      = 0x4        // Bit mask of ERRF field.
	CRS_ISR_ERRF          = 0x4        // Bit ERRF.
	CRS_ISR_ESYNCF_Pos    = 0x3        // Position of ESYNCF field.
	CRS_ISR_ESYNCF_Msk    = 0x8        // Bit mask of ESYNCF field.
	CRS_ISR_ESYNCF        = 0x8        // Bit ESYNCF.
	CRS_ISR_SYNCERR_Pos   = 0x8        // Position of SYNCERR field.
	CRS_ISR_SYNCERR_Msk   = 0x100      // Bit mask of SYNCERR field.
	CRS_ISR_SYNCERR       = 0x100      // Bit SYNCERR.
	CRS_ISR_SYNCMISS_Pos  = 0x9        // Position of SYNCMISS field.
	CRS_ISR_SYNCMISS_Msk  = 0x200      // Bit mask of SYNCMISS field.
	CRS_ISR_SYNCMISS      = 0x200      // Bit SYNCMISS.
	CRS_ISR_TRIMOVF_Pos   = 0xa        // Position of TRIMOVF field.
	CRS_ISR_TRIMOVF_Msk   = 0x400      // Bit mask of TRIMOVF field.
	CRS_ISR_TRIMOVF       = 0x400      // Bit TRIMOVF.
	CRS_ISR_FEDIR_Pos     = 0xf        // Position of FEDIR field.
	CRS_ISR_FEDIR_Msk     = 0x8000     // Bit mask of FEDIR field.
	CRS_ISR_FEDIR         = 0x8000     // Bit FEDIR.
	CRS_ISR_FECAP_Pos     = 0x10       // Position of FECAP field.
	CRS_ISR_FECAP_Msk     = 0xffff0000 // Bit mask of FECAP field.

	// ICR: CRS interrupt flag clear register
	CRS_ICR_SYNCOKC_Pos   = 0x0 // Position of SYNCOKC field.
	CRS_ICR_SYNCOKC_Msk   = 0x1 // Bit mask of SYNCOKC field.
	CRS_ICR_SYNCOKC       = 0x1 // Bit SYNCOKC.
	CRS_ICR_SYNCWARNC_Pos = 0x1 // Position of SYNCWARNC field.
	CRS_ICR_SYNCWARNC_Msk = 0x2 // Bit mask of SYNCWARNC field.
	CRS_ICR_SYNCWARNC     = 0x2 // Bit SYNCWARNC.
	CRS_ICR_ERRC_Pos      = 0x2 // Position of ERRC field.
	CRS_ICR_ERRC_Msk      = 0x4 // Bit mask of ERRC field.
	CRS_ICR_ERRC          = 0x4 // Bit ERRC.
	CRS_ICR_ESYNCC_Pos    = 0x3 // Position of ESYNCC field.
	CRS_ICR_ESYNCC_Msk    = 0x8 // Bit mask of ESYNCC field.
	CRS_ICR_ESYNCC        = 0x8 // Bit ESYNCC.
)
