// Automatically generated file. DO NOT EDIT.
// Generated by gen-device-svd.go from ATSAMD51N20A.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/Atmel

// +build sam,atsamd51n20a

// Microchip ATSAMD51N20A Microcontroller
//

package sam

import (
	"runtime/interrupt"
	"runtime/volatile"
	"unsafe"
)

// Some information about this device.
const (
	DEVICE = "ATSAMD51N20A"
)

// Interrupt numbers.
const (
	IRQ_PM            = 0   // Power Manager
	IRQ_MCLK          = 1   // Main Clock
	IRQ_OSCCTRL_XOSC0 = 2   // Oscillators Control
	IRQ_OSCCTRL_XOSC1 = 3   // Oscillators Control
	IRQ_OSCCTRL_DFLL  = 4   // Oscillators Control
	IRQ_OSCCTRL_DPLL0 = 5   // Oscillators Control
	IRQ_OSCCTRL_DPLL1 = 6   // Oscillators Control
	IRQ_OSC32KCTRL    = 7   // 32kHz Oscillators Control
	IRQ_SUPC_OTHER    = 8   // Supply Controller
	IRQ_SUPC_BODDET   = 9   // Supply Controller
	IRQ_WDT           = 10  // Watchdog Timer
	IRQ_RTC           = 11  // Real-Time Counter
	IRQ_EIC_EXTINT_0  = 12  // External Interrupt Controller
	IRQ_EIC_EXTINT_1  = 13  // External Interrupt Controller
	IRQ_EIC_EXTINT_2  = 14  // External Interrupt Controller
	IRQ_EIC_EXTINT_3  = 15  // External Interrupt Controller
	IRQ_EIC_EXTINT_4  = 16  // External Interrupt Controller
	IRQ_EIC_EXTINT_5  = 17  // External Interrupt Controller
	IRQ_EIC_EXTINT_6  = 18  // External Interrupt Controller
	IRQ_EIC_EXTINT_7  = 19  // External Interrupt Controller
	IRQ_EIC_EXTINT_8  = 20  // External Interrupt Controller
	IRQ_EIC_EXTINT_9  = 21  // External Interrupt Controller
	IRQ_EIC_EXTINT_10 = 22  // External Interrupt Controller
	IRQ_EIC_EXTINT_11 = 23  // External Interrupt Controller
	IRQ_EIC_EXTINT_12 = 24  // External Interrupt Controller
	IRQ_EIC_EXTINT_13 = 25  // External Interrupt Controller
	IRQ_EIC_EXTINT_14 = 26  // External Interrupt Controller
	IRQ_EIC_EXTINT_15 = 27  // External Interrupt Controller
	IRQ_FREQM         = 28  // Frequency Meter
	IRQ_NVMCTRL_0     = 29  // Non-Volatile Memory Controller
	IRQ_NVMCTRL_1     = 30  // Non-Volatile Memory Controller
	IRQ_DMAC_0        = 31  // Direct Memory Access Controller
	IRQ_DMAC_1        = 32  // Direct Memory Access Controller
	IRQ_DMAC_2        = 33  // Direct Memory Access Controller
	IRQ_DMAC_3        = 34  // Direct Memory Access Controller
	IRQ_DMAC_OTHER    = 35  // Direct Memory Access Controller
	IRQ_EVSYS_0       = 36  // Event System Interface
	IRQ_EVSYS_1       = 37  // Event System Interface
	IRQ_EVSYS_2       = 38  // Event System Interface
	IRQ_EVSYS_3       = 39  // Event System Interface
	IRQ_EVSYS_OTHER   = 40  // Event System Interface
	IRQ_PAC           = 41  // Peripheral Access Controller
	IRQ_RAMECC        = 45  // RAM ECC
	IRQ_SERCOM0_0     = 46  // Serial Communication Interface
	IRQ_SERCOM0_1     = 47  // Serial Communication Interface
	IRQ_SERCOM0_2     = 48  // Serial Communication Interface
	IRQ_SERCOM0_OTHER = 49  // Serial Communication Interface
	IRQ_SERCOM1_0     = 50  //
	IRQ_SERCOM1_1     = 51  //
	IRQ_SERCOM1_2     = 52  //
	IRQ_SERCOM1_OTHER = 53  //
	IRQ_SERCOM2_0     = 54  //
	IRQ_SERCOM2_1     = 55  //
	IRQ_SERCOM2_2     = 56  //
	IRQ_SERCOM2_OTHER = 57  //
	IRQ_SERCOM3_0     = 58  //
	IRQ_SERCOM3_1     = 59  //
	IRQ_SERCOM3_2     = 60  //
	IRQ_SERCOM3_OTHER = 61  //
	IRQ_SERCOM4_0     = 62  //
	IRQ_SERCOM4_1     = 63  //
	IRQ_SERCOM4_2     = 64  //
	IRQ_SERCOM4_OTHER = 65  //
	IRQ_SERCOM5_0     = 66  //
	IRQ_SERCOM5_1     = 67  //
	IRQ_SERCOM5_2     = 68  //
	IRQ_SERCOM5_OTHER = 69  //
	IRQ_SERCOM6_0     = 70  //
	IRQ_SERCOM6_1     = 71  //
	IRQ_SERCOM6_2     = 72  //
	IRQ_SERCOM6_OTHER = 73  //
	IRQ_SERCOM7_0     = 74  //
	IRQ_SERCOM7_1     = 75  //
	IRQ_SERCOM7_2     = 76  //
	IRQ_SERCOM7_OTHER = 77  //
	IRQ_USB_OTHER     = 80  // Universal Serial Bus
	IRQ_USB_SOF_HSOF  = 81  // Universal Serial Bus
	IRQ_USB_TRCPT0    = 82  // Universal Serial Bus
	IRQ_USB_TRCPT1    = 83  // Universal Serial Bus
	IRQ_TCC0_OTHER    = 85  // Timer Counter Control
	IRQ_TCC0_MC0      = 86  // Timer Counter Control
	IRQ_TCC0_MC1      = 87  // Timer Counter Control
	IRQ_TCC0_MC2      = 88  // Timer Counter Control
	IRQ_TCC0_MC3      = 89  // Timer Counter Control
	IRQ_TCC0_MC4      = 90  // Timer Counter Control
	IRQ_TCC0_MC5      = 91  // Timer Counter Control
	IRQ_TCC1_OTHER    = 92  //
	IRQ_TCC1_MC0      = 93  //
	IRQ_TCC1_MC1      = 94  //
	IRQ_TCC1_MC2      = 95  //
	IRQ_TCC1_MC3      = 96  //
	IRQ_TCC2_OTHER    = 97  //
	IRQ_TCC2_MC0      = 98  //
	IRQ_TCC2_MC1      = 99  //
	IRQ_TCC2_MC2      = 100 //
	IRQ_TCC3_OTHER    = 101 //
	IRQ_TCC3_MC0      = 102 //
	IRQ_TCC3_MC1      = 103 //
	IRQ_TCC4_OTHER    = 104 //
	IRQ_TCC4_MC0      = 105 //
	IRQ_TCC4_MC1      = 106 //
	IRQ_TC0           = 107 // Basic Timer Counter
	IRQ_TC1           = 108 //
	IRQ_TC2           = 109 //
	IRQ_TC3           = 110 //
	IRQ_TC4           = 111 //
	IRQ_TC5           = 112 //
	IRQ_TC6           = 113 //
	IRQ_TC7           = 114 //
	IRQ_PDEC_OTHER    = 115 // Quadrature Decodeur
	IRQ_PDEC_MC0      = 116 // Quadrature Decodeur
	IRQ_PDEC_MC1      = 117 // Quadrature Decodeur
	IRQ_ADC0_OTHER    = 118 // Analog Digital Converter
	IRQ_ADC0_RESRDY   = 119 // Analog Digital Converter
	IRQ_ADC1_OTHER    = 120 //
	IRQ_ADC1_RESRDY   = 121 //
	IRQ_AC            = 122 // Analog Comparators
	IRQ_DAC_OTHER     = 123 // Digital-to-Analog Converter
	IRQ_DAC_EMPTY_0   = 124 // Digital-to-Analog Converter
	IRQ_DAC_EMPTY_1   = 125 // Digital-to-Analog Converter
	IRQ_DAC_RESRDY_0  = 126 // Digital-to-Analog Converter
	IRQ_DAC_RESRDY_1  = 127 // Digital-to-Analog Converter
	IRQ_I2S           = 128 // Inter-IC Sound Interface
	IRQ_PCC           = 129 // Parallel Capture Controller
	IRQ_AES           = 130 // Advanced Encryption Standard
	IRQ_TRNG          = 131 // True Random Generator
	IRQ_ICM           = 132 // Integrity Check Monitor
	IRQ_QSPI          = 134 // Quad SPI interface
	IRQ_SDHC0         = 135 // SD/MMC Host Controller
	IRQ_SDHC1         = 136 //
	IRQ_max           = 136 // Highest interrupt number on this device.
)

// Map interrupt numbers to function names.
// These aren't real calls, they're removed by the compiler.
var (
	_ = interrupt.Register(IRQ_PM, "PM_IRQHandler")
	_ = interrupt.Register(IRQ_MCLK, "MCLK_IRQHandler")
	_ = interrupt.Register(IRQ_OSCCTRL_XOSC0, "OSCCTRL_XOSC0_IRQHandler")
	_ = interrupt.Register(IRQ_OSCCTRL_XOSC1, "OSCCTRL_XOSC1_IRQHandler")
	_ = interrupt.Register(IRQ_OSCCTRL_DFLL, "OSCCTRL_DFLL_IRQHandler")
	_ = interrupt.Register(IRQ_OSCCTRL_DPLL0, "OSCCTRL_DPLL0_IRQHandler")
	_ = interrupt.Register(IRQ_OSCCTRL_DPLL1, "OSCCTRL_DPLL1_IRQHandler")
	_ = interrupt.Register(IRQ_OSC32KCTRL, "OSC32KCTRL_IRQHandler")
	_ = interrupt.Register(IRQ_SUPC_OTHER, "SUPC_OTHER_IRQHandler")
	_ = interrupt.Register(IRQ_SUPC_BODDET, "SUPC_BODDET_IRQHandler")
	_ = interrupt.Register(IRQ_WDT, "WDT_IRQHandler")
	_ = interrupt.Register(IRQ_RTC, "RTC_IRQHandler")
	_ = interrupt.Register(IRQ_EIC_EXTINT_0, "EIC_EXTINT_0_IRQHandler")
	_ = interrupt.Register(IRQ_EIC_EXTINT_1, "EIC_EXTINT_1_IRQHandler")
	_ = interrupt.Register(IRQ_EIC_EXTINT_2, "EIC_EXTINT_2_IRQHandler")
	_ = interrupt.Register(IRQ_EIC_EXTINT_3, "EIC_EXTINT_3_IRQHandler")
	_ = interrupt.Register(IRQ_EIC_EXTINT_4, "EIC_EXTINT_4_IRQHandler")
	_ = interrupt.Register(IRQ_EIC_EXTINT_5, "EIC_EXTINT_5_IRQHandler")
	_ = interrupt.Register(IRQ_EIC_EXTINT_6, "EIC_EXTINT_6_IRQHandler")
	_ = interrupt.Register(IRQ_EIC_EXTINT_7, "EIC_EXTINT_7_IRQHandler")
	_ = interrupt.Register(IRQ_EIC_EXTINT_8, "EIC_EXTINT_8_IRQHandler")
	_ = interrupt.Register(IRQ_EIC_EXTINT_9, "EIC_EXTINT_9_IRQHandler")
	_ = interrupt.Register(IRQ_EIC_EXTINT_10, "EIC_EXTINT_10_IRQHandler")
	_ = interrupt.Register(IRQ_EIC_EXTINT_11, "EIC_EXTINT_11_IRQHandler")
	_ = interrupt.Register(IRQ_EIC_EXTINT_12, "EIC_EXTINT_12_IRQHandler")
	_ = interrupt.Register(IRQ_EIC_EXTINT_13, "EIC_EXTINT_13_IRQHandler")
	_ = interrupt.Register(IRQ_EIC_EXTINT_14, "EIC_EXTINT_14_IRQHandler")
	_ = interrupt.Register(IRQ_EIC_EXTINT_15, "EIC_EXTINT_15_IRQHandler")
	_ = interrupt.Register(IRQ_FREQM, "FREQM_IRQHandler")
	_ = interrupt.Register(IRQ_NVMCTRL_0, "NVMCTRL_0_IRQHandler")
	_ = interrupt.Register(IRQ_NVMCTRL_1, "NVMCTRL_1_IRQHandler")
	_ = interrupt.Register(IRQ_DMAC_0, "DMAC_0_IRQHandler")
	_ = interrupt.Register(IRQ_DMAC_1, "DMAC_1_IRQHandler")
	_ = interrupt.Register(IRQ_DMAC_2, "DMAC_2_IRQHandler")
	_ = interrupt.Register(IRQ_DMAC_3, "DMAC_3_IRQHandler")
	_ = interrupt.Register(IRQ_DMAC_OTHER, "DMAC_OTHER_IRQHandler")
	_ = interrupt.Register(IRQ_EVSYS_0, "EVSYS_0_IRQHandler")
	_ = interrupt.Register(IRQ_EVSYS_1, "EVSYS_1_IRQHandler")
	_ = interrupt.Register(IRQ_EVSYS_2, "EVSYS_2_IRQHandler")
	_ = interrupt.Register(IRQ_EVSYS_3, "EVSYS_3_IRQHandler")
	_ = interrupt.Register(IRQ_EVSYS_OTHER, "EVSYS_OTHER_IRQHandler")
	_ = interrupt.Register(IRQ_PAC, "PAC_IRQHandler")
	_ = interrupt.Register(IRQ_RAMECC, "RAMECC_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM0_0, "SERCOM0_0_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM0_1, "SERCOM0_1_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM0_2, "SERCOM0_2_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM0_OTHER, "SERCOM0_OTHER_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM1_0, "SERCOM1_0_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM1_1, "SERCOM1_1_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM1_2, "SERCOM1_2_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM1_OTHER, "SERCOM1_OTHER_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM2_0, "SERCOM2_0_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM2_1, "SERCOM2_1_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM2_2, "SERCOM2_2_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM2_OTHER, "SERCOM2_OTHER_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM3_0, "SERCOM3_0_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM3_1, "SERCOM3_1_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM3_2, "SERCOM3_2_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM3_OTHER, "SERCOM3_OTHER_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM4_0, "SERCOM4_0_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM4_1, "SERCOM4_1_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM4_2, "SERCOM4_2_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM4_OTHER, "SERCOM4_OTHER_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM5_0, "SERCOM5_0_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM5_1, "SERCOM5_1_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM5_2, "SERCOM5_2_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM5_OTHER, "SERCOM5_OTHER_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM6_0, "SERCOM6_0_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM6_1, "SERCOM6_1_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM6_2, "SERCOM6_2_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM6_OTHER, "SERCOM6_OTHER_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM7_0, "SERCOM7_0_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM7_1, "SERCOM7_1_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM7_2, "SERCOM7_2_IRQHandler")
	_ = interrupt.Register(IRQ_SERCOM7_OTHER, "SERCOM7_OTHER_IRQHandler")
	_ = interrupt.Register(IRQ_USB_OTHER, "USB_OTHER_IRQHandler")
	_ = interrupt.Register(IRQ_USB_SOF_HSOF, "USB_SOF_HSOF_IRQHandler")
	_ = interrupt.Register(IRQ_USB_TRCPT0, "USB_TRCPT0_IRQHandler")
	_ = interrupt.Register(IRQ_USB_TRCPT1, "USB_TRCPT1_IRQHandler")
	_ = interrupt.Register(IRQ_TCC0_OTHER, "TCC0_OTHER_IRQHandler")
	_ = interrupt.Register(IRQ_TCC0_MC0, "TCC0_MC0_IRQHandler")
	_ = interrupt.Register(IRQ_TCC0_MC1, "TCC0_MC1_IRQHandler")
	_ = interrupt.Register(IRQ_TCC0_MC2, "TCC0_MC2_IRQHandler")
	_ = interrupt.Register(IRQ_TCC0_MC3, "TCC0_MC3_IRQHandler")
	_ = interrupt.Register(IRQ_TCC0_MC4, "TCC0_MC4_IRQHandler")
	_ = interrupt.Register(IRQ_TCC0_MC5, "TCC0_MC5_IRQHandler")
	_ = interrupt.Register(IRQ_TCC1_OTHER, "TCC1_OTHER_IRQHandler")
	_ = interrupt.Register(IRQ_TCC1_MC0, "TCC1_MC0_IRQHandler")
	_ = interrupt.Register(IRQ_TCC1_MC1, "TCC1_MC1_IRQHandler")
	_ = interrupt.Register(IRQ_TCC1_MC2, "TCC1_MC2_IRQHandler")
	_ = interrupt.Register(IRQ_TCC1_MC3, "TCC1_MC3_IRQHandler")
	_ = interrupt.Register(IRQ_TCC2_OTHER, "TCC2_OTHER_IRQHandler")
	_ = interrupt.Register(IRQ_TCC2_MC0, "TCC2_MC0_IRQHandler")
	_ = interrupt.Register(IRQ_TCC2_MC1, "TCC2_MC1_IRQHandler")
	_ = interrupt.Register(IRQ_TCC2_MC2, "TCC2_MC2_IRQHandler")
	_ = interrupt.Register(IRQ_TCC3_OTHER, "TCC3_OTHER_IRQHandler")
	_ = interrupt.Register(IRQ_TCC3_MC0, "TCC3_MC0_IRQHandler")
	_ = interrupt.Register(IRQ_TCC3_MC1, "TCC3_MC1_IRQHandler")
	_ = interrupt.Register(IRQ_TCC4_OTHER, "TCC4_OTHER_IRQHandler")
	_ = interrupt.Register(IRQ_TCC4_MC0, "TCC4_MC0_IRQHandler")
	_ = interrupt.Register(IRQ_TCC4_MC1, "TCC4_MC1_IRQHandler")
	_ = interrupt.Register(IRQ_TC0, "TC0_IRQHandler")
	_ = interrupt.Register(IRQ_TC1, "TC1_IRQHandler")
	_ = interrupt.Register(IRQ_TC2, "TC2_IRQHandler")
	_ = interrupt.Register(IRQ_TC3, "TC3_IRQHandler")
	_ = interrupt.Register(IRQ_TC4, "TC4_IRQHandler")
	_ = interrupt.Register(IRQ_TC5, "TC5_IRQHandler")
	_ = interrupt.Register(IRQ_TC6, "TC6_IRQHandler")
	_ = interrupt.Register(IRQ_TC7, "TC7_IRQHandler")
	_ = interrupt.Register(IRQ_PDEC_OTHER, "PDEC_OTHER_IRQHandler")
	_ = interrupt.Register(IRQ_PDEC_MC0, "PDEC_MC0_IRQHandler")
	_ = interrupt.Register(IRQ_PDEC_MC1, "PDEC_MC1_IRQHandler")
	_ = interrupt.Register(IRQ_ADC0_OTHER, "ADC0_OTHER_IRQHandler")
	_ = interrupt.Register(IRQ_ADC0_RESRDY, "ADC0_RESRDY_IRQHandler")
	_ = interrupt.Register(IRQ_ADC1_OTHER, "ADC1_OTHER_IRQHandler")
	_ = interrupt.Register(IRQ_ADC1_RESRDY, "ADC1_RESRDY_IRQHandler")
	_ = interrupt.Register(IRQ_AC, "AC_IRQHandler")
	_ = interrupt.Register(IRQ_DAC_OTHER, "DAC_OTHER_IRQHandler")
	_ = interrupt.Register(IRQ_DAC_EMPTY_0, "DAC_EMPTY_0_IRQHandler")
	_ = interrupt.Register(IRQ_DAC_EMPTY_1, "DAC_EMPTY_1_IRQHandler")
	_ = interrupt.Register(IRQ_DAC_RESRDY_0, "DAC_RESRDY_0_IRQHandler")
	_ = interrupt.Register(IRQ_DAC_RESRDY_1, "DAC_RESRDY_1_IRQHandler")
	_ = interrupt.Register(IRQ_I2S, "I2S_IRQHandler")
	_ = interrupt.Register(IRQ_PCC, "PCC_IRQHandler")
	_ = interrupt.Register(IRQ_AES, "AES_IRQHandler")
	_ = interrupt.Register(IRQ_TRNG, "TRNG_IRQHandler")
	_ = interrupt.Register(IRQ_ICM, "ICM_IRQHandler")
	_ = interrupt.Register(IRQ_QSPI, "QSPI_IRQHandler")
	_ = interrupt.Register(IRQ_SDHC0, "SDHC0_IRQHandler")
	_ = interrupt.Register(IRQ_SDHC1, "SDHC1_IRQHandler")
)

// Peripherals.
var (
	AC                = (*AC_Type)(unsafe.Pointer(uintptr(0x42002000)))               // Analog Comparators
	ADC0              = (*ADC_Type)(unsafe.Pointer(uintptr(0x43001c00)))              // Analog Digital Converter
	AES               = (*AES_Type)(unsafe.Pointer(uintptr(0x42002400)))              // Advanced Encryption Standard
	CCL               = (*CCL_Type)(unsafe.Pointer(uintptr(0x42003800)))              // Configurable Custom Logic
	CMCC              = (*CMCC_Type)(unsafe.Pointer(uintptr(0x41006000)))             // Cortex M Cache Controller
	DAC               = (*DAC_Type)(unsafe.Pointer(uintptr(0x43002400)))              // Digital-to-Analog Converter
	DMAC              = (*DMAC_Type)(unsafe.Pointer(uintptr(0x4100a000)))             // Direct Memory Access Controller
	DSU               = (*DSU_Type)(unsafe.Pointer(uintptr(0x41002000)))              // Device Service Unit
	EIC               = (*EIC_Type)(unsafe.Pointer(uintptr(0x40002800)))              // External Interrupt Controller
	EVSYS             = (*EVSYS_Type)(unsafe.Pointer(uintptr(0x4100e000)))            // Event System Interface
	FREQM             = (*FREQM_Type)(unsafe.Pointer(uintptr(0x40002c00)))            // Frequency Meter
	GCLK              = (*GCLK_Type)(unsafe.Pointer(uintptr(0x40001c00)))             // Generic Clock Generator
	HMATRIX           = (*HMATRIXB_Type)(unsafe.Pointer(uintptr(0x4100c000)))         // HSB Matrix
	ICM               = (*ICM_Type)(unsafe.Pointer(uintptr(0x42002c00)))              // Integrity Check Monitor
	I2S               = (*I2S_Type)(unsafe.Pointer(uintptr(0x43002800)))              // Inter-IC Sound Interface
	MCLK              = (*MCLK_Type)(unsafe.Pointer(uintptr(0x40000800)))             // Main Clock
	NVMCTRL           = (*NVMCTRL_Type)(unsafe.Pointer(uintptr(0x41004000)))          // Non-Volatile Memory Controller
	OSCCTRL           = (*OSCCTRL_Type)(unsafe.Pointer(uintptr(0x40001000)))          // Oscillators Control
	OSC32KCTRL        = (*OSC32KCTRL_Type)(unsafe.Pointer(uintptr(0x40001400)))       // 32kHz Oscillators Control
	PAC               = (*PAC_Type)(unsafe.Pointer(uintptr(0x40000000)))              // Peripheral Access Controller
	PCC               = (*PCC_Type)(unsafe.Pointer(uintptr(0x43002c00)))              // Parallel Capture Controller
	PDEC              = (*PDEC_Type)(unsafe.Pointer(uintptr(0x42001c00)))             // Quadrature Decodeur
	PM                = (*PM_Type)(unsafe.Pointer(uintptr(0x40000400)))               // Power Manager
	PORT              = (*PORT_Type)(unsafe.Pointer(uintptr(0x41008000)))             // Port Module
	QSPI              = (*QSPI_Type)(unsafe.Pointer(uintptr(0x42003400)))             // Quad SPI interface
	RAMECC            = (*RAMECC_Type)(unsafe.Pointer(uintptr(0x41020000)))           // RAM ECC
	RSTC              = (*RSTC_Type)(unsafe.Pointer(uintptr(0x40000c00)))             // Reset Controller
	RTC               = (*RTC_Type)(unsafe.Pointer(uintptr(0x40002400)))              // Real-Time Counter
	RTC_MODE0         = (*RTC_MODE0_Type)(unsafe.Pointer(uintptr(0x40002400)))        // Real-Time Counter - MODE0
	RTC_MODE1         = (*RTC_MODE1_Type)(unsafe.Pointer(uintptr(0x40002400)))        // Real-Time Counter - MODE1
	RTC_MODE2         = (*RTC_MODE2_Type)(unsafe.Pointer(uintptr(0x40002400)))        // Real-Time Counter - MODE2
	SDHC0             = (*SDHC_Type)(unsafe.Pointer(uintptr(0x45000000)))             // SD/MMC Host Controller
	SERCOM0           = (*SERCOM_Type)(unsafe.Pointer(uintptr(0x40003000)))           // Serial Communication Interface
	SERCOM0_I2CM      = (*SERCOM_I2CM_Type)(unsafe.Pointer(uintptr(0x40003000)))      // Serial Communication Interface - I2CM
	SERCOM0_I2CS      = (*SERCOM_I2CS_Type)(unsafe.Pointer(uintptr(0x40003000)))      // Serial Communication Interface - I2CS
	SERCOM0_SPIS      = (*SERCOM_SPIS_Type)(unsafe.Pointer(uintptr(0x40003000)))      // Serial Communication Interface - SPIS
	SERCOM0_SPIM      = (*SERCOM_SPIM_Type)(unsafe.Pointer(uintptr(0x40003000)))      // Serial Communication Interface - SPIM
	SERCOM0_USART_EXT = (*SERCOM_USART_EXT_Type)(unsafe.Pointer(uintptr(0x40003000))) // Serial Communication Interface - USART_EXT
	SERCOM0_USART_INT = (*SERCOM_USART_INT_Type)(unsafe.Pointer(uintptr(0x40003000))) // Serial Communication Interface - USART_INT
	SUPC              = (*SUPC_Type)(unsafe.Pointer(uintptr(0x40001800)))             // Supply Controller
	TC0               = (*TC_Type)(unsafe.Pointer(uintptr(0x40003800)))               // Basic Timer Counter
	TC0_COUNT8        = (*TC_COUNT8_Type)(unsafe.Pointer(uintptr(0x40003800)))        // Basic Timer Counter - COUNT8
	TC0_COUNT16       = (*TC_COUNT16_Type)(unsafe.Pointer(uintptr(0x40003800)))       // Basic Timer Counter - COUNT16
	TC0_COUNT32       = (*TC_COUNT32_Type)(unsafe.Pointer(uintptr(0x40003800)))       // Basic Timer Counter - COUNT32
	TCC0              = (*TCC_Type)(unsafe.Pointer(uintptr(0x41016000)))              // Timer Counter Control
	TRNG              = (*TRNG_Type)(unsafe.Pointer(uintptr(0x42002800)))             // True Random Generator
	USB               = (*USB_Type)(unsafe.Pointer(uintptr(0x41000000)))              // Universal Serial Bus
	USB_DEVICE        = (*USB_DEVICE_Type)(unsafe.Pointer(uintptr(0x41000000)))       // Universal Serial Bus - DEVICE
	USB_HOST          = (*USB_HOST_Type)(unsafe.Pointer(uintptr(0x41000000)))         // Universal Serial Bus - HOST
	WDT               = (*WDT_Type)(unsafe.Pointer(uintptr(0x40002000)))              // Watchdog Timer
	CoreDebug         = (*CoreDebug_Type)(unsafe.Pointer(uintptr(0xe000edf0)))        // Core Debug Register
	DWT               = (*DWT_Type)(unsafe.Pointer(uintptr(0xe0001000)))              // Data Watchpoint and Trace Register
	ETM               = (*ETM_Type)(unsafe.Pointer(uintptr(0xe0041000)))              // Embedded Trace Macrocell
	FPU               = (*FPU_Type)(unsafe.Pointer(uintptr(0xe000ef30)))              // Floating Point Unit
	ITM               = (*ITM_Type)(unsafe.Pointer(uintptr(0xe0000000)))              // Instrumentation Trace Macrocell
	MPU               = (*MPU_Type)(unsafe.Pointer(uintptr(0xe000ed90)))              // Memory Protection Unit
	NVIC              = (*NVIC_Type)(unsafe.Pointer(uintptr(0xe000e100)))             // Nested Vectored Interrupt Controller
	SysTick           = (*SysTick_Type)(unsafe.Pointer(uintptr(0xe000e010)))          // System timer
	SystemControl     = (*SystemControl_Type)(unsafe.Pointer(uintptr(0xe000e000)))    // System Control Registers
	TPI               = (*TPI_Type)(unsafe.Pointer(uintptr(0xe0040000)))              // Trace Port Interface Register
	ADC1              = (*ADC_Type)(unsafe.Pointer(uintptr(0x43002000)))              // Analog Digital Converter
	SDHC1             = (*SDHC_Type)(unsafe.Pointer(uintptr(0x46000000)))             // SD/MMC Host Controller
	SERCOM1           = (*SERCOM_Type)(unsafe.Pointer(uintptr(0x40003400)))           // Serial Communication Interface
	SERCOM1_I2CM      = (*SERCOM_I2CM_Type)(unsafe.Pointer(uintptr(0x40003400)))      // Serial Communication Interface - I2CM
	SERCOM1_I2CS      = (*SERCOM_I2CS_Type)(unsafe.Pointer(uintptr(0x40003400)))      // Serial Communication Interface - I2CS
	SERCOM1_SPIS      = (*SERCOM_SPIS_Type)(unsafe.Pointer(uintptr(0x40003400)))      // Serial Communication Interface - SPIS
	SERCOM1_SPIM      = (*SERCOM_SPIM_Type)(unsafe.Pointer(uintptr(0x40003400)))      // Serial Communication Interface - SPIM
	SERCOM1_USART_EXT = (*SERCOM_USART_EXT_Type)(unsafe.Pointer(uintptr(0x40003400))) // Serial Communication Interface - USART_EXT
	SERCOM1_USART_INT = (*SERCOM_USART_INT_Type)(unsafe.Pointer(uintptr(0x40003400))) // Serial Communication Interface - USART_INT
	SERCOM2           = (*SERCOM_Type)(unsafe.Pointer(uintptr(0x41012000)))           // Serial Communication Interface
	SERCOM2_I2CM      = (*SERCOM_I2CM_Type)(unsafe.Pointer(uintptr(0x41012000)))      // Serial Communication Interface - I2CM
	SERCOM2_I2CS      = (*SERCOM_I2CS_Type)(unsafe.Pointer(uintptr(0x41012000)))      // Serial Communication Interface - I2CS
	SERCOM2_SPIS      = (*SERCOM_SPIS_Type)(unsafe.Pointer(uintptr(0x41012000)))      // Serial Communication Interface - SPIS
	SERCOM2_SPIM      = (*SERCOM_SPIM_Type)(unsafe.Pointer(uintptr(0x41012000)))      // Serial Communication Interface - SPIM
	SERCOM2_USART_EXT = (*SERCOM_USART_EXT_Type)(unsafe.Pointer(uintptr(0x41012000))) // Serial Communication Interface - USART_EXT
	SERCOM2_USART_INT = (*SERCOM_USART_INT_Type)(unsafe.Pointer(uintptr(0x41012000))) // Serial Communication Interface - USART_INT
	SERCOM3           = (*SERCOM_Type)(unsafe.Pointer(uintptr(0x41014000)))           // Serial Communication Interface
	SERCOM3_I2CM      = (*SERCOM_I2CM_Type)(unsafe.Pointer(uintptr(0x41014000)))      // Serial Communication Interface - I2CM
	SERCOM3_I2CS      = (*SERCOM_I2CS_Type)(unsafe.Pointer(uintptr(0x41014000)))      // Serial Communication Interface - I2CS
	SERCOM3_SPIS      = (*SERCOM_SPIS_Type)(unsafe.Pointer(uintptr(0x41014000)))      // Serial Communication Interface - SPIS
	SERCOM3_SPIM      = (*SERCOM_SPIM_Type)(unsafe.Pointer(uintptr(0x41014000)))      // Serial Communication Interface - SPIM
	SERCOM3_USART_EXT = (*SERCOM_USART_EXT_Type)(unsafe.Pointer(uintptr(0x41014000))) // Serial Communication Interface - USART_EXT
	SERCOM3_USART_INT = (*SERCOM_USART_INT_Type)(unsafe.Pointer(uintptr(0x41014000))) // Serial Communication Interface - USART_INT
	SERCOM4           = (*SERCOM_Type)(unsafe.Pointer(uintptr(0x43000000)))           // Serial Communication Interface
	SERCOM4_I2CM      = (*SERCOM_I2CM_Type)(unsafe.Pointer(uintptr(0x43000000)))      // Serial Communication Interface - I2CM
	SERCOM4_I2CS      = (*SERCOM_I2CS_Type)(unsafe.Pointer(uintptr(0x43000000)))      // Serial Communication Interface - I2CS
	SERCOM4_SPIS      = (*SERCOM_SPIS_Type)(unsafe.Pointer(uintptr(0x43000000)))      // Serial Communication Interface - SPIS
	SERCOM4_SPIM      = (*SERCOM_SPIM_Type)(unsafe.Pointer(uintptr(0x43000000)))      // Serial Communication Interface - SPIM
	SERCOM4_USART_EXT = (*SERCOM_USART_EXT_Type)(unsafe.Pointer(uintptr(0x43000000))) // Serial Communication Interface - USART_EXT
	SERCOM4_USART_INT = (*SERCOM_USART_INT_Type)(unsafe.Pointer(uintptr(0x43000000))) // Serial Communication Interface - USART_INT
	SERCOM5           = (*SERCOM_Type)(unsafe.Pointer(uintptr(0x43000400)))           // Serial Communication Interface
	SERCOM5_I2CM      = (*SERCOM_I2CM_Type)(unsafe.Pointer(uintptr(0x43000400)))      // Serial Communication Interface - I2CM
	SERCOM5_I2CS      = (*SERCOM_I2CS_Type)(unsafe.Pointer(uintptr(0x43000400)))      // Serial Communication Interface - I2CS
	SERCOM5_SPIS      = (*SERCOM_SPIS_Type)(unsafe.Pointer(uintptr(0x43000400)))      // Serial Communication Interface - SPIS
	SERCOM5_SPIM      = (*SERCOM_SPIM_Type)(unsafe.Pointer(uintptr(0x43000400)))      // Serial Communication Interface - SPIM
	SERCOM5_USART_EXT = (*SERCOM_USART_EXT_Type)(unsafe.Pointer(uintptr(0x43000400))) // Serial Communication Interface - USART_EXT
	SERCOM5_USART_INT = (*SERCOM_USART_INT_Type)(unsafe.Pointer(uintptr(0x43000400))) // Serial Communication Interface - USART_INT
	SERCOM6           = (*SERCOM_Type)(unsafe.Pointer(uintptr(0x43000800)))           // Serial Communication Interface
	SERCOM6_I2CM      = (*SERCOM_I2CM_Type)(unsafe.Pointer(uintptr(0x43000800)))      // Serial Communication Interface - I2CM
	SERCOM6_I2CS      = (*SERCOM_I2CS_Type)(unsafe.Pointer(uintptr(0x43000800)))      // Serial Communication Interface - I2CS
	SERCOM6_SPIS      = (*SERCOM_SPIS_Type)(unsafe.Pointer(uintptr(0x43000800)))      // Serial Communication Interface - SPIS
	SERCOM6_SPIM      = (*SERCOM_SPIM_Type)(unsafe.Pointer(uintptr(0x43000800)))      // Serial Communication Interface - SPIM
	SERCOM6_USART_EXT = (*SERCOM_USART_EXT_Type)(unsafe.Pointer(uintptr(0x43000800))) // Serial Communication Interface - USART_EXT
	SERCOM6_USART_INT = (*SERCOM_USART_INT_Type)(unsafe.Pointer(uintptr(0x43000800))) // Serial Communication Interface - USART_INT
	SERCOM7           = (*SERCOM_Type)(unsafe.Pointer(uintptr(0x43000c00)))           // Serial Communication Interface
	SERCOM7_I2CM      = (*SERCOM_I2CM_Type)(unsafe.Pointer(uintptr(0x43000c00)))      // Serial Communication Interface - I2CM
	SERCOM7_I2CS      = (*SERCOM_I2CS_Type)(unsafe.Pointer(uintptr(0x43000c00)))      // Serial Communication Interface - I2CS
	SERCOM7_SPIS      = (*SERCOM_SPIS_Type)(unsafe.Pointer(uintptr(0x43000c00)))      // Serial Communication Interface - SPIS
	SERCOM7_SPIM      = (*SERCOM_SPIM_Type)(unsafe.Pointer(uintptr(0x43000c00)))      // Serial Communication Interface - SPIM
	SERCOM7_USART_EXT = (*SERCOM_USART_EXT_Type)(unsafe.Pointer(uintptr(0x43000c00))) // Serial Communication Interface - USART_EXT
	SERCOM7_USART_INT = (*SERCOM_USART_INT_Type)(unsafe.Pointer(uintptr(0x43000c00))) // Serial Communication Interface - USART_INT
	TC1               = (*TC_Type)(unsafe.Pointer(uintptr(0x40003c00)))               // Basic Timer Counter
	TC1_COUNT8        = (*TC_COUNT8_Type)(unsafe.Pointer(uintptr(0x40003c00)))        // Basic Timer Counter - COUNT8
	TC1_COUNT16       = (*TC_COUNT16_Type)(unsafe.Pointer(uintptr(0x40003c00)))       // Basic Timer Counter - COUNT16
	TC1_COUNT32       = (*TC_COUNT32_Type)(unsafe.Pointer(uintptr(0x40003c00)))       // Basic Timer Counter - COUNT32
	TC2               = (*TC_Type)(unsafe.Pointer(uintptr(0x4101a000)))               // Basic Timer Counter
	TC2_COUNT8        = (*TC_COUNT8_Type)(unsafe.Pointer(uintptr(0x4101a000)))        // Basic Timer Counter - COUNT8
	TC2_COUNT16       = (*TC_COUNT16_Type)(unsafe.Pointer(uintptr(0x4101a000)))       // Basic Timer Counter - COUNT16
	TC2_COUNT32       = (*TC_COUNT32_Type)(unsafe.Pointer(uintptr(0x4101a000)))       // Basic Timer Counter - COUNT32
	TC3               = (*TC_Type)(unsafe.Pointer(uintptr(0x4101c000)))               // Basic Timer Counter
	TC3_COUNT8        = (*TC_COUNT8_Type)(unsafe.Pointer(uintptr(0x4101c000)))        // Basic Timer Counter - COUNT8
	TC3_COUNT16       = (*TC_COUNT16_Type)(unsafe.Pointer(uintptr(0x4101c000)))       // Basic Timer Counter - COUNT16
	TC3_COUNT32       = (*TC_COUNT32_Type)(unsafe.Pointer(uintptr(0x4101c000)))       // Basic Timer Counter - COUNT32
	TC4               = (*TC_Type)(unsafe.Pointer(uintptr(0x42001400)))               // Basic Timer Counter
	TC4_COUNT8        = (*TC_COUNT8_Type)(unsafe.Pointer(uintptr(0x42001400)))        // Basic Timer Counter - COUNT8
	TC4_COUNT16       = (*TC_COUNT16_Type)(unsafe.Pointer(uintptr(0x42001400)))       // Basic Timer Counter - COUNT16
	TC4_COUNT32       = (*TC_COUNT32_Type)(unsafe.Pointer(uintptr(0x42001400)))       // Basic Timer Counter - COUNT32
	TC5               = (*TC_Type)(unsafe.Pointer(uintptr(0x42001800)))               // Basic Timer Counter
	TC5_COUNT8        = (*TC_COUNT8_Type)(unsafe.Pointer(uintptr(0x42001800)))        // Basic Timer Counter - COUNT8
	TC5_COUNT16       = (*TC_COUNT16_Type)(unsafe.Pointer(uintptr(0x42001800)))       // Basic Timer Counter - COUNT16
	TC5_COUNT32       = (*TC_COUNT32_Type)(unsafe.Pointer(uintptr(0x42001800)))       // Basic Timer Counter - COUNT32
	TC6               = (*TC_Type)(unsafe.Pointer(uintptr(0x43001400)))               // Basic Timer Counter
	TC6_COUNT8        = (*TC_COUNT8_Type)(unsafe.Pointer(uintptr(0x43001400)))        // Basic Timer Counter - COUNT8
	TC6_COUNT16       = (*TC_COUNT16_Type)(unsafe.Pointer(uintptr(0x43001400)))       // Basic Timer Counter - COUNT16
	TC6_COUNT32       = (*TC_COUNT32_Type)(unsafe.Pointer(uintptr(0x43001400)))       // Basic Timer Counter - COUNT32
	TC7               = (*TC_Type)(unsafe.Pointer(uintptr(0x43001800)))               // Basic Timer Counter
	TC7_COUNT8        = (*TC_COUNT8_Type)(unsafe.Pointer(uintptr(0x43001800)))        // Basic Timer Counter - COUNT8
	TC7_COUNT16       = (*TC_COUNT16_Type)(unsafe.Pointer(uintptr(0x43001800)))       // Basic Timer Counter - COUNT16
	TC7_COUNT32       = (*TC_COUNT32_Type)(unsafe.Pointer(uintptr(0x43001800)))       // Basic Timer Counter - COUNT32
	TCC1              = (*TCC_Type)(unsafe.Pointer(uintptr(0x41018000)))              // Timer Counter Control
	TCC2              = (*TCC_Type)(unsafe.Pointer(uintptr(0x42000c00)))              // Timer Counter Control
	TCC3              = (*TCC_Type)(unsafe.Pointer(uintptr(0x42001000)))              // Timer Counter Control
	TCC4              = (*TCC_Type)(unsafe.Pointer(uintptr(0x43001000)))              // Timer Counter Control
)

// Analog Comparators
type AC_Type struct {
	CTRLA    volatile.Register8  // 0x0
	CTRLB    volatile.Register8  // 0x1
	EVCTRL   volatile.Register16 // 0x2
	INTENCLR volatile.Register8  // 0x4
	INTENSET volatile.Register8  // 0x5
	INTFLAG  volatile.Register8  // 0x6
	STATUSA  volatile.Register8  // 0x7
	STATUSB  volatile.Register8  // 0x8
	DBGCTRL  volatile.Register8  // 0x9
	WINCTRL  volatile.Register8  // 0xA
	_        byte
	SCALER   [2]volatile.Register8 // 0xC
	_        [2]byte
	COMPCTRL [2]volatile.Register32 // 0x10
	_        [8]byte
	SYNCBUSY volatile.Register32 // 0x20
	CALIB    volatile.Register16 // 0x24
}

// Analog Digital Converter
type ADC_Type struct {
	CTRLA      volatile.Register16 // 0x0
	EVCTRL     volatile.Register8  // 0x2
	DBGCTRL    volatile.Register8  // 0x3
	INPUTCTRL  volatile.Register16 // 0x4
	CTRLB      volatile.Register16 // 0x6
	REFCTRL    volatile.Register8  // 0x8
	_          byte
	AVGCTRL    volatile.Register8  // 0xA
	SAMPCTRL   volatile.Register8  // 0xB
	WINLT      volatile.Register16 // 0xC
	WINUT      volatile.Register16 // 0xE
	GAINCORR   volatile.Register16 // 0x10
	OFFSETCORR volatile.Register16 // 0x12
	SWTRIG     volatile.Register8  // 0x14
	_          [23]byte
	INTENCLR   volatile.Register8  // 0x2C
	INTENSET   volatile.Register8  // 0x2D
	INTFLAG    volatile.Register8  // 0x2E
	STATUS     volatile.Register8  // 0x2F
	SYNCBUSY   volatile.Register32 // 0x30
	DSEQDATA   volatile.Register32 // 0x34
	DSEQCTRL   volatile.Register32 // 0x38
	DSEQSTAT   volatile.Register32 // 0x3C
	RESULT     volatile.Register16 // 0x40
	_          [2]byte
	RESS       volatile.Register16 // 0x44
	_          [2]byte
	CALIB      volatile.Register16 // 0x48
}

// Advanced Encryption Standard
type AES_Type struct {
	CTRLA      volatile.Register32 // 0x0
	CTRLB      volatile.Register8  // 0x4
	INTENCLR   volatile.Register8  // 0x5
	INTENSET   volatile.Register8  // 0x6
	INTFLAG    volatile.Register8  // 0x7
	DATABUFPTR volatile.Register8  // 0x8
	DBGCTRL    volatile.Register8  // 0x9
	_          [2]byte
	KEYWORD    [8]volatile.Register32 // 0xC
	_          [12]byte
	INDATA     volatile.Register32    // 0x38
	INTVECTV   [4]volatile.Register32 // 0x3C
	_          [16]byte
	HASHKEY    [4]volatile.Register32 // 0x5C
	GHASH      [4]volatile.Register32 // 0x6C
	_          [4]byte
	CIPLEN     volatile.Register32 // 0x80
	RANDSEED   volatile.Register32 // 0x84
}

// Configurable Custom Logic
type CCL_Type struct {
	CTRL    volatile.Register8 // 0x0
	_       [3]byte
	SEQCTRL [2]volatile.Register8 // 0x4
	_       [2]byte
	LUTCTRL [4]volatile.Register32 // 0x8
}

// Cortex M Cache Controller
type CMCC_Type struct {
	TYPE   volatile.Register32 // 0x0
	CFG    volatile.Register32 // 0x4
	CTRL   volatile.Register32 // 0x8
	SR     volatile.Register32 // 0xC
	LCKWAY volatile.Register32 // 0x10
	_      [12]byte
	MAINT0 volatile.Register32 // 0x20
	MAINT1 volatile.Register32 // 0x24
	MCFG   volatile.Register32 // 0x28
	MEN    volatile.Register32 // 0x2C
	MCTRL  volatile.Register32 // 0x30
	MSR    volatile.Register32 // 0x34
}

// Digital-to-Analog Converter
type DAC_Type struct {
	CTRLA    volatile.Register8 // 0x0
	CTRLB    volatile.Register8 // 0x1
	EVCTRL   volatile.Register8 // 0x2
	_        byte
	INTENCLR volatile.Register8     // 0x4
	INTENSET volatile.Register8     // 0x5
	INTFLAG  volatile.Register8     // 0x6
	STATUS   volatile.Register8     // 0x7
	SYNCBUSY volatile.Register32    // 0x8
	DACCTRL  [2]volatile.Register16 // 0xC
	DATA     [2]volatile.Register16 // 0x10
	DATABUF  [2]volatile.Register16 // 0x14
	DBGCTRL  volatile.Register8     // 0x18
	_        [3]byte
	RESULT   [2]volatile.Register16 // 0x1C
}

// Direct Memory Access Controller
type DMAC_Type struct {
	CTRL       volatile.Register16 // 0x0
	CRCCTRL    volatile.Register16 // 0x2
	CRCDATAIN  volatile.Register32 // 0x4
	CRCCHKSUM  volatile.Register32 // 0x8
	CRCSTATUS  volatile.Register8  // 0xC
	DBGCTRL    volatile.Register8  // 0xD
	_          [2]byte
	SWTRIGCTRL volatile.Register32 // 0x10
	PRICTRL0   volatile.Register32 // 0x14
	_          [8]byte
	INTPEND    volatile.Register16 // 0x20
	_          [2]byte
	INTSTATUS  volatile.Register32 // 0x24
	BUSYCH     volatile.Register32 // 0x28
	PENDCH     volatile.Register32 // 0x2C
	ACTIVE     volatile.Register32 // 0x30
	BASEADDR   volatile.Register32 // 0x34
	WRBADDR    volatile.Register32 // 0x38
	_          [4]byte
	CHANNEL    [32]struct {
		CHCTRLA    volatile.Register32
		CHCTRLB    volatile.Register8
		CHPRILVL   volatile.Register8
		CHEVCTRL   volatile.Register8
		_          [5]byte
		CHINTENCLR volatile.Register8
		CHINTENSET volatile.Register8
		CHINTFLAG  volatile.Register8
		CHSTATUS   volatile.Register8
	} // 0x40
}

// Device Service Unit
type DSU_Type struct {
	CTRL    volatile.Register8 // 0x0
	STATUSA volatile.Register8 // 0x1
	STATUSB volatile.Register8 // 0x2
	_       byte
	ADDR    volatile.Register32    // 0x4
	LENGTH  volatile.Register32    // 0x8
	DATA    volatile.Register32    // 0xC
	DCC     [2]volatile.Register32 // 0x10
	DID     volatile.Register32    // 0x18
	CFG     volatile.Register32    // 0x1C
	_       [208]byte
	DCFG    [2]volatile.Register32 // 0xF0
	_       [3848]byte
	ENTRY0  volatile.Register32 // 0x1000
	ENTRY1  volatile.Register32 // 0x1004
	END     volatile.Register32 // 0x1008
	_       [4032]byte
	MEMTYPE volatile.Register32 // 0x1FCC
	PID4    volatile.Register32 // 0x1FD0
	PID5    volatile.Register32 // 0x1FD4
	PID6    volatile.Register32 // 0x1FD8
	PID7    volatile.Register32 // 0x1FDC
	PID0    volatile.Register32 // 0x1FE0
	PID1    volatile.Register32 // 0x1FE4
	PID2    volatile.Register32 // 0x1FE8
	PID3    volatile.Register32 // 0x1FEC
	CID0    volatile.Register32 // 0x1FF0
	CID1    volatile.Register32 // 0x1FF4
	CID2    volatile.Register32 // 0x1FF8
	CID3    volatile.Register32 // 0x1FFC
}

// External Interrupt Controller
type EIC_Type struct {
	CTRLA      volatile.Register8     // 0x0
	NMICTRL    volatile.Register8     // 0x1
	NMIFLAG    volatile.Register16    // 0x2
	SYNCBUSY   volatile.Register32    // 0x4
	EVCTRL     volatile.Register32    // 0x8
	INTENCLR   volatile.Register32    // 0xC
	INTENSET   volatile.Register32    // 0x10
	INTFLAG    volatile.Register32    // 0x14
	ASYNCH     volatile.Register32    // 0x18
	CONFIG     [2]volatile.Register32 // 0x1C
	_          [12]byte
	DEBOUNCEN  volatile.Register32 // 0x30
	DPRESCALER volatile.Register32 // 0x34
	PINSTATE   volatile.Register32 // 0x38
}

// Event System Interface
type EVSYS_Type struct {
	CTRLA     volatile.Register8 // 0x0
	_         [3]byte
	SWEVT     volatile.Register32 // 0x4
	PRICTRL   volatile.Register8  // 0x8
	_         [7]byte
	INTPEND   volatile.Register16 // 0x10
	_         [2]byte
	INTSTATUS volatile.Register32 // 0x14
	BUSYCH    volatile.Register32 // 0x18
	READYUSR  volatile.Register32 // 0x1C
	CHANNEL   [32]struct {
		CHANNEL    volatile.Register32
		CHINTENCLR volatile.Register8
		CHINTENSET volatile.Register8
		CHINTFLAG  volatile.Register8
		CHSTATUS   volatile.Register8
	} // 0x20
	USER [67]volatile.Register32 // 0x120
}

// Frequency Meter
type FREQM_Type struct {
	CTRLA    volatile.Register8  // 0x0
	CTRLB    volatile.Register8  // 0x1
	CFGA     volatile.Register16 // 0x2
	_        [4]byte
	INTENCLR volatile.Register8  // 0x8
	INTENSET volatile.Register8  // 0x9
	INTFLAG  volatile.Register8  // 0xA
	STATUS   volatile.Register8  // 0xB
	SYNCBUSY volatile.Register32 // 0xC
	VALUE    volatile.Register32 // 0x10
}

// Generic Clock Generator
type GCLK_Type struct {
	CTRLA    volatile.Register8 // 0x0
	_        [3]byte
	SYNCBUSY volatile.Register32 // 0x4
	_        [24]byte
	GENCTRL  [12]volatile.Register32 // 0x20
	_        [48]byte
	PCHCTRL  [48]volatile.Register32 // 0x80
}

// HSB Matrix
type HMATRIXB_Type struct {
	_   [128]byte
	PRS [16]struct {
		PRAS volatile.Register32
		PRBS volatile.Register32
	} // 0x80
}

// Integrity Check Monitor
type ICM_Type struct {
	CFG    volatile.Register32 // 0x0
	CTRL   volatile.Register32 // 0x4
	SR     volatile.Register32 // 0x8
	_      [4]byte
	IER    volatile.Register32 // 0x10
	IDR    volatile.Register32 // 0x14
	IMR    volatile.Register32 // 0x18
	ISR    volatile.Register32 // 0x1C
	UASR   volatile.Register32 // 0x20
	_      [12]byte
	DSCR   volatile.Register32    // 0x30
	HASH   volatile.Register32    // 0x34
	UIHVAL [8]volatile.Register32 // 0x38
}

// Inter-IC Sound Interface
type I2S_Type struct {
	CTRLA    volatile.Register8 // 0x0
	_        [3]byte
	CLKCTRL  [2]volatile.Register32 // 0x4
	INTENCLR volatile.Register16    // 0xC
	_        [2]byte
	INTENSET volatile.Register16 // 0x10
	_        [2]byte
	INTFLAG  volatile.Register16 // 0x14
	_        [2]byte
	SYNCBUSY volatile.Register16 // 0x18
	_        [6]byte
	TXCTRL   volatile.Register32 // 0x20
	RXCTRL   volatile.Register32 // 0x24
	_        [8]byte
	TXDATA   volatile.Register32 // 0x30
	RXDATA   volatile.Register32 // 0x34
}

// Main Clock
type MCLK_Type struct {
	_        byte
	INTENCLR volatile.Register8 // 0x1
	INTENSET volatile.Register8 // 0x2
	INTFLAG  volatile.Register8 // 0x3
	HSDIV    volatile.Register8 // 0x4
	CPUDIV   volatile.Register8 // 0x5
	_        [10]byte
	AHBMASK  volatile.Register32 // 0x10
	APBAMASK volatile.Register32 // 0x14
	APBBMASK volatile.Register32 // 0x18
	APBCMASK volatile.Register32 // 0x1C
	APBDMASK volatile.Register32 // 0x20
}

// Non-Volatile Memory Controller
type NVMCTRL_Type struct {
	CTRLA    volatile.Register16 // 0x0
	_        [2]byte
	CTRLB    volatile.Register16 // 0x4
	_        [2]byte
	PARAM    volatile.Register32    // 0x8
	INTENCLR volatile.Register16    // 0xC
	INTENSET volatile.Register16    // 0xE
	INTFLAG  volatile.Register16    // 0x10
	STATUS   volatile.Register16    // 0x12
	ADDR     volatile.Register32    // 0x14
	RUNLOCK  volatile.Register32    // 0x18
	PBLDATA  [2]volatile.Register32 // 0x1C
	ECCERR   volatile.Register32    // 0x24
	DBGCTRL  volatile.Register8     // 0x28
	_        byte
	SEECFG   volatile.Register8 // 0x2A
	_        byte
	SEESTAT  volatile.Register32 // 0x2C
}

// Oscillators Control
type OSCCTRL_Type struct {
	EVCTRL    volatile.Register8 // 0x0
	_         [3]byte
	INTENCLR  volatile.Register32    // 0x4
	INTENSET  volatile.Register32    // 0x8
	INTFLAG   volatile.Register32    // 0xC
	STATUS    volatile.Register32    // 0x10
	XOSCCTRL  [2]volatile.Register32 // 0x14
	DFLLCTRLA volatile.Register8     // 0x1C
	_         [3]byte
	DFLLCTRLB volatile.Register8 // 0x20
	_         [3]byte
	DFLLVAL   volatile.Register32 // 0x24
	DFLLMUL   volatile.Register32 // 0x28
	DFLLSYNC  volatile.Register8  // 0x2C
	_         [3]byte
	DPLL      [2]struct {
		DPLLCTRLA    volatile.Register8
		_            [3]byte
		DPLLRATIO    volatile.Register32
		DPLLCTRLB    volatile.Register32
		DPLLSYNCBUSY volatile.Register32
		DPLLSTATUS   volatile.Register32
	} // 0x30
}

// 32kHz Oscillators Control
type OSC32KCTRL_Type struct {
	INTENCLR  volatile.Register32 // 0x0
	INTENSET  volatile.Register32 // 0x4
	INTFLAG   volatile.Register32 // 0x8
	STATUS    volatile.Register32 // 0xC
	RTCCTRL   volatile.Register8  // 0x10
	_         [3]byte
	XOSC32K   volatile.Register16 // 0x14
	CFDCTRL   volatile.Register8  // 0x16
	EVCTRL    volatile.Register8  // 0x17
	_         [4]byte
	OSCULP32K volatile.Register32 // 0x1C
}

// Peripheral Access Controller
type PAC_Type struct {
	WRCTRL     volatile.Register32 // 0x0
	EVCTRL     volatile.Register8  // 0x4
	_          [3]byte
	INTENCLR   volatile.Register8 // 0x8
	INTENSET   volatile.Register8 // 0x9
	_          [6]byte
	INTFLAGAHB volatile.Register32 // 0x10
	INTFLAGA   volatile.Register32 // 0x14
	INTFLAGB   volatile.Register32 // 0x18
	INTFLAGC   volatile.Register32 // 0x1C
	INTFLAGD   volatile.Register32 // 0x20
	_          [16]byte
	STATUSA    volatile.Register32 // 0x34
	STATUSB    volatile.Register32 // 0x38
	STATUSC    volatile.Register32 // 0x3C
	STATUSD    volatile.Register32 // 0x40
}

// Parallel Capture Controller
type PCC_Type struct {
	MR   volatile.Register32 // 0x0
	IER  volatile.Register32 // 0x4
	IDR  volatile.Register32 // 0x8
	IMR  volatile.Register32 // 0xC
	ISR  volatile.Register32 // 0x10
	RHR  volatile.Register32 // 0x14
	_    [200]byte
	WPMR volatile.Register32 // 0xE0
	WPSR volatile.Register32 // 0xE4
}

// Quadrature Decodeur
type PDEC_Type struct {
	CTRLA     volatile.Register32 // 0x0
	CTRLBCLR  volatile.Register8  // 0x4
	CTRLBSET  volatile.Register8  // 0x5
	EVCTRL    volatile.Register16 // 0x6
	INTENCLR  volatile.Register8  // 0x8
	INTENSET  volatile.Register8  // 0x9
	INTFLAG   volatile.Register8  // 0xA
	_         byte
	STATUS    volatile.Register16 // 0xC
	_         byte
	DBGCTRL   volatile.Register8  // 0xF
	SYNCBUSY  volatile.Register32 // 0x10
	PRESC     volatile.Register8  // 0x14
	FILTER    volatile.Register8  // 0x15
	_         [2]byte
	PRESCBUF  volatile.Register8 // 0x18
	FILTERBUF volatile.Register8 // 0x19
	_         [2]byte
	COUNT     volatile.Register32    // 0x1C
	CC        [2]volatile.Register32 // 0x20
	_         [8]byte
	CCBUF     [2]volatile.Register32 // 0x30
}

// Power Manager
type PM_Type struct {
	CTRLA    volatile.Register8 // 0x0
	SLEEPCFG volatile.Register8 // 0x1
	_        [2]byte
	INTENCLR volatile.Register8 // 0x4
	INTENSET volatile.Register8 // 0x5
	INTFLAG  volatile.Register8 // 0x6
	_        byte
	STDBYCFG volatile.Register8 // 0x8
	HIBCFG   volatile.Register8 // 0x9
	BKUPCFG  volatile.Register8 // 0xA
	_        [7]byte
	PWSAKDLY volatile.Register8 // 0x12
}

// Port Module
type PORT_Type struct {
	GROUP [3]struct {
		DIR      volatile.Register32
		DIRCLR   volatile.Register32
		DIRSET   volatile.Register32
		DIRTGL   volatile.Register32
		OUT      volatile.Register32
		OUTCLR   volatile.Register32
		OUTSET   volatile.Register32
		OUTTGL   volatile.Register32
		IN       volatile.Register32
		CTRL     volatile.Register32
		WRCONFIG volatile.Register32
		EVCTRL   volatile.Register32
		PMUX     [16]volatile.Register8
		PINCFG   [32]volatile.Register8
		_        [32]byte
	} // 0x0
}

// Quad SPI interface
type QSPI_Type struct {
	CTRLA      volatile.Register32 // 0x0
	CTRLB      volatile.Register32 // 0x4
	BAUD       volatile.Register32 // 0x8
	RXDATA     volatile.Register32 // 0xC
	TXDATA     volatile.Register32 // 0x10
	INTENCLR   volatile.Register32 // 0x14
	INTENSET   volatile.Register32 // 0x18
	INTFLAG    volatile.Register32 // 0x1C
	STATUS     volatile.Register32 // 0x20
	_          [12]byte
	INSTRADDR  volatile.Register32 // 0x30
	INSTRCTRL  volatile.Register32 // 0x34
	INSTRFRAME volatile.Register32 // 0x38
	_          [4]byte
	SCRAMBCTRL volatile.Register32 // 0x40
	SCRAMBKEY  volatile.Register32 // 0x44
}

// RAM ECC
type RAMECC_Type struct {
	INTENCLR volatile.Register8  // 0x0
	INTENSET volatile.Register8  // 0x1
	INTFLAG  volatile.Register8  // 0x2
	STATUS   volatile.Register8  // 0x3
	ERRADDR  volatile.Register32 // 0x4
	_        [7]byte
	DBGCTRL  volatile.Register8 // 0xF
}

// Reset Controller
type RSTC_Type struct {
	RCAUSE   volatile.Register8 // 0x0
	_        byte
	BKUPEXIT volatile.Register8 // 0x2
}

// Real-Time Counter
type RTC_Type struct {
}

// Real-Time Counter - MODE0
type RTC_MODE0_Type struct {
	CTRLA     volatile.Register16 // 0x0
	CTRLB     volatile.Register16 // 0x2
	EVCTRL    volatile.Register32 // 0x4
	INTENCLR  volatile.Register16 // 0x8
	INTENSET  volatile.Register16 // 0xA
	INTFLAG   volatile.Register16 // 0xC
	DBGCTRL   volatile.Register8  // 0xE
	_         byte
	SYNCBUSY  volatile.Register32 // 0x10
	FREQCORR  volatile.Register8  // 0x14
	_         [3]byte
	COUNT     volatile.Register32 // 0x18
	_         [4]byte
	COMP      [2]volatile.Register32 // 0x20
	_         [24]byte
	GP        [4]volatile.Register32 // 0x40
	_         [16]byte
	TAMPCTRL  volatile.Register32 // 0x60
	TIMESTAMP volatile.Register32 // 0x64
	TAMPID    volatile.Register32 // 0x68
	_         [20]byte
	BKUP      [8]volatile.Register32 // 0x80
}

// Real-Time Counter - MODE1
type RTC_MODE1_Type struct {
	CTRLA     volatile.Register16 // 0x0
	CTRLB     volatile.Register16 // 0x2
	EVCTRL    volatile.Register32 // 0x4
	INTENCLR  volatile.Register16 // 0x8
	INTENSET  volatile.Register16 // 0xA
	INTFLAG   volatile.Register16 // 0xC
	DBGCTRL   volatile.Register8  // 0xE
	_         byte
	SYNCBUSY  volatile.Register32 // 0x10
	FREQCORR  volatile.Register8  // 0x14
	_         [3]byte
	COUNT     volatile.Register16 // 0x18
	_         [2]byte
	PER       volatile.Register16 // 0x1C
	_         [2]byte
	COMP      [4]volatile.Register16 // 0x20
	_         [24]byte
	GP        [4]volatile.Register32 // 0x40
	_         [16]byte
	TAMPCTRL  volatile.Register32 // 0x60
	TIMESTAMP volatile.Register32 // 0x64
	TAMPID    volatile.Register32 // 0x68
	_         [20]byte
	BKUP      [8]volatile.Register32 // 0x80
}

// Real-Time Counter - MODE2
type RTC_MODE2_Type struct {
	CTRLA     volatile.Register16 // 0x0
	CTRLB     volatile.Register16 // 0x2
	EVCTRL    volatile.Register32 // 0x4
	INTENCLR  volatile.Register16 // 0x8
	INTENSET  volatile.Register16 // 0xA
	INTFLAG   volatile.Register16 // 0xC
	DBGCTRL   volatile.Register8  // 0xE
	_         byte
	SYNCBUSY  volatile.Register32 // 0x10
	FREQCORR  volatile.Register8  // 0x14
	_         [3]byte
	CLOCK     volatile.Register32 // 0x18
	_         [4]byte
	ALARM0    volatile.Register32 // 0x20
	MASK0     volatile.Register8  // 0x24
	_         [3]byte
	ALARM1    volatile.Register32 // 0x28
	MASK1     volatile.Register8  // 0x2C
	_         [19]byte
	GP        [4]volatile.Register32 // 0x40
	_         [16]byte
	TAMPCTRL  volatile.Register32 // 0x60
	TIMESTAMP volatile.Register32 // 0x64
	TAMPID    volatile.Register32 // 0x68
	_         [20]byte
	BKUP      [8]volatile.Register32 // 0x80
}

// SD/MMC Host Controller
type SDHC_Type struct {
	SSAR    volatile.Register32    // 0x0
	BSR     volatile.Register16    // 0x4
	BCR     volatile.Register16    // 0x6
	ARG1R   volatile.Register32    // 0x8
	TMR     volatile.Register16    // 0xC
	CR      volatile.Register16    // 0xE
	RR      [4]volatile.Register32 // 0x10
	BDPR    volatile.Register32    // 0x20
	PSR     volatile.Register32    // 0x24
	HC1R    volatile.Register8     // 0x28
	PCR     volatile.Register8     // 0x29
	BGCR    volatile.Register8     // 0x2A
	WCR     volatile.Register8     // 0x2B
	CCR     volatile.Register16    // 0x2C
	TCR     volatile.Register8     // 0x2E
	SRR     volatile.Register8     // 0x2F
	NISTR   volatile.Register16    // 0x30
	EISTR   volatile.Register16    // 0x32
	NISTER  volatile.Register16    // 0x34
	EISTER  volatile.Register16    // 0x36
	NISIER  volatile.Register16    // 0x38
	EISIER  volatile.Register16    // 0x3A
	ACESR   volatile.Register16    // 0x3C
	HC2R    volatile.Register16    // 0x3E
	CA0R    volatile.Register32    // 0x40
	CA1R    volatile.Register32    // 0x44
	MCCAR   volatile.Register32    // 0x48
	_       [4]byte
	FERACES volatile.Register16 // 0x50
	FEREIS  volatile.Register16 // 0x52
	AESR    volatile.Register8  // 0x54
	_       [3]byte
	ASAR    [1]volatile.Register32 // 0x58
	_       [4]byte
	PVR     [8]volatile.Register16 // 0x60
	_       [140]byte
	SISR    volatile.Register16 // 0xFC
	HCVR    volatile.Register16 // 0xFE
	_       [260]byte
	MC1R    volatile.Register8 // 0x204
	MC2R    volatile.Register8 // 0x205
	_       [2]byte
	ACR     volatile.Register32 // 0x208
	CC2R    volatile.Register32 // 0x20C
	_       [32]byte
	CACR    volatile.Register32 // 0x230
	DBGR    volatile.Register8  // 0x234
}

// Serial Communication Interface
type SERCOM_Type struct {
}

// Serial Communication Interface - I2CM
type SERCOM_I2CM_Type struct {
	CTRLA    volatile.Register32 // 0x0
	CTRLB    volatile.Register32 // 0x4
	CTRLC    volatile.Register32 // 0x8
	BAUD     volatile.Register32 // 0xC
	_        [4]byte
	INTENCLR volatile.Register8 // 0x14
	_        byte
	INTENSET volatile.Register8 // 0x16
	_        byte
	INTFLAG  volatile.Register8 // 0x18
	_        byte
	STATUS   volatile.Register16 // 0x1A
	SYNCBUSY volatile.Register32 // 0x1C
	_        [4]byte
	ADDR     volatile.Register32 // 0x24
	DATA     volatile.Register8  // 0x28
	_        [7]byte
	DBGCTRL  volatile.Register8 // 0x30
}

// Serial Communication Interface - I2CS
type SERCOM_I2CS_Type struct {
	CTRLA    volatile.Register32 // 0x0
	CTRLB    volatile.Register32 // 0x4
	CTRLC    volatile.Register32 // 0x8
	_        [8]byte
	INTENCLR volatile.Register8 // 0x14
	_        byte
	INTENSET volatile.Register8 // 0x16
	_        byte
	INTFLAG  volatile.Register8 // 0x18
	_        byte
	STATUS   volatile.Register16 // 0x1A
	SYNCBUSY volatile.Register32 // 0x1C
	_        [2]byte
	LENGTH   volatile.Register16 // 0x22
	ADDR     volatile.Register32 // 0x24
	DATA     volatile.Register32 // 0x28
}

// Serial Communication Interface - SPIS
type SERCOM_SPIS_Type struct {
	CTRLA    volatile.Register32 // 0x0
	CTRLB    volatile.Register32 // 0x4
	CTRLC    volatile.Register32 // 0x8
	BAUD     volatile.Register8  // 0xC
	_        [7]byte
	INTENCLR volatile.Register8 // 0x14
	_        byte
	INTENSET volatile.Register8 // 0x16
	_        byte
	INTFLAG  volatile.Register8 // 0x18
	_        byte
	STATUS   volatile.Register16 // 0x1A
	SYNCBUSY volatile.Register32 // 0x1C
	_        [2]byte
	LENGTH   volatile.Register16 // 0x22
	ADDR     volatile.Register32 // 0x24
	DATA     volatile.Register32 // 0x28
	_        [4]byte
	DBGCTRL  volatile.Register8 // 0x30
}

// Serial Communication Interface - SPIM
type SERCOM_SPIM_Type struct {
	CTRLA    volatile.Register32 // 0x0
	CTRLB    volatile.Register32 // 0x4
	CTRLC    volatile.Register32 // 0x8
	BAUD     volatile.Register8  // 0xC
	_        [7]byte
	INTENCLR volatile.Register8 // 0x14
	_        byte
	INTENSET volatile.Register8 // 0x16
	_        byte
	INTFLAG  volatile.Register8 // 0x18
	_        byte
	STATUS   volatile.Register16 // 0x1A
	SYNCBUSY volatile.Register32 // 0x1C
	_        [2]byte
	LENGTH   volatile.Register16 // 0x22
	ADDR     volatile.Register32 // 0x24
	DATA     volatile.Register32 // 0x28
	_        [4]byte
	DBGCTRL  volatile.Register8 // 0x30
}

// Serial Communication Interface - USART_EXT
type SERCOM_USART_EXT_Type struct {
	CTRLA    volatile.Register32 // 0x0
	CTRLB    volatile.Register32 // 0x4
	CTRLC    volatile.Register32 // 0x8
	BAUD     volatile.Register16 // 0xC
	RXPL     volatile.Register8  // 0xE
	_        [5]byte
	INTENCLR volatile.Register8 // 0x14
	_        byte
	INTENSET volatile.Register8 // 0x16
	_        byte
	INTFLAG  volatile.Register8 // 0x18
	_        byte
	STATUS   volatile.Register16 // 0x1A
	SYNCBUSY volatile.Register32 // 0x1C
	RXERRCNT volatile.Register8  // 0x20
	_        byte
	LENGTH   volatile.Register16 // 0x22
	_        [4]byte
	DATA     volatile.Register32 // 0x28
	_        [4]byte
	DBGCTRL  volatile.Register8 // 0x30
}

// Serial Communication Interface - USART_INT
type SERCOM_USART_INT_Type struct {
	CTRLA    volatile.Register32 // 0x0
	CTRLB    volatile.Register32 // 0x4
	CTRLC    volatile.Register32 // 0x8
	BAUD     volatile.Register16 // 0xC
	RXPL     volatile.Register8  // 0xE
	_        [5]byte
	INTENCLR volatile.Register8 // 0x14
	_        byte
	INTENSET volatile.Register8 // 0x16
	_        byte
	INTFLAG  volatile.Register8 // 0x18
	_        byte
	STATUS   volatile.Register16 // 0x1A
	SYNCBUSY volatile.Register32 // 0x1C
	RXERRCNT volatile.Register8  // 0x20
	_        byte
	LENGTH   volatile.Register16 // 0x22
	_        [4]byte
	DATA     volatile.Register32 // 0x28
	_        [4]byte
	DBGCTRL  volatile.Register8 // 0x30
}

// Supply Controller
type SUPC_Type struct {
	INTENCLR volatile.Register32 // 0x0
	INTENSET volatile.Register32 // 0x4
	INTFLAG  volatile.Register32 // 0x8
	STATUS   volatile.Register32 // 0xC
	BOD33    volatile.Register32 // 0x10
	_        [4]byte
	VREG     volatile.Register32 // 0x18
	VREF     volatile.Register32 // 0x1C
	BBPS     volatile.Register32 // 0x20
	BKOUT    volatile.Register32 // 0x24
	BKIN     volatile.Register32 // 0x28
}

// Basic Timer Counter
type TC_Type struct {
}

// Basic Timer Counter - COUNT8
type TC_COUNT8_Type struct {
	CTRLA    volatile.Register32 // 0x0
	CTRLBCLR volatile.Register8  // 0x4
	CTRLBSET volatile.Register8  // 0x5
	EVCTRL   volatile.Register16 // 0x6
	INTENCLR volatile.Register8  // 0x8
	INTENSET volatile.Register8  // 0x9
	INTFLAG  volatile.Register8  // 0xA
	STATUS   volatile.Register8  // 0xB
	WAVE     volatile.Register8  // 0xC
	DRVCTRL  volatile.Register8  // 0xD
	_        byte
	DBGCTRL  volatile.Register8  // 0xF
	SYNCBUSY volatile.Register32 // 0x10
	COUNT    volatile.Register8  // 0x14
	_        [6]byte
	PER      volatile.Register8    // 0x1B
	CC       [2]volatile.Register8 // 0x1C
	_        [17]byte
	PERBUF   volatile.Register8    // 0x2F
	CCBUF    [2]volatile.Register8 // 0x30
}

// Basic Timer Counter - COUNT16
type TC_COUNT16_Type struct {
	CTRLA    volatile.Register32 // 0x0
	CTRLBCLR volatile.Register8  // 0x4
	CTRLBSET volatile.Register8  // 0x5
	EVCTRL   volatile.Register16 // 0x6
	INTENCLR volatile.Register8  // 0x8
	INTENSET volatile.Register8  // 0x9
	INTFLAG  volatile.Register8  // 0xA
	STATUS   volatile.Register8  // 0xB
	WAVE     volatile.Register8  // 0xC
	DRVCTRL  volatile.Register8  // 0xD
	_        byte
	DBGCTRL  volatile.Register8  // 0xF
	SYNCBUSY volatile.Register32 // 0x10
	COUNT    volatile.Register16 // 0x14
	_        [6]byte
	CC       [2]volatile.Register16 // 0x1C
	_        [16]byte
	CCBUF    [2]volatile.Register16 // 0x30
}

// Basic Timer Counter - COUNT32
type TC_COUNT32_Type struct {
	CTRLA    volatile.Register32 // 0x0
	CTRLBCLR volatile.Register8  // 0x4
	CTRLBSET volatile.Register8  // 0x5
	EVCTRL   volatile.Register16 // 0x6
	INTENCLR volatile.Register8  // 0x8
	INTENSET volatile.Register8  // 0x9
	INTFLAG  volatile.Register8  // 0xA
	STATUS   volatile.Register8  // 0xB
	WAVE     volatile.Register8  // 0xC
	DRVCTRL  volatile.Register8  // 0xD
	_        byte
	DBGCTRL  volatile.Register8  // 0xF
	SYNCBUSY volatile.Register32 // 0x10
	COUNT    volatile.Register32 // 0x14
	_        [4]byte
	CC       [2]volatile.Register32 // 0x1C
	_        [12]byte
	CCBUF    [2]volatile.Register32 // 0x30
}

// Timer Counter Control
type TCC_Type struct {
	CTRLA    volatile.Register32 // 0x0
	CTRLBCLR volatile.Register8  // 0x4
	CTRLBSET volatile.Register8  // 0x5
	_        [2]byte
	SYNCBUSY volatile.Register32 // 0x8
	FCTRLA   volatile.Register32 // 0xC
	FCTRLB   volatile.Register32 // 0x10
	WEXCTRL  volatile.Register32 // 0x14
	DRVCTRL  volatile.Register32 // 0x18
	_        [2]byte
	DBGCTRL  volatile.Register8 // 0x1E
	_        byte
	EVCTRL   volatile.Register32 // 0x20
	INTENCLR volatile.Register32 // 0x24
	INTENSET volatile.Register32 // 0x28
	INTFLAG  volatile.Register32 // 0x2C
	STATUS   volatile.Register32 // 0x30
	COUNT    volatile.Register32 // 0x34
	PATT     volatile.Register16 // 0x38
	_        [2]byte
	WAVE     volatile.Register32    // 0x3C
	PER      volatile.Register32    // 0x40
	CC       [6]volatile.Register32 // 0x44
	_        [8]byte
	PATTBUF  volatile.Register16 // 0x64
	_        [6]byte
	PERBUF   volatile.Register32    // 0x6C
	CCBUF    [6]volatile.Register32 // 0x70
}

// True Random Generator
type TRNG_Type struct {
	CTRLA    volatile.Register8 // 0x0
	_        [3]byte
	EVCTRL   volatile.Register8 // 0x4
	_        [3]byte
	INTENCLR volatile.Register8 // 0x8
	INTENSET volatile.Register8 // 0x9
	INTFLAG  volatile.Register8 // 0xA
	_        [21]byte
	DATA     volatile.Register32 // 0x20
}

// Universal Serial Bus
type USB_Type struct {
}

// Universal Serial Bus - DEVICE
type USB_DEVICE_Type struct {
	CTRLA           volatile.Register8 // 0x0
	_               byte
	SYNCBUSY        volatile.Register8 // 0x2
	QOSCTRL         volatile.Register8 // 0x3
	_               [4]byte
	CTRLB           volatile.Register16 // 0x8
	DADD            volatile.Register8  // 0xA
	_               byte
	STATUS          volatile.Register8 // 0xC
	FSMSTATUS       volatile.Register8 // 0xD
	_               [2]byte
	FNUM            volatile.Register16 // 0x10
	_               [2]byte
	INTENCLR        volatile.Register16 // 0x14
	_               [2]byte
	INTENSET        volatile.Register16 // 0x18
	_               [2]byte
	INTFLAG         volatile.Register16 // 0x1C
	_               [2]byte
	EPINTSMRY       volatile.Register16 // 0x20
	_               [2]byte
	DESCADD         volatile.Register32 // 0x24
	PADCAL          volatile.Register16 // 0x28
	_               [214]byte
	DEVICE_ENDPOINT [8]struct {
		EPCFG       volatile.Register8
		_           [3]byte
		EPSTATUSCLR volatile.Register8
		EPSTATUSSET volatile.Register8
		EPSTATUS    volatile.Register8
		EPINTFLAG   volatile.Register8
		EPINTENCLR  volatile.Register8
		EPINTENSET  volatile.Register8
		_           [22]byte
	} // 0x100
}

// Universal Serial Bus - HOST
type USB_HOST_Type struct {
	CTRLA     volatile.Register8 // 0x0
	_         byte
	SYNCBUSY  volatile.Register8 // 0x2
	QOSCTRL   volatile.Register8 // 0x3
	_         [4]byte
	CTRLB     volatile.Register16 // 0x8
	HSOFC     volatile.Register8  // 0xA
	_         byte
	STATUS    volatile.Register8 // 0xC
	FSMSTATUS volatile.Register8 // 0xD
	_         [2]byte
	FNUM      volatile.Register16 // 0x10
	FLENHIGH  volatile.Register8  // 0x12
	_         byte
	INTENCLR  volatile.Register16 // 0x14
	_         [2]byte
	INTENSET  volatile.Register16 // 0x18
	_         [2]byte
	INTFLAG   volatile.Register16 // 0x1C
	_         [2]byte
	PINTSMRY  volatile.Register16 // 0x20
	_         [2]byte
	DESCADD   volatile.Register32 // 0x24
	PADCAL    volatile.Register16 // 0x28
	_         [214]byte
	HOST_PIPE [8]struct {
		PCFG       volatile.Register8
		_          [2]byte
		BINTERVAL  volatile.Register8
		PSTATUSCLR volatile.Register8
		PSTATUSSET volatile.Register8
		PSTATUS    volatile.Register8
		PINTFLAG   volatile.Register8
		PINTENCLR  volatile.Register8
		PINTENSET  volatile.Register8
		_          [22]byte
	} // 0x100
}

// Watchdog Timer
type WDT_Type struct {
	CTRLA    volatile.Register8 // 0x0
	CONFIG   volatile.Register8 // 0x1
	EWCTRL   volatile.Register8 // 0x2
	_        byte
	INTENCLR volatile.Register8 // 0x4
	INTENSET volatile.Register8 // 0x5
	INTFLAG  volatile.Register8 // 0x6
	_        byte
	SYNCBUSY volatile.Register32 // 0x8
	CLEAR    volatile.Register8  // 0xC
}

// Core Debug Register
type CoreDebug_Type struct {
	DHCSR volatile.Register32 // 0x0
	DCRSR volatile.Register32 // 0x4
	DCRDR volatile.Register32 // 0x8
	DEMCR volatile.Register32 // 0xC
}

// Data Watchpoint and Trace Register
type DWT_Type struct {
	CTRL      volatile.Register32 // 0x0
	CYCCNT    volatile.Register32 // 0x4
	CPICNT    volatile.Register32 // 0x8
	EXCCNT    volatile.Register32 // 0xC
	SLEEPCNT  volatile.Register32 // 0x10
	LSUCNT    volatile.Register32 // 0x14
	FOLDCNT   volatile.Register32 // 0x18
	PCSR      volatile.Register32 // 0x1C
	COMP0     volatile.Register32 // 0x20
	MASK0     volatile.Register32 // 0x24
	FUNCTION0 volatile.Register32 // 0x28
	_         [4]byte
	COMP1     volatile.Register32 // 0x30
	MASK1     volatile.Register32 // 0x34
	FUNCTION1 volatile.Register32 // 0x38
	_         [4]byte
	COMP2     volatile.Register32 // 0x40
	MASK2     volatile.Register32 // 0x44
	FUNCTION2 volatile.Register32 // 0x48
	_         [4]byte
	COMP3     volatile.Register32 // 0x50
	MASK3     volatile.Register32 // 0x54
	FUNCTION3 volatile.Register32 // 0x58
}

// Embedded Trace Macrocell
type ETM_Type struct {
	CR         volatile.Register32 // 0x0
	CCR        volatile.Register32 // 0x4
	TRIGGER    volatile.Register32 // 0x8
	_          [4]byte
	SR         volatile.Register32 // 0x10
	SCR        volatile.Register32 // 0x14
	_          [8]byte
	TEEVR      volatile.Register32 // 0x20
	TECR1      volatile.Register32 // 0x24
	FFLR       volatile.Register32 // 0x28
	_          [276]byte
	CNTRLDVR1  volatile.Register32 // 0x140
	_          [156]byte
	SYNCFR     volatile.Register32 // 0x1E0
	IDR        volatile.Register32 // 0x1E4
	CCER       volatile.Register32 // 0x1E8
	_          [4]byte
	TESSEICR   volatile.Register32 // 0x1F0
	_          [4]byte
	TSEVT      volatile.Register32 // 0x1F8
	_          [4]byte
	TRACEIDR   volatile.Register32 // 0x200
	_          [4]byte
	IDR2       volatile.Register32 // 0x208
	_          [264]byte
	PDSR       volatile.Register32 // 0x314
	_          [3016]byte
	ITMISCIN   volatile.Register32 // 0xEE0
	_          [4]byte
	ITTRIGOUT  volatile.Register32 // 0xEE8
	_          [4]byte
	ITATBCTR2  volatile.Register32 // 0xEF0
	_          [4]byte
	ITATBCTR0  volatile.Register32 // 0xEF8
	_          [4]byte
	ITCTRL     volatile.Register32 // 0xF00
	_          [156]byte
	CLAIMSET   volatile.Register32 // 0xFA0
	CLAIMCLR   volatile.Register32 // 0xFA4
	_          [8]byte
	LAR        volatile.Register32 // 0xFB0
	LSR        volatile.Register32 // 0xFB4
	AUTHSTATUS volatile.Register32 // 0xFB8
	_          [16]byte
	DEVTYPE    volatile.Register32 // 0xFCC
	PIDR4      volatile.Register32 // 0xFD0
	PIDR5      volatile.Register32 // 0xFD4
	PIDR6      volatile.Register32 // 0xFD8
	PIDR7      volatile.Register32 // 0xFDC
	PIDR0      volatile.Register32 // 0xFE0
	PIDR1      volatile.Register32 // 0xFE4
	PIDR2      volatile.Register32 // 0xFE8
	PIDR3      volatile.Register32 // 0xFEC
	CIDR0      volatile.Register32 // 0xFF0
	CIDR1      volatile.Register32 // 0xFF4
	CIDR2      volatile.Register32 // 0xFF8
	CIDR3      volatile.Register32 // 0xFFC
}

// Floating Point Unit
type FPU_Type struct {
	_      [4]byte
	FPCCR  volatile.Register32 // 0x4
	FPCAR  volatile.Register32 // 0x8
	FPDSCR volatile.Register32 // 0xC
	MVFR0  volatile.Register32 // 0x10
	MVFR1  volatile.Register32 // 0x14
}

// Instrumentation Trace Macrocell
type ITM_Type struct {
	PORT_WORD_MODE [32]volatile.Register32 // 0x0
	_              [3456]byte
	TER            volatile.Register32 // 0xE00
	_              [60]byte
	TPR            volatile.Register32 // 0xE40
	_              [60]byte
	TCR            volatile.Register32 // 0xE80
	_              [116]byte
	IWR            volatile.Register32 // 0xEF8
	IRR            volatile.Register32 // 0xEFC
}

// Memory Protection Unit
type MPU_Type struct {
	TYPE    volatile.Register32 // 0x0
	CTRL    volatile.Register32 // 0x4
	RNR     volatile.Register32 // 0x8
	RBAR    volatile.Register32 // 0xC
	RASR    volatile.Register32 // 0x10
	RBAR_A1 volatile.Register32 // 0x14
	RASR_A1 volatile.Register32 // 0x18
	RBAR_A2 volatile.Register32 // 0x1C
	RASR_A2 volatile.Register32 // 0x20
	RBAR_A3 volatile.Register32 // 0x24
	RASR_A3 volatile.Register32 // 0x28
}

// Nested Vectored Interrupt Controller
type NVIC_Type struct {
	ISER [5]volatile.Register32 // 0x0
	_    [108]byte
	ICER [5]volatile.Register32 // 0x80
	_    [108]byte
	ISPR [5]volatile.Register32 // 0x100
	_    [108]byte
	ICPR [5]volatile.Register32 // 0x180
	_    [108]byte
	IABR [5]volatile.Register32 // 0x200
	_    [236]byte
	IP   [35]volatile.Register8 // 0x300
	_    [2781]byte
	STIR volatile.Register32 // 0xE00
}

// System timer
type SysTick_Type struct {
	CSR   volatile.Register32 // 0x0
	RVR   volatile.Register32 // 0x4
	CVR   volatile.Register32 // 0x8
	CALIB volatile.Register32 // 0xC
}

// System Control Registers
type SystemControl_Type struct {
	_     [4]byte
	ICTR  volatile.Register32 // 0x4
	ACTLR volatile.Register32 // 0x8
	_     [3316]byte
	CPUID volatile.Register32    // 0xD00
	ICSR  volatile.Register32    // 0xD04
	VTOR  volatile.Register32    // 0xD08
	AIRCR volatile.Register32    // 0xD0C
	SCR   volatile.Register32    // 0xD10
	CCR   volatile.Register32    // 0xD14
	SHPR1 volatile.Register32    // 0xD18
	SHPR2 volatile.Register32    // 0xD1C
	SHPR3 volatile.Register32    // 0xD20
	SHCSR volatile.Register32    // 0xD24
	CFSR  volatile.Register32    // 0xD28
	HFSR  volatile.Register32    // 0xD2C
	DFSR  volatile.Register32    // 0xD30
	MMFAR volatile.Register32    // 0xD34
	BFAR  volatile.Register32    // 0xD38
	AFSR  volatile.Register32    // 0xD3C
	PFR   [2]volatile.Register32 // 0xD40
	DFR   volatile.Register32    // 0xD48
	ADR   volatile.Register32    // 0xD4C
	MMFR  [4]volatile.Register32 // 0xD50
	ISAR  [5]volatile.Register32 // 0xD60
	_     [20]byte
	CPACR volatile.Register32 // 0xD88
}

// Trace Port Interface Register
type TPI_Type struct {
	SSPSR     volatile.Register32 // 0x0
	CSPSR     volatile.Register32 // 0x4
	_         [8]byte
	ACPR      volatile.Register32 // 0x10
	_         [220]byte
	SPPR      volatile.Register32 // 0xF0
	_         [524]byte
	FFSR      volatile.Register32 // 0x300
	FFCR      volatile.Register32 // 0x304
	FSCR      volatile.Register32 // 0x308
	_         [3036]byte
	TRIGGER   volatile.Register32 // 0xEE8
	FIFO0     volatile.Register32 // 0xEEC
	ITATBCTR2 volatile.Register32 // 0xEF0
	_         [4]byte
	ITATBCTR0 volatile.Register32 // 0xEF8
	FIFO1     volatile.Register32 // 0xEFC
	ITCTRL    volatile.Register32 // 0xF00
	_         [156]byte
	CLAIMSET  volatile.Register32 // 0xFA0
	CLAIMCLR  volatile.Register32 // 0xFA4
	_         [32]byte
	DEVID     volatile.Register32 // 0xFC8
	DEVTYPE   volatile.Register32 // 0xFCC
}

// Bitfields for AC: Analog Comparators
const (
	// CTRLA: Control A
	AC_CTRLA_SWRST_Pos  = 0x0 // Position of SWRST field.
	AC_CTRLA_SWRST_Msk  = 0x1 // Bit mask of SWRST field.
	AC_CTRLA_SWRST      = 0x1 // Bit SWRST.
	AC_CTRLA_ENABLE_Pos = 0x1 // Position of ENABLE field.
	AC_CTRLA_ENABLE_Msk = 0x2 // Bit mask of ENABLE field.
	AC_CTRLA_ENABLE     = 0x2 // Bit ENABLE.

	// CTRLB: Control B
	AC_CTRLB_START0_Pos = 0x0 // Position of START0 field.
	AC_CTRLB_START0_Msk = 0x1 // Bit mask of START0 field.
	AC_CTRLB_START0     = 0x1 // Bit START0.
	AC_CTRLB_START1_Pos = 0x1 // Position of START1 field.
	AC_CTRLB_START1_Msk = 0x2 // Bit mask of START1 field.
	AC_CTRLB_START1     = 0x2 // Bit START1.

	// EVCTRL: Event Control
	AC_EVCTRL_COMPEO0_Pos = 0x0    // Position of COMPEO0 field.
	AC_EVCTRL_COMPEO0_Msk = 0x1    // Bit mask of COMPEO0 field.
	AC_EVCTRL_COMPEO0     = 0x1    // Bit COMPEO0.
	AC_EVCTRL_COMPEO1_Pos = 0x1    // Position of COMPEO1 field.
	AC_EVCTRL_COMPEO1_Msk = 0x2    // Bit mask of COMPEO1 field.
	AC_EVCTRL_COMPEO1     = 0x2    // Bit COMPEO1.
	AC_EVCTRL_WINEO0_Pos  = 0x4    // Position of WINEO0 field.
	AC_EVCTRL_WINEO0_Msk  = 0x10   // Bit mask of WINEO0 field.
	AC_EVCTRL_WINEO0      = 0x10   // Bit WINEO0.
	AC_EVCTRL_COMPEI0_Pos = 0x8    // Position of COMPEI0 field.
	AC_EVCTRL_COMPEI0_Msk = 0x100  // Bit mask of COMPEI0 field.
	AC_EVCTRL_COMPEI0     = 0x100  // Bit COMPEI0.
	AC_EVCTRL_COMPEI1_Pos = 0x9    // Position of COMPEI1 field.
	AC_EVCTRL_COMPEI1_Msk = 0x200  // Bit mask of COMPEI1 field.
	AC_EVCTRL_COMPEI1     = 0x200  // Bit COMPEI1.
	AC_EVCTRL_INVEI0_Pos  = 0xc    // Position of INVEI0 field.
	AC_EVCTRL_INVEI0_Msk  = 0x1000 // Bit mask of INVEI0 field.
	AC_EVCTRL_INVEI0      = 0x1000 // Bit INVEI0.
	AC_EVCTRL_INVEI1_Pos  = 0xd    // Position of INVEI1 field.
	AC_EVCTRL_INVEI1_Msk  = 0x2000 // Bit mask of INVEI1 field.
	AC_EVCTRL_INVEI1      = 0x2000 // Bit INVEI1.

	// INTENCLR: Interrupt Enable Clear
	AC_INTENCLR_COMP0_Pos = 0x0  // Position of COMP0 field.
	AC_INTENCLR_COMP0_Msk = 0x1  // Bit mask of COMP0 field.
	AC_INTENCLR_COMP0     = 0x1  // Bit COMP0.
	AC_INTENCLR_COMP1_Pos = 0x1  // Position of COMP1 field.
	AC_INTENCLR_COMP1_Msk = 0x2  // Bit mask of COMP1 field.
	AC_INTENCLR_COMP1     = 0x2  // Bit COMP1.
	AC_INTENCLR_WIN0_Pos  = 0x4  // Position of WIN0 field.
	AC_INTENCLR_WIN0_Msk  = 0x10 // Bit mask of WIN0 field.
	AC_INTENCLR_WIN0      = 0x10 // Bit WIN0.

	// INTENSET: Interrupt Enable Set
	AC_INTENSET_COMP0_Pos = 0x0  // Position of COMP0 field.
	AC_INTENSET_COMP0_Msk = 0x1  // Bit mask of COMP0 field.
	AC_INTENSET_COMP0     = 0x1  // Bit COMP0.
	AC_INTENSET_COMP1_Pos = 0x1  // Position of COMP1 field.
	AC_INTENSET_COMP1_Msk = 0x2  // Bit mask of COMP1 field.
	AC_INTENSET_COMP1     = 0x2  // Bit COMP1.
	AC_INTENSET_WIN0_Pos  = 0x4  // Position of WIN0 field.
	AC_INTENSET_WIN0_Msk  = 0x10 // Bit mask of WIN0 field.
	AC_INTENSET_WIN0      = 0x10 // Bit WIN0.

	// INTFLAG: Interrupt Flag Status and Clear
	AC_INTFLAG_COMP0_Pos = 0x0  // Position of COMP0 field.
	AC_INTFLAG_COMP0_Msk = 0x1  // Bit mask of COMP0 field.
	AC_INTFLAG_COMP0     = 0x1  // Bit COMP0.
	AC_INTFLAG_COMP1_Pos = 0x1  // Position of COMP1 field.
	AC_INTFLAG_COMP1_Msk = 0x2  // Bit mask of COMP1 field.
	AC_INTFLAG_COMP1     = 0x2  // Bit COMP1.
	AC_INTFLAG_WIN0_Pos  = 0x4  // Position of WIN0 field.
	AC_INTFLAG_WIN0_Msk  = 0x10 // Bit mask of WIN0 field.
	AC_INTFLAG_WIN0      = 0x10 // Bit WIN0.

	// STATUSA: Status A
	AC_STATUSA_STATE0_Pos     = 0x0  // Position of STATE0 field.
	AC_STATUSA_STATE0_Msk     = 0x1  // Bit mask of STATE0 field.
	AC_STATUSA_STATE0         = 0x1  // Bit STATE0.
	AC_STATUSA_STATE1_Pos     = 0x1  // Position of STATE1 field.
	AC_STATUSA_STATE1_Msk     = 0x2  // Bit mask of STATE1 field.
	AC_STATUSA_STATE1         = 0x2  // Bit STATE1.
	AC_STATUSA_WSTATE0_Pos    = 0x4  // Position of WSTATE0 field.
	AC_STATUSA_WSTATE0_Msk    = 0x30 // Bit mask of WSTATE0 field.
	AC_STATUSA_WSTATE0_ABOVE  = 0x0  // Signal is above window
	AC_STATUSA_WSTATE0_INSIDE = 0x1  // Signal is inside window
	AC_STATUSA_WSTATE0_BELOW  = 0x2  // Signal is below window

	// STATUSB: Status B
	AC_STATUSB_READY0_Pos = 0x0 // Position of READY0 field.
	AC_STATUSB_READY0_Msk = 0x1 // Bit mask of READY0 field.
	AC_STATUSB_READY0     = 0x1 // Bit READY0.
	AC_STATUSB_READY1_Pos = 0x1 // Position of READY1 field.
	AC_STATUSB_READY1_Msk = 0x2 // Bit mask of READY1 field.
	AC_STATUSB_READY1     = 0x2 // Bit READY1.

	// DBGCTRL: Debug Control
	AC_DBGCTRL_DBGRUN_Pos = 0x0 // Position of DBGRUN field.
	AC_DBGCTRL_DBGRUN_Msk = 0x1 // Bit mask of DBGRUN field.
	AC_DBGCTRL_DBGRUN     = 0x1 // Bit DBGRUN.

	// WINCTRL: Window Control
	AC_WINCTRL_WEN0_Pos         = 0x0 // Position of WEN0 field.
	AC_WINCTRL_WEN0_Msk         = 0x1 // Bit mask of WEN0 field.
	AC_WINCTRL_WEN0             = 0x1 // Bit WEN0.
	AC_WINCTRL_WINTSEL0_Pos     = 0x1 // Position of WINTSEL0 field.
	AC_WINCTRL_WINTSEL0_Msk     = 0x6 // Bit mask of WINTSEL0 field.
	AC_WINCTRL_WINTSEL0_ABOVE   = 0x0 // Interrupt on signal above window
	AC_WINCTRL_WINTSEL0_INSIDE  = 0x1 // Interrupt on signal inside window
	AC_WINCTRL_WINTSEL0_BELOW   = 0x2 // Interrupt on signal below window
	AC_WINCTRL_WINTSEL0_OUTSIDE = 0x3 // Interrupt on signal outside window

	// SCALER: Scaler n
	AC_SCALER_VALUE_Pos = 0x0  // Position of VALUE field.
	AC_SCALER_VALUE_Msk = 0x3f // Bit mask of VALUE field.

	// COMPCTRL: Comparator Control n
	AC_COMPCTRL_ENABLE_Pos     = 0x1        // Position of ENABLE field.
	AC_COMPCTRL_ENABLE_Msk     = 0x2        // Bit mask of ENABLE field.
	AC_COMPCTRL_ENABLE         = 0x2        // Bit ENABLE.
	AC_COMPCTRL_SINGLE_Pos     = 0x2        // Position of SINGLE field.
	AC_COMPCTRL_SINGLE_Msk     = 0x4        // Bit mask of SINGLE field.
	AC_COMPCTRL_SINGLE         = 0x4        // Bit SINGLE.
	AC_COMPCTRL_INTSEL_Pos     = 0x3        // Position of INTSEL field.
	AC_COMPCTRL_INTSEL_Msk     = 0x18       // Bit mask of INTSEL field.
	AC_COMPCTRL_INTSEL_TOGGLE  = 0x0        // Interrupt on comparator output toggle
	AC_COMPCTRL_INTSEL_RISING  = 0x1        // Interrupt on comparator output rising
	AC_COMPCTRL_INTSEL_FALLING = 0x2        // Interrupt on comparator output falling
	AC_COMPCTRL_INTSEL_EOC     = 0x3        // Interrupt on end of comparison (single-shot mode only)
	AC_COMPCTRL_RUNSTDBY_Pos   = 0x6        // Position of RUNSTDBY field.
	AC_COMPCTRL_RUNSTDBY_Msk   = 0x40       // Bit mask of RUNSTDBY field.
	AC_COMPCTRL_RUNSTDBY       = 0x40       // Bit RUNSTDBY.
	AC_COMPCTRL_MUXNEG_Pos     = 0x8        // Position of MUXNEG field.
	AC_COMPCTRL_MUXNEG_Msk     = 0x700      // Bit mask of MUXNEG field.
	AC_COMPCTRL_MUXNEG_PIN0    = 0x0        // I/O pin 0
	AC_COMPCTRL_MUXNEG_PIN1    = 0x1        // I/O pin 1
	AC_COMPCTRL_MUXNEG_PIN2    = 0x2        // I/O pin 2
	AC_COMPCTRL_MUXNEG_PIN3    = 0x3        // I/O pin 3
	AC_COMPCTRL_MUXNEG_GND     = 0x4        // Ground
	AC_COMPCTRL_MUXNEG_VSCALE  = 0x5        // VDD scaler
	AC_COMPCTRL_MUXNEG_BANDGAP = 0x6        // Internal bandgap voltage
	AC_COMPCTRL_MUXNEG_DAC     = 0x7        // DAC output
	AC_COMPCTRL_MUXPOS_Pos     = 0xc        // Position of MUXPOS field.
	AC_COMPCTRL_MUXPOS_Msk     = 0x7000     // Bit mask of MUXPOS field.
	AC_COMPCTRL_MUXPOS_PIN0    = 0x0        // I/O pin 0
	AC_COMPCTRL_MUXPOS_PIN1    = 0x1        // I/O pin 1
	AC_COMPCTRL_MUXPOS_PIN2    = 0x2        // I/O pin 2
	AC_COMPCTRL_MUXPOS_PIN3    = 0x3        // I/O pin 3
	AC_COMPCTRL_MUXPOS_VSCALE  = 0x4        // VDD Scaler
	AC_COMPCTRL_SWAP_Pos       = 0xf        // Position of SWAP field.
	AC_COMPCTRL_SWAP_Msk       = 0x8000     // Bit mask of SWAP field.
	AC_COMPCTRL_SWAP           = 0x8000     // Bit SWAP.
	AC_COMPCTRL_SPEED_Pos      = 0x10       // Position of SPEED field.
	AC_COMPCTRL_SPEED_Msk      = 0x30000    // Bit mask of SPEED field.
	AC_COMPCTRL_SPEED_HIGH     = 0x3        // High speed
	AC_COMPCTRL_HYSTEN_Pos     = 0x13       // Position of HYSTEN field.
	AC_COMPCTRL_HYSTEN_Msk     = 0x80000    // Bit mask of HYSTEN field.
	AC_COMPCTRL_HYSTEN         = 0x80000    // Bit HYSTEN.
	AC_COMPCTRL_HYST_Pos       = 0x14       // Position of HYST field.
	AC_COMPCTRL_HYST_Msk       = 0x300000   // Bit mask of HYST field.
	AC_COMPCTRL_HYST_HYST50    = 0x0        // 50mV
	AC_COMPCTRL_HYST_HYST100   = 0x1        // 100mV
	AC_COMPCTRL_HYST_HYST150   = 0x2        // 150mV
	AC_COMPCTRL_FLEN_Pos       = 0x18       // Position of FLEN field.
	AC_COMPCTRL_FLEN_Msk       = 0x7000000  // Bit mask of FLEN field.
	AC_COMPCTRL_FLEN_OFF       = 0x0        // No filtering
	AC_COMPCTRL_FLEN_MAJ3      = 0x1        // 3-bit majority function (2 of 3)
	AC_COMPCTRL_FLEN_MAJ5      = 0x2        // 5-bit majority function (3 of 5)
	AC_COMPCTRL_OUT_Pos        = 0x1c       // Position of OUT field.
	AC_COMPCTRL_OUT_Msk        = 0x30000000 // Bit mask of OUT field.
	AC_COMPCTRL_OUT_OFF        = 0x0        // The output of COMPn is not routed to the COMPn I/O port
	AC_COMPCTRL_OUT_ASYNC      = 0x1        // The asynchronous output of COMPn is routed to the COMPn I/O port
	AC_COMPCTRL_OUT_SYNC       = 0x2        // The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port

	// SYNCBUSY: Synchronization Busy
	AC_SYNCBUSY_SWRST_Pos     = 0x0  // Position of SWRST field.
	AC_SYNCBUSY_SWRST_Msk     = 0x1  // Bit mask of SWRST field.
	AC_SYNCBUSY_SWRST         = 0x1  // Bit SWRST.
	AC_SYNCBUSY_ENABLE_Pos    = 0x1  // Position of ENABLE field.
	AC_SYNCBUSY_ENABLE_Msk    = 0x2  // Bit mask of ENABLE field.
	AC_SYNCBUSY_ENABLE        = 0x2  // Bit ENABLE.
	AC_SYNCBUSY_WINCTRL_Pos   = 0x2  // Position of WINCTRL field.
	AC_SYNCBUSY_WINCTRL_Msk   = 0x4  // Bit mask of WINCTRL field.
	AC_SYNCBUSY_WINCTRL       = 0x4  // Bit WINCTRL.
	AC_SYNCBUSY_COMPCTRL0_Pos = 0x3  // Position of COMPCTRL0 field.
	AC_SYNCBUSY_COMPCTRL0_Msk = 0x8  // Bit mask of COMPCTRL0 field.
	AC_SYNCBUSY_COMPCTRL0     = 0x8  // Bit COMPCTRL0.
	AC_SYNCBUSY_COMPCTRL1_Pos = 0x4  // Position of COMPCTRL1 field.
	AC_SYNCBUSY_COMPCTRL1_Msk = 0x10 // Bit mask of COMPCTRL1 field.
	AC_SYNCBUSY_COMPCTRL1     = 0x10 // Bit COMPCTRL1.

	// CALIB: Calibration
	AC_CALIB_BIAS0_Pos = 0x0 // Position of BIAS0 field.
	AC_CALIB_BIAS0_Msk = 0x3 // Bit mask of BIAS0 field.
)

// Bitfields for ADC0: Analog Digital Converter
const (
	// CTRLA: Control A
	ADC_CTRLA_SWRST_Pos          = 0x0    // Position of SWRST field.
	ADC_CTRLA_SWRST_Msk          = 0x1    // Bit mask of SWRST field.
	ADC_CTRLA_SWRST              = 0x1    // Bit SWRST.
	ADC_CTRLA_ENABLE_Pos         = 0x1    // Position of ENABLE field.
	ADC_CTRLA_ENABLE_Msk         = 0x2    // Bit mask of ENABLE field.
	ADC_CTRLA_ENABLE             = 0x2    // Bit ENABLE.
	ADC_CTRLA_DUALSEL_Pos        = 0x3    // Position of DUALSEL field.
	ADC_CTRLA_DUALSEL_Msk        = 0x18   // Bit mask of DUALSEL field.
	ADC_CTRLA_DUALSEL_BOTH       = 0x0    // Start event or software trigger will start a conversion on both ADCs
	ADC_CTRLA_DUALSEL_INTERLEAVE = 0x1    // START event or software trigger will alternatingly start a conversion on ADC0 and ADC1
	ADC_CTRLA_SLAVEEN_Pos        = 0x5    // Position of SLAVEEN field.
	ADC_CTRLA_SLAVEEN_Msk        = 0x20   // Bit mask of SLAVEEN field.
	ADC_CTRLA_SLAVEEN            = 0x20   // Bit SLAVEEN.
	ADC_CTRLA_RUNSTDBY_Pos       = 0x6    // Position of RUNSTDBY field.
	ADC_CTRLA_RUNSTDBY_Msk       = 0x40   // Bit mask of RUNSTDBY field.
	ADC_CTRLA_RUNSTDBY           = 0x40   // Bit RUNSTDBY.
	ADC_CTRLA_ONDEMAND_Pos       = 0x7    // Position of ONDEMAND field.
	ADC_CTRLA_ONDEMAND_Msk       = 0x80   // Bit mask of ONDEMAND field.
	ADC_CTRLA_ONDEMAND           = 0x80   // Bit ONDEMAND.
	ADC_CTRLA_PRESCALER_Pos      = 0x8    // Position of PRESCALER field.
	ADC_CTRLA_PRESCALER_Msk      = 0x700  // Bit mask of PRESCALER field.
	ADC_CTRLA_PRESCALER_DIV2     = 0x0    // Peripheral clock divided by 2
	ADC_CTRLA_PRESCALER_DIV4     = 0x1    // Peripheral clock divided by 4
	ADC_CTRLA_PRESCALER_DIV8     = 0x2    // Peripheral clock divided by 8
	ADC_CTRLA_PRESCALER_DIV16    = 0x3    // Peripheral clock divided by 16
	ADC_CTRLA_PRESCALER_DIV32    = 0x4    // Peripheral clock divided by 32
	ADC_CTRLA_PRESCALER_DIV64    = 0x5    // Peripheral clock divided by 64
	ADC_CTRLA_PRESCALER_DIV128   = 0x6    // Peripheral clock divided by 128
	ADC_CTRLA_PRESCALER_DIV256   = 0x7    // Peripheral clock divided by 256
	ADC_CTRLA_R2R_Pos            = 0xf    // Position of R2R field.
	ADC_CTRLA_R2R_Msk            = 0x8000 // Bit mask of R2R field.
	ADC_CTRLA_R2R                = 0x8000 // Bit R2R.

	// EVCTRL: Event Control
	ADC_EVCTRL_FLUSHEI_Pos  = 0x0  // Position of FLUSHEI field.
	ADC_EVCTRL_FLUSHEI_Msk  = 0x1  // Bit mask of FLUSHEI field.
	ADC_EVCTRL_FLUSHEI      = 0x1  // Bit FLUSHEI.
	ADC_EVCTRL_STARTEI_Pos  = 0x1  // Position of STARTEI field.
	ADC_EVCTRL_STARTEI_Msk  = 0x2  // Bit mask of STARTEI field.
	ADC_EVCTRL_STARTEI      = 0x2  // Bit STARTEI.
	ADC_EVCTRL_FLUSHINV_Pos = 0x2  // Position of FLUSHINV field.
	ADC_EVCTRL_FLUSHINV_Msk = 0x4  // Bit mask of FLUSHINV field.
	ADC_EVCTRL_FLUSHINV     = 0x4  // Bit FLUSHINV.
	ADC_EVCTRL_STARTINV_Pos = 0x3  // Position of STARTINV field.
	ADC_EVCTRL_STARTINV_Msk = 0x8  // Bit mask of STARTINV field.
	ADC_EVCTRL_STARTINV     = 0x8  // Bit STARTINV.
	ADC_EVCTRL_RESRDYEO_Pos = 0x4  // Position of RESRDYEO field.
	ADC_EVCTRL_RESRDYEO_Msk = 0x10 // Bit mask of RESRDYEO field.
	ADC_EVCTRL_RESRDYEO     = 0x10 // Bit RESRDYEO.
	ADC_EVCTRL_WINMONEO_Pos = 0x5  // Position of WINMONEO field.
	ADC_EVCTRL_WINMONEO_Msk = 0x20 // Bit mask of WINMONEO field.
	ADC_EVCTRL_WINMONEO     = 0x20 // Bit WINMONEO.

	// DBGCTRL: Debug Control
	ADC_DBGCTRL_DBGRUN_Pos = 0x0 // Position of DBGRUN field.
	ADC_DBGCTRL_DBGRUN_Msk = 0x1 // Bit mask of DBGRUN field.
	ADC_DBGCTRL_DBGRUN     = 0x1 // Bit DBGRUN.

	// INPUTCTRL: Input Control
	ADC_INPUTCTRL_MUXPOS_Pos           = 0x0    // Position of MUXPOS field.
	ADC_INPUTCTRL_MUXPOS_Msk           = 0x1f   // Bit mask of MUXPOS field.
	ADC_INPUTCTRL_MUXPOS_AIN0          = 0x0    // ADC AIN0 Pin
	ADC_INPUTCTRL_MUXPOS_AIN1          = 0x1    // ADC AIN1 Pin
	ADC_INPUTCTRL_MUXPOS_AIN2          = 0x2    // ADC AIN2 Pin
	ADC_INPUTCTRL_MUXPOS_AIN3          = 0x3    // ADC AIN3 Pin
	ADC_INPUTCTRL_MUXPOS_AIN4          = 0x4    // ADC AIN4 Pin
	ADC_INPUTCTRL_MUXPOS_AIN5          = 0x5    // ADC AIN5 Pin
	ADC_INPUTCTRL_MUXPOS_AIN6          = 0x6    // ADC AIN6 Pin
	ADC_INPUTCTRL_MUXPOS_AIN7          = 0x7    // ADC AIN7 Pin
	ADC_INPUTCTRL_MUXPOS_AIN8          = 0x8    // ADC AIN8 Pin
	ADC_INPUTCTRL_MUXPOS_AIN9          = 0x9    // ADC AIN9 Pin
	ADC_INPUTCTRL_MUXPOS_AIN10         = 0xa    // ADC AIN10 Pin
	ADC_INPUTCTRL_MUXPOS_AIN11         = 0xb    // ADC AIN11 Pin
	ADC_INPUTCTRL_MUXPOS_AIN12         = 0xc    // ADC AIN12 Pin
	ADC_INPUTCTRL_MUXPOS_AIN13         = 0xd    // ADC AIN13 Pin
	ADC_INPUTCTRL_MUXPOS_AIN14         = 0xe    // ADC AIN14 Pin
	ADC_INPUTCTRL_MUXPOS_AIN15         = 0xf    // ADC AIN15 Pin
	ADC_INPUTCTRL_MUXPOS_AIN16         = 0x10   // ADC AIN16 Pin
	ADC_INPUTCTRL_MUXPOS_AIN17         = 0x11   // ADC AIN17 Pin
	ADC_INPUTCTRL_MUXPOS_AIN18         = 0x12   // ADC AIN18 Pin
	ADC_INPUTCTRL_MUXPOS_AIN19         = 0x13   // ADC AIN19 Pin
	ADC_INPUTCTRL_MUXPOS_AIN20         = 0x14   // ADC AIN20 Pin
	ADC_INPUTCTRL_MUXPOS_AIN21         = 0x15   // ADC AIN21 Pin
	ADC_INPUTCTRL_MUXPOS_AIN22         = 0x16   // ADC AIN22 Pin
	ADC_INPUTCTRL_MUXPOS_AIN23         = 0x17   // ADC AIN23 Pin
	ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC = 0x18   // 1/4 Scaled Core Supply
	ADC_INPUTCTRL_MUXPOS_SCALEDVBAT    = 0x19   // 1/4 Scaled VBAT Supply
	ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC   = 0x1a   // 1/4 Scaled I/O Supply
	ADC_INPUTCTRL_MUXPOS_BANDGAP       = 0x1b   // Bandgap Voltage
	ADC_INPUTCTRL_MUXPOS_PTAT          = 0x1c   // Temperature Sensor
	ADC_INPUTCTRL_MUXPOS_CTAT          = 0x1d   // Temperature Sensor
	ADC_INPUTCTRL_MUXPOS_DAC           = 0x1e   // DAC Output
	ADC_INPUTCTRL_MUXPOS_PTC           = 0x1f   // PTC output (only on ADC0)
	ADC_INPUTCTRL_DIFFMODE_Pos         = 0x7    // Position of DIFFMODE field.
	ADC_INPUTCTRL_DIFFMODE_Msk         = 0x80   // Bit mask of DIFFMODE field.
	ADC_INPUTCTRL_DIFFMODE             = 0x80   // Bit DIFFMODE.
	ADC_INPUTCTRL_MUXNEG_Pos           = 0x8    // Position of MUXNEG field.
	ADC_INPUTCTRL_MUXNEG_Msk           = 0x1f00 // Bit mask of MUXNEG field.
	ADC_INPUTCTRL_MUXNEG_AIN0          = 0x0    // ADC AIN0 Pin
	ADC_INPUTCTRL_MUXNEG_AIN1          = 0x1    // ADC AIN1 Pin
	ADC_INPUTCTRL_MUXNEG_AIN2          = 0x2    // ADC AIN2 Pin
	ADC_INPUTCTRL_MUXNEG_AIN3          = 0x3    // ADC AIN3 Pin
	ADC_INPUTCTRL_MUXNEG_AIN4          = 0x4    // ADC AIN4 Pin
	ADC_INPUTCTRL_MUXNEG_AIN5          = 0x5    // ADC AIN5 Pin
	ADC_INPUTCTRL_MUXNEG_AIN6          = 0x6    // ADC AIN6 Pin
	ADC_INPUTCTRL_MUXNEG_AIN7          = 0x7    // ADC AIN7 Pin
	ADC_INPUTCTRL_MUXNEG_GND           = 0x18   // Internal Ground
	ADC_INPUTCTRL_DSEQSTOP_Pos         = 0xf    // Position of DSEQSTOP field.
	ADC_INPUTCTRL_DSEQSTOP_Msk         = 0x8000 // Bit mask of DSEQSTOP field.
	ADC_INPUTCTRL_DSEQSTOP             = 0x8000 // Bit DSEQSTOP.

	// CTRLB: Control B
	ADC_CTRLB_LEFTADJ_Pos     = 0x0   // Position of LEFTADJ field.
	ADC_CTRLB_LEFTADJ_Msk     = 0x1   // Bit mask of LEFTADJ field.
	ADC_CTRLB_LEFTADJ         = 0x1   // Bit LEFTADJ.
	ADC_CTRLB_FREERUN_Pos     = 0x1   // Position of FREERUN field.
	ADC_CTRLB_FREERUN_Msk     = 0x2   // Bit mask of FREERUN field.
	ADC_CTRLB_FREERUN         = 0x2   // Bit FREERUN.
	ADC_CTRLB_CORREN_Pos      = 0x2   // Position of CORREN field.
	ADC_CTRLB_CORREN_Msk      = 0x4   // Bit mask of CORREN field.
	ADC_CTRLB_CORREN          = 0x4   // Bit CORREN.
	ADC_CTRLB_RESSEL_Pos      = 0x3   // Position of RESSEL field.
	ADC_CTRLB_RESSEL_Msk      = 0x18  // Bit mask of RESSEL field.
	ADC_CTRLB_RESSEL_12BIT    = 0x0   // 12-bit result
	ADC_CTRLB_RESSEL_16BIT    = 0x1   // For averaging mode output
	ADC_CTRLB_RESSEL_10BIT    = 0x2   // 10-bit result
	ADC_CTRLB_RESSEL_8BIT     = 0x3   // 8-bit result
	ADC_CTRLB_WINMODE_Pos     = 0x8   // Position of WINMODE field.
	ADC_CTRLB_WINMODE_Msk     = 0x700 // Bit mask of WINMODE field.
	ADC_CTRLB_WINMODE_DISABLE = 0x0   // No window mode (default)
	ADC_CTRLB_WINMODE_MODE1   = 0x1   // RESULT > WINLT
	ADC_CTRLB_WINMODE_MODE2   = 0x2   // RESULT < WINUT
	ADC_CTRLB_WINMODE_MODE3   = 0x3   // WINLT < RESULT < WINUT
	ADC_CTRLB_WINMODE_MODE4   = 0x4   // !(WINLT < RESULT < WINUT)
	ADC_CTRLB_WINSS_Pos       = 0xb   // Position of WINSS field.
	ADC_CTRLB_WINSS_Msk       = 0x800 // Bit mask of WINSS field.
	ADC_CTRLB_WINSS           = 0x800 // Bit WINSS.

	// REFCTRL: Reference Control
	ADC_REFCTRL_REFSEL_Pos     = 0x0  // Position of REFSEL field.
	ADC_REFCTRL_REFSEL_Msk     = 0xf  // Bit mask of REFSEL field.
	ADC_REFCTRL_REFSEL_INTREF  = 0x0  // Internal Bandgap Reference
	ADC_REFCTRL_REFSEL_INTVCC0 = 0x2  // 1/2 VDDANA
	ADC_REFCTRL_REFSEL_INTVCC1 = 0x3  // VDDANA
	ADC_REFCTRL_REFSEL_AREFA   = 0x4  // External Reference
	ADC_REFCTRL_REFSEL_AREFB   = 0x5  // External Reference
	ADC_REFCTRL_REFSEL_AREFC   = 0x6  // External Reference (only on ADC1)
	ADC_REFCTRL_REFCOMP_Pos    = 0x7  // Position of REFCOMP field.
	ADC_REFCTRL_REFCOMP_Msk    = 0x80 // Bit mask of REFCOMP field.
	ADC_REFCTRL_REFCOMP        = 0x80 // Bit REFCOMP.

	// AVGCTRL: Average Control
	ADC_AVGCTRL_SAMPLENUM_Pos  = 0x0  // Position of SAMPLENUM field.
	ADC_AVGCTRL_SAMPLENUM_Msk  = 0xf  // Bit mask of SAMPLENUM field.
	ADC_AVGCTRL_SAMPLENUM_1    = 0x0  // 1 sample
	ADC_AVGCTRL_SAMPLENUM_2    = 0x1  // 2 samples
	ADC_AVGCTRL_SAMPLENUM_4    = 0x2  // 4 samples
	ADC_AVGCTRL_SAMPLENUM_8    = 0x3  // 8 samples
	ADC_AVGCTRL_SAMPLENUM_16   = 0x4  // 16 samples
	ADC_AVGCTRL_SAMPLENUM_32   = 0x5  // 32 samples
	ADC_AVGCTRL_SAMPLENUM_64   = 0x6  // 64 samples
	ADC_AVGCTRL_SAMPLENUM_128  = 0x7  // 128 samples
	ADC_AVGCTRL_SAMPLENUM_256  = 0x8  // 256 samples
	ADC_AVGCTRL_SAMPLENUM_512  = 0x9  // 512 samples
	ADC_AVGCTRL_SAMPLENUM_1024 = 0xa  // 1024 samples
	ADC_AVGCTRL_ADJRES_Pos     = 0x4  // Position of ADJRES field.
	ADC_AVGCTRL_ADJRES_Msk     = 0x70 // Bit mask of ADJRES field.

	// SAMPCTRL: Sample Time Control
	ADC_SAMPCTRL_SAMPLEN_Pos = 0x0  // Position of SAMPLEN field.
	ADC_SAMPCTRL_SAMPLEN_Msk = 0x3f // Bit mask of SAMPLEN field.
	ADC_SAMPCTRL_OFFCOMP_Pos = 0x7  // Position of OFFCOMP field.
	ADC_SAMPCTRL_OFFCOMP_Msk = 0x80 // Bit mask of OFFCOMP field.
	ADC_SAMPCTRL_OFFCOMP     = 0x80 // Bit OFFCOMP.

	// WINLT: Window Monitor Lower Threshold
	ADC_WINLT_WINLT_Pos = 0x0    // Position of WINLT field.
	ADC_WINLT_WINLT_Msk = 0xffff // Bit mask of WINLT field.

	// WINUT: Window Monitor Upper Threshold
	ADC_WINUT_WINUT_Pos = 0x0    // Position of WINUT field.
	ADC_WINUT_WINUT_Msk = 0xffff // Bit mask of WINUT field.

	// GAINCORR: Gain Correction
	ADC_GAINCORR_GAINCORR_Pos = 0x0   // Position of GAINCORR field.
	ADC_GAINCORR_GAINCORR_Msk = 0xfff // Bit mask of GAINCORR field.

	// OFFSETCORR: Offset Correction
	ADC_OFFSETCORR_OFFSETCORR_Pos = 0x0   // Position of OFFSETCORR field.
	ADC_OFFSETCORR_OFFSETCORR_Msk = 0xfff // Bit mask of OFFSETCORR field.

	// SWTRIG: Software Trigger
	ADC_SWTRIG_FLUSH_Pos = 0x0 // Position of FLUSH field.
	ADC_SWTRIG_FLUSH_Msk = 0x1 // Bit mask of FLUSH field.
	ADC_SWTRIG_FLUSH     = 0x1 // Bit FLUSH.
	ADC_SWTRIG_START_Pos = 0x1 // Position of START field.
	ADC_SWTRIG_START_Msk = 0x2 // Bit mask of START field.
	ADC_SWTRIG_START     = 0x2 // Bit START.

	// INTENCLR: Interrupt Enable Clear
	ADC_INTENCLR_RESRDY_Pos  = 0x0 // Position of RESRDY field.
	ADC_INTENCLR_RESRDY_Msk  = 0x1 // Bit mask of RESRDY field.
	ADC_INTENCLR_RESRDY      = 0x1 // Bit RESRDY.
	ADC_INTENCLR_OVERRUN_Pos = 0x1 // Position of OVERRUN field.
	ADC_INTENCLR_OVERRUN_Msk = 0x2 // Bit mask of OVERRUN field.
	ADC_INTENCLR_OVERRUN     = 0x2 // Bit OVERRUN.
	ADC_INTENCLR_WINMON_Pos  = 0x2 // Position of WINMON field.
	ADC_INTENCLR_WINMON_Msk  = 0x4 // Bit mask of WINMON field.
	ADC_INTENCLR_WINMON      = 0x4 // Bit WINMON.

	// INTENSET: Interrupt Enable Set
	ADC_INTENSET_RESRDY_Pos  = 0x0 // Position of RESRDY field.
	ADC_INTENSET_RESRDY_Msk  = 0x1 // Bit mask of RESRDY field.
	ADC_INTENSET_RESRDY      = 0x1 // Bit RESRDY.
	ADC_INTENSET_OVERRUN_Pos = 0x1 // Position of OVERRUN field.
	ADC_INTENSET_OVERRUN_Msk = 0x2 // Bit mask of OVERRUN field.
	ADC_INTENSET_OVERRUN     = 0x2 // Bit OVERRUN.
	ADC_INTENSET_WINMON_Pos  = 0x2 // Position of WINMON field.
	ADC_INTENSET_WINMON_Msk  = 0x4 // Bit mask of WINMON field.
	ADC_INTENSET_WINMON      = 0x4 // Bit WINMON.

	// INTFLAG: Interrupt Flag Status and Clear
	ADC_INTFLAG_RESRDY_Pos  = 0x0 // Position of RESRDY field.
	ADC_INTFLAG_RESRDY_Msk  = 0x1 // Bit mask of RESRDY field.
	ADC_INTFLAG_RESRDY      = 0x1 // Bit RESRDY.
	ADC_INTFLAG_OVERRUN_Pos = 0x1 // Position of OVERRUN field.
	ADC_INTFLAG_OVERRUN_Msk = 0x2 // Bit mask of OVERRUN field.
	ADC_INTFLAG_OVERRUN     = 0x2 // Bit OVERRUN.
	ADC_INTFLAG_WINMON_Pos  = 0x2 // Position of WINMON field.
	ADC_INTFLAG_WINMON_Msk  = 0x4 // Bit mask of WINMON field.
	ADC_INTFLAG_WINMON      = 0x4 // Bit WINMON.

	// STATUS: Status
	ADC_STATUS_ADCBUSY_Pos = 0x0  // Position of ADCBUSY field.
	ADC_STATUS_ADCBUSY_Msk = 0x1  // Bit mask of ADCBUSY field.
	ADC_STATUS_ADCBUSY     = 0x1  // Bit ADCBUSY.
	ADC_STATUS_WCC_Pos     = 0x2  // Position of WCC field.
	ADC_STATUS_WCC_Msk     = 0xfc // Bit mask of WCC field.

	// SYNCBUSY: Synchronization Busy
	ADC_SYNCBUSY_SWRST_Pos      = 0x0   // Position of SWRST field.
	ADC_SYNCBUSY_SWRST_Msk      = 0x1   // Bit mask of SWRST field.
	ADC_SYNCBUSY_SWRST          = 0x1   // Bit SWRST.
	ADC_SYNCBUSY_ENABLE_Pos     = 0x1   // Position of ENABLE field.
	ADC_SYNCBUSY_ENABLE_Msk     = 0x2   // Bit mask of ENABLE field.
	ADC_SYNCBUSY_ENABLE         = 0x2   // Bit ENABLE.
	ADC_SYNCBUSY_INPUTCTRL_Pos  = 0x2   // Position of INPUTCTRL field.
	ADC_SYNCBUSY_INPUTCTRL_Msk  = 0x4   // Bit mask of INPUTCTRL field.
	ADC_SYNCBUSY_INPUTCTRL      = 0x4   // Bit INPUTCTRL.
	ADC_SYNCBUSY_CTRLB_Pos      = 0x3   // Position of CTRLB field.
	ADC_SYNCBUSY_CTRLB_Msk      = 0x8   // Bit mask of CTRLB field.
	ADC_SYNCBUSY_CTRLB          = 0x8   // Bit CTRLB.
	ADC_SYNCBUSY_REFCTRL_Pos    = 0x4   // Position of REFCTRL field.
	ADC_SYNCBUSY_REFCTRL_Msk    = 0x10  // Bit mask of REFCTRL field.
	ADC_SYNCBUSY_REFCTRL        = 0x10  // Bit REFCTRL.
	ADC_SYNCBUSY_AVGCTRL_Pos    = 0x5   // Position of AVGCTRL field.
	ADC_SYNCBUSY_AVGCTRL_Msk    = 0x20  // Bit mask of AVGCTRL field.
	ADC_SYNCBUSY_AVGCTRL        = 0x20  // Bit AVGCTRL.
	ADC_SYNCBUSY_SAMPCTRL_Pos   = 0x6   // Position of SAMPCTRL field.
	ADC_SYNCBUSY_SAMPCTRL_Msk   = 0x40  // Bit mask of SAMPCTRL field.
	ADC_SYNCBUSY_SAMPCTRL       = 0x40  // Bit SAMPCTRL.
	ADC_SYNCBUSY_WINLT_Pos      = 0x7   // Position of WINLT field.
	ADC_SYNCBUSY_WINLT_Msk      = 0x80  // Bit mask of WINLT field.
	ADC_SYNCBUSY_WINLT          = 0x80  // Bit WINLT.
	ADC_SYNCBUSY_WINUT_Pos      = 0x8   // Position of WINUT field.
	ADC_SYNCBUSY_WINUT_Msk      = 0x100 // Bit mask of WINUT field.
	ADC_SYNCBUSY_WINUT          = 0x100 // Bit WINUT.
	ADC_SYNCBUSY_GAINCORR_Pos   = 0x9   // Position of GAINCORR field.
	ADC_SYNCBUSY_GAINCORR_Msk   = 0x200 // Bit mask of GAINCORR field.
	ADC_SYNCBUSY_GAINCORR       = 0x200 // Bit GAINCORR.
	ADC_SYNCBUSY_OFFSETCORR_Pos = 0xa   // Position of OFFSETCORR field.
	ADC_SYNCBUSY_OFFSETCORR_Msk = 0x400 // Bit mask of OFFSETCORR field.
	ADC_SYNCBUSY_OFFSETCORR     = 0x400 // Bit OFFSETCORR.
	ADC_SYNCBUSY_SWTRIG_Pos     = 0xb   // Position of SWTRIG field.
	ADC_SYNCBUSY_SWTRIG_Msk     = 0x800 // Bit mask of SWTRIG field.
	ADC_SYNCBUSY_SWTRIG         = 0x800 // Bit SWTRIG.

	// DSEQDATA: DMA Sequencial Data
	ADC_DSEQDATA_DATA_Pos = 0x0        // Position of DATA field.
	ADC_DSEQDATA_DATA_Msk = 0xffffffff // Bit mask of DATA field.

	// DSEQCTRL: DMA Sequential Control
	ADC_DSEQCTRL_INPUTCTRL_Pos  = 0x0        // Position of INPUTCTRL field.
	ADC_DSEQCTRL_INPUTCTRL_Msk  = 0x1        // Bit mask of INPUTCTRL field.
	ADC_DSEQCTRL_INPUTCTRL      = 0x1        // Bit INPUTCTRL.
	ADC_DSEQCTRL_CTRLB_Pos      = 0x1        // Position of CTRLB field.
	ADC_DSEQCTRL_CTRLB_Msk      = 0x2        // Bit mask of CTRLB field.
	ADC_DSEQCTRL_CTRLB          = 0x2        // Bit CTRLB.
	ADC_DSEQCTRL_REFCTRL_Pos    = 0x2        // Position of REFCTRL field.
	ADC_DSEQCTRL_REFCTRL_Msk    = 0x4        // Bit mask of REFCTRL field.
	ADC_DSEQCTRL_REFCTRL        = 0x4        // Bit REFCTRL.
	ADC_DSEQCTRL_AVGCTRL_Pos    = 0x3        // Position of AVGCTRL field.
	ADC_DSEQCTRL_AVGCTRL_Msk    = 0x8        // Bit mask of AVGCTRL field.
	ADC_DSEQCTRL_AVGCTRL        = 0x8        // Bit AVGCTRL.
	ADC_DSEQCTRL_SAMPCTRL_Pos   = 0x4        // Position of SAMPCTRL field.
	ADC_DSEQCTRL_SAMPCTRL_Msk   = 0x10       // Bit mask of SAMPCTRL field.
	ADC_DSEQCTRL_SAMPCTRL       = 0x10       // Bit SAMPCTRL.
	ADC_DSEQCTRL_WINLT_Pos      = 0x5        // Position of WINLT field.
	ADC_DSEQCTRL_WINLT_Msk      = 0x20       // Bit mask of WINLT field.
	ADC_DSEQCTRL_WINLT          = 0x20       // Bit WINLT.
	ADC_DSEQCTRL_WINUT_Pos      = 0x6        // Position of WINUT field.
	ADC_DSEQCTRL_WINUT_Msk      = 0x40       // Bit mask of WINUT field.
	ADC_DSEQCTRL_WINUT          = 0x40       // Bit WINUT.
	ADC_DSEQCTRL_GAINCORR_Pos   = 0x7        // Position of GAINCORR field.
	ADC_DSEQCTRL_GAINCORR_Msk   = 0x80       // Bit mask of GAINCORR field.
	ADC_DSEQCTRL_GAINCORR       = 0x80       // Bit GAINCORR.
	ADC_DSEQCTRL_OFFSETCORR_Pos = 0x8        // Position of OFFSETCORR field.
	ADC_DSEQCTRL_OFFSETCORR_Msk = 0x100      // Bit mask of OFFSETCORR field.
	ADC_DSEQCTRL_OFFSETCORR     = 0x100      // Bit OFFSETCORR.
	ADC_DSEQCTRL_AUTOSTART_Pos  = 0x1f       // Position of AUTOSTART field.
	ADC_DSEQCTRL_AUTOSTART_Msk  = 0x80000000 // Bit mask of AUTOSTART field.
	ADC_DSEQCTRL_AUTOSTART      = 0x80000000 // Bit AUTOSTART.

	// DSEQSTAT: DMA Sequencial Status
	ADC_DSEQSTAT_INPUTCTRL_Pos  = 0x0        // Position of INPUTCTRL field.
	ADC_DSEQSTAT_INPUTCTRL_Msk  = 0x1        // Bit mask of INPUTCTRL field.
	ADC_DSEQSTAT_INPUTCTRL      = 0x1        // Bit INPUTCTRL.
	ADC_DSEQSTAT_CTRLB_Pos      = 0x1        // Position of CTRLB field.
	ADC_DSEQSTAT_CTRLB_Msk      = 0x2        // Bit mask of CTRLB field.
	ADC_DSEQSTAT_CTRLB          = 0x2        // Bit CTRLB.
	ADC_DSEQSTAT_REFCTRL_Pos    = 0x2        // Position of REFCTRL field.
	ADC_DSEQSTAT_REFCTRL_Msk    = 0x4        // Bit mask of REFCTRL field.
	ADC_DSEQSTAT_REFCTRL        = 0x4        // Bit REFCTRL.
	ADC_DSEQSTAT_AVGCTRL_Pos    = 0x3        // Position of AVGCTRL field.
	ADC_DSEQSTAT_AVGCTRL_Msk    = 0x8        // Bit mask of AVGCTRL field.
	ADC_DSEQSTAT_AVGCTRL        = 0x8        // Bit AVGCTRL.
	ADC_DSEQSTAT_SAMPCTRL_Pos   = 0x4        // Position of SAMPCTRL field.
	ADC_DSEQSTAT_SAMPCTRL_Msk   = 0x10       // Bit mask of SAMPCTRL field.
	ADC_DSEQSTAT_SAMPCTRL       = 0x10       // Bit SAMPCTRL.
	ADC_DSEQSTAT_WINLT_Pos      = 0x5        // Position of WINLT field.
	ADC_DSEQSTAT_WINLT_Msk      = 0x20       // Bit mask of WINLT field.
	ADC_DSEQSTAT_WINLT          = 0x20       // Bit WINLT.
	ADC_DSEQSTAT_WINUT_Pos      = 0x6        // Position of WINUT field.
	ADC_DSEQSTAT_WINUT_Msk      = 0x40       // Bit mask of WINUT field.
	ADC_DSEQSTAT_WINUT          = 0x40       // Bit WINUT.
	ADC_DSEQSTAT_GAINCORR_Pos   = 0x7        // Position of GAINCORR field.
	ADC_DSEQSTAT_GAINCORR_Msk   = 0x80       // Bit mask of GAINCORR field.
	ADC_DSEQSTAT_GAINCORR       = 0x80       // Bit GAINCORR.
	ADC_DSEQSTAT_OFFSETCORR_Pos = 0x8        // Position of OFFSETCORR field.
	ADC_DSEQSTAT_OFFSETCORR_Msk = 0x100      // Bit mask of OFFSETCORR field.
	ADC_DSEQSTAT_OFFSETCORR     = 0x100      // Bit OFFSETCORR.
	ADC_DSEQSTAT_BUSY_Pos       = 0x1f       // Position of BUSY field.
	ADC_DSEQSTAT_BUSY_Msk       = 0x80000000 // Bit mask of BUSY field.
	ADC_DSEQSTAT_BUSY           = 0x80000000 // Bit BUSY.

	// RESULT: Result Conversion Value
	ADC_RESULT_RESULT_Pos = 0x0    // Position of RESULT field.
	ADC_RESULT_RESULT_Msk = 0xffff // Bit mask of RESULT field.

	// RESS: Last Sample Result
	ADC_RESS_RESS_Pos = 0x0    // Position of RESS field.
	ADC_RESS_RESS_Msk = 0xffff // Bit mask of RESS field.

	// CALIB: Calibration
	ADC_CALIB_BIASCOMP_Pos   = 0x0   // Position of BIASCOMP field.
	ADC_CALIB_BIASCOMP_Msk   = 0x7   // Bit mask of BIASCOMP field.
	ADC_CALIB_BIASR2R_Pos    = 0x4   // Position of BIASR2R field.
	ADC_CALIB_BIASR2R_Msk    = 0x70  // Bit mask of BIASR2R field.
	ADC_CALIB_BIASREFBUF_Pos = 0x8   // Position of BIASREFBUF field.
	ADC_CALIB_BIASREFBUF_Msk = 0x700 // Bit mask of BIASREFBUF field.
)

// Bitfields for AES: Advanced Encryption Standard
const (
	// CTRLA: Control A
	AES_CTRLA_SWRST_Pos        = 0x0     // Position of SWRST field.
	AES_CTRLA_SWRST_Msk        = 0x1     // Bit mask of SWRST field.
	AES_CTRLA_SWRST            = 0x1     // Bit SWRST.
	AES_CTRLA_ENABLE_Pos       = 0x1     // Position of ENABLE field.
	AES_CTRLA_ENABLE_Msk       = 0x2     // Bit mask of ENABLE field.
	AES_CTRLA_ENABLE           = 0x2     // Bit ENABLE.
	AES_CTRLA_AESMODE_Pos      = 0x2     // Position of AESMODE field.
	AES_CTRLA_AESMODE_Msk      = 0x1c    // Bit mask of AESMODE field.
	AES_CTRLA_AESMODE_ECB      = 0x0     // Electronic code book mode
	AES_CTRLA_AESMODE_CBC      = 0x1     // Cipher block chaining mode
	AES_CTRLA_AESMODE_OFB      = 0x2     // Output feedback mode
	AES_CTRLA_AESMODE_CFB      = 0x3     // Cipher feedback mode
	AES_CTRLA_AESMODE_COUNTER  = 0x4     // Counter mode
	AES_CTRLA_AESMODE_CCM      = 0x5     // CCM mode
	AES_CTRLA_AESMODE_GCM      = 0x6     // Galois counter mode
	AES_CTRLA_CFBS_Pos         = 0x5     // Position of CFBS field.
	AES_CTRLA_CFBS_Msk         = 0xe0    // Bit mask of CFBS field.
	AES_CTRLA_CFBS_128BIT      = 0x0     // 128-bit Input data block for Encryption/Decryption in Cipher Feedback mode
	AES_CTRLA_CFBS_64BIT       = 0x1     // 64-bit Input data block for Encryption/Decryption in Cipher Feedback mode
	AES_CTRLA_CFBS_32BIT       = 0x2     // 32-bit Input data block for Encryption/Decryption in Cipher Feedback mode
	AES_CTRLA_CFBS_16BIT       = 0x3     // 16-bit Input data block for Encryption/Decryption in Cipher Feedback mode
	AES_CTRLA_CFBS_8BIT        = 0x4     // 8-bit Input data block for Encryption/Decryption in Cipher Feedback mode
	AES_CTRLA_KEYSIZE_Pos      = 0x8     // Position of KEYSIZE field.
	AES_CTRLA_KEYSIZE_Msk      = 0x300   // Bit mask of KEYSIZE field.
	AES_CTRLA_KEYSIZE_128BIT   = 0x0     // 128-bit Key for Encryption / Decryption
	AES_CTRLA_KEYSIZE_192BIT   = 0x1     // 192-bit Key for Encryption / Decryption
	AES_CTRLA_KEYSIZE_256BIT   = 0x2     // 256-bit Key for Encryption / Decryption
	AES_CTRLA_CIPHER_Pos       = 0xa     // Position of CIPHER field.
	AES_CTRLA_CIPHER_Msk       = 0x400   // Bit mask of CIPHER field.
	AES_CTRLA_CIPHER           = 0x400   // Bit CIPHER.
	AES_CTRLA_CIPHER_DEC       = 0x0     // Decryption
	AES_CTRLA_CIPHER_ENC       = 0x1     // Encryption
	AES_CTRLA_STARTMODE_Pos    = 0xb     // Position of STARTMODE field.
	AES_CTRLA_STARTMODE_Msk    = 0x800   // Bit mask of STARTMODE field.
	AES_CTRLA_STARTMODE        = 0x800   // Bit STARTMODE.
	AES_CTRLA_STARTMODE_MANUAL = 0x0     // Start Encryption / Decryption in Manual mode
	AES_CTRLA_STARTMODE_AUTO   = 0x1     // Start Encryption / Decryption in Auto mode
	AES_CTRLA_LOD_Pos          = 0xc     // Position of LOD field.
	AES_CTRLA_LOD_Msk          = 0x1000  // Bit mask of LOD field.
	AES_CTRLA_LOD              = 0x1000  // Bit LOD.
	AES_CTRLA_LOD_NONE         = 0x0     // No effect
	AES_CTRLA_LOD_LAST         = 0x1     // Start encryption in Last Output Data mode
	AES_CTRLA_KEYGEN_Pos       = 0xd     // Position of KEYGEN field.
	AES_CTRLA_KEYGEN_Msk       = 0x2000  // Bit mask of KEYGEN field.
	AES_CTRLA_KEYGEN           = 0x2000  // Bit KEYGEN.
	AES_CTRLA_KEYGEN_NONE      = 0x0     // No effect
	AES_CTRLA_KEYGEN_LAST      = 0x1     // Start Computation of the last NK words of the expanded key
	AES_CTRLA_XORKEY_Pos       = 0xe     // Position of XORKEY field.
	AES_CTRLA_XORKEY_Msk       = 0x4000  // Bit mask of XORKEY field.
	AES_CTRLA_XORKEY           = 0x4000  // Bit XORKEY.
	AES_CTRLA_XORKEY_NONE      = 0x0     // No effect
	AES_CTRLA_XORKEY_XOR       = 0x1     // The user keyword gets XORed with the previous keyword register content.
	AES_CTRLA_CTYPE_Pos        = 0x10    // Position of CTYPE field.
	AES_CTRLA_CTYPE_Msk        = 0xf0000 // Bit mask of CTYPE field.

	// CTRLB: Control B
	AES_CTRLB_START_Pos  = 0x0 // Position of START field.
	AES_CTRLB_START_Msk  = 0x1 // Bit mask of START field.
	AES_CTRLB_START      = 0x1 // Bit START.
	AES_CTRLB_NEWMSG_Pos = 0x1 // Position of NEWMSG field.
	AES_CTRLB_NEWMSG_Msk = 0x2 // Bit mask of NEWMSG field.
	AES_CTRLB_NEWMSG     = 0x2 // Bit NEWMSG.
	AES_CTRLB_EOM_Pos    = 0x2 // Position of EOM field.
	AES_CTRLB_EOM_Msk    = 0x4 // Bit mask of EOM field.
	AES_CTRLB_EOM        = 0x4 // Bit EOM.
	AES_CTRLB_GFMUL_Pos  = 0x3 // Position of GFMUL field.
	AES_CTRLB_GFMUL_Msk  = 0x8 // Bit mask of GFMUL field.
	AES_CTRLB_GFMUL      = 0x8 // Bit GFMUL.

	// INTENCLR: Interrupt Enable Clear
	AES_INTENCLR_ENCCMP_Pos = 0x0 // Position of ENCCMP field.
	AES_INTENCLR_ENCCMP_Msk = 0x1 // Bit mask of ENCCMP field.
	AES_INTENCLR_ENCCMP     = 0x1 // Bit ENCCMP.
	AES_INTENCLR_GFMCMP_Pos = 0x1 // Position of GFMCMP field.
	AES_INTENCLR_GFMCMP_Msk = 0x2 // Bit mask of GFMCMP field.
	AES_INTENCLR_GFMCMP     = 0x2 // Bit GFMCMP.

	// INTENSET: Interrupt Enable Set
	AES_INTENSET_ENCCMP_Pos = 0x0 // Position of ENCCMP field.
	AES_INTENSET_ENCCMP_Msk = 0x1 // Bit mask of ENCCMP field.
	AES_INTENSET_ENCCMP     = 0x1 // Bit ENCCMP.
	AES_INTENSET_GFMCMP_Pos = 0x1 // Position of GFMCMP field.
	AES_INTENSET_GFMCMP_Msk = 0x2 // Bit mask of GFMCMP field.
	AES_INTENSET_GFMCMP     = 0x2 // Bit GFMCMP.

	// INTFLAG: Interrupt Flag Status
	AES_INTFLAG_ENCCMP_Pos = 0x0 // Position of ENCCMP field.
	AES_INTFLAG_ENCCMP_Msk = 0x1 // Bit mask of ENCCMP field.
	AES_INTFLAG_ENCCMP     = 0x1 // Bit ENCCMP.
	AES_INTFLAG_GFMCMP_Pos = 0x1 // Position of GFMCMP field.
	AES_INTFLAG_GFMCMP_Msk = 0x2 // Bit mask of GFMCMP field.
	AES_INTFLAG_GFMCMP     = 0x2 // Bit GFMCMP.

	// DATABUFPTR: Data buffer pointer
	AES_DATABUFPTR_INDATAPTR_Pos = 0x0 // Position of INDATAPTR field.
	AES_DATABUFPTR_INDATAPTR_Msk = 0x3 // Bit mask of INDATAPTR field.

	// DBGCTRL: Debug control
	AES_DBGCTRL_DBGRUN_Pos = 0x0 // Position of DBGRUN field.
	AES_DBGCTRL_DBGRUN_Msk = 0x1 // Bit mask of DBGRUN field.
	AES_DBGCTRL_DBGRUN     = 0x1 // Bit DBGRUN.
)

// Bitfields for CCL: Configurable Custom Logic
const (
	// CTRL: Control
	CCL_CTRL_SWRST_Pos    = 0x0  // Position of SWRST field.
	CCL_CTRL_SWRST_Msk    = 0x1  // Bit mask of SWRST field.
	CCL_CTRL_SWRST        = 0x1  // Bit SWRST.
	CCL_CTRL_ENABLE_Pos   = 0x1  // Position of ENABLE field.
	CCL_CTRL_ENABLE_Msk   = 0x2  // Bit mask of ENABLE field.
	CCL_CTRL_ENABLE       = 0x2  // Bit ENABLE.
	CCL_CTRL_RUNSTDBY_Pos = 0x6  // Position of RUNSTDBY field.
	CCL_CTRL_RUNSTDBY_Msk = 0x40 // Bit mask of RUNSTDBY field.
	CCL_CTRL_RUNSTDBY     = 0x40 // Bit RUNSTDBY.

	// SEQCTRL: SEQ Control x
	CCL_SEQCTRL_SEQSEL_Pos     = 0x0 // Position of SEQSEL field.
	CCL_SEQCTRL_SEQSEL_Msk     = 0xf // Bit mask of SEQSEL field.
	CCL_SEQCTRL_SEQSEL_DISABLE = 0x0 // Sequential logic is disabled
	CCL_SEQCTRL_SEQSEL_DFF     = 0x1 // D flip flop
	CCL_SEQCTRL_SEQSEL_JK      = 0x2 // JK flip flop
	CCL_SEQCTRL_SEQSEL_LATCH   = 0x3 // D latch
	CCL_SEQCTRL_SEQSEL_RS      = 0x4 // RS latch

	// LUTCTRL: LUT Control x
	CCL_LUTCTRL_ENABLE_Pos      = 0x1        // Position of ENABLE field.
	CCL_LUTCTRL_ENABLE_Msk      = 0x2        // Bit mask of ENABLE field.
	CCL_LUTCTRL_ENABLE          = 0x2        // Bit ENABLE.
	CCL_LUTCTRL_FILTSEL_Pos     = 0x4        // Position of FILTSEL field.
	CCL_LUTCTRL_FILTSEL_Msk     = 0x30       // Bit mask of FILTSEL field.
	CCL_LUTCTRL_FILTSEL_DISABLE = 0x0        // Filter disabled
	CCL_LUTCTRL_FILTSEL_SYNCH   = 0x1        // Synchronizer enabled
	CCL_LUTCTRL_FILTSEL_FILTER  = 0x2        // Filter enabled
	CCL_LUTCTRL_EDGESEL_Pos     = 0x7        // Position of EDGESEL field.
	CCL_LUTCTRL_EDGESEL_Msk     = 0x80       // Bit mask of EDGESEL field.
	CCL_LUTCTRL_EDGESEL         = 0x80       // Bit EDGESEL.
	CCL_LUTCTRL_INSEL0_Pos      = 0x8        // Position of INSEL0 field.
	CCL_LUTCTRL_INSEL0_Msk      = 0xf00      // Bit mask of INSEL0 field.
	CCL_LUTCTRL_INSEL0_MASK     = 0x0        // Masked input
	CCL_LUTCTRL_INSEL0_FEEDBACK = 0x1        // Feedback input source
	CCL_LUTCTRL_INSEL0_LINK     = 0x2        // Linked LUT input source
	CCL_LUTCTRL_INSEL0_EVENT    = 0x3        // Event input source
	CCL_LUTCTRL_INSEL0_IO       = 0x4        // I/O pin input source
	CCL_LUTCTRL_INSEL0_AC       = 0x5        // AC input source
	CCL_LUTCTRL_INSEL0_TC       = 0x6        // TC input source
	CCL_LUTCTRL_INSEL0_ALTTC    = 0x7        // Alternate TC input source
	CCL_LUTCTRL_INSEL0_TCC      = 0x8        // TCC input source
	CCL_LUTCTRL_INSEL0_SERCOM   = 0x9        // SERCOM input source
	CCL_LUTCTRL_INSEL1_Pos      = 0xc        // Position of INSEL1 field.
	CCL_LUTCTRL_INSEL1_Msk      = 0xf000     // Bit mask of INSEL1 field.
	CCL_LUTCTRL_INSEL1_MASK     = 0x0        // Masked input
	CCL_LUTCTRL_INSEL1_FEEDBACK = 0x1        // Feedback input source
	CCL_LUTCTRL_INSEL1_LINK     = 0x2        // Linked LUT input source
	CCL_LUTCTRL_INSEL1_EVENT    = 0x3        // Event input source
	CCL_LUTCTRL_INSEL1_IO       = 0x4        // I/O pin input source
	CCL_LUTCTRL_INSEL1_AC       = 0x5        // AC input source
	CCL_LUTCTRL_INSEL1_TC       = 0x6        // TC input source
	CCL_LUTCTRL_INSEL1_ALTTC    = 0x7        // Alternate TC input source
	CCL_LUTCTRL_INSEL1_TCC      = 0x8        // TCC input source
	CCL_LUTCTRL_INSEL1_SERCOM   = 0x9        // SERCOM input source
	CCL_LUTCTRL_INSEL2_Pos      = 0x10       // Position of INSEL2 field.
	CCL_LUTCTRL_INSEL2_Msk      = 0xf0000    // Bit mask of INSEL2 field.
	CCL_LUTCTRL_INSEL2_MASK     = 0x0        // Masked input
	CCL_LUTCTRL_INSEL2_FEEDBACK = 0x1        // Feedback input source
	CCL_LUTCTRL_INSEL2_LINK     = 0x2        // Linked LUT input source
	CCL_LUTCTRL_INSEL2_EVENT    = 0x3        // Event input source
	CCL_LUTCTRL_INSEL2_IO       = 0x4        // I/O pin input source
	CCL_LUTCTRL_INSEL2_AC       = 0x5        // AC input source
	CCL_LUTCTRL_INSEL2_TC       = 0x6        // TC input source
	CCL_LUTCTRL_INSEL2_ALTTC    = 0x7        // Alternate TC input source
	CCL_LUTCTRL_INSEL2_TCC      = 0x8        // TCC input source
	CCL_LUTCTRL_INSEL2_SERCOM   = 0x9        // SERCOM input source
	CCL_LUTCTRL_INVEI_Pos       = 0x14       // Position of INVEI field.
	CCL_LUTCTRL_INVEI_Msk       = 0x100000   // Bit mask of INVEI field.
	CCL_LUTCTRL_INVEI           = 0x100000   // Bit INVEI.
	CCL_LUTCTRL_LUTEI_Pos       = 0x15       // Position of LUTEI field.
	CCL_LUTCTRL_LUTEI_Msk       = 0x200000   // Bit mask of LUTEI field.
	CCL_LUTCTRL_LUTEI           = 0x200000   // Bit LUTEI.
	CCL_LUTCTRL_LUTEO_Pos       = 0x16       // Position of LUTEO field.
	CCL_LUTCTRL_LUTEO_Msk       = 0x400000   // Bit mask of LUTEO field.
	CCL_LUTCTRL_LUTEO           = 0x400000   // Bit LUTEO.
	CCL_LUTCTRL_TRUTH_Pos       = 0x18       // Position of TRUTH field.
	CCL_LUTCTRL_TRUTH_Msk       = 0xff000000 // Bit mask of TRUTH field.
)

// Bitfields for CMCC: Cortex M Cache Controller
const (
	// TYPE: Cache Type Register
	CMCC_TYPE_GCLK_Pos           = 0x1    // Position of GCLK field.
	CMCC_TYPE_GCLK_Msk           = 0x2    // Bit mask of GCLK field.
	CMCC_TYPE_GCLK               = 0x2    // Bit GCLK.
	CMCC_TYPE_RRP_Pos            = 0x4    // Position of RRP field.
	CMCC_TYPE_RRP_Msk            = 0x10   // Bit mask of RRP field.
	CMCC_TYPE_RRP                = 0x10   // Bit RRP.
	CMCC_TYPE_WAYNUM_Pos         = 0x5    // Position of WAYNUM field.
	CMCC_TYPE_WAYNUM_Msk         = 0x60   // Bit mask of WAYNUM field.
	CMCC_TYPE_WAYNUM_DMAPPED     = 0x0    // Direct Mapped Cache
	CMCC_TYPE_WAYNUM_ARCH2WAY    = 0x1    // 2-WAY set associative
	CMCC_TYPE_WAYNUM_ARCH4WAY    = 0x2    // 4-WAY set associative
	CMCC_TYPE_LCKDOWN_Pos        = 0x7    // Position of LCKDOWN field.
	CMCC_TYPE_LCKDOWN_Msk        = 0x80   // Bit mask of LCKDOWN field.
	CMCC_TYPE_LCKDOWN            = 0x80   // Bit LCKDOWN.
	CMCC_TYPE_CSIZE_Pos          = 0x8    // Position of CSIZE field.
	CMCC_TYPE_CSIZE_Msk          = 0x700  // Bit mask of CSIZE field.
	CMCC_TYPE_CSIZE_CSIZE_1KB    = 0x0    // Cache Size is 1 KB
	CMCC_TYPE_CSIZE_CSIZE_2KB    = 0x1    // Cache Size is 2 KB
	CMCC_TYPE_CSIZE_CSIZE_4KB    = 0x2    // Cache Size is 4 KB
	CMCC_TYPE_CSIZE_CSIZE_8KB    = 0x3    // Cache Size is 8 KB
	CMCC_TYPE_CSIZE_CSIZE_16KB   = 0x4    // Cache Size is 16 KB
	CMCC_TYPE_CSIZE_CSIZE_32KB   = 0x5    // Cache Size is 32 KB
	CMCC_TYPE_CSIZE_CSIZE_64KB   = 0x6    // Cache Size is 64 KB
	CMCC_TYPE_CLSIZE_Pos         = 0xb    // Position of CLSIZE field.
	CMCC_TYPE_CLSIZE_Msk         = 0x3800 // Bit mask of CLSIZE field.
	CMCC_TYPE_CLSIZE_CLSIZE_4B   = 0x0    // Cache Line Size is 4 bytes
	CMCC_TYPE_CLSIZE_CLSIZE_8B   = 0x1    // Cache Line Size is 8 bytes
	CMCC_TYPE_CLSIZE_CLSIZE_16B  = 0x2    // Cache Line Size is 16 bytes
	CMCC_TYPE_CLSIZE_CLSIZE_32B  = 0x3    // Cache Line Size is 32 bytes
	CMCC_TYPE_CLSIZE_CLSIZE_64B  = 0x4    // Cache Line Size is 64 bytes
	CMCC_TYPE_CLSIZE_CLSIZE_128B = 0x5    // Cache Line Size is 128 bytes

	// CFG: Cache Configuration Register
	CMCC_CFG_ICDIS_Pos               = 0x1  // Position of ICDIS field.
	CMCC_CFG_ICDIS_Msk               = 0x2  // Bit mask of ICDIS field.
	CMCC_CFG_ICDIS                   = 0x2  // Bit ICDIS.
	CMCC_CFG_DCDIS_Pos               = 0x2  // Position of DCDIS field.
	CMCC_CFG_DCDIS_Msk               = 0x4  // Bit mask of DCDIS field.
	CMCC_CFG_DCDIS                   = 0x4  // Bit DCDIS.
	CMCC_CFG_CSIZESW_Pos             = 0x4  // Position of CSIZESW field.
	CMCC_CFG_CSIZESW_Msk             = 0x70 // Bit mask of CSIZESW field.
	CMCC_CFG_CSIZESW_CONF_CSIZE_1KB  = 0x0  // The Cache Size is configured to 1KB
	CMCC_CFG_CSIZESW_CONF_CSIZE_2KB  = 0x1  // The Cache Size is configured to 2KB
	CMCC_CFG_CSIZESW_CONF_CSIZE_4KB  = 0x2  // The Cache Size is configured to 4KB
	CMCC_CFG_CSIZESW_CONF_CSIZE_8KB  = 0x3  // The Cache Size is configured to 8KB
	CMCC_CFG_CSIZESW_CONF_CSIZE_16KB = 0x4  // The Cache Size is configured to 16KB
	CMCC_CFG_CSIZESW_CONF_CSIZE_32KB = 0x5  // The Cache Size is configured to 32KB
	CMCC_CFG_CSIZESW_CONF_CSIZE_64KB = 0x6  // The Cache Size is configured to 64KB

	// CTRL: Cache Control Register
	CMCC_CTRL_CEN_Pos = 0x0 // Position of CEN field.
	CMCC_CTRL_CEN_Msk = 0x1 // Bit mask of CEN field.
	CMCC_CTRL_CEN     = 0x1 // Bit CEN.

	// SR: Cache Status Register
	CMCC_SR_CSTS_Pos = 0x0 // Position of CSTS field.
	CMCC_SR_CSTS_Msk = 0x1 // Bit mask of CSTS field.
	CMCC_SR_CSTS     = 0x1 // Bit CSTS.

	// LCKWAY: Cache Lock per Way Register
	CMCC_LCKWAY_LCKWAY_Pos = 0x0 // Position of LCKWAY field.
	CMCC_LCKWAY_LCKWAY_Msk = 0xf // Bit mask of LCKWAY field.

	// MAINT0: Cache Maintenance Register 0
	CMCC_MAINT0_INVALL_Pos = 0x0 // Position of INVALL field.
	CMCC_MAINT0_INVALL_Msk = 0x1 // Bit mask of INVALL field.
	CMCC_MAINT0_INVALL     = 0x1 // Bit INVALL.

	// MAINT1: Cache Maintenance Register 1
	CMCC_MAINT1_INDEX_Pos = 0x4        // Position of INDEX field.
	CMCC_MAINT1_INDEX_Msk = 0xff0      // Bit mask of INDEX field.
	CMCC_MAINT1_WAY_Pos   = 0x1c       // Position of WAY field.
	CMCC_MAINT1_WAY_Msk   = 0xf0000000 // Bit mask of WAY field.
	CMCC_MAINT1_WAY_WAY0  = 0x0        // Way 0 is selection for index invalidation
	CMCC_MAINT1_WAY_WAY1  = 0x1        // Way 1 is selection for index invalidation
	CMCC_MAINT1_WAY_WAY2  = 0x2        // Way 2 is selection for index invalidation
	CMCC_MAINT1_WAY_WAY3  = 0x3        // Way 3 is selection for index invalidation

	// MCFG: Cache Monitor Configuration Register
	CMCC_MCFG_MODE_Pos         = 0x0 // Position of MODE field.
	CMCC_MCFG_MODE_Msk         = 0x3 // Bit mask of MODE field.
	CMCC_MCFG_MODE_CYCLE_COUNT = 0x0 // Cycle counter
	CMCC_MCFG_MODE_IHIT_COUNT  = 0x1 // Instruction hit counter
	CMCC_MCFG_MODE_DHIT_COUNT  = 0x2 // Data hit counter

	// MEN: Cache Monitor Enable Register
	CMCC_MEN_MENABLE_Pos = 0x0 // Position of MENABLE field.
	CMCC_MEN_MENABLE_Msk = 0x1 // Bit mask of MENABLE field.
	CMCC_MEN_MENABLE     = 0x1 // Bit MENABLE.

	// MCTRL: Cache Monitor Control Register
	CMCC_MCTRL_SWRST_Pos = 0x0 // Position of SWRST field.
	CMCC_MCTRL_SWRST_Msk = 0x1 // Bit mask of SWRST field.
	CMCC_MCTRL_SWRST     = 0x1 // Bit SWRST.

	// MSR: Cache Monitor Status Register
	CMCC_MSR_EVENT_CNT_Pos = 0x0        // Position of EVENT_CNT field.
	CMCC_MSR_EVENT_CNT_Msk = 0xffffffff // Bit mask of EVENT_CNT field.
)

// Bitfields for DAC: Digital-to-Analog Converter
const (
	// CTRLA: Control A
	DAC_CTRLA_SWRST_Pos  = 0x0 // Position of SWRST field.
	DAC_CTRLA_SWRST_Msk  = 0x1 // Bit mask of SWRST field.
	DAC_CTRLA_SWRST      = 0x1 // Bit SWRST.
	DAC_CTRLA_ENABLE_Pos = 0x1 // Position of ENABLE field.
	DAC_CTRLA_ENABLE_Msk = 0x2 // Bit mask of ENABLE field.
	DAC_CTRLA_ENABLE     = 0x2 // Bit ENABLE.

	// CTRLB: Control B
	DAC_CTRLB_DIFF_Pos      = 0x0 // Position of DIFF field.
	DAC_CTRLB_DIFF_Msk      = 0x1 // Bit mask of DIFF field.
	DAC_CTRLB_DIFF          = 0x1 // Bit DIFF.
	DAC_CTRLB_REFSEL_Pos    = 0x1 // Position of REFSEL field.
	DAC_CTRLB_REFSEL_Msk    = 0x6 // Bit mask of REFSEL field.
	DAC_CTRLB_REFSEL_VREFPU = 0x0 // External reference unbuffered
	DAC_CTRLB_REFSEL_VDDANA = 0x1 // Analog supply
	DAC_CTRLB_REFSEL_VREFPB = 0x2 // External reference buffered
	DAC_CTRLB_REFSEL_INTREF = 0x3 // Internal bandgap reference

	// EVCTRL: Event Control
	DAC_EVCTRL_STARTEI0_Pos  = 0x0  // Position of STARTEI0 field.
	DAC_EVCTRL_STARTEI0_Msk  = 0x1  // Bit mask of STARTEI0 field.
	DAC_EVCTRL_STARTEI0      = 0x1  // Bit STARTEI0.
	DAC_EVCTRL_STARTEI1_Pos  = 0x1  // Position of STARTEI1 field.
	DAC_EVCTRL_STARTEI1_Msk  = 0x2  // Bit mask of STARTEI1 field.
	DAC_EVCTRL_STARTEI1      = 0x2  // Bit STARTEI1.
	DAC_EVCTRL_EMPTYEO0_Pos  = 0x2  // Position of EMPTYEO0 field.
	DAC_EVCTRL_EMPTYEO0_Msk  = 0x4  // Bit mask of EMPTYEO0 field.
	DAC_EVCTRL_EMPTYEO0      = 0x4  // Bit EMPTYEO0.
	DAC_EVCTRL_EMPTYEO1_Pos  = 0x3  // Position of EMPTYEO1 field.
	DAC_EVCTRL_EMPTYEO1_Msk  = 0x8  // Bit mask of EMPTYEO1 field.
	DAC_EVCTRL_EMPTYEO1      = 0x8  // Bit EMPTYEO1.
	DAC_EVCTRL_INVEI0_Pos    = 0x4  // Position of INVEI0 field.
	DAC_EVCTRL_INVEI0_Msk    = 0x10 // Bit mask of INVEI0 field.
	DAC_EVCTRL_INVEI0        = 0x10 // Bit INVEI0.
	DAC_EVCTRL_INVEI1_Pos    = 0x5  // Position of INVEI1 field.
	DAC_EVCTRL_INVEI1_Msk    = 0x20 // Bit mask of INVEI1 field.
	DAC_EVCTRL_INVEI1        = 0x20 // Bit INVEI1.
	DAC_EVCTRL_RESRDYEO0_Pos = 0x6  // Position of RESRDYEO0 field.
	DAC_EVCTRL_RESRDYEO0_Msk = 0x40 // Bit mask of RESRDYEO0 field.
	DAC_EVCTRL_RESRDYEO0     = 0x40 // Bit RESRDYEO0.
	DAC_EVCTRL_RESRDYEO1_Pos = 0x7  // Position of RESRDYEO1 field.
	DAC_EVCTRL_RESRDYEO1_Msk = 0x80 // Bit mask of RESRDYEO1 field.
	DAC_EVCTRL_RESRDYEO1     = 0x80 // Bit RESRDYEO1.

	// INTENCLR: Interrupt Enable Clear
	DAC_INTENCLR_UNDERRUN0_Pos = 0x0  // Position of UNDERRUN0 field.
	DAC_INTENCLR_UNDERRUN0_Msk = 0x1  // Bit mask of UNDERRUN0 field.
	DAC_INTENCLR_UNDERRUN0     = 0x1  // Bit UNDERRUN0.
	DAC_INTENCLR_UNDERRUN1_Pos = 0x1  // Position of UNDERRUN1 field.
	DAC_INTENCLR_UNDERRUN1_Msk = 0x2  // Bit mask of UNDERRUN1 field.
	DAC_INTENCLR_UNDERRUN1     = 0x2  // Bit UNDERRUN1.
	DAC_INTENCLR_EMPTY0_Pos    = 0x2  // Position of EMPTY0 field.
	DAC_INTENCLR_EMPTY0_Msk    = 0x4  // Bit mask of EMPTY0 field.
	DAC_INTENCLR_EMPTY0        = 0x4  // Bit EMPTY0.
	DAC_INTENCLR_EMPTY1_Pos    = 0x3  // Position of EMPTY1 field.
	DAC_INTENCLR_EMPTY1_Msk    = 0x8  // Bit mask of EMPTY1 field.
	DAC_INTENCLR_EMPTY1        = 0x8  // Bit EMPTY1.
	DAC_INTENCLR_RESRDY0_Pos   = 0x4  // Position of RESRDY0 field.
	DAC_INTENCLR_RESRDY0_Msk   = 0x10 // Bit mask of RESRDY0 field.
	DAC_INTENCLR_RESRDY0       = 0x10 // Bit RESRDY0.
	DAC_INTENCLR_RESRDY1_Pos   = 0x5  // Position of RESRDY1 field.
	DAC_INTENCLR_RESRDY1_Msk   = 0x20 // Bit mask of RESRDY1 field.
	DAC_INTENCLR_RESRDY1       = 0x20 // Bit RESRDY1.
	DAC_INTENCLR_OVERRUN0_Pos  = 0x6  // Position of OVERRUN0 field.
	DAC_INTENCLR_OVERRUN0_Msk  = 0x40 // Bit mask of OVERRUN0 field.
	DAC_INTENCLR_OVERRUN0      = 0x40 // Bit OVERRUN0.
	DAC_INTENCLR_OVERRUN1_Pos  = 0x7  // Position of OVERRUN1 field.
	DAC_INTENCLR_OVERRUN1_Msk  = 0x80 // Bit mask of OVERRUN1 field.
	DAC_INTENCLR_OVERRUN1      = 0x80 // Bit OVERRUN1.

	// INTENSET: Interrupt Enable Set
	DAC_INTENSET_UNDERRUN0_Pos = 0x0  // Position of UNDERRUN0 field.
	DAC_INTENSET_UNDERRUN0_Msk = 0x1  // Bit mask of UNDERRUN0 field.
	DAC_INTENSET_UNDERRUN0     = 0x1  // Bit UNDERRUN0.
	DAC_INTENSET_UNDERRUN1_Pos = 0x1  // Position of UNDERRUN1 field.
	DAC_INTENSET_UNDERRUN1_Msk = 0x2  // Bit mask of UNDERRUN1 field.
	DAC_INTENSET_UNDERRUN1     = 0x2  // Bit UNDERRUN1.
	DAC_INTENSET_EMPTY0_Pos    = 0x2  // Position of EMPTY0 field.
	DAC_INTENSET_EMPTY0_Msk    = 0x4  // Bit mask of EMPTY0 field.
	DAC_INTENSET_EMPTY0        = 0x4  // Bit EMPTY0.
	DAC_INTENSET_EMPTY1_Pos    = 0x3  // Position of EMPTY1 field.
	DAC_INTENSET_EMPTY1_Msk    = 0x8  // Bit mask of EMPTY1 field.
	DAC_INTENSET_EMPTY1        = 0x8  // Bit EMPTY1.
	DAC_INTENSET_RESRDY0_Pos   = 0x4  // Position of RESRDY0 field.
	DAC_INTENSET_RESRDY0_Msk   = 0x10 // Bit mask of RESRDY0 field.
	DAC_INTENSET_RESRDY0       = 0x10 // Bit RESRDY0.
	DAC_INTENSET_RESRDY1_Pos   = 0x5  // Position of RESRDY1 field.
	DAC_INTENSET_RESRDY1_Msk   = 0x20 // Bit mask of RESRDY1 field.
	DAC_INTENSET_RESRDY1       = 0x20 // Bit RESRDY1.
	DAC_INTENSET_OVERRUN0_Pos  = 0x6  // Position of OVERRUN0 field.
	DAC_INTENSET_OVERRUN0_Msk  = 0x40 // Bit mask of OVERRUN0 field.
	DAC_INTENSET_OVERRUN0      = 0x40 // Bit OVERRUN0.
	DAC_INTENSET_OVERRUN1_Pos  = 0x7  // Position of OVERRUN1 field.
	DAC_INTENSET_OVERRUN1_Msk  = 0x80 // Bit mask of OVERRUN1 field.
	DAC_INTENSET_OVERRUN1      = 0x80 // Bit OVERRUN1.

	// INTFLAG: Interrupt Flag Status and Clear
	DAC_INTFLAG_UNDERRUN0_Pos = 0x0  // Position of UNDERRUN0 field.
	DAC_INTFLAG_UNDERRUN0_Msk = 0x1  // Bit mask of UNDERRUN0 field.
	DAC_INTFLAG_UNDERRUN0     = 0x1  // Bit UNDERRUN0.
	DAC_INTFLAG_UNDERRUN1_Pos = 0x1  // Position of UNDERRUN1 field.
	DAC_INTFLAG_UNDERRUN1_Msk = 0x2  // Bit mask of UNDERRUN1 field.
	DAC_INTFLAG_UNDERRUN1     = 0x2  // Bit UNDERRUN1.
	DAC_INTFLAG_EMPTY0_Pos    = 0x2  // Position of EMPTY0 field.
	DAC_INTFLAG_EMPTY0_Msk    = 0x4  // Bit mask of EMPTY0 field.
	DAC_INTFLAG_EMPTY0        = 0x4  // Bit EMPTY0.
	DAC_INTFLAG_EMPTY1_Pos    = 0x3  // Position of EMPTY1 field.
	DAC_INTFLAG_EMPTY1_Msk    = 0x8  // Bit mask of EMPTY1 field.
	DAC_INTFLAG_EMPTY1        = 0x8  // Bit EMPTY1.
	DAC_INTFLAG_RESRDY0_Pos   = 0x4  // Position of RESRDY0 field.
	DAC_INTFLAG_RESRDY0_Msk   = 0x10 // Bit mask of RESRDY0 field.
	DAC_INTFLAG_RESRDY0       = 0x10 // Bit RESRDY0.
	DAC_INTFLAG_RESRDY1_Pos   = 0x5  // Position of RESRDY1 field.
	DAC_INTFLAG_RESRDY1_Msk   = 0x20 // Bit mask of RESRDY1 field.
	DAC_INTFLAG_RESRDY1       = 0x20 // Bit RESRDY1.
	DAC_INTFLAG_OVERRUN0_Pos  = 0x6  // Position of OVERRUN0 field.
	DAC_INTFLAG_OVERRUN0_Msk  = 0x40 // Bit mask of OVERRUN0 field.
	DAC_INTFLAG_OVERRUN0      = 0x40 // Bit OVERRUN0.
	DAC_INTFLAG_OVERRUN1_Pos  = 0x7  // Position of OVERRUN1 field.
	DAC_INTFLAG_OVERRUN1_Msk  = 0x80 // Bit mask of OVERRUN1 field.
	DAC_INTFLAG_OVERRUN1      = 0x80 // Bit OVERRUN1.

	// STATUS: Status
	DAC_STATUS_READY0_Pos = 0x0 // Position of READY0 field.
	DAC_STATUS_READY0_Msk = 0x1 // Bit mask of READY0 field.
	DAC_STATUS_READY0     = 0x1 // Bit READY0.
	DAC_STATUS_READY1_Pos = 0x1 // Position of READY1 field.
	DAC_STATUS_READY1_Msk = 0x2 // Bit mask of READY1 field.
	DAC_STATUS_READY1     = 0x2 // Bit READY1.
	DAC_STATUS_EOC0_Pos   = 0x2 // Position of EOC0 field.
	DAC_STATUS_EOC0_Msk   = 0x4 // Bit mask of EOC0 field.
	DAC_STATUS_EOC0       = 0x4 // Bit EOC0.
	DAC_STATUS_EOC1_Pos   = 0x3 // Position of EOC1 field.
	DAC_STATUS_EOC1_Msk   = 0x8 // Bit mask of EOC1 field.
	DAC_STATUS_EOC1       = 0x8 // Bit EOC1.

	// SYNCBUSY: Synchronization Busy
	DAC_SYNCBUSY_SWRST_Pos    = 0x0  // Position of SWRST field.
	DAC_SYNCBUSY_SWRST_Msk    = 0x1  // Bit mask of SWRST field.
	DAC_SYNCBUSY_SWRST        = 0x1  // Bit SWRST.
	DAC_SYNCBUSY_ENABLE_Pos   = 0x1  // Position of ENABLE field.
	DAC_SYNCBUSY_ENABLE_Msk   = 0x2  // Bit mask of ENABLE field.
	DAC_SYNCBUSY_ENABLE       = 0x2  // Bit ENABLE.
	DAC_SYNCBUSY_DATA0_Pos    = 0x2  // Position of DATA0 field.
	DAC_SYNCBUSY_DATA0_Msk    = 0x4  // Bit mask of DATA0 field.
	DAC_SYNCBUSY_DATA0        = 0x4  // Bit DATA0.
	DAC_SYNCBUSY_DATA1_Pos    = 0x3  // Position of DATA1 field.
	DAC_SYNCBUSY_DATA1_Msk    = 0x8  // Bit mask of DATA1 field.
	DAC_SYNCBUSY_DATA1        = 0x8  // Bit DATA1.
	DAC_SYNCBUSY_DATABUF0_Pos = 0x4  // Position of DATABUF0 field.
	DAC_SYNCBUSY_DATABUF0_Msk = 0x10 // Bit mask of DATABUF0 field.
	DAC_SYNCBUSY_DATABUF0     = 0x10 // Bit DATABUF0.
	DAC_SYNCBUSY_DATABUF1_Pos = 0x5  // Position of DATABUF1 field.
	DAC_SYNCBUSY_DATABUF1_Msk = 0x20 // Bit mask of DATABUF1 field.
	DAC_SYNCBUSY_DATABUF1     = 0x20 // Bit DATABUF1.

	// DACCTRL: DAC n Control
	DAC_DACCTRL_LEFTADJ_Pos        = 0x0    // Position of LEFTADJ field.
	DAC_DACCTRL_LEFTADJ_Msk        = 0x1    // Bit mask of LEFTADJ field.
	DAC_DACCTRL_LEFTADJ            = 0x1    // Bit LEFTADJ.
	DAC_DACCTRL_ENABLE_Pos         = 0x1    // Position of ENABLE field.
	DAC_DACCTRL_ENABLE_Msk         = 0x2    // Bit mask of ENABLE field.
	DAC_DACCTRL_ENABLE             = 0x2    // Bit ENABLE.
	DAC_DACCTRL_CCTRL_Pos          = 0x2    // Position of CCTRL field.
	DAC_DACCTRL_CCTRL_Msk          = 0xc    // Bit mask of CCTRL field.
	DAC_DACCTRL_CCTRL_CC100K       = 0x0    // 100kSPS
	DAC_DACCTRL_CCTRL_CC1M         = 0x1    // 500kSPS
	DAC_DACCTRL_CCTRL_CC12M        = 0x2    // 1MSPS
	DAC_DACCTRL_FEXT_Pos           = 0x5    // Position of FEXT field.
	DAC_DACCTRL_FEXT_Msk           = 0x20   // Bit mask of FEXT field.
	DAC_DACCTRL_FEXT               = 0x20   // Bit FEXT.
	DAC_DACCTRL_RUNSTDBY_Pos       = 0x6    // Position of RUNSTDBY field.
	DAC_DACCTRL_RUNSTDBY_Msk       = 0x40   // Bit mask of RUNSTDBY field.
	DAC_DACCTRL_RUNSTDBY           = 0x40   // Bit RUNSTDBY.
	DAC_DACCTRL_DITHER_Pos         = 0x7    // Position of DITHER field.
	DAC_DACCTRL_DITHER_Msk         = 0x80   // Bit mask of DITHER field.
	DAC_DACCTRL_DITHER             = 0x80   // Bit DITHER.
	DAC_DACCTRL_REFRESH_Pos        = 0x8    // Position of REFRESH field.
	DAC_DACCTRL_REFRESH_Msk        = 0xf00  // Bit mask of REFRESH field.
	DAC_DACCTRL_REFRESH_REFRESH_0  = 0x0    // Do not Refresh
	DAC_DACCTRL_REFRESH_REFRESH_1  = 0x1    // Refresh every 30 us
	DAC_DACCTRL_REFRESH_REFRESH_2  = 0x2    // Refresh every 60 us
	DAC_DACCTRL_REFRESH_REFRESH_3  = 0x3    // Refresh every 90 us
	DAC_DACCTRL_REFRESH_REFRESH_4  = 0x4    // Refresh every 120 us
	DAC_DACCTRL_REFRESH_REFRESH_5  = 0x5    // Refresh every 150 us
	DAC_DACCTRL_REFRESH_REFRESH_6  = 0x6    // Refresh every 180 us
	DAC_DACCTRL_REFRESH_REFRESH_7  = 0x7    // Refresh every 210 us
	DAC_DACCTRL_REFRESH_REFRESH_8  = 0x8    // Refresh every 240 us
	DAC_DACCTRL_REFRESH_REFRESH_9  = 0x9    // Refresh every 270 us
	DAC_DACCTRL_REFRESH_REFRESH_10 = 0xa    // Refresh every 300 us
	DAC_DACCTRL_REFRESH_REFRESH_11 = 0xb    // Refresh every 330 us
	DAC_DACCTRL_REFRESH_REFRESH_12 = 0xc    // Refresh every 360 us
	DAC_DACCTRL_REFRESH_REFRESH_13 = 0xd    // Refresh every 390 us
	DAC_DACCTRL_REFRESH_REFRESH_14 = 0xe    // Refresh every 420 us
	DAC_DACCTRL_REFRESH_REFRESH_15 = 0xf    // Refresh every 450 us
	DAC_DACCTRL_OSR_Pos            = 0xd    // Position of OSR field.
	DAC_DACCTRL_OSR_Msk            = 0xe000 // Bit mask of OSR field.
	DAC_DACCTRL_OSR_OSR_1          = 0x0    // No Over Sampling
	DAC_DACCTRL_OSR_OSR_2          = 0x1    // 2x Over Sampling Ratio
	DAC_DACCTRL_OSR_OSR_4          = 0x2    // 4x Over Sampling Ratio
	DAC_DACCTRL_OSR_OSR_8          = 0x3    // 8x Over Sampling Ratio
	DAC_DACCTRL_OSR_OSR_16         = 0x4    // 16x Over Sampling Ratio
	DAC_DACCTRL_OSR_OSR_32         = 0x5    // 32x Over Sampling Ratio

	// DATA: DAC n Data
	DAC_DATA_DATA_Pos = 0x0    // Position of DATA field.
	DAC_DATA_DATA_Msk = 0xffff // Bit mask of DATA field.

	// DATABUF: DAC n Data Buffer
	DAC_DATABUF_DATABUF_Pos = 0x0    // Position of DATABUF field.
	DAC_DATABUF_DATABUF_Msk = 0xffff // Bit mask of DATABUF field.

	// DBGCTRL: Debug Control
	DAC_DBGCTRL_DBGRUN_Pos = 0x0 // Position of DBGRUN field.
	DAC_DBGCTRL_DBGRUN_Msk = 0x1 // Bit mask of DBGRUN field.
	DAC_DBGCTRL_DBGRUN     = 0x1 // Bit DBGRUN.

	// RESULT: Filter Result
	DAC_RESULT_RESULT_Pos = 0x0    // Position of RESULT field.
	DAC_RESULT_RESULT_Msk = 0xffff // Bit mask of RESULT field.
)

// Bitfields for DMAC: Direct Memory Access Controller
const (
	// CTRL: Control
	DMAC_CTRL_SWRST_Pos     = 0x0   // Position of SWRST field.
	DMAC_CTRL_SWRST_Msk     = 0x1   // Bit mask of SWRST field.
	DMAC_CTRL_SWRST         = 0x1   // Bit SWRST.
	DMAC_CTRL_DMAENABLE_Pos = 0x1   // Position of DMAENABLE field.
	DMAC_CTRL_DMAENABLE_Msk = 0x2   // Bit mask of DMAENABLE field.
	DMAC_CTRL_DMAENABLE     = 0x2   // Bit DMAENABLE.
	DMAC_CTRL_LVLEN0_Pos    = 0x8   // Position of LVLEN0 field.
	DMAC_CTRL_LVLEN0_Msk    = 0x100 // Bit mask of LVLEN0 field.
	DMAC_CTRL_LVLEN0        = 0x100 // Bit LVLEN0.
	DMAC_CTRL_LVLEN1_Pos    = 0x9   // Position of LVLEN1 field.
	DMAC_CTRL_LVLEN1_Msk    = 0x200 // Bit mask of LVLEN1 field.
	DMAC_CTRL_LVLEN1        = 0x200 // Bit LVLEN1.
	DMAC_CTRL_LVLEN2_Pos    = 0xa   // Position of LVLEN2 field.
	DMAC_CTRL_LVLEN2_Msk    = 0x400 // Bit mask of LVLEN2 field.
	DMAC_CTRL_LVLEN2        = 0x400 // Bit LVLEN2.
	DMAC_CTRL_LVLEN3_Pos    = 0xb   // Position of LVLEN3 field.
	DMAC_CTRL_LVLEN3_Msk    = 0x800 // Bit mask of LVLEN3 field.
	DMAC_CTRL_LVLEN3        = 0x800 // Bit LVLEN3.

	// CRCCTRL: CRC Control
	DMAC_CRCCTRL_CRCBEATSIZE_Pos   = 0x0    // Position of CRCBEATSIZE field.
	DMAC_CRCCTRL_CRCBEATSIZE_Msk   = 0x3    // Bit mask of CRCBEATSIZE field.
	DMAC_CRCCTRL_CRCBEATSIZE_BYTE  = 0x0    // 8-bit bus transfer
	DMAC_CRCCTRL_CRCBEATSIZE_HWORD = 0x1    // 16-bit bus transfer
	DMAC_CRCCTRL_CRCBEATSIZE_WORD  = 0x2    // 32-bit bus transfer
	DMAC_CRCCTRL_CRCPOLY_Pos       = 0x2    // Position of CRCPOLY field.
	DMAC_CRCCTRL_CRCPOLY_Msk       = 0xc    // Bit mask of CRCPOLY field.
	DMAC_CRCCTRL_CRCPOLY_CRC16     = 0x0    // CRC-16 (CRC-CCITT)
	DMAC_CRCCTRL_CRCPOLY_CRC32     = 0x1    // CRC32 (IEEE 802.3)
	DMAC_CRCCTRL_CRCSRC_Pos        = 0x8    // Position of CRCSRC field.
	DMAC_CRCCTRL_CRCSRC_Msk        = 0x3f00 // Bit mask of CRCSRC field.
	DMAC_CRCCTRL_CRCSRC_DISABLE    = 0x0    // CRC Disabled
	DMAC_CRCCTRL_CRCSRC_IO         = 0x1    // I/O interface
	DMAC_CRCCTRL_CRCMODE_Pos       = 0xe    // Position of CRCMODE field.
	DMAC_CRCCTRL_CRCMODE_Msk       = 0xc000 // Bit mask of CRCMODE field.
	DMAC_CRCCTRL_CRCMODE_DEFAULT   = 0x0    // Default operating mode
	DMAC_CRCCTRL_CRCMODE_CRCMON    = 0x2    // Memory CRC monitor operating mode
	DMAC_CRCCTRL_CRCMODE_CRCGEN    = 0x3    // Memory CRC generation operating mode

	// CRCDATAIN: CRC Data Input
	DMAC_CRCDATAIN_CRCDATAIN_Pos = 0x0        // Position of CRCDATAIN field.
	DMAC_CRCDATAIN_CRCDATAIN_Msk = 0xffffffff // Bit mask of CRCDATAIN field.

	// CRCCHKSUM: CRC Checksum
	DMAC_CRCCHKSUM_CRCCHKSUM_Pos = 0x0        // Position of CRCCHKSUM field.
	DMAC_CRCCHKSUM_CRCCHKSUM_Msk = 0xffffffff // Bit mask of CRCCHKSUM field.

	// CRCSTATUS: CRC Status
	DMAC_CRCSTATUS_CRCBUSY_Pos = 0x0 // Position of CRCBUSY field.
	DMAC_CRCSTATUS_CRCBUSY_Msk = 0x1 // Bit mask of CRCBUSY field.
	DMAC_CRCSTATUS_CRCBUSY     = 0x1 // Bit CRCBUSY.
	DMAC_CRCSTATUS_CRCZERO_Pos = 0x1 // Position of CRCZERO field.
	DMAC_CRCSTATUS_CRCZERO_Msk = 0x2 // Bit mask of CRCZERO field.
	DMAC_CRCSTATUS_CRCZERO     = 0x2 // Bit CRCZERO.
	DMAC_CRCSTATUS_CRCERR_Pos  = 0x2 // Position of CRCERR field.
	DMAC_CRCSTATUS_CRCERR_Msk  = 0x4 // Bit mask of CRCERR field.
	DMAC_CRCSTATUS_CRCERR      = 0x4 // Bit CRCERR.

	// DBGCTRL: Debug Control
	DMAC_DBGCTRL_DBGRUN_Pos = 0x0 // Position of DBGRUN field.
	DMAC_DBGCTRL_DBGRUN_Msk = 0x1 // Bit mask of DBGRUN field.
	DMAC_DBGCTRL_DBGRUN     = 0x1 // Bit DBGRUN.

	// SWTRIGCTRL: Software Trigger Control
	DMAC_SWTRIGCTRL_SWTRIG0_Pos  = 0x0        // Position of SWTRIG0 field.
	DMAC_SWTRIGCTRL_SWTRIG0_Msk  = 0x1        // Bit mask of SWTRIG0 field.
	DMAC_SWTRIGCTRL_SWTRIG0      = 0x1        // Bit SWTRIG0.
	DMAC_SWTRIGCTRL_SWTRIG1_Pos  = 0x1        // Position of SWTRIG1 field.
	DMAC_SWTRIGCTRL_SWTRIG1_Msk  = 0x2        // Bit mask of SWTRIG1 field.
	DMAC_SWTRIGCTRL_SWTRIG1      = 0x2        // Bit SWTRIG1.
	DMAC_SWTRIGCTRL_SWTRIG2_Pos  = 0x2        // Position of SWTRIG2 field.
	DMAC_SWTRIGCTRL_SWTRIG2_Msk  = 0x4        // Bit mask of SWTRIG2 field.
	DMAC_SWTRIGCTRL_SWTRIG2      = 0x4        // Bit SWTRIG2.
	DMAC_SWTRIGCTRL_SWTRIG3_Pos  = 0x3        // Position of SWTRIG3 field.
	DMAC_SWTRIGCTRL_SWTRIG3_Msk  = 0x8        // Bit mask of SWTRIG3 field.
	DMAC_SWTRIGCTRL_SWTRIG3      = 0x8        // Bit SWTRIG3.
	DMAC_SWTRIGCTRL_SWTRIG4_Pos  = 0x4        // Position of SWTRIG4 field.
	DMAC_SWTRIGCTRL_SWTRIG4_Msk  = 0x10       // Bit mask of SWTRIG4 field.
	DMAC_SWTRIGCTRL_SWTRIG4      = 0x10       // Bit SWTRIG4.
	DMAC_SWTRIGCTRL_SWTRIG5_Pos  = 0x5        // Position of SWTRIG5 field.
	DMAC_SWTRIGCTRL_SWTRIG5_Msk  = 0x20       // Bit mask of SWTRIG5 field.
	DMAC_SWTRIGCTRL_SWTRIG5      = 0x20       // Bit SWTRIG5.
	DMAC_SWTRIGCTRL_SWTRIG6_Pos  = 0x6        // Position of SWTRIG6 field.
	DMAC_SWTRIGCTRL_SWTRIG6_Msk  = 0x40       // Bit mask of SWTRIG6 field.
	DMAC_SWTRIGCTRL_SWTRIG6      = 0x40       // Bit SWTRIG6.
	DMAC_SWTRIGCTRL_SWTRIG7_Pos  = 0x7        // Position of SWTRIG7 field.
	DMAC_SWTRIGCTRL_SWTRIG7_Msk  = 0x80       // Bit mask of SWTRIG7 field.
	DMAC_SWTRIGCTRL_SWTRIG7      = 0x80       // Bit SWTRIG7.
	DMAC_SWTRIGCTRL_SWTRIG8_Pos  = 0x8        // Position of SWTRIG8 field.
	DMAC_SWTRIGCTRL_SWTRIG8_Msk  = 0x100      // Bit mask of SWTRIG8 field.
	DMAC_SWTRIGCTRL_SWTRIG8      = 0x100      // Bit SWTRIG8.
	DMAC_SWTRIGCTRL_SWTRIG9_Pos  = 0x9        // Position of SWTRIG9 field.
	DMAC_SWTRIGCTRL_SWTRIG9_Msk  = 0x200      // Bit mask of SWTRIG9 field.
	DMAC_SWTRIGCTRL_SWTRIG9      = 0x200      // Bit SWTRIG9.
	DMAC_SWTRIGCTRL_SWTRIG10_Pos = 0xa        // Position of SWTRIG10 field.
	DMAC_SWTRIGCTRL_SWTRIG10_Msk = 0x400      // Bit mask of SWTRIG10 field.
	DMAC_SWTRIGCTRL_SWTRIG10     = 0x400      // Bit SWTRIG10.
	DMAC_SWTRIGCTRL_SWTRIG11_Pos = 0xb        // Position of SWTRIG11 field.
	DMAC_SWTRIGCTRL_SWTRIG11_Msk = 0x800      // Bit mask of SWTRIG11 field.
	DMAC_SWTRIGCTRL_SWTRIG11     = 0x800      // Bit SWTRIG11.
	DMAC_SWTRIGCTRL_SWTRIG12_Pos = 0xc        // Position of SWTRIG12 field.
	DMAC_SWTRIGCTRL_SWTRIG12_Msk = 0x1000     // Bit mask of SWTRIG12 field.
	DMAC_SWTRIGCTRL_SWTRIG12     = 0x1000     // Bit SWTRIG12.
	DMAC_SWTRIGCTRL_SWTRIG13_Pos = 0xd        // Position of SWTRIG13 field.
	DMAC_SWTRIGCTRL_SWTRIG13_Msk = 0x2000     // Bit mask of SWTRIG13 field.
	DMAC_SWTRIGCTRL_SWTRIG13     = 0x2000     // Bit SWTRIG13.
	DMAC_SWTRIGCTRL_SWTRIG14_Pos = 0xe        // Position of SWTRIG14 field.
	DMAC_SWTRIGCTRL_SWTRIG14_Msk = 0x4000     // Bit mask of SWTRIG14 field.
	DMAC_SWTRIGCTRL_SWTRIG14     = 0x4000     // Bit SWTRIG14.
	DMAC_SWTRIGCTRL_SWTRIG15_Pos = 0xf        // Position of SWTRIG15 field.
	DMAC_SWTRIGCTRL_SWTRIG15_Msk = 0x8000     // Bit mask of SWTRIG15 field.
	DMAC_SWTRIGCTRL_SWTRIG15     = 0x8000     // Bit SWTRIG15.
	DMAC_SWTRIGCTRL_SWTRIG16_Pos = 0x10       // Position of SWTRIG16 field.
	DMAC_SWTRIGCTRL_SWTRIG16_Msk = 0x10000    // Bit mask of SWTRIG16 field.
	DMAC_SWTRIGCTRL_SWTRIG16     = 0x10000    // Bit SWTRIG16.
	DMAC_SWTRIGCTRL_SWTRIG17_Pos = 0x11       // Position of SWTRIG17 field.
	DMAC_SWTRIGCTRL_SWTRIG17_Msk = 0x20000    // Bit mask of SWTRIG17 field.
	DMAC_SWTRIGCTRL_SWTRIG17     = 0x20000    // Bit SWTRIG17.
	DMAC_SWTRIGCTRL_SWTRIG18_Pos = 0x12       // Position of SWTRIG18 field.
	DMAC_SWTRIGCTRL_SWTRIG18_Msk = 0x40000    // Bit mask of SWTRIG18 field.
	DMAC_SWTRIGCTRL_SWTRIG18     = 0x40000    // Bit SWTRIG18.
	DMAC_SWTRIGCTRL_SWTRIG19_Pos = 0x13       // Position of SWTRIG19 field.
	DMAC_SWTRIGCTRL_SWTRIG19_Msk = 0x80000    // Bit mask of SWTRIG19 field.
	DMAC_SWTRIGCTRL_SWTRIG19     = 0x80000    // Bit SWTRIG19.
	DMAC_SWTRIGCTRL_SWTRIG20_Pos = 0x14       // Position of SWTRIG20 field.
	DMAC_SWTRIGCTRL_SWTRIG20_Msk = 0x100000   // Bit mask of SWTRIG20 field.
	DMAC_SWTRIGCTRL_SWTRIG20     = 0x100000   // Bit SWTRIG20.
	DMAC_SWTRIGCTRL_SWTRIG21_Pos = 0x15       // Position of SWTRIG21 field.
	DMAC_SWTRIGCTRL_SWTRIG21_Msk = 0x200000   // Bit mask of SWTRIG21 field.
	DMAC_SWTRIGCTRL_SWTRIG21     = 0x200000   // Bit SWTRIG21.
	DMAC_SWTRIGCTRL_SWTRIG22_Pos = 0x16       // Position of SWTRIG22 field.
	DMAC_SWTRIGCTRL_SWTRIG22_Msk = 0x400000   // Bit mask of SWTRIG22 field.
	DMAC_SWTRIGCTRL_SWTRIG22     = 0x400000   // Bit SWTRIG22.
	DMAC_SWTRIGCTRL_SWTRIG23_Pos = 0x17       // Position of SWTRIG23 field.
	DMAC_SWTRIGCTRL_SWTRIG23_Msk = 0x800000   // Bit mask of SWTRIG23 field.
	DMAC_SWTRIGCTRL_SWTRIG23     = 0x800000   // Bit SWTRIG23.
	DMAC_SWTRIGCTRL_SWTRIG24_Pos = 0x18       // Position of SWTRIG24 field.
	DMAC_SWTRIGCTRL_SWTRIG24_Msk = 0x1000000  // Bit mask of SWTRIG24 field.
	DMAC_SWTRIGCTRL_SWTRIG24     = 0x1000000  // Bit SWTRIG24.
	DMAC_SWTRIGCTRL_SWTRIG25_Pos = 0x19       // Position of SWTRIG25 field.
	DMAC_SWTRIGCTRL_SWTRIG25_Msk = 0x2000000  // Bit mask of SWTRIG25 field.
	DMAC_SWTRIGCTRL_SWTRIG25     = 0x2000000  // Bit SWTRIG25.
	DMAC_SWTRIGCTRL_SWTRIG26_Pos = 0x1a       // Position of SWTRIG26 field.
	DMAC_SWTRIGCTRL_SWTRIG26_Msk = 0x4000000  // Bit mask of SWTRIG26 field.
	DMAC_SWTRIGCTRL_SWTRIG26     = 0x4000000  // Bit SWTRIG26.
	DMAC_SWTRIGCTRL_SWTRIG27_Pos = 0x1b       // Position of SWTRIG27 field.
	DMAC_SWTRIGCTRL_SWTRIG27_Msk = 0x8000000  // Bit mask of SWTRIG27 field.
	DMAC_SWTRIGCTRL_SWTRIG27     = 0x8000000  // Bit SWTRIG27.
	DMAC_SWTRIGCTRL_SWTRIG28_Pos = 0x1c       // Position of SWTRIG28 field.
	DMAC_SWTRIGCTRL_SWTRIG28_Msk = 0x10000000 // Bit mask of SWTRIG28 field.
	DMAC_SWTRIGCTRL_SWTRIG28     = 0x10000000 // Bit SWTRIG28.
	DMAC_SWTRIGCTRL_SWTRIG29_Pos = 0x1d       // Position of SWTRIG29 field.
	DMAC_SWTRIGCTRL_SWTRIG29_Msk = 0x20000000 // Bit mask of SWTRIG29 field.
	DMAC_SWTRIGCTRL_SWTRIG29     = 0x20000000 // Bit SWTRIG29.
	DMAC_SWTRIGCTRL_SWTRIG30_Pos = 0x1e       // Position of SWTRIG30 field.
	DMAC_SWTRIGCTRL_SWTRIG30_Msk = 0x40000000 // Bit mask of SWTRIG30 field.
	DMAC_SWTRIGCTRL_SWTRIG30     = 0x40000000 // Bit SWTRIG30.
	DMAC_SWTRIGCTRL_SWTRIG31_Pos = 0x1f       // Position of SWTRIG31 field.
	DMAC_SWTRIGCTRL_SWTRIG31_Msk = 0x80000000 // Bit mask of SWTRIG31 field.
	DMAC_SWTRIGCTRL_SWTRIG31     = 0x80000000 // Bit SWTRIG31.

	// PRICTRL0: Priority Control 0
	DMAC_PRICTRL0_LVLPRI0_Pos    = 0x0        // Position of LVLPRI0 field.
	DMAC_PRICTRL0_LVLPRI0_Msk    = 0x1f       // Bit mask of LVLPRI0 field.
	DMAC_PRICTRL0_QOS0_Pos       = 0x5        // Position of QOS0 field.
	DMAC_PRICTRL0_QOS0_Msk       = 0x60       // Bit mask of QOS0 field.
	DMAC_PRICTRL0_QOS0_REGULAR   = 0x0        // Regular delivery
	DMAC_PRICTRL0_QOS0_SHORTAGE  = 0x1        // Bandwidth shortage
	DMAC_PRICTRL0_QOS0_SENSITIVE = 0x2        // Latency sensitive
	DMAC_PRICTRL0_QOS0_CRITICAL  = 0x3        // Latency critical
	DMAC_PRICTRL0_RRLVLEN0_Pos   = 0x7        // Position of RRLVLEN0 field.
	DMAC_PRICTRL0_RRLVLEN0_Msk   = 0x80       // Bit mask of RRLVLEN0 field.
	DMAC_PRICTRL0_RRLVLEN0       = 0x80       // Bit RRLVLEN0.
	DMAC_PRICTRL0_LVLPRI1_Pos    = 0x8        // Position of LVLPRI1 field.
	DMAC_PRICTRL0_LVLPRI1_Msk    = 0x1f00     // Bit mask of LVLPRI1 field.
	DMAC_PRICTRL0_QOS1_Pos       = 0xd        // Position of QOS1 field.
	DMAC_PRICTRL0_QOS1_Msk       = 0x6000     // Bit mask of QOS1 field.
	DMAC_PRICTRL0_QOS1_REGULAR   = 0x0        // Regular delivery
	DMAC_PRICTRL0_QOS1_SHORTAGE  = 0x1        // Bandwidth shortage
	DMAC_PRICTRL0_QOS1_SENSITIVE = 0x2        // Latency sensitive
	DMAC_PRICTRL0_QOS1_CRITICAL  = 0x3        // Latency critical
	DMAC_PRICTRL0_RRLVLEN1_Pos   = 0xf        // Position of RRLVLEN1 field.
	DMAC_PRICTRL0_RRLVLEN1_Msk   = 0x8000     // Bit mask of RRLVLEN1 field.
	DMAC_PRICTRL0_RRLVLEN1       = 0x8000     // Bit RRLVLEN1.
	DMAC_PRICTRL0_LVLPRI2_Pos    = 0x10       // Position of LVLPRI2 field.
	DMAC_PRICTRL0_LVLPRI2_Msk    = 0x1f0000   // Bit mask of LVLPRI2 field.
	DMAC_PRICTRL0_QOS2_Pos       = 0x15       // Position of QOS2 field.
	DMAC_PRICTRL0_QOS2_Msk       = 0x600000   // Bit mask of QOS2 field.
	DMAC_PRICTRL0_QOS2_REGULAR   = 0x0        // Regular delivery
	DMAC_PRICTRL0_QOS2_SHORTAGE  = 0x1        // Bandwidth shortage
	DMAC_PRICTRL0_QOS2_SENSITIVE = 0x2        // Latency sensitive
	DMAC_PRICTRL0_QOS2_CRITICAL  = 0x3        // Latency critical
	DMAC_PRICTRL0_RRLVLEN2_Pos   = 0x17       // Position of RRLVLEN2 field.
	DMAC_PRICTRL0_RRLVLEN2_Msk   = 0x800000   // Bit mask of RRLVLEN2 field.
	DMAC_PRICTRL0_RRLVLEN2       = 0x800000   // Bit RRLVLEN2.
	DMAC_PRICTRL0_LVLPRI3_Pos    = 0x18       // Position of LVLPRI3 field.
	DMAC_PRICTRL0_LVLPRI3_Msk    = 0x1f000000 // Bit mask of LVLPRI3 field.
	DMAC_PRICTRL0_QOS3_Pos       = 0x1d       // Position of QOS3 field.
	DMAC_PRICTRL0_QOS3_Msk       = 0x60000000 // Bit mask of QOS3 field.
	DMAC_PRICTRL0_QOS3_REGULAR   = 0x0        // Regular delivery
	DMAC_PRICTRL0_QOS3_SHORTAGE  = 0x1        // Bandwidth shortage
	DMAC_PRICTRL0_QOS3_SENSITIVE = 0x2        // Latency sensitive
	DMAC_PRICTRL0_QOS3_CRITICAL  = 0x3        // Latency critical
	DMAC_PRICTRL0_RRLVLEN3_Pos   = 0x1f       // Position of RRLVLEN3 field.
	DMAC_PRICTRL0_RRLVLEN3_Msk   = 0x80000000 // Bit mask of RRLVLEN3 field.
	DMAC_PRICTRL0_RRLVLEN3       = 0x80000000 // Bit RRLVLEN3.

	// INTPEND: Interrupt Pending
	DMAC_INTPEND_ID_Pos     = 0x0    // Position of ID field.
	DMAC_INTPEND_ID_Msk     = 0x1f   // Bit mask of ID field.
	DMAC_INTPEND_TERR_Pos   = 0x8    // Position of TERR field.
	DMAC_INTPEND_TERR_Msk   = 0x100  // Bit mask of TERR field.
	DMAC_INTPEND_TERR       = 0x100  // Bit TERR.
	DMAC_INTPEND_TCMPL_Pos  = 0x9    // Position of TCMPL field.
	DMAC_INTPEND_TCMPL_Msk  = 0x200  // Bit mask of TCMPL field.
	DMAC_INTPEND_TCMPL      = 0x200  // Bit TCMPL.
	DMAC_INTPEND_SUSP_Pos   = 0xa    // Position of SUSP field.
	DMAC_INTPEND_SUSP_Msk   = 0x400  // Bit mask of SUSP field.
	DMAC_INTPEND_SUSP       = 0x400  // Bit SUSP.
	DMAC_INTPEND_CRCERR_Pos = 0xc    // Position of CRCERR field.
	DMAC_INTPEND_CRCERR_Msk = 0x1000 // Bit mask of CRCERR field.
	DMAC_INTPEND_CRCERR     = 0x1000 // Bit CRCERR.
	DMAC_INTPEND_FERR_Pos   = 0xd    // Position of FERR field.
	DMAC_INTPEND_FERR_Msk   = 0x2000 // Bit mask of FERR field.
	DMAC_INTPEND_FERR       = 0x2000 // Bit FERR.
	DMAC_INTPEND_BUSY_Pos   = 0xe    // Position of BUSY field.
	DMAC_INTPEND_BUSY_Msk   = 0x4000 // Bit mask of BUSY field.
	DMAC_INTPEND_BUSY       = 0x4000 // Bit BUSY.
	DMAC_INTPEND_PEND_Pos   = 0xf    // Position of PEND field.
	DMAC_INTPEND_PEND_Msk   = 0x8000 // Bit mask of PEND field.
	DMAC_INTPEND_PEND       = 0x8000 // Bit PEND.

	// INTSTATUS: Interrupt Status
	DMAC_INTSTATUS_CHINT0_Pos  = 0x0        // Position of CHINT0 field.
	DMAC_INTSTATUS_CHINT0_Msk  = 0x1        // Bit mask of CHINT0 field.
	DMAC_INTSTATUS_CHINT0      = 0x1        // Bit CHINT0.
	DMAC_INTSTATUS_CHINT1_Pos  = 0x1        // Position of CHINT1 field.
	DMAC_INTSTATUS_CHINT1_Msk  = 0x2        // Bit mask of CHINT1 field.
	DMAC_INTSTATUS_CHINT1      = 0x2        // Bit CHINT1.
	DMAC_INTSTATUS_CHINT2_Pos  = 0x2        // Position of CHINT2 field.
	DMAC_INTSTATUS_CHINT2_Msk  = 0x4        // Bit mask of CHINT2 field.
	DMAC_INTSTATUS_CHINT2      = 0x4        // Bit CHINT2.
	DMAC_INTSTATUS_CHINT3_Pos  = 0x3        // Position of CHINT3 field.
	DMAC_INTSTATUS_CHINT3_Msk  = 0x8        // Bit mask of CHINT3 field.
	DMAC_INTSTATUS_CHINT3      = 0x8        // Bit CHINT3.
	DMAC_INTSTATUS_CHINT4_Pos  = 0x4        // Position of CHINT4 field.
	DMAC_INTSTATUS_CHINT4_Msk  = 0x10       // Bit mask of CHINT4 field.
	DMAC_INTSTATUS_CHINT4      = 0x10       // Bit CHINT4.
	DMAC_INTSTATUS_CHINT5_Pos  = 0x5        // Position of CHINT5 field.
	DMAC_INTSTATUS_CHINT5_Msk  = 0x20       // Bit mask of CHINT5 field.
	DMAC_INTSTATUS_CHINT5      = 0x20       // Bit CHINT5.
	DMAC_INTSTATUS_CHINT6_Pos  = 0x6        // Position of CHINT6 field.
	DMAC_INTSTATUS_CHINT6_Msk  = 0x40       // Bit mask of CHINT6 field.
	DMAC_INTSTATUS_CHINT6      = 0x40       // Bit CHINT6.
	DMAC_INTSTATUS_CHINT7_Pos  = 0x7        // Position of CHINT7 field.
	DMAC_INTSTATUS_CHINT7_Msk  = 0x80       // Bit mask of CHINT7 field.
	DMAC_INTSTATUS_CHINT7      = 0x80       // Bit CHINT7.
	DMAC_INTSTATUS_CHINT8_Pos  = 0x8        // Position of CHINT8 field.
	DMAC_INTSTATUS_CHINT8_Msk  = 0x100      // Bit mask of CHINT8 field.
	DMAC_INTSTATUS_CHINT8      = 0x100      // Bit CHINT8.
	DMAC_INTSTATUS_CHINT9_Pos  = 0x9        // Position of CHINT9 field.
	DMAC_INTSTATUS_CHINT9_Msk  = 0x200      // Bit mask of CHINT9 field.
	DMAC_INTSTATUS_CHINT9      = 0x200      // Bit CHINT9.
	DMAC_INTSTATUS_CHINT10_Pos = 0xa        // Position of CHINT10 field.
	DMAC_INTSTATUS_CHINT10_Msk = 0x400      // Bit mask of CHINT10 field.
	DMAC_INTSTATUS_CHINT10     = 0x400      // Bit CHINT10.
	DMAC_INTSTATUS_CHINT11_Pos = 0xb        // Position of CHINT11 field.
	DMAC_INTSTATUS_CHINT11_Msk = 0x800      // Bit mask of CHINT11 field.
	DMAC_INTSTATUS_CHINT11     = 0x800      // Bit CHINT11.
	DMAC_INTSTATUS_CHINT12_Pos = 0xc        // Position of CHINT12 field.
	DMAC_INTSTATUS_CHINT12_Msk = 0x1000     // Bit mask of CHINT12 field.
	DMAC_INTSTATUS_CHINT12     = 0x1000     // Bit CHINT12.
	DMAC_INTSTATUS_CHINT13_Pos = 0xd        // Position of CHINT13 field.
	DMAC_INTSTATUS_CHINT13_Msk = 0x2000     // Bit mask of CHINT13 field.
	DMAC_INTSTATUS_CHINT13     = 0x2000     // Bit CHINT13.
	DMAC_INTSTATUS_CHINT14_Pos = 0xe        // Position of CHINT14 field.
	DMAC_INTSTATUS_CHINT14_Msk = 0x4000     // Bit mask of CHINT14 field.
	DMAC_INTSTATUS_CHINT14     = 0x4000     // Bit CHINT14.
	DMAC_INTSTATUS_CHINT15_Pos = 0xf        // Position of CHINT15 field.
	DMAC_INTSTATUS_CHINT15_Msk = 0x8000     // Bit mask of CHINT15 field.
	DMAC_INTSTATUS_CHINT15     = 0x8000     // Bit CHINT15.
	DMAC_INTSTATUS_CHINT16_Pos = 0x10       // Position of CHINT16 field.
	DMAC_INTSTATUS_CHINT16_Msk = 0x10000    // Bit mask of CHINT16 field.
	DMAC_INTSTATUS_CHINT16     = 0x10000    // Bit CHINT16.
	DMAC_INTSTATUS_CHINT17_Pos = 0x11       // Position of CHINT17 field.
	DMAC_INTSTATUS_CHINT17_Msk = 0x20000    // Bit mask of CHINT17 field.
	DMAC_INTSTATUS_CHINT17     = 0x20000    // Bit CHINT17.
	DMAC_INTSTATUS_CHINT18_Pos = 0x12       // Position of CHINT18 field.
	DMAC_INTSTATUS_CHINT18_Msk = 0x40000    // Bit mask of CHINT18 field.
	DMAC_INTSTATUS_CHINT18     = 0x40000    // Bit CHINT18.
	DMAC_INTSTATUS_CHINT19_Pos = 0x13       // Position of CHINT19 field.
	DMAC_INTSTATUS_CHINT19_Msk = 0x80000    // Bit mask of CHINT19 field.
	DMAC_INTSTATUS_CHINT19     = 0x80000    // Bit CHINT19.
	DMAC_INTSTATUS_CHINT20_Pos = 0x14       // Position of CHINT20 field.
	DMAC_INTSTATUS_CHINT20_Msk = 0x100000   // Bit mask of CHINT20 field.
	DMAC_INTSTATUS_CHINT20     = 0x100000   // Bit CHINT20.
	DMAC_INTSTATUS_CHINT21_Pos = 0x15       // Position of CHINT21 field.
	DMAC_INTSTATUS_CHINT21_Msk = 0x200000   // Bit mask of CHINT21 field.
	DMAC_INTSTATUS_CHINT21     = 0x200000   // Bit CHINT21.
	DMAC_INTSTATUS_CHINT22_Pos = 0x16       // Position of CHINT22 field.
	DMAC_INTSTATUS_CHINT22_Msk = 0x400000   // Bit mask of CHINT22 field.
	DMAC_INTSTATUS_CHINT22     = 0x400000   // Bit CHINT22.
	DMAC_INTSTATUS_CHINT23_Pos = 0x17       // Position of CHINT23 field.
	DMAC_INTSTATUS_CHINT23_Msk = 0x800000   // Bit mask of CHINT23 field.
	DMAC_INTSTATUS_CHINT23     = 0x800000   // Bit CHINT23.
	DMAC_INTSTATUS_CHINT24_Pos = 0x18       // Position of CHINT24 field.
	DMAC_INTSTATUS_CHINT24_Msk = 0x1000000  // Bit mask of CHINT24 field.
	DMAC_INTSTATUS_CHINT24     = 0x1000000  // Bit CHINT24.
	DMAC_INTSTATUS_CHINT25_Pos = 0x19       // Position of CHINT25 field.
	DMAC_INTSTATUS_CHINT25_Msk = 0x2000000  // Bit mask of CHINT25 field.
	DMAC_INTSTATUS_CHINT25     = 0x2000000  // Bit CHINT25.
	DMAC_INTSTATUS_CHINT26_Pos = 0x1a       // Position of CHINT26 field.
	DMAC_INTSTATUS_CHINT26_Msk = 0x4000000  // Bit mask of CHINT26 field.
	DMAC_INTSTATUS_CHINT26     = 0x4000000  // Bit CHINT26.
	DMAC_INTSTATUS_CHINT27_Pos = 0x1b       // Position of CHINT27 field.
	DMAC_INTSTATUS_CHINT27_Msk = 0x8000000  // Bit mask of CHINT27 field.
	DMAC_INTSTATUS_CHINT27     = 0x8000000  // Bit CHINT27.
	DMAC_INTSTATUS_CHINT28_Pos = 0x1c       // Position of CHINT28 field.
	DMAC_INTSTATUS_CHINT28_Msk = 0x10000000 // Bit mask of CHINT28 field.
	DMAC_INTSTATUS_CHINT28     = 0x10000000 // Bit CHINT28.
	DMAC_INTSTATUS_CHINT29_Pos = 0x1d       // Position of CHINT29 field.
	DMAC_INTSTATUS_CHINT29_Msk = 0x20000000 // Bit mask of CHINT29 field.
	DMAC_INTSTATUS_CHINT29     = 0x20000000 // Bit CHINT29.
	DMAC_INTSTATUS_CHINT30_Pos = 0x1e       // Position of CHINT30 field.
	DMAC_INTSTATUS_CHINT30_Msk = 0x40000000 // Bit mask of CHINT30 field.
	DMAC_INTSTATUS_CHINT30     = 0x40000000 // Bit CHINT30.
	DMAC_INTSTATUS_CHINT31_Pos = 0x1f       // Position of CHINT31 field.
	DMAC_INTSTATUS_CHINT31_Msk = 0x80000000 // Bit mask of CHINT31 field.
	DMAC_INTSTATUS_CHINT31     = 0x80000000 // Bit CHINT31.

	// BUSYCH: Busy Channels
	DMAC_BUSYCH_BUSYCH0_Pos  = 0x0        // Position of BUSYCH0 field.
	DMAC_BUSYCH_BUSYCH0_Msk  = 0x1        // Bit mask of BUSYCH0 field.
	DMAC_BUSYCH_BUSYCH0      = 0x1        // Bit BUSYCH0.
	DMAC_BUSYCH_BUSYCH1_Pos  = 0x1        // Position of BUSYCH1 field.
	DMAC_BUSYCH_BUSYCH1_Msk  = 0x2        // Bit mask of BUSYCH1 field.
	DMAC_BUSYCH_BUSYCH1      = 0x2        // Bit BUSYCH1.
	DMAC_BUSYCH_BUSYCH2_Pos  = 0x2        // Position of BUSYCH2 field.
	DMAC_BUSYCH_BUSYCH2_Msk  = 0x4        // Bit mask of BUSYCH2 field.
	DMAC_BUSYCH_BUSYCH2      = 0x4        // Bit BUSYCH2.
	DMAC_BUSYCH_BUSYCH3_Pos  = 0x3        // Position of BUSYCH3 field.
	DMAC_BUSYCH_BUSYCH3_Msk  = 0x8        // Bit mask of BUSYCH3 field.
	DMAC_BUSYCH_BUSYCH3      = 0x8        // Bit BUSYCH3.
	DMAC_BUSYCH_BUSYCH4_Pos  = 0x4        // Position of BUSYCH4 field.
	DMAC_BUSYCH_BUSYCH4_Msk  = 0x10       // Bit mask of BUSYCH4 field.
	DMAC_BUSYCH_BUSYCH4      = 0x10       // Bit BUSYCH4.
	DMAC_BUSYCH_BUSYCH5_Pos  = 0x5        // Position of BUSYCH5 field.
	DMAC_BUSYCH_BUSYCH5_Msk  = 0x20       // Bit mask of BUSYCH5 field.
	DMAC_BUSYCH_BUSYCH5      = 0x20       // Bit BUSYCH5.
	DMAC_BUSYCH_BUSYCH6_Pos  = 0x6        // Position of BUSYCH6 field.
	DMAC_BUSYCH_BUSYCH6_Msk  = 0x40       // Bit mask of BUSYCH6 field.
	DMAC_BUSYCH_BUSYCH6      = 0x40       // Bit BUSYCH6.
	DMAC_BUSYCH_BUSYCH7_Pos  = 0x7        // Position of BUSYCH7 field.
	DMAC_BUSYCH_BUSYCH7_Msk  = 0x80       // Bit mask of BUSYCH7 field.
	DMAC_BUSYCH_BUSYCH7      = 0x80       // Bit BUSYCH7.
	DMAC_BUSYCH_BUSYCH8_Pos  = 0x8        // Position of BUSYCH8 field.
	DMAC_BUSYCH_BUSYCH8_Msk  = 0x100      // Bit mask of BUSYCH8 field.
	DMAC_BUSYCH_BUSYCH8      = 0x100      // Bit BUSYCH8.
	DMAC_BUSYCH_BUSYCH9_Pos  = 0x9        // Position of BUSYCH9 field.
	DMAC_BUSYCH_BUSYCH9_Msk  = 0x200      // Bit mask of BUSYCH9 field.
	DMAC_BUSYCH_BUSYCH9      = 0x200      // Bit BUSYCH9.
	DMAC_BUSYCH_BUSYCH10_Pos = 0xa        // Position of BUSYCH10 field.
	DMAC_BUSYCH_BUSYCH10_Msk = 0x400      // Bit mask of BUSYCH10 field.
	DMAC_BUSYCH_BUSYCH10     = 0x400      // Bit BUSYCH10.
	DMAC_BUSYCH_BUSYCH11_Pos = 0xb        // Position of BUSYCH11 field.
	DMAC_BUSYCH_BUSYCH11_Msk = 0x800      // Bit mask of BUSYCH11 field.
	DMAC_BUSYCH_BUSYCH11     = 0x800      // Bit BUSYCH11.
	DMAC_BUSYCH_BUSYCH12_Pos = 0xc        // Position of BUSYCH12 field.
	DMAC_BUSYCH_BUSYCH12_Msk = 0x1000     // Bit mask of BUSYCH12 field.
	DMAC_BUSYCH_BUSYCH12     = 0x1000     // Bit BUSYCH12.
	DMAC_BUSYCH_BUSYCH13_Pos = 0xd        // Position of BUSYCH13 field.
	DMAC_BUSYCH_BUSYCH13_Msk = 0x2000     // Bit mask of BUSYCH13 field.
	DMAC_BUSYCH_BUSYCH13     = 0x2000     // Bit BUSYCH13.
	DMAC_BUSYCH_BUSYCH14_Pos = 0xe        // Position of BUSYCH14 field.
	DMAC_BUSYCH_BUSYCH14_Msk = 0x4000     // Bit mask of BUSYCH14 field.
	DMAC_BUSYCH_BUSYCH14     = 0x4000     // Bit BUSYCH14.
	DMAC_BUSYCH_BUSYCH15_Pos = 0xf        // Position of BUSYCH15 field.
	DMAC_BUSYCH_BUSYCH15_Msk = 0x8000     // Bit mask of BUSYCH15 field.
	DMAC_BUSYCH_BUSYCH15     = 0x8000     // Bit BUSYCH15.
	DMAC_BUSYCH_BUSYCH16_Pos = 0x10       // Position of BUSYCH16 field.
	DMAC_BUSYCH_BUSYCH16_Msk = 0x10000    // Bit mask of BUSYCH16 field.
	DMAC_BUSYCH_BUSYCH16     = 0x10000    // Bit BUSYCH16.
	DMAC_BUSYCH_BUSYCH17_Pos = 0x11       // Position of BUSYCH17 field.
	DMAC_BUSYCH_BUSYCH17_Msk = 0x20000    // Bit mask of BUSYCH17 field.
	DMAC_BUSYCH_BUSYCH17     = 0x20000    // Bit BUSYCH17.
	DMAC_BUSYCH_BUSYCH18_Pos = 0x12       // Position of BUSYCH18 field.
	DMAC_BUSYCH_BUSYCH18_Msk = 0x40000    // Bit mask of BUSYCH18 field.
	DMAC_BUSYCH_BUSYCH18     = 0x40000    // Bit BUSYCH18.
	DMAC_BUSYCH_BUSYCH19_Pos = 0x13       // Position of BUSYCH19 field.
	DMAC_BUSYCH_BUSYCH19_Msk = 0x80000    // Bit mask of BUSYCH19 field.
	DMAC_BUSYCH_BUSYCH19     = 0x80000    // Bit BUSYCH19.
	DMAC_BUSYCH_BUSYCH20_Pos = 0x14       // Position of BUSYCH20 field.
	DMAC_BUSYCH_BUSYCH20_Msk = 0x100000   // Bit mask of BUSYCH20 field.
	DMAC_BUSYCH_BUSYCH20     = 0x100000   // Bit BUSYCH20.
	DMAC_BUSYCH_BUSYCH21_Pos = 0x15       // Position of BUSYCH21 field.
	DMAC_BUSYCH_BUSYCH21_Msk = 0x200000   // Bit mask of BUSYCH21 field.
	DMAC_BUSYCH_BUSYCH21     = 0x200000   // Bit BUSYCH21.
	DMAC_BUSYCH_BUSYCH22_Pos = 0x16       // Position of BUSYCH22 field.
	DMAC_BUSYCH_BUSYCH22_Msk = 0x400000   // Bit mask of BUSYCH22 field.
	DMAC_BUSYCH_BUSYCH22     = 0x400000   // Bit BUSYCH22.
	DMAC_BUSYCH_BUSYCH23_Pos = 0x17       // Position of BUSYCH23 field.
	DMAC_BUSYCH_BUSYCH23_Msk = 0x800000   // Bit mask of BUSYCH23 field.
	DMAC_BUSYCH_BUSYCH23     = 0x800000   // Bit BUSYCH23.
	DMAC_BUSYCH_BUSYCH24_Pos = 0x18       // Position of BUSYCH24 field.
	DMAC_BUSYCH_BUSYCH24_Msk = 0x1000000  // Bit mask of BUSYCH24 field.
	DMAC_BUSYCH_BUSYCH24     = 0x1000000  // Bit BUSYCH24.
	DMAC_BUSYCH_BUSYCH25_Pos = 0x19       // Position of BUSYCH25 field.
	DMAC_BUSYCH_BUSYCH25_Msk = 0x2000000  // Bit mask of BUSYCH25 field.
	DMAC_BUSYCH_BUSYCH25     = 0x2000000  // Bit BUSYCH25.
	DMAC_BUSYCH_BUSYCH26_Pos = 0x1a       // Position of BUSYCH26 field.
	DMAC_BUSYCH_BUSYCH26_Msk = 0x4000000  // Bit mask of BUSYCH26 field.
	DMAC_BUSYCH_BUSYCH26     = 0x4000000  // Bit BUSYCH26.
	DMAC_BUSYCH_BUSYCH27_Pos = 0x1b       // Position of BUSYCH27 field.
	DMAC_BUSYCH_BUSYCH27_Msk = 0x8000000  // Bit mask of BUSYCH27 field.
	DMAC_BUSYCH_BUSYCH27     = 0x8000000  // Bit BUSYCH27.
	DMAC_BUSYCH_BUSYCH28_Pos = 0x1c       // Position of BUSYCH28 field.
	DMAC_BUSYCH_BUSYCH28_Msk = 0x10000000 // Bit mask of BUSYCH28 field.
	DMAC_BUSYCH_BUSYCH28     = 0x10000000 // Bit BUSYCH28.
	DMAC_BUSYCH_BUSYCH29_Pos = 0x1d       // Position of BUSYCH29 field.
	DMAC_BUSYCH_BUSYCH29_Msk = 0x20000000 // Bit mask of BUSYCH29 field.
	DMAC_BUSYCH_BUSYCH29     = 0x20000000 // Bit BUSYCH29.
	DMAC_BUSYCH_BUSYCH30_Pos = 0x1e       // Position of BUSYCH30 field.
	DMAC_BUSYCH_BUSYCH30_Msk = 0x40000000 // Bit mask of BUSYCH30 field.
	DMAC_BUSYCH_BUSYCH30     = 0x40000000 // Bit BUSYCH30.
	DMAC_BUSYCH_BUSYCH31_Pos = 0x1f       // Position of BUSYCH31 field.
	DMAC_BUSYCH_BUSYCH31_Msk = 0x80000000 // Bit mask of BUSYCH31 field.
	DMAC_BUSYCH_BUSYCH31     = 0x80000000 // Bit BUSYCH31.

	// PENDCH: Pending Channels
	DMAC_PENDCH_PENDCH0_Pos  = 0x0        // Position of PENDCH0 field.
	DMAC_PENDCH_PENDCH0_Msk  = 0x1        // Bit mask of PENDCH0 field.
	DMAC_PENDCH_PENDCH0      = 0x1        // Bit PENDCH0.
	DMAC_PENDCH_PENDCH1_Pos  = 0x1        // Position of PENDCH1 field.
	DMAC_PENDCH_PENDCH1_Msk  = 0x2        // Bit mask of PENDCH1 field.
	DMAC_PENDCH_PENDCH1      = 0x2        // Bit PENDCH1.
	DMAC_PENDCH_PENDCH2_Pos  = 0x2        // Position of PENDCH2 field.
	DMAC_PENDCH_PENDCH2_Msk  = 0x4        // Bit mask of PENDCH2 field.
	DMAC_PENDCH_PENDCH2      = 0x4        // Bit PENDCH2.
	DMAC_PENDCH_PENDCH3_Pos  = 0x3        // Position of PENDCH3 field.
	DMAC_PENDCH_PENDCH3_Msk  = 0x8        // Bit mask of PENDCH3 field.
	DMAC_PENDCH_PENDCH3      = 0x8        // Bit PENDCH3.
	DMAC_PENDCH_PENDCH4_Pos  = 0x4        // Position of PENDCH4 field.
	DMAC_PENDCH_PENDCH4_Msk  = 0x10       // Bit mask of PENDCH4 field.
	DMAC_PENDCH_PENDCH4      = 0x10       // Bit PENDCH4.
	DMAC_PENDCH_PENDCH5_Pos  = 0x5        // Position of PENDCH5 field.
	DMAC_PENDCH_PENDCH5_Msk  = 0x20       // Bit mask of PENDCH5 field.
	DMAC_PENDCH_PENDCH5      = 0x20       // Bit PENDCH5.
	DMAC_PENDCH_PENDCH6_Pos  = 0x6        // Position of PENDCH6 field.
	DMAC_PENDCH_PENDCH6_Msk  = 0x40       // Bit mask of PENDCH6 field.
	DMAC_PENDCH_PENDCH6      = 0x40       // Bit PENDCH6.
	DMAC_PENDCH_PENDCH7_Pos  = 0x7        // Position of PENDCH7 field.
	DMAC_PENDCH_PENDCH7_Msk  = 0x80       // Bit mask of PENDCH7 field.
	DMAC_PENDCH_PENDCH7      = 0x80       // Bit PENDCH7.
	DMAC_PENDCH_PENDCH8_Pos  = 0x8        // Position of PENDCH8 field.
	DMAC_PENDCH_PENDCH8_Msk  = 0x100      // Bit mask of PENDCH8 field.
	DMAC_PENDCH_PENDCH8      = 0x100      // Bit PENDCH8.
	DMAC_PENDCH_PENDCH9_Pos  = 0x9        // Position of PENDCH9 field.
	DMAC_PENDCH_PENDCH9_Msk  = 0x200      // Bit mask of PENDCH9 field.
	DMAC_PENDCH_PENDCH9      = 0x200      // Bit PENDCH9.
	DMAC_PENDCH_PENDCH10_Pos = 0xa        // Position of PENDCH10 field.
	DMAC_PENDCH_PENDCH10_Msk = 0x400      // Bit mask of PENDCH10 field.
	DMAC_PENDCH_PENDCH10     = 0x400      // Bit PENDCH10.
	DMAC_PENDCH_PENDCH11_Pos = 0xb        // Position of PENDCH11 field.
	DMAC_PENDCH_PENDCH11_Msk = 0x800      // Bit mask of PENDCH11 field.
	DMAC_PENDCH_PENDCH11     = 0x800      // Bit PENDCH11.
	DMAC_PENDCH_PENDCH12_Pos = 0xc        // Position of PENDCH12 field.
	DMAC_PENDCH_PENDCH12_Msk = 0x1000     // Bit mask of PENDCH12 field.
	DMAC_PENDCH_PENDCH12     = 0x1000     // Bit PENDCH12.
	DMAC_PENDCH_PENDCH13_Pos = 0xd        // Position of PENDCH13 field.
	DMAC_PENDCH_PENDCH13_Msk = 0x2000     // Bit mask of PENDCH13 field.
	DMAC_PENDCH_PENDCH13     = 0x2000     // Bit PENDCH13.
	DMAC_PENDCH_PENDCH14_Pos = 0xe        // Position of PENDCH14 field.
	DMAC_PENDCH_PENDCH14_Msk = 0x4000     // Bit mask of PENDCH14 field.
	DMAC_PENDCH_PENDCH14     = 0x4000     // Bit PENDCH14.
	DMAC_PENDCH_PENDCH15_Pos = 0xf        // Position of PENDCH15 field.
	DMAC_PENDCH_PENDCH15_Msk = 0x8000     // Bit mask of PENDCH15 field.
	DMAC_PENDCH_PENDCH15     = 0x8000     // Bit PENDCH15.
	DMAC_PENDCH_PENDCH16_Pos = 0x10       // Position of PENDCH16 field.
	DMAC_PENDCH_PENDCH16_Msk = 0x10000    // Bit mask of PENDCH16 field.
	DMAC_PENDCH_PENDCH16     = 0x10000    // Bit PENDCH16.
	DMAC_PENDCH_PENDCH17_Pos = 0x11       // Position of PENDCH17 field.
	DMAC_PENDCH_PENDCH17_Msk = 0x20000    // Bit mask of PENDCH17 field.
	DMAC_PENDCH_PENDCH17     = 0x20000    // Bit PENDCH17.
	DMAC_PENDCH_PENDCH18_Pos = 0x12       // Position of PENDCH18 field.
	DMAC_PENDCH_PENDCH18_Msk = 0x40000    // Bit mask of PENDCH18 field.
	DMAC_PENDCH_PENDCH18     = 0x40000    // Bit PENDCH18.
	DMAC_PENDCH_PENDCH19_Pos = 0x13       // Position of PENDCH19 field.
	DMAC_PENDCH_PENDCH19_Msk = 0x80000    // Bit mask of PENDCH19 field.
	DMAC_PENDCH_PENDCH19     = 0x80000    // Bit PENDCH19.
	DMAC_PENDCH_PENDCH20_Pos = 0x14       // Position of PENDCH20 field.
	DMAC_PENDCH_PENDCH20_Msk = 0x100000   // Bit mask of PENDCH20 field.
	DMAC_PENDCH_PENDCH20     = 0x100000   // Bit PENDCH20.
	DMAC_PENDCH_PENDCH21_Pos = 0x15       // Position of PENDCH21 field.
	DMAC_PENDCH_PENDCH21_Msk = 0x200000   // Bit mask of PENDCH21 field.
	DMAC_PENDCH_PENDCH21     = 0x200000   // Bit PENDCH21.
	DMAC_PENDCH_PENDCH22_Pos = 0x16       // Position of PENDCH22 field.
	DMAC_PENDCH_PENDCH22_Msk = 0x400000   // Bit mask of PENDCH22 field.
	DMAC_PENDCH_PENDCH22     = 0x400000   // Bit PENDCH22.
	DMAC_PENDCH_PENDCH23_Pos = 0x17       // Position of PENDCH23 field.
	DMAC_PENDCH_PENDCH23_Msk = 0x800000   // Bit mask of PENDCH23 field.
	DMAC_PENDCH_PENDCH23     = 0x800000   // Bit PENDCH23.
	DMAC_PENDCH_PENDCH24_Pos = 0x18       // Position of PENDCH24 field.
	DMAC_PENDCH_PENDCH24_Msk = 0x1000000  // Bit mask of PENDCH24 field.
	DMAC_PENDCH_PENDCH24     = 0x1000000  // Bit PENDCH24.
	DMAC_PENDCH_PENDCH25_Pos = 0x19       // Position of PENDCH25 field.
	DMAC_PENDCH_PENDCH25_Msk = 0x2000000  // Bit mask of PENDCH25 field.
	DMAC_PENDCH_PENDCH25     = 0x2000000  // Bit PENDCH25.
	DMAC_PENDCH_PENDCH26_Pos = 0x1a       // Position of PENDCH26 field.
	DMAC_PENDCH_PENDCH26_Msk = 0x4000000  // Bit mask of PENDCH26 field.
	DMAC_PENDCH_PENDCH26     = 0x4000000  // Bit PENDCH26.
	DMAC_PENDCH_PENDCH27_Pos = 0x1b       // Position of PENDCH27 field.
	DMAC_PENDCH_PENDCH27_Msk = 0x8000000  // Bit mask of PENDCH27 field.
	DMAC_PENDCH_PENDCH27     = 0x8000000  // Bit PENDCH27.
	DMAC_PENDCH_PENDCH28_Pos = 0x1c       // Position of PENDCH28 field.
	DMAC_PENDCH_PENDCH28_Msk = 0x10000000 // Bit mask of PENDCH28 field.
	DMAC_PENDCH_PENDCH28     = 0x10000000 // Bit PENDCH28.
	DMAC_PENDCH_PENDCH29_Pos = 0x1d       // Position of PENDCH29 field.
	DMAC_PENDCH_PENDCH29_Msk = 0x20000000 // Bit mask of PENDCH29 field.
	DMAC_PENDCH_PENDCH29     = 0x20000000 // Bit PENDCH29.
	DMAC_PENDCH_PENDCH30_Pos = 0x1e       // Position of PENDCH30 field.
	DMAC_PENDCH_PENDCH30_Msk = 0x40000000 // Bit mask of PENDCH30 field.
	DMAC_PENDCH_PENDCH30     = 0x40000000 // Bit PENDCH30.
	DMAC_PENDCH_PENDCH31_Pos = 0x1f       // Position of PENDCH31 field.
	DMAC_PENDCH_PENDCH31_Msk = 0x80000000 // Bit mask of PENDCH31 field.
	DMAC_PENDCH_PENDCH31     = 0x80000000 // Bit PENDCH31.

	// ACTIVE: Active Channel and Levels
	DMAC_ACTIVE_LVLEX0_Pos = 0x0        // Position of LVLEX0 field.
	DMAC_ACTIVE_LVLEX0_Msk = 0x1        // Bit mask of LVLEX0 field.
	DMAC_ACTIVE_LVLEX0     = 0x1        // Bit LVLEX0.
	DMAC_ACTIVE_LVLEX1_Pos = 0x1        // Position of LVLEX1 field.
	DMAC_ACTIVE_LVLEX1_Msk = 0x2        // Bit mask of LVLEX1 field.
	DMAC_ACTIVE_LVLEX1     = 0x2        // Bit LVLEX1.
	DMAC_ACTIVE_LVLEX2_Pos = 0x2        // Position of LVLEX2 field.
	DMAC_ACTIVE_LVLEX2_Msk = 0x4        // Bit mask of LVLEX2 field.
	DMAC_ACTIVE_LVLEX2     = 0x4        // Bit LVLEX2.
	DMAC_ACTIVE_LVLEX3_Pos = 0x3        // Position of LVLEX3 field.
	DMAC_ACTIVE_LVLEX3_Msk = 0x8        // Bit mask of LVLEX3 field.
	DMAC_ACTIVE_LVLEX3     = 0x8        // Bit LVLEX3.
	DMAC_ACTIVE_ID_Pos     = 0x8        // Position of ID field.
	DMAC_ACTIVE_ID_Msk     = 0x1f00     // Bit mask of ID field.
	DMAC_ACTIVE_ABUSY_Pos  = 0xf        // Position of ABUSY field.
	DMAC_ACTIVE_ABUSY_Msk  = 0x8000     // Bit mask of ABUSY field.
	DMAC_ACTIVE_ABUSY      = 0x8000     // Bit ABUSY.
	DMAC_ACTIVE_BTCNT_Pos  = 0x10       // Position of BTCNT field.
	DMAC_ACTIVE_BTCNT_Msk  = 0xffff0000 // Bit mask of BTCNT field.

	// BASEADDR: Descriptor Memory Section Base Address
	DMAC_BASEADDR_BASEADDR_Pos = 0x0        // Position of BASEADDR field.
	DMAC_BASEADDR_BASEADDR_Msk = 0xffffffff // Bit mask of BASEADDR field.

	// WRBADDR: Write-Back Memory Section Base Address
	DMAC_WRBADDR_WRBADDR_Pos = 0x0        // Position of WRBADDR field.
	DMAC_WRBADDR_WRBADDR_Msk = 0xffffffff // Bit mask of WRBADDR field.

	// CHANNEL.CHCTRLA: Channel n Control A
	DMAC_CHANNEL_CHCTRLA_SWRST_Pos           = 0x0        // Position of SWRST field.
	DMAC_CHANNEL_CHCTRLA_SWRST_Msk           = 0x1        // Bit mask of SWRST field.
	DMAC_CHANNEL_CHCTRLA_SWRST               = 0x1        // Bit SWRST.
	DMAC_CHANNEL_CHCTRLA_ENABLE_Pos          = 0x1        // Position of ENABLE field.
	DMAC_CHANNEL_CHCTRLA_ENABLE_Msk          = 0x2        // Bit mask of ENABLE field.
	DMAC_CHANNEL_CHCTRLA_ENABLE              = 0x2        // Bit ENABLE.
	DMAC_CHANNEL_CHCTRLA_RUNSTDBY_Pos        = 0x6        // Position of RUNSTDBY field.
	DMAC_CHANNEL_CHCTRLA_RUNSTDBY_Msk        = 0x40       // Bit mask of RUNSTDBY field.
	DMAC_CHANNEL_CHCTRLA_RUNSTDBY            = 0x40       // Bit RUNSTDBY.
	DMAC_CHANNEL_CHCTRLA_TRIGSRC_Pos         = 0x8        // Position of TRIGSRC field.
	DMAC_CHANNEL_CHCTRLA_TRIGSRC_Msk         = 0x7f00     // Bit mask of TRIGSRC field.
	DMAC_CHANNEL_CHCTRLA_TRIGSRC_DISABLE     = 0x0        // Only software/event triggers
	DMAC_CHANNEL_CHCTRLA_TRIGACT_Pos         = 0x14       // Position of TRIGACT field.
	DMAC_CHANNEL_CHCTRLA_TRIGACT_Msk         = 0x300000   // Bit mask of TRIGACT field.
	DMAC_CHANNEL_CHCTRLA_TRIGACT_BLOCK       = 0x0        // One trigger required for each block transfer
	DMAC_CHANNEL_CHCTRLA_TRIGACT_BURST       = 0x2        // One trigger required for each burst transfer
	DMAC_CHANNEL_CHCTRLA_TRIGACT_TRANSACTION = 0x3        // One trigger required for each transaction
	DMAC_CHANNEL_CHCTRLA_BURSTLEN_Pos        = 0x18       // Position of BURSTLEN field.
	DMAC_CHANNEL_CHCTRLA_BURSTLEN_Msk        = 0xf000000  // Bit mask of BURSTLEN field.
	DMAC_CHANNEL_CHCTRLA_BURSTLEN_SINGLE     = 0x0        // Single-beat burst length
	DMAC_CHANNEL_CHCTRLA_BURSTLEN_2BEAT      = 0x1        // 2-beats burst length
	DMAC_CHANNEL_CHCTRLA_BURSTLEN_3BEAT      = 0x2        // 3-beats burst length
	DMAC_CHANNEL_CHCTRLA_BURSTLEN_4BEAT      = 0x3        // 4-beats burst length
	DMAC_CHANNEL_CHCTRLA_BURSTLEN_5BEAT      = 0x4        // 5-beats burst length
	DMAC_CHANNEL_CHCTRLA_BURSTLEN_6BEAT      = 0x5        // 6-beats burst length
	DMAC_CHANNEL_CHCTRLA_BURSTLEN_7BEAT      = 0x6        // 7-beats burst length
	DMAC_CHANNEL_CHCTRLA_BURSTLEN_8BEAT      = 0x7        // 8-beats burst length
	DMAC_CHANNEL_CHCTRLA_BURSTLEN_9BEAT      = 0x8        // 9-beats burst length
	DMAC_CHANNEL_CHCTRLA_BURSTLEN_10BEAT     = 0x9        // 10-beats burst length
	DMAC_CHANNEL_CHCTRLA_BURSTLEN_11BEAT     = 0xa        // 11-beats burst length
	DMAC_CHANNEL_CHCTRLA_BURSTLEN_12BEAT     = 0xb        // 12-beats burst length
	DMAC_CHANNEL_CHCTRLA_BURSTLEN_13BEAT     = 0xc        // 13-beats burst length
	DMAC_CHANNEL_CHCTRLA_BURSTLEN_14BEAT     = 0xd        // 14-beats burst length
	DMAC_CHANNEL_CHCTRLA_BURSTLEN_15BEAT     = 0xe        // 15-beats burst length
	DMAC_CHANNEL_CHCTRLA_BURSTLEN_16BEAT     = 0xf        // 16-beats burst length
	DMAC_CHANNEL_CHCTRLA_THRESHOLD_Pos       = 0x1c       // Position of THRESHOLD field.
	DMAC_CHANNEL_CHCTRLA_THRESHOLD_Msk       = 0x30000000 // Bit mask of THRESHOLD field.
	DMAC_CHANNEL_CHCTRLA_THRESHOLD_1BEAT     = 0x0        // Destination write starts after each beat source address read
	DMAC_CHANNEL_CHCTRLA_THRESHOLD_2BEATS    = 0x1        // Destination write starts after 2-beats source address read
	DMAC_CHANNEL_CHCTRLA_THRESHOLD_4BEATS    = 0x2        // Destination write starts after 4-beats source address read
	DMAC_CHANNEL_CHCTRLA_THRESHOLD_8BEATS    = 0x3        // Destination write starts after 8-beats source address read

	// CHANNEL.CHCTRLB: Channel n Control B
	DMAC_CHANNEL_CHCTRLB_CMD_Pos     = 0x0 // Position of CMD field.
	DMAC_CHANNEL_CHCTRLB_CMD_Msk     = 0x3 // Bit mask of CMD field.
	DMAC_CHANNEL_CHCTRLB_CMD_NOACT   = 0x0 // No action
	DMAC_CHANNEL_CHCTRLB_CMD_SUSPEND = 0x1 // Channel suspend operation
	DMAC_CHANNEL_CHCTRLB_CMD_RESUME  = 0x2 // Channel resume operation

	// CHANNEL.CHPRILVL: Channel n Priority Level
	DMAC_CHANNEL_CHPRILVL_PRILVL_Pos  = 0x0 // Position of PRILVL field.
	DMAC_CHANNEL_CHPRILVL_PRILVL_Msk  = 0x3 // Bit mask of PRILVL field.
	DMAC_CHANNEL_CHPRILVL_PRILVL_LVL0 = 0x0 // Channel Priority Level 0 (Lowest Level)
	DMAC_CHANNEL_CHPRILVL_PRILVL_LVL1 = 0x1 // Channel Priority Level 1
	DMAC_CHANNEL_CHPRILVL_PRILVL_LVL2 = 0x2 // Channel Priority Level 2
	DMAC_CHANNEL_CHPRILVL_PRILVL_LVL3 = 0x3 // Channel Priority Level 3 (Highest Level)

	// CHANNEL.CHEVCTRL: Channel n Event Control
	DMAC_CHANNEL_CHEVCTRL_EVACT_Pos       = 0x0  // Position of EVACT field.
	DMAC_CHANNEL_CHEVCTRL_EVACT_Msk       = 0x7  // Bit mask of EVACT field.
	DMAC_CHANNEL_CHEVCTRL_EVACT_NOACT     = 0x0  // No action
	DMAC_CHANNEL_CHEVCTRL_EVACT_TRIG      = 0x1  // Transfer and periodic transfer trigger
	DMAC_CHANNEL_CHEVCTRL_EVACT_CTRIG     = 0x2  // Conditional transfer trigger
	DMAC_CHANNEL_CHEVCTRL_EVACT_CBLOCK    = 0x3  // Conditional block transfer
	DMAC_CHANNEL_CHEVCTRL_EVACT_SUSPEND   = 0x4  // Channel suspend operation
	DMAC_CHANNEL_CHEVCTRL_EVACT_RESUME    = 0x5  // Channel resume operation
	DMAC_CHANNEL_CHEVCTRL_EVACT_SSKIP     = 0x6  // Skip next block suspend action
	DMAC_CHANNEL_CHEVCTRL_EVACT_INCPRI    = 0x7  // Increase priority
	DMAC_CHANNEL_CHEVCTRL_EVOMODE_Pos     = 0x4  // Position of EVOMODE field.
	DMAC_CHANNEL_CHEVCTRL_EVOMODE_Msk     = 0x30 // Bit mask of EVOMODE field.
	DMAC_CHANNEL_CHEVCTRL_EVOMODE_DEFAULT = 0x0  // Block event output selection. Refer to BTCTRL.EVOSEL for available selections.
	DMAC_CHANNEL_CHEVCTRL_EVOMODE_TRIGACT = 0x1  // Ongoing trigger action
	DMAC_CHANNEL_CHEVCTRL_EVIE_Pos        = 0x6  // Position of EVIE field.
	DMAC_CHANNEL_CHEVCTRL_EVIE_Msk        = 0x40 // Bit mask of EVIE field.
	DMAC_CHANNEL_CHEVCTRL_EVIE            = 0x40 // Bit EVIE.
	DMAC_CHANNEL_CHEVCTRL_EVOE_Pos        = 0x7  // Position of EVOE field.
	DMAC_CHANNEL_CHEVCTRL_EVOE_Msk        = 0x80 // Bit mask of EVOE field.
	DMAC_CHANNEL_CHEVCTRL_EVOE            = 0x80 // Bit EVOE.

	// CHANNEL.CHINTENCLR: Channel n Interrupt Enable Clear
	DMAC_CHANNEL_CHINTENCLR_TERR_Pos  = 0x0 // Position of TERR field.
	DMAC_CHANNEL_CHINTENCLR_TERR_Msk  = 0x1 // Bit mask of TERR field.
	DMAC_CHANNEL_CHINTENCLR_TERR      = 0x1 // Bit TERR.
	DMAC_CHANNEL_CHINTENCLR_TCMPL_Pos = 0x1 // Position of TCMPL field.
	DMAC_CHANNEL_CHINTENCLR_TCMPL_Msk = 0x2 // Bit mask of TCMPL field.
	DMAC_CHANNEL_CHINTENCLR_TCMPL     = 0x2 // Bit TCMPL.
	DMAC_CHANNEL_CHINTENCLR_SUSP_Pos  = 0x2 // Position of SUSP field.
	DMAC_CHANNEL_CHINTENCLR_SUSP_Msk  = 0x4 // Bit mask of SUSP field.
	DMAC_CHANNEL_CHINTENCLR_SUSP      = 0x4 // Bit SUSP.

	// CHANNEL.CHINTENSET: Channel n Interrupt Enable Set
	DMAC_CHANNEL_CHINTENSET_TERR_Pos  = 0x0 // Position of TERR field.
	DMAC_CHANNEL_CHINTENSET_TERR_Msk  = 0x1 // Bit mask of TERR field.
	DMAC_CHANNEL_CHINTENSET_TERR      = 0x1 // Bit TERR.
	DMAC_CHANNEL_CHINTENSET_TCMPL_Pos = 0x1 // Position of TCMPL field.
	DMAC_CHANNEL_CHINTENSET_TCMPL_Msk = 0x2 // Bit mask of TCMPL field.
	DMAC_CHANNEL_CHINTENSET_TCMPL     = 0x2 // Bit TCMPL.
	DMAC_CHANNEL_CHINTENSET_SUSP_Pos  = 0x2 // Position of SUSP field.
	DMAC_CHANNEL_CHINTENSET_SUSP_Msk  = 0x4 // Bit mask of SUSP field.
	DMAC_CHANNEL_CHINTENSET_SUSP      = 0x4 // Bit SUSP.

	// CHANNEL.CHINTFLAG: Channel n Interrupt Flag Status and Clear
	DMAC_CHANNEL_CHINTFLAG_TERR_Pos  = 0x0 // Position of TERR field.
	DMAC_CHANNEL_CHINTFLAG_TERR_Msk  = 0x1 // Bit mask of TERR field.
	DMAC_CHANNEL_CHINTFLAG_TERR      = 0x1 // Bit TERR.
	DMAC_CHANNEL_CHINTFLAG_TCMPL_Pos = 0x1 // Position of TCMPL field.
	DMAC_CHANNEL_CHINTFLAG_TCMPL_Msk = 0x2 // Bit mask of TCMPL field.
	DMAC_CHANNEL_CHINTFLAG_TCMPL     = 0x2 // Bit TCMPL.
	DMAC_CHANNEL_CHINTFLAG_SUSP_Pos  = 0x2 // Position of SUSP field.
	DMAC_CHANNEL_CHINTFLAG_SUSP_Msk  = 0x4 // Bit mask of SUSP field.
	DMAC_CHANNEL_CHINTFLAG_SUSP      = 0x4 // Bit SUSP.

	// CHANNEL.CHSTATUS: Channel n Status
	DMAC_CHANNEL_CHSTATUS_PEND_Pos   = 0x0 // Position of PEND field.
	DMAC_CHANNEL_CHSTATUS_PEND_Msk   = 0x1 // Bit mask of PEND field.
	DMAC_CHANNEL_CHSTATUS_PEND       = 0x1 // Bit PEND.
	DMAC_CHANNEL_CHSTATUS_BUSY_Pos   = 0x1 // Position of BUSY field.
	DMAC_CHANNEL_CHSTATUS_BUSY_Msk   = 0x2 // Bit mask of BUSY field.
	DMAC_CHANNEL_CHSTATUS_BUSY       = 0x2 // Bit BUSY.
	DMAC_CHANNEL_CHSTATUS_FERR_Pos   = 0x2 // Position of FERR field.
	DMAC_CHANNEL_CHSTATUS_FERR_Msk   = 0x4 // Bit mask of FERR field.
	DMAC_CHANNEL_CHSTATUS_FERR       = 0x4 // Bit FERR.
	DMAC_CHANNEL_CHSTATUS_CRCERR_Pos = 0x3 // Position of CRCERR field.
	DMAC_CHANNEL_CHSTATUS_CRCERR_Msk = 0x8 // Bit mask of CRCERR field.
	DMAC_CHANNEL_CHSTATUS_CRCERR     = 0x8 // Bit CRCERR.
)

// Bitfields for DSU: Device Service Unit
const (
	// CTRL: Control
	DSU_CTRL_SWRST_Pos = 0x0  // Position of SWRST field.
	DSU_CTRL_SWRST_Msk = 0x1  // Bit mask of SWRST field.
	DSU_CTRL_SWRST     = 0x1  // Bit SWRST.
	DSU_CTRL_CRC_Pos   = 0x2  // Position of CRC field.
	DSU_CTRL_CRC_Msk   = 0x4  // Bit mask of CRC field.
	DSU_CTRL_CRC       = 0x4  // Bit CRC.
	DSU_CTRL_MBIST_Pos = 0x3  // Position of MBIST field.
	DSU_CTRL_MBIST_Msk = 0x8  // Bit mask of MBIST field.
	DSU_CTRL_MBIST     = 0x8  // Bit MBIST.
	DSU_CTRL_CE_Pos    = 0x4  // Position of CE field.
	DSU_CTRL_CE_Msk    = 0x10 // Bit mask of CE field.
	DSU_CTRL_CE        = 0x10 // Bit CE.
	DSU_CTRL_ARR_Pos   = 0x6  // Position of ARR field.
	DSU_CTRL_ARR_Msk   = 0x40 // Bit mask of ARR field.
	DSU_CTRL_ARR       = 0x40 // Bit ARR.
	DSU_CTRL_SMSA_Pos  = 0x7  // Position of SMSA field.
	DSU_CTRL_SMSA_Msk  = 0x80 // Bit mask of SMSA field.
	DSU_CTRL_SMSA      = 0x80 // Bit SMSA.

	// STATUSA: Status A
	DSU_STATUSA_DONE_Pos    = 0x0  // Position of DONE field.
	DSU_STATUSA_DONE_Msk    = 0x1  // Bit mask of DONE field.
	DSU_STATUSA_DONE        = 0x1  // Bit DONE.
	DSU_STATUSA_CRSTEXT_Pos = 0x1  // Position of CRSTEXT field.
	DSU_STATUSA_CRSTEXT_Msk = 0x2  // Bit mask of CRSTEXT field.
	DSU_STATUSA_CRSTEXT     = 0x2  // Bit CRSTEXT.
	DSU_STATUSA_BERR_Pos    = 0x2  // Position of BERR field.
	DSU_STATUSA_BERR_Msk    = 0x4  // Bit mask of BERR field.
	DSU_STATUSA_BERR        = 0x4  // Bit BERR.
	DSU_STATUSA_FAIL_Pos    = 0x3  // Position of FAIL field.
	DSU_STATUSA_FAIL_Msk    = 0x8  // Bit mask of FAIL field.
	DSU_STATUSA_FAIL        = 0x8  // Bit FAIL.
	DSU_STATUSA_PERR_Pos    = 0x4  // Position of PERR field.
	DSU_STATUSA_PERR_Msk    = 0x10 // Bit mask of PERR field.
	DSU_STATUSA_PERR        = 0x10 // Bit PERR.

	// STATUSB: Status B
	DSU_STATUSB_PROT_Pos    = 0x0  // Position of PROT field.
	DSU_STATUSB_PROT_Msk    = 0x1  // Bit mask of PROT field.
	DSU_STATUSB_PROT        = 0x1  // Bit PROT.
	DSU_STATUSB_DBGPRES_Pos = 0x1  // Position of DBGPRES field.
	DSU_STATUSB_DBGPRES_Msk = 0x2  // Bit mask of DBGPRES field.
	DSU_STATUSB_DBGPRES     = 0x2  // Bit DBGPRES.
	DSU_STATUSB_DCCD0_Pos   = 0x2  // Position of DCCD0 field.
	DSU_STATUSB_DCCD0_Msk   = 0x4  // Bit mask of DCCD0 field.
	DSU_STATUSB_DCCD0       = 0x4  // Bit DCCD0.
	DSU_STATUSB_DCCD1_Pos   = 0x3  // Position of DCCD1 field.
	DSU_STATUSB_DCCD1_Msk   = 0x8  // Bit mask of DCCD1 field.
	DSU_STATUSB_DCCD1       = 0x8  // Bit DCCD1.
	DSU_STATUSB_HPE_Pos     = 0x4  // Position of HPE field.
	DSU_STATUSB_HPE_Msk     = 0x10 // Bit mask of HPE field.
	DSU_STATUSB_HPE         = 0x10 // Bit HPE.
	DSU_STATUSB_CELCK_Pos   = 0x5  // Position of CELCK field.
	DSU_STATUSB_CELCK_Msk   = 0x20 // Bit mask of CELCK field.
	DSU_STATUSB_CELCK       = 0x20 // Bit CELCK.
	DSU_STATUSB_TDCCD0_Pos  = 0x6  // Position of TDCCD0 field.
	DSU_STATUSB_TDCCD0_Msk  = 0x40 // Bit mask of TDCCD0 field.
	DSU_STATUSB_TDCCD0      = 0x40 // Bit TDCCD0.
	DSU_STATUSB_TDCCD1_Pos  = 0x7  // Position of TDCCD1 field.
	DSU_STATUSB_TDCCD1_Msk  = 0x80 // Bit mask of TDCCD1 field.
	DSU_STATUSB_TDCCD1      = 0x80 // Bit TDCCD1.

	// ADDR: Address
	DSU_ADDR_AMOD_Pos = 0x0        // Position of AMOD field.
	DSU_ADDR_AMOD_Msk = 0x3        // Bit mask of AMOD field.
	DSU_ADDR_ADDR_Pos = 0x2        // Position of ADDR field.
	DSU_ADDR_ADDR_Msk = 0xfffffffc // Bit mask of ADDR field.

	// LENGTH: Length
	DSU_LENGTH_LENGTH_Pos = 0x2        // Position of LENGTH field.
	DSU_LENGTH_LENGTH_Msk = 0xfffffffc // Bit mask of LENGTH field.

	// DATA: Data
	DSU_DATA_DATA_Pos = 0x0        // Position of DATA field.
	DSU_DATA_DATA_Msk = 0xffffffff // Bit mask of DATA field.

	// DCC: Debug Communication Channel n
	DSU_DCC_DATA_Pos = 0x0        // Position of DATA field.
	DSU_DCC_DATA_Msk = 0xffffffff // Bit mask of DATA field.

	// DID: Device Identification
	DSU_DID_DEVSEL_Pos     = 0x0        // Position of DEVSEL field.
	DSU_DID_DEVSEL_Msk     = 0xff       // Bit mask of DEVSEL field.
	DSU_DID_REVISION_Pos   = 0x8        // Position of REVISION field.
	DSU_DID_REVISION_Msk   = 0xf00      // Bit mask of REVISION field.
	DSU_DID_DIE_Pos        = 0xc        // Position of DIE field.
	DSU_DID_DIE_Msk        = 0xf000     // Bit mask of DIE field.
	DSU_DID_SERIES_Pos     = 0x10       // Position of SERIES field.
	DSU_DID_SERIES_Msk     = 0x3f0000   // Bit mask of SERIES field.
	DSU_DID_SERIES_0       = 0x0        // Cortex-M0+ processor, basic feature set
	DSU_DID_SERIES_1       = 0x1        // Cortex-M0+ processor, USB
	DSU_DID_FAMILY_Pos     = 0x17       // Position of FAMILY field.
	DSU_DID_FAMILY_Msk     = 0xf800000  // Bit mask of FAMILY field.
	DSU_DID_FAMILY_0       = 0x0        // General purpose microcontroller
	DSU_DID_FAMILY_1       = 0x1        // PicoPower
	DSU_DID_PROCESSOR_Pos  = 0x1c       // Position of PROCESSOR field.
	DSU_DID_PROCESSOR_Msk  = 0xf0000000 // Bit mask of PROCESSOR field.
	DSU_DID_PROCESSOR_CM0P = 0x1        // Cortex-M0+
	DSU_DID_PROCESSOR_CM23 = 0x2        // Cortex-M23
	DSU_DID_PROCESSOR_CM3  = 0x3        // Cortex-M3
	DSU_DID_PROCESSOR_CM4  = 0x5        // Cortex-M4
	DSU_DID_PROCESSOR_CM4F = 0x6        // Cortex-M4 with FPU
	DSU_DID_PROCESSOR_CM33 = 0x7        // Cortex-M33

	// CFG: Configuration
	DSU_CFG_LQOS_Pos          = 0x0  // Position of LQOS field.
	DSU_CFG_LQOS_Msk          = 0x3  // Bit mask of LQOS field.
	DSU_CFG_DCCDMALEVEL_Pos   = 0x2  // Position of DCCDMALEVEL field.
	DSU_CFG_DCCDMALEVEL_Msk   = 0xc  // Bit mask of DCCDMALEVEL field.
	DSU_CFG_DCCDMALEVEL_EMPTY = 0x0  // Trigger rises when DCC is empty
	DSU_CFG_DCCDMALEVEL_FULL  = 0x1  // Trigger rises when DCC is full
	DSU_CFG_ETBRAMEN_Pos      = 0x4  // Position of ETBRAMEN field.
	DSU_CFG_ETBRAMEN_Msk      = 0x10 // Bit mask of ETBRAMEN field.
	DSU_CFG_ETBRAMEN          = 0x10 // Bit ETBRAMEN.

	// DCFG: Device Configuration
	DSU_DCFG_DCFG_Pos = 0x0        // Position of DCFG field.
	DSU_DCFG_DCFG_Msk = 0xffffffff // Bit mask of DCFG field.

	// ENTRY0: CoreSight ROM Table Entry 0
	DSU_ENTRY0_EPRES_Pos  = 0x0        // Position of EPRES field.
	DSU_ENTRY0_EPRES_Msk  = 0x1        // Bit mask of EPRES field.
	DSU_ENTRY0_EPRES      = 0x1        // Bit EPRES.
	DSU_ENTRY0_FMT_Pos    = 0x1        // Position of FMT field.
	DSU_ENTRY0_FMT_Msk    = 0x2        // Bit mask of FMT field.
	DSU_ENTRY0_FMT        = 0x2        // Bit FMT.
	DSU_ENTRY0_ADDOFF_Pos = 0xc        // Position of ADDOFF field.
	DSU_ENTRY0_ADDOFF_Msk = 0xfffff000 // Bit mask of ADDOFF field.

	// END: CoreSight ROM Table End
	DSU_END_END_Pos = 0x0        // Position of END field.
	DSU_END_END_Msk = 0xffffffff // Bit mask of END field.

	// MEMTYPE: CoreSight ROM Table Memory Type
	DSU_MEMTYPE_SMEMP_Pos = 0x0 // Position of SMEMP field.
	DSU_MEMTYPE_SMEMP_Msk = 0x1 // Bit mask of SMEMP field.
	DSU_MEMTYPE_SMEMP     = 0x1 // Bit SMEMP.

	// PID4: Peripheral Identification 4
	DSU_PID4_JEPCC_Pos = 0x0  // Position of JEPCC field.
	DSU_PID4_JEPCC_Msk = 0xf  // Bit mask of JEPCC field.
	DSU_PID4_FKBC_Pos  = 0x4  // Position of FKBC field.
	DSU_PID4_FKBC_Msk  = 0xf0 // Bit mask of FKBC field.

	// PID0: Peripheral Identification 0
	DSU_PID0_PARTNBL_Pos = 0x0  // Position of PARTNBL field.
	DSU_PID0_PARTNBL_Msk = 0xff // Bit mask of PARTNBL field.

	// PID1: Peripheral Identification 1
	DSU_PID1_PARTNBH_Pos = 0x0  // Position of PARTNBH field.
	DSU_PID1_PARTNBH_Msk = 0xf  // Bit mask of PARTNBH field.
	DSU_PID1_JEPIDCL_Pos = 0x4  // Position of JEPIDCL field.
	DSU_PID1_JEPIDCL_Msk = 0xf0 // Bit mask of JEPIDCL field.

	// PID2: Peripheral Identification 2
	DSU_PID2_JEPIDCH_Pos  = 0x0  // Position of JEPIDCH field.
	DSU_PID2_JEPIDCH_Msk  = 0x7  // Bit mask of JEPIDCH field.
	DSU_PID2_JEPU_Pos     = 0x3  // Position of JEPU field.
	DSU_PID2_JEPU_Msk     = 0x8  // Bit mask of JEPU field.
	DSU_PID2_JEPU         = 0x8  // Bit JEPU.
	DSU_PID2_REVISION_Pos = 0x4  // Position of REVISION field.
	DSU_PID2_REVISION_Msk = 0xf0 // Bit mask of REVISION field.

	// PID3: Peripheral Identification 3
	DSU_PID3_CUSMOD_Pos = 0x0  // Position of CUSMOD field.
	DSU_PID3_CUSMOD_Msk = 0xf  // Bit mask of CUSMOD field.
	DSU_PID3_REVAND_Pos = 0x4  // Position of REVAND field.
	DSU_PID3_REVAND_Msk = 0xf0 // Bit mask of REVAND field.

	// CID0: Component Identification 0
	DSU_CID0_PREAMBLEB0_Pos = 0x0  // Position of PREAMBLEB0 field.
	DSU_CID0_PREAMBLEB0_Msk = 0xff // Bit mask of PREAMBLEB0 field.

	// CID1: Component Identification 1
	DSU_CID1_PREAMBLE_Pos = 0x0  // Position of PREAMBLE field.
	DSU_CID1_PREAMBLE_Msk = 0xf  // Bit mask of PREAMBLE field.
	DSU_CID1_CCLASS_Pos   = 0x4  // Position of CCLASS field.
	DSU_CID1_CCLASS_Msk   = 0xf0 // Bit mask of CCLASS field.

	// CID2: Component Identification 2
	DSU_CID2_PREAMBLEB2_Pos = 0x0  // Position of PREAMBLEB2 field.
	DSU_CID2_PREAMBLEB2_Msk = 0xff // Bit mask of PREAMBLEB2 field.

	// CID3: Component Identification 3
	DSU_CID3_PREAMBLEB3_Pos = 0x0  // Position of PREAMBLEB3 field.
	DSU_CID3_PREAMBLEB3_Msk = 0xff // Bit mask of PREAMBLEB3 field.
)

// Bitfields for EIC: External Interrupt Controller
const (
	// CTRLA: Control A
	EIC_CTRLA_SWRST_Pos        = 0x0  // Position of SWRST field.
	EIC_CTRLA_SWRST_Msk        = 0x1  // Bit mask of SWRST field.
	EIC_CTRLA_SWRST            = 0x1  // Bit SWRST.
	EIC_CTRLA_ENABLE_Pos       = 0x1  // Position of ENABLE field.
	EIC_CTRLA_ENABLE_Msk       = 0x2  // Bit mask of ENABLE field.
	EIC_CTRLA_ENABLE           = 0x2  // Bit ENABLE.
	EIC_CTRLA_CKSEL_Pos        = 0x4  // Position of CKSEL field.
	EIC_CTRLA_CKSEL_Msk        = 0x10 // Bit mask of CKSEL field.
	EIC_CTRLA_CKSEL            = 0x10 // Bit CKSEL.
	EIC_CTRLA_CKSEL_CLK_GCLK   = 0x0  // Clocked by GCLK
	EIC_CTRLA_CKSEL_CLK_ULP32K = 0x1  // Clocked by ULP32K

	// NMICTRL: Non-Maskable Interrupt Control
	EIC_NMICTRL_NMISENSE_Pos    = 0x0  // Position of NMISENSE field.
	EIC_NMICTRL_NMISENSE_Msk    = 0x7  // Bit mask of NMISENSE field.
	EIC_NMICTRL_NMISENSE_NONE   = 0x0  // No detection
	EIC_NMICTRL_NMISENSE_RISE   = 0x1  // Rising-edge detection
	EIC_NMICTRL_NMISENSE_FALL   = 0x2  // Falling-edge detection
	EIC_NMICTRL_NMISENSE_BOTH   = 0x3  // Both-edges detection
	EIC_NMICTRL_NMISENSE_HIGH   = 0x4  // High-level detection
	EIC_NMICTRL_NMISENSE_LOW    = 0x5  // Low-level detection
	EIC_NMICTRL_NMIFILTEN_Pos   = 0x3  // Position of NMIFILTEN field.
	EIC_NMICTRL_NMIFILTEN_Msk   = 0x8  // Bit mask of NMIFILTEN field.
	EIC_NMICTRL_NMIFILTEN       = 0x8  // Bit NMIFILTEN.
	EIC_NMICTRL_NMIASYNCH_Pos   = 0x4  // Position of NMIASYNCH field.
	EIC_NMICTRL_NMIASYNCH_Msk   = 0x10 // Bit mask of NMIASYNCH field.
	EIC_NMICTRL_NMIASYNCH       = 0x10 // Bit NMIASYNCH.
	EIC_NMICTRL_NMIASYNCH_SYNC  = 0x0  // Edge detection is clock synchronously operated
	EIC_NMICTRL_NMIASYNCH_ASYNC = 0x1  // Edge detection is clock asynchronously operated

	// NMIFLAG: Non-Maskable Interrupt Flag Status and Clear
	EIC_NMIFLAG_NMI_Pos = 0x0 // Position of NMI field.
	EIC_NMIFLAG_NMI_Msk = 0x1 // Bit mask of NMI field.
	EIC_NMIFLAG_NMI     = 0x1 // Bit NMI.

	// SYNCBUSY: Synchronization Busy
	EIC_SYNCBUSY_SWRST_Pos  = 0x0 // Position of SWRST field.
	EIC_SYNCBUSY_SWRST_Msk  = 0x1 // Bit mask of SWRST field.
	EIC_SYNCBUSY_SWRST      = 0x1 // Bit SWRST.
	EIC_SYNCBUSY_ENABLE_Pos = 0x1 // Position of ENABLE field.
	EIC_SYNCBUSY_ENABLE_Msk = 0x2 // Bit mask of ENABLE field.
	EIC_SYNCBUSY_ENABLE     = 0x2 // Bit ENABLE.

	// EVCTRL: Event Control
	EIC_EVCTRL_EXTINTEO_Pos = 0x0    // Position of EXTINTEO field.
	EIC_EVCTRL_EXTINTEO_Msk = 0xffff // Bit mask of EXTINTEO field.

	// INTENCLR: Interrupt Enable Clear
	EIC_INTENCLR_EXTINT_Pos = 0x0    // Position of EXTINT field.
	EIC_INTENCLR_EXTINT_Msk = 0xffff // Bit mask of EXTINT field.

	// INTENSET: Interrupt Enable Set
	EIC_INTENSET_EXTINT_Pos = 0x0    // Position of EXTINT field.
	EIC_INTENSET_EXTINT_Msk = 0xffff // Bit mask of EXTINT field.

	// INTFLAG: Interrupt Flag Status and Clear
	EIC_INTFLAG_EXTINT_Pos = 0x0    // Position of EXTINT field.
	EIC_INTFLAG_EXTINT_Msk = 0xffff // Bit mask of EXTINT field.

	// ASYNCH: External Interrupt Asynchronous Mode
	EIC_ASYNCH_ASYNCH_Pos   = 0x0    // Position of ASYNCH field.
	EIC_ASYNCH_ASYNCH_Msk   = 0xffff // Bit mask of ASYNCH field.
	EIC_ASYNCH_ASYNCH_SYNC  = 0x0    // Edge detection is clock synchronously operated
	EIC_ASYNCH_ASYNCH_ASYNC = 0x1    // Edge detection is clock asynchronously operated

	// CONFIG: External Interrupt Sense Configuration
	EIC_CONFIG_SENSE0_Pos  = 0x0        // Position of SENSE0 field.
	EIC_CONFIG_SENSE0_Msk  = 0x7        // Bit mask of SENSE0 field.
	EIC_CONFIG_SENSE0_NONE = 0x0        // No detection
	EIC_CONFIG_SENSE0_RISE = 0x1        // Rising edge detection
	EIC_CONFIG_SENSE0_FALL = 0x2        // Falling edge detection
	EIC_CONFIG_SENSE0_BOTH = 0x3        // Both edges detection
	EIC_CONFIG_SENSE0_HIGH = 0x4        // High level detection
	EIC_CONFIG_SENSE0_LOW  = 0x5        // Low level detection
	EIC_CONFIG_FILTEN0_Pos = 0x3        // Position of FILTEN0 field.
	EIC_CONFIG_FILTEN0_Msk = 0x8        // Bit mask of FILTEN0 field.
	EIC_CONFIG_FILTEN0     = 0x8        // Bit FILTEN0.
	EIC_CONFIG_SENSE1_Pos  = 0x4        // Position of SENSE1 field.
	EIC_CONFIG_SENSE1_Msk  = 0x70       // Bit mask of SENSE1 field.
	EIC_CONFIG_SENSE1_NONE = 0x0        // No detection
	EIC_CONFIG_SENSE1_RISE = 0x1        // Rising edge detection
	EIC_CONFIG_SENSE1_FALL = 0x2        // Falling edge detection
	EIC_CONFIG_SENSE1_BOTH = 0x3        // Both edges detection
	EIC_CONFIG_SENSE1_HIGH = 0x4        // High level detection
	EIC_CONFIG_SENSE1_LOW  = 0x5        // Low level detection
	EIC_CONFIG_FILTEN1_Pos = 0x7        // Position of FILTEN1 field.
	EIC_CONFIG_FILTEN1_Msk = 0x80       // Bit mask of FILTEN1 field.
	EIC_CONFIG_FILTEN1     = 0x80       // Bit FILTEN1.
	EIC_CONFIG_SENSE2_Pos  = 0x8        // Position of SENSE2 field.
	EIC_CONFIG_SENSE2_Msk  = 0x700      // Bit mask of SENSE2 field.
	EIC_CONFIG_SENSE2_NONE = 0x0        // No detection
	EIC_CONFIG_SENSE2_RISE = 0x1        // Rising edge detection
	EIC_CONFIG_SENSE2_FALL = 0x2        // Falling edge detection
	EIC_CONFIG_SENSE2_BOTH = 0x3        // Both edges detection
	EIC_CONFIG_SENSE2_HIGH = 0x4        // High level detection
	EIC_CONFIG_SENSE2_LOW  = 0x5        // Low level detection
	EIC_CONFIG_FILTEN2_Pos = 0xb        // Position of FILTEN2 field.
	EIC_CONFIG_FILTEN2_Msk = 0x800      // Bit mask of FILTEN2 field.
	EIC_CONFIG_FILTEN2     = 0x800      // Bit FILTEN2.
	EIC_CONFIG_SENSE3_Pos  = 0xc        // Position of SENSE3 field.
	EIC_CONFIG_SENSE3_Msk  = 0x7000     // Bit mask of SENSE3 field.
	EIC_CONFIG_SENSE3_NONE = 0x0        // No detection
	EIC_CONFIG_SENSE3_RISE = 0x1        // Rising edge detection
	EIC_CONFIG_SENSE3_FALL = 0x2        // Falling edge detection
	EIC_CONFIG_SENSE3_BOTH = 0x3        // Both edges detection
	EIC_CONFIG_SENSE3_HIGH = 0x4        // High level detection
	EIC_CONFIG_SENSE3_LOW  = 0x5        // Low level detection
	EIC_CONFIG_FILTEN3_Pos = 0xf        // Position of FILTEN3 field.
	EIC_CONFIG_FILTEN3_Msk = 0x8000     // Bit mask of FILTEN3 field.
	EIC_CONFIG_FILTEN3     = 0x8000     // Bit FILTEN3.
	EIC_CONFIG_SENSE4_Pos  = 0x10       // Position of SENSE4 field.
	EIC_CONFIG_SENSE4_Msk  = 0x70000    // Bit mask of SENSE4 field.
	EIC_CONFIG_SENSE4_NONE = 0x0        // No detection
	EIC_CONFIG_SENSE4_RISE = 0x1        // Rising edge detection
	EIC_CONFIG_SENSE4_FALL = 0x2        // Falling edge detection
	EIC_CONFIG_SENSE4_BOTH = 0x3        // Both edges detection
	EIC_CONFIG_SENSE4_HIGH = 0x4        // High level detection
	EIC_CONFIG_SENSE4_LOW  = 0x5        // Low level detection
	EIC_CONFIG_FILTEN4_Pos = 0x13       // Position of FILTEN4 field.
	EIC_CONFIG_FILTEN4_Msk = 0x80000    // Bit mask of FILTEN4 field.
	EIC_CONFIG_FILTEN4     = 0x80000    // Bit FILTEN4.
	EIC_CONFIG_SENSE5_Pos  = 0x14       // Position of SENSE5 field.
	EIC_CONFIG_SENSE5_Msk  = 0x700000   // Bit mask of SENSE5 field.
	EIC_CONFIG_SENSE5_NONE = 0x0        // No detection
	EIC_CONFIG_SENSE5_RISE = 0x1        // Rising edge detection
	EIC_CONFIG_SENSE5_FALL = 0x2        // Falling edge detection
	EIC_CONFIG_SENSE5_BOTH = 0x3        // Both edges detection
	EIC_CONFIG_SENSE5_HIGH = 0x4        // High level detection
	EIC_CONFIG_SENSE5_LOW  = 0x5        // Low level detection
	EIC_CONFIG_FILTEN5_Pos = 0x17       // Position of FILTEN5 field.
	EIC_CONFIG_FILTEN5_Msk = 0x800000   // Bit mask of FILTEN5 field.
	EIC_CONFIG_FILTEN5     = 0x800000   // Bit FILTEN5.
	EIC_CONFIG_SENSE6_Pos  = 0x18       // Position of SENSE6 field.
	EIC_CONFIG_SENSE6_Msk  = 0x7000000  // Bit mask of SENSE6 field.
	EIC_CONFIG_SENSE6_NONE = 0x0        // No detection
	EIC_CONFIG_SENSE6_RISE = 0x1        // Rising edge detection
	EIC_CONFIG_SENSE6_FALL = 0x2        // Falling edge detection
	EIC_CONFIG_SENSE6_BOTH = 0x3        // Both edges detection
	EIC_CONFIG_SENSE6_HIGH = 0x4        // High level detection
	EIC_CONFIG_SENSE6_LOW  = 0x5        // Low level detection
	EIC_CONFIG_FILTEN6_Pos = 0x1b       // Position of FILTEN6 field.
	EIC_CONFIG_FILTEN6_Msk = 0x8000000  // Bit mask of FILTEN6 field.
	EIC_CONFIG_FILTEN6     = 0x8000000  // Bit FILTEN6.
	EIC_CONFIG_SENSE7_Pos  = 0x1c       // Position of SENSE7 field.
	EIC_CONFIG_SENSE7_Msk  = 0x70000000 // Bit mask of SENSE7 field.
	EIC_CONFIG_SENSE7_NONE = 0x0        // No detection
	EIC_CONFIG_SENSE7_RISE = 0x1        // Rising edge detection
	EIC_CONFIG_SENSE7_FALL = 0x2        // Falling edge detection
	EIC_CONFIG_SENSE7_BOTH = 0x3        // Both edges detection
	EIC_CONFIG_SENSE7_HIGH = 0x4        // High level detection
	EIC_CONFIG_SENSE7_LOW  = 0x5        // Low level detection
	EIC_CONFIG_FILTEN7_Pos = 0x1f       // Position of FILTEN7 field.
	EIC_CONFIG_FILTEN7_Msk = 0x80000000 // Bit mask of FILTEN7 field.
	EIC_CONFIG_FILTEN7     = 0x80000000 // Bit FILTEN7.

	// DEBOUNCEN: Debouncer Enable
	EIC_DEBOUNCEN_DEBOUNCEN_Pos = 0x0    // Position of DEBOUNCEN field.
	EIC_DEBOUNCEN_DEBOUNCEN_Msk = 0xffff // Bit mask of DEBOUNCEN field.

	// DPRESCALER: Debouncer Prescaler
	EIC_DPRESCALER_PRESCALER0_Pos      = 0x0     // Position of PRESCALER0 field.
	EIC_DPRESCALER_PRESCALER0_Msk      = 0x7     // Bit mask of PRESCALER0 field.
	EIC_DPRESCALER_PRESCALER0_DIV2     = 0x0     // EIC clock divided by 2
	EIC_DPRESCALER_PRESCALER0_DIV4     = 0x1     // EIC clock divided by 4
	EIC_DPRESCALER_PRESCALER0_DIV8     = 0x2     // EIC clock divided by 8
	EIC_DPRESCALER_PRESCALER0_DIV16    = 0x3     // EIC clock divided by 16
	EIC_DPRESCALER_PRESCALER0_DIV32    = 0x4     // EIC clock divided by 32
	EIC_DPRESCALER_PRESCALER0_DIV64    = 0x5     // EIC clock divided by 64
	EIC_DPRESCALER_PRESCALER0_DIV128   = 0x6     // EIC clock divided by 128
	EIC_DPRESCALER_PRESCALER0_DIV256   = 0x7     // EIC clock divided by 256
	EIC_DPRESCALER_STATES0_Pos         = 0x3     // Position of STATES0 field.
	EIC_DPRESCALER_STATES0_Msk         = 0x8     // Bit mask of STATES0 field.
	EIC_DPRESCALER_STATES0             = 0x8     // Bit STATES0.
	EIC_DPRESCALER_STATES0_LFREQ3      = 0x0     // 3 low frequency samples
	EIC_DPRESCALER_STATES0_LFREQ7      = 0x1     // 7 low frequency samples
	EIC_DPRESCALER_PRESCALER1_Pos      = 0x4     // Position of PRESCALER1 field.
	EIC_DPRESCALER_PRESCALER1_Msk      = 0x70    // Bit mask of PRESCALER1 field.
	EIC_DPRESCALER_PRESCALER1_DIV2     = 0x0     // EIC clock divided by 2
	EIC_DPRESCALER_PRESCALER1_DIV4     = 0x1     // EIC clock divided by 4
	EIC_DPRESCALER_PRESCALER1_DIV8     = 0x2     // EIC clock divided by 8
	EIC_DPRESCALER_PRESCALER1_DIV16    = 0x3     // EIC clock divided by 16
	EIC_DPRESCALER_PRESCALER1_DIV32    = 0x4     // EIC clock divided by 32
	EIC_DPRESCALER_PRESCALER1_DIV64    = 0x5     // EIC clock divided by 64
	EIC_DPRESCALER_PRESCALER1_DIV128   = 0x6     // EIC clock divided by 128
	EIC_DPRESCALER_PRESCALER1_DIV256   = 0x7     // EIC clock divided by 256
	EIC_DPRESCALER_STATES1_Pos         = 0x7     // Position of STATES1 field.
	EIC_DPRESCALER_STATES1_Msk         = 0x80    // Bit mask of STATES1 field.
	EIC_DPRESCALER_STATES1             = 0x80    // Bit STATES1.
	EIC_DPRESCALER_STATES1_LFREQ3      = 0x0     // 3 low frequency samples
	EIC_DPRESCALER_STATES1_LFREQ7      = 0x1     // 7 low frequency samples
	EIC_DPRESCALER_TICKON_Pos          = 0x10    // Position of TICKON field.
	EIC_DPRESCALER_TICKON_Msk          = 0x10000 // Bit mask of TICKON field.
	EIC_DPRESCALER_TICKON              = 0x10000 // Bit TICKON.
	EIC_DPRESCALER_TICKON_CLK_GCLK_EIC = 0x0     // Clocked by GCLK
	EIC_DPRESCALER_TICKON_CLK_LFREQ    = 0x1     // Clocked by Low Frequency Clock

	// PINSTATE: Pin State
	EIC_PINSTATE_PINSTATE_Pos = 0x0    // Position of PINSTATE field.
	EIC_PINSTATE_PINSTATE_Msk = 0xffff // Bit mask of PINSTATE field.
)

// Bitfields for EVSYS: Event System Interface
const (
	// CTRLA: Control
	EVSYS_CTRLA_SWRST_Pos = 0x0 // Position of SWRST field.
	EVSYS_CTRLA_SWRST_Msk = 0x1 // Bit mask of SWRST field.
	EVSYS_CTRLA_SWRST     = 0x1 // Bit SWRST.

	// SWEVT: Software Event
	EVSYS_SWEVT_CHANNEL0_Pos  = 0x0        // Position of CHANNEL0 field.
	EVSYS_SWEVT_CHANNEL0_Msk  = 0x1        // Bit mask of CHANNEL0 field.
	EVSYS_SWEVT_CHANNEL0      = 0x1        // Bit CHANNEL0.
	EVSYS_SWEVT_CHANNEL1_Pos  = 0x1        // Position of CHANNEL1 field.
	EVSYS_SWEVT_CHANNEL1_Msk  = 0x2        // Bit mask of CHANNEL1 field.
	EVSYS_SWEVT_CHANNEL1      = 0x2        // Bit CHANNEL1.
	EVSYS_SWEVT_CHANNEL2_Pos  = 0x2        // Position of CHANNEL2 field.
	EVSYS_SWEVT_CHANNEL2_Msk  = 0x4        // Bit mask of CHANNEL2 field.
	EVSYS_SWEVT_CHANNEL2      = 0x4        // Bit CHANNEL2.
	EVSYS_SWEVT_CHANNEL3_Pos  = 0x3        // Position of CHANNEL3 field.
	EVSYS_SWEVT_CHANNEL3_Msk  = 0x8        // Bit mask of CHANNEL3 field.
	EVSYS_SWEVT_CHANNEL3      = 0x8        // Bit CHANNEL3.
	EVSYS_SWEVT_CHANNEL4_Pos  = 0x4        // Position of CHANNEL4 field.
	EVSYS_SWEVT_CHANNEL4_Msk  = 0x10       // Bit mask of CHANNEL4 field.
	EVSYS_SWEVT_CHANNEL4      = 0x10       // Bit CHANNEL4.
	EVSYS_SWEVT_CHANNEL5_Pos  = 0x5        // Position of CHANNEL5 field.
	EVSYS_SWEVT_CHANNEL5_Msk  = 0x20       // Bit mask of CHANNEL5 field.
	EVSYS_SWEVT_CHANNEL5      = 0x20       // Bit CHANNEL5.
	EVSYS_SWEVT_CHANNEL6_Pos  = 0x6        // Position of CHANNEL6 field.
	EVSYS_SWEVT_CHANNEL6_Msk  = 0x40       // Bit mask of CHANNEL6 field.
	EVSYS_SWEVT_CHANNEL6      = 0x40       // Bit CHANNEL6.
	EVSYS_SWEVT_CHANNEL7_Pos  = 0x7        // Position of CHANNEL7 field.
	EVSYS_SWEVT_CHANNEL7_Msk  = 0x80       // Bit mask of CHANNEL7 field.
	EVSYS_SWEVT_CHANNEL7      = 0x80       // Bit CHANNEL7.
	EVSYS_SWEVT_CHANNEL8_Pos  = 0x8        // Position of CHANNEL8 field.
	EVSYS_SWEVT_CHANNEL8_Msk  = 0x100      // Bit mask of CHANNEL8 field.
	EVSYS_SWEVT_CHANNEL8      = 0x100      // Bit CHANNEL8.
	EVSYS_SWEVT_CHANNEL9_Pos  = 0x9        // Position of CHANNEL9 field.
	EVSYS_SWEVT_CHANNEL9_Msk  = 0x200      // Bit mask of CHANNEL9 field.
	EVSYS_SWEVT_CHANNEL9      = 0x200      // Bit CHANNEL9.
	EVSYS_SWEVT_CHANNEL10_Pos = 0xa        // Position of CHANNEL10 field.
	EVSYS_SWEVT_CHANNEL10_Msk = 0x400      // Bit mask of CHANNEL10 field.
	EVSYS_SWEVT_CHANNEL10     = 0x400      // Bit CHANNEL10.
	EVSYS_SWEVT_CHANNEL11_Pos = 0xb        // Position of CHANNEL11 field.
	EVSYS_SWEVT_CHANNEL11_Msk = 0x800      // Bit mask of CHANNEL11 field.
	EVSYS_SWEVT_CHANNEL11     = 0x800      // Bit CHANNEL11.
	EVSYS_SWEVT_CHANNEL12_Pos = 0xc        // Position of CHANNEL12 field.
	EVSYS_SWEVT_CHANNEL12_Msk = 0x1000     // Bit mask of CHANNEL12 field.
	EVSYS_SWEVT_CHANNEL12     = 0x1000     // Bit CHANNEL12.
	EVSYS_SWEVT_CHANNEL13_Pos = 0xd        // Position of CHANNEL13 field.
	EVSYS_SWEVT_CHANNEL13_Msk = 0x2000     // Bit mask of CHANNEL13 field.
	EVSYS_SWEVT_CHANNEL13     = 0x2000     // Bit CHANNEL13.
	EVSYS_SWEVT_CHANNEL14_Pos = 0xe        // Position of CHANNEL14 field.
	EVSYS_SWEVT_CHANNEL14_Msk = 0x4000     // Bit mask of CHANNEL14 field.
	EVSYS_SWEVT_CHANNEL14     = 0x4000     // Bit CHANNEL14.
	EVSYS_SWEVT_CHANNEL15_Pos = 0xf        // Position of CHANNEL15 field.
	EVSYS_SWEVT_CHANNEL15_Msk = 0x8000     // Bit mask of CHANNEL15 field.
	EVSYS_SWEVT_CHANNEL15     = 0x8000     // Bit CHANNEL15.
	EVSYS_SWEVT_CHANNEL16_Pos = 0x10       // Position of CHANNEL16 field.
	EVSYS_SWEVT_CHANNEL16_Msk = 0x10000    // Bit mask of CHANNEL16 field.
	EVSYS_SWEVT_CHANNEL16     = 0x10000    // Bit CHANNEL16.
	EVSYS_SWEVT_CHANNEL17_Pos = 0x11       // Position of CHANNEL17 field.
	EVSYS_SWEVT_CHANNEL17_Msk = 0x20000    // Bit mask of CHANNEL17 field.
	EVSYS_SWEVT_CHANNEL17     = 0x20000    // Bit CHANNEL17.
	EVSYS_SWEVT_CHANNEL18_Pos = 0x12       // Position of CHANNEL18 field.
	EVSYS_SWEVT_CHANNEL18_Msk = 0x40000    // Bit mask of CHANNEL18 field.
	EVSYS_SWEVT_CHANNEL18     = 0x40000    // Bit CHANNEL18.
	EVSYS_SWEVT_CHANNEL19_Pos = 0x13       // Position of CHANNEL19 field.
	EVSYS_SWEVT_CHANNEL19_Msk = 0x80000    // Bit mask of CHANNEL19 field.
	EVSYS_SWEVT_CHANNEL19     = 0x80000    // Bit CHANNEL19.
	EVSYS_SWEVT_CHANNEL20_Pos = 0x14       // Position of CHANNEL20 field.
	EVSYS_SWEVT_CHANNEL20_Msk = 0x100000   // Bit mask of CHANNEL20 field.
	EVSYS_SWEVT_CHANNEL20     = 0x100000   // Bit CHANNEL20.
	EVSYS_SWEVT_CHANNEL21_Pos = 0x15       // Position of CHANNEL21 field.
	EVSYS_SWEVT_CHANNEL21_Msk = 0x200000   // Bit mask of CHANNEL21 field.
	EVSYS_SWEVT_CHANNEL21     = 0x200000   // Bit CHANNEL21.
	EVSYS_SWEVT_CHANNEL22_Pos = 0x16       // Position of CHANNEL22 field.
	EVSYS_SWEVT_CHANNEL22_Msk = 0x400000   // Bit mask of CHANNEL22 field.
	EVSYS_SWEVT_CHANNEL22     = 0x400000   // Bit CHANNEL22.
	EVSYS_SWEVT_CHANNEL23_Pos = 0x17       // Position of CHANNEL23 field.
	EVSYS_SWEVT_CHANNEL23_Msk = 0x800000   // Bit mask of CHANNEL23 field.
	EVSYS_SWEVT_CHANNEL23     = 0x800000   // Bit CHANNEL23.
	EVSYS_SWEVT_CHANNEL24_Pos = 0x18       // Position of CHANNEL24 field.
	EVSYS_SWEVT_CHANNEL24_Msk = 0x1000000  // Bit mask of CHANNEL24 field.
	EVSYS_SWEVT_CHANNEL24     = 0x1000000  // Bit CHANNEL24.
	EVSYS_SWEVT_CHANNEL25_Pos = 0x19       // Position of CHANNEL25 field.
	EVSYS_SWEVT_CHANNEL25_Msk = 0x2000000  // Bit mask of CHANNEL25 field.
	EVSYS_SWEVT_CHANNEL25     = 0x2000000  // Bit CHANNEL25.
	EVSYS_SWEVT_CHANNEL26_Pos = 0x1a       // Position of CHANNEL26 field.
	EVSYS_SWEVT_CHANNEL26_Msk = 0x4000000  // Bit mask of CHANNEL26 field.
	EVSYS_SWEVT_CHANNEL26     = 0x4000000  // Bit CHANNEL26.
	EVSYS_SWEVT_CHANNEL27_Pos = 0x1b       // Position of CHANNEL27 field.
	EVSYS_SWEVT_CHANNEL27_Msk = 0x8000000  // Bit mask of CHANNEL27 field.
	EVSYS_SWEVT_CHANNEL27     = 0x8000000  // Bit CHANNEL27.
	EVSYS_SWEVT_CHANNEL28_Pos = 0x1c       // Position of CHANNEL28 field.
	EVSYS_SWEVT_CHANNEL28_Msk = 0x10000000 // Bit mask of CHANNEL28 field.
	EVSYS_SWEVT_CHANNEL28     = 0x10000000 // Bit CHANNEL28.
	EVSYS_SWEVT_CHANNEL29_Pos = 0x1d       // Position of CHANNEL29 field.
	EVSYS_SWEVT_CHANNEL29_Msk = 0x20000000 // Bit mask of CHANNEL29 field.
	EVSYS_SWEVT_CHANNEL29     = 0x20000000 // Bit CHANNEL29.
	EVSYS_SWEVT_CHANNEL30_Pos = 0x1e       // Position of CHANNEL30 field.
	EVSYS_SWEVT_CHANNEL30_Msk = 0x40000000 // Bit mask of CHANNEL30 field.
	EVSYS_SWEVT_CHANNEL30     = 0x40000000 // Bit CHANNEL30.
	EVSYS_SWEVT_CHANNEL31_Pos = 0x1f       // Position of CHANNEL31 field.
	EVSYS_SWEVT_CHANNEL31_Msk = 0x80000000 // Bit mask of CHANNEL31 field.
	EVSYS_SWEVT_CHANNEL31     = 0x80000000 // Bit CHANNEL31.

	// PRICTRL: Priority Control
	EVSYS_PRICTRL_PRI_Pos  = 0x0  // Position of PRI field.
	EVSYS_PRICTRL_PRI_Msk  = 0xf  // Bit mask of PRI field.
	EVSYS_PRICTRL_RREN_Pos = 0x7  // Position of RREN field.
	EVSYS_PRICTRL_RREN_Msk = 0x80 // Bit mask of RREN field.
	EVSYS_PRICTRL_RREN     = 0x80 // Bit RREN.

	// INTPEND: Channel Pending Interrupt
	EVSYS_INTPEND_ID_Pos    = 0x0    // Position of ID field.
	EVSYS_INTPEND_ID_Msk    = 0xf    // Bit mask of ID field.
	EVSYS_INTPEND_OVR_Pos   = 0x8    // Position of OVR field.
	EVSYS_INTPEND_OVR_Msk   = 0x100  // Bit mask of OVR field.
	EVSYS_INTPEND_OVR       = 0x100  // Bit OVR.
	EVSYS_INTPEND_EVD_Pos   = 0x9    // Position of EVD field.
	EVSYS_INTPEND_EVD_Msk   = 0x200  // Bit mask of EVD field.
	EVSYS_INTPEND_EVD       = 0x200  // Bit EVD.
	EVSYS_INTPEND_READY_Pos = 0xe    // Position of READY field.
	EVSYS_INTPEND_READY_Msk = 0x4000 // Bit mask of READY field.
	EVSYS_INTPEND_READY     = 0x4000 // Bit READY.
	EVSYS_INTPEND_BUSY_Pos  = 0xf    // Position of BUSY field.
	EVSYS_INTPEND_BUSY_Msk  = 0x8000 // Bit mask of BUSY field.
	EVSYS_INTPEND_BUSY      = 0x8000 // Bit BUSY.

	// INTSTATUS: Interrupt Status
	EVSYS_INTSTATUS_CHINT0_Pos  = 0x0   // Position of CHINT0 field.
	EVSYS_INTSTATUS_CHINT0_Msk  = 0x1   // Bit mask of CHINT0 field.
	EVSYS_INTSTATUS_CHINT0      = 0x1   // Bit CHINT0.
	EVSYS_INTSTATUS_CHINT1_Pos  = 0x1   // Position of CHINT1 field.
	EVSYS_INTSTATUS_CHINT1_Msk  = 0x2   // Bit mask of CHINT1 field.
	EVSYS_INTSTATUS_CHINT1      = 0x2   // Bit CHINT1.
	EVSYS_INTSTATUS_CHINT2_Pos  = 0x2   // Position of CHINT2 field.
	EVSYS_INTSTATUS_CHINT2_Msk  = 0x4   // Bit mask of CHINT2 field.
	EVSYS_INTSTATUS_CHINT2      = 0x4   // Bit CHINT2.
	EVSYS_INTSTATUS_CHINT3_Pos  = 0x3   // Position of CHINT3 field.
	EVSYS_INTSTATUS_CHINT3_Msk  = 0x8   // Bit mask of CHINT3 field.
	EVSYS_INTSTATUS_CHINT3      = 0x8   // Bit CHINT3.
	EVSYS_INTSTATUS_CHINT4_Pos  = 0x4   // Position of CHINT4 field.
	EVSYS_INTSTATUS_CHINT4_Msk  = 0x10  // Bit mask of CHINT4 field.
	EVSYS_INTSTATUS_CHINT4      = 0x10  // Bit CHINT4.
	EVSYS_INTSTATUS_CHINT5_Pos  = 0x5   // Position of CHINT5 field.
	EVSYS_INTSTATUS_CHINT5_Msk  = 0x20  // Bit mask of CHINT5 field.
	EVSYS_INTSTATUS_CHINT5      = 0x20  // Bit CHINT5.
	EVSYS_INTSTATUS_CHINT6_Pos  = 0x6   // Position of CHINT6 field.
	EVSYS_INTSTATUS_CHINT6_Msk  = 0x40  // Bit mask of CHINT6 field.
	EVSYS_INTSTATUS_CHINT6      = 0x40  // Bit CHINT6.
	EVSYS_INTSTATUS_CHINT7_Pos  = 0x7   // Position of CHINT7 field.
	EVSYS_INTSTATUS_CHINT7_Msk  = 0x80  // Bit mask of CHINT7 field.
	EVSYS_INTSTATUS_CHINT7      = 0x80  // Bit CHINT7.
	EVSYS_INTSTATUS_CHINT8_Pos  = 0x8   // Position of CHINT8 field.
	EVSYS_INTSTATUS_CHINT8_Msk  = 0x100 // Bit mask of CHINT8 field.
	EVSYS_INTSTATUS_CHINT8      = 0x100 // Bit CHINT8.
	EVSYS_INTSTATUS_CHINT9_Pos  = 0x9   // Position of CHINT9 field.
	EVSYS_INTSTATUS_CHINT9_Msk  = 0x200 // Bit mask of CHINT9 field.
	EVSYS_INTSTATUS_CHINT9      = 0x200 // Bit CHINT9.
	EVSYS_INTSTATUS_CHINT10_Pos = 0xa   // Position of CHINT10 field.
	EVSYS_INTSTATUS_CHINT10_Msk = 0x400 // Bit mask of CHINT10 field.
	EVSYS_INTSTATUS_CHINT10     = 0x400 // Bit CHINT10.
	EVSYS_INTSTATUS_CHINT11_Pos = 0xb   // Position of CHINT11 field.
	EVSYS_INTSTATUS_CHINT11_Msk = 0x800 // Bit mask of CHINT11 field.
	EVSYS_INTSTATUS_CHINT11     = 0x800 // Bit CHINT11.

	// BUSYCH: Busy Channels
	EVSYS_BUSYCH_BUSYCH0_Pos  = 0x0   // Position of BUSYCH0 field.
	EVSYS_BUSYCH_BUSYCH0_Msk  = 0x1   // Bit mask of BUSYCH0 field.
	EVSYS_BUSYCH_BUSYCH0      = 0x1   // Bit BUSYCH0.
	EVSYS_BUSYCH_BUSYCH1_Pos  = 0x1   // Position of BUSYCH1 field.
	EVSYS_BUSYCH_BUSYCH1_Msk  = 0x2   // Bit mask of BUSYCH1 field.
	EVSYS_BUSYCH_BUSYCH1      = 0x2   // Bit BUSYCH1.
	EVSYS_BUSYCH_BUSYCH2_Pos  = 0x2   // Position of BUSYCH2 field.
	EVSYS_BUSYCH_BUSYCH2_Msk  = 0x4   // Bit mask of BUSYCH2 field.
	EVSYS_BUSYCH_BUSYCH2      = 0x4   // Bit BUSYCH2.
	EVSYS_BUSYCH_BUSYCH3_Pos  = 0x3   // Position of BUSYCH3 field.
	EVSYS_BUSYCH_BUSYCH3_Msk  = 0x8   // Bit mask of BUSYCH3 field.
	EVSYS_BUSYCH_BUSYCH3      = 0x8   // Bit BUSYCH3.
	EVSYS_BUSYCH_BUSYCH4_Pos  = 0x4   // Position of BUSYCH4 field.
	EVSYS_BUSYCH_BUSYCH4_Msk  = 0x10  // Bit mask of BUSYCH4 field.
	EVSYS_BUSYCH_BUSYCH4      = 0x10  // Bit BUSYCH4.
	EVSYS_BUSYCH_BUSYCH5_Pos  = 0x5   // Position of BUSYCH5 field.
	EVSYS_BUSYCH_BUSYCH5_Msk  = 0x20  // Bit mask of BUSYCH5 field.
	EVSYS_BUSYCH_BUSYCH5      = 0x20  // Bit BUSYCH5.
	EVSYS_BUSYCH_BUSYCH6_Pos  = 0x6   // Position of BUSYCH6 field.
	EVSYS_BUSYCH_BUSYCH6_Msk  = 0x40  // Bit mask of BUSYCH6 field.
	EVSYS_BUSYCH_BUSYCH6      = 0x40  // Bit BUSYCH6.
	EVSYS_BUSYCH_BUSYCH7_Pos  = 0x7   // Position of BUSYCH7 field.
	EVSYS_BUSYCH_BUSYCH7_Msk  = 0x80  // Bit mask of BUSYCH7 field.
	EVSYS_BUSYCH_BUSYCH7      = 0x80  // Bit BUSYCH7.
	EVSYS_BUSYCH_BUSYCH8_Pos  = 0x8   // Position of BUSYCH8 field.
	EVSYS_BUSYCH_BUSYCH8_Msk  = 0x100 // Bit mask of BUSYCH8 field.
	EVSYS_BUSYCH_BUSYCH8      = 0x100 // Bit BUSYCH8.
	EVSYS_BUSYCH_BUSYCH9_Pos  = 0x9   // Position of BUSYCH9 field.
	EVSYS_BUSYCH_BUSYCH9_Msk  = 0x200 // Bit mask of BUSYCH9 field.
	EVSYS_BUSYCH_BUSYCH9      = 0x200 // Bit BUSYCH9.
	EVSYS_BUSYCH_BUSYCH10_Pos = 0xa   // Position of BUSYCH10 field.
	EVSYS_BUSYCH_BUSYCH10_Msk = 0x400 // Bit mask of BUSYCH10 field.
	EVSYS_BUSYCH_BUSYCH10     = 0x400 // Bit BUSYCH10.
	EVSYS_BUSYCH_BUSYCH11_Pos = 0xb   // Position of BUSYCH11 field.
	EVSYS_BUSYCH_BUSYCH11_Msk = 0x800 // Bit mask of BUSYCH11 field.
	EVSYS_BUSYCH_BUSYCH11     = 0x800 // Bit BUSYCH11.

	// READYUSR: Ready Users
	EVSYS_READYUSR_READYUSR0_Pos  = 0x0   // Position of READYUSR0 field.
	EVSYS_READYUSR_READYUSR0_Msk  = 0x1   // Bit mask of READYUSR0 field.
	EVSYS_READYUSR_READYUSR0      = 0x1   // Bit READYUSR0.
	EVSYS_READYUSR_READYUSR1_Pos  = 0x1   // Position of READYUSR1 field.
	EVSYS_READYUSR_READYUSR1_Msk  = 0x2   // Bit mask of READYUSR1 field.
	EVSYS_READYUSR_READYUSR1      = 0x2   // Bit READYUSR1.
	EVSYS_READYUSR_READYUSR2_Pos  = 0x2   // Position of READYUSR2 field.
	EVSYS_READYUSR_READYUSR2_Msk  = 0x4   // Bit mask of READYUSR2 field.
	EVSYS_READYUSR_READYUSR2      = 0x4   // Bit READYUSR2.
	EVSYS_READYUSR_READYUSR3_Pos  = 0x3   // Position of READYUSR3 field.
	EVSYS_READYUSR_READYUSR3_Msk  = 0x8   // Bit mask of READYUSR3 field.
	EVSYS_READYUSR_READYUSR3      = 0x8   // Bit READYUSR3.
	EVSYS_READYUSR_READYUSR4_Pos  = 0x4   // Position of READYUSR4 field.
	EVSYS_READYUSR_READYUSR4_Msk  = 0x10  // Bit mask of READYUSR4 field.
	EVSYS_READYUSR_READYUSR4      = 0x10  // Bit READYUSR4.
	EVSYS_READYUSR_READYUSR5_Pos  = 0x5   // Position of READYUSR5 field.
	EVSYS_READYUSR_READYUSR5_Msk  = 0x20  // Bit mask of READYUSR5 field.
	EVSYS_READYUSR_READYUSR5      = 0x20  // Bit READYUSR5.
	EVSYS_READYUSR_READYUSR6_Pos  = 0x6   // Position of READYUSR6 field.
	EVSYS_READYUSR_READYUSR6_Msk  = 0x40  // Bit mask of READYUSR6 field.
	EVSYS_READYUSR_READYUSR6      = 0x40  // Bit READYUSR6.
	EVSYS_READYUSR_READYUSR7_Pos  = 0x7   // Position of READYUSR7 field.
	EVSYS_READYUSR_READYUSR7_Msk  = 0x80  // Bit mask of READYUSR7 field.
	EVSYS_READYUSR_READYUSR7      = 0x80  // Bit READYUSR7.
	EVSYS_READYUSR_READYUSR8_Pos  = 0x8   // Position of READYUSR8 field.
	EVSYS_READYUSR_READYUSR8_Msk  = 0x100 // Bit mask of READYUSR8 field.
	EVSYS_READYUSR_READYUSR8      = 0x100 // Bit READYUSR8.
	EVSYS_READYUSR_READYUSR9_Pos  = 0x9   // Position of READYUSR9 field.
	EVSYS_READYUSR_READYUSR9_Msk  = 0x200 // Bit mask of READYUSR9 field.
	EVSYS_READYUSR_READYUSR9      = 0x200 // Bit READYUSR9.
	EVSYS_READYUSR_READYUSR10_Pos = 0xa   // Position of READYUSR10 field.
	EVSYS_READYUSR_READYUSR10_Msk = 0x400 // Bit mask of READYUSR10 field.
	EVSYS_READYUSR_READYUSR10     = 0x400 // Bit READYUSR10.
	EVSYS_READYUSR_READYUSR11_Pos = 0xb   // Position of READYUSR11 field.
	EVSYS_READYUSR_READYUSR11_Msk = 0x800 // Bit mask of READYUSR11 field.
	EVSYS_READYUSR_READYUSR11     = 0x800 // Bit READYUSR11.

	// CHANNEL.CHANNEL: Channel n Control
	EVSYS_CHANNEL_CHANNEL_EVGEN_Pos            = 0x0    // Position of EVGEN field.
	EVSYS_CHANNEL_CHANNEL_EVGEN_Msk            = 0x7f   // Bit mask of EVGEN field.
	EVSYS_CHANNEL_CHANNEL_PATH_Pos             = 0x8    // Position of PATH field.
	EVSYS_CHANNEL_CHANNEL_PATH_Msk             = 0x300  // Bit mask of PATH field.
	EVSYS_CHANNEL_CHANNEL_PATH_SYNCHRONOUS     = 0x0    // Synchronous path
	EVSYS_CHANNEL_CHANNEL_PATH_RESYNCHRONIZED  = 0x1    // Resynchronized path
	EVSYS_CHANNEL_CHANNEL_PATH_ASYNCHRONOUS    = 0x2    // Asynchronous path
	EVSYS_CHANNEL_CHANNEL_EDGSEL_Pos           = 0xa    // Position of EDGSEL field.
	EVSYS_CHANNEL_CHANNEL_EDGSEL_Msk           = 0xc00  // Bit mask of EDGSEL field.
	EVSYS_CHANNEL_CHANNEL_EDGSEL_NO_EVT_OUTPUT = 0x0    // No event output when using the resynchronized or synchronous path
	EVSYS_CHANNEL_CHANNEL_EDGSEL_RISING_EDGE   = 0x1    // Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path
	EVSYS_CHANNEL_CHANNEL_EDGSEL_FALLING_EDGE  = 0x2    // Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path
	EVSYS_CHANNEL_CHANNEL_EDGSEL_BOTH_EDGES    = 0x3    // Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path
	EVSYS_CHANNEL_CHANNEL_RUNSTDBY_Pos         = 0xe    // Position of RUNSTDBY field.
	EVSYS_CHANNEL_CHANNEL_RUNSTDBY_Msk         = 0x4000 // Bit mask of RUNSTDBY field.
	EVSYS_CHANNEL_CHANNEL_RUNSTDBY             = 0x4000 // Bit RUNSTDBY.
	EVSYS_CHANNEL_CHANNEL_ONDEMAND_Pos         = 0xf    // Position of ONDEMAND field.
	EVSYS_CHANNEL_CHANNEL_ONDEMAND_Msk         = 0x8000 // Bit mask of ONDEMAND field.
	EVSYS_CHANNEL_CHANNEL_ONDEMAND             = 0x8000 // Bit ONDEMAND.

	// CHANNEL.CHINTENCLR: Channel n Interrupt Enable Clear
	EVSYS_CHANNEL_CHINTENCLR_OVR_Pos = 0x0 // Position of OVR field.
	EVSYS_CHANNEL_CHINTENCLR_OVR_Msk = 0x1 // Bit mask of OVR field.
	EVSYS_CHANNEL_CHINTENCLR_OVR     = 0x1 // Bit OVR.
	EVSYS_CHANNEL_CHINTENCLR_EVD_Pos = 0x1 // Position of EVD field.
	EVSYS_CHANNEL_CHINTENCLR_EVD_Msk = 0x2 // Bit mask of EVD field.
	EVSYS_CHANNEL_CHINTENCLR_EVD     = 0x2 // Bit EVD.

	// CHANNEL.CHINTENSET: Channel n Interrupt Enable Set
	EVSYS_CHANNEL_CHINTENSET_OVR_Pos = 0x0 // Position of OVR field.
	EVSYS_CHANNEL_CHINTENSET_OVR_Msk = 0x1 // Bit mask of OVR field.
	EVSYS_CHANNEL_CHINTENSET_OVR     = 0x1 // Bit OVR.
	EVSYS_CHANNEL_CHINTENSET_EVD_Pos = 0x1 // Position of EVD field.
	EVSYS_CHANNEL_CHINTENSET_EVD_Msk = 0x2 // Bit mask of EVD field.
	EVSYS_CHANNEL_CHINTENSET_EVD     = 0x2 // Bit EVD.

	// CHANNEL.CHINTFLAG: Channel n Interrupt Flag Status and Clear
	EVSYS_CHANNEL_CHINTFLAG_OVR_Pos = 0x0 // Position of OVR field.
	EVSYS_CHANNEL_CHINTFLAG_OVR_Msk = 0x1 // Bit mask of OVR field.
	EVSYS_CHANNEL_CHINTFLAG_OVR     = 0x1 // Bit OVR.
	EVSYS_CHANNEL_CHINTFLAG_EVD_Pos = 0x1 // Position of EVD field.
	EVSYS_CHANNEL_CHINTFLAG_EVD_Msk = 0x2 // Bit mask of EVD field.
	EVSYS_CHANNEL_CHINTFLAG_EVD     = 0x2 // Bit EVD.

	// CHANNEL.CHSTATUS: Channel n Status
	EVSYS_CHANNEL_CHSTATUS_RDYUSR_Pos = 0x0 // Position of RDYUSR field.
	EVSYS_CHANNEL_CHSTATUS_RDYUSR_Msk = 0x1 // Bit mask of RDYUSR field.
	EVSYS_CHANNEL_CHSTATUS_RDYUSR     = 0x1 // Bit RDYUSR.
	EVSYS_CHANNEL_CHSTATUS_BUSYCH_Pos = 0x1 // Position of BUSYCH field.
	EVSYS_CHANNEL_CHSTATUS_BUSYCH_Msk = 0x2 // Bit mask of BUSYCH field.
	EVSYS_CHANNEL_CHSTATUS_BUSYCH     = 0x2 // Bit BUSYCH.

	// USER: User Multiplexer n
	EVSYS_USER_CHANNEL_Pos = 0x0  // Position of CHANNEL field.
	EVSYS_USER_CHANNEL_Msk = 0x3f // Bit mask of CHANNEL field.
)

// Bitfields for FREQM: Frequency Meter
const (
	// CTRLA: Control A Register
	FREQM_CTRLA_SWRST_Pos  = 0x0 // Position of SWRST field.
	FREQM_CTRLA_SWRST_Msk  = 0x1 // Bit mask of SWRST field.
	FREQM_CTRLA_SWRST      = 0x1 // Bit SWRST.
	FREQM_CTRLA_ENABLE_Pos = 0x1 // Position of ENABLE field.
	FREQM_CTRLA_ENABLE_Msk = 0x2 // Bit mask of ENABLE field.
	FREQM_CTRLA_ENABLE     = 0x2 // Bit ENABLE.

	// CTRLB: Control B Register
	FREQM_CTRLB_START_Pos = 0x0 // Position of START field.
	FREQM_CTRLB_START_Msk = 0x1 // Bit mask of START field.
	FREQM_CTRLB_START     = 0x1 // Bit START.

	// CFGA: Config A register
	FREQM_CFGA_REFNUM_Pos = 0x0  // Position of REFNUM field.
	FREQM_CFGA_REFNUM_Msk = 0xff // Bit mask of REFNUM field.

	// INTENCLR: Interrupt Enable Clear Register
	FREQM_INTENCLR_DONE_Pos = 0x0 // Position of DONE field.
	FREQM_INTENCLR_DONE_Msk = 0x1 // Bit mask of DONE field.
	FREQM_INTENCLR_DONE     = 0x1 // Bit DONE.

	// INTENSET: Interrupt Enable Set Register
	FREQM_INTENSET_DONE_Pos = 0x0 // Position of DONE field.
	FREQM_INTENSET_DONE_Msk = 0x1 // Bit mask of DONE field.
	FREQM_INTENSET_DONE     = 0x1 // Bit DONE.

	// INTFLAG: Interrupt Flag Register
	FREQM_INTFLAG_DONE_Pos = 0x0 // Position of DONE field.
	FREQM_INTFLAG_DONE_Msk = 0x1 // Bit mask of DONE field.
	FREQM_INTFLAG_DONE     = 0x1 // Bit DONE.

	// STATUS: Status Register
	FREQM_STATUS_BUSY_Pos = 0x0 // Position of BUSY field.
	FREQM_STATUS_BUSY_Msk = 0x1 // Bit mask of BUSY field.
	FREQM_STATUS_BUSY     = 0x1 // Bit BUSY.
	FREQM_STATUS_OVF_Pos  = 0x1 // Position of OVF field.
	FREQM_STATUS_OVF_Msk  = 0x2 // Bit mask of OVF field.
	FREQM_STATUS_OVF      = 0x2 // Bit OVF.

	// SYNCBUSY: Synchronization Busy Register
	FREQM_SYNCBUSY_SWRST_Pos  = 0x0 // Position of SWRST field.
	FREQM_SYNCBUSY_SWRST_Msk  = 0x1 // Bit mask of SWRST field.
	FREQM_SYNCBUSY_SWRST      = 0x1 // Bit SWRST.
	FREQM_SYNCBUSY_ENABLE_Pos = 0x1 // Position of ENABLE field.
	FREQM_SYNCBUSY_ENABLE_Msk = 0x2 // Bit mask of ENABLE field.
	FREQM_SYNCBUSY_ENABLE     = 0x2 // Bit ENABLE.

	// VALUE: Count Value Register
	FREQM_VALUE_VALUE_Pos = 0x0      // Position of VALUE field.
	FREQM_VALUE_VALUE_Msk = 0xffffff // Bit mask of VALUE field.
)

// Bitfields for GCLK: Generic Clock Generator
const (
	// CTRLA: Control
	GCLK_CTRLA_SWRST_Pos = 0x0 // Position of SWRST field.
	GCLK_CTRLA_SWRST_Msk = 0x1 // Bit mask of SWRST field.
	GCLK_CTRLA_SWRST     = 0x1 // Bit SWRST.

	// SYNCBUSY: Synchronization Busy
	GCLK_SYNCBUSY_SWRST_Pos      = 0x0    // Position of SWRST field.
	GCLK_SYNCBUSY_SWRST_Msk      = 0x1    // Bit mask of SWRST field.
	GCLK_SYNCBUSY_SWRST          = 0x1    // Bit SWRST.
	GCLK_SYNCBUSY_GENCTRL_Pos    = 0x2    // Position of GENCTRL field.
	GCLK_SYNCBUSY_GENCTRL_Msk    = 0x3ffc // Bit mask of GENCTRL field.
	GCLK_SYNCBUSY_GENCTRL_GCLK0  = 0x1    // Generic clock generator 0
	GCLK_SYNCBUSY_GENCTRL_GCLK1  = 0x2    // Generic clock generator 1
	GCLK_SYNCBUSY_GENCTRL_GCLK2  = 0x4    // Generic clock generator 2
	GCLK_SYNCBUSY_GENCTRL_GCLK3  = 0x8    // Generic clock generator 3
	GCLK_SYNCBUSY_GENCTRL_GCLK4  = 0x10   // Generic clock generator 4
	GCLK_SYNCBUSY_GENCTRL_GCLK5  = 0x20   // Generic clock generator 5
	GCLK_SYNCBUSY_GENCTRL_GCLK6  = 0x40   // Generic clock generator 6
	GCLK_SYNCBUSY_GENCTRL_GCLK7  = 0x80   // Generic clock generator 7
	GCLK_SYNCBUSY_GENCTRL_GCLK8  = 0x100  // Generic clock generator 8
	GCLK_SYNCBUSY_GENCTRL_GCLK9  = 0x200  // Generic clock generator 9
	GCLK_SYNCBUSY_GENCTRL_GCLK10 = 0x400  // Generic clock generator 10
	GCLK_SYNCBUSY_GENCTRL_GCLK11 = 0x800  // Generic clock generator 11

	// GENCTRL: Generic Clock Generator Control
	GCLK_GENCTRL_SRC_Pos       = 0x0        // Position of SRC field.
	GCLK_GENCTRL_SRC_Msk       = 0xf        // Bit mask of SRC field.
	GCLK_GENCTRL_SRC_XOSC0     = 0x0        // XOSC0 oscillator output
	GCLK_GENCTRL_SRC_XOSC1     = 0x1        // XOSC1 oscillator output
	GCLK_GENCTRL_SRC_GCLKIN    = 0x2        // Generator input pad
	GCLK_GENCTRL_SRC_GCLKGEN1  = 0x3        // Generic clock generator 1 output
	GCLK_GENCTRL_SRC_OSCULP32K = 0x4        // OSCULP32K oscillator output
	GCLK_GENCTRL_SRC_XOSC32K   = 0x5        // XOSC32K oscillator output
	GCLK_GENCTRL_SRC_DFLL      = 0x6        // DFLL output
	GCLK_GENCTRL_SRC_DPLL0     = 0x7        // DPLL0 output
	GCLK_GENCTRL_SRC_DPLL1     = 0x8        // DPLL1 output
	GCLK_GENCTRL_GENEN_Pos     = 0x8        // Position of GENEN field.
	GCLK_GENCTRL_GENEN_Msk     = 0x100      // Bit mask of GENEN field.
	GCLK_GENCTRL_GENEN         = 0x100      // Bit GENEN.
	GCLK_GENCTRL_IDC_Pos       = 0x9        // Position of IDC field.
	GCLK_GENCTRL_IDC_Msk       = 0x200      // Bit mask of IDC field.
	GCLK_GENCTRL_IDC           = 0x200      // Bit IDC.
	GCLK_GENCTRL_OOV_Pos       = 0xa        // Position of OOV field.
	GCLK_GENCTRL_OOV_Msk       = 0x400      // Bit mask of OOV field.
	GCLK_GENCTRL_OOV           = 0x400      // Bit OOV.
	GCLK_GENCTRL_OE_Pos        = 0xb        // Position of OE field.
	GCLK_GENCTRL_OE_Msk        = 0x800      // Bit mask of OE field.
	GCLK_GENCTRL_OE            = 0x800      // Bit OE.
	GCLK_GENCTRL_DIVSEL_Pos    = 0xc        // Position of DIVSEL field.
	GCLK_GENCTRL_DIVSEL_Msk    = 0x1000     // Bit mask of DIVSEL field.
	GCLK_GENCTRL_DIVSEL        = 0x1000     // Bit DIVSEL.
	GCLK_GENCTRL_DIVSEL_DIV1   = 0x0        // Divide input directly by divider factor
	GCLK_GENCTRL_DIVSEL_DIV2   = 0x1        // Divide input by 2^(divider factor+ 1)
	GCLK_GENCTRL_RUNSTDBY_Pos  = 0xd        // Position of RUNSTDBY field.
	GCLK_GENCTRL_RUNSTDBY_Msk  = 0x2000     // Bit mask of RUNSTDBY field.
	GCLK_GENCTRL_RUNSTDBY      = 0x2000     // Bit RUNSTDBY.
	GCLK_GENCTRL_DIV_Pos       = 0x10       // Position of DIV field.
	GCLK_GENCTRL_DIV_Msk       = 0xffff0000 // Bit mask of DIV field.

	// PCHCTRL: Peripheral Clock Control
	GCLK_PCHCTRL_GEN_Pos     = 0x0  // Position of GEN field.
	GCLK_PCHCTRL_GEN_Msk     = 0xf  // Bit mask of GEN field.
	GCLK_PCHCTRL_GEN_GCLK0   = 0x0  // Generic clock generator 0
	GCLK_PCHCTRL_GEN_GCLK1   = 0x1  // Generic clock generator 1
	GCLK_PCHCTRL_GEN_GCLK2   = 0x2  // Generic clock generator 2
	GCLK_PCHCTRL_GEN_GCLK3   = 0x3  // Generic clock generator 3
	GCLK_PCHCTRL_GEN_GCLK4   = 0x4  // Generic clock generator 4
	GCLK_PCHCTRL_GEN_GCLK5   = 0x5  // Generic clock generator 5
	GCLK_PCHCTRL_GEN_GCLK6   = 0x6  // Generic clock generator 6
	GCLK_PCHCTRL_GEN_GCLK7   = 0x7  // Generic clock generator 7
	GCLK_PCHCTRL_GEN_GCLK8   = 0x8  // Generic clock generator 8
	GCLK_PCHCTRL_GEN_GCLK9   = 0x9  // Generic clock generator 9
	GCLK_PCHCTRL_GEN_GCLK10  = 0xa  // Generic clock generator 10
	GCLK_PCHCTRL_GEN_GCLK11  = 0xb  // Generic clock generator 11
	GCLK_PCHCTRL_CHEN_Pos    = 0x6  // Position of CHEN field.
	GCLK_PCHCTRL_CHEN_Msk    = 0x40 // Bit mask of CHEN field.
	GCLK_PCHCTRL_CHEN        = 0x40 // Bit CHEN.
	GCLK_PCHCTRL_WRTLOCK_Pos = 0x7  // Position of WRTLOCK field.
	GCLK_PCHCTRL_WRTLOCK_Msk = 0x80 // Bit mask of WRTLOCK field.
	GCLK_PCHCTRL_WRTLOCK     = 0x80 // Bit WRTLOCK.
)

// Bitfields for HMATRIX: HSB Matrix
const (
// PRS.PRAS: Priority A for Slave

// PRS.PRBS: Priority B for Slave
)

// Bitfields for ICM: Integrity Check Monitor
const (
	// CFG: Configuration
	ICM_CFG_WBDIS_Pos    = 0x0        // Position of WBDIS field.
	ICM_CFG_WBDIS_Msk    = 0x1        // Bit mask of WBDIS field.
	ICM_CFG_WBDIS        = 0x1        // Bit WBDIS.
	ICM_CFG_EOMDIS_Pos   = 0x1        // Position of EOMDIS field.
	ICM_CFG_EOMDIS_Msk   = 0x2        // Bit mask of EOMDIS field.
	ICM_CFG_EOMDIS       = 0x2        // Bit EOMDIS.
	ICM_CFG_SLBDIS_Pos   = 0x2        // Position of SLBDIS field.
	ICM_CFG_SLBDIS_Msk   = 0x4        // Bit mask of SLBDIS field.
	ICM_CFG_SLBDIS       = 0x4        // Bit SLBDIS.
	ICM_CFG_BBC_Pos      = 0x4        // Position of BBC field.
	ICM_CFG_BBC_Msk      = 0xf0       // Bit mask of BBC field.
	ICM_CFG_ASCD_Pos     = 0x8        // Position of ASCD field.
	ICM_CFG_ASCD_Msk     = 0x100      // Bit mask of ASCD field.
	ICM_CFG_ASCD         = 0x100      // Bit ASCD.
	ICM_CFG_DUALBUFF_Pos = 0x9        // Position of DUALBUFF field.
	ICM_CFG_DUALBUFF_Msk = 0x200      // Bit mask of DUALBUFF field.
	ICM_CFG_DUALBUFF     = 0x200      // Bit DUALBUFF.
	ICM_CFG_UIHASH_Pos   = 0xc        // Position of UIHASH field.
	ICM_CFG_UIHASH_Msk   = 0x1000     // Bit mask of UIHASH field.
	ICM_CFG_UIHASH       = 0x1000     // Bit UIHASH.
	ICM_CFG_UALGO_Pos    = 0xd        // Position of UALGO field.
	ICM_CFG_UALGO_Msk    = 0xe000     // Bit mask of UALGO field.
	ICM_CFG_UALGO_SHA1   = 0x0        // SHA1 Algorithm
	ICM_CFG_UALGO_SHA256 = 0x1        // SHA256 Algorithm
	ICM_CFG_UALGO_SHA224 = 0x4        // SHA224 Algorithm
	ICM_CFG_HAPROT_Pos   = 0x10       // Position of HAPROT field.
	ICM_CFG_HAPROT_Msk   = 0x3f0000   // Bit mask of HAPROT field.
	ICM_CFG_DAPROT_Pos   = 0x18       // Position of DAPROT field.
	ICM_CFG_DAPROT_Msk   = 0x3f000000 // Bit mask of DAPROT field.

	// CTRL: Control
	ICM_CTRL_ENABLE_Pos  = 0x0    // Position of ENABLE field.
	ICM_CTRL_ENABLE_Msk  = 0x1    // Bit mask of ENABLE field.
	ICM_CTRL_ENABLE      = 0x1    // Bit ENABLE.
	ICM_CTRL_DISABLE_Pos = 0x1    // Position of DISABLE field.
	ICM_CTRL_DISABLE_Msk = 0x2    // Bit mask of DISABLE field.
	ICM_CTRL_DISABLE     = 0x2    // Bit DISABLE.
	ICM_CTRL_SWRST_Pos   = 0x2    // Position of SWRST field.
	ICM_CTRL_SWRST_Msk   = 0x4    // Bit mask of SWRST field.
	ICM_CTRL_SWRST       = 0x4    // Bit SWRST.
	ICM_CTRL_REHASH_Pos  = 0x4    // Position of REHASH field.
	ICM_CTRL_REHASH_Msk  = 0xf0   // Bit mask of REHASH field.
	ICM_CTRL_RMDIS_Pos   = 0x8    // Position of RMDIS field.
	ICM_CTRL_RMDIS_Msk   = 0xf00  // Bit mask of RMDIS field.
	ICM_CTRL_RMEN_Pos    = 0xc    // Position of RMEN field.
	ICM_CTRL_RMEN_Msk    = 0xf000 // Bit mask of RMEN field.

	// SR: Status
	ICM_SR_ENABLE_Pos   = 0x0    // Position of ENABLE field.
	ICM_SR_ENABLE_Msk   = 0x1    // Bit mask of ENABLE field.
	ICM_SR_ENABLE       = 0x1    // Bit ENABLE.
	ICM_SR_RAWRMDIS_Pos = 0x8    // Position of RAWRMDIS field.
	ICM_SR_RAWRMDIS_Msk = 0xf00  // Bit mask of RAWRMDIS field.
	ICM_SR_RMDIS_Pos    = 0xc    // Position of RMDIS field.
	ICM_SR_RMDIS_Msk    = 0xf000 // Bit mask of RMDIS field.

	// IER: Interrupt Enable
	ICM_IER_RHC_Pos  = 0x0       // Position of RHC field.
	ICM_IER_RHC_Msk  = 0xf       // Bit mask of RHC field.
	ICM_IER_RDM_Pos  = 0x4       // Position of RDM field.
	ICM_IER_RDM_Msk  = 0xf0      // Bit mask of RDM field.
	ICM_IER_RBE_Pos  = 0x8       // Position of RBE field.
	ICM_IER_RBE_Msk  = 0xf00     // Bit mask of RBE field.
	ICM_IER_RWC_Pos  = 0xc       // Position of RWC field.
	ICM_IER_RWC_Msk  = 0xf000    // Bit mask of RWC field.
	ICM_IER_REC_Pos  = 0x10      // Position of REC field.
	ICM_IER_REC_Msk  = 0xf0000   // Bit mask of REC field.
	ICM_IER_RSU_Pos  = 0x14      // Position of RSU field.
	ICM_IER_RSU_Msk  = 0xf00000  // Bit mask of RSU field.
	ICM_IER_URAD_Pos = 0x18      // Position of URAD field.
	ICM_IER_URAD_Msk = 0x1000000 // Bit mask of URAD field.
	ICM_IER_URAD     = 0x1000000 // Bit URAD.

	// IDR: Interrupt Disable
	ICM_IDR_RHC_Pos  = 0x0       // Position of RHC field.
	ICM_IDR_RHC_Msk  = 0xf       // Bit mask of RHC field.
	ICM_IDR_RDM_Pos  = 0x4       // Position of RDM field.
	ICM_IDR_RDM_Msk  = 0xf0      // Bit mask of RDM field.
	ICM_IDR_RBE_Pos  = 0x8       // Position of RBE field.
	ICM_IDR_RBE_Msk  = 0xf00     // Bit mask of RBE field.
	ICM_IDR_RWC_Pos  = 0xc       // Position of RWC field.
	ICM_IDR_RWC_Msk  = 0xf000    // Bit mask of RWC field.
	ICM_IDR_REC_Pos  = 0x10      // Position of REC field.
	ICM_IDR_REC_Msk  = 0xf0000   // Bit mask of REC field.
	ICM_IDR_RSU_Pos  = 0x14      // Position of RSU field.
	ICM_IDR_RSU_Msk  = 0xf00000  // Bit mask of RSU field.
	ICM_IDR_URAD_Pos = 0x18      // Position of URAD field.
	ICM_IDR_URAD_Msk = 0x1000000 // Bit mask of URAD field.
	ICM_IDR_URAD     = 0x1000000 // Bit URAD.

	// IMR: Interrupt Mask
	ICM_IMR_RHC_Pos  = 0x0       // Position of RHC field.
	ICM_IMR_RHC_Msk  = 0xf       // Bit mask of RHC field.
	ICM_IMR_RDM_Pos  = 0x4       // Position of RDM field.
	ICM_IMR_RDM_Msk  = 0xf0      // Bit mask of RDM field.
	ICM_IMR_RBE_Pos  = 0x8       // Position of RBE field.
	ICM_IMR_RBE_Msk  = 0xf00     // Bit mask of RBE field.
	ICM_IMR_RWC_Pos  = 0xc       // Position of RWC field.
	ICM_IMR_RWC_Msk  = 0xf000    // Bit mask of RWC field.
	ICM_IMR_REC_Pos  = 0x10      // Position of REC field.
	ICM_IMR_REC_Msk  = 0xf0000   // Bit mask of REC field.
	ICM_IMR_RSU_Pos  = 0x14      // Position of RSU field.
	ICM_IMR_RSU_Msk  = 0xf00000  // Bit mask of RSU field.
	ICM_IMR_URAD_Pos = 0x18      // Position of URAD field.
	ICM_IMR_URAD_Msk = 0x1000000 // Bit mask of URAD field.
	ICM_IMR_URAD     = 0x1000000 // Bit URAD.

	// ISR: Interrupt Status
	ICM_ISR_RHC_Pos  = 0x0       // Position of RHC field.
	ICM_ISR_RHC_Msk  = 0xf       // Bit mask of RHC field.
	ICM_ISR_RDM_Pos  = 0x4       // Position of RDM field.
	ICM_ISR_RDM_Msk  = 0xf0      // Bit mask of RDM field.
	ICM_ISR_RBE_Pos  = 0x8       // Position of RBE field.
	ICM_ISR_RBE_Msk  = 0xf00     // Bit mask of RBE field.
	ICM_ISR_RWC_Pos  = 0xc       // Position of RWC field.
	ICM_ISR_RWC_Msk  = 0xf000    // Bit mask of RWC field.
	ICM_ISR_REC_Pos  = 0x10      // Position of REC field.
	ICM_ISR_REC_Msk  = 0xf0000   // Bit mask of REC field.
	ICM_ISR_RSU_Pos  = 0x14      // Position of RSU field.
	ICM_ISR_RSU_Msk  = 0xf00000  // Bit mask of RSU field.
	ICM_ISR_URAD_Pos = 0x18      // Position of URAD field.
	ICM_ISR_URAD_Msk = 0x1000000 // Bit mask of URAD field.
	ICM_ISR_URAD     = 0x1000000 // Bit URAD.

	// UASR: Undefined Access Status
	ICM_UASR_URAT_Pos                  = 0x0 // Position of URAT field.
	ICM_UASR_URAT_Msk                  = 0x7 // Bit mask of URAT field.
	ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER = 0x0 // Unspecified structure member set to one detected when the descriptor is loaded
	ICM_UASR_URAT_CFG_MODIFIED         = 0x1 // CFG modified during active monitoring
	ICM_UASR_URAT_DSCR_MODIFIED        = 0x2 // DSCR modified during active monitoring
	ICM_UASR_URAT_HASH_MODIFIED        = 0x3 // HASH modified during active monitoring
	ICM_UASR_URAT_READ_ACCESS          = 0x4 // Write-only register read access

	// DSCR: Region Descriptor Area Start Address
	ICM_DSCR_DASA_Pos = 0x6        // Position of DASA field.
	ICM_DSCR_DASA_Msk = 0xffffffc0 // Bit mask of DASA field.

	// HASH: Region Hash Area Start Address
	ICM_HASH_HASA_Pos = 0x7        // Position of HASA field.
	ICM_HASH_HASA_Msk = 0xffffff80 // Bit mask of HASA field.

	// UIHVAL: User Initial Hash Value n
	ICM_UIHVAL_VAL_Pos = 0x0        // Position of VAL field.
	ICM_UIHVAL_VAL_Msk = 0xffffffff // Bit mask of VAL field.
)

// Bitfields for I2S: Inter-IC Sound Interface
const (
	// CTRLA: Control A
	I2S_CTRLA_SWRST_Pos  = 0x0  // Position of SWRST field.
	I2S_CTRLA_SWRST_Msk  = 0x1  // Bit mask of SWRST field.
	I2S_CTRLA_SWRST      = 0x1  // Bit SWRST.
	I2S_CTRLA_ENABLE_Pos = 0x1  // Position of ENABLE field.
	I2S_CTRLA_ENABLE_Msk = 0x2  // Bit mask of ENABLE field.
	I2S_CTRLA_ENABLE     = 0x2  // Bit ENABLE.
	I2S_CTRLA_CKEN0_Pos  = 0x2  // Position of CKEN0 field.
	I2S_CTRLA_CKEN0_Msk  = 0x4  // Bit mask of CKEN0 field.
	I2S_CTRLA_CKEN0      = 0x4  // Bit CKEN0.
	I2S_CTRLA_CKEN1_Pos  = 0x3  // Position of CKEN1 field.
	I2S_CTRLA_CKEN1_Msk  = 0x8  // Bit mask of CKEN1 field.
	I2S_CTRLA_CKEN1      = 0x8  // Bit CKEN1.
	I2S_CTRLA_TXEN_Pos   = 0x4  // Position of TXEN field.
	I2S_CTRLA_TXEN_Msk   = 0x10 // Bit mask of TXEN field.
	I2S_CTRLA_TXEN       = 0x10 // Bit TXEN.
	I2S_CTRLA_RXEN_Pos   = 0x5  // Position of RXEN field.
	I2S_CTRLA_RXEN_Msk   = 0x20 // Bit mask of RXEN field.
	I2S_CTRLA_RXEN       = 0x20 // Bit RXEN.

	// CLKCTRL: Clock Unit n Control
	I2S_CLKCTRL_SLOTSIZE_Pos  = 0x0        // Position of SLOTSIZE field.
	I2S_CLKCTRL_SLOTSIZE_Msk  = 0x3        // Bit mask of SLOTSIZE field.
	I2S_CLKCTRL_SLOTSIZE_8    = 0x0        // 8-bit Slot for Clock Unit n
	I2S_CLKCTRL_SLOTSIZE_16   = 0x1        // 16-bit Slot for Clock Unit n
	I2S_CLKCTRL_SLOTSIZE_24   = 0x2        // 24-bit Slot for Clock Unit n
	I2S_CLKCTRL_SLOTSIZE_32   = 0x3        // 32-bit Slot for Clock Unit n
	I2S_CLKCTRL_NBSLOTS_Pos   = 0x2        // Position of NBSLOTS field.
	I2S_CLKCTRL_NBSLOTS_Msk   = 0x1c       // Bit mask of NBSLOTS field.
	I2S_CLKCTRL_FSWIDTH_Pos   = 0x5        // Position of FSWIDTH field.
	I2S_CLKCTRL_FSWIDTH_Msk   = 0x60       // Bit mask of FSWIDTH field.
	I2S_CLKCTRL_FSWIDTH_SLOT  = 0x0        // Frame Sync Pulse is 1 Slot wide (default for I2S protocol)
	I2S_CLKCTRL_FSWIDTH_HALF  = 0x1        // Frame Sync Pulse is half a Frame wide
	I2S_CLKCTRL_FSWIDTH_BIT   = 0x2        // Frame Sync Pulse is 1 Bit wide
	I2S_CLKCTRL_FSWIDTH_BURST = 0x3        // Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested
	I2S_CLKCTRL_BITDELAY_Pos  = 0x7        // Position of BITDELAY field.
	I2S_CLKCTRL_BITDELAY_Msk  = 0x80       // Bit mask of BITDELAY field.
	I2S_CLKCTRL_BITDELAY      = 0x80       // Bit BITDELAY.
	I2S_CLKCTRL_BITDELAY_LJ   = 0x0        // Left Justified (0 Bit Delay)
	I2S_CLKCTRL_BITDELAY_I2S  = 0x1        // I2S (1 Bit Delay)
	I2S_CLKCTRL_FSSEL_Pos     = 0x8        // Position of FSSEL field.
	I2S_CLKCTRL_FSSEL_Msk     = 0x100      // Bit mask of FSSEL field.
	I2S_CLKCTRL_FSSEL         = 0x100      // Bit FSSEL.
	I2S_CLKCTRL_FSSEL_SCKDIV  = 0x0        // Divided Serial Clock n is used as Frame Sync n source
	I2S_CLKCTRL_FSSEL_FSPIN   = 0x1        // FSn input pin is used as Frame Sync n source
	I2S_CLKCTRL_FSINV_Pos     = 0x9        // Position of FSINV field.
	I2S_CLKCTRL_FSINV_Msk     = 0x200      // Bit mask of FSINV field.
	I2S_CLKCTRL_FSINV         = 0x200      // Bit FSINV.
	I2S_CLKCTRL_FSOUTINV_Pos  = 0xa        // Position of FSOUTINV field.
	I2S_CLKCTRL_FSOUTINV_Msk  = 0x400      // Bit mask of FSOUTINV field.
	I2S_CLKCTRL_FSOUTINV      = 0x400      // Bit FSOUTINV.
	I2S_CLKCTRL_SCKSEL_Pos    = 0xb        // Position of SCKSEL field.
	I2S_CLKCTRL_SCKSEL_Msk    = 0x800      // Bit mask of SCKSEL field.
	I2S_CLKCTRL_SCKSEL        = 0x800      // Bit SCKSEL.
	I2S_CLKCTRL_SCKSEL_MCKDIV = 0x0        // Divided Master Clock n is used as Serial Clock n source
	I2S_CLKCTRL_SCKSEL_SCKPIN = 0x1        // SCKn input pin is used as Serial Clock n source
	I2S_CLKCTRL_SCKOUTINV_Pos = 0xc        // Position of SCKOUTINV field.
	I2S_CLKCTRL_SCKOUTINV_Msk = 0x1000     // Bit mask of SCKOUTINV field.
	I2S_CLKCTRL_SCKOUTINV     = 0x1000     // Bit SCKOUTINV.
	I2S_CLKCTRL_MCKSEL_Pos    = 0xd        // Position of MCKSEL field.
	I2S_CLKCTRL_MCKSEL_Msk    = 0x2000     // Bit mask of MCKSEL field.
	I2S_CLKCTRL_MCKSEL        = 0x2000     // Bit MCKSEL.
	I2S_CLKCTRL_MCKSEL_GCLK   = 0x0        // GCLK_I2S_n is used as Master Clock n source
	I2S_CLKCTRL_MCKSEL_MCKPIN = 0x1        // MCKn input pin is used as Master Clock n source
	I2S_CLKCTRL_MCKEN_Pos     = 0xe        // Position of MCKEN field.
	I2S_CLKCTRL_MCKEN_Msk     = 0x4000     // Bit mask of MCKEN field.
	I2S_CLKCTRL_MCKEN         = 0x4000     // Bit MCKEN.
	I2S_CLKCTRL_MCKOUTINV_Pos = 0xf        // Position of MCKOUTINV field.
	I2S_CLKCTRL_MCKOUTINV_Msk = 0x8000     // Bit mask of MCKOUTINV field.
	I2S_CLKCTRL_MCKOUTINV     = 0x8000     // Bit MCKOUTINV.
	I2S_CLKCTRL_MCKDIV_Pos    = 0x10       // Position of MCKDIV field.
	I2S_CLKCTRL_MCKDIV_Msk    = 0x3f0000   // Bit mask of MCKDIV field.
	I2S_CLKCTRL_MCKOUTDIV_Pos = 0x18       // Position of MCKOUTDIV field.
	I2S_CLKCTRL_MCKOUTDIV_Msk = 0x3f000000 // Bit mask of MCKOUTDIV field.

	// INTENCLR: Interrupt Enable Clear
	I2S_INTENCLR_RXRDY0_Pos = 0x0    // Position of RXRDY0 field.
	I2S_INTENCLR_RXRDY0_Msk = 0x1    // Bit mask of RXRDY0 field.
	I2S_INTENCLR_RXRDY0     = 0x1    // Bit RXRDY0.
	I2S_INTENCLR_RXRDY1_Pos = 0x1    // Position of RXRDY1 field.
	I2S_INTENCLR_RXRDY1_Msk = 0x2    // Bit mask of RXRDY1 field.
	I2S_INTENCLR_RXRDY1     = 0x2    // Bit RXRDY1.
	I2S_INTENCLR_RXOR0_Pos  = 0x4    // Position of RXOR0 field.
	I2S_INTENCLR_RXOR0_Msk  = 0x10   // Bit mask of RXOR0 field.
	I2S_INTENCLR_RXOR0      = 0x10   // Bit RXOR0.
	I2S_INTENCLR_RXOR1_Pos  = 0x5    // Position of RXOR1 field.
	I2S_INTENCLR_RXOR1_Msk  = 0x20   // Bit mask of RXOR1 field.
	I2S_INTENCLR_RXOR1      = 0x20   // Bit RXOR1.
	I2S_INTENCLR_TXRDY0_Pos = 0x8    // Position of TXRDY0 field.
	I2S_INTENCLR_TXRDY0_Msk = 0x100  // Bit mask of TXRDY0 field.
	I2S_INTENCLR_TXRDY0     = 0x100  // Bit TXRDY0.
	I2S_INTENCLR_TXRDY1_Pos = 0x9    // Position of TXRDY1 field.
	I2S_INTENCLR_TXRDY1_Msk = 0x200  // Bit mask of TXRDY1 field.
	I2S_INTENCLR_TXRDY1     = 0x200  // Bit TXRDY1.
	I2S_INTENCLR_TXUR0_Pos  = 0xc    // Position of TXUR0 field.
	I2S_INTENCLR_TXUR0_Msk  = 0x1000 // Bit mask of TXUR0 field.
	I2S_INTENCLR_TXUR0      = 0x1000 // Bit TXUR0.
	I2S_INTENCLR_TXUR1_Pos  = 0xd    // Position of TXUR1 field.
	I2S_INTENCLR_TXUR1_Msk  = 0x2000 // Bit mask of TXUR1 field.
	I2S_INTENCLR_TXUR1      = 0x2000 // Bit TXUR1.

	// INTENSET: Interrupt Enable Set
	I2S_INTENSET_RXRDY0_Pos = 0x0    // Position of RXRDY0 field.
	I2S_INTENSET_RXRDY0_Msk = 0x1    // Bit mask of RXRDY0 field.
	I2S_INTENSET_RXRDY0     = 0x1    // Bit RXRDY0.
	I2S_INTENSET_RXRDY1_Pos = 0x1    // Position of RXRDY1 field.
	I2S_INTENSET_RXRDY1_Msk = 0x2    // Bit mask of RXRDY1 field.
	I2S_INTENSET_RXRDY1     = 0x2    // Bit RXRDY1.
	I2S_INTENSET_RXOR0_Pos  = 0x4    // Position of RXOR0 field.
	I2S_INTENSET_RXOR0_Msk  = 0x10   // Bit mask of RXOR0 field.
	I2S_INTENSET_RXOR0      = 0x10   // Bit RXOR0.
	I2S_INTENSET_RXOR1_Pos  = 0x5    // Position of RXOR1 field.
	I2S_INTENSET_RXOR1_Msk  = 0x20   // Bit mask of RXOR1 field.
	I2S_INTENSET_RXOR1      = 0x20   // Bit RXOR1.
	I2S_INTENSET_TXRDY0_Pos = 0x8    // Position of TXRDY0 field.
	I2S_INTENSET_TXRDY0_Msk = 0x100  // Bit mask of TXRDY0 field.
	I2S_INTENSET_TXRDY0     = 0x100  // Bit TXRDY0.
	I2S_INTENSET_TXRDY1_Pos = 0x9    // Position of TXRDY1 field.
	I2S_INTENSET_TXRDY1_Msk = 0x200  // Bit mask of TXRDY1 field.
	I2S_INTENSET_TXRDY1     = 0x200  // Bit TXRDY1.
	I2S_INTENSET_TXUR0_Pos  = 0xc    // Position of TXUR0 field.
	I2S_INTENSET_TXUR0_Msk  = 0x1000 // Bit mask of TXUR0 field.
	I2S_INTENSET_TXUR0      = 0x1000 // Bit TXUR0.
	I2S_INTENSET_TXUR1_Pos  = 0xd    // Position of TXUR1 field.
	I2S_INTENSET_TXUR1_Msk  = 0x2000 // Bit mask of TXUR1 field.
	I2S_INTENSET_TXUR1      = 0x2000 // Bit TXUR1.

	// INTFLAG: Interrupt Flag Status and Clear
	I2S_INTFLAG_RXRDY0_Pos = 0x0    // Position of RXRDY0 field.
	I2S_INTFLAG_RXRDY0_Msk = 0x1    // Bit mask of RXRDY0 field.
	I2S_INTFLAG_RXRDY0     = 0x1    // Bit RXRDY0.
	I2S_INTFLAG_RXRDY1_Pos = 0x1    // Position of RXRDY1 field.
	I2S_INTFLAG_RXRDY1_Msk = 0x2    // Bit mask of RXRDY1 field.
	I2S_INTFLAG_RXRDY1     = 0x2    // Bit RXRDY1.
	I2S_INTFLAG_RXOR0_Pos  = 0x4    // Position of RXOR0 field.
	I2S_INTFLAG_RXOR0_Msk  = 0x10   // Bit mask of RXOR0 field.
	I2S_INTFLAG_RXOR0      = 0x10   // Bit RXOR0.
	I2S_INTFLAG_RXOR1_Pos  = 0x5    // Position of RXOR1 field.
	I2S_INTFLAG_RXOR1_Msk  = 0x20   // Bit mask of RXOR1 field.
	I2S_INTFLAG_RXOR1      = 0x20   // Bit RXOR1.
	I2S_INTFLAG_TXRDY0_Pos = 0x8    // Position of TXRDY0 field.
	I2S_INTFLAG_TXRDY0_Msk = 0x100  // Bit mask of TXRDY0 field.
	I2S_INTFLAG_TXRDY0     = 0x100  // Bit TXRDY0.
	I2S_INTFLAG_TXRDY1_Pos = 0x9    // Position of TXRDY1 field.
	I2S_INTFLAG_TXRDY1_Msk = 0x200  // Bit mask of TXRDY1 field.
	I2S_INTFLAG_TXRDY1     = 0x200  // Bit TXRDY1.
	I2S_INTFLAG_TXUR0_Pos  = 0xc    // Position of TXUR0 field.
	I2S_INTFLAG_TXUR0_Msk  = 0x1000 // Bit mask of TXUR0 field.
	I2S_INTFLAG_TXUR0      = 0x1000 // Bit TXUR0.
	I2S_INTFLAG_TXUR1_Pos  = 0xd    // Position of TXUR1 field.
	I2S_INTFLAG_TXUR1_Msk  = 0x2000 // Bit mask of TXUR1 field.
	I2S_INTFLAG_TXUR1      = 0x2000 // Bit TXUR1.

	// SYNCBUSY: Synchronization Status
	I2S_SYNCBUSY_SWRST_Pos  = 0x0   // Position of SWRST field.
	I2S_SYNCBUSY_SWRST_Msk  = 0x1   // Bit mask of SWRST field.
	I2S_SYNCBUSY_SWRST      = 0x1   // Bit SWRST.
	I2S_SYNCBUSY_ENABLE_Pos = 0x1   // Position of ENABLE field.
	I2S_SYNCBUSY_ENABLE_Msk = 0x2   // Bit mask of ENABLE field.
	I2S_SYNCBUSY_ENABLE     = 0x2   // Bit ENABLE.
	I2S_SYNCBUSY_CKEN0_Pos  = 0x2   // Position of CKEN0 field.
	I2S_SYNCBUSY_CKEN0_Msk  = 0x4   // Bit mask of CKEN0 field.
	I2S_SYNCBUSY_CKEN0      = 0x4   // Bit CKEN0.
	I2S_SYNCBUSY_CKEN1_Pos  = 0x3   // Position of CKEN1 field.
	I2S_SYNCBUSY_CKEN1_Msk  = 0x8   // Bit mask of CKEN1 field.
	I2S_SYNCBUSY_CKEN1      = 0x8   // Bit CKEN1.
	I2S_SYNCBUSY_TXEN_Pos   = 0x4   // Position of TXEN field.
	I2S_SYNCBUSY_TXEN_Msk   = 0x10  // Bit mask of TXEN field.
	I2S_SYNCBUSY_TXEN       = 0x10  // Bit TXEN.
	I2S_SYNCBUSY_RXEN_Pos   = 0x5   // Position of RXEN field.
	I2S_SYNCBUSY_RXEN_Msk   = 0x20  // Bit mask of RXEN field.
	I2S_SYNCBUSY_RXEN       = 0x20  // Bit RXEN.
	I2S_SYNCBUSY_TXDATA_Pos = 0x8   // Position of TXDATA field.
	I2S_SYNCBUSY_TXDATA_Msk = 0x100 // Bit mask of TXDATA field.
	I2S_SYNCBUSY_TXDATA     = 0x100 // Bit TXDATA.
	I2S_SYNCBUSY_RXDATA_Pos = 0x9   // Position of RXDATA field.
	I2S_SYNCBUSY_RXDATA_Msk = 0x200 // Bit mask of RXDATA field.
	I2S_SYNCBUSY_RXDATA     = 0x200 // Bit RXDATA.

	// TXCTRL: Tx Serializer Control
	I2S_TXCTRL_SERMODE_Pos    = 0x0       // Position of SERMODE field.
	I2S_TXCTRL_SERMODE_Msk    = 0x3       // Bit mask of SERMODE field.
	I2S_TXCTRL_SERMODE_RX     = 0x0       // Receive
	I2S_TXCTRL_SERMODE_TX     = 0x1       // Transmit
	I2S_TXCTRL_SERMODE_PDM2   = 0x2       // Receive one PDM data on each serial clock edge
	I2S_TXCTRL_TXDEFAULT_Pos  = 0x2       // Position of TXDEFAULT field.
	I2S_TXCTRL_TXDEFAULT_Msk  = 0xc       // Bit mask of TXDEFAULT field.
	I2S_TXCTRL_TXDEFAULT_ZERO = 0x0       // Output Default Value is 0
	I2S_TXCTRL_TXDEFAULT_ONE  = 0x1       // Output Default Value is 1
	I2S_TXCTRL_TXDEFAULT_HIZ  = 0x3       // Output Default Value is high impedance
	I2S_TXCTRL_TXSAME_Pos     = 0x4       // Position of TXSAME field.
	I2S_TXCTRL_TXSAME_Msk     = 0x10      // Bit mask of TXSAME field.
	I2S_TXCTRL_TXSAME         = 0x10      // Bit TXSAME.
	I2S_TXCTRL_TXSAME_ZERO    = 0x0       // Zero data transmitted in case of underrun
	I2S_TXCTRL_TXSAME_SAME    = 0x1       // Last data transmitted in case of underrun
	I2S_TXCTRL_CLKSEL_Pos     = 0x5       // Position of CLKSEL field.
	I2S_TXCTRL_CLKSEL_Msk     = 0x20      // Bit mask of CLKSEL field.
	I2S_TXCTRL_CLKSEL         = 0x20      // Bit CLKSEL.
	I2S_TXCTRL_CLKSEL_CLK0    = 0x0       // Use Clock Unit 0
	I2S_TXCTRL_CLKSEL_CLK1    = 0x1       // Use Clock Unit 1
	I2S_TXCTRL_SLOTADJ_Pos    = 0x7       // Position of SLOTADJ field.
	I2S_TXCTRL_SLOTADJ_Msk    = 0x80      // Bit mask of SLOTADJ field.
	I2S_TXCTRL_SLOTADJ        = 0x80      // Bit SLOTADJ.
	I2S_TXCTRL_SLOTADJ_RIGHT  = 0x0       // Data is right adjusted in slot
	I2S_TXCTRL_SLOTADJ_LEFT   = 0x1       // Data is left adjusted in slot
	I2S_TXCTRL_DATASIZE_Pos   = 0x8       // Position of DATASIZE field.
	I2S_TXCTRL_DATASIZE_Msk   = 0x700     // Bit mask of DATASIZE field.
	I2S_TXCTRL_DATASIZE_32    = 0x0       // 32 bits
	I2S_TXCTRL_DATASIZE_24    = 0x1       // 24 bits
	I2S_TXCTRL_DATASIZE_20    = 0x2       // 20 bits
	I2S_TXCTRL_DATASIZE_18    = 0x3       // 18 bits
	I2S_TXCTRL_DATASIZE_16    = 0x4       // 16 bits
	I2S_TXCTRL_DATASIZE_16C   = 0x5       // 16 bits compact stereo
	I2S_TXCTRL_DATASIZE_8     = 0x6       // 8 bits
	I2S_TXCTRL_DATASIZE_8C    = 0x7       // 8 bits compact stereo
	I2S_TXCTRL_WORDADJ_Pos    = 0xc       // Position of WORDADJ field.
	I2S_TXCTRL_WORDADJ_Msk    = 0x1000    // Bit mask of WORDADJ field.
	I2S_TXCTRL_WORDADJ        = 0x1000    // Bit WORDADJ.
	I2S_TXCTRL_WORDADJ_RIGHT  = 0x0       // Data is right adjusted in word
	I2S_TXCTRL_WORDADJ_LEFT   = 0x1       // Data is left adjusted in word
	I2S_TXCTRL_EXTEND_Pos     = 0xd       // Position of EXTEND field.
	I2S_TXCTRL_EXTEND_Msk     = 0x6000    // Bit mask of EXTEND field.
	I2S_TXCTRL_EXTEND_ZERO    = 0x0       // Extend with zeroes
	I2S_TXCTRL_EXTEND_ONE     = 0x1       // Extend with ones
	I2S_TXCTRL_EXTEND_MSBIT   = 0x2       // Extend with Most Significant Bit
	I2S_TXCTRL_EXTEND_LSBIT   = 0x3       // Extend with Least Significant Bit
	I2S_TXCTRL_BITREV_Pos     = 0xf       // Position of BITREV field.
	I2S_TXCTRL_BITREV_Msk     = 0x8000    // Bit mask of BITREV field.
	I2S_TXCTRL_BITREV         = 0x8000    // Bit BITREV.
	I2S_TXCTRL_BITREV_MSBIT   = 0x0       // Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)
	I2S_TXCTRL_BITREV_LSBIT   = 0x1       // Transfer Data Least Significant Bit (LSB) first
	I2S_TXCTRL_SLOTDIS0_Pos   = 0x10      // Position of SLOTDIS0 field.
	I2S_TXCTRL_SLOTDIS0_Msk   = 0x10000   // Bit mask of SLOTDIS0 field.
	I2S_TXCTRL_SLOTDIS0       = 0x10000   // Bit SLOTDIS0.
	I2S_TXCTRL_SLOTDIS1_Pos   = 0x11      // Position of SLOTDIS1 field.
	I2S_TXCTRL_SLOTDIS1_Msk   = 0x20000   // Bit mask of SLOTDIS1 field.
	I2S_TXCTRL_SLOTDIS1       = 0x20000   // Bit SLOTDIS1.
	I2S_TXCTRL_SLOTDIS2_Pos   = 0x12      // Position of SLOTDIS2 field.
	I2S_TXCTRL_SLOTDIS2_Msk   = 0x40000   // Bit mask of SLOTDIS2 field.
	I2S_TXCTRL_SLOTDIS2       = 0x40000   // Bit SLOTDIS2.
	I2S_TXCTRL_SLOTDIS3_Pos   = 0x13      // Position of SLOTDIS3 field.
	I2S_TXCTRL_SLOTDIS3_Msk   = 0x80000   // Bit mask of SLOTDIS3 field.
	I2S_TXCTRL_SLOTDIS3       = 0x80000   // Bit SLOTDIS3.
	I2S_TXCTRL_SLOTDIS4_Pos   = 0x14      // Position of SLOTDIS4 field.
	I2S_TXCTRL_SLOTDIS4_Msk   = 0x100000  // Bit mask of SLOTDIS4 field.
	I2S_TXCTRL_SLOTDIS4       = 0x100000  // Bit SLOTDIS4.
	I2S_TXCTRL_SLOTDIS5_Pos   = 0x15      // Position of SLOTDIS5 field.
	I2S_TXCTRL_SLOTDIS5_Msk   = 0x200000  // Bit mask of SLOTDIS5 field.
	I2S_TXCTRL_SLOTDIS5       = 0x200000  // Bit SLOTDIS5.
	I2S_TXCTRL_SLOTDIS6_Pos   = 0x16      // Position of SLOTDIS6 field.
	I2S_TXCTRL_SLOTDIS6_Msk   = 0x400000  // Bit mask of SLOTDIS6 field.
	I2S_TXCTRL_SLOTDIS6       = 0x400000  // Bit SLOTDIS6.
	I2S_TXCTRL_SLOTDIS7_Pos   = 0x17      // Position of SLOTDIS7 field.
	I2S_TXCTRL_SLOTDIS7_Msk   = 0x800000  // Bit mask of SLOTDIS7 field.
	I2S_TXCTRL_SLOTDIS7       = 0x800000  // Bit SLOTDIS7.
	I2S_TXCTRL_MONO_Pos       = 0x18      // Position of MONO field.
	I2S_TXCTRL_MONO_Msk       = 0x1000000 // Bit mask of MONO field.
	I2S_TXCTRL_MONO           = 0x1000000 // Bit MONO.
	I2S_TXCTRL_MONO_STEREO    = 0x0       // Normal mode
	I2S_TXCTRL_MONO_MONO      = 0x1       // Left channel data is duplicated to right channel
	I2S_TXCTRL_DMA_Pos        = 0x19      // Position of DMA field.
	I2S_TXCTRL_DMA_Msk        = 0x2000000 // Bit mask of DMA field.
	I2S_TXCTRL_DMA            = 0x2000000 // Bit DMA.
	I2S_TXCTRL_DMA_SINGLE     = 0x0       // Single DMA channel
	I2S_TXCTRL_DMA_MULTIPLE   = 0x1       // One DMA channel per data channel

	// RXCTRL: Rx Serializer Control
	I2S_RXCTRL_SERMODE_Pos   = 0x0       // Position of SERMODE field.
	I2S_RXCTRL_SERMODE_Msk   = 0x3       // Bit mask of SERMODE field.
	I2S_RXCTRL_SERMODE_RX    = 0x0       // Receive
	I2S_RXCTRL_SERMODE_PDM2  = 0x2       // Receive one PDM data on each serial clock edge
	I2S_RXCTRL_CLKSEL_Pos    = 0x5       // Position of CLKSEL field.
	I2S_RXCTRL_CLKSEL_Msk    = 0x20      // Bit mask of CLKSEL field.
	I2S_RXCTRL_CLKSEL        = 0x20      // Bit CLKSEL.
	I2S_RXCTRL_CLKSEL_CLK0   = 0x0       // Use Clock Unit 0
	I2S_RXCTRL_CLKSEL_CLK1   = 0x1       // Use Clock Unit 1
	I2S_RXCTRL_SLOTADJ_Pos   = 0x7       // Position of SLOTADJ field.
	I2S_RXCTRL_SLOTADJ_Msk   = 0x80      // Bit mask of SLOTADJ field.
	I2S_RXCTRL_SLOTADJ       = 0x80      // Bit SLOTADJ.
	I2S_RXCTRL_SLOTADJ_RIGHT = 0x0       // Data is right adjusted in slot
	I2S_RXCTRL_SLOTADJ_LEFT  = 0x1       // Data is left adjusted in slot
	I2S_RXCTRL_DATASIZE_Pos  = 0x8       // Position of DATASIZE field.
	I2S_RXCTRL_DATASIZE_Msk  = 0x700     // Bit mask of DATASIZE field.
	I2S_RXCTRL_DATASIZE_32   = 0x0       // 32 bits
	I2S_RXCTRL_DATASIZE_24   = 0x1       // 24 bits
	I2S_RXCTRL_DATASIZE_20   = 0x2       // 20 bits
	I2S_RXCTRL_DATASIZE_18   = 0x3       // 18 bits
	I2S_RXCTRL_DATASIZE_16   = 0x4       // 16 bits
	I2S_RXCTRL_DATASIZE_16C  = 0x5       // 16 bits compact stereo
	I2S_RXCTRL_DATASIZE_8    = 0x6       // 8 bits
	I2S_RXCTRL_DATASIZE_8C   = 0x7       // 8 bits compact stereo
	I2S_RXCTRL_WORDADJ_Pos   = 0xc       // Position of WORDADJ field.
	I2S_RXCTRL_WORDADJ_Msk   = 0x1000    // Bit mask of WORDADJ field.
	I2S_RXCTRL_WORDADJ       = 0x1000    // Bit WORDADJ.
	I2S_RXCTRL_WORDADJ_RIGHT = 0x0       // Data is right adjusted in word
	I2S_RXCTRL_WORDADJ_LEFT  = 0x1       // Data is left adjusted in word
	I2S_RXCTRL_EXTEND_Pos    = 0xd       // Position of EXTEND field.
	I2S_RXCTRL_EXTEND_Msk    = 0x6000    // Bit mask of EXTEND field.
	I2S_RXCTRL_EXTEND_ZERO   = 0x0       // Extend with zeroes
	I2S_RXCTRL_EXTEND_ONE    = 0x1       // Extend with ones
	I2S_RXCTRL_EXTEND_MSBIT  = 0x2       // Extend with Most Significant Bit
	I2S_RXCTRL_EXTEND_LSBIT  = 0x3       // Extend with Least Significant Bit
	I2S_RXCTRL_BITREV_Pos    = 0xf       // Position of BITREV field.
	I2S_RXCTRL_BITREV_Msk    = 0x8000    // Bit mask of BITREV field.
	I2S_RXCTRL_BITREV        = 0x8000    // Bit BITREV.
	I2S_RXCTRL_BITREV_MSBIT  = 0x0       // Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)
	I2S_RXCTRL_BITREV_LSBIT  = 0x1       // Transfer Data Least Significant Bit (LSB) first
	I2S_RXCTRL_SLOTDIS0_Pos  = 0x10      // Position of SLOTDIS0 field.
	I2S_RXCTRL_SLOTDIS0_Msk  = 0x10000   // Bit mask of SLOTDIS0 field.
	I2S_RXCTRL_SLOTDIS0      = 0x10000   // Bit SLOTDIS0.
	I2S_RXCTRL_SLOTDIS1_Pos  = 0x11      // Position of SLOTDIS1 field.
	I2S_RXCTRL_SLOTDIS1_Msk  = 0x20000   // Bit mask of SLOTDIS1 field.
	I2S_RXCTRL_SLOTDIS1      = 0x20000   // Bit SLOTDIS1.
	I2S_RXCTRL_SLOTDIS2_Pos  = 0x12      // Position of SLOTDIS2 field.
	I2S_RXCTRL_SLOTDIS2_Msk  = 0x40000   // Bit mask of SLOTDIS2 field.
	I2S_RXCTRL_SLOTDIS2      = 0x40000   // Bit SLOTDIS2.
	I2S_RXCTRL_SLOTDIS3_Pos  = 0x13      // Position of SLOTDIS3 field.
	I2S_RXCTRL_SLOTDIS3_Msk  = 0x80000   // Bit mask of SLOTDIS3 field.
	I2S_RXCTRL_SLOTDIS3      = 0x80000   // Bit SLOTDIS3.
	I2S_RXCTRL_SLOTDIS4_Pos  = 0x14      // Position of SLOTDIS4 field.
	I2S_RXCTRL_SLOTDIS4_Msk  = 0x100000  // Bit mask of SLOTDIS4 field.
	I2S_RXCTRL_SLOTDIS4      = 0x100000  // Bit SLOTDIS4.
	I2S_RXCTRL_SLOTDIS5_Pos  = 0x15      // Position of SLOTDIS5 field.
	I2S_RXCTRL_SLOTDIS5_Msk  = 0x200000  // Bit mask of SLOTDIS5 field.
	I2S_RXCTRL_SLOTDIS5      = 0x200000  // Bit SLOTDIS5.
	I2S_RXCTRL_SLOTDIS6_Pos  = 0x16      // Position of SLOTDIS6 field.
	I2S_RXCTRL_SLOTDIS6_Msk  = 0x400000  // Bit mask of SLOTDIS6 field.
	I2S_RXCTRL_SLOTDIS6      = 0x400000  // Bit SLOTDIS6.
	I2S_RXCTRL_SLOTDIS7_Pos  = 0x17      // Position of SLOTDIS7 field.
	I2S_RXCTRL_SLOTDIS7_Msk  = 0x800000  // Bit mask of SLOTDIS7 field.
	I2S_RXCTRL_SLOTDIS7      = 0x800000  // Bit SLOTDIS7.
	I2S_RXCTRL_MONO_Pos      = 0x18      // Position of MONO field.
	I2S_RXCTRL_MONO_Msk      = 0x1000000 // Bit mask of MONO field.
	I2S_RXCTRL_MONO          = 0x1000000 // Bit MONO.
	I2S_RXCTRL_MONO_STEREO   = 0x0       // Normal mode
	I2S_RXCTRL_MONO_MONO     = 0x1       // Left channel data is duplicated to right channel
	I2S_RXCTRL_DMA_Pos       = 0x19      // Position of DMA field.
	I2S_RXCTRL_DMA_Msk       = 0x2000000 // Bit mask of DMA field.
	I2S_RXCTRL_DMA           = 0x2000000 // Bit DMA.
	I2S_RXCTRL_DMA_SINGLE    = 0x0       // Single DMA channel
	I2S_RXCTRL_DMA_MULTIPLE  = 0x1       // One DMA channel per data channel
	I2S_RXCTRL_RXLOOP_Pos    = 0x1a      // Position of RXLOOP field.
	I2S_RXCTRL_RXLOOP_Msk    = 0x4000000 // Bit mask of RXLOOP field.
	I2S_RXCTRL_RXLOOP        = 0x4000000 // Bit RXLOOP.

	// TXDATA: Tx Data
	I2S_TXDATA_DATA_Pos = 0x0        // Position of DATA field.
	I2S_TXDATA_DATA_Msk = 0xffffffff // Bit mask of DATA field.

	// RXDATA: Rx Data
	I2S_RXDATA_DATA_Pos = 0x0        // Position of DATA field.
	I2S_RXDATA_DATA_Msk = 0xffffffff // Bit mask of DATA field.
)

// Bitfields for MCLK: Main Clock
const (
	// INTENCLR: Interrupt Enable Clear
	MCLK_INTENCLR_CKRDY_Pos = 0x0 // Position of CKRDY field.
	MCLK_INTENCLR_CKRDY_Msk = 0x1 // Bit mask of CKRDY field.
	MCLK_INTENCLR_CKRDY     = 0x1 // Bit CKRDY.

	// INTENSET: Interrupt Enable Set
	MCLK_INTENSET_CKRDY_Pos = 0x0 // Position of CKRDY field.
	MCLK_INTENSET_CKRDY_Msk = 0x1 // Bit mask of CKRDY field.
	MCLK_INTENSET_CKRDY     = 0x1 // Bit CKRDY.

	// INTFLAG: Interrupt Flag Status and Clear
	MCLK_INTFLAG_CKRDY_Pos = 0x0 // Position of CKRDY field.
	MCLK_INTFLAG_CKRDY_Msk = 0x1 // Bit mask of CKRDY field.
	MCLK_INTFLAG_CKRDY     = 0x1 // Bit CKRDY.

	// HSDIV: HS Clock Division
	MCLK_HSDIV_DIV_Pos  = 0x0  // Position of DIV field.
	MCLK_HSDIV_DIV_Msk  = 0xff // Bit mask of DIV field.
	MCLK_HSDIV_DIV_DIV1 = 0x1  // Divide by 1

	// CPUDIV: CPU Clock Division
	MCLK_CPUDIV_DIV_Pos    = 0x0  // Position of DIV field.
	MCLK_CPUDIV_DIV_Msk    = 0xff // Bit mask of DIV field.
	MCLK_CPUDIV_DIV_DIV1   = 0x1  // Divide by 1
	MCLK_CPUDIV_DIV_DIV2   = 0x2  // Divide by 2
	MCLK_CPUDIV_DIV_DIV4   = 0x4  // Divide by 4
	MCLK_CPUDIV_DIV_DIV8   = 0x8  // Divide by 8
	MCLK_CPUDIV_DIV_DIV16  = 0x10 // Divide by 16
	MCLK_CPUDIV_DIV_DIV32  = 0x20 // Divide by 32
	MCLK_CPUDIV_DIV_DIV64  = 0x40 // Divide by 64
	MCLK_CPUDIV_DIV_DIV128 = 0x80 // Divide by 128

	// AHBMASK: AHB Mask
	MCLK_AHBMASK_HPB0__Pos             = 0x0      // Position of HPB0_ field.
	MCLK_AHBMASK_HPB0__Msk             = 0x1      // Bit mask of HPB0_ field.
	MCLK_AHBMASK_HPB0_                 = 0x1      // Bit HPB0_.
	MCLK_AHBMASK_HPB1__Pos             = 0x1      // Position of HPB1_ field.
	MCLK_AHBMASK_HPB1__Msk             = 0x2      // Bit mask of HPB1_ field.
	MCLK_AHBMASK_HPB1_                 = 0x2      // Bit HPB1_.
	MCLK_AHBMASK_HPB2__Pos             = 0x2      // Position of HPB2_ field.
	MCLK_AHBMASK_HPB2__Msk             = 0x4      // Bit mask of HPB2_ field.
	MCLK_AHBMASK_HPB2_                 = 0x4      // Bit HPB2_.
	MCLK_AHBMASK_HPB3__Pos             = 0x3      // Position of HPB3_ field.
	MCLK_AHBMASK_HPB3__Msk             = 0x8      // Bit mask of HPB3_ field.
	MCLK_AHBMASK_HPB3_                 = 0x8      // Bit HPB3_.
	MCLK_AHBMASK_DSU__Pos              = 0x4      // Position of DSU_ field.
	MCLK_AHBMASK_DSU__Msk              = 0x10     // Bit mask of DSU_ field.
	MCLK_AHBMASK_DSU_                  = 0x10     // Bit DSU_.
	MCLK_AHBMASK_HMATRIX__Pos          = 0x5      // Position of HMATRIX_ field.
	MCLK_AHBMASK_HMATRIX__Msk          = 0x20     // Bit mask of HMATRIX_ field.
	MCLK_AHBMASK_HMATRIX_              = 0x20     // Bit HMATRIX_.
	MCLK_AHBMASK_NVMCTRL__Pos          = 0x6      // Position of NVMCTRL_ field.
	MCLK_AHBMASK_NVMCTRL__Msk          = 0x40     // Bit mask of NVMCTRL_ field.
	MCLK_AHBMASK_NVMCTRL_              = 0x40     // Bit NVMCTRL_.
	MCLK_AHBMASK_HSRAM__Pos            = 0x7      // Position of HSRAM_ field.
	MCLK_AHBMASK_HSRAM__Msk            = 0x80     // Bit mask of HSRAM_ field.
	MCLK_AHBMASK_HSRAM_                = 0x80     // Bit HSRAM_.
	MCLK_AHBMASK_CMCC__Pos             = 0x8      // Position of CMCC_ field.
	MCLK_AHBMASK_CMCC__Msk             = 0x100    // Bit mask of CMCC_ field.
	MCLK_AHBMASK_CMCC_                 = 0x100    // Bit CMCC_.
	MCLK_AHBMASK_DMAC__Pos             = 0x9      // Position of DMAC_ field.
	MCLK_AHBMASK_DMAC__Msk             = 0x200    // Bit mask of DMAC_ field.
	MCLK_AHBMASK_DMAC_                 = 0x200    // Bit DMAC_.
	MCLK_AHBMASK_USB__Pos              = 0xa      // Position of USB_ field.
	MCLK_AHBMASK_USB__Msk              = 0x400    // Bit mask of USB_ field.
	MCLK_AHBMASK_USB_                  = 0x400    // Bit USB_.
	MCLK_AHBMASK_BKUPRAM__Pos          = 0xb      // Position of BKUPRAM_ field.
	MCLK_AHBMASK_BKUPRAM__Msk          = 0x800    // Bit mask of BKUPRAM_ field.
	MCLK_AHBMASK_BKUPRAM_              = 0x800    // Bit BKUPRAM_.
	MCLK_AHBMASK_PAC__Pos              = 0xc      // Position of PAC_ field.
	MCLK_AHBMASK_PAC__Msk              = 0x1000   // Bit mask of PAC_ field.
	MCLK_AHBMASK_PAC_                  = 0x1000   // Bit PAC_.
	MCLK_AHBMASK_QSPI__Pos             = 0xd      // Position of QSPI_ field.
	MCLK_AHBMASK_QSPI__Msk             = 0x2000   // Bit mask of QSPI_ field.
	MCLK_AHBMASK_QSPI_                 = 0x2000   // Bit QSPI_.
	MCLK_AHBMASK_SDHC0__Pos            = 0xf      // Position of SDHC0_ field.
	MCLK_AHBMASK_SDHC0__Msk            = 0x8000   // Bit mask of SDHC0_ field.
	MCLK_AHBMASK_SDHC0_                = 0x8000   // Bit SDHC0_.
	MCLK_AHBMASK_SDHC1__Pos            = 0x10     // Position of SDHC1_ field.
	MCLK_AHBMASK_SDHC1__Msk            = 0x10000  // Bit mask of SDHC1_ field.
	MCLK_AHBMASK_SDHC1_                = 0x10000  // Bit SDHC1_.
	MCLK_AHBMASK_ICM__Pos              = 0x13     // Position of ICM_ field.
	MCLK_AHBMASK_ICM__Msk              = 0x80000  // Bit mask of ICM_ field.
	MCLK_AHBMASK_ICM_                  = 0x80000  // Bit ICM_.
	MCLK_AHBMASK_PUKCC__Pos            = 0x14     // Position of PUKCC_ field.
	MCLK_AHBMASK_PUKCC__Msk            = 0x100000 // Bit mask of PUKCC_ field.
	MCLK_AHBMASK_PUKCC_                = 0x100000 // Bit PUKCC_.
	MCLK_AHBMASK_QSPI_2X__Pos          = 0x15     // Position of QSPI_2X_ field.
	MCLK_AHBMASK_QSPI_2X__Msk          = 0x200000 // Bit mask of QSPI_2X_ field.
	MCLK_AHBMASK_QSPI_2X_              = 0x200000 // Bit QSPI_2X_.
	MCLK_AHBMASK_NVMCTRL_SMEEPROM__Pos = 0x16     // Position of NVMCTRL_SMEEPROM_ field.
	MCLK_AHBMASK_NVMCTRL_SMEEPROM__Msk = 0x400000 // Bit mask of NVMCTRL_SMEEPROM_ field.
	MCLK_AHBMASK_NVMCTRL_SMEEPROM_     = 0x400000 // Bit NVMCTRL_SMEEPROM_.
	MCLK_AHBMASK_NVMCTRL_CACHE__Pos    = 0x17     // Position of NVMCTRL_CACHE_ field.
	MCLK_AHBMASK_NVMCTRL_CACHE__Msk    = 0x800000 // Bit mask of NVMCTRL_CACHE_ field.
	MCLK_AHBMASK_NVMCTRL_CACHE_        = 0x800000 // Bit NVMCTRL_CACHE_.

	// APBAMASK: APBA Mask
	MCLK_APBAMASK_PAC__Pos        = 0x0    // Position of PAC_ field.
	MCLK_APBAMASK_PAC__Msk        = 0x1    // Bit mask of PAC_ field.
	MCLK_APBAMASK_PAC_            = 0x1    // Bit PAC_.
	MCLK_APBAMASK_PM__Pos         = 0x1    // Position of PM_ field.
	MCLK_APBAMASK_PM__Msk         = 0x2    // Bit mask of PM_ field.
	MCLK_APBAMASK_PM_             = 0x2    // Bit PM_.
	MCLK_APBAMASK_MCLK__Pos       = 0x2    // Position of MCLK_ field.
	MCLK_APBAMASK_MCLK__Msk       = 0x4    // Bit mask of MCLK_ field.
	MCLK_APBAMASK_MCLK_           = 0x4    // Bit MCLK_.
	MCLK_APBAMASK_RSTC__Pos       = 0x3    // Position of RSTC_ field.
	MCLK_APBAMASK_RSTC__Msk       = 0x8    // Bit mask of RSTC_ field.
	MCLK_APBAMASK_RSTC_           = 0x8    // Bit RSTC_.
	MCLK_APBAMASK_OSCCTRL__Pos    = 0x4    // Position of OSCCTRL_ field.
	MCLK_APBAMASK_OSCCTRL__Msk    = 0x10   // Bit mask of OSCCTRL_ field.
	MCLK_APBAMASK_OSCCTRL_        = 0x10   // Bit OSCCTRL_.
	MCLK_APBAMASK_OSC32KCTRL__Pos = 0x5    // Position of OSC32KCTRL_ field.
	MCLK_APBAMASK_OSC32KCTRL__Msk = 0x20   // Bit mask of OSC32KCTRL_ field.
	MCLK_APBAMASK_OSC32KCTRL_     = 0x20   // Bit OSC32KCTRL_.
	MCLK_APBAMASK_SUPC__Pos       = 0x6    // Position of SUPC_ field.
	MCLK_APBAMASK_SUPC__Msk       = 0x40   // Bit mask of SUPC_ field.
	MCLK_APBAMASK_SUPC_           = 0x40   // Bit SUPC_.
	MCLK_APBAMASK_GCLK__Pos       = 0x7    // Position of GCLK_ field.
	MCLK_APBAMASK_GCLK__Msk       = 0x80   // Bit mask of GCLK_ field.
	MCLK_APBAMASK_GCLK_           = 0x80   // Bit GCLK_.
	MCLK_APBAMASK_WDT__Pos        = 0x8    // Position of WDT_ field.
	MCLK_APBAMASK_WDT__Msk        = 0x100  // Bit mask of WDT_ field.
	MCLK_APBAMASK_WDT_            = 0x100  // Bit WDT_.
	MCLK_APBAMASK_RTC__Pos        = 0x9    // Position of RTC_ field.
	MCLK_APBAMASK_RTC__Msk        = 0x200  // Bit mask of RTC_ field.
	MCLK_APBAMASK_RTC_            = 0x200  // Bit RTC_.
	MCLK_APBAMASK_EIC__Pos        = 0xa    // Position of EIC_ field.
	MCLK_APBAMASK_EIC__Msk        = 0x400  // Bit mask of EIC_ field.
	MCLK_APBAMASK_EIC_            = 0x400  // Bit EIC_.
	MCLK_APBAMASK_FREQM__Pos      = 0xb    // Position of FREQM_ field.
	MCLK_APBAMASK_FREQM__Msk      = 0x800  // Bit mask of FREQM_ field.
	MCLK_APBAMASK_FREQM_          = 0x800  // Bit FREQM_.
	MCLK_APBAMASK_SERCOM0__Pos    = 0xc    // Position of SERCOM0_ field.
	MCLK_APBAMASK_SERCOM0__Msk    = 0x1000 // Bit mask of SERCOM0_ field.
	MCLK_APBAMASK_SERCOM0_        = 0x1000 // Bit SERCOM0_.
	MCLK_APBAMASK_SERCOM1__Pos    = 0xd    // Position of SERCOM1_ field.
	MCLK_APBAMASK_SERCOM1__Msk    = 0x2000 // Bit mask of SERCOM1_ field.
	MCLK_APBAMASK_SERCOM1_        = 0x2000 // Bit SERCOM1_.
	MCLK_APBAMASK_TC0__Pos        = 0xe    // Position of TC0_ field.
	MCLK_APBAMASK_TC0__Msk        = 0x4000 // Bit mask of TC0_ field.
	MCLK_APBAMASK_TC0_            = 0x4000 // Bit TC0_.
	MCLK_APBAMASK_TC1__Pos        = 0xf    // Position of TC1_ field.
	MCLK_APBAMASK_TC1__Msk        = 0x8000 // Bit mask of TC1_ field.
	MCLK_APBAMASK_TC1_            = 0x8000 // Bit TC1_.

	// APBBMASK: APBB Mask
	MCLK_APBBMASK_USB__Pos     = 0x0     // Position of USB_ field.
	MCLK_APBBMASK_USB__Msk     = 0x1     // Bit mask of USB_ field.
	MCLK_APBBMASK_USB_         = 0x1     // Bit USB_.
	MCLK_APBBMASK_DSU__Pos     = 0x1     // Position of DSU_ field.
	MCLK_APBBMASK_DSU__Msk     = 0x2     // Bit mask of DSU_ field.
	MCLK_APBBMASK_DSU_         = 0x2     // Bit DSU_.
	MCLK_APBBMASK_NVMCTRL__Pos = 0x2     // Position of NVMCTRL_ field.
	MCLK_APBBMASK_NVMCTRL__Msk = 0x4     // Bit mask of NVMCTRL_ field.
	MCLK_APBBMASK_NVMCTRL_     = 0x4     // Bit NVMCTRL_.
	MCLK_APBBMASK_PORT__Pos    = 0x4     // Position of PORT_ field.
	MCLK_APBBMASK_PORT__Msk    = 0x10    // Bit mask of PORT_ field.
	MCLK_APBBMASK_PORT_        = 0x10    // Bit PORT_.
	MCLK_APBBMASK_HMATRIX__Pos = 0x6     // Position of HMATRIX_ field.
	MCLK_APBBMASK_HMATRIX__Msk = 0x40    // Bit mask of HMATRIX_ field.
	MCLK_APBBMASK_HMATRIX_     = 0x40    // Bit HMATRIX_.
	MCLK_APBBMASK_EVSYS__Pos   = 0x7     // Position of EVSYS_ field.
	MCLK_APBBMASK_EVSYS__Msk   = 0x80    // Bit mask of EVSYS_ field.
	MCLK_APBBMASK_EVSYS_       = 0x80    // Bit EVSYS_.
	MCLK_APBBMASK_SERCOM2__Pos = 0x9     // Position of SERCOM2_ field.
	MCLK_APBBMASK_SERCOM2__Msk = 0x200   // Bit mask of SERCOM2_ field.
	MCLK_APBBMASK_SERCOM2_     = 0x200   // Bit SERCOM2_.
	MCLK_APBBMASK_SERCOM3__Pos = 0xa     // Position of SERCOM3_ field.
	MCLK_APBBMASK_SERCOM3__Msk = 0x400   // Bit mask of SERCOM3_ field.
	MCLK_APBBMASK_SERCOM3_     = 0x400   // Bit SERCOM3_.
	MCLK_APBBMASK_TCC0__Pos    = 0xb     // Position of TCC0_ field.
	MCLK_APBBMASK_TCC0__Msk    = 0x800   // Bit mask of TCC0_ field.
	MCLK_APBBMASK_TCC0_        = 0x800   // Bit TCC0_.
	MCLK_APBBMASK_TCC1__Pos    = 0xc     // Position of TCC1_ field.
	MCLK_APBBMASK_TCC1__Msk    = 0x1000  // Bit mask of TCC1_ field.
	MCLK_APBBMASK_TCC1_        = 0x1000  // Bit TCC1_.
	MCLK_APBBMASK_TC2__Pos     = 0xd     // Position of TC2_ field.
	MCLK_APBBMASK_TC2__Msk     = 0x2000  // Bit mask of TC2_ field.
	MCLK_APBBMASK_TC2_         = 0x2000  // Bit TC2_.
	MCLK_APBBMASK_TC3__Pos     = 0xe     // Position of TC3_ field.
	MCLK_APBBMASK_TC3__Msk     = 0x4000  // Bit mask of TC3_ field.
	MCLK_APBBMASK_TC3_         = 0x4000  // Bit TC3_.
	MCLK_APBBMASK_RAMECC__Pos  = 0x10    // Position of RAMECC_ field.
	MCLK_APBBMASK_RAMECC__Msk  = 0x10000 // Bit mask of RAMECC_ field.
	MCLK_APBBMASK_RAMECC_      = 0x10000 // Bit RAMECC_.

	// APBCMASK: APBC Mask
	MCLK_APBCMASK_TCC2__Pos = 0x3    // Position of TCC2_ field.
	MCLK_APBCMASK_TCC2__Msk = 0x8    // Bit mask of TCC2_ field.
	MCLK_APBCMASK_TCC2_     = 0x8    // Bit TCC2_.
	MCLK_APBCMASK_TCC3__Pos = 0x4    // Position of TCC3_ field.
	MCLK_APBCMASK_TCC3__Msk = 0x10   // Bit mask of TCC3_ field.
	MCLK_APBCMASK_TCC3_     = 0x10   // Bit TCC3_.
	MCLK_APBCMASK_TC4__Pos  = 0x5    // Position of TC4_ field.
	MCLK_APBCMASK_TC4__Msk  = 0x20   // Bit mask of TC4_ field.
	MCLK_APBCMASK_TC4_      = 0x20   // Bit TC4_.
	MCLK_APBCMASK_TC5__Pos  = 0x6    // Position of TC5_ field.
	MCLK_APBCMASK_TC5__Msk  = 0x40   // Bit mask of TC5_ field.
	MCLK_APBCMASK_TC5_      = 0x40   // Bit TC5_.
	MCLK_APBCMASK_PDEC__Pos = 0x7    // Position of PDEC_ field.
	MCLK_APBCMASK_PDEC__Msk = 0x80   // Bit mask of PDEC_ field.
	MCLK_APBCMASK_PDEC_     = 0x80   // Bit PDEC_.
	MCLK_APBCMASK_AC__Pos   = 0x8    // Position of AC_ field.
	MCLK_APBCMASK_AC__Msk   = 0x100  // Bit mask of AC_ field.
	MCLK_APBCMASK_AC_       = 0x100  // Bit AC_.
	MCLK_APBCMASK_AES__Pos  = 0x9    // Position of AES_ field.
	MCLK_APBCMASK_AES__Msk  = 0x200  // Bit mask of AES_ field.
	MCLK_APBCMASK_AES_      = 0x200  // Bit AES_.
	MCLK_APBCMASK_TRNG__Pos = 0xa    // Position of TRNG_ field.
	MCLK_APBCMASK_TRNG__Msk = 0x400  // Bit mask of TRNG_ field.
	MCLK_APBCMASK_TRNG_     = 0x400  // Bit TRNG_.
	MCLK_APBCMASK_ICM__Pos  = 0xb    // Position of ICM_ field.
	MCLK_APBCMASK_ICM__Msk  = 0x800  // Bit mask of ICM_ field.
	MCLK_APBCMASK_ICM_      = 0x800  // Bit ICM_.
	MCLK_APBCMASK_QSPI__Pos = 0xd    // Position of QSPI_ field.
	MCLK_APBCMASK_QSPI__Msk = 0x2000 // Bit mask of QSPI_ field.
	MCLK_APBCMASK_QSPI_     = 0x2000 // Bit QSPI_.
	MCLK_APBCMASK_CCL__Pos  = 0xe    // Position of CCL_ field.
	MCLK_APBCMASK_CCL__Msk  = 0x4000 // Bit mask of CCL_ field.
	MCLK_APBCMASK_CCL_      = 0x4000 // Bit CCL_.

	// APBDMASK: APBD Mask
	MCLK_APBDMASK_SERCOM4__Pos = 0x0   // Position of SERCOM4_ field.
	MCLK_APBDMASK_SERCOM4__Msk = 0x1   // Bit mask of SERCOM4_ field.
	MCLK_APBDMASK_SERCOM4_     = 0x1   // Bit SERCOM4_.
	MCLK_APBDMASK_SERCOM5__Pos = 0x1   // Position of SERCOM5_ field.
	MCLK_APBDMASK_SERCOM5__Msk = 0x2   // Bit mask of SERCOM5_ field.
	MCLK_APBDMASK_SERCOM5_     = 0x2   // Bit SERCOM5_.
	MCLK_APBDMASK_SERCOM6__Pos = 0x2   // Position of SERCOM6_ field.
	MCLK_APBDMASK_SERCOM6__Msk = 0x4   // Bit mask of SERCOM6_ field.
	MCLK_APBDMASK_SERCOM6_     = 0x4   // Bit SERCOM6_.
	MCLK_APBDMASK_SERCOM7__Pos = 0x3   // Position of SERCOM7_ field.
	MCLK_APBDMASK_SERCOM7__Msk = 0x8   // Bit mask of SERCOM7_ field.
	MCLK_APBDMASK_SERCOM7_     = 0x8   // Bit SERCOM7_.
	MCLK_APBDMASK_TCC4__Pos    = 0x4   // Position of TCC4_ field.
	MCLK_APBDMASK_TCC4__Msk    = 0x10  // Bit mask of TCC4_ field.
	MCLK_APBDMASK_TCC4_        = 0x10  // Bit TCC4_.
	MCLK_APBDMASK_TC6__Pos     = 0x5   // Position of TC6_ field.
	MCLK_APBDMASK_TC6__Msk     = 0x20  // Bit mask of TC6_ field.
	MCLK_APBDMASK_TC6_         = 0x20  // Bit TC6_.
	MCLK_APBDMASK_TC7__Pos     = 0x6   // Position of TC7_ field.
	MCLK_APBDMASK_TC7__Msk     = 0x40  // Bit mask of TC7_ field.
	MCLK_APBDMASK_TC7_         = 0x40  // Bit TC7_.
	MCLK_APBDMASK_ADC0__Pos    = 0x7   // Position of ADC0_ field.
	MCLK_APBDMASK_ADC0__Msk    = 0x80  // Bit mask of ADC0_ field.
	MCLK_APBDMASK_ADC0_        = 0x80  // Bit ADC0_.
	MCLK_APBDMASK_ADC1__Pos    = 0x8   // Position of ADC1_ field.
	MCLK_APBDMASK_ADC1__Msk    = 0x100 // Bit mask of ADC1_ field.
	MCLK_APBDMASK_ADC1_        = 0x100 // Bit ADC1_.
	MCLK_APBDMASK_DAC__Pos     = 0x9   // Position of DAC_ field.
	MCLK_APBDMASK_DAC__Msk     = 0x200 // Bit mask of DAC_ field.
	MCLK_APBDMASK_DAC_         = 0x200 // Bit DAC_.
	MCLK_APBDMASK_I2S__Pos     = 0xa   // Position of I2S_ field.
	MCLK_APBDMASK_I2S__Msk     = 0x400 // Bit mask of I2S_ field.
	MCLK_APBDMASK_I2S_         = 0x400 // Bit I2S_.
	MCLK_APBDMASK_PCC__Pos     = 0xb   // Position of PCC_ field.
	MCLK_APBDMASK_PCC__Msk     = 0x800 // Bit mask of PCC_ field.
	MCLK_APBDMASK_PCC_         = 0x800 // Bit PCC_.
)

// Bitfields for NVMCTRL: Non-Volatile Memory Controller
const (
	// CTRLA: Control A
	NVMCTRL_CTRLA_AUTOWS_Pos    = 0x2    // Position of AUTOWS field.
	NVMCTRL_CTRLA_AUTOWS_Msk    = 0x4    // Bit mask of AUTOWS field.
	NVMCTRL_CTRLA_AUTOWS        = 0x4    // Bit AUTOWS.
	NVMCTRL_CTRLA_SUSPEN_Pos    = 0x3    // Position of SUSPEN field.
	NVMCTRL_CTRLA_SUSPEN_Msk    = 0x8    // Bit mask of SUSPEN field.
	NVMCTRL_CTRLA_SUSPEN        = 0x8    // Bit SUSPEN.
	NVMCTRL_CTRLA_WMODE_Pos     = 0x4    // Position of WMODE field.
	NVMCTRL_CTRLA_WMODE_Msk     = 0x30   // Bit mask of WMODE field.
	NVMCTRL_CTRLA_WMODE_MAN     = 0x0    // Manual Write
	NVMCTRL_CTRLA_WMODE_ADW     = 0x1    // Automatic Double Word Write
	NVMCTRL_CTRLA_WMODE_AQW     = 0x2    // Automatic Quad Word
	NVMCTRL_CTRLA_WMODE_AP      = 0x3    // Automatic Page Write
	NVMCTRL_CTRLA_PRM_Pos       = 0x6    // Position of PRM field.
	NVMCTRL_CTRLA_PRM_Msk       = 0xc0   // Bit mask of PRM field.
	NVMCTRL_CTRLA_PRM_SEMIAUTO  = 0x0    // NVM block enters low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode upon first access.
	NVMCTRL_CTRLA_PRM_FULLAUTO  = 0x1    // NVM block enters low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode when system is not in standby mode.
	NVMCTRL_CTRLA_PRM_MANUAL    = 0x3    // NVM block does not enter low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode upon first access.
	NVMCTRL_CTRLA_RWS_Pos       = 0x8    // Position of RWS field.
	NVMCTRL_CTRLA_RWS_Msk       = 0xf00  // Bit mask of RWS field.
	NVMCTRL_CTRLA_AHBNS0_Pos    = 0xc    // Position of AHBNS0 field.
	NVMCTRL_CTRLA_AHBNS0_Msk    = 0x1000 // Bit mask of AHBNS0 field.
	NVMCTRL_CTRLA_AHBNS0        = 0x1000 // Bit AHBNS0.
	NVMCTRL_CTRLA_AHBNS1_Pos    = 0xd    // Position of AHBNS1 field.
	NVMCTRL_CTRLA_AHBNS1_Msk    = 0x2000 // Bit mask of AHBNS1 field.
	NVMCTRL_CTRLA_AHBNS1        = 0x2000 // Bit AHBNS1.
	NVMCTRL_CTRLA_CACHEDIS0_Pos = 0xe    // Position of CACHEDIS0 field.
	NVMCTRL_CTRLA_CACHEDIS0_Msk = 0x4000 // Bit mask of CACHEDIS0 field.
	NVMCTRL_CTRLA_CACHEDIS0     = 0x4000 // Bit CACHEDIS0.
	NVMCTRL_CTRLA_CACHEDIS1_Pos = 0xf    // Position of CACHEDIS1 field.
	NVMCTRL_CTRLA_CACHEDIS1_Msk = 0x8000 // Bit mask of CACHEDIS1 field.
	NVMCTRL_CTRLA_CACHEDIS1     = 0x8000 // Bit CACHEDIS1.

	// CTRLB: Control B
	NVMCTRL_CTRLB_CMD_Pos      = 0x0    // Position of CMD field.
	NVMCTRL_CTRLB_CMD_Msk      = 0x7f   // Bit mask of CMD field.
	NVMCTRL_CTRLB_CMD_EP       = 0x0    // Erase Page - Only supported in the USER and AUX pages.
	NVMCTRL_CTRLB_CMD_EB       = 0x1    // Erase Block - Erases the block addressed by the ADDR register, not supported in the user page
	NVMCTRL_CTRLB_CMD_WP       = 0x3    // Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register, not supported in the user page
	NVMCTRL_CTRLB_CMD_WQW      = 0x4    // Write Quad Word - Writes a 128-bit word at the location addressed by the ADDR register.
	NVMCTRL_CTRLB_CMD_SWRST    = 0x10   // Software Reset - Power-Cycle the NVM memory and replay the device automatic calibration procedure and resets the module configuration registers
	NVMCTRL_CTRLB_CMD_LR       = 0x11   // Lock Region - Locks the region containing the address location in the ADDR register.
	NVMCTRL_CTRLB_CMD_UR       = 0x12   // Unlock Region - Unlocks the region containing the address location in the ADDR register.
	NVMCTRL_CTRLB_CMD_SPRM     = 0x13   // Sets the power reduction mode.
	NVMCTRL_CTRLB_CMD_CPRM     = 0x14   // Clears the power reduction mode.
	NVMCTRL_CTRLB_CMD_PBC      = 0x15   // Page Buffer Clear - Clears the page buffer.
	NVMCTRL_CTRLB_CMD_SSB      = 0x16   // Set Security Bit
	NVMCTRL_CTRLB_CMD_BKSWRST  = 0x17   // Bank swap and system reset, if SMEE is used also reallocate SMEE data into the opposite BANK
	NVMCTRL_CTRLB_CMD_CELCK    = 0x18   // Chip Erase Lock - DSU.CE command is not available
	NVMCTRL_CTRLB_CMD_CEULCK   = 0x19   // Chip Erase Unlock - DSU.CE command is available
	NVMCTRL_CTRLB_CMD_SBPDIS   = 0x1a   // Sets STATUS.BPDIS, Boot loader protection is discarded until CBPDIS is issued or next start-up sequence
	NVMCTRL_CTRLB_CMD_CBPDIS   = 0x1b   // Clears STATUS.BPDIS, Boot loader protection is not discarded
	NVMCTRL_CTRLB_CMD_ASEES0   = 0x30   // Activate SmartEEPROM Sector 0, deactivate Sector 1
	NVMCTRL_CTRLB_CMD_ASEES1   = 0x31   // Activate SmartEEPROM Sector 1, deactivate Sector 0
	NVMCTRL_CTRLB_CMD_SEERALOC = 0x32   // Starts SmartEEPROM sector reallocation algorithm
	NVMCTRL_CTRLB_CMD_SEEFLUSH = 0x33   // Flush SMEE data when in buffered mode
	NVMCTRL_CTRLB_CMD_LSEE     = 0x34   // Lock access to SmartEEPROM data from any mean
	NVMCTRL_CTRLB_CMD_USEE     = 0x35   // Unlock access to SmartEEPROM data
	NVMCTRL_CTRLB_CMD_LSEER    = 0x36   // Lock access to the SmartEEPROM Register Address Space (above 64KB)
	NVMCTRL_CTRLB_CMD_USEER    = 0x37   // Unlock access to the SmartEEPROM Register Address Space (above 64KB)
	NVMCTRL_CTRLB_CMDEX_Pos    = 0x8    // Position of CMDEX field.
	NVMCTRL_CTRLB_CMDEX_Msk    = 0xff00 // Bit mask of CMDEX field.
	NVMCTRL_CTRLB_CMDEX_KEY    = 0xa5   // Execution Key

	// PARAM: NVM Parameter
	NVMCTRL_PARAM_NVMP_Pos = 0x0        // Position of NVMP field.
	NVMCTRL_PARAM_NVMP_Msk = 0xffff     // Bit mask of NVMP field.
	NVMCTRL_PARAM_PSZ_Pos  = 0x10       // Position of PSZ field.
	NVMCTRL_PARAM_PSZ_Msk  = 0x70000    // Bit mask of PSZ field.
	NVMCTRL_PARAM_PSZ_8    = 0x0        // 8 bytes
	NVMCTRL_PARAM_PSZ_16   = 0x1        // 16 bytes
	NVMCTRL_PARAM_PSZ_32   = 0x2        // 32 bytes
	NVMCTRL_PARAM_PSZ_64   = 0x3        // 64 bytes
	NVMCTRL_PARAM_PSZ_128  = 0x4        // 128 bytes
	NVMCTRL_PARAM_PSZ_256  = 0x5        // 256 bytes
	NVMCTRL_PARAM_PSZ_512  = 0x6        // 512 bytes
	NVMCTRL_PARAM_PSZ_1024 = 0x7        // 1024 bytes
	NVMCTRL_PARAM_SEE_Pos  = 0x1f       // Position of SEE field.
	NVMCTRL_PARAM_SEE_Msk  = 0x80000000 // Bit mask of SEE field.
	NVMCTRL_PARAM_SEE      = 0x80000000 // Bit SEE.
	NVMCTRL_PARAM_SEE_A    = 0xa        // 163840 bytes
	NVMCTRL_PARAM_SEE_9    = 0x9        // 147456 bytes
	NVMCTRL_PARAM_SEE_8    = 0x8        // 131072 bytes
	NVMCTRL_PARAM_SEE_7    = 0x7        // 114688 bytes
	NVMCTRL_PARAM_SEE_6    = 0x6        // 98304 bytes
	NVMCTRL_PARAM_SEE_5    = 0x5        // 81920 bytes
	NVMCTRL_PARAM_SEE_4    = 0x4        // 65536 bytes
	NVMCTRL_PARAM_SEE_3    = 0x3        // 49152 bytes
	NVMCTRL_PARAM_SEE_2    = 0x2        // 32768 bytes
	NVMCTRL_PARAM_SEE_1    = 0x1        // 16384 bytes
	NVMCTRL_PARAM_SEE_0    = 0x0        // 0 bytes

	// INTENCLR: Interrupt Enable Clear
	NVMCTRL_INTENCLR_DONE_Pos     = 0x0   // Position of DONE field.
	NVMCTRL_INTENCLR_DONE_Msk     = 0x1   // Bit mask of DONE field.
	NVMCTRL_INTENCLR_DONE         = 0x1   // Bit DONE.
	NVMCTRL_INTENCLR_ADDRE_Pos    = 0x1   // Position of ADDRE field.
	NVMCTRL_INTENCLR_ADDRE_Msk    = 0x2   // Bit mask of ADDRE field.
	NVMCTRL_INTENCLR_ADDRE        = 0x2   // Bit ADDRE.
	NVMCTRL_INTENCLR_PROGE_Pos    = 0x2   // Position of PROGE field.
	NVMCTRL_INTENCLR_PROGE_Msk    = 0x4   // Bit mask of PROGE field.
	NVMCTRL_INTENCLR_PROGE        = 0x4   // Bit PROGE.
	NVMCTRL_INTENCLR_LOCKE_Pos    = 0x3   // Position of LOCKE field.
	NVMCTRL_INTENCLR_LOCKE_Msk    = 0x8   // Bit mask of LOCKE field.
	NVMCTRL_INTENCLR_LOCKE        = 0x8   // Bit LOCKE.
	NVMCTRL_INTENCLR_ECCSE_Pos    = 0x4   // Position of ECCSE field.
	NVMCTRL_INTENCLR_ECCSE_Msk    = 0x10  // Bit mask of ECCSE field.
	NVMCTRL_INTENCLR_ECCSE        = 0x10  // Bit ECCSE.
	NVMCTRL_INTENCLR_ECCDE_Pos    = 0x5   // Position of ECCDE field.
	NVMCTRL_INTENCLR_ECCDE_Msk    = 0x20  // Bit mask of ECCDE field.
	NVMCTRL_INTENCLR_ECCDE        = 0x20  // Bit ECCDE.
	NVMCTRL_INTENCLR_NVME_Pos     = 0x6   // Position of NVME field.
	NVMCTRL_INTENCLR_NVME_Msk     = 0x40  // Bit mask of NVME field.
	NVMCTRL_INTENCLR_NVME         = 0x40  // Bit NVME.
	NVMCTRL_INTENCLR_SUSP_Pos     = 0x7   // Position of SUSP field.
	NVMCTRL_INTENCLR_SUSP_Msk     = 0x80  // Bit mask of SUSP field.
	NVMCTRL_INTENCLR_SUSP         = 0x80  // Bit SUSP.
	NVMCTRL_INTENCLR_SEESFULL_Pos = 0x8   // Position of SEESFULL field.
	NVMCTRL_INTENCLR_SEESFULL_Msk = 0x100 // Bit mask of SEESFULL field.
	NVMCTRL_INTENCLR_SEESFULL     = 0x100 // Bit SEESFULL.
	NVMCTRL_INTENCLR_SEESOVF_Pos  = 0x9   // Position of SEESOVF field.
	NVMCTRL_INTENCLR_SEESOVF_Msk  = 0x200 // Bit mask of SEESOVF field.
	NVMCTRL_INTENCLR_SEESOVF      = 0x200 // Bit SEESOVF.
	NVMCTRL_INTENCLR_SEEWRC_Pos   = 0xa   // Position of SEEWRC field.
	NVMCTRL_INTENCLR_SEEWRC_Msk   = 0x400 // Bit mask of SEEWRC field.
	NVMCTRL_INTENCLR_SEEWRC       = 0x400 // Bit SEEWRC.

	// INTENSET: Interrupt Enable Set
	NVMCTRL_INTENSET_DONE_Pos     = 0x0   // Position of DONE field.
	NVMCTRL_INTENSET_DONE_Msk     = 0x1   // Bit mask of DONE field.
	NVMCTRL_INTENSET_DONE         = 0x1   // Bit DONE.
	NVMCTRL_INTENSET_ADDRE_Pos    = 0x1   // Position of ADDRE field.
	NVMCTRL_INTENSET_ADDRE_Msk    = 0x2   // Bit mask of ADDRE field.
	NVMCTRL_INTENSET_ADDRE        = 0x2   // Bit ADDRE.
	NVMCTRL_INTENSET_PROGE_Pos    = 0x2   // Position of PROGE field.
	NVMCTRL_INTENSET_PROGE_Msk    = 0x4   // Bit mask of PROGE field.
	NVMCTRL_INTENSET_PROGE        = 0x4   // Bit PROGE.
	NVMCTRL_INTENSET_LOCKE_Pos    = 0x3   // Position of LOCKE field.
	NVMCTRL_INTENSET_LOCKE_Msk    = 0x8   // Bit mask of LOCKE field.
	NVMCTRL_INTENSET_LOCKE        = 0x8   // Bit LOCKE.
	NVMCTRL_INTENSET_ECCSE_Pos    = 0x4   // Position of ECCSE field.
	NVMCTRL_INTENSET_ECCSE_Msk    = 0x10  // Bit mask of ECCSE field.
	NVMCTRL_INTENSET_ECCSE        = 0x10  // Bit ECCSE.
	NVMCTRL_INTENSET_ECCDE_Pos    = 0x5   // Position of ECCDE field.
	NVMCTRL_INTENSET_ECCDE_Msk    = 0x20  // Bit mask of ECCDE field.
	NVMCTRL_INTENSET_ECCDE        = 0x20  // Bit ECCDE.
	NVMCTRL_INTENSET_NVME_Pos     = 0x6   // Position of NVME field.
	NVMCTRL_INTENSET_NVME_Msk     = 0x40  // Bit mask of NVME field.
	NVMCTRL_INTENSET_NVME         = 0x40  // Bit NVME.
	NVMCTRL_INTENSET_SUSP_Pos     = 0x7   // Position of SUSP field.
	NVMCTRL_INTENSET_SUSP_Msk     = 0x80  // Bit mask of SUSP field.
	NVMCTRL_INTENSET_SUSP         = 0x80  // Bit SUSP.
	NVMCTRL_INTENSET_SEESFULL_Pos = 0x8   // Position of SEESFULL field.
	NVMCTRL_INTENSET_SEESFULL_Msk = 0x100 // Bit mask of SEESFULL field.
	NVMCTRL_INTENSET_SEESFULL     = 0x100 // Bit SEESFULL.
	NVMCTRL_INTENSET_SEESOVF_Pos  = 0x9   // Position of SEESOVF field.
	NVMCTRL_INTENSET_SEESOVF_Msk  = 0x200 // Bit mask of SEESOVF field.
	NVMCTRL_INTENSET_SEESOVF      = 0x200 // Bit SEESOVF.
	NVMCTRL_INTENSET_SEEWRC_Pos   = 0xa   // Position of SEEWRC field.
	NVMCTRL_INTENSET_SEEWRC_Msk   = 0x400 // Bit mask of SEEWRC field.
	NVMCTRL_INTENSET_SEEWRC       = 0x400 // Bit SEEWRC.

	// INTFLAG: Interrupt Flag Status and Clear
	NVMCTRL_INTFLAG_DONE_Pos     = 0x0   // Position of DONE field.
	NVMCTRL_INTFLAG_DONE_Msk     = 0x1   // Bit mask of DONE field.
	NVMCTRL_INTFLAG_DONE         = 0x1   // Bit DONE.
	NVMCTRL_INTFLAG_ADDRE_Pos    = 0x1   // Position of ADDRE field.
	NVMCTRL_INTFLAG_ADDRE_Msk    = 0x2   // Bit mask of ADDRE field.
	NVMCTRL_INTFLAG_ADDRE        = 0x2   // Bit ADDRE.
	NVMCTRL_INTFLAG_PROGE_Pos    = 0x2   // Position of PROGE field.
	NVMCTRL_INTFLAG_PROGE_Msk    = 0x4   // Bit mask of PROGE field.
	NVMCTRL_INTFLAG_PROGE        = 0x4   // Bit PROGE.
	NVMCTRL_INTFLAG_LOCKE_Pos    = 0x3   // Position of LOCKE field.
	NVMCTRL_INTFLAG_LOCKE_Msk    = 0x8   // Bit mask of LOCKE field.
	NVMCTRL_INTFLAG_LOCKE        = 0x8   // Bit LOCKE.
	NVMCTRL_INTFLAG_ECCSE_Pos    = 0x4   // Position of ECCSE field.
	NVMCTRL_INTFLAG_ECCSE_Msk    = 0x10  // Bit mask of ECCSE field.
	NVMCTRL_INTFLAG_ECCSE        = 0x10  // Bit ECCSE.
	NVMCTRL_INTFLAG_ECCDE_Pos    = 0x5   // Position of ECCDE field.
	NVMCTRL_INTFLAG_ECCDE_Msk    = 0x20  // Bit mask of ECCDE field.
	NVMCTRL_INTFLAG_ECCDE        = 0x20  // Bit ECCDE.
	NVMCTRL_INTFLAG_NVME_Pos     = 0x6   // Position of NVME field.
	NVMCTRL_INTFLAG_NVME_Msk     = 0x40  // Bit mask of NVME field.
	NVMCTRL_INTFLAG_NVME         = 0x40  // Bit NVME.
	NVMCTRL_INTFLAG_SUSP_Pos     = 0x7   // Position of SUSP field.
	NVMCTRL_INTFLAG_SUSP_Msk     = 0x80  // Bit mask of SUSP field.
	NVMCTRL_INTFLAG_SUSP         = 0x80  // Bit SUSP.
	NVMCTRL_INTFLAG_SEESFULL_Pos = 0x8   // Position of SEESFULL field.
	NVMCTRL_INTFLAG_SEESFULL_Msk = 0x100 // Bit mask of SEESFULL field.
	NVMCTRL_INTFLAG_SEESFULL     = 0x100 // Bit SEESFULL.
	NVMCTRL_INTFLAG_SEESOVF_Pos  = 0x9   // Position of SEESOVF field.
	NVMCTRL_INTFLAG_SEESOVF_Msk  = 0x200 // Bit mask of SEESOVF field.
	NVMCTRL_INTFLAG_SEESOVF      = 0x200 // Bit SEESOVF.
	NVMCTRL_INTFLAG_SEEWRC_Pos   = 0xa   // Position of SEEWRC field.
	NVMCTRL_INTFLAG_SEEWRC_Msk   = 0x400 // Bit mask of SEEWRC field.
	NVMCTRL_INTFLAG_SEEWRC       = 0x400 // Bit SEEWRC.

	// STATUS: Status
	NVMCTRL_STATUS_READY_Pos    = 0x0   // Position of READY field.
	NVMCTRL_STATUS_READY_Msk    = 0x1   // Bit mask of READY field.
	NVMCTRL_STATUS_READY        = 0x1   // Bit READY.
	NVMCTRL_STATUS_PRM_Pos      = 0x1   // Position of PRM field.
	NVMCTRL_STATUS_PRM_Msk      = 0x2   // Bit mask of PRM field.
	NVMCTRL_STATUS_PRM          = 0x2   // Bit PRM.
	NVMCTRL_STATUS_LOAD_Pos     = 0x2   // Position of LOAD field.
	NVMCTRL_STATUS_LOAD_Msk     = 0x4   // Bit mask of LOAD field.
	NVMCTRL_STATUS_LOAD         = 0x4   // Bit LOAD.
	NVMCTRL_STATUS_SUSP_Pos     = 0x3   // Position of SUSP field.
	NVMCTRL_STATUS_SUSP_Msk     = 0x8   // Bit mask of SUSP field.
	NVMCTRL_STATUS_SUSP         = 0x8   // Bit SUSP.
	NVMCTRL_STATUS_AFIRST_Pos   = 0x4   // Position of AFIRST field.
	NVMCTRL_STATUS_AFIRST_Msk   = 0x10  // Bit mask of AFIRST field.
	NVMCTRL_STATUS_AFIRST       = 0x10  // Bit AFIRST.
	NVMCTRL_STATUS_BPDIS_Pos    = 0x5   // Position of BPDIS field.
	NVMCTRL_STATUS_BPDIS_Msk    = 0x20  // Bit mask of BPDIS field.
	NVMCTRL_STATUS_BPDIS        = 0x20  // Bit BPDIS.
	NVMCTRL_STATUS_BOOTPROT_Pos = 0x8   // Position of BOOTPROT field.
	NVMCTRL_STATUS_BOOTPROT_Msk = 0xf00 // Bit mask of BOOTPROT field.
	NVMCTRL_STATUS_BOOTPROT_0   = 0xf   // 0 kbytes
	NVMCTRL_STATUS_BOOTPROT_8   = 0xe   // 8 kbytes
	NVMCTRL_STATUS_BOOTPROT_16  = 0xd   // 16 kbytes
	NVMCTRL_STATUS_BOOTPROT_24  = 0xc   // 24 kbytes
	NVMCTRL_STATUS_BOOTPROT_32  = 0xb   // 32 kbytes
	NVMCTRL_STATUS_BOOTPROT_40  = 0xa   // 40 kbytes
	NVMCTRL_STATUS_BOOTPROT_48  = 0x9   // 48 kbytes
	NVMCTRL_STATUS_BOOTPROT_56  = 0x8   // 56 kbytes
	NVMCTRL_STATUS_BOOTPROT_64  = 0x7   // 64 kbytes
	NVMCTRL_STATUS_BOOTPROT_72  = 0x6   // 72 kbytes
	NVMCTRL_STATUS_BOOTPROT_80  = 0x5   // 80 kbytes
	NVMCTRL_STATUS_BOOTPROT_88  = 0x4   // 88 kbytes
	NVMCTRL_STATUS_BOOTPROT_96  = 0x3   // 96 kbytes
	NVMCTRL_STATUS_BOOTPROT_104 = 0x2   // 104 kbytes
	NVMCTRL_STATUS_BOOTPROT_112 = 0x1   // 112 kbytes
	NVMCTRL_STATUS_BOOTPROT_120 = 0x0   // 120 kbytes

	// ADDR: Address
	NVMCTRL_ADDR_ADDR_Pos = 0x0      // Position of ADDR field.
	NVMCTRL_ADDR_ADDR_Msk = 0xffffff // Bit mask of ADDR field.

	// RUNLOCK: Lock Section
	NVMCTRL_RUNLOCK_RUNLOCK_Pos = 0x0        // Position of RUNLOCK field.
	NVMCTRL_RUNLOCK_RUNLOCK_Msk = 0xffffffff // Bit mask of RUNLOCK field.

	// PBLDATA: Page Buffer Load Data x
	NVMCTRL_PBLDATA_DATA_Pos = 0x0        // Position of DATA field.
	NVMCTRL_PBLDATA_DATA_Msk = 0xffffffff // Bit mask of DATA field.

	// ECCERR: ECC Error Status Register
	NVMCTRL_ECCERR_ADDR_Pos     = 0x0        // Position of ADDR field.
	NVMCTRL_ECCERR_ADDR_Msk     = 0xffffff   // Bit mask of ADDR field.
	NVMCTRL_ECCERR_TYPEL_Pos    = 0x1c       // Position of TYPEL field.
	NVMCTRL_ECCERR_TYPEL_Msk    = 0x30000000 // Bit mask of TYPEL field.
	NVMCTRL_ECCERR_TYPEL_None   = 0x0        // No Error Detected Since Last Read
	NVMCTRL_ECCERR_TYPEL_Single = 0x1        // At Least One Single Error Detected Since last Read
	NVMCTRL_ECCERR_TYPEL_Dual   = 0x2        // At Least One Dual Error Detected Since Last Read
	NVMCTRL_ECCERR_TYPEH_Pos    = 0x1e       // Position of TYPEH field.
	NVMCTRL_ECCERR_TYPEH_Msk    = 0xc0000000 // Bit mask of TYPEH field.
	NVMCTRL_ECCERR_TYPEH_None   = 0x0        // No Error Detected Since Last Read
	NVMCTRL_ECCERR_TYPEH_Single = 0x1        // At Least One Single Error Detected Since last Read
	NVMCTRL_ECCERR_TYPEH_Dual   = 0x2        // At Least One Dual Error Detected Since Last Read

	// DBGCTRL: Debug Control
	NVMCTRL_DBGCTRL_ECCDIS_Pos  = 0x0 // Position of ECCDIS field.
	NVMCTRL_DBGCTRL_ECCDIS_Msk  = 0x1 // Bit mask of ECCDIS field.
	NVMCTRL_DBGCTRL_ECCDIS      = 0x1 // Bit ECCDIS.
	NVMCTRL_DBGCTRL_ECCELOG_Pos = 0x1 // Position of ECCELOG field.
	NVMCTRL_DBGCTRL_ECCELOG_Msk = 0x2 // Bit mask of ECCELOG field.
	NVMCTRL_DBGCTRL_ECCELOG     = 0x2 // Bit ECCELOG.

	// SEECFG: SmartEEPROM Configuration Register
	NVMCTRL_SEECFG_WMODE_Pos        = 0x0 // Position of WMODE field.
	NVMCTRL_SEECFG_WMODE_Msk        = 0x1 // Bit mask of WMODE field.
	NVMCTRL_SEECFG_WMODE            = 0x1 // Bit WMODE.
	NVMCTRL_SEECFG_WMODE_UNBUFFERED = 0x0 // A NVM write command is issued after each write in the pagebuffer
	NVMCTRL_SEECFG_WMODE_BUFFERED   = 0x1 // A NVM write command is issued when a write to a new page is requested
	NVMCTRL_SEECFG_APRDIS_Pos       = 0x1 // Position of APRDIS field.
	NVMCTRL_SEECFG_APRDIS_Msk       = 0x2 // Bit mask of APRDIS field.
	NVMCTRL_SEECFG_APRDIS           = 0x2 // Bit APRDIS.

	// SEESTAT: SmartEEPROM Status Register
	NVMCTRL_SEESTAT_ASEES_Pos = 0x0     // Position of ASEES field.
	NVMCTRL_SEESTAT_ASEES_Msk = 0x1     // Bit mask of ASEES field.
	NVMCTRL_SEESTAT_ASEES     = 0x1     // Bit ASEES.
	NVMCTRL_SEESTAT_LOAD_Pos  = 0x1     // Position of LOAD field.
	NVMCTRL_SEESTAT_LOAD_Msk  = 0x2     // Bit mask of LOAD field.
	NVMCTRL_SEESTAT_LOAD      = 0x2     // Bit LOAD.
	NVMCTRL_SEESTAT_BUSY_Pos  = 0x2     // Position of BUSY field.
	NVMCTRL_SEESTAT_BUSY_Msk  = 0x4     // Bit mask of BUSY field.
	NVMCTRL_SEESTAT_BUSY      = 0x4     // Bit BUSY.
	NVMCTRL_SEESTAT_LOCK_Pos  = 0x3     // Position of LOCK field.
	NVMCTRL_SEESTAT_LOCK_Msk  = 0x8     // Bit mask of LOCK field.
	NVMCTRL_SEESTAT_LOCK      = 0x8     // Bit LOCK.
	NVMCTRL_SEESTAT_RLOCK_Pos = 0x4     // Position of RLOCK field.
	NVMCTRL_SEESTAT_RLOCK_Msk = 0x10    // Bit mask of RLOCK field.
	NVMCTRL_SEESTAT_RLOCK     = 0x10    // Bit RLOCK.
	NVMCTRL_SEESTAT_SBLK_Pos  = 0x8     // Position of SBLK field.
	NVMCTRL_SEESTAT_SBLK_Msk  = 0xf00   // Bit mask of SBLK field.
	NVMCTRL_SEESTAT_PSZ_Pos   = 0x10    // Position of PSZ field.
	NVMCTRL_SEESTAT_PSZ_Msk   = 0x70000 // Bit mask of PSZ field.
)

// Bitfields for OSCCTRL: Oscillators Control
const (
	// EVCTRL: Event Control
	OSCCTRL_EVCTRL_CFDEO0_Pos = 0x0 // Position of CFDEO0 field.
	OSCCTRL_EVCTRL_CFDEO0_Msk = 0x1 // Bit mask of CFDEO0 field.
	OSCCTRL_EVCTRL_CFDEO0     = 0x1 // Bit CFDEO0.
	OSCCTRL_EVCTRL_CFDEO1_Pos = 0x1 // Position of CFDEO1 field.
	OSCCTRL_EVCTRL_CFDEO1_Msk = 0x2 // Bit mask of CFDEO1 field.
	OSCCTRL_EVCTRL_CFDEO1     = 0x2 // Bit CFDEO1.

	// INTENCLR: Interrupt Enable Clear
	OSCCTRL_INTENCLR_XOSCRDY0_Pos   = 0x0       // Position of XOSCRDY0 field.
	OSCCTRL_INTENCLR_XOSCRDY0_Msk   = 0x1       // Bit mask of XOSCRDY0 field.
	OSCCTRL_INTENCLR_XOSCRDY0       = 0x1       // Bit XOSCRDY0.
	OSCCTRL_INTENCLR_XOSCRDY1_Pos   = 0x1       // Position of XOSCRDY1 field.
	OSCCTRL_INTENCLR_XOSCRDY1_Msk   = 0x2       // Bit mask of XOSCRDY1 field.
	OSCCTRL_INTENCLR_XOSCRDY1       = 0x2       // Bit XOSCRDY1.
	OSCCTRL_INTENCLR_XOSCFAIL0_Pos  = 0x2       // Position of XOSCFAIL0 field.
	OSCCTRL_INTENCLR_XOSCFAIL0_Msk  = 0x4       // Bit mask of XOSCFAIL0 field.
	OSCCTRL_INTENCLR_XOSCFAIL0      = 0x4       // Bit XOSCFAIL0.
	OSCCTRL_INTENCLR_XOSCFAIL1_Pos  = 0x3       // Position of XOSCFAIL1 field.
	OSCCTRL_INTENCLR_XOSCFAIL1_Msk  = 0x8       // Bit mask of XOSCFAIL1 field.
	OSCCTRL_INTENCLR_XOSCFAIL1      = 0x8       // Bit XOSCFAIL1.
	OSCCTRL_INTENCLR_DFLLRDY_Pos    = 0x8       // Position of DFLLRDY field.
	OSCCTRL_INTENCLR_DFLLRDY_Msk    = 0x100     // Bit mask of DFLLRDY field.
	OSCCTRL_INTENCLR_DFLLRDY        = 0x100     // Bit DFLLRDY.
	OSCCTRL_INTENCLR_DFLLOOB_Pos    = 0x9       // Position of DFLLOOB field.
	OSCCTRL_INTENCLR_DFLLOOB_Msk    = 0x200     // Bit mask of DFLLOOB field.
	OSCCTRL_INTENCLR_DFLLOOB        = 0x200     // Bit DFLLOOB.
	OSCCTRL_INTENCLR_DFLLLCKF_Pos   = 0xa       // Position of DFLLLCKF field.
	OSCCTRL_INTENCLR_DFLLLCKF_Msk   = 0x400     // Bit mask of DFLLLCKF field.
	OSCCTRL_INTENCLR_DFLLLCKF       = 0x400     // Bit DFLLLCKF.
	OSCCTRL_INTENCLR_DFLLLCKC_Pos   = 0xb       // Position of DFLLLCKC field.
	OSCCTRL_INTENCLR_DFLLLCKC_Msk   = 0x800     // Bit mask of DFLLLCKC field.
	OSCCTRL_INTENCLR_DFLLLCKC       = 0x800     // Bit DFLLLCKC.
	OSCCTRL_INTENCLR_DFLLRCS_Pos    = 0xc       // Position of DFLLRCS field.
	OSCCTRL_INTENCLR_DFLLRCS_Msk    = 0x1000    // Bit mask of DFLLRCS field.
	OSCCTRL_INTENCLR_DFLLRCS        = 0x1000    // Bit DFLLRCS.
	OSCCTRL_INTENCLR_DPLL0LCKR_Pos  = 0x10      // Position of DPLL0LCKR field.
	OSCCTRL_INTENCLR_DPLL0LCKR_Msk  = 0x10000   // Bit mask of DPLL0LCKR field.
	OSCCTRL_INTENCLR_DPLL0LCKR      = 0x10000   // Bit DPLL0LCKR.
	OSCCTRL_INTENCLR_DPLL0LCKF_Pos  = 0x11      // Position of DPLL0LCKF field.
	OSCCTRL_INTENCLR_DPLL0LCKF_Msk  = 0x20000   // Bit mask of DPLL0LCKF field.
	OSCCTRL_INTENCLR_DPLL0LCKF      = 0x20000   // Bit DPLL0LCKF.
	OSCCTRL_INTENCLR_DPLL0LTO_Pos   = 0x12      // Position of DPLL0LTO field.
	OSCCTRL_INTENCLR_DPLL0LTO_Msk   = 0x40000   // Bit mask of DPLL0LTO field.
	OSCCTRL_INTENCLR_DPLL0LTO       = 0x40000   // Bit DPLL0LTO.
	OSCCTRL_INTENCLR_DPLL0LDRTO_Pos = 0x13      // Position of DPLL0LDRTO field.
	OSCCTRL_INTENCLR_DPLL0LDRTO_Msk = 0x80000   // Bit mask of DPLL0LDRTO field.
	OSCCTRL_INTENCLR_DPLL0LDRTO     = 0x80000   // Bit DPLL0LDRTO.
	OSCCTRL_INTENCLR_DPLL1LCKR_Pos  = 0x18      // Position of DPLL1LCKR field.
	OSCCTRL_INTENCLR_DPLL1LCKR_Msk  = 0x1000000 // Bit mask of DPLL1LCKR field.
	OSCCTRL_INTENCLR_DPLL1LCKR      = 0x1000000 // Bit DPLL1LCKR.
	OSCCTRL_INTENCLR_DPLL1LCKF_Pos  = 0x19      // Position of DPLL1LCKF field.
	OSCCTRL_INTENCLR_DPLL1LCKF_Msk  = 0x2000000 // Bit mask of DPLL1LCKF field.
	OSCCTRL_INTENCLR_DPLL1LCKF      = 0x2000000 // Bit DPLL1LCKF.
	OSCCTRL_INTENCLR_DPLL1LTO_Pos   = 0x1a      // Position of DPLL1LTO field.
	OSCCTRL_INTENCLR_DPLL1LTO_Msk   = 0x4000000 // Bit mask of DPLL1LTO field.
	OSCCTRL_INTENCLR_DPLL1LTO       = 0x4000000 // Bit DPLL1LTO.
	OSCCTRL_INTENCLR_DPLL1LDRTO_Pos = 0x1b      // Position of DPLL1LDRTO field.
	OSCCTRL_INTENCLR_DPLL1LDRTO_Msk = 0x8000000 // Bit mask of DPLL1LDRTO field.
	OSCCTRL_INTENCLR_DPLL1LDRTO     = 0x8000000 // Bit DPLL1LDRTO.

	// INTENSET: Interrupt Enable Set
	OSCCTRL_INTENSET_XOSCRDY0_Pos   = 0x0       // Position of XOSCRDY0 field.
	OSCCTRL_INTENSET_XOSCRDY0_Msk   = 0x1       // Bit mask of XOSCRDY0 field.
	OSCCTRL_INTENSET_XOSCRDY0       = 0x1       // Bit XOSCRDY0.
	OSCCTRL_INTENSET_XOSCRDY1_Pos   = 0x1       // Position of XOSCRDY1 field.
	OSCCTRL_INTENSET_XOSCRDY1_Msk   = 0x2       // Bit mask of XOSCRDY1 field.
	OSCCTRL_INTENSET_XOSCRDY1       = 0x2       // Bit XOSCRDY1.
	OSCCTRL_INTENSET_XOSCFAIL0_Pos  = 0x2       // Position of XOSCFAIL0 field.
	OSCCTRL_INTENSET_XOSCFAIL0_Msk  = 0x4       // Bit mask of XOSCFAIL0 field.
	OSCCTRL_INTENSET_XOSCFAIL0      = 0x4       // Bit XOSCFAIL0.
	OSCCTRL_INTENSET_XOSCFAIL1_Pos  = 0x3       // Position of XOSCFAIL1 field.
	OSCCTRL_INTENSET_XOSCFAIL1_Msk  = 0x8       // Bit mask of XOSCFAIL1 field.
	OSCCTRL_INTENSET_XOSCFAIL1      = 0x8       // Bit XOSCFAIL1.
	OSCCTRL_INTENSET_DFLLRDY_Pos    = 0x8       // Position of DFLLRDY field.
	OSCCTRL_INTENSET_DFLLRDY_Msk    = 0x100     // Bit mask of DFLLRDY field.
	OSCCTRL_INTENSET_DFLLRDY        = 0x100     // Bit DFLLRDY.
	OSCCTRL_INTENSET_DFLLOOB_Pos    = 0x9       // Position of DFLLOOB field.
	OSCCTRL_INTENSET_DFLLOOB_Msk    = 0x200     // Bit mask of DFLLOOB field.
	OSCCTRL_INTENSET_DFLLOOB        = 0x200     // Bit DFLLOOB.
	OSCCTRL_INTENSET_DFLLLCKF_Pos   = 0xa       // Position of DFLLLCKF field.
	OSCCTRL_INTENSET_DFLLLCKF_Msk   = 0x400     // Bit mask of DFLLLCKF field.
	OSCCTRL_INTENSET_DFLLLCKF       = 0x400     // Bit DFLLLCKF.
	OSCCTRL_INTENSET_DFLLLCKC_Pos   = 0xb       // Position of DFLLLCKC field.
	OSCCTRL_INTENSET_DFLLLCKC_Msk   = 0x800     // Bit mask of DFLLLCKC field.
	OSCCTRL_INTENSET_DFLLLCKC       = 0x800     // Bit DFLLLCKC.
	OSCCTRL_INTENSET_DFLLRCS_Pos    = 0xc       // Position of DFLLRCS field.
	OSCCTRL_INTENSET_DFLLRCS_Msk    = 0x1000    // Bit mask of DFLLRCS field.
	OSCCTRL_INTENSET_DFLLRCS        = 0x1000    // Bit DFLLRCS.
	OSCCTRL_INTENSET_DPLL0LCKR_Pos  = 0x10      // Position of DPLL0LCKR field.
	OSCCTRL_INTENSET_DPLL0LCKR_Msk  = 0x10000   // Bit mask of DPLL0LCKR field.
	OSCCTRL_INTENSET_DPLL0LCKR      = 0x10000   // Bit DPLL0LCKR.
	OSCCTRL_INTENSET_DPLL0LCKF_Pos  = 0x11      // Position of DPLL0LCKF field.
	OSCCTRL_INTENSET_DPLL0LCKF_Msk  = 0x20000   // Bit mask of DPLL0LCKF field.
	OSCCTRL_INTENSET_DPLL0LCKF      = 0x20000   // Bit DPLL0LCKF.
	OSCCTRL_INTENSET_DPLL0LTO_Pos   = 0x12      // Position of DPLL0LTO field.
	OSCCTRL_INTENSET_DPLL0LTO_Msk   = 0x40000   // Bit mask of DPLL0LTO field.
	OSCCTRL_INTENSET_DPLL0LTO       = 0x40000   // Bit DPLL0LTO.
	OSCCTRL_INTENSET_DPLL0LDRTO_Pos = 0x13      // Position of DPLL0LDRTO field.
	OSCCTRL_INTENSET_DPLL0LDRTO_Msk = 0x80000   // Bit mask of DPLL0LDRTO field.
	OSCCTRL_INTENSET_DPLL0LDRTO     = 0x80000   // Bit DPLL0LDRTO.
	OSCCTRL_INTENSET_DPLL1LCKR_Pos  = 0x18      // Position of DPLL1LCKR field.
	OSCCTRL_INTENSET_DPLL1LCKR_Msk  = 0x1000000 // Bit mask of DPLL1LCKR field.
	OSCCTRL_INTENSET_DPLL1LCKR      = 0x1000000 // Bit DPLL1LCKR.
	OSCCTRL_INTENSET_DPLL1LCKF_Pos  = 0x19      // Position of DPLL1LCKF field.
	OSCCTRL_INTENSET_DPLL1LCKF_Msk  = 0x2000000 // Bit mask of DPLL1LCKF field.
	OSCCTRL_INTENSET_DPLL1LCKF      = 0x2000000 // Bit DPLL1LCKF.
	OSCCTRL_INTENSET_DPLL1LTO_Pos   = 0x1a      // Position of DPLL1LTO field.
	OSCCTRL_INTENSET_DPLL1LTO_Msk   = 0x4000000 // Bit mask of DPLL1LTO field.
	OSCCTRL_INTENSET_DPLL1LTO       = 0x4000000 // Bit DPLL1LTO.
	OSCCTRL_INTENSET_DPLL1LDRTO_Pos = 0x1b      // Position of DPLL1LDRTO field.
	OSCCTRL_INTENSET_DPLL1LDRTO_Msk = 0x8000000 // Bit mask of DPLL1LDRTO field.
	OSCCTRL_INTENSET_DPLL1LDRTO     = 0x8000000 // Bit DPLL1LDRTO.

	// INTFLAG: Interrupt Flag Status and Clear
	OSCCTRL_INTFLAG_XOSCRDY0_Pos   = 0x0       // Position of XOSCRDY0 field.
	OSCCTRL_INTFLAG_XOSCRDY0_Msk   = 0x1       // Bit mask of XOSCRDY0 field.
	OSCCTRL_INTFLAG_XOSCRDY0       = 0x1       // Bit XOSCRDY0.
	OSCCTRL_INTFLAG_XOSCRDY1_Pos   = 0x1       // Position of XOSCRDY1 field.
	OSCCTRL_INTFLAG_XOSCRDY1_Msk   = 0x2       // Bit mask of XOSCRDY1 field.
	OSCCTRL_INTFLAG_XOSCRDY1       = 0x2       // Bit XOSCRDY1.
	OSCCTRL_INTFLAG_XOSCFAIL0_Pos  = 0x2       // Position of XOSCFAIL0 field.
	OSCCTRL_INTFLAG_XOSCFAIL0_Msk  = 0x4       // Bit mask of XOSCFAIL0 field.
	OSCCTRL_INTFLAG_XOSCFAIL0      = 0x4       // Bit XOSCFAIL0.
	OSCCTRL_INTFLAG_XOSCFAIL1_Pos  = 0x3       // Position of XOSCFAIL1 field.
	OSCCTRL_INTFLAG_XOSCFAIL1_Msk  = 0x8       // Bit mask of XOSCFAIL1 field.
	OSCCTRL_INTFLAG_XOSCFAIL1      = 0x8       // Bit XOSCFAIL1.
	OSCCTRL_INTFLAG_DFLLRDY_Pos    = 0x8       // Position of DFLLRDY field.
	OSCCTRL_INTFLAG_DFLLRDY_Msk    = 0x100     // Bit mask of DFLLRDY field.
	OSCCTRL_INTFLAG_DFLLRDY        = 0x100     // Bit DFLLRDY.
	OSCCTRL_INTFLAG_DFLLOOB_Pos    = 0x9       // Position of DFLLOOB field.
	OSCCTRL_INTFLAG_DFLLOOB_Msk    = 0x200     // Bit mask of DFLLOOB field.
	OSCCTRL_INTFLAG_DFLLOOB        = 0x200     // Bit DFLLOOB.
	OSCCTRL_INTFLAG_DFLLLCKF_Pos   = 0xa       // Position of DFLLLCKF field.
	OSCCTRL_INTFLAG_DFLLLCKF_Msk   = 0x400     // Bit mask of DFLLLCKF field.
	OSCCTRL_INTFLAG_DFLLLCKF       = 0x400     // Bit DFLLLCKF.
	OSCCTRL_INTFLAG_DFLLLCKC_Pos   = 0xb       // Position of DFLLLCKC field.
	OSCCTRL_INTFLAG_DFLLLCKC_Msk   = 0x800     // Bit mask of DFLLLCKC field.
	OSCCTRL_INTFLAG_DFLLLCKC       = 0x800     // Bit DFLLLCKC.
	OSCCTRL_INTFLAG_DFLLRCS_Pos    = 0xc       // Position of DFLLRCS field.
	OSCCTRL_INTFLAG_DFLLRCS_Msk    = 0x1000    // Bit mask of DFLLRCS field.
	OSCCTRL_INTFLAG_DFLLRCS        = 0x1000    // Bit DFLLRCS.
	OSCCTRL_INTFLAG_DPLL0LCKR_Pos  = 0x10      // Position of DPLL0LCKR field.
	OSCCTRL_INTFLAG_DPLL0LCKR_Msk  = 0x10000   // Bit mask of DPLL0LCKR field.
	OSCCTRL_INTFLAG_DPLL0LCKR      = 0x10000   // Bit DPLL0LCKR.
	OSCCTRL_INTFLAG_DPLL0LCKF_Pos  = 0x11      // Position of DPLL0LCKF field.
	OSCCTRL_INTFLAG_DPLL0LCKF_Msk  = 0x20000   // Bit mask of DPLL0LCKF field.
	OSCCTRL_INTFLAG_DPLL0LCKF      = 0x20000   // Bit DPLL0LCKF.
	OSCCTRL_INTFLAG_DPLL0LTO_Pos   = 0x12      // Position of DPLL0LTO field.
	OSCCTRL_INTFLAG_DPLL0LTO_Msk   = 0x40000   // Bit mask of DPLL0LTO field.
	OSCCTRL_INTFLAG_DPLL0LTO       = 0x40000   // Bit DPLL0LTO.
	OSCCTRL_INTFLAG_DPLL0LDRTO_Pos = 0x13      // Position of DPLL0LDRTO field.
	OSCCTRL_INTFLAG_DPLL0LDRTO_Msk = 0x80000   // Bit mask of DPLL0LDRTO field.
	OSCCTRL_INTFLAG_DPLL0LDRTO     = 0x80000   // Bit DPLL0LDRTO.
	OSCCTRL_INTFLAG_DPLL1LCKR_Pos  = 0x18      // Position of DPLL1LCKR field.
	OSCCTRL_INTFLAG_DPLL1LCKR_Msk  = 0x1000000 // Bit mask of DPLL1LCKR field.
	OSCCTRL_INTFLAG_DPLL1LCKR      = 0x1000000 // Bit DPLL1LCKR.
	OSCCTRL_INTFLAG_DPLL1LCKF_Pos  = 0x19      // Position of DPLL1LCKF field.
	OSCCTRL_INTFLAG_DPLL1LCKF_Msk  = 0x2000000 // Bit mask of DPLL1LCKF field.
	OSCCTRL_INTFLAG_DPLL1LCKF      = 0x2000000 // Bit DPLL1LCKF.
	OSCCTRL_INTFLAG_DPLL1LTO_Pos   = 0x1a      // Position of DPLL1LTO field.
	OSCCTRL_INTFLAG_DPLL1LTO_Msk   = 0x4000000 // Bit mask of DPLL1LTO field.
	OSCCTRL_INTFLAG_DPLL1LTO       = 0x4000000 // Bit DPLL1LTO.
	OSCCTRL_INTFLAG_DPLL1LDRTO_Pos = 0x1b      // Position of DPLL1LDRTO field.
	OSCCTRL_INTFLAG_DPLL1LDRTO_Msk = 0x8000000 // Bit mask of DPLL1LDRTO field.
	OSCCTRL_INTFLAG_DPLL1LDRTO     = 0x8000000 // Bit DPLL1LDRTO.

	// STATUS: Status
	OSCCTRL_STATUS_XOSCRDY0_Pos   = 0x0       // Position of XOSCRDY0 field.
	OSCCTRL_STATUS_XOSCRDY0_Msk   = 0x1       // Bit mask of XOSCRDY0 field.
	OSCCTRL_STATUS_XOSCRDY0       = 0x1       // Bit XOSCRDY0.
	OSCCTRL_STATUS_XOSCRDY1_Pos   = 0x1       // Position of XOSCRDY1 field.
	OSCCTRL_STATUS_XOSCRDY1_Msk   = 0x2       // Bit mask of XOSCRDY1 field.
	OSCCTRL_STATUS_XOSCRDY1       = 0x2       // Bit XOSCRDY1.
	OSCCTRL_STATUS_XOSCFAIL0_Pos  = 0x2       // Position of XOSCFAIL0 field.
	OSCCTRL_STATUS_XOSCFAIL0_Msk  = 0x4       // Bit mask of XOSCFAIL0 field.
	OSCCTRL_STATUS_XOSCFAIL0      = 0x4       // Bit XOSCFAIL0.
	OSCCTRL_STATUS_XOSCFAIL1_Pos  = 0x3       // Position of XOSCFAIL1 field.
	OSCCTRL_STATUS_XOSCFAIL1_Msk  = 0x8       // Bit mask of XOSCFAIL1 field.
	OSCCTRL_STATUS_XOSCFAIL1      = 0x8       // Bit XOSCFAIL1.
	OSCCTRL_STATUS_XOSCCKSW0_Pos  = 0x4       // Position of XOSCCKSW0 field.
	OSCCTRL_STATUS_XOSCCKSW0_Msk  = 0x10      // Bit mask of XOSCCKSW0 field.
	OSCCTRL_STATUS_XOSCCKSW0      = 0x10      // Bit XOSCCKSW0.
	OSCCTRL_STATUS_XOSCCKSW1_Pos  = 0x5       // Position of XOSCCKSW1 field.
	OSCCTRL_STATUS_XOSCCKSW1_Msk  = 0x20      // Bit mask of XOSCCKSW1 field.
	OSCCTRL_STATUS_XOSCCKSW1      = 0x20      // Bit XOSCCKSW1.
	OSCCTRL_STATUS_DFLLRDY_Pos    = 0x8       // Position of DFLLRDY field.
	OSCCTRL_STATUS_DFLLRDY_Msk    = 0x100     // Bit mask of DFLLRDY field.
	OSCCTRL_STATUS_DFLLRDY        = 0x100     // Bit DFLLRDY.
	OSCCTRL_STATUS_DFLLOOB_Pos    = 0x9       // Position of DFLLOOB field.
	OSCCTRL_STATUS_DFLLOOB_Msk    = 0x200     // Bit mask of DFLLOOB field.
	OSCCTRL_STATUS_DFLLOOB        = 0x200     // Bit DFLLOOB.
	OSCCTRL_STATUS_DFLLLCKF_Pos   = 0xa       // Position of DFLLLCKF field.
	OSCCTRL_STATUS_DFLLLCKF_Msk   = 0x400     // Bit mask of DFLLLCKF field.
	OSCCTRL_STATUS_DFLLLCKF       = 0x400     // Bit DFLLLCKF.
	OSCCTRL_STATUS_DFLLLCKC_Pos   = 0xb       // Position of DFLLLCKC field.
	OSCCTRL_STATUS_DFLLLCKC_Msk   = 0x800     // Bit mask of DFLLLCKC field.
	OSCCTRL_STATUS_DFLLLCKC       = 0x800     // Bit DFLLLCKC.
	OSCCTRL_STATUS_DFLLRCS_Pos    = 0xc       // Position of DFLLRCS field.
	OSCCTRL_STATUS_DFLLRCS_Msk    = 0x1000    // Bit mask of DFLLRCS field.
	OSCCTRL_STATUS_DFLLRCS        = 0x1000    // Bit DFLLRCS.
	OSCCTRL_STATUS_DPLL0LCKR_Pos  = 0x10      // Position of DPLL0LCKR field.
	OSCCTRL_STATUS_DPLL0LCKR_Msk  = 0x10000   // Bit mask of DPLL0LCKR field.
	OSCCTRL_STATUS_DPLL0LCKR      = 0x10000   // Bit DPLL0LCKR.
	OSCCTRL_STATUS_DPLL0LCKF_Pos  = 0x11      // Position of DPLL0LCKF field.
	OSCCTRL_STATUS_DPLL0LCKF_Msk  = 0x20000   // Bit mask of DPLL0LCKF field.
	OSCCTRL_STATUS_DPLL0LCKF      = 0x20000   // Bit DPLL0LCKF.
	OSCCTRL_STATUS_DPLL0TO_Pos    = 0x12      // Position of DPLL0TO field.
	OSCCTRL_STATUS_DPLL0TO_Msk    = 0x40000   // Bit mask of DPLL0TO field.
	OSCCTRL_STATUS_DPLL0TO        = 0x40000   // Bit DPLL0TO.
	OSCCTRL_STATUS_DPLL0LDRTO_Pos = 0x13      // Position of DPLL0LDRTO field.
	OSCCTRL_STATUS_DPLL0LDRTO_Msk = 0x80000   // Bit mask of DPLL0LDRTO field.
	OSCCTRL_STATUS_DPLL0LDRTO     = 0x80000   // Bit DPLL0LDRTO.
	OSCCTRL_STATUS_DPLL1LCKR_Pos  = 0x18      // Position of DPLL1LCKR field.
	OSCCTRL_STATUS_DPLL1LCKR_Msk  = 0x1000000 // Bit mask of DPLL1LCKR field.
	OSCCTRL_STATUS_DPLL1LCKR      = 0x1000000 // Bit DPLL1LCKR.
	OSCCTRL_STATUS_DPLL1LCKF_Pos  = 0x19      // Position of DPLL1LCKF field.
	OSCCTRL_STATUS_DPLL1LCKF_Msk  = 0x2000000 // Bit mask of DPLL1LCKF field.
	OSCCTRL_STATUS_DPLL1LCKF      = 0x2000000 // Bit DPLL1LCKF.
	OSCCTRL_STATUS_DPLL1TO_Pos    = 0x1a      // Position of DPLL1TO field.
	OSCCTRL_STATUS_DPLL1TO_Msk    = 0x4000000 // Bit mask of DPLL1TO field.
	OSCCTRL_STATUS_DPLL1TO        = 0x4000000 // Bit DPLL1TO.
	OSCCTRL_STATUS_DPLL1LDRTO_Pos = 0x1b      // Position of DPLL1LDRTO field.
	OSCCTRL_STATUS_DPLL1LDRTO_Msk = 0x8000000 // Bit mask of DPLL1LDRTO field.
	OSCCTRL_STATUS_DPLL1LDRTO     = 0x8000000 // Bit DPLL1LDRTO.

	// XOSCCTRL: External Multipurpose Crystal Oscillator Control
	OSCCTRL_XOSCCTRL_ENABLE_Pos         = 0x1       // Position of ENABLE field.
	OSCCTRL_XOSCCTRL_ENABLE_Msk         = 0x2       // Bit mask of ENABLE field.
	OSCCTRL_XOSCCTRL_ENABLE             = 0x2       // Bit ENABLE.
	OSCCTRL_XOSCCTRL_XTALEN_Pos         = 0x2       // Position of XTALEN field.
	OSCCTRL_XOSCCTRL_XTALEN_Msk         = 0x4       // Bit mask of XTALEN field.
	OSCCTRL_XOSCCTRL_XTALEN             = 0x4       // Bit XTALEN.
	OSCCTRL_XOSCCTRL_RUNSTDBY_Pos       = 0x6       // Position of RUNSTDBY field.
	OSCCTRL_XOSCCTRL_RUNSTDBY_Msk       = 0x40      // Bit mask of RUNSTDBY field.
	OSCCTRL_XOSCCTRL_RUNSTDBY           = 0x40      // Bit RUNSTDBY.
	OSCCTRL_XOSCCTRL_ONDEMAND_Pos       = 0x7       // Position of ONDEMAND field.
	OSCCTRL_XOSCCTRL_ONDEMAND_Msk       = 0x80      // Bit mask of ONDEMAND field.
	OSCCTRL_XOSCCTRL_ONDEMAND           = 0x80      // Bit ONDEMAND.
	OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos     = 0x8       // Position of LOWBUFGAIN field.
	OSCCTRL_XOSCCTRL_LOWBUFGAIN_Msk     = 0x100     // Bit mask of LOWBUFGAIN field.
	OSCCTRL_XOSCCTRL_LOWBUFGAIN         = 0x100     // Bit LOWBUFGAIN.
	OSCCTRL_XOSCCTRL_IPTAT_Pos          = 0x9       // Position of IPTAT field.
	OSCCTRL_XOSCCTRL_IPTAT_Msk          = 0x600     // Bit mask of IPTAT field.
	OSCCTRL_XOSCCTRL_IMULT_Pos          = 0xb       // Position of IMULT field.
	OSCCTRL_XOSCCTRL_IMULT_Msk          = 0x7800    // Bit mask of IMULT field.
	OSCCTRL_XOSCCTRL_ENALC_Pos          = 0xf       // Position of ENALC field.
	OSCCTRL_XOSCCTRL_ENALC_Msk          = 0x8000    // Bit mask of ENALC field.
	OSCCTRL_XOSCCTRL_ENALC              = 0x8000    // Bit ENALC.
	OSCCTRL_XOSCCTRL_CFDEN_Pos          = 0x10      // Position of CFDEN field.
	OSCCTRL_XOSCCTRL_CFDEN_Msk          = 0x10000   // Bit mask of CFDEN field.
	OSCCTRL_XOSCCTRL_CFDEN              = 0x10000   // Bit CFDEN.
	OSCCTRL_XOSCCTRL_SWBEN_Pos          = 0x11      // Position of SWBEN field.
	OSCCTRL_XOSCCTRL_SWBEN_Msk          = 0x20000   // Bit mask of SWBEN field.
	OSCCTRL_XOSCCTRL_SWBEN              = 0x20000   // Bit SWBEN.
	OSCCTRL_XOSCCTRL_STARTUP_Pos        = 0x14      // Position of STARTUP field.
	OSCCTRL_XOSCCTRL_STARTUP_Msk        = 0xf00000  // Bit mask of STARTUP field.
	OSCCTRL_XOSCCTRL_STARTUP_CYCLE1     = 0x0       // 31 us
	OSCCTRL_XOSCCTRL_STARTUP_CYCLE2     = 0x1       // 61 us
	OSCCTRL_XOSCCTRL_STARTUP_CYCLE4     = 0x2       // 122 us
	OSCCTRL_XOSCCTRL_STARTUP_CYCLE8     = 0x3       // 244 us
	OSCCTRL_XOSCCTRL_STARTUP_CYCLE16    = 0x4       // 488 us
	OSCCTRL_XOSCCTRL_STARTUP_CYCLE32    = 0x5       // 977 us
	OSCCTRL_XOSCCTRL_STARTUP_CYCLE64    = 0x6       // 1953 us
	OSCCTRL_XOSCCTRL_STARTUP_CYCLE128   = 0x7       // 3906 us
	OSCCTRL_XOSCCTRL_STARTUP_CYCLE256   = 0x8       // 7813 us
	OSCCTRL_XOSCCTRL_STARTUP_CYCLE512   = 0x9       // 15625 us
	OSCCTRL_XOSCCTRL_STARTUP_CYCLE1024  = 0xa       // 31250 us
	OSCCTRL_XOSCCTRL_STARTUP_CYCLE2048  = 0xb       // 62500 us
	OSCCTRL_XOSCCTRL_STARTUP_CYCLE4096  = 0xc       // 125000 us
	OSCCTRL_XOSCCTRL_STARTUP_CYCLE8192  = 0xd       // 250000 us
	OSCCTRL_XOSCCTRL_STARTUP_CYCLE16384 = 0xe       // 500000 us
	OSCCTRL_XOSCCTRL_STARTUP_CYCLE32768 = 0xf       // 1000000 us
	OSCCTRL_XOSCCTRL_CFDPRESC_Pos       = 0x18      // Position of CFDPRESC field.
	OSCCTRL_XOSCCTRL_CFDPRESC_Msk       = 0xf000000 // Bit mask of CFDPRESC field.
	OSCCTRL_XOSCCTRL_CFDPRESC_DIV1      = 0x0       // 48 MHz
	OSCCTRL_XOSCCTRL_CFDPRESC_DIV2      = 0x1       // 24 MHz
	OSCCTRL_XOSCCTRL_CFDPRESC_DIV4      = 0x2       // 12 MHz
	OSCCTRL_XOSCCTRL_CFDPRESC_DIV8      = 0x3       // 6 MHz
	OSCCTRL_XOSCCTRL_CFDPRESC_DIV16     = 0x4       // 3 MHz
	OSCCTRL_XOSCCTRL_CFDPRESC_DIV32     = 0x5       // 1.5 MHz
	OSCCTRL_XOSCCTRL_CFDPRESC_DIV64     = 0x6       // 0.75 MHz
	OSCCTRL_XOSCCTRL_CFDPRESC_DIV128    = 0x7       // 0.3125 MHz

	// DFLLCTRLA: DFLL48M Control A
	OSCCTRL_DFLLCTRLA_ENABLE_Pos   = 0x1  // Position of ENABLE field.
	OSCCTRL_DFLLCTRLA_ENABLE_Msk   = 0x2  // Bit mask of ENABLE field.
	OSCCTRL_DFLLCTRLA_ENABLE       = 0x2  // Bit ENABLE.
	OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos = 0x6  // Position of RUNSTDBY field.
	OSCCTRL_DFLLCTRLA_RUNSTDBY_Msk = 0x40 // Bit mask of RUNSTDBY field.
	OSCCTRL_DFLLCTRLA_RUNSTDBY     = 0x40 // Bit RUNSTDBY.
	OSCCTRL_DFLLCTRLA_ONDEMAND_Pos = 0x7  // Position of ONDEMAND field.
	OSCCTRL_DFLLCTRLA_ONDEMAND_Msk = 0x80 // Bit mask of ONDEMAND field.
	OSCCTRL_DFLLCTRLA_ONDEMAND     = 0x80 // Bit ONDEMAND.

	// DFLLCTRLB: DFLL48M Control B
	OSCCTRL_DFLLCTRLB_MODE_Pos     = 0x0  // Position of MODE field.
	OSCCTRL_DFLLCTRLB_MODE_Msk     = 0x1  // Bit mask of MODE field.
	OSCCTRL_DFLLCTRLB_MODE         = 0x1  // Bit MODE.
	OSCCTRL_DFLLCTRLB_STABLE_Pos   = 0x1  // Position of STABLE field.
	OSCCTRL_DFLLCTRLB_STABLE_Msk   = 0x2  // Bit mask of STABLE field.
	OSCCTRL_DFLLCTRLB_STABLE       = 0x2  // Bit STABLE.
	OSCCTRL_DFLLCTRLB_LLAW_Pos     = 0x2  // Position of LLAW field.
	OSCCTRL_DFLLCTRLB_LLAW_Msk     = 0x4  // Bit mask of LLAW field.
	OSCCTRL_DFLLCTRLB_LLAW         = 0x4  // Bit LLAW.
	OSCCTRL_DFLLCTRLB_USBCRM_Pos   = 0x3  // Position of USBCRM field.
	OSCCTRL_DFLLCTRLB_USBCRM_Msk   = 0x8  // Bit mask of USBCRM field.
	OSCCTRL_DFLLCTRLB_USBCRM       = 0x8  // Bit USBCRM.
	OSCCTRL_DFLLCTRLB_CCDIS_Pos    = 0x4  // Position of CCDIS field.
	OSCCTRL_DFLLCTRLB_CCDIS_Msk    = 0x10 // Bit mask of CCDIS field.
	OSCCTRL_DFLLCTRLB_CCDIS        = 0x10 // Bit CCDIS.
	OSCCTRL_DFLLCTRLB_QLDIS_Pos    = 0x5  // Position of QLDIS field.
	OSCCTRL_DFLLCTRLB_QLDIS_Msk    = 0x20 // Bit mask of QLDIS field.
	OSCCTRL_DFLLCTRLB_QLDIS        = 0x20 // Bit QLDIS.
	OSCCTRL_DFLLCTRLB_BPLCKC_Pos   = 0x6  // Position of BPLCKC field.
	OSCCTRL_DFLLCTRLB_BPLCKC_Msk   = 0x40 // Bit mask of BPLCKC field.
	OSCCTRL_DFLLCTRLB_BPLCKC       = 0x40 // Bit BPLCKC.
	OSCCTRL_DFLLCTRLB_WAITLOCK_Pos = 0x7  // Position of WAITLOCK field.
	OSCCTRL_DFLLCTRLB_WAITLOCK_Msk = 0x80 // Bit mask of WAITLOCK field.
	OSCCTRL_DFLLCTRLB_WAITLOCK     = 0x80 // Bit WAITLOCK.

	// DFLLVAL: DFLL48M Value
	OSCCTRL_DFLLVAL_FINE_Pos   = 0x0        // Position of FINE field.
	OSCCTRL_DFLLVAL_FINE_Msk   = 0xff       // Bit mask of FINE field.
	OSCCTRL_DFLLVAL_COARSE_Pos = 0xa        // Position of COARSE field.
	OSCCTRL_DFLLVAL_COARSE_Msk = 0xfc00     // Bit mask of COARSE field.
	OSCCTRL_DFLLVAL_DIFF_Pos   = 0x10       // Position of DIFF field.
	OSCCTRL_DFLLVAL_DIFF_Msk   = 0xffff0000 // Bit mask of DIFF field.

	// DFLLMUL: DFLL48M Multiplier
	OSCCTRL_DFLLMUL_MUL_Pos   = 0x0        // Position of MUL field.
	OSCCTRL_DFLLMUL_MUL_Msk   = 0xffff     // Bit mask of MUL field.
	OSCCTRL_DFLLMUL_FSTEP_Pos = 0x10       // Position of FSTEP field.
	OSCCTRL_DFLLMUL_FSTEP_Msk = 0xff0000   // Bit mask of FSTEP field.
	OSCCTRL_DFLLMUL_CSTEP_Pos = 0x1a       // Position of CSTEP field.
	OSCCTRL_DFLLMUL_CSTEP_Msk = 0xfc000000 // Bit mask of CSTEP field.

	// DFLLSYNC: DFLL48M Synchronization
	OSCCTRL_DFLLSYNC_ENABLE_Pos    = 0x1  // Position of ENABLE field.
	OSCCTRL_DFLLSYNC_ENABLE_Msk    = 0x2  // Bit mask of ENABLE field.
	OSCCTRL_DFLLSYNC_ENABLE        = 0x2  // Bit ENABLE.
	OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos = 0x2  // Position of DFLLCTRLB field.
	OSCCTRL_DFLLSYNC_DFLLCTRLB_Msk = 0x4  // Bit mask of DFLLCTRLB field.
	OSCCTRL_DFLLSYNC_DFLLCTRLB     = 0x4  // Bit DFLLCTRLB.
	OSCCTRL_DFLLSYNC_DFLLVAL_Pos   = 0x3  // Position of DFLLVAL field.
	OSCCTRL_DFLLSYNC_DFLLVAL_Msk   = 0x8  // Bit mask of DFLLVAL field.
	OSCCTRL_DFLLSYNC_DFLLVAL       = 0x8  // Bit DFLLVAL.
	OSCCTRL_DFLLSYNC_DFLLMUL_Pos   = 0x4  // Position of DFLLMUL field.
	OSCCTRL_DFLLSYNC_DFLLMUL_Msk   = 0x10 // Bit mask of DFLLMUL field.
	OSCCTRL_DFLLSYNC_DFLLMUL       = 0x10 // Bit DFLLMUL.

	// DPLL.DPLLCTRLA: DPLL Control A
	OSCCTRL_DPLL_DPLLCTRLA_ENABLE_Pos   = 0x1  // Position of ENABLE field.
	OSCCTRL_DPLL_DPLLCTRLA_ENABLE_Msk   = 0x2  // Bit mask of ENABLE field.
	OSCCTRL_DPLL_DPLLCTRLA_ENABLE       = 0x2  // Bit ENABLE.
	OSCCTRL_DPLL_DPLLCTRLA_RUNSTDBY_Pos = 0x6  // Position of RUNSTDBY field.
	OSCCTRL_DPLL_DPLLCTRLA_RUNSTDBY_Msk = 0x40 // Bit mask of RUNSTDBY field.
	OSCCTRL_DPLL_DPLLCTRLA_RUNSTDBY     = 0x40 // Bit RUNSTDBY.
	OSCCTRL_DPLL_DPLLCTRLA_ONDEMAND_Pos = 0x7  // Position of ONDEMAND field.
	OSCCTRL_DPLL_DPLLCTRLA_ONDEMAND_Msk = 0x80 // Bit mask of ONDEMAND field.
	OSCCTRL_DPLL_DPLLCTRLA_ONDEMAND     = 0x80 // Bit ONDEMAND.

	// DPLL.DPLLRATIO: DPLL Ratio Control
	OSCCTRL_DPLL_DPLLRATIO_LDR_Pos     = 0x0      // Position of LDR field.
	OSCCTRL_DPLL_DPLLRATIO_LDR_Msk     = 0x1fff   // Bit mask of LDR field.
	OSCCTRL_DPLL_DPLLRATIO_LDRFRAC_Pos = 0x10     // Position of LDRFRAC field.
	OSCCTRL_DPLL_DPLLRATIO_LDRFRAC_Msk = 0x1f0000 // Bit mask of LDRFRAC field.

	// DPLL.DPLLCTRLB: DPLL Control B
	OSCCTRL_DPLL_DPLLCTRLB_FILTER_Pos        = 0x0       // Position of FILTER field.
	OSCCTRL_DPLL_DPLLCTRLB_FILTER_Msk        = 0xf       // Bit mask of FILTER field.
	OSCCTRL_DPLL_DPLLCTRLB_FILTER_FILTER1    = 0x0       // Bandwidth = 92.7Khz and Damping Factor = 0.76
	OSCCTRL_DPLL_DPLLCTRLB_FILTER_FILTER2    = 0x1       // Bandwidth = 131Khz and Damping Factor = 1.08
	OSCCTRL_DPLL_DPLLCTRLB_FILTER_FILTER3    = 0x2       // Bandwidth = 46.4Khz and Damping Factor = 0.38
	OSCCTRL_DPLL_DPLLCTRLB_FILTER_FILTER4    = 0x3       // Bandwidth = 65.6Khz and Damping Factor = 0.54
	OSCCTRL_DPLL_DPLLCTRLB_FILTER_FILTER5    = 0x4       // Bandwidth = 131Khz and Damping Factor = 0.56
	OSCCTRL_DPLL_DPLLCTRLB_FILTER_FILTER6    = 0x5       // Bandwidth = 185Khz and Damping Factor = 0.79
	OSCCTRL_DPLL_DPLLCTRLB_FILTER_FILTER7    = 0x6       // Bandwidth = 65.6Khz and Damping Factor = 0.28
	OSCCTRL_DPLL_DPLLCTRLB_FILTER_FILTER8    = 0x7       // Bandwidth = 92.7Khz and Damping Factor = 0.39
	OSCCTRL_DPLL_DPLLCTRLB_FILTER_FILTER9    = 0x8       // Bandwidth = 46.4Khz and Damping Factor = 1.49
	OSCCTRL_DPLL_DPLLCTRLB_FILTER_FILTER10   = 0x9       // Bandwidth = 65.6Khz and Damping Factor = 2.11
	OSCCTRL_DPLL_DPLLCTRLB_FILTER_FILTER11   = 0xa       // Bandwidth = 23.2Khz and Damping Factor = 0.75
	OSCCTRL_DPLL_DPLLCTRLB_FILTER_FILTER12   = 0xb       // Bandwidth = 32.8Khz and Damping Factor = 1.06
	OSCCTRL_DPLL_DPLLCTRLB_FILTER_FILTER13   = 0xc       // Bandwidth = 65.6Khz and Damping Factor = 1.07
	OSCCTRL_DPLL_DPLLCTRLB_FILTER_FILTER14   = 0xd       // Bandwidth = 92.7Khz and Damping Factor = 1.51
	OSCCTRL_DPLL_DPLLCTRLB_FILTER_FILTER15   = 0xe       // Bandwidth = 32.8Khz and Damping Factor = 0.53
	OSCCTRL_DPLL_DPLLCTRLB_FILTER_FILTER16   = 0xf       // Bandwidth = 46.4Khz and Damping Factor = 0.75
	OSCCTRL_DPLL_DPLLCTRLB_WUF_Pos           = 0x4       // Position of WUF field.
	OSCCTRL_DPLL_DPLLCTRLB_WUF_Msk           = 0x10      // Bit mask of WUF field.
	OSCCTRL_DPLL_DPLLCTRLB_WUF               = 0x10      // Bit WUF.
	OSCCTRL_DPLL_DPLLCTRLB_REFCLK_Pos        = 0x5       // Position of REFCLK field.
	OSCCTRL_DPLL_DPLLCTRLB_REFCLK_Msk        = 0xe0      // Bit mask of REFCLK field.
	OSCCTRL_DPLL_DPLLCTRLB_REFCLK_GCLK       = 0x0       // Dedicated GCLK clock reference
	OSCCTRL_DPLL_DPLLCTRLB_REFCLK_XOSC32     = 0x1       // XOSC32K clock reference
	OSCCTRL_DPLL_DPLLCTRLB_REFCLK_XOSC0      = 0x2       // XOSC0 clock reference
	OSCCTRL_DPLL_DPLLCTRLB_REFCLK_XOSC1      = 0x3       // XOSC1 clock reference
	OSCCTRL_DPLL_DPLLCTRLB_LTIME_Pos         = 0x8       // Position of LTIME field.
	OSCCTRL_DPLL_DPLLCTRLB_LTIME_Msk         = 0x700     // Bit mask of LTIME field.
	OSCCTRL_DPLL_DPLLCTRLB_LTIME_DEFAULT     = 0x0       // No time-out. Automatic lock
	OSCCTRL_DPLL_DPLLCTRLB_LTIME_800US       = 0x4       // Time-out if no lock within 800us
	OSCCTRL_DPLL_DPLLCTRLB_LTIME_900US       = 0x5       // Time-out if no lock within 900us
	OSCCTRL_DPLL_DPLLCTRLB_LTIME_1MS         = 0x6       // Time-out if no lock within 1ms
	OSCCTRL_DPLL_DPLLCTRLB_LTIME_1P1MS       = 0x7       // Time-out if no lock within 1.1ms
	OSCCTRL_DPLL_DPLLCTRLB_LBYPASS_Pos       = 0xb       // Position of LBYPASS field.
	OSCCTRL_DPLL_DPLLCTRLB_LBYPASS_Msk       = 0x800     // Bit mask of LBYPASS field.
	OSCCTRL_DPLL_DPLLCTRLB_LBYPASS           = 0x800     // Bit LBYPASS.
	OSCCTRL_DPLL_DPLLCTRLB_DCOFILTER_Pos     = 0xc       // Position of DCOFILTER field.
	OSCCTRL_DPLL_DPLLCTRLB_DCOFILTER_Msk     = 0x7000    // Bit mask of DCOFILTER field.
	OSCCTRL_DPLL_DPLLCTRLB_DCOFILTER_FILTER1 = 0x0       // Capacitor(pF) = 0.5 and Bandwidth Fn (MHz) = 3.21
	OSCCTRL_DPLL_DPLLCTRLB_DCOFILTER_FILTER2 = 0x1       // Capacitor(pF) = 1 and Bandwidth Fn (MHz) = 1.6
	OSCCTRL_DPLL_DPLLCTRLB_DCOFILTER_FILTER3 = 0x2       // Capacitor(pF) = 1.5 and Bandwidth Fn (MHz) = 1.1
	OSCCTRL_DPLL_DPLLCTRLB_DCOFILTER_FILTER4 = 0x3       // Capacitor(pF) = 2 and Bandwidth Fn (MHz) = 0.8
	OSCCTRL_DPLL_DPLLCTRLB_DCOFILTER_FILTER5 = 0x4       // Capacitor(pF) = 2.5 and Bandwidth Fn (MHz) = 0.64
	OSCCTRL_DPLL_DPLLCTRLB_DCOFILTER_FILTER6 = 0x5       // Capacitor(pF) = 3 and Bandwidth Fn (MHz) = 0.55
	OSCCTRL_DPLL_DPLLCTRLB_DCOFILTER_FILTER7 = 0x6       // Capacitor(pF) = 3.5 and Bandwidth Fn (MHz) = 0.45
	OSCCTRL_DPLL_DPLLCTRLB_DCOFILTER_FILTER8 = 0x7       // Capacitor(pF) = 4 and Bandwidth Fn (MHz) = 0.4
	OSCCTRL_DPLL_DPLLCTRLB_DCOEN_Pos         = 0xf       // Position of DCOEN field.
	OSCCTRL_DPLL_DPLLCTRLB_DCOEN_Msk         = 0x8000    // Bit mask of DCOEN field.
	OSCCTRL_DPLL_DPLLCTRLB_DCOEN             = 0x8000    // Bit DCOEN.
	OSCCTRL_DPLL_DPLLCTRLB_DIV_Pos           = 0x10      // Position of DIV field.
	OSCCTRL_DPLL_DPLLCTRLB_DIV_Msk           = 0x7ff0000 // Bit mask of DIV field.

	// DPLL.DPLLSYNCBUSY: DPLL Synchronization Busy
	OSCCTRL_DPLL_DPLLSYNCBUSY_ENABLE_Pos    = 0x1 // Position of ENABLE field.
	OSCCTRL_DPLL_DPLLSYNCBUSY_ENABLE_Msk    = 0x2 // Bit mask of ENABLE field.
	OSCCTRL_DPLL_DPLLSYNCBUSY_ENABLE        = 0x2 // Bit ENABLE.
	OSCCTRL_DPLL_DPLLSYNCBUSY_DPLLRATIO_Pos = 0x2 // Position of DPLLRATIO field.
	OSCCTRL_DPLL_DPLLSYNCBUSY_DPLLRATIO_Msk = 0x4 // Bit mask of DPLLRATIO field.
	OSCCTRL_DPLL_DPLLSYNCBUSY_DPLLRATIO     = 0x4 // Bit DPLLRATIO.

	// DPLL.DPLLSTATUS: DPLL Status
	OSCCTRL_DPLL_DPLLSTATUS_LOCK_Pos   = 0x0 // Position of LOCK field.
	OSCCTRL_DPLL_DPLLSTATUS_LOCK_Msk   = 0x1 // Bit mask of LOCK field.
	OSCCTRL_DPLL_DPLLSTATUS_LOCK       = 0x1 // Bit LOCK.
	OSCCTRL_DPLL_DPLLSTATUS_CLKRDY_Pos = 0x1 // Position of CLKRDY field.
	OSCCTRL_DPLL_DPLLSTATUS_CLKRDY_Msk = 0x2 // Bit mask of CLKRDY field.
	OSCCTRL_DPLL_DPLLSTATUS_CLKRDY     = 0x2 // Bit CLKRDY.
)

// Bitfields for OSC32KCTRL: 32kHz Oscillators Control
const (
	// INTENCLR: Interrupt Enable Clear
	OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos  = 0x0 // Position of XOSC32KRDY field.
	OSC32KCTRL_INTENCLR_XOSC32KRDY_Msk  = 0x1 // Bit mask of XOSC32KRDY field.
	OSC32KCTRL_INTENCLR_XOSC32KRDY      = 0x1 // Bit XOSC32KRDY.
	OSC32KCTRL_INTENCLR_XOSC32KFAIL_Pos = 0x2 // Position of XOSC32KFAIL field.
	OSC32KCTRL_INTENCLR_XOSC32KFAIL_Msk = 0x4 // Bit mask of XOSC32KFAIL field.
	OSC32KCTRL_INTENCLR_XOSC32KFAIL     = 0x4 // Bit XOSC32KFAIL.

	// INTENSET: Interrupt Enable Set
	OSC32KCTRL_INTENSET_XOSC32KRDY_Pos  = 0x0 // Position of XOSC32KRDY field.
	OSC32KCTRL_INTENSET_XOSC32KRDY_Msk  = 0x1 // Bit mask of XOSC32KRDY field.
	OSC32KCTRL_INTENSET_XOSC32KRDY      = 0x1 // Bit XOSC32KRDY.
	OSC32KCTRL_INTENSET_XOSC32KFAIL_Pos = 0x2 // Position of XOSC32KFAIL field.
	OSC32KCTRL_INTENSET_XOSC32KFAIL_Msk = 0x4 // Bit mask of XOSC32KFAIL field.
	OSC32KCTRL_INTENSET_XOSC32KFAIL     = 0x4 // Bit XOSC32KFAIL.

	// INTFLAG: Interrupt Flag Status and Clear
	OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos  = 0x0 // Position of XOSC32KRDY field.
	OSC32KCTRL_INTFLAG_XOSC32KRDY_Msk  = 0x1 // Bit mask of XOSC32KRDY field.
	OSC32KCTRL_INTFLAG_XOSC32KRDY      = 0x1 // Bit XOSC32KRDY.
	OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos = 0x2 // Position of XOSC32KFAIL field.
	OSC32KCTRL_INTFLAG_XOSC32KFAIL_Msk = 0x4 // Bit mask of XOSC32KFAIL field.
	OSC32KCTRL_INTFLAG_XOSC32KFAIL     = 0x4 // Bit XOSC32KFAIL.

	// STATUS: Power and Clocks Status
	OSC32KCTRL_STATUS_XOSC32KRDY_Pos  = 0x0 // Position of XOSC32KRDY field.
	OSC32KCTRL_STATUS_XOSC32KRDY_Msk  = 0x1 // Bit mask of XOSC32KRDY field.
	OSC32KCTRL_STATUS_XOSC32KRDY      = 0x1 // Bit XOSC32KRDY.
	OSC32KCTRL_STATUS_XOSC32KFAIL_Pos = 0x2 // Position of XOSC32KFAIL field.
	OSC32KCTRL_STATUS_XOSC32KFAIL_Msk = 0x4 // Bit mask of XOSC32KFAIL field.
	OSC32KCTRL_STATUS_XOSC32KFAIL     = 0x4 // Bit XOSC32KFAIL.
	OSC32KCTRL_STATUS_XOSC32KSW_Pos   = 0x3 // Position of XOSC32KSW field.
	OSC32KCTRL_STATUS_XOSC32KSW_Msk   = 0x8 // Bit mask of XOSC32KSW field.
	OSC32KCTRL_STATUS_XOSC32KSW       = 0x8 // Bit XOSC32KSW.

	// RTCCTRL: RTC Clock Selection
	OSC32KCTRL_RTCCTRL_RTCSEL_Pos     = 0x0 // Position of RTCSEL field.
	OSC32KCTRL_RTCCTRL_RTCSEL_Msk     = 0x7 // Bit mask of RTCSEL field.
	OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K   = 0x0 // 1.024kHz from 32kHz internal ULP oscillator
	OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K  = 0x1 // 32.768kHz from 32kHz internal ULP oscillator
	OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K  = 0x4 // 1.024kHz from 32.768kHz internal oscillator
	OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K = 0x5 // 32.768kHz from 32.768kHz external crystal oscillator

	// XOSC32K: 32kHz External Crystal Oscillator (XOSC32K) Control
	OSC32KCTRL_XOSC32K_ENABLE_Pos          = 0x1    // Position of ENABLE field.
	OSC32KCTRL_XOSC32K_ENABLE_Msk          = 0x2    // Bit mask of ENABLE field.
	OSC32KCTRL_XOSC32K_ENABLE              = 0x2    // Bit ENABLE.
	OSC32KCTRL_XOSC32K_XTALEN_Pos          = 0x2    // Position of XTALEN field.
	OSC32KCTRL_XOSC32K_XTALEN_Msk          = 0x4    // Bit mask of XTALEN field.
	OSC32KCTRL_XOSC32K_XTALEN              = 0x4    // Bit XTALEN.
	OSC32KCTRL_XOSC32K_EN32K_Pos           = 0x3    // Position of EN32K field.
	OSC32KCTRL_XOSC32K_EN32K_Msk           = 0x8    // Bit mask of EN32K field.
	OSC32KCTRL_XOSC32K_EN32K               = 0x8    // Bit EN32K.
	OSC32KCTRL_XOSC32K_EN1K_Pos            = 0x4    // Position of EN1K field.
	OSC32KCTRL_XOSC32K_EN1K_Msk            = 0x10   // Bit mask of EN1K field.
	OSC32KCTRL_XOSC32K_EN1K                = 0x10   // Bit EN1K.
	OSC32KCTRL_XOSC32K_RUNSTDBY_Pos        = 0x6    // Position of RUNSTDBY field.
	OSC32KCTRL_XOSC32K_RUNSTDBY_Msk        = 0x40   // Bit mask of RUNSTDBY field.
	OSC32KCTRL_XOSC32K_RUNSTDBY            = 0x40   // Bit RUNSTDBY.
	OSC32KCTRL_XOSC32K_ONDEMAND_Pos        = 0x7    // Position of ONDEMAND field.
	OSC32KCTRL_XOSC32K_ONDEMAND_Msk        = 0x80   // Bit mask of ONDEMAND field.
	OSC32KCTRL_XOSC32K_ONDEMAND            = 0x80   // Bit ONDEMAND.
	OSC32KCTRL_XOSC32K_STARTUP_Pos         = 0x8    // Position of STARTUP field.
	OSC32KCTRL_XOSC32K_STARTUP_Msk         = 0x700  // Bit mask of STARTUP field.
	OSC32KCTRL_XOSC32K_STARTUP_CYCLE2048   = 0x0    // 62.6 ms
	OSC32KCTRL_XOSC32K_STARTUP_CYCLE4096   = 0x1    // 125 ms
	OSC32KCTRL_XOSC32K_STARTUP_CYCLE16384  = 0x2    // 500 ms
	OSC32KCTRL_XOSC32K_STARTUP_CYCLE32768  = 0x3    // 1000 ms
	OSC32KCTRL_XOSC32K_STARTUP_CYCLE65536  = 0x4    // 2000 ms
	OSC32KCTRL_XOSC32K_STARTUP_CYCLE131072 = 0x5    // 4000 ms
	OSC32KCTRL_XOSC32K_STARTUP_CYCLE262144 = 0x6    // 8000 ms
	OSC32KCTRL_XOSC32K_WRTLOCK_Pos         = 0xc    // Position of WRTLOCK field.
	OSC32KCTRL_XOSC32K_WRTLOCK_Msk         = 0x1000 // Bit mask of WRTLOCK field.
	OSC32KCTRL_XOSC32K_WRTLOCK             = 0x1000 // Bit WRTLOCK.
	OSC32KCTRL_XOSC32K_CGM_Pos             = 0xd    // Position of CGM field.
	OSC32KCTRL_XOSC32K_CGM_Msk             = 0x6000 // Bit mask of CGM field.
	OSC32KCTRL_XOSC32K_CGM_XT              = 0x1    // Standard mode
	OSC32KCTRL_XOSC32K_CGM_HS              = 0x2    // High Speed mode

	// CFDCTRL: Clock Failure Detector Control
	OSC32KCTRL_CFDCTRL_CFDEN_Pos    = 0x0 // Position of CFDEN field.
	OSC32KCTRL_CFDCTRL_CFDEN_Msk    = 0x1 // Bit mask of CFDEN field.
	OSC32KCTRL_CFDCTRL_CFDEN        = 0x1 // Bit CFDEN.
	OSC32KCTRL_CFDCTRL_SWBACK_Pos   = 0x1 // Position of SWBACK field.
	OSC32KCTRL_CFDCTRL_SWBACK_Msk   = 0x2 // Bit mask of SWBACK field.
	OSC32KCTRL_CFDCTRL_SWBACK       = 0x2 // Bit SWBACK.
	OSC32KCTRL_CFDCTRL_CFDPRESC_Pos = 0x2 // Position of CFDPRESC field.
	OSC32KCTRL_CFDCTRL_CFDPRESC_Msk = 0x4 // Bit mask of CFDPRESC field.
	OSC32KCTRL_CFDCTRL_CFDPRESC     = 0x4 // Bit CFDPRESC.

	// EVCTRL: Event Control
	OSC32KCTRL_EVCTRL_CFDEO_Pos = 0x0 // Position of CFDEO field.
	OSC32KCTRL_EVCTRL_CFDEO_Msk = 0x1 // Bit mask of CFDEO field.
	OSC32KCTRL_EVCTRL_CFDEO     = 0x1 // Bit CFDEO.

	// OSCULP32K: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control
	OSC32KCTRL_OSCULP32K_EN32K_Pos   = 0x1    // Position of EN32K field.
	OSC32KCTRL_OSCULP32K_EN32K_Msk   = 0x2    // Bit mask of EN32K field.
	OSC32KCTRL_OSCULP32K_EN32K       = 0x2    // Bit EN32K.
	OSC32KCTRL_OSCULP32K_EN1K_Pos    = 0x2    // Position of EN1K field.
	OSC32KCTRL_OSCULP32K_EN1K_Msk    = 0x4    // Bit mask of EN1K field.
	OSC32KCTRL_OSCULP32K_EN1K        = 0x4    // Bit EN1K.
	OSC32KCTRL_OSCULP32K_CALIB_Pos   = 0x8    // Position of CALIB field.
	OSC32KCTRL_OSCULP32K_CALIB_Msk   = 0x3f00 // Bit mask of CALIB field.
	OSC32KCTRL_OSCULP32K_WRTLOCK_Pos = 0xf    // Position of WRTLOCK field.
	OSC32KCTRL_OSCULP32K_WRTLOCK_Msk = 0x8000 // Bit mask of WRTLOCK field.
	OSC32KCTRL_OSCULP32K_WRTLOCK     = 0x8000 // Bit WRTLOCK.
)

// Bitfields for PAC: Peripheral Access Controller
const (
	// WRCTRL: Write control
	PAC_WRCTRL_PERID_Pos  = 0x0      // Position of PERID field.
	PAC_WRCTRL_PERID_Msk  = 0xffff   // Bit mask of PERID field.
	PAC_WRCTRL_KEY_Pos    = 0x10     // Position of KEY field.
	PAC_WRCTRL_KEY_Msk    = 0xff0000 // Bit mask of KEY field.
	PAC_WRCTRL_KEY_OFF    = 0x0      // No action
	PAC_WRCTRL_KEY_CLR    = 0x1      // Clear protection
	PAC_WRCTRL_KEY_SET    = 0x2      // Set protection
	PAC_WRCTRL_KEY_SETLCK = 0x3      // Set and lock protection

	// EVCTRL: Event control
	PAC_EVCTRL_ERREO_Pos = 0x0 // Position of ERREO field.
	PAC_EVCTRL_ERREO_Msk = 0x1 // Bit mask of ERREO field.
	PAC_EVCTRL_ERREO     = 0x1 // Bit ERREO.

	// INTENCLR: Interrupt enable clear
	PAC_INTENCLR_ERR_Pos = 0x0 // Position of ERR field.
	PAC_INTENCLR_ERR_Msk = 0x1 // Bit mask of ERR field.
	PAC_INTENCLR_ERR     = 0x1 // Bit ERR.

	// INTENSET: Interrupt enable set
	PAC_INTENSET_ERR_Pos = 0x0 // Position of ERR field.
	PAC_INTENSET_ERR_Msk = 0x1 // Bit mask of ERR field.
	PAC_INTENSET_ERR     = 0x1 // Bit ERR.

	// INTFLAGAHB: Bridge interrupt flag status
	PAC_INTFLAGAHB_FLASH__Pos      = 0x0    // Position of FLASH_ field.
	PAC_INTFLAGAHB_FLASH__Msk      = 0x1    // Bit mask of FLASH_ field.
	PAC_INTFLAGAHB_FLASH_          = 0x1    // Bit FLASH_.
	PAC_INTFLAGAHB_FLASH_ALT__Pos  = 0x1    // Position of FLASH_ALT_ field.
	PAC_INTFLAGAHB_FLASH_ALT__Msk  = 0x2    // Bit mask of FLASH_ALT_ field.
	PAC_INTFLAGAHB_FLASH_ALT_      = 0x2    // Bit FLASH_ALT_.
	PAC_INTFLAGAHB_SEEPROM__Pos    = 0x2    // Position of SEEPROM_ field.
	PAC_INTFLAGAHB_SEEPROM__Msk    = 0x4    // Bit mask of SEEPROM_ field.
	PAC_INTFLAGAHB_SEEPROM_        = 0x4    // Bit SEEPROM_.
	PAC_INTFLAGAHB_RAMCM4S__Pos    = 0x3    // Position of RAMCM4S_ field.
	PAC_INTFLAGAHB_RAMCM4S__Msk    = 0x8    // Bit mask of RAMCM4S_ field.
	PAC_INTFLAGAHB_RAMCM4S_        = 0x8    // Bit RAMCM4S_.
	PAC_INTFLAGAHB_RAMPPPDSU__Pos  = 0x4    // Position of RAMPPPDSU_ field.
	PAC_INTFLAGAHB_RAMPPPDSU__Msk  = 0x10   // Bit mask of RAMPPPDSU_ field.
	PAC_INTFLAGAHB_RAMPPPDSU_      = 0x10   // Bit RAMPPPDSU_.
	PAC_INTFLAGAHB_RAMDMAWR__Pos   = 0x5    // Position of RAMDMAWR_ field.
	PAC_INTFLAGAHB_RAMDMAWR__Msk   = 0x20   // Bit mask of RAMDMAWR_ field.
	PAC_INTFLAGAHB_RAMDMAWR_       = 0x20   // Bit RAMDMAWR_.
	PAC_INTFLAGAHB_RAMDMACICM__Pos = 0x6    // Position of RAMDMACICM_ field.
	PAC_INTFLAGAHB_RAMDMACICM__Msk = 0x40   // Bit mask of RAMDMACICM_ field.
	PAC_INTFLAGAHB_RAMDMACICM_     = 0x40   // Bit RAMDMACICM_.
	PAC_INTFLAGAHB_HPB0__Pos       = 0x7    // Position of HPB0_ field.
	PAC_INTFLAGAHB_HPB0__Msk       = 0x80   // Bit mask of HPB0_ field.
	PAC_INTFLAGAHB_HPB0_           = 0x80   // Bit HPB0_.
	PAC_INTFLAGAHB_HPB1__Pos       = 0x8    // Position of HPB1_ field.
	PAC_INTFLAGAHB_HPB1__Msk       = 0x100  // Bit mask of HPB1_ field.
	PAC_INTFLAGAHB_HPB1_           = 0x100  // Bit HPB1_.
	PAC_INTFLAGAHB_HPB2__Pos       = 0x9    // Position of HPB2_ field.
	PAC_INTFLAGAHB_HPB2__Msk       = 0x200  // Bit mask of HPB2_ field.
	PAC_INTFLAGAHB_HPB2_           = 0x200  // Bit HPB2_.
	PAC_INTFLAGAHB_HPB3__Pos       = 0xa    // Position of HPB3_ field.
	PAC_INTFLAGAHB_HPB3__Msk       = 0x400  // Bit mask of HPB3_ field.
	PAC_INTFLAGAHB_HPB3_           = 0x400  // Bit HPB3_.
	PAC_INTFLAGAHB_PUKCC__Pos      = 0xb    // Position of PUKCC_ field.
	PAC_INTFLAGAHB_PUKCC__Msk      = 0x800  // Bit mask of PUKCC_ field.
	PAC_INTFLAGAHB_PUKCC_          = 0x800  // Bit PUKCC_.
	PAC_INTFLAGAHB_SDHC0__Pos      = 0xc    // Position of SDHC0_ field.
	PAC_INTFLAGAHB_SDHC0__Msk      = 0x1000 // Bit mask of SDHC0_ field.
	PAC_INTFLAGAHB_SDHC0_          = 0x1000 // Bit SDHC0_.
	PAC_INTFLAGAHB_SDHC1__Pos      = 0xd    // Position of SDHC1_ field.
	PAC_INTFLAGAHB_SDHC1__Msk      = 0x2000 // Bit mask of SDHC1_ field.
	PAC_INTFLAGAHB_SDHC1_          = 0x2000 // Bit SDHC1_.
	PAC_INTFLAGAHB_QSPI__Pos       = 0xe    // Position of QSPI_ field.
	PAC_INTFLAGAHB_QSPI__Msk       = 0x4000 // Bit mask of QSPI_ field.
	PAC_INTFLAGAHB_QSPI_           = 0x4000 // Bit QSPI_.
	PAC_INTFLAGAHB_BKUPRAM__Pos    = 0xf    // Position of BKUPRAM_ field.
	PAC_INTFLAGAHB_BKUPRAM__Msk    = 0x8000 // Bit mask of BKUPRAM_ field.
	PAC_INTFLAGAHB_BKUPRAM_        = 0x8000 // Bit BKUPRAM_.

	// INTFLAGA: Peripheral interrupt flag status - Bridge A
	PAC_INTFLAGA_PAC__Pos        = 0x0    // Position of PAC_ field.
	PAC_INTFLAGA_PAC__Msk        = 0x1    // Bit mask of PAC_ field.
	PAC_INTFLAGA_PAC_            = 0x1    // Bit PAC_.
	PAC_INTFLAGA_PM__Pos         = 0x1    // Position of PM_ field.
	PAC_INTFLAGA_PM__Msk         = 0x2    // Bit mask of PM_ field.
	PAC_INTFLAGA_PM_             = 0x2    // Bit PM_.
	PAC_INTFLAGA_MCLK__Pos       = 0x2    // Position of MCLK_ field.
	PAC_INTFLAGA_MCLK__Msk       = 0x4    // Bit mask of MCLK_ field.
	PAC_INTFLAGA_MCLK_           = 0x4    // Bit MCLK_.
	PAC_INTFLAGA_RSTC__Pos       = 0x3    // Position of RSTC_ field.
	PAC_INTFLAGA_RSTC__Msk       = 0x8    // Bit mask of RSTC_ field.
	PAC_INTFLAGA_RSTC_           = 0x8    // Bit RSTC_.
	PAC_INTFLAGA_OSCCTRL__Pos    = 0x4    // Position of OSCCTRL_ field.
	PAC_INTFLAGA_OSCCTRL__Msk    = 0x10   // Bit mask of OSCCTRL_ field.
	PAC_INTFLAGA_OSCCTRL_        = 0x10   // Bit OSCCTRL_.
	PAC_INTFLAGA_OSC32KCTRL__Pos = 0x5    // Position of OSC32KCTRL_ field.
	PAC_INTFLAGA_OSC32KCTRL__Msk = 0x20   // Bit mask of OSC32KCTRL_ field.
	PAC_INTFLAGA_OSC32KCTRL_     = 0x20   // Bit OSC32KCTRL_.
	PAC_INTFLAGA_SUPC__Pos       = 0x6    // Position of SUPC_ field.
	PAC_INTFLAGA_SUPC__Msk       = 0x40   // Bit mask of SUPC_ field.
	PAC_INTFLAGA_SUPC_           = 0x40   // Bit SUPC_.
	PAC_INTFLAGA_GCLK__Pos       = 0x7    // Position of GCLK_ field.
	PAC_INTFLAGA_GCLK__Msk       = 0x80   // Bit mask of GCLK_ field.
	PAC_INTFLAGA_GCLK_           = 0x80   // Bit GCLK_.
	PAC_INTFLAGA_WDT__Pos        = 0x8    // Position of WDT_ field.
	PAC_INTFLAGA_WDT__Msk        = 0x100  // Bit mask of WDT_ field.
	PAC_INTFLAGA_WDT_            = 0x100  // Bit WDT_.
	PAC_INTFLAGA_RTC__Pos        = 0x9    // Position of RTC_ field.
	PAC_INTFLAGA_RTC__Msk        = 0x200  // Bit mask of RTC_ field.
	PAC_INTFLAGA_RTC_            = 0x200  // Bit RTC_.
	PAC_INTFLAGA_EIC__Pos        = 0xa    // Position of EIC_ field.
	PAC_INTFLAGA_EIC__Msk        = 0x400  // Bit mask of EIC_ field.
	PAC_INTFLAGA_EIC_            = 0x400  // Bit EIC_.
	PAC_INTFLAGA_FREQM__Pos      = 0xb    // Position of FREQM_ field.
	PAC_INTFLAGA_FREQM__Msk      = 0x800  // Bit mask of FREQM_ field.
	PAC_INTFLAGA_FREQM_          = 0x800  // Bit FREQM_.
	PAC_INTFLAGA_SERCOM0__Pos    = 0xc    // Position of SERCOM0_ field.
	PAC_INTFLAGA_SERCOM0__Msk    = 0x1000 // Bit mask of SERCOM0_ field.
	PAC_INTFLAGA_SERCOM0_        = 0x1000 // Bit SERCOM0_.
	PAC_INTFLAGA_SERCOM1__Pos    = 0xd    // Position of SERCOM1_ field.
	PAC_INTFLAGA_SERCOM1__Msk    = 0x2000 // Bit mask of SERCOM1_ field.
	PAC_INTFLAGA_SERCOM1_        = 0x2000 // Bit SERCOM1_.
	PAC_INTFLAGA_TC0__Pos        = 0xe    // Position of TC0_ field.
	PAC_INTFLAGA_TC0__Msk        = 0x4000 // Bit mask of TC0_ field.
	PAC_INTFLAGA_TC0_            = 0x4000 // Bit TC0_.
	PAC_INTFLAGA_TC1__Pos        = 0xf    // Position of TC1_ field.
	PAC_INTFLAGA_TC1__Msk        = 0x8000 // Bit mask of TC1_ field.
	PAC_INTFLAGA_TC1_            = 0x8000 // Bit TC1_.

	// INTFLAGB: Peripheral interrupt flag status - Bridge B
	PAC_INTFLAGB_USB__Pos     = 0x0     // Position of USB_ field.
	PAC_INTFLAGB_USB__Msk     = 0x1     // Bit mask of USB_ field.
	PAC_INTFLAGB_USB_         = 0x1     // Bit USB_.
	PAC_INTFLAGB_DSU__Pos     = 0x1     // Position of DSU_ field.
	PAC_INTFLAGB_DSU__Msk     = 0x2     // Bit mask of DSU_ field.
	PAC_INTFLAGB_DSU_         = 0x2     // Bit DSU_.
	PAC_INTFLAGB_NVMCTRL__Pos = 0x2     // Position of NVMCTRL_ field.
	PAC_INTFLAGB_NVMCTRL__Msk = 0x4     // Bit mask of NVMCTRL_ field.
	PAC_INTFLAGB_NVMCTRL_     = 0x4     // Bit NVMCTRL_.
	PAC_INTFLAGB_CMCC__Pos    = 0x3     // Position of CMCC_ field.
	PAC_INTFLAGB_CMCC__Msk    = 0x8     // Bit mask of CMCC_ field.
	PAC_INTFLAGB_CMCC_        = 0x8     // Bit CMCC_.
	PAC_INTFLAGB_PORT__Pos    = 0x4     // Position of PORT_ field.
	PAC_INTFLAGB_PORT__Msk    = 0x10    // Bit mask of PORT_ field.
	PAC_INTFLAGB_PORT_        = 0x10    // Bit PORT_.
	PAC_INTFLAGB_DMAC__Pos    = 0x5     // Position of DMAC_ field.
	PAC_INTFLAGB_DMAC__Msk    = 0x20    // Bit mask of DMAC_ field.
	PAC_INTFLAGB_DMAC_        = 0x20    // Bit DMAC_.
	PAC_INTFLAGB_HMATRIX__Pos = 0x6     // Position of HMATRIX_ field.
	PAC_INTFLAGB_HMATRIX__Msk = 0x40    // Bit mask of HMATRIX_ field.
	PAC_INTFLAGB_HMATRIX_     = 0x40    // Bit HMATRIX_.
	PAC_INTFLAGB_EVSYS__Pos   = 0x7     // Position of EVSYS_ field.
	PAC_INTFLAGB_EVSYS__Msk   = 0x80    // Bit mask of EVSYS_ field.
	PAC_INTFLAGB_EVSYS_       = 0x80    // Bit EVSYS_.
	PAC_INTFLAGB_SERCOM2__Pos = 0x9     // Position of SERCOM2_ field.
	PAC_INTFLAGB_SERCOM2__Msk = 0x200   // Bit mask of SERCOM2_ field.
	PAC_INTFLAGB_SERCOM2_     = 0x200   // Bit SERCOM2_.
	PAC_INTFLAGB_SERCOM3__Pos = 0xa     // Position of SERCOM3_ field.
	PAC_INTFLAGB_SERCOM3__Msk = 0x400   // Bit mask of SERCOM3_ field.
	PAC_INTFLAGB_SERCOM3_     = 0x400   // Bit SERCOM3_.
	PAC_INTFLAGB_TCC0__Pos    = 0xb     // Position of TCC0_ field.
	PAC_INTFLAGB_TCC0__Msk    = 0x800   // Bit mask of TCC0_ field.
	PAC_INTFLAGB_TCC0_        = 0x800   // Bit TCC0_.
	PAC_INTFLAGB_TCC1__Pos    = 0xc     // Position of TCC1_ field.
	PAC_INTFLAGB_TCC1__Msk    = 0x1000  // Bit mask of TCC1_ field.
	PAC_INTFLAGB_TCC1_        = 0x1000  // Bit TCC1_.
	PAC_INTFLAGB_TC2__Pos     = 0xd     // Position of TC2_ field.
	PAC_INTFLAGB_TC2__Msk     = 0x2000  // Bit mask of TC2_ field.
	PAC_INTFLAGB_TC2_         = 0x2000  // Bit TC2_.
	PAC_INTFLAGB_TC3__Pos     = 0xe     // Position of TC3_ field.
	PAC_INTFLAGB_TC3__Msk     = 0x4000  // Bit mask of TC3_ field.
	PAC_INTFLAGB_TC3_         = 0x4000  // Bit TC3_.
	PAC_INTFLAGB_RAMECC__Pos  = 0x10    // Position of RAMECC_ field.
	PAC_INTFLAGB_RAMECC__Msk  = 0x10000 // Bit mask of RAMECC_ field.
	PAC_INTFLAGB_RAMECC_      = 0x10000 // Bit RAMECC_.

	// INTFLAGC: Peripheral interrupt flag status - Bridge C
	PAC_INTFLAGC_TCC2__Pos  = 0x3    // Position of TCC2_ field.
	PAC_INTFLAGC_TCC2__Msk  = 0x8    // Bit mask of TCC2_ field.
	PAC_INTFLAGC_TCC2_      = 0x8    // Bit TCC2_.
	PAC_INTFLAGC_TCC3__Pos  = 0x4    // Position of TCC3_ field.
	PAC_INTFLAGC_TCC3__Msk  = 0x10   // Bit mask of TCC3_ field.
	PAC_INTFLAGC_TCC3_      = 0x10   // Bit TCC3_.
	PAC_INTFLAGC_TC4__Pos   = 0x5    // Position of TC4_ field.
	PAC_INTFLAGC_TC4__Msk   = 0x20   // Bit mask of TC4_ field.
	PAC_INTFLAGC_TC4_       = 0x20   // Bit TC4_.
	PAC_INTFLAGC_TC5__Pos   = 0x6    // Position of TC5_ field.
	PAC_INTFLAGC_TC5__Msk   = 0x40   // Bit mask of TC5_ field.
	PAC_INTFLAGC_TC5_       = 0x40   // Bit TC5_.
	PAC_INTFLAGC_PDEC__Pos  = 0x7    // Position of PDEC_ field.
	PAC_INTFLAGC_PDEC__Msk  = 0x80   // Bit mask of PDEC_ field.
	PAC_INTFLAGC_PDEC_      = 0x80   // Bit PDEC_.
	PAC_INTFLAGC_AC__Pos    = 0x8    // Position of AC_ field.
	PAC_INTFLAGC_AC__Msk    = 0x100  // Bit mask of AC_ field.
	PAC_INTFLAGC_AC_        = 0x100  // Bit AC_.
	PAC_INTFLAGC_AES__Pos   = 0x9    // Position of AES_ field.
	PAC_INTFLAGC_AES__Msk   = 0x200  // Bit mask of AES_ field.
	PAC_INTFLAGC_AES_       = 0x200  // Bit AES_.
	PAC_INTFLAGC_TRNG__Pos  = 0xa    // Position of TRNG_ field.
	PAC_INTFLAGC_TRNG__Msk  = 0x400  // Bit mask of TRNG_ field.
	PAC_INTFLAGC_TRNG_      = 0x400  // Bit TRNG_.
	PAC_INTFLAGC_ICM__Pos   = 0xb    // Position of ICM_ field.
	PAC_INTFLAGC_ICM__Msk   = 0x800  // Bit mask of ICM_ field.
	PAC_INTFLAGC_ICM_       = 0x800  // Bit ICM_.
	PAC_INTFLAGC_PUKCC__Pos = 0xc    // Position of PUKCC_ field.
	PAC_INTFLAGC_PUKCC__Msk = 0x1000 // Bit mask of PUKCC_ field.
	PAC_INTFLAGC_PUKCC_     = 0x1000 // Bit PUKCC_.
	PAC_INTFLAGC_QSPI__Pos  = 0xd    // Position of QSPI_ field.
	PAC_INTFLAGC_QSPI__Msk  = 0x2000 // Bit mask of QSPI_ field.
	PAC_INTFLAGC_QSPI_      = 0x2000 // Bit QSPI_.
	PAC_INTFLAGC_CCL__Pos   = 0xe    // Position of CCL_ field.
	PAC_INTFLAGC_CCL__Msk   = 0x4000 // Bit mask of CCL_ field.
	PAC_INTFLAGC_CCL_       = 0x4000 // Bit CCL_.

	// INTFLAGD: Peripheral interrupt flag status - Bridge D
	PAC_INTFLAGD_SERCOM4__Pos = 0x0   // Position of SERCOM4_ field.
	PAC_INTFLAGD_SERCOM4__Msk = 0x1   // Bit mask of SERCOM4_ field.
	PAC_INTFLAGD_SERCOM4_     = 0x1   // Bit SERCOM4_.
	PAC_INTFLAGD_SERCOM5__Pos = 0x1   // Position of SERCOM5_ field.
	PAC_INTFLAGD_SERCOM5__Msk = 0x2   // Bit mask of SERCOM5_ field.
	PAC_INTFLAGD_SERCOM5_     = 0x2   // Bit SERCOM5_.
	PAC_INTFLAGD_SERCOM6__Pos = 0x2   // Position of SERCOM6_ field.
	PAC_INTFLAGD_SERCOM6__Msk = 0x4   // Bit mask of SERCOM6_ field.
	PAC_INTFLAGD_SERCOM6_     = 0x4   // Bit SERCOM6_.
	PAC_INTFLAGD_SERCOM7__Pos = 0x3   // Position of SERCOM7_ field.
	PAC_INTFLAGD_SERCOM7__Msk = 0x8   // Bit mask of SERCOM7_ field.
	PAC_INTFLAGD_SERCOM7_     = 0x8   // Bit SERCOM7_.
	PAC_INTFLAGD_TCC4__Pos    = 0x4   // Position of TCC4_ field.
	PAC_INTFLAGD_TCC4__Msk    = 0x10  // Bit mask of TCC4_ field.
	PAC_INTFLAGD_TCC4_        = 0x10  // Bit TCC4_.
	PAC_INTFLAGD_TC6__Pos     = 0x5   // Position of TC6_ field.
	PAC_INTFLAGD_TC6__Msk     = 0x20  // Bit mask of TC6_ field.
	PAC_INTFLAGD_TC6_         = 0x20  // Bit TC6_.
	PAC_INTFLAGD_TC7__Pos     = 0x6   // Position of TC7_ field.
	PAC_INTFLAGD_TC7__Msk     = 0x40  // Bit mask of TC7_ field.
	PAC_INTFLAGD_TC7_         = 0x40  // Bit TC7_.
	PAC_INTFLAGD_ADC0__Pos    = 0x7   // Position of ADC0_ field.
	PAC_INTFLAGD_ADC0__Msk    = 0x80  // Bit mask of ADC0_ field.
	PAC_INTFLAGD_ADC0_        = 0x80  // Bit ADC0_.
	PAC_INTFLAGD_ADC1__Pos    = 0x8   // Position of ADC1_ field.
	PAC_INTFLAGD_ADC1__Msk    = 0x100 // Bit mask of ADC1_ field.
	PAC_INTFLAGD_ADC1_        = 0x100 // Bit ADC1_.
	PAC_INTFLAGD_DAC__Pos     = 0x9   // Position of DAC_ field.
	PAC_INTFLAGD_DAC__Msk     = 0x200 // Bit mask of DAC_ field.
	PAC_INTFLAGD_DAC_         = 0x200 // Bit DAC_.
	PAC_INTFLAGD_I2S__Pos     = 0xa   // Position of I2S_ field.
	PAC_INTFLAGD_I2S__Msk     = 0x400 // Bit mask of I2S_ field.
	PAC_INTFLAGD_I2S_         = 0x400 // Bit I2S_.
	PAC_INTFLAGD_PCC__Pos     = 0xb   // Position of PCC_ field.
	PAC_INTFLAGD_PCC__Msk     = 0x800 // Bit mask of PCC_ field.
	PAC_INTFLAGD_PCC_         = 0x800 // Bit PCC_.

	// STATUSA: Peripheral write protection status - Bridge A
	PAC_STATUSA_PAC__Pos        = 0x0    // Position of PAC_ field.
	PAC_STATUSA_PAC__Msk        = 0x1    // Bit mask of PAC_ field.
	PAC_STATUSA_PAC_            = 0x1    // Bit PAC_.
	PAC_STATUSA_PM__Pos         = 0x1    // Position of PM_ field.
	PAC_STATUSA_PM__Msk         = 0x2    // Bit mask of PM_ field.
	PAC_STATUSA_PM_             = 0x2    // Bit PM_.
	PAC_STATUSA_MCLK__Pos       = 0x2    // Position of MCLK_ field.
	PAC_STATUSA_MCLK__Msk       = 0x4    // Bit mask of MCLK_ field.
	PAC_STATUSA_MCLK_           = 0x4    // Bit MCLK_.
	PAC_STATUSA_RSTC__Pos       = 0x3    // Position of RSTC_ field.
	PAC_STATUSA_RSTC__Msk       = 0x8    // Bit mask of RSTC_ field.
	PAC_STATUSA_RSTC_           = 0x8    // Bit RSTC_.
	PAC_STATUSA_OSCCTRL__Pos    = 0x4    // Position of OSCCTRL_ field.
	PAC_STATUSA_OSCCTRL__Msk    = 0x10   // Bit mask of OSCCTRL_ field.
	PAC_STATUSA_OSCCTRL_        = 0x10   // Bit OSCCTRL_.
	PAC_STATUSA_OSC32KCTRL__Pos = 0x5    // Position of OSC32KCTRL_ field.
	PAC_STATUSA_OSC32KCTRL__Msk = 0x20   // Bit mask of OSC32KCTRL_ field.
	PAC_STATUSA_OSC32KCTRL_     = 0x20   // Bit OSC32KCTRL_.
	PAC_STATUSA_SUPC__Pos       = 0x6    // Position of SUPC_ field.
	PAC_STATUSA_SUPC__Msk       = 0x40   // Bit mask of SUPC_ field.
	PAC_STATUSA_SUPC_           = 0x40   // Bit SUPC_.
	PAC_STATUSA_GCLK__Pos       = 0x7    // Position of GCLK_ field.
	PAC_STATUSA_GCLK__Msk       = 0x80   // Bit mask of GCLK_ field.
	PAC_STATUSA_GCLK_           = 0x80   // Bit GCLK_.
	PAC_STATUSA_WDT__Pos        = 0x8    // Position of WDT_ field.
	PAC_STATUSA_WDT__Msk        = 0x100  // Bit mask of WDT_ field.
	PAC_STATUSA_WDT_            = 0x100  // Bit WDT_.
	PAC_STATUSA_RTC__Pos        = 0x9    // Position of RTC_ field.
	PAC_STATUSA_RTC__Msk        = 0x200  // Bit mask of RTC_ field.
	PAC_STATUSA_RTC_            = 0x200  // Bit RTC_.
	PAC_STATUSA_EIC__Pos        = 0xa    // Position of EIC_ field.
	PAC_STATUSA_EIC__Msk        = 0x400  // Bit mask of EIC_ field.
	PAC_STATUSA_EIC_            = 0x400  // Bit EIC_.
	PAC_STATUSA_FREQM__Pos      = 0xb    // Position of FREQM_ field.
	PAC_STATUSA_FREQM__Msk      = 0x800  // Bit mask of FREQM_ field.
	PAC_STATUSA_FREQM_          = 0x800  // Bit FREQM_.
	PAC_STATUSA_SERCOM0__Pos    = 0xc    // Position of SERCOM0_ field.
	PAC_STATUSA_SERCOM0__Msk    = 0x1000 // Bit mask of SERCOM0_ field.
	PAC_STATUSA_SERCOM0_        = 0x1000 // Bit SERCOM0_.
	PAC_STATUSA_SERCOM1__Pos    = 0xd    // Position of SERCOM1_ field.
	PAC_STATUSA_SERCOM1__Msk    = 0x2000 // Bit mask of SERCOM1_ field.
	PAC_STATUSA_SERCOM1_        = 0x2000 // Bit SERCOM1_.
	PAC_STATUSA_TC0__Pos        = 0xe    // Position of TC0_ field.
	PAC_STATUSA_TC0__Msk        = 0x4000 // Bit mask of TC0_ field.
	PAC_STATUSA_TC0_            = 0x4000 // Bit TC0_.
	PAC_STATUSA_TC1__Pos        = 0xf    // Position of TC1_ field.
	PAC_STATUSA_TC1__Msk        = 0x8000 // Bit mask of TC1_ field.
	PAC_STATUSA_TC1_            = 0x8000 // Bit TC1_.

	// STATUSB: Peripheral write protection status - Bridge B
	PAC_STATUSB_USB__Pos     = 0x0     // Position of USB_ field.
	PAC_STATUSB_USB__Msk     = 0x1     // Bit mask of USB_ field.
	PAC_STATUSB_USB_         = 0x1     // Bit USB_.
	PAC_STATUSB_DSU__Pos     = 0x1     // Position of DSU_ field.
	PAC_STATUSB_DSU__Msk     = 0x2     // Bit mask of DSU_ field.
	PAC_STATUSB_DSU_         = 0x2     // Bit DSU_.
	PAC_STATUSB_NVMCTRL__Pos = 0x2     // Position of NVMCTRL_ field.
	PAC_STATUSB_NVMCTRL__Msk = 0x4     // Bit mask of NVMCTRL_ field.
	PAC_STATUSB_NVMCTRL_     = 0x4     // Bit NVMCTRL_.
	PAC_STATUSB_CMCC__Pos    = 0x3     // Position of CMCC_ field.
	PAC_STATUSB_CMCC__Msk    = 0x8     // Bit mask of CMCC_ field.
	PAC_STATUSB_CMCC_        = 0x8     // Bit CMCC_.
	PAC_STATUSB_PORT__Pos    = 0x4     // Position of PORT_ field.
	PAC_STATUSB_PORT__Msk    = 0x10    // Bit mask of PORT_ field.
	PAC_STATUSB_PORT_        = 0x10    // Bit PORT_.
	PAC_STATUSB_DMAC__Pos    = 0x5     // Position of DMAC_ field.
	PAC_STATUSB_DMAC__Msk    = 0x20    // Bit mask of DMAC_ field.
	PAC_STATUSB_DMAC_        = 0x20    // Bit DMAC_.
	PAC_STATUSB_HMATRIX__Pos = 0x6     // Position of HMATRIX_ field.
	PAC_STATUSB_HMATRIX__Msk = 0x40    // Bit mask of HMATRIX_ field.
	PAC_STATUSB_HMATRIX_     = 0x40    // Bit HMATRIX_.
	PAC_STATUSB_EVSYS__Pos   = 0x7     // Position of EVSYS_ field.
	PAC_STATUSB_EVSYS__Msk   = 0x80    // Bit mask of EVSYS_ field.
	PAC_STATUSB_EVSYS_       = 0x80    // Bit EVSYS_.
	PAC_STATUSB_SERCOM2__Pos = 0x9     // Position of SERCOM2_ field.
	PAC_STATUSB_SERCOM2__Msk = 0x200   // Bit mask of SERCOM2_ field.
	PAC_STATUSB_SERCOM2_     = 0x200   // Bit SERCOM2_.
	PAC_STATUSB_SERCOM3__Pos = 0xa     // Position of SERCOM3_ field.
	PAC_STATUSB_SERCOM3__Msk = 0x400   // Bit mask of SERCOM3_ field.
	PAC_STATUSB_SERCOM3_     = 0x400   // Bit SERCOM3_.
	PAC_STATUSB_TCC0__Pos    = 0xb     // Position of TCC0_ field.
	PAC_STATUSB_TCC0__Msk    = 0x800   // Bit mask of TCC0_ field.
	PAC_STATUSB_TCC0_        = 0x800   // Bit TCC0_.
	PAC_STATUSB_TCC1__Pos    = 0xc     // Position of TCC1_ field.
	PAC_STATUSB_TCC1__Msk    = 0x1000  // Bit mask of TCC1_ field.
	PAC_STATUSB_TCC1_        = 0x1000  // Bit TCC1_.
	PAC_STATUSB_TC2__Pos     = 0xd     // Position of TC2_ field.
	PAC_STATUSB_TC2__Msk     = 0x2000  // Bit mask of TC2_ field.
	PAC_STATUSB_TC2_         = 0x2000  // Bit TC2_.
	PAC_STATUSB_TC3__Pos     = 0xe     // Position of TC3_ field.
	PAC_STATUSB_TC3__Msk     = 0x4000  // Bit mask of TC3_ field.
	PAC_STATUSB_TC3_         = 0x4000  // Bit TC3_.
	PAC_STATUSB_RAMECC__Pos  = 0x10    // Position of RAMECC_ field.
	PAC_STATUSB_RAMECC__Msk  = 0x10000 // Bit mask of RAMECC_ field.
	PAC_STATUSB_RAMECC_      = 0x10000 // Bit RAMECC_.

	// STATUSC: Peripheral write protection status - Bridge C
	PAC_STATUSC_TCC2__Pos  = 0x3    // Position of TCC2_ field.
	PAC_STATUSC_TCC2__Msk  = 0x8    // Bit mask of TCC2_ field.
	PAC_STATUSC_TCC2_      = 0x8    // Bit TCC2_.
	PAC_STATUSC_TCC3__Pos  = 0x4    // Position of TCC3_ field.
	PAC_STATUSC_TCC3__Msk  = 0x10   // Bit mask of TCC3_ field.
	PAC_STATUSC_TCC3_      = 0x10   // Bit TCC3_.
	PAC_STATUSC_TC4__Pos   = 0x5    // Position of TC4_ field.
	PAC_STATUSC_TC4__Msk   = 0x20   // Bit mask of TC4_ field.
	PAC_STATUSC_TC4_       = 0x20   // Bit TC4_.
	PAC_STATUSC_TC5__Pos   = 0x6    // Position of TC5_ field.
	PAC_STATUSC_TC5__Msk   = 0x40   // Bit mask of TC5_ field.
	PAC_STATUSC_TC5_       = 0x40   // Bit TC5_.
	PAC_STATUSC_PDEC__Pos  = 0x7    // Position of PDEC_ field.
	PAC_STATUSC_PDEC__Msk  = 0x80   // Bit mask of PDEC_ field.
	PAC_STATUSC_PDEC_      = 0x80   // Bit PDEC_.
	PAC_STATUSC_AC__Pos    = 0x8    // Position of AC_ field.
	PAC_STATUSC_AC__Msk    = 0x100  // Bit mask of AC_ field.
	PAC_STATUSC_AC_        = 0x100  // Bit AC_.
	PAC_STATUSC_AES__Pos   = 0x9    // Position of AES_ field.
	PAC_STATUSC_AES__Msk   = 0x200  // Bit mask of AES_ field.
	PAC_STATUSC_AES_       = 0x200  // Bit AES_.
	PAC_STATUSC_TRNG__Pos  = 0xa    // Position of TRNG_ field.
	PAC_STATUSC_TRNG__Msk  = 0x400  // Bit mask of TRNG_ field.
	PAC_STATUSC_TRNG_      = 0x400  // Bit TRNG_.
	PAC_STATUSC_ICM__Pos   = 0xb    // Position of ICM_ field.
	PAC_STATUSC_ICM__Msk   = 0x800  // Bit mask of ICM_ field.
	PAC_STATUSC_ICM_       = 0x800  // Bit ICM_.
	PAC_STATUSC_PUKCC__Pos = 0xc    // Position of PUKCC_ field.
	PAC_STATUSC_PUKCC__Msk = 0x1000 // Bit mask of PUKCC_ field.
	PAC_STATUSC_PUKCC_     = 0x1000 // Bit PUKCC_.
	PAC_STATUSC_QSPI__Pos  = 0xd    // Position of QSPI_ field.
	PAC_STATUSC_QSPI__Msk  = 0x2000 // Bit mask of QSPI_ field.
	PAC_STATUSC_QSPI_      = 0x2000 // Bit QSPI_.
	PAC_STATUSC_CCL__Pos   = 0xe    // Position of CCL_ field.
	PAC_STATUSC_CCL__Msk   = 0x4000 // Bit mask of CCL_ field.
	PAC_STATUSC_CCL_       = 0x4000 // Bit CCL_.

	// STATUSD: Peripheral write protection status - Bridge D
	PAC_STATUSD_SERCOM4__Pos = 0x0   // Position of SERCOM4_ field.
	PAC_STATUSD_SERCOM4__Msk = 0x1   // Bit mask of SERCOM4_ field.
	PAC_STATUSD_SERCOM4_     = 0x1   // Bit SERCOM4_.
	PAC_STATUSD_SERCOM5__Pos = 0x1   // Position of SERCOM5_ field.
	PAC_STATUSD_SERCOM5__Msk = 0x2   // Bit mask of SERCOM5_ field.
	PAC_STATUSD_SERCOM5_     = 0x2   // Bit SERCOM5_.
	PAC_STATUSD_SERCOM6__Pos = 0x2   // Position of SERCOM6_ field.
	PAC_STATUSD_SERCOM6__Msk = 0x4   // Bit mask of SERCOM6_ field.
	PAC_STATUSD_SERCOM6_     = 0x4   // Bit SERCOM6_.
	PAC_STATUSD_SERCOM7__Pos = 0x3   // Position of SERCOM7_ field.
	PAC_STATUSD_SERCOM7__Msk = 0x8   // Bit mask of SERCOM7_ field.
	PAC_STATUSD_SERCOM7_     = 0x8   // Bit SERCOM7_.
	PAC_STATUSD_TCC4__Pos    = 0x4   // Position of TCC4_ field.
	PAC_STATUSD_TCC4__Msk    = 0x10  // Bit mask of TCC4_ field.
	PAC_STATUSD_TCC4_        = 0x10  // Bit TCC4_.
	PAC_STATUSD_TC6__Pos     = 0x5   // Position of TC6_ field.
	PAC_STATUSD_TC6__Msk     = 0x20  // Bit mask of TC6_ field.
	PAC_STATUSD_TC6_         = 0x20  // Bit TC6_.
	PAC_STATUSD_TC7__Pos     = 0x6   // Position of TC7_ field.
	PAC_STATUSD_TC7__Msk     = 0x40  // Bit mask of TC7_ field.
	PAC_STATUSD_TC7_         = 0x40  // Bit TC7_.
	PAC_STATUSD_ADC0__Pos    = 0x7   // Position of ADC0_ field.
	PAC_STATUSD_ADC0__Msk    = 0x80  // Bit mask of ADC0_ field.
	PAC_STATUSD_ADC0_        = 0x80  // Bit ADC0_.
	PAC_STATUSD_ADC1__Pos    = 0x8   // Position of ADC1_ field.
	PAC_STATUSD_ADC1__Msk    = 0x100 // Bit mask of ADC1_ field.
	PAC_STATUSD_ADC1_        = 0x100 // Bit ADC1_.
	PAC_STATUSD_DAC__Pos     = 0x9   // Position of DAC_ field.
	PAC_STATUSD_DAC__Msk     = 0x200 // Bit mask of DAC_ field.
	PAC_STATUSD_DAC_         = 0x200 // Bit DAC_.
	PAC_STATUSD_I2S__Pos     = 0xa   // Position of I2S_ field.
	PAC_STATUSD_I2S__Msk     = 0x400 // Bit mask of I2S_ field.
	PAC_STATUSD_I2S_         = 0x400 // Bit I2S_.
	PAC_STATUSD_PCC__Pos     = 0xb   // Position of PCC_ field.
	PAC_STATUSD_PCC__Msk     = 0x800 // Bit mask of PCC_ field.
	PAC_STATUSD_PCC_         = 0x800 // Bit PCC_.
)

// Bitfields for PCC: Parallel Capture Controller
const (
	// MR: Mode Register
	PCC_MR_PCEN_Pos  = 0x0        // Position of PCEN field.
	PCC_MR_PCEN_Msk  = 0x1        // Bit mask of PCEN field.
	PCC_MR_PCEN      = 0x1        // Bit PCEN.
	PCC_MR_DSIZE_Pos = 0x4        // Position of DSIZE field.
	PCC_MR_DSIZE_Msk = 0x30       // Bit mask of DSIZE field.
	PCC_MR_SCALE_Pos = 0x8        // Position of SCALE field.
	PCC_MR_SCALE_Msk = 0x100      // Bit mask of SCALE field.
	PCC_MR_SCALE     = 0x100      // Bit SCALE.
	PCC_MR_ALWYS_Pos = 0x9        // Position of ALWYS field.
	PCC_MR_ALWYS_Msk = 0x200      // Bit mask of ALWYS field.
	PCC_MR_ALWYS     = 0x200      // Bit ALWYS.
	PCC_MR_HALFS_Pos = 0xa        // Position of HALFS field.
	PCC_MR_HALFS_Msk = 0x400      // Bit mask of HALFS field.
	PCC_MR_HALFS     = 0x400      // Bit HALFS.
	PCC_MR_FRSTS_Pos = 0xb        // Position of FRSTS field.
	PCC_MR_FRSTS_Msk = 0x800      // Bit mask of FRSTS field.
	PCC_MR_FRSTS     = 0x800      // Bit FRSTS.
	PCC_MR_ISIZE_Pos = 0x10       // Position of ISIZE field.
	PCC_MR_ISIZE_Msk = 0x70000    // Bit mask of ISIZE field.
	PCC_MR_CID_Pos   = 0x1e       // Position of CID field.
	PCC_MR_CID_Msk   = 0xc0000000 // Bit mask of CID field.

	// IER: Interrupt Enable Register
	PCC_IER_DRDY_Pos = 0x0 // Position of DRDY field.
	PCC_IER_DRDY_Msk = 0x1 // Bit mask of DRDY field.
	PCC_IER_DRDY     = 0x1 // Bit DRDY.
	PCC_IER_OVRE_Pos = 0x1 // Position of OVRE field.
	PCC_IER_OVRE_Msk = 0x2 // Bit mask of OVRE field.
	PCC_IER_OVRE     = 0x2 // Bit OVRE.

	// IDR: Interrupt Disable Register
	PCC_IDR_DRDY_Pos = 0x0 // Position of DRDY field.
	PCC_IDR_DRDY_Msk = 0x1 // Bit mask of DRDY field.
	PCC_IDR_DRDY     = 0x1 // Bit DRDY.
	PCC_IDR_OVRE_Pos = 0x1 // Position of OVRE field.
	PCC_IDR_OVRE_Msk = 0x2 // Bit mask of OVRE field.
	PCC_IDR_OVRE     = 0x2 // Bit OVRE.

	// IMR: Interrupt Mask Register
	PCC_IMR_DRDY_Pos = 0x0 // Position of DRDY field.
	PCC_IMR_DRDY_Msk = 0x1 // Bit mask of DRDY field.
	PCC_IMR_DRDY     = 0x1 // Bit DRDY.
	PCC_IMR_OVRE_Pos = 0x1 // Position of OVRE field.
	PCC_IMR_OVRE_Msk = 0x2 // Bit mask of OVRE field.
	PCC_IMR_OVRE     = 0x2 // Bit OVRE.

	// ISR: Interrupt Status Register
	PCC_ISR_DRDY_Pos = 0x0 // Position of DRDY field.
	PCC_ISR_DRDY_Msk = 0x1 // Bit mask of DRDY field.
	PCC_ISR_DRDY     = 0x1 // Bit DRDY.
	PCC_ISR_OVRE_Pos = 0x1 // Position of OVRE field.
	PCC_ISR_OVRE_Msk = 0x2 // Bit mask of OVRE field.
	PCC_ISR_OVRE     = 0x2 // Bit OVRE.

	// RHR: Reception Holding Register
	PCC_RHR_RDATA_Pos = 0x0        // Position of RDATA field.
	PCC_RHR_RDATA_Msk = 0xffffffff // Bit mask of RDATA field.

	// WPMR: Write Protection Mode Register
	PCC_WPMR_WPEN_Pos  = 0x0        // Position of WPEN field.
	PCC_WPMR_WPEN_Msk  = 0x1        // Bit mask of WPEN field.
	PCC_WPMR_WPEN      = 0x1        // Bit WPEN.
	PCC_WPMR_WPKEY_Pos = 0x8        // Position of WPKEY field.
	PCC_WPMR_WPKEY_Msk = 0xffffff00 // Bit mask of WPKEY field.

	// WPSR: Write Protection Status Register
	PCC_WPSR_WPVS_Pos   = 0x0      // Position of WPVS field.
	PCC_WPSR_WPVS_Msk   = 0x1      // Bit mask of WPVS field.
	PCC_WPSR_WPVS       = 0x1      // Bit WPVS.
	PCC_WPSR_WPVSRC_Pos = 0x8      // Position of WPVSRC field.
	PCC_WPSR_WPVSRC_Msk = 0xffff00 // Bit mask of WPVSRC field.
)

// Bitfields for PDEC: Quadrature Decodeur
const (
	// CTRLA: Control A
	PDEC_CTRLA_SWRST_Pos    = 0x0        // Position of SWRST field.
	PDEC_CTRLA_SWRST_Msk    = 0x1        // Bit mask of SWRST field.
	PDEC_CTRLA_SWRST        = 0x1        // Bit SWRST.
	PDEC_CTRLA_ENABLE_Pos   = 0x1        // Position of ENABLE field.
	PDEC_CTRLA_ENABLE_Msk   = 0x2        // Bit mask of ENABLE field.
	PDEC_CTRLA_ENABLE       = 0x2        // Bit ENABLE.
	PDEC_CTRLA_MODE_Pos     = 0x2        // Position of MODE field.
	PDEC_CTRLA_MODE_Msk     = 0xc        // Bit mask of MODE field.
	PDEC_CTRLA_MODE_QDEC    = 0x0        // QDEC operating mode
	PDEC_CTRLA_MODE_HALL    = 0x1        // HALL operating mode
	PDEC_CTRLA_MODE_COUNTER = 0x2        // COUNTER operating mode
	PDEC_CTRLA_RUNSTDBY_Pos = 0x6        // Position of RUNSTDBY field.
	PDEC_CTRLA_RUNSTDBY_Msk = 0x40       // Bit mask of RUNSTDBY field.
	PDEC_CTRLA_RUNSTDBY     = 0x40       // Bit RUNSTDBY.
	PDEC_CTRLA_CONF_Pos     = 0x8        // Position of CONF field.
	PDEC_CTRLA_CONF_Msk     = 0x700      // Bit mask of CONF field.
	PDEC_CTRLA_CONF_X4      = 0x0        // Quadrature decoder direction
	PDEC_CTRLA_CONF_X4S     = 0x1        // Secure Quadrature decoder direction
	PDEC_CTRLA_CONF_X2      = 0x2        // Decoder direction
	PDEC_CTRLA_CONF_X2S     = 0x3        // Secure decoder direction
	PDEC_CTRLA_CONF_AUTOC   = 0x4        // Auto correction mode
	PDEC_CTRLA_ALOCK_Pos    = 0xb        // Position of ALOCK field.
	PDEC_CTRLA_ALOCK_Msk    = 0x800      // Bit mask of ALOCK field.
	PDEC_CTRLA_ALOCK        = 0x800      // Bit ALOCK.
	PDEC_CTRLA_SWAP_Pos     = 0xe        // Position of SWAP field.
	PDEC_CTRLA_SWAP_Msk     = 0x4000     // Bit mask of SWAP field.
	PDEC_CTRLA_SWAP         = 0x4000     // Bit SWAP.
	PDEC_CTRLA_PEREN_Pos    = 0xf        // Position of PEREN field.
	PDEC_CTRLA_PEREN_Msk    = 0x8000     // Bit mask of PEREN field.
	PDEC_CTRLA_PEREN        = 0x8000     // Bit PEREN.
	PDEC_CTRLA_PINEN0_Pos   = 0x10       // Position of PINEN0 field.
	PDEC_CTRLA_PINEN0_Msk   = 0x10000    // Bit mask of PINEN0 field.
	PDEC_CTRLA_PINEN0       = 0x10000    // Bit PINEN0.
	PDEC_CTRLA_PINEN1_Pos   = 0x11       // Position of PINEN1 field.
	PDEC_CTRLA_PINEN1_Msk   = 0x20000    // Bit mask of PINEN1 field.
	PDEC_CTRLA_PINEN1       = 0x20000    // Bit PINEN1.
	PDEC_CTRLA_PINEN2_Pos   = 0x12       // Position of PINEN2 field.
	PDEC_CTRLA_PINEN2_Msk   = 0x40000    // Bit mask of PINEN2 field.
	PDEC_CTRLA_PINEN2       = 0x40000    // Bit PINEN2.
	PDEC_CTRLA_PINVEN0_Pos  = 0x14       // Position of PINVEN0 field.
	PDEC_CTRLA_PINVEN0_Msk  = 0x100000   // Bit mask of PINVEN0 field.
	PDEC_CTRLA_PINVEN0      = 0x100000   // Bit PINVEN0.
	PDEC_CTRLA_PINVEN1_Pos  = 0x15       // Position of PINVEN1 field.
	PDEC_CTRLA_PINVEN1_Msk  = 0x200000   // Bit mask of PINVEN1 field.
	PDEC_CTRLA_PINVEN1      = 0x200000   // Bit PINVEN1.
	PDEC_CTRLA_PINVEN2_Pos  = 0x16       // Position of PINVEN2 field.
	PDEC_CTRLA_PINVEN2_Msk  = 0x400000   // Bit mask of PINVEN2 field.
	PDEC_CTRLA_PINVEN2      = 0x400000   // Bit PINVEN2.
	PDEC_CTRLA_ANGULAR_Pos  = 0x18       // Position of ANGULAR field.
	PDEC_CTRLA_ANGULAR_Msk  = 0x7000000  // Bit mask of ANGULAR field.
	PDEC_CTRLA_MAXCMP_Pos   = 0x1c       // Position of MAXCMP field.
	PDEC_CTRLA_MAXCMP_Msk   = 0xf0000000 // Bit mask of MAXCMP field.

	// CTRLBCLR: Control B Clear
	PDEC_CTRLBCLR_LUPD_Pos      = 0x1  // Position of LUPD field.
	PDEC_CTRLBCLR_LUPD_Msk      = 0x2  // Bit mask of LUPD field.
	PDEC_CTRLBCLR_LUPD          = 0x2  // Bit LUPD.
	PDEC_CTRLBCLR_CMD_Pos       = 0x5  // Position of CMD field.
	PDEC_CTRLBCLR_CMD_Msk       = 0xe0 // Bit mask of CMD field.
	PDEC_CTRLBCLR_CMD_NONE      = 0x0  // No action
	PDEC_CTRLBCLR_CMD_RETRIGGER = 0x1  // Force a counter restart or retrigger
	PDEC_CTRLBCLR_CMD_UPDATE    = 0x2  // Force update of double buffered registers
	PDEC_CTRLBCLR_CMD_READSYNC  = 0x3  // Force a read synchronization of COUNT
	PDEC_CTRLBCLR_CMD_START     = 0x4  // Start QDEC/HALL
	PDEC_CTRLBCLR_CMD_STOP      = 0x5  // Stop QDEC/HALL

	// CTRLBSET: Control B Set
	PDEC_CTRLBSET_LUPD_Pos      = 0x1  // Position of LUPD field.
	PDEC_CTRLBSET_LUPD_Msk      = 0x2  // Bit mask of LUPD field.
	PDEC_CTRLBSET_LUPD          = 0x2  // Bit LUPD.
	PDEC_CTRLBSET_CMD_Pos       = 0x5  // Position of CMD field.
	PDEC_CTRLBSET_CMD_Msk       = 0xe0 // Bit mask of CMD field.
	PDEC_CTRLBSET_CMD_NONE      = 0x0  // No action
	PDEC_CTRLBSET_CMD_RETRIGGER = 0x1  // Force a counter restart or retrigger
	PDEC_CTRLBSET_CMD_UPDATE    = 0x2  // Force update of double buffered registers
	PDEC_CTRLBSET_CMD_READSYNC  = 0x3  // Force a read synchronization of COUNT
	PDEC_CTRLBSET_CMD_START     = 0x4  // Start QDEC/HALL
	PDEC_CTRLBSET_CMD_STOP      = 0x5  // Stop QDEC/HALL

	// EVCTRL: Event Control
	PDEC_EVCTRL_EVACT_Pos       = 0x0    // Position of EVACT field.
	PDEC_EVCTRL_EVACT_Msk       = 0x3    // Bit mask of EVACT field.
	PDEC_EVCTRL_EVACT_OFF       = 0x0    // Event action disabled
	PDEC_EVCTRL_EVACT_RETRIGGER = 0x1    // Start, restart or retrigger on event
	PDEC_EVCTRL_EVACT_COUNT     = 0x2    // Count on event
	PDEC_EVCTRL_EVINV_Pos       = 0x2    // Position of EVINV field.
	PDEC_EVCTRL_EVINV_Msk       = 0x1c   // Bit mask of EVINV field.
	PDEC_EVCTRL_EVEI_Pos        = 0x5    // Position of EVEI field.
	PDEC_EVCTRL_EVEI_Msk        = 0xe0   // Bit mask of EVEI field.
	PDEC_EVCTRL_OVFEO_Pos       = 0x8    // Position of OVFEO field.
	PDEC_EVCTRL_OVFEO_Msk       = 0x100  // Bit mask of OVFEO field.
	PDEC_EVCTRL_OVFEO           = 0x100  // Bit OVFEO.
	PDEC_EVCTRL_ERREO_Pos       = 0x9    // Position of ERREO field.
	PDEC_EVCTRL_ERREO_Msk       = 0x200  // Bit mask of ERREO field.
	PDEC_EVCTRL_ERREO           = 0x200  // Bit ERREO.
	PDEC_EVCTRL_DIREO_Pos       = 0xa    // Position of DIREO field.
	PDEC_EVCTRL_DIREO_Msk       = 0x400  // Bit mask of DIREO field.
	PDEC_EVCTRL_DIREO           = 0x400  // Bit DIREO.
	PDEC_EVCTRL_VLCEO_Pos       = 0xb    // Position of VLCEO field.
	PDEC_EVCTRL_VLCEO_Msk       = 0x800  // Bit mask of VLCEO field.
	PDEC_EVCTRL_VLCEO           = 0x800  // Bit VLCEO.
	PDEC_EVCTRL_MCEO0_Pos       = 0xc    // Position of MCEO0 field.
	PDEC_EVCTRL_MCEO0_Msk       = 0x1000 // Bit mask of MCEO0 field.
	PDEC_EVCTRL_MCEO0           = 0x1000 // Bit MCEO0.
	PDEC_EVCTRL_MCEO1_Pos       = 0xd    // Position of MCEO1 field.
	PDEC_EVCTRL_MCEO1_Msk       = 0x2000 // Bit mask of MCEO1 field.
	PDEC_EVCTRL_MCEO1           = 0x2000 // Bit MCEO1.

	// INTENCLR: Interrupt Enable Clear
	PDEC_INTENCLR_OVF_Pos = 0x0  // Position of OVF field.
	PDEC_INTENCLR_OVF_Msk = 0x1  // Bit mask of OVF field.
	PDEC_INTENCLR_OVF     = 0x1  // Bit OVF.
	PDEC_INTENCLR_ERR_Pos = 0x1  // Position of ERR field.
	PDEC_INTENCLR_ERR_Msk = 0x2  // Bit mask of ERR field.
	PDEC_INTENCLR_ERR     = 0x2  // Bit ERR.
	PDEC_INTENCLR_DIR_Pos = 0x2  // Position of DIR field.
	PDEC_INTENCLR_DIR_Msk = 0x4  // Bit mask of DIR field.
	PDEC_INTENCLR_DIR     = 0x4  // Bit DIR.
	PDEC_INTENCLR_VLC_Pos = 0x3  // Position of VLC field.
	PDEC_INTENCLR_VLC_Msk = 0x8  // Bit mask of VLC field.
	PDEC_INTENCLR_VLC     = 0x8  // Bit VLC.
	PDEC_INTENCLR_MC0_Pos = 0x4  // Position of MC0 field.
	PDEC_INTENCLR_MC0_Msk = 0x10 // Bit mask of MC0 field.
	PDEC_INTENCLR_MC0     = 0x10 // Bit MC0.
	PDEC_INTENCLR_MC1_Pos = 0x5  // Position of MC1 field.
	PDEC_INTENCLR_MC1_Msk = 0x20 // Bit mask of MC1 field.
	PDEC_INTENCLR_MC1     = 0x20 // Bit MC1.

	// INTENSET: Interrupt Enable Set
	PDEC_INTENSET_OVF_Pos = 0x0  // Position of OVF field.
	PDEC_INTENSET_OVF_Msk = 0x1  // Bit mask of OVF field.
	PDEC_INTENSET_OVF     = 0x1  // Bit OVF.
	PDEC_INTENSET_ERR_Pos = 0x1  // Position of ERR field.
	PDEC_INTENSET_ERR_Msk = 0x2  // Bit mask of ERR field.
	PDEC_INTENSET_ERR     = 0x2  // Bit ERR.
	PDEC_INTENSET_DIR_Pos = 0x2  // Position of DIR field.
	PDEC_INTENSET_DIR_Msk = 0x4  // Bit mask of DIR field.
	PDEC_INTENSET_DIR     = 0x4  // Bit DIR.
	PDEC_INTENSET_VLC_Pos = 0x3  // Position of VLC field.
	PDEC_INTENSET_VLC_Msk = 0x8  // Bit mask of VLC field.
	PDEC_INTENSET_VLC     = 0x8  // Bit VLC.
	PDEC_INTENSET_MC0_Pos = 0x4  // Position of MC0 field.
	PDEC_INTENSET_MC0_Msk = 0x10 // Bit mask of MC0 field.
	PDEC_INTENSET_MC0     = 0x10 // Bit MC0.
	PDEC_INTENSET_MC1_Pos = 0x5  // Position of MC1 field.
	PDEC_INTENSET_MC1_Msk = 0x20 // Bit mask of MC1 field.
	PDEC_INTENSET_MC1     = 0x20 // Bit MC1.

	// INTFLAG: Interrupt Flag Status and Clear
	PDEC_INTFLAG_OVF_Pos = 0x0  // Position of OVF field.
	PDEC_INTFLAG_OVF_Msk = 0x1  // Bit mask of OVF field.
	PDEC_INTFLAG_OVF     = 0x1  // Bit OVF.
	PDEC_INTFLAG_ERR_Pos = 0x1  // Position of ERR field.
	PDEC_INTFLAG_ERR_Msk = 0x2  // Bit mask of ERR field.
	PDEC_INTFLAG_ERR     = 0x2  // Bit ERR.
	PDEC_INTFLAG_DIR_Pos = 0x2  // Position of DIR field.
	PDEC_INTFLAG_DIR_Msk = 0x4  // Bit mask of DIR field.
	PDEC_INTFLAG_DIR     = 0x4  // Bit DIR.
	PDEC_INTFLAG_VLC_Pos = 0x3  // Position of VLC field.
	PDEC_INTFLAG_VLC_Msk = 0x8  // Bit mask of VLC field.
	PDEC_INTFLAG_VLC     = 0x8  // Bit VLC.
	PDEC_INTFLAG_MC0_Pos = 0x4  // Position of MC0 field.
	PDEC_INTFLAG_MC0_Msk = 0x10 // Bit mask of MC0 field.
	PDEC_INTFLAG_MC0     = 0x10 // Bit MC0.
	PDEC_INTFLAG_MC1_Pos = 0x5  // Position of MC1 field.
	PDEC_INTFLAG_MC1_Msk = 0x20 // Bit mask of MC1 field.
	PDEC_INTFLAG_MC1     = 0x20 // Bit MC1.

	// STATUS: Status
	PDEC_STATUS_QERR_Pos       = 0x0    // Position of QERR field.
	PDEC_STATUS_QERR_Msk       = 0x1    // Bit mask of QERR field.
	PDEC_STATUS_QERR           = 0x1    // Bit QERR.
	PDEC_STATUS_IDXERR_Pos     = 0x1    // Position of IDXERR field.
	PDEC_STATUS_IDXERR_Msk     = 0x2    // Bit mask of IDXERR field.
	PDEC_STATUS_IDXERR         = 0x2    // Bit IDXERR.
	PDEC_STATUS_MPERR_Pos      = 0x2    // Position of MPERR field.
	PDEC_STATUS_MPERR_Msk      = 0x4    // Bit mask of MPERR field.
	PDEC_STATUS_MPERR          = 0x4    // Bit MPERR.
	PDEC_STATUS_WINERR_Pos     = 0x4    // Position of WINERR field.
	PDEC_STATUS_WINERR_Msk     = 0x10   // Bit mask of WINERR field.
	PDEC_STATUS_WINERR         = 0x10   // Bit WINERR.
	PDEC_STATUS_HERR_Pos       = 0x5    // Position of HERR field.
	PDEC_STATUS_HERR_Msk       = 0x20   // Bit mask of HERR field.
	PDEC_STATUS_HERR           = 0x20   // Bit HERR.
	PDEC_STATUS_STOP_Pos       = 0x6    // Position of STOP field.
	PDEC_STATUS_STOP_Msk       = 0x40   // Bit mask of STOP field.
	PDEC_STATUS_STOP           = 0x40   // Bit STOP.
	PDEC_STATUS_DIR_Pos        = 0x7    // Position of DIR field.
	PDEC_STATUS_DIR_Msk        = 0x80   // Bit mask of DIR field.
	PDEC_STATUS_DIR            = 0x80   // Bit DIR.
	PDEC_STATUS_PRESCBUFV_Pos  = 0x8    // Position of PRESCBUFV field.
	PDEC_STATUS_PRESCBUFV_Msk  = 0x100  // Bit mask of PRESCBUFV field.
	PDEC_STATUS_PRESCBUFV      = 0x100  // Bit PRESCBUFV.
	PDEC_STATUS_FILTERBUFV_Pos = 0x9    // Position of FILTERBUFV field.
	PDEC_STATUS_FILTERBUFV_Msk = 0x200  // Bit mask of FILTERBUFV field.
	PDEC_STATUS_FILTERBUFV     = 0x200  // Bit FILTERBUFV.
	PDEC_STATUS_CCBUFV0_Pos    = 0xc    // Position of CCBUFV0 field.
	PDEC_STATUS_CCBUFV0_Msk    = 0x1000 // Bit mask of CCBUFV0 field.
	PDEC_STATUS_CCBUFV0        = 0x1000 // Bit CCBUFV0.
	PDEC_STATUS_CCBUFV1_Pos    = 0xd    // Position of CCBUFV1 field.
	PDEC_STATUS_CCBUFV1_Msk    = 0x2000 // Bit mask of CCBUFV1 field.
	PDEC_STATUS_CCBUFV1        = 0x2000 // Bit CCBUFV1.

	// DBGCTRL: Debug Control
	PDEC_DBGCTRL_DBGRUN_Pos = 0x0 // Position of DBGRUN field.
	PDEC_DBGCTRL_DBGRUN_Msk = 0x1 // Bit mask of DBGRUN field.
	PDEC_DBGCTRL_DBGRUN     = 0x1 // Bit DBGRUN.

	// SYNCBUSY: Synchronization Status
	PDEC_SYNCBUSY_SWRST_Pos  = 0x0   // Position of SWRST field.
	PDEC_SYNCBUSY_SWRST_Msk  = 0x1   // Bit mask of SWRST field.
	PDEC_SYNCBUSY_SWRST      = 0x1   // Bit SWRST.
	PDEC_SYNCBUSY_ENABLE_Pos = 0x1   // Position of ENABLE field.
	PDEC_SYNCBUSY_ENABLE_Msk = 0x2   // Bit mask of ENABLE field.
	PDEC_SYNCBUSY_ENABLE     = 0x2   // Bit ENABLE.
	PDEC_SYNCBUSY_CTRLB_Pos  = 0x2   // Position of CTRLB field.
	PDEC_SYNCBUSY_CTRLB_Msk  = 0x4   // Bit mask of CTRLB field.
	PDEC_SYNCBUSY_CTRLB      = 0x4   // Bit CTRLB.
	PDEC_SYNCBUSY_STATUS_Pos = 0x3   // Position of STATUS field.
	PDEC_SYNCBUSY_STATUS_Msk = 0x8   // Bit mask of STATUS field.
	PDEC_SYNCBUSY_STATUS     = 0x8   // Bit STATUS.
	PDEC_SYNCBUSY_PRESC_Pos  = 0x4   // Position of PRESC field.
	PDEC_SYNCBUSY_PRESC_Msk  = 0x10  // Bit mask of PRESC field.
	PDEC_SYNCBUSY_PRESC      = 0x10  // Bit PRESC.
	PDEC_SYNCBUSY_FILTER_Pos = 0x5   // Position of FILTER field.
	PDEC_SYNCBUSY_FILTER_Msk = 0x20  // Bit mask of FILTER field.
	PDEC_SYNCBUSY_FILTER     = 0x20  // Bit FILTER.
	PDEC_SYNCBUSY_COUNT_Pos  = 0x6   // Position of COUNT field.
	PDEC_SYNCBUSY_COUNT_Msk  = 0x40  // Bit mask of COUNT field.
	PDEC_SYNCBUSY_COUNT      = 0x40  // Bit COUNT.
	PDEC_SYNCBUSY_CC0_Pos    = 0x7   // Position of CC0 field.
	PDEC_SYNCBUSY_CC0_Msk    = 0x80  // Bit mask of CC0 field.
	PDEC_SYNCBUSY_CC0        = 0x80  // Bit CC0.
	PDEC_SYNCBUSY_CC1_Pos    = 0x8   // Position of CC1 field.
	PDEC_SYNCBUSY_CC1_Msk    = 0x100 // Bit mask of CC1 field.
	PDEC_SYNCBUSY_CC1        = 0x100 // Bit CC1.

	// PRESC: Prescaler Value
	PDEC_PRESC_PRESC_Pos     = 0x0 // Position of PRESC field.
	PDEC_PRESC_PRESC_Msk     = 0xf // Bit mask of PRESC field.
	PDEC_PRESC_PRESC_DIV1    = 0x0 // No division
	PDEC_PRESC_PRESC_DIV2    = 0x1 // Divide by 2
	PDEC_PRESC_PRESC_DIV4    = 0x2 // Divide by 4
	PDEC_PRESC_PRESC_DIV8    = 0x3 // Divide by 8
	PDEC_PRESC_PRESC_DIV16   = 0x4 // Divide by 16
	PDEC_PRESC_PRESC_DIV32   = 0x5 // Divide by 32
	PDEC_PRESC_PRESC_DIV64   = 0x6 // Divide by 64
	PDEC_PRESC_PRESC_DIV128  = 0x7 // Divide by 128
	PDEC_PRESC_PRESC_DIV256  = 0x8 // Divide by 256
	PDEC_PRESC_PRESC_DIV512  = 0x9 // Divide by 512
	PDEC_PRESC_PRESC_DIV1024 = 0xa // Divide by 1024

	// FILTER: Filter Value
	PDEC_FILTER_FILTER_Pos = 0x0  // Position of FILTER field.
	PDEC_FILTER_FILTER_Msk = 0xff // Bit mask of FILTER field.

	// PRESCBUF: Prescaler Buffer Value
	PDEC_PRESCBUF_PRESCBUF_Pos     = 0x0 // Position of PRESCBUF field.
	PDEC_PRESCBUF_PRESCBUF_Msk     = 0xf // Bit mask of PRESCBUF field.
	PDEC_PRESCBUF_PRESCBUF_DIV1    = 0x0 // No division
	PDEC_PRESCBUF_PRESCBUF_DIV2    = 0x1 // Divide by 2
	PDEC_PRESCBUF_PRESCBUF_DIV4    = 0x2 // Divide by 4
	PDEC_PRESCBUF_PRESCBUF_DIV8    = 0x3 // Divide by 8
	PDEC_PRESCBUF_PRESCBUF_DIV16   = 0x4 // Divide by 16
	PDEC_PRESCBUF_PRESCBUF_DIV32   = 0x5 // Divide by 32
	PDEC_PRESCBUF_PRESCBUF_DIV64   = 0x6 // Divide by 64
	PDEC_PRESCBUF_PRESCBUF_DIV128  = 0x7 // Divide by 128
	PDEC_PRESCBUF_PRESCBUF_DIV256  = 0x8 // Divide by 256
	PDEC_PRESCBUF_PRESCBUF_DIV512  = 0x9 // Divide by 512
	PDEC_PRESCBUF_PRESCBUF_DIV1024 = 0xa // Divide by 1024

	// FILTERBUF: Filter Buffer Value
	PDEC_FILTERBUF_FILTERBUF_Pos = 0x0  // Position of FILTERBUF field.
	PDEC_FILTERBUF_FILTERBUF_Msk = 0xff // Bit mask of FILTERBUF field.

	// COUNT: Counter Value
	PDEC_COUNT_COUNT_Pos = 0x0    // Position of COUNT field.
	PDEC_COUNT_COUNT_Msk = 0xffff // Bit mask of COUNT field.

	// CC: Channel n Compare Value
	PDEC_CC_CC_Pos = 0x0    // Position of CC field.
	PDEC_CC_CC_Msk = 0xffff // Bit mask of CC field.

	// CCBUF: Channel Compare Buffer Value
	PDEC_CCBUF_CCBUF_Pos = 0x0    // Position of CCBUF field.
	PDEC_CCBUF_CCBUF_Msk = 0xffff // Bit mask of CCBUF field.
)

// Bitfields for PM: Power Manager
const (
	// CTRLA: Control A
	PM_CTRLA_IORET_Pos = 0x2 // Position of IORET field.
	PM_CTRLA_IORET_Msk = 0x4 // Bit mask of IORET field.
	PM_CTRLA_IORET     = 0x4 // Bit IORET.

	// SLEEPCFG: Sleep Configuration
	PM_SLEEPCFG_SLEEPMODE_Pos       = 0x0 // Position of SLEEPMODE field.
	PM_SLEEPCFG_SLEEPMODE_Msk       = 0x7 // Bit mask of SLEEPMODE field.
	PM_SLEEPCFG_SLEEPMODE_IDLE      = 0x2 // CPU, AHBx, and APBx clocks are OFF
	PM_SLEEPCFG_SLEEPMODE_STANDBY   = 0x4 // All Clocks are OFF
	PM_SLEEPCFG_SLEEPMODE_HIBERNATE = 0x5 // Backup domain is ON as well as some PDRAMs
	PM_SLEEPCFG_SLEEPMODE_BACKUP    = 0x6 // Only Backup domain is powered ON
	PM_SLEEPCFG_SLEEPMODE_OFF       = 0x7 // All power domains are powered OFF

	// INTENCLR: Interrupt Enable Clear
	PM_INTENCLR_SLEEPRDY_Pos = 0x0 // Position of SLEEPRDY field.
	PM_INTENCLR_SLEEPRDY_Msk = 0x1 // Bit mask of SLEEPRDY field.
	PM_INTENCLR_SLEEPRDY     = 0x1 // Bit SLEEPRDY.

	// INTENSET: Interrupt Enable Set
	PM_INTENSET_SLEEPRDY_Pos = 0x0 // Position of SLEEPRDY field.
	PM_INTENSET_SLEEPRDY_Msk = 0x1 // Bit mask of SLEEPRDY field.
	PM_INTENSET_SLEEPRDY     = 0x1 // Bit SLEEPRDY.

	// INTFLAG: Interrupt Flag Status and Clear
	PM_INTFLAG_SLEEPRDY_Pos = 0x0 // Position of SLEEPRDY field.
	PM_INTFLAG_SLEEPRDY_Msk = 0x1 // Bit mask of SLEEPRDY field.
	PM_INTFLAG_SLEEPRDY     = 0x1 // Bit SLEEPRDY.

	// STDBYCFG: Standby Configuration
	PM_STDBYCFG_RAMCFG_Pos        = 0x0  // Position of RAMCFG field.
	PM_STDBYCFG_RAMCFG_Msk        = 0x3  // Bit mask of RAMCFG field.
	PM_STDBYCFG_RAMCFG_RET        = 0x0  // All the system RAM is retained
	PM_STDBYCFG_RAMCFG_PARTIAL    = 0x1  // Only the first 32Kbytes of the system RAM is retained
	PM_STDBYCFG_RAMCFG_OFF        = 0x2  // All the system RAM is turned OFF
	PM_STDBYCFG_FASTWKUP_Pos      = 0x4  // Position of FASTWKUP field.
	PM_STDBYCFG_FASTWKUP_Msk      = 0x30 // Bit mask of FASTWKUP field.
	PM_STDBYCFG_FASTWKUP_NO       = 0x0  // Fast Wakeup is disabled
	PM_STDBYCFG_FASTWKUP_NVM      = 0x1  // Fast Wakeup is enabled on NVM
	PM_STDBYCFG_FASTWKUP_MAINVREG = 0x2  // Fast Wakeup is enabled on the main voltage regulator (MAINVREG)
	PM_STDBYCFG_FASTWKUP_BOTH     = 0x3  // Fast Wakeup is enabled on both NVM and MAINVREG

	// HIBCFG: Hibernate Configuration
	PM_HIBCFG_RAMCFG_Pos      = 0x0 // Position of RAMCFG field.
	PM_HIBCFG_RAMCFG_Msk      = 0x3 // Bit mask of RAMCFG field.
	PM_HIBCFG_RAMCFG_RET      = 0x0 // All the system RAM is retained
	PM_HIBCFG_RAMCFG_PARTIAL  = 0x1 // Only the first 32Kbytes of the system RAM is retained
	PM_HIBCFG_RAMCFG_OFF      = 0x2 // All the system RAM is turned OFF
	PM_HIBCFG_BRAMCFG_Pos     = 0x2 // Position of BRAMCFG field.
	PM_HIBCFG_BRAMCFG_Msk     = 0xc // Bit mask of BRAMCFG field.
	PM_HIBCFG_BRAMCFG_RET     = 0x0 // All the backup RAM is retained
	PM_HIBCFG_BRAMCFG_PARTIAL = 0x1 // Only the first 4Kbytes of the backup RAM is retained
	PM_HIBCFG_BRAMCFG_OFF     = 0x2 // All the backup RAM is turned OFF

	// BKUPCFG: Backup Configuration
	PM_BKUPCFG_BRAMCFG_Pos     = 0x0 // Position of BRAMCFG field.
	PM_BKUPCFG_BRAMCFG_Msk     = 0x3 // Bit mask of BRAMCFG field.
	PM_BKUPCFG_BRAMCFG_RET     = 0x0 // All the backup RAM is retained
	PM_BKUPCFG_BRAMCFG_PARTIAL = 0x1 // Only the first 4Kbytes of the backup RAM is retained
	PM_BKUPCFG_BRAMCFG_OFF     = 0x2 // All the backup RAM is turned OFF

	// PWSAKDLY: Power Switch Acknowledge Delay
	PM_PWSAKDLY_DLYVAL_Pos = 0x0  // Position of DLYVAL field.
	PM_PWSAKDLY_DLYVAL_Msk = 0x7f // Bit mask of DLYVAL field.
	PM_PWSAKDLY_IGNACK_Pos = 0x7  // Position of IGNACK field.
	PM_PWSAKDLY_IGNACK_Msk = 0x80 // Bit mask of IGNACK field.
	PM_PWSAKDLY_IGNACK     = 0x80 // Bit IGNACK.
)

// Bitfields for PORT: Port Module
const (
	// GROUP.DIR: Data Direction
	PORT_GROUP_DIR_DIR_Pos = 0x0        // Position of DIR field.
	PORT_GROUP_DIR_DIR_Msk = 0xffffffff // Bit mask of DIR field.

	// GROUP.DIRCLR: Data Direction Clear
	PORT_GROUP_DIRCLR_DIRCLR_Pos = 0x0        // Position of DIRCLR field.
	PORT_GROUP_DIRCLR_DIRCLR_Msk = 0xffffffff // Bit mask of DIRCLR field.

	// GROUP.DIRSET: Data Direction Set
	PORT_GROUP_DIRSET_DIRSET_Pos = 0x0        // Position of DIRSET field.
	PORT_GROUP_DIRSET_DIRSET_Msk = 0xffffffff // Bit mask of DIRSET field.

	// GROUP.DIRTGL: Data Direction Toggle
	PORT_GROUP_DIRTGL_DIRTGL_Pos = 0x0        // Position of DIRTGL field.
	PORT_GROUP_DIRTGL_DIRTGL_Msk = 0xffffffff // Bit mask of DIRTGL field.

	// GROUP.OUT: Data Output Value
	PORT_GROUP_OUT_OUT_Pos = 0x0        // Position of OUT field.
	PORT_GROUP_OUT_OUT_Msk = 0xffffffff // Bit mask of OUT field.

	// GROUP.OUTCLR: Data Output Value Clear
	PORT_GROUP_OUTCLR_OUTCLR_Pos = 0x0        // Position of OUTCLR field.
	PORT_GROUP_OUTCLR_OUTCLR_Msk = 0xffffffff // Bit mask of OUTCLR field.

	// GROUP.OUTSET: Data Output Value Set
	PORT_GROUP_OUTSET_OUTSET_Pos = 0x0        // Position of OUTSET field.
	PORT_GROUP_OUTSET_OUTSET_Msk = 0xffffffff // Bit mask of OUTSET field.

	// GROUP.OUTTGL: Data Output Value Toggle
	PORT_GROUP_OUTTGL_OUTTGL_Pos = 0x0        // Position of OUTTGL field.
	PORT_GROUP_OUTTGL_OUTTGL_Msk = 0xffffffff // Bit mask of OUTTGL field.

	// GROUP.IN: Data Input Value
	PORT_GROUP_IN_IN_Pos = 0x0        // Position of IN field.
	PORT_GROUP_IN_IN_Msk = 0xffffffff // Bit mask of IN field.

	// GROUP.CTRL: Control
	PORT_GROUP_CTRL_SAMPLING_Pos = 0x0        // Position of SAMPLING field.
	PORT_GROUP_CTRL_SAMPLING_Msk = 0xffffffff // Bit mask of SAMPLING field.

	// GROUP.WRCONFIG: Write Configuration
	PORT_GROUP_WRCONFIG_PINMASK_Pos  = 0x0        // Position of PINMASK field.
	PORT_GROUP_WRCONFIG_PINMASK_Msk  = 0xffff     // Bit mask of PINMASK field.
	PORT_GROUP_WRCONFIG_PMUXEN_Pos   = 0x10       // Position of PMUXEN field.
	PORT_GROUP_WRCONFIG_PMUXEN_Msk   = 0x10000    // Bit mask of PMUXEN field.
	PORT_GROUP_WRCONFIG_PMUXEN       = 0x10000    // Bit PMUXEN.
	PORT_GROUP_WRCONFIG_INEN_Pos     = 0x11       // Position of INEN field.
	PORT_GROUP_WRCONFIG_INEN_Msk     = 0x20000    // Bit mask of INEN field.
	PORT_GROUP_WRCONFIG_INEN         = 0x20000    // Bit INEN.
	PORT_GROUP_WRCONFIG_PULLEN_Pos   = 0x12       // Position of PULLEN field.
	PORT_GROUP_WRCONFIG_PULLEN_Msk   = 0x40000    // Bit mask of PULLEN field.
	PORT_GROUP_WRCONFIG_PULLEN       = 0x40000    // Bit PULLEN.
	PORT_GROUP_WRCONFIG_DRVSTR_Pos   = 0x16       // Position of DRVSTR field.
	PORT_GROUP_WRCONFIG_DRVSTR_Msk   = 0x400000   // Bit mask of DRVSTR field.
	PORT_GROUP_WRCONFIG_DRVSTR       = 0x400000   // Bit DRVSTR.
	PORT_GROUP_WRCONFIG_PMUX_Pos     = 0x18       // Position of PMUX field.
	PORT_GROUP_WRCONFIG_PMUX_Msk     = 0xf000000  // Bit mask of PMUX field.
	PORT_GROUP_WRCONFIG_WRPMUX_Pos   = 0x1c       // Position of WRPMUX field.
	PORT_GROUP_WRCONFIG_WRPMUX_Msk   = 0x10000000 // Bit mask of WRPMUX field.
	PORT_GROUP_WRCONFIG_WRPMUX       = 0x10000000 // Bit WRPMUX.
	PORT_GROUP_WRCONFIG_WRPINCFG_Pos = 0x1e       // Position of WRPINCFG field.
	PORT_GROUP_WRCONFIG_WRPINCFG_Msk = 0x40000000 // Bit mask of WRPINCFG field.
	PORT_GROUP_WRCONFIG_WRPINCFG     = 0x40000000 // Bit WRPINCFG.
	PORT_GROUP_WRCONFIG_HWSEL_Pos    = 0x1f       // Position of HWSEL field.
	PORT_GROUP_WRCONFIG_HWSEL_Msk    = 0x80000000 // Bit mask of HWSEL field.
	PORT_GROUP_WRCONFIG_HWSEL        = 0x80000000 // Bit HWSEL.

	// GROUP.EVCTRL: Event Input Control
	PORT_GROUP_EVCTRL_PID0_Pos    = 0x0        // Position of PID0 field.
	PORT_GROUP_EVCTRL_PID0_Msk    = 0x1f       // Bit mask of PID0 field.
	PORT_GROUP_EVCTRL_EVACT0_Pos  = 0x5        // Position of EVACT0 field.
	PORT_GROUP_EVCTRL_EVACT0_Msk  = 0x60       // Bit mask of EVACT0 field.
	PORT_GROUP_EVCTRL_EVACT0_OUT  = 0x0        // Event output to pin
	PORT_GROUP_EVCTRL_EVACT0_SET  = 0x1        // Set output register of pin on event
	PORT_GROUP_EVCTRL_EVACT0_CLR  = 0x2        // Clear output register of pin on event
	PORT_GROUP_EVCTRL_EVACT0_TGL  = 0x3        // Toggle output register of pin on event
	PORT_GROUP_EVCTRL_PORTEI0_Pos = 0x7        // Position of PORTEI0 field.
	PORT_GROUP_EVCTRL_PORTEI0_Msk = 0x80       // Bit mask of PORTEI0 field.
	PORT_GROUP_EVCTRL_PORTEI0     = 0x80       // Bit PORTEI0.
	PORT_GROUP_EVCTRL_PID1_Pos    = 0x8        // Position of PID1 field.
	PORT_GROUP_EVCTRL_PID1_Msk    = 0x1f00     // Bit mask of PID1 field.
	PORT_GROUP_EVCTRL_EVACT1_Pos  = 0xd        // Position of EVACT1 field.
	PORT_GROUP_EVCTRL_EVACT1_Msk  = 0x6000     // Bit mask of EVACT1 field.
	PORT_GROUP_EVCTRL_PORTEI1_Pos = 0xf        // Position of PORTEI1 field.
	PORT_GROUP_EVCTRL_PORTEI1_Msk = 0x8000     // Bit mask of PORTEI1 field.
	PORT_GROUP_EVCTRL_PORTEI1     = 0x8000     // Bit PORTEI1.
	PORT_GROUP_EVCTRL_PID2_Pos    = 0x10       // Position of PID2 field.
	PORT_GROUP_EVCTRL_PID2_Msk    = 0x1f0000   // Bit mask of PID2 field.
	PORT_GROUP_EVCTRL_EVACT2_Pos  = 0x15       // Position of EVACT2 field.
	PORT_GROUP_EVCTRL_EVACT2_Msk  = 0x600000   // Bit mask of EVACT2 field.
	PORT_GROUP_EVCTRL_PORTEI2_Pos = 0x17       // Position of PORTEI2 field.
	PORT_GROUP_EVCTRL_PORTEI2_Msk = 0x800000   // Bit mask of PORTEI2 field.
	PORT_GROUP_EVCTRL_PORTEI2     = 0x800000   // Bit PORTEI2.
	PORT_GROUP_EVCTRL_PID3_Pos    = 0x18       // Position of PID3 field.
	PORT_GROUP_EVCTRL_PID3_Msk    = 0x1f000000 // Bit mask of PID3 field.
	PORT_GROUP_EVCTRL_EVACT3_Pos  = 0x1d       // Position of EVACT3 field.
	PORT_GROUP_EVCTRL_EVACT3_Msk  = 0x60000000 // Bit mask of EVACT3 field.
	PORT_GROUP_EVCTRL_PORTEI3_Pos = 0x1f       // Position of PORTEI3 field.
	PORT_GROUP_EVCTRL_PORTEI3_Msk = 0x80000000 // Bit mask of PORTEI3 field.
	PORT_GROUP_EVCTRL_PORTEI3     = 0x80000000 // Bit PORTEI3.

	// GROUP.PMUX: Peripheral Multiplexing
	PORT_GROUP_PMUX_PMUXE_Pos = 0x0  // Position of PMUXE field.
	PORT_GROUP_PMUX_PMUXE_Msk = 0xf  // Bit mask of PMUXE field.
	PORT_GROUP_PMUX_PMUXO_Pos = 0x4  // Position of PMUXO field.
	PORT_GROUP_PMUX_PMUXO_Msk = 0xf0 // Bit mask of PMUXO field.

	// GROUP.PINCFG: Pin Configuration
	PORT_GROUP_PINCFG_PMUXEN_Pos = 0x0  // Position of PMUXEN field.
	PORT_GROUP_PINCFG_PMUXEN_Msk = 0x1  // Bit mask of PMUXEN field.
	PORT_GROUP_PINCFG_PMUXEN     = 0x1  // Bit PMUXEN.
	PORT_GROUP_PINCFG_INEN_Pos   = 0x1  // Position of INEN field.
	PORT_GROUP_PINCFG_INEN_Msk   = 0x2  // Bit mask of INEN field.
	PORT_GROUP_PINCFG_INEN       = 0x2  // Bit INEN.
	PORT_GROUP_PINCFG_PULLEN_Pos = 0x2  // Position of PULLEN field.
	PORT_GROUP_PINCFG_PULLEN_Msk = 0x4  // Bit mask of PULLEN field.
	PORT_GROUP_PINCFG_PULLEN     = 0x4  // Bit PULLEN.
	PORT_GROUP_PINCFG_DRVSTR_Pos = 0x6  // Position of DRVSTR field.
	PORT_GROUP_PINCFG_DRVSTR_Msk = 0x40 // Bit mask of DRVSTR field.
	PORT_GROUP_PINCFG_DRVSTR     = 0x40 // Bit DRVSTR.
)

// Bitfields for QSPI: Quad SPI interface
const (
	// CTRLA: Control A
	QSPI_CTRLA_SWRST_Pos    = 0x0       // Position of SWRST field.
	QSPI_CTRLA_SWRST_Msk    = 0x1       // Bit mask of SWRST field.
	QSPI_CTRLA_SWRST        = 0x1       // Bit SWRST.
	QSPI_CTRLA_ENABLE_Pos   = 0x1       // Position of ENABLE field.
	QSPI_CTRLA_ENABLE_Msk   = 0x2       // Bit mask of ENABLE field.
	QSPI_CTRLA_ENABLE       = 0x2       // Bit ENABLE.
	QSPI_CTRLA_LASTXFER_Pos = 0x18      // Position of LASTXFER field.
	QSPI_CTRLA_LASTXFER_Msk = 0x1000000 // Bit mask of LASTXFER field.
	QSPI_CTRLA_LASTXFER     = 0x1000000 // Bit LASTXFER.

	// CTRLB: Control B
	QSPI_CTRLB_MODE_Pos              = 0x0        // Position of MODE field.
	QSPI_CTRLB_MODE_Msk              = 0x1        // Bit mask of MODE field.
	QSPI_CTRLB_MODE                  = 0x1        // Bit MODE.
	QSPI_CTRLB_MODE_SPI              = 0x0        // SPI operating mode
	QSPI_CTRLB_MODE_MEMORY           = 0x1        // Serial Memory operating mode
	QSPI_CTRLB_LOOPEN_Pos            = 0x1        // Position of LOOPEN field.
	QSPI_CTRLB_LOOPEN_Msk            = 0x2        // Bit mask of LOOPEN field.
	QSPI_CTRLB_LOOPEN                = 0x2        // Bit LOOPEN.
	QSPI_CTRLB_WDRBT_Pos             = 0x2        // Position of WDRBT field.
	QSPI_CTRLB_WDRBT_Msk             = 0x4        // Bit mask of WDRBT field.
	QSPI_CTRLB_WDRBT                 = 0x4        // Bit WDRBT.
	QSPI_CTRLB_SMEMREG_Pos           = 0x3        // Position of SMEMREG field.
	QSPI_CTRLB_SMEMREG_Msk           = 0x8        // Bit mask of SMEMREG field.
	QSPI_CTRLB_SMEMREG               = 0x8        // Bit SMEMREG.
	QSPI_CTRLB_CSMODE_Pos            = 0x4        // Position of CSMODE field.
	QSPI_CTRLB_CSMODE_Msk            = 0x30       // Bit mask of CSMODE field.
	QSPI_CTRLB_CSMODE_NORELOAD       = 0x0        // The chip select is deasserted if TD has not been reloaded before the end of the current transfer.
	QSPI_CTRLB_CSMODE_LASTXFER       = 0x1        // The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in TD has been transferred.
	QSPI_CTRLB_CSMODE_SYSTEMATICALLY = 0x2        // The chip select is deasserted systematically after each transfer.
	QSPI_CTRLB_DATALEN_Pos           = 0x8        // Position of DATALEN field.
	QSPI_CTRLB_DATALEN_Msk           = 0xf00      // Bit mask of DATALEN field.
	QSPI_CTRLB_DATALEN_8BITS         = 0x0        // 8-bits transfer
	QSPI_CTRLB_DATALEN_9BITS         = 0x1        // 9 bits transfer
	QSPI_CTRLB_DATALEN_10BITS        = 0x2        // 10-bits transfer
	QSPI_CTRLB_DATALEN_11BITS        = 0x3        // 11-bits transfer
	QSPI_CTRLB_DATALEN_12BITS        = 0x4        // 12-bits transfer
	QSPI_CTRLB_DATALEN_13BITS        = 0x5        // 13-bits transfer
	QSPI_CTRLB_DATALEN_14BITS        = 0x6        // 14-bits transfer
	QSPI_CTRLB_DATALEN_15BITS        = 0x7        // 15-bits transfer
	QSPI_CTRLB_DATALEN_16BITS        = 0x8        // 16-bits transfer
	QSPI_CTRLB_DLYBCT_Pos            = 0x10       // Position of DLYBCT field.
	QSPI_CTRLB_DLYBCT_Msk            = 0xff0000   // Bit mask of DLYBCT field.
	QSPI_CTRLB_DLYCS_Pos             = 0x18       // Position of DLYCS field.
	QSPI_CTRLB_DLYCS_Msk             = 0xff000000 // Bit mask of DLYCS field.

	// BAUD: Baud Rate
	QSPI_BAUD_CPOL_Pos  = 0x0      // Position of CPOL field.
	QSPI_BAUD_CPOL_Msk  = 0x1      // Bit mask of CPOL field.
	QSPI_BAUD_CPOL      = 0x1      // Bit CPOL.
	QSPI_BAUD_CPHA_Pos  = 0x1      // Position of CPHA field.
	QSPI_BAUD_CPHA_Msk  = 0x2      // Bit mask of CPHA field.
	QSPI_BAUD_CPHA      = 0x2      // Bit CPHA.
	QSPI_BAUD_BAUD_Pos  = 0x8      // Position of BAUD field.
	QSPI_BAUD_BAUD_Msk  = 0xff00   // Bit mask of BAUD field.
	QSPI_BAUD_DLYBS_Pos = 0x10     // Position of DLYBS field.
	QSPI_BAUD_DLYBS_Msk = 0xff0000 // Bit mask of DLYBS field.

	// RXDATA: Receive Data
	QSPI_RXDATA_DATA_Pos = 0x0    // Position of DATA field.
	QSPI_RXDATA_DATA_Msk = 0xffff // Bit mask of DATA field.

	// TXDATA: Transmit Data
	QSPI_TXDATA_DATA_Pos = 0x0    // Position of DATA field.
	QSPI_TXDATA_DATA_Msk = 0xffff // Bit mask of DATA field.

	// INTENCLR: Interrupt Enable Clear
	QSPI_INTENCLR_RXC_Pos      = 0x0   // Position of RXC field.
	QSPI_INTENCLR_RXC_Msk      = 0x1   // Bit mask of RXC field.
	QSPI_INTENCLR_RXC          = 0x1   // Bit RXC.
	QSPI_INTENCLR_DRE_Pos      = 0x1   // Position of DRE field.
	QSPI_INTENCLR_DRE_Msk      = 0x2   // Bit mask of DRE field.
	QSPI_INTENCLR_DRE          = 0x2   // Bit DRE.
	QSPI_INTENCLR_TXC_Pos      = 0x2   // Position of TXC field.
	QSPI_INTENCLR_TXC_Msk      = 0x4   // Bit mask of TXC field.
	QSPI_INTENCLR_TXC          = 0x4   // Bit TXC.
	QSPI_INTENCLR_ERROR_Pos    = 0x3   // Position of ERROR field.
	QSPI_INTENCLR_ERROR_Msk    = 0x8   // Bit mask of ERROR field.
	QSPI_INTENCLR_ERROR        = 0x8   // Bit ERROR.
	QSPI_INTENCLR_CSRISE_Pos   = 0x8   // Position of CSRISE field.
	QSPI_INTENCLR_CSRISE_Msk   = 0x100 // Bit mask of CSRISE field.
	QSPI_INTENCLR_CSRISE       = 0x100 // Bit CSRISE.
	QSPI_INTENCLR_INSTREND_Pos = 0xa   // Position of INSTREND field.
	QSPI_INTENCLR_INSTREND_Msk = 0x400 // Bit mask of INSTREND field.
	QSPI_INTENCLR_INSTREND     = 0x400 // Bit INSTREND.

	// INTENSET: Interrupt Enable Set
	QSPI_INTENSET_RXC_Pos      = 0x0   // Position of RXC field.
	QSPI_INTENSET_RXC_Msk      = 0x1   // Bit mask of RXC field.
	QSPI_INTENSET_RXC          = 0x1   // Bit RXC.
	QSPI_INTENSET_DRE_Pos      = 0x1   // Position of DRE field.
	QSPI_INTENSET_DRE_Msk      = 0x2   // Bit mask of DRE field.
	QSPI_INTENSET_DRE          = 0x2   // Bit DRE.
	QSPI_INTENSET_TXC_Pos      = 0x2   // Position of TXC field.
	QSPI_INTENSET_TXC_Msk      = 0x4   // Bit mask of TXC field.
	QSPI_INTENSET_TXC          = 0x4   // Bit TXC.
	QSPI_INTENSET_ERROR_Pos    = 0x3   // Position of ERROR field.
	QSPI_INTENSET_ERROR_Msk    = 0x8   // Bit mask of ERROR field.
	QSPI_INTENSET_ERROR        = 0x8   // Bit ERROR.
	QSPI_INTENSET_CSRISE_Pos   = 0x8   // Position of CSRISE field.
	QSPI_INTENSET_CSRISE_Msk   = 0x100 // Bit mask of CSRISE field.
	QSPI_INTENSET_CSRISE       = 0x100 // Bit CSRISE.
	QSPI_INTENSET_INSTREND_Pos = 0xa   // Position of INSTREND field.
	QSPI_INTENSET_INSTREND_Msk = 0x400 // Bit mask of INSTREND field.
	QSPI_INTENSET_INSTREND     = 0x400 // Bit INSTREND.

	// INTFLAG: Interrupt Flag Status and Clear
	QSPI_INTFLAG_RXC_Pos      = 0x0   // Position of RXC field.
	QSPI_INTFLAG_RXC_Msk      = 0x1   // Bit mask of RXC field.
	QSPI_INTFLAG_RXC          = 0x1   // Bit RXC.
	QSPI_INTFLAG_DRE_Pos      = 0x1   // Position of DRE field.
	QSPI_INTFLAG_DRE_Msk      = 0x2   // Bit mask of DRE field.
	QSPI_INTFLAG_DRE          = 0x2   // Bit DRE.
	QSPI_INTFLAG_TXC_Pos      = 0x2   // Position of TXC field.
	QSPI_INTFLAG_TXC_Msk      = 0x4   // Bit mask of TXC field.
	QSPI_INTFLAG_TXC          = 0x4   // Bit TXC.
	QSPI_INTFLAG_ERROR_Pos    = 0x3   // Position of ERROR field.
	QSPI_INTFLAG_ERROR_Msk    = 0x8   // Bit mask of ERROR field.
	QSPI_INTFLAG_ERROR        = 0x8   // Bit ERROR.
	QSPI_INTFLAG_CSRISE_Pos   = 0x8   // Position of CSRISE field.
	QSPI_INTFLAG_CSRISE_Msk   = 0x100 // Bit mask of CSRISE field.
	QSPI_INTFLAG_CSRISE       = 0x100 // Bit CSRISE.
	QSPI_INTFLAG_INSTREND_Pos = 0xa   // Position of INSTREND field.
	QSPI_INTFLAG_INSTREND_Msk = 0x400 // Bit mask of INSTREND field.
	QSPI_INTFLAG_INSTREND     = 0x400 // Bit INSTREND.

	// STATUS: Status Register
	QSPI_STATUS_ENABLE_Pos   = 0x1   // Position of ENABLE field.
	QSPI_STATUS_ENABLE_Msk   = 0x2   // Bit mask of ENABLE field.
	QSPI_STATUS_ENABLE       = 0x2   // Bit ENABLE.
	QSPI_STATUS_CSSTATUS_Pos = 0x9   // Position of CSSTATUS field.
	QSPI_STATUS_CSSTATUS_Msk = 0x200 // Bit mask of CSSTATUS field.
	QSPI_STATUS_CSSTATUS     = 0x200 // Bit CSSTATUS.

	// INSTRADDR: Instruction Address
	QSPI_INSTRADDR_ADDR_Pos = 0x0        // Position of ADDR field.
	QSPI_INSTRADDR_ADDR_Msk = 0xffffffff // Bit mask of ADDR field.

	// INSTRCTRL: Instruction Code
	QSPI_INSTRCTRL_INSTR_Pos   = 0x0      // Position of INSTR field.
	QSPI_INSTRCTRL_INSTR_Msk   = 0xff     // Bit mask of INSTR field.
	QSPI_INSTRCTRL_OPTCODE_Pos = 0x10     // Position of OPTCODE field.
	QSPI_INSTRCTRL_OPTCODE_Msk = 0xff0000 // Bit mask of OPTCODE field.

	// INSTRFRAME: Instruction Frame
	QSPI_INSTRFRAME_WIDTH_Pos            = 0x0      // Position of WIDTH field.
	QSPI_INSTRFRAME_WIDTH_Msk            = 0x7      // Bit mask of WIDTH field.
	QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI = 0x0      // Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI
	QSPI_INSTRFRAME_WIDTH_DUAL_OUTPUT    = 0x1      // Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI
	QSPI_INSTRFRAME_WIDTH_QUAD_OUTPUT    = 0x2      // Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI
	QSPI_INSTRFRAME_WIDTH_DUAL_IO        = 0x3      // Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI
	QSPI_INSTRFRAME_WIDTH_QUAD_IO        = 0x4      // Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI
	QSPI_INSTRFRAME_WIDTH_DUAL_CMD       = 0x5      // Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI
	QSPI_INSTRFRAME_WIDTH_QUAD_CMD       = 0x6      // Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI
	QSPI_INSTRFRAME_INSTREN_Pos          = 0x4      // Position of INSTREN field.
	QSPI_INSTRFRAME_INSTREN_Msk          = 0x10     // Bit mask of INSTREN field.
	QSPI_INSTRFRAME_INSTREN              = 0x10     // Bit INSTREN.
	QSPI_INSTRFRAME_ADDREN_Pos           = 0x5      // Position of ADDREN field.
	QSPI_INSTRFRAME_ADDREN_Msk           = 0x20     // Bit mask of ADDREN field.
	QSPI_INSTRFRAME_ADDREN               = 0x20     // Bit ADDREN.
	QSPI_INSTRFRAME_OPTCODEEN_Pos        = 0x6      // Position of OPTCODEEN field.
	QSPI_INSTRFRAME_OPTCODEEN_Msk        = 0x40     // Bit mask of OPTCODEEN field.
	QSPI_INSTRFRAME_OPTCODEEN            = 0x40     // Bit OPTCODEEN.
	QSPI_INSTRFRAME_DATAEN_Pos           = 0x7      // Position of DATAEN field.
	QSPI_INSTRFRAME_DATAEN_Msk           = 0x80     // Bit mask of DATAEN field.
	QSPI_INSTRFRAME_DATAEN               = 0x80     // Bit DATAEN.
	QSPI_INSTRFRAME_OPTCODELEN_Pos       = 0x8      // Position of OPTCODELEN field.
	QSPI_INSTRFRAME_OPTCODELEN_Msk       = 0x300    // Bit mask of OPTCODELEN field.
	QSPI_INSTRFRAME_OPTCODELEN_1BIT      = 0x0      // 1-bit length option code
	QSPI_INSTRFRAME_OPTCODELEN_2BITS     = 0x1      // 2-bits length option code
	QSPI_INSTRFRAME_OPTCODELEN_4BITS     = 0x2      // 4-bits length option code
	QSPI_INSTRFRAME_OPTCODELEN_8BITS     = 0x3      // 8-bits length option code
	QSPI_INSTRFRAME_ADDRLEN_Pos          = 0xa      // Position of ADDRLEN field.
	QSPI_INSTRFRAME_ADDRLEN_Msk          = 0x400    // Bit mask of ADDRLEN field.
	QSPI_INSTRFRAME_ADDRLEN              = 0x400    // Bit ADDRLEN.
	QSPI_INSTRFRAME_ADDRLEN_24BITS       = 0x0      // 24-bits address length
	QSPI_INSTRFRAME_ADDRLEN_32BITS       = 0x1      // 32-bits address length
	QSPI_INSTRFRAME_TFRTYPE_Pos          = 0xc      // Position of TFRTYPE field.
	QSPI_INSTRFRAME_TFRTYPE_Msk          = 0x3000   // Bit mask of TFRTYPE field.
	QSPI_INSTRFRAME_TFRTYPE_READ         = 0x0      // Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial flash memory is not possible.
	QSPI_INSTRFRAME_TFRTYPE_READMEMORY   = 0x1      // Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial flash memory is possible.
	QSPI_INSTRFRAME_TFRTYPE_WRITE        = 0x2      // Write transfer into the serial memory.Scrambling is not performed.
	QSPI_INSTRFRAME_TFRTYPE_WRITEMEMORY  = 0x3      // Write data transfer into the serial memory.If enabled, scrambling is performed.
	QSPI_INSTRFRAME_CRMODE_Pos           = 0xe      // Position of CRMODE field.
	QSPI_INSTRFRAME_CRMODE_Msk           = 0x4000   // Bit mask of CRMODE field.
	QSPI_INSTRFRAME_CRMODE               = 0x4000   // Bit CRMODE.
	QSPI_INSTRFRAME_DDREN_Pos            = 0xf      // Position of DDREN field.
	QSPI_INSTRFRAME_DDREN_Msk            = 0x8000   // Bit mask of DDREN field.
	QSPI_INSTRFRAME_DDREN                = 0x8000   // Bit DDREN.
	QSPI_INSTRFRAME_DUMMYLEN_Pos         = 0x10     // Position of DUMMYLEN field.
	QSPI_INSTRFRAME_DUMMYLEN_Msk         = 0x1f0000 // Bit mask of DUMMYLEN field.

	// SCRAMBCTRL: Scrambling Mode
	QSPI_SCRAMBCTRL_ENABLE_Pos    = 0x0 // Position of ENABLE field.
	QSPI_SCRAMBCTRL_ENABLE_Msk    = 0x1 // Bit mask of ENABLE field.
	QSPI_SCRAMBCTRL_ENABLE        = 0x1 // Bit ENABLE.
	QSPI_SCRAMBCTRL_RANDOMDIS_Pos = 0x1 // Position of RANDOMDIS field.
	QSPI_SCRAMBCTRL_RANDOMDIS_Msk = 0x2 // Bit mask of RANDOMDIS field.
	QSPI_SCRAMBCTRL_RANDOMDIS     = 0x2 // Bit RANDOMDIS.

	// SCRAMBKEY: Scrambling Key
	QSPI_SCRAMBKEY_KEY_Pos = 0x0        // Position of KEY field.
	QSPI_SCRAMBKEY_KEY_Msk = 0xffffffff // Bit mask of KEY field.
)

// Bitfields for RAMECC: RAM ECC
const (
	// INTENCLR: Interrupt Enable Clear
	RAMECC_INTENCLR_SINGLEE_Pos = 0x0 // Position of SINGLEE field.
	RAMECC_INTENCLR_SINGLEE_Msk = 0x1 // Bit mask of SINGLEE field.
	RAMECC_INTENCLR_SINGLEE     = 0x1 // Bit SINGLEE.
	RAMECC_INTENCLR_DUALE_Pos   = 0x1 // Position of DUALE field.
	RAMECC_INTENCLR_DUALE_Msk   = 0x2 // Bit mask of DUALE field.
	RAMECC_INTENCLR_DUALE       = 0x2 // Bit DUALE.

	// INTENSET: Interrupt Enable Set
	RAMECC_INTENSET_SINGLEE_Pos = 0x0 // Position of SINGLEE field.
	RAMECC_INTENSET_SINGLEE_Msk = 0x1 // Bit mask of SINGLEE field.
	RAMECC_INTENSET_SINGLEE     = 0x1 // Bit SINGLEE.
	RAMECC_INTENSET_DUALE_Pos   = 0x1 // Position of DUALE field.
	RAMECC_INTENSET_DUALE_Msk   = 0x2 // Bit mask of DUALE field.
	RAMECC_INTENSET_DUALE       = 0x2 // Bit DUALE.

	// INTFLAG: Interrupt Flag
	RAMECC_INTFLAG_SINGLEE_Pos = 0x0 // Position of SINGLEE field.
	RAMECC_INTFLAG_SINGLEE_Msk = 0x1 // Bit mask of SINGLEE field.
	RAMECC_INTFLAG_SINGLEE     = 0x1 // Bit SINGLEE.
	RAMECC_INTFLAG_DUALE_Pos   = 0x1 // Position of DUALE field.
	RAMECC_INTFLAG_DUALE_Msk   = 0x2 // Bit mask of DUALE field.
	RAMECC_INTFLAG_DUALE       = 0x2 // Bit DUALE.

	// STATUS: Status
	RAMECC_STATUS_ECCDIS_Pos = 0x0 // Position of ECCDIS field.
	RAMECC_STATUS_ECCDIS_Msk = 0x1 // Bit mask of ECCDIS field.
	RAMECC_STATUS_ECCDIS     = 0x1 // Bit ECCDIS.

	// ERRADDR: Error Address
	RAMECC_ERRADDR_ERRADDR_Pos = 0x0     // Position of ERRADDR field.
	RAMECC_ERRADDR_ERRADDR_Msk = 0x1ffff // Bit mask of ERRADDR field.

	// DBGCTRL: Debug Control
	RAMECC_DBGCTRL_ECCDIS_Pos  = 0x0 // Position of ECCDIS field.
	RAMECC_DBGCTRL_ECCDIS_Msk  = 0x1 // Bit mask of ECCDIS field.
	RAMECC_DBGCTRL_ECCDIS      = 0x1 // Bit ECCDIS.
	RAMECC_DBGCTRL_ECCELOG_Pos = 0x1 // Position of ECCELOG field.
	RAMECC_DBGCTRL_ECCELOG_Msk = 0x2 // Bit mask of ECCELOG field.
	RAMECC_DBGCTRL_ECCELOG     = 0x2 // Bit ECCELOG.
)

// Bitfields for RSTC: Reset Controller
const (
	// RCAUSE: Reset Cause
	RSTC_RCAUSE_POR_Pos     = 0x0  // Position of POR field.
	RSTC_RCAUSE_POR_Msk     = 0x1  // Bit mask of POR field.
	RSTC_RCAUSE_POR         = 0x1  // Bit POR.
	RSTC_RCAUSE_BODCORE_Pos = 0x1  // Position of BODCORE field.
	RSTC_RCAUSE_BODCORE_Msk = 0x2  // Bit mask of BODCORE field.
	RSTC_RCAUSE_BODCORE     = 0x2  // Bit BODCORE.
	RSTC_RCAUSE_BODVDD_Pos  = 0x2  // Position of BODVDD field.
	RSTC_RCAUSE_BODVDD_Msk  = 0x4  // Bit mask of BODVDD field.
	RSTC_RCAUSE_BODVDD      = 0x4  // Bit BODVDD.
	RSTC_RCAUSE_NVM_Pos     = 0x3  // Position of NVM field.
	RSTC_RCAUSE_NVM_Msk     = 0x8  // Bit mask of NVM field.
	RSTC_RCAUSE_NVM         = 0x8  // Bit NVM.
	RSTC_RCAUSE_EXT_Pos     = 0x4  // Position of EXT field.
	RSTC_RCAUSE_EXT_Msk     = 0x10 // Bit mask of EXT field.
	RSTC_RCAUSE_EXT         = 0x10 // Bit EXT.
	RSTC_RCAUSE_WDT_Pos     = 0x5  // Position of WDT field.
	RSTC_RCAUSE_WDT_Msk     = 0x20 // Bit mask of WDT field.
	RSTC_RCAUSE_WDT         = 0x20 // Bit WDT.
	RSTC_RCAUSE_SYST_Pos    = 0x6  // Position of SYST field.
	RSTC_RCAUSE_SYST_Msk    = 0x40 // Bit mask of SYST field.
	RSTC_RCAUSE_SYST        = 0x40 // Bit SYST.
	RSTC_RCAUSE_BACKUP_Pos  = 0x7  // Position of BACKUP field.
	RSTC_RCAUSE_BACKUP_Msk  = 0x80 // Bit mask of BACKUP field.
	RSTC_RCAUSE_BACKUP      = 0x80 // Bit BACKUP.

	// BKUPEXIT: Backup Exit Source
	RSTC_BKUPEXIT_RTC_Pos  = 0x1  // Position of RTC field.
	RSTC_BKUPEXIT_RTC_Msk  = 0x2  // Bit mask of RTC field.
	RSTC_BKUPEXIT_RTC      = 0x2  // Bit RTC.
	RSTC_BKUPEXIT_BBPS_Pos = 0x2  // Position of BBPS field.
	RSTC_BKUPEXIT_BBPS_Msk = 0x4  // Bit mask of BBPS field.
	RSTC_BKUPEXIT_BBPS     = 0x4  // Bit BBPS.
	RSTC_BKUPEXIT_HIB_Pos  = 0x7  // Position of HIB field.
	RSTC_BKUPEXIT_HIB_Msk  = 0x80 // Bit mask of HIB field.
	RSTC_BKUPEXIT_HIB      = 0x80 // Bit HIB.
)

// Bitfields for RTC: Real-Time Counter
const ()

// Bitfields for RTC_MODE0: Real-Time Counter - MODE0
const (
	// CTRLA: MODE0 Control A
	RTC_MODE0_CTRLA_SWRST_Pos         = 0x0    // Position of SWRST field.
	RTC_MODE0_CTRLA_SWRST_Msk         = 0x1    // Bit mask of SWRST field.
	RTC_MODE0_CTRLA_SWRST             = 0x1    // Bit SWRST.
	RTC_MODE0_CTRLA_ENABLE_Pos        = 0x1    // Position of ENABLE field.
	RTC_MODE0_CTRLA_ENABLE_Msk        = 0x2    // Bit mask of ENABLE field.
	RTC_MODE0_CTRLA_ENABLE            = 0x2    // Bit ENABLE.
	RTC_MODE0_CTRLA_MODE_Pos          = 0x2    // Position of MODE field.
	RTC_MODE0_CTRLA_MODE_Msk          = 0xc    // Bit mask of MODE field.
	RTC_MODE0_CTRLA_MODE_COUNT32      = 0x0    // Mode 0: 32-bit Counter
	RTC_MODE0_CTRLA_MODE_COUNT16      = 0x1    // Mode 1: 16-bit Counter
	RTC_MODE0_CTRLA_MODE_CLOCK        = 0x2    // Mode 2: Clock/Calendar
	RTC_MODE0_CTRLA_MATCHCLR_Pos      = 0x7    // Position of MATCHCLR field.
	RTC_MODE0_CTRLA_MATCHCLR_Msk      = 0x80   // Bit mask of MATCHCLR field.
	RTC_MODE0_CTRLA_MATCHCLR          = 0x80   // Bit MATCHCLR.
	RTC_MODE0_CTRLA_PRESCALER_Pos     = 0x8    // Position of PRESCALER field.
	RTC_MODE0_CTRLA_PRESCALER_Msk     = 0xf00  // Bit mask of PRESCALER field.
	RTC_MODE0_CTRLA_PRESCALER_OFF     = 0x0    // CLK_RTC_CNT = GCLK_RTC/1
	RTC_MODE0_CTRLA_PRESCALER_DIV1    = 0x1    // CLK_RTC_CNT = GCLK_RTC/1
	RTC_MODE0_CTRLA_PRESCALER_DIV2    = 0x2    // CLK_RTC_CNT = GCLK_RTC/2
	RTC_MODE0_CTRLA_PRESCALER_DIV4    = 0x3    // CLK_RTC_CNT = GCLK_RTC/4
	RTC_MODE0_CTRLA_PRESCALER_DIV8    = 0x4    // CLK_RTC_CNT = GCLK_RTC/8
	RTC_MODE0_CTRLA_PRESCALER_DIV16   = 0x5    // CLK_RTC_CNT = GCLK_RTC/16
	RTC_MODE0_CTRLA_PRESCALER_DIV32   = 0x6    // CLK_RTC_CNT = GCLK_RTC/32
	RTC_MODE0_CTRLA_PRESCALER_DIV64   = 0x7    // CLK_RTC_CNT = GCLK_RTC/64
	RTC_MODE0_CTRLA_PRESCALER_DIV128  = 0x8    // CLK_RTC_CNT = GCLK_RTC/128
	RTC_MODE0_CTRLA_PRESCALER_DIV256  = 0x9    // CLK_RTC_CNT = GCLK_RTC/256
	RTC_MODE0_CTRLA_PRESCALER_DIV512  = 0xa    // CLK_RTC_CNT = GCLK_RTC/512
	RTC_MODE0_CTRLA_PRESCALER_DIV1024 = 0xb    // CLK_RTC_CNT = GCLK_RTC/1024
	RTC_MODE0_CTRLA_BKTRST_Pos        = 0xd    // Position of BKTRST field.
	RTC_MODE0_CTRLA_BKTRST_Msk        = 0x2000 // Bit mask of BKTRST field.
	RTC_MODE0_CTRLA_BKTRST            = 0x2000 // Bit BKTRST.
	RTC_MODE0_CTRLA_GPTRST_Pos        = 0xe    // Position of GPTRST field.
	RTC_MODE0_CTRLA_GPTRST_Msk        = 0x4000 // Bit mask of GPTRST field.
	RTC_MODE0_CTRLA_GPTRST            = 0x4000 // Bit GPTRST.
	RTC_MODE0_CTRLA_COUNTSYNC_Pos     = 0xf    // Position of COUNTSYNC field.
	RTC_MODE0_CTRLA_COUNTSYNC_Msk     = 0x8000 // Bit mask of COUNTSYNC field.
	RTC_MODE0_CTRLA_COUNTSYNC         = 0x8000 // Bit COUNTSYNC.

	// CTRLB: MODE0 Control B
	RTC_MODE0_CTRLB_GP0EN_Pos    = 0x0    // Position of GP0EN field.
	RTC_MODE0_CTRLB_GP0EN_Msk    = 0x1    // Bit mask of GP0EN field.
	RTC_MODE0_CTRLB_GP0EN        = 0x1    // Bit GP0EN.
	RTC_MODE0_CTRLB_GP2EN_Pos    = 0x1    // Position of GP2EN field.
	RTC_MODE0_CTRLB_GP2EN_Msk    = 0x2    // Bit mask of GP2EN field.
	RTC_MODE0_CTRLB_GP2EN        = 0x2    // Bit GP2EN.
	RTC_MODE0_CTRLB_DEBMAJ_Pos   = 0x4    // Position of DEBMAJ field.
	RTC_MODE0_CTRLB_DEBMAJ_Msk   = 0x10   // Bit mask of DEBMAJ field.
	RTC_MODE0_CTRLB_DEBMAJ       = 0x10   // Bit DEBMAJ.
	RTC_MODE0_CTRLB_DEBASYNC_Pos = 0x5    // Position of DEBASYNC field.
	RTC_MODE0_CTRLB_DEBASYNC_Msk = 0x20   // Bit mask of DEBASYNC field.
	RTC_MODE0_CTRLB_DEBASYNC     = 0x20   // Bit DEBASYNC.
	RTC_MODE0_CTRLB_RTCOUT_Pos   = 0x6    // Position of RTCOUT field.
	RTC_MODE0_CTRLB_RTCOUT_Msk   = 0x40   // Bit mask of RTCOUT field.
	RTC_MODE0_CTRLB_RTCOUT       = 0x40   // Bit RTCOUT.
	RTC_MODE0_CTRLB_DMAEN_Pos    = 0x7    // Position of DMAEN field.
	RTC_MODE0_CTRLB_DMAEN_Msk    = 0x80   // Bit mask of DMAEN field.
	RTC_MODE0_CTRLB_DMAEN        = 0x80   // Bit DMAEN.
	RTC_MODE0_CTRLB_DEBF_Pos     = 0x8    // Position of DEBF field.
	RTC_MODE0_CTRLB_DEBF_Msk     = 0x700  // Bit mask of DEBF field.
	RTC_MODE0_CTRLB_DEBF_DIV2    = 0x0    // CLK_RTC_DEB = CLK_RTC/2
	RTC_MODE0_CTRLB_DEBF_DIV4    = 0x1    // CLK_RTC_DEB = CLK_RTC/4
	RTC_MODE0_CTRLB_DEBF_DIV8    = 0x2    // CLK_RTC_DEB = CLK_RTC/8
	RTC_MODE0_CTRLB_DEBF_DIV16   = 0x3    // CLK_RTC_DEB = CLK_RTC/16
	RTC_MODE0_CTRLB_DEBF_DIV32   = 0x4    // CLK_RTC_DEB = CLK_RTC/32
	RTC_MODE0_CTRLB_DEBF_DIV64   = 0x5    // CLK_RTC_DEB = CLK_RTC/64
	RTC_MODE0_CTRLB_DEBF_DIV128  = 0x6    // CLK_RTC_DEB = CLK_RTC/128
	RTC_MODE0_CTRLB_DEBF_DIV256  = 0x7    // CLK_RTC_DEB = CLK_RTC/256
	RTC_MODE0_CTRLB_ACTF_Pos     = 0xc    // Position of ACTF field.
	RTC_MODE0_CTRLB_ACTF_Msk     = 0x7000 // Bit mask of ACTF field.
	RTC_MODE0_CTRLB_ACTF_DIV2    = 0x0    // CLK_RTC_OUT = CLK_RTC/2
	RTC_MODE0_CTRLB_ACTF_DIV4    = 0x1    // CLK_RTC_OUT = CLK_RTC/4
	RTC_MODE0_CTRLB_ACTF_DIV8    = 0x2    // CLK_RTC_OUT = CLK_RTC/8
	RTC_MODE0_CTRLB_ACTF_DIV16   = 0x3    // CLK_RTC_OUT = CLK_RTC/16
	RTC_MODE0_CTRLB_ACTF_DIV32   = 0x4    // CLK_RTC_OUT = CLK_RTC/32
	RTC_MODE0_CTRLB_ACTF_DIV64   = 0x5    // CLK_RTC_OUT = CLK_RTC/64
	RTC_MODE0_CTRLB_ACTF_DIV128  = 0x6    // CLK_RTC_OUT = CLK_RTC/128
	RTC_MODE0_CTRLB_ACTF_DIV256  = 0x7    // CLK_RTC_OUT = CLK_RTC/256

	// EVCTRL: MODE0 Event Control
	RTC_MODE0_EVCTRL_PEREO0_Pos   = 0x0     // Position of PEREO0 field.
	RTC_MODE0_EVCTRL_PEREO0_Msk   = 0x1     // Bit mask of PEREO0 field.
	RTC_MODE0_EVCTRL_PEREO0       = 0x1     // Bit PEREO0.
	RTC_MODE0_EVCTRL_PEREO1_Pos   = 0x1     // Position of PEREO1 field.
	RTC_MODE0_EVCTRL_PEREO1_Msk   = 0x2     // Bit mask of PEREO1 field.
	RTC_MODE0_EVCTRL_PEREO1       = 0x2     // Bit PEREO1.
	RTC_MODE0_EVCTRL_PEREO2_Pos   = 0x2     // Position of PEREO2 field.
	RTC_MODE0_EVCTRL_PEREO2_Msk   = 0x4     // Bit mask of PEREO2 field.
	RTC_MODE0_EVCTRL_PEREO2       = 0x4     // Bit PEREO2.
	RTC_MODE0_EVCTRL_PEREO3_Pos   = 0x3     // Position of PEREO3 field.
	RTC_MODE0_EVCTRL_PEREO3_Msk   = 0x8     // Bit mask of PEREO3 field.
	RTC_MODE0_EVCTRL_PEREO3       = 0x8     // Bit PEREO3.
	RTC_MODE0_EVCTRL_PEREO4_Pos   = 0x4     // Position of PEREO4 field.
	RTC_MODE0_EVCTRL_PEREO4_Msk   = 0x10    // Bit mask of PEREO4 field.
	RTC_MODE0_EVCTRL_PEREO4       = 0x10    // Bit PEREO4.
	RTC_MODE0_EVCTRL_PEREO5_Pos   = 0x5     // Position of PEREO5 field.
	RTC_MODE0_EVCTRL_PEREO5_Msk   = 0x20    // Bit mask of PEREO5 field.
	RTC_MODE0_EVCTRL_PEREO5       = 0x20    // Bit PEREO5.
	RTC_MODE0_EVCTRL_PEREO6_Pos   = 0x6     // Position of PEREO6 field.
	RTC_MODE0_EVCTRL_PEREO6_Msk   = 0x40    // Bit mask of PEREO6 field.
	RTC_MODE0_EVCTRL_PEREO6       = 0x40    // Bit PEREO6.
	RTC_MODE0_EVCTRL_PEREO7_Pos   = 0x7     // Position of PEREO7 field.
	RTC_MODE0_EVCTRL_PEREO7_Msk   = 0x80    // Bit mask of PEREO7 field.
	RTC_MODE0_EVCTRL_PEREO7       = 0x80    // Bit PEREO7.
	RTC_MODE0_EVCTRL_CMPEO0_Pos   = 0x8     // Position of CMPEO0 field.
	RTC_MODE0_EVCTRL_CMPEO0_Msk   = 0x100   // Bit mask of CMPEO0 field.
	RTC_MODE0_EVCTRL_CMPEO0       = 0x100   // Bit CMPEO0.
	RTC_MODE0_EVCTRL_CMPEO1_Pos   = 0x9     // Position of CMPEO1 field.
	RTC_MODE0_EVCTRL_CMPEO1_Msk   = 0x200   // Bit mask of CMPEO1 field.
	RTC_MODE0_EVCTRL_CMPEO1       = 0x200   // Bit CMPEO1.
	RTC_MODE0_EVCTRL_TAMPEREO_Pos = 0xe     // Position of TAMPEREO field.
	RTC_MODE0_EVCTRL_TAMPEREO_Msk = 0x4000  // Bit mask of TAMPEREO field.
	RTC_MODE0_EVCTRL_TAMPEREO     = 0x4000  // Bit TAMPEREO.
	RTC_MODE0_EVCTRL_OVFEO_Pos    = 0xf     // Position of OVFEO field.
	RTC_MODE0_EVCTRL_OVFEO_Msk    = 0x8000  // Bit mask of OVFEO field.
	RTC_MODE0_EVCTRL_OVFEO        = 0x8000  // Bit OVFEO.
	RTC_MODE0_EVCTRL_TAMPEVEI_Pos = 0x10    // Position of TAMPEVEI field.
	RTC_MODE0_EVCTRL_TAMPEVEI_Msk = 0x10000 // Bit mask of TAMPEVEI field.
	RTC_MODE0_EVCTRL_TAMPEVEI     = 0x10000 // Bit TAMPEVEI.

	// INTENCLR: MODE0 Interrupt Enable Clear
	RTC_MODE0_INTENCLR_PER0_Pos   = 0x0    // Position of PER0 field.
	RTC_MODE0_INTENCLR_PER0_Msk   = 0x1    // Bit mask of PER0 field.
	RTC_MODE0_INTENCLR_PER0       = 0x1    // Bit PER0.
	RTC_MODE0_INTENCLR_PER1_Pos   = 0x1    // Position of PER1 field.
	RTC_MODE0_INTENCLR_PER1_Msk   = 0x2    // Bit mask of PER1 field.
	RTC_MODE0_INTENCLR_PER1       = 0x2    // Bit PER1.
	RTC_MODE0_INTENCLR_PER2_Pos   = 0x2    // Position of PER2 field.
	RTC_MODE0_INTENCLR_PER2_Msk   = 0x4    // Bit mask of PER2 field.
	RTC_MODE0_INTENCLR_PER2       = 0x4    // Bit PER2.
	RTC_MODE0_INTENCLR_PER3_Pos   = 0x3    // Position of PER3 field.
	RTC_MODE0_INTENCLR_PER3_Msk   = 0x8    // Bit mask of PER3 field.
	RTC_MODE0_INTENCLR_PER3       = 0x8    // Bit PER3.
	RTC_MODE0_INTENCLR_PER4_Pos   = 0x4    // Position of PER4 field.
	RTC_MODE0_INTENCLR_PER4_Msk   = 0x10   // Bit mask of PER4 field.
	RTC_MODE0_INTENCLR_PER4       = 0x10   // Bit PER4.
	RTC_MODE0_INTENCLR_PER5_Pos   = 0x5    // Position of PER5 field.
	RTC_MODE0_INTENCLR_PER5_Msk   = 0x20   // Bit mask of PER5 field.
	RTC_MODE0_INTENCLR_PER5       = 0x20   // Bit PER5.
	RTC_MODE0_INTENCLR_PER6_Pos   = 0x6    // Position of PER6 field.
	RTC_MODE0_INTENCLR_PER6_Msk   = 0x40   // Bit mask of PER6 field.
	RTC_MODE0_INTENCLR_PER6       = 0x40   // Bit PER6.
	RTC_MODE0_INTENCLR_PER7_Pos   = 0x7    // Position of PER7 field.
	RTC_MODE0_INTENCLR_PER7_Msk   = 0x80   // Bit mask of PER7 field.
	RTC_MODE0_INTENCLR_PER7       = 0x80   // Bit PER7.
	RTC_MODE0_INTENCLR_CMP0_Pos   = 0x8    // Position of CMP0 field.
	RTC_MODE0_INTENCLR_CMP0_Msk   = 0x100  // Bit mask of CMP0 field.
	RTC_MODE0_INTENCLR_CMP0       = 0x100  // Bit CMP0.
	RTC_MODE0_INTENCLR_CMP1_Pos   = 0x9    // Position of CMP1 field.
	RTC_MODE0_INTENCLR_CMP1_Msk   = 0x200  // Bit mask of CMP1 field.
	RTC_MODE0_INTENCLR_CMP1       = 0x200  // Bit CMP1.
	RTC_MODE0_INTENCLR_TAMPER_Pos = 0xe    // Position of TAMPER field.
	RTC_MODE0_INTENCLR_TAMPER_Msk = 0x4000 // Bit mask of TAMPER field.
	RTC_MODE0_INTENCLR_TAMPER     = 0x4000 // Bit TAMPER.
	RTC_MODE0_INTENCLR_OVF_Pos    = 0xf    // Position of OVF field.
	RTC_MODE0_INTENCLR_OVF_Msk    = 0x8000 // Bit mask of OVF field.
	RTC_MODE0_INTENCLR_OVF        = 0x8000 // Bit OVF.

	// INTENSET: MODE0 Interrupt Enable Set
	RTC_MODE0_INTENSET_PER0_Pos   = 0x0    // Position of PER0 field.
	RTC_MODE0_INTENSET_PER0_Msk   = 0x1    // Bit mask of PER0 field.
	RTC_MODE0_INTENSET_PER0       = 0x1    // Bit PER0.
	RTC_MODE0_INTENSET_PER1_Pos   = 0x1    // Position of PER1 field.
	RTC_MODE0_INTENSET_PER1_Msk   = 0x2    // Bit mask of PER1 field.
	RTC_MODE0_INTENSET_PER1       = 0x2    // Bit PER1.
	RTC_MODE0_INTENSET_PER2_Pos   = 0x2    // Position of PER2 field.
	RTC_MODE0_INTENSET_PER2_Msk   = 0x4    // Bit mask of PER2 field.
	RTC_MODE0_INTENSET_PER2       = 0x4    // Bit PER2.
	RTC_MODE0_INTENSET_PER3_Pos   = 0x3    // Position of PER3 field.
	RTC_MODE0_INTENSET_PER3_Msk   = 0x8    // Bit mask of PER3 field.
	RTC_MODE0_INTENSET_PER3       = 0x8    // Bit PER3.
	RTC_MODE0_INTENSET_PER4_Pos   = 0x4    // Position of PER4 field.
	RTC_MODE0_INTENSET_PER4_Msk   = 0x10   // Bit mask of PER4 field.
	RTC_MODE0_INTENSET_PER4       = 0x10   // Bit PER4.
	RTC_MODE0_INTENSET_PER5_Pos   = 0x5    // Position of PER5 field.
	RTC_MODE0_INTENSET_PER5_Msk   = 0x20   // Bit mask of PER5 field.
	RTC_MODE0_INTENSET_PER5       = 0x20   // Bit PER5.
	RTC_MODE0_INTENSET_PER6_Pos   = 0x6    // Position of PER6 field.
	RTC_MODE0_INTENSET_PER6_Msk   = 0x40   // Bit mask of PER6 field.
	RTC_MODE0_INTENSET_PER6       = 0x40   // Bit PER6.
	RTC_MODE0_INTENSET_PER7_Pos   = 0x7    // Position of PER7 field.
	RTC_MODE0_INTENSET_PER7_Msk   = 0x80   // Bit mask of PER7 field.
	RTC_MODE0_INTENSET_PER7       = 0x80   // Bit PER7.
	RTC_MODE0_INTENSET_CMP0_Pos   = 0x8    // Position of CMP0 field.
	RTC_MODE0_INTENSET_CMP0_Msk   = 0x100  // Bit mask of CMP0 field.
	RTC_MODE0_INTENSET_CMP0       = 0x100  // Bit CMP0.
	RTC_MODE0_INTENSET_CMP1_Pos   = 0x9    // Position of CMP1 field.
	RTC_MODE0_INTENSET_CMP1_Msk   = 0x200  // Bit mask of CMP1 field.
	RTC_MODE0_INTENSET_CMP1       = 0x200  // Bit CMP1.
	RTC_MODE0_INTENSET_TAMPER_Pos = 0xe    // Position of TAMPER field.
	RTC_MODE0_INTENSET_TAMPER_Msk = 0x4000 // Bit mask of TAMPER field.
	RTC_MODE0_INTENSET_TAMPER     = 0x4000 // Bit TAMPER.
	RTC_MODE0_INTENSET_OVF_Pos    = 0xf    // Position of OVF field.
	RTC_MODE0_INTENSET_OVF_Msk    = 0x8000 // Bit mask of OVF field.
	RTC_MODE0_INTENSET_OVF        = 0x8000 // Bit OVF.

	// INTFLAG: MODE0 Interrupt Flag Status and Clear
	RTC_MODE0_INTFLAG_PER0_Pos   = 0x0    // Position of PER0 field.
	RTC_MODE0_INTFLAG_PER0_Msk   = 0x1    // Bit mask of PER0 field.
	RTC_MODE0_INTFLAG_PER0       = 0x1    // Bit PER0.
	RTC_MODE0_INTFLAG_PER1_Pos   = 0x1    // Position of PER1 field.
	RTC_MODE0_INTFLAG_PER1_Msk   = 0x2    // Bit mask of PER1 field.
	RTC_MODE0_INTFLAG_PER1       = 0x2    // Bit PER1.
	RTC_MODE0_INTFLAG_PER2_Pos   = 0x2    // Position of PER2 field.
	RTC_MODE0_INTFLAG_PER2_Msk   = 0x4    // Bit mask of PER2 field.
	RTC_MODE0_INTFLAG_PER2       = 0x4    // Bit PER2.
	RTC_MODE0_INTFLAG_PER3_Pos   = 0x3    // Position of PER3 field.
	RTC_MODE0_INTFLAG_PER3_Msk   = 0x8    // Bit mask of PER3 field.
	RTC_MODE0_INTFLAG_PER3       = 0x8    // Bit PER3.
	RTC_MODE0_INTFLAG_PER4_Pos   = 0x4    // Position of PER4 field.
	RTC_MODE0_INTFLAG_PER4_Msk   = 0x10   // Bit mask of PER4 field.
	RTC_MODE0_INTFLAG_PER4       = 0x10   // Bit PER4.
	RTC_MODE0_INTFLAG_PER5_Pos   = 0x5    // Position of PER5 field.
	RTC_MODE0_INTFLAG_PER5_Msk   = 0x20   // Bit mask of PER5 field.
	RTC_MODE0_INTFLAG_PER5       = 0x20   // Bit PER5.
	RTC_MODE0_INTFLAG_PER6_Pos   = 0x6    // Position of PER6 field.
	RTC_MODE0_INTFLAG_PER6_Msk   = 0x40   // Bit mask of PER6 field.
	RTC_MODE0_INTFLAG_PER6       = 0x40   // Bit PER6.
	RTC_MODE0_INTFLAG_PER7_Pos   = 0x7    // Position of PER7 field.
	RTC_MODE0_INTFLAG_PER7_Msk   = 0x80   // Bit mask of PER7 field.
	RTC_MODE0_INTFLAG_PER7       = 0x80   // Bit PER7.
	RTC_MODE0_INTFLAG_CMP0_Pos   = 0x8    // Position of CMP0 field.
	RTC_MODE0_INTFLAG_CMP0_Msk   = 0x100  // Bit mask of CMP0 field.
	RTC_MODE0_INTFLAG_CMP0       = 0x100  // Bit CMP0.
	RTC_MODE0_INTFLAG_CMP1_Pos   = 0x9    // Position of CMP1 field.
	RTC_MODE0_INTFLAG_CMP1_Msk   = 0x200  // Bit mask of CMP1 field.
	RTC_MODE0_INTFLAG_CMP1       = 0x200  // Bit CMP1.
	RTC_MODE0_INTFLAG_TAMPER_Pos = 0xe    // Position of TAMPER field.
	RTC_MODE0_INTFLAG_TAMPER_Msk = 0x4000 // Bit mask of TAMPER field.
	RTC_MODE0_INTFLAG_TAMPER     = 0x4000 // Bit TAMPER.
	RTC_MODE0_INTFLAG_OVF_Pos    = 0xf    // Position of OVF field.
	RTC_MODE0_INTFLAG_OVF_Msk    = 0x8000 // Bit mask of OVF field.
	RTC_MODE0_INTFLAG_OVF        = 0x8000 // Bit OVF.

	// DBGCTRL: Debug Control
	RTC_MODE0_DBGCTRL_DBGRUN_Pos = 0x0 // Position of DBGRUN field.
	RTC_MODE0_DBGCTRL_DBGRUN_Msk = 0x1 // Bit mask of DBGRUN field.
	RTC_MODE0_DBGCTRL_DBGRUN     = 0x1 // Bit DBGRUN.

	// SYNCBUSY: MODE0 Synchronization Busy Status
	RTC_MODE0_SYNCBUSY_SWRST_Pos     = 0x0     // Position of SWRST field.
	RTC_MODE0_SYNCBUSY_SWRST_Msk     = 0x1     // Bit mask of SWRST field.
	RTC_MODE0_SYNCBUSY_SWRST         = 0x1     // Bit SWRST.
	RTC_MODE0_SYNCBUSY_ENABLE_Pos    = 0x1     // Position of ENABLE field.
	RTC_MODE0_SYNCBUSY_ENABLE_Msk    = 0x2     // Bit mask of ENABLE field.
	RTC_MODE0_SYNCBUSY_ENABLE        = 0x2     // Bit ENABLE.
	RTC_MODE0_SYNCBUSY_FREQCORR_Pos  = 0x2     // Position of FREQCORR field.
	RTC_MODE0_SYNCBUSY_FREQCORR_Msk  = 0x4     // Bit mask of FREQCORR field.
	RTC_MODE0_SYNCBUSY_FREQCORR      = 0x4     // Bit FREQCORR.
	RTC_MODE0_SYNCBUSY_COUNT_Pos     = 0x3     // Position of COUNT field.
	RTC_MODE0_SYNCBUSY_COUNT_Msk     = 0x8     // Bit mask of COUNT field.
	RTC_MODE0_SYNCBUSY_COUNT         = 0x8     // Bit COUNT.
	RTC_MODE0_SYNCBUSY_COMP0_Pos     = 0x5     // Position of COMP0 field.
	RTC_MODE0_SYNCBUSY_COMP0_Msk     = 0x20    // Bit mask of COMP0 field.
	RTC_MODE0_SYNCBUSY_COMP0         = 0x20    // Bit COMP0.
	RTC_MODE0_SYNCBUSY_COMP1_Pos     = 0x6     // Position of COMP1 field.
	RTC_MODE0_SYNCBUSY_COMP1_Msk     = 0x40    // Bit mask of COMP1 field.
	RTC_MODE0_SYNCBUSY_COMP1         = 0x40    // Bit COMP1.
	RTC_MODE0_SYNCBUSY_COUNTSYNC_Pos = 0xf     // Position of COUNTSYNC field.
	RTC_MODE0_SYNCBUSY_COUNTSYNC_Msk = 0x8000  // Bit mask of COUNTSYNC field.
	RTC_MODE0_SYNCBUSY_COUNTSYNC     = 0x8000  // Bit COUNTSYNC.
	RTC_MODE0_SYNCBUSY_GP0_Pos       = 0x10    // Position of GP0 field.
	RTC_MODE0_SYNCBUSY_GP0_Msk       = 0x10000 // Bit mask of GP0 field.
	RTC_MODE0_SYNCBUSY_GP0           = 0x10000 // Bit GP0.
	RTC_MODE0_SYNCBUSY_GP1_Pos       = 0x11    // Position of GP1 field.
	RTC_MODE0_SYNCBUSY_GP1_Msk       = 0x20000 // Bit mask of GP1 field.
	RTC_MODE0_SYNCBUSY_GP1           = 0x20000 // Bit GP1.
	RTC_MODE0_SYNCBUSY_GP2_Pos       = 0x12    // Position of GP2 field.
	RTC_MODE0_SYNCBUSY_GP2_Msk       = 0x40000 // Bit mask of GP2 field.
	RTC_MODE0_SYNCBUSY_GP2           = 0x40000 // Bit GP2.
	RTC_MODE0_SYNCBUSY_GP3_Pos       = 0x13    // Position of GP3 field.
	RTC_MODE0_SYNCBUSY_GP3_Msk       = 0x80000 // Bit mask of GP3 field.
	RTC_MODE0_SYNCBUSY_GP3           = 0x80000 // Bit GP3.

	// FREQCORR: Frequency Correction
	RTC_MODE0_FREQCORR_VALUE_Pos = 0x0  // Position of VALUE field.
	RTC_MODE0_FREQCORR_VALUE_Msk = 0x7f // Bit mask of VALUE field.
	RTC_MODE0_FREQCORR_SIGN_Pos  = 0x7  // Position of SIGN field.
	RTC_MODE0_FREQCORR_SIGN_Msk  = 0x80 // Bit mask of SIGN field.
	RTC_MODE0_FREQCORR_SIGN      = 0x80 // Bit SIGN.

	// COUNT: MODE0 Counter Value
	RTC_MODE0_COUNT_COUNT_Pos = 0x0        // Position of COUNT field.
	RTC_MODE0_COUNT_COUNT_Msk = 0xffffffff // Bit mask of COUNT field.

	// COMP: MODE0 Compare n Value
	RTC_MODE0_COMP_COMP_Pos = 0x0        // Position of COMP field.
	RTC_MODE0_COMP_COMP_Msk = 0xffffffff // Bit mask of COMP field.

	// GP: General Purpose
	RTC_MODE0_GP_GP_Pos = 0x0        // Position of GP field.
	RTC_MODE0_GP_GP_Msk = 0xffffffff // Bit mask of GP field.

	// TAMPCTRL: Tamper Control
	RTC_MODE0_TAMPCTRL_IN0ACT_Pos     = 0x0        // Position of IN0ACT field.
	RTC_MODE0_TAMPCTRL_IN0ACT_Msk     = 0x3        // Bit mask of IN0ACT field.
	RTC_MODE0_TAMPCTRL_IN0ACT_OFF     = 0x0        // Off (Disabled)
	RTC_MODE0_TAMPCTRL_IN0ACT_WAKE    = 0x1        // Wake without timestamp
	RTC_MODE0_TAMPCTRL_IN0ACT_CAPTURE = 0x2        // Capture timestamp
	RTC_MODE0_TAMPCTRL_IN0ACT_ACTL    = 0x3        // Compare IN0 to OUT
	RTC_MODE0_TAMPCTRL_IN1ACT_Pos     = 0x2        // Position of IN1ACT field.
	RTC_MODE0_TAMPCTRL_IN1ACT_Msk     = 0xc        // Bit mask of IN1ACT field.
	RTC_MODE0_TAMPCTRL_IN1ACT_OFF     = 0x0        // Off (Disabled)
	RTC_MODE0_TAMPCTRL_IN1ACT_WAKE    = 0x1        // Wake without timestamp
	RTC_MODE0_TAMPCTRL_IN1ACT_CAPTURE = 0x2        // Capture timestamp
	RTC_MODE0_TAMPCTRL_IN1ACT_ACTL    = 0x3        // Compare IN1 to OUT
	RTC_MODE0_TAMPCTRL_IN2ACT_Pos     = 0x4        // Position of IN2ACT field.
	RTC_MODE0_TAMPCTRL_IN2ACT_Msk     = 0x30       // Bit mask of IN2ACT field.
	RTC_MODE0_TAMPCTRL_IN2ACT_OFF     = 0x0        // Off (Disabled)
	RTC_MODE0_TAMPCTRL_IN2ACT_WAKE    = 0x1        // Wake without timestamp
	RTC_MODE0_TAMPCTRL_IN2ACT_CAPTURE = 0x2        // Capture timestamp
	RTC_MODE0_TAMPCTRL_IN2ACT_ACTL    = 0x3        // Compare IN2 to OUT
	RTC_MODE0_TAMPCTRL_IN3ACT_Pos     = 0x6        // Position of IN3ACT field.
	RTC_MODE0_TAMPCTRL_IN3ACT_Msk     = 0xc0       // Bit mask of IN3ACT field.
	RTC_MODE0_TAMPCTRL_IN3ACT_OFF     = 0x0        // Off (Disabled)
	RTC_MODE0_TAMPCTRL_IN3ACT_WAKE    = 0x1        // Wake without timestamp
	RTC_MODE0_TAMPCTRL_IN3ACT_CAPTURE = 0x2        // Capture timestamp
	RTC_MODE0_TAMPCTRL_IN3ACT_ACTL    = 0x3        // Compare IN3 to OUT
	RTC_MODE0_TAMPCTRL_IN4ACT_Pos     = 0x8        // Position of IN4ACT field.
	RTC_MODE0_TAMPCTRL_IN4ACT_Msk     = 0x300      // Bit mask of IN4ACT field.
	RTC_MODE0_TAMPCTRL_IN4ACT_OFF     = 0x0        // Off (Disabled)
	RTC_MODE0_TAMPCTRL_IN4ACT_WAKE    = 0x1        // Wake without timestamp
	RTC_MODE0_TAMPCTRL_IN4ACT_CAPTURE = 0x2        // Capture timestamp
	RTC_MODE0_TAMPCTRL_IN4ACT_ACTL    = 0x3        // Compare IN4 to OUT
	RTC_MODE0_TAMPCTRL_TAMLVL0_Pos    = 0x10       // Position of TAMLVL0 field.
	RTC_MODE0_TAMPCTRL_TAMLVL0_Msk    = 0x10000    // Bit mask of TAMLVL0 field.
	RTC_MODE0_TAMPCTRL_TAMLVL0        = 0x10000    // Bit TAMLVL0.
	RTC_MODE0_TAMPCTRL_TAMLVL1_Pos    = 0x11       // Position of TAMLVL1 field.
	RTC_MODE0_TAMPCTRL_TAMLVL1_Msk    = 0x20000    // Bit mask of TAMLVL1 field.
	RTC_MODE0_TAMPCTRL_TAMLVL1        = 0x20000    // Bit TAMLVL1.
	RTC_MODE0_TAMPCTRL_TAMLVL2_Pos    = 0x12       // Position of TAMLVL2 field.
	RTC_MODE0_TAMPCTRL_TAMLVL2_Msk    = 0x40000    // Bit mask of TAMLVL2 field.
	RTC_MODE0_TAMPCTRL_TAMLVL2        = 0x40000    // Bit TAMLVL2.
	RTC_MODE0_TAMPCTRL_TAMLVL3_Pos    = 0x13       // Position of TAMLVL3 field.
	RTC_MODE0_TAMPCTRL_TAMLVL3_Msk    = 0x80000    // Bit mask of TAMLVL3 field.
	RTC_MODE0_TAMPCTRL_TAMLVL3        = 0x80000    // Bit TAMLVL3.
	RTC_MODE0_TAMPCTRL_TAMLVL4_Pos    = 0x14       // Position of TAMLVL4 field.
	RTC_MODE0_TAMPCTRL_TAMLVL4_Msk    = 0x100000   // Bit mask of TAMLVL4 field.
	RTC_MODE0_TAMPCTRL_TAMLVL4        = 0x100000   // Bit TAMLVL4.
	RTC_MODE0_TAMPCTRL_DEBNC0_Pos     = 0x18       // Position of DEBNC0 field.
	RTC_MODE0_TAMPCTRL_DEBNC0_Msk     = 0x1000000  // Bit mask of DEBNC0 field.
	RTC_MODE0_TAMPCTRL_DEBNC0         = 0x1000000  // Bit DEBNC0.
	RTC_MODE0_TAMPCTRL_DEBNC1_Pos     = 0x19       // Position of DEBNC1 field.
	RTC_MODE0_TAMPCTRL_DEBNC1_Msk     = 0x2000000  // Bit mask of DEBNC1 field.
	RTC_MODE0_TAMPCTRL_DEBNC1         = 0x2000000  // Bit DEBNC1.
	RTC_MODE0_TAMPCTRL_DEBNC2_Pos     = 0x1a       // Position of DEBNC2 field.
	RTC_MODE0_TAMPCTRL_DEBNC2_Msk     = 0x4000000  // Bit mask of DEBNC2 field.
	RTC_MODE0_TAMPCTRL_DEBNC2         = 0x4000000  // Bit DEBNC2.
	RTC_MODE0_TAMPCTRL_DEBNC3_Pos     = 0x1b       // Position of DEBNC3 field.
	RTC_MODE0_TAMPCTRL_DEBNC3_Msk     = 0x8000000  // Bit mask of DEBNC3 field.
	RTC_MODE0_TAMPCTRL_DEBNC3         = 0x8000000  // Bit DEBNC3.
	RTC_MODE0_TAMPCTRL_DEBNC4_Pos     = 0x1c       // Position of DEBNC4 field.
	RTC_MODE0_TAMPCTRL_DEBNC4_Msk     = 0x10000000 // Bit mask of DEBNC4 field.
	RTC_MODE0_TAMPCTRL_DEBNC4         = 0x10000000 // Bit DEBNC4.

	// TIMESTAMP: MODE0 Timestamp
	RTC_MODE0_TIMESTAMP_COUNT_Pos = 0x0        // Position of COUNT field.
	RTC_MODE0_TIMESTAMP_COUNT_Msk = 0xffffffff // Bit mask of COUNT field.

	// TAMPID: Tamper ID
	RTC_MODE0_TAMPID_TAMPID0_Pos = 0x0        // Position of TAMPID0 field.
	RTC_MODE0_TAMPID_TAMPID0_Msk = 0x1        // Bit mask of TAMPID0 field.
	RTC_MODE0_TAMPID_TAMPID0     = 0x1        // Bit TAMPID0.
	RTC_MODE0_TAMPID_TAMPID1_Pos = 0x1        // Position of TAMPID1 field.
	RTC_MODE0_TAMPID_TAMPID1_Msk = 0x2        // Bit mask of TAMPID1 field.
	RTC_MODE0_TAMPID_TAMPID1     = 0x2        // Bit TAMPID1.
	RTC_MODE0_TAMPID_TAMPID2_Pos = 0x2        // Position of TAMPID2 field.
	RTC_MODE0_TAMPID_TAMPID2_Msk = 0x4        // Bit mask of TAMPID2 field.
	RTC_MODE0_TAMPID_TAMPID2     = 0x4        // Bit TAMPID2.
	RTC_MODE0_TAMPID_TAMPID3_Pos = 0x3        // Position of TAMPID3 field.
	RTC_MODE0_TAMPID_TAMPID3_Msk = 0x8        // Bit mask of TAMPID3 field.
	RTC_MODE0_TAMPID_TAMPID3     = 0x8        // Bit TAMPID3.
	RTC_MODE0_TAMPID_TAMPID4_Pos = 0x4        // Position of TAMPID4 field.
	RTC_MODE0_TAMPID_TAMPID4_Msk = 0x10       // Bit mask of TAMPID4 field.
	RTC_MODE0_TAMPID_TAMPID4     = 0x10       // Bit TAMPID4.
	RTC_MODE0_TAMPID_TAMPEVT_Pos = 0x1f       // Position of TAMPEVT field.
	RTC_MODE0_TAMPID_TAMPEVT_Msk = 0x80000000 // Bit mask of TAMPEVT field.
	RTC_MODE0_TAMPID_TAMPEVT     = 0x80000000 // Bit TAMPEVT.

	// BKUP: Backup
	RTC_MODE0_BKUP_BKUP_Pos = 0x0        // Position of BKUP field.
	RTC_MODE0_BKUP_BKUP_Msk = 0xffffffff // Bit mask of BKUP field.
)

// Bitfields for RTC_MODE1: Real-Time Counter - MODE1
const (
	// CTRLA: MODE1 Control A
	RTC_MODE1_CTRLA_SWRST_Pos         = 0x0    // Position of SWRST field.
	RTC_MODE1_CTRLA_SWRST_Msk         = 0x1    // Bit mask of SWRST field.
	RTC_MODE1_CTRLA_SWRST             = 0x1    // Bit SWRST.
	RTC_MODE1_CTRLA_ENABLE_Pos        = 0x1    // Position of ENABLE field.
	RTC_MODE1_CTRLA_ENABLE_Msk        = 0x2    // Bit mask of ENABLE field.
	RTC_MODE1_CTRLA_ENABLE            = 0x2    // Bit ENABLE.
	RTC_MODE1_CTRLA_MODE_Pos          = 0x2    // Position of MODE field.
	RTC_MODE1_CTRLA_MODE_Msk          = 0xc    // Bit mask of MODE field.
	RTC_MODE1_CTRLA_MODE_COUNT32      = 0x0    // Mode 0: 32-bit Counter
	RTC_MODE1_CTRLA_MODE_COUNT16      = 0x1    // Mode 1: 16-bit Counter
	RTC_MODE1_CTRLA_MODE_CLOCK        = 0x2    // Mode 2: Clock/Calendar
	RTC_MODE1_CTRLA_PRESCALER_Pos     = 0x8    // Position of PRESCALER field.
	RTC_MODE1_CTRLA_PRESCALER_Msk     = 0xf00  // Bit mask of PRESCALER field.
	RTC_MODE1_CTRLA_PRESCALER_OFF     = 0x0    // CLK_RTC_CNT = GCLK_RTC/1
	RTC_MODE1_CTRLA_PRESCALER_DIV1    = 0x1    // CLK_RTC_CNT = GCLK_RTC/1
	RTC_MODE1_CTRLA_PRESCALER_DIV2    = 0x2    // CLK_RTC_CNT = GCLK_RTC/2
	RTC_MODE1_CTRLA_PRESCALER_DIV4    = 0x3    // CLK_RTC_CNT = GCLK_RTC/4
	RTC_MODE1_CTRLA_PRESCALER_DIV8    = 0x4    // CLK_RTC_CNT = GCLK_RTC/8
	RTC_MODE1_CTRLA_PRESCALER_DIV16   = 0x5    // CLK_RTC_CNT = GCLK_RTC/16
	RTC_MODE1_CTRLA_PRESCALER_DIV32   = 0x6    // CLK_RTC_CNT = GCLK_RTC/32
	RTC_MODE1_CTRLA_PRESCALER_DIV64   = 0x7    // CLK_RTC_CNT = GCLK_RTC/64
	RTC_MODE1_CTRLA_PRESCALER_DIV128  = 0x8    // CLK_RTC_CNT = GCLK_RTC/128
	RTC_MODE1_CTRLA_PRESCALER_DIV256  = 0x9    // CLK_RTC_CNT = GCLK_RTC/256
	RTC_MODE1_CTRLA_PRESCALER_DIV512  = 0xa    // CLK_RTC_CNT = GCLK_RTC/512
	RTC_MODE1_CTRLA_PRESCALER_DIV1024 = 0xb    // CLK_RTC_CNT = GCLK_RTC/1024
	RTC_MODE1_CTRLA_BKTRST_Pos        = 0xd    // Position of BKTRST field.
	RTC_MODE1_CTRLA_BKTRST_Msk        = 0x2000 // Bit mask of BKTRST field.
	RTC_MODE1_CTRLA_BKTRST            = 0x2000 // Bit BKTRST.
	RTC_MODE1_CTRLA_GPTRST_Pos        = 0xe    // Position of GPTRST field.
	RTC_MODE1_CTRLA_GPTRST_Msk        = 0x4000 // Bit mask of GPTRST field.
	RTC_MODE1_CTRLA_GPTRST            = 0x4000 // Bit GPTRST.
	RTC_MODE1_CTRLA_COUNTSYNC_Pos     = 0xf    // Position of COUNTSYNC field.
	RTC_MODE1_CTRLA_COUNTSYNC_Msk     = 0x8000 // Bit mask of COUNTSYNC field.
	RTC_MODE1_CTRLA_COUNTSYNC         = 0x8000 // Bit COUNTSYNC.

	// CTRLB: MODE1 Control B
	RTC_MODE1_CTRLB_GP0EN_Pos    = 0x0    // Position of GP0EN field.
	RTC_MODE1_CTRLB_GP0EN_Msk    = 0x1    // Bit mask of GP0EN field.
	RTC_MODE1_CTRLB_GP0EN        = 0x1    // Bit GP0EN.
	RTC_MODE1_CTRLB_GP2EN_Pos    = 0x1    // Position of GP2EN field.
	RTC_MODE1_CTRLB_GP2EN_Msk    = 0x2    // Bit mask of GP2EN field.
	RTC_MODE1_CTRLB_GP2EN        = 0x2    // Bit GP2EN.
	RTC_MODE1_CTRLB_DEBMAJ_Pos   = 0x4    // Position of DEBMAJ field.
	RTC_MODE1_CTRLB_DEBMAJ_Msk   = 0x10   // Bit mask of DEBMAJ field.
	RTC_MODE1_CTRLB_DEBMAJ       = 0x10   // Bit DEBMAJ.
	RTC_MODE1_CTRLB_DEBASYNC_Pos = 0x5    // Position of DEBASYNC field.
	RTC_MODE1_CTRLB_DEBASYNC_Msk = 0x20   // Bit mask of DEBASYNC field.
	RTC_MODE1_CTRLB_DEBASYNC     = 0x20   // Bit DEBASYNC.
	RTC_MODE1_CTRLB_RTCOUT_Pos   = 0x6    // Position of RTCOUT field.
	RTC_MODE1_CTRLB_RTCOUT_Msk   = 0x40   // Bit mask of RTCOUT field.
	RTC_MODE1_CTRLB_RTCOUT       = 0x40   // Bit RTCOUT.
	RTC_MODE1_CTRLB_DMAEN_Pos    = 0x7    // Position of DMAEN field.
	RTC_MODE1_CTRLB_DMAEN_Msk    = 0x80   // Bit mask of DMAEN field.
	RTC_MODE1_CTRLB_DMAEN        = 0x80   // Bit DMAEN.
	RTC_MODE1_CTRLB_DEBF_Pos     = 0x8    // Position of DEBF field.
	RTC_MODE1_CTRLB_DEBF_Msk     = 0x700  // Bit mask of DEBF field.
	RTC_MODE1_CTRLB_DEBF_DIV2    = 0x0    // CLK_RTC_DEB = CLK_RTC/2
	RTC_MODE1_CTRLB_DEBF_DIV4    = 0x1    // CLK_RTC_DEB = CLK_RTC/4
	RTC_MODE1_CTRLB_DEBF_DIV8    = 0x2    // CLK_RTC_DEB = CLK_RTC/8
	RTC_MODE1_CTRLB_DEBF_DIV16   = 0x3    // CLK_RTC_DEB = CLK_RTC/16
	RTC_MODE1_CTRLB_DEBF_DIV32   = 0x4    // CLK_RTC_DEB = CLK_RTC/32
	RTC_MODE1_CTRLB_DEBF_DIV64   = 0x5    // CLK_RTC_DEB = CLK_RTC/64
	RTC_MODE1_CTRLB_DEBF_DIV128  = 0x6    // CLK_RTC_DEB = CLK_RTC/128
	RTC_MODE1_CTRLB_DEBF_DIV256  = 0x7    // CLK_RTC_DEB = CLK_RTC/256
	RTC_MODE1_CTRLB_ACTF_Pos     = 0xc    // Position of ACTF field.
	RTC_MODE1_CTRLB_ACTF_Msk     = 0x7000 // Bit mask of ACTF field.
	RTC_MODE1_CTRLB_ACTF_DIV2    = 0x0    // CLK_RTC_OUT = CLK_RTC/2
	RTC_MODE1_CTRLB_ACTF_DIV4    = 0x1    // CLK_RTC_OUT = CLK_RTC/4
	RTC_MODE1_CTRLB_ACTF_DIV8    = 0x2    // CLK_RTC_OUT = CLK_RTC/8
	RTC_MODE1_CTRLB_ACTF_DIV16   = 0x3    // CLK_RTC_OUT = CLK_RTC/16
	RTC_MODE1_CTRLB_ACTF_DIV32   = 0x4    // CLK_RTC_OUT = CLK_RTC/32
	RTC_MODE1_CTRLB_ACTF_DIV64   = 0x5    // CLK_RTC_OUT = CLK_RTC/64
	RTC_MODE1_CTRLB_ACTF_DIV128  = 0x6    // CLK_RTC_OUT = CLK_RTC/128
	RTC_MODE1_CTRLB_ACTF_DIV256  = 0x7    // CLK_RTC_OUT = CLK_RTC/256

	// EVCTRL: MODE1 Event Control
	RTC_MODE1_EVCTRL_PEREO0_Pos   = 0x0     // Position of PEREO0 field.
	RTC_MODE1_EVCTRL_PEREO0_Msk   = 0x1     // Bit mask of PEREO0 field.
	RTC_MODE1_EVCTRL_PEREO0       = 0x1     // Bit PEREO0.
	RTC_MODE1_EVCTRL_PEREO1_Pos   = 0x1     // Position of PEREO1 field.
	RTC_MODE1_EVCTRL_PEREO1_Msk   = 0x2     // Bit mask of PEREO1 field.
	RTC_MODE1_EVCTRL_PEREO1       = 0x2     // Bit PEREO1.
	RTC_MODE1_EVCTRL_PEREO2_Pos   = 0x2     // Position of PEREO2 field.
	RTC_MODE1_EVCTRL_PEREO2_Msk   = 0x4     // Bit mask of PEREO2 field.
	RTC_MODE1_EVCTRL_PEREO2       = 0x4     // Bit PEREO2.
	RTC_MODE1_EVCTRL_PEREO3_Pos   = 0x3     // Position of PEREO3 field.
	RTC_MODE1_EVCTRL_PEREO3_Msk   = 0x8     // Bit mask of PEREO3 field.
	RTC_MODE1_EVCTRL_PEREO3       = 0x8     // Bit PEREO3.
	RTC_MODE1_EVCTRL_PEREO4_Pos   = 0x4     // Position of PEREO4 field.
	RTC_MODE1_EVCTRL_PEREO4_Msk   = 0x10    // Bit mask of PEREO4 field.
	RTC_MODE1_EVCTRL_PEREO4       = 0x10    // Bit PEREO4.
	RTC_MODE1_EVCTRL_PEREO5_Pos   = 0x5     // Position of PEREO5 field.
	RTC_MODE1_EVCTRL_PEREO5_Msk   = 0x20    // Bit mask of PEREO5 field.
	RTC_MODE1_EVCTRL_PEREO5       = 0x20    // Bit PEREO5.
	RTC_MODE1_EVCTRL_PEREO6_Pos   = 0x6     // Position of PEREO6 field.
	RTC_MODE1_EVCTRL_PEREO6_Msk   = 0x40    // Bit mask of PEREO6 field.
	RTC_MODE1_EVCTRL_PEREO6       = 0x40    // Bit PEREO6.
	RTC_MODE1_EVCTRL_PEREO7_Pos   = 0x7     // Position of PEREO7 field.
	RTC_MODE1_EVCTRL_PEREO7_Msk   = 0x80    // Bit mask of PEREO7 field.
	RTC_MODE1_EVCTRL_PEREO7       = 0x80    // Bit PEREO7.
	RTC_MODE1_EVCTRL_CMPEO0_Pos   = 0x8     // Position of CMPEO0 field.
	RTC_MODE1_EVCTRL_CMPEO0_Msk   = 0x100   // Bit mask of CMPEO0 field.
	RTC_MODE1_EVCTRL_CMPEO0       = 0x100   // Bit CMPEO0.
	RTC_MODE1_EVCTRL_CMPEO1_Pos   = 0x9     // Position of CMPEO1 field.
	RTC_MODE1_EVCTRL_CMPEO1_Msk   = 0x200   // Bit mask of CMPEO1 field.
	RTC_MODE1_EVCTRL_CMPEO1       = 0x200   // Bit CMPEO1.
	RTC_MODE1_EVCTRL_CMPEO2_Pos   = 0xa     // Position of CMPEO2 field.
	RTC_MODE1_EVCTRL_CMPEO2_Msk   = 0x400   // Bit mask of CMPEO2 field.
	RTC_MODE1_EVCTRL_CMPEO2       = 0x400   // Bit CMPEO2.
	RTC_MODE1_EVCTRL_CMPEO3_Pos   = 0xb     // Position of CMPEO3 field.
	RTC_MODE1_EVCTRL_CMPEO3_Msk   = 0x800   // Bit mask of CMPEO3 field.
	RTC_MODE1_EVCTRL_CMPEO3       = 0x800   // Bit CMPEO3.
	RTC_MODE1_EVCTRL_TAMPEREO_Pos = 0xe     // Position of TAMPEREO field.
	RTC_MODE1_EVCTRL_TAMPEREO_Msk = 0x4000  // Bit mask of TAMPEREO field.
	RTC_MODE1_EVCTRL_TAMPEREO     = 0x4000  // Bit TAMPEREO.
	RTC_MODE1_EVCTRL_OVFEO_Pos    = 0xf     // Position of OVFEO field.
	RTC_MODE1_EVCTRL_OVFEO_Msk    = 0x8000  // Bit mask of OVFEO field.
	RTC_MODE1_EVCTRL_OVFEO        = 0x8000  // Bit OVFEO.
	RTC_MODE1_EVCTRL_TAMPEVEI_Pos = 0x10    // Position of TAMPEVEI field.
	RTC_MODE1_EVCTRL_TAMPEVEI_Msk = 0x10000 // Bit mask of TAMPEVEI field.
	RTC_MODE1_EVCTRL_TAMPEVEI     = 0x10000 // Bit TAMPEVEI.

	// INTENCLR: MODE1 Interrupt Enable Clear
	RTC_MODE1_INTENCLR_PER0_Pos   = 0x0    // Position of PER0 field.
	RTC_MODE1_INTENCLR_PER0_Msk   = 0x1    // Bit mask of PER0 field.
	RTC_MODE1_INTENCLR_PER0       = 0x1    // Bit PER0.
	RTC_MODE1_INTENCLR_PER1_Pos   = 0x1    // Position of PER1 field.
	RTC_MODE1_INTENCLR_PER1_Msk   = 0x2    // Bit mask of PER1 field.
	RTC_MODE1_INTENCLR_PER1       = 0x2    // Bit PER1.
	RTC_MODE1_INTENCLR_PER2_Pos   = 0x2    // Position of PER2 field.
	RTC_MODE1_INTENCLR_PER2_Msk   = 0x4    // Bit mask of PER2 field.
	RTC_MODE1_INTENCLR_PER2       = 0x4    // Bit PER2.
	RTC_MODE1_INTENCLR_PER3_Pos   = 0x3    // Position of PER3 field.
	RTC_MODE1_INTENCLR_PER3_Msk   = 0x8    // Bit mask of PER3 field.
	RTC_MODE1_INTENCLR_PER3       = 0x8    // Bit PER3.
	RTC_MODE1_INTENCLR_PER4_Pos   = 0x4    // Position of PER4 field.
	RTC_MODE1_INTENCLR_PER4_Msk   = 0x10   // Bit mask of PER4 field.
	RTC_MODE1_INTENCLR_PER4       = 0x10   // Bit PER4.
	RTC_MODE1_INTENCLR_PER5_Pos   = 0x5    // Position of PER5 field.
	RTC_MODE1_INTENCLR_PER5_Msk   = 0x20   // Bit mask of PER5 field.
	RTC_MODE1_INTENCLR_PER5       = 0x20   // Bit PER5.
	RTC_MODE1_INTENCLR_PER6_Pos   = 0x6    // Position of PER6 field.
	RTC_MODE1_INTENCLR_PER6_Msk   = 0x40   // Bit mask of PER6 field.
	RTC_MODE1_INTENCLR_PER6       = 0x40   // Bit PER6.
	RTC_MODE1_INTENCLR_PER7_Pos   = 0x7    // Position of PER7 field.
	RTC_MODE1_INTENCLR_PER7_Msk   = 0x80   // Bit mask of PER7 field.
	RTC_MODE1_INTENCLR_PER7       = 0x80   // Bit PER7.
	RTC_MODE1_INTENCLR_CMP0_Pos   = 0x8    // Position of CMP0 field.
	RTC_MODE1_INTENCLR_CMP0_Msk   = 0x100  // Bit mask of CMP0 field.
	RTC_MODE1_INTENCLR_CMP0       = 0x100  // Bit CMP0.
	RTC_MODE1_INTENCLR_CMP1_Pos   = 0x9    // Position of CMP1 field.
	RTC_MODE1_INTENCLR_CMP1_Msk   = 0x200  // Bit mask of CMP1 field.
	RTC_MODE1_INTENCLR_CMP1       = 0x200  // Bit CMP1.
	RTC_MODE1_INTENCLR_CMP2_Pos   = 0xa    // Position of CMP2 field.
	RTC_MODE1_INTENCLR_CMP2_Msk   = 0x400  // Bit mask of CMP2 field.
	RTC_MODE1_INTENCLR_CMP2       = 0x400  // Bit CMP2.
	RTC_MODE1_INTENCLR_CMP3_Pos   = 0xb    // Position of CMP3 field.
	RTC_MODE1_INTENCLR_CMP3_Msk   = 0x800  // Bit mask of CMP3 field.
	RTC_MODE1_INTENCLR_CMP3       = 0x800  // Bit CMP3.
	RTC_MODE1_INTENCLR_TAMPER_Pos = 0xe    // Position of TAMPER field.
	RTC_MODE1_INTENCLR_TAMPER_Msk = 0x4000 // Bit mask of TAMPER field.
	RTC_MODE1_INTENCLR_TAMPER     = 0x4000 // Bit TAMPER.
	RTC_MODE1_INTENCLR_OVF_Pos    = 0xf    // Position of OVF field.
	RTC_MODE1_INTENCLR_OVF_Msk    = 0x8000 // Bit mask of OVF field.
	RTC_MODE1_INTENCLR_OVF        = 0x8000 // Bit OVF.

	// INTENSET: MODE1 Interrupt Enable Set
	RTC_MODE1_INTENSET_PER0_Pos   = 0x0    // Position of PER0 field.
	RTC_MODE1_INTENSET_PER0_Msk   = 0x1    // Bit mask of PER0 field.
	RTC_MODE1_INTENSET_PER0       = 0x1    // Bit PER0.
	RTC_MODE1_INTENSET_PER1_Pos   = 0x1    // Position of PER1 field.
	RTC_MODE1_INTENSET_PER1_Msk   = 0x2    // Bit mask of PER1 field.
	RTC_MODE1_INTENSET_PER1       = 0x2    // Bit PER1.
	RTC_MODE1_INTENSET_PER2_Pos   = 0x2    // Position of PER2 field.
	RTC_MODE1_INTENSET_PER2_Msk   = 0x4    // Bit mask of PER2 field.
	RTC_MODE1_INTENSET_PER2       = 0x4    // Bit PER2.
	RTC_MODE1_INTENSET_PER3_Pos   = 0x3    // Position of PER3 field.
	RTC_MODE1_INTENSET_PER3_Msk   = 0x8    // Bit mask of PER3 field.
	RTC_MODE1_INTENSET_PER3       = 0x8    // Bit PER3.
	RTC_MODE1_INTENSET_PER4_Pos   = 0x4    // Position of PER4 field.
	RTC_MODE1_INTENSET_PER4_Msk   = 0x10   // Bit mask of PER4 field.
	RTC_MODE1_INTENSET_PER4       = 0x10   // Bit PER4.
	RTC_MODE1_INTENSET_PER5_Pos   = 0x5    // Position of PER5 field.
	RTC_MODE1_INTENSET_PER5_Msk   = 0x20   // Bit mask of PER5 field.
	RTC_MODE1_INTENSET_PER5       = 0x20   // Bit PER5.
	RTC_MODE1_INTENSET_PER6_Pos   = 0x6    // Position of PER6 field.
	RTC_MODE1_INTENSET_PER6_Msk   = 0x40   // Bit mask of PER6 field.
	RTC_MODE1_INTENSET_PER6       = 0x40   // Bit PER6.
	RTC_MODE1_INTENSET_PER7_Pos   = 0x7    // Position of PER7 field.
	RTC_MODE1_INTENSET_PER7_Msk   = 0x80   // Bit mask of PER7 field.
	RTC_MODE1_INTENSET_PER7       = 0x80   // Bit PER7.
	RTC_MODE1_INTENSET_CMP0_Pos   = 0x8    // Position of CMP0 field.
	RTC_MODE1_INTENSET_CMP0_Msk   = 0x100  // Bit mask of CMP0 field.
	RTC_MODE1_INTENSET_CMP0       = 0x100  // Bit CMP0.
	RTC_MODE1_INTENSET_CMP1_Pos   = 0x9    // Position of CMP1 field.
	RTC_MODE1_INTENSET_CMP1_Msk   = 0x200  // Bit mask of CMP1 field.
	RTC_MODE1_INTENSET_CMP1       = 0x200  // Bit CMP1.
	RTC_MODE1_INTENSET_CMP2_Pos   = 0xa    // Position of CMP2 field.
	RTC_MODE1_INTENSET_CMP2_Msk   = 0x400  // Bit mask of CMP2 field.
	RTC_MODE1_INTENSET_CMP2       = 0x400  // Bit CMP2.
	RTC_MODE1_INTENSET_CMP3_Pos   = 0xb    // Position of CMP3 field.
	RTC_MODE1_INTENSET_CMP3_Msk   = 0x800  // Bit mask of CMP3 field.
	RTC_MODE1_INTENSET_CMP3       = 0x800  // Bit CMP3.
	RTC_MODE1_INTENSET_TAMPER_Pos = 0xe    // Position of TAMPER field.
	RTC_MODE1_INTENSET_TAMPER_Msk = 0x4000 // Bit mask of TAMPER field.
	RTC_MODE1_INTENSET_TAMPER     = 0x4000 // Bit TAMPER.
	RTC_MODE1_INTENSET_OVF_Pos    = 0xf    // Position of OVF field.
	RTC_MODE1_INTENSET_OVF_Msk    = 0x8000 // Bit mask of OVF field.
	RTC_MODE1_INTENSET_OVF        = 0x8000 // Bit OVF.

	// INTFLAG: MODE1 Interrupt Flag Status and Clear
	RTC_MODE1_INTFLAG_PER0_Pos   = 0x0    // Position of PER0 field.
	RTC_MODE1_INTFLAG_PER0_Msk   = 0x1    // Bit mask of PER0 field.
	RTC_MODE1_INTFLAG_PER0       = 0x1    // Bit PER0.
	RTC_MODE1_INTFLAG_PER1_Pos   = 0x1    // Position of PER1 field.
	RTC_MODE1_INTFLAG_PER1_Msk   = 0x2    // Bit mask of PER1 field.
	RTC_MODE1_INTFLAG_PER1       = 0x2    // Bit PER1.
	RTC_MODE1_INTFLAG_PER2_Pos   = 0x2    // Position of PER2 field.
	RTC_MODE1_INTFLAG_PER2_Msk   = 0x4    // Bit mask of PER2 field.
	RTC_MODE1_INTFLAG_PER2       = 0x4    // Bit PER2.
	RTC_MODE1_INTFLAG_PER3_Pos   = 0x3    // Position of PER3 field.
	RTC_MODE1_INTFLAG_PER3_Msk   = 0x8    // Bit mask of PER3 field.
	RTC_MODE1_INTFLAG_PER3       = 0x8    // Bit PER3.
	RTC_MODE1_INTFLAG_PER4_Pos   = 0x4    // Position of PER4 field.
	RTC_MODE1_INTFLAG_PER4_Msk   = 0x10   // Bit mask of PER4 field.
	RTC_MODE1_INTFLAG_PER4       = 0x10   // Bit PER4.
	RTC_MODE1_INTFLAG_PER5_Pos   = 0x5    // Position of PER5 field.
	RTC_MODE1_INTFLAG_PER5_Msk   = 0x20   // Bit mask of PER5 field.
	RTC_MODE1_INTFLAG_PER5       = 0x20   // Bit PER5.
	RTC_MODE1_INTFLAG_PER6_Pos   = 0x6    // Position of PER6 field.
	RTC_MODE1_INTFLAG_PER6_Msk   = 0x40   // Bit mask of PER6 field.
	RTC_MODE1_INTFLAG_PER6       = 0x40   // Bit PER6.
	RTC_MODE1_INTFLAG_PER7_Pos   = 0x7    // Position of PER7 field.
	RTC_MODE1_INTFLAG_PER7_Msk   = 0x80   // Bit mask of PER7 field.
	RTC_MODE1_INTFLAG_PER7       = 0x80   // Bit PER7.
	RTC_MODE1_INTFLAG_CMP0_Pos   = 0x8    // Position of CMP0 field.
	RTC_MODE1_INTFLAG_CMP0_Msk   = 0x100  // Bit mask of CMP0 field.
	RTC_MODE1_INTFLAG_CMP0       = 0x100  // Bit CMP0.
	RTC_MODE1_INTFLAG_CMP1_Pos   = 0x9    // Position of CMP1 field.
	RTC_MODE1_INTFLAG_CMP1_Msk   = 0x200  // Bit mask of CMP1 field.
	RTC_MODE1_INTFLAG_CMP1       = 0x200  // Bit CMP1.
	RTC_MODE1_INTFLAG_CMP2_Pos   = 0xa    // Position of CMP2 field.
	RTC_MODE1_INTFLAG_CMP2_Msk   = 0x400  // Bit mask of CMP2 field.
	RTC_MODE1_INTFLAG_CMP2       = 0x400  // Bit CMP2.
	RTC_MODE1_INTFLAG_CMP3_Pos   = 0xb    // Position of CMP3 field.
	RTC_MODE1_INTFLAG_CMP3_Msk   = 0x800  // Bit mask of CMP3 field.
	RTC_MODE1_INTFLAG_CMP3       = 0x800  // Bit CMP3.
	RTC_MODE1_INTFLAG_TAMPER_Pos = 0xe    // Position of TAMPER field.
	RTC_MODE1_INTFLAG_TAMPER_Msk = 0x4000 // Bit mask of TAMPER field.
	RTC_MODE1_INTFLAG_TAMPER     = 0x4000 // Bit TAMPER.
	RTC_MODE1_INTFLAG_OVF_Pos    = 0xf    // Position of OVF field.
	RTC_MODE1_INTFLAG_OVF_Msk    = 0x8000 // Bit mask of OVF field.
	RTC_MODE1_INTFLAG_OVF        = 0x8000 // Bit OVF.

	// DBGCTRL: Debug Control
	RTC_MODE1_DBGCTRL_DBGRUN_Pos = 0x0 // Position of DBGRUN field.
	RTC_MODE1_DBGCTRL_DBGRUN_Msk = 0x1 // Bit mask of DBGRUN field.
	RTC_MODE1_DBGCTRL_DBGRUN     = 0x1 // Bit DBGRUN.

	// SYNCBUSY: MODE1 Synchronization Busy Status
	RTC_MODE1_SYNCBUSY_SWRST_Pos     = 0x0     // Position of SWRST field.
	RTC_MODE1_SYNCBUSY_SWRST_Msk     = 0x1     // Bit mask of SWRST field.
	RTC_MODE1_SYNCBUSY_SWRST         = 0x1     // Bit SWRST.
	RTC_MODE1_SYNCBUSY_ENABLE_Pos    = 0x1     // Position of ENABLE field.
	RTC_MODE1_SYNCBUSY_ENABLE_Msk    = 0x2     // Bit mask of ENABLE field.
	RTC_MODE1_SYNCBUSY_ENABLE        = 0x2     // Bit ENABLE.
	RTC_MODE1_SYNCBUSY_FREQCORR_Pos  = 0x2     // Position of FREQCORR field.
	RTC_MODE1_SYNCBUSY_FREQCORR_Msk  = 0x4     // Bit mask of FREQCORR field.
	RTC_MODE1_SYNCBUSY_FREQCORR      = 0x4     // Bit FREQCORR.
	RTC_MODE1_SYNCBUSY_COUNT_Pos     = 0x3     // Position of COUNT field.
	RTC_MODE1_SYNCBUSY_COUNT_Msk     = 0x8     // Bit mask of COUNT field.
	RTC_MODE1_SYNCBUSY_COUNT         = 0x8     // Bit COUNT.
	RTC_MODE1_SYNCBUSY_PER_Pos       = 0x4     // Position of PER field.
	RTC_MODE1_SYNCBUSY_PER_Msk       = 0x10    // Bit mask of PER field.
	RTC_MODE1_SYNCBUSY_PER           = 0x10    // Bit PER.
	RTC_MODE1_SYNCBUSY_COMP0_Pos     = 0x5     // Position of COMP0 field.
	RTC_MODE1_SYNCBUSY_COMP0_Msk     = 0x20    // Bit mask of COMP0 field.
	RTC_MODE1_SYNCBUSY_COMP0         = 0x20    // Bit COMP0.
	RTC_MODE1_SYNCBUSY_COMP1_Pos     = 0x6     // Position of COMP1 field.
	RTC_MODE1_SYNCBUSY_COMP1_Msk     = 0x40    // Bit mask of COMP1 field.
	RTC_MODE1_SYNCBUSY_COMP1         = 0x40    // Bit COMP1.
	RTC_MODE1_SYNCBUSY_COMP2_Pos     = 0x7     // Position of COMP2 field.
	RTC_MODE1_SYNCBUSY_COMP2_Msk     = 0x80    // Bit mask of COMP2 field.
	RTC_MODE1_SYNCBUSY_COMP2         = 0x80    // Bit COMP2.
	RTC_MODE1_SYNCBUSY_COMP3_Pos     = 0x8     // Position of COMP3 field.
	RTC_MODE1_SYNCBUSY_COMP3_Msk     = 0x100   // Bit mask of COMP3 field.
	RTC_MODE1_SYNCBUSY_COMP3         = 0x100   // Bit COMP3.
	RTC_MODE1_SYNCBUSY_COUNTSYNC_Pos = 0xf     // Position of COUNTSYNC field.
	RTC_MODE1_SYNCBUSY_COUNTSYNC_Msk = 0x8000  // Bit mask of COUNTSYNC field.
	RTC_MODE1_SYNCBUSY_COUNTSYNC     = 0x8000  // Bit COUNTSYNC.
	RTC_MODE1_SYNCBUSY_GP0_Pos       = 0x10    // Position of GP0 field.
	RTC_MODE1_SYNCBUSY_GP0_Msk       = 0x10000 // Bit mask of GP0 field.
	RTC_MODE1_SYNCBUSY_GP0           = 0x10000 // Bit GP0.
	RTC_MODE1_SYNCBUSY_GP1_Pos       = 0x11    // Position of GP1 field.
	RTC_MODE1_SYNCBUSY_GP1_Msk       = 0x20000 // Bit mask of GP1 field.
	RTC_MODE1_SYNCBUSY_GP1           = 0x20000 // Bit GP1.
	RTC_MODE1_SYNCBUSY_GP2_Pos       = 0x12    // Position of GP2 field.
	RTC_MODE1_SYNCBUSY_GP2_Msk       = 0x40000 // Bit mask of GP2 field.
	RTC_MODE1_SYNCBUSY_GP2           = 0x40000 // Bit GP2.
	RTC_MODE1_SYNCBUSY_GP3_Pos       = 0x13    // Position of GP3 field.
	RTC_MODE1_SYNCBUSY_GP3_Msk       = 0x80000 // Bit mask of GP3 field.
	RTC_MODE1_SYNCBUSY_GP3           = 0x80000 // Bit GP3.

	// FREQCORR: Frequency Correction
	RTC_MODE1_FREQCORR_VALUE_Pos = 0x0  // Position of VALUE field.
	RTC_MODE1_FREQCORR_VALUE_Msk = 0x7f // Bit mask of VALUE field.
	RTC_MODE1_FREQCORR_SIGN_Pos  = 0x7  // Position of SIGN field.
	RTC_MODE1_FREQCORR_SIGN_Msk  = 0x80 // Bit mask of SIGN field.
	RTC_MODE1_FREQCORR_SIGN      = 0x80 // Bit SIGN.

	// COUNT: MODE1 Counter Value
	RTC_MODE1_COUNT_COUNT_Pos = 0x0    // Position of COUNT field.
	RTC_MODE1_COUNT_COUNT_Msk = 0xffff // Bit mask of COUNT field.

	// PER: MODE1 Counter Period
	RTC_MODE1_PER_PER_Pos = 0x0    // Position of PER field.
	RTC_MODE1_PER_PER_Msk = 0xffff // Bit mask of PER field.

	// COMP: MODE1 Compare n Value
	RTC_MODE1_COMP_COMP_Pos = 0x0    // Position of COMP field.
	RTC_MODE1_COMP_COMP_Msk = 0xffff // Bit mask of COMP field.

	// GP: General Purpose
	RTC_MODE1_GP_GP_Pos = 0x0        // Position of GP field.
	RTC_MODE1_GP_GP_Msk = 0xffffffff // Bit mask of GP field.

	// TAMPCTRL: Tamper Control
	RTC_MODE1_TAMPCTRL_IN0ACT_Pos     = 0x0        // Position of IN0ACT field.
	RTC_MODE1_TAMPCTRL_IN0ACT_Msk     = 0x3        // Bit mask of IN0ACT field.
	RTC_MODE1_TAMPCTRL_IN0ACT_OFF     = 0x0        // Off (Disabled)
	RTC_MODE1_TAMPCTRL_IN0ACT_WAKE    = 0x1        // Wake without timestamp
	RTC_MODE1_TAMPCTRL_IN0ACT_CAPTURE = 0x2        // Capture timestamp
	RTC_MODE1_TAMPCTRL_IN0ACT_ACTL    = 0x3        // Compare IN0 to OUT
	RTC_MODE1_TAMPCTRL_IN1ACT_Pos     = 0x2        // Position of IN1ACT field.
	RTC_MODE1_TAMPCTRL_IN1ACT_Msk     = 0xc        // Bit mask of IN1ACT field.
	RTC_MODE1_TAMPCTRL_IN1ACT_OFF     = 0x0        // Off (Disabled)
	RTC_MODE1_TAMPCTRL_IN1ACT_WAKE    = 0x1        // Wake without timestamp
	RTC_MODE1_TAMPCTRL_IN1ACT_CAPTURE = 0x2        // Capture timestamp
	RTC_MODE1_TAMPCTRL_IN1ACT_ACTL    = 0x3        // Compare IN1 to OUT
	RTC_MODE1_TAMPCTRL_IN2ACT_Pos     = 0x4        // Position of IN2ACT field.
	RTC_MODE1_TAMPCTRL_IN2ACT_Msk     = 0x30       // Bit mask of IN2ACT field.
	RTC_MODE1_TAMPCTRL_IN2ACT_OFF     = 0x0        // Off (Disabled)
	RTC_MODE1_TAMPCTRL_IN2ACT_WAKE    = 0x1        // Wake without timestamp
	RTC_MODE1_TAMPCTRL_IN2ACT_CAPTURE = 0x2        // Capture timestamp
	RTC_MODE1_TAMPCTRL_IN2ACT_ACTL    = 0x3        // Compare IN2 to OUT
	RTC_MODE1_TAMPCTRL_IN3ACT_Pos     = 0x6        // Position of IN3ACT field.
	RTC_MODE1_TAMPCTRL_IN3ACT_Msk     = 0xc0       // Bit mask of IN3ACT field.
	RTC_MODE1_TAMPCTRL_IN3ACT_OFF     = 0x0        // Off (Disabled)
	RTC_MODE1_TAMPCTRL_IN3ACT_WAKE    = 0x1        // Wake without timestamp
	RTC_MODE1_TAMPCTRL_IN3ACT_CAPTURE = 0x2        // Capture timestamp
	RTC_MODE1_TAMPCTRL_IN3ACT_ACTL    = 0x3        // Compare IN3 to OUT
	RTC_MODE1_TAMPCTRL_IN4ACT_Pos     = 0x8        // Position of IN4ACT field.
	RTC_MODE1_TAMPCTRL_IN4ACT_Msk     = 0x300      // Bit mask of IN4ACT field.
	RTC_MODE1_TAMPCTRL_IN4ACT_OFF     = 0x0        // Off (Disabled)
	RTC_MODE1_TAMPCTRL_IN4ACT_WAKE    = 0x1        // Wake without timestamp
	RTC_MODE1_TAMPCTRL_IN4ACT_CAPTURE = 0x2        // Capture timestamp
	RTC_MODE1_TAMPCTRL_IN4ACT_ACTL    = 0x3        // Compare IN4 to OUT
	RTC_MODE1_TAMPCTRL_TAMLVL0_Pos    = 0x10       // Position of TAMLVL0 field.
	RTC_MODE1_TAMPCTRL_TAMLVL0_Msk    = 0x10000    // Bit mask of TAMLVL0 field.
	RTC_MODE1_TAMPCTRL_TAMLVL0        = 0x10000    // Bit TAMLVL0.
	RTC_MODE1_TAMPCTRL_TAMLVL1_Pos    = 0x11       // Position of TAMLVL1 field.
	RTC_MODE1_TAMPCTRL_TAMLVL1_Msk    = 0x20000    // Bit mask of TAMLVL1 field.
	RTC_MODE1_TAMPCTRL_TAMLVL1        = 0x20000    // Bit TAMLVL1.
	RTC_MODE1_TAMPCTRL_TAMLVL2_Pos    = 0x12       // Position of TAMLVL2 field.
	RTC_MODE1_TAMPCTRL_TAMLVL2_Msk    = 0x40000    // Bit mask of TAMLVL2 field.
	RTC_MODE1_TAMPCTRL_TAMLVL2        = 0x40000    // Bit TAMLVL2.
	RTC_MODE1_TAMPCTRL_TAMLVL3_Pos    = 0x13       // Position of TAMLVL3 field.
	RTC_MODE1_TAMPCTRL_TAMLVL3_Msk    = 0x80000    // Bit mask of TAMLVL3 field.
	RTC_MODE1_TAMPCTRL_TAMLVL3        = 0x80000    // Bit TAMLVL3.
	RTC_MODE1_TAMPCTRL_TAMLVL4_Pos    = 0x14       // Position of TAMLVL4 field.
	RTC_MODE1_TAMPCTRL_TAMLVL4_Msk    = 0x100000   // Bit mask of TAMLVL4 field.
	RTC_MODE1_TAMPCTRL_TAMLVL4        = 0x100000   // Bit TAMLVL4.
	RTC_MODE1_TAMPCTRL_DEBNC0_Pos     = 0x18       // Position of DEBNC0 field.
	RTC_MODE1_TAMPCTRL_DEBNC0_Msk     = 0x1000000  // Bit mask of DEBNC0 field.
	RTC_MODE1_TAMPCTRL_DEBNC0         = 0x1000000  // Bit DEBNC0.
	RTC_MODE1_TAMPCTRL_DEBNC1_Pos     = 0x19       // Position of DEBNC1 field.
	RTC_MODE1_TAMPCTRL_DEBNC1_Msk     = 0x2000000  // Bit mask of DEBNC1 field.
	RTC_MODE1_TAMPCTRL_DEBNC1         = 0x2000000  // Bit DEBNC1.
	RTC_MODE1_TAMPCTRL_DEBNC2_Pos     = 0x1a       // Position of DEBNC2 field.
	RTC_MODE1_TAMPCTRL_DEBNC2_Msk     = 0x4000000  // Bit mask of DEBNC2 field.
	RTC_MODE1_TAMPCTRL_DEBNC2         = 0x4000000  // Bit DEBNC2.
	RTC_MODE1_TAMPCTRL_DEBNC3_Pos     = 0x1b       // Position of DEBNC3 field.
	RTC_MODE1_TAMPCTRL_DEBNC3_Msk     = 0x8000000  // Bit mask of DEBNC3 field.
	RTC_MODE1_TAMPCTRL_DEBNC3         = 0x8000000  // Bit DEBNC3.
	RTC_MODE1_TAMPCTRL_DEBNC4_Pos     = 0x1c       // Position of DEBNC4 field.
	RTC_MODE1_TAMPCTRL_DEBNC4_Msk     = 0x10000000 // Bit mask of DEBNC4 field.
	RTC_MODE1_TAMPCTRL_DEBNC4         = 0x10000000 // Bit DEBNC4.

	// TIMESTAMP: MODE1 Timestamp
	RTC_MODE1_TIMESTAMP_COUNT_Pos = 0x0    // Position of COUNT field.
	RTC_MODE1_TIMESTAMP_COUNT_Msk = 0xffff // Bit mask of COUNT field.

	// TAMPID: Tamper ID
	RTC_MODE1_TAMPID_TAMPID0_Pos = 0x0        // Position of TAMPID0 field.
	RTC_MODE1_TAMPID_TAMPID0_Msk = 0x1        // Bit mask of TAMPID0 field.
	RTC_MODE1_TAMPID_TAMPID0     = 0x1        // Bit TAMPID0.
	RTC_MODE1_TAMPID_TAMPID1_Pos = 0x1        // Position of TAMPID1 field.
	RTC_MODE1_TAMPID_TAMPID1_Msk = 0x2        // Bit mask of TAMPID1 field.
	RTC_MODE1_TAMPID_TAMPID1     = 0x2        // Bit TAMPID1.
	RTC_MODE1_TAMPID_TAMPID2_Pos = 0x2        // Position of TAMPID2 field.
	RTC_MODE1_TAMPID_TAMPID2_Msk = 0x4        // Bit mask of TAMPID2 field.
	RTC_MODE1_TAMPID_TAMPID2     = 0x4        // Bit TAMPID2.
	RTC_MODE1_TAMPID_TAMPID3_Pos = 0x3        // Position of TAMPID3 field.
	RTC_MODE1_TAMPID_TAMPID3_Msk = 0x8        // Bit mask of TAMPID3 field.
	RTC_MODE1_TAMPID_TAMPID3     = 0x8        // Bit TAMPID3.
	RTC_MODE1_TAMPID_TAMPID4_Pos = 0x4        // Position of TAMPID4 field.
	RTC_MODE1_TAMPID_TAMPID4_Msk = 0x10       // Bit mask of TAMPID4 field.
	RTC_MODE1_TAMPID_TAMPID4     = 0x10       // Bit TAMPID4.
	RTC_MODE1_TAMPID_TAMPEVT_Pos = 0x1f       // Position of TAMPEVT field.
	RTC_MODE1_TAMPID_TAMPEVT_Msk = 0x80000000 // Bit mask of TAMPEVT field.
	RTC_MODE1_TAMPID_TAMPEVT     = 0x80000000 // Bit TAMPEVT.

	// BKUP: Backup
	RTC_MODE1_BKUP_BKUP_Pos = 0x0        // Position of BKUP field.
	RTC_MODE1_BKUP_BKUP_Msk = 0xffffffff // Bit mask of BKUP field.
)

// Bitfields for RTC_MODE2: Real-Time Counter - MODE2
const (
	// CTRLA: MODE2 Control A
	RTC_MODE2_CTRLA_SWRST_Pos         = 0x0    // Position of SWRST field.
	RTC_MODE2_CTRLA_SWRST_Msk         = 0x1    // Bit mask of SWRST field.
	RTC_MODE2_CTRLA_SWRST             = 0x1    // Bit SWRST.
	RTC_MODE2_CTRLA_ENABLE_Pos        = 0x1    // Position of ENABLE field.
	RTC_MODE2_CTRLA_ENABLE_Msk        = 0x2    // Bit mask of ENABLE field.
	RTC_MODE2_CTRLA_ENABLE            = 0x2    // Bit ENABLE.
	RTC_MODE2_CTRLA_MODE_Pos          = 0x2    // Position of MODE field.
	RTC_MODE2_CTRLA_MODE_Msk          = 0xc    // Bit mask of MODE field.
	RTC_MODE2_CTRLA_MODE_COUNT32      = 0x0    // Mode 0: 32-bit Counter
	RTC_MODE2_CTRLA_MODE_COUNT16      = 0x1    // Mode 1: 16-bit Counter
	RTC_MODE2_CTRLA_MODE_CLOCK        = 0x2    // Mode 2: Clock/Calendar
	RTC_MODE2_CTRLA_CLKREP_Pos        = 0x6    // Position of CLKREP field.
	RTC_MODE2_CTRLA_CLKREP_Msk        = 0x40   // Bit mask of CLKREP field.
	RTC_MODE2_CTRLA_CLKREP            = 0x40   // Bit CLKREP.
	RTC_MODE2_CTRLA_MATCHCLR_Pos      = 0x7    // Position of MATCHCLR field.
	RTC_MODE2_CTRLA_MATCHCLR_Msk      = 0x80   // Bit mask of MATCHCLR field.
	RTC_MODE2_CTRLA_MATCHCLR          = 0x80   // Bit MATCHCLR.
	RTC_MODE2_CTRLA_PRESCALER_Pos     = 0x8    // Position of PRESCALER field.
	RTC_MODE2_CTRLA_PRESCALER_Msk     = 0xf00  // Bit mask of PRESCALER field.
	RTC_MODE2_CTRLA_PRESCALER_OFF     = 0x0    // CLK_RTC_CNT = GCLK_RTC/1
	RTC_MODE2_CTRLA_PRESCALER_DIV1    = 0x1    // CLK_RTC_CNT = GCLK_RTC/1
	RTC_MODE2_CTRLA_PRESCALER_DIV2    = 0x2    // CLK_RTC_CNT = GCLK_RTC/2
	RTC_MODE2_CTRLA_PRESCALER_DIV4    = 0x3    // CLK_RTC_CNT = GCLK_RTC/4
	RTC_MODE2_CTRLA_PRESCALER_DIV8    = 0x4    // CLK_RTC_CNT = GCLK_RTC/8
	RTC_MODE2_CTRLA_PRESCALER_DIV16   = 0x5    // CLK_RTC_CNT = GCLK_RTC/16
	RTC_MODE2_CTRLA_PRESCALER_DIV32   = 0x6    // CLK_RTC_CNT = GCLK_RTC/32
	RTC_MODE2_CTRLA_PRESCALER_DIV64   = 0x7    // CLK_RTC_CNT = GCLK_RTC/64
	RTC_MODE2_CTRLA_PRESCALER_DIV128  = 0x8    // CLK_RTC_CNT = GCLK_RTC/128
	RTC_MODE2_CTRLA_PRESCALER_DIV256  = 0x9    // CLK_RTC_CNT = GCLK_RTC/256
	RTC_MODE2_CTRLA_PRESCALER_DIV512  = 0xa    // CLK_RTC_CNT = GCLK_RTC/512
	RTC_MODE2_CTRLA_PRESCALER_DIV1024 = 0xb    // CLK_RTC_CNT = GCLK_RTC/1024
	RTC_MODE2_CTRLA_BKTRST_Pos        = 0xd    // Position of BKTRST field.
	RTC_MODE2_CTRLA_BKTRST_Msk        = 0x2000 // Bit mask of BKTRST field.
	RTC_MODE2_CTRLA_BKTRST            = 0x2000 // Bit BKTRST.
	RTC_MODE2_CTRLA_GPTRST_Pos        = 0xe    // Position of GPTRST field.
	RTC_MODE2_CTRLA_GPTRST_Msk        = 0x4000 // Bit mask of GPTRST field.
	RTC_MODE2_CTRLA_GPTRST            = 0x4000 // Bit GPTRST.
	RTC_MODE2_CTRLA_CLOCKSYNC_Pos     = 0xf    // Position of CLOCKSYNC field.
	RTC_MODE2_CTRLA_CLOCKSYNC_Msk     = 0x8000 // Bit mask of CLOCKSYNC field.
	RTC_MODE2_CTRLA_CLOCKSYNC         = 0x8000 // Bit CLOCKSYNC.

	// CTRLB: MODE2 Control B
	RTC_MODE2_CTRLB_GP0EN_Pos    = 0x0    // Position of GP0EN field.
	RTC_MODE2_CTRLB_GP0EN_Msk    = 0x1    // Bit mask of GP0EN field.
	RTC_MODE2_CTRLB_GP0EN        = 0x1    // Bit GP0EN.
	RTC_MODE2_CTRLB_GP2EN_Pos    = 0x1    // Position of GP2EN field.
	RTC_MODE2_CTRLB_GP2EN_Msk    = 0x2    // Bit mask of GP2EN field.
	RTC_MODE2_CTRLB_GP2EN        = 0x2    // Bit GP2EN.
	RTC_MODE2_CTRLB_DEBMAJ_Pos   = 0x4    // Position of DEBMAJ field.
	RTC_MODE2_CTRLB_DEBMAJ_Msk   = 0x10   // Bit mask of DEBMAJ field.
	RTC_MODE2_CTRLB_DEBMAJ       = 0x10   // Bit DEBMAJ.
	RTC_MODE2_CTRLB_DEBASYNC_Pos = 0x5    // Position of DEBASYNC field.
	RTC_MODE2_CTRLB_DEBASYNC_Msk = 0x20   // Bit mask of DEBASYNC field.
	RTC_MODE2_CTRLB_DEBASYNC     = 0x20   // Bit DEBASYNC.
	RTC_MODE2_CTRLB_RTCOUT_Pos   = 0x6    // Position of RTCOUT field.
	RTC_MODE2_CTRLB_RTCOUT_Msk   = 0x40   // Bit mask of RTCOUT field.
	RTC_MODE2_CTRLB_RTCOUT       = 0x40   // Bit RTCOUT.
	RTC_MODE2_CTRLB_DMAEN_Pos    = 0x7    // Position of DMAEN field.
	RTC_MODE2_CTRLB_DMAEN_Msk    = 0x80   // Bit mask of DMAEN field.
	RTC_MODE2_CTRLB_DMAEN        = 0x80   // Bit DMAEN.
	RTC_MODE2_CTRLB_DEBF_Pos     = 0x8    // Position of DEBF field.
	RTC_MODE2_CTRLB_DEBF_Msk     = 0x700  // Bit mask of DEBF field.
	RTC_MODE2_CTRLB_DEBF_DIV2    = 0x0    // CLK_RTC_DEB = CLK_RTC/2
	RTC_MODE2_CTRLB_DEBF_DIV4    = 0x1    // CLK_RTC_DEB = CLK_RTC/4
	RTC_MODE2_CTRLB_DEBF_DIV8    = 0x2    // CLK_RTC_DEB = CLK_RTC/8
	RTC_MODE2_CTRLB_DEBF_DIV16   = 0x3    // CLK_RTC_DEB = CLK_RTC/16
	RTC_MODE2_CTRLB_DEBF_DIV32   = 0x4    // CLK_RTC_DEB = CLK_RTC/32
	RTC_MODE2_CTRLB_DEBF_DIV64   = 0x5    // CLK_RTC_DEB = CLK_RTC/64
	RTC_MODE2_CTRLB_DEBF_DIV128  = 0x6    // CLK_RTC_DEB = CLK_RTC/128
	RTC_MODE2_CTRLB_DEBF_DIV256  = 0x7    // CLK_RTC_DEB = CLK_RTC/256
	RTC_MODE2_CTRLB_ACTF_Pos     = 0xc    // Position of ACTF field.
	RTC_MODE2_CTRLB_ACTF_Msk     = 0x7000 // Bit mask of ACTF field.
	RTC_MODE2_CTRLB_ACTF_DIV2    = 0x0    // CLK_RTC_OUT = CLK_RTC/2
	RTC_MODE2_CTRLB_ACTF_DIV4    = 0x1    // CLK_RTC_OUT = CLK_RTC/4
	RTC_MODE2_CTRLB_ACTF_DIV8    = 0x2    // CLK_RTC_OUT = CLK_RTC/8
	RTC_MODE2_CTRLB_ACTF_DIV16   = 0x3    // CLK_RTC_OUT = CLK_RTC/16
	RTC_MODE2_CTRLB_ACTF_DIV32   = 0x4    // CLK_RTC_OUT = CLK_RTC/32
	RTC_MODE2_CTRLB_ACTF_DIV64   = 0x5    // CLK_RTC_OUT = CLK_RTC/64
	RTC_MODE2_CTRLB_ACTF_DIV128  = 0x6    // CLK_RTC_OUT = CLK_RTC/128
	RTC_MODE2_CTRLB_ACTF_DIV256  = 0x7    // CLK_RTC_OUT = CLK_RTC/256

	// EVCTRL: MODE2 Event Control
	RTC_MODE2_EVCTRL_PEREO0_Pos   = 0x0     // Position of PEREO0 field.
	RTC_MODE2_EVCTRL_PEREO0_Msk   = 0x1     // Bit mask of PEREO0 field.
	RTC_MODE2_EVCTRL_PEREO0       = 0x1     // Bit PEREO0.
	RTC_MODE2_EVCTRL_PEREO1_Pos   = 0x1     // Position of PEREO1 field.
	RTC_MODE2_EVCTRL_PEREO1_Msk   = 0x2     // Bit mask of PEREO1 field.
	RTC_MODE2_EVCTRL_PEREO1       = 0x2     // Bit PEREO1.
	RTC_MODE2_EVCTRL_PEREO2_Pos   = 0x2     // Position of PEREO2 field.
	RTC_MODE2_EVCTRL_PEREO2_Msk   = 0x4     // Bit mask of PEREO2 field.
	RTC_MODE2_EVCTRL_PEREO2       = 0x4     // Bit PEREO2.
	RTC_MODE2_EVCTRL_PEREO3_Pos   = 0x3     // Position of PEREO3 field.
	RTC_MODE2_EVCTRL_PEREO3_Msk   = 0x8     // Bit mask of PEREO3 field.
	RTC_MODE2_EVCTRL_PEREO3       = 0x8     // Bit PEREO3.
	RTC_MODE2_EVCTRL_PEREO4_Pos   = 0x4     // Position of PEREO4 field.
	RTC_MODE2_EVCTRL_PEREO4_Msk   = 0x10    // Bit mask of PEREO4 field.
	RTC_MODE2_EVCTRL_PEREO4       = 0x10    // Bit PEREO4.
	RTC_MODE2_EVCTRL_PEREO5_Pos   = 0x5     // Position of PEREO5 field.
	RTC_MODE2_EVCTRL_PEREO5_Msk   = 0x20    // Bit mask of PEREO5 field.
	RTC_MODE2_EVCTRL_PEREO5       = 0x20    // Bit PEREO5.
	RTC_MODE2_EVCTRL_PEREO6_Pos   = 0x6     // Position of PEREO6 field.
	RTC_MODE2_EVCTRL_PEREO6_Msk   = 0x40    // Bit mask of PEREO6 field.
	RTC_MODE2_EVCTRL_PEREO6       = 0x40    // Bit PEREO6.
	RTC_MODE2_EVCTRL_PEREO7_Pos   = 0x7     // Position of PEREO7 field.
	RTC_MODE2_EVCTRL_PEREO7_Msk   = 0x80    // Bit mask of PEREO7 field.
	RTC_MODE2_EVCTRL_PEREO7       = 0x80    // Bit PEREO7.
	RTC_MODE2_EVCTRL_ALARMEO0_Pos = 0x8     // Position of ALARMEO0 field.
	RTC_MODE2_EVCTRL_ALARMEO0_Msk = 0x100   // Bit mask of ALARMEO0 field.
	RTC_MODE2_EVCTRL_ALARMEO0     = 0x100   // Bit ALARMEO0.
	RTC_MODE2_EVCTRL_ALARMEO1_Pos = 0x9     // Position of ALARMEO1 field.
	RTC_MODE2_EVCTRL_ALARMEO1_Msk = 0x200   // Bit mask of ALARMEO1 field.
	RTC_MODE2_EVCTRL_ALARMEO1     = 0x200   // Bit ALARMEO1.
	RTC_MODE2_EVCTRL_TAMPEREO_Pos = 0xe     // Position of TAMPEREO field.
	RTC_MODE2_EVCTRL_TAMPEREO_Msk = 0x4000  // Bit mask of TAMPEREO field.
	RTC_MODE2_EVCTRL_TAMPEREO     = 0x4000  // Bit TAMPEREO.
	RTC_MODE2_EVCTRL_OVFEO_Pos    = 0xf     // Position of OVFEO field.
	RTC_MODE2_EVCTRL_OVFEO_Msk    = 0x8000  // Bit mask of OVFEO field.
	RTC_MODE2_EVCTRL_OVFEO        = 0x8000  // Bit OVFEO.
	RTC_MODE2_EVCTRL_TAMPEVEI_Pos = 0x10    // Position of TAMPEVEI field.
	RTC_MODE2_EVCTRL_TAMPEVEI_Msk = 0x10000 // Bit mask of TAMPEVEI field.
	RTC_MODE2_EVCTRL_TAMPEVEI     = 0x10000 // Bit TAMPEVEI.

	// INTENCLR: MODE2 Interrupt Enable Clear
	RTC_MODE2_INTENCLR_PER0_Pos   = 0x0    // Position of PER0 field.
	RTC_MODE2_INTENCLR_PER0_Msk   = 0x1    // Bit mask of PER0 field.
	RTC_MODE2_INTENCLR_PER0       = 0x1    // Bit PER0.
	RTC_MODE2_INTENCLR_PER1_Pos   = 0x1    // Position of PER1 field.
	RTC_MODE2_INTENCLR_PER1_Msk   = 0x2    // Bit mask of PER1 field.
	RTC_MODE2_INTENCLR_PER1       = 0x2    // Bit PER1.
	RTC_MODE2_INTENCLR_PER2_Pos   = 0x2    // Position of PER2 field.
	RTC_MODE2_INTENCLR_PER2_Msk   = 0x4    // Bit mask of PER2 field.
	RTC_MODE2_INTENCLR_PER2       = 0x4    // Bit PER2.
	RTC_MODE2_INTENCLR_PER3_Pos   = 0x3    // Position of PER3 field.
	RTC_MODE2_INTENCLR_PER3_Msk   = 0x8    // Bit mask of PER3 field.
	RTC_MODE2_INTENCLR_PER3       = 0x8    // Bit PER3.
	RTC_MODE2_INTENCLR_PER4_Pos   = 0x4    // Position of PER4 field.
	RTC_MODE2_INTENCLR_PER4_Msk   = 0x10   // Bit mask of PER4 field.
	RTC_MODE2_INTENCLR_PER4       = 0x10   // Bit PER4.
	RTC_MODE2_INTENCLR_PER5_Pos   = 0x5    // Position of PER5 field.
	RTC_MODE2_INTENCLR_PER5_Msk   = 0x20   // Bit mask of PER5 field.
	RTC_MODE2_INTENCLR_PER5       = 0x20   // Bit PER5.
	RTC_MODE2_INTENCLR_PER6_Pos   = 0x6    // Position of PER6 field.
	RTC_MODE2_INTENCLR_PER6_Msk   = 0x40   // Bit mask of PER6 field.
	RTC_MODE2_INTENCLR_PER6       = 0x40   // Bit PER6.
	RTC_MODE2_INTENCLR_PER7_Pos   = 0x7    // Position of PER7 field.
	RTC_MODE2_INTENCLR_PER7_Msk   = 0x80   // Bit mask of PER7 field.
	RTC_MODE2_INTENCLR_PER7       = 0x80   // Bit PER7.
	RTC_MODE2_INTENCLR_ALARM0_Pos = 0x8    // Position of ALARM0 field.
	RTC_MODE2_INTENCLR_ALARM0_Msk = 0x100  // Bit mask of ALARM0 field.
	RTC_MODE2_INTENCLR_ALARM0     = 0x100  // Bit ALARM0.
	RTC_MODE2_INTENCLR_ALARM1_Pos = 0x9    // Position of ALARM1 field.
	RTC_MODE2_INTENCLR_ALARM1_Msk = 0x200  // Bit mask of ALARM1 field.
	RTC_MODE2_INTENCLR_ALARM1     = 0x200  // Bit ALARM1.
	RTC_MODE2_INTENCLR_TAMPER_Pos = 0xe    // Position of TAMPER field.
	RTC_MODE2_INTENCLR_TAMPER_Msk = 0x4000 // Bit mask of TAMPER field.
	RTC_MODE2_INTENCLR_TAMPER     = 0x4000 // Bit TAMPER.
	RTC_MODE2_INTENCLR_OVF_Pos    = 0xf    // Position of OVF field.
	RTC_MODE2_INTENCLR_OVF_Msk    = 0x8000 // Bit mask of OVF field.
	RTC_MODE2_INTENCLR_OVF        = 0x8000 // Bit OVF.

	// INTENSET: MODE2 Interrupt Enable Set
	RTC_MODE2_INTENSET_PER0_Pos   = 0x0    // Position of PER0 field.
	RTC_MODE2_INTENSET_PER0_Msk   = 0x1    // Bit mask of PER0 field.
	RTC_MODE2_INTENSET_PER0       = 0x1    // Bit PER0.
	RTC_MODE2_INTENSET_PER1_Pos   = 0x1    // Position of PER1 field.
	RTC_MODE2_INTENSET_PER1_Msk   = 0x2    // Bit mask of PER1 field.
	RTC_MODE2_INTENSET_PER1       = 0x2    // Bit PER1.
	RTC_MODE2_INTENSET_PER2_Pos   = 0x2    // Position of PER2 field.
	RTC_MODE2_INTENSET_PER2_Msk   = 0x4    // Bit mask of PER2 field.
	RTC_MODE2_INTENSET_PER2       = 0x4    // Bit PER2.
	RTC_MODE2_INTENSET_PER3_Pos   = 0x3    // Position of PER3 field.
	RTC_MODE2_INTENSET_PER3_Msk   = 0x8    // Bit mask of PER3 field.
	RTC_MODE2_INTENSET_PER3       = 0x8    // Bit PER3.
	RTC_MODE2_INTENSET_PER4_Pos   = 0x4    // Position of PER4 field.
	RTC_MODE2_INTENSET_PER4_Msk   = 0x10   // Bit mask of PER4 field.
	RTC_MODE2_INTENSET_PER4       = 0x10   // Bit PER4.
	RTC_MODE2_INTENSET_PER5_Pos   = 0x5    // Position of PER5 field.
	RTC_MODE2_INTENSET_PER5_Msk   = 0x20   // Bit mask of PER5 field.
	RTC_MODE2_INTENSET_PER5       = 0x20   // Bit PER5.
	RTC_MODE2_INTENSET_PER6_Pos   = 0x6    // Position of PER6 field.
	RTC_MODE2_INTENSET_PER6_Msk   = 0x40   // Bit mask of PER6 field.
	RTC_MODE2_INTENSET_PER6       = 0x40   // Bit PER6.
	RTC_MODE2_INTENSET_PER7_Pos   = 0x7    // Position of PER7 field.
	RTC_MODE2_INTENSET_PER7_Msk   = 0x80   // Bit mask of PER7 field.
	RTC_MODE2_INTENSET_PER7       = 0x80   // Bit PER7.
	RTC_MODE2_INTENSET_ALARM0_Pos = 0x8    // Position of ALARM0 field.
	RTC_MODE2_INTENSET_ALARM0_Msk = 0x100  // Bit mask of ALARM0 field.
	RTC_MODE2_INTENSET_ALARM0     = 0x100  // Bit ALARM0.
	RTC_MODE2_INTENSET_ALARM1_Pos = 0x9    // Position of ALARM1 field.
	RTC_MODE2_INTENSET_ALARM1_Msk = 0x200  // Bit mask of ALARM1 field.
	RTC_MODE2_INTENSET_ALARM1     = 0x200  // Bit ALARM1.
	RTC_MODE2_INTENSET_TAMPER_Pos = 0xe    // Position of TAMPER field.
	RTC_MODE2_INTENSET_TAMPER_Msk = 0x4000 // Bit mask of TAMPER field.
	RTC_MODE2_INTENSET_TAMPER     = 0x4000 // Bit TAMPER.
	RTC_MODE2_INTENSET_OVF_Pos    = 0xf    // Position of OVF field.
	RTC_MODE2_INTENSET_OVF_Msk    = 0x8000 // Bit mask of OVF field.
	RTC_MODE2_INTENSET_OVF        = 0x8000 // Bit OVF.

	// INTFLAG: MODE2 Interrupt Flag Status and Clear
	RTC_MODE2_INTFLAG_PER0_Pos   = 0x0    // Position of PER0 field.
	RTC_MODE2_INTFLAG_PER0_Msk   = 0x1    // Bit mask of PER0 field.
	RTC_MODE2_INTFLAG_PER0       = 0x1    // Bit PER0.
	RTC_MODE2_INTFLAG_PER1_Pos   = 0x1    // Position of PER1 field.
	RTC_MODE2_INTFLAG_PER1_Msk   = 0x2    // Bit mask of PER1 field.
	RTC_MODE2_INTFLAG_PER1       = 0x2    // Bit PER1.
	RTC_MODE2_INTFLAG_PER2_Pos   = 0x2    // Position of PER2 field.
	RTC_MODE2_INTFLAG_PER2_Msk   = 0x4    // Bit mask of PER2 field.
	RTC_MODE2_INTFLAG_PER2       = 0x4    // Bit PER2.
	RTC_MODE2_INTFLAG_PER3_Pos   = 0x3    // Position of PER3 field.
	RTC_MODE2_INTFLAG_PER3_Msk   = 0x8    // Bit mask of PER3 field.
	RTC_MODE2_INTFLAG_PER3       = 0x8    // Bit PER3.
	RTC_MODE2_INTFLAG_PER4_Pos   = 0x4    // Position of PER4 field.
	RTC_MODE2_INTFLAG_PER4_Msk   = 0x10   // Bit mask of PER4 field.
	RTC_MODE2_INTFLAG_PER4       = 0x10   // Bit PER4.
	RTC_MODE2_INTFLAG_PER5_Pos   = 0x5    // Position of PER5 field.
	RTC_MODE2_INTFLAG_PER5_Msk   = 0x20   // Bit mask of PER5 field.
	RTC_MODE2_INTFLAG_PER5       = 0x20   // Bit PER5.
	RTC_MODE2_INTFLAG_PER6_Pos   = 0x6    // Position of PER6 field.
	RTC_MODE2_INTFLAG_PER6_Msk   = 0x40   // Bit mask of PER6 field.
	RTC_MODE2_INTFLAG_PER6       = 0x40   // Bit PER6.
	RTC_MODE2_INTFLAG_PER7_Pos   = 0x7    // Position of PER7 field.
	RTC_MODE2_INTFLAG_PER7_Msk   = 0x80   // Bit mask of PER7 field.
	RTC_MODE2_INTFLAG_PER7       = 0x80   // Bit PER7.
	RTC_MODE2_INTFLAG_ALARM0_Pos = 0x8    // Position of ALARM0 field.
	RTC_MODE2_INTFLAG_ALARM0_Msk = 0x100  // Bit mask of ALARM0 field.
	RTC_MODE2_INTFLAG_ALARM0     = 0x100  // Bit ALARM0.
	RTC_MODE2_INTFLAG_ALARM1_Pos = 0x9    // Position of ALARM1 field.
	RTC_MODE2_INTFLAG_ALARM1_Msk = 0x200  // Bit mask of ALARM1 field.
	RTC_MODE2_INTFLAG_ALARM1     = 0x200  // Bit ALARM1.
	RTC_MODE2_INTFLAG_TAMPER_Pos = 0xe    // Position of TAMPER field.
	RTC_MODE2_INTFLAG_TAMPER_Msk = 0x4000 // Bit mask of TAMPER field.
	RTC_MODE2_INTFLAG_TAMPER     = 0x4000 // Bit TAMPER.
	RTC_MODE2_INTFLAG_OVF_Pos    = 0xf    // Position of OVF field.
	RTC_MODE2_INTFLAG_OVF_Msk    = 0x8000 // Bit mask of OVF field.
	RTC_MODE2_INTFLAG_OVF        = 0x8000 // Bit OVF.

	// DBGCTRL: Debug Control
	RTC_MODE2_DBGCTRL_DBGRUN_Pos = 0x0 // Position of DBGRUN field.
	RTC_MODE2_DBGCTRL_DBGRUN_Msk = 0x1 // Bit mask of DBGRUN field.
	RTC_MODE2_DBGCTRL_DBGRUN     = 0x1 // Bit DBGRUN.

	// SYNCBUSY: MODE2 Synchronization Busy Status
	RTC_MODE2_SYNCBUSY_SWRST_Pos     = 0x0     // Position of SWRST field.
	RTC_MODE2_SYNCBUSY_SWRST_Msk     = 0x1     // Bit mask of SWRST field.
	RTC_MODE2_SYNCBUSY_SWRST         = 0x1     // Bit SWRST.
	RTC_MODE2_SYNCBUSY_ENABLE_Pos    = 0x1     // Position of ENABLE field.
	RTC_MODE2_SYNCBUSY_ENABLE_Msk    = 0x2     // Bit mask of ENABLE field.
	RTC_MODE2_SYNCBUSY_ENABLE        = 0x2     // Bit ENABLE.
	RTC_MODE2_SYNCBUSY_FREQCORR_Pos  = 0x2     // Position of FREQCORR field.
	RTC_MODE2_SYNCBUSY_FREQCORR_Msk  = 0x4     // Bit mask of FREQCORR field.
	RTC_MODE2_SYNCBUSY_FREQCORR      = 0x4     // Bit FREQCORR.
	RTC_MODE2_SYNCBUSY_CLOCK_Pos     = 0x3     // Position of CLOCK field.
	RTC_MODE2_SYNCBUSY_CLOCK_Msk     = 0x8     // Bit mask of CLOCK field.
	RTC_MODE2_SYNCBUSY_CLOCK         = 0x8     // Bit CLOCK.
	RTC_MODE2_SYNCBUSY_ALARM0_Pos    = 0x5     // Position of ALARM0 field.
	RTC_MODE2_SYNCBUSY_ALARM0_Msk    = 0x20    // Bit mask of ALARM0 field.
	RTC_MODE2_SYNCBUSY_ALARM0        = 0x20    // Bit ALARM0.
	RTC_MODE2_SYNCBUSY_ALARM1_Pos    = 0x6     // Position of ALARM1 field.
	RTC_MODE2_SYNCBUSY_ALARM1_Msk    = 0x40    // Bit mask of ALARM1 field.
	RTC_MODE2_SYNCBUSY_ALARM1        = 0x40    // Bit ALARM1.
	RTC_MODE2_SYNCBUSY_MASK0_Pos     = 0xb     // Position of MASK0 field.
	RTC_MODE2_SYNCBUSY_MASK0_Msk     = 0x800   // Bit mask of MASK0 field.
	RTC_MODE2_SYNCBUSY_MASK0         = 0x800   // Bit MASK0.
	RTC_MODE2_SYNCBUSY_MASK1_Pos     = 0xc     // Position of MASK1 field.
	RTC_MODE2_SYNCBUSY_MASK1_Msk     = 0x1000  // Bit mask of MASK1 field.
	RTC_MODE2_SYNCBUSY_MASK1         = 0x1000  // Bit MASK1.
	RTC_MODE2_SYNCBUSY_CLOCKSYNC_Pos = 0xf     // Position of CLOCKSYNC field.
	RTC_MODE2_SYNCBUSY_CLOCKSYNC_Msk = 0x8000  // Bit mask of CLOCKSYNC field.
	RTC_MODE2_SYNCBUSY_CLOCKSYNC     = 0x8000  // Bit CLOCKSYNC.
	RTC_MODE2_SYNCBUSY_GP0_Pos       = 0x10    // Position of GP0 field.
	RTC_MODE2_SYNCBUSY_GP0_Msk       = 0x10000 // Bit mask of GP0 field.
	RTC_MODE2_SYNCBUSY_GP0           = 0x10000 // Bit GP0.
	RTC_MODE2_SYNCBUSY_GP1_Pos       = 0x11    // Position of GP1 field.
	RTC_MODE2_SYNCBUSY_GP1_Msk       = 0x20000 // Bit mask of GP1 field.
	RTC_MODE2_SYNCBUSY_GP1           = 0x20000 // Bit GP1.
	RTC_MODE2_SYNCBUSY_GP2_Pos       = 0x12    // Position of GP2 field.
	RTC_MODE2_SYNCBUSY_GP2_Msk       = 0x40000 // Bit mask of GP2 field.
	RTC_MODE2_SYNCBUSY_GP2           = 0x40000 // Bit GP2.
	RTC_MODE2_SYNCBUSY_GP3_Pos       = 0x13    // Position of GP3 field.
	RTC_MODE2_SYNCBUSY_GP3_Msk       = 0x80000 // Bit mask of GP3 field.
	RTC_MODE2_SYNCBUSY_GP3           = 0x80000 // Bit GP3.

	// FREQCORR: Frequency Correction
	RTC_MODE2_FREQCORR_VALUE_Pos = 0x0  // Position of VALUE field.
	RTC_MODE2_FREQCORR_VALUE_Msk = 0x7f // Bit mask of VALUE field.
	RTC_MODE2_FREQCORR_SIGN_Pos  = 0x7  // Position of SIGN field.
	RTC_MODE2_FREQCORR_SIGN_Msk  = 0x80 // Bit mask of SIGN field.
	RTC_MODE2_FREQCORR_SIGN      = 0x80 // Bit SIGN.

	// CLOCK: MODE2 Clock Value
	RTC_MODE2_CLOCK_SECOND_Pos = 0x0        // Position of SECOND field.
	RTC_MODE2_CLOCK_SECOND_Msk = 0x3f       // Bit mask of SECOND field.
	RTC_MODE2_CLOCK_MINUTE_Pos = 0x6        // Position of MINUTE field.
	RTC_MODE2_CLOCK_MINUTE_Msk = 0xfc0      // Bit mask of MINUTE field.
	RTC_MODE2_CLOCK_HOUR_Pos   = 0xc        // Position of HOUR field.
	RTC_MODE2_CLOCK_HOUR_Msk   = 0x1f000    // Bit mask of HOUR field.
	RTC_MODE2_CLOCK_HOUR_AM    = 0x0        // AM when CLKREP in 12-hour
	RTC_MODE2_CLOCK_HOUR_PM    = 0x10       // PM when CLKREP in 12-hour
	RTC_MODE2_CLOCK_DAY_Pos    = 0x11       // Position of DAY field.
	RTC_MODE2_CLOCK_DAY_Msk    = 0x3e0000   // Bit mask of DAY field.
	RTC_MODE2_CLOCK_MONTH_Pos  = 0x16       // Position of MONTH field.
	RTC_MODE2_CLOCK_MONTH_Msk  = 0x3c00000  // Bit mask of MONTH field.
	RTC_MODE2_CLOCK_YEAR_Pos   = 0x1a       // Position of YEAR field.
	RTC_MODE2_CLOCK_YEAR_Msk   = 0xfc000000 // Bit mask of YEAR field.

	// ALARM0: MODE2_ALARM Alarm n Value
	RTC_MODE2_ALARM0_SECOND_Pos = 0x0        // Position of SECOND field.
	RTC_MODE2_ALARM0_SECOND_Msk = 0x3f       // Bit mask of SECOND field.
	RTC_MODE2_ALARM0_MINUTE_Pos = 0x6        // Position of MINUTE field.
	RTC_MODE2_ALARM0_MINUTE_Msk = 0xfc0      // Bit mask of MINUTE field.
	RTC_MODE2_ALARM0_HOUR_Pos   = 0xc        // Position of HOUR field.
	RTC_MODE2_ALARM0_HOUR_Msk   = 0x1f000    // Bit mask of HOUR field.
	RTC_MODE2_ALARM0_HOUR_AM    = 0x0        // Morning hour
	RTC_MODE2_ALARM0_HOUR_PM    = 0x10       // Afternoon hour
	RTC_MODE2_ALARM0_DAY_Pos    = 0x11       // Position of DAY field.
	RTC_MODE2_ALARM0_DAY_Msk    = 0x3e0000   // Bit mask of DAY field.
	RTC_MODE2_ALARM0_MONTH_Pos  = 0x16       // Position of MONTH field.
	RTC_MODE2_ALARM0_MONTH_Msk  = 0x3c00000  // Bit mask of MONTH field.
	RTC_MODE2_ALARM0_YEAR_Pos   = 0x1a       // Position of YEAR field.
	RTC_MODE2_ALARM0_YEAR_Msk   = 0xfc000000 // Bit mask of YEAR field.

	// MASK0: MODE2_ALARM Alarm n Mask
	RTC_MODE2_MASK0_SEL_Pos          = 0x0 // Position of SEL field.
	RTC_MODE2_MASK0_SEL_Msk          = 0x7 // Bit mask of SEL field.
	RTC_MODE2_MASK0_SEL_OFF          = 0x0 // Alarm Disabled
	RTC_MODE2_MASK0_SEL_SS           = 0x1 // Match seconds only
	RTC_MODE2_MASK0_SEL_MMSS         = 0x2 // Match seconds and minutes only
	RTC_MODE2_MASK0_SEL_HHMMSS       = 0x3 // Match seconds, minutes, and hours only
	RTC_MODE2_MASK0_SEL_DDHHMMSS     = 0x4 // Match seconds, minutes, hours, and days only
	RTC_MODE2_MASK0_SEL_MMDDHHMMSS   = 0x5 // Match seconds, minutes, hours, days, and months only
	RTC_MODE2_MASK0_SEL_YYMMDDHHMMSS = 0x6 // Match seconds, minutes, hours, days, months, and years

	// ALARM1: MODE2_ALARM Alarm n Value
	RTC_MODE2_ALARM1_SECOND_Pos = 0x0        // Position of SECOND field.
	RTC_MODE2_ALARM1_SECOND_Msk = 0x3f       // Bit mask of SECOND field.
	RTC_MODE2_ALARM1_MINUTE_Pos = 0x6        // Position of MINUTE field.
	RTC_MODE2_ALARM1_MINUTE_Msk = 0xfc0      // Bit mask of MINUTE field.
	RTC_MODE2_ALARM1_HOUR_Pos   = 0xc        // Position of HOUR field.
	RTC_MODE2_ALARM1_HOUR_Msk   = 0x1f000    // Bit mask of HOUR field.
	RTC_MODE2_ALARM1_HOUR_AM    = 0x0        // Morning hour
	RTC_MODE2_ALARM1_HOUR_PM    = 0x10       // Afternoon hour
	RTC_MODE2_ALARM1_DAY_Pos    = 0x11       // Position of DAY field.
	RTC_MODE2_ALARM1_DAY_Msk    = 0x3e0000   // Bit mask of DAY field.
	RTC_MODE2_ALARM1_MONTH_Pos  = 0x16       // Position of MONTH field.
	RTC_MODE2_ALARM1_MONTH_Msk  = 0x3c00000  // Bit mask of MONTH field.
	RTC_MODE2_ALARM1_YEAR_Pos   = 0x1a       // Position of YEAR field.
	RTC_MODE2_ALARM1_YEAR_Msk   = 0xfc000000 // Bit mask of YEAR field.

	// MASK1: MODE2_ALARM Alarm n Mask
	RTC_MODE2_MASK1_SEL_Pos          = 0x0 // Position of SEL field.
	RTC_MODE2_MASK1_SEL_Msk          = 0x7 // Bit mask of SEL field.
	RTC_MODE2_MASK1_SEL_OFF          = 0x0 // Alarm Disabled
	RTC_MODE2_MASK1_SEL_SS           = 0x1 // Match seconds only
	RTC_MODE2_MASK1_SEL_MMSS         = 0x2 // Match seconds and minutes only
	RTC_MODE2_MASK1_SEL_HHMMSS       = 0x3 // Match seconds, minutes, and hours only
	RTC_MODE2_MASK1_SEL_DDHHMMSS     = 0x4 // Match seconds, minutes, hours, and days only
	RTC_MODE2_MASK1_SEL_MMDDHHMMSS   = 0x5 // Match seconds, minutes, hours, days, and months only
	RTC_MODE2_MASK1_SEL_YYMMDDHHMMSS = 0x6 // Match seconds, minutes, hours, days, months, and years

	// GP: General Purpose
	RTC_MODE2_GP_GP_Pos = 0x0        // Position of GP field.
	RTC_MODE2_GP_GP_Msk = 0xffffffff // Bit mask of GP field.

	// TAMPCTRL: Tamper Control
	RTC_MODE2_TAMPCTRL_IN0ACT_Pos     = 0x0        // Position of IN0ACT field.
	RTC_MODE2_TAMPCTRL_IN0ACT_Msk     = 0x3        // Bit mask of IN0ACT field.
	RTC_MODE2_TAMPCTRL_IN0ACT_OFF     = 0x0        // Off (Disabled)
	RTC_MODE2_TAMPCTRL_IN0ACT_WAKE    = 0x1        // Wake without timestamp
	RTC_MODE2_TAMPCTRL_IN0ACT_CAPTURE = 0x2        // Capture timestamp
	RTC_MODE2_TAMPCTRL_IN0ACT_ACTL    = 0x3        // Compare IN0 to OUT
	RTC_MODE2_TAMPCTRL_IN1ACT_Pos     = 0x2        // Position of IN1ACT field.
	RTC_MODE2_TAMPCTRL_IN1ACT_Msk     = 0xc        // Bit mask of IN1ACT field.
	RTC_MODE2_TAMPCTRL_IN1ACT_OFF     = 0x0        // Off (Disabled)
	RTC_MODE2_TAMPCTRL_IN1ACT_WAKE    = 0x1        // Wake without timestamp
	RTC_MODE2_TAMPCTRL_IN1ACT_CAPTURE = 0x2        // Capture timestamp
	RTC_MODE2_TAMPCTRL_IN1ACT_ACTL    = 0x3        // Compare IN1 to OUT
	RTC_MODE2_TAMPCTRL_IN2ACT_Pos     = 0x4        // Position of IN2ACT field.
	RTC_MODE2_TAMPCTRL_IN2ACT_Msk     = 0x30       // Bit mask of IN2ACT field.
	RTC_MODE2_TAMPCTRL_IN2ACT_OFF     = 0x0        // Off (Disabled)
	RTC_MODE2_TAMPCTRL_IN2ACT_WAKE    = 0x1        // Wake without timestamp
	RTC_MODE2_TAMPCTRL_IN2ACT_CAPTURE = 0x2        // Capture timestamp
	RTC_MODE2_TAMPCTRL_IN2ACT_ACTL    = 0x3        // Compare IN2 to OUT
	RTC_MODE2_TAMPCTRL_IN3ACT_Pos     = 0x6        // Position of IN3ACT field.
	RTC_MODE2_TAMPCTRL_IN3ACT_Msk     = 0xc0       // Bit mask of IN3ACT field.
	RTC_MODE2_TAMPCTRL_IN3ACT_OFF     = 0x0        // Off (Disabled)
	RTC_MODE2_TAMPCTRL_IN3ACT_WAKE    = 0x1        // Wake without timestamp
	RTC_MODE2_TAMPCTRL_IN3ACT_CAPTURE = 0x2        // Capture timestamp
	RTC_MODE2_TAMPCTRL_IN3ACT_ACTL    = 0x3        // Compare IN3 to OUT
	RTC_MODE2_TAMPCTRL_IN4ACT_Pos     = 0x8        // Position of IN4ACT field.
	RTC_MODE2_TAMPCTRL_IN4ACT_Msk     = 0x300      // Bit mask of IN4ACT field.
	RTC_MODE2_TAMPCTRL_IN4ACT_OFF     = 0x0        // Off (Disabled)
	RTC_MODE2_TAMPCTRL_IN4ACT_WAKE    = 0x1        // Wake without timestamp
	RTC_MODE2_TAMPCTRL_IN4ACT_CAPTURE = 0x2        // Capture timestamp
	RTC_MODE2_TAMPCTRL_IN4ACT_ACTL    = 0x3        // Compare IN4 to OUT
	RTC_MODE2_TAMPCTRL_TAMLVL0_Pos    = 0x10       // Position of TAMLVL0 field.
	RTC_MODE2_TAMPCTRL_TAMLVL0_Msk    = 0x10000    // Bit mask of TAMLVL0 field.
	RTC_MODE2_TAMPCTRL_TAMLVL0        = 0x10000    // Bit TAMLVL0.
	RTC_MODE2_TAMPCTRL_TAMLVL1_Pos    = 0x11       // Position of TAMLVL1 field.
	RTC_MODE2_TAMPCTRL_TAMLVL1_Msk    = 0x20000    // Bit mask of TAMLVL1 field.
	RTC_MODE2_TAMPCTRL_TAMLVL1        = 0x20000    // Bit TAMLVL1.
	RTC_MODE2_TAMPCTRL_TAMLVL2_Pos    = 0x12       // Position of TAMLVL2 field.
	RTC_MODE2_TAMPCTRL_TAMLVL2_Msk    = 0x40000    // Bit mask of TAMLVL2 field.
	RTC_MODE2_TAMPCTRL_TAMLVL2        = 0x40000    // Bit TAMLVL2.
	RTC_MODE2_TAMPCTRL_TAMLVL3_Pos    = 0x13       // Position of TAMLVL3 field.
	RTC_MODE2_TAMPCTRL_TAMLVL3_Msk    = 0x80000    // Bit mask of TAMLVL3 field.
	RTC_MODE2_TAMPCTRL_TAMLVL3        = 0x80000    // Bit TAMLVL3.
	RTC_MODE2_TAMPCTRL_TAMLVL4_Pos    = 0x14       // Position of TAMLVL4 field.
	RTC_MODE2_TAMPCTRL_TAMLVL4_Msk    = 0x100000   // Bit mask of TAMLVL4 field.
	RTC_MODE2_TAMPCTRL_TAMLVL4        = 0x100000   // Bit TAMLVL4.
	RTC_MODE2_TAMPCTRL_DEBNC0_Pos     = 0x18       // Position of DEBNC0 field.
	RTC_MODE2_TAMPCTRL_DEBNC0_Msk     = 0x1000000  // Bit mask of DEBNC0 field.
	RTC_MODE2_TAMPCTRL_DEBNC0         = 0x1000000  // Bit DEBNC0.
	RTC_MODE2_TAMPCTRL_DEBNC1_Pos     = 0x19       // Position of DEBNC1 field.
	RTC_MODE2_TAMPCTRL_DEBNC1_Msk     = 0x2000000  // Bit mask of DEBNC1 field.
	RTC_MODE2_TAMPCTRL_DEBNC1         = 0x2000000  // Bit DEBNC1.
	RTC_MODE2_TAMPCTRL_DEBNC2_Pos     = 0x1a       // Position of DEBNC2 field.
	RTC_MODE2_TAMPCTRL_DEBNC2_Msk     = 0x4000000  // Bit mask of DEBNC2 field.
	RTC_MODE2_TAMPCTRL_DEBNC2         = 0x4000000  // Bit DEBNC2.
	RTC_MODE2_TAMPCTRL_DEBNC3_Pos     = 0x1b       // Position of DEBNC3 field.
	RTC_MODE2_TAMPCTRL_DEBNC3_Msk     = 0x8000000  // Bit mask of DEBNC3 field.
	RTC_MODE2_TAMPCTRL_DEBNC3         = 0x8000000  // Bit DEBNC3.
	RTC_MODE2_TAMPCTRL_DEBNC4_Pos     = 0x1c       // Position of DEBNC4 field.
	RTC_MODE2_TAMPCTRL_DEBNC4_Msk     = 0x10000000 // Bit mask of DEBNC4 field.
	RTC_MODE2_TAMPCTRL_DEBNC4         = 0x10000000 // Bit DEBNC4.

	// TIMESTAMP: MODE2 Timestamp
	RTC_MODE2_TIMESTAMP_SECOND_Pos = 0x0        // Position of SECOND field.
	RTC_MODE2_TIMESTAMP_SECOND_Msk = 0x3f       // Bit mask of SECOND field.
	RTC_MODE2_TIMESTAMP_MINUTE_Pos = 0x6        // Position of MINUTE field.
	RTC_MODE2_TIMESTAMP_MINUTE_Msk = 0xfc0      // Bit mask of MINUTE field.
	RTC_MODE2_TIMESTAMP_HOUR_Pos   = 0xc        // Position of HOUR field.
	RTC_MODE2_TIMESTAMP_HOUR_Msk   = 0x1f000    // Bit mask of HOUR field.
	RTC_MODE2_TIMESTAMP_HOUR_AM    = 0x0        // AM when CLKREP in 12-hour
	RTC_MODE2_TIMESTAMP_HOUR_PM    = 0x10       // PM when CLKREP in 12-hour
	RTC_MODE2_TIMESTAMP_DAY_Pos    = 0x11       // Position of DAY field.
	RTC_MODE2_TIMESTAMP_DAY_Msk    = 0x3e0000   // Bit mask of DAY field.
	RTC_MODE2_TIMESTAMP_MONTH_Pos  = 0x16       // Position of MONTH field.
	RTC_MODE2_TIMESTAMP_MONTH_Msk  = 0x3c00000  // Bit mask of MONTH field.
	RTC_MODE2_TIMESTAMP_YEAR_Pos   = 0x1a       // Position of YEAR field.
	RTC_MODE2_TIMESTAMP_YEAR_Msk   = 0xfc000000 // Bit mask of YEAR field.

	// TAMPID: Tamper ID
	RTC_MODE2_TAMPID_TAMPID0_Pos = 0x0        // Position of TAMPID0 field.
	RTC_MODE2_TAMPID_TAMPID0_Msk = 0x1        // Bit mask of TAMPID0 field.
	RTC_MODE2_TAMPID_TAMPID0     = 0x1        // Bit TAMPID0.
	RTC_MODE2_TAMPID_TAMPID1_Pos = 0x1        // Position of TAMPID1 field.
	RTC_MODE2_TAMPID_TAMPID1_Msk = 0x2        // Bit mask of TAMPID1 field.
	RTC_MODE2_TAMPID_TAMPID1     = 0x2        // Bit TAMPID1.
	RTC_MODE2_TAMPID_TAMPID2_Pos = 0x2        // Position of TAMPID2 field.
	RTC_MODE2_TAMPID_TAMPID2_Msk = 0x4        // Bit mask of TAMPID2 field.
	RTC_MODE2_TAMPID_TAMPID2     = 0x4        // Bit TAMPID2.
	RTC_MODE2_TAMPID_TAMPID3_Pos = 0x3        // Position of TAMPID3 field.
	RTC_MODE2_TAMPID_TAMPID3_Msk = 0x8        // Bit mask of TAMPID3 field.
	RTC_MODE2_TAMPID_TAMPID3     = 0x8        // Bit TAMPID3.
	RTC_MODE2_TAMPID_TAMPID4_Pos = 0x4        // Position of TAMPID4 field.
	RTC_MODE2_TAMPID_TAMPID4_Msk = 0x10       // Bit mask of TAMPID4 field.
	RTC_MODE2_TAMPID_TAMPID4     = 0x10       // Bit TAMPID4.
	RTC_MODE2_TAMPID_TAMPEVT_Pos = 0x1f       // Position of TAMPEVT field.
	RTC_MODE2_TAMPID_TAMPEVT_Msk = 0x80000000 // Bit mask of TAMPEVT field.
	RTC_MODE2_TAMPID_TAMPEVT     = 0x80000000 // Bit TAMPEVT.

	// BKUP: Backup
	RTC_MODE2_BKUP_BKUP_Pos = 0x0        // Position of BKUP field.
	RTC_MODE2_BKUP_BKUP_Msk = 0xffffffff // Bit mask of BKUP field.
)

// Bitfields for SDHC0: SD/MMC Host Controller
const (
	// SSAR: SDMA System Address / Argument 2
	SDHC_SSAR_ADDR_Pos = 0x0        // Position of ADDR field.
	SDHC_SSAR_ADDR_Msk = 0xffffffff // Bit mask of ADDR field.

	// SSAR_CMD23_MODE: SDMA System Address / Argument 2
	SDHC_SSAR_CMD23_MODE_ARG2_Pos = 0x0        // Position of ARG2 field.
	SDHC_SSAR_CMD23_MODE_ARG2_Msk = 0xffffffff // Bit mask of ARG2 field.

	// BSR: Block Size
	SDHC_BSR_BLOCKSIZE_Pos = 0x0    // Position of BLOCKSIZE field.
	SDHC_BSR_BLOCKSIZE_Msk = 0x3ff  // Bit mask of BLOCKSIZE field.
	SDHC_BSR_BOUNDARY_Pos  = 0xc    // Position of BOUNDARY field.
	SDHC_BSR_BOUNDARY_Msk  = 0x7000 // Bit mask of BOUNDARY field.
	SDHC_BSR_BOUNDARY_4K   = 0x0    // 4k bytes
	SDHC_BSR_BOUNDARY_8K   = 0x1    // 8k bytes
	SDHC_BSR_BOUNDARY_16K  = 0x2    // 16k bytes
	SDHC_BSR_BOUNDARY_32K  = 0x3    // 32k bytes
	SDHC_BSR_BOUNDARY_64K  = 0x4    // 64k bytes
	SDHC_BSR_BOUNDARY_128K = 0x5    // 128k bytes
	SDHC_BSR_BOUNDARY_256K = 0x6    // 256k bytes
	SDHC_BSR_BOUNDARY_512K = 0x7    // 512k bytes

	// BCR: Block Count
	SDHC_BCR_BCNT_Pos = 0x0    // Position of BCNT field.
	SDHC_BCR_BCNT_Msk = 0xffff // Bit mask of BCNT field.

	// ARG1R: Argument 1
	SDHC_ARG1R_ARG_Pos = 0x0        // Position of ARG field.
	SDHC_ARG1R_ARG_Msk = 0xffffffff // Bit mask of ARG field.

	// TMR: Transfer Mode
	SDHC_TMR_DMAEN_Pos       = 0x0  // Position of DMAEN field.
	SDHC_TMR_DMAEN_Msk       = 0x1  // Bit mask of DMAEN field.
	SDHC_TMR_DMAEN           = 0x1  // Bit DMAEN.
	SDHC_TMR_DMAEN_DISABLE   = 0x0  // No data transfer or Non DMA data transfer
	SDHC_TMR_DMAEN_ENABLE    = 0x1  // DMA data transfer
	SDHC_TMR_BCEN_Pos        = 0x1  // Position of BCEN field.
	SDHC_TMR_BCEN_Msk        = 0x2  // Bit mask of BCEN field.
	SDHC_TMR_BCEN            = 0x2  // Bit BCEN.
	SDHC_TMR_BCEN_DISABLE    = 0x0  // Disable
	SDHC_TMR_BCEN_ENABLE     = 0x1  // Enable
	SDHC_TMR_ACMDEN_Pos      = 0x2  // Position of ACMDEN field.
	SDHC_TMR_ACMDEN_Msk      = 0xc  // Bit mask of ACMDEN field.
	SDHC_TMR_ACMDEN_DISABLED = 0x0  // Auto Command Disabled
	SDHC_TMR_ACMDEN_CMD12    = 0x1  // Auto CMD12 Enable
	SDHC_TMR_ACMDEN_CMD23    = 0x2  // Auto CMD23 Enable
	SDHC_TMR_DTDSEL_Pos      = 0x4  // Position of DTDSEL field.
	SDHC_TMR_DTDSEL_Msk      = 0x10 // Bit mask of DTDSEL field.
	SDHC_TMR_DTDSEL          = 0x10 // Bit DTDSEL.
	SDHC_TMR_DTDSEL_WRITE    = 0x0  // Write (Host to Card)
	SDHC_TMR_DTDSEL_READ     = 0x1  // Read (Card to Host)
	SDHC_TMR_MSBSEL_Pos      = 0x5  // Position of MSBSEL field.
	SDHC_TMR_MSBSEL_Msk      = 0x20 // Bit mask of MSBSEL field.
	SDHC_TMR_MSBSEL          = 0x20 // Bit MSBSEL.
	SDHC_TMR_MSBSEL_SINGLE   = 0x0  // Single Block
	SDHC_TMR_MSBSEL_MULTIPLE = 0x1  // Multiple Block

	// CR: Command
	SDHC_CR_RESPTYP_Pos         = 0x0    // Position of RESPTYP field.
	SDHC_CR_RESPTYP_Msk         = 0x3    // Bit mask of RESPTYP field.
	SDHC_CR_RESPTYP_NONE        = 0x0    // No response
	SDHC_CR_RESPTYP_136_BIT     = 0x1    // 136-bit response
	SDHC_CR_RESPTYP_48_BIT      = 0x2    // 48-bit response
	SDHC_CR_RESPTYP_48_BIT_BUSY = 0x3    // 48-bit response check busy after response
	SDHC_CR_CMDCCEN_Pos         = 0x3    // Position of CMDCCEN field.
	SDHC_CR_CMDCCEN_Msk         = 0x8    // Bit mask of CMDCCEN field.
	SDHC_CR_CMDCCEN             = 0x8    // Bit CMDCCEN.
	SDHC_CR_CMDCCEN_DISABLE     = 0x0    // Disable
	SDHC_CR_CMDCCEN_ENABLE      = 0x1    // Enable
	SDHC_CR_CMDICEN_Pos         = 0x4    // Position of CMDICEN field.
	SDHC_CR_CMDICEN_Msk         = 0x10   // Bit mask of CMDICEN field.
	SDHC_CR_CMDICEN             = 0x10   // Bit CMDICEN.
	SDHC_CR_CMDICEN_DISABLE     = 0x0    // Disable
	SDHC_CR_CMDICEN_ENABLE      = 0x1    // Enable
	SDHC_CR_DPSEL_Pos           = 0x5    // Position of DPSEL field.
	SDHC_CR_DPSEL_Msk           = 0x20   // Bit mask of DPSEL field.
	SDHC_CR_DPSEL               = 0x20   // Bit DPSEL.
	SDHC_CR_DPSEL_NO_DATA       = 0x0    // No Data Present
	SDHC_CR_DPSEL_DATA          = 0x1    // Data Present
	SDHC_CR_CMDTYP_Pos          = 0x6    // Position of CMDTYP field.
	SDHC_CR_CMDTYP_Msk          = 0xc0   // Bit mask of CMDTYP field.
	SDHC_CR_CMDTYP_NORMAL       = 0x0    // Other commands
	SDHC_CR_CMDTYP_SUSPEND      = 0x1    // CMD52 for writing Bus Suspend in CCCR
	SDHC_CR_CMDTYP_RESUME       = 0x2    // CMD52 for writing Function Select in CCCR
	SDHC_CR_CMDTYP_ABORT        = 0x3    // CMD12, CMD52 for writing I/O Abort in CCCR
	SDHC_CR_CMDIDX_Pos          = 0x8    // Position of CMDIDX field.
	SDHC_CR_CMDIDX_Msk          = 0x3f00 // Bit mask of CMDIDX field.

	// RR: Response
	SDHC_RR_CMDRESP_Pos = 0x0        // Position of CMDRESP field.
	SDHC_RR_CMDRESP_Msk = 0xffffffff // Bit mask of CMDRESP field.

	// BDPR: Buffer Data Port
	SDHC_BDPR_BUFDATA_Pos = 0x0        // Position of BUFDATA field.
	SDHC_BDPR_BUFDATA_Msk = 0xffffffff // Bit mask of BUFDATA field.

	// PSR: Present State
	SDHC_PSR_CMDINHC_Pos     = 0x0       // Position of CMDINHC field.
	SDHC_PSR_CMDINHC_Msk     = 0x1       // Bit mask of CMDINHC field.
	SDHC_PSR_CMDINHC         = 0x1       // Bit CMDINHC.
	SDHC_PSR_CMDINHC_CAN     = 0x0       // Can issue command using only CMD line
	SDHC_PSR_CMDINHC_CANNOT  = 0x1       // Cannot issue command
	SDHC_PSR_CMDINHD_Pos     = 0x1       // Position of CMDINHD field.
	SDHC_PSR_CMDINHD_Msk     = 0x2       // Bit mask of CMDINHD field.
	SDHC_PSR_CMDINHD         = 0x2       // Bit CMDINHD.
	SDHC_PSR_CMDINHD_CAN     = 0x0       // Can issue command which uses the DAT line
	SDHC_PSR_CMDINHD_CANNOT  = 0x1       // Cannot issue command which uses the DAT line
	SDHC_PSR_DLACT_Pos       = 0x2       // Position of DLACT field.
	SDHC_PSR_DLACT_Msk       = 0x4       // Bit mask of DLACT field.
	SDHC_PSR_DLACT           = 0x4       // Bit DLACT.
	SDHC_PSR_DLACT_INACTIVE  = 0x0       // DAT Line Inactive
	SDHC_PSR_DLACT_ACTIVE    = 0x1       // DAT Line Active
	SDHC_PSR_RTREQ_Pos       = 0x3       // Position of RTREQ field.
	SDHC_PSR_RTREQ_Msk       = 0x8       // Bit mask of RTREQ field.
	SDHC_PSR_RTREQ           = 0x8       // Bit RTREQ.
	SDHC_PSR_RTREQ_OK        = 0x0       // Fixed or well-tuned sampling clock
	SDHC_PSR_RTREQ_REQUIRED  = 0x1       // Sampling clock needs re-tuning
	SDHC_PSR_WTACT_Pos       = 0x8       // Position of WTACT field.
	SDHC_PSR_WTACT_Msk       = 0x100     // Bit mask of WTACT field.
	SDHC_PSR_WTACT           = 0x100     // Bit WTACT.
	SDHC_PSR_WTACT_NO        = 0x0       // No valid data
	SDHC_PSR_WTACT_YES       = 0x1       // Transferring data
	SDHC_PSR_RTACT_Pos       = 0x9       // Position of RTACT field.
	SDHC_PSR_RTACT_Msk       = 0x200     // Bit mask of RTACT field.
	SDHC_PSR_RTACT           = 0x200     // Bit RTACT.
	SDHC_PSR_RTACT_NO        = 0x0       // No valid data
	SDHC_PSR_RTACT_YES       = 0x1       // Transferring data
	SDHC_PSR_BUFWREN_Pos     = 0xa       // Position of BUFWREN field.
	SDHC_PSR_BUFWREN_Msk     = 0x400     // Bit mask of BUFWREN field.
	SDHC_PSR_BUFWREN         = 0x400     // Bit BUFWREN.
	SDHC_PSR_BUFWREN_DISABLE = 0x0       // Write disable
	SDHC_PSR_BUFWREN_ENABLE  = 0x1       // Write enable
	SDHC_PSR_BUFRDEN_Pos     = 0xb       // Position of BUFRDEN field.
	SDHC_PSR_BUFRDEN_Msk     = 0x800     // Bit mask of BUFRDEN field.
	SDHC_PSR_BUFRDEN         = 0x800     // Bit BUFRDEN.
	SDHC_PSR_BUFRDEN_DISABLE = 0x0       // Read disable
	SDHC_PSR_BUFRDEN_ENABLE  = 0x1       // Read enable
	SDHC_PSR_CARDINS_Pos     = 0x10      // Position of CARDINS field.
	SDHC_PSR_CARDINS_Msk     = 0x10000   // Bit mask of CARDINS field.
	SDHC_PSR_CARDINS         = 0x10000   // Bit CARDINS.
	SDHC_PSR_CARDINS_NO      = 0x0       // Reset or Debouncing or No Card
	SDHC_PSR_CARDINS_YES     = 0x1       // Card inserted
	SDHC_PSR_CARDSS_Pos      = 0x11      // Position of CARDSS field.
	SDHC_PSR_CARDSS_Msk      = 0x20000   // Bit mask of CARDSS field.
	SDHC_PSR_CARDSS          = 0x20000   // Bit CARDSS.
	SDHC_PSR_CARDSS_NO       = 0x0       // Reset or Debouncing
	SDHC_PSR_CARDSS_YES      = 0x1       // No Card or Insered
	SDHC_PSR_CARDDPL_Pos     = 0x12      // Position of CARDDPL field.
	SDHC_PSR_CARDDPL_Msk     = 0x40000   // Bit mask of CARDDPL field.
	SDHC_PSR_CARDDPL         = 0x40000   // Bit CARDDPL.
	SDHC_PSR_CARDDPL_NO      = 0x0       // No card present (SDCD#=1)
	SDHC_PSR_CARDDPL_YES     = 0x1       // Card present (SDCD#=0)
	SDHC_PSR_WRPPL_Pos       = 0x13      // Position of WRPPL field.
	SDHC_PSR_WRPPL_Msk       = 0x80000   // Bit mask of WRPPL field.
	SDHC_PSR_WRPPL           = 0x80000   // Bit WRPPL.
	SDHC_PSR_WRPPL_PROTECTED = 0x0       // Write protected (SDWP#=0)
	SDHC_PSR_WRPPL_ENABLED   = 0x1       // Write enabled (SDWP#=1)
	SDHC_PSR_DATLL_Pos       = 0x14      // Position of DATLL field.
	SDHC_PSR_DATLL_Msk       = 0xf00000  // Bit mask of DATLL field.
	SDHC_PSR_CMDLL_Pos       = 0x18      // Position of CMDLL field.
	SDHC_PSR_CMDLL_Msk       = 0x1000000 // Bit mask of CMDLL field.
	SDHC_PSR_CMDLL           = 0x1000000 // Bit CMDLL.

	// HC1R: Host Control 1
	SDHC_HC1R_LEDCTRL_Pos     = 0x0  // Position of LEDCTRL field.
	SDHC_HC1R_LEDCTRL_Msk     = 0x1  // Bit mask of LEDCTRL field.
	SDHC_HC1R_LEDCTRL         = 0x1  // Bit LEDCTRL.
	SDHC_HC1R_LEDCTRL_OFF     = 0x0  // LED off
	SDHC_HC1R_LEDCTRL_ON      = 0x1  // LED on
	SDHC_HC1R_DW_Pos          = 0x1  // Position of DW field.
	SDHC_HC1R_DW_Msk          = 0x2  // Bit mask of DW field.
	SDHC_HC1R_DW              = 0x2  // Bit DW.
	SDHC_HC1R_DW_1BIT         = 0x0  // 1-bit mode
	SDHC_HC1R_DW_4BIT         = 0x1  // 4-bit mode
	SDHC_HC1R_HSEN_Pos        = 0x2  // Position of HSEN field.
	SDHC_HC1R_HSEN_Msk        = 0x4  // Bit mask of HSEN field.
	SDHC_HC1R_HSEN            = 0x4  // Bit HSEN.
	SDHC_HC1R_HSEN_NORMAL     = 0x0  // Normal Speed mode
	SDHC_HC1R_HSEN_HIGH       = 0x1  // High Speed mode
	SDHC_HC1R_DMASEL_Pos      = 0x3  // Position of DMASEL field.
	SDHC_HC1R_DMASEL_Msk      = 0x18 // Bit mask of DMASEL field.
	SDHC_HC1R_DMASEL_SDMA     = 0x0  // SDMA is selected
	SDHC_HC1R_DMASEL_32BIT    = 0x2  // 32-bit Address ADMA2 is selected
	SDHC_HC1R_CARDDTL_Pos     = 0x6  // Position of CARDDTL field.
	SDHC_HC1R_CARDDTL_Msk     = 0x40 // Bit mask of CARDDTL field.
	SDHC_HC1R_CARDDTL         = 0x40 // Bit CARDDTL.
	SDHC_HC1R_CARDDTL_NO      = 0x0  // No Card
	SDHC_HC1R_CARDDTL_YES     = 0x1  // Card Inserted
	SDHC_HC1R_CARDDSEL_Pos    = 0x7  // Position of CARDDSEL field.
	SDHC_HC1R_CARDDSEL_Msk    = 0x80 // Bit mask of CARDDSEL field.
	SDHC_HC1R_CARDDSEL        = 0x80 // Bit CARDDSEL.
	SDHC_HC1R_CARDDSEL_NORMAL = 0x0  // SDCD# is selected (for normal use)
	SDHC_HC1R_CARDDSEL_TEST   = 0x1  // The Card Select Test Level is selected (for test purpose)

	// HC1R_EMMC_MODE: Host Control 1
	SDHC_HC1R_EMMC_MODE_DW_Pos       = 0x1  // Position of DW field.
	SDHC_HC1R_EMMC_MODE_DW_Msk       = 0x2  // Bit mask of DW field.
	SDHC_HC1R_EMMC_MODE_DW           = 0x2  // Bit DW.
	SDHC_HC1R_EMMC_MODE_DW_1BIT      = 0x0  // 1-bit mode
	SDHC_HC1R_EMMC_MODE_DW_4BIT      = 0x1  // 4-bit mode
	SDHC_HC1R_EMMC_MODE_HSEN_Pos     = 0x2  // Position of HSEN field.
	SDHC_HC1R_EMMC_MODE_HSEN_Msk     = 0x4  // Bit mask of HSEN field.
	SDHC_HC1R_EMMC_MODE_HSEN         = 0x4  // Bit HSEN.
	SDHC_HC1R_EMMC_MODE_HSEN_NORMAL  = 0x0  // Normal Speed mode
	SDHC_HC1R_EMMC_MODE_HSEN_HIGH    = 0x1  // High Speed mode
	SDHC_HC1R_EMMC_MODE_DMASEL_Pos   = 0x3  // Position of DMASEL field.
	SDHC_HC1R_EMMC_MODE_DMASEL_Msk   = 0x18 // Bit mask of DMASEL field.
	SDHC_HC1R_EMMC_MODE_DMASEL_SDMA  = 0x0  // SDMA is selected
	SDHC_HC1R_EMMC_MODE_DMASEL_32BIT = 0x2  // 32-bit Address ADMA2 is selected

	// PCR: Power Control
	SDHC_PCR_SDBPWR_Pos  = 0x0 // Position of SDBPWR field.
	SDHC_PCR_SDBPWR_Msk  = 0x1 // Bit mask of SDBPWR field.
	SDHC_PCR_SDBPWR      = 0x1 // Bit SDBPWR.
	SDHC_PCR_SDBPWR_OFF  = 0x0 // Power off
	SDHC_PCR_SDBPWR_ON   = 0x1 // Power on
	SDHC_PCR_SDBVSEL_Pos = 0x1 // Position of SDBVSEL field.
	SDHC_PCR_SDBVSEL_Msk = 0xe // Bit mask of SDBVSEL field.
	SDHC_PCR_SDBVSEL_1V8 = 0x5 // 1.8V (Typ.)
	SDHC_PCR_SDBVSEL_3V0 = 0x6 // 3.0V (Typ.)
	SDHC_PCR_SDBVSEL_3V3 = 0x7 // 3.3V (Typ.)

	// BGCR: Block Gap Control
	SDHC_BGCR_STPBGR_Pos      = 0x0 // Position of STPBGR field.
	SDHC_BGCR_STPBGR_Msk      = 0x1 // Bit mask of STPBGR field.
	SDHC_BGCR_STPBGR          = 0x1 // Bit STPBGR.
	SDHC_BGCR_STPBGR_TRANSFER = 0x0 // Transfer
	SDHC_BGCR_STPBGR_STOP     = 0x1 // Stop
	SDHC_BGCR_CONTR_Pos       = 0x1 // Position of CONTR field.
	SDHC_BGCR_CONTR_Msk       = 0x2 // Bit mask of CONTR field.
	SDHC_BGCR_CONTR           = 0x2 // Bit CONTR.
	SDHC_BGCR_CONTR_GO_ON     = 0x0 // Not affected
	SDHC_BGCR_CONTR_RESTART   = 0x1 // Restart
	SDHC_BGCR_RWCTRL_Pos      = 0x2 // Position of RWCTRL field.
	SDHC_BGCR_RWCTRL_Msk      = 0x4 // Bit mask of RWCTRL field.
	SDHC_BGCR_RWCTRL          = 0x4 // Bit RWCTRL.
	SDHC_BGCR_RWCTRL_DISABLE  = 0x0 // Disable Read Wait Control
	SDHC_BGCR_RWCTRL_ENABLE   = 0x1 // Enable Read Wait Control
	SDHC_BGCR_INTBG_Pos       = 0x3 // Position of INTBG field.
	SDHC_BGCR_INTBG_Msk       = 0x8 // Bit mask of INTBG field.
	SDHC_BGCR_INTBG           = 0x8 // Bit INTBG.
	SDHC_BGCR_INTBG_DISABLED  = 0x0 // Disabled
	SDHC_BGCR_INTBG_ENABLED   = 0x1 // Enabled

	// BGCR_EMMC_MODE: Block Gap Control
	SDHC_BGCR_EMMC_MODE_STPBGR_Pos      = 0x0 // Position of STPBGR field.
	SDHC_BGCR_EMMC_MODE_STPBGR_Msk      = 0x1 // Bit mask of STPBGR field.
	SDHC_BGCR_EMMC_MODE_STPBGR          = 0x1 // Bit STPBGR.
	SDHC_BGCR_EMMC_MODE_STPBGR_TRANSFER = 0x0 // Transfer
	SDHC_BGCR_EMMC_MODE_STPBGR_STOP     = 0x1 // Stop
	SDHC_BGCR_EMMC_MODE_CONTR_Pos       = 0x1 // Position of CONTR field.
	SDHC_BGCR_EMMC_MODE_CONTR_Msk       = 0x2 // Bit mask of CONTR field.
	SDHC_BGCR_EMMC_MODE_CONTR           = 0x2 // Bit CONTR.
	SDHC_BGCR_EMMC_MODE_CONTR_GO_ON     = 0x0 // Not affected
	SDHC_BGCR_EMMC_MODE_CONTR_RESTART   = 0x1 // Restart

	// WCR: Wakeup Control
	SDHC_WCR_WKENCINT_Pos     = 0x0 // Position of WKENCINT field.
	SDHC_WCR_WKENCINT_Msk     = 0x1 // Bit mask of WKENCINT field.
	SDHC_WCR_WKENCINT         = 0x1 // Bit WKENCINT.
	SDHC_WCR_WKENCINT_DISABLE = 0x0 // Disable
	SDHC_WCR_WKENCINT_ENABLE  = 0x1 // Enable
	SDHC_WCR_WKENCINS_Pos     = 0x1 // Position of WKENCINS field.
	SDHC_WCR_WKENCINS_Msk     = 0x2 // Bit mask of WKENCINS field.
	SDHC_WCR_WKENCINS         = 0x2 // Bit WKENCINS.
	SDHC_WCR_WKENCINS_DISABLE = 0x0 // Disable
	SDHC_WCR_WKENCINS_ENABLE  = 0x1 // Enable
	SDHC_WCR_WKENCREM_Pos     = 0x2 // Position of WKENCREM field.
	SDHC_WCR_WKENCREM_Msk     = 0x4 // Bit mask of WKENCREM field.
	SDHC_WCR_WKENCREM         = 0x4 // Bit WKENCREM.
	SDHC_WCR_WKENCREM_DISABLE = 0x0 // Disable
	SDHC_WCR_WKENCREM_ENABLE  = 0x1 // Enable

	// CCR: Clock Control
	SDHC_CCR_INTCLKEN_Pos      = 0x0    // Position of INTCLKEN field.
	SDHC_CCR_INTCLKEN_Msk      = 0x1    // Bit mask of INTCLKEN field.
	SDHC_CCR_INTCLKEN          = 0x1    // Bit INTCLKEN.
	SDHC_CCR_INTCLKEN_OFF      = 0x0    // Stop
	SDHC_CCR_INTCLKEN_ON       = 0x1    // Oscillate
	SDHC_CCR_INTCLKS_Pos       = 0x1    // Position of INTCLKS field.
	SDHC_CCR_INTCLKS_Msk       = 0x2    // Bit mask of INTCLKS field.
	SDHC_CCR_INTCLKS           = 0x2    // Bit INTCLKS.
	SDHC_CCR_INTCLKS_NOT_READY = 0x0    // Not Ready
	SDHC_CCR_INTCLKS_READY     = 0x1    // Ready
	SDHC_CCR_SDCLKEN_Pos       = 0x2    // Position of SDCLKEN field.
	SDHC_CCR_SDCLKEN_Msk       = 0x4    // Bit mask of SDCLKEN field.
	SDHC_CCR_SDCLKEN           = 0x4    // Bit SDCLKEN.
	SDHC_CCR_SDCLKEN_DISABLE   = 0x0    // Disable
	SDHC_CCR_SDCLKEN_ENABLE    = 0x1    // Enable
	SDHC_CCR_CLKGSEL_Pos       = 0x5    // Position of CLKGSEL field.
	SDHC_CCR_CLKGSEL_Msk       = 0x20   // Bit mask of CLKGSEL field.
	SDHC_CCR_CLKGSEL           = 0x20   // Bit CLKGSEL.
	SDHC_CCR_CLKGSEL_DIV       = 0x0    // Divided Clock Mode
	SDHC_CCR_CLKGSEL_PROG      = 0x1    // Programmable Clock Mode
	SDHC_CCR_USDCLKFSEL_Pos    = 0x6    // Position of USDCLKFSEL field.
	SDHC_CCR_USDCLKFSEL_Msk    = 0xc0   // Bit mask of USDCLKFSEL field.
	SDHC_CCR_SDCLKFSEL_Pos     = 0x8    // Position of SDCLKFSEL field.
	SDHC_CCR_SDCLKFSEL_Msk     = 0xff00 // Bit mask of SDCLKFSEL field.

	// TCR: Timeout Control
	SDHC_TCR_DTCVAL_Pos = 0x0 // Position of DTCVAL field.
	SDHC_TCR_DTCVAL_Msk = 0xf // Bit mask of DTCVAL field.

	// SRR: Software Reset
	SDHC_SRR_SWRSTALL_Pos   = 0x0 // Position of SWRSTALL field.
	SDHC_SRR_SWRSTALL_Msk   = 0x1 // Bit mask of SWRSTALL field.
	SDHC_SRR_SWRSTALL       = 0x1 // Bit SWRSTALL.
	SDHC_SRR_SWRSTALL_WORK  = 0x0 // Work
	SDHC_SRR_SWRSTALL_RESET = 0x1 // Reset
	SDHC_SRR_SWRSTCMD_Pos   = 0x1 // Position of SWRSTCMD field.
	SDHC_SRR_SWRSTCMD_Msk   = 0x2 // Bit mask of SWRSTCMD field.
	SDHC_SRR_SWRSTCMD       = 0x2 // Bit SWRSTCMD.
	SDHC_SRR_SWRSTCMD_WORK  = 0x0 // Work
	SDHC_SRR_SWRSTCMD_RESET = 0x1 // Reset
	SDHC_SRR_SWRSTDAT_Pos   = 0x2 // Position of SWRSTDAT field.
	SDHC_SRR_SWRSTDAT_Msk   = 0x4 // Bit mask of SWRSTDAT field.
	SDHC_SRR_SWRSTDAT       = 0x4 // Bit SWRSTDAT.
	SDHC_SRR_SWRSTDAT_WORK  = 0x0 // Work
	SDHC_SRR_SWRSTDAT_RESET = 0x1 // Reset

	// NISTR: Normal Interrupt Status
	SDHC_NISTR_CMDC_Pos   = 0x0    // Position of CMDC field.
	SDHC_NISTR_CMDC_Msk   = 0x1    // Bit mask of CMDC field.
	SDHC_NISTR_CMDC       = 0x1    // Bit CMDC.
	SDHC_NISTR_CMDC_NO    = 0x0    // No command complete
	SDHC_NISTR_CMDC_YES   = 0x1    // Command complete
	SDHC_NISTR_TRFC_Pos   = 0x1    // Position of TRFC field.
	SDHC_NISTR_TRFC_Msk   = 0x2    // Bit mask of TRFC field.
	SDHC_NISTR_TRFC       = 0x2    // Bit TRFC.
	SDHC_NISTR_TRFC_NO    = 0x0    // Not complete
	SDHC_NISTR_TRFC_YES   = 0x1    // Command execution is completed
	SDHC_NISTR_BLKGE_Pos  = 0x2    // Position of BLKGE field.
	SDHC_NISTR_BLKGE_Msk  = 0x4    // Bit mask of BLKGE field.
	SDHC_NISTR_BLKGE      = 0x4    // Bit BLKGE.
	SDHC_NISTR_BLKGE_NO   = 0x0    // No Block Gap Event
	SDHC_NISTR_BLKGE_STOP = 0x1    // Transaction stopped at block gap
	SDHC_NISTR_DMAINT_Pos = 0x3    // Position of DMAINT field.
	SDHC_NISTR_DMAINT_Msk = 0x8    // Bit mask of DMAINT field.
	SDHC_NISTR_DMAINT     = 0x8    // Bit DMAINT.
	SDHC_NISTR_DMAINT_NO  = 0x0    // No DMA Interrupt
	SDHC_NISTR_DMAINT_YES = 0x1    // DMA Interrupt is generated
	SDHC_NISTR_BWRRDY_Pos = 0x4    // Position of BWRRDY field.
	SDHC_NISTR_BWRRDY_Msk = 0x10   // Bit mask of BWRRDY field.
	SDHC_NISTR_BWRRDY     = 0x10   // Bit BWRRDY.
	SDHC_NISTR_BWRRDY_NO  = 0x0    // Not ready to write buffer
	SDHC_NISTR_BWRRDY_YES = 0x1    // Ready to write buffer
	SDHC_NISTR_BRDRDY_Pos = 0x5    // Position of BRDRDY field.
	SDHC_NISTR_BRDRDY_Msk = 0x20   // Bit mask of BRDRDY field.
	SDHC_NISTR_BRDRDY     = 0x20   // Bit BRDRDY.
	SDHC_NISTR_BRDRDY_NO  = 0x0    // Not ready to read buffer
	SDHC_NISTR_BRDRDY_YES = 0x1    // Ready to read buffer
	SDHC_NISTR_CINS_Pos   = 0x6    // Position of CINS field.
	SDHC_NISTR_CINS_Msk   = 0x40   // Bit mask of CINS field.
	SDHC_NISTR_CINS       = 0x40   // Bit CINS.
	SDHC_NISTR_CINS_NO    = 0x0    // Card state stable or Debouncing
	SDHC_NISTR_CINS_YES   = 0x1    // Card inserted
	SDHC_NISTR_CREM_Pos   = 0x7    // Position of CREM field.
	SDHC_NISTR_CREM_Msk   = 0x80   // Bit mask of CREM field.
	SDHC_NISTR_CREM       = 0x80   // Bit CREM.
	SDHC_NISTR_CREM_NO    = 0x0    // Card state stable or Debouncing
	SDHC_NISTR_CREM_YES   = 0x1    // Card Removed
	SDHC_NISTR_CINT_Pos   = 0x8    // Position of CINT field.
	SDHC_NISTR_CINT_Msk   = 0x100  // Bit mask of CINT field.
	SDHC_NISTR_CINT       = 0x100  // Bit CINT.
	SDHC_NISTR_CINT_NO    = 0x0    // No Card Interrupt
	SDHC_NISTR_CINT_YES   = 0x1    // Generate Card Interrupt
	SDHC_NISTR_ERRINT_Pos = 0xf    // Position of ERRINT field.
	SDHC_NISTR_ERRINT_Msk = 0x8000 // Bit mask of ERRINT field.
	SDHC_NISTR_ERRINT     = 0x8000 // Bit ERRINT.
	SDHC_NISTR_ERRINT_NO  = 0x0    // No Error
	SDHC_NISTR_ERRINT_YES = 0x1    // Error

	// NISTR_EMMC_MODE: Normal Interrupt Status
	SDHC_NISTR_EMMC_MODE_CMDC_Pos   = 0x0    // Position of CMDC field.
	SDHC_NISTR_EMMC_MODE_CMDC_Msk   = 0x1    // Bit mask of CMDC field.
	SDHC_NISTR_EMMC_MODE_CMDC       = 0x1    // Bit CMDC.
	SDHC_NISTR_EMMC_MODE_CMDC_NO    = 0x0    // No command complete
	SDHC_NISTR_EMMC_MODE_CMDC_YES   = 0x1    // Command complete
	SDHC_NISTR_EMMC_MODE_TRFC_Pos   = 0x1    // Position of TRFC field.
	SDHC_NISTR_EMMC_MODE_TRFC_Msk   = 0x2    // Bit mask of TRFC field.
	SDHC_NISTR_EMMC_MODE_TRFC       = 0x2    // Bit TRFC.
	SDHC_NISTR_EMMC_MODE_TRFC_NO    = 0x0    // Not complete
	SDHC_NISTR_EMMC_MODE_TRFC_YES   = 0x1    // Command execution is completed
	SDHC_NISTR_EMMC_MODE_BLKGE_Pos  = 0x2    // Position of BLKGE field.
	SDHC_NISTR_EMMC_MODE_BLKGE_Msk  = 0x4    // Bit mask of BLKGE field.
	SDHC_NISTR_EMMC_MODE_BLKGE      = 0x4    // Bit BLKGE.
	SDHC_NISTR_EMMC_MODE_BLKGE_NO   = 0x0    // No Block Gap Event
	SDHC_NISTR_EMMC_MODE_BLKGE_STOP = 0x1    // Transaction stopped at block gap
	SDHC_NISTR_EMMC_MODE_DMAINT_Pos = 0x3    // Position of DMAINT field.
	SDHC_NISTR_EMMC_MODE_DMAINT_Msk = 0x8    // Bit mask of DMAINT field.
	SDHC_NISTR_EMMC_MODE_DMAINT     = 0x8    // Bit DMAINT.
	SDHC_NISTR_EMMC_MODE_DMAINT_NO  = 0x0    // No DMA Interrupt
	SDHC_NISTR_EMMC_MODE_DMAINT_YES = 0x1    // DMA Interrupt is generated
	SDHC_NISTR_EMMC_MODE_BWRRDY_Pos = 0x4    // Position of BWRRDY field.
	SDHC_NISTR_EMMC_MODE_BWRRDY_Msk = 0x10   // Bit mask of BWRRDY field.
	SDHC_NISTR_EMMC_MODE_BWRRDY     = 0x10   // Bit BWRRDY.
	SDHC_NISTR_EMMC_MODE_BWRRDY_NO  = 0x0    // Not ready to write buffer
	SDHC_NISTR_EMMC_MODE_BWRRDY_YES = 0x1    // Ready to write buffer
	SDHC_NISTR_EMMC_MODE_BRDRDY_Pos = 0x5    // Position of BRDRDY field.
	SDHC_NISTR_EMMC_MODE_BRDRDY_Msk = 0x20   // Bit mask of BRDRDY field.
	SDHC_NISTR_EMMC_MODE_BRDRDY     = 0x20   // Bit BRDRDY.
	SDHC_NISTR_EMMC_MODE_BRDRDY_NO  = 0x0    // Not ready to read buffer
	SDHC_NISTR_EMMC_MODE_BRDRDY_YES = 0x1    // Ready to read buffer
	SDHC_NISTR_EMMC_MODE_BOOTAR_Pos = 0xe    // Position of BOOTAR field.
	SDHC_NISTR_EMMC_MODE_BOOTAR_Msk = 0x4000 // Bit mask of BOOTAR field.
	SDHC_NISTR_EMMC_MODE_BOOTAR     = 0x4000 // Bit BOOTAR.
	SDHC_NISTR_EMMC_MODE_ERRINT_Pos = 0xf    // Position of ERRINT field.
	SDHC_NISTR_EMMC_MODE_ERRINT_Msk = 0x8000 // Bit mask of ERRINT field.
	SDHC_NISTR_EMMC_MODE_ERRINT     = 0x8000 // Bit ERRINT.
	SDHC_NISTR_EMMC_MODE_ERRINT_NO  = 0x0    // No Error
	SDHC_NISTR_EMMC_MODE_ERRINT_YES = 0x1    // Error

	// EISTR: Error Interrupt Status
	SDHC_EISTR_CMDTEO_Pos = 0x0   // Position of CMDTEO field.
	SDHC_EISTR_CMDTEO_Msk = 0x1   // Bit mask of CMDTEO field.
	SDHC_EISTR_CMDTEO     = 0x1   // Bit CMDTEO.
	SDHC_EISTR_CMDTEO_NO  = 0x0   // No Error
	SDHC_EISTR_CMDTEO_YES = 0x1   // Timeout
	SDHC_EISTR_CMDCRC_Pos = 0x1   // Position of CMDCRC field.
	SDHC_EISTR_CMDCRC_Msk = 0x2   // Bit mask of CMDCRC field.
	SDHC_EISTR_CMDCRC     = 0x2   // Bit CMDCRC.
	SDHC_EISTR_CMDCRC_NO  = 0x0   // No Error
	SDHC_EISTR_CMDCRC_YES = 0x1   // CRC Error Generated
	SDHC_EISTR_CMDEND_Pos = 0x2   // Position of CMDEND field.
	SDHC_EISTR_CMDEND_Msk = 0x4   // Bit mask of CMDEND field.
	SDHC_EISTR_CMDEND     = 0x4   // Bit CMDEND.
	SDHC_EISTR_CMDEND_NO  = 0x0   // No error
	SDHC_EISTR_CMDEND_YES = 0x1   // End Bit Error Generated
	SDHC_EISTR_CMDIDX_Pos = 0x3   // Position of CMDIDX field.
	SDHC_EISTR_CMDIDX_Msk = 0x8   // Bit mask of CMDIDX field.
	SDHC_EISTR_CMDIDX     = 0x8   // Bit CMDIDX.
	SDHC_EISTR_CMDIDX_NO  = 0x0   // No Error
	SDHC_EISTR_CMDIDX_YES = 0x1   // Error
	SDHC_EISTR_DATTEO_Pos = 0x4   // Position of DATTEO field.
	SDHC_EISTR_DATTEO_Msk = 0x10  // Bit mask of DATTEO field.
	SDHC_EISTR_DATTEO     = 0x10  // Bit DATTEO.
	SDHC_EISTR_DATTEO_NO  = 0x0   // No Error
	SDHC_EISTR_DATTEO_YES = 0x1   // Timeout
	SDHC_EISTR_DATCRC_Pos = 0x5   // Position of DATCRC field.
	SDHC_EISTR_DATCRC_Msk = 0x20  // Bit mask of DATCRC field.
	SDHC_EISTR_DATCRC     = 0x20  // Bit DATCRC.
	SDHC_EISTR_DATCRC_NO  = 0x0   // No Error
	SDHC_EISTR_DATCRC_YES = 0x1   // Error
	SDHC_EISTR_DATEND_Pos = 0x6   // Position of DATEND field.
	SDHC_EISTR_DATEND_Msk = 0x40  // Bit mask of DATEND field.
	SDHC_EISTR_DATEND     = 0x40  // Bit DATEND.
	SDHC_EISTR_DATEND_NO  = 0x0   // No Error
	SDHC_EISTR_DATEND_YES = 0x1   // Error
	SDHC_EISTR_CURLIM_Pos = 0x7   // Position of CURLIM field.
	SDHC_EISTR_CURLIM_Msk = 0x80  // Bit mask of CURLIM field.
	SDHC_EISTR_CURLIM     = 0x80  // Bit CURLIM.
	SDHC_EISTR_CURLIM_NO  = 0x0   // No Error
	SDHC_EISTR_CURLIM_YES = 0x1   // Power Fail
	SDHC_EISTR_ACMD_Pos   = 0x8   // Position of ACMD field.
	SDHC_EISTR_ACMD_Msk   = 0x100 // Bit mask of ACMD field.
	SDHC_EISTR_ACMD       = 0x100 // Bit ACMD.
	SDHC_EISTR_ACMD_NO    = 0x0   // No Error
	SDHC_EISTR_ACMD_YES   = 0x1   // Error
	SDHC_EISTR_ADMA_Pos   = 0x9   // Position of ADMA field.
	SDHC_EISTR_ADMA_Msk   = 0x200 // Bit mask of ADMA field.
	SDHC_EISTR_ADMA       = 0x200 // Bit ADMA.
	SDHC_EISTR_ADMA_NO    = 0x0   // No Error
	SDHC_EISTR_ADMA_YES   = 0x1   // Error

	// EISTR_EMMC_MODE: Error Interrupt Status
	SDHC_EISTR_EMMC_MODE_CMDTEO_Pos = 0x0    // Position of CMDTEO field.
	SDHC_EISTR_EMMC_MODE_CMDTEO_Msk = 0x1    // Bit mask of CMDTEO field.
	SDHC_EISTR_EMMC_MODE_CMDTEO     = 0x1    // Bit CMDTEO.
	SDHC_EISTR_EMMC_MODE_CMDTEO_NO  = 0x0    // No Error
	SDHC_EISTR_EMMC_MODE_CMDTEO_YES = 0x1    // Timeout
	SDHC_EISTR_EMMC_MODE_CMDCRC_Pos = 0x1    // Position of CMDCRC field.
	SDHC_EISTR_EMMC_MODE_CMDCRC_Msk = 0x2    // Bit mask of CMDCRC field.
	SDHC_EISTR_EMMC_MODE_CMDCRC     = 0x2    // Bit CMDCRC.
	SDHC_EISTR_EMMC_MODE_CMDCRC_NO  = 0x0    // No Error
	SDHC_EISTR_EMMC_MODE_CMDCRC_YES = 0x1    // CRC Error Generated
	SDHC_EISTR_EMMC_MODE_CMDEND_Pos = 0x2    // Position of CMDEND field.
	SDHC_EISTR_EMMC_MODE_CMDEND_Msk = 0x4    // Bit mask of CMDEND field.
	SDHC_EISTR_EMMC_MODE_CMDEND     = 0x4    // Bit CMDEND.
	SDHC_EISTR_EMMC_MODE_CMDEND_NO  = 0x0    // No error
	SDHC_EISTR_EMMC_MODE_CMDEND_YES = 0x1    // End Bit Error Generated
	SDHC_EISTR_EMMC_MODE_CMDIDX_Pos = 0x3    // Position of CMDIDX field.
	SDHC_EISTR_EMMC_MODE_CMDIDX_Msk = 0x8    // Bit mask of CMDIDX field.
	SDHC_EISTR_EMMC_MODE_CMDIDX     = 0x8    // Bit CMDIDX.
	SDHC_EISTR_EMMC_MODE_CMDIDX_NO  = 0x0    // No Error
	SDHC_EISTR_EMMC_MODE_CMDIDX_YES = 0x1    // Error
	SDHC_EISTR_EMMC_MODE_DATTEO_Pos = 0x4    // Position of DATTEO field.
	SDHC_EISTR_EMMC_MODE_DATTEO_Msk = 0x10   // Bit mask of DATTEO field.
	SDHC_EISTR_EMMC_MODE_DATTEO     = 0x10   // Bit DATTEO.
	SDHC_EISTR_EMMC_MODE_DATTEO_NO  = 0x0    // No Error
	SDHC_EISTR_EMMC_MODE_DATTEO_YES = 0x1    // Timeout
	SDHC_EISTR_EMMC_MODE_DATCRC_Pos = 0x5    // Position of DATCRC field.
	SDHC_EISTR_EMMC_MODE_DATCRC_Msk = 0x20   // Bit mask of DATCRC field.
	SDHC_EISTR_EMMC_MODE_DATCRC     = 0x20   // Bit DATCRC.
	SDHC_EISTR_EMMC_MODE_DATCRC_NO  = 0x0    // No Error
	SDHC_EISTR_EMMC_MODE_DATCRC_YES = 0x1    // Error
	SDHC_EISTR_EMMC_MODE_DATEND_Pos = 0x6    // Position of DATEND field.
	SDHC_EISTR_EMMC_MODE_DATEND_Msk = 0x40   // Bit mask of DATEND field.
	SDHC_EISTR_EMMC_MODE_DATEND     = 0x40   // Bit DATEND.
	SDHC_EISTR_EMMC_MODE_DATEND_NO  = 0x0    // No Error
	SDHC_EISTR_EMMC_MODE_DATEND_YES = 0x1    // Error
	SDHC_EISTR_EMMC_MODE_CURLIM_Pos = 0x7    // Position of CURLIM field.
	SDHC_EISTR_EMMC_MODE_CURLIM_Msk = 0x80   // Bit mask of CURLIM field.
	SDHC_EISTR_EMMC_MODE_CURLIM     = 0x80   // Bit CURLIM.
	SDHC_EISTR_EMMC_MODE_CURLIM_NO  = 0x0    // No Error
	SDHC_EISTR_EMMC_MODE_CURLIM_YES = 0x1    // Power Fail
	SDHC_EISTR_EMMC_MODE_ACMD_Pos   = 0x8    // Position of ACMD field.
	SDHC_EISTR_EMMC_MODE_ACMD_Msk   = 0x100  // Bit mask of ACMD field.
	SDHC_EISTR_EMMC_MODE_ACMD       = 0x100  // Bit ACMD.
	SDHC_EISTR_EMMC_MODE_ACMD_NO    = 0x0    // No Error
	SDHC_EISTR_EMMC_MODE_ACMD_YES   = 0x1    // Error
	SDHC_EISTR_EMMC_MODE_ADMA_Pos   = 0x9    // Position of ADMA field.
	SDHC_EISTR_EMMC_MODE_ADMA_Msk   = 0x200  // Bit mask of ADMA field.
	SDHC_EISTR_EMMC_MODE_ADMA       = 0x200  // Bit ADMA.
	SDHC_EISTR_EMMC_MODE_ADMA_NO    = 0x0    // No Error
	SDHC_EISTR_EMMC_MODE_ADMA_YES   = 0x1    // Error
	SDHC_EISTR_EMMC_MODE_BOOTAE_Pos = 0xc    // Position of BOOTAE field.
	SDHC_EISTR_EMMC_MODE_BOOTAE_Msk = 0x1000 // Bit mask of BOOTAE field.
	SDHC_EISTR_EMMC_MODE_BOOTAE     = 0x1000 // Bit BOOTAE.
	SDHC_EISTR_EMMC_MODE_BOOTAE_0   = 0x0    // FIFO contains at least one byte
	SDHC_EISTR_EMMC_MODE_BOOTAE_1   = 0x1    // FIFO is empty

	// NISTER: Normal Interrupt Status Enable
	SDHC_NISTER_CMDC_Pos       = 0x0   // Position of CMDC field.
	SDHC_NISTER_CMDC_Msk       = 0x1   // Bit mask of CMDC field.
	SDHC_NISTER_CMDC           = 0x1   // Bit CMDC.
	SDHC_NISTER_CMDC_MASKED    = 0x0   // Masked
	SDHC_NISTER_CMDC_ENABLED   = 0x1   // Enabled
	SDHC_NISTER_TRFC_Pos       = 0x1   // Position of TRFC field.
	SDHC_NISTER_TRFC_Msk       = 0x2   // Bit mask of TRFC field.
	SDHC_NISTER_TRFC           = 0x2   // Bit TRFC.
	SDHC_NISTER_TRFC_MASKED    = 0x0   // Masked
	SDHC_NISTER_TRFC_ENABLED   = 0x1   // Enabled
	SDHC_NISTER_BLKGE_Pos      = 0x2   // Position of BLKGE field.
	SDHC_NISTER_BLKGE_Msk      = 0x4   // Bit mask of BLKGE field.
	SDHC_NISTER_BLKGE          = 0x4   // Bit BLKGE.
	SDHC_NISTER_BLKGE_MASKED   = 0x0   // Masked
	SDHC_NISTER_BLKGE_ENABLED  = 0x1   // Enabled
	SDHC_NISTER_DMAINT_Pos     = 0x3   // Position of DMAINT field.
	SDHC_NISTER_DMAINT_Msk     = 0x8   // Bit mask of DMAINT field.
	SDHC_NISTER_DMAINT         = 0x8   // Bit DMAINT.
	SDHC_NISTER_DMAINT_MASKED  = 0x0   // Masked
	SDHC_NISTER_DMAINT_ENABLED = 0x1   // Enabled
	SDHC_NISTER_BWRRDY_Pos     = 0x4   // Position of BWRRDY field.
	SDHC_NISTER_BWRRDY_Msk     = 0x10  // Bit mask of BWRRDY field.
	SDHC_NISTER_BWRRDY         = 0x10  // Bit BWRRDY.
	SDHC_NISTER_BWRRDY_MASKED  = 0x0   // Masked
	SDHC_NISTER_BWRRDY_ENABLED = 0x1   // Enabled
	SDHC_NISTER_BRDRDY_Pos     = 0x5   // Position of BRDRDY field.
	SDHC_NISTER_BRDRDY_Msk     = 0x20  // Bit mask of BRDRDY field.
	SDHC_NISTER_BRDRDY         = 0x20  // Bit BRDRDY.
	SDHC_NISTER_BRDRDY_MASKED  = 0x0   // Masked
	SDHC_NISTER_BRDRDY_ENABLED = 0x1   // Enabled
	SDHC_NISTER_CINS_Pos       = 0x6   // Position of CINS field.
	SDHC_NISTER_CINS_Msk       = 0x40  // Bit mask of CINS field.
	SDHC_NISTER_CINS           = 0x40  // Bit CINS.
	SDHC_NISTER_CINS_MASKED    = 0x0   // Masked
	SDHC_NISTER_CINS_ENABLED   = 0x1   // Enabled
	SDHC_NISTER_CREM_Pos       = 0x7   // Position of CREM field.
	SDHC_NISTER_CREM_Msk       = 0x80  // Bit mask of CREM field.
	SDHC_NISTER_CREM           = 0x80  // Bit CREM.
	SDHC_NISTER_CREM_MASKED    = 0x0   // Masked
	SDHC_NISTER_CREM_ENABLED   = 0x1   // Enabled
	SDHC_NISTER_CINT_Pos       = 0x8   // Position of CINT field.
	SDHC_NISTER_CINT_Msk       = 0x100 // Bit mask of CINT field.
	SDHC_NISTER_CINT           = 0x100 // Bit CINT.
	SDHC_NISTER_CINT_MASKED    = 0x0   // Masked
	SDHC_NISTER_CINT_ENABLED   = 0x1   // Enabled

	// NISTER_EMMC_MODE: Normal Interrupt Status Enable
	SDHC_NISTER_EMMC_MODE_CMDC_Pos       = 0x0    // Position of CMDC field.
	SDHC_NISTER_EMMC_MODE_CMDC_Msk       = 0x1    // Bit mask of CMDC field.
	SDHC_NISTER_EMMC_MODE_CMDC           = 0x1    // Bit CMDC.
	SDHC_NISTER_EMMC_MODE_CMDC_MASKED    = 0x0    // Masked
	SDHC_NISTER_EMMC_MODE_CMDC_ENABLED   = 0x1    // Enabled
	SDHC_NISTER_EMMC_MODE_TRFC_Pos       = 0x1    // Position of TRFC field.
	SDHC_NISTER_EMMC_MODE_TRFC_Msk       = 0x2    // Bit mask of TRFC field.
	SDHC_NISTER_EMMC_MODE_TRFC           = 0x2    // Bit TRFC.
	SDHC_NISTER_EMMC_MODE_TRFC_MASKED    = 0x0    // Masked
	SDHC_NISTER_EMMC_MODE_TRFC_ENABLED   = 0x1    // Enabled
	SDHC_NISTER_EMMC_MODE_BLKGE_Pos      = 0x2    // Position of BLKGE field.
	SDHC_NISTER_EMMC_MODE_BLKGE_Msk      = 0x4    // Bit mask of BLKGE field.
	SDHC_NISTER_EMMC_MODE_BLKGE          = 0x4    // Bit BLKGE.
	SDHC_NISTER_EMMC_MODE_BLKGE_MASKED   = 0x0    // Masked
	SDHC_NISTER_EMMC_MODE_BLKGE_ENABLED  = 0x1    // Enabled
	SDHC_NISTER_EMMC_MODE_DMAINT_Pos     = 0x3    // Position of DMAINT field.
	SDHC_NISTER_EMMC_MODE_DMAINT_Msk     = 0x8    // Bit mask of DMAINT field.
	SDHC_NISTER_EMMC_MODE_DMAINT         = 0x8    // Bit DMAINT.
	SDHC_NISTER_EMMC_MODE_DMAINT_MASKED  = 0x0    // Masked
	SDHC_NISTER_EMMC_MODE_DMAINT_ENABLED = 0x1    // Enabled
	SDHC_NISTER_EMMC_MODE_BWRRDY_Pos     = 0x4    // Position of BWRRDY field.
	SDHC_NISTER_EMMC_MODE_BWRRDY_Msk     = 0x10   // Bit mask of BWRRDY field.
	SDHC_NISTER_EMMC_MODE_BWRRDY         = 0x10   // Bit BWRRDY.
	SDHC_NISTER_EMMC_MODE_BWRRDY_MASKED  = 0x0    // Masked
	SDHC_NISTER_EMMC_MODE_BWRRDY_ENABLED = 0x1    // Enabled
	SDHC_NISTER_EMMC_MODE_BRDRDY_Pos     = 0x5    // Position of BRDRDY field.
	SDHC_NISTER_EMMC_MODE_BRDRDY_Msk     = 0x20   // Bit mask of BRDRDY field.
	SDHC_NISTER_EMMC_MODE_BRDRDY         = 0x20   // Bit BRDRDY.
	SDHC_NISTER_EMMC_MODE_BRDRDY_MASKED  = 0x0    // Masked
	SDHC_NISTER_EMMC_MODE_BRDRDY_ENABLED = 0x1    // Enabled
	SDHC_NISTER_EMMC_MODE_BOOTAR_Pos     = 0xe    // Position of BOOTAR field.
	SDHC_NISTER_EMMC_MODE_BOOTAR_Msk     = 0x4000 // Bit mask of BOOTAR field.
	SDHC_NISTER_EMMC_MODE_BOOTAR         = 0x4000 // Bit BOOTAR.

	// EISTER: Error Interrupt Status Enable
	SDHC_EISTER_CMDTEO_Pos     = 0x0   // Position of CMDTEO field.
	SDHC_EISTER_CMDTEO_Msk     = 0x1   // Bit mask of CMDTEO field.
	SDHC_EISTER_CMDTEO         = 0x1   // Bit CMDTEO.
	SDHC_EISTER_CMDTEO_MASKED  = 0x0   // Masked
	SDHC_EISTER_CMDTEO_ENABLED = 0x1   // Enabled
	SDHC_EISTER_CMDCRC_Pos     = 0x1   // Position of CMDCRC field.
	SDHC_EISTER_CMDCRC_Msk     = 0x2   // Bit mask of CMDCRC field.
	SDHC_EISTER_CMDCRC         = 0x2   // Bit CMDCRC.
	SDHC_EISTER_CMDCRC_MASKED  = 0x0   // Masked
	SDHC_EISTER_CMDCRC_ENABLED = 0x1   // Enabled
	SDHC_EISTER_CMDEND_Pos     = 0x2   // Position of CMDEND field.
	SDHC_EISTER_CMDEND_Msk     = 0x4   // Bit mask of CMDEND field.
	SDHC_EISTER_CMDEND         = 0x4   // Bit CMDEND.
	SDHC_EISTER_CMDEND_MASKED  = 0x0   // Masked
	SDHC_EISTER_CMDEND_ENABLED = 0x1   // Enabled
	SDHC_EISTER_CMDIDX_Pos     = 0x3   // Position of CMDIDX field.
	SDHC_EISTER_CMDIDX_Msk     = 0x8   // Bit mask of CMDIDX field.
	SDHC_EISTER_CMDIDX         = 0x8   // Bit CMDIDX.
	SDHC_EISTER_CMDIDX_MASKED  = 0x0   // Masked
	SDHC_EISTER_CMDIDX_ENABLED = 0x1   // Enabled
	SDHC_EISTER_DATTEO_Pos     = 0x4   // Position of DATTEO field.
	SDHC_EISTER_DATTEO_Msk     = 0x10  // Bit mask of DATTEO field.
	SDHC_EISTER_DATTEO         = 0x10  // Bit DATTEO.
	SDHC_EISTER_DATTEO_MASKED  = 0x0   // Masked
	SDHC_EISTER_DATTEO_ENABLED = 0x1   // Enabled
	SDHC_EISTER_DATCRC_Pos     = 0x5   // Position of DATCRC field.
	SDHC_EISTER_DATCRC_Msk     = 0x20  // Bit mask of DATCRC field.
	SDHC_EISTER_DATCRC         = 0x20  // Bit DATCRC.
	SDHC_EISTER_DATCRC_MASKED  = 0x0   // Masked
	SDHC_EISTER_DATCRC_ENABLED = 0x1   // Enabled
	SDHC_EISTER_DATEND_Pos     = 0x6   // Position of DATEND field.
	SDHC_EISTER_DATEND_Msk     = 0x40  // Bit mask of DATEND field.
	SDHC_EISTER_DATEND         = 0x40  // Bit DATEND.
	SDHC_EISTER_DATEND_MASKED  = 0x0   // Masked
	SDHC_EISTER_DATEND_ENABLED = 0x1   // Enabled
	SDHC_EISTER_CURLIM_Pos     = 0x7   // Position of CURLIM field.
	SDHC_EISTER_CURLIM_Msk     = 0x80  // Bit mask of CURLIM field.
	SDHC_EISTER_CURLIM         = 0x80  // Bit CURLIM.
	SDHC_EISTER_CURLIM_MASKED  = 0x0   // Masked
	SDHC_EISTER_CURLIM_ENABLED = 0x1   // Enabled
	SDHC_EISTER_ACMD_Pos       = 0x8   // Position of ACMD field.
	SDHC_EISTER_ACMD_Msk       = 0x100 // Bit mask of ACMD field.
	SDHC_EISTER_ACMD           = 0x100 // Bit ACMD.
	SDHC_EISTER_ACMD_MASKED    = 0x0   // Masked
	SDHC_EISTER_ACMD_ENABLED   = 0x1   // Enabled
	SDHC_EISTER_ADMA_Pos       = 0x9   // Position of ADMA field.
	SDHC_EISTER_ADMA_Msk       = 0x200 // Bit mask of ADMA field.
	SDHC_EISTER_ADMA           = 0x200 // Bit ADMA.
	SDHC_EISTER_ADMA_MASKED    = 0x0   // Masked
	SDHC_EISTER_ADMA_ENABLED   = 0x1   // Enabled

	// EISTER_EMMC_MODE: Error Interrupt Status Enable
	SDHC_EISTER_EMMC_MODE_CMDTEO_Pos     = 0x0    // Position of CMDTEO field.
	SDHC_EISTER_EMMC_MODE_CMDTEO_Msk     = 0x1    // Bit mask of CMDTEO field.
	SDHC_EISTER_EMMC_MODE_CMDTEO         = 0x1    // Bit CMDTEO.
	SDHC_EISTER_EMMC_MODE_CMDTEO_MASKED  = 0x0    // Masked
	SDHC_EISTER_EMMC_MODE_CMDTEO_ENABLED = 0x1    // Enabled
	SDHC_EISTER_EMMC_MODE_CMDCRC_Pos     = 0x1    // Position of CMDCRC field.
	SDHC_EISTER_EMMC_MODE_CMDCRC_Msk     = 0x2    // Bit mask of CMDCRC field.
	SDHC_EISTER_EMMC_MODE_CMDCRC         = 0x2    // Bit CMDCRC.
	SDHC_EISTER_EMMC_MODE_CMDCRC_MASKED  = 0x0    // Masked
	SDHC_EISTER_EMMC_MODE_CMDCRC_ENABLED = 0x1    // Enabled
	SDHC_EISTER_EMMC_MODE_CMDEND_Pos     = 0x2    // Position of CMDEND field.
	SDHC_EISTER_EMMC_MODE_CMDEND_Msk     = 0x4    // Bit mask of CMDEND field.
	SDHC_EISTER_EMMC_MODE_CMDEND         = 0x4    // Bit CMDEND.
	SDHC_EISTER_EMMC_MODE_CMDEND_MASKED  = 0x0    // Masked
	SDHC_EISTER_EMMC_MODE_CMDEND_ENABLED = 0x1    // Enabled
	SDHC_EISTER_EMMC_MODE_CMDIDX_Pos     = 0x3    // Position of CMDIDX field.
	SDHC_EISTER_EMMC_MODE_CMDIDX_Msk     = 0x8    // Bit mask of CMDIDX field.
	SDHC_EISTER_EMMC_MODE_CMDIDX         = 0x8    // Bit CMDIDX.
	SDHC_EISTER_EMMC_MODE_CMDIDX_MASKED  = 0x0    // Masked
	SDHC_EISTER_EMMC_MODE_CMDIDX_ENABLED = 0x1    // Enabled
	SDHC_EISTER_EMMC_MODE_DATTEO_Pos     = 0x4    // Position of DATTEO field.
	SDHC_EISTER_EMMC_MODE_DATTEO_Msk     = 0x10   // Bit mask of DATTEO field.
	SDHC_EISTER_EMMC_MODE_DATTEO         = 0x10   // Bit DATTEO.
	SDHC_EISTER_EMMC_MODE_DATTEO_MASKED  = 0x0    // Masked
	SDHC_EISTER_EMMC_MODE_DATTEO_ENABLED = 0x1    // Enabled
	SDHC_EISTER_EMMC_MODE_DATCRC_Pos     = 0x5    // Position of DATCRC field.
	SDHC_EISTER_EMMC_MODE_DATCRC_Msk     = 0x20   // Bit mask of DATCRC field.
	SDHC_EISTER_EMMC_MODE_DATCRC         = 0x20   // Bit DATCRC.
	SDHC_EISTER_EMMC_MODE_DATCRC_MASKED  = 0x0    // Masked
	SDHC_EISTER_EMMC_MODE_DATCRC_ENABLED = 0x1    // Enabled
	SDHC_EISTER_EMMC_MODE_DATEND_Pos     = 0x6    // Position of DATEND field.
	SDHC_EISTER_EMMC_MODE_DATEND_Msk     = 0x40   // Bit mask of DATEND field.
	SDHC_EISTER_EMMC_MODE_DATEND         = 0x40   // Bit DATEND.
	SDHC_EISTER_EMMC_MODE_DATEND_MASKED  = 0x0    // Masked
	SDHC_EISTER_EMMC_MODE_DATEND_ENABLED = 0x1    // Enabled
	SDHC_EISTER_EMMC_MODE_CURLIM_Pos     = 0x7    // Position of CURLIM field.
	SDHC_EISTER_EMMC_MODE_CURLIM_Msk     = 0x80   // Bit mask of CURLIM field.
	SDHC_EISTER_EMMC_MODE_CURLIM         = 0x80   // Bit CURLIM.
	SDHC_EISTER_EMMC_MODE_CURLIM_MASKED  = 0x0    // Masked
	SDHC_EISTER_EMMC_MODE_CURLIM_ENABLED = 0x1    // Enabled
	SDHC_EISTER_EMMC_MODE_ACMD_Pos       = 0x8    // Position of ACMD field.
	SDHC_EISTER_EMMC_MODE_ACMD_Msk       = 0x100  // Bit mask of ACMD field.
	SDHC_EISTER_EMMC_MODE_ACMD           = 0x100  // Bit ACMD.
	SDHC_EISTER_EMMC_MODE_ACMD_MASKED    = 0x0    // Masked
	SDHC_EISTER_EMMC_MODE_ACMD_ENABLED   = 0x1    // Enabled
	SDHC_EISTER_EMMC_MODE_ADMA_Pos       = 0x9    // Position of ADMA field.
	SDHC_EISTER_EMMC_MODE_ADMA_Msk       = 0x200  // Bit mask of ADMA field.
	SDHC_EISTER_EMMC_MODE_ADMA           = 0x200  // Bit ADMA.
	SDHC_EISTER_EMMC_MODE_ADMA_MASKED    = 0x0    // Masked
	SDHC_EISTER_EMMC_MODE_ADMA_ENABLED   = 0x1    // Enabled
	SDHC_EISTER_EMMC_MODE_BOOTAE_Pos     = 0xc    // Position of BOOTAE field.
	SDHC_EISTER_EMMC_MODE_BOOTAE_Msk     = 0x1000 // Bit mask of BOOTAE field.
	SDHC_EISTER_EMMC_MODE_BOOTAE         = 0x1000 // Bit BOOTAE.

	// NISIER: Normal Interrupt Signal Enable
	SDHC_NISIER_CMDC_Pos       = 0x0   // Position of CMDC field.
	SDHC_NISIER_CMDC_Msk       = 0x1   // Bit mask of CMDC field.
	SDHC_NISIER_CMDC           = 0x1   // Bit CMDC.
	SDHC_NISIER_CMDC_MASKED    = 0x0   // Masked
	SDHC_NISIER_CMDC_ENABLED   = 0x1   // Enabled
	SDHC_NISIER_TRFC_Pos       = 0x1   // Position of TRFC field.
	SDHC_NISIER_TRFC_Msk       = 0x2   // Bit mask of TRFC field.
	SDHC_NISIER_TRFC           = 0x2   // Bit TRFC.
	SDHC_NISIER_TRFC_MASKED    = 0x0   // Masked
	SDHC_NISIER_TRFC_ENABLED   = 0x1   // Enabled
	SDHC_NISIER_BLKGE_Pos      = 0x2   // Position of BLKGE field.
	SDHC_NISIER_BLKGE_Msk      = 0x4   // Bit mask of BLKGE field.
	SDHC_NISIER_BLKGE          = 0x4   // Bit BLKGE.
	SDHC_NISIER_BLKGE_MASKED   = 0x0   // Masked
	SDHC_NISIER_BLKGE_ENABLED  = 0x1   // Enabled
	SDHC_NISIER_DMAINT_Pos     = 0x3   // Position of DMAINT field.
	SDHC_NISIER_DMAINT_Msk     = 0x8   // Bit mask of DMAINT field.
	SDHC_NISIER_DMAINT         = 0x8   // Bit DMAINT.
	SDHC_NISIER_DMAINT_MASKED  = 0x0   // Masked
	SDHC_NISIER_DMAINT_ENABLED = 0x1   // Enabled
	SDHC_NISIER_BWRRDY_Pos     = 0x4   // Position of BWRRDY field.
	SDHC_NISIER_BWRRDY_Msk     = 0x10  // Bit mask of BWRRDY field.
	SDHC_NISIER_BWRRDY         = 0x10  // Bit BWRRDY.
	SDHC_NISIER_BWRRDY_MASKED  = 0x0   // Masked
	SDHC_NISIER_BWRRDY_ENABLED = 0x1   // Enabled
	SDHC_NISIER_BRDRDY_Pos     = 0x5   // Position of BRDRDY field.
	SDHC_NISIER_BRDRDY_Msk     = 0x20  // Bit mask of BRDRDY field.
	SDHC_NISIER_BRDRDY         = 0x20  // Bit BRDRDY.
	SDHC_NISIER_BRDRDY_MASKED  = 0x0   // Masked
	SDHC_NISIER_BRDRDY_ENABLED = 0x1   // Enabled
	SDHC_NISIER_CINS_Pos       = 0x6   // Position of CINS field.
	SDHC_NISIER_CINS_Msk       = 0x40  // Bit mask of CINS field.
	SDHC_NISIER_CINS           = 0x40  // Bit CINS.
	SDHC_NISIER_CINS_MASKED    = 0x0   // Masked
	SDHC_NISIER_CINS_ENABLED   = 0x1   // Enabled
	SDHC_NISIER_CREM_Pos       = 0x7   // Position of CREM field.
	SDHC_NISIER_CREM_Msk       = 0x80  // Bit mask of CREM field.
	SDHC_NISIER_CREM           = 0x80  // Bit CREM.
	SDHC_NISIER_CREM_MASKED    = 0x0   // Masked
	SDHC_NISIER_CREM_ENABLED   = 0x1   // Enabled
	SDHC_NISIER_CINT_Pos       = 0x8   // Position of CINT field.
	SDHC_NISIER_CINT_Msk       = 0x100 // Bit mask of CINT field.
	SDHC_NISIER_CINT           = 0x100 // Bit CINT.
	SDHC_NISIER_CINT_MASKED    = 0x0   // Masked
	SDHC_NISIER_CINT_ENABLED   = 0x1   // Enabled

	// NISIER_EMMC_MODE: Normal Interrupt Signal Enable
	SDHC_NISIER_EMMC_MODE_CMDC_Pos       = 0x0    // Position of CMDC field.
	SDHC_NISIER_EMMC_MODE_CMDC_Msk       = 0x1    // Bit mask of CMDC field.
	SDHC_NISIER_EMMC_MODE_CMDC           = 0x1    // Bit CMDC.
	SDHC_NISIER_EMMC_MODE_CMDC_MASKED    = 0x0    // Masked
	SDHC_NISIER_EMMC_MODE_CMDC_ENABLED   = 0x1    // Enabled
	SDHC_NISIER_EMMC_MODE_TRFC_Pos       = 0x1    // Position of TRFC field.
	SDHC_NISIER_EMMC_MODE_TRFC_Msk       = 0x2    // Bit mask of TRFC field.
	SDHC_NISIER_EMMC_MODE_TRFC           = 0x2    // Bit TRFC.
	SDHC_NISIER_EMMC_MODE_TRFC_MASKED    = 0x0    // Masked
	SDHC_NISIER_EMMC_MODE_TRFC_ENABLED   = 0x1    // Enabled
	SDHC_NISIER_EMMC_MODE_BLKGE_Pos      = 0x2    // Position of BLKGE field.
	SDHC_NISIER_EMMC_MODE_BLKGE_Msk      = 0x4    // Bit mask of BLKGE field.
	SDHC_NISIER_EMMC_MODE_BLKGE          = 0x4    // Bit BLKGE.
	SDHC_NISIER_EMMC_MODE_BLKGE_MASKED   = 0x0    // Masked
	SDHC_NISIER_EMMC_MODE_BLKGE_ENABLED  = 0x1    // Enabled
	SDHC_NISIER_EMMC_MODE_DMAINT_Pos     = 0x3    // Position of DMAINT field.
	SDHC_NISIER_EMMC_MODE_DMAINT_Msk     = 0x8    // Bit mask of DMAINT field.
	SDHC_NISIER_EMMC_MODE_DMAINT         = 0x8    // Bit DMAINT.
	SDHC_NISIER_EMMC_MODE_DMAINT_MASKED  = 0x0    // Masked
	SDHC_NISIER_EMMC_MODE_DMAINT_ENABLED = 0x1    // Enabled
	SDHC_NISIER_EMMC_MODE_BWRRDY_Pos     = 0x4    // Position of BWRRDY field.
	SDHC_NISIER_EMMC_MODE_BWRRDY_Msk     = 0x10   // Bit mask of BWRRDY field.
	SDHC_NISIER_EMMC_MODE_BWRRDY         = 0x10   // Bit BWRRDY.
	SDHC_NISIER_EMMC_MODE_BWRRDY_MASKED  = 0x0    // Masked
	SDHC_NISIER_EMMC_MODE_BWRRDY_ENABLED = 0x1    // Enabled
	SDHC_NISIER_EMMC_MODE_BRDRDY_Pos     = 0x5    // Position of BRDRDY field.
	SDHC_NISIER_EMMC_MODE_BRDRDY_Msk     = 0x20   // Bit mask of BRDRDY field.
	SDHC_NISIER_EMMC_MODE_BRDRDY         = 0x20   // Bit BRDRDY.
	SDHC_NISIER_EMMC_MODE_BRDRDY_MASKED  = 0x0    // Masked
	SDHC_NISIER_EMMC_MODE_BRDRDY_ENABLED = 0x1    // Enabled
	SDHC_NISIER_EMMC_MODE_BOOTAR_Pos     = 0xe    // Position of BOOTAR field.
	SDHC_NISIER_EMMC_MODE_BOOTAR_Msk     = 0x4000 // Bit mask of BOOTAR field.
	SDHC_NISIER_EMMC_MODE_BOOTAR         = 0x4000 // Bit BOOTAR.

	// EISIER: Error Interrupt Signal Enable
	SDHC_EISIER_CMDTEO_Pos     = 0x0   // Position of CMDTEO field.
	SDHC_EISIER_CMDTEO_Msk     = 0x1   // Bit mask of CMDTEO field.
	SDHC_EISIER_CMDTEO         = 0x1   // Bit CMDTEO.
	SDHC_EISIER_CMDTEO_MASKED  = 0x0   // Masked
	SDHC_EISIER_CMDTEO_ENABLED = 0x1   // Enabled
	SDHC_EISIER_CMDCRC_Pos     = 0x1   // Position of CMDCRC field.
	SDHC_EISIER_CMDCRC_Msk     = 0x2   // Bit mask of CMDCRC field.
	SDHC_EISIER_CMDCRC         = 0x2   // Bit CMDCRC.
	SDHC_EISIER_CMDCRC_MASKED  = 0x0   // Masked
	SDHC_EISIER_CMDCRC_ENABLED = 0x1   // Enabled
	SDHC_EISIER_CMDEND_Pos     = 0x2   // Position of CMDEND field.
	SDHC_EISIER_CMDEND_Msk     = 0x4   // Bit mask of CMDEND field.
	SDHC_EISIER_CMDEND         = 0x4   // Bit CMDEND.
	SDHC_EISIER_CMDEND_MASKED  = 0x0   // Masked
	SDHC_EISIER_CMDEND_ENABLED = 0x1   // Enabled
	SDHC_EISIER_CMDIDX_Pos     = 0x3   // Position of CMDIDX field.
	SDHC_EISIER_CMDIDX_Msk     = 0x8   // Bit mask of CMDIDX field.
	SDHC_EISIER_CMDIDX         = 0x8   // Bit CMDIDX.
	SDHC_EISIER_CMDIDX_MASKED  = 0x0   // Masked
	SDHC_EISIER_CMDIDX_ENABLED = 0x1   // Enabled
	SDHC_EISIER_DATTEO_Pos     = 0x4   // Position of DATTEO field.
	SDHC_EISIER_DATTEO_Msk     = 0x10  // Bit mask of DATTEO field.
	SDHC_EISIER_DATTEO         = 0x10  // Bit DATTEO.
	SDHC_EISIER_DATTEO_MASKED  = 0x0   // Masked
	SDHC_EISIER_DATTEO_ENABLED = 0x1   // Enabled
	SDHC_EISIER_DATCRC_Pos     = 0x5   // Position of DATCRC field.
	SDHC_EISIER_DATCRC_Msk     = 0x20  // Bit mask of DATCRC field.
	SDHC_EISIER_DATCRC         = 0x20  // Bit DATCRC.
	SDHC_EISIER_DATCRC_MASKED  = 0x0   // Masked
	SDHC_EISIER_DATCRC_ENABLED = 0x1   // Enabled
	SDHC_EISIER_DATEND_Pos     = 0x6   // Position of DATEND field.
	SDHC_EISIER_DATEND_Msk     = 0x40  // Bit mask of DATEND field.
	SDHC_EISIER_DATEND         = 0x40  // Bit DATEND.
	SDHC_EISIER_DATEND_MASKED  = 0x0   // Masked
	SDHC_EISIER_DATEND_ENABLED = 0x1   // Enabled
	SDHC_EISIER_CURLIM_Pos     = 0x7   // Position of CURLIM field.
	SDHC_EISIER_CURLIM_Msk     = 0x80  // Bit mask of CURLIM field.
	SDHC_EISIER_CURLIM         = 0x80  // Bit CURLIM.
	SDHC_EISIER_CURLIM_MASKED  = 0x0   // Masked
	SDHC_EISIER_CURLIM_ENABLED = 0x1   // Enabled
	SDHC_EISIER_ACMD_Pos       = 0x8   // Position of ACMD field.
	SDHC_EISIER_ACMD_Msk       = 0x100 // Bit mask of ACMD field.
	SDHC_EISIER_ACMD           = 0x100 // Bit ACMD.
	SDHC_EISIER_ACMD_MASKED    = 0x0   // Masked
	SDHC_EISIER_ACMD_ENABLED   = 0x1   // Enabled
	SDHC_EISIER_ADMA_Pos       = 0x9   // Position of ADMA field.
	SDHC_EISIER_ADMA_Msk       = 0x200 // Bit mask of ADMA field.
	SDHC_EISIER_ADMA           = 0x200 // Bit ADMA.
	SDHC_EISIER_ADMA_MASKED    = 0x0   // Masked
	SDHC_EISIER_ADMA_ENABLED   = 0x1   // Enabled

	// EISIER_EMMC_MODE: Error Interrupt Signal Enable
	SDHC_EISIER_EMMC_MODE_CMDTEO_Pos     = 0x0    // Position of CMDTEO field.
	SDHC_EISIER_EMMC_MODE_CMDTEO_Msk     = 0x1    // Bit mask of CMDTEO field.
	SDHC_EISIER_EMMC_MODE_CMDTEO         = 0x1    // Bit CMDTEO.
	SDHC_EISIER_EMMC_MODE_CMDTEO_MASKED  = 0x0    // Masked
	SDHC_EISIER_EMMC_MODE_CMDTEO_ENABLED = 0x1    // Enabled
	SDHC_EISIER_EMMC_MODE_CMDCRC_Pos     = 0x1    // Position of CMDCRC field.
	SDHC_EISIER_EMMC_MODE_CMDCRC_Msk     = 0x2    // Bit mask of CMDCRC field.
	SDHC_EISIER_EMMC_MODE_CMDCRC         = 0x2    // Bit CMDCRC.
	SDHC_EISIER_EMMC_MODE_CMDCRC_MASKED  = 0x0    // Masked
	SDHC_EISIER_EMMC_MODE_CMDCRC_ENABLED = 0x1    // Enabled
	SDHC_EISIER_EMMC_MODE_CMDEND_Pos     = 0x2    // Position of CMDEND field.
	SDHC_EISIER_EMMC_MODE_CMDEND_Msk     = 0x4    // Bit mask of CMDEND field.
	SDHC_EISIER_EMMC_MODE_CMDEND         = 0x4    // Bit CMDEND.
	SDHC_EISIER_EMMC_MODE_CMDEND_MASKED  = 0x0    // Masked
	SDHC_EISIER_EMMC_MODE_CMDEND_ENABLED = 0x1    // Enabled
	SDHC_EISIER_EMMC_MODE_CMDIDX_Pos     = 0x3    // Position of CMDIDX field.
	SDHC_EISIER_EMMC_MODE_CMDIDX_Msk     = 0x8    // Bit mask of CMDIDX field.
	SDHC_EISIER_EMMC_MODE_CMDIDX         = 0x8    // Bit CMDIDX.
	SDHC_EISIER_EMMC_MODE_CMDIDX_MASKED  = 0x0    // Masked
	SDHC_EISIER_EMMC_MODE_CMDIDX_ENABLED = 0x1    // Enabled
	SDHC_EISIER_EMMC_MODE_DATTEO_Pos     = 0x4    // Position of DATTEO field.
	SDHC_EISIER_EMMC_MODE_DATTEO_Msk     = 0x10   // Bit mask of DATTEO field.
	SDHC_EISIER_EMMC_MODE_DATTEO         = 0x10   // Bit DATTEO.
	SDHC_EISIER_EMMC_MODE_DATTEO_MASKED  = 0x0    // Masked
	SDHC_EISIER_EMMC_MODE_DATTEO_ENABLED = 0x1    // Enabled
	SDHC_EISIER_EMMC_MODE_DATCRC_Pos     = 0x5    // Position of DATCRC field.
	SDHC_EISIER_EMMC_MODE_DATCRC_Msk     = 0x20   // Bit mask of DATCRC field.
	SDHC_EISIER_EMMC_MODE_DATCRC         = 0x20   // Bit DATCRC.
	SDHC_EISIER_EMMC_MODE_DATCRC_MASKED  = 0x0    // Masked
	SDHC_EISIER_EMMC_MODE_DATCRC_ENABLED = 0x1    // Enabled
	SDHC_EISIER_EMMC_MODE_DATEND_Pos     = 0x6    // Position of DATEND field.
	SDHC_EISIER_EMMC_MODE_DATEND_Msk     = 0x40   // Bit mask of DATEND field.
	SDHC_EISIER_EMMC_MODE_DATEND         = 0x40   // Bit DATEND.
	SDHC_EISIER_EMMC_MODE_DATEND_MASKED  = 0x0    // Masked
	SDHC_EISIER_EMMC_MODE_DATEND_ENABLED = 0x1    // Enabled
	SDHC_EISIER_EMMC_MODE_CURLIM_Pos     = 0x7    // Position of CURLIM field.
	SDHC_EISIER_EMMC_MODE_CURLIM_Msk     = 0x80   // Bit mask of CURLIM field.
	SDHC_EISIER_EMMC_MODE_CURLIM         = 0x80   // Bit CURLIM.
	SDHC_EISIER_EMMC_MODE_CURLIM_MASKED  = 0x0    // Masked
	SDHC_EISIER_EMMC_MODE_CURLIM_ENABLED = 0x1    // Enabled
	SDHC_EISIER_EMMC_MODE_ACMD_Pos       = 0x8    // Position of ACMD field.
	SDHC_EISIER_EMMC_MODE_ACMD_Msk       = 0x100  // Bit mask of ACMD field.
	SDHC_EISIER_EMMC_MODE_ACMD           = 0x100  // Bit ACMD.
	SDHC_EISIER_EMMC_MODE_ACMD_MASKED    = 0x0    // Masked
	SDHC_EISIER_EMMC_MODE_ACMD_ENABLED   = 0x1    // Enabled
	SDHC_EISIER_EMMC_MODE_ADMA_Pos       = 0x9    // Position of ADMA field.
	SDHC_EISIER_EMMC_MODE_ADMA_Msk       = 0x200  // Bit mask of ADMA field.
	SDHC_EISIER_EMMC_MODE_ADMA           = 0x200  // Bit ADMA.
	SDHC_EISIER_EMMC_MODE_ADMA_MASKED    = 0x0    // Masked
	SDHC_EISIER_EMMC_MODE_ADMA_ENABLED   = 0x1    // Enabled
	SDHC_EISIER_EMMC_MODE_BOOTAE_Pos     = 0xc    // Position of BOOTAE field.
	SDHC_EISIER_EMMC_MODE_BOOTAE_Msk     = 0x1000 // Bit mask of BOOTAE field.
	SDHC_EISIER_EMMC_MODE_BOOTAE         = 0x1000 // Bit BOOTAE.

	// ACESR: Auto CMD Error Status
	SDHC_ACESR_ACMD12NE_Pos      = 0x0  // Position of ACMD12NE field.
	SDHC_ACESR_ACMD12NE_Msk      = 0x1  // Bit mask of ACMD12NE field.
	SDHC_ACESR_ACMD12NE          = 0x1  // Bit ACMD12NE.
	SDHC_ACESR_ACMD12NE_EXEC     = 0x0  // Executed
	SDHC_ACESR_ACMD12NE_NOT_EXEC = 0x1  // Not executed
	SDHC_ACESR_ACMDTEO_Pos       = 0x1  // Position of ACMDTEO field.
	SDHC_ACESR_ACMDTEO_Msk       = 0x2  // Bit mask of ACMDTEO field.
	SDHC_ACESR_ACMDTEO           = 0x2  // Bit ACMDTEO.
	SDHC_ACESR_ACMDTEO_NO        = 0x0  // No error
	SDHC_ACESR_ACMDTEO_YES       = 0x1  // Timeout
	SDHC_ACESR_ACMDCRC_Pos       = 0x2  // Position of ACMDCRC field.
	SDHC_ACESR_ACMDCRC_Msk       = 0x4  // Bit mask of ACMDCRC field.
	SDHC_ACESR_ACMDCRC           = 0x4  // Bit ACMDCRC.
	SDHC_ACESR_ACMDCRC_NO        = 0x0  // No error
	SDHC_ACESR_ACMDCRC_YES       = 0x1  // CRC Error Generated
	SDHC_ACESR_ACMDEND_Pos       = 0x3  // Position of ACMDEND field.
	SDHC_ACESR_ACMDEND_Msk       = 0x8  // Bit mask of ACMDEND field.
	SDHC_ACESR_ACMDEND           = 0x8  // Bit ACMDEND.
	SDHC_ACESR_ACMDEND_NO        = 0x0  // No error
	SDHC_ACESR_ACMDEND_YES       = 0x1  // End Bit Error Generated
	SDHC_ACESR_ACMDIDX_Pos       = 0x4  // Position of ACMDIDX field.
	SDHC_ACESR_ACMDIDX_Msk       = 0x10 // Bit mask of ACMDIDX field.
	SDHC_ACESR_ACMDIDX           = 0x10 // Bit ACMDIDX.
	SDHC_ACESR_ACMDIDX_NO        = 0x0  // No error
	SDHC_ACESR_ACMDIDX_YES       = 0x1  // Error
	SDHC_ACESR_CMDNI_Pos         = 0x7  // Position of CMDNI field.
	SDHC_ACESR_CMDNI_Msk         = 0x80 // Bit mask of CMDNI field.
	SDHC_ACESR_CMDNI             = 0x80 // Bit CMDNI.
	SDHC_ACESR_CMDNI_OK          = 0x0  // No error
	SDHC_ACESR_CMDNI_NOT_ISSUED  = 0x1  // Not Issued

	// HC2R: Host Control 2
	SDHC_HC2R_UHSMS_Pos        = 0x0    // Position of UHSMS field.
	SDHC_HC2R_UHSMS_Msk        = 0x7    // Bit mask of UHSMS field.
	SDHC_HC2R_UHSMS_SDR12      = 0x0    // SDR12
	SDHC_HC2R_UHSMS_SDR25      = 0x1    // SDR25
	SDHC_HC2R_UHSMS_SDR50      = 0x2    // SDR50
	SDHC_HC2R_UHSMS_SDR104     = 0x3    // SDR104
	SDHC_HC2R_UHSMS_DDR50      = 0x4    // DDR50
	SDHC_HC2R_VS18EN_Pos       = 0x3    // Position of VS18EN field.
	SDHC_HC2R_VS18EN_Msk       = 0x8    // Bit mask of VS18EN field.
	SDHC_HC2R_VS18EN           = 0x8    // Bit VS18EN.
	SDHC_HC2R_VS18EN_S33V      = 0x0    // 3.3V Signaling
	SDHC_HC2R_VS18EN_S18V      = 0x1    // 1.8V Signaling
	SDHC_HC2R_DRVSEL_Pos       = 0x4    // Position of DRVSEL field.
	SDHC_HC2R_DRVSEL_Msk       = 0x30   // Bit mask of DRVSEL field.
	SDHC_HC2R_DRVSEL_B         = 0x0    // Driver Type B is Selected (Default)
	SDHC_HC2R_DRVSEL_A         = 0x1    // Driver Type A is Selected
	SDHC_HC2R_DRVSEL_C         = 0x2    // Driver Type C is Selected
	SDHC_HC2R_DRVSEL_D         = 0x3    // Driver Type D is Selected
	SDHC_HC2R_EXTUN_Pos        = 0x6    // Position of EXTUN field.
	SDHC_HC2R_EXTUN_Msk        = 0x40   // Bit mask of EXTUN field.
	SDHC_HC2R_EXTUN            = 0x40   // Bit EXTUN.
	SDHC_HC2R_EXTUN_NO         = 0x0    // Not Tuned or Tuning Completed
	SDHC_HC2R_EXTUN_REQUESTED  = 0x1    // Execute Tuning
	SDHC_HC2R_SLCKSEL_Pos      = 0x7    // Position of SLCKSEL field.
	SDHC_HC2R_SLCKSEL_Msk      = 0x80   // Bit mask of SLCKSEL field.
	SDHC_HC2R_SLCKSEL          = 0x80   // Bit SLCKSEL.
	SDHC_HC2R_SLCKSEL_FIXED    = 0x0    // Fixed clock is used to sample data
	SDHC_HC2R_SLCKSEL_TUNED    = 0x1    // Tuned clock is used to sample data
	SDHC_HC2R_ASINTEN_Pos      = 0xe    // Position of ASINTEN field.
	SDHC_HC2R_ASINTEN_Msk      = 0x4000 // Bit mask of ASINTEN field.
	SDHC_HC2R_ASINTEN          = 0x4000 // Bit ASINTEN.
	SDHC_HC2R_ASINTEN_DISABLED = 0x0    // Disabled
	SDHC_HC2R_ASINTEN_ENABLED  = 0x1    // Enabled
	SDHC_HC2R_PVALEN_Pos       = 0xf    // Position of PVALEN field.
	SDHC_HC2R_PVALEN_Msk       = 0x8000 // Bit mask of PVALEN field.
	SDHC_HC2R_PVALEN           = 0x8000 // Bit PVALEN.
	SDHC_HC2R_PVALEN_HOST      = 0x0    // SDCLK and Driver Strength are controlled by Host Controller
	SDHC_HC2R_PVALEN_AUTO      = 0x1    // Automatic Selection by Preset Value is Enabled

	// HC2R_EMMC_MODE: Host Control 2
	SDHC_HC2R_EMMC_MODE_HS200EN_Pos     = 0x0    // Position of HS200EN field.
	SDHC_HC2R_EMMC_MODE_HS200EN_Msk     = 0xf    // Bit mask of HS200EN field.
	SDHC_HC2R_EMMC_MODE_HS200EN_SDR12   = 0x0    // SDR12
	SDHC_HC2R_EMMC_MODE_HS200EN_SDR25   = 0x1    // SDR25
	SDHC_HC2R_EMMC_MODE_HS200EN_SDR50   = 0x2    // SDR50
	SDHC_HC2R_EMMC_MODE_HS200EN_SDR104  = 0x3    // SDR104
	SDHC_HC2R_EMMC_MODE_HS200EN_DDR50   = 0x4    // DDR50
	SDHC_HC2R_EMMC_MODE_DRVSEL_Pos      = 0x4    // Position of DRVSEL field.
	SDHC_HC2R_EMMC_MODE_DRVSEL_Msk      = 0x30   // Bit mask of DRVSEL field.
	SDHC_HC2R_EMMC_MODE_DRVSEL_B        = 0x0    // Driver Type B is Selected (Default)
	SDHC_HC2R_EMMC_MODE_DRVSEL_A        = 0x1    // Driver Type A is Selected
	SDHC_HC2R_EMMC_MODE_DRVSEL_C        = 0x2    // Driver Type C is Selected
	SDHC_HC2R_EMMC_MODE_DRVSEL_D        = 0x3    // Driver Type D is Selected
	SDHC_HC2R_EMMC_MODE_EXTUN_Pos       = 0x6    // Position of EXTUN field.
	SDHC_HC2R_EMMC_MODE_EXTUN_Msk       = 0x40   // Bit mask of EXTUN field.
	SDHC_HC2R_EMMC_MODE_EXTUN           = 0x40   // Bit EXTUN.
	SDHC_HC2R_EMMC_MODE_EXTUN_NO        = 0x0    // Not Tuned or Tuning Completed
	SDHC_HC2R_EMMC_MODE_EXTUN_REQUESTED = 0x1    // Execute Tuning
	SDHC_HC2R_EMMC_MODE_SLCKSEL_Pos     = 0x7    // Position of SLCKSEL field.
	SDHC_HC2R_EMMC_MODE_SLCKSEL_Msk     = 0x80   // Bit mask of SLCKSEL field.
	SDHC_HC2R_EMMC_MODE_SLCKSEL         = 0x80   // Bit SLCKSEL.
	SDHC_HC2R_EMMC_MODE_SLCKSEL_FIXED   = 0x0    // Fixed clock is used to sample data
	SDHC_HC2R_EMMC_MODE_SLCKSEL_TUNED   = 0x1    // Tuned clock is used to sample data
	SDHC_HC2R_EMMC_MODE_PVALEN_Pos      = 0xf    // Position of PVALEN field.
	SDHC_HC2R_EMMC_MODE_PVALEN_Msk      = 0x8000 // Bit mask of PVALEN field.
	SDHC_HC2R_EMMC_MODE_PVALEN          = 0x8000 // Bit PVALEN.
	SDHC_HC2R_EMMC_MODE_PVALEN_HOST     = 0x0    // SDCLK and Driver Strength are controlled by Host Controller
	SDHC_HC2R_EMMC_MODE_PVALEN_AUTO     = 0x1    // Automatic Selection by Preset Value is Enabled

	// CA0R: Capabilities 0
	SDHC_CA0R_TEOCLKF_Pos      = 0x0        // Position of TEOCLKF field.
	SDHC_CA0R_TEOCLKF_Msk      = 0x3f       // Bit mask of TEOCLKF field.
	SDHC_CA0R_TEOCLKF_OTHER    = 0x0        // Get information via another method
	SDHC_CA0R_TEOCLKU_Pos      = 0x7        // Position of TEOCLKU field.
	SDHC_CA0R_TEOCLKU_Msk      = 0x80       // Bit mask of TEOCLKU field.
	SDHC_CA0R_TEOCLKU          = 0x80       // Bit TEOCLKU.
	SDHC_CA0R_TEOCLKU_KHZ      = 0x0        // KHz
	SDHC_CA0R_TEOCLKU_MHZ      = 0x1        // MHz
	SDHC_CA0R_BASECLKF_Pos     = 0x8        // Position of BASECLKF field.
	SDHC_CA0R_BASECLKF_Msk     = 0xff00     // Bit mask of BASECLKF field.
	SDHC_CA0R_BASECLKF_OTHER   = 0x0        // Get information via another method
	SDHC_CA0R_MAXBLKL_Pos      = 0x10       // Position of MAXBLKL field.
	SDHC_CA0R_MAXBLKL_Msk      = 0x30000    // Bit mask of MAXBLKL field.
	SDHC_CA0R_MAXBLKL_512      = 0x0        // 512 bytes
	SDHC_CA0R_MAXBLKL_1024     = 0x1        // 1024 bytes
	SDHC_CA0R_MAXBLKL_2048     = 0x2        // 2048 bytes
	SDHC_CA0R_ED8SUP_Pos       = 0x12       // Position of ED8SUP field.
	SDHC_CA0R_ED8SUP_Msk       = 0x40000    // Bit mask of ED8SUP field.
	SDHC_CA0R_ED8SUP           = 0x40000    // Bit ED8SUP.
	SDHC_CA0R_ED8SUP_NO        = 0x0        // 8-bit Bus Width not Supported
	SDHC_CA0R_ED8SUP_YES       = 0x1        // 8-bit Bus Width Supported
	SDHC_CA0R_ADMA2SUP_Pos     = 0x13       // Position of ADMA2SUP field.
	SDHC_CA0R_ADMA2SUP_Msk     = 0x80000    // Bit mask of ADMA2SUP field.
	SDHC_CA0R_ADMA2SUP         = 0x80000    // Bit ADMA2SUP.
	SDHC_CA0R_ADMA2SUP_NO      = 0x0        // ADMA2 not Supported
	SDHC_CA0R_ADMA2SUP_YES     = 0x1        // ADMA2 Supported
	SDHC_CA0R_HSSUP_Pos        = 0x15       // Position of HSSUP field.
	SDHC_CA0R_HSSUP_Msk        = 0x200000   // Bit mask of HSSUP field.
	SDHC_CA0R_HSSUP            = 0x200000   // Bit HSSUP.
	SDHC_CA0R_HSSUP_NO         = 0x0        // High Speed not Supported
	SDHC_CA0R_HSSUP_YES        = 0x1        // High Speed Supported
	SDHC_CA0R_SDMASUP_Pos      = 0x16       // Position of SDMASUP field.
	SDHC_CA0R_SDMASUP_Msk      = 0x400000   // Bit mask of SDMASUP field.
	SDHC_CA0R_SDMASUP          = 0x400000   // Bit SDMASUP.
	SDHC_CA0R_SDMASUP_NO       = 0x0        // SDMA not Supported
	SDHC_CA0R_SDMASUP_YES      = 0x1        // SDMA Supported
	SDHC_CA0R_SRSUP_Pos        = 0x17       // Position of SRSUP field.
	SDHC_CA0R_SRSUP_Msk        = 0x800000   // Bit mask of SRSUP field.
	SDHC_CA0R_SRSUP            = 0x800000   // Bit SRSUP.
	SDHC_CA0R_SRSUP_NO         = 0x0        // Suspend/Resume not Supported
	SDHC_CA0R_SRSUP_YES        = 0x1        // Suspend/Resume Supported
	SDHC_CA0R_V33VSUP_Pos      = 0x18       // Position of V33VSUP field.
	SDHC_CA0R_V33VSUP_Msk      = 0x1000000  // Bit mask of V33VSUP field.
	SDHC_CA0R_V33VSUP          = 0x1000000  // Bit V33VSUP.
	SDHC_CA0R_V33VSUP_NO       = 0x0        // 3.3V Not Supported
	SDHC_CA0R_V33VSUP_YES      = 0x1        // 3.3V Supported
	SDHC_CA0R_V30VSUP_Pos      = 0x19       // Position of V30VSUP field.
	SDHC_CA0R_V30VSUP_Msk      = 0x2000000  // Bit mask of V30VSUP field.
	SDHC_CA0R_V30VSUP          = 0x2000000  // Bit V30VSUP.
	SDHC_CA0R_V30VSUP_NO       = 0x0        // 3.0V Not Supported
	SDHC_CA0R_V30VSUP_YES      = 0x1        // 3.0V Supported
	SDHC_CA0R_V18VSUP_Pos      = 0x1a       // Position of V18VSUP field.
	SDHC_CA0R_V18VSUP_Msk      = 0x4000000  // Bit mask of V18VSUP field.
	SDHC_CA0R_V18VSUP          = 0x4000000  // Bit V18VSUP.
	SDHC_CA0R_V18VSUP_NO       = 0x0        // 1.8V Not Supported
	SDHC_CA0R_V18VSUP_YES      = 0x1        // 1.8V Supported
	SDHC_CA0R_SB64SUP_Pos      = 0x1c       // Position of SB64SUP field.
	SDHC_CA0R_SB64SUP_Msk      = 0x10000000 // Bit mask of SB64SUP field.
	SDHC_CA0R_SB64SUP          = 0x10000000 // Bit SB64SUP.
	SDHC_CA0R_SB64SUP_NO       = 0x0        // 32-bit Address Descriptors and System Bus
	SDHC_CA0R_SB64SUP_YES      = 0x1        // 64-bit Address Descriptors and System Bus
	SDHC_CA0R_ASINTSUP_Pos     = 0x1d       // Position of ASINTSUP field.
	SDHC_CA0R_ASINTSUP_Msk     = 0x20000000 // Bit mask of ASINTSUP field.
	SDHC_CA0R_ASINTSUP         = 0x20000000 // Bit ASINTSUP.
	SDHC_CA0R_ASINTSUP_NO      = 0x0        // Asynchronous Interrupt not Supported
	SDHC_CA0R_ASINTSUP_YES     = 0x1        // Asynchronous Interrupt supported
	SDHC_CA0R_SLTYPE_Pos       = 0x1e       // Position of SLTYPE field.
	SDHC_CA0R_SLTYPE_Msk       = 0xc0000000 // Bit mask of SLTYPE field.
	SDHC_CA0R_SLTYPE_REMOVABLE = 0x0        // Removable Card Slot
	SDHC_CA0R_SLTYPE_EMBEDDED  = 0x1        // Embedded Slot for One Device

	// CA1R: Capabilities 1
	SDHC_CA1R_SDR50SUP_Pos    = 0x0      // Position of SDR50SUP field.
	SDHC_CA1R_SDR50SUP_Msk    = 0x1      // Bit mask of SDR50SUP field.
	SDHC_CA1R_SDR50SUP        = 0x1      // Bit SDR50SUP.
	SDHC_CA1R_SDR50SUP_NO     = 0x0      // SDR50 is Not Supported
	SDHC_CA1R_SDR50SUP_YES    = 0x1      // SDR50 is Supported
	SDHC_CA1R_SDR104SUP_Pos   = 0x1      // Position of SDR104SUP field.
	SDHC_CA1R_SDR104SUP_Msk   = 0x2      // Bit mask of SDR104SUP field.
	SDHC_CA1R_SDR104SUP       = 0x2      // Bit SDR104SUP.
	SDHC_CA1R_SDR104SUP_NO    = 0x0      // SDR104 is Not Supported
	SDHC_CA1R_SDR104SUP_YES   = 0x1      // SDR104 is Supported
	SDHC_CA1R_DDR50SUP_Pos    = 0x2      // Position of DDR50SUP field.
	SDHC_CA1R_DDR50SUP_Msk    = 0x4      // Bit mask of DDR50SUP field.
	SDHC_CA1R_DDR50SUP        = 0x4      // Bit DDR50SUP.
	SDHC_CA1R_DDR50SUP_NO     = 0x0      // DDR50 is Not Supported
	SDHC_CA1R_DDR50SUP_YES    = 0x1      // DDR50 is Supported
	SDHC_CA1R_DRVASUP_Pos     = 0x4      // Position of DRVASUP field.
	SDHC_CA1R_DRVASUP_Msk     = 0x10     // Bit mask of DRVASUP field.
	SDHC_CA1R_DRVASUP         = 0x10     // Bit DRVASUP.
	SDHC_CA1R_DRVASUP_NO      = 0x0      // Driver Type A is Not Supported
	SDHC_CA1R_DRVASUP_YES     = 0x1      // Driver Type A is Supported
	SDHC_CA1R_DRVCSUP_Pos     = 0x5      // Position of DRVCSUP field.
	SDHC_CA1R_DRVCSUP_Msk     = 0x20     // Bit mask of DRVCSUP field.
	SDHC_CA1R_DRVCSUP         = 0x20     // Bit DRVCSUP.
	SDHC_CA1R_DRVCSUP_NO      = 0x0      // Driver Type C is Not Supported
	SDHC_CA1R_DRVCSUP_YES     = 0x1      // Driver Type C is Supported
	SDHC_CA1R_DRVDSUP_Pos     = 0x6      // Position of DRVDSUP field.
	SDHC_CA1R_DRVDSUP_Msk     = 0x40     // Bit mask of DRVDSUP field.
	SDHC_CA1R_DRVDSUP         = 0x40     // Bit DRVDSUP.
	SDHC_CA1R_DRVDSUP_NO      = 0x0      // Driver Type D is Not Supported
	SDHC_CA1R_DRVDSUP_YES     = 0x1      // Driver Type D is Supported
	SDHC_CA1R_TCNTRT_Pos      = 0x8      // Position of TCNTRT field.
	SDHC_CA1R_TCNTRT_Msk      = 0xf00    // Bit mask of TCNTRT field.
	SDHC_CA1R_TCNTRT_DISABLED = 0x0      // Re-Tuning Timer disabled
	SDHC_CA1R_TCNTRT_1S       = 0x1      // 1 second
	SDHC_CA1R_TCNTRT_2S       = 0x2      // 2 seconds
	SDHC_CA1R_TCNTRT_4S       = 0x3      // 4 seconds
	SDHC_CA1R_TCNTRT_8S       = 0x4      // 8 seconds
	SDHC_CA1R_TCNTRT_16S      = 0x5      // 16 seconds
	SDHC_CA1R_TCNTRT_32S      = 0x6      // 32 seconds
	SDHC_CA1R_TCNTRT_64S      = 0x7      // 64 seconds
	SDHC_CA1R_TCNTRT_128S     = 0x8      // 128 seconds
	SDHC_CA1R_TCNTRT_256S     = 0x9      // 256 seconds
	SDHC_CA1R_TCNTRT_512S     = 0xa      // 512 seconds
	SDHC_CA1R_TCNTRT_1024S    = 0xb      // 1024 seconds
	SDHC_CA1R_TCNTRT_OTHER    = 0xf      // Get information from other source
	SDHC_CA1R_TSDR50_Pos      = 0xd      // Position of TSDR50 field.
	SDHC_CA1R_TSDR50_Msk      = 0x2000   // Bit mask of TSDR50 field.
	SDHC_CA1R_TSDR50          = 0x2000   // Bit TSDR50.
	SDHC_CA1R_TSDR50_NO       = 0x0      // SDR50 does not require tuning
	SDHC_CA1R_TSDR50_YES      = 0x1      // SDR50 requires tuning
	SDHC_CA1R_CLKMULT_Pos     = 0x10     // Position of CLKMULT field.
	SDHC_CA1R_CLKMULT_Msk     = 0xff0000 // Bit mask of CLKMULT field.
	SDHC_CA1R_CLKMULT_NO      = 0x0      // Clock Multiplier is Not Supported

	// MCCAR: Maximum Current Capabilities
	SDHC_MCCAR_MAXCUR33V_Pos   = 0x0      // Position of MAXCUR33V field.
	SDHC_MCCAR_MAXCUR33V_Msk   = 0xff     // Bit mask of MAXCUR33V field.
	SDHC_MCCAR_MAXCUR33V_OTHER = 0x0      // Get information via another method
	SDHC_MCCAR_MAXCUR33V_4MA   = 0x1      // 4mA
	SDHC_MCCAR_MAXCUR33V_8MA   = 0x2      // 8mA
	SDHC_MCCAR_MAXCUR33V_12MA  = 0x3      // 12mA
	SDHC_MCCAR_MAXCUR30V_Pos   = 0x8      // Position of MAXCUR30V field.
	SDHC_MCCAR_MAXCUR30V_Msk   = 0xff00   // Bit mask of MAXCUR30V field.
	SDHC_MCCAR_MAXCUR30V_OTHER = 0x0      // Get information via another method
	SDHC_MCCAR_MAXCUR30V_4MA   = 0x1      // 4mA
	SDHC_MCCAR_MAXCUR30V_8MA   = 0x2      // 8mA
	SDHC_MCCAR_MAXCUR30V_12MA  = 0x3      // 12mA
	SDHC_MCCAR_MAXCUR18V_Pos   = 0x10     // Position of MAXCUR18V field.
	SDHC_MCCAR_MAXCUR18V_Msk   = 0xff0000 // Bit mask of MAXCUR18V field.
	SDHC_MCCAR_MAXCUR18V_OTHER = 0x0      // Get information via another method
	SDHC_MCCAR_MAXCUR18V_4MA   = 0x1      // 4mA
	SDHC_MCCAR_MAXCUR18V_8MA   = 0x2      // 8mA
	SDHC_MCCAR_MAXCUR18V_12MA  = 0x3      // 12mA

	// FERACES: Force Event for Auto CMD Error Status
	SDHC_FERACES_ACMD12NE_Pos = 0x0  // Position of ACMD12NE field.
	SDHC_FERACES_ACMD12NE_Msk = 0x1  // Bit mask of ACMD12NE field.
	SDHC_FERACES_ACMD12NE     = 0x1  // Bit ACMD12NE.
	SDHC_FERACES_ACMD12NE_NO  = 0x0  // No Interrupt
	SDHC_FERACES_ACMD12NE_YES = 0x1  // Interrupt is generated
	SDHC_FERACES_ACMDTEO_Pos  = 0x1  // Position of ACMDTEO field.
	SDHC_FERACES_ACMDTEO_Msk  = 0x2  // Bit mask of ACMDTEO field.
	SDHC_FERACES_ACMDTEO      = 0x2  // Bit ACMDTEO.
	SDHC_FERACES_ACMDTEO_NO   = 0x0  // No Interrupt
	SDHC_FERACES_ACMDTEO_YES  = 0x1  // Interrupt is generated
	SDHC_FERACES_ACMDCRC_Pos  = 0x2  // Position of ACMDCRC field.
	SDHC_FERACES_ACMDCRC_Msk  = 0x4  // Bit mask of ACMDCRC field.
	SDHC_FERACES_ACMDCRC      = 0x4  // Bit ACMDCRC.
	SDHC_FERACES_ACMDCRC_NO   = 0x0  // No Interrupt
	SDHC_FERACES_ACMDCRC_YES  = 0x1  // Interrupt is generated
	SDHC_FERACES_ACMDEND_Pos  = 0x3  // Position of ACMDEND field.
	SDHC_FERACES_ACMDEND_Msk  = 0x8  // Bit mask of ACMDEND field.
	SDHC_FERACES_ACMDEND      = 0x8  // Bit ACMDEND.
	SDHC_FERACES_ACMDEND_NO   = 0x0  // No Interrupt
	SDHC_FERACES_ACMDEND_YES  = 0x1  // Interrupt is generated
	SDHC_FERACES_ACMDIDX_Pos  = 0x4  // Position of ACMDIDX field.
	SDHC_FERACES_ACMDIDX_Msk  = 0x10 // Bit mask of ACMDIDX field.
	SDHC_FERACES_ACMDIDX      = 0x10 // Bit ACMDIDX.
	SDHC_FERACES_ACMDIDX_NO   = 0x0  // No Interrupt
	SDHC_FERACES_ACMDIDX_YES  = 0x1  // Interrupt is generated
	SDHC_FERACES_CMDNI_Pos    = 0x7  // Position of CMDNI field.
	SDHC_FERACES_CMDNI_Msk    = 0x80 // Bit mask of CMDNI field.
	SDHC_FERACES_CMDNI        = 0x80 // Bit CMDNI.
	SDHC_FERACES_CMDNI_NO     = 0x0  // No Interrupt
	SDHC_FERACES_CMDNI_YES    = 0x1  // Interrupt is generated

	// FEREIS: Force Event for Error Interrupt Status
	SDHC_FEREIS_CMDTEO_Pos = 0x0    // Position of CMDTEO field.
	SDHC_FEREIS_CMDTEO_Msk = 0x1    // Bit mask of CMDTEO field.
	SDHC_FEREIS_CMDTEO     = 0x1    // Bit CMDTEO.
	SDHC_FEREIS_CMDTEO_NO  = 0x0    // No Interrupt
	SDHC_FEREIS_CMDTEO_YES = 0x1    // Interrupt is generated
	SDHC_FEREIS_CMDCRC_Pos = 0x1    // Position of CMDCRC field.
	SDHC_FEREIS_CMDCRC_Msk = 0x2    // Bit mask of CMDCRC field.
	SDHC_FEREIS_CMDCRC     = 0x2    // Bit CMDCRC.
	SDHC_FEREIS_CMDCRC_NO  = 0x0    // No Interrupt
	SDHC_FEREIS_CMDCRC_YES = 0x1    // Interrupt is generated
	SDHC_FEREIS_CMDEND_Pos = 0x2    // Position of CMDEND field.
	SDHC_FEREIS_CMDEND_Msk = 0x4    // Bit mask of CMDEND field.
	SDHC_FEREIS_CMDEND     = 0x4    // Bit CMDEND.
	SDHC_FEREIS_CMDEND_NO  = 0x0    // No Interrupt
	SDHC_FEREIS_CMDEND_YES = 0x1    // Interrupt is generated
	SDHC_FEREIS_CMDIDX_Pos = 0x3    // Position of CMDIDX field.
	SDHC_FEREIS_CMDIDX_Msk = 0x8    // Bit mask of CMDIDX field.
	SDHC_FEREIS_CMDIDX     = 0x8    // Bit CMDIDX.
	SDHC_FEREIS_CMDIDX_NO  = 0x0    // No Interrupt
	SDHC_FEREIS_CMDIDX_YES = 0x1    // Interrupt is generated
	SDHC_FEREIS_DATTEO_Pos = 0x4    // Position of DATTEO field.
	SDHC_FEREIS_DATTEO_Msk = 0x10   // Bit mask of DATTEO field.
	SDHC_FEREIS_DATTEO     = 0x10   // Bit DATTEO.
	SDHC_FEREIS_DATTEO_NO  = 0x0    // No Interrupt
	SDHC_FEREIS_DATTEO_YES = 0x1    // Interrupt is generated
	SDHC_FEREIS_DATCRC_Pos = 0x5    // Position of DATCRC field.
	SDHC_FEREIS_DATCRC_Msk = 0x20   // Bit mask of DATCRC field.
	SDHC_FEREIS_DATCRC     = 0x20   // Bit DATCRC.
	SDHC_FEREIS_DATCRC_NO  = 0x0    // No Interrupt
	SDHC_FEREIS_DATCRC_YES = 0x1    // Interrupt is generated
	SDHC_FEREIS_DATEND_Pos = 0x6    // Position of DATEND field.
	SDHC_FEREIS_DATEND_Msk = 0x40   // Bit mask of DATEND field.
	SDHC_FEREIS_DATEND     = 0x40   // Bit DATEND.
	SDHC_FEREIS_DATEND_NO  = 0x0    // No Interrupt
	SDHC_FEREIS_DATEND_YES = 0x1    // Interrupt is generated
	SDHC_FEREIS_CURLIM_Pos = 0x7    // Position of CURLIM field.
	SDHC_FEREIS_CURLIM_Msk = 0x80   // Bit mask of CURLIM field.
	SDHC_FEREIS_CURLIM     = 0x80   // Bit CURLIM.
	SDHC_FEREIS_CURLIM_NO  = 0x0    // No Interrupt
	SDHC_FEREIS_CURLIM_YES = 0x1    // Interrupt is generated
	SDHC_FEREIS_ACMD_Pos   = 0x8    // Position of ACMD field.
	SDHC_FEREIS_ACMD_Msk   = 0x100  // Bit mask of ACMD field.
	SDHC_FEREIS_ACMD       = 0x100  // Bit ACMD.
	SDHC_FEREIS_ACMD_NO    = 0x0    // No Interrupt
	SDHC_FEREIS_ACMD_YES   = 0x1    // Interrupt is generated
	SDHC_FEREIS_ADMA_Pos   = 0x9    // Position of ADMA field.
	SDHC_FEREIS_ADMA_Msk   = 0x200  // Bit mask of ADMA field.
	SDHC_FEREIS_ADMA       = 0x200  // Bit ADMA.
	SDHC_FEREIS_ADMA_NO    = 0x0    // No Interrupt
	SDHC_FEREIS_ADMA_YES   = 0x1    // Interrupt is generated
	SDHC_FEREIS_BOOTAE_Pos = 0xc    // Position of BOOTAE field.
	SDHC_FEREIS_BOOTAE_Msk = 0x1000 // Bit mask of BOOTAE field.
	SDHC_FEREIS_BOOTAE     = 0x1000 // Bit BOOTAE.
	SDHC_FEREIS_BOOTAE_NO  = 0x0    // No Interrupt
	SDHC_FEREIS_BOOTAE_YES = 0x1    // Interrupt is generated

	// AESR: ADMA Error Status
	SDHC_AESR_ERRST_Pos  = 0x0 // Position of ERRST field.
	SDHC_AESR_ERRST_Msk  = 0x3 // Bit mask of ERRST field.
	SDHC_AESR_ERRST_STOP = 0x0 // ST_STOP (Stop DMA)
	SDHC_AESR_ERRST_FDS  = 0x1 // ST_FDS (Fetch Descriptor)
	SDHC_AESR_ERRST_TFR  = 0x3 // ST_TFR (Transfer Data)
	SDHC_AESR_LMIS_Pos   = 0x2 // Position of LMIS field.
	SDHC_AESR_LMIS_Msk   = 0x4 // Bit mask of LMIS field.
	SDHC_AESR_LMIS       = 0x4 // Bit LMIS.
	SDHC_AESR_LMIS_NO    = 0x0 // No Error
	SDHC_AESR_LMIS_YES   = 0x1 // Error

	// ASAR: ADMA System Address n
	SDHC_ASAR_ADMASA_Pos = 0x0        // Position of ADMASA field.
	SDHC_ASAR_ADMASA_Msk = 0xffffffff // Bit mask of ADMASA field.

	// PVR: Preset Value n
	SDHC_PVR_SDCLKFSEL_Pos = 0x0    // Position of SDCLKFSEL field.
	SDHC_PVR_SDCLKFSEL_Msk = 0x3ff  // Bit mask of SDCLKFSEL field.
	SDHC_PVR_CLKGSEL_Pos   = 0xa    // Position of CLKGSEL field.
	SDHC_PVR_CLKGSEL_Msk   = 0x400  // Bit mask of CLKGSEL field.
	SDHC_PVR_CLKGSEL       = 0x400  // Bit CLKGSEL.
	SDHC_PVR_CLKGSEL_DIV   = 0x0    // Host Controller Ver2.00 Compatible Clock Generator (Divider)
	SDHC_PVR_CLKGSEL_PROG  = 0x1    // Programmable Clock Generator
	SDHC_PVR_DRVSEL_Pos    = 0xe    // Position of DRVSEL field.
	SDHC_PVR_DRVSEL_Msk    = 0xc000 // Bit mask of DRVSEL field.
	SDHC_PVR_DRVSEL_B      = 0x0    // Driver Type B is Selected
	SDHC_PVR_DRVSEL_A      = 0x1    // Driver Type A is Selected
	SDHC_PVR_DRVSEL_C      = 0x2    // Driver Type C is Selected
	SDHC_PVR_DRVSEL_D      = 0x3    // Driver Type D is Selected

	// SISR: Slot Interrupt Status
	SDHC_SISR_INTSSL_Pos = 0x0 // Position of INTSSL field.
	SDHC_SISR_INTSSL_Msk = 0x1 // Bit mask of INTSSL field.
	SDHC_SISR_INTSSL     = 0x1 // Bit INTSSL.

	// HCVR: Host Controller Version
	SDHC_HCVR_SVER_Pos = 0x0    // Position of SVER field.
	SDHC_HCVR_SVER_Msk = 0xff   // Bit mask of SVER field.
	SDHC_HCVR_VVER_Pos = 0x8    // Position of VVER field.
	SDHC_HCVR_VVER_Msk = 0xff00 // Bit mask of VVER field.

	// MC1R: MMC Control 1
	SDHC_MC1R_CMDTYP_Pos     = 0x0  // Position of CMDTYP field.
	SDHC_MC1R_CMDTYP_Msk     = 0x3  // Bit mask of CMDTYP field.
	SDHC_MC1R_CMDTYP_NORMAL  = 0x0  // Not a MMC specific command
	SDHC_MC1R_CMDTYP_WAITIRQ = 0x1  // Wait IRQ Command
	SDHC_MC1R_CMDTYP_STREAM  = 0x2  // Stream Command
	SDHC_MC1R_CMDTYP_BOOT    = 0x3  // Boot Command
	SDHC_MC1R_DDR_Pos        = 0x3  // Position of DDR field.
	SDHC_MC1R_DDR_Msk        = 0x8  // Bit mask of DDR field.
	SDHC_MC1R_DDR            = 0x8  // Bit DDR.
	SDHC_MC1R_OPD_Pos        = 0x4  // Position of OPD field.
	SDHC_MC1R_OPD_Msk        = 0x10 // Bit mask of OPD field.
	SDHC_MC1R_OPD            = 0x10 // Bit OPD.
	SDHC_MC1R_BOOTA_Pos      = 0x5  // Position of BOOTA field.
	SDHC_MC1R_BOOTA_Msk      = 0x20 // Bit mask of BOOTA field.
	SDHC_MC1R_BOOTA          = 0x20 // Bit BOOTA.
	SDHC_MC1R_RSTN_Pos       = 0x6  // Position of RSTN field.
	SDHC_MC1R_RSTN_Msk       = 0x40 // Bit mask of RSTN field.
	SDHC_MC1R_RSTN           = 0x40 // Bit RSTN.
	SDHC_MC1R_FCD_Pos        = 0x7  // Position of FCD field.
	SDHC_MC1R_FCD_Msk        = 0x80 // Bit mask of FCD field.
	SDHC_MC1R_FCD            = 0x80 // Bit FCD.

	// MC2R: MMC Control 2
	SDHC_MC2R_SRESP_Pos = 0x0 // Position of SRESP field.
	SDHC_MC2R_SRESP_Msk = 0x1 // Bit mask of SRESP field.
	SDHC_MC2R_SRESP     = 0x1 // Bit SRESP.
	SDHC_MC2R_ABOOT_Pos = 0x1 // Position of ABOOT field.
	SDHC_MC2R_ABOOT_Msk = 0x2 // Bit mask of ABOOT field.
	SDHC_MC2R_ABOOT     = 0x2 // Bit ABOOT.

	// ACR: AHB Control
	SDHC_ACR_BMAX_Pos    = 0x0 // Position of BMAX field.
	SDHC_ACR_BMAX_Msk    = 0x3 // Bit mask of BMAX field.
	SDHC_ACR_BMAX_INCR16 = 0x0
	SDHC_ACR_BMAX_INCR8  = 0x1
	SDHC_ACR_BMAX_INCR4  = 0x2
	SDHC_ACR_BMAX_SINGLE = 0x3

	// CC2R: Clock Control 2
	SDHC_CC2R_FSDCLKD_Pos      = 0x0 // Position of FSDCLKD field.
	SDHC_CC2R_FSDCLKD_Msk      = 0x1 // Bit mask of FSDCLKD field.
	SDHC_CC2R_FSDCLKD          = 0x1 // Bit FSDCLKD.
	SDHC_CC2R_FSDCLKD_NOEFFECT = 0x0 // No effect
	SDHC_CC2R_FSDCLKD_DISABLE  = 0x1 // SDCLK can be stopped at any time after DATA transfer.SDCLK enable forcing for 8 SDCLK cycles is disabled

	// CACR: Capabilities Control
	SDHC_CACR_CAPWREN_Pos = 0x0    // Position of CAPWREN field.
	SDHC_CACR_CAPWREN_Msk = 0x1    // Bit mask of CAPWREN field.
	SDHC_CACR_CAPWREN     = 0x1    // Bit CAPWREN.
	SDHC_CACR_KEY_Pos     = 0x8    // Position of KEY field.
	SDHC_CACR_KEY_Msk     = 0xff00 // Bit mask of KEY field.

	// DBGR: Debug
	SDHC_DBGR_NIDBG_Pos   = 0x0 // Position of NIDBG field.
	SDHC_DBGR_NIDBG_Msk   = 0x1 // Bit mask of NIDBG field.
	SDHC_DBGR_NIDBG       = 0x1 // Bit NIDBG.
	SDHC_DBGR_NIDBG_IDBG  = 0x0 // Debugging is intrusive (reads of BDPR from debugger are considered and increment the internal buffer pointer)
	SDHC_DBGR_NIDBG_NIDBG = 0x1 // Debugging is not intrusive (reads of BDPR from debugger are discarded and do not increment the internal buffer pointer)
)

// Bitfields for SERCOM0: Serial Communication Interface
const ()

// Bitfields for SERCOM0_I2CM: Serial Communication Interface - I2CM
const (
	// CTRLA: I2CM Control A
	SERCOM_I2CM_CTRLA_SWRST_Pos                    = 0x0        // Position of SWRST field.
	SERCOM_I2CM_CTRLA_SWRST_Msk                    = 0x1        // Bit mask of SWRST field.
	SERCOM_I2CM_CTRLA_SWRST                        = 0x1        // Bit SWRST.
	SERCOM_I2CM_CTRLA_ENABLE_Pos                   = 0x1        // Position of ENABLE field.
	SERCOM_I2CM_CTRLA_ENABLE_Msk                   = 0x2        // Bit mask of ENABLE field.
	SERCOM_I2CM_CTRLA_ENABLE                       = 0x2        // Bit ENABLE.
	SERCOM_I2CM_CTRLA_MODE_Pos                     = 0x2        // Position of MODE field.
	SERCOM_I2CM_CTRLA_MODE_Msk                     = 0x1c       // Bit mask of MODE field.
	SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK           = 0x0        // USART with external clock
	SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK           = 0x1        // USART with internal clock
	SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE               = 0x2        // SPI in slave operation
	SERCOM_I2CM_CTRLA_MODE_SPI_MASTER              = 0x3        // SPI in master operation
	SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE               = 0x4        // I2C slave operation
	SERCOM_I2CM_CTRLA_MODE_I2C_MASTER              = 0x5        // I2C master operation
	SERCOM_I2CM_CTRLA_RUNSTDBY_Pos                 = 0x7        // Position of RUNSTDBY field.
	SERCOM_I2CM_CTRLA_RUNSTDBY_Msk                 = 0x80       // Bit mask of RUNSTDBY field.
	SERCOM_I2CM_CTRLA_RUNSTDBY                     = 0x80       // Bit RUNSTDBY.
	SERCOM_I2CM_CTRLA_PINOUT_Pos                   = 0x10       // Position of PINOUT field.
	SERCOM_I2CM_CTRLA_PINOUT_Msk                   = 0x10000    // Bit mask of PINOUT field.
	SERCOM_I2CM_CTRLA_PINOUT                       = 0x10000    // Bit PINOUT.
	SERCOM_I2CM_CTRLA_SDAHOLD_Pos                  = 0x14       // Position of SDAHOLD field.
	SERCOM_I2CM_CTRLA_SDAHOLD_Msk                  = 0x300000   // Bit mask of SDAHOLD field.
	SERCOM_I2CM_CTRLA_SDAHOLD_DISABLE              = 0x0        // Disabled
	SERCOM_I2CM_CTRLA_SDAHOLD_75NS                 = 0x1        // 50-100ns hold time
	SERCOM_I2CM_CTRLA_SDAHOLD_450NS                = 0x2        // 300-600ns hold time
	SERCOM_I2CM_CTRLA_SDAHOLD_600NS                = 0x3        // 400-800ns hold time
	SERCOM_I2CM_CTRLA_MEXTTOEN_Pos                 = 0x16       // Position of MEXTTOEN field.
	SERCOM_I2CM_CTRLA_MEXTTOEN_Msk                 = 0x400000   // Bit mask of MEXTTOEN field.
	SERCOM_I2CM_CTRLA_MEXTTOEN                     = 0x400000   // Bit MEXTTOEN.
	SERCOM_I2CM_CTRLA_SEXTTOEN_Pos                 = 0x17       // Position of SEXTTOEN field.
	SERCOM_I2CM_CTRLA_SEXTTOEN_Msk                 = 0x800000   // Bit mask of SEXTTOEN field.
	SERCOM_I2CM_CTRLA_SEXTTOEN                     = 0x800000   // Bit SEXTTOEN.
	SERCOM_I2CM_CTRLA_SPEED_Pos                    = 0x18       // Position of SPEED field.
	SERCOM_I2CM_CTRLA_SPEED_Msk                    = 0x3000000  // Bit mask of SPEED field.
	SERCOM_I2CM_CTRLA_SPEED_STANDARD_AND_FAST_MODE = 0x0        // Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz
	SERCOM_I2CM_CTRLA_SPEED_FASTPLUS_MODE          = 0x1        // Fast-mode Plus Upto 1MHz
	SERCOM_I2CM_CTRLA_SPEED_HIGH_SPEED_MODE        = 0x2        // High-speed mode Upto 3.4MHz
	SERCOM_I2CM_CTRLA_SCLSM_Pos                    = 0x1b       // Position of SCLSM field.
	SERCOM_I2CM_CTRLA_SCLSM_Msk                    = 0x8000000  // Bit mask of SCLSM field.
	SERCOM_I2CM_CTRLA_SCLSM                        = 0x8000000  // Bit SCLSM.
	SERCOM_I2CM_CTRLA_INACTOUT_Pos                 = 0x1c       // Position of INACTOUT field.
	SERCOM_I2CM_CTRLA_INACTOUT_Msk                 = 0x30000000 // Bit mask of INACTOUT field.
	SERCOM_I2CM_CTRLA_INACTOUT_DISABLE             = 0x0        // Disabled
	SERCOM_I2CM_CTRLA_INACTOUT_55US                = 0x1        // 5-6 SCL Time-Out(50-60us)
	SERCOM_I2CM_CTRLA_INACTOUT_105US               = 0x2        // 10-11 SCL Time-Out(100-110us)
	SERCOM_I2CM_CTRLA_INACTOUT_205US               = 0x3        // 20-21 SCL Time-Out(200-210us)
	SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos                = 0x1e       // Position of LOWTOUTEN field.
	SERCOM_I2CM_CTRLA_LOWTOUTEN_Msk                = 0x40000000 // Bit mask of LOWTOUTEN field.
	SERCOM_I2CM_CTRLA_LOWTOUTEN                    = 0x40000000 // Bit LOWTOUTEN.

	// CTRLB: I2CM Control B
	SERCOM_I2CM_CTRLB_SMEN_Pos   = 0x8     // Position of SMEN field.
	SERCOM_I2CM_CTRLB_SMEN_Msk   = 0x100   // Bit mask of SMEN field.
	SERCOM_I2CM_CTRLB_SMEN       = 0x100   // Bit SMEN.
	SERCOM_I2CM_CTRLB_QCEN_Pos   = 0x9     // Position of QCEN field.
	SERCOM_I2CM_CTRLB_QCEN_Msk   = 0x200   // Bit mask of QCEN field.
	SERCOM_I2CM_CTRLB_QCEN       = 0x200   // Bit QCEN.
	SERCOM_I2CM_CTRLB_CMD_Pos    = 0x10    // Position of CMD field.
	SERCOM_I2CM_CTRLB_CMD_Msk    = 0x30000 // Bit mask of CMD field.
	SERCOM_I2CM_CTRLB_ACKACT_Pos = 0x12    // Position of ACKACT field.
	SERCOM_I2CM_CTRLB_ACKACT_Msk = 0x40000 // Bit mask of ACKACT field.
	SERCOM_I2CM_CTRLB_ACKACT     = 0x40000 // Bit ACKACT.

	// CTRLC: I2CM Control C
	SERCOM_I2CM_CTRLC_DATA32B_Pos              = 0x18      // Position of DATA32B field.
	SERCOM_I2CM_CTRLC_DATA32B_Msk              = 0x1000000 // Bit mask of DATA32B field.
	SERCOM_I2CM_CTRLC_DATA32B                  = 0x1000000 // Bit DATA32B.
	SERCOM_I2CM_CTRLC_DATA32B_DATA_TRANS_8BIT  = 0x0       // Data transaction from/to DATA register are 8-bit
	SERCOM_I2CM_CTRLC_DATA32B_DATA_TRANS_32BIT = 0x1       // Data transaction from/to DATA register are 32-bit

	// BAUD: I2CM Baud Rate
	SERCOM_I2CM_BAUD_BAUD_Pos      = 0x0        // Position of BAUD field.
	SERCOM_I2CM_BAUD_BAUD_Msk      = 0xff       // Bit mask of BAUD field.
	SERCOM_I2CM_BAUD_BAUDLOW_Pos   = 0x8        // Position of BAUDLOW field.
	SERCOM_I2CM_BAUD_BAUDLOW_Msk   = 0xff00     // Bit mask of BAUDLOW field.
	SERCOM_I2CM_BAUD_HSBAUD_Pos    = 0x10       // Position of HSBAUD field.
	SERCOM_I2CM_BAUD_HSBAUD_Msk    = 0xff0000   // Bit mask of HSBAUD field.
	SERCOM_I2CM_BAUD_HSBAUDLOW_Pos = 0x18       // Position of HSBAUDLOW field.
	SERCOM_I2CM_BAUD_HSBAUDLOW_Msk = 0xff000000 // Bit mask of HSBAUDLOW field.

	// INTENCLR: I2CM Interrupt Enable Clear
	SERCOM_I2CM_INTENCLR_MB_Pos    = 0x0  // Position of MB field.
	SERCOM_I2CM_INTENCLR_MB_Msk    = 0x1  // Bit mask of MB field.
	SERCOM_I2CM_INTENCLR_MB        = 0x1  // Bit MB.
	SERCOM_I2CM_INTENCLR_SB_Pos    = 0x1  // Position of SB field.
	SERCOM_I2CM_INTENCLR_SB_Msk    = 0x2  // Bit mask of SB field.
	SERCOM_I2CM_INTENCLR_SB        = 0x2  // Bit SB.
	SERCOM_I2CM_INTENCLR_ERROR_Pos = 0x7  // Position of ERROR field.
	SERCOM_I2CM_INTENCLR_ERROR_Msk = 0x80 // Bit mask of ERROR field.
	SERCOM_I2CM_INTENCLR_ERROR     = 0x80 // Bit ERROR.

	// INTENSET: I2CM Interrupt Enable Set
	SERCOM_I2CM_INTENSET_MB_Pos    = 0x0  // Position of MB field.
	SERCOM_I2CM_INTENSET_MB_Msk    = 0x1  // Bit mask of MB field.
	SERCOM_I2CM_INTENSET_MB        = 0x1  // Bit MB.
	SERCOM_I2CM_INTENSET_SB_Pos    = 0x1  // Position of SB field.
	SERCOM_I2CM_INTENSET_SB_Msk    = 0x2  // Bit mask of SB field.
	SERCOM_I2CM_INTENSET_SB        = 0x2  // Bit SB.
	SERCOM_I2CM_INTENSET_ERROR_Pos = 0x7  // Position of ERROR field.
	SERCOM_I2CM_INTENSET_ERROR_Msk = 0x80 // Bit mask of ERROR field.
	SERCOM_I2CM_INTENSET_ERROR     = 0x80 // Bit ERROR.

	// INTFLAG: I2CM Interrupt Flag Status and Clear
	SERCOM_I2CM_INTFLAG_MB_Pos    = 0x0  // Position of MB field.
	SERCOM_I2CM_INTFLAG_MB_Msk    = 0x1  // Bit mask of MB field.
	SERCOM_I2CM_INTFLAG_MB        = 0x1  // Bit MB.
	SERCOM_I2CM_INTFLAG_SB_Pos    = 0x1  // Position of SB field.
	SERCOM_I2CM_INTFLAG_SB_Msk    = 0x2  // Bit mask of SB field.
	SERCOM_I2CM_INTFLAG_SB        = 0x2  // Bit SB.
	SERCOM_I2CM_INTFLAG_ERROR_Pos = 0x7  // Position of ERROR field.
	SERCOM_I2CM_INTFLAG_ERROR_Msk = 0x80 // Bit mask of ERROR field.
	SERCOM_I2CM_INTFLAG_ERROR     = 0x80 // Bit ERROR.

	// STATUS: I2CM Status
	SERCOM_I2CM_STATUS_BUSERR_Pos   = 0x0   // Position of BUSERR field.
	SERCOM_I2CM_STATUS_BUSERR_Msk   = 0x1   // Bit mask of BUSERR field.
	SERCOM_I2CM_STATUS_BUSERR       = 0x1   // Bit BUSERR.
	SERCOM_I2CM_STATUS_ARBLOST_Pos  = 0x1   // Position of ARBLOST field.
	SERCOM_I2CM_STATUS_ARBLOST_Msk  = 0x2   // Bit mask of ARBLOST field.
	SERCOM_I2CM_STATUS_ARBLOST      = 0x2   // Bit ARBLOST.
	SERCOM_I2CM_STATUS_RXNACK_Pos   = 0x2   // Position of RXNACK field.
	SERCOM_I2CM_STATUS_RXNACK_Msk   = 0x4   // Bit mask of RXNACK field.
	SERCOM_I2CM_STATUS_RXNACK       = 0x4   // Bit RXNACK.
	SERCOM_I2CM_STATUS_BUSSTATE_Pos = 0x4   // Position of BUSSTATE field.
	SERCOM_I2CM_STATUS_BUSSTATE_Msk = 0x30  // Bit mask of BUSSTATE field.
	SERCOM_I2CM_STATUS_LOWTOUT_Pos  = 0x6   // Position of LOWTOUT field.
	SERCOM_I2CM_STATUS_LOWTOUT_Msk  = 0x40  // Bit mask of LOWTOUT field.
	SERCOM_I2CM_STATUS_LOWTOUT      = 0x40  // Bit LOWTOUT.
	SERCOM_I2CM_STATUS_CLKHOLD_Pos  = 0x7   // Position of CLKHOLD field.
	SERCOM_I2CM_STATUS_CLKHOLD_Msk  = 0x80  // Bit mask of CLKHOLD field.
	SERCOM_I2CM_STATUS_CLKHOLD      = 0x80  // Bit CLKHOLD.
	SERCOM_I2CM_STATUS_MEXTTOUT_Pos = 0x8   // Position of MEXTTOUT field.
	SERCOM_I2CM_STATUS_MEXTTOUT_Msk = 0x100 // Bit mask of MEXTTOUT field.
	SERCOM_I2CM_STATUS_MEXTTOUT     = 0x100 // Bit MEXTTOUT.
	SERCOM_I2CM_STATUS_SEXTTOUT_Pos = 0x9   // Position of SEXTTOUT field.
	SERCOM_I2CM_STATUS_SEXTTOUT_Msk = 0x200 // Bit mask of SEXTTOUT field.
	SERCOM_I2CM_STATUS_SEXTTOUT     = 0x200 // Bit SEXTTOUT.
	SERCOM_I2CM_STATUS_LENERR_Pos   = 0xa   // Position of LENERR field.
	SERCOM_I2CM_STATUS_LENERR_Msk   = 0x400 // Bit mask of LENERR field.
	SERCOM_I2CM_STATUS_LENERR       = 0x400 // Bit LENERR.

	// SYNCBUSY: I2CM Synchronization Busy
	SERCOM_I2CM_SYNCBUSY_SWRST_Pos  = 0x0  // Position of SWRST field.
	SERCOM_I2CM_SYNCBUSY_SWRST_Msk  = 0x1  // Bit mask of SWRST field.
	SERCOM_I2CM_SYNCBUSY_SWRST      = 0x1  // Bit SWRST.
	SERCOM_I2CM_SYNCBUSY_ENABLE_Pos = 0x1  // Position of ENABLE field.
	SERCOM_I2CM_SYNCBUSY_ENABLE_Msk = 0x2  // Bit mask of ENABLE field.
	SERCOM_I2CM_SYNCBUSY_ENABLE     = 0x2  // Bit ENABLE.
	SERCOM_I2CM_SYNCBUSY_SYSOP_Pos  = 0x2  // Position of SYSOP field.
	SERCOM_I2CM_SYNCBUSY_SYSOP_Msk  = 0x4  // Bit mask of SYSOP field.
	SERCOM_I2CM_SYNCBUSY_SYSOP      = 0x4  // Bit SYSOP.
	SERCOM_I2CM_SYNCBUSY_LENGTH_Pos = 0x4  // Position of LENGTH field.
	SERCOM_I2CM_SYNCBUSY_LENGTH_Msk = 0x10 // Bit mask of LENGTH field.
	SERCOM_I2CM_SYNCBUSY_LENGTH     = 0x10 // Bit LENGTH.

	// ADDR: I2CM Address
	SERCOM_I2CM_ADDR_ADDR_Pos     = 0x0      // Position of ADDR field.
	SERCOM_I2CM_ADDR_ADDR_Msk     = 0x7ff    // Bit mask of ADDR field.
	SERCOM_I2CM_ADDR_LENEN_Pos    = 0xd      // Position of LENEN field.
	SERCOM_I2CM_ADDR_LENEN_Msk    = 0x2000   // Bit mask of LENEN field.
	SERCOM_I2CM_ADDR_LENEN        = 0x2000   // Bit LENEN.
	SERCOM_I2CM_ADDR_HS_Pos       = 0xe      // Position of HS field.
	SERCOM_I2CM_ADDR_HS_Msk       = 0x4000   // Bit mask of HS field.
	SERCOM_I2CM_ADDR_HS           = 0x4000   // Bit HS.
	SERCOM_I2CM_ADDR_TENBITEN_Pos = 0xf      // Position of TENBITEN field.
	SERCOM_I2CM_ADDR_TENBITEN_Msk = 0x8000   // Bit mask of TENBITEN field.
	SERCOM_I2CM_ADDR_TENBITEN     = 0x8000   // Bit TENBITEN.
	SERCOM_I2CM_ADDR_LEN_Pos      = 0x10     // Position of LEN field.
	SERCOM_I2CM_ADDR_LEN_Msk      = 0xff0000 // Bit mask of LEN field.

	// DATA: I2CM Data
	SERCOM_I2CM_DATA_DATA_Pos = 0x0  // Position of DATA field.
	SERCOM_I2CM_DATA_DATA_Msk = 0xff // Bit mask of DATA field.

	// DBGCTRL: I2CM Debug Control
	SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos = 0x0 // Position of DBGSTOP field.
	SERCOM_I2CM_DBGCTRL_DBGSTOP_Msk = 0x1 // Bit mask of DBGSTOP field.
	SERCOM_I2CM_DBGCTRL_DBGSTOP     = 0x1 // Bit DBGSTOP.
)

// Bitfields for SERCOM0_I2CS: Serial Communication Interface - I2CS
const (
	// CTRLA: I2CS Control A
	SERCOM_I2CS_CTRLA_SWRST_Pos                    = 0x0        // Position of SWRST field.
	SERCOM_I2CS_CTRLA_SWRST_Msk                    = 0x1        // Bit mask of SWRST field.
	SERCOM_I2CS_CTRLA_SWRST                        = 0x1        // Bit SWRST.
	SERCOM_I2CS_CTRLA_ENABLE_Pos                   = 0x1        // Position of ENABLE field.
	SERCOM_I2CS_CTRLA_ENABLE_Msk                   = 0x2        // Bit mask of ENABLE field.
	SERCOM_I2CS_CTRLA_ENABLE                       = 0x2        // Bit ENABLE.
	SERCOM_I2CS_CTRLA_MODE_Pos                     = 0x2        // Position of MODE field.
	SERCOM_I2CS_CTRLA_MODE_Msk                     = 0x1c       // Bit mask of MODE field.
	SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK           = 0x0        // USART with external clock
	SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK           = 0x1        // USART with internal clock
	SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE               = 0x2        // SPI in slave operation
	SERCOM_I2CS_CTRLA_MODE_SPI_MASTER              = 0x3        // SPI in master operation
	SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE               = 0x4        // I2C slave operation
	SERCOM_I2CS_CTRLA_MODE_I2C_MASTER              = 0x5        // I2C master operation
	SERCOM_I2CS_CTRLA_RUNSTDBY_Pos                 = 0x7        // Position of RUNSTDBY field.
	SERCOM_I2CS_CTRLA_RUNSTDBY_Msk                 = 0x80       // Bit mask of RUNSTDBY field.
	SERCOM_I2CS_CTRLA_RUNSTDBY                     = 0x80       // Bit RUNSTDBY.
	SERCOM_I2CS_CTRLA_PINOUT_Pos                   = 0x10       // Position of PINOUT field.
	SERCOM_I2CS_CTRLA_PINOUT_Msk                   = 0x10000    // Bit mask of PINOUT field.
	SERCOM_I2CS_CTRLA_PINOUT                       = 0x10000    // Bit PINOUT.
	SERCOM_I2CS_CTRLA_SDAHOLD_Pos                  = 0x14       // Position of SDAHOLD field.
	SERCOM_I2CS_CTRLA_SDAHOLD_Msk                  = 0x300000   // Bit mask of SDAHOLD field.
	SERCOM_I2CS_CTRLA_SDAHOLD_DISABLE              = 0x0        // Disabled
	SERCOM_I2CS_CTRLA_SDAHOLD_75NS                 = 0x1        // 50-100ns hold time
	SERCOM_I2CS_CTRLA_SDAHOLD_450NS                = 0x2        // 300-600ns hold time
	SERCOM_I2CS_CTRLA_SDAHOLD_600NS                = 0x3        // 400-800ns hold time
	SERCOM_I2CS_CTRLA_SEXTTOEN_Pos                 = 0x17       // Position of SEXTTOEN field.
	SERCOM_I2CS_CTRLA_SEXTTOEN_Msk                 = 0x800000   // Bit mask of SEXTTOEN field.
	SERCOM_I2CS_CTRLA_SEXTTOEN                     = 0x800000   // Bit SEXTTOEN.
	SERCOM_I2CS_CTRLA_SPEED_Pos                    = 0x18       // Position of SPEED field.
	SERCOM_I2CS_CTRLA_SPEED_Msk                    = 0x3000000  // Bit mask of SPEED field.
	SERCOM_I2CS_CTRLA_SPEED_STANDARD_AND_FAST_MODE = 0x0        // Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz
	SERCOM_I2CS_CTRLA_SPEED_FASTPLUS_MODE          = 0x1        // Fast-mode Plus Upto 1MHz
	SERCOM_I2CS_CTRLA_SPEED_HIGH_SPEED_MODE        = 0x2        // High-speed mode Upto 3.4MHz
	SERCOM_I2CS_CTRLA_SCLSM_Pos                    = 0x1b       // Position of SCLSM field.
	SERCOM_I2CS_CTRLA_SCLSM_Msk                    = 0x8000000  // Bit mask of SCLSM field.
	SERCOM_I2CS_CTRLA_SCLSM                        = 0x8000000  // Bit SCLSM.
	SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos                = 0x1e       // Position of LOWTOUTEN field.
	SERCOM_I2CS_CTRLA_LOWTOUTEN_Msk                = 0x40000000 // Bit mask of LOWTOUTEN field.
	SERCOM_I2CS_CTRLA_LOWTOUTEN                    = 0x40000000 // Bit LOWTOUTEN.

	// CTRLB: I2CS Control B
	SERCOM_I2CS_CTRLB_SMEN_Pos   = 0x8     // Position of SMEN field.
	SERCOM_I2CS_CTRLB_SMEN_Msk   = 0x100   // Bit mask of SMEN field.
	SERCOM_I2CS_CTRLB_SMEN       = 0x100   // Bit SMEN.
	SERCOM_I2CS_CTRLB_GCMD_Pos   = 0x9     // Position of GCMD field.
	SERCOM_I2CS_CTRLB_GCMD_Msk   = 0x200   // Bit mask of GCMD field.
	SERCOM_I2CS_CTRLB_GCMD       = 0x200   // Bit GCMD.
	SERCOM_I2CS_CTRLB_AACKEN_Pos = 0xa     // Position of AACKEN field.
	SERCOM_I2CS_CTRLB_AACKEN_Msk = 0x400   // Bit mask of AACKEN field.
	SERCOM_I2CS_CTRLB_AACKEN     = 0x400   // Bit AACKEN.
	SERCOM_I2CS_CTRLB_AMODE_Pos  = 0xe     // Position of AMODE field.
	SERCOM_I2CS_CTRLB_AMODE_Msk  = 0xc000  // Bit mask of AMODE field.
	SERCOM_I2CS_CTRLB_CMD_Pos    = 0x10    // Position of CMD field.
	SERCOM_I2CS_CTRLB_CMD_Msk    = 0x30000 // Bit mask of CMD field.
	SERCOM_I2CS_CTRLB_ACKACT_Pos = 0x12    // Position of ACKACT field.
	SERCOM_I2CS_CTRLB_ACKACT_Msk = 0x40000 // Bit mask of ACKACT field.
	SERCOM_I2CS_CTRLB_ACKACT     = 0x40000 // Bit ACKACT.

	// CTRLC: I2CS Control C
	SERCOM_I2CS_CTRLC_SDASETUP_Pos             = 0x0       // Position of SDASETUP field.
	SERCOM_I2CS_CTRLC_SDASETUP_Msk             = 0xf       // Bit mask of SDASETUP field.
	SERCOM_I2CS_CTRLC_DATA32B_Pos              = 0x18      // Position of DATA32B field.
	SERCOM_I2CS_CTRLC_DATA32B_Msk              = 0x1000000 // Bit mask of DATA32B field.
	SERCOM_I2CS_CTRLC_DATA32B                  = 0x1000000 // Bit DATA32B.
	SERCOM_I2CS_CTRLC_DATA32B_DATA_TRANS_8BIT  = 0x0       // Data transaction from/to DATA register are 8-bit
	SERCOM_I2CS_CTRLC_DATA32B_DATA_TRANS_32BIT = 0x1       // Data transaction from/to DATA register are 32-bit

	// INTENCLR: I2CS Interrupt Enable Clear
	SERCOM_I2CS_INTENCLR_PREC_Pos   = 0x0  // Position of PREC field.
	SERCOM_I2CS_INTENCLR_PREC_Msk   = 0x1  // Bit mask of PREC field.
	SERCOM_I2CS_INTENCLR_PREC       = 0x1  // Bit PREC.
	SERCOM_I2CS_INTENCLR_AMATCH_Pos = 0x1  // Position of AMATCH field.
	SERCOM_I2CS_INTENCLR_AMATCH_Msk = 0x2  // Bit mask of AMATCH field.
	SERCOM_I2CS_INTENCLR_AMATCH     = 0x2  // Bit AMATCH.
	SERCOM_I2CS_INTENCLR_DRDY_Pos   = 0x2  // Position of DRDY field.
	SERCOM_I2CS_INTENCLR_DRDY_Msk   = 0x4  // Bit mask of DRDY field.
	SERCOM_I2CS_INTENCLR_DRDY       = 0x4  // Bit DRDY.
	SERCOM_I2CS_INTENCLR_ERROR_Pos  = 0x7  // Position of ERROR field.
	SERCOM_I2CS_INTENCLR_ERROR_Msk  = 0x80 // Bit mask of ERROR field.
	SERCOM_I2CS_INTENCLR_ERROR      = 0x80 // Bit ERROR.

	// INTENSET: I2CS Interrupt Enable Set
	SERCOM_I2CS_INTENSET_PREC_Pos   = 0x0  // Position of PREC field.
	SERCOM_I2CS_INTENSET_PREC_Msk   = 0x1  // Bit mask of PREC field.
	SERCOM_I2CS_INTENSET_PREC       = 0x1  // Bit PREC.
	SERCOM_I2CS_INTENSET_AMATCH_Pos = 0x1  // Position of AMATCH field.
	SERCOM_I2CS_INTENSET_AMATCH_Msk = 0x2  // Bit mask of AMATCH field.
	SERCOM_I2CS_INTENSET_AMATCH     = 0x2  // Bit AMATCH.
	SERCOM_I2CS_INTENSET_DRDY_Pos   = 0x2  // Position of DRDY field.
	SERCOM_I2CS_INTENSET_DRDY_Msk   = 0x4  // Bit mask of DRDY field.
	SERCOM_I2CS_INTENSET_DRDY       = 0x4  // Bit DRDY.
	SERCOM_I2CS_INTENSET_ERROR_Pos  = 0x7  // Position of ERROR field.
	SERCOM_I2CS_INTENSET_ERROR_Msk  = 0x80 // Bit mask of ERROR field.
	SERCOM_I2CS_INTENSET_ERROR      = 0x80 // Bit ERROR.

	// INTFLAG: I2CS Interrupt Flag Status and Clear
	SERCOM_I2CS_INTFLAG_PREC_Pos   = 0x0  // Position of PREC field.
	SERCOM_I2CS_INTFLAG_PREC_Msk   = 0x1  // Bit mask of PREC field.
	SERCOM_I2CS_INTFLAG_PREC       = 0x1  // Bit PREC.
	SERCOM_I2CS_INTFLAG_AMATCH_Pos = 0x1  // Position of AMATCH field.
	SERCOM_I2CS_INTFLAG_AMATCH_Msk = 0x2  // Bit mask of AMATCH field.
	SERCOM_I2CS_INTFLAG_AMATCH     = 0x2  // Bit AMATCH.
	SERCOM_I2CS_INTFLAG_DRDY_Pos   = 0x2  // Position of DRDY field.
	SERCOM_I2CS_INTFLAG_DRDY_Msk   = 0x4  // Bit mask of DRDY field.
	SERCOM_I2CS_INTFLAG_DRDY       = 0x4  // Bit DRDY.
	SERCOM_I2CS_INTFLAG_ERROR_Pos  = 0x7  // Position of ERROR field.
	SERCOM_I2CS_INTFLAG_ERROR_Msk  = 0x80 // Bit mask of ERROR field.
	SERCOM_I2CS_INTFLAG_ERROR      = 0x80 // Bit ERROR.

	// STATUS: I2CS Status
	SERCOM_I2CS_STATUS_BUSERR_Pos   = 0x0   // Position of BUSERR field.
	SERCOM_I2CS_STATUS_BUSERR_Msk   = 0x1   // Bit mask of BUSERR field.
	SERCOM_I2CS_STATUS_BUSERR       = 0x1   // Bit BUSERR.
	SERCOM_I2CS_STATUS_COLL_Pos     = 0x1   // Position of COLL field.
	SERCOM_I2CS_STATUS_COLL_Msk     = 0x2   // Bit mask of COLL field.
	SERCOM_I2CS_STATUS_COLL         = 0x2   // Bit COLL.
	SERCOM_I2CS_STATUS_RXNACK_Pos   = 0x2   // Position of RXNACK field.
	SERCOM_I2CS_STATUS_RXNACK_Msk   = 0x4   // Bit mask of RXNACK field.
	SERCOM_I2CS_STATUS_RXNACK       = 0x4   // Bit RXNACK.
	SERCOM_I2CS_STATUS_DIR_Pos      = 0x3   // Position of DIR field.
	SERCOM_I2CS_STATUS_DIR_Msk      = 0x8   // Bit mask of DIR field.
	SERCOM_I2CS_STATUS_DIR          = 0x8   // Bit DIR.
	SERCOM_I2CS_STATUS_SR_Pos       = 0x4   // Position of SR field.
	SERCOM_I2CS_STATUS_SR_Msk       = 0x10  // Bit mask of SR field.
	SERCOM_I2CS_STATUS_SR           = 0x10  // Bit SR.
	SERCOM_I2CS_STATUS_LOWTOUT_Pos  = 0x6   // Position of LOWTOUT field.
	SERCOM_I2CS_STATUS_LOWTOUT_Msk  = 0x40  // Bit mask of LOWTOUT field.
	SERCOM_I2CS_STATUS_LOWTOUT      = 0x40  // Bit LOWTOUT.
	SERCOM_I2CS_STATUS_CLKHOLD_Pos  = 0x7   // Position of CLKHOLD field.
	SERCOM_I2CS_STATUS_CLKHOLD_Msk  = 0x80  // Bit mask of CLKHOLD field.
	SERCOM_I2CS_STATUS_CLKHOLD      = 0x80  // Bit CLKHOLD.
	SERCOM_I2CS_STATUS_SEXTTOUT_Pos = 0x9   // Position of SEXTTOUT field.
	SERCOM_I2CS_STATUS_SEXTTOUT_Msk = 0x200 // Bit mask of SEXTTOUT field.
	SERCOM_I2CS_STATUS_SEXTTOUT     = 0x200 // Bit SEXTTOUT.
	SERCOM_I2CS_STATUS_HS_Pos       = 0xa   // Position of HS field.
	SERCOM_I2CS_STATUS_HS_Msk       = 0x400 // Bit mask of HS field.
	SERCOM_I2CS_STATUS_HS           = 0x400 // Bit HS.
	SERCOM_I2CS_STATUS_LENERR_Pos   = 0xb   // Position of LENERR field.
	SERCOM_I2CS_STATUS_LENERR_Msk   = 0x800 // Bit mask of LENERR field.
	SERCOM_I2CS_STATUS_LENERR       = 0x800 // Bit LENERR.

	// SYNCBUSY: I2CS Synchronization Busy
	SERCOM_I2CS_SYNCBUSY_SWRST_Pos  = 0x0  // Position of SWRST field.
	SERCOM_I2CS_SYNCBUSY_SWRST_Msk  = 0x1  // Bit mask of SWRST field.
	SERCOM_I2CS_SYNCBUSY_SWRST      = 0x1  // Bit SWRST.
	SERCOM_I2CS_SYNCBUSY_ENABLE_Pos = 0x1  // Position of ENABLE field.
	SERCOM_I2CS_SYNCBUSY_ENABLE_Msk = 0x2  // Bit mask of ENABLE field.
	SERCOM_I2CS_SYNCBUSY_ENABLE     = 0x2  // Bit ENABLE.
	SERCOM_I2CS_SYNCBUSY_LENGTH_Pos = 0x4  // Position of LENGTH field.
	SERCOM_I2CS_SYNCBUSY_LENGTH_Msk = 0x10 // Bit mask of LENGTH field.
	SERCOM_I2CS_SYNCBUSY_LENGTH     = 0x10 // Bit LENGTH.

	// LENGTH: I2CS Length
	SERCOM_I2CS_LENGTH_LEN_Pos   = 0x0   // Position of LEN field.
	SERCOM_I2CS_LENGTH_LEN_Msk   = 0xff  // Bit mask of LEN field.
	SERCOM_I2CS_LENGTH_LENEN_Pos = 0x8   // Position of LENEN field.
	SERCOM_I2CS_LENGTH_LENEN_Msk = 0x100 // Bit mask of LENEN field.
	SERCOM_I2CS_LENGTH_LENEN     = 0x100 // Bit LENEN.

	// ADDR: I2CS Address
	SERCOM_I2CS_ADDR_GENCEN_Pos   = 0x0       // Position of GENCEN field.
	SERCOM_I2CS_ADDR_GENCEN_Msk   = 0x1       // Bit mask of GENCEN field.
	SERCOM_I2CS_ADDR_GENCEN       = 0x1       // Bit GENCEN.
	SERCOM_I2CS_ADDR_ADDR_Pos     = 0x1       // Position of ADDR field.
	SERCOM_I2CS_ADDR_ADDR_Msk     = 0x7fe     // Bit mask of ADDR field.
	SERCOM_I2CS_ADDR_TENBITEN_Pos = 0xf       // Position of TENBITEN field.
	SERCOM_I2CS_ADDR_TENBITEN_Msk = 0x8000    // Bit mask of TENBITEN field.
	SERCOM_I2CS_ADDR_TENBITEN     = 0x8000    // Bit TENBITEN.
	SERCOM_I2CS_ADDR_ADDRMASK_Pos = 0x11      // Position of ADDRMASK field.
	SERCOM_I2CS_ADDR_ADDRMASK_Msk = 0x7fe0000 // Bit mask of ADDRMASK field.

	// DATA: I2CS Data
	SERCOM_I2CS_DATA_DATA_Pos = 0x0        // Position of DATA field.
	SERCOM_I2CS_DATA_DATA_Msk = 0xffffffff // Bit mask of DATA field.
)

// Bitfields for SERCOM0_SPIS: Serial Communication Interface - SPIS
const (
	// CTRLA: SPIS Control A
	SERCOM_SPIS_CTRLA_SWRST_Pos                = 0x0        // Position of SWRST field.
	SERCOM_SPIS_CTRLA_SWRST_Msk                = 0x1        // Bit mask of SWRST field.
	SERCOM_SPIS_CTRLA_SWRST                    = 0x1        // Bit SWRST.
	SERCOM_SPIS_CTRLA_ENABLE_Pos               = 0x1        // Position of ENABLE field.
	SERCOM_SPIS_CTRLA_ENABLE_Msk               = 0x2        // Bit mask of ENABLE field.
	SERCOM_SPIS_CTRLA_ENABLE                   = 0x2        // Bit ENABLE.
	SERCOM_SPIS_CTRLA_MODE_Pos                 = 0x2        // Position of MODE field.
	SERCOM_SPIS_CTRLA_MODE_Msk                 = 0x1c       // Bit mask of MODE field.
	SERCOM_SPIS_CTRLA_MODE_USART_EXT_CLK       = 0x0        // USART with external clock
	SERCOM_SPIS_CTRLA_MODE_USART_INT_CLK       = 0x1        // USART with internal clock
	SERCOM_SPIS_CTRLA_MODE_SPI_SLAVE           = 0x2        // SPI in slave operation
	SERCOM_SPIS_CTRLA_MODE_SPI_MASTER          = 0x3        // SPI in master operation
	SERCOM_SPIS_CTRLA_MODE_I2C_SLAVE           = 0x4        // I2C slave operation
	SERCOM_SPIS_CTRLA_MODE_I2C_MASTER          = 0x5        // I2C master operation
	SERCOM_SPIS_CTRLA_RUNSTDBY_Pos             = 0x7        // Position of RUNSTDBY field.
	SERCOM_SPIS_CTRLA_RUNSTDBY_Msk             = 0x80       // Bit mask of RUNSTDBY field.
	SERCOM_SPIS_CTRLA_RUNSTDBY                 = 0x80       // Bit RUNSTDBY.
	SERCOM_SPIS_CTRLA_IBON_Pos                 = 0x8        // Position of IBON field.
	SERCOM_SPIS_CTRLA_IBON_Msk                 = 0x100      // Bit mask of IBON field.
	SERCOM_SPIS_CTRLA_IBON                     = 0x100      // Bit IBON.
	SERCOM_SPIS_CTRLA_DOPO_Pos                 = 0x10       // Position of DOPO field.
	SERCOM_SPIS_CTRLA_DOPO_Msk                 = 0x30000    // Bit mask of DOPO field.
	SERCOM_SPIS_CTRLA_DOPO_PAD0                = 0x0        // DO on PAD[0], SCK on PAD[1] and SS on PAD[2]
	SERCOM_SPIS_CTRLA_DOPO_PAD2                = 0x2        // DO on PAD[3], SCK on PAD[1] and SS on PAD[2]
	SERCOM_SPIS_CTRLA_DIPO_Pos                 = 0x14       // Position of DIPO field.
	SERCOM_SPIS_CTRLA_DIPO_Msk                 = 0x300000   // Bit mask of DIPO field.
	SERCOM_SPIS_CTRLA_DIPO_PAD0                = 0x0        // SERCOM PAD[0] is used as data input
	SERCOM_SPIS_CTRLA_DIPO_PAD1                = 0x1        // SERCOM PAD[1] is used as data input
	SERCOM_SPIS_CTRLA_DIPO_PAD2                = 0x2        // SERCOM PAD[2] is used as data input
	SERCOM_SPIS_CTRLA_DIPO_PAD3                = 0x3        // SERCOM PAD[3] is used as data input
	SERCOM_SPIS_CTRLA_FORM_Pos                 = 0x18       // Position of FORM field.
	SERCOM_SPIS_CTRLA_FORM_Msk                 = 0xf000000  // Bit mask of FORM field.
	SERCOM_SPIS_CTRLA_FORM_SPI_FRAME           = 0x0        // SPI Frame
	SERCOM_SPIS_CTRLA_FORM_SPI_FRAME_WITH_ADDR = 0x2        // SPI Frame with Addr
	SERCOM_SPIS_CTRLA_CPHA_Pos                 = 0x1c       // Position of CPHA field.
	SERCOM_SPIS_CTRLA_CPHA_Msk                 = 0x10000000 // Bit mask of CPHA field.
	SERCOM_SPIS_CTRLA_CPHA                     = 0x10000000 // Bit CPHA.
	SERCOM_SPIS_CTRLA_CPHA_LEADING_EDGE        = 0x0        // The data is sampled on a leading SCK edge and changed on a trailing SCK edge
	SERCOM_SPIS_CTRLA_CPHA_TRAILING_EDGE       = 0x1        // The data is sampled on a trailing SCK edge and changed on a leading SCK edge
	SERCOM_SPIS_CTRLA_CPOL_Pos                 = 0x1d       // Position of CPOL field.
	SERCOM_SPIS_CTRLA_CPOL_Msk                 = 0x20000000 // Bit mask of CPOL field.
	SERCOM_SPIS_CTRLA_CPOL                     = 0x20000000 // Bit CPOL.
	SERCOM_SPIS_CTRLA_CPOL_IDLE_LOW            = 0x0        // SCK is low when idle
	SERCOM_SPIS_CTRLA_CPOL_IDLE_HIGH           = 0x1        // SCK is high when idle
	SERCOM_SPIS_CTRLA_DORD_Pos                 = 0x1e       // Position of DORD field.
	SERCOM_SPIS_CTRLA_DORD_Msk                 = 0x40000000 // Bit mask of DORD field.
	SERCOM_SPIS_CTRLA_DORD                     = 0x40000000 // Bit DORD.
	SERCOM_SPIS_CTRLA_DORD_MSB                 = 0x0        // MSB is transferred first
	SERCOM_SPIS_CTRLA_DORD_LSB                 = 0x1        // LSB is transferred first

	// CTRLB: SPIS Control B
	SERCOM_SPIS_CTRLB_CHSIZE_Pos        = 0x0     // Position of CHSIZE field.
	SERCOM_SPIS_CTRLB_CHSIZE_Msk        = 0x7     // Bit mask of CHSIZE field.
	SERCOM_SPIS_CTRLB_CHSIZE_8_BIT      = 0x0     // 8 bits
	SERCOM_SPIS_CTRLB_CHSIZE_9_BIT      = 0x1     // 9 bits
	SERCOM_SPIS_CTRLB_PLOADEN_Pos       = 0x6     // Position of PLOADEN field.
	SERCOM_SPIS_CTRLB_PLOADEN_Msk       = 0x40    // Bit mask of PLOADEN field.
	SERCOM_SPIS_CTRLB_PLOADEN           = 0x40    // Bit PLOADEN.
	SERCOM_SPIS_CTRLB_SSDE_Pos          = 0x9     // Position of SSDE field.
	SERCOM_SPIS_CTRLB_SSDE_Msk          = 0x200   // Bit mask of SSDE field.
	SERCOM_SPIS_CTRLB_SSDE              = 0x200   // Bit SSDE.
	SERCOM_SPIS_CTRLB_MSSEN_Pos         = 0xd     // Position of MSSEN field.
	SERCOM_SPIS_CTRLB_MSSEN_Msk         = 0x2000  // Bit mask of MSSEN field.
	SERCOM_SPIS_CTRLB_MSSEN             = 0x2000  // Bit MSSEN.
	SERCOM_SPIS_CTRLB_AMODE_Pos         = 0xe     // Position of AMODE field.
	SERCOM_SPIS_CTRLB_AMODE_Msk         = 0xc000  // Bit mask of AMODE field.
	SERCOM_SPIS_CTRLB_AMODE_MASK        = 0x0     // SPI Address mask
	SERCOM_SPIS_CTRLB_AMODE_2_ADDRESSES = 0x1     // Two unique Addressess
	SERCOM_SPIS_CTRLB_AMODE_RANGE       = 0x2     // Address Range
	SERCOM_SPIS_CTRLB_RXEN_Pos          = 0x11    // Position of RXEN field.
	SERCOM_SPIS_CTRLB_RXEN_Msk          = 0x20000 // Bit mask of RXEN field.
	SERCOM_SPIS_CTRLB_RXEN              = 0x20000 // Bit RXEN.

	// CTRLC: SPIS Control C
	SERCOM_SPIS_CTRLC_ICSPACE_Pos              = 0x0       // Position of ICSPACE field.
	SERCOM_SPIS_CTRLC_ICSPACE_Msk              = 0x3f      // Bit mask of ICSPACE field.
	SERCOM_SPIS_CTRLC_DATA32B_Pos              = 0x18      // Position of DATA32B field.
	SERCOM_SPIS_CTRLC_DATA32B_Msk              = 0x1000000 // Bit mask of DATA32B field.
	SERCOM_SPIS_CTRLC_DATA32B                  = 0x1000000 // Bit DATA32B.
	SERCOM_SPIS_CTRLC_DATA32B_DATA_TRANS_8BIT  = 0x0       // Transaction from and to DATA register are 8-bit
	SERCOM_SPIS_CTRLC_DATA32B_DATA_TRANS_32BIT = 0x1       // Transaction from and to DATA register are 32-bit

	// BAUD: SPIS Baud Rate
	SERCOM_SPIS_BAUD_BAUD_Pos = 0x0  // Position of BAUD field.
	SERCOM_SPIS_BAUD_BAUD_Msk = 0xff // Bit mask of BAUD field.

	// INTENCLR: SPIS Interrupt Enable Clear
	SERCOM_SPIS_INTENCLR_DRE_Pos   = 0x0  // Position of DRE field.
	SERCOM_SPIS_INTENCLR_DRE_Msk   = 0x1  // Bit mask of DRE field.
	SERCOM_SPIS_INTENCLR_DRE       = 0x1  // Bit DRE.
	SERCOM_SPIS_INTENCLR_TXC_Pos   = 0x1  // Position of TXC field.
	SERCOM_SPIS_INTENCLR_TXC_Msk   = 0x2  // Bit mask of TXC field.
	SERCOM_SPIS_INTENCLR_TXC       = 0x2  // Bit TXC.
	SERCOM_SPIS_INTENCLR_RXC_Pos   = 0x2  // Position of RXC field.
	SERCOM_SPIS_INTENCLR_RXC_Msk   = 0x4  // Bit mask of RXC field.
	SERCOM_SPIS_INTENCLR_RXC       = 0x4  // Bit RXC.
	SERCOM_SPIS_INTENCLR_SSL_Pos   = 0x3  // Position of SSL field.
	SERCOM_SPIS_INTENCLR_SSL_Msk   = 0x8  // Bit mask of SSL field.
	SERCOM_SPIS_INTENCLR_SSL       = 0x8  // Bit SSL.
	SERCOM_SPIS_INTENCLR_ERROR_Pos = 0x7  // Position of ERROR field.
	SERCOM_SPIS_INTENCLR_ERROR_Msk = 0x80 // Bit mask of ERROR field.
	SERCOM_SPIS_INTENCLR_ERROR     = 0x80 // Bit ERROR.

	// INTENSET: SPIS Interrupt Enable Set
	SERCOM_SPIS_INTENSET_DRE_Pos   = 0x0  // Position of DRE field.
	SERCOM_SPIS_INTENSET_DRE_Msk   = 0x1  // Bit mask of DRE field.
	SERCOM_SPIS_INTENSET_DRE       = 0x1  // Bit DRE.
	SERCOM_SPIS_INTENSET_TXC_Pos   = 0x1  // Position of TXC field.
	SERCOM_SPIS_INTENSET_TXC_Msk   = 0x2  // Bit mask of TXC field.
	SERCOM_SPIS_INTENSET_TXC       = 0x2  // Bit TXC.
	SERCOM_SPIS_INTENSET_RXC_Pos   = 0x2  // Position of RXC field.
	SERCOM_SPIS_INTENSET_RXC_Msk   = 0x4  // Bit mask of RXC field.
	SERCOM_SPIS_INTENSET_RXC       = 0x4  // Bit RXC.
	SERCOM_SPIS_INTENSET_SSL_Pos   = 0x3  // Position of SSL field.
	SERCOM_SPIS_INTENSET_SSL_Msk   = 0x8  // Bit mask of SSL field.
	SERCOM_SPIS_INTENSET_SSL       = 0x8  // Bit SSL.
	SERCOM_SPIS_INTENSET_ERROR_Pos = 0x7  // Position of ERROR field.
	SERCOM_SPIS_INTENSET_ERROR_Msk = 0x80 // Bit mask of ERROR field.
	SERCOM_SPIS_INTENSET_ERROR     = 0x80 // Bit ERROR.

	// INTFLAG: SPIS Interrupt Flag Status and Clear
	SERCOM_SPIS_INTFLAG_DRE_Pos   = 0x0  // Position of DRE field.
	SERCOM_SPIS_INTFLAG_DRE_Msk   = 0x1  // Bit mask of DRE field.
	SERCOM_SPIS_INTFLAG_DRE       = 0x1  // Bit DRE.
	SERCOM_SPIS_INTFLAG_TXC_Pos   = 0x1  // Position of TXC field.
	SERCOM_SPIS_INTFLAG_TXC_Msk   = 0x2  // Bit mask of TXC field.
	SERCOM_SPIS_INTFLAG_TXC       = 0x2  // Bit TXC.
	SERCOM_SPIS_INTFLAG_RXC_Pos   = 0x2  // Position of RXC field.
	SERCOM_SPIS_INTFLAG_RXC_Msk   = 0x4  // Bit mask of RXC field.
	SERCOM_SPIS_INTFLAG_RXC       = 0x4  // Bit RXC.
	SERCOM_SPIS_INTFLAG_SSL_Pos   = 0x3  // Position of SSL field.
	SERCOM_SPIS_INTFLAG_SSL_Msk   = 0x8  // Bit mask of SSL field.
	SERCOM_SPIS_INTFLAG_SSL       = 0x8  // Bit SSL.
	SERCOM_SPIS_INTFLAG_ERROR_Pos = 0x7  // Position of ERROR field.
	SERCOM_SPIS_INTFLAG_ERROR_Msk = 0x80 // Bit mask of ERROR field.
	SERCOM_SPIS_INTFLAG_ERROR     = 0x80 // Bit ERROR.

	// STATUS: SPIS Status
	SERCOM_SPIS_STATUS_BUFOVF_Pos = 0x2   // Position of BUFOVF field.
	SERCOM_SPIS_STATUS_BUFOVF_Msk = 0x4   // Bit mask of BUFOVF field.
	SERCOM_SPIS_STATUS_BUFOVF     = 0x4   // Bit BUFOVF.
	SERCOM_SPIS_STATUS_LENERR_Pos = 0xb   // Position of LENERR field.
	SERCOM_SPIS_STATUS_LENERR_Msk = 0x800 // Bit mask of LENERR field.
	SERCOM_SPIS_STATUS_LENERR     = 0x800 // Bit LENERR.

	// SYNCBUSY: SPIS Synchronization Busy
	SERCOM_SPIS_SYNCBUSY_SWRST_Pos  = 0x0  // Position of SWRST field.
	SERCOM_SPIS_SYNCBUSY_SWRST_Msk  = 0x1  // Bit mask of SWRST field.
	SERCOM_SPIS_SYNCBUSY_SWRST      = 0x1  // Bit SWRST.
	SERCOM_SPIS_SYNCBUSY_ENABLE_Pos = 0x1  // Position of ENABLE field.
	SERCOM_SPIS_SYNCBUSY_ENABLE_Msk = 0x2  // Bit mask of ENABLE field.
	SERCOM_SPIS_SYNCBUSY_ENABLE     = 0x2  // Bit ENABLE.
	SERCOM_SPIS_SYNCBUSY_CTRLB_Pos  = 0x2  // Position of CTRLB field.
	SERCOM_SPIS_SYNCBUSY_CTRLB_Msk  = 0x4  // Bit mask of CTRLB field.
	SERCOM_SPIS_SYNCBUSY_CTRLB      = 0x4  // Bit CTRLB.
	SERCOM_SPIS_SYNCBUSY_LENGTH_Pos = 0x4  // Position of LENGTH field.
	SERCOM_SPIS_SYNCBUSY_LENGTH_Msk = 0x10 // Bit mask of LENGTH field.
	SERCOM_SPIS_SYNCBUSY_LENGTH     = 0x10 // Bit LENGTH.

	// LENGTH: SPIS Length
	SERCOM_SPIS_LENGTH_LEN_Pos   = 0x0   // Position of LEN field.
	SERCOM_SPIS_LENGTH_LEN_Msk   = 0xff  // Bit mask of LEN field.
	SERCOM_SPIS_LENGTH_LENEN_Pos = 0x8   // Position of LENEN field.
	SERCOM_SPIS_LENGTH_LENEN_Msk = 0x100 // Bit mask of LENEN field.
	SERCOM_SPIS_LENGTH_LENEN     = 0x100 // Bit LENEN.

	// ADDR: SPIS Address
	SERCOM_SPIS_ADDR_ADDR_Pos     = 0x0      // Position of ADDR field.
	SERCOM_SPIS_ADDR_ADDR_Msk     = 0xff     // Bit mask of ADDR field.
	SERCOM_SPIS_ADDR_ADDRMASK_Pos = 0x10     // Position of ADDRMASK field.
	SERCOM_SPIS_ADDR_ADDRMASK_Msk = 0xff0000 // Bit mask of ADDRMASK field.

	// DATA: SPIS Data
	SERCOM_SPIS_DATA_DATA_Pos = 0x0        // Position of DATA field.
	SERCOM_SPIS_DATA_DATA_Msk = 0xffffffff // Bit mask of DATA field.

	// DBGCTRL: SPIS Debug Control
	SERCOM_SPIS_DBGCTRL_DBGSTOP_Pos = 0x0 // Position of DBGSTOP field.
	SERCOM_SPIS_DBGCTRL_DBGSTOP_Msk = 0x1 // Bit mask of DBGSTOP field.
	SERCOM_SPIS_DBGCTRL_DBGSTOP     = 0x1 // Bit DBGSTOP.
)

// Bitfields for SERCOM0_SPIM: Serial Communication Interface - SPIM
const (
	// CTRLA: SPIM Control A
	SERCOM_SPIM_CTRLA_SWRST_Pos                = 0x0        // Position of SWRST field.
	SERCOM_SPIM_CTRLA_SWRST_Msk                = 0x1        // Bit mask of SWRST field.
	SERCOM_SPIM_CTRLA_SWRST                    = 0x1        // Bit SWRST.
	SERCOM_SPIM_CTRLA_ENABLE_Pos               = 0x1        // Position of ENABLE field.
	SERCOM_SPIM_CTRLA_ENABLE_Msk               = 0x2        // Bit mask of ENABLE field.
	SERCOM_SPIM_CTRLA_ENABLE                   = 0x2        // Bit ENABLE.
	SERCOM_SPIM_CTRLA_MODE_Pos                 = 0x2        // Position of MODE field.
	SERCOM_SPIM_CTRLA_MODE_Msk                 = 0x1c       // Bit mask of MODE field.
	SERCOM_SPIM_CTRLA_MODE_USART_EXT_CLK       = 0x0        // USART with external clock
	SERCOM_SPIM_CTRLA_MODE_USART_INT_CLK       = 0x1        // USART with internal clock
	SERCOM_SPIM_CTRLA_MODE_SPI_SLAVE           = 0x2        // SPI in slave operation
	SERCOM_SPIM_CTRLA_MODE_SPI_MASTER          = 0x3        // SPI in master operation
	SERCOM_SPIM_CTRLA_MODE_I2C_SLAVE           = 0x4        // I2C slave operation
	SERCOM_SPIM_CTRLA_MODE_I2C_MASTER          = 0x5        // I2C master operation
	SERCOM_SPIM_CTRLA_RUNSTDBY_Pos             = 0x7        // Position of RUNSTDBY field.
	SERCOM_SPIM_CTRLA_RUNSTDBY_Msk             = 0x80       // Bit mask of RUNSTDBY field.
	SERCOM_SPIM_CTRLA_RUNSTDBY                 = 0x80       // Bit RUNSTDBY.
	SERCOM_SPIM_CTRLA_IBON_Pos                 = 0x8        // Position of IBON field.
	SERCOM_SPIM_CTRLA_IBON_Msk                 = 0x100      // Bit mask of IBON field.
	SERCOM_SPIM_CTRLA_IBON                     = 0x100      // Bit IBON.
	SERCOM_SPIM_CTRLA_DOPO_Pos                 = 0x10       // Position of DOPO field.
	SERCOM_SPIM_CTRLA_DOPO_Msk                 = 0x30000    // Bit mask of DOPO field.
	SERCOM_SPIM_CTRLA_DOPO_PAD0                = 0x0        // DO on PAD[0], SCK on PAD[1] and SS on PAD[2]
	SERCOM_SPIM_CTRLA_DOPO_PAD2                = 0x2        // DO on PAD[3], SCK on PAD[1] and SS on PAD[2]
	SERCOM_SPIM_CTRLA_DIPO_Pos                 = 0x14       // Position of DIPO field.
	SERCOM_SPIM_CTRLA_DIPO_Msk                 = 0x300000   // Bit mask of DIPO field.
	SERCOM_SPIM_CTRLA_DIPO_PAD0                = 0x0        // SERCOM PAD[0] is used as data input
	SERCOM_SPIM_CTRLA_DIPO_PAD1                = 0x1        // SERCOM PAD[1] is used as data input
	SERCOM_SPIM_CTRLA_DIPO_PAD2                = 0x2        // SERCOM PAD[2] is used as data input
	SERCOM_SPIM_CTRLA_DIPO_PAD3                = 0x3        // SERCOM PAD[3] is used as data input
	SERCOM_SPIM_CTRLA_FORM_Pos                 = 0x18       // Position of FORM field.
	SERCOM_SPIM_CTRLA_FORM_Msk                 = 0xf000000  // Bit mask of FORM field.
	SERCOM_SPIM_CTRLA_FORM_SPI_FRAME           = 0x0        // SPI Frame
	SERCOM_SPIM_CTRLA_FORM_SPI_FRAME_WITH_ADDR = 0x2        // SPI Frame with Addr
	SERCOM_SPIM_CTRLA_CPHA_Pos                 = 0x1c       // Position of CPHA field.
	SERCOM_SPIM_CTRLA_CPHA_Msk                 = 0x10000000 // Bit mask of CPHA field.
	SERCOM_SPIM_CTRLA_CPHA                     = 0x10000000 // Bit CPHA.
	SERCOM_SPIM_CTRLA_CPHA_LEADING_EDGE        = 0x0        // The data is sampled on a leading SCK edge and changed on a trailing SCK edge
	SERCOM_SPIM_CTRLA_CPHA_TRAILING_EDGE       = 0x1        // The data is sampled on a trailing SCK edge and changed on a leading SCK edge
	SERCOM_SPIM_CTRLA_CPOL_Pos                 = 0x1d       // Position of CPOL field.
	SERCOM_SPIM_CTRLA_CPOL_Msk                 = 0x20000000 // Bit mask of CPOL field.
	SERCOM_SPIM_CTRLA_CPOL                     = 0x20000000 // Bit CPOL.
	SERCOM_SPIM_CTRLA_CPOL_IDLE_LOW            = 0x0        // SCK is low when idle
	SERCOM_SPIM_CTRLA_CPOL_IDLE_HIGH           = 0x1        // SCK is high when idle
	SERCOM_SPIM_CTRLA_DORD_Pos                 = 0x1e       // Position of DORD field.
	SERCOM_SPIM_CTRLA_DORD_Msk                 = 0x40000000 // Bit mask of DORD field.
	SERCOM_SPIM_CTRLA_DORD                     = 0x40000000 // Bit DORD.
	SERCOM_SPIM_CTRLA_DORD_MSB                 = 0x0        // MSB is transferred first
	SERCOM_SPIM_CTRLA_DORD_LSB                 = 0x1        // LSB is transferred first

	// CTRLB: SPIM Control B
	SERCOM_SPIM_CTRLB_CHSIZE_Pos        = 0x0     // Position of CHSIZE field.
	SERCOM_SPIM_CTRLB_CHSIZE_Msk        = 0x7     // Bit mask of CHSIZE field.
	SERCOM_SPIM_CTRLB_CHSIZE_8_BIT      = 0x0     // 8 bits
	SERCOM_SPIM_CTRLB_CHSIZE_9_BIT      = 0x1     // 9 bits
	SERCOM_SPIM_CTRLB_PLOADEN_Pos       = 0x6     // Position of PLOADEN field.
	SERCOM_SPIM_CTRLB_PLOADEN_Msk       = 0x40    // Bit mask of PLOADEN field.
	SERCOM_SPIM_CTRLB_PLOADEN           = 0x40    // Bit PLOADEN.
	SERCOM_SPIM_CTRLB_SSDE_Pos          = 0x9     // Position of SSDE field.
	SERCOM_SPIM_CTRLB_SSDE_Msk          = 0x200   // Bit mask of SSDE field.
	SERCOM_SPIM_CTRLB_SSDE              = 0x200   // Bit SSDE.
	SERCOM_SPIM_CTRLB_MSSEN_Pos         = 0xd     // Position of MSSEN field.
	SERCOM_SPIM_CTRLB_MSSEN_Msk         = 0x2000  // Bit mask of MSSEN field.
	SERCOM_SPIM_CTRLB_MSSEN             = 0x2000  // Bit MSSEN.
	SERCOM_SPIM_CTRLB_AMODE_Pos         = 0xe     // Position of AMODE field.
	SERCOM_SPIM_CTRLB_AMODE_Msk         = 0xc000  // Bit mask of AMODE field.
	SERCOM_SPIM_CTRLB_AMODE_MASK        = 0x0     // SPI Address mask
	SERCOM_SPIM_CTRLB_AMODE_2_ADDRESSES = 0x1     // Two unique Addressess
	SERCOM_SPIM_CTRLB_AMODE_RANGE       = 0x2     // Address Range
	SERCOM_SPIM_CTRLB_RXEN_Pos          = 0x11    // Position of RXEN field.
	SERCOM_SPIM_CTRLB_RXEN_Msk          = 0x20000 // Bit mask of RXEN field.
	SERCOM_SPIM_CTRLB_RXEN              = 0x20000 // Bit RXEN.

	// CTRLC: SPIM Control C
	SERCOM_SPIM_CTRLC_ICSPACE_Pos              = 0x0       // Position of ICSPACE field.
	SERCOM_SPIM_CTRLC_ICSPACE_Msk              = 0x3f      // Bit mask of ICSPACE field.
	SERCOM_SPIM_CTRLC_DATA32B_Pos              = 0x18      // Position of DATA32B field.
	SERCOM_SPIM_CTRLC_DATA32B_Msk              = 0x1000000 // Bit mask of DATA32B field.
	SERCOM_SPIM_CTRLC_DATA32B                  = 0x1000000 // Bit DATA32B.
	SERCOM_SPIM_CTRLC_DATA32B_DATA_TRANS_8BIT  = 0x0       // Transaction from and to DATA register are 8-bit
	SERCOM_SPIM_CTRLC_DATA32B_DATA_TRANS_32BIT = 0x1       // Transaction from and to DATA register are 32-bit

	// BAUD: SPIM Baud Rate
	SERCOM_SPIM_BAUD_BAUD_Pos = 0x0  // Position of BAUD field.
	SERCOM_SPIM_BAUD_BAUD_Msk = 0xff // Bit mask of BAUD field.

	// INTENCLR: SPIM Interrupt Enable Clear
	SERCOM_SPIM_INTENCLR_DRE_Pos   = 0x0  // Position of DRE field.
	SERCOM_SPIM_INTENCLR_DRE_Msk   = 0x1  // Bit mask of DRE field.
	SERCOM_SPIM_INTENCLR_DRE       = 0x1  // Bit DRE.
	SERCOM_SPIM_INTENCLR_TXC_Pos   = 0x1  // Position of TXC field.
	SERCOM_SPIM_INTENCLR_TXC_Msk   = 0x2  // Bit mask of TXC field.
	SERCOM_SPIM_INTENCLR_TXC       = 0x2  // Bit TXC.
	SERCOM_SPIM_INTENCLR_RXC_Pos   = 0x2  // Position of RXC field.
	SERCOM_SPIM_INTENCLR_RXC_Msk   = 0x4  // Bit mask of RXC field.
	SERCOM_SPIM_INTENCLR_RXC       = 0x4  // Bit RXC.
	SERCOM_SPIM_INTENCLR_SSL_Pos   = 0x3  // Position of SSL field.
	SERCOM_SPIM_INTENCLR_SSL_Msk   = 0x8  // Bit mask of SSL field.
	SERCOM_SPIM_INTENCLR_SSL       = 0x8  // Bit SSL.
	SERCOM_SPIM_INTENCLR_ERROR_Pos = 0x7  // Position of ERROR field.
	SERCOM_SPIM_INTENCLR_ERROR_Msk = 0x80 // Bit mask of ERROR field.
	SERCOM_SPIM_INTENCLR_ERROR     = 0x80 // Bit ERROR.

	// INTENSET: SPIM Interrupt Enable Set
	SERCOM_SPIM_INTENSET_DRE_Pos   = 0x0  // Position of DRE field.
	SERCOM_SPIM_INTENSET_DRE_Msk   = 0x1  // Bit mask of DRE field.
	SERCOM_SPIM_INTENSET_DRE       = 0x1  // Bit DRE.
	SERCOM_SPIM_INTENSET_TXC_Pos   = 0x1  // Position of TXC field.
	SERCOM_SPIM_INTENSET_TXC_Msk   = 0x2  // Bit mask of TXC field.
	SERCOM_SPIM_INTENSET_TXC       = 0x2  // Bit TXC.
	SERCOM_SPIM_INTENSET_RXC_Pos   = 0x2  // Position of RXC field.
	SERCOM_SPIM_INTENSET_RXC_Msk   = 0x4  // Bit mask of RXC field.
	SERCOM_SPIM_INTENSET_RXC       = 0x4  // Bit RXC.
	SERCOM_SPIM_INTENSET_SSL_Pos   = 0x3  // Position of SSL field.
	SERCOM_SPIM_INTENSET_SSL_Msk   = 0x8  // Bit mask of SSL field.
	SERCOM_SPIM_INTENSET_SSL       = 0x8  // Bit SSL.
	SERCOM_SPIM_INTENSET_ERROR_Pos = 0x7  // Position of ERROR field.
	SERCOM_SPIM_INTENSET_ERROR_Msk = 0x80 // Bit mask of ERROR field.
	SERCOM_SPIM_INTENSET_ERROR     = 0x80 // Bit ERROR.

	// INTFLAG: SPIM Interrupt Flag Status and Clear
	SERCOM_SPIM_INTFLAG_DRE_Pos   = 0x0  // Position of DRE field.
	SERCOM_SPIM_INTFLAG_DRE_Msk   = 0x1  // Bit mask of DRE field.
	SERCOM_SPIM_INTFLAG_DRE       = 0x1  // Bit DRE.
	SERCOM_SPIM_INTFLAG_TXC_Pos   = 0x1  // Position of TXC field.
	SERCOM_SPIM_INTFLAG_TXC_Msk   = 0x2  // Bit mask of TXC field.
	SERCOM_SPIM_INTFLAG_TXC       = 0x2  // Bit TXC.
	SERCOM_SPIM_INTFLAG_RXC_Pos   = 0x2  // Position of RXC field.
	SERCOM_SPIM_INTFLAG_RXC_Msk   = 0x4  // Bit mask of RXC field.
	SERCOM_SPIM_INTFLAG_RXC       = 0x4  // Bit RXC.
	SERCOM_SPIM_INTFLAG_SSL_Pos   = 0x3  // Position of SSL field.
	SERCOM_SPIM_INTFLAG_SSL_Msk   = 0x8  // Bit mask of SSL field.
	SERCOM_SPIM_INTFLAG_SSL       = 0x8  // Bit SSL.
	SERCOM_SPIM_INTFLAG_ERROR_Pos = 0x7  // Position of ERROR field.
	SERCOM_SPIM_INTFLAG_ERROR_Msk = 0x80 // Bit mask of ERROR field.
	SERCOM_SPIM_INTFLAG_ERROR     = 0x80 // Bit ERROR.

	// STATUS: SPIM Status
	SERCOM_SPIM_STATUS_BUFOVF_Pos = 0x2   // Position of BUFOVF field.
	SERCOM_SPIM_STATUS_BUFOVF_Msk = 0x4   // Bit mask of BUFOVF field.
	SERCOM_SPIM_STATUS_BUFOVF     = 0x4   // Bit BUFOVF.
	SERCOM_SPIM_STATUS_LENERR_Pos = 0xb   // Position of LENERR field.
	SERCOM_SPIM_STATUS_LENERR_Msk = 0x800 // Bit mask of LENERR field.
	SERCOM_SPIM_STATUS_LENERR     = 0x800 // Bit LENERR.

	// SYNCBUSY: SPIM Synchronization Busy
	SERCOM_SPIM_SYNCBUSY_SWRST_Pos  = 0x0  // Position of SWRST field.
	SERCOM_SPIM_SYNCBUSY_SWRST_Msk  = 0x1  // Bit mask of SWRST field.
	SERCOM_SPIM_SYNCBUSY_SWRST      = 0x1  // Bit SWRST.
	SERCOM_SPIM_SYNCBUSY_ENABLE_Pos = 0x1  // Position of ENABLE field.
	SERCOM_SPIM_SYNCBUSY_ENABLE_Msk = 0x2  // Bit mask of ENABLE field.
	SERCOM_SPIM_SYNCBUSY_ENABLE     = 0x2  // Bit ENABLE.
	SERCOM_SPIM_SYNCBUSY_CTRLB_Pos  = 0x2  // Position of CTRLB field.
	SERCOM_SPIM_SYNCBUSY_CTRLB_Msk  = 0x4  // Bit mask of CTRLB field.
	SERCOM_SPIM_SYNCBUSY_CTRLB      = 0x4  // Bit CTRLB.
	SERCOM_SPIM_SYNCBUSY_LENGTH_Pos = 0x4  // Position of LENGTH field.
	SERCOM_SPIM_SYNCBUSY_LENGTH_Msk = 0x10 // Bit mask of LENGTH field.
	SERCOM_SPIM_SYNCBUSY_LENGTH     = 0x10 // Bit LENGTH.

	// LENGTH: SPIM Length
	SERCOM_SPIM_LENGTH_LEN_Pos   = 0x0   // Position of LEN field.
	SERCOM_SPIM_LENGTH_LEN_Msk   = 0xff  // Bit mask of LEN field.
	SERCOM_SPIM_LENGTH_LENEN_Pos = 0x8   // Position of LENEN field.
	SERCOM_SPIM_LENGTH_LENEN_Msk = 0x100 // Bit mask of LENEN field.
	SERCOM_SPIM_LENGTH_LENEN     = 0x100 // Bit LENEN.

	// ADDR: SPIM Address
	SERCOM_SPIM_ADDR_ADDR_Pos     = 0x0      // Position of ADDR field.
	SERCOM_SPIM_ADDR_ADDR_Msk     = 0xff     // Bit mask of ADDR field.
	SERCOM_SPIM_ADDR_ADDRMASK_Pos = 0x10     // Position of ADDRMASK field.
	SERCOM_SPIM_ADDR_ADDRMASK_Msk = 0xff0000 // Bit mask of ADDRMASK field.

	// DATA: SPIM Data
	SERCOM_SPIM_DATA_DATA_Pos = 0x0        // Position of DATA field.
	SERCOM_SPIM_DATA_DATA_Msk = 0xffffffff // Bit mask of DATA field.

	// DBGCTRL: SPIM Debug Control
	SERCOM_SPIM_DBGCTRL_DBGSTOP_Pos = 0x0 // Position of DBGSTOP field.
	SERCOM_SPIM_DBGCTRL_DBGSTOP_Msk = 0x1 // Bit mask of DBGSTOP field.
	SERCOM_SPIM_DBGCTRL_DBGSTOP     = 0x1 // Bit DBGSTOP.
)

// Bitfields for SERCOM0_USART_EXT: Serial Communication Interface - USART_EXT
const (
	// CTRLA: USART_EXT Control A
	SERCOM_USART_EXT_CTRLA_SWRST_Pos                              = 0x0        // Position of SWRST field.
	SERCOM_USART_EXT_CTRLA_SWRST_Msk                              = 0x1        // Bit mask of SWRST field.
	SERCOM_USART_EXT_CTRLA_SWRST                                  = 0x1        // Bit SWRST.
	SERCOM_USART_EXT_CTRLA_ENABLE_Pos                             = 0x1        // Position of ENABLE field.
	SERCOM_USART_EXT_CTRLA_ENABLE_Msk                             = 0x2        // Bit mask of ENABLE field.
	SERCOM_USART_EXT_CTRLA_ENABLE                                 = 0x2        // Bit ENABLE.
	SERCOM_USART_EXT_CTRLA_MODE_Pos                               = 0x2        // Position of MODE field.
	SERCOM_USART_EXT_CTRLA_MODE_Msk                               = 0x1c       // Bit mask of MODE field.
	SERCOM_USART_EXT_CTRLA_MODE_USART_EXT_CLK                     = 0x0        // USART with external clock
	SERCOM_USART_EXT_CTRLA_MODE_USART_INT_CLK                     = 0x1        // USART with internal clock
	SERCOM_USART_EXT_CTRLA_MODE_SPI_SLAVE                         = 0x2        // SPI in slave operation
	SERCOM_USART_EXT_CTRLA_MODE_SPI_MASTER                        = 0x3        // SPI in master operation
	SERCOM_USART_EXT_CTRLA_MODE_I2C_SLAVE                         = 0x4        // I2C slave operation
	SERCOM_USART_EXT_CTRLA_MODE_I2C_MASTER                        = 0x5        // I2C master operation
	SERCOM_USART_EXT_CTRLA_RUNSTDBY_Pos                           = 0x7        // Position of RUNSTDBY field.
	SERCOM_USART_EXT_CTRLA_RUNSTDBY_Msk                           = 0x80       // Bit mask of RUNSTDBY field.
	SERCOM_USART_EXT_CTRLA_RUNSTDBY                               = 0x80       // Bit RUNSTDBY.
	SERCOM_USART_EXT_CTRLA_IBON_Pos                               = 0x8        // Position of IBON field.
	SERCOM_USART_EXT_CTRLA_IBON_Msk                               = 0x100      // Bit mask of IBON field.
	SERCOM_USART_EXT_CTRLA_IBON                                   = 0x100      // Bit IBON.
	SERCOM_USART_EXT_CTRLA_TXINV_Pos                              = 0x9        // Position of TXINV field.
	SERCOM_USART_EXT_CTRLA_TXINV_Msk                              = 0x200      // Bit mask of TXINV field.
	SERCOM_USART_EXT_CTRLA_TXINV                                  = 0x200      // Bit TXINV.
	SERCOM_USART_EXT_CTRLA_RXINV_Pos                              = 0xa        // Position of RXINV field.
	SERCOM_USART_EXT_CTRLA_RXINV_Msk                              = 0x400      // Bit mask of RXINV field.
	SERCOM_USART_EXT_CTRLA_RXINV                                  = 0x400      // Bit RXINV.
	SERCOM_USART_EXT_CTRLA_SAMPR_Pos                              = 0xd        // Position of SAMPR field.
	SERCOM_USART_EXT_CTRLA_SAMPR_Msk                              = 0xe000     // Bit mask of SAMPR field.
	SERCOM_USART_EXT_CTRLA_SAMPR_16X_ARITHMETIC                   = 0x0        // 16x over-sampling using arithmetic baudrate generation
	SERCOM_USART_EXT_CTRLA_SAMPR_16X_FRACTIONAL                   = 0x1        // 16x over-sampling using fractional baudrate generation
	SERCOM_USART_EXT_CTRLA_SAMPR_8X_ARITHMETIC                    = 0x2        // 8x over-sampling using arithmetic baudrate generation
	SERCOM_USART_EXT_CTRLA_SAMPR_8X_FRACTIONAL                    = 0x3        // 8x over-sampling using fractional baudrate generation
	SERCOM_USART_EXT_CTRLA_SAMPR_3X_ARITHMETIC                    = 0x4        // 3x over-sampling using arithmetic baudrate generation
	SERCOM_USART_EXT_CTRLA_TXPO_Pos                               = 0x10       // Position of TXPO field.
	SERCOM_USART_EXT_CTRLA_TXPO_Msk                               = 0x30000    // Bit mask of TXPO field.
	SERCOM_USART_EXT_CTRLA_TXPO_PAD0                              = 0x0        // SERCOM PAD[0] is used for data transmission
	SERCOM_USART_EXT_CTRLA_TXPO_PAD3                              = 0x3        // SERCOM_PAD[0] is used for data transmission
	SERCOM_USART_EXT_CTRLA_RXPO_Pos                               = 0x14       // Position of RXPO field.
	SERCOM_USART_EXT_CTRLA_RXPO_Msk                               = 0x300000   // Bit mask of RXPO field.
	SERCOM_USART_EXT_CTRLA_RXPO_PAD0                              = 0x0        // SERCOM PAD[0] is used for data reception
	SERCOM_USART_EXT_CTRLA_RXPO_PAD1                              = 0x1        // SERCOM PAD[1] is used for data reception
	SERCOM_USART_EXT_CTRLA_RXPO_PAD2                              = 0x2        // SERCOM PAD[2] is used for data reception
	SERCOM_USART_EXT_CTRLA_RXPO_PAD3                              = 0x3        // SERCOM PAD[3] is used for data reception
	SERCOM_USART_EXT_CTRLA_SAMPA_Pos                              = 0x16       // Position of SAMPA field.
	SERCOM_USART_EXT_CTRLA_SAMPA_Msk                              = 0xc00000   // Bit mask of SAMPA field.
	SERCOM_USART_EXT_CTRLA_FORM_Pos                               = 0x18       // Position of FORM field.
	SERCOM_USART_EXT_CTRLA_FORM_Msk                               = 0xf000000  // Bit mask of FORM field.
	SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_NO_PARITY             = 0x0        // USART frame
	SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_WITH_PARITY           = 0x1        // USART frame with parity
	SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_LIN_MASTER_MODE       = 0x2        // LIN Master - Break and sync generation
	SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_AUTO_BAUD_NO_PARITY   = 0x4        // Auto-baud - break detection and auto-baud
	SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_AUTO_BAUD_WITH_PARITY = 0x5        // Auto-baud - break detection and auto-baud with parity
	SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_ISO_7816              = 0x7        // ISO 7816
	SERCOM_USART_EXT_CTRLA_CMODE_Pos                              = 0x1c       // Position of CMODE field.
	SERCOM_USART_EXT_CTRLA_CMODE_Msk                              = 0x10000000 // Bit mask of CMODE field.
	SERCOM_USART_EXT_CTRLA_CMODE                                  = 0x10000000 // Bit CMODE.
	SERCOM_USART_EXT_CTRLA_CMODE_ASYNC                            = 0x0        // Asynchronous Communication
	SERCOM_USART_EXT_CTRLA_CMODE_SYNC                             = 0x1        // Synchronous Communication
	SERCOM_USART_EXT_CTRLA_CPOL_Pos                               = 0x1d       // Position of CPOL field.
	SERCOM_USART_EXT_CTRLA_CPOL_Msk                               = 0x20000000 // Bit mask of CPOL field.
	SERCOM_USART_EXT_CTRLA_CPOL                                   = 0x20000000 // Bit CPOL.
	SERCOM_USART_EXT_CTRLA_CPOL_IDLE_LOW                          = 0x0        // TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge
	SERCOM_USART_EXT_CTRLA_CPOL_IDLE_HIGH                         = 0x1        // TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge
	SERCOM_USART_EXT_CTRLA_DORD_Pos                               = 0x1e       // Position of DORD field.
	SERCOM_USART_EXT_CTRLA_DORD_Msk                               = 0x40000000 // Bit mask of DORD field.
	SERCOM_USART_EXT_CTRLA_DORD                                   = 0x40000000 // Bit DORD.
	SERCOM_USART_EXT_CTRLA_DORD_MSB                               = 0x0        // MSB is transmitted first
	SERCOM_USART_EXT_CTRLA_DORD_LSB                               = 0x1        // LSB is transmitted first

	// CTRLB: USART_EXT Control B
	SERCOM_USART_EXT_CTRLB_CHSIZE_Pos   = 0x0       // Position of CHSIZE field.
	SERCOM_USART_EXT_CTRLB_CHSIZE_Msk   = 0x7       // Bit mask of CHSIZE field.
	SERCOM_USART_EXT_CTRLB_CHSIZE_8_BIT = 0x0       // 8 Bits
	SERCOM_USART_EXT_CTRLB_CHSIZE_9_BIT = 0x1       // 9 Bits
	SERCOM_USART_EXT_CTRLB_CHSIZE_5_BIT = 0x5       // 5 Bits
	SERCOM_USART_EXT_CTRLB_CHSIZE_6_BIT = 0x6       // 6 Bits
	SERCOM_USART_EXT_CTRLB_CHSIZE_7_BIT = 0x7       // 7 Bits
	SERCOM_USART_EXT_CTRLB_SBMODE_Pos   = 0x6       // Position of SBMODE field.
	SERCOM_USART_EXT_CTRLB_SBMODE_Msk   = 0x40      // Bit mask of SBMODE field.
	SERCOM_USART_EXT_CTRLB_SBMODE       = 0x40      // Bit SBMODE.
	SERCOM_USART_EXT_CTRLB_SBMODE_1_BIT = 0x0       // One Stop Bit
	SERCOM_USART_EXT_CTRLB_SBMODE_2_BIT = 0x1       // Two Stop Bits
	SERCOM_USART_EXT_CTRLB_COLDEN_Pos   = 0x8       // Position of COLDEN field.
	SERCOM_USART_EXT_CTRLB_COLDEN_Msk   = 0x100     // Bit mask of COLDEN field.
	SERCOM_USART_EXT_CTRLB_COLDEN       = 0x100     // Bit COLDEN.
	SERCOM_USART_EXT_CTRLB_SFDE_Pos     = 0x9       // Position of SFDE field.
	SERCOM_USART_EXT_CTRLB_SFDE_Msk     = 0x200     // Bit mask of SFDE field.
	SERCOM_USART_EXT_CTRLB_SFDE         = 0x200     // Bit SFDE.
	SERCOM_USART_EXT_CTRLB_ENC_Pos      = 0xa       // Position of ENC field.
	SERCOM_USART_EXT_CTRLB_ENC_Msk      = 0x400     // Bit mask of ENC field.
	SERCOM_USART_EXT_CTRLB_ENC          = 0x400     // Bit ENC.
	SERCOM_USART_EXT_CTRLB_PMODE_Pos    = 0xd       // Position of PMODE field.
	SERCOM_USART_EXT_CTRLB_PMODE_Msk    = 0x2000    // Bit mask of PMODE field.
	SERCOM_USART_EXT_CTRLB_PMODE        = 0x2000    // Bit PMODE.
	SERCOM_USART_EXT_CTRLB_PMODE_EVEN   = 0x0       // Even Parity
	SERCOM_USART_EXT_CTRLB_PMODE_ODD    = 0x1       // Odd Parity
	SERCOM_USART_EXT_CTRLB_TXEN_Pos     = 0x10      // Position of TXEN field.
	SERCOM_USART_EXT_CTRLB_TXEN_Msk     = 0x10000   // Bit mask of TXEN field.
	SERCOM_USART_EXT_CTRLB_TXEN         = 0x10000   // Bit TXEN.
	SERCOM_USART_EXT_CTRLB_RXEN_Pos     = 0x11      // Position of RXEN field.
	SERCOM_USART_EXT_CTRLB_RXEN_Msk     = 0x20000   // Bit mask of RXEN field.
	SERCOM_USART_EXT_CTRLB_RXEN         = 0x20000   // Bit RXEN.
	SERCOM_USART_EXT_CTRLB_LINCMD_Pos   = 0x18      // Position of LINCMD field.
	SERCOM_USART_EXT_CTRLB_LINCMD_Msk   = 0x3000000 // Bit mask of LINCMD field.

	// CTRLC: USART_EXT Control C
	SERCOM_USART_EXT_CTRLC_GTIME_Pos                            = 0x0       // Position of GTIME field.
	SERCOM_USART_EXT_CTRLC_GTIME_Msk                            = 0x7       // Bit mask of GTIME field.
	SERCOM_USART_EXT_CTRLC_BRKLEN_Pos                           = 0x8       // Position of BRKLEN field.
	SERCOM_USART_EXT_CTRLC_BRKLEN_Msk                           = 0x300     // Bit mask of BRKLEN field.
	SERCOM_USART_EXT_CTRLC_HDRDLY_Pos                           = 0xa       // Position of HDRDLY field.
	SERCOM_USART_EXT_CTRLC_HDRDLY_Msk                           = 0xc00     // Bit mask of HDRDLY field.
	SERCOM_USART_EXT_CTRLC_INACK_Pos                            = 0x10      // Position of INACK field.
	SERCOM_USART_EXT_CTRLC_INACK_Msk                            = 0x10000   // Bit mask of INACK field.
	SERCOM_USART_EXT_CTRLC_INACK                                = 0x10000   // Bit INACK.
	SERCOM_USART_EXT_CTRLC_DSNACK_Pos                           = 0x11      // Position of DSNACK field.
	SERCOM_USART_EXT_CTRLC_DSNACK_Msk                           = 0x20000   // Bit mask of DSNACK field.
	SERCOM_USART_EXT_CTRLC_DSNACK                               = 0x20000   // Bit DSNACK.
	SERCOM_USART_EXT_CTRLC_MAXITER_Pos                          = 0x14      // Position of MAXITER field.
	SERCOM_USART_EXT_CTRLC_MAXITER_Msk                          = 0x700000  // Bit mask of MAXITER field.
	SERCOM_USART_EXT_CTRLC_DATA32B_Pos                          = 0x18      // Position of DATA32B field.
	SERCOM_USART_EXT_CTRLC_DATA32B_Msk                          = 0x3000000 // Bit mask of DATA32B field.
	SERCOM_USART_EXT_CTRLC_DATA32B_DATA_READ_WRITE_CHSIZE       = 0x0       // Data reads and writes according CTRLB.CHSIZE
	SERCOM_USART_EXT_CTRLC_DATA32B_DATA_READ_CHSIZE_WRITE_32BIT = 0x1       // Data reads according CTRLB.CHSIZE and writes according 32-bit extension
	SERCOM_USART_EXT_CTRLC_DATA32B_DATA_READ_32BIT_WRITE_CHSIZE = 0x2       // Data reads according 32-bit extension and writes according CTRLB.CHSIZE
	SERCOM_USART_EXT_CTRLC_DATA32B_DATA_READ_WRITE_32BIT        = 0x3       // Data reads and writes according 32-bit extension

	// BAUD: USART_EXT Baud Rate
	SERCOM_USART_EXT_BAUD_BAUD_Pos = 0x0    // Position of BAUD field.
	SERCOM_USART_EXT_BAUD_BAUD_Msk = 0xffff // Bit mask of BAUD field.

	// BAUD_FRAC_MODE: USART_EXT Baud Rate
	SERCOM_USART_EXT_BAUD_FRAC_MODE_BAUD_Pos = 0x0    // Position of BAUD field.
	SERCOM_USART_EXT_BAUD_FRAC_MODE_BAUD_Msk = 0x1fff // Bit mask of BAUD field.
	SERCOM_USART_EXT_BAUD_FRAC_MODE_FP_Pos   = 0xd    // Position of FP field.
	SERCOM_USART_EXT_BAUD_FRAC_MODE_FP_Msk   = 0xe000 // Bit mask of FP field.

	// BAUD_FRACFP_MODE: USART_EXT Baud Rate
	SERCOM_USART_EXT_BAUD_FRACFP_MODE_BAUD_Pos = 0x0    // Position of BAUD field.
	SERCOM_USART_EXT_BAUD_FRACFP_MODE_BAUD_Msk = 0x1fff // Bit mask of BAUD field.
	SERCOM_USART_EXT_BAUD_FRACFP_MODE_FP_Pos   = 0xd    // Position of FP field.
	SERCOM_USART_EXT_BAUD_FRACFP_MODE_FP_Msk   = 0xe000 // Bit mask of FP field.

	// BAUD_USARTFP_MODE: USART_EXT Baud Rate
	SERCOM_USART_EXT_BAUD_USARTFP_MODE_BAUD_Pos = 0x0    // Position of BAUD field.
	SERCOM_USART_EXT_BAUD_USARTFP_MODE_BAUD_Msk = 0xffff // Bit mask of BAUD field.

	// RXPL: USART_EXT Receive Pulse Length
	SERCOM_USART_EXT_RXPL_RXPL_Pos = 0x0  // Position of RXPL field.
	SERCOM_USART_EXT_RXPL_RXPL_Msk = 0xff // Bit mask of RXPL field.

	// INTENCLR: USART_EXT Interrupt Enable Clear
	SERCOM_USART_EXT_INTENCLR_DRE_Pos   = 0x0  // Position of DRE field.
	SERCOM_USART_EXT_INTENCLR_DRE_Msk   = 0x1  // Bit mask of DRE field.
	SERCOM_USART_EXT_INTENCLR_DRE       = 0x1  // Bit DRE.
	SERCOM_USART_EXT_INTENCLR_TXC_Pos   = 0x1  // Position of TXC field.
	SERCOM_USART_EXT_INTENCLR_TXC_Msk   = 0x2  // Bit mask of TXC field.
	SERCOM_USART_EXT_INTENCLR_TXC       = 0x2  // Bit TXC.
	SERCOM_USART_EXT_INTENCLR_RXC_Pos   = 0x2  // Position of RXC field.
	SERCOM_USART_EXT_INTENCLR_RXC_Msk   = 0x4  // Bit mask of RXC field.
	SERCOM_USART_EXT_INTENCLR_RXC       = 0x4  // Bit RXC.
	SERCOM_USART_EXT_INTENCLR_RXS_Pos   = 0x3  // Position of RXS field.
	SERCOM_USART_EXT_INTENCLR_RXS_Msk   = 0x8  // Bit mask of RXS field.
	SERCOM_USART_EXT_INTENCLR_RXS       = 0x8  // Bit RXS.
	SERCOM_USART_EXT_INTENCLR_CTSIC_Pos = 0x4  // Position of CTSIC field.
	SERCOM_USART_EXT_INTENCLR_CTSIC_Msk = 0x10 // Bit mask of CTSIC field.
	SERCOM_USART_EXT_INTENCLR_CTSIC     = 0x10 // Bit CTSIC.
	SERCOM_USART_EXT_INTENCLR_RXBRK_Pos = 0x5  // Position of RXBRK field.
	SERCOM_USART_EXT_INTENCLR_RXBRK_Msk = 0x20 // Bit mask of RXBRK field.
	SERCOM_USART_EXT_INTENCLR_RXBRK     = 0x20 // Bit RXBRK.
	SERCOM_USART_EXT_INTENCLR_ERROR_Pos = 0x7  // Position of ERROR field.
	SERCOM_USART_EXT_INTENCLR_ERROR_Msk = 0x80 // Bit mask of ERROR field.
	SERCOM_USART_EXT_INTENCLR_ERROR     = 0x80 // Bit ERROR.

	// INTENSET: USART_EXT Interrupt Enable Set
	SERCOM_USART_EXT_INTENSET_DRE_Pos   = 0x0  // Position of DRE field.
	SERCOM_USART_EXT_INTENSET_DRE_Msk   = 0x1  // Bit mask of DRE field.
	SERCOM_USART_EXT_INTENSET_DRE       = 0x1  // Bit DRE.
	SERCOM_USART_EXT_INTENSET_TXC_Pos   = 0x1  // Position of TXC field.
	SERCOM_USART_EXT_INTENSET_TXC_Msk   = 0x2  // Bit mask of TXC field.
	SERCOM_USART_EXT_INTENSET_TXC       = 0x2  // Bit TXC.
	SERCOM_USART_EXT_INTENSET_RXC_Pos   = 0x2  // Position of RXC field.
	SERCOM_USART_EXT_INTENSET_RXC_Msk   = 0x4  // Bit mask of RXC field.
	SERCOM_USART_EXT_INTENSET_RXC       = 0x4  // Bit RXC.
	SERCOM_USART_EXT_INTENSET_RXS_Pos   = 0x3  // Position of RXS field.
	SERCOM_USART_EXT_INTENSET_RXS_Msk   = 0x8  // Bit mask of RXS field.
	SERCOM_USART_EXT_INTENSET_RXS       = 0x8  // Bit RXS.
	SERCOM_USART_EXT_INTENSET_CTSIC_Pos = 0x4  // Position of CTSIC field.
	SERCOM_USART_EXT_INTENSET_CTSIC_Msk = 0x10 // Bit mask of CTSIC field.
	SERCOM_USART_EXT_INTENSET_CTSIC     = 0x10 // Bit CTSIC.
	SERCOM_USART_EXT_INTENSET_RXBRK_Pos = 0x5  // Position of RXBRK field.
	SERCOM_USART_EXT_INTENSET_RXBRK_Msk = 0x20 // Bit mask of RXBRK field.
	SERCOM_USART_EXT_INTENSET_RXBRK     = 0x20 // Bit RXBRK.
	SERCOM_USART_EXT_INTENSET_ERROR_Pos = 0x7  // Position of ERROR field.
	SERCOM_USART_EXT_INTENSET_ERROR_Msk = 0x80 // Bit mask of ERROR field.
	SERCOM_USART_EXT_INTENSET_ERROR     = 0x80 // Bit ERROR.

	// INTFLAG: USART_EXT Interrupt Flag Status and Clear
	SERCOM_USART_EXT_INTFLAG_DRE_Pos   = 0x0  // Position of DRE field.
	SERCOM_USART_EXT_INTFLAG_DRE_Msk   = 0x1  // Bit mask of DRE field.
	SERCOM_USART_EXT_INTFLAG_DRE       = 0x1  // Bit DRE.
	SERCOM_USART_EXT_INTFLAG_TXC_Pos   = 0x1  // Position of TXC field.
	SERCOM_USART_EXT_INTFLAG_TXC_Msk   = 0x2  // Bit mask of TXC field.
	SERCOM_USART_EXT_INTFLAG_TXC       = 0x2  // Bit TXC.
	SERCOM_USART_EXT_INTFLAG_RXC_Pos   = 0x2  // Position of RXC field.
	SERCOM_USART_EXT_INTFLAG_RXC_Msk   = 0x4  // Bit mask of RXC field.
	SERCOM_USART_EXT_INTFLAG_RXC       = 0x4  // Bit RXC.
	SERCOM_USART_EXT_INTFLAG_RXS_Pos   = 0x3  // Position of RXS field.
	SERCOM_USART_EXT_INTFLAG_RXS_Msk   = 0x8  // Bit mask of RXS field.
	SERCOM_USART_EXT_INTFLAG_RXS       = 0x8  // Bit RXS.
	SERCOM_USART_EXT_INTFLAG_CTSIC_Pos = 0x4  // Position of CTSIC field.
	SERCOM_USART_EXT_INTFLAG_CTSIC_Msk = 0x10 // Bit mask of CTSIC field.
	SERCOM_USART_EXT_INTFLAG_CTSIC     = 0x10 // Bit CTSIC.
	SERCOM_USART_EXT_INTFLAG_RXBRK_Pos = 0x5  // Position of RXBRK field.
	SERCOM_USART_EXT_INTFLAG_RXBRK_Msk = 0x20 // Bit mask of RXBRK field.
	SERCOM_USART_EXT_INTFLAG_RXBRK     = 0x20 // Bit RXBRK.
	SERCOM_USART_EXT_INTFLAG_ERROR_Pos = 0x7  // Position of ERROR field.
	SERCOM_USART_EXT_INTFLAG_ERROR_Msk = 0x80 // Bit mask of ERROR field.
	SERCOM_USART_EXT_INTFLAG_ERROR     = 0x80 // Bit ERROR.

	// STATUS: USART_EXT Status
	SERCOM_USART_EXT_STATUS_PERR_Pos   = 0x0  // Position of PERR field.
	SERCOM_USART_EXT_STATUS_PERR_Msk   = 0x1  // Bit mask of PERR field.
	SERCOM_USART_EXT_STATUS_PERR       = 0x1  // Bit PERR.
	SERCOM_USART_EXT_STATUS_FERR_Pos   = 0x1  // Position of FERR field.
	SERCOM_USART_EXT_STATUS_FERR_Msk   = 0x2  // Bit mask of FERR field.
	SERCOM_USART_EXT_STATUS_FERR       = 0x2  // Bit FERR.
	SERCOM_USART_EXT_STATUS_BUFOVF_Pos = 0x2  // Position of BUFOVF field.
	SERCOM_USART_EXT_STATUS_BUFOVF_Msk = 0x4  // Bit mask of BUFOVF field.
	SERCOM_USART_EXT_STATUS_BUFOVF     = 0x4  // Bit BUFOVF.
	SERCOM_USART_EXT_STATUS_CTS_Pos    = 0x3  // Position of CTS field.
	SERCOM_USART_EXT_STATUS_CTS_Msk    = 0x8  // Bit mask of CTS field.
	SERCOM_USART_EXT_STATUS_CTS        = 0x8  // Bit CTS.
	SERCOM_USART_EXT_STATUS_ISF_Pos    = 0x4  // Position of ISF field.
	SERCOM_USART_EXT_STATUS_ISF_Msk    = 0x10 // Bit mask of ISF field.
	SERCOM_USART_EXT_STATUS_ISF        = 0x10 // Bit ISF.
	SERCOM_USART_EXT_STATUS_COLL_Pos   = 0x5  // Position of COLL field.
	SERCOM_USART_EXT_STATUS_COLL_Msk   = 0x20 // Bit mask of COLL field.
	SERCOM_USART_EXT_STATUS_COLL       = 0x20 // Bit COLL.
	SERCOM_USART_EXT_STATUS_TXE_Pos    = 0x6  // Position of TXE field.
	SERCOM_USART_EXT_STATUS_TXE_Msk    = 0x40 // Bit mask of TXE field.
	SERCOM_USART_EXT_STATUS_TXE        = 0x40 // Bit TXE.
	SERCOM_USART_EXT_STATUS_ITER_Pos   = 0x7  // Position of ITER field.
	SERCOM_USART_EXT_STATUS_ITER_Msk   = 0x80 // Bit mask of ITER field.
	SERCOM_USART_EXT_STATUS_ITER       = 0x80 // Bit ITER.

	// SYNCBUSY: USART_EXT Synchronization Busy
	SERCOM_USART_EXT_SYNCBUSY_SWRST_Pos    = 0x0  // Position of SWRST field.
	SERCOM_USART_EXT_SYNCBUSY_SWRST_Msk    = 0x1  // Bit mask of SWRST field.
	SERCOM_USART_EXT_SYNCBUSY_SWRST        = 0x1  // Bit SWRST.
	SERCOM_USART_EXT_SYNCBUSY_ENABLE_Pos   = 0x1  // Position of ENABLE field.
	SERCOM_USART_EXT_SYNCBUSY_ENABLE_Msk   = 0x2  // Bit mask of ENABLE field.
	SERCOM_USART_EXT_SYNCBUSY_ENABLE       = 0x2  // Bit ENABLE.
	SERCOM_USART_EXT_SYNCBUSY_CTRLB_Pos    = 0x2  // Position of CTRLB field.
	SERCOM_USART_EXT_SYNCBUSY_CTRLB_Msk    = 0x4  // Bit mask of CTRLB field.
	SERCOM_USART_EXT_SYNCBUSY_CTRLB        = 0x4  // Bit CTRLB.
	SERCOM_USART_EXT_SYNCBUSY_RXERRCNT_Pos = 0x3  // Position of RXERRCNT field.
	SERCOM_USART_EXT_SYNCBUSY_RXERRCNT_Msk = 0x8  // Bit mask of RXERRCNT field.
	SERCOM_USART_EXT_SYNCBUSY_RXERRCNT     = 0x8  // Bit RXERRCNT.
	SERCOM_USART_EXT_SYNCBUSY_LENGTH_Pos   = 0x4  // Position of LENGTH field.
	SERCOM_USART_EXT_SYNCBUSY_LENGTH_Msk   = 0x10 // Bit mask of LENGTH field.
	SERCOM_USART_EXT_SYNCBUSY_LENGTH       = 0x10 // Bit LENGTH.

	// LENGTH: USART_EXT Length
	SERCOM_USART_EXT_LENGTH_LEN_Pos   = 0x0   // Position of LEN field.
	SERCOM_USART_EXT_LENGTH_LEN_Msk   = 0xff  // Bit mask of LEN field.
	SERCOM_USART_EXT_LENGTH_LENEN_Pos = 0x8   // Position of LENEN field.
	SERCOM_USART_EXT_LENGTH_LENEN_Msk = 0x300 // Bit mask of LENEN field.

	// DATA: USART_EXT Data
	SERCOM_USART_EXT_DATA_DATA_Pos = 0x0        // Position of DATA field.
	SERCOM_USART_EXT_DATA_DATA_Msk = 0xffffffff // Bit mask of DATA field.

	// DBGCTRL: USART_EXT Debug Control
	SERCOM_USART_EXT_DBGCTRL_DBGSTOP_Pos = 0x0 // Position of DBGSTOP field.
	SERCOM_USART_EXT_DBGCTRL_DBGSTOP_Msk = 0x1 // Bit mask of DBGSTOP field.
	SERCOM_USART_EXT_DBGCTRL_DBGSTOP     = 0x1 // Bit DBGSTOP.
)

// Bitfields for SERCOM0_USART_INT: Serial Communication Interface - USART_INT
const (
	// CTRLA: USART_INT Control A
	SERCOM_USART_INT_CTRLA_SWRST_Pos                              = 0x0        // Position of SWRST field.
	SERCOM_USART_INT_CTRLA_SWRST_Msk                              = 0x1        // Bit mask of SWRST field.
	SERCOM_USART_INT_CTRLA_SWRST                                  = 0x1        // Bit SWRST.
	SERCOM_USART_INT_CTRLA_ENABLE_Pos                             = 0x1        // Position of ENABLE field.
	SERCOM_USART_INT_CTRLA_ENABLE_Msk                             = 0x2        // Bit mask of ENABLE field.
	SERCOM_USART_INT_CTRLA_ENABLE                                 = 0x2        // Bit ENABLE.
	SERCOM_USART_INT_CTRLA_MODE_Pos                               = 0x2        // Position of MODE field.
	SERCOM_USART_INT_CTRLA_MODE_Msk                               = 0x1c       // Bit mask of MODE field.
	SERCOM_USART_INT_CTRLA_MODE_USART_EXT_CLK                     = 0x0        // USART with external clock
	SERCOM_USART_INT_CTRLA_MODE_USART_INT_CLK                     = 0x1        // USART with internal clock
	SERCOM_USART_INT_CTRLA_MODE_SPI_SLAVE                         = 0x2        // SPI in slave operation
	SERCOM_USART_INT_CTRLA_MODE_SPI_MASTER                        = 0x3        // SPI in master operation
	SERCOM_USART_INT_CTRLA_MODE_I2C_SLAVE                         = 0x4        // I2C slave operation
	SERCOM_USART_INT_CTRLA_MODE_I2C_MASTER                        = 0x5        // I2C master operation
	SERCOM_USART_INT_CTRLA_RUNSTDBY_Pos                           = 0x7        // Position of RUNSTDBY field.
	SERCOM_USART_INT_CTRLA_RUNSTDBY_Msk                           = 0x80       // Bit mask of RUNSTDBY field.
	SERCOM_USART_INT_CTRLA_RUNSTDBY                               = 0x80       // Bit RUNSTDBY.
	SERCOM_USART_INT_CTRLA_IBON_Pos                               = 0x8        // Position of IBON field.
	SERCOM_USART_INT_CTRLA_IBON_Msk                               = 0x100      // Bit mask of IBON field.
	SERCOM_USART_INT_CTRLA_IBON                                   = 0x100      // Bit IBON.
	SERCOM_USART_INT_CTRLA_TXINV_Pos                              = 0x9        // Position of TXINV field.
	SERCOM_USART_INT_CTRLA_TXINV_Msk                              = 0x200      // Bit mask of TXINV field.
	SERCOM_USART_INT_CTRLA_TXINV                                  = 0x200      // Bit TXINV.
	SERCOM_USART_INT_CTRLA_RXINV_Pos                              = 0xa        // Position of RXINV field.
	SERCOM_USART_INT_CTRLA_RXINV_Msk                              = 0x400      // Bit mask of RXINV field.
	SERCOM_USART_INT_CTRLA_RXINV                                  = 0x400      // Bit RXINV.
	SERCOM_USART_INT_CTRLA_SAMPR_Pos                              = 0xd        // Position of SAMPR field.
	SERCOM_USART_INT_CTRLA_SAMPR_Msk                              = 0xe000     // Bit mask of SAMPR field.
	SERCOM_USART_INT_CTRLA_SAMPR_16X_ARITHMETIC                   = 0x0        // 16x over-sampling using arithmetic baudrate generation
	SERCOM_USART_INT_CTRLA_SAMPR_16X_FRACTIONAL                   = 0x1        // 16x over-sampling using fractional baudrate generation
	SERCOM_USART_INT_CTRLA_SAMPR_8X_ARITHMETIC                    = 0x2        // 8x over-sampling using arithmetic baudrate generation
	SERCOM_USART_INT_CTRLA_SAMPR_8X_FRACTIONAL                    = 0x3        // 8x over-sampling using fractional baudrate generation
	SERCOM_USART_INT_CTRLA_SAMPR_3X_ARITHMETIC                    = 0x4        // 3x over-sampling using arithmetic baudrate generation
	SERCOM_USART_INT_CTRLA_TXPO_Pos                               = 0x10       // Position of TXPO field.
	SERCOM_USART_INT_CTRLA_TXPO_Msk                               = 0x30000    // Bit mask of TXPO field.
	SERCOM_USART_INT_CTRLA_TXPO_PAD0                              = 0x0        // SERCOM PAD[0] is used for data transmission
	SERCOM_USART_INT_CTRLA_TXPO_PAD3                              = 0x3        // SERCOM_PAD[0] is used for data transmission
	SERCOM_USART_INT_CTRLA_RXPO_Pos                               = 0x14       // Position of RXPO field.
	SERCOM_USART_INT_CTRLA_RXPO_Msk                               = 0x300000   // Bit mask of RXPO field.
	SERCOM_USART_INT_CTRLA_RXPO_PAD0                              = 0x0        // SERCOM PAD[0] is used for data reception
	SERCOM_USART_INT_CTRLA_RXPO_PAD1                              = 0x1        // SERCOM PAD[1] is used for data reception
	SERCOM_USART_INT_CTRLA_RXPO_PAD2                              = 0x2        // SERCOM PAD[2] is used for data reception
	SERCOM_USART_INT_CTRLA_RXPO_PAD3                              = 0x3        // SERCOM PAD[3] is used for data reception
	SERCOM_USART_INT_CTRLA_SAMPA_Pos                              = 0x16       // Position of SAMPA field.
	SERCOM_USART_INT_CTRLA_SAMPA_Msk                              = 0xc00000   // Bit mask of SAMPA field.
	SERCOM_USART_INT_CTRLA_FORM_Pos                               = 0x18       // Position of FORM field.
	SERCOM_USART_INT_CTRLA_FORM_Msk                               = 0xf000000  // Bit mask of FORM field.
	SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_NO_PARITY             = 0x0        // USART frame
	SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_WITH_PARITY           = 0x1        // USART frame with parity
	SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_LIN_MASTER_MODE       = 0x2        // LIN Master - Break and sync generation
	SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_AUTO_BAUD_NO_PARITY   = 0x4        // Auto-baud - break detection and auto-baud
	SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_AUTO_BAUD_WITH_PARITY = 0x5        // Auto-baud - break detection and auto-baud with parity
	SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_ISO_7816              = 0x7        // ISO 7816
	SERCOM_USART_INT_CTRLA_CMODE_Pos                              = 0x1c       // Position of CMODE field.
	SERCOM_USART_INT_CTRLA_CMODE_Msk                              = 0x10000000 // Bit mask of CMODE field.
	SERCOM_USART_INT_CTRLA_CMODE                                  = 0x10000000 // Bit CMODE.
	SERCOM_USART_INT_CTRLA_CMODE_ASYNC                            = 0x0        // Asynchronous Communication
	SERCOM_USART_INT_CTRLA_CMODE_SYNC                             = 0x1        // Synchronous Communication
	SERCOM_USART_INT_CTRLA_CPOL_Pos                               = 0x1d       // Position of CPOL field.
	SERCOM_USART_INT_CTRLA_CPOL_Msk                               = 0x20000000 // Bit mask of CPOL field.
	SERCOM_USART_INT_CTRLA_CPOL                                   = 0x20000000 // Bit CPOL.
	SERCOM_USART_INT_CTRLA_CPOL_IDLE_LOW                          = 0x0        // TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge
	SERCOM_USART_INT_CTRLA_CPOL_IDLE_HIGH                         = 0x1        // TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge
	SERCOM_USART_INT_CTRLA_DORD_Pos                               = 0x1e       // Position of DORD field.
	SERCOM_USART_INT_CTRLA_DORD_Msk                               = 0x40000000 // Bit mask of DORD field.
	SERCOM_USART_INT_CTRLA_DORD                                   = 0x40000000 // Bit DORD.
	SERCOM_USART_INT_CTRLA_DORD_MSB                               = 0x0        // MSB is transmitted first
	SERCOM_USART_INT_CTRLA_DORD_LSB                               = 0x1        // LSB is transmitted first

	// CTRLB: USART_INT Control B
	SERCOM_USART_INT_CTRLB_CHSIZE_Pos   = 0x0       // Position of CHSIZE field.
	SERCOM_USART_INT_CTRLB_CHSIZE_Msk   = 0x7       // Bit mask of CHSIZE field.
	SERCOM_USART_INT_CTRLB_CHSIZE_8_BIT = 0x0       // 8 Bits
	SERCOM_USART_INT_CTRLB_CHSIZE_9_BIT = 0x1       // 9 Bits
	SERCOM_USART_INT_CTRLB_CHSIZE_5_BIT = 0x5       // 5 Bits
	SERCOM_USART_INT_CTRLB_CHSIZE_6_BIT = 0x6       // 6 Bits
	SERCOM_USART_INT_CTRLB_CHSIZE_7_BIT = 0x7       // 7 Bits
	SERCOM_USART_INT_CTRLB_SBMODE_Pos   = 0x6       // Position of SBMODE field.
	SERCOM_USART_INT_CTRLB_SBMODE_Msk   = 0x40      // Bit mask of SBMODE field.
	SERCOM_USART_INT_CTRLB_SBMODE       = 0x40      // Bit SBMODE.
	SERCOM_USART_INT_CTRLB_SBMODE_1_BIT = 0x0       // One Stop Bit
	SERCOM_USART_INT_CTRLB_SBMODE_2_BIT = 0x1       // Two Stop Bits
	SERCOM_USART_INT_CTRLB_COLDEN_Pos   = 0x8       // Position of COLDEN field.
	SERCOM_USART_INT_CTRLB_COLDEN_Msk   = 0x100     // Bit mask of COLDEN field.
	SERCOM_USART_INT_CTRLB_COLDEN       = 0x100     // Bit COLDEN.
	SERCOM_USART_INT_CTRLB_SFDE_Pos     = 0x9       // Position of SFDE field.
	SERCOM_USART_INT_CTRLB_SFDE_Msk     = 0x200     // Bit mask of SFDE field.
	SERCOM_USART_INT_CTRLB_SFDE         = 0x200     // Bit SFDE.
	SERCOM_USART_INT_CTRLB_ENC_Pos      = 0xa       // Position of ENC field.
	SERCOM_USART_INT_CTRLB_ENC_Msk      = 0x400     // Bit mask of ENC field.
	SERCOM_USART_INT_CTRLB_ENC          = 0x400     // Bit ENC.
	SERCOM_USART_INT_CTRLB_PMODE_Pos    = 0xd       // Position of PMODE field.
	SERCOM_USART_INT_CTRLB_PMODE_Msk    = 0x2000    // Bit mask of PMODE field.
	SERCOM_USART_INT_CTRLB_PMODE        = 0x2000    // Bit PMODE.
	SERCOM_USART_INT_CTRLB_PMODE_EVEN   = 0x0       // Even Parity
	SERCOM_USART_INT_CTRLB_PMODE_ODD    = 0x1       // Odd Parity
	SERCOM_USART_INT_CTRLB_TXEN_Pos     = 0x10      // Position of TXEN field.
	SERCOM_USART_INT_CTRLB_TXEN_Msk     = 0x10000   // Bit mask of TXEN field.
	SERCOM_USART_INT_CTRLB_TXEN         = 0x10000   // Bit TXEN.
	SERCOM_USART_INT_CTRLB_RXEN_Pos     = 0x11      // Position of RXEN field.
	SERCOM_USART_INT_CTRLB_RXEN_Msk     = 0x20000   // Bit mask of RXEN field.
	SERCOM_USART_INT_CTRLB_RXEN         = 0x20000   // Bit RXEN.
	SERCOM_USART_INT_CTRLB_LINCMD_Pos   = 0x18      // Position of LINCMD field.
	SERCOM_USART_INT_CTRLB_LINCMD_Msk   = 0x3000000 // Bit mask of LINCMD field.

	// CTRLC: USART_INT Control C
	SERCOM_USART_INT_CTRLC_GTIME_Pos                            = 0x0       // Position of GTIME field.
	SERCOM_USART_INT_CTRLC_GTIME_Msk                            = 0x7       // Bit mask of GTIME field.
	SERCOM_USART_INT_CTRLC_BRKLEN_Pos                           = 0x8       // Position of BRKLEN field.
	SERCOM_USART_INT_CTRLC_BRKLEN_Msk                           = 0x300     // Bit mask of BRKLEN field.
	SERCOM_USART_INT_CTRLC_HDRDLY_Pos                           = 0xa       // Position of HDRDLY field.
	SERCOM_USART_INT_CTRLC_HDRDLY_Msk                           = 0xc00     // Bit mask of HDRDLY field.
	SERCOM_USART_INT_CTRLC_INACK_Pos                            = 0x10      // Position of INACK field.
	SERCOM_USART_INT_CTRLC_INACK_Msk                            = 0x10000   // Bit mask of INACK field.
	SERCOM_USART_INT_CTRLC_INACK                                = 0x10000   // Bit INACK.
	SERCOM_USART_INT_CTRLC_DSNACK_Pos                           = 0x11      // Position of DSNACK field.
	SERCOM_USART_INT_CTRLC_DSNACK_Msk                           = 0x20000   // Bit mask of DSNACK field.
	SERCOM_USART_INT_CTRLC_DSNACK                               = 0x20000   // Bit DSNACK.
	SERCOM_USART_INT_CTRLC_MAXITER_Pos                          = 0x14      // Position of MAXITER field.
	SERCOM_USART_INT_CTRLC_MAXITER_Msk                          = 0x700000  // Bit mask of MAXITER field.
	SERCOM_USART_INT_CTRLC_DATA32B_Pos                          = 0x18      // Position of DATA32B field.
	SERCOM_USART_INT_CTRLC_DATA32B_Msk                          = 0x3000000 // Bit mask of DATA32B field.
	SERCOM_USART_INT_CTRLC_DATA32B_DATA_READ_WRITE_CHSIZE       = 0x0       // Data reads and writes according CTRLB.CHSIZE
	SERCOM_USART_INT_CTRLC_DATA32B_DATA_READ_CHSIZE_WRITE_32BIT = 0x1       // Data reads according CTRLB.CHSIZE and writes according 32-bit extension
	SERCOM_USART_INT_CTRLC_DATA32B_DATA_READ_32BIT_WRITE_CHSIZE = 0x2       // Data reads according 32-bit extension and writes according CTRLB.CHSIZE
	SERCOM_USART_INT_CTRLC_DATA32B_DATA_READ_WRITE_32BIT        = 0x3       // Data reads and writes according 32-bit extension

	// BAUD: USART_INT Baud Rate
	SERCOM_USART_INT_BAUD_BAUD_Pos = 0x0    // Position of BAUD field.
	SERCOM_USART_INT_BAUD_BAUD_Msk = 0xffff // Bit mask of BAUD field.

	// BAUD_FRAC_MODE: USART_INT Baud Rate
	SERCOM_USART_INT_BAUD_FRAC_MODE_BAUD_Pos = 0x0    // Position of BAUD field.
	SERCOM_USART_INT_BAUD_FRAC_MODE_BAUD_Msk = 0x1fff // Bit mask of BAUD field.
	SERCOM_USART_INT_BAUD_FRAC_MODE_FP_Pos   = 0xd    // Position of FP field.
	SERCOM_USART_INT_BAUD_FRAC_MODE_FP_Msk   = 0xe000 // Bit mask of FP field.

	// BAUD_FRACFP_MODE: USART_INT Baud Rate
	SERCOM_USART_INT_BAUD_FRACFP_MODE_BAUD_Pos = 0x0    // Position of BAUD field.
	SERCOM_USART_INT_BAUD_FRACFP_MODE_BAUD_Msk = 0x1fff // Bit mask of BAUD field.
	SERCOM_USART_INT_BAUD_FRACFP_MODE_FP_Pos   = 0xd    // Position of FP field.
	SERCOM_USART_INT_BAUD_FRACFP_MODE_FP_Msk   = 0xe000 // Bit mask of FP field.

	// BAUD_USARTFP_MODE: USART_INT Baud Rate
	SERCOM_USART_INT_BAUD_USARTFP_MODE_BAUD_Pos = 0x0    // Position of BAUD field.
	SERCOM_USART_INT_BAUD_USARTFP_MODE_BAUD_Msk = 0xffff // Bit mask of BAUD field.

	// RXPL: USART_INT Receive Pulse Length
	SERCOM_USART_INT_RXPL_RXPL_Pos = 0x0  // Position of RXPL field.
	SERCOM_USART_INT_RXPL_RXPL_Msk = 0xff // Bit mask of RXPL field.

	// INTENCLR: USART_INT Interrupt Enable Clear
	SERCOM_USART_INT_INTENCLR_DRE_Pos   = 0x0  // Position of DRE field.
	SERCOM_USART_INT_INTENCLR_DRE_Msk   = 0x1  // Bit mask of DRE field.
	SERCOM_USART_INT_INTENCLR_DRE       = 0x1  // Bit DRE.
	SERCOM_USART_INT_INTENCLR_TXC_Pos   = 0x1  // Position of TXC field.
	SERCOM_USART_INT_INTENCLR_TXC_Msk   = 0x2  // Bit mask of TXC field.
	SERCOM_USART_INT_INTENCLR_TXC       = 0x2  // Bit TXC.
	SERCOM_USART_INT_INTENCLR_RXC_Pos   = 0x2  // Position of RXC field.
	SERCOM_USART_INT_INTENCLR_RXC_Msk   = 0x4  // Bit mask of RXC field.
	SERCOM_USART_INT_INTENCLR_RXC       = 0x4  // Bit RXC.
	SERCOM_USART_INT_INTENCLR_RXS_Pos   = 0x3  // Position of RXS field.
	SERCOM_USART_INT_INTENCLR_RXS_Msk   = 0x8  // Bit mask of RXS field.
	SERCOM_USART_INT_INTENCLR_RXS       = 0x8  // Bit RXS.
	SERCOM_USART_INT_INTENCLR_CTSIC_Pos = 0x4  // Position of CTSIC field.
	SERCOM_USART_INT_INTENCLR_CTSIC_Msk = 0x10 // Bit mask of CTSIC field.
	SERCOM_USART_INT_INTENCLR_CTSIC     = 0x10 // Bit CTSIC.
	SERCOM_USART_INT_INTENCLR_RXBRK_Pos = 0x5  // Position of RXBRK field.
	SERCOM_USART_INT_INTENCLR_RXBRK_Msk = 0x20 // Bit mask of RXBRK field.
	SERCOM_USART_INT_INTENCLR_RXBRK     = 0x20 // Bit RXBRK.
	SERCOM_USART_INT_INTENCLR_ERROR_Pos = 0x7  // Position of ERROR field.
	SERCOM_USART_INT_INTENCLR_ERROR_Msk = 0x80 // Bit mask of ERROR field.
	SERCOM_USART_INT_INTENCLR_ERROR     = 0x80 // Bit ERROR.

	// INTENSET: USART_INT Interrupt Enable Set
	SERCOM_USART_INT_INTENSET_DRE_Pos   = 0x0  // Position of DRE field.
	SERCOM_USART_INT_INTENSET_DRE_Msk   = 0x1  // Bit mask of DRE field.
	SERCOM_USART_INT_INTENSET_DRE       = 0x1  // Bit DRE.
	SERCOM_USART_INT_INTENSET_TXC_Pos   = 0x1  // Position of TXC field.
	SERCOM_USART_INT_INTENSET_TXC_Msk   = 0x2  // Bit mask of TXC field.
	SERCOM_USART_INT_INTENSET_TXC       = 0x2  // Bit TXC.
	SERCOM_USART_INT_INTENSET_RXC_Pos   = 0x2  // Position of RXC field.
	SERCOM_USART_INT_INTENSET_RXC_Msk   = 0x4  // Bit mask of RXC field.
	SERCOM_USART_INT_INTENSET_RXC       = 0x4  // Bit RXC.
	SERCOM_USART_INT_INTENSET_RXS_Pos   = 0x3  // Position of RXS field.
	SERCOM_USART_INT_INTENSET_RXS_Msk   = 0x8  // Bit mask of RXS field.
	SERCOM_USART_INT_INTENSET_RXS       = 0x8  // Bit RXS.
	SERCOM_USART_INT_INTENSET_CTSIC_Pos = 0x4  // Position of CTSIC field.
	SERCOM_USART_INT_INTENSET_CTSIC_Msk = 0x10 // Bit mask of CTSIC field.
	SERCOM_USART_INT_INTENSET_CTSIC     = 0x10 // Bit CTSIC.
	SERCOM_USART_INT_INTENSET_RXBRK_Pos = 0x5  // Position of RXBRK field.
	SERCOM_USART_INT_INTENSET_RXBRK_Msk = 0x20 // Bit mask of RXBRK field.
	SERCOM_USART_INT_INTENSET_RXBRK     = 0x20 // Bit RXBRK.
	SERCOM_USART_INT_INTENSET_ERROR_Pos = 0x7  // Position of ERROR field.
	SERCOM_USART_INT_INTENSET_ERROR_Msk = 0x80 // Bit mask of ERROR field.
	SERCOM_USART_INT_INTENSET_ERROR     = 0x80 // Bit ERROR.

	// INTFLAG: USART_INT Interrupt Flag Status and Clear
	SERCOM_USART_INT_INTFLAG_DRE_Pos   = 0x0  // Position of DRE field.
	SERCOM_USART_INT_INTFLAG_DRE_Msk   = 0x1  // Bit mask of DRE field.
	SERCOM_USART_INT_INTFLAG_DRE       = 0x1  // Bit DRE.
	SERCOM_USART_INT_INTFLAG_TXC_Pos   = 0x1  // Position of TXC field.
	SERCOM_USART_INT_INTFLAG_TXC_Msk   = 0x2  // Bit mask of TXC field.
	SERCOM_USART_INT_INTFLAG_TXC       = 0x2  // Bit TXC.
	SERCOM_USART_INT_INTFLAG_RXC_Pos   = 0x2  // Position of RXC field.
	SERCOM_USART_INT_INTFLAG_RXC_Msk   = 0x4  // Bit mask of RXC field.
	SERCOM_USART_INT_INTFLAG_RXC       = 0x4  // Bit RXC.
	SERCOM_USART_INT_INTFLAG_RXS_Pos   = 0x3  // Position of RXS field.
	SERCOM_USART_INT_INTFLAG_RXS_Msk   = 0x8  // Bit mask of RXS field.
	SERCOM_USART_INT_INTFLAG_RXS       = 0x8  // Bit RXS.
	SERCOM_USART_INT_INTFLAG_CTSIC_Pos = 0x4  // Position of CTSIC field.
	SERCOM_USART_INT_INTFLAG_CTSIC_Msk = 0x10 // Bit mask of CTSIC field.
	SERCOM_USART_INT_INTFLAG_CTSIC     = 0x10 // Bit CTSIC.
	SERCOM_USART_INT_INTFLAG_RXBRK_Pos = 0x5  // Position of RXBRK field.
	SERCOM_USART_INT_INTFLAG_RXBRK_Msk = 0x20 // Bit mask of RXBRK field.
	SERCOM_USART_INT_INTFLAG_RXBRK     = 0x20 // Bit RXBRK.
	SERCOM_USART_INT_INTFLAG_ERROR_Pos = 0x7  // Position of ERROR field.
	SERCOM_USART_INT_INTFLAG_ERROR_Msk = 0x80 // Bit mask of ERROR field.
	SERCOM_USART_INT_INTFLAG_ERROR     = 0x80 // Bit ERROR.

	// STATUS: USART_INT Status
	SERCOM_USART_INT_STATUS_PERR_Pos   = 0x0  // Position of PERR field.
	SERCOM_USART_INT_STATUS_PERR_Msk   = 0x1  // Bit mask of PERR field.
	SERCOM_USART_INT_STATUS_PERR       = 0x1  // Bit PERR.
	SERCOM_USART_INT_STATUS_FERR_Pos   = 0x1  // Position of FERR field.
	SERCOM_USART_INT_STATUS_FERR_Msk   = 0x2  // Bit mask of FERR field.
	SERCOM_USART_INT_STATUS_FERR       = 0x2  // Bit FERR.
	SERCOM_USART_INT_STATUS_BUFOVF_Pos = 0x2  // Position of BUFOVF field.
	SERCOM_USART_INT_STATUS_BUFOVF_Msk = 0x4  // Bit mask of BUFOVF field.
	SERCOM_USART_INT_STATUS_BUFOVF     = 0x4  // Bit BUFOVF.
	SERCOM_USART_INT_STATUS_CTS_Pos    = 0x3  // Position of CTS field.
	SERCOM_USART_INT_STATUS_CTS_Msk    = 0x8  // Bit mask of CTS field.
	SERCOM_USART_INT_STATUS_CTS        = 0x8  // Bit CTS.
	SERCOM_USART_INT_STATUS_ISF_Pos    = 0x4  // Position of ISF field.
	SERCOM_USART_INT_STATUS_ISF_Msk    = 0x10 // Bit mask of ISF field.
	SERCOM_USART_INT_STATUS_ISF        = 0x10 // Bit ISF.
	SERCOM_USART_INT_STATUS_COLL_Pos   = 0x5  // Position of COLL field.
	SERCOM_USART_INT_STATUS_COLL_Msk   = 0x20 // Bit mask of COLL field.
	SERCOM_USART_INT_STATUS_COLL       = 0x20 // Bit COLL.
	SERCOM_USART_INT_STATUS_TXE_Pos    = 0x6  // Position of TXE field.
	SERCOM_USART_INT_STATUS_TXE_Msk    = 0x40 // Bit mask of TXE field.
	SERCOM_USART_INT_STATUS_TXE        = 0x40 // Bit TXE.
	SERCOM_USART_INT_STATUS_ITER_Pos   = 0x7  // Position of ITER field.
	SERCOM_USART_INT_STATUS_ITER_Msk   = 0x80 // Bit mask of ITER field.
	SERCOM_USART_INT_STATUS_ITER       = 0x80 // Bit ITER.

	// SYNCBUSY: USART_INT Synchronization Busy
	SERCOM_USART_INT_SYNCBUSY_SWRST_Pos    = 0x0  // Position of SWRST field.
	SERCOM_USART_INT_SYNCBUSY_SWRST_Msk    = 0x1  // Bit mask of SWRST field.
	SERCOM_USART_INT_SYNCBUSY_SWRST        = 0x1  // Bit SWRST.
	SERCOM_USART_INT_SYNCBUSY_ENABLE_Pos   = 0x1  // Position of ENABLE field.
	SERCOM_USART_INT_SYNCBUSY_ENABLE_Msk   = 0x2  // Bit mask of ENABLE field.
	SERCOM_USART_INT_SYNCBUSY_ENABLE       = 0x2  // Bit ENABLE.
	SERCOM_USART_INT_SYNCBUSY_CTRLB_Pos    = 0x2  // Position of CTRLB field.
	SERCOM_USART_INT_SYNCBUSY_CTRLB_Msk    = 0x4  // Bit mask of CTRLB field.
	SERCOM_USART_INT_SYNCBUSY_CTRLB        = 0x4  // Bit CTRLB.
	SERCOM_USART_INT_SYNCBUSY_RXERRCNT_Pos = 0x3  // Position of RXERRCNT field.
	SERCOM_USART_INT_SYNCBUSY_RXERRCNT_Msk = 0x8  // Bit mask of RXERRCNT field.
	SERCOM_USART_INT_SYNCBUSY_RXERRCNT     = 0x8  // Bit RXERRCNT.
	SERCOM_USART_INT_SYNCBUSY_LENGTH_Pos   = 0x4  // Position of LENGTH field.
	SERCOM_USART_INT_SYNCBUSY_LENGTH_Msk   = 0x10 // Bit mask of LENGTH field.
	SERCOM_USART_INT_SYNCBUSY_LENGTH       = 0x10 // Bit LENGTH.

	// LENGTH: USART_INT Length
	SERCOM_USART_INT_LENGTH_LEN_Pos   = 0x0   // Position of LEN field.
	SERCOM_USART_INT_LENGTH_LEN_Msk   = 0xff  // Bit mask of LEN field.
	SERCOM_USART_INT_LENGTH_LENEN_Pos = 0x8   // Position of LENEN field.
	SERCOM_USART_INT_LENGTH_LENEN_Msk = 0x300 // Bit mask of LENEN field.

	// DATA: USART_INT Data
	SERCOM_USART_INT_DATA_DATA_Pos = 0x0        // Position of DATA field.
	SERCOM_USART_INT_DATA_DATA_Msk = 0xffffffff // Bit mask of DATA field.

	// DBGCTRL: USART_INT Debug Control
	SERCOM_USART_INT_DBGCTRL_DBGSTOP_Pos = 0x0 // Position of DBGSTOP field.
	SERCOM_USART_INT_DBGCTRL_DBGSTOP_Msk = 0x1 // Bit mask of DBGSTOP field.
	SERCOM_USART_INT_DBGCTRL_DBGSTOP     = 0x1 // Bit DBGSTOP.
)

// Bitfields for SUPC: Supply Controller
const (
	// INTENCLR: Interrupt Enable Clear
	SUPC_INTENCLR_BOD33RDY_Pos = 0x0   // Position of BOD33RDY field.
	SUPC_INTENCLR_BOD33RDY_Msk = 0x1   // Bit mask of BOD33RDY field.
	SUPC_INTENCLR_BOD33RDY     = 0x1   // Bit BOD33RDY.
	SUPC_INTENCLR_BOD33DET_Pos = 0x1   // Position of BOD33DET field.
	SUPC_INTENCLR_BOD33DET_Msk = 0x2   // Bit mask of BOD33DET field.
	SUPC_INTENCLR_BOD33DET     = 0x2   // Bit BOD33DET.
	SUPC_INTENCLR_B33SRDY_Pos  = 0x2   // Position of B33SRDY field.
	SUPC_INTENCLR_B33SRDY_Msk  = 0x4   // Bit mask of B33SRDY field.
	SUPC_INTENCLR_B33SRDY      = 0x4   // Bit B33SRDY.
	SUPC_INTENCLR_VREGRDY_Pos  = 0x8   // Position of VREGRDY field.
	SUPC_INTENCLR_VREGRDY_Msk  = 0x100 // Bit mask of VREGRDY field.
	SUPC_INTENCLR_VREGRDY      = 0x100 // Bit VREGRDY.
	SUPC_INTENCLR_VCORERDY_Pos = 0xa   // Position of VCORERDY field.
	SUPC_INTENCLR_VCORERDY_Msk = 0x400 // Bit mask of VCORERDY field.
	SUPC_INTENCLR_VCORERDY     = 0x400 // Bit VCORERDY.

	// INTENSET: Interrupt Enable Set
	SUPC_INTENSET_BOD33RDY_Pos = 0x0   // Position of BOD33RDY field.
	SUPC_INTENSET_BOD33RDY_Msk = 0x1   // Bit mask of BOD33RDY field.
	SUPC_INTENSET_BOD33RDY     = 0x1   // Bit BOD33RDY.
	SUPC_INTENSET_BOD33DET_Pos = 0x1   // Position of BOD33DET field.
	SUPC_INTENSET_BOD33DET_Msk = 0x2   // Bit mask of BOD33DET field.
	SUPC_INTENSET_BOD33DET     = 0x2   // Bit BOD33DET.
	SUPC_INTENSET_B33SRDY_Pos  = 0x2   // Position of B33SRDY field.
	SUPC_INTENSET_B33SRDY_Msk  = 0x4   // Bit mask of B33SRDY field.
	SUPC_INTENSET_B33SRDY      = 0x4   // Bit B33SRDY.
	SUPC_INTENSET_VREGRDY_Pos  = 0x8   // Position of VREGRDY field.
	SUPC_INTENSET_VREGRDY_Msk  = 0x100 // Bit mask of VREGRDY field.
	SUPC_INTENSET_VREGRDY      = 0x100 // Bit VREGRDY.
	SUPC_INTENSET_VCORERDY_Pos = 0xa   // Position of VCORERDY field.
	SUPC_INTENSET_VCORERDY_Msk = 0x400 // Bit mask of VCORERDY field.
	SUPC_INTENSET_VCORERDY     = 0x400 // Bit VCORERDY.

	// INTFLAG: Interrupt Flag Status and Clear
	SUPC_INTFLAG_BOD33RDY_Pos = 0x0   // Position of BOD33RDY field.
	SUPC_INTFLAG_BOD33RDY_Msk = 0x1   // Bit mask of BOD33RDY field.
	SUPC_INTFLAG_BOD33RDY     = 0x1   // Bit BOD33RDY.
	SUPC_INTFLAG_BOD33DET_Pos = 0x1   // Position of BOD33DET field.
	SUPC_INTFLAG_BOD33DET_Msk = 0x2   // Bit mask of BOD33DET field.
	SUPC_INTFLAG_BOD33DET     = 0x2   // Bit BOD33DET.
	SUPC_INTFLAG_B33SRDY_Pos  = 0x2   // Position of B33SRDY field.
	SUPC_INTFLAG_B33SRDY_Msk  = 0x4   // Bit mask of B33SRDY field.
	SUPC_INTFLAG_B33SRDY      = 0x4   // Bit B33SRDY.
	SUPC_INTFLAG_VREGRDY_Pos  = 0x8   // Position of VREGRDY field.
	SUPC_INTFLAG_VREGRDY_Msk  = 0x100 // Bit mask of VREGRDY field.
	SUPC_INTFLAG_VREGRDY      = 0x100 // Bit VREGRDY.
	SUPC_INTFLAG_VCORERDY_Pos = 0xa   // Position of VCORERDY field.
	SUPC_INTFLAG_VCORERDY_Msk = 0x400 // Bit mask of VCORERDY field.
	SUPC_INTFLAG_VCORERDY     = 0x400 // Bit VCORERDY.

	// STATUS: Power and Clocks Status
	SUPC_STATUS_BOD33RDY_Pos = 0x0   // Position of BOD33RDY field.
	SUPC_STATUS_BOD33RDY_Msk = 0x1   // Bit mask of BOD33RDY field.
	SUPC_STATUS_BOD33RDY     = 0x1   // Bit BOD33RDY.
	SUPC_STATUS_BOD33DET_Pos = 0x1   // Position of BOD33DET field.
	SUPC_STATUS_BOD33DET_Msk = 0x2   // Bit mask of BOD33DET field.
	SUPC_STATUS_BOD33DET     = 0x2   // Bit BOD33DET.
	SUPC_STATUS_B33SRDY_Pos  = 0x2   // Position of B33SRDY field.
	SUPC_STATUS_B33SRDY_Msk  = 0x4   // Bit mask of B33SRDY field.
	SUPC_STATUS_B33SRDY      = 0x4   // Bit B33SRDY.
	SUPC_STATUS_VREGRDY_Pos  = 0x8   // Position of VREGRDY field.
	SUPC_STATUS_VREGRDY_Msk  = 0x100 // Bit mask of VREGRDY field.
	SUPC_STATUS_VREGRDY      = 0x100 // Bit VREGRDY.
	SUPC_STATUS_VCORERDY_Pos = 0xa   // Position of VCORERDY field.
	SUPC_STATUS_VCORERDY_Msk = 0x400 // Bit mask of VCORERDY field.
	SUPC_STATUS_VCORERDY     = 0x400 // Bit VCORERDY.

	// BOD33: BOD33 Control
	SUPC_BOD33_ENABLE_Pos    = 0x1        // Position of ENABLE field.
	SUPC_BOD33_ENABLE_Msk    = 0x2        // Bit mask of ENABLE field.
	SUPC_BOD33_ENABLE        = 0x2        // Bit ENABLE.
	SUPC_BOD33_ACTION_Pos    = 0x2        // Position of ACTION field.
	SUPC_BOD33_ACTION_Msk    = 0xc        // Bit mask of ACTION field.
	SUPC_BOD33_ACTION_NONE   = 0x0        // No action
	SUPC_BOD33_ACTION_RESET  = 0x1        // The BOD33 generates a reset
	SUPC_BOD33_ACTION_INT    = 0x2        // The BOD33 generates an interrupt
	SUPC_BOD33_ACTION_BKUP   = 0x3        // The BOD33 puts the device in backup sleep mode
	SUPC_BOD33_STDBYCFG_Pos  = 0x4        // Position of STDBYCFG field.
	SUPC_BOD33_STDBYCFG_Msk  = 0x10       // Bit mask of STDBYCFG field.
	SUPC_BOD33_STDBYCFG      = 0x10       // Bit STDBYCFG.
	SUPC_BOD33_RUNSTDBY_Pos  = 0x5        // Position of RUNSTDBY field.
	SUPC_BOD33_RUNSTDBY_Msk  = 0x20       // Bit mask of RUNSTDBY field.
	SUPC_BOD33_RUNSTDBY      = 0x20       // Bit RUNSTDBY.
	SUPC_BOD33_RUNHIB_Pos    = 0x6        // Position of RUNHIB field.
	SUPC_BOD33_RUNHIB_Msk    = 0x40       // Bit mask of RUNHIB field.
	SUPC_BOD33_RUNHIB        = 0x40       // Bit RUNHIB.
	SUPC_BOD33_RUNBKUP_Pos   = 0x7        // Position of RUNBKUP field.
	SUPC_BOD33_RUNBKUP_Msk   = 0x80       // Bit mask of RUNBKUP field.
	SUPC_BOD33_RUNBKUP       = 0x80       // Bit RUNBKUP.
	SUPC_BOD33_HYST_Pos      = 0x8        // Position of HYST field.
	SUPC_BOD33_HYST_Msk      = 0xf00      // Bit mask of HYST field.
	SUPC_BOD33_PSEL_Pos      = 0xc        // Position of PSEL field.
	SUPC_BOD33_PSEL_Msk      = 0x7000     // Bit mask of PSEL field.
	SUPC_BOD33_PSEL_NODIV    = 0x0        // Not divided
	SUPC_BOD33_PSEL_DIV4     = 0x1        // Divide clock by 4
	SUPC_BOD33_PSEL_DIV8     = 0x2        // Divide clock by 8
	SUPC_BOD33_PSEL_DIV16    = 0x3        // Divide clock by 16
	SUPC_BOD33_PSEL_DIV32    = 0x4        // Divide clock by 32
	SUPC_BOD33_PSEL_DIV64    = 0x5        // Divide clock by 64
	SUPC_BOD33_PSEL_DIV128   = 0x6        // Divide clock by 128
	SUPC_BOD33_PSEL_DIV256   = 0x7        // Divide clock by 256
	SUPC_BOD33_LEVEL_Pos     = 0x10       // Position of LEVEL field.
	SUPC_BOD33_LEVEL_Msk     = 0xff0000   // Bit mask of LEVEL field.
	SUPC_BOD33_VBATLEVEL_Pos = 0x18       // Position of VBATLEVEL field.
	SUPC_BOD33_VBATLEVEL_Msk = 0xff000000 // Bit mask of VBATLEVEL field.

	// VREG: VREG Control
	SUPC_VREG_ENABLE_Pos  = 0x1       // Position of ENABLE field.
	SUPC_VREG_ENABLE_Msk  = 0x2       // Bit mask of ENABLE field.
	SUPC_VREG_ENABLE      = 0x2       // Bit ENABLE.
	SUPC_VREG_SEL_Pos     = 0x2       // Position of SEL field.
	SUPC_VREG_SEL_Msk     = 0x4       // Bit mask of SEL field.
	SUPC_VREG_SEL         = 0x4       // Bit SEL.
	SUPC_VREG_SEL_LDO     = 0x0       // LDO selection
	SUPC_VREG_SEL_BUCK    = 0x1       // Buck selection
	SUPC_VREG_RUNBKUP_Pos = 0x7       // Position of RUNBKUP field.
	SUPC_VREG_RUNBKUP_Msk = 0x80      // Bit mask of RUNBKUP field.
	SUPC_VREG_RUNBKUP     = 0x80      // Bit RUNBKUP.
	SUPC_VREG_VSEN_Pos    = 0x10      // Position of VSEN field.
	SUPC_VREG_VSEN_Msk    = 0x10000   // Bit mask of VSEN field.
	SUPC_VREG_VSEN        = 0x10000   // Bit VSEN.
	SUPC_VREG_VSPER_Pos   = 0x18      // Position of VSPER field.
	SUPC_VREG_VSPER_Msk   = 0x7000000 // Bit mask of VSPER field.

	// VREF: VREF Control
	SUPC_VREF_TSEN_Pos     = 0x1     // Position of TSEN field.
	SUPC_VREF_TSEN_Msk     = 0x2     // Bit mask of TSEN field.
	SUPC_VREF_TSEN         = 0x2     // Bit TSEN.
	SUPC_VREF_VREFOE_Pos   = 0x2     // Position of VREFOE field.
	SUPC_VREF_VREFOE_Msk   = 0x4     // Bit mask of VREFOE field.
	SUPC_VREF_VREFOE       = 0x4     // Bit VREFOE.
	SUPC_VREF_TSSEL_Pos    = 0x3     // Position of TSSEL field.
	SUPC_VREF_TSSEL_Msk    = 0x8     // Bit mask of TSSEL field.
	SUPC_VREF_TSSEL        = 0x8     // Bit TSSEL.
	SUPC_VREF_RUNSTDBY_Pos = 0x6     // Position of RUNSTDBY field.
	SUPC_VREF_RUNSTDBY_Msk = 0x40    // Bit mask of RUNSTDBY field.
	SUPC_VREF_RUNSTDBY     = 0x40    // Bit RUNSTDBY.
	SUPC_VREF_ONDEMAND_Pos = 0x7     // Position of ONDEMAND field.
	SUPC_VREF_ONDEMAND_Msk = 0x80    // Bit mask of ONDEMAND field.
	SUPC_VREF_ONDEMAND     = 0x80    // Bit ONDEMAND.
	SUPC_VREF_SEL_Pos      = 0x10    // Position of SEL field.
	SUPC_VREF_SEL_Msk      = 0xf0000 // Bit mask of SEL field.
	SUPC_VREF_SEL_1V0      = 0x0     // 1.0V voltage reference typical value
	SUPC_VREF_SEL_1V1      = 0x1     // 1.1V voltage reference typical value
	SUPC_VREF_SEL_1V2      = 0x2     // 1.2V voltage reference typical value
	SUPC_VREF_SEL_1V25     = 0x3     // 1.25V voltage reference typical value
	SUPC_VREF_SEL_2V0      = 0x4     // 2.0V voltage reference typical value
	SUPC_VREF_SEL_2V2      = 0x5     // 2.2V voltage reference typical value
	SUPC_VREF_SEL_2V4      = 0x6     // 2.4V voltage reference typical value
	SUPC_VREF_SEL_2V5      = 0x7     // 2.5V voltage reference typical value

	// BBPS: Battery Backup Power Switch
	SUPC_BBPS_CONF_Pos    = 0x0 // Position of CONF field.
	SUPC_BBPS_CONF_Msk    = 0x1 // Bit mask of CONF field.
	SUPC_BBPS_CONF        = 0x1 // Bit CONF.
	SUPC_BBPS_CONF_BOD33  = 0x0 // The power switch is handled by the BOD33
	SUPC_BBPS_CONF_FORCED = 0x1 // In Backup Domain, the backup domain is always supplied by battery backup power
	SUPC_BBPS_WAKEEN_Pos  = 0x2 // Position of WAKEEN field.
	SUPC_BBPS_WAKEEN_Msk  = 0x4 // Bit mask of WAKEEN field.
	SUPC_BBPS_WAKEEN      = 0x4 // Bit WAKEEN.

	// BKOUT: Backup Output Control
	SUPC_BKOUT_ENOUT0_Pos     = 0x0       // Position of ENOUT0 field.
	SUPC_BKOUT_ENOUT0_Msk     = 0x1       // Bit mask of ENOUT0 field.
	SUPC_BKOUT_ENOUT0         = 0x1       // Bit ENOUT0.
	SUPC_BKOUT_ENOUT1_Pos     = 0x1       // Position of ENOUT1 field.
	SUPC_BKOUT_ENOUT1_Msk     = 0x2       // Bit mask of ENOUT1 field.
	SUPC_BKOUT_ENOUT1         = 0x2       // Bit ENOUT1.
	SUPC_BKOUT_CLROUT0_Pos    = 0x8       // Position of CLROUT0 field.
	SUPC_BKOUT_CLROUT0_Msk    = 0x100     // Bit mask of CLROUT0 field.
	SUPC_BKOUT_CLROUT0        = 0x100     // Bit CLROUT0.
	SUPC_BKOUT_CLROUT1_Pos    = 0x9       // Position of CLROUT1 field.
	SUPC_BKOUT_CLROUT1_Msk    = 0x200     // Bit mask of CLROUT1 field.
	SUPC_BKOUT_CLROUT1        = 0x200     // Bit CLROUT1.
	SUPC_BKOUT_SETOUT0_Pos    = 0x10      // Position of SETOUT0 field.
	SUPC_BKOUT_SETOUT0_Msk    = 0x10000   // Bit mask of SETOUT0 field.
	SUPC_BKOUT_SETOUT0        = 0x10000   // Bit SETOUT0.
	SUPC_BKOUT_SETOUT1_Pos    = 0x11      // Position of SETOUT1 field.
	SUPC_BKOUT_SETOUT1_Msk    = 0x20000   // Bit mask of SETOUT1 field.
	SUPC_BKOUT_SETOUT1        = 0x20000   // Bit SETOUT1.
	SUPC_BKOUT_RTCTGLOUT0_Pos = 0x18      // Position of RTCTGLOUT0 field.
	SUPC_BKOUT_RTCTGLOUT0_Msk = 0x1000000 // Bit mask of RTCTGLOUT0 field.
	SUPC_BKOUT_RTCTGLOUT0     = 0x1000000 // Bit RTCTGLOUT0.
	SUPC_BKOUT_RTCTGLOUT1_Pos = 0x19      // Position of RTCTGLOUT1 field.
	SUPC_BKOUT_RTCTGLOUT1_Msk = 0x2000000 // Bit mask of RTCTGLOUT1 field.
	SUPC_BKOUT_RTCTGLOUT1     = 0x2000000 // Bit RTCTGLOUT1.

	// BKIN: Backup Input Control
	SUPC_BKIN_BKIN0_Pos = 0x0 // Position of BKIN0 field.
	SUPC_BKIN_BKIN0_Msk = 0x1 // Bit mask of BKIN0 field.
	SUPC_BKIN_BKIN0     = 0x1 // Bit BKIN0.
	SUPC_BKIN_BKIN1_Pos = 0x1 // Position of BKIN1 field.
	SUPC_BKIN_BKIN1_Msk = 0x2 // Bit mask of BKIN1 field.
	SUPC_BKIN_BKIN1     = 0x2 // Bit BKIN1.
)

// Bitfields for TC0: Basic Timer Counter
const ()

// Bitfields for TC0_COUNT8: Basic Timer Counter - COUNT8
const (
	// CTRLA: Control A
	TC_COUNT8_CTRLA_SWRST_Pos         = 0x0        // Position of SWRST field.
	TC_COUNT8_CTRLA_SWRST_Msk         = 0x1        // Bit mask of SWRST field.
	TC_COUNT8_CTRLA_SWRST             = 0x1        // Bit SWRST.
	TC_COUNT8_CTRLA_ENABLE_Pos        = 0x1        // Position of ENABLE field.
	TC_COUNT8_CTRLA_ENABLE_Msk        = 0x2        // Bit mask of ENABLE field.
	TC_COUNT8_CTRLA_ENABLE            = 0x2        // Bit ENABLE.
	TC_COUNT8_CTRLA_MODE_Pos          = 0x2        // Position of MODE field.
	TC_COUNT8_CTRLA_MODE_Msk          = 0xc        // Bit mask of MODE field.
	TC_COUNT8_CTRLA_MODE_COUNT16      = 0x0        // Counter in 16-bit mode
	TC_COUNT8_CTRLA_MODE_COUNT8       = 0x1        // Counter in 8-bit mode
	TC_COUNT8_CTRLA_MODE_COUNT32      = 0x2        // Counter in 32-bit mode
	TC_COUNT8_CTRLA_PRESCSYNC_Pos     = 0x4        // Position of PRESCSYNC field.
	TC_COUNT8_CTRLA_PRESCSYNC_Msk     = 0x30       // Bit mask of PRESCSYNC field.
	TC_COUNT8_CTRLA_PRESCSYNC_GCLK    = 0x0        // Reload or reset the counter on next generic clock
	TC_COUNT8_CTRLA_PRESCSYNC_PRESC   = 0x1        // Reload or reset the counter on next prescaler clock
	TC_COUNT8_CTRLA_PRESCSYNC_RESYNC  = 0x2        // Reload or reset the counter on next generic clock and reset the prescaler counter
	TC_COUNT8_CTRLA_RUNSTDBY_Pos      = 0x6        // Position of RUNSTDBY field.
	TC_COUNT8_CTRLA_RUNSTDBY_Msk      = 0x40       // Bit mask of RUNSTDBY field.
	TC_COUNT8_CTRLA_RUNSTDBY          = 0x40       // Bit RUNSTDBY.
	TC_COUNT8_CTRLA_ONDEMAND_Pos      = 0x7        // Position of ONDEMAND field.
	TC_COUNT8_CTRLA_ONDEMAND_Msk      = 0x80       // Bit mask of ONDEMAND field.
	TC_COUNT8_CTRLA_ONDEMAND          = 0x80       // Bit ONDEMAND.
	TC_COUNT8_CTRLA_PRESCALER_Pos     = 0x8        // Position of PRESCALER field.
	TC_COUNT8_CTRLA_PRESCALER_Msk     = 0x700      // Bit mask of PRESCALER field.
	TC_COUNT8_CTRLA_PRESCALER_DIV1    = 0x0        // Prescaler: GCLK_TC
	TC_COUNT8_CTRLA_PRESCALER_DIV2    = 0x1        // Prescaler: GCLK_TC/2
	TC_COUNT8_CTRLA_PRESCALER_DIV4    = 0x2        // Prescaler: GCLK_TC/4
	TC_COUNT8_CTRLA_PRESCALER_DIV8    = 0x3        // Prescaler: GCLK_TC/8
	TC_COUNT8_CTRLA_PRESCALER_DIV16   = 0x4        // Prescaler: GCLK_TC/16
	TC_COUNT8_CTRLA_PRESCALER_DIV64   = 0x5        // Prescaler: GCLK_TC/64
	TC_COUNT8_CTRLA_PRESCALER_DIV256  = 0x6        // Prescaler: GCLK_TC/256
	TC_COUNT8_CTRLA_PRESCALER_DIV1024 = 0x7        // Prescaler: GCLK_TC/1024
	TC_COUNT8_CTRLA_ALOCK_Pos         = 0xb        // Position of ALOCK field.
	TC_COUNT8_CTRLA_ALOCK_Msk         = 0x800      // Bit mask of ALOCK field.
	TC_COUNT8_CTRLA_ALOCK             = 0x800      // Bit ALOCK.
	TC_COUNT8_CTRLA_CAPTEN0_Pos       = 0x10       // Position of CAPTEN0 field.
	TC_COUNT8_CTRLA_CAPTEN0_Msk       = 0x10000    // Bit mask of CAPTEN0 field.
	TC_COUNT8_CTRLA_CAPTEN0           = 0x10000    // Bit CAPTEN0.
	TC_COUNT8_CTRLA_CAPTEN1_Pos       = 0x11       // Position of CAPTEN1 field.
	TC_COUNT8_CTRLA_CAPTEN1_Msk       = 0x20000    // Bit mask of CAPTEN1 field.
	TC_COUNT8_CTRLA_CAPTEN1           = 0x20000    // Bit CAPTEN1.
	TC_COUNT8_CTRLA_COPEN0_Pos        = 0x14       // Position of COPEN0 field.
	TC_COUNT8_CTRLA_COPEN0_Msk        = 0x100000   // Bit mask of COPEN0 field.
	TC_COUNT8_CTRLA_COPEN0            = 0x100000   // Bit COPEN0.
	TC_COUNT8_CTRLA_COPEN1_Pos        = 0x15       // Position of COPEN1 field.
	TC_COUNT8_CTRLA_COPEN1_Msk        = 0x200000   // Bit mask of COPEN1 field.
	TC_COUNT8_CTRLA_COPEN1            = 0x200000   // Bit COPEN1.
	TC_COUNT8_CTRLA_CAPTMODE0_Pos     = 0x18       // Position of CAPTMODE0 field.
	TC_COUNT8_CTRLA_CAPTMODE0_Msk     = 0x3000000  // Bit mask of CAPTMODE0 field.
	TC_COUNT8_CTRLA_CAPTMODE0_DEFAULT = 0x0        // Default capture
	TC_COUNT8_CTRLA_CAPTMODE0_CAPTMIN = 0x1        // Minimum capture
	TC_COUNT8_CTRLA_CAPTMODE0_CAPTMAX = 0x2        // Maximum capture
	TC_COUNT8_CTRLA_CAPTMODE1_Pos     = 0x1b       // Position of CAPTMODE1 field.
	TC_COUNT8_CTRLA_CAPTMODE1_Msk     = 0x18000000 // Bit mask of CAPTMODE1 field.
	TC_COUNT8_CTRLA_CAPTMODE1_DEFAULT = 0x0        // Default capture
	TC_COUNT8_CTRLA_CAPTMODE1_CAPTMIN = 0x1        // Minimum capture
	TC_COUNT8_CTRLA_CAPTMODE1_CAPTMAX = 0x2        // Maximum capture

	// CTRLBCLR: Control B Clear
	TC_COUNT8_CTRLBCLR_DIR_Pos       = 0x0  // Position of DIR field.
	TC_COUNT8_CTRLBCLR_DIR_Msk       = 0x1  // Bit mask of DIR field.
	TC_COUNT8_CTRLBCLR_DIR           = 0x1  // Bit DIR.
	TC_COUNT8_CTRLBCLR_LUPD_Pos      = 0x1  // Position of LUPD field.
	TC_COUNT8_CTRLBCLR_LUPD_Msk      = 0x2  // Bit mask of LUPD field.
	TC_COUNT8_CTRLBCLR_LUPD          = 0x2  // Bit LUPD.
	TC_COUNT8_CTRLBCLR_ONESHOT_Pos   = 0x2  // Position of ONESHOT field.
	TC_COUNT8_CTRLBCLR_ONESHOT_Msk   = 0x4  // Bit mask of ONESHOT field.
	TC_COUNT8_CTRLBCLR_ONESHOT       = 0x4  // Bit ONESHOT.
	TC_COUNT8_CTRLBCLR_CMD_Pos       = 0x5  // Position of CMD field.
	TC_COUNT8_CTRLBCLR_CMD_Msk       = 0xe0 // Bit mask of CMD field.
	TC_COUNT8_CTRLBCLR_CMD_NONE      = 0x0  // No action
	TC_COUNT8_CTRLBCLR_CMD_RETRIGGER = 0x1  // Force a start, restart or retrigger
	TC_COUNT8_CTRLBCLR_CMD_STOP      = 0x2  // Force a stop
	TC_COUNT8_CTRLBCLR_CMD_UPDATE    = 0x3  // Force update of double-buffered register
	TC_COUNT8_CTRLBCLR_CMD_READSYNC  = 0x4  // Force a read synchronization of COUNT
	TC_COUNT8_CTRLBCLR_CMD_DMAOS     = 0x5  // One-shot DMA trigger

	// CTRLBSET: Control B Set
	TC_COUNT8_CTRLBSET_DIR_Pos       = 0x0  // Position of DIR field.
	TC_COUNT8_CTRLBSET_DIR_Msk       = 0x1  // Bit mask of DIR field.
	TC_COUNT8_CTRLBSET_DIR           = 0x1  // Bit DIR.
	TC_COUNT8_CTRLBSET_LUPD_Pos      = 0x1  // Position of LUPD field.
	TC_COUNT8_CTRLBSET_LUPD_Msk      = 0x2  // Bit mask of LUPD field.
	TC_COUNT8_CTRLBSET_LUPD          = 0x2  // Bit LUPD.
	TC_COUNT8_CTRLBSET_ONESHOT_Pos   = 0x2  // Position of ONESHOT field.
	TC_COUNT8_CTRLBSET_ONESHOT_Msk   = 0x4  // Bit mask of ONESHOT field.
	TC_COUNT8_CTRLBSET_ONESHOT       = 0x4  // Bit ONESHOT.
	TC_COUNT8_CTRLBSET_CMD_Pos       = 0x5  // Position of CMD field.
	TC_COUNT8_CTRLBSET_CMD_Msk       = 0xe0 // Bit mask of CMD field.
	TC_COUNT8_CTRLBSET_CMD_NONE      = 0x0  // No action
	TC_COUNT8_CTRLBSET_CMD_RETRIGGER = 0x1  // Force a start, restart or retrigger
	TC_COUNT8_CTRLBSET_CMD_STOP      = 0x2  // Force a stop
	TC_COUNT8_CTRLBSET_CMD_UPDATE    = 0x3  // Force update of double-buffered register
	TC_COUNT8_CTRLBSET_CMD_READSYNC  = 0x4  // Force a read synchronization of COUNT
	TC_COUNT8_CTRLBSET_CMD_DMAOS     = 0x5  // One-shot DMA trigger

	// EVCTRL: Event Control
	TC_COUNT8_EVCTRL_EVACT_Pos       = 0x0    // Position of EVACT field.
	TC_COUNT8_EVCTRL_EVACT_Msk       = 0x7    // Bit mask of EVACT field.
	TC_COUNT8_EVCTRL_EVACT_OFF       = 0x0    // Event action disabled
	TC_COUNT8_EVCTRL_EVACT_RETRIGGER = 0x1    // Start, restart or retrigger TC on event
	TC_COUNT8_EVCTRL_EVACT_COUNT     = 0x2    // Count on event
	TC_COUNT8_EVCTRL_EVACT_START     = 0x3    // Start TC on event
	TC_COUNT8_EVCTRL_EVACT_STAMP     = 0x4    // Time stamp capture
	TC_COUNT8_EVCTRL_EVACT_PPW       = 0x5    // Period catured in CC0, pulse width in CC1
	TC_COUNT8_EVCTRL_EVACT_PWP       = 0x6    // Period catured in CC1, pulse width in CC0
	TC_COUNT8_EVCTRL_EVACT_PW        = 0x7    // Pulse width capture
	TC_COUNT8_EVCTRL_TCINV_Pos       = 0x4    // Position of TCINV field.
	TC_COUNT8_EVCTRL_TCINV_Msk       = 0x10   // Bit mask of TCINV field.
	TC_COUNT8_EVCTRL_TCINV           = 0x10   // Bit TCINV.
	TC_COUNT8_EVCTRL_TCEI_Pos        = 0x5    // Position of TCEI field.
	TC_COUNT8_EVCTRL_TCEI_Msk        = 0x20   // Bit mask of TCEI field.
	TC_COUNT8_EVCTRL_TCEI            = 0x20   // Bit TCEI.
	TC_COUNT8_EVCTRL_OVFEO_Pos       = 0x8    // Position of OVFEO field.
	TC_COUNT8_EVCTRL_OVFEO_Msk       = 0x100  // Bit mask of OVFEO field.
	TC_COUNT8_EVCTRL_OVFEO           = 0x100  // Bit OVFEO.
	TC_COUNT8_EVCTRL_MCEO0_Pos       = 0xc    // Position of MCEO0 field.
	TC_COUNT8_EVCTRL_MCEO0_Msk       = 0x1000 // Bit mask of MCEO0 field.
	TC_COUNT8_EVCTRL_MCEO0           = 0x1000 // Bit MCEO0.
	TC_COUNT8_EVCTRL_MCEO1_Pos       = 0xd    // Position of MCEO1 field.
	TC_COUNT8_EVCTRL_MCEO1_Msk       = 0x2000 // Bit mask of MCEO1 field.
	TC_COUNT8_EVCTRL_MCEO1           = 0x2000 // Bit MCEO1.

	// INTENCLR: Interrupt Enable Clear
	TC_COUNT8_INTENCLR_OVF_Pos = 0x0  // Position of OVF field.
	TC_COUNT8_INTENCLR_OVF_Msk = 0x1  // Bit mask of OVF field.
	TC_COUNT8_INTENCLR_OVF     = 0x1  // Bit OVF.
	TC_COUNT8_INTENCLR_ERR_Pos = 0x1  // Position of ERR field.
	TC_COUNT8_INTENCLR_ERR_Msk = 0x2  // Bit mask of ERR field.
	TC_COUNT8_INTENCLR_ERR     = 0x2  // Bit ERR.
	TC_COUNT8_INTENCLR_MC0_Pos = 0x4  // Position of MC0 field.
	TC_COUNT8_INTENCLR_MC0_Msk = 0x10 // Bit mask of MC0 field.
	TC_COUNT8_INTENCLR_MC0     = 0x10 // Bit MC0.
	TC_COUNT8_INTENCLR_MC1_Pos = 0x5  // Position of MC1 field.
	TC_COUNT8_INTENCLR_MC1_Msk = 0x20 // Bit mask of MC1 field.
	TC_COUNT8_INTENCLR_MC1     = 0x20 // Bit MC1.

	// INTENSET: Interrupt Enable Set
	TC_COUNT8_INTENSET_OVF_Pos = 0x0  // Position of OVF field.
	TC_COUNT8_INTENSET_OVF_Msk = 0x1  // Bit mask of OVF field.
	TC_COUNT8_INTENSET_OVF     = 0x1  // Bit OVF.
	TC_COUNT8_INTENSET_ERR_Pos = 0x1  // Position of ERR field.
	TC_COUNT8_INTENSET_ERR_Msk = 0x2  // Bit mask of ERR field.
	TC_COUNT8_INTENSET_ERR     = 0x2  // Bit ERR.
	TC_COUNT8_INTENSET_MC0_Pos = 0x4  // Position of MC0 field.
	TC_COUNT8_INTENSET_MC0_Msk = 0x10 // Bit mask of MC0 field.
	TC_COUNT8_INTENSET_MC0     = 0x10 // Bit MC0.
	TC_COUNT8_INTENSET_MC1_Pos = 0x5  // Position of MC1 field.
	TC_COUNT8_INTENSET_MC1_Msk = 0x20 // Bit mask of MC1 field.
	TC_COUNT8_INTENSET_MC1     = 0x20 // Bit MC1.

	// INTFLAG: Interrupt Flag Status and Clear
	TC_COUNT8_INTFLAG_OVF_Pos = 0x0  // Position of OVF field.
	TC_COUNT8_INTFLAG_OVF_Msk = 0x1  // Bit mask of OVF field.
	TC_COUNT8_INTFLAG_OVF     = 0x1  // Bit OVF.
	TC_COUNT8_INTFLAG_ERR_Pos = 0x1  // Position of ERR field.
	TC_COUNT8_INTFLAG_ERR_Msk = 0x2  // Bit mask of ERR field.
	TC_COUNT8_INTFLAG_ERR     = 0x2  // Bit ERR.
	TC_COUNT8_INTFLAG_MC0_Pos = 0x4  // Position of MC0 field.
	TC_COUNT8_INTFLAG_MC0_Msk = 0x10 // Bit mask of MC0 field.
	TC_COUNT8_INTFLAG_MC0     = 0x10 // Bit MC0.
	TC_COUNT8_INTFLAG_MC1_Pos = 0x5  // Position of MC1 field.
	TC_COUNT8_INTFLAG_MC1_Msk = 0x20 // Bit mask of MC1 field.
	TC_COUNT8_INTFLAG_MC1     = 0x20 // Bit MC1.

	// STATUS: Status
	TC_COUNT8_STATUS_STOP_Pos    = 0x0  // Position of STOP field.
	TC_COUNT8_STATUS_STOP_Msk    = 0x1  // Bit mask of STOP field.
	TC_COUNT8_STATUS_STOP        = 0x1  // Bit STOP.
	TC_COUNT8_STATUS_SLAVE_Pos   = 0x1  // Position of SLAVE field.
	TC_COUNT8_STATUS_SLAVE_Msk   = 0x2  // Bit mask of SLAVE field.
	TC_COUNT8_STATUS_SLAVE       = 0x2  // Bit SLAVE.
	TC_COUNT8_STATUS_PERBUFV_Pos = 0x3  // Position of PERBUFV field.
	TC_COUNT8_STATUS_PERBUFV_Msk = 0x8  // Bit mask of PERBUFV field.
	TC_COUNT8_STATUS_PERBUFV     = 0x8  // Bit PERBUFV.
	TC_COUNT8_STATUS_CCBUFV0_Pos = 0x4  // Position of CCBUFV0 field.
	TC_COUNT8_STATUS_CCBUFV0_Msk = 0x10 // Bit mask of CCBUFV0 field.
	TC_COUNT8_STATUS_CCBUFV0     = 0x10 // Bit CCBUFV0.
	TC_COUNT8_STATUS_CCBUFV1_Pos = 0x5  // Position of CCBUFV1 field.
	TC_COUNT8_STATUS_CCBUFV1_Msk = 0x20 // Bit mask of CCBUFV1 field.
	TC_COUNT8_STATUS_CCBUFV1     = 0x20 // Bit CCBUFV1.

	// WAVE: Waveform Generation Control
	TC_COUNT8_WAVE_WAVEGEN_Pos  = 0x0 // Position of WAVEGEN field.
	TC_COUNT8_WAVE_WAVEGEN_Msk  = 0x3 // Bit mask of WAVEGEN field.
	TC_COUNT8_WAVE_WAVEGEN_NFRQ = 0x0 // Normal frequency
	TC_COUNT8_WAVE_WAVEGEN_MFRQ = 0x1 // Match frequency
	TC_COUNT8_WAVE_WAVEGEN_NPWM = 0x2 // Normal PWM
	TC_COUNT8_WAVE_WAVEGEN_MPWM = 0x3 // Match PWM

	// DRVCTRL: Control C
	TC_COUNT8_DRVCTRL_INVEN0_Pos = 0x0 // Position of INVEN0 field.
	TC_COUNT8_DRVCTRL_INVEN0_Msk = 0x1 // Bit mask of INVEN0 field.
	TC_COUNT8_DRVCTRL_INVEN0     = 0x1 // Bit INVEN0.
	TC_COUNT8_DRVCTRL_INVEN1_Pos = 0x1 // Position of INVEN1 field.
	TC_COUNT8_DRVCTRL_INVEN1_Msk = 0x2 // Bit mask of INVEN1 field.
	TC_COUNT8_DRVCTRL_INVEN1     = 0x2 // Bit INVEN1.

	// DBGCTRL: Debug Control
	TC_COUNT8_DBGCTRL_DBGRUN_Pos = 0x0 // Position of DBGRUN field.
	TC_COUNT8_DBGCTRL_DBGRUN_Msk = 0x1 // Bit mask of DBGRUN field.
	TC_COUNT8_DBGCTRL_DBGRUN     = 0x1 // Bit DBGRUN.

	// SYNCBUSY: Synchronization Status
	TC_COUNT8_SYNCBUSY_SWRST_Pos  = 0x0  // Position of SWRST field.
	TC_COUNT8_SYNCBUSY_SWRST_Msk  = 0x1  // Bit mask of SWRST field.
	TC_COUNT8_SYNCBUSY_SWRST      = 0x1  // Bit SWRST.
	TC_COUNT8_SYNCBUSY_ENABLE_Pos = 0x1  // Position of ENABLE field.
	TC_COUNT8_SYNCBUSY_ENABLE_Msk = 0x2  // Bit mask of ENABLE field.
	TC_COUNT8_SYNCBUSY_ENABLE     = 0x2  // Bit ENABLE.
	TC_COUNT8_SYNCBUSY_CTRLB_Pos  = 0x2  // Position of CTRLB field.
	TC_COUNT8_SYNCBUSY_CTRLB_Msk  = 0x4  // Bit mask of CTRLB field.
	TC_COUNT8_SYNCBUSY_CTRLB      = 0x4  // Bit CTRLB.
	TC_COUNT8_SYNCBUSY_STATUS_Pos = 0x3  // Position of STATUS field.
	TC_COUNT8_SYNCBUSY_STATUS_Msk = 0x8  // Bit mask of STATUS field.
	TC_COUNT8_SYNCBUSY_STATUS     = 0x8  // Bit STATUS.
	TC_COUNT8_SYNCBUSY_COUNT_Pos  = 0x4  // Position of COUNT field.
	TC_COUNT8_SYNCBUSY_COUNT_Msk  = 0x10 // Bit mask of COUNT field.
	TC_COUNT8_SYNCBUSY_COUNT      = 0x10 // Bit COUNT.
	TC_COUNT8_SYNCBUSY_PER_Pos    = 0x5  // Position of PER field.
	TC_COUNT8_SYNCBUSY_PER_Msk    = 0x20 // Bit mask of PER field.
	TC_COUNT8_SYNCBUSY_PER        = 0x20 // Bit PER.
	TC_COUNT8_SYNCBUSY_CC0_Pos    = 0x6  // Position of CC0 field.
	TC_COUNT8_SYNCBUSY_CC0_Msk    = 0x40 // Bit mask of CC0 field.
	TC_COUNT8_SYNCBUSY_CC0        = 0x40 // Bit CC0.
	TC_COUNT8_SYNCBUSY_CC1_Pos    = 0x7  // Position of CC1 field.
	TC_COUNT8_SYNCBUSY_CC1_Msk    = 0x80 // Bit mask of CC1 field.
	TC_COUNT8_SYNCBUSY_CC1        = 0x80 // Bit CC1.

	// COUNT: COUNT8 Count
	TC_COUNT8_COUNT_COUNT_Pos = 0x0  // Position of COUNT field.
	TC_COUNT8_COUNT_COUNT_Msk = 0xff // Bit mask of COUNT field.

	// PER: COUNT8 Period
	TC_COUNT8_PER_PER_Pos = 0x0  // Position of PER field.
	TC_COUNT8_PER_PER_Msk = 0xff // Bit mask of PER field.

	// CC: COUNT8 Compare and Capture
	TC_COUNT8_CC_CC_Pos = 0x0  // Position of CC field.
	TC_COUNT8_CC_CC_Msk = 0xff // Bit mask of CC field.

	// PERBUF: COUNT8 Period Buffer
	TC_COUNT8_PERBUF_PERBUF_Pos = 0x0  // Position of PERBUF field.
	TC_COUNT8_PERBUF_PERBUF_Msk = 0xff // Bit mask of PERBUF field.

	// CCBUF: COUNT8 Compare and Capture Buffer
	TC_COUNT8_CCBUF_CCBUF_Pos = 0x0  // Position of CCBUF field.
	TC_COUNT8_CCBUF_CCBUF_Msk = 0xff // Bit mask of CCBUF field.
)

// Bitfields for TC0_COUNT16: Basic Timer Counter - COUNT16
const (
	// CTRLA: Control A
	TC_COUNT16_CTRLA_SWRST_Pos         = 0x0        // Position of SWRST field.
	TC_COUNT16_CTRLA_SWRST_Msk         = 0x1        // Bit mask of SWRST field.
	TC_COUNT16_CTRLA_SWRST             = 0x1        // Bit SWRST.
	TC_COUNT16_CTRLA_ENABLE_Pos        = 0x1        // Position of ENABLE field.
	TC_COUNT16_CTRLA_ENABLE_Msk        = 0x2        // Bit mask of ENABLE field.
	TC_COUNT16_CTRLA_ENABLE            = 0x2        // Bit ENABLE.
	TC_COUNT16_CTRLA_MODE_Pos          = 0x2        // Position of MODE field.
	TC_COUNT16_CTRLA_MODE_Msk          = 0xc        // Bit mask of MODE field.
	TC_COUNT16_CTRLA_MODE_COUNT16      = 0x0        // Counter in 16-bit mode
	TC_COUNT16_CTRLA_MODE_COUNT8       = 0x1        // Counter in 8-bit mode
	TC_COUNT16_CTRLA_MODE_COUNT32      = 0x2        // Counter in 32-bit mode
	TC_COUNT16_CTRLA_PRESCSYNC_Pos     = 0x4        // Position of PRESCSYNC field.
	TC_COUNT16_CTRLA_PRESCSYNC_Msk     = 0x30       // Bit mask of PRESCSYNC field.
	TC_COUNT16_CTRLA_PRESCSYNC_GCLK    = 0x0        // Reload or reset the counter on next generic clock
	TC_COUNT16_CTRLA_PRESCSYNC_PRESC   = 0x1        // Reload or reset the counter on next prescaler clock
	TC_COUNT16_CTRLA_PRESCSYNC_RESYNC  = 0x2        // Reload or reset the counter on next generic clock and reset the prescaler counter
	TC_COUNT16_CTRLA_RUNSTDBY_Pos      = 0x6        // Position of RUNSTDBY field.
	TC_COUNT16_CTRLA_RUNSTDBY_Msk      = 0x40       // Bit mask of RUNSTDBY field.
	TC_COUNT16_CTRLA_RUNSTDBY          = 0x40       // Bit RUNSTDBY.
	TC_COUNT16_CTRLA_ONDEMAND_Pos      = 0x7        // Position of ONDEMAND field.
	TC_COUNT16_CTRLA_ONDEMAND_Msk      = 0x80       // Bit mask of ONDEMAND field.
	TC_COUNT16_CTRLA_ONDEMAND          = 0x80       // Bit ONDEMAND.
	TC_COUNT16_CTRLA_PRESCALER_Pos     = 0x8        // Position of PRESCALER field.
	TC_COUNT16_CTRLA_PRESCALER_Msk     = 0x700      // Bit mask of PRESCALER field.
	TC_COUNT16_CTRLA_PRESCALER_DIV1    = 0x0        // Prescaler: GCLK_TC
	TC_COUNT16_CTRLA_PRESCALER_DIV2    = 0x1        // Prescaler: GCLK_TC/2
	TC_COUNT16_CTRLA_PRESCALER_DIV4    = 0x2        // Prescaler: GCLK_TC/4
	TC_COUNT16_CTRLA_PRESCALER_DIV8    = 0x3        // Prescaler: GCLK_TC/8
	TC_COUNT16_CTRLA_PRESCALER_DIV16   = 0x4        // Prescaler: GCLK_TC/16
	TC_COUNT16_CTRLA_PRESCALER_DIV64   = 0x5        // Prescaler: GCLK_TC/64
	TC_COUNT16_CTRLA_PRESCALER_DIV256  = 0x6        // Prescaler: GCLK_TC/256
	TC_COUNT16_CTRLA_PRESCALER_DIV1024 = 0x7        // Prescaler: GCLK_TC/1024
	TC_COUNT16_CTRLA_ALOCK_Pos         = 0xb        // Position of ALOCK field.
	TC_COUNT16_CTRLA_ALOCK_Msk         = 0x800      // Bit mask of ALOCK field.
	TC_COUNT16_CTRLA_ALOCK             = 0x800      // Bit ALOCK.
	TC_COUNT16_CTRLA_CAPTEN0_Pos       = 0x10       // Position of CAPTEN0 field.
	TC_COUNT16_CTRLA_CAPTEN0_Msk       = 0x10000    // Bit mask of CAPTEN0 field.
	TC_COUNT16_CTRLA_CAPTEN0           = 0x10000    // Bit CAPTEN0.
	TC_COUNT16_CTRLA_CAPTEN1_Pos       = 0x11       // Position of CAPTEN1 field.
	TC_COUNT16_CTRLA_CAPTEN1_Msk       = 0x20000    // Bit mask of CAPTEN1 field.
	TC_COUNT16_CTRLA_CAPTEN1           = 0x20000    // Bit CAPTEN1.
	TC_COUNT16_CTRLA_COPEN0_Pos        = 0x14       // Position of COPEN0 field.
	TC_COUNT16_CTRLA_COPEN0_Msk        = 0x100000   // Bit mask of COPEN0 field.
	TC_COUNT16_CTRLA_COPEN0            = 0x100000   // Bit COPEN0.
	TC_COUNT16_CTRLA_COPEN1_Pos        = 0x15       // Position of COPEN1 field.
	TC_COUNT16_CTRLA_COPEN1_Msk        = 0x200000   // Bit mask of COPEN1 field.
	TC_COUNT16_CTRLA_COPEN1            = 0x200000   // Bit COPEN1.
	TC_COUNT16_CTRLA_CAPTMODE0_Pos     = 0x18       // Position of CAPTMODE0 field.
	TC_COUNT16_CTRLA_CAPTMODE0_Msk     = 0x3000000  // Bit mask of CAPTMODE0 field.
	TC_COUNT16_CTRLA_CAPTMODE0_DEFAULT = 0x0        // Default capture
	TC_COUNT16_CTRLA_CAPTMODE0_CAPTMIN = 0x1        // Minimum capture
	TC_COUNT16_CTRLA_CAPTMODE0_CAPTMAX = 0x2        // Maximum capture
	TC_COUNT16_CTRLA_CAPTMODE1_Pos     = 0x1b       // Position of CAPTMODE1 field.
	TC_COUNT16_CTRLA_CAPTMODE1_Msk     = 0x18000000 // Bit mask of CAPTMODE1 field.
	TC_COUNT16_CTRLA_CAPTMODE1_DEFAULT = 0x0        // Default capture
	TC_COUNT16_CTRLA_CAPTMODE1_CAPTMIN = 0x1        // Minimum capture
	TC_COUNT16_CTRLA_CAPTMODE1_CAPTMAX = 0x2        // Maximum capture

	// CTRLBCLR: Control B Clear
	TC_COUNT16_CTRLBCLR_DIR_Pos       = 0x0  // Position of DIR field.
	TC_COUNT16_CTRLBCLR_DIR_Msk       = 0x1  // Bit mask of DIR field.
	TC_COUNT16_CTRLBCLR_DIR           = 0x1  // Bit DIR.
	TC_COUNT16_CTRLBCLR_LUPD_Pos      = 0x1  // Position of LUPD field.
	TC_COUNT16_CTRLBCLR_LUPD_Msk      = 0x2  // Bit mask of LUPD field.
	TC_COUNT16_CTRLBCLR_LUPD          = 0x2  // Bit LUPD.
	TC_COUNT16_CTRLBCLR_ONESHOT_Pos   = 0x2  // Position of ONESHOT field.
	TC_COUNT16_CTRLBCLR_ONESHOT_Msk   = 0x4  // Bit mask of ONESHOT field.
	TC_COUNT16_CTRLBCLR_ONESHOT       = 0x4  // Bit ONESHOT.
	TC_COUNT16_CTRLBCLR_CMD_Pos       = 0x5  // Position of CMD field.
	TC_COUNT16_CTRLBCLR_CMD_Msk       = 0xe0 // Bit mask of CMD field.
	TC_COUNT16_CTRLBCLR_CMD_NONE      = 0x0  // No action
	TC_COUNT16_CTRLBCLR_CMD_RETRIGGER = 0x1  // Force a start, restart or retrigger
	TC_COUNT16_CTRLBCLR_CMD_STOP      = 0x2  // Force a stop
	TC_COUNT16_CTRLBCLR_CMD_UPDATE    = 0x3  // Force update of double-buffered register
	TC_COUNT16_CTRLBCLR_CMD_READSYNC  = 0x4  // Force a read synchronization of COUNT
	TC_COUNT16_CTRLBCLR_CMD_DMAOS     = 0x5  // One-shot DMA trigger

	// CTRLBSET: Control B Set
	TC_COUNT16_CTRLBSET_DIR_Pos       = 0x0  // Position of DIR field.
	TC_COUNT16_CTRLBSET_DIR_Msk       = 0x1  // Bit mask of DIR field.
	TC_COUNT16_CTRLBSET_DIR           = 0x1  // Bit DIR.
	TC_COUNT16_CTRLBSET_LUPD_Pos      = 0x1  // Position of LUPD field.
	TC_COUNT16_CTRLBSET_LUPD_Msk      = 0x2  // Bit mask of LUPD field.
	TC_COUNT16_CTRLBSET_LUPD          = 0x2  // Bit LUPD.
	TC_COUNT16_CTRLBSET_ONESHOT_Pos   = 0x2  // Position of ONESHOT field.
	TC_COUNT16_CTRLBSET_ONESHOT_Msk   = 0x4  // Bit mask of ONESHOT field.
	TC_COUNT16_CTRLBSET_ONESHOT       = 0x4  // Bit ONESHOT.
	TC_COUNT16_CTRLBSET_CMD_Pos       = 0x5  // Position of CMD field.
	TC_COUNT16_CTRLBSET_CMD_Msk       = 0xe0 // Bit mask of CMD field.
	TC_COUNT16_CTRLBSET_CMD_NONE      = 0x0  // No action
	TC_COUNT16_CTRLBSET_CMD_RETRIGGER = 0x1  // Force a start, restart or retrigger
	TC_COUNT16_CTRLBSET_CMD_STOP      = 0x2  // Force a stop
	TC_COUNT16_CTRLBSET_CMD_UPDATE    = 0x3  // Force update of double-buffered register
	TC_COUNT16_CTRLBSET_CMD_READSYNC  = 0x4  // Force a read synchronization of COUNT
	TC_COUNT16_CTRLBSET_CMD_DMAOS     = 0x5  // One-shot DMA trigger

	// EVCTRL: Event Control
	TC_COUNT16_EVCTRL_EVACT_Pos       = 0x0    // Position of EVACT field.
	TC_COUNT16_EVCTRL_EVACT_Msk       = 0x7    // Bit mask of EVACT field.
	TC_COUNT16_EVCTRL_EVACT_OFF       = 0x0    // Event action disabled
	TC_COUNT16_EVCTRL_EVACT_RETRIGGER = 0x1    // Start, restart or retrigger TC on event
	TC_COUNT16_EVCTRL_EVACT_COUNT     = 0x2    // Count on event
	TC_COUNT16_EVCTRL_EVACT_START     = 0x3    // Start TC on event
	TC_COUNT16_EVCTRL_EVACT_STAMP     = 0x4    // Time stamp capture
	TC_COUNT16_EVCTRL_EVACT_PPW       = 0x5    // Period catured in CC0, pulse width in CC1
	TC_COUNT16_EVCTRL_EVACT_PWP       = 0x6    // Period catured in CC1, pulse width in CC0
	TC_COUNT16_EVCTRL_EVACT_PW        = 0x7    // Pulse width capture
	TC_COUNT16_EVCTRL_TCINV_Pos       = 0x4    // Position of TCINV field.
	TC_COUNT16_EVCTRL_TCINV_Msk       = 0x10   // Bit mask of TCINV field.
	TC_COUNT16_EVCTRL_TCINV           = 0x10   // Bit TCINV.
	TC_COUNT16_EVCTRL_TCEI_Pos        = 0x5    // Position of TCEI field.
	TC_COUNT16_EVCTRL_TCEI_Msk        = 0x20   // Bit mask of TCEI field.
	TC_COUNT16_EVCTRL_TCEI            = 0x20   // Bit TCEI.
	TC_COUNT16_EVCTRL_OVFEO_Pos       = 0x8    // Position of OVFEO field.
	TC_COUNT16_EVCTRL_OVFEO_Msk       = 0x100  // Bit mask of OVFEO field.
	TC_COUNT16_EVCTRL_OVFEO           = 0x100  // Bit OVFEO.
	TC_COUNT16_EVCTRL_MCEO0_Pos       = 0xc    // Position of MCEO0 field.
	TC_COUNT16_EVCTRL_MCEO0_Msk       = 0x1000 // Bit mask of MCEO0 field.
	TC_COUNT16_EVCTRL_MCEO0           = 0x1000 // Bit MCEO0.
	TC_COUNT16_EVCTRL_MCEO1_Pos       = 0xd    // Position of MCEO1 field.
	TC_COUNT16_EVCTRL_MCEO1_Msk       = 0x2000 // Bit mask of MCEO1 field.
	TC_COUNT16_EVCTRL_MCEO1           = 0x2000 // Bit MCEO1.

	// INTENCLR: Interrupt Enable Clear
	TC_COUNT16_INTENCLR_OVF_Pos = 0x0  // Position of OVF field.
	TC_COUNT16_INTENCLR_OVF_Msk = 0x1  // Bit mask of OVF field.
	TC_COUNT16_INTENCLR_OVF     = 0x1  // Bit OVF.
	TC_COUNT16_INTENCLR_ERR_Pos = 0x1  // Position of ERR field.
	TC_COUNT16_INTENCLR_ERR_Msk = 0x2  // Bit mask of ERR field.
	TC_COUNT16_INTENCLR_ERR     = 0x2  // Bit ERR.
	TC_COUNT16_INTENCLR_MC0_Pos = 0x4  // Position of MC0 field.
	TC_COUNT16_INTENCLR_MC0_Msk = 0x10 // Bit mask of MC0 field.
	TC_COUNT16_INTENCLR_MC0     = 0x10 // Bit MC0.
	TC_COUNT16_INTENCLR_MC1_Pos = 0x5  // Position of MC1 field.
	TC_COUNT16_INTENCLR_MC1_Msk = 0x20 // Bit mask of MC1 field.
	TC_COUNT16_INTENCLR_MC1     = 0x20 // Bit MC1.

	// INTENSET: Interrupt Enable Set
	TC_COUNT16_INTENSET_OVF_Pos = 0x0  // Position of OVF field.
	TC_COUNT16_INTENSET_OVF_Msk = 0x1  // Bit mask of OVF field.
	TC_COUNT16_INTENSET_OVF     = 0x1  // Bit OVF.
	TC_COUNT16_INTENSET_ERR_Pos = 0x1  // Position of ERR field.
	TC_COUNT16_INTENSET_ERR_Msk = 0x2  // Bit mask of ERR field.
	TC_COUNT16_INTENSET_ERR     = 0x2  // Bit ERR.
	TC_COUNT16_INTENSET_MC0_Pos = 0x4  // Position of MC0 field.
	TC_COUNT16_INTENSET_MC0_Msk = 0x10 // Bit mask of MC0 field.
	TC_COUNT16_INTENSET_MC0     = 0x10 // Bit MC0.
	TC_COUNT16_INTENSET_MC1_Pos = 0x5  // Position of MC1 field.
	TC_COUNT16_INTENSET_MC1_Msk = 0x20 // Bit mask of MC1 field.
	TC_COUNT16_INTENSET_MC1     = 0x20 // Bit MC1.

	// INTFLAG: Interrupt Flag Status and Clear
	TC_COUNT16_INTFLAG_OVF_Pos = 0x0  // Position of OVF field.
	TC_COUNT16_INTFLAG_OVF_Msk = 0x1  // Bit mask of OVF field.
	TC_COUNT16_INTFLAG_OVF     = 0x1  // Bit OVF.
	TC_COUNT16_INTFLAG_ERR_Pos = 0x1  // Position of ERR field.
	TC_COUNT16_INTFLAG_ERR_Msk = 0x2  // Bit mask of ERR field.
	TC_COUNT16_INTFLAG_ERR     = 0x2  // Bit ERR.
	TC_COUNT16_INTFLAG_MC0_Pos = 0x4  // Position of MC0 field.
	TC_COUNT16_INTFLAG_MC0_Msk = 0x10 // Bit mask of MC0 field.
	TC_COUNT16_INTFLAG_MC0     = 0x10 // Bit MC0.
	TC_COUNT16_INTFLAG_MC1_Pos = 0x5  // Position of MC1 field.
	TC_COUNT16_INTFLAG_MC1_Msk = 0x20 // Bit mask of MC1 field.
	TC_COUNT16_INTFLAG_MC1     = 0x20 // Bit MC1.

	// STATUS: Status
	TC_COUNT16_STATUS_STOP_Pos    = 0x0  // Position of STOP field.
	TC_COUNT16_STATUS_STOP_Msk    = 0x1  // Bit mask of STOP field.
	TC_COUNT16_STATUS_STOP        = 0x1  // Bit STOP.
	TC_COUNT16_STATUS_SLAVE_Pos   = 0x1  // Position of SLAVE field.
	TC_COUNT16_STATUS_SLAVE_Msk   = 0x2  // Bit mask of SLAVE field.
	TC_COUNT16_STATUS_SLAVE       = 0x2  // Bit SLAVE.
	TC_COUNT16_STATUS_PERBUFV_Pos = 0x3  // Position of PERBUFV field.
	TC_COUNT16_STATUS_PERBUFV_Msk = 0x8  // Bit mask of PERBUFV field.
	TC_COUNT16_STATUS_PERBUFV     = 0x8  // Bit PERBUFV.
	TC_COUNT16_STATUS_CCBUFV0_Pos = 0x4  // Position of CCBUFV0 field.
	TC_COUNT16_STATUS_CCBUFV0_Msk = 0x10 // Bit mask of CCBUFV0 field.
	TC_COUNT16_STATUS_CCBUFV0     = 0x10 // Bit CCBUFV0.
	TC_COUNT16_STATUS_CCBUFV1_Pos = 0x5  // Position of CCBUFV1 field.
	TC_COUNT16_STATUS_CCBUFV1_Msk = 0x20 // Bit mask of CCBUFV1 field.
	TC_COUNT16_STATUS_CCBUFV1     = 0x20 // Bit CCBUFV1.

	// WAVE: Waveform Generation Control
	TC_COUNT16_WAVE_WAVEGEN_Pos  = 0x0 // Position of WAVEGEN field.
	TC_COUNT16_WAVE_WAVEGEN_Msk  = 0x3 // Bit mask of WAVEGEN field.
	TC_COUNT16_WAVE_WAVEGEN_NFRQ = 0x0 // Normal frequency
	TC_COUNT16_WAVE_WAVEGEN_MFRQ = 0x1 // Match frequency
	TC_COUNT16_WAVE_WAVEGEN_NPWM = 0x2 // Normal PWM
	TC_COUNT16_WAVE_WAVEGEN_MPWM = 0x3 // Match PWM

	// DRVCTRL: Control C
	TC_COUNT16_DRVCTRL_INVEN0_Pos = 0x0 // Position of INVEN0 field.
	TC_COUNT16_DRVCTRL_INVEN0_Msk = 0x1 // Bit mask of INVEN0 field.
	TC_COUNT16_DRVCTRL_INVEN0     = 0x1 // Bit INVEN0.
	TC_COUNT16_DRVCTRL_INVEN1_Pos = 0x1 // Position of INVEN1 field.
	TC_COUNT16_DRVCTRL_INVEN1_Msk = 0x2 // Bit mask of INVEN1 field.
	TC_COUNT16_DRVCTRL_INVEN1     = 0x2 // Bit INVEN1.

	// DBGCTRL: Debug Control
	TC_COUNT16_DBGCTRL_DBGRUN_Pos = 0x0 // Position of DBGRUN field.
	TC_COUNT16_DBGCTRL_DBGRUN_Msk = 0x1 // Bit mask of DBGRUN field.
	TC_COUNT16_DBGCTRL_DBGRUN     = 0x1 // Bit DBGRUN.

	// SYNCBUSY: Synchronization Status
	TC_COUNT16_SYNCBUSY_SWRST_Pos  = 0x0  // Position of SWRST field.
	TC_COUNT16_SYNCBUSY_SWRST_Msk  = 0x1  // Bit mask of SWRST field.
	TC_COUNT16_SYNCBUSY_SWRST      = 0x1  // Bit SWRST.
	TC_COUNT16_SYNCBUSY_ENABLE_Pos = 0x1  // Position of ENABLE field.
	TC_COUNT16_SYNCBUSY_ENABLE_Msk = 0x2  // Bit mask of ENABLE field.
	TC_COUNT16_SYNCBUSY_ENABLE     = 0x2  // Bit ENABLE.
	TC_COUNT16_SYNCBUSY_CTRLB_Pos  = 0x2  // Position of CTRLB field.
	TC_COUNT16_SYNCBUSY_CTRLB_Msk  = 0x4  // Bit mask of CTRLB field.
	TC_COUNT16_SYNCBUSY_CTRLB      = 0x4  // Bit CTRLB.
	TC_COUNT16_SYNCBUSY_STATUS_Pos = 0x3  // Position of STATUS field.
	TC_COUNT16_SYNCBUSY_STATUS_Msk = 0x8  // Bit mask of STATUS field.
	TC_COUNT16_SYNCBUSY_STATUS     = 0x8  // Bit STATUS.
	TC_COUNT16_SYNCBUSY_COUNT_Pos  = 0x4  // Position of COUNT field.
	TC_COUNT16_SYNCBUSY_COUNT_Msk  = 0x10 // Bit mask of COUNT field.
	TC_COUNT16_SYNCBUSY_COUNT      = 0x10 // Bit COUNT.
	TC_COUNT16_SYNCBUSY_PER_Pos    = 0x5  // Position of PER field.
	TC_COUNT16_SYNCBUSY_PER_Msk    = 0x20 // Bit mask of PER field.
	TC_COUNT16_SYNCBUSY_PER        = 0x20 // Bit PER.
	TC_COUNT16_SYNCBUSY_CC0_Pos    = 0x6  // Position of CC0 field.
	TC_COUNT16_SYNCBUSY_CC0_Msk    = 0x40 // Bit mask of CC0 field.
	TC_COUNT16_SYNCBUSY_CC0        = 0x40 // Bit CC0.
	TC_COUNT16_SYNCBUSY_CC1_Pos    = 0x7  // Position of CC1 field.
	TC_COUNT16_SYNCBUSY_CC1_Msk    = 0x80 // Bit mask of CC1 field.
	TC_COUNT16_SYNCBUSY_CC1        = 0x80 // Bit CC1.

	// COUNT: COUNT16 Count
	TC_COUNT16_COUNT_COUNT_Pos = 0x0    // Position of COUNT field.
	TC_COUNT16_COUNT_COUNT_Msk = 0xffff // Bit mask of COUNT field.

	// CC: COUNT16 Compare and Capture
	TC_COUNT16_CC_CC_Pos = 0x0    // Position of CC field.
	TC_COUNT16_CC_CC_Msk = 0xffff // Bit mask of CC field.

	// CCBUF: COUNT16 Compare and Capture Buffer
	TC_COUNT16_CCBUF_CCBUF_Pos = 0x0    // Position of CCBUF field.
	TC_COUNT16_CCBUF_CCBUF_Msk = 0xffff // Bit mask of CCBUF field.
)

// Bitfields for TC0_COUNT32: Basic Timer Counter - COUNT32
const (
	// CTRLA: Control A
	TC_COUNT32_CTRLA_SWRST_Pos         = 0x0        // Position of SWRST field.
	TC_COUNT32_CTRLA_SWRST_Msk         = 0x1        // Bit mask of SWRST field.
	TC_COUNT32_CTRLA_SWRST             = 0x1        // Bit SWRST.
	TC_COUNT32_CTRLA_ENABLE_Pos        = 0x1        // Position of ENABLE field.
	TC_COUNT32_CTRLA_ENABLE_Msk        = 0x2        // Bit mask of ENABLE field.
	TC_COUNT32_CTRLA_ENABLE            = 0x2        // Bit ENABLE.
	TC_COUNT32_CTRLA_MODE_Pos          = 0x2        // Position of MODE field.
	TC_COUNT32_CTRLA_MODE_Msk          = 0xc        // Bit mask of MODE field.
	TC_COUNT32_CTRLA_MODE_COUNT16      = 0x0        // Counter in 16-bit mode
	TC_COUNT32_CTRLA_MODE_COUNT8       = 0x1        // Counter in 8-bit mode
	TC_COUNT32_CTRLA_MODE_COUNT32      = 0x2        // Counter in 32-bit mode
	TC_COUNT32_CTRLA_PRESCSYNC_Pos     = 0x4        // Position of PRESCSYNC field.
	TC_COUNT32_CTRLA_PRESCSYNC_Msk     = 0x30       // Bit mask of PRESCSYNC field.
	TC_COUNT32_CTRLA_PRESCSYNC_GCLK    = 0x0        // Reload or reset the counter on next generic clock
	TC_COUNT32_CTRLA_PRESCSYNC_PRESC   = 0x1        // Reload or reset the counter on next prescaler clock
	TC_COUNT32_CTRLA_PRESCSYNC_RESYNC  = 0x2        // Reload or reset the counter on next generic clock and reset the prescaler counter
	TC_COUNT32_CTRLA_RUNSTDBY_Pos      = 0x6        // Position of RUNSTDBY field.
	TC_COUNT32_CTRLA_RUNSTDBY_Msk      = 0x40       // Bit mask of RUNSTDBY field.
	TC_COUNT32_CTRLA_RUNSTDBY          = 0x40       // Bit RUNSTDBY.
	TC_COUNT32_CTRLA_ONDEMAND_Pos      = 0x7        // Position of ONDEMAND field.
	TC_COUNT32_CTRLA_ONDEMAND_Msk      = 0x80       // Bit mask of ONDEMAND field.
	TC_COUNT32_CTRLA_ONDEMAND          = 0x80       // Bit ONDEMAND.
	TC_COUNT32_CTRLA_PRESCALER_Pos     = 0x8        // Position of PRESCALER field.
	TC_COUNT32_CTRLA_PRESCALER_Msk     = 0x700      // Bit mask of PRESCALER field.
	TC_COUNT32_CTRLA_PRESCALER_DIV1    = 0x0        // Prescaler: GCLK_TC
	TC_COUNT32_CTRLA_PRESCALER_DIV2    = 0x1        // Prescaler: GCLK_TC/2
	TC_COUNT32_CTRLA_PRESCALER_DIV4    = 0x2        // Prescaler: GCLK_TC/4
	TC_COUNT32_CTRLA_PRESCALER_DIV8    = 0x3        // Prescaler: GCLK_TC/8
	TC_COUNT32_CTRLA_PRESCALER_DIV16   = 0x4        // Prescaler: GCLK_TC/16
	TC_COUNT32_CTRLA_PRESCALER_DIV64   = 0x5        // Prescaler: GCLK_TC/64
	TC_COUNT32_CTRLA_PRESCALER_DIV256  = 0x6        // Prescaler: GCLK_TC/256
	TC_COUNT32_CTRLA_PRESCALER_DIV1024 = 0x7        // Prescaler: GCLK_TC/1024
	TC_COUNT32_CTRLA_ALOCK_Pos         = 0xb        // Position of ALOCK field.
	TC_COUNT32_CTRLA_ALOCK_Msk         = 0x800      // Bit mask of ALOCK field.
	TC_COUNT32_CTRLA_ALOCK             = 0x800      // Bit ALOCK.
	TC_COUNT32_CTRLA_CAPTEN0_Pos       = 0x10       // Position of CAPTEN0 field.
	TC_COUNT32_CTRLA_CAPTEN0_Msk       = 0x10000    // Bit mask of CAPTEN0 field.
	TC_COUNT32_CTRLA_CAPTEN0           = 0x10000    // Bit CAPTEN0.
	TC_COUNT32_CTRLA_CAPTEN1_Pos       = 0x11       // Position of CAPTEN1 field.
	TC_COUNT32_CTRLA_CAPTEN1_Msk       = 0x20000    // Bit mask of CAPTEN1 field.
	TC_COUNT32_CTRLA_CAPTEN1           = 0x20000    // Bit CAPTEN1.
	TC_COUNT32_CTRLA_COPEN0_Pos        = 0x14       // Position of COPEN0 field.
	TC_COUNT32_CTRLA_COPEN0_Msk        = 0x100000   // Bit mask of COPEN0 field.
	TC_COUNT32_CTRLA_COPEN0            = 0x100000   // Bit COPEN0.
	TC_COUNT32_CTRLA_COPEN1_Pos        = 0x15       // Position of COPEN1 field.
	TC_COUNT32_CTRLA_COPEN1_Msk        = 0x200000   // Bit mask of COPEN1 field.
	TC_COUNT32_CTRLA_COPEN1            = 0x200000   // Bit COPEN1.
	TC_COUNT32_CTRLA_CAPTMODE0_Pos     = 0x18       // Position of CAPTMODE0 field.
	TC_COUNT32_CTRLA_CAPTMODE0_Msk     = 0x3000000  // Bit mask of CAPTMODE0 field.
	TC_COUNT32_CTRLA_CAPTMODE0_DEFAULT = 0x0        // Default capture
	TC_COUNT32_CTRLA_CAPTMODE0_CAPTMIN = 0x1        // Minimum capture
	TC_COUNT32_CTRLA_CAPTMODE0_CAPTMAX = 0x2        // Maximum capture
	TC_COUNT32_CTRLA_CAPTMODE1_Pos     = 0x1b       // Position of CAPTMODE1 field.
	TC_COUNT32_CTRLA_CAPTMODE1_Msk     = 0x18000000 // Bit mask of CAPTMODE1 field.
	TC_COUNT32_CTRLA_CAPTMODE1_DEFAULT = 0x0        // Default capture
	TC_COUNT32_CTRLA_CAPTMODE1_CAPTMIN = 0x1        // Minimum capture
	TC_COUNT32_CTRLA_CAPTMODE1_CAPTMAX = 0x2        // Maximum capture

	// CTRLBCLR: Control B Clear
	TC_COUNT32_CTRLBCLR_DIR_Pos       = 0x0  // Position of DIR field.
	TC_COUNT32_CTRLBCLR_DIR_Msk       = 0x1  // Bit mask of DIR field.
	TC_COUNT32_CTRLBCLR_DIR           = 0x1  // Bit DIR.
	TC_COUNT32_CTRLBCLR_LUPD_Pos      = 0x1  // Position of LUPD field.
	TC_COUNT32_CTRLBCLR_LUPD_Msk      = 0x2  // Bit mask of LUPD field.
	TC_COUNT32_CTRLBCLR_LUPD          = 0x2  // Bit LUPD.
	TC_COUNT32_CTRLBCLR_ONESHOT_Pos   = 0x2  // Position of ONESHOT field.
	TC_COUNT32_CTRLBCLR_ONESHOT_Msk   = 0x4  // Bit mask of ONESHOT field.
	TC_COUNT32_CTRLBCLR_ONESHOT       = 0x4  // Bit ONESHOT.
	TC_COUNT32_CTRLBCLR_CMD_Pos       = 0x5  // Position of CMD field.
	TC_COUNT32_CTRLBCLR_CMD_Msk       = 0xe0 // Bit mask of CMD field.
	TC_COUNT32_CTRLBCLR_CMD_NONE      = 0x0  // No action
	TC_COUNT32_CTRLBCLR_CMD_RETRIGGER = 0x1  // Force a start, restart or retrigger
	TC_COUNT32_CTRLBCLR_CMD_STOP      = 0x2  // Force a stop
	TC_COUNT32_CTRLBCLR_CMD_UPDATE    = 0x3  // Force update of double-buffered register
	TC_COUNT32_CTRLBCLR_CMD_READSYNC  = 0x4  // Force a read synchronization of COUNT
	TC_COUNT32_CTRLBCLR_CMD_DMAOS     = 0x5  // One-shot DMA trigger

	// CTRLBSET: Control B Set
	TC_COUNT32_CTRLBSET_DIR_Pos       = 0x0  // Position of DIR field.
	TC_COUNT32_CTRLBSET_DIR_Msk       = 0x1  // Bit mask of DIR field.
	TC_COUNT32_CTRLBSET_DIR           = 0x1  // Bit DIR.
	TC_COUNT32_CTRLBSET_LUPD_Pos      = 0x1  // Position of LUPD field.
	TC_COUNT32_CTRLBSET_LUPD_Msk      = 0x2  // Bit mask of LUPD field.
	TC_COUNT32_CTRLBSET_LUPD          = 0x2  // Bit LUPD.
	TC_COUNT32_CTRLBSET_ONESHOT_Pos   = 0x2  // Position of ONESHOT field.
	TC_COUNT32_CTRLBSET_ONESHOT_Msk   = 0x4  // Bit mask of ONESHOT field.
	TC_COUNT32_CTRLBSET_ONESHOT       = 0x4  // Bit ONESHOT.
	TC_COUNT32_CTRLBSET_CMD_Pos       = 0x5  // Position of CMD field.
	TC_COUNT32_CTRLBSET_CMD_Msk       = 0xe0 // Bit mask of CMD field.
	TC_COUNT32_CTRLBSET_CMD_NONE      = 0x0  // No action
	TC_COUNT32_CTRLBSET_CMD_RETRIGGER = 0x1  // Force a start, restart or retrigger
	TC_COUNT32_CTRLBSET_CMD_STOP      = 0x2  // Force a stop
	TC_COUNT32_CTRLBSET_CMD_UPDATE    = 0x3  // Force update of double-buffered register
	TC_COUNT32_CTRLBSET_CMD_READSYNC  = 0x4  // Force a read synchronization of COUNT
	TC_COUNT32_CTRLBSET_CMD_DMAOS     = 0x5  // One-shot DMA trigger

	// EVCTRL: Event Control
	TC_COUNT32_EVCTRL_EVACT_Pos       = 0x0    // Position of EVACT field.
	TC_COUNT32_EVCTRL_EVACT_Msk       = 0x7    // Bit mask of EVACT field.
	TC_COUNT32_EVCTRL_EVACT_OFF       = 0x0    // Event action disabled
	TC_COUNT32_EVCTRL_EVACT_RETRIGGER = 0x1    // Start, restart or retrigger TC on event
	TC_COUNT32_EVCTRL_EVACT_COUNT     = 0x2    // Count on event
	TC_COUNT32_EVCTRL_EVACT_START     = 0x3    // Start TC on event
	TC_COUNT32_EVCTRL_EVACT_STAMP     = 0x4    // Time stamp capture
	TC_COUNT32_EVCTRL_EVACT_PPW       = 0x5    // Period catured in CC0, pulse width in CC1
	TC_COUNT32_EVCTRL_EVACT_PWP       = 0x6    // Period catured in CC1, pulse width in CC0
	TC_COUNT32_EVCTRL_EVACT_PW        = 0x7    // Pulse width capture
	TC_COUNT32_EVCTRL_TCINV_Pos       = 0x4    // Position of TCINV field.
	TC_COUNT32_EVCTRL_TCINV_Msk       = 0x10   // Bit mask of TCINV field.
	TC_COUNT32_EVCTRL_TCINV           = 0x10   // Bit TCINV.
	TC_COUNT32_EVCTRL_TCEI_Pos        = 0x5    // Position of TCEI field.
	TC_COUNT32_EVCTRL_TCEI_Msk        = 0x20   // Bit mask of TCEI field.
	TC_COUNT32_EVCTRL_TCEI            = 0x20   // Bit TCEI.
	TC_COUNT32_EVCTRL_OVFEO_Pos       = 0x8    // Position of OVFEO field.
	TC_COUNT32_EVCTRL_OVFEO_Msk       = 0x100  // Bit mask of OVFEO field.
	TC_COUNT32_EVCTRL_OVFEO           = 0x100  // Bit OVFEO.
	TC_COUNT32_EVCTRL_MCEO0_Pos       = 0xc    // Position of MCEO0 field.
	TC_COUNT32_EVCTRL_MCEO0_Msk       = 0x1000 // Bit mask of MCEO0 field.
	TC_COUNT32_EVCTRL_MCEO0           = 0x1000 // Bit MCEO0.
	TC_COUNT32_EVCTRL_MCEO1_Pos       = 0xd    // Position of MCEO1 field.
	TC_COUNT32_EVCTRL_MCEO1_Msk       = 0x2000 // Bit mask of MCEO1 field.
	TC_COUNT32_EVCTRL_MCEO1           = 0x2000 // Bit MCEO1.

	// INTENCLR: Interrupt Enable Clear
	TC_COUNT32_INTENCLR_OVF_Pos = 0x0  // Position of OVF field.
	TC_COUNT32_INTENCLR_OVF_Msk = 0x1  // Bit mask of OVF field.
	TC_COUNT32_INTENCLR_OVF     = 0x1  // Bit OVF.
	TC_COUNT32_INTENCLR_ERR_Pos = 0x1  // Position of ERR field.
	TC_COUNT32_INTENCLR_ERR_Msk = 0x2  // Bit mask of ERR field.
	TC_COUNT32_INTENCLR_ERR     = 0x2  // Bit ERR.
	TC_COUNT32_INTENCLR_MC0_Pos = 0x4  // Position of MC0 field.
	TC_COUNT32_INTENCLR_MC0_Msk = 0x10 // Bit mask of MC0 field.
	TC_COUNT32_INTENCLR_MC0     = 0x10 // Bit MC0.
	TC_COUNT32_INTENCLR_MC1_Pos = 0x5  // Position of MC1 field.
	TC_COUNT32_INTENCLR_MC1_Msk = 0x20 // Bit mask of MC1 field.
	TC_COUNT32_INTENCLR_MC1     = 0x20 // Bit MC1.

	// INTENSET: Interrupt Enable Set
	TC_COUNT32_INTENSET_OVF_Pos = 0x0  // Position of OVF field.
	TC_COUNT32_INTENSET_OVF_Msk = 0x1  // Bit mask of OVF field.
	TC_COUNT32_INTENSET_OVF     = 0x1  // Bit OVF.
	TC_COUNT32_INTENSET_ERR_Pos = 0x1  // Position of ERR field.
	TC_COUNT32_INTENSET_ERR_Msk = 0x2  // Bit mask of ERR field.
	TC_COUNT32_INTENSET_ERR     = 0x2  // Bit ERR.
	TC_COUNT32_INTENSET_MC0_Pos = 0x4  // Position of MC0 field.
	TC_COUNT32_INTENSET_MC0_Msk = 0x10 // Bit mask of MC0 field.
	TC_COUNT32_INTENSET_MC0     = 0x10 // Bit MC0.
	TC_COUNT32_INTENSET_MC1_Pos = 0x5  // Position of MC1 field.
	TC_COUNT32_INTENSET_MC1_Msk = 0x20 // Bit mask of MC1 field.
	TC_COUNT32_INTENSET_MC1     = 0x20 // Bit MC1.

	// INTFLAG: Interrupt Flag Status and Clear
	TC_COUNT32_INTFLAG_OVF_Pos = 0x0  // Position of OVF field.
	TC_COUNT32_INTFLAG_OVF_Msk = 0x1  // Bit mask of OVF field.
	TC_COUNT32_INTFLAG_OVF     = 0x1  // Bit OVF.
	TC_COUNT32_INTFLAG_ERR_Pos = 0x1  // Position of ERR field.
	TC_COUNT32_INTFLAG_ERR_Msk = 0x2  // Bit mask of ERR field.
	TC_COUNT32_INTFLAG_ERR     = 0x2  // Bit ERR.
	TC_COUNT32_INTFLAG_MC0_Pos = 0x4  // Position of MC0 field.
	TC_COUNT32_INTFLAG_MC0_Msk = 0x10 // Bit mask of MC0 field.
	TC_COUNT32_INTFLAG_MC0     = 0x10 // Bit MC0.
	TC_COUNT32_INTFLAG_MC1_Pos = 0x5  // Position of MC1 field.
	TC_COUNT32_INTFLAG_MC1_Msk = 0x20 // Bit mask of MC1 field.
	TC_COUNT32_INTFLAG_MC1     = 0x20 // Bit MC1.

	// STATUS: Status
	TC_COUNT32_STATUS_STOP_Pos    = 0x0  // Position of STOP field.
	TC_COUNT32_STATUS_STOP_Msk    = 0x1  // Bit mask of STOP field.
	TC_COUNT32_STATUS_STOP        = 0x1  // Bit STOP.
	TC_COUNT32_STATUS_SLAVE_Pos   = 0x1  // Position of SLAVE field.
	TC_COUNT32_STATUS_SLAVE_Msk   = 0x2  // Bit mask of SLAVE field.
	TC_COUNT32_STATUS_SLAVE       = 0x2  // Bit SLAVE.
	TC_COUNT32_STATUS_PERBUFV_Pos = 0x3  // Position of PERBUFV field.
	TC_COUNT32_STATUS_PERBUFV_Msk = 0x8  // Bit mask of PERBUFV field.
	TC_COUNT32_STATUS_PERBUFV     = 0x8  // Bit PERBUFV.
	TC_COUNT32_STATUS_CCBUFV0_Pos = 0x4  // Position of CCBUFV0 field.
	TC_COUNT32_STATUS_CCBUFV0_Msk = 0x10 // Bit mask of CCBUFV0 field.
	TC_COUNT32_STATUS_CCBUFV0     = 0x10 // Bit CCBUFV0.
	TC_COUNT32_STATUS_CCBUFV1_Pos = 0x5  // Position of CCBUFV1 field.
	TC_COUNT32_STATUS_CCBUFV1_Msk = 0x20 // Bit mask of CCBUFV1 field.
	TC_COUNT32_STATUS_CCBUFV1     = 0x20 // Bit CCBUFV1.

	// WAVE: Waveform Generation Control
	TC_COUNT32_WAVE_WAVEGEN_Pos  = 0x0 // Position of WAVEGEN field.
	TC_COUNT32_WAVE_WAVEGEN_Msk  = 0x3 // Bit mask of WAVEGEN field.
	TC_COUNT32_WAVE_WAVEGEN_NFRQ = 0x0 // Normal frequency
	TC_COUNT32_WAVE_WAVEGEN_MFRQ = 0x1 // Match frequency
	TC_COUNT32_WAVE_WAVEGEN_NPWM = 0x2 // Normal PWM
	TC_COUNT32_WAVE_WAVEGEN_MPWM = 0x3 // Match PWM

	// DRVCTRL: Control C
	TC_COUNT32_DRVCTRL_INVEN0_Pos = 0x0 // Position of INVEN0 field.
	TC_COUNT32_DRVCTRL_INVEN0_Msk = 0x1 // Bit mask of INVEN0 field.
	TC_COUNT32_DRVCTRL_INVEN0     = 0x1 // Bit INVEN0.
	TC_COUNT32_DRVCTRL_INVEN1_Pos = 0x1 // Position of INVEN1 field.
	TC_COUNT32_DRVCTRL_INVEN1_Msk = 0x2 // Bit mask of INVEN1 field.
	TC_COUNT32_DRVCTRL_INVEN1     = 0x2 // Bit INVEN1.

	// DBGCTRL: Debug Control
	TC_COUNT32_DBGCTRL_DBGRUN_Pos = 0x0 // Position of DBGRUN field.
	TC_COUNT32_DBGCTRL_DBGRUN_Msk = 0x1 // Bit mask of DBGRUN field.
	TC_COUNT32_DBGCTRL_DBGRUN     = 0x1 // Bit DBGRUN.

	// SYNCBUSY: Synchronization Status
	TC_COUNT32_SYNCBUSY_SWRST_Pos  = 0x0  // Position of SWRST field.
	TC_COUNT32_SYNCBUSY_SWRST_Msk  = 0x1  // Bit mask of SWRST field.
	TC_COUNT32_SYNCBUSY_SWRST      = 0x1  // Bit SWRST.
	TC_COUNT32_SYNCBUSY_ENABLE_Pos = 0x1  // Position of ENABLE field.
	TC_COUNT32_SYNCBUSY_ENABLE_Msk = 0x2  // Bit mask of ENABLE field.
	TC_COUNT32_SYNCBUSY_ENABLE     = 0x2  // Bit ENABLE.
	TC_COUNT32_SYNCBUSY_CTRLB_Pos  = 0x2  // Position of CTRLB field.
	TC_COUNT32_SYNCBUSY_CTRLB_Msk  = 0x4  // Bit mask of CTRLB field.
	TC_COUNT32_SYNCBUSY_CTRLB      = 0x4  // Bit CTRLB.
	TC_COUNT32_SYNCBUSY_STATUS_Pos = 0x3  // Position of STATUS field.
	TC_COUNT32_SYNCBUSY_STATUS_Msk = 0x8  // Bit mask of STATUS field.
	TC_COUNT32_SYNCBUSY_STATUS     = 0x8  // Bit STATUS.
	TC_COUNT32_SYNCBUSY_COUNT_Pos  = 0x4  // Position of COUNT field.
	TC_COUNT32_SYNCBUSY_COUNT_Msk  = 0x10 // Bit mask of COUNT field.
	TC_COUNT32_SYNCBUSY_COUNT      = 0x10 // Bit COUNT.
	TC_COUNT32_SYNCBUSY_PER_Pos    = 0x5  // Position of PER field.
	TC_COUNT32_SYNCBUSY_PER_Msk    = 0x20 // Bit mask of PER field.
	TC_COUNT32_SYNCBUSY_PER        = 0x20 // Bit PER.
	TC_COUNT32_SYNCBUSY_CC0_Pos    = 0x6  // Position of CC0 field.
	TC_COUNT32_SYNCBUSY_CC0_Msk    = 0x40 // Bit mask of CC0 field.
	TC_COUNT32_SYNCBUSY_CC0        = 0x40 // Bit CC0.
	TC_COUNT32_SYNCBUSY_CC1_Pos    = 0x7  // Position of CC1 field.
	TC_COUNT32_SYNCBUSY_CC1_Msk    = 0x80 // Bit mask of CC1 field.
	TC_COUNT32_SYNCBUSY_CC1        = 0x80 // Bit CC1.

	// COUNT: COUNT32 Count
	TC_COUNT32_COUNT_COUNT_Pos = 0x0        // Position of COUNT field.
	TC_COUNT32_COUNT_COUNT_Msk = 0xffffffff // Bit mask of COUNT field.

	// CC: COUNT32 Compare and Capture
	TC_COUNT32_CC_CC_Pos = 0x0        // Position of CC field.
	TC_COUNT32_CC_CC_Msk = 0xffffffff // Bit mask of CC field.

	// CCBUF: COUNT32 Compare and Capture Buffer
	TC_COUNT32_CCBUF_CCBUF_Pos = 0x0        // Position of CCBUF field.
	TC_COUNT32_CCBUF_CCBUF_Msk = 0xffffffff // Bit mask of CCBUF field.
)

// Bitfields for TCC0: Timer Counter Control
const (
	// CTRLA: Control A
	TCC_CTRLA_SWRST_Pos         = 0x0        // Position of SWRST field.
	TCC_CTRLA_SWRST_Msk         = 0x1        // Bit mask of SWRST field.
	TCC_CTRLA_SWRST             = 0x1        // Bit SWRST.
	TCC_CTRLA_ENABLE_Pos        = 0x1        // Position of ENABLE field.
	TCC_CTRLA_ENABLE_Msk        = 0x2        // Bit mask of ENABLE field.
	TCC_CTRLA_ENABLE            = 0x2        // Bit ENABLE.
	TCC_CTRLA_RESOLUTION_Pos    = 0x5        // Position of RESOLUTION field.
	TCC_CTRLA_RESOLUTION_Msk    = 0x60       // Bit mask of RESOLUTION field.
	TCC_CTRLA_RESOLUTION_NONE   = 0x0        // Dithering is disabled
	TCC_CTRLA_RESOLUTION_DITH4  = 0x1        // Dithering is done every 16 PWM frames
	TCC_CTRLA_RESOLUTION_DITH5  = 0x2        // Dithering is done every 32 PWM frames
	TCC_CTRLA_RESOLUTION_DITH6  = 0x3        // Dithering is done every 64 PWM frames
	TCC_CTRLA_PRESCALER_Pos     = 0x8        // Position of PRESCALER field.
	TCC_CTRLA_PRESCALER_Msk     = 0x700      // Bit mask of PRESCALER field.
	TCC_CTRLA_PRESCALER_DIV1    = 0x0        // No division
	TCC_CTRLA_PRESCALER_DIV2    = 0x1        // Divide by 2
	TCC_CTRLA_PRESCALER_DIV4    = 0x2        // Divide by 4
	TCC_CTRLA_PRESCALER_DIV8    = 0x3        // Divide by 8
	TCC_CTRLA_PRESCALER_DIV16   = 0x4        // Divide by 16
	TCC_CTRLA_PRESCALER_DIV64   = 0x5        // Divide by 64
	TCC_CTRLA_PRESCALER_DIV256  = 0x6        // Divide by 256
	TCC_CTRLA_PRESCALER_DIV1024 = 0x7        // Divide by 1024
	TCC_CTRLA_RUNSTDBY_Pos      = 0xb        // Position of RUNSTDBY field.
	TCC_CTRLA_RUNSTDBY_Msk      = 0x800      // Bit mask of RUNSTDBY field.
	TCC_CTRLA_RUNSTDBY          = 0x800      // Bit RUNSTDBY.
	TCC_CTRLA_PRESCSYNC_Pos     = 0xc        // Position of PRESCSYNC field.
	TCC_CTRLA_PRESCSYNC_Msk     = 0x3000     // Bit mask of PRESCSYNC field.
	TCC_CTRLA_PRESCSYNC_GCLK    = 0x0        // Reload or reset counter on next GCLK
	TCC_CTRLA_PRESCSYNC_PRESC   = 0x1        // Reload or reset counter on next prescaler clock
	TCC_CTRLA_PRESCSYNC_RESYNC  = 0x2        // Reload or reset counter on next GCLK and reset prescaler counter
	TCC_CTRLA_ALOCK_Pos         = 0xe        // Position of ALOCK field.
	TCC_CTRLA_ALOCK_Msk         = 0x4000     // Bit mask of ALOCK field.
	TCC_CTRLA_ALOCK             = 0x4000     // Bit ALOCK.
	TCC_CTRLA_MSYNC_Pos         = 0xf        // Position of MSYNC field.
	TCC_CTRLA_MSYNC_Msk         = 0x8000     // Bit mask of MSYNC field.
	TCC_CTRLA_MSYNC             = 0x8000     // Bit MSYNC.
	TCC_CTRLA_DMAOS_Pos         = 0x17       // Position of DMAOS field.
	TCC_CTRLA_DMAOS_Msk         = 0x800000   // Bit mask of DMAOS field.
	TCC_CTRLA_DMAOS             = 0x800000   // Bit DMAOS.
	TCC_CTRLA_CPTEN0_Pos        = 0x18       // Position of CPTEN0 field.
	TCC_CTRLA_CPTEN0_Msk        = 0x1000000  // Bit mask of CPTEN0 field.
	TCC_CTRLA_CPTEN0            = 0x1000000  // Bit CPTEN0.
	TCC_CTRLA_CPTEN1_Pos        = 0x19       // Position of CPTEN1 field.
	TCC_CTRLA_CPTEN1_Msk        = 0x2000000  // Bit mask of CPTEN1 field.
	TCC_CTRLA_CPTEN1            = 0x2000000  // Bit CPTEN1.
	TCC_CTRLA_CPTEN2_Pos        = 0x1a       // Position of CPTEN2 field.
	TCC_CTRLA_CPTEN2_Msk        = 0x4000000  // Bit mask of CPTEN2 field.
	TCC_CTRLA_CPTEN2            = 0x4000000  // Bit CPTEN2.
	TCC_CTRLA_CPTEN3_Pos        = 0x1b       // Position of CPTEN3 field.
	TCC_CTRLA_CPTEN3_Msk        = 0x8000000  // Bit mask of CPTEN3 field.
	TCC_CTRLA_CPTEN3            = 0x8000000  // Bit CPTEN3.
	TCC_CTRLA_CPTEN4_Pos        = 0x1c       // Position of CPTEN4 field.
	TCC_CTRLA_CPTEN4_Msk        = 0x10000000 // Bit mask of CPTEN4 field.
	TCC_CTRLA_CPTEN4            = 0x10000000 // Bit CPTEN4.
	TCC_CTRLA_CPTEN5_Pos        = 0x1d       // Position of CPTEN5 field.
	TCC_CTRLA_CPTEN5_Msk        = 0x20000000 // Bit mask of CPTEN5 field.
	TCC_CTRLA_CPTEN5            = 0x20000000 // Bit CPTEN5.

	// CTRLBCLR: Control B Clear
	TCC_CTRLBCLR_DIR_Pos        = 0x0  // Position of DIR field.
	TCC_CTRLBCLR_DIR_Msk        = 0x1  // Bit mask of DIR field.
	TCC_CTRLBCLR_DIR            = 0x1  // Bit DIR.
	TCC_CTRLBCLR_LUPD_Pos       = 0x1  // Position of LUPD field.
	TCC_CTRLBCLR_LUPD_Msk       = 0x2  // Bit mask of LUPD field.
	TCC_CTRLBCLR_LUPD           = 0x2  // Bit LUPD.
	TCC_CTRLBCLR_ONESHOT_Pos    = 0x2  // Position of ONESHOT field.
	TCC_CTRLBCLR_ONESHOT_Msk    = 0x4  // Bit mask of ONESHOT field.
	TCC_CTRLBCLR_ONESHOT        = 0x4  // Bit ONESHOT.
	TCC_CTRLBCLR_IDXCMD_Pos     = 0x3  // Position of IDXCMD field.
	TCC_CTRLBCLR_IDXCMD_Msk     = 0x18 // Bit mask of IDXCMD field.
	TCC_CTRLBCLR_IDXCMD_DISABLE = 0x0  // Command disabled: Index toggles between cycles A and B
	TCC_CTRLBCLR_IDXCMD_SET     = 0x1  // Set index: cycle B will be forced in the next cycle
	TCC_CTRLBCLR_IDXCMD_CLEAR   = 0x2  // Clear index: cycle A will be forced in the next cycle
	TCC_CTRLBCLR_IDXCMD_HOLD    = 0x3  // Hold index: the next cycle will be the same as the current cycle
	TCC_CTRLBCLR_CMD_Pos        = 0x5  // Position of CMD field.
	TCC_CTRLBCLR_CMD_Msk        = 0xe0 // Bit mask of CMD field.
	TCC_CTRLBCLR_CMD_NONE       = 0x0  // No action
	TCC_CTRLBCLR_CMD_RETRIGGER  = 0x1  // Clear start, restart or retrigger
	TCC_CTRLBCLR_CMD_STOP       = 0x2  // Force stop
	TCC_CTRLBCLR_CMD_UPDATE     = 0x3  // Force update or double buffered registers
	TCC_CTRLBCLR_CMD_READSYNC   = 0x4  // Force COUNT read synchronization
	TCC_CTRLBCLR_CMD_DMAOS      = 0x5  // One-shot DMA trigger

	// CTRLBSET: Control B Set
	TCC_CTRLBSET_DIR_Pos        = 0x0  // Position of DIR field.
	TCC_CTRLBSET_DIR_Msk        = 0x1  // Bit mask of DIR field.
	TCC_CTRLBSET_DIR            = 0x1  // Bit DIR.
	TCC_CTRLBSET_LUPD_Pos       = 0x1  // Position of LUPD field.
	TCC_CTRLBSET_LUPD_Msk       = 0x2  // Bit mask of LUPD field.
	TCC_CTRLBSET_LUPD           = 0x2  // Bit LUPD.
	TCC_CTRLBSET_ONESHOT_Pos    = 0x2  // Position of ONESHOT field.
	TCC_CTRLBSET_ONESHOT_Msk    = 0x4  // Bit mask of ONESHOT field.
	TCC_CTRLBSET_ONESHOT        = 0x4  // Bit ONESHOT.
	TCC_CTRLBSET_IDXCMD_Pos     = 0x3  // Position of IDXCMD field.
	TCC_CTRLBSET_IDXCMD_Msk     = 0x18 // Bit mask of IDXCMD field.
	TCC_CTRLBSET_IDXCMD_DISABLE = 0x0  // Command disabled: Index toggles between cycles A and B
	TCC_CTRLBSET_IDXCMD_SET     = 0x1  // Set index: cycle B will be forced in the next cycle
	TCC_CTRLBSET_IDXCMD_CLEAR   = 0x2  // Clear index: cycle A will be forced in the next cycle
	TCC_CTRLBSET_IDXCMD_HOLD    = 0x3  // Hold index: the next cycle will be the same as the current cycle
	TCC_CTRLBSET_CMD_Pos        = 0x5  // Position of CMD field.
	TCC_CTRLBSET_CMD_Msk        = 0xe0 // Bit mask of CMD field.
	TCC_CTRLBSET_CMD_NONE       = 0x0  // No action
	TCC_CTRLBSET_CMD_RETRIGGER  = 0x1  // Clear start, restart or retrigger
	TCC_CTRLBSET_CMD_STOP       = 0x2  // Force stop
	TCC_CTRLBSET_CMD_UPDATE     = 0x3  // Force update or double buffered registers
	TCC_CTRLBSET_CMD_READSYNC   = 0x4  // Force COUNT read synchronization
	TCC_CTRLBSET_CMD_DMAOS      = 0x5  // One-shot DMA trigger

	// SYNCBUSY: Synchronization Busy
	TCC_SYNCBUSY_SWRST_Pos  = 0x0    // Position of SWRST field.
	TCC_SYNCBUSY_SWRST_Msk  = 0x1    // Bit mask of SWRST field.
	TCC_SYNCBUSY_SWRST      = 0x1    // Bit SWRST.
	TCC_SYNCBUSY_ENABLE_Pos = 0x1    // Position of ENABLE field.
	TCC_SYNCBUSY_ENABLE_Msk = 0x2    // Bit mask of ENABLE field.
	TCC_SYNCBUSY_ENABLE     = 0x2    // Bit ENABLE.
	TCC_SYNCBUSY_CTRLB_Pos  = 0x2    // Position of CTRLB field.
	TCC_SYNCBUSY_CTRLB_Msk  = 0x4    // Bit mask of CTRLB field.
	TCC_SYNCBUSY_CTRLB      = 0x4    // Bit CTRLB.
	TCC_SYNCBUSY_STATUS_Pos = 0x3    // Position of STATUS field.
	TCC_SYNCBUSY_STATUS_Msk = 0x8    // Bit mask of STATUS field.
	TCC_SYNCBUSY_STATUS     = 0x8    // Bit STATUS.
	TCC_SYNCBUSY_COUNT_Pos  = 0x4    // Position of COUNT field.
	TCC_SYNCBUSY_COUNT_Msk  = 0x10   // Bit mask of COUNT field.
	TCC_SYNCBUSY_COUNT      = 0x10   // Bit COUNT.
	TCC_SYNCBUSY_PATT_Pos   = 0x5    // Position of PATT field.
	TCC_SYNCBUSY_PATT_Msk   = 0x20   // Bit mask of PATT field.
	TCC_SYNCBUSY_PATT       = 0x20   // Bit PATT.
	TCC_SYNCBUSY_WAVE_Pos   = 0x6    // Position of WAVE field.
	TCC_SYNCBUSY_WAVE_Msk   = 0x40   // Bit mask of WAVE field.
	TCC_SYNCBUSY_WAVE       = 0x40   // Bit WAVE.
	TCC_SYNCBUSY_PER_Pos    = 0x7    // Position of PER field.
	TCC_SYNCBUSY_PER_Msk    = 0x80   // Bit mask of PER field.
	TCC_SYNCBUSY_PER        = 0x80   // Bit PER.
	TCC_SYNCBUSY_CC0_Pos    = 0x8    // Position of CC0 field.
	TCC_SYNCBUSY_CC0_Msk    = 0x100  // Bit mask of CC0 field.
	TCC_SYNCBUSY_CC0        = 0x100  // Bit CC0.
	TCC_SYNCBUSY_CC1_Pos    = 0x9    // Position of CC1 field.
	TCC_SYNCBUSY_CC1_Msk    = 0x200  // Bit mask of CC1 field.
	TCC_SYNCBUSY_CC1        = 0x200  // Bit CC1.
	TCC_SYNCBUSY_CC2_Pos    = 0xa    // Position of CC2 field.
	TCC_SYNCBUSY_CC2_Msk    = 0x400  // Bit mask of CC2 field.
	TCC_SYNCBUSY_CC2        = 0x400  // Bit CC2.
	TCC_SYNCBUSY_CC3_Pos    = 0xb    // Position of CC3 field.
	TCC_SYNCBUSY_CC3_Msk    = 0x800  // Bit mask of CC3 field.
	TCC_SYNCBUSY_CC3        = 0x800  // Bit CC3.
	TCC_SYNCBUSY_CC4_Pos    = 0xc    // Position of CC4 field.
	TCC_SYNCBUSY_CC4_Msk    = 0x1000 // Bit mask of CC4 field.
	TCC_SYNCBUSY_CC4        = 0x1000 // Bit CC4.
	TCC_SYNCBUSY_CC5_Pos    = 0xd    // Position of CC5 field.
	TCC_SYNCBUSY_CC5_Msk    = 0x2000 // Bit mask of CC5 field.
	TCC_SYNCBUSY_CC5        = 0x2000 // Bit CC5.

	// FCTRLA: Recoverable Fault A Configuration
	TCC_FCTRLA_SRC_Pos          = 0x0       // Position of SRC field.
	TCC_FCTRLA_SRC_Msk          = 0x3       // Bit mask of SRC field.
	TCC_FCTRLA_SRC_DISABLE      = 0x0       // Fault input disabled
	TCC_FCTRLA_SRC_ENABLE       = 0x1       // MCEx (x=0,1) event input
	TCC_FCTRLA_SRC_INVERT       = 0x2       // Inverted MCEx (x=0,1) event input
	TCC_FCTRLA_SRC_ALTFAULT     = 0x3       // Alternate fault (A or B) state at the end of the previous period
	TCC_FCTRLA_KEEP_Pos         = 0x3       // Position of KEEP field.
	TCC_FCTRLA_KEEP_Msk         = 0x8       // Bit mask of KEEP field.
	TCC_FCTRLA_KEEP             = 0x8       // Bit KEEP.
	TCC_FCTRLA_QUAL_Pos         = 0x4       // Position of QUAL field.
	TCC_FCTRLA_QUAL_Msk         = 0x10      // Bit mask of QUAL field.
	TCC_FCTRLA_QUAL             = 0x10      // Bit QUAL.
	TCC_FCTRLA_BLANK_Pos        = 0x5       // Position of BLANK field.
	TCC_FCTRLA_BLANK_Msk        = 0x60      // Bit mask of BLANK field.
	TCC_FCTRLA_BLANK_START      = 0x0       // Blanking applied from start of the ramp
	TCC_FCTRLA_BLANK_RISE       = 0x1       // Blanking applied from rising edge of the output waveform
	TCC_FCTRLA_BLANK_FALL       = 0x2       // Blanking applied from falling edge of the output waveform
	TCC_FCTRLA_BLANK_BOTH       = 0x3       // Blanking applied from each toggle of the output waveform
	TCC_FCTRLA_RESTART_Pos      = 0x7       // Position of RESTART field.
	TCC_FCTRLA_RESTART_Msk      = 0x80      // Bit mask of RESTART field.
	TCC_FCTRLA_RESTART          = 0x80      // Bit RESTART.
	TCC_FCTRLA_HALT_Pos         = 0x8       // Position of HALT field.
	TCC_FCTRLA_HALT_Msk         = 0x300     // Bit mask of HALT field.
	TCC_FCTRLA_HALT_DISABLE     = 0x0       // Halt action disabled
	TCC_FCTRLA_HALT_HW          = 0x1       // Hardware halt action
	TCC_FCTRLA_HALT_SW          = 0x2       // Software halt action
	TCC_FCTRLA_HALT_NR          = 0x3       // Non-recoverable fault
	TCC_FCTRLA_CHSEL_Pos        = 0xa       // Position of CHSEL field.
	TCC_FCTRLA_CHSEL_Msk        = 0xc00     // Bit mask of CHSEL field.
	TCC_FCTRLA_CHSEL_CC0        = 0x0       // Capture value stored in channel 0
	TCC_FCTRLA_CHSEL_CC1        = 0x1       // Capture value stored in channel 1
	TCC_FCTRLA_CHSEL_CC2        = 0x2       // Capture value stored in channel 2
	TCC_FCTRLA_CHSEL_CC3        = 0x3       // Capture value stored in channel 3
	TCC_FCTRLA_CAPTURE_Pos      = 0xc       // Position of CAPTURE field.
	TCC_FCTRLA_CAPTURE_Msk      = 0x7000    // Bit mask of CAPTURE field.
	TCC_FCTRLA_CAPTURE_DISABLE  = 0x0       // No capture
	TCC_FCTRLA_CAPTURE_CAPT     = 0x1       // Capture on fault
	TCC_FCTRLA_CAPTURE_CAPTMIN  = 0x2       // Minimum capture
	TCC_FCTRLA_CAPTURE_CAPTMAX  = 0x3       // Maximum capture
	TCC_FCTRLA_CAPTURE_LOCMIN   = 0x4       // Minimum local detection
	TCC_FCTRLA_CAPTURE_LOCMAX   = 0x5       // Maximum local detection
	TCC_FCTRLA_CAPTURE_DERIV0   = 0x6       // Minimum and maximum local detection
	TCC_FCTRLA_CAPTURE_CAPTMARK = 0x7       // Capture with ramp index as MSB value
	TCC_FCTRLA_BLANKPRESC_Pos   = 0xf       // Position of BLANKPRESC field.
	TCC_FCTRLA_BLANKPRESC_Msk   = 0x8000    // Bit mask of BLANKPRESC field.
	TCC_FCTRLA_BLANKPRESC       = 0x8000    // Bit BLANKPRESC.
	TCC_FCTRLA_BLANKVAL_Pos     = 0x10      // Position of BLANKVAL field.
	TCC_FCTRLA_BLANKVAL_Msk     = 0xff0000  // Bit mask of BLANKVAL field.
	TCC_FCTRLA_FILTERVAL_Pos    = 0x18      // Position of FILTERVAL field.
	TCC_FCTRLA_FILTERVAL_Msk    = 0xf000000 // Bit mask of FILTERVAL field.

	// FCTRLB: Recoverable Fault B Configuration
	TCC_FCTRLB_SRC_Pos          = 0x0       // Position of SRC field.
	TCC_FCTRLB_SRC_Msk          = 0x3       // Bit mask of SRC field.
	TCC_FCTRLB_SRC_DISABLE      = 0x0       // Fault input disabled
	TCC_FCTRLB_SRC_ENABLE       = 0x1       // MCEx (x=0,1) event input
	TCC_FCTRLB_SRC_INVERT       = 0x2       // Inverted MCEx (x=0,1) event input
	TCC_FCTRLB_SRC_ALTFAULT     = 0x3       // Alternate fault (A or B) state at the end of the previous period
	TCC_FCTRLB_KEEP_Pos         = 0x3       // Position of KEEP field.
	TCC_FCTRLB_KEEP_Msk         = 0x8       // Bit mask of KEEP field.
	TCC_FCTRLB_KEEP             = 0x8       // Bit KEEP.
	TCC_FCTRLB_QUAL_Pos         = 0x4       // Position of QUAL field.
	TCC_FCTRLB_QUAL_Msk         = 0x10      // Bit mask of QUAL field.
	TCC_FCTRLB_QUAL             = 0x10      // Bit QUAL.
	TCC_FCTRLB_BLANK_Pos        = 0x5       // Position of BLANK field.
	TCC_FCTRLB_BLANK_Msk        = 0x60      // Bit mask of BLANK field.
	TCC_FCTRLB_BLANK_START      = 0x0       // Blanking applied from start of the ramp
	TCC_FCTRLB_BLANK_RISE       = 0x1       // Blanking applied from rising edge of the output waveform
	TCC_FCTRLB_BLANK_FALL       = 0x2       // Blanking applied from falling edge of the output waveform
	TCC_FCTRLB_BLANK_BOTH       = 0x3       // Blanking applied from each toggle of the output waveform
	TCC_FCTRLB_RESTART_Pos      = 0x7       // Position of RESTART field.
	TCC_FCTRLB_RESTART_Msk      = 0x80      // Bit mask of RESTART field.
	TCC_FCTRLB_RESTART          = 0x80      // Bit RESTART.
	TCC_FCTRLB_HALT_Pos         = 0x8       // Position of HALT field.
	TCC_FCTRLB_HALT_Msk         = 0x300     // Bit mask of HALT field.
	TCC_FCTRLB_HALT_DISABLE     = 0x0       // Halt action disabled
	TCC_FCTRLB_HALT_HW          = 0x1       // Hardware halt action
	TCC_FCTRLB_HALT_SW          = 0x2       // Software halt action
	TCC_FCTRLB_HALT_NR          = 0x3       // Non-recoverable fault
	TCC_FCTRLB_CHSEL_Pos        = 0xa       // Position of CHSEL field.
	TCC_FCTRLB_CHSEL_Msk        = 0xc00     // Bit mask of CHSEL field.
	TCC_FCTRLB_CHSEL_CC0        = 0x0       // Capture value stored in channel 0
	TCC_FCTRLB_CHSEL_CC1        = 0x1       // Capture value stored in channel 1
	TCC_FCTRLB_CHSEL_CC2        = 0x2       // Capture value stored in channel 2
	TCC_FCTRLB_CHSEL_CC3        = 0x3       // Capture value stored in channel 3
	TCC_FCTRLB_CAPTURE_Pos      = 0xc       // Position of CAPTURE field.
	TCC_FCTRLB_CAPTURE_Msk      = 0x7000    // Bit mask of CAPTURE field.
	TCC_FCTRLB_CAPTURE_DISABLE  = 0x0       // No capture
	TCC_FCTRLB_CAPTURE_CAPT     = 0x1       // Capture on fault
	TCC_FCTRLB_CAPTURE_CAPTMIN  = 0x2       // Minimum capture
	TCC_FCTRLB_CAPTURE_CAPTMAX  = 0x3       // Maximum capture
	TCC_FCTRLB_CAPTURE_LOCMIN   = 0x4       // Minimum local detection
	TCC_FCTRLB_CAPTURE_LOCMAX   = 0x5       // Maximum local detection
	TCC_FCTRLB_CAPTURE_DERIV0   = 0x6       // Minimum and maximum local detection
	TCC_FCTRLB_CAPTURE_CAPTMARK = 0x7       // Capture with ramp index as MSB value
	TCC_FCTRLB_BLANKPRESC_Pos   = 0xf       // Position of BLANKPRESC field.
	TCC_FCTRLB_BLANKPRESC_Msk   = 0x8000    // Bit mask of BLANKPRESC field.
	TCC_FCTRLB_BLANKPRESC       = 0x8000    // Bit BLANKPRESC.
	TCC_FCTRLB_BLANKVAL_Pos     = 0x10      // Position of BLANKVAL field.
	TCC_FCTRLB_BLANKVAL_Msk     = 0xff0000  // Bit mask of BLANKVAL field.
	TCC_FCTRLB_FILTERVAL_Pos    = 0x18      // Position of FILTERVAL field.
	TCC_FCTRLB_FILTERVAL_Msk    = 0xf000000 // Bit mask of FILTERVAL field.

	// WEXCTRL: Waveform Extension Configuration
	TCC_WEXCTRL_OTMX_Pos   = 0x0        // Position of OTMX field.
	TCC_WEXCTRL_OTMX_Msk   = 0x3        // Bit mask of OTMX field.
	TCC_WEXCTRL_DTIEN0_Pos = 0x8        // Position of DTIEN0 field.
	TCC_WEXCTRL_DTIEN0_Msk = 0x100      // Bit mask of DTIEN0 field.
	TCC_WEXCTRL_DTIEN0     = 0x100      // Bit DTIEN0.
	TCC_WEXCTRL_DTIEN1_Pos = 0x9        // Position of DTIEN1 field.
	TCC_WEXCTRL_DTIEN1_Msk = 0x200      // Bit mask of DTIEN1 field.
	TCC_WEXCTRL_DTIEN1     = 0x200      // Bit DTIEN1.
	TCC_WEXCTRL_DTIEN2_Pos = 0xa        // Position of DTIEN2 field.
	TCC_WEXCTRL_DTIEN2_Msk = 0x400      // Bit mask of DTIEN2 field.
	TCC_WEXCTRL_DTIEN2     = 0x400      // Bit DTIEN2.
	TCC_WEXCTRL_DTIEN3_Pos = 0xb        // Position of DTIEN3 field.
	TCC_WEXCTRL_DTIEN3_Msk = 0x800      // Bit mask of DTIEN3 field.
	TCC_WEXCTRL_DTIEN3     = 0x800      // Bit DTIEN3.
	TCC_WEXCTRL_DTLS_Pos   = 0x10       // Position of DTLS field.
	TCC_WEXCTRL_DTLS_Msk   = 0xff0000   // Bit mask of DTLS field.
	TCC_WEXCTRL_DTHS_Pos   = 0x18       // Position of DTHS field.
	TCC_WEXCTRL_DTHS_Msk   = 0xff000000 // Bit mask of DTHS field.

	// DRVCTRL: Driver Control
	TCC_DRVCTRL_NRE0_Pos       = 0x0        // Position of NRE0 field.
	TCC_DRVCTRL_NRE0_Msk       = 0x1        // Bit mask of NRE0 field.
	TCC_DRVCTRL_NRE0           = 0x1        // Bit NRE0.
	TCC_DRVCTRL_NRE1_Pos       = 0x1        // Position of NRE1 field.
	TCC_DRVCTRL_NRE1_Msk       = 0x2        // Bit mask of NRE1 field.
	TCC_DRVCTRL_NRE1           = 0x2        // Bit NRE1.
	TCC_DRVCTRL_NRE2_Pos       = 0x2        // Position of NRE2 field.
	TCC_DRVCTRL_NRE2_Msk       = 0x4        // Bit mask of NRE2 field.
	TCC_DRVCTRL_NRE2           = 0x4        // Bit NRE2.
	TCC_DRVCTRL_NRE3_Pos       = 0x3        // Position of NRE3 field.
	TCC_DRVCTRL_NRE3_Msk       = 0x8        // Bit mask of NRE3 field.
	TCC_DRVCTRL_NRE3           = 0x8        // Bit NRE3.
	TCC_DRVCTRL_NRE4_Pos       = 0x4        // Position of NRE4 field.
	TCC_DRVCTRL_NRE4_Msk       = 0x10       // Bit mask of NRE4 field.
	TCC_DRVCTRL_NRE4           = 0x10       // Bit NRE4.
	TCC_DRVCTRL_NRE5_Pos       = 0x5        // Position of NRE5 field.
	TCC_DRVCTRL_NRE5_Msk       = 0x20       // Bit mask of NRE5 field.
	TCC_DRVCTRL_NRE5           = 0x20       // Bit NRE5.
	TCC_DRVCTRL_NRE6_Pos       = 0x6        // Position of NRE6 field.
	TCC_DRVCTRL_NRE6_Msk       = 0x40       // Bit mask of NRE6 field.
	TCC_DRVCTRL_NRE6           = 0x40       // Bit NRE6.
	TCC_DRVCTRL_NRE7_Pos       = 0x7        // Position of NRE7 field.
	TCC_DRVCTRL_NRE7_Msk       = 0x80       // Bit mask of NRE7 field.
	TCC_DRVCTRL_NRE7           = 0x80       // Bit NRE7.
	TCC_DRVCTRL_NRV0_Pos       = 0x8        // Position of NRV0 field.
	TCC_DRVCTRL_NRV0_Msk       = 0x100      // Bit mask of NRV0 field.
	TCC_DRVCTRL_NRV0           = 0x100      // Bit NRV0.
	TCC_DRVCTRL_NRV1_Pos       = 0x9        // Position of NRV1 field.
	TCC_DRVCTRL_NRV1_Msk       = 0x200      // Bit mask of NRV1 field.
	TCC_DRVCTRL_NRV1           = 0x200      // Bit NRV1.
	TCC_DRVCTRL_NRV2_Pos       = 0xa        // Position of NRV2 field.
	TCC_DRVCTRL_NRV2_Msk       = 0x400      // Bit mask of NRV2 field.
	TCC_DRVCTRL_NRV2           = 0x400      // Bit NRV2.
	TCC_DRVCTRL_NRV3_Pos       = 0xb        // Position of NRV3 field.
	TCC_DRVCTRL_NRV3_Msk       = 0x800      // Bit mask of NRV3 field.
	TCC_DRVCTRL_NRV3           = 0x800      // Bit NRV3.
	TCC_DRVCTRL_NRV4_Pos       = 0xc        // Position of NRV4 field.
	TCC_DRVCTRL_NRV4_Msk       = 0x1000     // Bit mask of NRV4 field.
	TCC_DRVCTRL_NRV4           = 0x1000     // Bit NRV4.
	TCC_DRVCTRL_NRV5_Pos       = 0xd        // Position of NRV5 field.
	TCC_DRVCTRL_NRV5_Msk       = 0x2000     // Bit mask of NRV5 field.
	TCC_DRVCTRL_NRV5           = 0x2000     // Bit NRV5.
	TCC_DRVCTRL_NRV6_Pos       = 0xe        // Position of NRV6 field.
	TCC_DRVCTRL_NRV6_Msk       = 0x4000     // Bit mask of NRV6 field.
	TCC_DRVCTRL_NRV6           = 0x4000     // Bit NRV6.
	TCC_DRVCTRL_NRV7_Pos       = 0xf        // Position of NRV7 field.
	TCC_DRVCTRL_NRV7_Msk       = 0x8000     // Bit mask of NRV7 field.
	TCC_DRVCTRL_NRV7           = 0x8000     // Bit NRV7.
	TCC_DRVCTRL_INVEN0_Pos     = 0x10       // Position of INVEN0 field.
	TCC_DRVCTRL_INVEN0_Msk     = 0x10000    // Bit mask of INVEN0 field.
	TCC_DRVCTRL_INVEN0         = 0x10000    // Bit INVEN0.
	TCC_DRVCTRL_INVEN1_Pos     = 0x11       // Position of INVEN1 field.
	TCC_DRVCTRL_INVEN1_Msk     = 0x20000    // Bit mask of INVEN1 field.
	TCC_DRVCTRL_INVEN1         = 0x20000    // Bit INVEN1.
	TCC_DRVCTRL_INVEN2_Pos     = 0x12       // Position of INVEN2 field.
	TCC_DRVCTRL_INVEN2_Msk     = 0x40000    // Bit mask of INVEN2 field.
	TCC_DRVCTRL_INVEN2         = 0x40000    // Bit INVEN2.
	TCC_DRVCTRL_INVEN3_Pos     = 0x13       // Position of INVEN3 field.
	TCC_DRVCTRL_INVEN3_Msk     = 0x80000    // Bit mask of INVEN3 field.
	TCC_DRVCTRL_INVEN3         = 0x80000    // Bit INVEN3.
	TCC_DRVCTRL_INVEN4_Pos     = 0x14       // Position of INVEN4 field.
	TCC_DRVCTRL_INVEN4_Msk     = 0x100000   // Bit mask of INVEN4 field.
	TCC_DRVCTRL_INVEN4         = 0x100000   // Bit INVEN4.
	TCC_DRVCTRL_INVEN5_Pos     = 0x15       // Position of INVEN5 field.
	TCC_DRVCTRL_INVEN5_Msk     = 0x200000   // Bit mask of INVEN5 field.
	TCC_DRVCTRL_INVEN5         = 0x200000   // Bit INVEN5.
	TCC_DRVCTRL_INVEN6_Pos     = 0x16       // Position of INVEN6 field.
	TCC_DRVCTRL_INVEN6_Msk     = 0x400000   // Bit mask of INVEN6 field.
	TCC_DRVCTRL_INVEN6         = 0x400000   // Bit INVEN6.
	TCC_DRVCTRL_INVEN7_Pos     = 0x17       // Position of INVEN7 field.
	TCC_DRVCTRL_INVEN7_Msk     = 0x800000   // Bit mask of INVEN7 field.
	TCC_DRVCTRL_INVEN7         = 0x800000   // Bit INVEN7.
	TCC_DRVCTRL_FILTERVAL0_Pos = 0x18       // Position of FILTERVAL0 field.
	TCC_DRVCTRL_FILTERVAL0_Msk = 0xf000000  // Bit mask of FILTERVAL0 field.
	TCC_DRVCTRL_FILTERVAL1_Pos = 0x1c       // Position of FILTERVAL1 field.
	TCC_DRVCTRL_FILTERVAL1_Msk = 0xf0000000 // Bit mask of FILTERVAL1 field.

	// DBGCTRL: Debug Control
	TCC_DBGCTRL_DBGRUN_Pos = 0x0 // Position of DBGRUN field.
	TCC_DBGCTRL_DBGRUN_Msk = 0x1 // Bit mask of DBGRUN field.
	TCC_DBGCTRL_DBGRUN     = 0x1 // Bit DBGRUN.
	TCC_DBGCTRL_FDDBD_Pos  = 0x2 // Position of FDDBD field.
	TCC_DBGCTRL_FDDBD_Msk  = 0x4 // Bit mask of FDDBD field.
	TCC_DBGCTRL_FDDBD      = 0x4 // Bit FDDBD.

	// EVCTRL: Event Control
	TCC_EVCTRL_EVACT0_Pos       = 0x0        // Position of EVACT0 field.
	TCC_EVCTRL_EVACT0_Msk       = 0x7        // Bit mask of EVACT0 field.
	TCC_EVCTRL_EVACT0_OFF       = 0x0        // Event action disabled
	TCC_EVCTRL_EVACT0_RETRIGGER = 0x1        // Start, restart or re-trigger counter on event
	TCC_EVCTRL_EVACT0_COUNTEV   = 0x2        // Count on event
	TCC_EVCTRL_EVACT0_START     = 0x3        // Start counter on event
	TCC_EVCTRL_EVACT0_INC       = 0x4        // Increment counter on event
	TCC_EVCTRL_EVACT0_COUNT     = 0x5        // Count on active state of asynchronous event
	TCC_EVCTRL_EVACT0_STAMP     = 0x6        // Stamp capture
	TCC_EVCTRL_EVACT0_FAULT     = 0x7        // Non-recoverable fault
	TCC_EVCTRL_EVACT1_Pos       = 0x3        // Position of EVACT1 field.
	TCC_EVCTRL_EVACT1_Msk       = 0x38       // Bit mask of EVACT1 field.
	TCC_EVCTRL_EVACT1_OFF       = 0x0        // Event action disabled
	TCC_EVCTRL_EVACT1_RETRIGGER = 0x1        // Re-trigger counter on event
	TCC_EVCTRL_EVACT1_DIR       = 0x2        // Direction control
	TCC_EVCTRL_EVACT1_STOP      = 0x3        // Stop counter on event
	TCC_EVCTRL_EVACT1_DEC       = 0x4        // Decrement counter on event
	TCC_EVCTRL_EVACT1_PPW       = 0x5        // Period capture value in CC0 register, pulse width capture value in CC1 register
	TCC_EVCTRL_EVACT1_PWP       = 0x6        // Period capture value in CC1 register, pulse width capture value in CC0 register
	TCC_EVCTRL_EVACT1_FAULT     = 0x7        // Non-recoverable fault
	TCC_EVCTRL_CNTSEL_Pos       = 0x6        // Position of CNTSEL field.
	TCC_EVCTRL_CNTSEL_Msk       = 0xc0       // Bit mask of CNTSEL field.
	TCC_EVCTRL_CNTSEL_START     = 0x0        // An interrupt/event is generated when a new counter cycle starts
	TCC_EVCTRL_CNTSEL_END       = 0x1        // An interrupt/event is generated when a counter cycle ends
	TCC_EVCTRL_CNTSEL_BETWEEN   = 0x2        // An interrupt/event is generated when a counter cycle ends, except for the first and last cycles
	TCC_EVCTRL_CNTSEL_BOUNDARY  = 0x3        // An interrupt/event is generated when a new counter cycle starts or a counter cycle ends
	TCC_EVCTRL_OVFEO_Pos        = 0x8        // Position of OVFEO field.
	TCC_EVCTRL_OVFEO_Msk        = 0x100      // Bit mask of OVFEO field.
	TCC_EVCTRL_OVFEO            = 0x100      // Bit OVFEO.
	TCC_EVCTRL_TRGEO_Pos        = 0x9        // Position of TRGEO field.
	TCC_EVCTRL_TRGEO_Msk        = 0x200      // Bit mask of TRGEO field.
	TCC_EVCTRL_TRGEO            = 0x200      // Bit TRGEO.
	TCC_EVCTRL_CNTEO_Pos        = 0xa        // Position of CNTEO field.
	TCC_EVCTRL_CNTEO_Msk        = 0x400      // Bit mask of CNTEO field.
	TCC_EVCTRL_CNTEO            = 0x400      // Bit CNTEO.
	TCC_EVCTRL_TCINV0_Pos       = 0xc        // Position of TCINV0 field.
	TCC_EVCTRL_TCINV0_Msk       = 0x1000     // Bit mask of TCINV0 field.
	TCC_EVCTRL_TCINV0           = 0x1000     // Bit TCINV0.
	TCC_EVCTRL_TCINV1_Pos       = 0xd        // Position of TCINV1 field.
	TCC_EVCTRL_TCINV1_Msk       = 0x2000     // Bit mask of TCINV1 field.
	TCC_EVCTRL_TCINV1           = 0x2000     // Bit TCINV1.
	TCC_EVCTRL_TCEI0_Pos        = 0xe        // Position of TCEI0 field.
	TCC_EVCTRL_TCEI0_Msk        = 0x4000     // Bit mask of TCEI0 field.
	TCC_EVCTRL_TCEI0            = 0x4000     // Bit TCEI0.
	TCC_EVCTRL_TCEI1_Pos        = 0xf        // Position of TCEI1 field.
	TCC_EVCTRL_TCEI1_Msk        = 0x8000     // Bit mask of TCEI1 field.
	TCC_EVCTRL_TCEI1            = 0x8000     // Bit TCEI1.
	TCC_EVCTRL_MCEI0_Pos        = 0x10       // Position of MCEI0 field.
	TCC_EVCTRL_MCEI0_Msk        = 0x10000    // Bit mask of MCEI0 field.
	TCC_EVCTRL_MCEI0            = 0x10000    // Bit MCEI0.
	TCC_EVCTRL_MCEI1_Pos        = 0x11       // Position of MCEI1 field.
	TCC_EVCTRL_MCEI1_Msk        = 0x20000    // Bit mask of MCEI1 field.
	TCC_EVCTRL_MCEI1            = 0x20000    // Bit MCEI1.
	TCC_EVCTRL_MCEI2_Pos        = 0x12       // Position of MCEI2 field.
	TCC_EVCTRL_MCEI2_Msk        = 0x40000    // Bit mask of MCEI2 field.
	TCC_EVCTRL_MCEI2            = 0x40000    // Bit MCEI2.
	TCC_EVCTRL_MCEI3_Pos        = 0x13       // Position of MCEI3 field.
	TCC_EVCTRL_MCEI3_Msk        = 0x80000    // Bit mask of MCEI3 field.
	TCC_EVCTRL_MCEI3            = 0x80000    // Bit MCEI3.
	TCC_EVCTRL_MCEI4_Pos        = 0x14       // Position of MCEI4 field.
	TCC_EVCTRL_MCEI4_Msk        = 0x100000   // Bit mask of MCEI4 field.
	TCC_EVCTRL_MCEI4            = 0x100000   // Bit MCEI4.
	TCC_EVCTRL_MCEI5_Pos        = 0x15       // Position of MCEI5 field.
	TCC_EVCTRL_MCEI5_Msk        = 0x200000   // Bit mask of MCEI5 field.
	TCC_EVCTRL_MCEI5            = 0x200000   // Bit MCEI5.
	TCC_EVCTRL_MCEO0_Pos        = 0x18       // Position of MCEO0 field.
	TCC_EVCTRL_MCEO0_Msk        = 0x1000000  // Bit mask of MCEO0 field.
	TCC_EVCTRL_MCEO0            = 0x1000000  // Bit MCEO0.
	TCC_EVCTRL_MCEO1_Pos        = 0x19       // Position of MCEO1 field.
	TCC_EVCTRL_MCEO1_Msk        = 0x2000000  // Bit mask of MCEO1 field.
	TCC_EVCTRL_MCEO1            = 0x2000000  // Bit MCEO1.
	TCC_EVCTRL_MCEO2_Pos        = 0x1a       // Position of MCEO2 field.
	TCC_EVCTRL_MCEO2_Msk        = 0x4000000  // Bit mask of MCEO2 field.
	TCC_EVCTRL_MCEO2            = 0x4000000  // Bit MCEO2.
	TCC_EVCTRL_MCEO3_Pos        = 0x1b       // Position of MCEO3 field.
	TCC_EVCTRL_MCEO3_Msk        = 0x8000000  // Bit mask of MCEO3 field.
	TCC_EVCTRL_MCEO3            = 0x8000000  // Bit MCEO3.
	TCC_EVCTRL_MCEO4_Pos        = 0x1c       // Position of MCEO4 field.
	TCC_EVCTRL_MCEO4_Msk        = 0x10000000 // Bit mask of MCEO4 field.
	TCC_EVCTRL_MCEO4            = 0x10000000 // Bit MCEO4.
	TCC_EVCTRL_MCEO5_Pos        = 0x1d       // Position of MCEO5 field.
	TCC_EVCTRL_MCEO5_Msk        = 0x20000000 // Bit mask of MCEO5 field.
	TCC_EVCTRL_MCEO5            = 0x20000000 // Bit MCEO5.

	// INTENCLR: Interrupt Enable Clear
	TCC_INTENCLR_OVF_Pos    = 0x0      // Position of OVF field.
	TCC_INTENCLR_OVF_Msk    = 0x1      // Bit mask of OVF field.
	TCC_INTENCLR_OVF        = 0x1      // Bit OVF.
	TCC_INTENCLR_TRG_Pos    = 0x1      // Position of TRG field.
	TCC_INTENCLR_TRG_Msk    = 0x2      // Bit mask of TRG field.
	TCC_INTENCLR_TRG        = 0x2      // Bit TRG.
	TCC_INTENCLR_CNT_Pos    = 0x2      // Position of CNT field.
	TCC_INTENCLR_CNT_Msk    = 0x4      // Bit mask of CNT field.
	TCC_INTENCLR_CNT        = 0x4      // Bit CNT.
	TCC_INTENCLR_ERR_Pos    = 0x3      // Position of ERR field.
	TCC_INTENCLR_ERR_Msk    = 0x8      // Bit mask of ERR field.
	TCC_INTENCLR_ERR        = 0x8      // Bit ERR.
	TCC_INTENCLR_UFS_Pos    = 0xa      // Position of UFS field.
	TCC_INTENCLR_UFS_Msk    = 0x400    // Bit mask of UFS field.
	TCC_INTENCLR_UFS        = 0x400    // Bit UFS.
	TCC_INTENCLR_DFS_Pos    = 0xb      // Position of DFS field.
	TCC_INTENCLR_DFS_Msk    = 0x800    // Bit mask of DFS field.
	TCC_INTENCLR_DFS        = 0x800    // Bit DFS.
	TCC_INTENCLR_FAULTA_Pos = 0xc      // Position of FAULTA field.
	TCC_INTENCLR_FAULTA_Msk = 0x1000   // Bit mask of FAULTA field.
	TCC_INTENCLR_FAULTA     = 0x1000   // Bit FAULTA.
	TCC_INTENCLR_FAULTB_Pos = 0xd      // Position of FAULTB field.
	TCC_INTENCLR_FAULTB_Msk = 0x2000   // Bit mask of FAULTB field.
	TCC_INTENCLR_FAULTB     = 0x2000   // Bit FAULTB.
	TCC_INTENCLR_FAULT0_Pos = 0xe      // Position of FAULT0 field.
	TCC_INTENCLR_FAULT0_Msk = 0x4000   // Bit mask of FAULT0 field.
	TCC_INTENCLR_FAULT0     = 0x4000   // Bit FAULT0.
	TCC_INTENCLR_FAULT1_Pos = 0xf      // Position of FAULT1 field.
	TCC_INTENCLR_FAULT1_Msk = 0x8000   // Bit mask of FAULT1 field.
	TCC_INTENCLR_FAULT1     = 0x8000   // Bit FAULT1.
	TCC_INTENCLR_MC0_Pos    = 0x10     // Position of MC0 field.
	TCC_INTENCLR_MC0_Msk    = 0x10000  // Bit mask of MC0 field.
	TCC_INTENCLR_MC0        = 0x10000  // Bit MC0.
	TCC_INTENCLR_MC1_Pos    = 0x11     // Position of MC1 field.
	TCC_INTENCLR_MC1_Msk    = 0x20000  // Bit mask of MC1 field.
	TCC_INTENCLR_MC1        = 0x20000  // Bit MC1.
	TCC_INTENCLR_MC2_Pos    = 0x12     // Position of MC2 field.
	TCC_INTENCLR_MC2_Msk    = 0x40000  // Bit mask of MC2 field.
	TCC_INTENCLR_MC2        = 0x40000  // Bit MC2.
	TCC_INTENCLR_MC3_Pos    = 0x13     // Position of MC3 field.
	TCC_INTENCLR_MC3_Msk    = 0x80000  // Bit mask of MC3 field.
	TCC_INTENCLR_MC3        = 0x80000  // Bit MC3.
	TCC_INTENCLR_MC4_Pos    = 0x14     // Position of MC4 field.
	TCC_INTENCLR_MC4_Msk    = 0x100000 // Bit mask of MC4 field.
	TCC_INTENCLR_MC4        = 0x100000 // Bit MC4.
	TCC_INTENCLR_MC5_Pos    = 0x15     // Position of MC5 field.
	TCC_INTENCLR_MC5_Msk    = 0x200000 // Bit mask of MC5 field.
	TCC_INTENCLR_MC5        = 0x200000 // Bit MC5.

	// INTENSET: Interrupt Enable Set
	TCC_INTENSET_OVF_Pos    = 0x0      // Position of OVF field.
	TCC_INTENSET_OVF_Msk    = 0x1      // Bit mask of OVF field.
	TCC_INTENSET_OVF        = 0x1      // Bit OVF.
	TCC_INTENSET_TRG_Pos    = 0x1      // Position of TRG field.
	TCC_INTENSET_TRG_Msk    = 0x2      // Bit mask of TRG field.
	TCC_INTENSET_TRG        = 0x2      // Bit TRG.
	TCC_INTENSET_CNT_Pos    = 0x2      // Position of CNT field.
	TCC_INTENSET_CNT_Msk    = 0x4      // Bit mask of CNT field.
	TCC_INTENSET_CNT        = 0x4      // Bit CNT.
	TCC_INTENSET_ERR_Pos    = 0x3      // Position of ERR field.
	TCC_INTENSET_ERR_Msk    = 0x8      // Bit mask of ERR field.
	TCC_INTENSET_ERR        = 0x8      // Bit ERR.
	TCC_INTENSET_UFS_Pos    = 0xa      // Position of UFS field.
	TCC_INTENSET_UFS_Msk    = 0x400    // Bit mask of UFS field.
	TCC_INTENSET_UFS        = 0x400    // Bit UFS.
	TCC_INTENSET_DFS_Pos    = 0xb      // Position of DFS field.
	TCC_INTENSET_DFS_Msk    = 0x800    // Bit mask of DFS field.
	TCC_INTENSET_DFS        = 0x800    // Bit DFS.
	TCC_INTENSET_FAULTA_Pos = 0xc      // Position of FAULTA field.
	TCC_INTENSET_FAULTA_Msk = 0x1000   // Bit mask of FAULTA field.
	TCC_INTENSET_FAULTA     = 0x1000   // Bit FAULTA.
	TCC_INTENSET_FAULTB_Pos = 0xd      // Position of FAULTB field.
	TCC_INTENSET_FAULTB_Msk = 0x2000   // Bit mask of FAULTB field.
	TCC_INTENSET_FAULTB     = 0x2000   // Bit FAULTB.
	TCC_INTENSET_FAULT0_Pos = 0xe      // Position of FAULT0 field.
	TCC_INTENSET_FAULT0_Msk = 0x4000   // Bit mask of FAULT0 field.
	TCC_INTENSET_FAULT0     = 0x4000   // Bit FAULT0.
	TCC_INTENSET_FAULT1_Pos = 0xf      // Position of FAULT1 field.
	TCC_INTENSET_FAULT1_Msk = 0x8000   // Bit mask of FAULT1 field.
	TCC_INTENSET_FAULT1     = 0x8000   // Bit FAULT1.
	TCC_INTENSET_MC0_Pos    = 0x10     // Position of MC0 field.
	TCC_INTENSET_MC0_Msk    = 0x10000  // Bit mask of MC0 field.
	TCC_INTENSET_MC0        = 0x10000  // Bit MC0.
	TCC_INTENSET_MC1_Pos    = 0x11     // Position of MC1 field.
	TCC_INTENSET_MC1_Msk    = 0x20000  // Bit mask of MC1 field.
	TCC_INTENSET_MC1        = 0x20000  // Bit MC1.
	TCC_INTENSET_MC2_Pos    = 0x12     // Position of MC2 field.
	TCC_INTENSET_MC2_Msk    = 0x40000  // Bit mask of MC2 field.
	TCC_INTENSET_MC2        = 0x40000  // Bit MC2.
	TCC_INTENSET_MC3_Pos    = 0x13     // Position of MC3 field.
	TCC_INTENSET_MC3_Msk    = 0x80000  // Bit mask of MC3 field.
	TCC_INTENSET_MC3        = 0x80000  // Bit MC3.
	TCC_INTENSET_MC4_Pos    = 0x14     // Position of MC4 field.
	TCC_INTENSET_MC4_Msk    = 0x100000 // Bit mask of MC4 field.
	TCC_INTENSET_MC4        = 0x100000 // Bit MC4.
	TCC_INTENSET_MC5_Pos    = 0x15     // Position of MC5 field.
	TCC_INTENSET_MC5_Msk    = 0x200000 // Bit mask of MC5 field.
	TCC_INTENSET_MC5        = 0x200000 // Bit MC5.

	// INTFLAG: Interrupt Flag Status and Clear
	TCC_INTFLAG_OVF_Pos    = 0x0      // Position of OVF field.
	TCC_INTFLAG_OVF_Msk    = 0x1      // Bit mask of OVF field.
	TCC_INTFLAG_OVF        = 0x1      // Bit OVF.
	TCC_INTFLAG_TRG_Pos    = 0x1      // Position of TRG field.
	TCC_INTFLAG_TRG_Msk    = 0x2      // Bit mask of TRG field.
	TCC_INTFLAG_TRG        = 0x2      // Bit TRG.
	TCC_INTFLAG_CNT_Pos    = 0x2      // Position of CNT field.
	TCC_INTFLAG_CNT_Msk    = 0x4      // Bit mask of CNT field.
	TCC_INTFLAG_CNT        = 0x4      // Bit CNT.
	TCC_INTFLAG_ERR_Pos    = 0x3      // Position of ERR field.
	TCC_INTFLAG_ERR_Msk    = 0x8      // Bit mask of ERR field.
	TCC_INTFLAG_ERR        = 0x8      // Bit ERR.
	TCC_INTFLAG_UFS_Pos    = 0xa      // Position of UFS field.
	TCC_INTFLAG_UFS_Msk    = 0x400    // Bit mask of UFS field.
	TCC_INTFLAG_UFS        = 0x400    // Bit UFS.
	TCC_INTFLAG_DFS_Pos    = 0xb      // Position of DFS field.
	TCC_INTFLAG_DFS_Msk    = 0x800    // Bit mask of DFS field.
	TCC_INTFLAG_DFS        = 0x800    // Bit DFS.
	TCC_INTFLAG_FAULTA_Pos = 0xc      // Position of FAULTA field.
	TCC_INTFLAG_FAULTA_Msk = 0x1000   // Bit mask of FAULTA field.
	TCC_INTFLAG_FAULTA     = 0x1000   // Bit FAULTA.
	TCC_INTFLAG_FAULTB_Pos = 0xd      // Position of FAULTB field.
	TCC_INTFLAG_FAULTB_Msk = 0x2000   // Bit mask of FAULTB field.
	TCC_INTFLAG_FAULTB     = 0x2000   // Bit FAULTB.
	TCC_INTFLAG_FAULT0_Pos = 0xe      // Position of FAULT0 field.
	TCC_INTFLAG_FAULT0_Msk = 0x4000   // Bit mask of FAULT0 field.
	TCC_INTFLAG_FAULT0     = 0x4000   // Bit FAULT0.
	TCC_INTFLAG_FAULT1_Pos = 0xf      // Position of FAULT1 field.
	TCC_INTFLAG_FAULT1_Msk = 0x8000   // Bit mask of FAULT1 field.
	TCC_INTFLAG_FAULT1     = 0x8000   // Bit FAULT1.
	TCC_INTFLAG_MC0_Pos    = 0x10     // Position of MC0 field.
	TCC_INTFLAG_MC0_Msk    = 0x10000  // Bit mask of MC0 field.
	TCC_INTFLAG_MC0        = 0x10000  // Bit MC0.
	TCC_INTFLAG_MC1_Pos    = 0x11     // Position of MC1 field.
	TCC_INTFLAG_MC1_Msk    = 0x20000  // Bit mask of MC1 field.
	TCC_INTFLAG_MC1        = 0x20000  // Bit MC1.
	TCC_INTFLAG_MC2_Pos    = 0x12     // Position of MC2 field.
	TCC_INTFLAG_MC2_Msk    = 0x40000  // Bit mask of MC2 field.
	TCC_INTFLAG_MC2        = 0x40000  // Bit MC2.
	TCC_INTFLAG_MC3_Pos    = 0x13     // Position of MC3 field.
	TCC_INTFLAG_MC3_Msk    = 0x80000  // Bit mask of MC3 field.
	TCC_INTFLAG_MC3        = 0x80000  // Bit MC3.
	TCC_INTFLAG_MC4_Pos    = 0x14     // Position of MC4 field.
	TCC_INTFLAG_MC4_Msk    = 0x100000 // Bit mask of MC4 field.
	TCC_INTFLAG_MC4        = 0x100000 // Bit MC4.
	TCC_INTFLAG_MC5_Pos    = 0x15     // Position of MC5 field.
	TCC_INTFLAG_MC5_Msk    = 0x200000 // Bit mask of MC5 field.
	TCC_INTFLAG_MC5        = 0x200000 // Bit MC5.

	// STATUS: Status
	TCC_STATUS_STOP_Pos     = 0x0        // Position of STOP field.
	TCC_STATUS_STOP_Msk     = 0x1        // Bit mask of STOP field.
	TCC_STATUS_STOP         = 0x1        // Bit STOP.
	TCC_STATUS_IDX_Pos      = 0x1        // Position of IDX field.
	TCC_STATUS_IDX_Msk      = 0x2        // Bit mask of IDX field.
	TCC_STATUS_IDX          = 0x2        // Bit IDX.
	TCC_STATUS_UFS_Pos      = 0x2        // Position of UFS field.
	TCC_STATUS_UFS_Msk      = 0x4        // Bit mask of UFS field.
	TCC_STATUS_UFS          = 0x4        // Bit UFS.
	TCC_STATUS_DFS_Pos      = 0x3        // Position of DFS field.
	TCC_STATUS_DFS_Msk      = 0x8        // Bit mask of DFS field.
	TCC_STATUS_DFS          = 0x8        // Bit DFS.
	TCC_STATUS_SLAVE_Pos    = 0x4        // Position of SLAVE field.
	TCC_STATUS_SLAVE_Msk    = 0x10       // Bit mask of SLAVE field.
	TCC_STATUS_SLAVE        = 0x10       // Bit SLAVE.
	TCC_STATUS_PATTBUFV_Pos = 0x5        // Position of PATTBUFV field.
	TCC_STATUS_PATTBUFV_Msk = 0x20       // Bit mask of PATTBUFV field.
	TCC_STATUS_PATTBUFV     = 0x20       // Bit PATTBUFV.
	TCC_STATUS_PERBUFV_Pos  = 0x7        // Position of PERBUFV field.
	TCC_STATUS_PERBUFV_Msk  = 0x80       // Bit mask of PERBUFV field.
	TCC_STATUS_PERBUFV      = 0x80       // Bit PERBUFV.
	TCC_STATUS_FAULTAIN_Pos = 0x8        // Position of FAULTAIN field.
	TCC_STATUS_FAULTAIN_Msk = 0x100      // Bit mask of FAULTAIN field.
	TCC_STATUS_FAULTAIN     = 0x100      // Bit FAULTAIN.
	TCC_STATUS_FAULTBIN_Pos = 0x9        // Position of FAULTBIN field.
	TCC_STATUS_FAULTBIN_Msk = 0x200      // Bit mask of FAULTBIN field.
	TCC_STATUS_FAULTBIN     = 0x200      // Bit FAULTBIN.
	TCC_STATUS_FAULT0IN_Pos = 0xa        // Position of FAULT0IN field.
	TCC_STATUS_FAULT0IN_Msk = 0x400      // Bit mask of FAULT0IN field.
	TCC_STATUS_FAULT0IN     = 0x400      // Bit FAULT0IN.
	TCC_STATUS_FAULT1IN_Pos = 0xb        // Position of FAULT1IN field.
	TCC_STATUS_FAULT1IN_Msk = 0x800      // Bit mask of FAULT1IN field.
	TCC_STATUS_FAULT1IN     = 0x800      // Bit FAULT1IN.
	TCC_STATUS_FAULTA_Pos   = 0xc        // Position of FAULTA field.
	TCC_STATUS_FAULTA_Msk   = 0x1000     // Bit mask of FAULTA field.
	TCC_STATUS_FAULTA       = 0x1000     // Bit FAULTA.
	TCC_STATUS_FAULTB_Pos   = 0xd        // Position of FAULTB field.
	TCC_STATUS_FAULTB_Msk   = 0x2000     // Bit mask of FAULTB field.
	TCC_STATUS_FAULTB       = 0x2000     // Bit FAULTB.
	TCC_STATUS_FAULT0_Pos   = 0xe        // Position of FAULT0 field.
	TCC_STATUS_FAULT0_Msk   = 0x4000     // Bit mask of FAULT0 field.
	TCC_STATUS_FAULT0       = 0x4000     // Bit FAULT0.
	TCC_STATUS_FAULT1_Pos   = 0xf        // Position of FAULT1 field.
	TCC_STATUS_FAULT1_Msk   = 0x8000     // Bit mask of FAULT1 field.
	TCC_STATUS_FAULT1       = 0x8000     // Bit FAULT1.
	TCC_STATUS_CCBUFV0_Pos  = 0x10       // Position of CCBUFV0 field.
	TCC_STATUS_CCBUFV0_Msk  = 0x10000    // Bit mask of CCBUFV0 field.
	TCC_STATUS_CCBUFV0      = 0x10000    // Bit CCBUFV0.
	TCC_STATUS_CCBUFV1_Pos  = 0x11       // Position of CCBUFV1 field.
	TCC_STATUS_CCBUFV1_Msk  = 0x20000    // Bit mask of CCBUFV1 field.
	TCC_STATUS_CCBUFV1      = 0x20000    // Bit CCBUFV1.
	TCC_STATUS_CCBUFV2_Pos  = 0x12       // Position of CCBUFV2 field.
	TCC_STATUS_CCBUFV2_Msk  = 0x40000    // Bit mask of CCBUFV2 field.
	TCC_STATUS_CCBUFV2      = 0x40000    // Bit CCBUFV2.
	TCC_STATUS_CCBUFV3_Pos  = 0x13       // Position of CCBUFV3 field.
	TCC_STATUS_CCBUFV3_Msk  = 0x80000    // Bit mask of CCBUFV3 field.
	TCC_STATUS_CCBUFV3      = 0x80000    // Bit CCBUFV3.
	TCC_STATUS_CCBUFV4_Pos  = 0x14       // Position of CCBUFV4 field.
	TCC_STATUS_CCBUFV4_Msk  = 0x100000   // Bit mask of CCBUFV4 field.
	TCC_STATUS_CCBUFV4      = 0x100000   // Bit CCBUFV4.
	TCC_STATUS_CCBUFV5_Pos  = 0x15       // Position of CCBUFV5 field.
	TCC_STATUS_CCBUFV5_Msk  = 0x200000   // Bit mask of CCBUFV5 field.
	TCC_STATUS_CCBUFV5      = 0x200000   // Bit CCBUFV5.
	TCC_STATUS_CMP0_Pos     = 0x18       // Position of CMP0 field.
	TCC_STATUS_CMP0_Msk     = 0x1000000  // Bit mask of CMP0 field.
	TCC_STATUS_CMP0         = 0x1000000  // Bit CMP0.
	TCC_STATUS_CMP1_Pos     = 0x19       // Position of CMP1 field.
	TCC_STATUS_CMP1_Msk     = 0x2000000  // Bit mask of CMP1 field.
	TCC_STATUS_CMP1         = 0x2000000  // Bit CMP1.
	TCC_STATUS_CMP2_Pos     = 0x1a       // Position of CMP2 field.
	TCC_STATUS_CMP2_Msk     = 0x4000000  // Bit mask of CMP2 field.
	TCC_STATUS_CMP2         = 0x4000000  // Bit CMP2.
	TCC_STATUS_CMP3_Pos     = 0x1b       // Position of CMP3 field.
	TCC_STATUS_CMP3_Msk     = 0x8000000  // Bit mask of CMP3 field.
	TCC_STATUS_CMP3         = 0x8000000  // Bit CMP3.
	TCC_STATUS_CMP4_Pos     = 0x1c       // Position of CMP4 field.
	TCC_STATUS_CMP4_Msk     = 0x10000000 // Bit mask of CMP4 field.
	TCC_STATUS_CMP4         = 0x10000000 // Bit CMP4.
	TCC_STATUS_CMP5_Pos     = 0x1d       // Position of CMP5 field.
	TCC_STATUS_CMP5_Msk     = 0x20000000 // Bit mask of CMP5 field.
	TCC_STATUS_CMP5         = 0x20000000 // Bit CMP5.

	// COUNT: Count
	TCC_COUNT_COUNT_Pos = 0x0      // Position of COUNT field.
	TCC_COUNT_COUNT_Msk = 0xffffff // Bit mask of COUNT field.

	// COUNT_DITH4_MODE: Count
	TCC_COUNT_DITH4_MODE_COUNT_Pos = 0x4      // Position of COUNT field.
	TCC_COUNT_DITH4_MODE_COUNT_Msk = 0xfffff0 // Bit mask of COUNT field.

	// COUNT_DITH5_MODE: Count
	TCC_COUNT_DITH5_MODE_COUNT_Pos = 0x5      // Position of COUNT field.
	TCC_COUNT_DITH5_MODE_COUNT_Msk = 0xffffe0 // Bit mask of COUNT field.

	// COUNT_DITH6_MODE: Count
	TCC_COUNT_DITH6_MODE_COUNT_Pos = 0x6      // Position of COUNT field.
	TCC_COUNT_DITH6_MODE_COUNT_Msk = 0xffffc0 // Bit mask of COUNT field.

	// PATT: Pattern
	TCC_PATT_PGE0_Pos = 0x0    // Position of PGE0 field.
	TCC_PATT_PGE0_Msk = 0x1    // Bit mask of PGE0 field.
	TCC_PATT_PGE0     = 0x1    // Bit PGE0.
	TCC_PATT_PGE1_Pos = 0x1    // Position of PGE1 field.
	TCC_PATT_PGE1_Msk = 0x2    // Bit mask of PGE1 field.
	TCC_PATT_PGE1     = 0x2    // Bit PGE1.
	TCC_PATT_PGE2_Pos = 0x2    // Position of PGE2 field.
	TCC_PATT_PGE2_Msk = 0x4    // Bit mask of PGE2 field.
	TCC_PATT_PGE2     = 0x4    // Bit PGE2.
	TCC_PATT_PGE3_Pos = 0x3    // Position of PGE3 field.
	TCC_PATT_PGE3_Msk = 0x8    // Bit mask of PGE3 field.
	TCC_PATT_PGE3     = 0x8    // Bit PGE3.
	TCC_PATT_PGE4_Pos = 0x4    // Position of PGE4 field.
	TCC_PATT_PGE4_Msk = 0x10   // Bit mask of PGE4 field.
	TCC_PATT_PGE4     = 0x10   // Bit PGE4.
	TCC_PATT_PGE5_Pos = 0x5    // Position of PGE5 field.
	TCC_PATT_PGE5_Msk = 0x20   // Bit mask of PGE5 field.
	TCC_PATT_PGE5     = 0x20   // Bit PGE5.
	TCC_PATT_PGE6_Pos = 0x6    // Position of PGE6 field.
	TCC_PATT_PGE6_Msk = 0x40   // Bit mask of PGE6 field.
	TCC_PATT_PGE6     = 0x40   // Bit PGE6.
	TCC_PATT_PGE7_Pos = 0x7    // Position of PGE7 field.
	TCC_PATT_PGE7_Msk = 0x80   // Bit mask of PGE7 field.
	TCC_PATT_PGE7     = 0x80   // Bit PGE7.
	TCC_PATT_PGV0_Pos = 0x8    // Position of PGV0 field.
	TCC_PATT_PGV0_Msk = 0x100  // Bit mask of PGV0 field.
	TCC_PATT_PGV0     = 0x100  // Bit PGV0.
	TCC_PATT_PGV1_Pos = 0x9    // Position of PGV1 field.
	TCC_PATT_PGV1_Msk = 0x200  // Bit mask of PGV1 field.
	TCC_PATT_PGV1     = 0x200  // Bit PGV1.
	TCC_PATT_PGV2_Pos = 0xa    // Position of PGV2 field.
	TCC_PATT_PGV2_Msk = 0x400  // Bit mask of PGV2 field.
	TCC_PATT_PGV2     = 0x400  // Bit PGV2.
	TCC_PATT_PGV3_Pos = 0xb    // Position of PGV3 field.
	TCC_PATT_PGV3_Msk = 0x800  // Bit mask of PGV3 field.
	TCC_PATT_PGV3     = 0x800  // Bit PGV3.
	TCC_PATT_PGV4_Pos = 0xc    // Position of PGV4 field.
	TCC_PATT_PGV4_Msk = 0x1000 // Bit mask of PGV4 field.
	TCC_PATT_PGV4     = 0x1000 // Bit PGV4.
	TCC_PATT_PGV5_Pos = 0xd    // Position of PGV5 field.
	TCC_PATT_PGV5_Msk = 0x2000 // Bit mask of PGV5 field.
	TCC_PATT_PGV5     = 0x2000 // Bit PGV5.
	TCC_PATT_PGV6_Pos = 0xe    // Position of PGV6 field.
	TCC_PATT_PGV6_Msk = 0x4000 // Bit mask of PGV6 field.
	TCC_PATT_PGV6     = 0x4000 // Bit PGV6.
	TCC_PATT_PGV7_Pos = 0xf    // Position of PGV7 field.
	TCC_PATT_PGV7_Msk = 0x8000 // Bit mask of PGV7 field.
	TCC_PATT_PGV7     = 0x8000 // Bit PGV7.

	// WAVE: Waveform Control
	TCC_WAVE_WAVEGEN_Pos        = 0x0       // Position of WAVEGEN field.
	TCC_WAVE_WAVEGEN_Msk        = 0x7       // Bit mask of WAVEGEN field.
	TCC_WAVE_WAVEGEN_NFRQ       = 0x0       // Normal frequency
	TCC_WAVE_WAVEGEN_MFRQ       = 0x1       // Match frequency
	TCC_WAVE_WAVEGEN_NPWM       = 0x2       // Normal PWM
	TCC_WAVE_WAVEGEN_DSCRITICAL = 0x4       // Dual-slope critical
	TCC_WAVE_WAVEGEN_DSBOTTOM   = 0x5       // Dual-slope with interrupt/event condition when COUNT reaches ZERO
	TCC_WAVE_WAVEGEN_DSBOTH     = 0x6       // Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP
	TCC_WAVE_WAVEGEN_DSTOP      = 0x7       // Dual-slope with interrupt/event condition when COUNT reaches TOP
	TCC_WAVE_RAMP_Pos           = 0x4       // Position of RAMP field.
	TCC_WAVE_RAMP_Msk           = 0x30      // Bit mask of RAMP field.
	TCC_WAVE_RAMP_RAMP1         = 0x0       // RAMP1 operation
	TCC_WAVE_RAMP_RAMP2A        = 0x1       // Alternative RAMP2 operation
	TCC_WAVE_RAMP_RAMP2         = 0x2       // RAMP2 operation
	TCC_WAVE_RAMP_RAMP2C        = 0x3       // Critical RAMP2 operation
	TCC_WAVE_CIPEREN_Pos        = 0x7       // Position of CIPEREN field.
	TCC_WAVE_CIPEREN_Msk        = 0x80      // Bit mask of CIPEREN field.
	TCC_WAVE_CIPEREN            = 0x80      // Bit CIPEREN.
	TCC_WAVE_CICCEN0_Pos        = 0x8       // Position of CICCEN0 field.
	TCC_WAVE_CICCEN0_Msk        = 0x100     // Bit mask of CICCEN0 field.
	TCC_WAVE_CICCEN0            = 0x100     // Bit CICCEN0.
	TCC_WAVE_CICCEN1_Pos        = 0x9       // Position of CICCEN1 field.
	TCC_WAVE_CICCEN1_Msk        = 0x200     // Bit mask of CICCEN1 field.
	TCC_WAVE_CICCEN1            = 0x200     // Bit CICCEN1.
	TCC_WAVE_CICCEN2_Pos        = 0xa       // Position of CICCEN2 field.
	TCC_WAVE_CICCEN2_Msk        = 0x400     // Bit mask of CICCEN2 field.
	TCC_WAVE_CICCEN2            = 0x400     // Bit CICCEN2.
	TCC_WAVE_CICCEN3_Pos        = 0xb       // Position of CICCEN3 field.
	TCC_WAVE_CICCEN3_Msk        = 0x800     // Bit mask of CICCEN3 field.
	TCC_WAVE_CICCEN3            = 0x800     // Bit CICCEN3.
	TCC_WAVE_POL0_Pos           = 0x10      // Position of POL0 field.
	TCC_WAVE_POL0_Msk           = 0x10000   // Bit mask of POL0 field.
	TCC_WAVE_POL0               = 0x10000   // Bit POL0.
	TCC_WAVE_POL1_Pos           = 0x11      // Position of POL1 field.
	TCC_WAVE_POL1_Msk           = 0x20000   // Bit mask of POL1 field.
	TCC_WAVE_POL1               = 0x20000   // Bit POL1.
	TCC_WAVE_POL2_Pos           = 0x12      // Position of POL2 field.
	TCC_WAVE_POL2_Msk           = 0x40000   // Bit mask of POL2 field.
	TCC_WAVE_POL2               = 0x40000   // Bit POL2.
	TCC_WAVE_POL3_Pos           = 0x13      // Position of POL3 field.
	TCC_WAVE_POL3_Msk           = 0x80000   // Bit mask of POL3 field.
	TCC_WAVE_POL3               = 0x80000   // Bit POL3.
	TCC_WAVE_POL4_Pos           = 0x14      // Position of POL4 field.
	TCC_WAVE_POL4_Msk           = 0x100000  // Bit mask of POL4 field.
	TCC_WAVE_POL4               = 0x100000  // Bit POL4.
	TCC_WAVE_POL5_Pos           = 0x15      // Position of POL5 field.
	TCC_WAVE_POL5_Msk           = 0x200000  // Bit mask of POL5 field.
	TCC_WAVE_POL5               = 0x200000  // Bit POL5.
	TCC_WAVE_SWAP0_Pos          = 0x18      // Position of SWAP0 field.
	TCC_WAVE_SWAP0_Msk          = 0x1000000 // Bit mask of SWAP0 field.
	TCC_WAVE_SWAP0              = 0x1000000 // Bit SWAP0.
	TCC_WAVE_SWAP1_Pos          = 0x19      // Position of SWAP1 field.
	TCC_WAVE_SWAP1_Msk          = 0x2000000 // Bit mask of SWAP1 field.
	TCC_WAVE_SWAP1              = 0x2000000 // Bit SWAP1.
	TCC_WAVE_SWAP2_Pos          = 0x1a      // Position of SWAP2 field.
	TCC_WAVE_SWAP2_Msk          = 0x4000000 // Bit mask of SWAP2 field.
	TCC_WAVE_SWAP2              = 0x4000000 // Bit SWAP2.
	TCC_WAVE_SWAP3_Pos          = 0x1b      // Position of SWAP3 field.
	TCC_WAVE_SWAP3_Msk          = 0x8000000 // Bit mask of SWAP3 field.
	TCC_WAVE_SWAP3              = 0x8000000 // Bit SWAP3.

	// PER: Period
	TCC_PER_PER_Pos = 0x0      // Position of PER field.
	TCC_PER_PER_Msk = 0xffffff // Bit mask of PER field.

	// PER_DITH4_MODE: Period
	TCC_PER_DITH4_MODE_DITHER_Pos = 0x0      // Position of DITHER field.
	TCC_PER_DITH4_MODE_DITHER_Msk = 0xf      // Bit mask of DITHER field.
	TCC_PER_DITH4_MODE_PER_Pos    = 0x4      // Position of PER field.
	TCC_PER_DITH4_MODE_PER_Msk    = 0xfffff0 // Bit mask of PER field.

	// PER_DITH5_MODE: Period
	TCC_PER_DITH5_MODE_DITHER_Pos = 0x0      // Position of DITHER field.
	TCC_PER_DITH5_MODE_DITHER_Msk = 0x1f     // Bit mask of DITHER field.
	TCC_PER_DITH5_MODE_PER_Pos    = 0x5      // Position of PER field.
	TCC_PER_DITH5_MODE_PER_Msk    = 0xffffe0 // Bit mask of PER field.

	// PER_DITH6_MODE: Period
	TCC_PER_DITH6_MODE_DITHER_Pos = 0x0      // Position of DITHER field.
	TCC_PER_DITH6_MODE_DITHER_Msk = 0x3f     // Bit mask of DITHER field.
	TCC_PER_DITH6_MODE_PER_Pos    = 0x6      // Position of PER field.
	TCC_PER_DITH6_MODE_PER_Msk    = 0xffffc0 // Bit mask of PER field.

	// CC: Compare and Capture
	TCC_CC_CC_Pos = 0x0      // Position of CC field.
	TCC_CC_CC_Msk = 0xffffff // Bit mask of CC field.

	// CC_DITH4_MODE: Compare and Capture
	TCC_CC_DITH4_MODE_DITHER_Pos = 0x0      // Position of DITHER field.
	TCC_CC_DITH4_MODE_DITHER_Msk = 0xf      // Bit mask of DITHER field.
	TCC_CC_DITH4_MODE_CC_Pos     = 0x4      // Position of CC field.
	TCC_CC_DITH4_MODE_CC_Msk     = 0xfffff0 // Bit mask of CC field.

	// CC_DITH5_MODE: Compare and Capture
	TCC_CC_DITH5_MODE_DITHER_Pos = 0x0      // Position of DITHER field.
	TCC_CC_DITH5_MODE_DITHER_Msk = 0x1f     // Bit mask of DITHER field.
	TCC_CC_DITH5_MODE_CC_Pos     = 0x5      // Position of CC field.
	TCC_CC_DITH5_MODE_CC_Msk     = 0xffffe0 // Bit mask of CC field.

	// CC_DITH6_MODE: Compare and Capture
	TCC_CC_DITH6_MODE_DITHER_Pos = 0x0      // Position of DITHER field.
	TCC_CC_DITH6_MODE_DITHER_Msk = 0x3f     // Bit mask of DITHER field.
	TCC_CC_DITH6_MODE_CC_Pos     = 0x6      // Position of CC field.
	TCC_CC_DITH6_MODE_CC_Msk     = 0xffffc0 // Bit mask of CC field.

	// PATTBUF: Pattern Buffer
	TCC_PATTBUF_PGEB0_Pos = 0x0    // Position of PGEB0 field.
	TCC_PATTBUF_PGEB0_Msk = 0x1    // Bit mask of PGEB0 field.
	TCC_PATTBUF_PGEB0     = 0x1    // Bit PGEB0.
	TCC_PATTBUF_PGEB1_Pos = 0x1    // Position of PGEB1 field.
	TCC_PATTBUF_PGEB1_Msk = 0x2    // Bit mask of PGEB1 field.
	TCC_PATTBUF_PGEB1     = 0x2    // Bit PGEB1.
	TCC_PATTBUF_PGEB2_Pos = 0x2    // Position of PGEB2 field.
	TCC_PATTBUF_PGEB2_Msk = 0x4    // Bit mask of PGEB2 field.
	TCC_PATTBUF_PGEB2     = 0x4    // Bit PGEB2.
	TCC_PATTBUF_PGEB3_Pos = 0x3    // Position of PGEB3 field.
	TCC_PATTBUF_PGEB3_Msk = 0x8    // Bit mask of PGEB3 field.
	TCC_PATTBUF_PGEB3     = 0x8    // Bit PGEB3.
	TCC_PATTBUF_PGEB4_Pos = 0x4    // Position of PGEB4 field.
	TCC_PATTBUF_PGEB4_Msk = 0x10   // Bit mask of PGEB4 field.
	TCC_PATTBUF_PGEB4     = 0x10   // Bit PGEB4.
	TCC_PATTBUF_PGEB5_Pos = 0x5    // Position of PGEB5 field.
	TCC_PATTBUF_PGEB5_Msk = 0x20   // Bit mask of PGEB5 field.
	TCC_PATTBUF_PGEB5     = 0x20   // Bit PGEB5.
	TCC_PATTBUF_PGEB6_Pos = 0x6    // Position of PGEB6 field.
	TCC_PATTBUF_PGEB6_Msk = 0x40   // Bit mask of PGEB6 field.
	TCC_PATTBUF_PGEB6     = 0x40   // Bit PGEB6.
	TCC_PATTBUF_PGEB7_Pos = 0x7    // Position of PGEB7 field.
	TCC_PATTBUF_PGEB7_Msk = 0x80   // Bit mask of PGEB7 field.
	TCC_PATTBUF_PGEB7     = 0x80   // Bit PGEB7.
	TCC_PATTBUF_PGVB0_Pos = 0x8    // Position of PGVB0 field.
	TCC_PATTBUF_PGVB0_Msk = 0x100  // Bit mask of PGVB0 field.
	TCC_PATTBUF_PGVB0     = 0x100  // Bit PGVB0.
	TCC_PATTBUF_PGVB1_Pos = 0x9    // Position of PGVB1 field.
	TCC_PATTBUF_PGVB1_Msk = 0x200  // Bit mask of PGVB1 field.
	TCC_PATTBUF_PGVB1     = 0x200  // Bit PGVB1.
	TCC_PATTBUF_PGVB2_Pos = 0xa    // Position of PGVB2 field.
	TCC_PATTBUF_PGVB2_Msk = 0x400  // Bit mask of PGVB2 field.
	TCC_PATTBUF_PGVB2     = 0x400  // Bit PGVB2.
	TCC_PATTBUF_PGVB3_Pos = 0xb    // Position of PGVB3 field.
	TCC_PATTBUF_PGVB3_Msk = 0x800  // Bit mask of PGVB3 field.
	TCC_PATTBUF_PGVB3     = 0x800  // Bit PGVB3.
	TCC_PATTBUF_PGVB4_Pos = 0xc    // Position of PGVB4 field.
	TCC_PATTBUF_PGVB4_Msk = 0x1000 // Bit mask of PGVB4 field.
	TCC_PATTBUF_PGVB4     = 0x1000 // Bit PGVB4.
	TCC_PATTBUF_PGVB5_Pos = 0xd    // Position of PGVB5 field.
	TCC_PATTBUF_PGVB5_Msk = 0x2000 // Bit mask of PGVB5 field.
	TCC_PATTBUF_PGVB5     = 0x2000 // Bit PGVB5.
	TCC_PATTBUF_PGVB6_Pos = 0xe    // Position of PGVB6 field.
	TCC_PATTBUF_PGVB6_Msk = 0x4000 // Bit mask of PGVB6 field.
	TCC_PATTBUF_PGVB6     = 0x4000 // Bit PGVB6.
	TCC_PATTBUF_PGVB7_Pos = 0xf    // Position of PGVB7 field.
	TCC_PATTBUF_PGVB7_Msk = 0x8000 // Bit mask of PGVB7 field.
	TCC_PATTBUF_PGVB7     = 0x8000 // Bit PGVB7.

	// PERBUF: Period Buffer
	TCC_PERBUF_PERBUF_Pos = 0x0      // Position of PERBUF field.
	TCC_PERBUF_PERBUF_Msk = 0xffffff // Bit mask of PERBUF field.

	// PERBUF_DITH4_MODE: Period Buffer
	TCC_PERBUF_DITH4_MODE_DITHERBUF_Pos = 0x0      // Position of DITHERBUF field.
	TCC_PERBUF_DITH4_MODE_DITHERBUF_Msk = 0xf      // Bit mask of DITHERBUF field.
	TCC_PERBUF_DITH4_MODE_PERBUF_Pos    = 0x4      // Position of PERBUF field.
	TCC_PERBUF_DITH4_MODE_PERBUF_Msk    = 0xfffff0 // Bit mask of PERBUF field.

	// PERBUF_DITH5_MODE: Period Buffer
	TCC_PERBUF_DITH5_MODE_DITHERBUF_Pos = 0x0      // Position of DITHERBUF field.
	TCC_PERBUF_DITH5_MODE_DITHERBUF_Msk = 0x1f     // Bit mask of DITHERBUF field.
	TCC_PERBUF_DITH5_MODE_PERBUF_Pos    = 0x5      // Position of PERBUF field.
	TCC_PERBUF_DITH5_MODE_PERBUF_Msk    = 0xffffe0 // Bit mask of PERBUF field.

	// PERBUF_DITH6_MODE: Period Buffer
	TCC_PERBUF_DITH6_MODE_DITHERBUF_Pos = 0x0      // Position of DITHERBUF field.
	TCC_PERBUF_DITH6_MODE_DITHERBUF_Msk = 0x3f     // Bit mask of DITHERBUF field.
	TCC_PERBUF_DITH6_MODE_PERBUF_Pos    = 0x6      // Position of PERBUF field.
	TCC_PERBUF_DITH6_MODE_PERBUF_Msk    = 0xffffc0 // Bit mask of PERBUF field.

	// CCBUF: Compare and Capture Buffer
	TCC_CCBUF_CCBUF_Pos = 0x0      // Position of CCBUF field.
	TCC_CCBUF_CCBUF_Msk = 0xffffff // Bit mask of CCBUF field.

	// CCBUF_DITH4_MODE: Compare and Capture Buffer
	TCC_CCBUF_DITH4_MODE_CCBUF_Pos     = 0x0      // Position of CCBUF field.
	TCC_CCBUF_DITH4_MODE_CCBUF_Msk     = 0xf      // Bit mask of CCBUF field.
	TCC_CCBUF_DITH4_MODE_DITHERBUF_Pos = 0x4      // Position of DITHERBUF field.
	TCC_CCBUF_DITH4_MODE_DITHERBUF_Msk = 0xfffff0 // Bit mask of DITHERBUF field.

	// CCBUF_DITH5_MODE: Compare and Capture Buffer
	TCC_CCBUF_DITH5_MODE_DITHERBUF_Pos = 0x0      // Position of DITHERBUF field.
	TCC_CCBUF_DITH5_MODE_DITHERBUF_Msk = 0x1f     // Bit mask of DITHERBUF field.
	TCC_CCBUF_DITH5_MODE_CCBUF_Pos     = 0x5      // Position of CCBUF field.
	TCC_CCBUF_DITH5_MODE_CCBUF_Msk     = 0xffffe0 // Bit mask of CCBUF field.

	// CCBUF_DITH6_MODE: Compare and Capture Buffer
	TCC_CCBUF_DITH6_MODE_DITHERBUF_Pos = 0x0      // Position of DITHERBUF field.
	TCC_CCBUF_DITH6_MODE_DITHERBUF_Msk = 0x3f     // Bit mask of DITHERBUF field.
	TCC_CCBUF_DITH6_MODE_CCBUF_Pos     = 0x6      // Position of CCBUF field.
	TCC_CCBUF_DITH6_MODE_CCBUF_Msk     = 0xffffc0 // Bit mask of CCBUF field.
)

// Bitfields for TRNG: True Random Generator
const (
	// CTRLA: Control A
	TRNG_CTRLA_ENABLE_Pos   = 0x1  // Position of ENABLE field.
	TRNG_CTRLA_ENABLE_Msk   = 0x2  // Bit mask of ENABLE field.
	TRNG_CTRLA_ENABLE       = 0x2  // Bit ENABLE.
	TRNG_CTRLA_RUNSTDBY_Pos = 0x6  // Position of RUNSTDBY field.
	TRNG_CTRLA_RUNSTDBY_Msk = 0x40 // Bit mask of RUNSTDBY field.
	TRNG_CTRLA_RUNSTDBY     = 0x40 // Bit RUNSTDBY.

	// EVCTRL: Event Control
	TRNG_EVCTRL_DATARDYEO_Pos = 0x0 // Position of DATARDYEO field.
	TRNG_EVCTRL_DATARDYEO_Msk = 0x1 // Bit mask of DATARDYEO field.
	TRNG_EVCTRL_DATARDYEO     = 0x1 // Bit DATARDYEO.

	// INTENCLR: Interrupt Enable Clear
	TRNG_INTENCLR_DATARDY_Pos = 0x0 // Position of DATARDY field.
	TRNG_INTENCLR_DATARDY_Msk = 0x1 // Bit mask of DATARDY field.
	TRNG_INTENCLR_DATARDY     = 0x1 // Bit DATARDY.

	// INTENSET: Interrupt Enable Set
	TRNG_INTENSET_DATARDY_Pos = 0x0 // Position of DATARDY field.
	TRNG_INTENSET_DATARDY_Msk = 0x1 // Bit mask of DATARDY field.
	TRNG_INTENSET_DATARDY     = 0x1 // Bit DATARDY.

	// INTFLAG: Interrupt Flag Status and Clear
	TRNG_INTFLAG_DATARDY_Pos = 0x0 // Position of DATARDY field.
	TRNG_INTFLAG_DATARDY_Msk = 0x1 // Bit mask of DATARDY field.
	TRNG_INTFLAG_DATARDY     = 0x1 // Bit DATARDY.

	// DATA: Output Data
	TRNG_DATA_DATA_Pos = 0x0        // Position of DATA field.
	TRNG_DATA_DATA_Msk = 0xffffffff // Bit mask of DATA field.
)

// Bitfields for USB: Universal Serial Bus
const ()

// Bitfields for USB_DEVICE: Universal Serial Bus - DEVICE
const (
	// CTRLA: Control A
	USB_DEVICE_CTRLA_SWRST_Pos    = 0x0  // Position of SWRST field.
	USB_DEVICE_CTRLA_SWRST_Msk    = 0x1  // Bit mask of SWRST field.
	USB_DEVICE_CTRLA_SWRST        = 0x1  // Bit SWRST.
	USB_DEVICE_CTRLA_ENABLE_Pos   = 0x1  // Position of ENABLE field.
	USB_DEVICE_CTRLA_ENABLE_Msk   = 0x2  // Bit mask of ENABLE field.
	USB_DEVICE_CTRLA_ENABLE       = 0x2  // Bit ENABLE.
	USB_DEVICE_CTRLA_RUNSTDBY_Pos = 0x2  // Position of RUNSTDBY field.
	USB_DEVICE_CTRLA_RUNSTDBY_Msk = 0x4  // Bit mask of RUNSTDBY field.
	USB_DEVICE_CTRLA_RUNSTDBY     = 0x4  // Bit RUNSTDBY.
	USB_DEVICE_CTRLA_MODE_Pos     = 0x7  // Position of MODE field.
	USB_DEVICE_CTRLA_MODE_Msk     = 0x80 // Bit mask of MODE field.
	USB_DEVICE_CTRLA_MODE         = 0x80 // Bit MODE.
	USB_DEVICE_CTRLA_MODE_DEVICE  = 0x0  // Device Mode
	USB_DEVICE_CTRLA_MODE_HOST    = 0x1  // Host Mode

	// SYNCBUSY: Synchronization Busy
	USB_DEVICE_SYNCBUSY_SWRST_Pos  = 0x0 // Position of SWRST field.
	USB_DEVICE_SYNCBUSY_SWRST_Msk  = 0x1 // Bit mask of SWRST field.
	USB_DEVICE_SYNCBUSY_SWRST      = 0x1 // Bit SWRST.
	USB_DEVICE_SYNCBUSY_ENABLE_Pos = 0x1 // Position of ENABLE field.
	USB_DEVICE_SYNCBUSY_ENABLE_Msk = 0x2 // Bit mask of ENABLE field.
	USB_DEVICE_SYNCBUSY_ENABLE     = 0x2 // Bit ENABLE.

	// QOSCTRL: USB Quality Of Service
	USB_DEVICE_QOSCTRL_CQOS_Pos = 0x0 // Position of CQOS field.
	USB_DEVICE_QOSCTRL_CQOS_Msk = 0x3 // Bit mask of CQOS field.
	USB_DEVICE_QOSCTRL_DQOS_Pos = 0x2 // Position of DQOS field.
	USB_DEVICE_QOSCTRL_DQOS_Msk = 0xc // Bit mask of DQOS field.

	// CTRLB: DEVICE Control B
	USB_DEVICE_CTRLB_DETACH_Pos    = 0x0   // Position of DETACH field.
	USB_DEVICE_CTRLB_DETACH_Msk    = 0x1   // Bit mask of DETACH field.
	USB_DEVICE_CTRLB_DETACH        = 0x1   // Bit DETACH.
	USB_DEVICE_CTRLB_UPRSM_Pos     = 0x1   // Position of UPRSM field.
	USB_DEVICE_CTRLB_UPRSM_Msk     = 0x2   // Bit mask of UPRSM field.
	USB_DEVICE_CTRLB_UPRSM         = 0x2   // Bit UPRSM.
	USB_DEVICE_CTRLB_SPDCONF_Pos   = 0x2   // Position of SPDCONF field.
	USB_DEVICE_CTRLB_SPDCONF_Msk   = 0xc   // Bit mask of SPDCONF field.
	USB_DEVICE_CTRLB_SPDCONF_FS    = 0x0   // FS : Full Speed
	USB_DEVICE_CTRLB_SPDCONF_LS    = 0x1   // LS : Low Speed
	USB_DEVICE_CTRLB_SPDCONF_HS    = 0x2   // HS : High Speed capable
	USB_DEVICE_CTRLB_SPDCONF_HSTM  = 0x3   // HSTM: High Speed Test Mode (force high-speed mode for test mode)
	USB_DEVICE_CTRLB_NREPLY_Pos    = 0x4   // Position of NREPLY field.
	USB_DEVICE_CTRLB_NREPLY_Msk    = 0x10  // Bit mask of NREPLY field.
	USB_DEVICE_CTRLB_NREPLY        = 0x10  // Bit NREPLY.
	USB_DEVICE_CTRLB_TSTJ_Pos      = 0x5   // Position of TSTJ field.
	USB_DEVICE_CTRLB_TSTJ_Msk      = 0x20  // Bit mask of TSTJ field.
	USB_DEVICE_CTRLB_TSTJ          = 0x20  // Bit TSTJ.
	USB_DEVICE_CTRLB_TSTK_Pos      = 0x6   // Position of TSTK field.
	USB_DEVICE_CTRLB_TSTK_Msk      = 0x40  // Bit mask of TSTK field.
	USB_DEVICE_CTRLB_TSTK          = 0x40  // Bit TSTK.
	USB_DEVICE_CTRLB_TSTPCKT_Pos   = 0x7   // Position of TSTPCKT field.
	USB_DEVICE_CTRLB_TSTPCKT_Msk   = 0x80  // Bit mask of TSTPCKT field.
	USB_DEVICE_CTRLB_TSTPCKT       = 0x80  // Bit TSTPCKT.
	USB_DEVICE_CTRLB_OPMODE2_Pos   = 0x8   // Position of OPMODE2 field.
	USB_DEVICE_CTRLB_OPMODE2_Msk   = 0x100 // Bit mask of OPMODE2 field.
	USB_DEVICE_CTRLB_OPMODE2       = 0x100 // Bit OPMODE2.
	USB_DEVICE_CTRLB_GNAK_Pos      = 0x9   // Position of GNAK field.
	USB_DEVICE_CTRLB_GNAK_Msk      = 0x200 // Bit mask of GNAK field.
	USB_DEVICE_CTRLB_GNAK          = 0x200 // Bit GNAK.
	USB_DEVICE_CTRLB_LPMHDSK_Pos   = 0xa   // Position of LPMHDSK field.
	USB_DEVICE_CTRLB_LPMHDSK_Msk   = 0xc00 // Bit mask of LPMHDSK field.
	USB_DEVICE_CTRLB_LPMHDSK_NO    = 0x0   // No handshake. LPM is not supported
	USB_DEVICE_CTRLB_LPMHDSK_ACK   = 0x1   // ACK
	USB_DEVICE_CTRLB_LPMHDSK_NYET  = 0x2   // NYET
	USB_DEVICE_CTRLB_LPMHDSK_STALL = 0x3   // STALL

	// DADD: DEVICE Device Address
	USB_DEVICE_DADD_DADD_Pos  = 0x0  // Position of DADD field.
	USB_DEVICE_DADD_DADD_Msk  = 0x7f // Bit mask of DADD field.
	USB_DEVICE_DADD_ADDEN_Pos = 0x7  // Position of ADDEN field.
	USB_DEVICE_DADD_ADDEN_Msk = 0x80 // Bit mask of ADDEN field.
	USB_DEVICE_DADD_ADDEN     = 0x80 // Bit ADDEN.

	// STATUS: DEVICE Status
	USB_DEVICE_STATUS_SPEED_Pos     = 0x2  // Position of SPEED field.
	USB_DEVICE_STATUS_SPEED_Msk     = 0xc  // Bit mask of SPEED field.
	USB_DEVICE_STATUS_SPEED_FS      = 0x0  // Full-speed mode
	USB_DEVICE_STATUS_SPEED_LS      = 0x1  // Low-speed mode
	USB_DEVICE_STATUS_SPEED_HS      = 0x2  // High-speed mode
	USB_DEVICE_STATUS_LINESTATE_Pos = 0x6  // Position of LINESTATE field.
	USB_DEVICE_STATUS_LINESTATE_Msk = 0xc0 // Bit mask of LINESTATE field.
	USB_DEVICE_STATUS_LINESTATE_0   = 0x0  // SE0/RESET
	USB_DEVICE_STATUS_LINESTATE_1   = 0x1  // FS-J or LS-K State
	USB_DEVICE_STATUS_LINESTATE_2   = 0x2  // FS-K or LS-J State

	// FSMSTATUS: Finite State Machine Status
	USB_DEVICE_FSMSTATUS_FSMSTATE_Pos      = 0x0  // Position of FSMSTATE field.
	USB_DEVICE_FSMSTATUS_FSMSTATE_Msk      = 0x7f // Bit mask of FSMSTATE field.
	USB_DEVICE_FSMSTATUS_FSMSTATE_OFF      = 0x1  // OFF (L3). It corresponds to the powered-off, disconnected, and disabled state
	USB_DEVICE_FSMSTATUS_FSMSTATE_ON       = 0x2  // ON (L0). It corresponds to the Idle and Active states
	USB_DEVICE_FSMSTATUS_FSMSTATE_SUSPEND  = 0x4  // SUSPEND (L2)
	USB_DEVICE_FSMSTATUS_FSMSTATE_SLEEP    = 0x8  // SLEEP (L1)
	USB_DEVICE_FSMSTATUS_FSMSTATE_DNRESUME = 0x10 // DNRESUME. Down Stream Resume.
	USB_DEVICE_FSMSTATUS_FSMSTATE_UPRESUME = 0x20 // UPRESUME. Up Stream Resume.
	USB_DEVICE_FSMSTATUS_FSMSTATE_RESET    = 0x40 // RESET. USB lines Reset.

	// FNUM: DEVICE Device Frame Number
	USB_DEVICE_FNUM_MFNUM_Pos  = 0x0    // Position of MFNUM field.
	USB_DEVICE_FNUM_MFNUM_Msk  = 0x7    // Bit mask of MFNUM field.
	USB_DEVICE_FNUM_FNUM_Pos   = 0x3    // Position of FNUM field.
	USB_DEVICE_FNUM_FNUM_Msk   = 0x3ff8 // Bit mask of FNUM field.
	USB_DEVICE_FNUM_FNCERR_Pos = 0xf    // Position of FNCERR field.
	USB_DEVICE_FNUM_FNCERR_Msk = 0x8000 // Bit mask of FNCERR field.
	USB_DEVICE_FNUM_FNCERR     = 0x8000 // Bit FNCERR.

	// INTENCLR: DEVICE Device Interrupt Enable Clear
	USB_DEVICE_INTENCLR_SUSPEND_Pos = 0x0   // Position of SUSPEND field.
	USB_DEVICE_INTENCLR_SUSPEND_Msk = 0x1   // Bit mask of SUSPEND field.
	USB_DEVICE_INTENCLR_SUSPEND     = 0x1   // Bit SUSPEND.
	USB_DEVICE_INTENCLR_MSOF_Pos    = 0x1   // Position of MSOF field.
	USB_DEVICE_INTENCLR_MSOF_Msk    = 0x2   // Bit mask of MSOF field.
	USB_DEVICE_INTENCLR_MSOF        = 0x2   // Bit MSOF.
	USB_DEVICE_INTENCLR_SOF_Pos     = 0x2   // Position of SOF field.
	USB_DEVICE_INTENCLR_SOF_Msk     = 0x4   // Bit mask of SOF field.
	USB_DEVICE_INTENCLR_SOF         = 0x4   // Bit SOF.
	USB_DEVICE_INTENCLR_EORST_Pos   = 0x3   // Position of EORST field.
	USB_DEVICE_INTENCLR_EORST_Msk   = 0x8   // Bit mask of EORST field.
	USB_DEVICE_INTENCLR_EORST       = 0x8   // Bit EORST.
	USB_DEVICE_INTENCLR_WAKEUP_Pos  = 0x4   // Position of WAKEUP field.
	USB_DEVICE_INTENCLR_WAKEUP_Msk  = 0x10  // Bit mask of WAKEUP field.
	USB_DEVICE_INTENCLR_WAKEUP      = 0x10  // Bit WAKEUP.
	USB_DEVICE_INTENCLR_EORSM_Pos   = 0x5   // Position of EORSM field.
	USB_DEVICE_INTENCLR_EORSM_Msk   = 0x20  // Bit mask of EORSM field.
	USB_DEVICE_INTENCLR_EORSM       = 0x20  // Bit EORSM.
	USB_DEVICE_INTENCLR_UPRSM_Pos   = 0x6   // Position of UPRSM field.
	USB_DEVICE_INTENCLR_UPRSM_Msk   = 0x40  // Bit mask of UPRSM field.
	USB_DEVICE_INTENCLR_UPRSM       = 0x40  // Bit UPRSM.
	USB_DEVICE_INTENCLR_RAMACER_Pos = 0x7   // Position of RAMACER field.
	USB_DEVICE_INTENCLR_RAMACER_Msk = 0x80  // Bit mask of RAMACER field.
	USB_DEVICE_INTENCLR_RAMACER     = 0x80  // Bit RAMACER.
	USB_DEVICE_INTENCLR_LPMNYET_Pos = 0x8   // Position of LPMNYET field.
	USB_DEVICE_INTENCLR_LPMNYET_Msk = 0x100 // Bit mask of LPMNYET field.
	USB_DEVICE_INTENCLR_LPMNYET     = 0x100 // Bit LPMNYET.
	USB_DEVICE_INTENCLR_LPMSUSP_Pos = 0x9   // Position of LPMSUSP field.
	USB_DEVICE_INTENCLR_LPMSUSP_Msk = 0x200 // Bit mask of LPMSUSP field.
	USB_DEVICE_INTENCLR_LPMSUSP     = 0x200 // Bit LPMSUSP.

	// INTENSET: DEVICE Device Interrupt Enable Set
	USB_DEVICE_INTENSET_SUSPEND_Pos = 0x0   // Position of SUSPEND field.
	USB_DEVICE_INTENSET_SUSPEND_Msk = 0x1   // Bit mask of SUSPEND field.
	USB_DEVICE_INTENSET_SUSPEND     = 0x1   // Bit SUSPEND.
	USB_DEVICE_INTENSET_MSOF_Pos    = 0x1   // Position of MSOF field.
	USB_DEVICE_INTENSET_MSOF_Msk    = 0x2   // Bit mask of MSOF field.
	USB_DEVICE_INTENSET_MSOF        = 0x2   // Bit MSOF.
	USB_DEVICE_INTENSET_SOF_Pos     = 0x2   // Position of SOF field.
	USB_DEVICE_INTENSET_SOF_Msk     = 0x4   // Bit mask of SOF field.
	USB_DEVICE_INTENSET_SOF         = 0x4   // Bit SOF.
	USB_DEVICE_INTENSET_EORST_Pos   = 0x3   // Position of EORST field.
	USB_DEVICE_INTENSET_EORST_Msk   = 0x8   // Bit mask of EORST field.
	USB_DEVICE_INTENSET_EORST       = 0x8   // Bit EORST.
	USB_DEVICE_INTENSET_WAKEUP_Pos  = 0x4   // Position of WAKEUP field.
	USB_DEVICE_INTENSET_WAKEUP_Msk  = 0x10  // Bit mask of WAKEUP field.
	USB_DEVICE_INTENSET_WAKEUP      = 0x10  // Bit WAKEUP.
	USB_DEVICE_INTENSET_EORSM_Pos   = 0x5   // Position of EORSM field.
	USB_DEVICE_INTENSET_EORSM_Msk   = 0x20  // Bit mask of EORSM field.
	USB_DEVICE_INTENSET_EORSM       = 0x20  // Bit EORSM.
	USB_DEVICE_INTENSET_UPRSM_Pos   = 0x6   // Position of UPRSM field.
	USB_DEVICE_INTENSET_UPRSM_Msk   = 0x40  // Bit mask of UPRSM field.
	USB_DEVICE_INTENSET_UPRSM       = 0x40  // Bit UPRSM.
	USB_DEVICE_INTENSET_RAMACER_Pos = 0x7   // Position of RAMACER field.
	USB_DEVICE_INTENSET_RAMACER_Msk = 0x80  // Bit mask of RAMACER field.
	USB_DEVICE_INTENSET_RAMACER     = 0x80  // Bit RAMACER.
	USB_DEVICE_INTENSET_LPMNYET_Pos = 0x8   // Position of LPMNYET field.
	USB_DEVICE_INTENSET_LPMNYET_Msk = 0x100 // Bit mask of LPMNYET field.
	USB_DEVICE_INTENSET_LPMNYET     = 0x100 // Bit LPMNYET.
	USB_DEVICE_INTENSET_LPMSUSP_Pos = 0x9   // Position of LPMSUSP field.
	USB_DEVICE_INTENSET_LPMSUSP_Msk = 0x200 // Bit mask of LPMSUSP field.
	USB_DEVICE_INTENSET_LPMSUSP     = 0x200 // Bit LPMSUSP.

	// INTFLAG: DEVICE Device Interrupt Flag
	USB_DEVICE_INTFLAG_SUSPEND_Pos = 0x0   // Position of SUSPEND field.
	USB_DEVICE_INTFLAG_SUSPEND_Msk = 0x1   // Bit mask of SUSPEND field.
	USB_DEVICE_INTFLAG_SUSPEND     = 0x1   // Bit SUSPEND.
	USB_DEVICE_INTFLAG_MSOF_Pos    = 0x1   // Position of MSOF field.
	USB_DEVICE_INTFLAG_MSOF_Msk    = 0x2   // Bit mask of MSOF field.
	USB_DEVICE_INTFLAG_MSOF        = 0x2   // Bit MSOF.
	USB_DEVICE_INTFLAG_SOF_Pos     = 0x2   // Position of SOF field.
	USB_DEVICE_INTFLAG_SOF_Msk     = 0x4   // Bit mask of SOF field.
	USB_DEVICE_INTFLAG_SOF         = 0x4   // Bit SOF.
	USB_DEVICE_INTFLAG_EORST_Pos   = 0x3   // Position of EORST field.
	USB_DEVICE_INTFLAG_EORST_Msk   = 0x8   // Bit mask of EORST field.
	USB_DEVICE_INTFLAG_EORST       = 0x8   // Bit EORST.
	USB_DEVICE_INTFLAG_WAKEUP_Pos  = 0x4   // Position of WAKEUP field.
	USB_DEVICE_INTFLAG_WAKEUP_Msk  = 0x10  // Bit mask of WAKEUP field.
	USB_DEVICE_INTFLAG_WAKEUP      = 0x10  // Bit WAKEUP.
	USB_DEVICE_INTFLAG_EORSM_Pos   = 0x5   // Position of EORSM field.
	USB_DEVICE_INTFLAG_EORSM_Msk   = 0x20  // Bit mask of EORSM field.
	USB_DEVICE_INTFLAG_EORSM       = 0x20  // Bit EORSM.
	USB_DEVICE_INTFLAG_UPRSM_Pos   = 0x6   // Position of UPRSM field.
	USB_DEVICE_INTFLAG_UPRSM_Msk   = 0x40  // Bit mask of UPRSM field.
	USB_DEVICE_INTFLAG_UPRSM       = 0x40  // Bit UPRSM.
	USB_DEVICE_INTFLAG_RAMACER_Pos = 0x7   // Position of RAMACER field.
	USB_DEVICE_INTFLAG_RAMACER_Msk = 0x80  // Bit mask of RAMACER field.
	USB_DEVICE_INTFLAG_RAMACER     = 0x80  // Bit RAMACER.
	USB_DEVICE_INTFLAG_LPMNYET_Pos = 0x8   // Position of LPMNYET field.
	USB_DEVICE_INTFLAG_LPMNYET_Msk = 0x100 // Bit mask of LPMNYET field.
	USB_DEVICE_INTFLAG_LPMNYET     = 0x100 // Bit LPMNYET.
	USB_DEVICE_INTFLAG_LPMSUSP_Pos = 0x9   // Position of LPMSUSP field.
	USB_DEVICE_INTFLAG_LPMSUSP_Msk = 0x200 // Bit mask of LPMSUSP field.
	USB_DEVICE_INTFLAG_LPMSUSP     = 0x200 // Bit LPMSUSP.

	// EPINTSMRY: DEVICE End Point Interrupt Summary
	USB_DEVICE_EPINTSMRY_EPINT0_Pos = 0x0  // Position of EPINT0 field.
	USB_DEVICE_EPINTSMRY_EPINT0_Msk = 0x1  // Bit mask of EPINT0 field.
	USB_DEVICE_EPINTSMRY_EPINT0     = 0x1  // Bit EPINT0.
	USB_DEVICE_EPINTSMRY_EPINT1_Pos = 0x1  // Position of EPINT1 field.
	USB_DEVICE_EPINTSMRY_EPINT1_Msk = 0x2  // Bit mask of EPINT1 field.
	USB_DEVICE_EPINTSMRY_EPINT1     = 0x2  // Bit EPINT1.
	USB_DEVICE_EPINTSMRY_EPINT2_Pos = 0x2  // Position of EPINT2 field.
	USB_DEVICE_EPINTSMRY_EPINT2_Msk = 0x4  // Bit mask of EPINT2 field.
	USB_DEVICE_EPINTSMRY_EPINT2     = 0x4  // Bit EPINT2.
	USB_DEVICE_EPINTSMRY_EPINT3_Pos = 0x3  // Position of EPINT3 field.
	USB_DEVICE_EPINTSMRY_EPINT3_Msk = 0x8  // Bit mask of EPINT3 field.
	USB_DEVICE_EPINTSMRY_EPINT3     = 0x8  // Bit EPINT3.
	USB_DEVICE_EPINTSMRY_EPINT4_Pos = 0x4  // Position of EPINT4 field.
	USB_DEVICE_EPINTSMRY_EPINT4_Msk = 0x10 // Bit mask of EPINT4 field.
	USB_DEVICE_EPINTSMRY_EPINT4     = 0x10 // Bit EPINT4.
	USB_DEVICE_EPINTSMRY_EPINT5_Pos = 0x5  // Position of EPINT5 field.
	USB_DEVICE_EPINTSMRY_EPINT5_Msk = 0x20 // Bit mask of EPINT5 field.
	USB_DEVICE_EPINTSMRY_EPINT5     = 0x20 // Bit EPINT5.
	USB_DEVICE_EPINTSMRY_EPINT6_Pos = 0x6  // Position of EPINT6 field.
	USB_DEVICE_EPINTSMRY_EPINT6_Msk = 0x40 // Bit mask of EPINT6 field.
	USB_DEVICE_EPINTSMRY_EPINT6     = 0x40 // Bit EPINT6.
	USB_DEVICE_EPINTSMRY_EPINT7_Pos = 0x7  // Position of EPINT7 field.
	USB_DEVICE_EPINTSMRY_EPINT7_Msk = 0x80 // Bit mask of EPINT7 field.
	USB_DEVICE_EPINTSMRY_EPINT7     = 0x80 // Bit EPINT7.

	// DESCADD: Descriptor Address
	USB_DEVICE_DESCADD_DESCADD_Pos = 0x0        // Position of DESCADD field.
	USB_DEVICE_DESCADD_DESCADD_Msk = 0xffffffff // Bit mask of DESCADD field.

	// PADCAL: USB PAD Calibration
	USB_DEVICE_PADCAL_TRANSP_Pos = 0x0    // Position of TRANSP field.
	USB_DEVICE_PADCAL_TRANSP_Msk = 0x1f   // Bit mask of TRANSP field.
	USB_DEVICE_PADCAL_TRANSN_Pos = 0x6    // Position of TRANSN field.
	USB_DEVICE_PADCAL_TRANSN_Msk = 0x7c0  // Bit mask of TRANSN field.
	USB_DEVICE_PADCAL_TRIM_Pos   = 0xc    // Position of TRIM field.
	USB_DEVICE_PADCAL_TRIM_Msk   = 0x7000 // Bit mask of TRIM field.

	// DEVICE_ENDPOINT.EPCFG: DEVICE_ENDPOINT End Point Configuration
	USB_DEVICE_ENDPOINT_EPCFG_EPTYPE0_Pos = 0x0  // Position of EPTYPE0 field.
	USB_DEVICE_ENDPOINT_EPCFG_EPTYPE0_Msk = 0x7  // Bit mask of EPTYPE0 field.
	USB_DEVICE_ENDPOINT_EPCFG_EPTYPE1_Pos = 0x4  // Position of EPTYPE1 field.
	USB_DEVICE_ENDPOINT_EPCFG_EPTYPE1_Msk = 0x70 // Bit mask of EPTYPE1 field.
	USB_DEVICE_ENDPOINT_EPCFG_NYETDIS_Pos = 0x7  // Position of NYETDIS field.
	USB_DEVICE_ENDPOINT_EPCFG_NYETDIS_Msk = 0x80 // Bit mask of NYETDIS field.
	USB_DEVICE_ENDPOINT_EPCFG_NYETDIS     = 0x80 // Bit NYETDIS.

	// DEVICE_ENDPOINT.EPSTATUSCLR: DEVICE_ENDPOINT End Point Pipe Status Clear
	USB_DEVICE_ENDPOINT_EPSTATUSCLR_DTGLOUT_Pos  = 0x0  // Position of DTGLOUT field.
	USB_DEVICE_ENDPOINT_EPSTATUSCLR_DTGLOUT_Msk  = 0x1  // Bit mask of DTGLOUT field.
	USB_DEVICE_ENDPOINT_EPSTATUSCLR_DTGLOUT      = 0x1  // Bit DTGLOUT.
	USB_DEVICE_ENDPOINT_EPSTATUSCLR_DTGLIN_Pos   = 0x1  // Position of DTGLIN field.
	USB_DEVICE_ENDPOINT_EPSTATUSCLR_DTGLIN_Msk   = 0x2  // Bit mask of DTGLIN field.
	USB_DEVICE_ENDPOINT_EPSTATUSCLR_DTGLIN       = 0x2  // Bit DTGLIN.
	USB_DEVICE_ENDPOINT_EPSTATUSCLR_CURBK_Pos    = 0x2  // Position of CURBK field.
	USB_DEVICE_ENDPOINT_EPSTATUSCLR_CURBK_Msk    = 0x4  // Bit mask of CURBK field.
	USB_DEVICE_ENDPOINT_EPSTATUSCLR_CURBK        = 0x4  // Bit CURBK.
	USB_DEVICE_ENDPOINT_EPSTATUSCLR_STALLRQ0_Pos = 0x4  // Position of STALLRQ0 field.
	USB_DEVICE_ENDPOINT_EPSTATUSCLR_STALLRQ0_Msk = 0x10 // Bit mask of STALLRQ0 field.
	USB_DEVICE_ENDPOINT_EPSTATUSCLR_STALLRQ0     = 0x10 // Bit STALLRQ0.
	USB_DEVICE_ENDPOINT_EPSTATUSCLR_STALLRQ1_Pos = 0x5  // Position of STALLRQ1 field.
	USB_DEVICE_ENDPOINT_EPSTATUSCLR_STALLRQ1_Msk = 0x20 // Bit mask of STALLRQ1 field.
	USB_DEVICE_ENDPOINT_EPSTATUSCLR_STALLRQ1     = 0x20 // Bit STALLRQ1.
	USB_DEVICE_ENDPOINT_EPSTATUSCLR_BK0RDY_Pos   = 0x6  // Position of BK0RDY field.
	USB_DEVICE_ENDPOINT_EPSTATUSCLR_BK0RDY_Msk   = 0x40 // Bit mask of BK0RDY field.
	USB_DEVICE_ENDPOINT_EPSTATUSCLR_BK0RDY       = 0x40 // Bit BK0RDY.
	USB_DEVICE_ENDPOINT_EPSTATUSCLR_BK1RDY_Pos   = 0x7  // Position of BK1RDY field.
	USB_DEVICE_ENDPOINT_EPSTATUSCLR_BK1RDY_Msk   = 0x80 // Bit mask of BK1RDY field.
	USB_DEVICE_ENDPOINT_EPSTATUSCLR_BK1RDY       = 0x80 // Bit BK1RDY.

	// DEVICE_ENDPOINT.EPSTATUSSET: DEVICE_ENDPOINT End Point Pipe Status Set
	USB_DEVICE_ENDPOINT_EPSTATUSSET_DTGLOUT_Pos  = 0x0  // Position of DTGLOUT field.
	USB_DEVICE_ENDPOINT_EPSTATUSSET_DTGLOUT_Msk  = 0x1  // Bit mask of DTGLOUT field.
	USB_DEVICE_ENDPOINT_EPSTATUSSET_DTGLOUT      = 0x1  // Bit DTGLOUT.
	USB_DEVICE_ENDPOINT_EPSTATUSSET_DTGLIN_Pos   = 0x1  // Position of DTGLIN field.
	USB_DEVICE_ENDPOINT_EPSTATUSSET_DTGLIN_Msk   = 0x2  // Bit mask of DTGLIN field.
	USB_DEVICE_ENDPOINT_EPSTATUSSET_DTGLIN       = 0x2  // Bit DTGLIN.
	USB_DEVICE_ENDPOINT_EPSTATUSSET_CURBK_Pos    = 0x2  // Position of CURBK field.
	USB_DEVICE_ENDPOINT_EPSTATUSSET_CURBK_Msk    = 0x4  // Bit mask of CURBK field.
	USB_DEVICE_ENDPOINT_EPSTATUSSET_CURBK        = 0x4  // Bit CURBK.
	USB_DEVICE_ENDPOINT_EPSTATUSSET_STALLRQ0_Pos = 0x4  // Position of STALLRQ0 field.
	USB_DEVICE_ENDPOINT_EPSTATUSSET_STALLRQ0_Msk = 0x10 // Bit mask of STALLRQ0 field.
	USB_DEVICE_ENDPOINT_EPSTATUSSET_STALLRQ0     = 0x10 // Bit STALLRQ0.
	USB_DEVICE_ENDPOINT_EPSTATUSSET_STALLRQ1_Pos = 0x5  // Position of STALLRQ1 field.
	USB_DEVICE_ENDPOINT_EPSTATUSSET_STALLRQ1_Msk = 0x20 // Bit mask of STALLRQ1 field.
	USB_DEVICE_ENDPOINT_EPSTATUSSET_STALLRQ1     = 0x20 // Bit STALLRQ1.
	USB_DEVICE_ENDPOINT_EPSTATUSSET_BK0RDY_Pos   = 0x6  // Position of BK0RDY field.
	USB_DEVICE_ENDPOINT_EPSTATUSSET_BK0RDY_Msk   = 0x40 // Bit mask of BK0RDY field.
	USB_DEVICE_ENDPOINT_EPSTATUSSET_BK0RDY       = 0x40 // Bit BK0RDY.
	USB_DEVICE_ENDPOINT_EPSTATUSSET_BK1RDY_Pos   = 0x7  // Position of BK1RDY field.
	USB_DEVICE_ENDPOINT_EPSTATUSSET_BK1RDY_Msk   = 0x80 // Bit mask of BK1RDY field.
	USB_DEVICE_ENDPOINT_EPSTATUSSET_BK1RDY       = 0x80 // Bit BK1RDY.

	// DEVICE_ENDPOINT.EPSTATUS: DEVICE_ENDPOINT End Point Pipe Status
	USB_DEVICE_ENDPOINT_EPSTATUS_DTGLOUT_Pos  = 0x0  // Position of DTGLOUT field.
	USB_DEVICE_ENDPOINT_EPSTATUS_DTGLOUT_Msk  = 0x1  // Bit mask of DTGLOUT field.
	USB_DEVICE_ENDPOINT_EPSTATUS_DTGLOUT      = 0x1  // Bit DTGLOUT.
	USB_DEVICE_ENDPOINT_EPSTATUS_DTGLIN_Pos   = 0x1  // Position of DTGLIN field.
	USB_DEVICE_ENDPOINT_EPSTATUS_DTGLIN_Msk   = 0x2  // Bit mask of DTGLIN field.
	USB_DEVICE_ENDPOINT_EPSTATUS_DTGLIN       = 0x2  // Bit DTGLIN.
	USB_DEVICE_ENDPOINT_EPSTATUS_CURBK_Pos    = 0x2  // Position of CURBK field.
	USB_DEVICE_ENDPOINT_EPSTATUS_CURBK_Msk    = 0x4  // Bit mask of CURBK field.
	USB_DEVICE_ENDPOINT_EPSTATUS_CURBK        = 0x4  // Bit CURBK.
	USB_DEVICE_ENDPOINT_EPSTATUS_STALLRQ0_Pos = 0x4  // Position of STALLRQ0 field.
	USB_DEVICE_ENDPOINT_EPSTATUS_STALLRQ0_Msk = 0x10 // Bit mask of STALLRQ0 field.
	USB_DEVICE_ENDPOINT_EPSTATUS_STALLRQ0     = 0x10 // Bit STALLRQ0.
	USB_DEVICE_ENDPOINT_EPSTATUS_STALLRQ1_Pos = 0x5  // Position of STALLRQ1 field.
	USB_DEVICE_ENDPOINT_EPSTATUS_STALLRQ1_Msk = 0x20 // Bit mask of STALLRQ1 field.
	USB_DEVICE_ENDPOINT_EPSTATUS_STALLRQ1     = 0x20 // Bit STALLRQ1.
	USB_DEVICE_ENDPOINT_EPSTATUS_BK0RDY_Pos   = 0x6  // Position of BK0RDY field.
	USB_DEVICE_ENDPOINT_EPSTATUS_BK0RDY_Msk   = 0x40 // Bit mask of BK0RDY field.
	USB_DEVICE_ENDPOINT_EPSTATUS_BK0RDY       = 0x40 // Bit BK0RDY.
	USB_DEVICE_ENDPOINT_EPSTATUS_BK1RDY_Pos   = 0x7  // Position of BK1RDY field.
	USB_DEVICE_ENDPOINT_EPSTATUS_BK1RDY_Msk   = 0x80 // Bit mask of BK1RDY field.
	USB_DEVICE_ENDPOINT_EPSTATUS_BK1RDY       = 0x80 // Bit BK1RDY.

	// DEVICE_ENDPOINT.EPINTFLAG: DEVICE_ENDPOINT End Point Interrupt Flag
	USB_DEVICE_ENDPOINT_EPINTFLAG_TRCPT0_Pos  = 0x0  // Position of TRCPT0 field.
	USB_DEVICE_ENDPOINT_EPINTFLAG_TRCPT0_Msk  = 0x1  // Bit mask of TRCPT0 field.
	USB_DEVICE_ENDPOINT_EPINTFLAG_TRCPT0      = 0x1  // Bit TRCPT0.
	USB_DEVICE_ENDPOINT_EPINTFLAG_TRCPT1_Pos  = 0x1  // Position of TRCPT1 field.
	USB_DEVICE_ENDPOINT_EPINTFLAG_TRCPT1_Msk  = 0x2  // Bit mask of TRCPT1 field.
	USB_DEVICE_ENDPOINT_EPINTFLAG_TRCPT1      = 0x2  // Bit TRCPT1.
	USB_DEVICE_ENDPOINT_EPINTFLAG_TRFAIL0_Pos = 0x2  // Position of TRFAIL0 field.
	USB_DEVICE_ENDPOINT_EPINTFLAG_TRFAIL0_Msk = 0x4  // Bit mask of TRFAIL0 field.
	USB_DEVICE_ENDPOINT_EPINTFLAG_TRFAIL0     = 0x4  // Bit TRFAIL0.
	USB_DEVICE_ENDPOINT_EPINTFLAG_TRFAIL1_Pos = 0x3  // Position of TRFAIL1 field.
	USB_DEVICE_ENDPOINT_EPINTFLAG_TRFAIL1_Msk = 0x8  // Bit mask of TRFAIL1 field.
	USB_DEVICE_ENDPOINT_EPINTFLAG_TRFAIL1     = 0x8  // Bit TRFAIL1.
	USB_DEVICE_ENDPOINT_EPINTFLAG_RXSTP_Pos   = 0x4  // Position of RXSTP field.
	USB_DEVICE_ENDPOINT_EPINTFLAG_RXSTP_Msk   = 0x10 // Bit mask of RXSTP field.
	USB_DEVICE_ENDPOINT_EPINTFLAG_RXSTP       = 0x10 // Bit RXSTP.
	USB_DEVICE_ENDPOINT_EPINTFLAG_STALL0_Pos  = 0x5  // Position of STALL0 field.
	USB_DEVICE_ENDPOINT_EPINTFLAG_STALL0_Msk  = 0x20 // Bit mask of STALL0 field.
	USB_DEVICE_ENDPOINT_EPINTFLAG_STALL0      = 0x20 // Bit STALL0.
	USB_DEVICE_ENDPOINT_EPINTFLAG_STALL1_Pos  = 0x6  // Position of STALL1 field.
	USB_DEVICE_ENDPOINT_EPINTFLAG_STALL1_Msk  = 0x40 // Bit mask of STALL1 field.
	USB_DEVICE_ENDPOINT_EPINTFLAG_STALL1      = 0x40 // Bit STALL1.

	// DEVICE_ENDPOINT.EPINTENCLR: DEVICE_ENDPOINT End Point Interrupt Clear Flag
	USB_DEVICE_ENDPOINT_EPINTENCLR_TRCPT0_Pos  = 0x0  // Position of TRCPT0 field.
	USB_DEVICE_ENDPOINT_EPINTENCLR_TRCPT0_Msk  = 0x1  // Bit mask of TRCPT0 field.
	USB_DEVICE_ENDPOINT_EPINTENCLR_TRCPT0      = 0x1  // Bit TRCPT0.
	USB_DEVICE_ENDPOINT_EPINTENCLR_TRCPT1_Pos  = 0x1  // Position of TRCPT1 field.
	USB_DEVICE_ENDPOINT_EPINTENCLR_TRCPT1_Msk  = 0x2  // Bit mask of TRCPT1 field.
	USB_DEVICE_ENDPOINT_EPINTENCLR_TRCPT1      = 0x2  // Bit TRCPT1.
	USB_DEVICE_ENDPOINT_EPINTENCLR_TRFAIL0_Pos = 0x2  // Position of TRFAIL0 field.
	USB_DEVICE_ENDPOINT_EPINTENCLR_TRFAIL0_Msk = 0x4  // Bit mask of TRFAIL0 field.
	USB_DEVICE_ENDPOINT_EPINTENCLR_TRFAIL0     = 0x4  // Bit TRFAIL0.
	USB_DEVICE_ENDPOINT_EPINTENCLR_TRFAIL1_Pos = 0x3  // Position of TRFAIL1 field.
	USB_DEVICE_ENDPOINT_EPINTENCLR_TRFAIL1_Msk = 0x8  // Bit mask of TRFAIL1 field.
	USB_DEVICE_ENDPOINT_EPINTENCLR_TRFAIL1     = 0x8  // Bit TRFAIL1.
	USB_DEVICE_ENDPOINT_EPINTENCLR_RXSTP_Pos   = 0x4  // Position of RXSTP field.
	USB_DEVICE_ENDPOINT_EPINTENCLR_RXSTP_Msk   = 0x10 // Bit mask of RXSTP field.
	USB_DEVICE_ENDPOINT_EPINTENCLR_RXSTP       = 0x10 // Bit RXSTP.
	USB_DEVICE_ENDPOINT_EPINTENCLR_STALL0_Pos  = 0x5  // Position of STALL0 field.
	USB_DEVICE_ENDPOINT_EPINTENCLR_STALL0_Msk  = 0x20 // Bit mask of STALL0 field.
	USB_DEVICE_ENDPOINT_EPINTENCLR_STALL0      = 0x20 // Bit STALL0.
	USB_DEVICE_ENDPOINT_EPINTENCLR_STALL1_Pos  = 0x6  // Position of STALL1 field.
	USB_DEVICE_ENDPOINT_EPINTENCLR_STALL1_Msk  = 0x40 // Bit mask of STALL1 field.
	USB_DEVICE_ENDPOINT_EPINTENCLR_STALL1      = 0x40 // Bit STALL1.

	// DEVICE_ENDPOINT.EPINTENSET: DEVICE_ENDPOINT End Point Interrupt Set Flag
	USB_DEVICE_ENDPOINT_EPINTENSET_TRCPT0_Pos  = 0x0  // Position of TRCPT0 field.
	USB_DEVICE_ENDPOINT_EPINTENSET_TRCPT0_Msk  = 0x1  // Bit mask of TRCPT0 field.
	USB_DEVICE_ENDPOINT_EPINTENSET_TRCPT0      = 0x1  // Bit TRCPT0.
	USB_DEVICE_ENDPOINT_EPINTENSET_TRCPT1_Pos  = 0x1  // Position of TRCPT1 field.
	USB_DEVICE_ENDPOINT_EPINTENSET_TRCPT1_Msk  = 0x2  // Bit mask of TRCPT1 field.
	USB_DEVICE_ENDPOINT_EPINTENSET_TRCPT1      = 0x2  // Bit TRCPT1.
	USB_DEVICE_ENDPOINT_EPINTENSET_TRFAIL0_Pos = 0x2  // Position of TRFAIL0 field.
	USB_DEVICE_ENDPOINT_EPINTENSET_TRFAIL0_Msk = 0x4  // Bit mask of TRFAIL0 field.
	USB_DEVICE_ENDPOINT_EPINTENSET_TRFAIL0     = 0x4  // Bit TRFAIL0.
	USB_DEVICE_ENDPOINT_EPINTENSET_TRFAIL1_Pos = 0x3  // Position of TRFAIL1 field.
	USB_DEVICE_ENDPOINT_EPINTENSET_TRFAIL1_Msk = 0x8  // Bit mask of TRFAIL1 field.
	USB_DEVICE_ENDPOINT_EPINTENSET_TRFAIL1     = 0x8  // Bit TRFAIL1.
	USB_DEVICE_ENDPOINT_EPINTENSET_RXSTP_Pos   = 0x4  // Position of RXSTP field.
	USB_DEVICE_ENDPOINT_EPINTENSET_RXSTP_Msk   = 0x10 // Bit mask of RXSTP field.
	USB_DEVICE_ENDPOINT_EPINTENSET_RXSTP       = 0x10 // Bit RXSTP.
	USB_DEVICE_ENDPOINT_EPINTENSET_STALL0_Pos  = 0x5  // Position of STALL0 field.
	USB_DEVICE_ENDPOINT_EPINTENSET_STALL0_Msk  = 0x20 // Bit mask of STALL0 field.
	USB_DEVICE_ENDPOINT_EPINTENSET_STALL0      = 0x20 // Bit STALL0.
	USB_DEVICE_ENDPOINT_EPINTENSET_STALL1_Pos  = 0x6  // Position of STALL1 field.
	USB_DEVICE_ENDPOINT_EPINTENSET_STALL1_Msk  = 0x40 // Bit mask of STALL1 field.
	USB_DEVICE_ENDPOINT_EPINTENSET_STALL1      = 0x40 // Bit STALL1.
)

// Bitfields for USB_HOST: Universal Serial Bus - HOST
const (
	// CTRLA: Control A
	USB_HOST_CTRLA_SWRST_Pos    = 0x0  // Position of SWRST field.
	USB_HOST_CTRLA_SWRST_Msk    = 0x1  // Bit mask of SWRST field.
	USB_HOST_CTRLA_SWRST        = 0x1  // Bit SWRST.
	USB_HOST_CTRLA_ENABLE_Pos   = 0x1  // Position of ENABLE field.
	USB_HOST_CTRLA_ENABLE_Msk   = 0x2  // Bit mask of ENABLE field.
	USB_HOST_CTRLA_ENABLE       = 0x2  // Bit ENABLE.
	USB_HOST_CTRLA_RUNSTDBY_Pos = 0x2  // Position of RUNSTDBY field.
	USB_HOST_CTRLA_RUNSTDBY_Msk = 0x4  // Bit mask of RUNSTDBY field.
	USB_HOST_CTRLA_RUNSTDBY     = 0x4  // Bit RUNSTDBY.
	USB_HOST_CTRLA_MODE_Pos     = 0x7  // Position of MODE field.
	USB_HOST_CTRLA_MODE_Msk     = 0x80 // Bit mask of MODE field.
	USB_HOST_CTRLA_MODE         = 0x80 // Bit MODE.
	USB_HOST_CTRLA_MODE_DEVICE  = 0x0  // Device Mode
	USB_HOST_CTRLA_MODE_HOST    = 0x1  // Host Mode

	// SYNCBUSY: Synchronization Busy
	USB_HOST_SYNCBUSY_SWRST_Pos  = 0x0 // Position of SWRST field.
	USB_HOST_SYNCBUSY_SWRST_Msk  = 0x1 // Bit mask of SWRST field.
	USB_HOST_SYNCBUSY_SWRST      = 0x1 // Bit SWRST.
	USB_HOST_SYNCBUSY_ENABLE_Pos = 0x1 // Position of ENABLE field.
	USB_HOST_SYNCBUSY_ENABLE_Msk = 0x2 // Bit mask of ENABLE field.
	USB_HOST_SYNCBUSY_ENABLE     = 0x2 // Bit ENABLE.

	// QOSCTRL: USB Quality Of Service
	USB_HOST_QOSCTRL_CQOS_Pos = 0x0 // Position of CQOS field.
	USB_HOST_QOSCTRL_CQOS_Msk = 0x3 // Bit mask of CQOS field.
	USB_HOST_QOSCTRL_DQOS_Pos = 0x2 // Position of DQOS field.
	USB_HOST_QOSCTRL_DQOS_Msk = 0xc // Bit mask of DQOS field.

	// CTRLB: HOST Control B
	USB_HOST_CTRLB_RESUME_Pos     = 0x1   // Position of RESUME field.
	USB_HOST_CTRLB_RESUME_Msk     = 0x2   // Bit mask of RESUME field.
	USB_HOST_CTRLB_RESUME         = 0x2   // Bit RESUME.
	USB_HOST_CTRLB_SPDCONF_Pos    = 0x2   // Position of SPDCONF field.
	USB_HOST_CTRLB_SPDCONF_Msk    = 0xc   // Bit mask of SPDCONF field.
	USB_HOST_CTRLB_SPDCONF_NORMAL = 0x0   // Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable.
	USB_HOST_CTRLB_SPDCONF_FS     = 0x3   // Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only.
	USB_HOST_CTRLB_AUTORESUME_Pos = 0x4   // Position of AUTORESUME field.
	USB_HOST_CTRLB_AUTORESUME_Msk = 0x10  // Bit mask of AUTORESUME field.
	USB_HOST_CTRLB_AUTORESUME     = 0x10  // Bit AUTORESUME.
	USB_HOST_CTRLB_TSTJ_Pos       = 0x5   // Position of TSTJ field.
	USB_HOST_CTRLB_TSTJ_Msk       = 0x20  // Bit mask of TSTJ field.
	USB_HOST_CTRLB_TSTJ           = 0x20  // Bit TSTJ.
	USB_HOST_CTRLB_TSTK_Pos       = 0x6   // Position of TSTK field.
	USB_HOST_CTRLB_TSTK_Msk       = 0x40  // Bit mask of TSTK field.
	USB_HOST_CTRLB_TSTK           = 0x40  // Bit TSTK.
	USB_HOST_CTRLB_SOFE_Pos       = 0x8   // Position of SOFE field.
	USB_HOST_CTRLB_SOFE_Msk       = 0x100 // Bit mask of SOFE field.
	USB_HOST_CTRLB_SOFE           = 0x100 // Bit SOFE.
	USB_HOST_CTRLB_BUSRESET_Pos   = 0x9   // Position of BUSRESET field.
	USB_HOST_CTRLB_BUSRESET_Msk   = 0x200 // Bit mask of BUSRESET field.
	USB_HOST_CTRLB_BUSRESET       = 0x200 // Bit BUSRESET.
	USB_HOST_CTRLB_VBUSOK_Pos     = 0xa   // Position of VBUSOK field.
	USB_HOST_CTRLB_VBUSOK_Msk     = 0x400 // Bit mask of VBUSOK field.
	USB_HOST_CTRLB_VBUSOK         = 0x400 // Bit VBUSOK.
	USB_HOST_CTRLB_L1RESUME_Pos   = 0xb   // Position of L1RESUME field.
	USB_HOST_CTRLB_L1RESUME_Msk   = 0x800 // Bit mask of L1RESUME field.
	USB_HOST_CTRLB_L1RESUME       = 0x800 // Bit L1RESUME.

	// HSOFC: HOST Host Start Of Frame Control
	USB_HOST_HSOFC_FLENC_Pos  = 0x0  // Position of FLENC field.
	USB_HOST_HSOFC_FLENC_Msk  = 0xf  // Bit mask of FLENC field.
	USB_HOST_HSOFC_FLENCE_Pos = 0x7  // Position of FLENCE field.
	USB_HOST_HSOFC_FLENCE_Msk = 0x80 // Bit mask of FLENCE field.
	USB_HOST_HSOFC_FLENCE     = 0x80 // Bit FLENCE.

	// STATUS: HOST Status
	USB_HOST_STATUS_SPEED_Pos     = 0x2  // Position of SPEED field.
	USB_HOST_STATUS_SPEED_Msk     = 0xc  // Bit mask of SPEED field.
	USB_HOST_STATUS_LINESTATE_Pos = 0x6  // Position of LINESTATE field.
	USB_HOST_STATUS_LINESTATE_Msk = 0xc0 // Bit mask of LINESTATE field.

	// FSMSTATUS: Finite State Machine Status
	USB_HOST_FSMSTATUS_FSMSTATE_Pos      = 0x0  // Position of FSMSTATE field.
	USB_HOST_FSMSTATUS_FSMSTATE_Msk      = 0x7f // Bit mask of FSMSTATE field.
	USB_HOST_FSMSTATUS_FSMSTATE_OFF      = 0x1  // OFF (L3). It corresponds to the powered-off, disconnected, and disabled state
	USB_HOST_FSMSTATUS_FSMSTATE_ON       = 0x2  // ON (L0). It corresponds to the Idle and Active states
	USB_HOST_FSMSTATUS_FSMSTATE_SUSPEND  = 0x4  // SUSPEND (L2)
	USB_HOST_FSMSTATUS_FSMSTATE_SLEEP    = 0x8  // SLEEP (L1)
	USB_HOST_FSMSTATUS_FSMSTATE_DNRESUME = 0x10 // DNRESUME. Down Stream Resume.
	USB_HOST_FSMSTATUS_FSMSTATE_UPRESUME = 0x20 // UPRESUME. Up Stream Resume.
	USB_HOST_FSMSTATUS_FSMSTATE_RESET    = 0x40 // RESET. USB lines Reset.

	// FNUM: HOST Host Frame Number
	USB_HOST_FNUM_MFNUM_Pos = 0x0    // Position of MFNUM field.
	USB_HOST_FNUM_MFNUM_Msk = 0x7    // Bit mask of MFNUM field.
	USB_HOST_FNUM_FNUM_Pos  = 0x3    // Position of FNUM field.
	USB_HOST_FNUM_FNUM_Msk  = 0x3ff8 // Bit mask of FNUM field.

	// FLENHIGH: HOST Host Frame Length
	USB_HOST_FLENHIGH_FLENHIGH_Pos = 0x0  // Position of FLENHIGH field.
	USB_HOST_FLENHIGH_FLENHIGH_Msk = 0xff // Bit mask of FLENHIGH field.

	// INTENCLR: HOST Host Interrupt Enable Clear
	USB_HOST_INTENCLR_HSOF_Pos    = 0x2   // Position of HSOF field.
	USB_HOST_INTENCLR_HSOF_Msk    = 0x4   // Bit mask of HSOF field.
	USB_HOST_INTENCLR_HSOF        = 0x4   // Bit HSOF.
	USB_HOST_INTENCLR_RST_Pos     = 0x3   // Position of RST field.
	USB_HOST_INTENCLR_RST_Msk     = 0x8   // Bit mask of RST field.
	USB_HOST_INTENCLR_RST         = 0x8   // Bit RST.
	USB_HOST_INTENCLR_WAKEUP_Pos  = 0x4   // Position of WAKEUP field.
	USB_HOST_INTENCLR_WAKEUP_Msk  = 0x10  // Bit mask of WAKEUP field.
	USB_HOST_INTENCLR_WAKEUP      = 0x10  // Bit WAKEUP.
	USB_HOST_INTENCLR_DNRSM_Pos   = 0x5   // Position of DNRSM field.
	USB_HOST_INTENCLR_DNRSM_Msk   = 0x20  // Bit mask of DNRSM field.
	USB_HOST_INTENCLR_DNRSM       = 0x20  // Bit DNRSM.
	USB_HOST_INTENCLR_UPRSM_Pos   = 0x6   // Position of UPRSM field.
	USB_HOST_INTENCLR_UPRSM_Msk   = 0x40  // Bit mask of UPRSM field.
	USB_HOST_INTENCLR_UPRSM       = 0x40  // Bit UPRSM.
	USB_HOST_INTENCLR_RAMACER_Pos = 0x7   // Position of RAMACER field.
	USB_HOST_INTENCLR_RAMACER_Msk = 0x80  // Bit mask of RAMACER field.
	USB_HOST_INTENCLR_RAMACER     = 0x80  // Bit RAMACER.
	USB_HOST_INTENCLR_DCONN_Pos   = 0x8   // Position of DCONN field.
	USB_HOST_INTENCLR_DCONN_Msk   = 0x100 // Bit mask of DCONN field.
	USB_HOST_INTENCLR_DCONN       = 0x100 // Bit DCONN.
	USB_HOST_INTENCLR_DDISC_Pos   = 0x9   // Position of DDISC field.
	USB_HOST_INTENCLR_DDISC_Msk   = 0x200 // Bit mask of DDISC field.
	USB_HOST_INTENCLR_DDISC       = 0x200 // Bit DDISC.

	// INTENSET: HOST Host Interrupt Enable Set
	USB_HOST_INTENSET_HSOF_Pos    = 0x2   // Position of HSOF field.
	USB_HOST_INTENSET_HSOF_Msk    = 0x4   // Bit mask of HSOF field.
	USB_HOST_INTENSET_HSOF        = 0x4   // Bit HSOF.
	USB_HOST_INTENSET_RST_Pos     = 0x3   // Position of RST field.
	USB_HOST_INTENSET_RST_Msk     = 0x8   // Bit mask of RST field.
	USB_HOST_INTENSET_RST         = 0x8   // Bit RST.
	USB_HOST_INTENSET_WAKEUP_Pos  = 0x4   // Position of WAKEUP field.
	USB_HOST_INTENSET_WAKEUP_Msk  = 0x10  // Bit mask of WAKEUP field.
	USB_HOST_INTENSET_WAKEUP      = 0x10  // Bit WAKEUP.
	USB_HOST_INTENSET_DNRSM_Pos   = 0x5   // Position of DNRSM field.
	USB_HOST_INTENSET_DNRSM_Msk   = 0x20  // Bit mask of DNRSM field.
	USB_HOST_INTENSET_DNRSM       = 0x20  // Bit DNRSM.
	USB_HOST_INTENSET_UPRSM_Pos   = 0x6   // Position of UPRSM field.
	USB_HOST_INTENSET_UPRSM_Msk   = 0x40  // Bit mask of UPRSM field.
	USB_HOST_INTENSET_UPRSM       = 0x40  // Bit UPRSM.
	USB_HOST_INTENSET_RAMACER_Pos = 0x7   // Position of RAMACER field.
	USB_HOST_INTENSET_RAMACER_Msk = 0x80  // Bit mask of RAMACER field.
	USB_HOST_INTENSET_RAMACER     = 0x80  // Bit RAMACER.
	USB_HOST_INTENSET_DCONN_Pos   = 0x8   // Position of DCONN field.
	USB_HOST_INTENSET_DCONN_Msk   = 0x100 // Bit mask of DCONN field.
	USB_HOST_INTENSET_DCONN       = 0x100 // Bit DCONN.
	USB_HOST_INTENSET_DDISC_Pos   = 0x9   // Position of DDISC field.
	USB_HOST_INTENSET_DDISC_Msk   = 0x200 // Bit mask of DDISC field.
	USB_HOST_INTENSET_DDISC       = 0x200 // Bit DDISC.

	// INTFLAG: HOST Host Interrupt Flag
	USB_HOST_INTFLAG_HSOF_Pos    = 0x2   // Position of HSOF field.
	USB_HOST_INTFLAG_HSOF_Msk    = 0x4   // Bit mask of HSOF field.
	USB_HOST_INTFLAG_HSOF        = 0x4   // Bit HSOF.
	USB_HOST_INTFLAG_RST_Pos     = 0x3   // Position of RST field.
	USB_HOST_INTFLAG_RST_Msk     = 0x8   // Bit mask of RST field.
	USB_HOST_INTFLAG_RST         = 0x8   // Bit RST.
	USB_HOST_INTFLAG_WAKEUP_Pos  = 0x4   // Position of WAKEUP field.
	USB_HOST_INTFLAG_WAKEUP_Msk  = 0x10  // Bit mask of WAKEUP field.
	USB_HOST_INTFLAG_WAKEUP      = 0x10  // Bit WAKEUP.
	USB_HOST_INTFLAG_DNRSM_Pos   = 0x5   // Position of DNRSM field.
	USB_HOST_INTFLAG_DNRSM_Msk   = 0x20  // Bit mask of DNRSM field.
	USB_HOST_INTFLAG_DNRSM       = 0x20  // Bit DNRSM.
	USB_HOST_INTFLAG_UPRSM_Pos   = 0x6   // Position of UPRSM field.
	USB_HOST_INTFLAG_UPRSM_Msk   = 0x40  // Bit mask of UPRSM field.
	USB_HOST_INTFLAG_UPRSM       = 0x40  // Bit UPRSM.
	USB_HOST_INTFLAG_RAMACER_Pos = 0x7   // Position of RAMACER field.
	USB_HOST_INTFLAG_RAMACER_Msk = 0x80  // Bit mask of RAMACER field.
	USB_HOST_INTFLAG_RAMACER     = 0x80  // Bit RAMACER.
	USB_HOST_INTFLAG_DCONN_Pos   = 0x8   // Position of DCONN field.
	USB_HOST_INTFLAG_DCONN_Msk   = 0x100 // Bit mask of DCONN field.
	USB_HOST_INTFLAG_DCONN       = 0x100 // Bit DCONN.
	USB_HOST_INTFLAG_DDISC_Pos   = 0x9   // Position of DDISC field.
	USB_HOST_INTFLAG_DDISC_Msk   = 0x200 // Bit mask of DDISC field.
	USB_HOST_INTFLAG_DDISC       = 0x200 // Bit DDISC.

	// PINTSMRY: HOST Pipe Interrupt Summary
	USB_HOST_PINTSMRY_EPINT0_Pos = 0x0  // Position of EPINT0 field.
	USB_HOST_PINTSMRY_EPINT0_Msk = 0x1  // Bit mask of EPINT0 field.
	USB_HOST_PINTSMRY_EPINT0     = 0x1  // Bit EPINT0.
	USB_HOST_PINTSMRY_EPINT1_Pos = 0x1  // Position of EPINT1 field.
	USB_HOST_PINTSMRY_EPINT1_Msk = 0x2  // Bit mask of EPINT1 field.
	USB_HOST_PINTSMRY_EPINT1     = 0x2  // Bit EPINT1.
	USB_HOST_PINTSMRY_EPINT2_Pos = 0x2  // Position of EPINT2 field.
	USB_HOST_PINTSMRY_EPINT2_Msk = 0x4  // Bit mask of EPINT2 field.
	USB_HOST_PINTSMRY_EPINT2     = 0x4  // Bit EPINT2.
	USB_HOST_PINTSMRY_EPINT3_Pos = 0x3  // Position of EPINT3 field.
	USB_HOST_PINTSMRY_EPINT3_Msk = 0x8  // Bit mask of EPINT3 field.
	USB_HOST_PINTSMRY_EPINT3     = 0x8  // Bit EPINT3.
	USB_HOST_PINTSMRY_EPINT4_Pos = 0x4  // Position of EPINT4 field.
	USB_HOST_PINTSMRY_EPINT4_Msk = 0x10 // Bit mask of EPINT4 field.
	USB_HOST_PINTSMRY_EPINT4     = 0x10 // Bit EPINT4.
	USB_HOST_PINTSMRY_EPINT5_Pos = 0x5  // Position of EPINT5 field.
	USB_HOST_PINTSMRY_EPINT5_Msk = 0x20 // Bit mask of EPINT5 field.
	USB_HOST_PINTSMRY_EPINT5     = 0x20 // Bit EPINT5.
	USB_HOST_PINTSMRY_EPINT6_Pos = 0x6  // Position of EPINT6 field.
	USB_HOST_PINTSMRY_EPINT6_Msk = 0x40 // Bit mask of EPINT6 field.
	USB_HOST_PINTSMRY_EPINT6     = 0x40 // Bit EPINT6.
	USB_HOST_PINTSMRY_EPINT7_Pos = 0x7  // Position of EPINT7 field.
	USB_HOST_PINTSMRY_EPINT7_Msk = 0x80 // Bit mask of EPINT7 field.
	USB_HOST_PINTSMRY_EPINT7     = 0x80 // Bit EPINT7.

	// DESCADD: Descriptor Address
	USB_HOST_DESCADD_DESCADD_Pos = 0x0        // Position of DESCADD field.
	USB_HOST_DESCADD_DESCADD_Msk = 0xffffffff // Bit mask of DESCADD field.

	// PADCAL: USB PAD Calibration
	USB_HOST_PADCAL_TRANSP_Pos = 0x0    // Position of TRANSP field.
	USB_HOST_PADCAL_TRANSP_Msk = 0x1f   // Bit mask of TRANSP field.
	USB_HOST_PADCAL_TRANSN_Pos = 0x6    // Position of TRANSN field.
	USB_HOST_PADCAL_TRANSN_Msk = 0x7c0  // Bit mask of TRANSN field.
	USB_HOST_PADCAL_TRIM_Pos   = 0xc    // Position of TRIM field.
	USB_HOST_PADCAL_TRIM_Msk   = 0x7000 // Bit mask of TRIM field.

	// HOST_PIPE.PCFG: HOST_PIPE End Point Configuration
	USB_HOST_PIPE_PCFG_PTOKEN_Pos = 0x0  // Position of PTOKEN field.
	USB_HOST_PIPE_PCFG_PTOKEN_Msk = 0x3  // Bit mask of PTOKEN field.
	USB_HOST_PIPE_PCFG_BK_Pos     = 0x2  // Position of BK field.
	USB_HOST_PIPE_PCFG_BK_Msk     = 0x4  // Bit mask of BK field.
	USB_HOST_PIPE_PCFG_BK         = 0x4  // Bit BK.
	USB_HOST_PIPE_PCFG_PTYPE_Pos  = 0x3  // Position of PTYPE field.
	USB_HOST_PIPE_PCFG_PTYPE_Msk  = 0x38 // Bit mask of PTYPE field.

	// HOST_PIPE.BINTERVAL: HOST_PIPE Bus Access Period of Pipe
	USB_HOST_PIPE_BINTERVAL_BITINTERVAL_Pos = 0x0  // Position of BITINTERVAL field.
	USB_HOST_PIPE_BINTERVAL_BITINTERVAL_Msk = 0xff // Bit mask of BITINTERVAL field.

	// HOST_PIPE.PSTATUSCLR: HOST_PIPE End Point Pipe Status Clear
	USB_HOST_PIPE_PSTATUSCLR_DTGL_Pos    = 0x0  // Position of DTGL field.
	USB_HOST_PIPE_PSTATUSCLR_DTGL_Msk    = 0x1  // Bit mask of DTGL field.
	USB_HOST_PIPE_PSTATUSCLR_DTGL        = 0x1  // Bit DTGL.
	USB_HOST_PIPE_PSTATUSCLR_CURBK_Pos   = 0x2  // Position of CURBK field.
	USB_HOST_PIPE_PSTATUSCLR_CURBK_Msk   = 0x4  // Bit mask of CURBK field.
	USB_HOST_PIPE_PSTATUSCLR_CURBK       = 0x4  // Bit CURBK.
	USB_HOST_PIPE_PSTATUSCLR_PFREEZE_Pos = 0x4  // Position of PFREEZE field.
	USB_HOST_PIPE_PSTATUSCLR_PFREEZE_Msk = 0x10 // Bit mask of PFREEZE field.
	USB_HOST_PIPE_PSTATUSCLR_PFREEZE     = 0x10 // Bit PFREEZE.
	USB_HOST_PIPE_PSTATUSCLR_BK0RDY_Pos  = 0x6  // Position of BK0RDY field.
	USB_HOST_PIPE_PSTATUSCLR_BK0RDY_Msk  = 0x40 // Bit mask of BK0RDY field.
	USB_HOST_PIPE_PSTATUSCLR_BK0RDY      = 0x40 // Bit BK0RDY.
	USB_HOST_PIPE_PSTATUSCLR_BK1RDY_Pos  = 0x7  // Position of BK1RDY field.
	USB_HOST_PIPE_PSTATUSCLR_BK1RDY_Msk  = 0x80 // Bit mask of BK1RDY field.
	USB_HOST_PIPE_PSTATUSCLR_BK1RDY      = 0x80 // Bit BK1RDY.

	// HOST_PIPE.PSTATUSSET: HOST_PIPE End Point Pipe Status Set
	USB_HOST_PIPE_PSTATUSSET_DTGL_Pos    = 0x0  // Position of DTGL field.
	USB_HOST_PIPE_PSTATUSSET_DTGL_Msk    = 0x1  // Bit mask of DTGL field.
	USB_HOST_PIPE_PSTATUSSET_DTGL        = 0x1  // Bit DTGL.
	USB_HOST_PIPE_PSTATUSSET_CURBK_Pos   = 0x2  // Position of CURBK field.
	USB_HOST_PIPE_PSTATUSSET_CURBK_Msk   = 0x4  // Bit mask of CURBK field.
	USB_HOST_PIPE_PSTATUSSET_CURBK       = 0x4  // Bit CURBK.
	USB_HOST_PIPE_PSTATUSSET_PFREEZE_Pos = 0x4  // Position of PFREEZE field.
	USB_HOST_PIPE_PSTATUSSET_PFREEZE_Msk = 0x10 // Bit mask of PFREEZE field.
	USB_HOST_PIPE_PSTATUSSET_PFREEZE     = 0x10 // Bit PFREEZE.
	USB_HOST_PIPE_PSTATUSSET_BK0RDY_Pos  = 0x6  // Position of BK0RDY field.
	USB_HOST_PIPE_PSTATUSSET_BK0RDY_Msk  = 0x40 // Bit mask of BK0RDY field.
	USB_HOST_PIPE_PSTATUSSET_BK0RDY      = 0x40 // Bit BK0RDY.
	USB_HOST_PIPE_PSTATUSSET_BK1RDY_Pos  = 0x7  // Position of BK1RDY field.
	USB_HOST_PIPE_PSTATUSSET_BK1RDY_Msk  = 0x80 // Bit mask of BK1RDY field.
	USB_HOST_PIPE_PSTATUSSET_BK1RDY      = 0x80 // Bit BK1RDY.

	// HOST_PIPE.PSTATUS: HOST_PIPE End Point Pipe Status
	USB_HOST_PIPE_PSTATUS_DTGL_Pos    = 0x0  // Position of DTGL field.
	USB_HOST_PIPE_PSTATUS_DTGL_Msk    = 0x1  // Bit mask of DTGL field.
	USB_HOST_PIPE_PSTATUS_DTGL        = 0x1  // Bit DTGL.
	USB_HOST_PIPE_PSTATUS_CURBK_Pos   = 0x2  // Position of CURBK field.
	USB_HOST_PIPE_PSTATUS_CURBK_Msk   = 0x4  // Bit mask of CURBK field.
	USB_HOST_PIPE_PSTATUS_CURBK       = 0x4  // Bit CURBK.
	USB_HOST_PIPE_PSTATUS_PFREEZE_Pos = 0x4  // Position of PFREEZE field.
	USB_HOST_PIPE_PSTATUS_PFREEZE_Msk = 0x10 // Bit mask of PFREEZE field.
	USB_HOST_PIPE_PSTATUS_PFREEZE     = 0x10 // Bit PFREEZE.
	USB_HOST_PIPE_PSTATUS_BK0RDY_Pos  = 0x6  // Position of BK0RDY field.
	USB_HOST_PIPE_PSTATUS_BK0RDY_Msk  = 0x40 // Bit mask of BK0RDY field.
	USB_HOST_PIPE_PSTATUS_BK0RDY      = 0x40 // Bit BK0RDY.
	USB_HOST_PIPE_PSTATUS_BK1RDY_Pos  = 0x7  // Position of BK1RDY field.
	USB_HOST_PIPE_PSTATUS_BK1RDY_Msk  = 0x80 // Bit mask of BK1RDY field.
	USB_HOST_PIPE_PSTATUS_BK1RDY      = 0x80 // Bit BK1RDY.

	// HOST_PIPE.PINTFLAG: HOST_PIPE Pipe Interrupt Flag
	USB_HOST_PIPE_PINTFLAG_TRCPT0_Pos = 0x0  // Position of TRCPT0 field.
	USB_HOST_PIPE_PINTFLAG_TRCPT0_Msk = 0x1  // Bit mask of TRCPT0 field.
	USB_HOST_PIPE_PINTFLAG_TRCPT0     = 0x1  // Bit TRCPT0.
	USB_HOST_PIPE_PINTFLAG_TRCPT1_Pos = 0x1  // Position of TRCPT1 field.
	USB_HOST_PIPE_PINTFLAG_TRCPT1_Msk = 0x2  // Bit mask of TRCPT1 field.
	USB_HOST_PIPE_PINTFLAG_TRCPT1     = 0x2  // Bit TRCPT1.
	USB_HOST_PIPE_PINTFLAG_TRFAIL_Pos = 0x2  // Position of TRFAIL field.
	USB_HOST_PIPE_PINTFLAG_TRFAIL_Msk = 0x4  // Bit mask of TRFAIL field.
	USB_HOST_PIPE_PINTFLAG_TRFAIL     = 0x4  // Bit TRFAIL.
	USB_HOST_PIPE_PINTFLAG_PERR_Pos   = 0x3  // Position of PERR field.
	USB_HOST_PIPE_PINTFLAG_PERR_Msk   = 0x8  // Bit mask of PERR field.
	USB_HOST_PIPE_PINTFLAG_PERR       = 0x8  // Bit PERR.
	USB_HOST_PIPE_PINTFLAG_TXSTP_Pos  = 0x4  // Position of TXSTP field.
	USB_HOST_PIPE_PINTFLAG_TXSTP_Msk  = 0x10 // Bit mask of TXSTP field.
	USB_HOST_PIPE_PINTFLAG_TXSTP      = 0x10 // Bit TXSTP.
	USB_HOST_PIPE_PINTFLAG_STALL_Pos  = 0x5  // Position of STALL field.
	USB_HOST_PIPE_PINTFLAG_STALL_Msk  = 0x20 // Bit mask of STALL field.
	USB_HOST_PIPE_PINTFLAG_STALL      = 0x20 // Bit STALL.

	// HOST_PIPE.PINTENCLR: HOST_PIPE Pipe Interrupt Flag Clear
	USB_HOST_PIPE_PINTENCLR_TRCPT0_Pos = 0x0  // Position of TRCPT0 field.
	USB_HOST_PIPE_PINTENCLR_TRCPT0_Msk = 0x1  // Bit mask of TRCPT0 field.
	USB_HOST_PIPE_PINTENCLR_TRCPT0     = 0x1  // Bit TRCPT0.
	USB_HOST_PIPE_PINTENCLR_TRCPT1_Pos = 0x1  // Position of TRCPT1 field.
	USB_HOST_PIPE_PINTENCLR_TRCPT1_Msk = 0x2  // Bit mask of TRCPT1 field.
	USB_HOST_PIPE_PINTENCLR_TRCPT1     = 0x2  // Bit TRCPT1.
	USB_HOST_PIPE_PINTENCLR_TRFAIL_Pos = 0x2  // Position of TRFAIL field.
	USB_HOST_PIPE_PINTENCLR_TRFAIL_Msk = 0x4  // Bit mask of TRFAIL field.
	USB_HOST_PIPE_PINTENCLR_TRFAIL     = 0x4  // Bit TRFAIL.
	USB_HOST_PIPE_PINTENCLR_PERR_Pos   = 0x3  // Position of PERR field.
	USB_HOST_PIPE_PINTENCLR_PERR_Msk   = 0x8  // Bit mask of PERR field.
	USB_HOST_PIPE_PINTENCLR_PERR       = 0x8  // Bit PERR.
	USB_HOST_PIPE_PINTENCLR_TXSTP_Pos  = 0x4  // Position of TXSTP field.
	USB_HOST_PIPE_PINTENCLR_TXSTP_Msk  = 0x10 // Bit mask of TXSTP field.
	USB_HOST_PIPE_PINTENCLR_TXSTP      = 0x10 // Bit TXSTP.
	USB_HOST_PIPE_PINTENCLR_STALL_Pos  = 0x5  // Position of STALL field.
	USB_HOST_PIPE_PINTENCLR_STALL_Msk  = 0x20 // Bit mask of STALL field.
	USB_HOST_PIPE_PINTENCLR_STALL      = 0x20 // Bit STALL.

	// HOST_PIPE.PINTENSET: HOST_PIPE Pipe Interrupt Flag Set
	USB_HOST_PIPE_PINTENSET_TRCPT0_Pos = 0x0  // Position of TRCPT0 field.
	USB_HOST_PIPE_PINTENSET_TRCPT0_Msk = 0x1  // Bit mask of TRCPT0 field.
	USB_HOST_PIPE_PINTENSET_TRCPT0     = 0x1  // Bit TRCPT0.
	USB_HOST_PIPE_PINTENSET_TRCPT1_Pos = 0x1  // Position of TRCPT1 field.
	USB_HOST_PIPE_PINTENSET_TRCPT1_Msk = 0x2  // Bit mask of TRCPT1 field.
	USB_HOST_PIPE_PINTENSET_TRCPT1     = 0x2  // Bit TRCPT1.
	USB_HOST_PIPE_PINTENSET_TRFAIL_Pos = 0x2  // Position of TRFAIL field.
	USB_HOST_PIPE_PINTENSET_TRFAIL_Msk = 0x4  // Bit mask of TRFAIL field.
	USB_HOST_PIPE_PINTENSET_TRFAIL     = 0x4  // Bit TRFAIL.
	USB_HOST_PIPE_PINTENSET_PERR_Pos   = 0x3  // Position of PERR field.
	USB_HOST_PIPE_PINTENSET_PERR_Msk   = 0x8  // Bit mask of PERR field.
	USB_HOST_PIPE_PINTENSET_PERR       = 0x8  // Bit PERR.
	USB_HOST_PIPE_PINTENSET_TXSTP_Pos  = 0x4  // Position of TXSTP field.
	USB_HOST_PIPE_PINTENSET_TXSTP_Msk  = 0x10 // Bit mask of TXSTP field.
	USB_HOST_PIPE_PINTENSET_TXSTP      = 0x10 // Bit TXSTP.
	USB_HOST_PIPE_PINTENSET_STALL_Pos  = 0x5  // Position of STALL field.
	USB_HOST_PIPE_PINTENSET_STALL_Msk  = 0x20 // Bit mask of STALL field.
	USB_HOST_PIPE_PINTENSET_STALL      = 0x20 // Bit STALL.
)

// Bitfields for WDT: Watchdog Timer
const (
	// CTRLA: Control
	WDT_CTRLA_ENABLE_Pos   = 0x1  // Position of ENABLE field.
	WDT_CTRLA_ENABLE_Msk   = 0x2  // Bit mask of ENABLE field.
	WDT_CTRLA_ENABLE       = 0x2  // Bit ENABLE.
	WDT_CTRLA_WEN_Pos      = 0x2  // Position of WEN field.
	WDT_CTRLA_WEN_Msk      = 0x4  // Bit mask of WEN field.
	WDT_CTRLA_WEN          = 0x4  // Bit WEN.
	WDT_CTRLA_ALWAYSON_Pos = 0x7  // Position of ALWAYSON field.
	WDT_CTRLA_ALWAYSON_Msk = 0x80 // Bit mask of ALWAYSON field.
	WDT_CTRLA_ALWAYSON     = 0x80 // Bit ALWAYSON.

	// CONFIG: Configuration
	WDT_CONFIG_PER_Pos         = 0x0  // Position of PER field.
	WDT_CONFIG_PER_Msk         = 0xf  // Bit mask of PER field.
	WDT_CONFIG_PER_CYC8        = 0x0  // 8 clock cycles
	WDT_CONFIG_PER_CYC16       = 0x1  // 16 clock cycles
	WDT_CONFIG_PER_CYC32       = 0x2  // 32 clock cycles
	WDT_CONFIG_PER_CYC64       = 0x3  // 64 clock cycles
	WDT_CONFIG_PER_CYC128      = 0x4  // 128 clock cycles
	WDT_CONFIG_PER_CYC256      = 0x5  // 256 clock cycles
	WDT_CONFIG_PER_CYC512      = 0x6  // 512 clock cycles
	WDT_CONFIG_PER_CYC1024     = 0x7  // 1024 clock cycles
	WDT_CONFIG_PER_CYC2048     = 0x8  // 2048 clock cycles
	WDT_CONFIG_PER_CYC4096     = 0x9  // 4096 clock cycles
	WDT_CONFIG_PER_CYC8192     = 0xa  // 8192 clock cycles
	WDT_CONFIG_PER_CYC16384    = 0xb  // 16384 clock cycles
	WDT_CONFIG_WINDOW_Pos      = 0x4  // Position of WINDOW field.
	WDT_CONFIG_WINDOW_Msk      = 0xf0 // Bit mask of WINDOW field.
	WDT_CONFIG_WINDOW_CYC8     = 0x0  // 8 clock cycles
	WDT_CONFIG_WINDOW_CYC16    = 0x1  // 16 clock cycles
	WDT_CONFIG_WINDOW_CYC32    = 0x2  // 32 clock cycles
	WDT_CONFIG_WINDOW_CYC64    = 0x3  // 64 clock cycles
	WDT_CONFIG_WINDOW_CYC128   = 0x4  // 128 clock cycles
	WDT_CONFIG_WINDOW_CYC256   = 0x5  // 256 clock cycles
	WDT_CONFIG_WINDOW_CYC512   = 0x6  // 512 clock cycles
	WDT_CONFIG_WINDOW_CYC1024  = 0x7  // 1024 clock cycles
	WDT_CONFIG_WINDOW_CYC2048  = 0x8  // 2048 clock cycles
	WDT_CONFIG_WINDOW_CYC4096  = 0x9  // 4096 clock cycles
	WDT_CONFIG_WINDOW_CYC8192  = 0xa  // 8192 clock cycles
	WDT_CONFIG_WINDOW_CYC16384 = 0xb  // 16384 clock cycles

	// EWCTRL: Early Warning Interrupt Control
	WDT_EWCTRL_EWOFFSET_Pos      = 0x0 // Position of EWOFFSET field.
	WDT_EWCTRL_EWOFFSET_Msk      = 0xf // Bit mask of EWOFFSET field.
	WDT_EWCTRL_EWOFFSET_CYC8     = 0x0 // 8 clock cycles
	WDT_EWCTRL_EWOFFSET_CYC16    = 0x1 // 16 clock cycles
	WDT_EWCTRL_EWOFFSET_CYC32    = 0x2 // 32 clock cycles
	WDT_EWCTRL_EWOFFSET_CYC64    = 0x3 // 64 clock cycles
	WDT_EWCTRL_EWOFFSET_CYC128   = 0x4 // 128 clock cycles
	WDT_EWCTRL_EWOFFSET_CYC256   = 0x5 // 256 clock cycles
	WDT_EWCTRL_EWOFFSET_CYC512   = 0x6 // 512 clock cycles
	WDT_EWCTRL_EWOFFSET_CYC1024  = 0x7 // 1024 clock cycles
	WDT_EWCTRL_EWOFFSET_CYC2048  = 0x8 // 2048 clock cycles
	WDT_EWCTRL_EWOFFSET_CYC4096  = 0x9 // 4096 clock cycles
	WDT_EWCTRL_EWOFFSET_CYC8192  = 0xa // 8192 clock cycles
	WDT_EWCTRL_EWOFFSET_CYC16384 = 0xb // 16384 clock cycles

	// INTENCLR: Interrupt Enable Clear
	WDT_INTENCLR_EW_Pos = 0x0 // Position of EW field.
	WDT_INTENCLR_EW_Msk = 0x1 // Bit mask of EW field.
	WDT_INTENCLR_EW     = 0x1 // Bit EW.

	// INTENSET: Interrupt Enable Set
	WDT_INTENSET_EW_Pos = 0x0 // Position of EW field.
	WDT_INTENSET_EW_Msk = 0x1 // Bit mask of EW field.
	WDT_INTENSET_EW     = 0x1 // Bit EW.

	// INTFLAG: Interrupt Flag Status and Clear
	WDT_INTFLAG_EW_Pos = 0x0 // Position of EW field.
	WDT_INTFLAG_EW_Msk = 0x1 // Bit mask of EW field.
	WDT_INTFLAG_EW     = 0x1 // Bit EW.

	// SYNCBUSY: Synchronization Busy
	WDT_SYNCBUSY_ENABLE_Pos   = 0x1  // Position of ENABLE field.
	WDT_SYNCBUSY_ENABLE_Msk   = 0x2  // Bit mask of ENABLE field.
	WDT_SYNCBUSY_ENABLE       = 0x2  // Bit ENABLE.
	WDT_SYNCBUSY_WEN_Pos      = 0x2  // Position of WEN field.
	WDT_SYNCBUSY_WEN_Msk      = 0x4  // Bit mask of WEN field.
	WDT_SYNCBUSY_WEN          = 0x4  // Bit WEN.
	WDT_SYNCBUSY_ALWAYSON_Pos = 0x3  // Position of ALWAYSON field.
	WDT_SYNCBUSY_ALWAYSON_Msk = 0x8  // Bit mask of ALWAYSON field.
	WDT_SYNCBUSY_ALWAYSON     = 0x8  // Bit ALWAYSON.
	WDT_SYNCBUSY_CLEAR_Pos    = 0x4  // Position of CLEAR field.
	WDT_SYNCBUSY_CLEAR_Msk    = 0x10 // Bit mask of CLEAR field.
	WDT_SYNCBUSY_CLEAR        = 0x10 // Bit CLEAR.

	// CLEAR: Clear
	WDT_CLEAR_CLEAR_Pos = 0x0  // Position of CLEAR field.
	WDT_CLEAR_CLEAR_Msk = 0xff // Bit mask of CLEAR field.
	WDT_CLEAR_CLEAR_KEY = 0xa5 // Clear Key
)

// Bitfields for CoreDebug: Core Debug Register
const (
	// DHCSR: Debug Halting Control and Status Register
	CoreDebug_DHCSR_C_DEBUGEN_Pos   = 0x0        // Position of C_DEBUGEN field.
	CoreDebug_DHCSR_C_DEBUGEN_Msk   = 0x1        // Bit mask of C_DEBUGEN field.
	CoreDebug_DHCSR_C_DEBUGEN       = 0x1        // Bit C_DEBUGEN.
	CoreDebug_DHCSR_C_HALT_Pos      = 0x1        // Position of C_HALT field.
	CoreDebug_DHCSR_C_HALT_Msk      = 0x2        // Bit mask of C_HALT field.
	CoreDebug_DHCSR_C_HALT          = 0x2        // Bit C_HALT.
	CoreDebug_DHCSR_C_STEP_Pos      = 0x2        // Position of C_STEP field.
	CoreDebug_DHCSR_C_STEP_Msk      = 0x4        // Bit mask of C_STEP field.
	CoreDebug_DHCSR_C_STEP          = 0x4        // Bit C_STEP.
	CoreDebug_DHCSR_C_MASKINTS_Pos  = 0x3        // Position of C_MASKINTS field.
	CoreDebug_DHCSR_C_MASKINTS_Msk  = 0x8        // Bit mask of C_MASKINTS field.
	CoreDebug_DHCSR_C_MASKINTS      = 0x8        // Bit C_MASKINTS.
	CoreDebug_DHCSR_C_SNAPSTALL_Pos = 0x5        // Position of C_SNAPSTALL field.
	CoreDebug_DHCSR_C_SNAPSTALL_Msk = 0x20       // Bit mask of C_SNAPSTALL field.
	CoreDebug_DHCSR_C_SNAPSTALL     = 0x20       // Bit C_SNAPSTALL.
	CoreDebug_DHCSR_S_REGRDY_Pos    = 0x10       // Position of S_REGRDY field.
	CoreDebug_DHCSR_S_REGRDY_Msk    = 0x10000    // Bit mask of S_REGRDY field.
	CoreDebug_DHCSR_S_REGRDY        = 0x10000    // Bit S_REGRDY.
	CoreDebug_DHCSR_S_HALT_Pos      = 0x11       // Position of S_HALT field.
	CoreDebug_DHCSR_S_HALT_Msk      = 0x20000    // Bit mask of S_HALT field.
	CoreDebug_DHCSR_S_HALT          = 0x20000    // Bit S_HALT.
	CoreDebug_DHCSR_S_SLEEP_Pos     = 0x12       // Position of S_SLEEP field.
	CoreDebug_DHCSR_S_SLEEP_Msk     = 0x40000    // Bit mask of S_SLEEP field.
	CoreDebug_DHCSR_S_SLEEP         = 0x40000    // Bit S_SLEEP.
	CoreDebug_DHCSR_S_LOCKUP_Pos    = 0x13       // Position of S_LOCKUP field.
	CoreDebug_DHCSR_S_LOCKUP_Msk    = 0x80000    // Bit mask of S_LOCKUP field.
	CoreDebug_DHCSR_S_LOCKUP        = 0x80000    // Bit S_LOCKUP.
	CoreDebug_DHCSR_S_RETIRE_ST_Pos = 0x18       // Position of S_RETIRE_ST field.
	CoreDebug_DHCSR_S_RETIRE_ST_Msk = 0x1000000  // Bit mask of S_RETIRE_ST field.
	CoreDebug_DHCSR_S_RETIRE_ST     = 0x1000000  // Bit S_RETIRE_ST.
	CoreDebug_DHCSR_S_RESET_ST_Pos  = 0x19       // Position of S_RESET_ST field.
	CoreDebug_DHCSR_S_RESET_ST_Msk  = 0x2000000  // Bit mask of S_RESET_ST field.
	CoreDebug_DHCSR_S_RESET_ST      = 0x2000000  // Bit S_RESET_ST.
	CoreDebug_DHCSR_DBGKEY_Pos      = 0x10       // Position of DBGKEY field.
	CoreDebug_DHCSR_DBGKEY_Msk      = 0xffff0000 // Bit mask of DBGKEY field.

	// DCRSR: Debug Core Register Selector Register
	CoreDebug_DCRSR_REGSEL_Pos = 0x0     // Position of REGSEL field.
	CoreDebug_DCRSR_REGSEL_Msk = 0x1f    // Bit mask of REGSEL field.
	CoreDebug_DCRSR_REGWnR_Pos = 0x10    // Position of REGWnR field.
	CoreDebug_DCRSR_REGWnR_Msk = 0x10000 // Bit mask of REGWnR field.
	CoreDebug_DCRSR_REGWnR     = 0x10000 // Bit REGWnR.

	// DEMCR: Debug Exception and Monitor Control Register
	CoreDebug_DEMCR_VC_CORERESET_Pos = 0x0       // Position of VC_CORERESET field.
	CoreDebug_DEMCR_VC_CORERESET_Msk = 0x1       // Bit mask of VC_CORERESET field.
	CoreDebug_DEMCR_VC_CORERESET     = 0x1       // Bit VC_CORERESET.
	CoreDebug_DEMCR_VC_MMERR_Pos     = 0x4       // Position of VC_MMERR field.
	CoreDebug_DEMCR_VC_MMERR_Msk     = 0x10      // Bit mask of VC_MMERR field.
	CoreDebug_DEMCR_VC_MMERR         = 0x10      // Bit VC_MMERR.
	CoreDebug_DEMCR_VC_NOCPERR_Pos   = 0x5       // Position of VC_NOCPERR field.
	CoreDebug_DEMCR_VC_NOCPERR_Msk   = 0x20      // Bit mask of VC_NOCPERR field.
	CoreDebug_DEMCR_VC_NOCPERR       = 0x20      // Bit VC_NOCPERR.
	CoreDebug_DEMCR_VC_CHKERR_Pos    = 0x6       // Position of VC_CHKERR field.
	CoreDebug_DEMCR_VC_CHKERR_Msk    = 0x40      // Bit mask of VC_CHKERR field.
	CoreDebug_DEMCR_VC_CHKERR        = 0x40      // Bit VC_CHKERR.
	CoreDebug_DEMCR_VC_STATERR_Pos   = 0x7       // Position of VC_STATERR field.
	CoreDebug_DEMCR_VC_STATERR_Msk   = 0x80      // Bit mask of VC_STATERR field.
	CoreDebug_DEMCR_VC_STATERR       = 0x80      // Bit VC_STATERR.
	CoreDebug_DEMCR_VC_BUSERR_Pos    = 0x8       // Position of VC_BUSERR field.
	CoreDebug_DEMCR_VC_BUSERR_Msk    = 0x100     // Bit mask of VC_BUSERR field.
	CoreDebug_DEMCR_VC_BUSERR        = 0x100     // Bit VC_BUSERR.
	CoreDebug_DEMCR_VC_INTERR_Pos    = 0x9       // Position of VC_INTERR field.
	CoreDebug_DEMCR_VC_INTERR_Msk    = 0x200     // Bit mask of VC_INTERR field.
	CoreDebug_DEMCR_VC_INTERR        = 0x200     // Bit VC_INTERR.
	CoreDebug_DEMCR_VC_HARDERR_Pos   = 0xa       // Position of VC_HARDERR field.
	CoreDebug_DEMCR_VC_HARDERR_Msk   = 0x400     // Bit mask of VC_HARDERR field.
	CoreDebug_DEMCR_VC_HARDERR       = 0x400     // Bit VC_HARDERR.
	CoreDebug_DEMCR_MON_EN_Pos       = 0x10      // Position of MON_EN field.
	CoreDebug_DEMCR_MON_EN_Msk       = 0x10000   // Bit mask of MON_EN field.
	CoreDebug_DEMCR_MON_EN           = 0x10000   // Bit MON_EN.
	CoreDebug_DEMCR_MON_PEND_Pos     = 0x11      // Position of MON_PEND field.
	CoreDebug_DEMCR_MON_PEND_Msk     = 0x20000   // Bit mask of MON_PEND field.
	CoreDebug_DEMCR_MON_PEND         = 0x20000   // Bit MON_PEND.
	CoreDebug_DEMCR_MON_STEP_Pos     = 0x12      // Position of MON_STEP field.
	CoreDebug_DEMCR_MON_STEP_Msk     = 0x40000   // Bit mask of MON_STEP field.
	CoreDebug_DEMCR_MON_STEP         = 0x40000   // Bit MON_STEP.
	CoreDebug_DEMCR_MON_REQ_Pos      = 0x13      // Position of MON_REQ field.
	CoreDebug_DEMCR_MON_REQ_Msk      = 0x80000   // Bit mask of MON_REQ field.
	CoreDebug_DEMCR_MON_REQ          = 0x80000   // Bit MON_REQ.
	CoreDebug_DEMCR_TRCENA_Pos       = 0x18      // Position of TRCENA field.
	CoreDebug_DEMCR_TRCENA_Msk       = 0x1000000 // Bit mask of TRCENA field.
	CoreDebug_DEMCR_TRCENA           = 0x1000000 // Bit TRCENA.
)

// Bitfields for DWT: Data Watchpoint and Trace Register
const (
	// CTRL: Control Register
	DWT_CTRL_CYCCNTENA_Pos   = 0x0        // Position of CYCCNTENA field.
	DWT_CTRL_CYCCNTENA_Msk   = 0x1        // Bit mask of CYCCNTENA field.
	DWT_CTRL_CYCCNTENA       = 0x1        // Bit CYCCNTENA.
	DWT_CTRL_POSTPRESET_Pos  = 0x1        // Position of POSTPRESET field.
	DWT_CTRL_POSTPRESET_Msk  = 0x1e       // Bit mask of POSTPRESET field.
	DWT_CTRL_POSTINIT_Pos    = 0x5        // Position of POSTINIT field.
	DWT_CTRL_POSTINIT_Msk    = 0x1e0      // Bit mask of POSTINIT field.
	DWT_CTRL_CYCTAP_Pos      = 0x9        // Position of CYCTAP field.
	DWT_CTRL_CYCTAP_Msk      = 0x200      // Bit mask of CYCTAP field.
	DWT_CTRL_CYCTAP          = 0x200      // Bit CYCTAP.
	DWT_CTRL_SYNCTAP_Pos     = 0xa        // Position of SYNCTAP field.
	DWT_CTRL_SYNCTAP_Msk     = 0xc00      // Bit mask of SYNCTAP field.
	DWT_CTRL_PCSAMPLENA_Pos  = 0xc        // Position of PCSAMPLENA field.
	DWT_CTRL_PCSAMPLENA_Msk  = 0x1000     // Bit mask of PCSAMPLENA field.
	DWT_CTRL_PCSAMPLENA      = 0x1000     // Bit PCSAMPLENA.
	DWT_CTRL_EXCTRCENA_Pos   = 0x10       // Position of EXCTRCENA field.
	DWT_CTRL_EXCTRCENA_Msk   = 0x10000    // Bit mask of EXCTRCENA field.
	DWT_CTRL_EXCTRCENA       = 0x10000    // Bit EXCTRCENA.
	DWT_CTRL_CPIEVTENA_Pos   = 0x11       // Position of CPIEVTENA field.
	DWT_CTRL_CPIEVTENA_Msk   = 0x20000    // Bit mask of CPIEVTENA field.
	DWT_CTRL_CPIEVTENA       = 0x20000    // Bit CPIEVTENA.
	DWT_CTRL_EXCEVTENA_Pos   = 0x12       // Position of EXCEVTENA field.
	DWT_CTRL_EXCEVTENA_Msk   = 0x40000    // Bit mask of EXCEVTENA field.
	DWT_CTRL_EXCEVTENA       = 0x40000    // Bit EXCEVTENA.
	DWT_CTRL_SLEEPEVTENA_Pos = 0x13       // Position of SLEEPEVTENA field.
	DWT_CTRL_SLEEPEVTENA_Msk = 0x80000    // Bit mask of SLEEPEVTENA field.
	DWT_CTRL_SLEEPEVTENA     = 0x80000    // Bit SLEEPEVTENA.
	DWT_CTRL_LSUEVTENA_Pos   = 0x14       // Position of LSUEVTENA field.
	DWT_CTRL_LSUEVTENA_Msk   = 0x100000   // Bit mask of LSUEVTENA field.
	DWT_CTRL_LSUEVTENA       = 0x100000   // Bit LSUEVTENA.
	DWT_CTRL_FOLDEVTENA_Pos  = 0x15       // Position of FOLDEVTENA field.
	DWT_CTRL_FOLDEVTENA_Msk  = 0x200000   // Bit mask of FOLDEVTENA field.
	DWT_CTRL_FOLDEVTENA      = 0x200000   // Bit FOLDEVTENA.
	DWT_CTRL_CYCEVTENA_Pos   = 0x16       // Position of CYCEVTENA field.
	DWT_CTRL_CYCEVTENA_Msk   = 0x400000   // Bit mask of CYCEVTENA field.
	DWT_CTRL_CYCEVTENA       = 0x400000   // Bit CYCEVTENA.
	DWT_CTRL_NOPRFCNT_Pos    = 0x18       // Position of NOPRFCNT field.
	DWT_CTRL_NOPRFCNT_Msk    = 0x1000000  // Bit mask of NOPRFCNT field.
	DWT_CTRL_NOPRFCNT        = 0x1000000  // Bit NOPRFCNT.
	DWT_CTRL_NOCYCCNT_Pos    = 0x19       // Position of NOCYCCNT field.
	DWT_CTRL_NOCYCCNT_Msk    = 0x2000000  // Bit mask of NOCYCCNT field.
	DWT_CTRL_NOCYCCNT        = 0x2000000  // Bit NOCYCCNT.
	DWT_CTRL_NOEXTTRIG_Pos   = 0x1a       // Position of NOEXTTRIG field.
	DWT_CTRL_NOEXTTRIG_Msk   = 0x4000000  // Bit mask of NOEXTTRIG field.
	DWT_CTRL_NOEXTTRIG       = 0x4000000  // Bit NOEXTTRIG.
	DWT_CTRL_NOTRCPKT_Pos    = 0x1b       // Position of NOTRCPKT field.
	DWT_CTRL_NOTRCPKT_Msk    = 0x8000000  // Bit mask of NOTRCPKT field.
	DWT_CTRL_NOTRCPKT        = 0x8000000  // Bit NOTRCPKT.
	DWT_CTRL_NUMCOMP_Pos     = 0x1c       // Position of NUMCOMP field.
	DWT_CTRL_NUMCOMP_Msk     = 0xf0000000 // Bit mask of NUMCOMP field.

	// CPICNT: CPI Count Register
	DWT_CPICNT_CPICNT_Pos = 0x0  // Position of CPICNT field.
	DWT_CPICNT_CPICNT_Msk = 0xff // Bit mask of CPICNT field.

	// EXCCNT: Exception Overhead Count Register
	DWT_EXCCNT_EXCCNT_Pos = 0x0  // Position of EXCCNT field.
	DWT_EXCCNT_EXCCNT_Msk = 0xff // Bit mask of EXCCNT field.

	// SLEEPCNT: Sleep Count Register
	DWT_SLEEPCNT_SLEEPCNT_Pos = 0x0  // Position of SLEEPCNT field.
	DWT_SLEEPCNT_SLEEPCNT_Msk = 0xff // Bit mask of SLEEPCNT field.

	// LSUCNT: LSU Count Register
	DWT_LSUCNT_LSUCNT_Pos = 0x0  // Position of LSUCNT field.
	DWT_LSUCNT_LSUCNT_Msk = 0xff // Bit mask of LSUCNT field.

	// FOLDCNT: Folded-instruction Count Register
	DWT_FOLDCNT_FOLDCNT_Pos = 0x0  // Position of FOLDCNT field.
	DWT_FOLDCNT_FOLDCNT_Msk = 0xff // Bit mask of FOLDCNT field.

	// MASK0: Mask Register 0
	DWT_MASK0_MASK_Pos = 0x0  // Position of MASK field.
	DWT_MASK0_MASK_Msk = 0x1f // Bit mask of MASK field.

	// FUNCTION0: Function Register 0
	DWT_FUNCTION0_FUNCTION_Pos   = 0x0       // Position of FUNCTION field.
	DWT_FUNCTION0_FUNCTION_Msk   = 0xf       // Bit mask of FUNCTION field.
	DWT_FUNCTION0_EMITRANGE_Pos  = 0x5       // Position of EMITRANGE field.
	DWT_FUNCTION0_EMITRANGE_Msk  = 0x20      // Bit mask of EMITRANGE field.
	DWT_FUNCTION0_EMITRANGE      = 0x20      // Bit EMITRANGE.
	DWT_FUNCTION0_CYCMATCH_Pos   = 0x7       // Position of CYCMATCH field.
	DWT_FUNCTION0_CYCMATCH_Msk   = 0x80      // Bit mask of CYCMATCH field.
	DWT_FUNCTION0_CYCMATCH       = 0x80      // Bit CYCMATCH.
	DWT_FUNCTION0_DATAVMATCH_Pos = 0x8       // Position of DATAVMATCH field.
	DWT_FUNCTION0_DATAVMATCH_Msk = 0x100     // Bit mask of DATAVMATCH field.
	DWT_FUNCTION0_DATAVMATCH     = 0x100     // Bit DATAVMATCH.
	DWT_FUNCTION0_LNK1ENA_Pos    = 0x9       // Position of LNK1ENA field.
	DWT_FUNCTION0_LNK1ENA_Msk    = 0x200     // Bit mask of LNK1ENA field.
	DWT_FUNCTION0_LNK1ENA        = 0x200     // Bit LNK1ENA.
	DWT_FUNCTION0_DATAVSIZE_Pos  = 0xa       // Position of DATAVSIZE field.
	DWT_FUNCTION0_DATAVSIZE_Msk  = 0xc00     // Bit mask of DATAVSIZE field.
	DWT_FUNCTION0_DATAVADDR0_Pos = 0xc       // Position of DATAVADDR0 field.
	DWT_FUNCTION0_DATAVADDR0_Msk = 0xf000    // Bit mask of DATAVADDR0 field.
	DWT_FUNCTION0_DATAVADDR1_Pos = 0x10      // Position of DATAVADDR1 field.
	DWT_FUNCTION0_DATAVADDR1_Msk = 0xf0000   // Bit mask of DATAVADDR1 field.
	DWT_FUNCTION0_MATCHED_Pos    = 0x18      // Position of MATCHED field.
	DWT_FUNCTION0_MATCHED_Msk    = 0x1000000 // Bit mask of MATCHED field.
	DWT_FUNCTION0_MATCHED        = 0x1000000 // Bit MATCHED.

	// MASK1: Mask Register 1
	DWT_MASK1_MASK_Pos = 0x0  // Position of MASK field.
	DWT_MASK1_MASK_Msk = 0x1f // Bit mask of MASK field.

	// FUNCTION1: Function Register 1
	DWT_FUNCTION1_FUNCTION_Pos   = 0x0       // Position of FUNCTION field.
	DWT_FUNCTION1_FUNCTION_Msk   = 0xf       // Bit mask of FUNCTION field.
	DWT_FUNCTION1_EMITRANGE_Pos  = 0x5       // Position of EMITRANGE field.
	DWT_FUNCTION1_EMITRANGE_Msk  = 0x20      // Bit mask of EMITRANGE field.
	DWT_FUNCTION1_EMITRANGE      = 0x20      // Bit EMITRANGE.
	DWT_FUNCTION1_CYCMATCH_Pos   = 0x7       // Position of CYCMATCH field.
	DWT_FUNCTION1_CYCMATCH_Msk   = 0x80      // Bit mask of CYCMATCH field.
	DWT_FUNCTION1_CYCMATCH       = 0x80      // Bit CYCMATCH.
	DWT_FUNCTION1_DATAVMATCH_Pos = 0x8       // Position of DATAVMATCH field.
	DWT_FUNCTION1_DATAVMATCH_Msk = 0x100     // Bit mask of DATAVMATCH field.
	DWT_FUNCTION1_DATAVMATCH     = 0x100     // Bit DATAVMATCH.
	DWT_FUNCTION1_LNK1ENA_Pos    = 0x9       // Position of LNK1ENA field.
	DWT_FUNCTION1_LNK1ENA_Msk    = 0x200     // Bit mask of LNK1ENA field.
	DWT_FUNCTION1_LNK1ENA        = 0x200     // Bit LNK1ENA.
	DWT_FUNCTION1_DATAVSIZE_Pos  = 0xa       // Position of DATAVSIZE field.
	DWT_FUNCTION1_DATAVSIZE_Msk  = 0xc00     // Bit mask of DATAVSIZE field.
	DWT_FUNCTION1_DATAVADDR0_Pos = 0xc       // Position of DATAVADDR0 field.
	DWT_FUNCTION1_DATAVADDR0_Msk = 0xf000    // Bit mask of DATAVADDR0 field.
	DWT_FUNCTION1_DATAVADDR1_Pos = 0x10      // Position of DATAVADDR1 field.
	DWT_FUNCTION1_DATAVADDR1_Msk = 0xf0000   // Bit mask of DATAVADDR1 field.
	DWT_FUNCTION1_MATCHED_Pos    = 0x18      // Position of MATCHED field.
	DWT_FUNCTION1_MATCHED_Msk    = 0x1000000 // Bit mask of MATCHED field.
	DWT_FUNCTION1_MATCHED        = 0x1000000 // Bit MATCHED.

	// MASK2: Mask Register 2
	DWT_MASK2_MASK_Pos = 0x0  // Position of MASK field.
	DWT_MASK2_MASK_Msk = 0x1f // Bit mask of MASK field.

	// FUNCTION2: Function Register 2
	DWT_FUNCTION2_FUNCTION_Pos   = 0x0       // Position of FUNCTION field.
	DWT_FUNCTION2_FUNCTION_Msk   = 0xf       // Bit mask of FUNCTION field.
	DWT_FUNCTION2_EMITRANGE_Pos  = 0x5       // Position of EMITRANGE field.
	DWT_FUNCTION2_EMITRANGE_Msk  = 0x20      // Bit mask of EMITRANGE field.
	DWT_FUNCTION2_EMITRANGE      = 0x20      // Bit EMITRANGE.
	DWT_FUNCTION2_CYCMATCH_Pos   = 0x7       // Position of CYCMATCH field.
	DWT_FUNCTION2_CYCMATCH_Msk   = 0x80      // Bit mask of CYCMATCH field.
	DWT_FUNCTION2_CYCMATCH       = 0x80      // Bit CYCMATCH.
	DWT_FUNCTION2_DATAVMATCH_Pos = 0x8       // Position of DATAVMATCH field.
	DWT_FUNCTION2_DATAVMATCH_Msk = 0x100     // Bit mask of DATAVMATCH field.
	DWT_FUNCTION2_DATAVMATCH     = 0x100     // Bit DATAVMATCH.
	DWT_FUNCTION2_LNK1ENA_Pos    = 0x9       // Position of LNK1ENA field.
	DWT_FUNCTION2_LNK1ENA_Msk    = 0x200     // Bit mask of LNK1ENA field.
	DWT_FUNCTION2_LNK1ENA        = 0x200     // Bit LNK1ENA.
	DWT_FUNCTION2_DATAVSIZE_Pos  = 0xa       // Position of DATAVSIZE field.
	DWT_FUNCTION2_DATAVSIZE_Msk  = 0xc00     // Bit mask of DATAVSIZE field.
	DWT_FUNCTION2_DATAVADDR0_Pos = 0xc       // Position of DATAVADDR0 field.
	DWT_FUNCTION2_DATAVADDR0_Msk = 0xf000    // Bit mask of DATAVADDR0 field.
	DWT_FUNCTION2_DATAVADDR1_Pos = 0x10      // Position of DATAVADDR1 field.
	DWT_FUNCTION2_DATAVADDR1_Msk = 0xf0000   // Bit mask of DATAVADDR1 field.
	DWT_FUNCTION2_MATCHED_Pos    = 0x18      // Position of MATCHED field.
	DWT_FUNCTION2_MATCHED_Msk    = 0x1000000 // Bit mask of MATCHED field.
	DWT_FUNCTION2_MATCHED        = 0x1000000 // Bit MATCHED.

	// MASK3: Mask Register 3
	DWT_MASK3_MASK_Pos = 0x0  // Position of MASK field.
	DWT_MASK3_MASK_Msk = 0x1f // Bit mask of MASK field.

	// FUNCTION3: Function Register 3
	DWT_FUNCTION3_FUNCTION_Pos   = 0x0       // Position of FUNCTION field.
	DWT_FUNCTION3_FUNCTION_Msk   = 0xf       // Bit mask of FUNCTION field.
	DWT_FUNCTION3_EMITRANGE_Pos  = 0x5       // Position of EMITRANGE field.
	DWT_FUNCTION3_EMITRANGE_Msk  = 0x20      // Bit mask of EMITRANGE field.
	DWT_FUNCTION3_EMITRANGE      = 0x20      // Bit EMITRANGE.
	DWT_FUNCTION3_CYCMATCH_Pos   = 0x7       // Position of CYCMATCH field.
	DWT_FUNCTION3_CYCMATCH_Msk   = 0x80      // Bit mask of CYCMATCH field.
	DWT_FUNCTION3_CYCMATCH       = 0x80      // Bit CYCMATCH.
	DWT_FUNCTION3_DATAVMATCH_Pos = 0x8       // Position of DATAVMATCH field.
	DWT_FUNCTION3_DATAVMATCH_Msk = 0x100     // Bit mask of DATAVMATCH field.
	DWT_FUNCTION3_DATAVMATCH     = 0x100     // Bit DATAVMATCH.
	DWT_FUNCTION3_LNK1ENA_Pos    = 0x9       // Position of LNK1ENA field.
	DWT_FUNCTION3_LNK1ENA_Msk    = 0x200     // Bit mask of LNK1ENA field.
	DWT_FUNCTION3_LNK1ENA        = 0x200     // Bit LNK1ENA.
	DWT_FUNCTION3_DATAVSIZE_Pos  = 0xa       // Position of DATAVSIZE field.
	DWT_FUNCTION3_DATAVSIZE_Msk  = 0xc00     // Bit mask of DATAVSIZE field.
	DWT_FUNCTION3_DATAVADDR0_Pos = 0xc       // Position of DATAVADDR0 field.
	DWT_FUNCTION3_DATAVADDR0_Msk = 0xf000    // Bit mask of DATAVADDR0 field.
	DWT_FUNCTION3_DATAVADDR1_Pos = 0x10      // Position of DATAVADDR1 field.
	DWT_FUNCTION3_DATAVADDR1_Msk = 0xf0000   // Bit mask of DATAVADDR1 field.
	DWT_FUNCTION3_MATCHED_Pos    = 0x18      // Position of MATCHED field.
	DWT_FUNCTION3_MATCHED_Msk    = 0x1000000 // Bit mask of MATCHED field.
	DWT_FUNCTION3_MATCHED        = 0x1000000 // Bit MATCHED.
)

// Bitfields for ETM: Embedded Trace Macrocell
const (
	// CR: ETM Main Control Register
	ETM_CR_ETMPD_Pos     = 0x0        // Position of ETMPD field.
	ETM_CR_ETMPD_Msk     = 0x1        // Bit mask of ETMPD field.
	ETM_CR_ETMPD         = 0x1        // Bit ETMPD.
	ETM_CR_PORTSIZE_Pos  = 0x4        // Position of PORTSIZE field.
	ETM_CR_PORTSIZE_Msk  = 0x70       // Bit mask of PORTSIZE field.
	ETM_CR_STALL_Pos     = 0x7        // Position of STALL field.
	ETM_CR_STALL_Msk     = 0x80       // Bit mask of STALL field.
	ETM_CR_STALL         = 0x80       // Bit STALL.
	ETM_CR_BROUT_Pos     = 0x8        // Position of BROUT field.
	ETM_CR_BROUT_Msk     = 0x100      // Bit mask of BROUT field.
	ETM_CR_BROUT         = 0x100      // Bit BROUT.
	ETM_CR_DBGRQ_Pos     = 0x9        // Position of DBGRQ field.
	ETM_CR_DBGRQ_Msk     = 0x200      // Bit mask of DBGRQ field.
	ETM_CR_DBGRQ         = 0x200      // Bit DBGRQ.
	ETM_CR_PROG_Pos      = 0xa        // Position of PROG field.
	ETM_CR_PROG_Msk      = 0x400      // Bit mask of PROG field.
	ETM_CR_PROG          = 0x400      // Bit PROG.
	ETM_CR_PORTSEL_Pos   = 0xb        // Position of PORTSEL field.
	ETM_CR_PORTSEL_Msk   = 0x800      // Bit mask of PORTSEL field.
	ETM_CR_PORTSEL       = 0x800      // Bit PORTSEL.
	ETM_CR_PORTMODE2_Pos = 0xd        // Position of PORTMODE2 field.
	ETM_CR_PORTMODE2_Msk = 0x2000     // Bit mask of PORTMODE2 field.
	ETM_CR_PORTMODE2     = 0x2000     // Bit PORTMODE2.
	ETM_CR_PORTMODE_Pos  = 0x10       // Position of PORTMODE field.
	ETM_CR_PORTMODE_Msk  = 0x30000    // Bit mask of PORTMODE field.
	ETM_CR_PORTSIZE3_Pos = 0x15       // Position of PORTSIZE3 field.
	ETM_CR_PORTSIZE3_Msk = 0x200000   // Bit mask of PORTSIZE3 field.
	ETM_CR_PORTSIZE3     = 0x200000   // Bit PORTSIZE3.
	ETM_CR_TSEN_Pos      = 0x1c       // Position of TSEN field.
	ETM_CR_TSEN_Msk      = 0x10000000 // Bit mask of TSEN field.
	ETM_CR_TSEN          = 0x10000000 // Bit TSEN.

	// ITCTRL: ETM Integration Mode Control Register
	ETM_ITCTRL_INTEGRATION_Pos = 0x0 // Position of INTEGRATION field.
	ETM_ITCTRL_INTEGRATION_Msk = 0x1 // Bit mask of INTEGRATION field.
	ETM_ITCTRL_INTEGRATION     = 0x1 // Bit INTEGRATION.

	// LSR: ETM Lock Status Register
	ETM_LSR_Present_Pos = 0x0 // Position of Present field.
	ETM_LSR_Present_Msk = 0x1 // Bit mask of Present field.
	ETM_LSR_Present     = 0x1 // Bit Present.
	ETM_LSR_Access_Pos  = 0x1 // Position of Access field.
	ETM_LSR_Access_Msk  = 0x2 // Bit mask of Access field.
	ETM_LSR_Access      = 0x2 // Bit Access.
	ETM_LSR_ByteAcc_Pos = 0x2 // Position of ByteAcc field.
	ETM_LSR_ByteAcc_Msk = 0x4 // Bit mask of ByteAcc field.
	ETM_LSR_ByteAcc     = 0x4 // Bit ByteAcc.
)

// Bitfields for FPU: Floating Point Unit
const (
	// FPCCR: Floating-Point Context Control Register
	FPU_FPCCR_LSPACT_Pos = 0x0        // Position of LSPACT field.
	FPU_FPCCR_LSPACT_Msk = 0x1        // Bit mask of LSPACT field.
	FPU_FPCCR_LSPACT     = 0x1        // Bit LSPACT.
	FPU_FPCCR_USER_Pos   = 0x1        // Position of USER field.
	FPU_FPCCR_USER_Msk   = 0x2        // Bit mask of USER field.
	FPU_FPCCR_USER       = 0x2        // Bit USER.
	FPU_FPCCR_THREAD_Pos = 0x3        // Position of THREAD field.
	FPU_FPCCR_THREAD_Msk = 0x8        // Bit mask of THREAD field.
	FPU_FPCCR_THREAD     = 0x8        // Bit THREAD.
	FPU_FPCCR_HFRDY_Pos  = 0x4        // Position of HFRDY field.
	FPU_FPCCR_HFRDY_Msk  = 0x10       // Bit mask of HFRDY field.
	FPU_FPCCR_HFRDY      = 0x10       // Bit HFRDY.
	FPU_FPCCR_MMRDY_Pos  = 0x5        // Position of MMRDY field.
	FPU_FPCCR_MMRDY_Msk  = 0x20       // Bit mask of MMRDY field.
	FPU_FPCCR_MMRDY      = 0x20       // Bit MMRDY.
	FPU_FPCCR_BFRDY_Pos  = 0x6        // Position of BFRDY field.
	FPU_FPCCR_BFRDY_Msk  = 0x40       // Bit mask of BFRDY field.
	FPU_FPCCR_BFRDY      = 0x40       // Bit BFRDY.
	FPU_FPCCR_MONRDY_Pos = 0x8        // Position of MONRDY field.
	FPU_FPCCR_MONRDY_Msk = 0x100      // Bit mask of MONRDY field.
	FPU_FPCCR_MONRDY     = 0x100      // Bit MONRDY.
	FPU_FPCCR_LSPEN_Pos  = 0x1e       // Position of LSPEN field.
	FPU_FPCCR_LSPEN_Msk  = 0x40000000 // Bit mask of LSPEN field.
	FPU_FPCCR_LSPEN      = 0x40000000 // Bit LSPEN.
	FPU_FPCCR_ASPEN_Pos  = 0x1f       // Position of ASPEN field.
	FPU_FPCCR_ASPEN_Msk  = 0x80000000 // Bit mask of ASPEN field.
	FPU_FPCCR_ASPEN      = 0x80000000 // Bit ASPEN.

	// FPCAR: Floating-Point Context Address Register
	FPU_FPCAR_ADDRESS_Pos = 0x3        // Position of ADDRESS field.
	FPU_FPCAR_ADDRESS_Msk = 0xfffffff8 // Bit mask of ADDRESS field.

	// FPDSCR: Floating-Point Default Status Control Register
	FPU_FPDSCR_RMODE_Pos = 0x16      // Position of RMODE field.
	FPU_FPDSCR_RMODE_Msk = 0xc00000  // Bit mask of RMODE field.
	FPU_FPDSCR_RMODE_RN  = 0x0       // Round to Nearest
	FPU_FPDSCR_RMODE_RP  = 0x1       // Round towards Positive Infinity
	FPU_FPDSCR_RMODE_RM  = 0x2       // Round towards Negative Infinity
	FPU_FPDSCR_RMODE_RZ  = 0x3       // Round towards Zero
	FPU_FPDSCR_FZ_Pos    = 0x18      // Position of FZ field.
	FPU_FPDSCR_FZ_Msk    = 0x1000000 // Bit mask of FZ field.
	FPU_FPDSCR_FZ        = 0x1000000 // Bit FZ.
	FPU_FPDSCR_DN_Pos    = 0x19      // Position of DN field.
	FPU_FPDSCR_DN_Msk    = 0x2000000 // Bit mask of DN field.
	FPU_FPDSCR_DN        = 0x2000000 // Bit DN.
	FPU_FPDSCR_AHP_Pos   = 0x1a      // Position of AHP field.
	FPU_FPDSCR_AHP_Msk   = 0x4000000 // Bit mask of AHP field.
	FPU_FPDSCR_AHP       = 0x4000000 // Bit AHP.

	// MVFR0: Media and FP Feature Register 0
	FPU_MVFR0_A_SIMD_registers_Pos  = 0x0        // Position of A_SIMD_registers field.
	FPU_MVFR0_A_SIMD_registers_Msk  = 0xf        // Bit mask of A_SIMD_registers field.
	FPU_MVFR0_Single_precision_Pos  = 0x4        // Position of Single_precision field.
	FPU_MVFR0_Single_precision_Msk  = 0xf0       // Bit mask of Single_precision field.
	FPU_MVFR0_Double_precision_Pos  = 0x8        // Position of Double_precision field.
	FPU_MVFR0_Double_precision_Msk  = 0xf00      // Bit mask of Double_precision field.
	FPU_MVFR0_FP_excep_trapping_Pos = 0xc        // Position of FP_excep_trapping field.
	FPU_MVFR0_FP_excep_trapping_Msk = 0xf000     // Bit mask of FP_excep_trapping field.
	FPU_MVFR0_Divide_Pos            = 0x10       // Position of Divide field.
	FPU_MVFR0_Divide_Msk            = 0xf0000    // Bit mask of Divide field.
	FPU_MVFR0_Square_root_Pos       = 0x14       // Position of Square_root field.
	FPU_MVFR0_Square_root_Msk       = 0xf00000   // Bit mask of Square_root field.
	FPU_MVFR0_Short_vectors_Pos     = 0x18       // Position of Short_vectors field.
	FPU_MVFR0_Short_vectors_Msk     = 0xf000000  // Bit mask of Short_vectors field.
	FPU_MVFR0_FP_rounding_modes_Pos = 0x1c       // Position of FP_rounding_modes field.
	FPU_MVFR0_FP_rounding_modes_Msk = 0xf0000000 // Bit mask of FP_rounding_modes field.

	// MVFR1: Media and FP Feature Register 1
	FPU_MVFR1_FtZ_mode_Pos     = 0x0        // Position of FtZ_mode field.
	FPU_MVFR1_FtZ_mode_Msk     = 0xf        // Bit mask of FtZ_mode field.
	FPU_MVFR1_D_NaN_mode_Pos   = 0x4        // Position of D_NaN_mode field.
	FPU_MVFR1_D_NaN_mode_Msk   = 0xf0       // Bit mask of D_NaN_mode field.
	FPU_MVFR1_FP_HPFP_Pos      = 0x18       // Position of FP_HPFP field.
	FPU_MVFR1_FP_HPFP_Msk      = 0xf000000  // Bit mask of FP_HPFP field.
	FPU_MVFR1_FP_fused_MAC_Pos = 0x1c       // Position of FP_fused_MAC field.
	FPU_MVFR1_FP_fused_MAC_Msk = 0xf0000000 // Bit mask of FP_fused_MAC field.
)

// Bitfields for ITM: Instrumentation Trace Macrocell
const (
	// PORT_WORD_MODE: ITM Stimulus Port Registers
	ITM_PORT_WORD_MODE_PORT_Pos = 0x0        // Position of PORT field.
	ITM_PORT_WORD_MODE_PORT_Msk = 0xffffffff // Bit mask of PORT field.

	// PORT_BYTE_MODE: ITM Stimulus Port Registers
	ITM_PORT_BYTE_MODE_PORT_Pos = 0x0  // Position of PORT field.
	ITM_PORT_BYTE_MODE_PORT_Msk = 0xff // Bit mask of PORT field.

	// PORT_HWORD_MODE: ITM Stimulus Port Registers
	ITM_PORT_HWORD_MODE_PORT_Pos = 0x0    // Position of PORT field.
	ITM_PORT_HWORD_MODE_PORT_Msk = 0xffff // Bit mask of PORT field.

	// TPR: ITM Trace Privilege Register
	ITM_TPR_PRIVMASK_Pos = 0x0 // Position of PRIVMASK field.
	ITM_TPR_PRIVMASK_Msk = 0xf // Bit mask of PRIVMASK field.

	// TCR: ITM Trace Control Register
	ITM_TCR_ITMENA_Pos     = 0x0      // Position of ITMENA field.
	ITM_TCR_ITMENA_Msk     = 0x1      // Bit mask of ITMENA field.
	ITM_TCR_ITMENA         = 0x1      // Bit ITMENA.
	ITM_TCR_TSENA_Pos      = 0x1      // Position of TSENA field.
	ITM_TCR_TSENA_Msk      = 0x2      // Bit mask of TSENA field.
	ITM_TCR_TSENA          = 0x2      // Bit TSENA.
	ITM_TCR_SYNCENA_Pos    = 0x2      // Position of SYNCENA field.
	ITM_TCR_SYNCENA_Msk    = 0x4      // Bit mask of SYNCENA field.
	ITM_TCR_SYNCENA        = 0x4      // Bit SYNCENA.
	ITM_TCR_DWTENA_Pos     = 0x3      // Position of DWTENA field.
	ITM_TCR_DWTENA_Msk     = 0x8      // Bit mask of DWTENA field.
	ITM_TCR_DWTENA         = 0x8      // Bit DWTENA.
	ITM_TCR_SWOENA_Pos     = 0x4      // Position of SWOENA field.
	ITM_TCR_SWOENA_Msk     = 0x10     // Bit mask of SWOENA field.
	ITM_TCR_SWOENA         = 0x10     // Bit SWOENA.
	ITM_TCR_STALLENA_Pos   = 0x5      // Position of STALLENA field.
	ITM_TCR_STALLENA_Msk   = 0x20     // Bit mask of STALLENA field.
	ITM_TCR_STALLENA       = 0x20     // Bit STALLENA.
	ITM_TCR_TSPrescale_Pos = 0x8      // Position of TSPrescale field.
	ITM_TCR_TSPrescale_Msk = 0x300    // Bit mask of TSPrescale field.
	ITM_TCR_GTSFREQ_Pos    = 0xa      // Position of GTSFREQ field.
	ITM_TCR_GTSFREQ_Msk    = 0xc00    // Bit mask of GTSFREQ field.
	ITM_TCR_TraceBusID_Pos = 0x10     // Position of TraceBusID field.
	ITM_TCR_TraceBusID_Msk = 0x7f0000 // Bit mask of TraceBusID field.
	ITM_TCR_BUSY_Pos       = 0x17     // Position of BUSY field.
	ITM_TCR_BUSY_Msk       = 0x800000 // Bit mask of BUSY field.
	ITM_TCR_BUSY           = 0x800000 // Bit BUSY.

	// IWR: ITM Integration Write Register
	ITM_IWR_ATVALIDM_Pos = 0x0 // Position of ATVALIDM field.
	ITM_IWR_ATVALIDM_Msk = 0x1 // Bit mask of ATVALIDM field.
	ITM_IWR_ATVALIDM     = 0x1 // Bit ATVALIDM.

	// IRR: ITM Integration Read Register
	ITM_IRR_ATREADYM_Pos = 0x0 // Position of ATREADYM field.
	ITM_IRR_ATREADYM_Msk = 0x1 // Bit mask of ATREADYM field.
	ITM_IRR_ATREADYM     = 0x1 // Bit ATREADYM.
)

// Bitfields for MPU: Memory Protection Unit
const (
	// TYPE: MPU Type Register
	MPU_TYPE_SEPARATE_Pos = 0x0      // Position of SEPARATE field.
	MPU_TYPE_SEPARATE_Msk = 0x1      // Bit mask of SEPARATE field.
	MPU_TYPE_SEPARATE     = 0x1      // Bit SEPARATE.
	MPU_TYPE_DREGION_Pos  = 0x8      // Position of DREGION field.
	MPU_TYPE_DREGION_Msk  = 0xff00   // Bit mask of DREGION field.
	MPU_TYPE_IREGION_Pos  = 0x10     // Position of IREGION field.
	MPU_TYPE_IREGION_Msk  = 0xff0000 // Bit mask of IREGION field.

	// CTRL: MPU Control Register
	MPU_CTRL_ENABLE_Pos     = 0x0 // Position of ENABLE field.
	MPU_CTRL_ENABLE_Msk     = 0x1 // Bit mask of ENABLE field.
	MPU_CTRL_ENABLE         = 0x1 // Bit ENABLE.
	MPU_CTRL_HFNMIENA_Pos   = 0x1 // Position of HFNMIENA field.
	MPU_CTRL_HFNMIENA_Msk   = 0x2 // Bit mask of HFNMIENA field.
	MPU_CTRL_HFNMIENA       = 0x2 // Bit HFNMIENA.
	MPU_CTRL_PRIVDEFENA_Pos = 0x2 // Position of PRIVDEFENA field.
	MPU_CTRL_PRIVDEFENA_Msk = 0x4 // Bit mask of PRIVDEFENA field.
	MPU_CTRL_PRIVDEFENA     = 0x4 // Bit PRIVDEFENA.

	// RNR: MPU Region Number Register
	MPU_RNR_REGION_Pos = 0x0  // Position of REGION field.
	MPU_RNR_REGION_Msk = 0xff // Bit mask of REGION field.

	// RBAR: MPU Region Base Address Register
	MPU_RBAR_REGION_Pos = 0x0        // Position of REGION field.
	MPU_RBAR_REGION_Msk = 0xf        // Bit mask of REGION field.
	MPU_RBAR_VALID_Pos  = 0x4        // Position of VALID field.
	MPU_RBAR_VALID_Msk  = 0x10       // Bit mask of VALID field.
	MPU_RBAR_VALID      = 0x10       // Bit VALID.
	MPU_RBAR_ADDR_Pos   = 0x5        // Position of ADDR field.
	MPU_RBAR_ADDR_Msk   = 0xffffffe0 // Bit mask of ADDR field.

	// RASR: MPU Region Attribute and Size Register
	MPU_RASR_ENABLE_Pos = 0x0        // Position of ENABLE field.
	MPU_RASR_ENABLE_Msk = 0x1        // Bit mask of ENABLE field.
	MPU_RASR_ENABLE     = 0x1        // Bit ENABLE.
	MPU_RASR_SIZE_Pos   = 0x1        // Position of SIZE field.
	MPU_RASR_SIZE_Msk   = 0x2        // Bit mask of SIZE field.
	MPU_RASR_SIZE       = 0x2        // Bit SIZE.
	MPU_RASR_SRD_Pos    = 0x8        // Position of SRD field.
	MPU_RASR_SRD_Msk    = 0xff00     // Bit mask of SRD field.
	MPU_RASR_B_Pos      = 0x10       // Position of B field.
	MPU_RASR_B_Msk      = 0x10000    // Bit mask of B field.
	MPU_RASR_B          = 0x10000    // Bit B.
	MPU_RASR_C_Pos      = 0x11       // Position of C field.
	MPU_RASR_C_Msk      = 0x20000    // Bit mask of C field.
	MPU_RASR_C          = 0x20000    // Bit C.
	MPU_RASR_S_Pos      = 0x12       // Position of S field.
	MPU_RASR_S_Msk      = 0x40000    // Bit mask of S field.
	MPU_RASR_S          = 0x40000    // Bit S.
	MPU_RASR_TEX_Pos    = 0x13       // Position of TEX field.
	MPU_RASR_TEX_Msk    = 0x380000   // Bit mask of TEX field.
	MPU_RASR_AP_Pos     = 0x18       // Position of AP field.
	MPU_RASR_AP_Msk     = 0x7000000  // Bit mask of AP field.
	MPU_RASR_XN_Pos     = 0x1c       // Position of XN field.
	MPU_RASR_XN_Msk     = 0x10000000 // Bit mask of XN field.
	MPU_RASR_XN         = 0x10000000 // Bit XN.

	// RBAR_A1: MPU Alias 1 Region Base Address Register
	MPU_RBAR_A1_REGION_Pos = 0x0        // Position of REGION field.
	MPU_RBAR_A1_REGION_Msk = 0xf        // Bit mask of REGION field.
	MPU_RBAR_A1_VALID_Pos  = 0x4        // Position of VALID field.
	MPU_RBAR_A1_VALID_Msk  = 0x10       // Bit mask of VALID field.
	MPU_RBAR_A1_VALID      = 0x10       // Bit VALID.
	MPU_RBAR_A1_ADDR_Pos   = 0x5        // Position of ADDR field.
	MPU_RBAR_A1_ADDR_Msk   = 0xffffffe0 // Bit mask of ADDR field.

	// RASR_A1: MPU Alias 1 Region Attribute and Size Register
	MPU_RASR_A1_ENABLE_Pos = 0x0        // Position of ENABLE field.
	MPU_RASR_A1_ENABLE_Msk = 0x1        // Bit mask of ENABLE field.
	MPU_RASR_A1_ENABLE     = 0x1        // Bit ENABLE.
	MPU_RASR_A1_SIZE_Pos   = 0x1        // Position of SIZE field.
	MPU_RASR_A1_SIZE_Msk   = 0x2        // Bit mask of SIZE field.
	MPU_RASR_A1_SIZE       = 0x2        // Bit SIZE.
	MPU_RASR_A1_SRD_Pos    = 0x8        // Position of SRD field.
	MPU_RASR_A1_SRD_Msk    = 0xff00     // Bit mask of SRD field.
	MPU_RASR_A1_B_Pos      = 0x10       // Position of B field.
	MPU_RASR_A1_B_Msk      = 0x10000    // Bit mask of B field.
	MPU_RASR_A1_B          = 0x10000    // Bit B.
	MPU_RASR_A1_C_Pos      = 0x11       // Position of C field.
	MPU_RASR_A1_C_Msk      = 0x20000    // Bit mask of C field.
	MPU_RASR_A1_C          = 0x20000    // Bit C.
	MPU_RASR_A1_S_Pos      = 0x12       // Position of S field.
	MPU_RASR_A1_S_Msk      = 0x40000    // Bit mask of S field.
	MPU_RASR_A1_S          = 0x40000    // Bit S.
	MPU_RASR_A1_TEX_Pos    = 0x13       // Position of TEX field.
	MPU_RASR_A1_TEX_Msk    = 0x380000   // Bit mask of TEX field.
	MPU_RASR_A1_AP_Pos     = 0x18       // Position of AP field.
	MPU_RASR_A1_AP_Msk     = 0x7000000  // Bit mask of AP field.
	MPU_RASR_A1_XN_Pos     = 0x1c       // Position of XN field.
	MPU_RASR_A1_XN_Msk     = 0x10000000 // Bit mask of XN field.
	MPU_RASR_A1_XN         = 0x10000000 // Bit XN.

	// RBAR_A2: MPU Alias 2 Region Base Address Register
	MPU_RBAR_A2_REGION_Pos = 0x0        // Position of REGION field.
	MPU_RBAR_A2_REGION_Msk = 0xf        // Bit mask of REGION field.
	MPU_RBAR_A2_VALID_Pos  = 0x4        // Position of VALID field.
	MPU_RBAR_A2_VALID_Msk  = 0x10       // Bit mask of VALID field.
	MPU_RBAR_A2_VALID      = 0x10       // Bit VALID.
	MPU_RBAR_A2_ADDR_Pos   = 0x5        // Position of ADDR field.
	MPU_RBAR_A2_ADDR_Msk   = 0xffffffe0 // Bit mask of ADDR field.

	// RASR_A2: MPU Alias 2 Region Attribute and Size Register
	MPU_RASR_A2_ENABLE_Pos = 0x0        // Position of ENABLE field.
	MPU_RASR_A2_ENABLE_Msk = 0x1        // Bit mask of ENABLE field.
	MPU_RASR_A2_ENABLE     = 0x1        // Bit ENABLE.
	MPU_RASR_A2_SIZE_Pos   = 0x1        // Position of SIZE field.
	MPU_RASR_A2_SIZE_Msk   = 0x2        // Bit mask of SIZE field.
	MPU_RASR_A2_SIZE       = 0x2        // Bit SIZE.
	MPU_RASR_A2_SRD_Pos    = 0x8        // Position of SRD field.
	MPU_RASR_A2_SRD_Msk    = 0xff00     // Bit mask of SRD field.
	MPU_RASR_A2_B_Pos      = 0x10       // Position of B field.
	MPU_RASR_A2_B_Msk      = 0x10000    // Bit mask of B field.
	MPU_RASR_A2_B          = 0x10000    // Bit B.
	MPU_RASR_A2_C_Pos      = 0x11       // Position of C field.
	MPU_RASR_A2_C_Msk      = 0x20000    // Bit mask of C field.
	MPU_RASR_A2_C          = 0x20000    // Bit C.
	MPU_RASR_A2_S_Pos      = 0x12       // Position of S field.
	MPU_RASR_A2_S_Msk      = 0x40000    // Bit mask of S field.
	MPU_RASR_A2_S          = 0x40000    // Bit S.
	MPU_RASR_A2_TEX_Pos    = 0x13       // Position of TEX field.
	MPU_RASR_A2_TEX_Msk    = 0x380000   // Bit mask of TEX field.
	MPU_RASR_A2_AP_Pos     = 0x18       // Position of AP field.
	MPU_RASR_A2_AP_Msk     = 0x7000000  // Bit mask of AP field.
	MPU_RASR_A2_XN_Pos     = 0x1c       // Position of XN field.
	MPU_RASR_A2_XN_Msk     = 0x10000000 // Bit mask of XN field.
	MPU_RASR_A2_XN         = 0x10000000 // Bit XN.

	// RBAR_A3: MPU Alias 3 Region Base Address Register
	MPU_RBAR_A3_REGION_Pos = 0x0        // Position of REGION field.
	MPU_RBAR_A3_REGION_Msk = 0xf        // Bit mask of REGION field.
	MPU_RBAR_A3_VALID_Pos  = 0x4        // Position of VALID field.
	MPU_RBAR_A3_VALID_Msk  = 0x10       // Bit mask of VALID field.
	MPU_RBAR_A3_VALID      = 0x10       // Bit VALID.
	MPU_RBAR_A3_ADDR_Pos   = 0x5        // Position of ADDR field.
	MPU_RBAR_A3_ADDR_Msk   = 0xffffffe0 // Bit mask of ADDR field.

	// RASR_A3: MPU Alias 3 Region Attribute and Size Register
	MPU_RASR_A3_ENABLE_Pos = 0x0        // Position of ENABLE field.
	MPU_RASR_A3_ENABLE_Msk = 0x1        // Bit mask of ENABLE field.
	MPU_RASR_A3_ENABLE     = 0x1        // Bit ENABLE.
	MPU_RASR_A3_SIZE_Pos   = 0x1        // Position of SIZE field.
	MPU_RASR_A3_SIZE_Msk   = 0x2        // Bit mask of SIZE field.
	MPU_RASR_A3_SIZE       = 0x2        // Bit SIZE.
	MPU_RASR_A3_SRD_Pos    = 0x8        // Position of SRD field.
	MPU_RASR_A3_SRD_Msk    = 0xff00     // Bit mask of SRD field.
	MPU_RASR_A3_B_Pos      = 0x10       // Position of B field.
	MPU_RASR_A3_B_Msk      = 0x10000    // Bit mask of B field.
	MPU_RASR_A3_B          = 0x10000    // Bit B.
	MPU_RASR_A3_C_Pos      = 0x11       // Position of C field.
	MPU_RASR_A3_C_Msk      = 0x20000    // Bit mask of C field.
	MPU_RASR_A3_C          = 0x20000    // Bit C.
	MPU_RASR_A3_S_Pos      = 0x12       // Position of S field.
	MPU_RASR_A3_S_Msk      = 0x40000    // Bit mask of S field.
	MPU_RASR_A3_S          = 0x40000    // Bit S.
	MPU_RASR_A3_TEX_Pos    = 0x13       // Position of TEX field.
	MPU_RASR_A3_TEX_Msk    = 0x380000   // Bit mask of TEX field.
	MPU_RASR_A3_AP_Pos     = 0x18       // Position of AP field.
	MPU_RASR_A3_AP_Msk     = 0x7000000  // Bit mask of AP field.
	MPU_RASR_A3_XN_Pos     = 0x1c       // Position of XN field.
	MPU_RASR_A3_XN_Msk     = 0x10000000 // Bit mask of XN field.
	MPU_RASR_A3_XN         = 0x10000000 // Bit XN.
)

// Bitfields for NVIC: Nested Vectored Interrupt Controller
const (
	// ISER: Interrupt Set Enable Register
	NVIC_ISER_SETENA_Pos = 0x0        // Position of SETENA field.
	NVIC_ISER_SETENA_Msk = 0xffffffff // Bit mask of SETENA field.

	// ICER: Interrupt Clear Enable Register
	NVIC_ICER_CLRENA_Pos = 0x0        // Position of CLRENA field.
	NVIC_ICER_CLRENA_Msk = 0xffffffff // Bit mask of CLRENA field.

	// ISPR: Interrupt Set Pending Register
	NVIC_ISPR_SETPEND_Pos = 0x0        // Position of SETPEND field.
	NVIC_ISPR_SETPEND_Msk = 0xffffffff // Bit mask of SETPEND field.

	// ICPR: Interrupt Clear Pending Register
	NVIC_ICPR_CLRPEND_Pos = 0x0        // Position of CLRPEND field.
	NVIC_ICPR_CLRPEND_Msk = 0xffffffff // Bit mask of CLRPEND field.

	// IABR: Interrupt Active Bit Register
	NVIC_IABR_ACTIVE_Pos = 0x0        // Position of ACTIVE field.
	NVIC_IABR_ACTIVE_Msk = 0xffffffff // Bit mask of ACTIVE field.

	// IP: Interrupt Priority Register n
	NVIC_IP_PRI0_Pos = 0x0 // Position of PRI0 field.
	NVIC_IP_PRI0_Msk = 0x7 // Bit mask of PRI0 field.

	// STIR: Software Trigger Interrupt Register
	NVIC_STIR_INTID_Pos = 0x0   // Position of INTID field.
	NVIC_STIR_INTID_Msk = 0x1ff // Bit mask of INTID field.
)

// Bitfields for SysTick: System timer
const (
	// CSR: SysTick Control and Status Register
	SysTick_CSR_ENABLE_Pos        = 0x0     // Position of ENABLE field.
	SysTick_CSR_ENABLE_Msk        = 0x1     // Bit mask of ENABLE field.
	SysTick_CSR_ENABLE            = 0x1     // Bit ENABLE.
	SysTick_CSR_ENABLE_VALUE_0    = 0x0     // Counter disabled
	SysTick_CSR_ENABLE_VALUE_1    = 0x1     // Counter enabled
	SysTick_CSR_TICKINT_Pos       = 0x1     // Position of TICKINT field.
	SysTick_CSR_TICKINT_Msk       = 0x2     // Bit mask of TICKINT field.
	SysTick_CSR_TICKINT           = 0x2     // Bit TICKINT.
	SysTick_CSR_TICKINT_VALUE_0   = 0x0     // Counting down to 0 does not assert the SysTick exception request
	SysTick_CSR_TICKINT_VALUE_1   = 0x1     // Counting down to 0 asserts the SysTick exception request
	SysTick_CSR_CLKSOURCE_Pos     = 0x2     // Position of CLKSOURCE field.
	SysTick_CSR_CLKSOURCE_Msk     = 0x4     // Bit mask of CLKSOURCE field.
	SysTick_CSR_CLKSOURCE         = 0x4     // Bit CLKSOURCE.
	SysTick_CSR_CLKSOURCE_VALUE_0 = 0x0     // External clock
	SysTick_CSR_CLKSOURCE_VALUE_1 = 0x1     // Processor clock
	SysTick_CSR_COUNTFLAG_Pos     = 0x10    // Position of COUNTFLAG field.
	SysTick_CSR_COUNTFLAG_Msk     = 0x10000 // Bit mask of COUNTFLAG field.
	SysTick_CSR_COUNTFLAG         = 0x10000 // Bit COUNTFLAG.

	// RVR: SysTick Reload Value Register
	SysTick_RVR_RELOAD_Pos = 0x0      // Position of RELOAD field.
	SysTick_RVR_RELOAD_Msk = 0xffffff // Bit mask of RELOAD field.

	// CVR: SysTick Current Value Register
	SysTick_CVR_CURRENT_Pos = 0x0      // Position of CURRENT field.
	SysTick_CVR_CURRENT_Msk = 0xffffff // Bit mask of CURRENT field.

	// CALIB: SysTick Calibration Value Register
	SysTick_CALIB_TENMS_Pos     = 0x0        // Position of TENMS field.
	SysTick_CALIB_TENMS_Msk     = 0xffffff   // Bit mask of TENMS field.
	SysTick_CALIB_SKEW_Pos      = 0x1e       // Position of SKEW field.
	SysTick_CALIB_SKEW_Msk      = 0x40000000 // Bit mask of SKEW field.
	SysTick_CALIB_SKEW          = 0x40000000 // Bit SKEW.
	SysTick_CALIB_SKEW_VALUE_0  = 0x0        // 10ms calibration value is exact
	SysTick_CALIB_SKEW_VALUE_1  = 0x1        // 10ms calibration value is inexact, because of the clock frequency
	SysTick_CALIB_NOREF_Pos     = 0x1f       // Position of NOREF field.
	SysTick_CALIB_NOREF_Msk     = 0x80000000 // Bit mask of NOREF field.
	SysTick_CALIB_NOREF         = 0x80000000 // Bit NOREF.
	SysTick_CALIB_NOREF_VALUE_0 = 0x0        // The reference clock is provided
	SysTick_CALIB_NOREF_VALUE_1 = 0x1        // The reference clock is not provided
)

// Bitfields for SystemControl: System Control Registers
const (
	// ICTR: Interrupt Controller Type Register
	SystemControl_ICTR_INTLINESNUM_Pos = 0x0 // Position of INTLINESNUM field.
	SystemControl_ICTR_INTLINESNUM_Msk = 0xf // Bit mask of INTLINESNUM field.

	// ACTLR: Auxiliary Control Register
	SystemControl_ACTLR_DISMCYCINT_Pos = 0x0   // Position of DISMCYCINT field.
	SystemControl_ACTLR_DISMCYCINT_Msk = 0x1   // Bit mask of DISMCYCINT field.
	SystemControl_ACTLR_DISMCYCINT     = 0x1   // Bit DISMCYCINT.
	SystemControl_ACTLR_DISDEFWBUF_Pos = 0x1   // Position of DISDEFWBUF field.
	SystemControl_ACTLR_DISDEFWBUF_Msk = 0x2   // Bit mask of DISDEFWBUF field.
	SystemControl_ACTLR_DISDEFWBUF     = 0x2   // Bit DISDEFWBUF.
	SystemControl_ACTLR_DISFOLD_Pos    = 0x2   // Position of DISFOLD field.
	SystemControl_ACTLR_DISFOLD_Msk    = 0x4   // Bit mask of DISFOLD field.
	SystemControl_ACTLR_DISFOLD        = 0x4   // Bit DISFOLD.
	SystemControl_ACTLR_DISFPCA_Pos    = 0x8   // Position of DISFPCA field.
	SystemControl_ACTLR_DISFPCA_Msk    = 0x100 // Bit mask of DISFPCA field.
	SystemControl_ACTLR_DISFPCA        = 0x100 // Bit DISFPCA.
	SystemControl_ACTLR_DISOOFP_Pos    = 0x9   // Position of DISOOFP field.
	SystemControl_ACTLR_DISOOFP_Msk    = 0x200 // Bit mask of DISOOFP field.
	SystemControl_ACTLR_DISOOFP        = 0x200 // Bit DISOOFP.

	// CPUID: CPUID Base Register
	SystemControl_CPUID_REVISION_Pos    = 0x0        // Position of REVISION field.
	SystemControl_CPUID_REVISION_Msk    = 0xf        // Bit mask of REVISION field.
	SystemControl_CPUID_PARTNO_Pos      = 0x4        // Position of PARTNO field.
	SystemControl_CPUID_PARTNO_Msk      = 0xfff0     // Bit mask of PARTNO field.
	SystemControl_CPUID_CONSTANT_Pos    = 0x10       // Position of CONSTANT field.
	SystemControl_CPUID_CONSTANT_Msk    = 0xf0000    // Bit mask of CONSTANT field.
	SystemControl_CPUID_VARIANT_Pos     = 0x14       // Position of VARIANT field.
	SystemControl_CPUID_VARIANT_Msk     = 0xf00000   // Bit mask of VARIANT field.
	SystemControl_CPUID_IMPLEMENTER_Pos = 0x18       // Position of IMPLEMENTER field.
	SystemControl_CPUID_IMPLEMENTER_Msk = 0xff000000 // Bit mask of IMPLEMENTER field.

	// ICSR: Interrupt Control and State Register
	SystemControl_ICSR_VECTACTIVE_Pos     = 0x0        // Position of VECTACTIVE field.
	SystemControl_ICSR_VECTACTIVE_Msk     = 0x1ff      // Bit mask of VECTACTIVE field.
	SystemControl_ICSR_RETTOBASE_Pos      = 0xb        // Position of RETTOBASE field.
	SystemControl_ICSR_RETTOBASE_Msk      = 0x800      // Bit mask of RETTOBASE field.
	SystemControl_ICSR_RETTOBASE          = 0x800      // Bit RETTOBASE.
	SystemControl_ICSR_VECTPENDING_Pos    = 0xc        // Position of VECTPENDING field.
	SystemControl_ICSR_VECTPENDING_Msk    = 0x3f000    // Bit mask of VECTPENDING field.
	SystemControl_ICSR_ISRPENDING_Pos     = 0x16       // Position of ISRPENDING field.
	SystemControl_ICSR_ISRPENDING_Msk     = 0x400000   // Bit mask of ISRPENDING field.
	SystemControl_ICSR_ISRPENDING         = 0x400000   // Bit ISRPENDING.
	SystemControl_ICSR_ISRPREEMPT_Pos     = 0x17       // Position of ISRPREEMPT field.
	SystemControl_ICSR_ISRPREEMPT_Msk     = 0x800000   // Bit mask of ISRPREEMPT field.
	SystemControl_ICSR_ISRPREEMPT         = 0x800000   // Bit ISRPREEMPT.
	SystemControl_ICSR_PENDSTCLR_Pos      = 0x19       // Position of PENDSTCLR field.
	SystemControl_ICSR_PENDSTCLR_Msk      = 0x2000000  // Bit mask of PENDSTCLR field.
	SystemControl_ICSR_PENDSTCLR          = 0x2000000  // Bit PENDSTCLR.
	SystemControl_ICSR_PENDSTCLR_VALUE_0  = 0x0        // No effect
	SystemControl_ICSR_PENDSTCLR_VALUE_1  = 0x1        // Removes the pending state from the SysTick exception
	SystemControl_ICSR_PENDSTSET_Pos      = 0x1a       // Position of PENDSTSET field.
	SystemControl_ICSR_PENDSTSET_Msk      = 0x4000000  // Bit mask of PENDSTSET field.
	SystemControl_ICSR_PENDSTSET          = 0x4000000  // Bit PENDSTSET.
	SystemControl_ICSR_PENDSTSET_VALUE_0  = 0x0        // Write: no effect; read: SysTick exception is not pending
	SystemControl_ICSR_PENDSTSET_VALUE_1  = 0x1        // Write: changes SysTick exception state to pending; read: SysTick exception is pending
	SystemControl_ICSR_PENDSVCLR_Pos      = 0x1b       // Position of PENDSVCLR field.
	SystemControl_ICSR_PENDSVCLR_Msk      = 0x8000000  // Bit mask of PENDSVCLR field.
	SystemControl_ICSR_PENDSVCLR          = 0x8000000  // Bit PENDSVCLR.
	SystemControl_ICSR_PENDSVCLR_VALUE_0  = 0x0        // No effect
	SystemControl_ICSR_PENDSVCLR_VALUE_1  = 0x1        // Removes the pending state from the PendSV exception
	SystemControl_ICSR_PENDSVSET_Pos      = 0x1c       // Position of PENDSVSET field.
	SystemControl_ICSR_PENDSVSET_Msk      = 0x10000000 // Bit mask of PENDSVSET field.
	SystemControl_ICSR_PENDSVSET          = 0x10000000 // Bit PENDSVSET.
	SystemControl_ICSR_PENDSVSET_VALUE_0  = 0x0        // Write: no effect; read: PendSV exception is not pending
	SystemControl_ICSR_PENDSVSET_VALUE_1  = 0x1        // Write: changes PendSV exception state to pending; read: PendSV exception is pending
	SystemControl_ICSR_NMIPENDSET_Pos     = 0x1f       // Position of NMIPENDSET field.
	SystemControl_ICSR_NMIPENDSET_Msk     = 0x80000000 // Bit mask of NMIPENDSET field.
	SystemControl_ICSR_NMIPENDSET         = 0x80000000 // Bit NMIPENDSET.
	SystemControl_ICSR_NMIPENDSET_VALUE_0 = 0x0        // Write: no effect; read: NMI exception is not pending
	SystemControl_ICSR_NMIPENDSET_VALUE_1 = 0x1        // Write: changes NMI exception state to pending; read: NMI exception is pending

	// VTOR: Vector Table Offset Register
	SystemControl_VTOR_TBLOFF_Pos = 0x7        // Position of TBLOFF field.
	SystemControl_VTOR_TBLOFF_Msk = 0xffffff80 // Bit mask of TBLOFF field.

	// AIRCR: Application Interrupt and Reset Control Register
	SystemControl_AIRCR_VECTRESET_Pos       = 0x0        // Position of VECTRESET field.
	SystemControl_AIRCR_VECTRESET_Msk       = 0x1        // Bit mask of VECTRESET field.
	SystemControl_AIRCR_VECTRESET           = 0x1        // Bit VECTRESET.
	SystemControl_AIRCR_VECTCLRACTIVE_Pos   = 0x1        // Position of VECTCLRACTIVE field.
	SystemControl_AIRCR_VECTCLRACTIVE_Msk   = 0x2        // Bit mask of VECTCLRACTIVE field.
	SystemControl_AIRCR_VECTCLRACTIVE       = 0x2        // Bit VECTCLRACTIVE.
	SystemControl_AIRCR_SYSRESETREQ_Pos     = 0x2        // Position of SYSRESETREQ field.
	SystemControl_AIRCR_SYSRESETREQ_Msk     = 0x4        // Bit mask of SYSRESETREQ field.
	SystemControl_AIRCR_SYSRESETREQ         = 0x4        // Bit SYSRESETREQ.
	SystemControl_AIRCR_SYSRESETREQ_VALUE_0 = 0x0        // No system reset request
	SystemControl_AIRCR_SYSRESETREQ_VALUE_1 = 0x1        // Asserts a signal to the outer system that requests a reset
	SystemControl_AIRCR_PRIGROUP_Pos        = 0x8        // Position of PRIGROUP field.
	SystemControl_AIRCR_PRIGROUP_Msk        = 0x700      // Bit mask of PRIGROUP field.
	SystemControl_AIRCR_ENDIANNESS_Pos      = 0xf        // Position of ENDIANNESS field.
	SystemControl_AIRCR_ENDIANNESS_Msk      = 0x8000     // Bit mask of ENDIANNESS field.
	SystemControl_AIRCR_ENDIANNESS          = 0x8000     // Bit ENDIANNESS.
	SystemControl_AIRCR_ENDIANNESS_VALUE_0  = 0x0        // Little-endian
	SystemControl_AIRCR_ENDIANNESS_VALUE_1  = 0x1        // Big-endian
	SystemControl_AIRCR_VECTKEY_Pos         = 0x10       // Position of VECTKEY field.
	SystemControl_AIRCR_VECTKEY_Msk         = 0xffff0000 // Bit mask of VECTKEY field.

	// SCR: System Control Register
	SystemControl_SCR_SLEEPONEXIT_Pos     = 0x1  // Position of SLEEPONEXIT field.
	SystemControl_SCR_SLEEPONEXIT_Msk     = 0x2  // Bit mask of SLEEPONEXIT field.
	SystemControl_SCR_SLEEPONEXIT         = 0x2  // Bit SLEEPONEXIT.
	SystemControl_SCR_SLEEPONEXIT_VALUE_0 = 0x0  // Do not sleep when returning to Thread mode
	SystemControl_SCR_SLEEPONEXIT_VALUE_1 = 0x1  // Enter sleep, or deep sleep, on return from an ISR
	SystemControl_SCR_SLEEPDEEP_Pos       = 0x2  // Position of SLEEPDEEP field.
	SystemControl_SCR_SLEEPDEEP_Msk       = 0x4  // Bit mask of SLEEPDEEP field.
	SystemControl_SCR_SLEEPDEEP           = 0x4  // Bit SLEEPDEEP.
	SystemControl_SCR_SLEEPDEEP_VALUE_0   = 0x0  // Sleep
	SystemControl_SCR_SLEEPDEEP_VALUE_1   = 0x1  // Deep sleep
	SystemControl_SCR_SEVONPEND_Pos       = 0x4  // Position of SEVONPEND field.
	SystemControl_SCR_SEVONPEND_Msk       = 0x10 // Bit mask of SEVONPEND field.
	SystemControl_SCR_SEVONPEND           = 0x10 // Bit SEVONPEND.
	SystemControl_SCR_SEVONPEND_VALUE_0   = 0x0  // Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded
	SystemControl_SCR_SEVONPEND_VALUE_1   = 0x1  // Enabled events and all interrupts, including disabled interrupts, can wakeup the processor

	// CCR: Configuration and Control Register
	SystemControl_CCR_NONBASETHRDENA_Pos  = 0x0   // Position of NONBASETHRDENA field.
	SystemControl_CCR_NONBASETHRDENA_Msk  = 0x1   // Bit mask of NONBASETHRDENA field.
	SystemControl_CCR_NONBASETHRDENA      = 0x1   // Bit NONBASETHRDENA.
	SystemControl_CCR_USERSETMPEND_Pos    = 0x1   // Position of USERSETMPEND field.
	SystemControl_CCR_USERSETMPEND_Msk    = 0x2   // Bit mask of USERSETMPEND field.
	SystemControl_CCR_USERSETMPEND        = 0x2   // Bit USERSETMPEND.
	SystemControl_CCR_UNALIGN_TRP_Pos     = 0x3   // Position of UNALIGN_TRP field.
	SystemControl_CCR_UNALIGN_TRP_Msk     = 0x8   // Bit mask of UNALIGN_TRP field.
	SystemControl_CCR_UNALIGN_TRP         = 0x8   // Bit UNALIGN_TRP.
	SystemControl_CCR_UNALIGN_TRP_VALUE_0 = 0x0   // Do not trap unaligned halfword and word accesses
	SystemControl_CCR_UNALIGN_TRP_VALUE_1 = 0x1   // Trap unaligned halfword and word accesses
	SystemControl_CCR_DIV_0_TRP_Pos       = 0x4   // Position of DIV_0_TRP field.
	SystemControl_CCR_DIV_0_TRP_Msk       = 0x10  // Bit mask of DIV_0_TRP field.
	SystemControl_CCR_DIV_0_TRP           = 0x10  // Bit DIV_0_TRP.
	SystemControl_CCR_BFHFNMIGN_Pos       = 0x8   // Position of BFHFNMIGN field.
	SystemControl_CCR_BFHFNMIGN_Msk       = 0x100 // Bit mask of BFHFNMIGN field.
	SystemControl_CCR_BFHFNMIGN           = 0x100 // Bit BFHFNMIGN.
	SystemControl_CCR_STKALIGN_Pos        = 0x9   // Position of STKALIGN field.
	SystemControl_CCR_STKALIGN_Msk        = 0x200 // Bit mask of STKALIGN field.
	SystemControl_CCR_STKALIGN            = 0x200 // Bit STKALIGN.
	SystemControl_CCR_STKALIGN_VALUE_0    = 0x0   // 4-byte aligned
	SystemControl_CCR_STKALIGN_VALUE_1    = 0x1   // 8-byte aligned

	// SHPR1: System Handler Priority Register 1
	SystemControl_SHPR1_PRI_4_Pos = 0x0      // Position of PRI_4 field.
	SystemControl_SHPR1_PRI_4_Msk = 0xff     // Bit mask of PRI_4 field.
	SystemControl_SHPR1_PRI_5_Pos = 0x8      // Position of PRI_5 field.
	SystemControl_SHPR1_PRI_5_Msk = 0xff00   // Bit mask of PRI_5 field.
	SystemControl_SHPR1_PRI_6_Pos = 0x10     // Position of PRI_6 field.
	SystemControl_SHPR1_PRI_6_Msk = 0xff0000 // Bit mask of PRI_6 field.

	// SHPR2: System Handler Priority Register 2
	SystemControl_SHPR2_PRI_11_Pos = 0x18       // Position of PRI_11 field.
	SystemControl_SHPR2_PRI_11_Msk = 0xff000000 // Bit mask of PRI_11 field.

	// SHPR3: System Handler Priority Register 3
	SystemControl_SHPR3_PRI_14_Pos = 0x10       // Position of PRI_14 field.
	SystemControl_SHPR3_PRI_14_Msk = 0xff0000   // Bit mask of PRI_14 field.
	SystemControl_SHPR3_PRI_15_Pos = 0x18       // Position of PRI_15 field.
	SystemControl_SHPR3_PRI_15_Msk = 0xff000000 // Bit mask of PRI_15 field.

	// SHCSR: System Handler Control and State Register
	SystemControl_SHCSR_MEMFAULTACT_Pos    = 0x0     // Position of MEMFAULTACT field.
	SystemControl_SHCSR_MEMFAULTACT_Msk    = 0x1     // Bit mask of MEMFAULTACT field.
	SystemControl_SHCSR_MEMFAULTACT        = 0x1     // Bit MEMFAULTACT.
	SystemControl_SHCSR_BUSFAULTACT_Pos    = 0x1     // Position of BUSFAULTACT field.
	SystemControl_SHCSR_BUSFAULTACT_Msk    = 0x2     // Bit mask of BUSFAULTACT field.
	SystemControl_SHCSR_BUSFAULTACT        = 0x2     // Bit BUSFAULTACT.
	SystemControl_SHCSR_USGFAULTACT_Pos    = 0x3     // Position of USGFAULTACT field.
	SystemControl_SHCSR_USGFAULTACT_Msk    = 0x8     // Bit mask of USGFAULTACT field.
	SystemControl_SHCSR_USGFAULTACT        = 0x8     // Bit USGFAULTACT.
	SystemControl_SHCSR_SVCALLACT_Pos      = 0x7     // Position of SVCALLACT field.
	SystemControl_SHCSR_SVCALLACT_Msk      = 0x80    // Bit mask of SVCALLACT field.
	SystemControl_SHCSR_SVCALLACT          = 0x80    // Bit SVCALLACT.
	SystemControl_SHCSR_MONITORACT_Pos     = 0x8     // Position of MONITORACT field.
	SystemControl_SHCSR_MONITORACT_Msk     = 0x100   // Bit mask of MONITORACT field.
	SystemControl_SHCSR_MONITORACT         = 0x100   // Bit MONITORACT.
	SystemControl_SHCSR_PENDSVACT_Pos      = 0xa     // Position of PENDSVACT field.
	SystemControl_SHCSR_PENDSVACT_Msk      = 0x400   // Bit mask of PENDSVACT field.
	SystemControl_SHCSR_PENDSVACT          = 0x400   // Bit PENDSVACT.
	SystemControl_SHCSR_SYSTICKACT_Pos     = 0xb     // Position of SYSTICKACT field.
	SystemControl_SHCSR_SYSTICKACT_Msk     = 0x800   // Bit mask of SYSTICKACT field.
	SystemControl_SHCSR_SYSTICKACT         = 0x800   // Bit SYSTICKACT.
	SystemControl_SHCSR_USGFAULTPENDED_Pos = 0xc     // Position of USGFAULTPENDED field.
	SystemControl_SHCSR_USGFAULTPENDED_Msk = 0x1000  // Bit mask of USGFAULTPENDED field.
	SystemControl_SHCSR_USGFAULTPENDED     = 0x1000  // Bit USGFAULTPENDED.
	SystemControl_SHCSR_MEMFAULTPENDED_Pos = 0xd     // Position of MEMFAULTPENDED field.
	SystemControl_SHCSR_MEMFAULTPENDED_Msk = 0x2000  // Bit mask of MEMFAULTPENDED field.
	SystemControl_SHCSR_MEMFAULTPENDED     = 0x2000  // Bit MEMFAULTPENDED.
	SystemControl_SHCSR_BUSFAULTPENDED_Pos = 0xe     // Position of BUSFAULTPENDED field.
	SystemControl_SHCSR_BUSFAULTPENDED_Msk = 0x4000  // Bit mask of BUSFAULTPENDED field.
	SystemControl_SHCSR_BUSFAULTPENDED     = 0x4000  // Bit BUSFAULTPENDED.
	SystemControl_SHCSR_SVCALLPENDED_Pos   = 0xf     // Position of SVCALLPENDED field.
	SystemControl_SHCSR_SVCALLPENDED_Msk   = 0x8000  // Bit mask of SVCALLPENDED field.
	SystemControl_SHCSR_SVCALLPENDED       = 0x8000  // Bit SVCALLPENDED.
	SystemControl_SHCSR_MEMFAULTENA_Pos    = 0x10    // Position of MEMFAULTENA field.
	SystemControl_SHCSR_MEMFAULTENA_Msk    = 0x10000 // Bit mask of MEMFAULTENA field.
	SystemControl_SHCSR_MEMFAULTENA        = 0x10000 // Bit MEMFAULTENA.
	SystemControl_SHCSR_BUSFAULTENA_Pos    = 0x11    // Position of BUSFAULTENA field.
	SystemControl_SHCSR_BUSFAULTENA_Msk    = 0x20000 // Bit mask of BUSFAULTENA field.
	SystemControl_SHCSR_BUSFAULTENA        = 0x20000 // Bit BUSFAULTENA.
	SystemControl_SHCSR_USGFAULTENA_Pos    = 0x12    // Position of USGFAULTENA field.
	SystemControl_SHCSR_USGFAULTENA_Msk    = 0x40000 // Bit mask of USGFAULTENA field.
	SystemControl_SHCSR_USGFAULTENA        = 0x40000 // Bit USGFAULTENA.

	// CFSR: Configurable Fault Status Register
	SystemControl_CFSR_IACCVIOL_Pos    = 0x0       // Position of IACCVIOL field.
	SystemControl_CFSR_IACCVIOL_Msk    = 0x1       // Bit mask of IACCVIOL field.
	SystemControl_CFSR_IACCVIOL        = 0x1       // Bit IACCVIOL.
	SystemControl_CFSR_DACCVIOL_Pos    = 0x1       // Position of DACCVIOL field.
	SystemControl_CFSR_DACCVIOL_Msk    = 0x2       // Bit mask of DACCVIOL field.
	SystemControl_CFSR_DACCVIOL        = 0x2       // Bit DACCVIOL.
	SystemControl_CFSR_MUNSTKERR_Pos   = 0x3       // Position of MUNSTKERR field.
	SystemControl_CFSR_MUNSTKERR_Msk   = 0x8       // Bit mask of MUNSTKERR field.
	SystemControl_CFSR_MUNSTKERR       = 0x8       // Bit MUNSTKERR.
	SystemControl_CFSR_MSTKERR_Pos     = 0x4       // Position of MSTKERR field.
	SystemControl_CFSR_MSTKERR_Msk     = 0x10      // Bit mask of MSTKERR field.
	SystemControl_CFSR_MSTKERR         = 0x10      // Bit MSTKERR.
	SystemControl_CFSR_MLSPERR_Pos     = 0x5       // Position of MLSPERR field.
	SystemControl_CFSR_MLSPERR_Msk     = 0x20      // Bit mask of MLSPERR field.
	SystemControl_CFSR_MLSPERR         = 0x20      // Bit MLSPERR.
	SystemControl_CFSR_MMARVALID_Pos   = 0x7       // Position of MMARVALID field.
	SystemControl_CFSR_MMARVALID_Msk   = 0x80      // Bit mask of MMARVALID field.
	SystemControl_CFSR_MMARVALID       = 0x80      // Bit MMARVALID.
	SystemControl_CFSR_IBUSERR_Pos     = 0x8       // Position of IBUSERR field.
	SystemControl_CFSR_IBUSERR_Msk     = 0x100     // Bit mask of IBUSERR field.
	SystemControl_CFSR_IBUSERR         = 0x100     // Bit IBUSERR.
	SystemControl_CFSR_PRECISERR_Pos   = 0x9       // Position of PRECISERR field.
	SystemControl_CFSR_PRECISERR_Msk   = 0x200     // Bit mask of PRECISERR field.
	SystemControl_CFSR_PRECISERR       = 0x200     // Bit PRECISERR.
	SystemControl_CFSR_IMPRECISERR_Pos = 0xa       // Position of IMPRECISERR field.
	SystemControl_CFSR_IMPRECISERR_Msk = 0x400     // Bit mask of IMPRECISERR field.
	SystemControl_CFSR_IMPRECISERR     = 0x400     // Bit IMPRECISERR.
	SystemControl_CFSR_UNSTKERR_Pos    = 0xb       // Position of UNSTKERR field.
	SystemControl_CFSR_UNSTKERR_Msk    = 0x800     // Bit mask of UNSTKERR field.
	SystemControl_CFSR_UNSTKERR        = 0x800     // Bit UNSTKERR.
	SystemControl_CFSR_STKERR_Pos      = 0xc       // Position of STKERR field.
	SystemControl_CFSR_STKERR_Msk      = 0x1000    // Bit mask of STKERR field.
	SystemControl_CFSR_STKERR          = 0x1000    // Bit STKERR.
	SystemControl_CFSR_LSPERR_Pos      = 0xd       // Position of LSPERR field.
	SystemControl_CFSR_LSPERR_Msk      = 0x2000    // Bit mask of LSPERR field.
	SystemControl_CFSR_LSPERR          = 0x2000    // Bit LSPERR.
	SystemControl_CFSR_BFARVALID_Pos   = 0xf       // Position of BFARVALID field.
	SystemControl_CFSR_BFARVALID_Msk   = 0x8000    // Bit mask of BFARVALID field.
	SystemControl_CFSR_BFARVALID       = 0x8000    // Bit BFARVALID.
	SystemControl_CFSR_UNDEFINSTR_Pos  = 0x10      // Position of UNDEFINSTR field.
	SystemControl_CFSR_UNDEFINSTR_Msk  = 0x10000   // Bit mask of UNDEFINSTR field.
	SystemControl_CFSR_UNDEFINSTR      = 0x10000   // Bit UNDEFINSTR.
	SystemControl_CFSR_INVSTATE_Pos    = 0x11      // Position of INVSTATE field.
	SystemControl_CFSR_INVSTATE_Msk    = 0x20000   // Bit mask of INVSTATE field.
	SystemControl_CFSR_INVSTATE        = 0x20000   // Bit INVSTATE.
	SystemControl_CFSR_INVPC_Pos       = 0x12      // Position of INVPC field.
	SystemControl_CFSR_INVPC_Msk       = 0x40000   // Bit mask of INVPC field.
	SystemControl_CFSR_INVPC           = 0x40000   // Bit INVPC.
	SystemControl_CFSR_NOCP_Pos        = 0x13      // Position of NOCP field.
	SystemControl_CFSR_NOCP_Msk        = 0x80000   // Bit mask of NOCP field.
	SystemControl_CFSR_NOCP            = 0x80000   // Bit NOCP.
	SystemControl_CFSR_UNALIGNED_Pos   = 0x18      // Position of UNALIGNED field.
	SystemControl_CFSR_UNALIGNED_Msk   = 0x1000000 // Bit mask of UNALIGNED field.
	SystemControl_CFSR_UNALIGNED       = 0x1000000 // Bit UNALIGNED.
	SystemControl_CFSR_DIVBYZERO_Pos   = 0x19      // Position of DIVBYZERO field.
	SystemControl_CFSR_DIVBYZERO_Msk   = 0x2000000 // Bit mask of DIVBYZERO field.
	SystemControl_CFSR_DIVBYZERO       = 0x2000000 // Bit DIVBYZERO.

	// HFSR: HardFault Status Register
	SystemControl_HFSR_VECTTBL_Pos  = 0x1        // Position of VECTTBL field.
	SystemControl_HFSR_VECTTBL_Msk  = 0x2        // Bit mask of VECTTBL field.
	SystemControl_HFSR_VECTTBL      = 0x2        // Bit VECTTBL.
	SystemControl_HFSR_FORCED_Pos   = 0x1e       // Position of FORCED field.
	SystemControl_HFSR_FORCED_Msk   = 0x40000000 // Bit mask of FORCED field.
	SystemControl_HFSR_FORCED       = 0x40000000 // Bit FORCED.
	SystemControl_HFSR_DEBUGEVT_Pos = 0x1f       // Position of DEBUGEVT field.
	SystemControl_HFSR_DEBUGEVT_Msk = 0x80000000 // Bit mask of DEBUGEVT field.
	SystemControl_HFSR_DEBUGEVT     = 0x80000000 // Bit DEBUGEVT.

	// DFSR: Debug Fault Status Register
	SystemControl_DFSR_HALTED_Pos   = 0x0  // Position of HALTED field.
	SystemControl_DFSR_HALTED_Msk   = 0x1  // Bit mask of HALTED field.
	SystemControl_DFSR_HALTED       = 0x1  // Bit HALTED.
	SystemControl_DFSR_BKPT_Pos     = 0x1  // Position of BKPT field.
	SystemControl_DFSR_BKPT_Msk     = 0x2  // Bit mask of BKPT field.
	SystemControl_DFSR_BKPT         = 0x2  // Bit BKPT.
	SystemControl_DFSR_DWTTRAP_Pos  = 0x2  // Position of DWTTRAP field.
	SystemControl_DFSR_DWTTRAP_Msk  = 0x4  // Bit mask of DWTTRAP field.
	SystemControl_DFSR_DWTTRAP      = 0x4  // Bit DWTTRAP.
	SystemControl_DFSR_VCATCH_Pos   = 0x3  // Position of VCATCH field.
	SystemControl_DFSR_VCATCH_Msk   = 0x8  // Bit mask of VCATCH field.
	SystemControl_DFSR_VCATCH       = 0x8  // Bit VCATCH.
	SystemControl_DFSR_EXTERNAL_Pos = 0x4  // Position of EXTERNAL field.
	SystemControl_DFSR_EXTERNAL_Msk = 0x10 // Bit mask of EXTERNAL field.
	SystemControl_DFSR_EXTERNAL     = 0x10 // Bit EXTERNAL.

	// MMFAR: MemManage Fault Address Register
	SystemControl_MMFAR_ADDRESS_Pos = 0x0        // Position of ADDRESS field.
	SystemControl_MMFAR_ADDRESS_Msk = 0xffffffff // Bit mask of ADDRESS field.

	// BFAR: BusFault Address Register
	SystemControl_BFAR_ADDRESS_Pos = 0x0        // Position of ADDRESS field.
	SystemControl_BFAR_ADDRESS_Msk = 0xffffffff // Bit mask of ADDRESS field.

	// AFSR: Auxiliary Fault Status Register
	SystemControl_AFSR_IMPDEF_Pos = 0x0        // Position of IMPDEF field.
	SystemControl_AFSR_IMPDEF_Msk = 0xffffffff // Bit mask of IMPDEF field.

	// CPACR: Coprocessor Access Control Register
	SystemControl_CPACR_CP10_Pos    = 0x14     // Position of CP10 field.
	SystemControl_CPACR_CP10_Msk    = 0x300000 // Bit mask of CP10 field.
	SystemControl_CPACR_CP10_DENIED = 0x0      // Access denied
	SystemControl_CPACR_CP10_PRIV   = 0x1      // Privileged access only
	SystemControl_CPACR_CP10_FULL   = 0x3      // Full access
	SystemControl_CPACR_CP11_Pos    = 0x16     // Position of CP11 field.
	SystemControl_CPACR_CP11_Msk    = 0xc00000 // Bit mask of CP11 field.
	SystemControl_CPACR_CP11_DENIED = 0x0      // Access denied
	SystemControl_CPACR_CP11_PRIV   = 0x1      // Privileged access only
	SystemControl_CPACR_CP11_FULL   = 0x3      // Full access
)

// Bitfields for TPI: Trace Port Interface Register
const (
	// ACPR: Asynchronous Clock Prescaler Register
	TPI_ACPR_PRESCALER_Pos = 0x0    // Position of PRESCALER field.
	TPI_ACPR_PRESCALER_Msk = 0x1fff // Bit mask of PRESCALER field.

	// SPPR: Selected Pin Protocol Register
	TPI_SPPR_TXMODE_Pos = 0x0 // Position of TXMODE field.
	TPI_SPPR_TXMODE_Msk = 0x3 // Bit mask of TXMODE field.

	// FFSR: Formatter and Flush Status Register
	TPI_FFSR_FlInProg_Pos  = 0x0 // Position of FlInProg field.
	TPI_FFSR_FlInProg_Msk  = 0x1 // Bit mask of FlInProg field.
	TPI_FFSR_FlInProg      = 0x1 // Bit FlInProg.
	TPI_FFSR_FtStopped_Pos = 0x1 // Position of FtStopped field.
	TPI_FFSR_FtStopped_Msk = 0x2 // Bit mask of FtStopped field.
	TPI_FFSR_FtStopped     = 0x2 // Bit FtStopped.
	TPI_FFSR_TCPresent_Pos = 0x2 // Position of TCPresent field.
	TPI_FFSR_TCPresent_Msk = 0x4 // Bit mask of TCPresent field.
	TPI_FFSR_TCPresent     = 0x4 // Bit TCPresent.
	TPI_FFSR_FtNonStop_Pos = 0x3 // Position of FtNonStop field.
	TPI_FFSR_FtNonStop_Msk = 0x8 // Bit mask of FtNonStop field.
	TPI_FFSR_FtNonStop     = 0x8 // Bit FtNonStop.

	// FFCR: Formatter and Flush Control Register
	TPI_FFCR_EnFCont_Pos = 0x1   // Position of EnFCont field.
	TPI_FFCR_EnFCont_Msk = 0x2   // Bit mask of EnFCont field.
	TPI_FFCR_EnFCont     = 0x2   // Bit EnFCont.
	TPI_FFCR_TrigIn_Pos  = 0x8   // Position of TrigIn field.
	TPI_FFCR_TrigIn_Msk  = 0x100 // Bit mask of TrigIn field.
	TPI_FFCR_TrigIn      = 0x100 // Bit TrigIn.

	// TRIGGER: TRIGGER
	TPI_TRIGGER_TRIGGER_Pos = 0x0 // Position of TRIGGER field.
	TPI_TRIGGER_TRIGGER_Msk = 0x1 // Bit mask of TRIGGER field.
	TPI_TRIGGER_TRIGGER     = 0x1 // Bit TRIGGER.

	// FIFO0: Integration ETM Data
	TPI_FIFO0_ETM0_Pos          = 0x0        // Position of ETM0 field.
	TPI_FIFO0_ETM0_Msk          = 0xff       // Bit mask of ETM0 field.
	TPI_FIFO0_ETM1_Pos          = 0x8        // Position of ETM1 field.
	TPI_FIFO0_ETM1_Msk          = 0xff00     // Bit mask of ETM1 field.
	TPI_FIFO0_ETM2_Pos          = 0x10       // Position of ETM2 field.
	TPI_FIFO0_ETM2_Msk          = 0xff0000   // Bit mask of ETM2 field.
	TPI_FIFO0_ETM_bytecount_Pos = 0x18       // Position of ETM_bytecount field.
	TPI_FIFO0_ETM_bytecount_Msk = 0x3000000  // Bit mask of ETM_bytecount field.
	TPI_FIFO0_ETM_ATVALID_Pos   = 0x1a       // Position of ETM_ATVALID field.
	TPI_FIFO0_ETM_ATVALID_Msk   = 0x4000000  // Bit mask of ETM_ATVALID field.
	TPI_FIFO0_ETM_ATVALID       = 0x4000000  // Bit ETM_ATVALID.
	TPI_FIFO0_ITM_bytecount_Pos = 0x1b       // Position of ITM_bytecount field.
	TPI_FIFO0_ITM_bytecount_Msk = 0x18000000 // Bit mask of ITM_bytecount field.
	TPI_FIFO0_ITM_ATVALID_Pos   = 0x1d       // Position of ITM_ATVALID field.
	TPI_FIFO0_ITM_ATVALID_Msk   = 0x20000000 // Bit mask of ITM_ATVALID field.
	TPI_FIFO0_ITM_ATVALID       = 0x20000000 // Bit ITM_ATVALID.

	// ITATBCTR2: ITATBCTR2
	TPI_ITATBCTR2_ATREADY_Pos = 0x0 // Position of ATREADY field.
	TPI_ITATBCTR2_ATREADY_Msk = 0x1 // Bit mask of ATREADY field.
	TPI_ITATBCTR2_ATREADY     = 0x1 // Bit ATREADY.

	// ITATBCTR0: ITATBCTR0
	TPI_ITATBCTR0_ATREADY_Pos = 0x0 // Position of ATREADY field.
	TPI_ITATBCTR0_ATREADY_Msk = 0x1 // Bit mask of ATREADY field.
	TPI_ITATBCTR0_ATREADY     = 0x1 // Bit ATREADY.

	// FIFO1: Integration ITM Data
	TPI_FIFO1_ITM0_Pos          = 0x0        // Position of ITM0 field.
	TPI_FIFO1_ITM0_Msk          = 0xff       // Bit mask of ITM0 field.
	TPI_FIFO1_ITM1_Pos          = 0x8        // Position of ITM1 field.
	TPI_FIFO1_ITM1_Msk          = 0xff00     // Bit mask of ITM1 field.
	TPI_FIFO1_ITM2_Pos          = 0x10       // Position of ITM2 field.
	TPI_FIFO1_ITM2_Msk          = 0xff0000   // Bit mask of ITM2 field.
	TPI_FIFO1_ETM_bytecount_Pos = 0x18       // Position of ETM_bytecount field.
	TPI_FIFO1_ETM_bytecount_Msk = 0x3000000  // Bit mask of ETM_bytecount field.
	TPI_FIFO1_ETM_ATVALID_Pos   = 0x1a       // Position of ETM_ATVALID field.
	TPI_FIFO1_ETM_ATVALID_Msk   = 0x4000000  // Bit mask of ETM_ATVALID field.
	TPI_FIFO1_ETM_ATVALID       = 0x4000000  // Bit ETM_ATVALID.
	TPI_FIFO1_ITM_bytecount_Pos = 0x1b       // Position of ITM_bytecount field.
	TPI_FIFO1_ITM_bytecount_Msk = 0x18000000 // Bit mask of ITM_bytecount field.
	TPI_FIFO1_ITM_ATVALID_Pos   = 0x1d       // Position of ITM_ATVALID field.
	TPI_FIFO1_ITM_ATVALID_Msk   = 0x20000000 // Bit mask of ITM_ATVALID field.
	TPI_FIFO1_ITM_ATVALID       = 0x20000000 // Bit ITM_ATVALID.

	// ITCTRL: Integration Mode Control
	TPI_ITCTRL_Mode_Pos = 0x0 // Position of Mode field.
	TPI_ITCTRL_Mode_Msk = 0x1 // Bit mask of Mode field.
	TPI_ITCTRL_Mode     = 0x1 // Bit Mode.

	// DEVID: TPIU_DEVID
	TPI_DEVID_NrTraceInput_Pos = 0x0   // Position of NrTraceInput field.
	TPI_DEVID_NrTraceInput_Msk = 0x1   // Bit mask of NrTraceInput field.
	TPI_DEVID_NrTraceInput     = 0x1   // Bit NrTraceInput.
	TPI_DEVID_AsynClkIn_Pos    = 0x5   // Position of AsynClkIn field.
	TPI_DEVID_AsynClkIn_Msk    = 0x20  // Bit mask of AsynClkIn field.
	TPI_DEVID_AsynClkIn        = 0x20  // Bit AsynClkIn.
	TPI_DEVID_MinBufSz_Pos     = 0x6   // Position of MinBufSz field.
	TPI_DEVID_MinBufSz_Msk     = 0x1c0 // Bit mask of MinBufSz field.
	TPI_DEVID_PTINVALID_Pos    = 0x9   // Position of PTINVALID field.
	TPI_DEVID_PTINVALID_Msk    = 0x200 // Bit mask of PTINVALID field.
	TPI_DEVID_PTINVALID        = 0x200 // Bit PTINVALID.
	TPI_DEVID_MANCVALID_Pos    = 0xa   // Position of MANCVALID field.
	TPI_DEVID_MANCVALID_Msk    = 0x400 // Bit mask of MANCVALID field.
	TPI_DEVID_MANCVALID        = 0x400 // Bit MANCVALID.
	TPI_DEVID_NRZVALID_Pos     = 0xb   // Position of NRZVALID field.
	TPI_DEVID_NRZVALID_Msk     = 0x800 // Bit mask of NRZVALID field.
	TPI_DEVID_NRZVALID         = 0x800 // Bit NRZVALID.

	// DEVTYPE: TPIU_DEVTYPE
	TPI_DEVTYPE_SubType_Pos   = 0x0  // Position of SubType field.
	TPI_DEVTYPE_SubType_Msk   = 0xf  // Bit mask of SubType field.
	TPI_DEVTYPE_MajorType_Pos = 0x4  // Position of MajorType field.
	TPI_DEVTYPE_MajorType_Msk = 0xf0 // Bit mask of MajorType field.
)
