// Automatically generated file. DO NOT EDIT.
// Generated by gen-device-svd.go from MK22F25612.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/NXP

// +build nxp,mk22f25612

// MK22F25612 NXP Microcontroller
//
//     Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:
//     o Redistributions of source code must retain the above copyright notice, this list
//     of conditions and the following disclaimer.
//     o Redistributions in binary form must reproduce the above copyright notice, this
//     list of conditions and the following disclaimer in the documentation and/or
//     other materials provided with the distribution.
//     o Neither the name of the copyright holder nor the names of its
//     contributors may be used to endorse or promote products derived from this
//     software without specific prior written permission.
//     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
//     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
//     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
//     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
//     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
//     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
//     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
//     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
//     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
//     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
package nxp

import (
	"runtime/interrupt"
	"runtime/volatile"
	"unsafe"
)

// Some information about this device.
const (
	DEVICE = "MK22F25612"
)

// Interrupt numbers.
const (
	IRQ_DMA0           = 0  // Enhanced direct memory access controller
	IRQ_DMA1           = 1  // Enhanced direct memory access controller
	IRQ_DMA2           = 2  // Enhanced direct memory access controller
	IRQ_DMA3           = 3  // Enhanced direct memory access controller
	IRQ_DMA4           = 4  // Enhanced direct memory access controller
	IRQ_DMA5           = 5  // Enhanced direct memory access controller
	IRQ_DMA6           = 6  // Enhanced direct memory access controller
	IRQ_DMA7           = 7  // Enhanced direct memory access controller
	IRQ_DMA8           = 8  // Enhanced direct memory access controller
	IRQ_DMA9           = 9  // Enhanced direct memory access controller
	IRQ_DMA10          = 10 // Enhanced direct memory access controller
	IRQ_DMA11          = 11 // Enhanced direct memory access controller
	IRQ_DMA12          = 12 // Enhanced direct memory access controller
	IRQ_DMA13          = 13 // Enhanced direct memory access controller
	IRQ_DMA14          = 14 // Enhanced direct memory access controller
	IRQ_DMA15          = 15 // Enhanced direct memory access controller
	IRQ_DMA_Error      = 16 // Enhanced direct memory access controller
	IRQ_MCM            = 17 // Core Platform Miscellaneous Control Module
	IRQ_FTF            = 18 // Flash Memory Interface
	IRQ_Read_Collision = 19 // Flash Memory Interface
	IRQ_LVD_LVW        = 20 // Power Management Controller
	IRQ_LLWU           = 21 // Low leakage wakeup unit
	IRQ_WDOG_EWM       = 22 // Generation 2008 Watchdog Timer // External Watchdog Monitor
	IRQ_RNG            = 23 // Random Number Generator Accelerator
	IRQ_I2C0           = 24 // Inter-Integrated Circuit
	IRQ_I2C1           = 25 // Inter-Integrated Circuit
	IRQ_SPI0           = 26 // Serial Peripheral Interface
	IRQ_SPI1           = 27 // Serial Peripheral Interface
	IRQ_I2S0_Tx        = 28 // Inter-IC Sound / Synchronous Audio Interface
	IRQ_I2S0_Rx        = 29 // Inter-IC Sound / Synchronous Audio Interface
	IRQ_LPUART0        = 30 // Universal Asynchronous Receiver/Transmitter
	IRQ_UART0_RX_TX    = 31 // Serial Communication Interface
	IRQ_UART0_ERR      = 32 // Serial Communication Interface
	IRQ_UART1_RX_TX    = 33 // Serial Communication Interface
	IRQ_UART1_ERR      = 34 // Serial Communication Interface
	IRQ_UART2_RX_TX    = 35 // Serial Communication Interface
	IRQ_UART2_ERR      = 36 // Serial Communication Interface
	IRQ_ADC0           = 39 // Analog-to-Digital Converter
	IRQ_CMP0           = 40 // High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)
	IRQ_CMP1           = 41 // High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)
	IRQ_FTM0           = 42 // FlexTimer Module
	IRQ_FTM1           = 43 // FlexTimer Module
	IRQ_FTM2           = 44 // FlexTimer Module
	IRQ_RTC            = 46 // Secure Real Time Clock
	IRQ_RTC_Seconds    = 47 // Secure Real Time Clock
	IRQ_PIT0           = 48 // Periodic Interrupt Timer
	IRQ_PIT1           = 49 // Periodic Interrupt Timer
	IRQ_PIT2           = 50 // Periodic Interrupt Timer
	IRQ_PIT3           = 51 // Periodic Interrupt Timer
	IRQ_PDB0           = 52 // Programmable Delay Block
	IRQ_USB0           = 53 // Universal Serial Bus, OTG Capable Controller
	IRQ_DAC0           = 56 // 12-Bit Digital-to-Analog Converter
	IRQ_LPTMR0         = 58 // Low Power Timer
	IRQ_PORTA          = 59 // Pin Control and Interrupts // General Purpose Input/Output
	IRQ_PORTB          = 60 // Pin Control and Interrupts // General Purpose Input/Output
	IRQ_PORTC          = 61 // Pin Control and Interrupts // General Purpose Input/Output
	IRQ_PORTD          = 62 // Pin Control and Interrupts // General Purpose Input/Output
	IRQ_PORTE          = 63 // Pin Control and Interrupts // General Purpose Input/Output
	IRQ_ADC1           = 73 // Analog-to-Digital Converter
	IRQ_max            = 73 // Highest interrupt number on this device.
)

// Map interrupt numbers to function names.
// These aren't real calls, they're removed by the compiler.
var (
	_ = interrupt.Register(IRQ_DMA0, "DMA0_IRQHandler")
	_ = interrupt.Register(IRQ_DMA1, "DMA1_IRQHandler")
	_ = interrupt.Register(IRQ_DMA2, "DMA2_IRQHandler")
	_ = interrupt.Register(IRQ_DMA3, "DMA3_IRQHandler")
	_ = interrupt.Register(IRQ_DMA4, "DMA4_IRQHandler")
	_ = interrupt.Register(IRQ_DMA5, "DMA5_IRQHandler")
	_ = interrupt.Register(IRQ_DMA6, "DMA6_IRQHandler")
	_ = interrupt.Register(IRQ_DMA7, "DMA7_IRQHandler")
	_ = interrupt.Register(IRQ_DMA8, "DMA8_IRQHandler")
	_ = interrupt.Register(IRQ_DMA9, "DMA9_IRQHandler")
	_ = interrupt.Register(IRQ_DMA10, "DMA10_IRQHandler")
	_ = interrupt.Register(IRQ_DMA11, "DMA11_IRQHandler")
	_ = interrupt.Register(IRQ_DMA12, "DMA12_IRQHandler")
	_ = interrupt.Register(IRQ_DMA13, "DMA13_IRQHandler")
	_ = interrupt.Register(IRQ_DMA14, "DMA14_IRQHandler")
	_ = interrupt.Register(IRQ_DMA15, "DMA15_IRQHandler")
	_ = interrupt.Register(IRQ_DMA_Error, "DMA_Error_IRQHandler")
	_ = interrupt.Register(IRQ_MCM, "MCM_IRQHandler")
	_ = interrupt.Register(IRQ_FTF, "FTF_IRQHandler")
	_ = interrupt.Register(IRQ_Read_Collision, "Read_Collision_IRQHandler")
	_ = interrupt.Register(IRQ_LVD_LVW, "LVD_LVW_IRQHandler")
	_ = interrupt.Register(IRQ_LLWU, "LLWU_IRQHandler")
	_ = interrupt.Register(IRQ_WDOG_EWM, "WDOG_EWM_IRQHandler")
	_ = interrupt.Register(IRQ_RNG, "RNG_IRQHandler")
	_ = interrupt.Register(IRQ_I2C0, "I2C0_IRQHandler")
	_ = interrupt.Register(IRQ_I2C1, "I2C1_IRQHandler")
	_ = interrupt.Register(IRQ_SPI0, "SPI0_IRQHandler")
	_ = interrupt.Register(IRQ_SPI1, "SPI1_IRQHandler")
	_ = interrupt.Register(IRQ_I2S0_Tx, "I2S0_Tx_IRQHandler")
	_ = interrupt.Register(IRQ_I2S0_Rx, "I2S0_Rx_IRQHandler")
	_ = interrupt.Register(IRQ_LPUART0, "LPUART0_IRQHandler")
	_ = interrupt.Register(IRQ_UART0_RX_TX, "UART0_RX_TX_IRQHandler")
	_ = interrupt.Register(IRQ_UART0_ERR, "UART0_ERR_IRQHandler")
	_ = interrupt.Register(IRQ_UART1_RX_TX, "UART1_RX_TX_IRQHandler")
	_ = interrupt.Register(IRQ_UART1_ERR, "UART1_ERR_IRQHandler")
	_ = interrupt.Register(IRQ_UART2_RX_TX, "UART2_RX_TX_IRQHandler")
	_ = interrupt.Register(IRQ_UART2_ERR, "UART2_ERR_IRQHandler")
	_ = interrupt.Register(IRQ_ADC0, "ADC0_IRQHandler")
	_ = interrupt.Register(IRQ_CMP0, "CMP0_IRQHandler")
	_ = interrupt.Register(IRQ_CMP1, "CMP1_IRQHandler")
	_ = interrupt.Register(IRQ_FTM0, "FTM0_IRQHandler")
	_ = interrupt.Register(IRQ_FTM1, "FTM1_IRQHandler")
	_ = interrupt.Register(IRQ_FTM2, "FTM2_IRQHandler")
	_ = interrupt.Register(IRQ_RTC, "RTC_IRQHandler")
	_ = interrupt.Register(IRQ_RTC_Seconds, "RTC_Seconds_IRQHandler")
	_ = interrupt.Register(IRQ_PIT0, "PIT0_IRQHandler")
	_ = interrupt.Register(IRQ_PIT1, "PIT1_IRQHandler")
	_ = interrupt.Register(IRQ_PIT2, "PIT2_IRQHandler")
	_ = interrupt.Register(IRQ_PIT3, "PIT3_IRQHandler")
	_ = interrupt.Register(IRQ_PDB0, "PDB0_IRQHandler")
	_ = interrupt.Register(IRQ_USB0, "USB0_IRQHandler")
	_ = interrupt.Register(IRQ_DAC0, "DAC0_IRQHandler")
	_ = interrupt.Register(IRQ_LPTMR0, "LPTMR0_IRQHandler")
	_ = interrupt.Register(IRQ_PORTA, "PORTA_IRQHandler")
	_ = interrupt.Register(IRQ_PORTB, "PORTB_IRQHandler")
	_ = interrupt.Register(IRQ_PORTC, "PORTC_IRQHandler")
	_ = interrupt.Register(IRQ_PORTD, "PORTD_IRQHandler")
	_ = interrupt.Register(IRQ_PORTE, "PORTE_IRQHandler")
	_ = interrupt.Register(IRQ_ADC1, "ADC1_IRQHandler")
)

// Peripherals.
var (
	FTFA_FlashConfig = (*FTFA_FlashConfig_Type)(unsafe.Pointer(uintptr(0x400)))   // Flash configuration field
	DMA              = (*DMA_Type)(unsafe.Pointer(uintptr(0x40008000)))           // Enhanced direct memory access controller
	FMC              = (*FMC_Type)(unsafe.Pointer(uintptr(0x4001f000)))           // Flash Memory Controller
	FTFA             = (*FTFA_Type)(unsafe.Pointer(uintptr(0x40020000)))          // Flash Memory Interface
	DMAMUX           = (*DMAMUX_Type)(unsafe.Pointer(uintptr(0x40021000)))        // DMA channel multiplexor
	ADC0             = (*ADC_Type)(unsafe.Pointer(uintptr(0x4003b000)))           // Analog-to-Digital Converter
	ADC1             = (*ADC_Type)(unsafe.Pointer(uintptr(0x40027000)))           // Analog-to-Digital Converter
	RNG              = (*RNG_Type)(unsafe.Pointer(uintptr(0x40029000)))           // Random Number Generator Accelerator
	LPUART0          = (*LPUART0_Type)(unsafe.Pointer(uintptr(0x4002a000)))       // Universal Asynchronous Receiver/Transmitter
	SPI0             = (*SPI_Type)(unsafe.Pointer(uintptr(0x4002c000)))           // Serial Peripheral Interface
	SPI1             = (*SPI_Type)(unsafe.Pointer(uintptr(0x4002d000)))           // Serial Peripheral Interface
	I2S0             = (*I2S0_Type)(unsafe.Pointer(uintptr(0x4002f000)))          // Inter-IC Sound / Synchronous Audio Interface
	CRC              = (*CRC_Type)(unsafe.Pointer(uintptr(0x40032000)))           // Cyclic Redundancy Check
	PDB0             = (*PDB0_Type)(unsafe.Pointer(uintptr(0x40036000)))          // Programmable Delay Block
	PIT              = (*PIT_Type)(unsafe.Pointer(uintptr(0x40037000)))           // Periodic Interrupt Timer
	FTM0             = (*FTM_Type)(unsafe.Pointer(uintptr(0x40038000)))           // FlexTimer Module
	FTM1             = (*FTM_Type)(unsafe.Pointer(uintptr(0x40039000)))           // FlexTimer Module
	FTM2             = (*FTM_Type)(unsafe.Pointer(uintptr(0x4003a000)))           // FlexTimer Module
	RTC              = (*RTC_Type)(unsafe.Pointer(uintptr(0x4003d000)))           // Secure Real Time Clock
	RFVBAT           = (*RFVBAT_Type)(unsafe.Pointer(uintptr(0x4003e000)))        // VBAT register file
	DAC0             = (*DAC0_Type)(unsafe.Pointer(uintptr(0x4003f000)))          // 12-Bit Digital-to-Analog Converter
	LPTMR0           = (*LPTMR0_Type)(unsafe.Pointer(uintptr(0x40040000)))        // Low Power Timer
	RFSYS            = (*RFSYS_Type)(unsafe.Pointer(uintptr(0x40041000)))         // System register file
	SIM              = (*SIM_Type)(unsafe.Pointer(uintptr(0x40047000)))           // System Integration Module
	PORTA            = (*PORT_Type)(unsafe.Pointer(uintptr(0x40049000)))          // Pin Control and Interrupts
	PORTB            = (*PORT_Type)(unsafe.Pointer(uintptr(0x4004a000)))          // Pin Control and Interrupts
	PORTC            = (*PORT_Type)(unsafe.Pointer(uintptr(0x4004b000)))          // Pin Control and Interrupts
	PORTD            = (*PORT_Type)(unsafe.Pointer(uintptr(0x4004c000)))          // Pin Control and Interrupts
	PORTE            = (*PORT_Type)(unsafe.Pointer(uintptr(0x4004d000)))          // Pin Control and Interrupts
	WDOG             = (*WDOG_Type)(unsafe.Pointer(uintptr(0x40052000)))          // Generation 2008 Watchdog Timer
	EWM              = (*EWM_Type)(unsafe.Pointer(uintptr(0x40061000)))           // External Watchdog Monitor
	MCG              = (*MCG_Type)(unsafe.Pointer(uintptr(0x40064000)))           // Multipurpose Clock Generator module
	OSC              = (*OSC_Type)(unsafe.Pointer(uintptr(0x40065000)))           // Oscillator
	I2C0             = (*I2C_Type)(unsafe.Pointer(uintptr(0x40066000)))           // Inter-Integrated Circuit
	I2C1             = (*I2C_Type)(unsafe.Pointer(uintptr(0x40067000)))           // Inter-Integrated Circuit
	UART0            = (*UART_Type)(unsafe.Pointer(uintptr(0x4006a000)))          // Serial Communication Interface
	UART1            = (*UART_Type)(unsafe.Pointer(uintptr(0x4006b000)))          // Serial Communication Interface
	UART2            = (*UART_Type)(unsafe.Pointer(uintptr(0x4006c000)))          // Serial Communication Interface
	USB0             = (*USB0_Type)(unsafe.Pointer(uintptr(0x40072000)))          // Universal Serial Bus, OTG Capable Controller
	CMP0             = (*CMP_Type)(unsafe.Pointer(uintptr(0x40073000)))           // High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)
	CMP1             = (*CMP_Type)(unsafe.Pointer(uintptr(0x40073008)))           // High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)
	VREF             = (*VREF_Type)(unsafe.Pointer(uintptr(0x40074000)))          // Voltage Reference
	LLWU             = (*LLWU_Type)(unsafe.Pointer(uintptr(0x4007c000)))          // Low leakage wakeup unit
	PMC              = (*PMC_Type)(unsafe.Pointer(uintptr(0x4007d000)))           // Power Management Controller
	SMC              = (*SMC_Type)(unsafe.Pointer(uintptr(0x4007e000)))           // System Mode Controller
	RCM              = (*RCM_Type)(unsafe.Pointer(uintptr(0x4007f000)))           // Reset Control Module
	GPIOA            = (*GPIO_Type)(unsafe.Pointer(uintptr(0x400ff000)))          // General Purpose Input/Output
	GPIOB            = (*GPIO_Type)(unsafe.Pointer(uintptr(0x400ff040)))          // General Purpose Input/Output
	GPIOC            = (*GPIO_Type)(unsafe.Pointer(uintptr(0x400ff080)))          // General Purpose Input/Output
	GPIOD            = (*GPIO_Type)(unsafe.Pointer(uintptr(0x400ff0c0)))          // General Purpose Input/Output
	GPIOE            = (*GPIO_Type)(unsafe.Pointer(uintptr(0x400ff100)))          // General Purpose Input/Output
	SystemControl    = (*SystemControl_Type)(unsafe.Pointer(uintptr(0xe000e000))) // System Control Block
	SysTick          = (*SysTick_Type)(unsafe.Pointer(uintptr(0xe000e010)))       // System timer
	NVIC             = (*NVIC_Type)(unsafe.Pointer(uintptr(0xe000e100)))          // Nested Vectored Interrupt Controller
	MCM              = (*MCM_Type)(unsafe.Pointer(uintptr(0xe0080000)))           // Core Platform Miscellaneous Control Module
)

// Flash configuration field
type FTFA_FlashConfig_Type struct {
	BACKKEY3 volatile.Register8 // 0x0
	BACKKEY2 volatile.Register8 // 0x1
	BACKKEY1 volatile.Register8 // 0x2
	BACKKEY0 volatile.Register8 // 0x3
	BACKKEY7 volatile.Register8 // 0x4
	BACKKEY6 volatile.Register8 // 0x5
	BACKKEY5 volatile.Register8 // 0x6
	BACKKEY4 volatile.Register8 // 0x7
	FPROT3   volatile.Register8 // 0x8
	FPROT2   volatile.Register8 // 0x9
	FPROT1   volatile.Register8 // 0xA
	FPROT0   volatile.Register8 // 0xB
	FSEC     volatile.Register8 // 0xC
	FOPT     volatile.Register8 // 0xD
}

// Enhanced direct memory access controller
type DMA_Type struct {
	CR                  volatile.Register32 // 0x0
	ES                  volatile.Register32 // 0x4
	_                   [4]byte
	ERQ                 volatile.Register32 // 0xC
	_                   [4]byte
	EEI                 volatile.Register32 // 0x14
	CEEI                volatile.Register8  // 0x18
	SEEI                volatile.Register8  // 0x19
	CERQ                volatile.Register8  // 0x1A
	SERQ                volatile.Register8  // 0x1B
	CDNE                volatile.Register8  // 0x1C
	SSRT                volatile.Register8  // 0x1D
	CERR                volatile.Register8  // 0x1E
	CINT                volatile.Register8  // 0x1F
	_                   [4]byte
	INT                 volatile.Register32 // 0x24
	_                   [4]byte
	ERR                 volatile.Register32 // 0x2C
	_                   [4]byte
	HRS                 volatile.Register32 // 0x34
	_                   [12]byte
	EARS                volatile.Register32 // 0x44
	_                   [184]byte
	DCHPRI3             volatile.Register8 // 0x100
	DCHPRI2             volatile.Register8 // 0x101
	DCHPRI1             volatile.Register8 // 0x102
	DCHPRI0             volatile.Register8 // 0x103
	DCHPRI7             volatile.Register8 // 0x104
	DCHPRI6             volatile.Register8 // 0x105
	DCHPRI5             volatile.Register8 // 0x106
	DCHPRI4             volatile.Register8 // 0x107
	DCHPRI11            volatile.Register8 // 0x108
	DCHPRI10            volatile.Register8 // 0x109
	DCHPRI9             volatile.Register8 // 0x10A
	DCHPRI8             volatile.Register8 // 0x10B
	DCHPRI15            volatile.Register8 // 0x10C
	DCHPRI14            volatile.Register8 // 0x10D
	DCHPRI13            volatile.Register8 // 0x10E
	DCHPRI12            volatile.Register8 // 0x10F
	_                   [3824]byte
	TCD0_SADDR          volatile.Register32 // 0x1000
	TCD0_SOFF           volatile.Register16 // 0x1004
	TCD0_ATTR           volatile.Register16 // 0x1006
	TCD0_NBYTES_MLNO    volatile.Register32 // 0x1008
	TCD0_SLAST          volatile.Register32 // 0x100C
	TCD0_DADDR          volatile.Register32 // 0x1010
	TCD0_DOFF           volatile.Register16 // 0x1014
	TCD0_CITER_ELINKNO  volatile.Register16 // 0x1016
	TCD0_DLASTSGA       volatile.Register32 // 0x1018
	TCD0_CSR            volatile.Register16 // 0x101C
	TCD0_BITER_ELINKNO  volatile.Register16 // 0x101E
	TCD1_SADDR          volatile.Register32 // 0x1020
	TCD1_SOFF           volatile.Register16 // 0x1024
	TCD1_ATTR           volatile.Register16 // 0x1026
	TCD1_NBYTES_MLNO    volatile.Register32 // 0x1028
	TCD1_SLAST          volatile.Register32 // 0x102C
	TCD1_DADDR          volatile.Register32 // 0x1030
	TCD1_DOFF           volatile.Register16 // 0x1034
	TCD1_CITER_ELINKNO  volatile.Register16 // 0x1036
	TCD1_DLASTSGA       volatile.Register32 // 0x1038
	TCD1_CSR            volatile.Register16 // 0x103C
	TCD1_BITER_ELINKNO  volatile.Register16 // 0x103E
	TCD2_SADDR          volatile.Register32 // 0x1040
	TCD2_SOFF           volatile.Register16 // 0x1044
	TCD2_ATTR           volatile.Register16 // 0x1046
	TCD2_NBYTES_MLNO    volatile.Register32 // 0x1048
	TCD2_SLAST          volatile.Register32 // 0x104C
	TCD2_DADDR          volatile.Register32 // 0x1050
	TCD2_DOFF           volatile.Register16 // 0x1054
	TCD2_CITER_ELINKNO  volatile.Register16 // 0x1056
	TCD2_DLASTSGA       volatile.Register32 // 0x1058
	TCD2_CSR            volatile.Register16 // 0x105C
	TCD2_BITER_ELINKNO  volatile.Register16 // 0x105E
	TCD3_SADDR          volatile.Register32 // 0x1060
	TCD3_SOFF           volatile.Register16 // 0x1064
	TCD3_ATTR           volatile.Register16 // 0x1066
	TCD3_NBYTES_MLNO    volatile.Register32 // 0x1068
	TCD3_SLAST          volatile.Register32 // 0x106C
	TCD3_DADDR          volatile.Register32 // 0x1070
	TCD3_DOFF           volatile.Register16 // 0x1074
	TCD3_CITER_ELINKNO  volatile.Register16 // 0x1076
	TCD3_DLASTSGA       volatile.Register32 // 0x1078
	TCD3_CSR            volatile.Register16 // 0x107C
	TCD3_BITER_ELINKNO  volatile.Register16 // 0x107E
	TCD4_SADDR          volatile.Register32 // 0x1080
	TCD4_SOFF           volatile.Register16 // 0x1084
	TCD4_ATTR           volatile.Register16 // 0x1086
	TCD4_NBYTES_MLNO    volatile.Register32 // 0x1088
	TCD4_SLAST          volatile.Register32 // 0x108C
	TCD4_DADDR          volatile.Register32 // 0x1090
	TCD4_DOFF           volatile.Register16 // 0x1094
	TCD4_CITER_ELINKNO  volatile.Register16 // 0x1096
	TCD4_DLASTSGA       volatile.Register32 // 0x1098
	TCD4_CSR            volatile.Register16 // 0x109C
	TCD4_BITER_ELINKNO  volatile.Register16 // 0x109E
	TCD5_SADDR          volatile.Register32 // 0x10A0
	TCD5_SOFF           volatile.Register16 // 0x10A4
	TCD5_ATTR           volatile.Register16 // 0x10A6
	TCD5_NBYTES_MLNO    volatile.Register32 // 0x10A8
	TCD5_SLAST          volatile.Register32 // 0x10AC
	TCD5_DADDR          volatile.Register32 // 0x10B0
	TCD5_DOFF           volatile.Register16 // 0x10B4
	TCD5_CITER_ELINKNO  volatile.Register16 // 0x10B6
	TCD5_DLASTSGA       volatile.Register32 // 0x10B8
	TCD5_CSR            volatile.Register16 // 0x10BC
	TCD5_BITER_ELINKNO  volatile.Register16 // 0x10BE
	TCD6_SADDR          volatile.Register32 // 0x10C0
	TCD6_SOFF           volatile.Register16 // 0x10C4
	TCD6_ATTR           volatile.Register16 // 0x10C6
	TCD6_NBYTES_MLNO    volatile.Register32 // 0x10C8
	TCD6_SLAST          volatile.Register32 // 0x10CC
	TCD6_DADDR          volatile.Register32 // 0x10D0
	TCD6_DOFF           volatile.Register16 // 0x10D4
	TCD6_CITER_ELINKNO  volatile.Register16 // 0x10D6
	TCD6_DLASTSGA       volatile.Register32 // 0x10D8
	TCD6_CSR            volatile.Register16 // 0x10DC
	TCD6_BITER_ELINKNO  volatile.Register16 // 0x10DE
	TCD7_SADDR          volatile.Register32 // 0x10E0
	TCD7_SOFF           volatile.Register16 // 0x10E4
	TCD7_ATTR           volatile.Register16 // 0x10E6
	TCD7_NBYTES_MLNO    volatile.Register32 // 0x10E8
	TCD7_SLAST          volatile.Register32 // 0x10EC
	TCD7_DADDR          volatile.Register32 // 0x10F0
	TCD7_DOFF           volatile.Register16 // 0x10F4
	TCD7_CITER_ELINKNO  volatile.Register16 // 0x10F6
	TCD7_DLASTSGA       volatile.Register32 // 0x10F8
	TCD7_CSR            volatile.Register16 // 0x10FC
	TCD7_BITER_ELINKNO  volatile.Register16 // 0x10FE
	TCD8_SADDR          volatile.Register32 // 0x1100
	TCD8_SOFF           volatile.Register16 // 0x1104
	TCD8_ATTR           volatile.Register16 // 0x1106
	TCD8_NBYTES_MLNO    volatile.Register32 // 0x1108
	TCD8_SLAST          volatile.Register32 // 0x110C
	TCD8_DADDR          volatile.Register32 // 0x1110
	TCD8_DOFF           volatile.Register16 // 0x1114
	TCD8_CITER_ELINKNO  volatile.Register16 // 0x1116
	TCD8_DLASTSGA       volatile.Register32 // 0x1118
	TCD8_CSR            volatile.Register16 // 0x111C
	TCD8_BITER_ELINKNO  volatile.Register16 // 0x111E
	TCD9_SADDR          volatile.Register32 // 0x1120
	TCD9_SOFF           volatile.Register16 // 0x1124
	TCD9_ATTR           volatile.Register16 // 0x1126
	TCD9_NBYTES_MLNO    volatile.Register32 // 0x1128
	TCD9_SLAST          volatile.Register32 // 0x112C
	TCD9_DADDR          volatile.Register32 // 0x1130
	TCD9_DOFF           volatile.Register16 // 0x1134
	TCD9_CITER_ELINKNO  volatile.Register16 // 0x1136
	TCD9_DLASTSGA       volatile.Register32 // 0x1138
	TCD9_CSR            volatile.Register16 // 0x113C
	TCD9_BITER_ELINKNO  volatile.Register16 // 0x113E
	TCD10_SADDR         volatile.Register32 // 0x1140
	TCD10_SOFF          volatile.Register16 // 0x1144
	TCD10_ATTR          volatile.Register16 // 0x1146
	TCD10_NBYTES_MLNO   volatile.Register32 // 0x1148
	TCD10_SLAST         volatile.Register32 // 0x114C
	TCD10_DADDR         volatile.Register32 // 0x1150
	TCD10_DOFF          volatile.Register16 // 0x1154
	TCD10_CITER_ELINKNO volatile.Register16 // 0x1156
	TCD10_DLASTSGA      volatile.Register32 // 0x1158
	TCD10_CSR           volatile.Register16 // 0x115C
	TCD10_BITER_ELINKNO volatile.Register16 // 0x115E
	TCD11_SADDR         volatile.Register32 // 0x1160
	TCD11_SOFF          volatile.Register16 // 0x1164
	TCD11_ATTR          volatile.Register16 // 0x1166
	TCD11_NBYTES_MLNO   volatile.Register32 // 0x1168
	TCD11_SLAST         volatile.Register32 // 0x116C
	TCD11_DADDR         volatile.Register32 // 0x1170
	TCD11_DOFF          volatile.Register16 // 0x1174
	TCD11_CITER_ELINKNO volatile.Register16 // 0x1176
	TCD11_DLASTSGA      volatile.Register32 // 0x1178
	TCD11_CSR           volatile.Register16 // 0x117C
	TCD11_BITER_ELINKNO volatile.Register16 // 0x117E
	TCD12_SADDR         volatile.Register32 // 0x1180
	TCD12_SOFF          volatile.Register16 // 0x1184
	TCD12_ATTR          volatile.Register16 // 0x1186
	TCD12_NBYTES_MLNO   volatile.Register32 // 0x1188
	TCD12_SLAST         volatile.Register32 // 0x118C
	TCD12_DADDR         volatile.Register32 // 0x1190
	TCD12_DOFF          volatile.Register16 // 0x1194
	TCD12_CITER_ELINKNO volatile.Register16 // 0x1196
	TCD12_DLASTSGA      volatile.Register32 // 0x1198
	TCD12_CSR           volatile.Register16 // 0x119C
	TCD12_BITER_ELINKNO volatile.Register16 // 0x119E
	TCD13_SADDR         volatile.Register32 // 0x11A0
	TCD13_SOFF          volatile.Register16 // 0x11A4
	TCD13_ATTR          volatile.Register16 // 0x11A6
	TCD13_NBYTES_MLNO   volatile.Register32 // 0x11A8
	TCD13_SLAST         volatile.Register32 // 0x11AC
	TCD13_DADDR         volatile.Register32 // 0x11B0
	TCD13_DOFF          volatile.Register16 // 0x11B4
	TCD13_CITER_ELINKNO volatile.Register16 // 0x11B6
	TCD13_DLASTSGA      volatile.Register32 // 0x11B8
	TCD13_CSR           volatile.Register16 // 0x11BC
	TCD13_BITER_ELINKNO volatile.Register16 // 0x11BE
	TCD14_SADDR         volatile.Register32 // 0x11C0
	TCD14_SOFF          volatile.Register16 // 0x11C4
	TCD14_ATTR          volatile.Register16 // 0x11C6
	TCD14_NBYTES_MLNO   volatile.Register32 // 0x11C8
	TCD14_SLAST         volatile.Register32 // 0x11CC
	TCD14_DADDR         volatile.Register32 // 0x11D0
	TCD14_DOFF          volatile.Register16 // 0x11D4
	TCD14_CITER_ELINKNO volatile.Register16 // 0x11D6
	TCD14_DLASTSGA      volatile.Register32 // 0x11D8
	TCD14_CSR           volatile.Register16 // 0x11DC
	TCD14_BITER_ELINKNO volatile.Register16 // 0x11DE
	TCD15_SADDR         volatile.Register32 // 0x11E0
	TCD15_SOFF          volatile.Register16 // 0x11E4
	TCD15_ATTR          volatile.Register16 // 0x11E6
	TCD15_NBYTES_MLNO   volatile.Register32 // 0x11E8
	TCD15_SLAST         volatile.Register32 // 0x11EC
	TCD15_DADDR         volatile.Register32 // 0x11F0
	TCD15_DOFF          volatile.Register16 // 0x11F4
	TCD15_CITER_ELINKNO volatile.Register16 // 0x11F6
	TCD15_DLASTSGA      volatile.Register32 // 0x11F8
	TCD15_CSR           volatile.Register16 // 0x11FC
	TCD15_BITER_ELINKNO volatile.Register16 // 0x11FE
}

// Flash Memory Controller
type FMC_Type struct {
	PFAPR     volatile.Register32 // 0x0
	PFB0CR    volatile.Register32 // 0x4
	PFB1CR    volatile.Register32 // 0x8
	_         [244]byte
	TAGVDW0S0 volatile.Register32 // 0x100
	TAGVDW0S1 volatile.Register32 // 0x104
	TAGVDW0S2 volatile.Register32 // 0x108
	TAGVDW0S3 volatile.Register32 // 0x10C
	TAGVDW0S4 volatile.Register32 // 0x110
	TAGVDW0S5 volatile.Register32 // 0x114
	TAGVDW0S6 volatile.Register32 // 0x118
	TAGVDW0S7 volatile.Register32 // 0x11C
	TAGVDW1S0 volatile.Register32 // 0x120
	TAGVDW1S1 volatile.Register32 // 0x124
	TAGVDW1S2 volatile.Register32 // 0x128
	TAGVDW1S3 volatile.Register32 // 0x12C
	TAGVDW1S4 volatile.Register32 // 0x130
	TAGVDW1S5 volatile.Register32 // 0x134
	TAGVDW1S6 volatile.Register32 // 0x138
	TAGVDW1S7 volatile.Register32 // 0x13C
	TAGVDW2S0 volatile.Register32 // 0x140
	TAGVDW2S1 volatile.Register32 // 0x144
	TAGVDW2S2 volatile.Register32 // 0x148
	TAGVDW2S3 volatile.Register32 // 0x14C
	TAGVDW2S4 volatile.Register32 // 0x150
	TAGVDW2S5 volatile.Register32 // 0x154
	TAGVDW2S6 volatile.Register32 // 0x158
	TAGVDW2S7 volatile.Register32 // 0x15C
	TAGVDW3S0 volatile.Register32 // 0x160
	TAGVDW3S1 volatile.Register32 // 0x164
	TAGVDW3S2 volatile.Register32 // 0x168
	TAGVDW3S3 volatile.Register32 // 0x16C
	TAGVDW3S4 volatile.Register32 // 0x170
	TAGVDW3S5 volatile.Register32 // 0x174
	TAGVDW3S6 volatile.Register32 // 0x178
	TAGVDW3S7 volatile.Register32 // 0x17C
	_         [128]byte
	DATAW0S0U volatile.Register32 // 0x200
	DATAW0S0L volatile.Register32 // 0x204
	DATAW0S1U volatile.Register32 // 0x208
	DATAW0S1L volatile.Register32 // 0x20C
	DATAW0S2U volatile.Register32 // 0x210
	DATAW0S2L volatile.Register32 // 0x214
	DATAW0S3U volatile.Register32 // 0x218
	DATAW0S3L volatile.Register32 // 0x21C
	DATAW0S4U volatile.Register32 // 0x220
	DATAW0S4L volatile.Register32 // 0x224
	DATAW0S5U volatile.Register32 // 0x228
	DATAW0S5L volatile.Register32 // 0x22C
	DATAW0S6U volatile.Register32 // 0x230
	DATAW0S6L volatile.Register32 // 0x234
	DATAW0S7U volatile.Register32 // 0x238
	DATAW0S7L volatile.Register32 // 0x23C
	DATAW1S0U volatile.Register32 // 0x240
	DATAW1S0L volatile.Register32 // 0x244
	DATAW1S1U volatile.Register32 // 0x248
	DATAW1S1L volatile.Register32 // 0x24C
	DATAW1S2U volatile.Register32 // 0x250
	DATAW1S2L volatile.Register32 // 0x254
	DATAW1S3U volatile.Register32 // 0x258
	DATAW1S3L volatile.Register32 // 0x25C
	DATAW1S4U volatile.Register32 // 0x260
	DATAW1S4L volatile.Register32 // 0x264
	DATAW1S5U volatile.Register32 // 0x268
	DATAW1S5L volatile.Register32 // 0x26C
	DATAW1S6U volatile.Register32 // 0x270
	DATAW1S6L volatile.Register32 // 0x274
	DATAW1S7U volatile.Register32 // 0x278
	DATAW1S7L volatile.Register32 // 0x27C
	DATAW2S0U volatile.Register32 // 0x280
	DATAW2S0L volatile.Register32 // 0x284
	DATAW2S1U volatile.Register32 // 0x288
	DATAW2S1L volatile.Register32 // 0x28C
	DATAW2S2U volatile.Register32 // 0x290
	DATAW2S2L volatile.Register32 // 0x294
	DATAW2S3U volatile.Register32 // 0x298
	DATAW2S3L volatile.Register32 // 0x29C
	DATAW2S4U volatile.Register32 // 0x2A0
	DATAW2S4L volatile.Register32 // 0x2A4
	DATAW2S5U volatile.Register32 // 0x2A8
	DATAW2S5L volatile.Register32 // 0x2AC
	DATAW2S6U volatile.Register32 // 0x2B0
	DATAW2S6L volatile.Register32 // 0x2B4
	DATAW2S7U volatile.Register32 // 0x2B8
	DATAW2S7L volatile.Register32 // 0x2BC
	DATAW3S0U volatile.Register32 // 0x2C0
	DATAW3S0L volatile.Register32 // 0x2C4
	DATAW3S1U volatile.Register32 // 0x2C8
	DATAW3S1L volatile.Register32 // 0x2CC
	DATAW3S2U volatile.Register32 // 0x2D0
	DATAW3S2L volatile.Register32 // 0x2D4
	DATAW3S3U volatile.Register32 // 0x2D8
	DATAW3S3L volatile.Register32 // 0x2DC
	DATAW3S4U volatile.Register32 // 0x2E0
	DATAW3S4L volatile.Register32 // 0x2E4
	DATAW3S5U volatile.Register32 // 0x2E8
	DATAW3S5L volatile.Register32 // 0x2EC
	DATAW3S6U volatile.Register32 // 0x2F0
	DATAW3S6L volatile.Register32 // 0x2F4
	DATAW3S7U volatile.Register32 // 0x2F8
	DATAW3S7L volatile.Register32 // 0x2FC
}

// Flash Memory Interface
type FTFA_Type struct {
	FSTAT  volatile.Register8 // 0x0
	FCNFG  volatile.Register8 // 0x1
	FSEC   volatile.Register8 // 0x2
	FOPT   volatile.Register8 // 0x3
	FCCOB3 volatile.Register8 // 0x4
	FCCOB2 volatile.Register8 // 0x5
	FCCOB1 volatile.Register8 // 0x6
	FCCOB0 volatile.Register8 // 0x7
	FCCOB7 volatile.Register8 // 0x8
	FCCOB6 volatile.Register8 // 0x9
	FCCOB5 volatile.Register8 // 0xA
	FCCOB4 volatile.Register8 // 0xB
	FCCOBB volatile.Register8 // 0xC
	FCCOBA volatile.Register8 // 0xD
	FCCOB9 volatile.Register8 // 0xE
	FCCOB8 volatile.Register8 // 0xF
	FPROT3 volatile.Register8 // 0x10
	FPROT2 volatile.Register8 // 0x11
	FPROT1 volatile.Register8 // 0x12
	FPROT0 volatile.Register8 // 0x13
	_      [4]byte
	XACCH3 volatile.Register8 // 0x18
	XACCH2 volatile.Register8 // 0x19
	XACCH1 volatile.Register8 // 0x1A
	XACCH0 volatile.Register8 // 0x1B
	XACCL3 volatile.Register8 // 0x1C
	XACCL2 volatile.Register8 // 0x1D
	XACCL1 volatile.Register8 // 0x1E
	XACCL0 volatile.Register8 // 0x1F
	SACCH3 volatile.Register8 // 0x20
	SACCH2 volatile.Register8 // 0x21
	SACCH1 volatile.Register8 // 0x22
	SACCH0 volatile.Register8 // 0x23
	SACCL3 volatile.Register8 // 0x24
	SACCL2 volatile.Register8 // 0x25
	SACCL1 volatile.Register8 // 0x26
	SACCL0 volatile.Register8 // 0x27
	FACSS  volatile.Register8 // 0x28
	_      [2]byte
	FACSN  volatile.Register8 // 0x2B
}

// DMA channel multiplexor
type DMAMUX_Type struct {
	CHCFG0  volatile.Register8 // 0x0
	CHCFG1  volatile.Register8 // 0x1
	CHCFG2  volatile.Register8 // 0x2
	CHCFG3  volatile.Register8 // 0x3
	CHCFG4  volatile.Register8 // 0x4
	CHCFG5  volatile.Register8 // 0x5
	CHCFG6  volatile.Register8 // 0x6
	CHCFG7  volatile.Register8 // 0x7
	CHCFG8  volatile.Register8 // 0x8
	CHCFG9  volatile.Register8 // 0x9
	CHCFG10 volatile.Register8 // 0xA
	CHCFG11 volatile.Register8 // 0xB
	CHCFG12 volatile.Register8 // 0xC
	CHCFG13 volatile.Register8 // 0xD
	CHCFG14 volatile.Register8 // 0xE
	CHCFG15 volatile.Register8 // 0xF
}

// Analog-to-Digital Converter
type ADC_Type struct {
	SC1A volatile.Register32 // 0x0
	SC1B volatile.Register32 // 0x4
	CFG1 volatile.Register32 // 0x8
	CFG2 volatile.Register32 // 0xC
	RA   volatile.Register32 // 0x10
	RB   volatile.Register32 // 0x14
	CV1  volatile.Register32 // 0x18
	CV2  volatile.Register32 // 0x1C
	SC2  volatile.Register32 // 0x20
	SC3  volatile.Register32 // 0x24
	OFS  volatile.Register32 // 0x28
	PG   volatile.Register32 // 0x2C
	MG   volatile.Register32 // 0x30
	CLPD volatile.Register32 // 0x34
	CLPS volatile.Register32 // 0x38
	CLP4 volatile.Register32 // 0x3C
	CLP3 volatile.Register32 // 0x40
	CLP2 volatile.Register32 // 0x44
	CLP1 volatile.Register32 // 0x48
	CLP0 volatile.Register32 // 0x4C
	_    [4]byte
	CLMD volatile.Register32 // 0x54
	CLMS volatile.Register32 // 0x58
	CLM4 volatile.Register32 // 0x5C
	CLM3 volatile.Register32 // 0x60
	CLM2 volatile.Register32 // 0x64
	CLM1 volatile.Register32 // 0x68
	CLM0 volatile.Register32 // 0x6C
}

// Random Number Generator Accelerator
type RNG_Type struct {
	CR volatile.Register32 // 0x0
	SR volatile.Register32 // 0x4
	ER volatile.Register32 // 0x8
	OR volatile.Register32 // 0xC
}

// Universal Asynchronous Receiver/Transmitter
type LPUART0_Type struct {
	BAUD  volatile.Register32 // 0x0
	STAT  volatile.Register32 // 0x4
	CTRL  volatile.Register32 // 0x8
	DATA  volatile.Register32 // 0xC
	MATCH volatile.Register32 // 0x10
	MODIR volatile.Register32 // 0x14
}

// Serial Peripheral Interface
type SPI_Type struct {
	MCR   volatile.Register32 // 0x0
	_     [4]byte
	TCR   volatile.Register32 // 0x8
	CTAR0 volatile.Register32 // 0xC
	CTAR1 volatile.Register32 // 0x10
	_     [24]byte
	SR    volatile.Register32 // 0x2C
	RSER  volatile.Register32 // 0x30
	PUSHR volatile.Register32 // 0x34
	POPR  volatile.Register32 // 0x38
	TXFR0 volatile.Register32 // 0x3C
	TXFR1 volatile.Register32 // 0x40
	TXFR2 volatile.Register32 // 0x44
	TXFR3 volatile.Register32 // 0x48
	_     [48]byte
	RXFR0 volatile.Register32 // 0x7C
	RXFR1 volatile.Register32 // 0x80
	RXFR2 volatile.Register32 // 0x84
	RXFR3 volatile.Register32 // 0x88
}

// Inter-IC Sound / Synchronous Audio Interface
type I2S0_Type struct {
	TCSR volatile.Register32 // 0x0
	TCR1 volatile.Register32 // 0x4
	TCR2 volatile.Register32 // 0x8
	TCR3 volatile.Register32 // 0xC
	TCR4 volatile.Register32 // 0x10
	TCR5 volatile.Register32 // 0x14
	_    [8]byte
	TDR  volatile.Register32 // 0x20
	_    [28]byte
	TFR  volatile.Register32 // 0x40
	_    [28]byte
	TMR  volatile.Register32 // 0x60
	_    [28]byte
	RCSR volatile.Register32 // 0x80
	RCR1 volatile.Register32 // 0x84
	RCR2 volatile.Register32 // 0x88
	RCR3 volatile.Register32 // 0x8C
	RCR4 volatile.Register32 // 0x90
	RCR5 volatile.Register32 // 0x94
	_    [8]byte
	RDR  volatile.Register32 // 0xA0
	_    [28]byte
	RFR  volatile.Register32 // 0xC0
	_    [28]byte
	RMR  volatile.Register32 // 0xE0
	_    [28]byte
	MCR  volatile.Register32 // 0x100
	MDR  volatile.Register32 // 0x104
}

// Cyclic Redundancy Check
type CRC_Type struct {
	DATA  volatile.Register32 // 0x0
	GPOLY volatile.Register32 // 0x4
	CTRL  volatile.Register32 // 0x8
}

// Programmable Delay Block
type PDB0_Type struct {
	SC      volatile.Register32 // 0x0
	MOD     volatile.Register32 // 0x4
	CNT     volatile.Register32 // 0x8
	IDLY    volatile.Register32 // 0xC
	CH0C1   volatile.Register32 // 0x10
	CH0S    volatile.Register32 // 0x14
	CH0DLY0 volatile.Register32 // 0x18
	CH0DLY1 volatile.Register32 // 0x1C
	_       [24]byte
	CH1C1   volatile.Register32 // 0x38
	CH1S    volatile.Register32 // 0x3C
	CH1DLY0 volatile.Register32 // 0x40
	CH1DLY1 volatile.Register32 // 0x44
	_       [264]byte
	DACINTC volatile.Register32 // 0x150
	DACINT  volatile.Register32 // 0x154
	_       [56]byte
	POEN    volatile.Register32 // 0x190
	PO0DLY  volatile.Register32 // 0x194
	PO1DLY  volatile.Register32 // 0x198
}

// Periodic Interrupt Timer
type PIT_Type struct {
	MCR    volatile.Register32 // 0x0
	_      [252]byte
	LDVAL0 volatile.Register32 // 0x100
	CVAL0  volatile.Register32 // 0x104
	TCTRL0 volatile.Register32 // 0x108
	TFLG0  volatile.Register32 // 0x10C
	LDVAL1 volatile.Register32 // 0x110
	CVAL1  volatile.Register32 // 0x114
	TCTRL1 volatile.Register32 // 0x118
	TFLG1  volatile.Register32 // 0x11C
	LDVAL2 volatile.Register32 // 0x120
	CVAL2  volatile.Register32 // 0x124
	TCTRL2 volatile.Register32 // 0x128
	TFLG2  volatile.Register32 // 0x12C
	LDVAL3 volatile.Register32 // 0x130
	CVAL3  volatile.Register32 // 0x134
	TCTRL3 volatile.Register32 // 0x138
	TFLG3  volatile.Register32 // 0x13C
}

// FlexTimer Module
type FTM_Type struct {
	SC       volatile.Register32 // 0x0
	CNT      volatile.Register32 // 0x4
	MOD      volatile.Register32 // 0x8
	C0SC     volatile.Register32 // 0xC
	C0V      volatile.Register32 // 0x10
	C1SC     volatile.Register32 // 0x14
	C1V      volatile.Register32 // 0x18
	C2SC     volatile.Register32 // 0x1C
	C2V      volatile.Register32 // 0x20
	C3SC     volatile.Register32 // 0x24
	C3V      volatile.Register32 // 0x28
	C4SC     volatile.Register32 // 0x2C
	C4V      volatile.Register32 // 0x30
	C5SC     volatile.Register32 // 0x34
	C5V      volatile.Register32 // 0x38
	C6SC     volatile.Register32 // 0x3C
	C6V      volatile.Register32 // 0x40
	C7SC     volatile.Register32 // 0x44
	C7V      volatile.Register32 // 0x48
	CNTIN    volatile.Register32 // 0x4C
	STATUS   volatile.Register32 // 0x50
	MODE     volatile.Register32 // 0x54
	SYNC     volatile.Register32 // 0x58
	OUTINIT  volatile.Register32 // 0x5C
	OUTMASK  volatile.Register32 // 0x60
	COMBINE  volatile.Register32 // 0x64
	DEADTIME volatile.Register32 // 0x68
	EXTTRIG  volatile.Register32 // 0x6C
	POL      volatile.Register32 // 0x70
	FMS      volatile.Register32 // 0x74
	FILTER   volatile.Register32 // 0x78
	FLTCTRL  volatile.Register32 // 0x7C
	QDCTRL   volatile.Register32 // 0x80
	CONF     volatile.Register32 // 0x84
	FLTPOL   volatile.Register32 // 0x88
	SYNCONF  volatile.Register32 // 0x8C
	INVCTRL  volatile.Register32 // 0x90
	SWOCTRL  volatile.Register32 // 0x94
	PWMLOAD  volatile.Register32 // 0x98
}

// Secure Real Time Clock
type RTC_Type struct {
	TSR volatile.Register32 // 0x0
	TPR volatile.Register32 // 0x4
	TAR volatile.Register32 // 0x8
	TCR volatile.Register32 // 0xC
	CR  volatile.Register32 // 0x10
	SR  volatile.Register32 // 0x14
	LR  volatile.Register32 // 0x18
	IER volatile.Register32 // 0x1C
	_   [2016]byte
	WAR volatile.Register32 // 0x800
	RAR volatile.Register32 // 0x804
}

// VBAT register file
type RFVBAT_Type struct {
	REG0 volatile.Register32 // 0x0
	REG1 volatile.Register32 // 0x4
	REG2 volatile.Register32 // 0x8
	REG3 volatile.Register32 // 0xC
	REG4 volatile.Register32 // 0x10
	REG5 volatile.Register32 // 0x14
	REG6 volatile.Register32 // 0x18
	REG7 volatile.Register32 // 0x1C
}

// 12-Bit Digital-to-Analog Converter
type DAC0_Type struct {
	DAT0L  volatile.Register8 // 0x0
	DAT0H  volatile.Register8 // 0x1
	DAT1L  volatile.Register8 // 0x2
	DAT1H  volatile.Register8 // 0x3
	DAT2L  volatile.Register8 // 0x4
	DAT2H  volatile.Register8 // 0x5
	DAT3L  volatile.Register8 // 0x6
	DAT3H  volatile.Register8 // 0x7
	DAT4L  volatile.Register8 // 0x8
	DAT4H  volatile.Register8 // 0x9
	DAT5L  volatile.Register8 // 0xA
	DAT5H  volatile.Register8 // 0xB
	DAT6L  volatile.Register8 // 0xC
	DAT6H  volatile.Register8 // 0xD
	DAT7L  volatile.Register8 // 0xE
	DAT7H  volatile.Register8 // 0xF
	DAT8L  volatile.Register8 // 0x10
	DAT8H  volatile.Register8 // 0x11
	DAT9L  volatile.Register8 // 0x12
	DAT9H  volatile.Register8 // 0x13
	DAT10L volatile.Register8 // 0x14
	DAT10H volatile.Register8 // 0x15
	DAT11L volatile.Register8 // 0x16
	DAT11H volatile.Register8 // 0x17
	DAT12L volatile.Register8 // 0x18
	DAT12H volatile.Register8 // 0x19
	DAT13L volatile.Register8 // 0x1A
	DAT13H volatile.Register8 // 0x1B
	DAT14L volatile.Register8 // 0x1C
	DAT14H volatile.Register8 // 0x1D
	DAT15L volatile.Register8 // 0x1E
	DAT15H volatile.Register8 // 0x1F
	SR     volatile.Register8 // 0x20
	C0     volatile.Register8 // 0x21
	C1     volatile.Register8 // 0x22
	C2     volatile.Register8 // 0x23
}

// Low Power Timer
type LPTMR0_Type struct {
	CSR volatile.Register32 // 0x0
	PSR volatile.Register32 // 0x4
	CMR volatile.Register32 // 0x8
	CNR volatile.Register32 // 0xC
}

// System register file
type RFSYS_Type struct {
	REG0 volatile.Register32 // 0x0
	REG1 volatile.Register32 // 0x4
	REG2 volatile.Register32 // 0x8
	REG3 volatile.Register32 // 0xC
	REG4 volatile.Register32 // 0x10
	REG5 volatile.Register32 // 0x14
	REG6 volatile.Register32 // 0x18
	REG7 volatile.Register32 // 0x1C
}

// System Integration Module
type SIM_Type struct {
	SOPT1    volatile.Register32 // 0x0
	SOPT1CFG volatile.Register32 // 0x4
	_        [4092]byte
	SOPT2    volatile.Register32 // 0x1004
	_        [4]byte
	SOPT4    volatile.Register32 // 0x100C
	SOPT5    volatile.Register32 // 0x1010
	_        [4]byte
	SOPT7    volatile.Register32 // 0x1018
	SOPT8    volatile.Register32 // 0x101C
	_        [4]byte
	SDID     volatile.Register32 // 0x1024
	_        [12]byte
	SCGC4    volatile.Register32 // 0x1034
	SCGC5    volatile.Register32 // 0x1038
	SCGC6    volatile.Register32 // 0x103C
	SCGC7    volatile.Register32 // 0x1040
	CLKDIV1  volatile.Register32 // 0x1044
	CLKDIV2  volatile.Register32 // 0x1048
	FCFG1    volatile.Register32 // 0x104C
	FCFG2    volatile.Register32 // 0x1050
	UIDH     volatile.Register32 // 0x1054
	UIDMH    volatile.Register32 // 0x1058
	UIDML    volatile.Register32 // 0x105C
	UIDL     volatile.Register32 // 0x1060
}

// Pin Control and Interrupts
type PORT_Type struct {
	PCR0  volatile.Register32 // 0x0
	PCR1  volatile.Register32 // 0x4
	PCR2  volatile.Register32 // 0x8
	PCR3  volatile.Register32 // 0xC
	PCR4  volatile.Register32 // 0x10
	PCR5  volatile.Register32 // 0x14
	PCR6  volatile.Register32 // 0x18
	PCR7  volatile.Register32 // 0x1C
	PCR8  volatile.Register32 // 0x20
	PCR9  volatile.Register32 // 0x24
	PCR10 volatile.Register32 // 0x28
	PCR11 volatile.Register32 // 0x2C
	PCR12 volatile.Register32 // 0x30
	PCR13 volatile.Register32 // 0x34
	PCR14 volatile.Register32 // 0x38
	PCR15 volatile.Register32 // 0x3C
	PCR16 volatile.Register32 // 0x40
	PCR17 volatile.Register32 // 0x44
	PCR18 volatile.Register32 // 0x48
	PCR19 volatile.Register32 // 0x4C
	PCR20 volatile.Register32 // 0x50
	PCR21 volatile.Register32 // 0x54
	PCR22 volatile.Register32 // 0x58
	PCR23 volatile.Register32 // 0x5C
	PCR24 volatile.Register32 // 0x60
	PCR25 volatile.Register32 // 0x64
	PCR26 volatile.Register32 // 0x68
	PCR27 volatile.Register32 // 0x6C
	PCR28 volatile.Register32 // 0x70
	PCR29 volatile.Register32 // 0x74
	PCR30 volatile.Register32 // 0x78
	PCR31 volatile.Register32 // 0x7C
	GPCLR volatile.Register32 // 0x80
	GPCHR volatile.Register32 // 0x84
	_     [24]byte
	ISFR  volatile.Register32 // 0xA0
}

// Generation 2008 Watchdog Timer
type WDOG_Type struct {
	STCTRLH volatile.Register16 // 0x0
	STCTRLL volatile.Register16 // 0x2
	TOVALH  volatile.Register16 // 0x4
	TOVALL  volatile.Register16 // 0x6
	WINH    volatile.Register16 // 0x8
	WINL    volatile.Register16 // 0xA
	REFRESH volatile.Register16 // 0xC
	UNLOCK  volatile.Register16 // 0xE
	TMROUTH volatile.Register16 // 0x10
	TMROUTL volatile.Register16 // 0x12
	RSTCNT  volatile.Register16 // 0x14
	PRESC   volatile.Register16 // 0x16
}

// External Watchdog Monitor
type EWM_Type struct {
	CTRL         volatile.Register8 // 0x0
	SERV         volatile.Register8 // 0x1
	CMPL         volatile.Register8 // 0x2
	CMPH         volatile.Register8 // 0x3
	_            byte
	CLKPRESCALER volatile.Register8 // 0x5
}

// Multipurpose Clock Generator module
type MCG_Type struct {
	C1    volatile.Register8 // 0x0
	C2    volatile.Register8 // 0x1
	C3    volatile.Register8 // 0x2
	C4    volatile.Register8 // 0x3
	C5    volatile.Register8 // 0x4
	C6    volatile.Register8 // 0x5
	S     volatile.Register8 // 0x6
	_     byte
	SC    volatile.Register8 // 0x8
	_     byte
	ATCVH volatile.Register8 // 0xA
	ATCVL volatile.Register8 // 0xB
	C7    volatile.Register8 // 0xC
	C8    volatile.Register8 // 0xD
}

// Oscillator
type OSC_Type struct {
	CR  volatile.Register8 // 0x0
	_   byte
	DIV volatile.Register8 // 0x2
}

// Inter-Integrated Circuit
type I2C_Type struct {
	A1   volatile.Register8 // 0x0
	F    volatile.Register8 // 0x1
	C1   volatile.Register8 // 0x2
	S    volatile.Register8 // 0x3
	D    volatile.Register8 // 0x4
	C2   volatile.Register8 // 0x5
	FLT  volatile.Register8 // 0x6
	RA   volatile.Register8 // 0x7
	SMB  volatile.Register8 // 0x8
	A2   volatile.Register8 // 0x9
	SLTH volatile.Register8 // 0xA
	SLTL volatile.Register8 // 0xB
}

// Serial Communication Interface
type UART_Type struct {
	BDH        volatile.Register8 // 0x0
	BDL        volatile.Register8 // 0x1
	C1         volatile.Register8 // 0x2
	C2         volatile.Register8 // 0x3
	S1         volatile.Register8 // 0x4
	S2         volatile.Register8 // 0x5
	C3         volatile.Register8 // 0x6
	D          volatile.Register8 // 0x7
	MA1        volatile.Register8 // 0x8
	MA2        volatile.Register8 // 0x9
	C4         volatile.Register8 // 0xA
	C5         volatile.Register8 // 0xB
	ED         volatile.Register8 // 0xC
	MODEM      volatile.Register8 // 0xD
	IR         volatile.Register8 // 0xE
	_          byte
	PFIFO      volatile.Register8 // 0x10
	CFIFO      volatile.Register8 // 0x11
	SFIFO      volatile.Register8 // 0x12
	TWFIFO     volatile.Register8 // 0x13
	TCFIFO     volatile.Register8 // 0x14
	RWFIFO     volatile.Register8 // 0x15
	RCFIFO     volatile.Register8 // 0x16
	_          byte
	C7816      volatile.Register8 // 0x18
	IE7816     volatile.Register8 // 0x19
	IS7816     volatile.Register8 // 0x1A
	WP7816     volatile.Register8 // 0x1B
	WN7816     volatile.Register8 // 0x1C
	WF7816     volatile.Register8 // 0x1D
	ET7816     volatile.Register8 // 0x1E
	TL7816     volatile.Register8 // 0x1F
	_          [26]byte
	AP7816A_T0 volatile.Register8 // 0x3A
	AP7816B_T0 volatile.Register8 // 0x3B
	WP7816A_T0 volatile.Register8 // 0x3C
	WP7816B_T0 volatile.Register8 // 0x3D
	WGP7816_T1 volatile.Register8 // 0x3E
	WP7816C_T1 volatile.Register8 // 0x3F
}

// Universal Serial Bus, OTG Capable Controller
type USB0_Type struct {
	PERID                  volatile.Register8 // 0x0
	_                      [3]byte
	IDCOMP                 volatile.Register8 // 0x4
	_                      [3]byte
	REV                    volatile.Register8 // 0x8
	_                      [3]byte
	ADDINFO                volatile.Register8 // 0xC
	_                      [3]byte
	OTGISTAT               volatile.Register8 // 0x10
	_                      [3]byte
	OTGICR                 volatile.Register8 // 0x14
	_                      [3]byte
	OTGSTAT                volatile.Register8 // 0x18
	_                      [3]byte
	OTGCTL                 volatile.Register8 // 0x1C
	_                      [99]byte
	ISTAT                  volatile.Register8 // 0x80
	_                      [3]byte
	INTEN                  volatile.Register8 // 0x84
	_                      [3]byte
	ERRSTAT                volatile.Register8 // 0x88
	_                      [3]byte
	ERREN                  volatile.Register8 // 0x8C
	_                      [3]byte
	STAT                   volatile.Register8 // 0x90
	_                      [3]byte
	CTL                    volatile.Register8 // 0x94
	_                      [3]byte
	ADDR                   volatile.Register8 // 0x98
	_                      [3]byte
	BDTPAGE1               volatile.Register8 // 0x9C
	_                      [3]byte
	FRMNUML                volatile.Register8 // 0xA0
	_                      [3]byte
	FRMNUMH                volatile.Register8 // 0xA4
	_                      [3]byte
	TOKEN                  volatile.Register8 // 0xA8
	_                      [3]byte
	SOFTHLD                volatile.Register8 // 0xAC
	_                      [3]byte
	BDTPAGE2               volatile.Register8 // 0xB0
	_                      [3]byte
	BDTPAGE3               volatile.Register8 // 0xB4
	_                      [11]byte
	ENDPT0                 volatile.Register8 // 0xC0
	_                      [3]byte
	ENDPT1                 volatile.Register8 // 0xC4
	_                      [3]byte
	ENDPT2                 volatile.Register8 // 0xC8
	_                      [3]byte
	ENDPT3                 volatile.Register8 // 0xCC
	_                      [3]byte
	ENDPT4                 volatile.Register8 // 0xD0
	_                      [3]byte
	ENDPT5                 volatile.Register8 // 0xD4
	_                      [3]byte
	ENDPT6                 volatile.Register8 // 0xD8
	_                      [3]byte
	ENDPT7                 volatile.Register8 // 0xDC
	_                      [3]byte
	ENDPT8                 volatile.Register8 // 0xE0
	_                      [3]byte
	ENDPT9                 volatile.Register8 // 0xE4
	_                      [3]byte
	ENDPT10                volatile.Register8 // 0xE8
	_                      [3]byte
	ENDPT11                volatile.Register8 // 0xEC
	_                      [3]byte
	ENDPT12                volatile.Register8 // 0xF0
	_                      [3]byte
	ENDPT13                volatile.Register8 // 0xF4
	_                      [3]byte
	ENDPT14                volatile.Register8 // 0xF8
	_                      [3]byte
	ENDPT15                volatile.Register8 // 0xFC
	_                      [3]byte
	USBCTRL                volatile.Register8 // 0x100
	_                      [3]byte
	OBSERVE                volatile.Register8 // 0x104
	_                      [3]byte
	CONTROL                volatile.Register8 // 0x108
	_                      [3]byte
	USBTRC0                volatile.Register8 // 0x10C
	_                      [7]byte
	USBFRMADJUST           volatile.Register8 // 0x114
	_                      [43]byte
	CLK_RECOVER_CTRL       volatile.Register8 // 0x140
	_                      [3]byte
	CLK_RECOVER_IRC_EN     volatile.Register8 // 0x144
	_                      [23]byte
	CLK_RECOVER_INT_STATUS volatile.Register8 // 0x15C
}

// High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)
type CMP_Type struct {
	CR0   volatile.Register8 // 0x0
	CR1   volatile.Register8 // 0x1
	FPR   volatile.Register8 // 0x2
	SCR   volatile.Register8 // 0x3
	DACCR volatile.Register8 // 0x4
	MUXCR volatile.Register8 // 0x5
}

// Voltage Reference
type VREF_Type struct {
	TRM volatile.Register8 // 0x0
	SC  volatile.Register8 // 0x1
}

// Low leakage wakeup unit
type LLWU_Type struct {
	PE1   volatile.Register8 // 0x0
	PE2   volatile.Register8 // 0x1
	PE3   volatile.Register8 // 0x2
	PE4   volatile.Register8 // 0x3
	ME    volatile.Register8 // 0x4
	F1    volatile.Register8 // 0x5
	F2    volatile.Register8 // 0x6
	F3    volatile.Register8 // 0x7
	FILT1 volatile.Register8 // 0x8
	FILT2 volatile.Register8 // 0x9
}

// Power Management Controller
type PMC_Type struct {
	LVDSC1 volatile.Register8 // 0x0
	LVDSC2 volatile.Register8 // 0x1
	REGSC  volatile.Register8 // 0x2
}

// System Mode Controller
type SMC_Type struct {
	PMPROT   volatile.Register8 // 0x0
	PMCTRL   volatile.Register8 // 0x1
	STOPCTRL volatile.Register8 // 0x2
	PMSTAT   volatile.Register8 // 0x3
}

// Reset Control Module
type RCM_Type struct {
	SRS0  volatile.Register8 // 0x0
	SRS1  volatile.Register8 // 0x1
	_     [2]byte
	RPFC  volatile.Register8 // 0x4
	RPFW  volatile.Register8 // 0x5
	_     byte
	MR    volatile.Register8 // 0x7
	SSRS0 volatile.Register8 // 0x8
	SSRS1 volatile.Register8 // 0x9
}

// General Purpose Input/Output
type GPIO_Type struct {
	PDOR volatile.Register32 // 0x0
	PSOR volatile.Register32 // 0x4
	PCOR volatile.Register32 // 0x8
	PTOR volatile.Register32 // 0xC
	PDIR volatile.Register32 // 0x10
	PDDR volatile.Register32 // 0x14
}

// System Control Block
type SystemControl_Type struct {
	_      [8]byte
	ACTLR  volatile.Register32 // 0x8
	_      [3316]byte
	CPUID  volatile.Register32 // 0xD00
	ICSR   volatile.Register32 // 0xD04
	VTOR   volatile.Register32 // 0xD08
	AIRCR  volatile.Register32 // 0xD0C
	SCR    volatile.Register32 // 0xD10
	CCR    volatile.Register32 // 0xD14
	SHPR1  volatile.Register32 // 0xD18
	SHPR2  volatile.Register32 // 0xD1C
	SHPR3  volatile.Register32 // 0xD20
	SHCSR  volatile.Register32 // 0xD24
	CFSR   volatile.Register32 // 0xD28
	HFSR   volatile.Register32 // 0xD2C
	DFSR   volatile.Register32 // 0xD30
	MMFAR  volatile.Register32 // 0xD34
	BFAR   volatile.Register32 // 0xD38
	AFSR   volatile.Register32 // 0xD3C
	_      [72]byte
	CPACR  volatile.Register32 // 0xD88
	_      [424]byte
	FPCCR  volatile.Register32 // 0xF34
	FPCAR  volatile.Register32 // 0xF38
	FPDSCR volatile.Register32 // 0xF3C
}

// System timer
type SysTick_Type struct {
	CSR   volatile.Register32 // 0x0
	RVR   volatile.Register32 // 0x4
	CVR   volatile.Register32 // 0x8
	CALIB volatile.Register32 // 0xC
}

// Nested Vectored Interrupt Controller
type NVIC_Type struct {
	NVICISER0 volatile.Register32 // 0x0
	NVICISER1 volatile.Register32 // 0x4
	NVICISER2 volatile.Register32 // 0x8
	NVICISER3 volatile.Register32 // 0xC
	_         [112]byte
	NVICICER0 volatile.Register32 // 0x80
	NVICICER1 volatile.Register32 // 0x84
	NVICICER2 volatile.Register32 // 0x88
	NVICICER3 volatile.Register32 // 0x8C
	_         [112]byte
	NVICISPR0 volatile.Register32 // 0x100
	NVICISPR1 volatile.Register32 // 0x104
	NVICISPR2 volatile.Register32 // 0x108
	NVICISPR3 volatile.Register32 // 0x10C
	_         [112]byte
	NVICICPR0 volatile.Register32 // 0x180
	NVICICPR1 volatile.Register32 // 0x184
	NVICICPR2 volatile.Register32 // 0x188
	NVICICPR3 volatile.Register32 // 0x18C
	_         [112]byte
	NVICIABR0 volatile.Register32 // 0x200
	NVICIABR1 volatile.Register32 // 0x204
	NVICIABR2 volatile.Register32 // 0x208
	NVICIABR3 volatile.Register32 // 0x20C
	_         [240]byte
	NVICIP0   volatile.Register8 // 0x300
	NVICIP1   volatile.Register8 // 0x301
	NVICIP2   volatile.Register8 // 0x302
	NVICIP3   volatile.Register8 // 0x303
	NVICIP4   volatile.Register8 // 0x304
	NVICIP5   volatile.Register8 // 0x305
	NVICIP6   volatile.Register8 // 0x306
	NVICIP7   volatile.Register8 // 0x307
	NVICIP8   volatile.Register8 // 0x308
	NVICIP9   volatile.Register8 // 0x309
	NVICIP10  volatile.Register8 // 0x30A
	NVICIP11  volatile.Register8 // 0x30B
	NVICIP12  volatile.Register8 // 0x30C
	NVICIP13  volatile.Register8 // 0x30D
	NVICIP14  volatile.Register8 // 0x30E
	NVICIP15  volatile.Register8 // 0x30F
	NVICIP16  volatile.Register8 // 0x310
	NVICIP17  volatile.Register8 // 0x311
	NVICIP18  volatile.Register8 // 0x312
	NVICIP19  volatile.Register8 // 0x313
	NVICIP20  volatile.Register8 // 0x314
	NVICIP21  volatile.Register8 // 0x315
	NVICIP22  volatile.Register8 // 0x316
	NVICIP23  volatile.Register8 // 0x317
	NVICIP24  volatile.Register8 // 0x318
	NVICIP25  volatile.Register8 // 0x319
	NVICIP26  volatile.Register8 // 0x31A
	NVICIP27  volatile.Register8 // 0x31B
	NVICIP28  volatile.Register8 // 0x31C
	NVICIP29  volatile.Register8 // 0x31D
	NVICIP30  volatile.Register8 // 0x31E
	NVICIP31  volatile.Register8 // 0x31F
	NVICIP32  volatile.Register8 // 0x320
	NVICIP33  volatile.Register8 // 0x321
	NVICIP34  volatile.Register8 // 0x322
	NVICIP35  volatile.Register8 // 0x323
	NVICIP36  volatile.Register8 // 0x324
	NVICIP37  volatile.Register8 // 0x325
	NVICIP38  volatile.Register8 // 0x326
	NVICIP39  volatile.Register8 // 0x327
	NVICIP40  volatile.Register8 // 0x328
	NVICIP41  volatile.Register8 // 0x329
	NVICIP42  volatile.Register8 // 0x32A
	NVICIP43  volatile.Register8 // 0x32B
	NVICIP44  volatile.Register8 // 0x32C
	NVICIP45  volatile.Register8 // 0x32D
	NVICIP46  volatile.Register8 // 0x32E
	NVICIP47  volatile.Register8 // 0x32F
	NVICIP48  volatile.Register8 // 0x330
	NVICIP49  volatile.Register8 // 0x331
	NVICIP50  volatile.Register8 // 0x332
	NVICIP51  volatile.Register8 // 0x333
	NVICIP52  volatile.Register8 // 0x334
	NVICIP53  volatile.Register8 // 0x335
	NVICIP54  volatile.Register8 // 0x336
	NVICIP55  volatile.Register8 // 0x337
	NVICIP56  volatile.Register8 // 0x338
	NVICIP57  volatile.Register8 // 0x339
	NVICIP58  volatile.Register8 // 0x33A
	NVICIP59  volatile.Register8 // 0x33B
	NVICIP60  volatile.Register8 // 0x33C
	NVICIP61  volatile.Register8 // 0x33D
	NVICIP62  volatile.Register8 // 0x33E
	NVICIP63  volatile.Register8 // 0x33F
	NVICIP64  volatile.Register8 // 0x340
	NVICIP65  volatile.Register8 // 0x341
	NVICIP66  volatile.Register8 // 0x342
	NVICIP67  volatile.Register8 // 0x343
	NVICIP68  volatile.Register8 // 0x344
	NVICIP69  volatile.Register8 // 0x345
	NVICIP70  volatile.Register8 // 0x346
	NVICIP71  volatile.Register8 // 0x347
	NVICIP72  volatile.Register8 // 0x348
	NVICIP73  volatile.Register8 // 0x349
	NVICIP74  volatile.Register8 // 0x34A
	NVICIP75  volatile.Register8 // 0x34B
	NVICIP76  volatile.Register8 // 0x34C
	NVICIP77  volatile.Register8 // 0x34D
	NVICIP78  volatile.Register8 // 0x34E
	NVICIP79  volatile.Register8 // 0x34F
	NVICIP80  volatile.Register8 // 0x350
	NVICIP81  volatile.Register8 // 0x351
	NVICIP82  volatile.Register8 // 0x352
	NVICIP83  volatile.Register8 // 0x353
	NVICIP84  volatile.Register8 // 0x354
	NVICIP85  volatile.Register8 // 0x355
	NVICIP86  volatile.Register8 // 0x356
	NVICIP87  volatile.Register8 // 0x357
	NVICIP88  volatile.Register8 // 0x358
	NVICIP89  volatile.Register8 // 0x359
	NVICIP90  volatile.Register8 // 0x35A
	NVICIP91  volatile.Register8 // 0x35B
	NVICIP92  volatile.Register8 // 0x35C
	NVICIP93  volatile.Register8 // 0x35D
	NVICIP94  volatile.Register8 // 0x35E
	NVICIP95  volatile.Register8 // 0x35F
	NVICIP96  volatile.Register8 // 0x360
	NVICIP97  volatile.Register8 // 0x361
	NVICIP98  volatile.Register8 // 0x362
	NVICIP99  volatile.Register8 // 0x363
	NVICIP100 volatile.Register8 // 0x364
	NVICIP101 volatile.Register8 // 0x365
	NVICIP102 volatile.Register8 // 0x366
	NVICIP103 volatile.Register8 // 0x367
	NVICIP104 volatile.Register8 // 0x368
	NVICIP105 volatile.Register8 // 0x369
	_         [2710]byte
	NVICSTIR  volatile.Register32 // 0xE00
}

// Core Platform Miscellaneous Control Module
type MCM_Type struct {
	_     [8]byte
	PLASC volatile.Register16 // 0x8
	PLAMC volatile.Register16 // 0xA
	PLACR volatile.Register32 // 0xC
	ISCR  volatile.Register32 // 0x10
	_     [44]byte
	CPO   volatile.Register32 // 0x40
}

// Bitfields for FTFA_FlashConfig: Flash configuration field
const (
	// BACKKEY3: Backdoor Comparison Key 3.
	FTFA_FlashConfig_BACKKEY3_KEY_Pos = 0x0  // Position of KEY field.
	FTFA_FlashConfig_BACKKEY3_KEY_Msk = 0xff // Bit mask of KEY field.

	// BACKKEY2: Backdoor Comparison Key 2.
	FTFA_FlashConfig_BACKKEY2_KEY_Pos = 0x0  // Position of KEY field.
	FTFA_FlashConfig_BACKKEY2_KEY_Msk = 0xff // Bit mask of KEY field.

	// BACKKEY1: Backdoor Comparison Key 1.
	FTFA_FlashConfig_BACKKEY1_KEY_Pos = 0x0  // Position of KEY field.
	FTFA_FlashConfig_BACKKEY1_KEY_Msk = 0xff // Bit mask of KEY field.

	// BACKKEY0: Backdoor Comparison Key 0.
	FTFA_FlashConfig_BACKKEY0_KEY_Pos = 0x0  // Position of KEY field.
	FTFA_FlashConfig_BACKKEY0_KEY_Msk = 0xff // Bit mask of KEY field.

	// BACKKEY7: Backdoor Comparison Key 7.
	FTFA_FlashConfig_BACKKEY7_KEY_Pos = 0x0  // Position of KEY field.
	FTFA_FlashConfig_BACKKEY7_KEY_Msk = 0xff // Bit mask of KEY field.

	// BACKKEY6: Backdoor Comparison Key 6.
	FTFA_FlashConfig_BACKKEY6_KEY_Pos = 0x0  // Position of KEY field.
	FTFA_FlashConfig_BACKKEY6_KEY_Msk = 0xff // Bit mask of KEY field.

	// BACKKEY5: Backdoor Comparison Key 5.
	FTFA_FlashConfig_BACKKEY5_KEY_Pos = 0x0  // Position of KEY field.
	FTFA_FlashConfig_BACKKEY5_KEY_Msk = 0xff // Bit mask of KEY field.

	// BACKKEY4: Backdoor Comparison Key 4.
	FTFA_FlashConfig_BACKKEY4_KEY_Pos = 0x0  // Position of KEY field.
	FTFA_FlashConfig_BACKKEY4_KEY_Msk = 0xff // Bit mask of KEY field.

	// FPROT3: Non-volatile P-Flash Protection 1 - Low Register
	FTFA_FlashConfig_FPROT3_PROT_Pos = 0x0  // Position of PROT field.
	FTFA_FlashConfig_FPROT3_PROT_Msk = 0xff // Bit mask of PROT field.

	// FPROT2: Non-volatile P-Flash Protection 1 - High Register
	FTFA_FlashConfig_FPROT2_PROT_Pos = 0x0  // Position of PROT field.
	FTFA_FlashConfig_FPROT2_PROT_Msk = 0xff // Bit mask of PROT field.

	// FPROT1: Non-volatile P-Flash Protection 0 - Low Register
	FTFA_FlashConfig_FPROT1_PROT_Pos = 0x0  // Position of PROT field.
	FTFA_FlashConfig_FPROT1_PROT_Msk = 0xff // Bit mask of PROT field.

	// FPROT0: Non-volatile P-Flash Protection 0 - High Register
	FTFA_FlashConfig_FPROT0_PROT_Pos = 0x0  // Position of PROT field.
	FTFA_FlashConfig_FPROT0_PROT_Msk = 0xff // Bit mask of PROT field.

	// FSEC: Non-volatile Flash Security Register
	FTFA_FlashConfig_FSEC_SEC_Pos    = 0x0  // Position of SEC field.
	FTFA_FlashConfig_FSEC_SEC_Msk    = 0x3  // Bit mask of SEC field.
	FTFA_FlashConfig_FSEC_SEC_10     = 0x2  // MCU security status is unsecure
	FTFA_FlashConfig_FSEC_SEC_11     = 0x3  // MCU security status is secure
	FTFA_FlashConfig_FSEC_FSLACC_Pos = 0x2  // Position of FSLACC field.
	FTFA_FlashConfig_FSEC_FSLACC_Msk = 0xc  // Bit mask of FSLACC field.
	FTFA_FlashConfig_FSEC_FSLACC_10  = 0x2  // Freescale factory access denied
	FTFA_FlashConfig_FSEC_FSLACC_11  = 0x3  // Freescale factory access granted
	FTFA_FlashConfig_FSEC_MEEN_Pos   = 0x4  // Position of MEEN field.
	FTFA_FlashConfig_FSEC_MEEN_Msk   = 0x30 // Bit mask of MEEN field.
	FTFA_FlashConfig_FSEC_MEEN_10    = 0x2  // Mass erase is disabled
	FTFA_FlashConfig_FSEC_MEEN_11    = 0x3  // Mass erase is enabled
	FTFA_FlashConfig_FSEC_KEYEN_Pos  = 0x6  // Position of KEYEN field.
	FTFA_FlashConfig_FSEC_KEYEN_Msk  = 0xc0 // Bit mask of KEYEN field.
	FTFA_FlashConfig_FSEC_KEYEN_10   = 0x2  // Backdoor key access enabled
	FTFA_FlashConfig_FSEC_KEYEN_11   = 0x3  // Backdoor key access disabled

	// FOPT: Non-volatile Flash Option Register
	FTFA_FlashConfig_FOPT_LPBOOT_Pos     = 0x0  // Position of LPBOOT field.
	FTFA_FlashConfig_FOPT_LPBOOT_Msk     = 0x1  // Bit mask of LPBOOT field.
	FTFA_FlashConfig_FOPT_LPBOOT         = 0x1  // Bit LPBOOT.
	FTFA_FlashConfig_FOPT_LPBOOT_00      = 0x0  // Low-power boot
	FTFA_FlashConfig_FOPT_LPBOOT_01      = 0x1  // Normal boot
	FTFA_FlashConfig_FOPT_EZPORT_DIS_Pos = 0x1  // Position of EZPORT_DIS field.
	FTFA_FlashConfig_FOPT_EZPORT_DIS_Msk = 0x2  // Bit mask of EZPORT_DIS field.
	FTFA_FlashConfig_FOPT_EZPORT_DIS     = 0x2  // Bit EZPORT_DIS.
	FTFA_FlashConfig_FOPT_EZPORT_DIS_00  = 0x0  // EzPort operation is disabled
	FTFA_FlashConfig_FOPT_EZPORT_DIS_01  = 0x1  // EzPort operation is enabled
	FTFA_FlashConfig_FOPT_NMI_DIS_Pos    = 0x2  // Position of NMI_DIS field.
	FTFA_FlashConfig_FOPT_NMI_DIS_Msk    = 0x4  // Bit mask of NMI_DIS field.
	FTFA_FlashConfig_FOPT_NMI_DIS        = 0x4  // Bit NMI_DIS.
	FTFA_FlashConfig_FOPT_NMI_DIS_00     = 0x0  // NMI interrupts are always blocked
	FTFA_FlashConfig_FOPT_NMI_DIS_01     = 0x1  // NMI_b pin/interrupts reset default to enabled
	FTFA_FlashConfig_FOPT_FAST_INIT_Pos  = 0x5  // Position of FAST_INIT field.
	FTFA_FlashConfig_FOPT_FAST_INIT_Msk  = 0x20 // Bit mask of FAST_INIT field.
	FTFA_FlashConfig_FOPT_FAST_INIT      = 0x20 // Bit FAST_INIT.
	FTFA_FlashConfig_FOPT_FAST_INIT_00   = 0x0  // Slower initialization
	FTFA_FlashConfig_FOPT_FAST_INIT_01   = 0x1  // Fast Initialization
)

// Bitfields for DMA: Enhanced direct memory access controller
const (
	// CR: Control Register
	DMA_CR_EDBG_Pos = 0x1     // Position of EDBG field.
	DMA_CR_EDBG_Msk = 0x2     // Bit mask of EDBG field.
	DMA_CR_EDBG     = 0x2     // Bit EDBG.
	DMA_CR_EDBG_0   = 0x0     // When in debug mode, the DMA continues to operate.
	DMA_CR_EDBG_1   = 0x1     // When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared.
	DMA_CR_ERCA_Pos = 0x2     // Position of ERCA field.
	DMA_CR_ERCA_Msk = 0x4     // Bit mask of ERCA field.
	DMA_CR_ERCA     = 0x4     // Bit ERCA.
	DMA_CR_ERCA_0   = 0x0     // Fixed priority arbitration is used for channel selection .
	DMA_CR_ERCA_1   = 0x1     // Round robin arbitration is used for channel selection .
	DMA_CR_HOE_Pos  = 0x4     // Position of HOE field.
	DMA_CR_HOE_Msk  = 0x10    // Bit mask of HOE field.
	DMA_CR_HOE      = 0x10    // Bit HOE.
	DMA_CR_HOE_0    = 0x0     // Normal operation
	DMA_CR_HOE_1    = 0x1     // Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared.
	DMA_CR_HALT_Pos = 0x5     // Position of HALT field.
	DMA_CR_HALT_Msk = 0x20    // Bit mask of HALT field.
	DMA_CR_HALT     = 0x20    // Bit HALT.
	DMA_CR_HALT_0   = 0x0     // Normal operation
	DMA_CR_HALT_1   = 0x1     // Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared.
	DMA_CR_CLM_Pos  = 0x6     // Position of CLM field.
	DMA_CR_CLM_Msk  = 0x40    // Bit mask of CLM field.
	DMA_CR_CLM      = 0x40    // Bit CLM.
	DMA_CR_CLM_0    = 0x0     // A minor loop channel link made to itself goes through channel arbitration before being activated again.
	DMA_CR_CLM_1    = 0x1     // A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop.
	DMA_CR_EMLM_Pos = 0x7     // Position of EMLM field.
	DMA_CR_EMLM_Msk = 0x80    // Bit mask of EMLM field.
	DMA_CR_EMLM     = 0x80    // Bit EMLM.
	DMA_CR_EMLM_0   = 0x0     // Disabled. TCDn.word2 is defined as a 32-bit NBYTES field.
	DMA_CR_EMLM_1   = 0x1     // Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled.
	DMA_CR_ECX_Pos  = 0x10    // Position of ECX field.
	DMA_CR_ECX_Msk  = 0x10000 // Bit mask of ECX field.
	DMA_CR_ECX      = 0x10000 // Bit ECX.
	DMA_CR_ECX_0    = 0x0     // Normal operation
	DMA_CR_ECX_1    = 0x1     // Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt.
	DMA_CR_CX_Pos   = 0x11    // Position of CX field.
	DMA_CR_CX_Msk   = 0x20000 // Bit mask of CX field.
	DMA_CR_CX       = 0x20000 // Bit CX.
	DMA_CR_CX_0     = 0x0     // Normal operation
	DMA_CR_CX_1     = 0x1     // Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed.

	// ES: Error Status Register
	DMA_ES_DBE_Pos    = 0x0        // Position of DBE field.
	DMA_ES_DBE_Msk    = 0x1        // Bit mask of DBE field.
	DMA_ES_DBE        = 0x1        // Bit DBE.
	DMA_ES_DBE_0      = 0x0        // No destination bus error
	DMA_ES_DBE_1      = 0x1        // The last recorded error was a bus error on a destination write
	DMA_ES_SBE_Pos    = 0x1        // Position of SBE field.
	DMA_ES_SBE_Msk    = 0x2        // Bit mask of SBE field.
	DMA_ES_SBE        = 0x2        // Bit SBE.
	DMA_ES_SBE_0      = 0x0        // No source bus error
	DMA_ES_SBE_1      = 0x1        // The last recorded error was a bus error on a source read
	DMA_ES_SGE_Pos    = 0x2        // Position of SGE field.
	DMA_ES_SGE_Msk    = 0x4        // Bit mask of SGE field.
	DMA_ES_SGE        = 0x4        // Bit SGE.
	DMA_ES_SGE_0      = 0x0        // No scatter/gather configuration error
	DMA_ES_SGE_1      = 0x1        // The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary.
	DMA_ES_NCE_Pos    = 0x3        // Position of NCE field.
	DMA_ES_NCE_Msk    = 0x8        // Bit mask of NCE field.
	DMA_ES_NCE        = 0x8        // Bit NCE.
	DMA_ES_NCE_0      = 0x0        // No NBYTES/CITER configuration error
	DMA_ES_NCE_1      = 0x1        // The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]
	DMA_ES_DOE_Pos    = 0x4        // Position of DOE field.
	DMA_ES_DOE_Msk    = 0x10       // Bit mask of DOE field.
	DMA_ES_DOE        = 0x10       // Bit DOE.
	DMA_ES_DOE_0      = 0x0        // No destination offset configuration error
	DMA_ES_DOE_1      = 0x1        // The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
	DMA_ES_DAE_Pos    = 0x5        // Position of DAE field.
	DMA_ES_DAE_Msk    = 0x20       // Bit mask of DAE field.
	DMA_ES_DAE        = 0x20       // Bit DAE.
	DMA_ES_DAE_0      = 0x0        // No destination address configuration error
	DMA_ES_DAE_1      = 0x1        // The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].
	DMA_ES_SOE_Pos    = 0x6        // Position of SOE field.
	DMA_ES_SOE_Msk    = 0x40       // Bit mask of SOE field.
	DMA_ES_SOE        = 0x40       // Bit SOE.
	DMA_ES_SOE_0      = 0x0        // No source offset configuration error
	DMA_ES_SOE_1      = 0x1        // The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
	DMA_ES_SAE_Pos    = 0x7        // Position of SAE field.
	DMA_ES_SAE_Msk    = 0x80       // Bit mask of SAE field.
	DMA_ES_SAE        = 0x80       // Bit SAE.
	DMA_ES_SAE_0      = 0x0        // No source address configuration error.
	DMA_ES_SAE_1      = 0x1        // The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].
	DMA_ES_ERRCHN_Pos = 0x8        // Position of ERRCHN field.
	DMA_ES_ERRCHN_Msk = 0xf00      // Bit mask of ERRCHN field.
	DMA_ES_CPE_Pos    = 0xe        // Position of CPE field.
	DMA_ES_CPE_Msk    = 0x4000     // Bit mask of CPE field.
	DMA_ES_CPE        = 0x4000     // Bit CPE.
	DMA_ES_CPE_0      = 0x0        // No channel priority error
	DMA_ES_CPE_1      = 0x1        // The last recorded error was a configuration error in the channel priorities . Channel priorities are not unique.
	DMA_ES_ECX_Pos    = 0x10       // Position of ECX field.
	DMA_ES_ECX_Msk    = 0x10000    // Bit mask of ECX field.
	DMA_ES_ECX        = 0x10000    // Bit ECX.
	DMA_ES_ECX_0      = 0x0        // No canceled transfers
	DMA_ES_ECX_1      = 0x1        // The last recorded entry was a canceled transfer by the error cancel transfer input
	DMA_ES_VLD_Pos    = 0x1f       // Position of VLD field.
	DMA_ES_VLD_Msk    = 0x80000000 // Bit mask of VLD field.
	DMA_ES_VLD        = 0x80000000 // Bit VLD.
	DMA_ES_VLD_0      = 0x0        // No ERR bits are set
	DMA_ES_VLD_1      = 0x1        // At least one ERR bit is set indicating a valid error exists that has not been cleared

	// ERQ: Enable Request Register
	DMA_ERQ_ERQ0_Pos  = 0x0    // Position of ERQ0 field.
	DMA_ERQ_ERQ0_Msk  = 0x1    // Bit mask of ERQ0 field.
	DMA_ERQ_ERQ0      = 0x1    // Bit ERQ0.
	DMA_ERQ_ERQ0_0    = 0x0    // The DMA request signal for the corresponding channel is disabled
	DMA_ERQ_ERQ0_1    = 0x1    // The DMA request signal for the corresponding channel is enabled
	DMA_ERQ_ERQ1_Pos  = 0x1    // Position of ERQ1 field.
	DMA_ERQ_ERQ1_Msk  = 0x2    // Bit mask of ERQ1 field.
	DMA_ERQ_ERQ1      = 0x2    // Bit ERQ1.
	DMA_ERQ_ERQ1_0    = 0x0    // The DMA request signal for the corresponding channel is disabled
	DMA_ERQ_ERQ1_1    = 0x1    // The DMA request signal for the corresponding channel is enabled
	DMA_ERQ_ERQ2_Pos  = 0x2    // Position of ERQ2 field.
	DMA_ERQ_ERQ2_Msk  = 0x4    // Bit mask of ERQ2 field.
	DMA_ERQ_ERQ2      = 0x4    // Bit ERQ2.
	DMA_ERQ_ERQ2_0    = 0x0    // The DMA request signal for the corresponding channel is disabled
	DMA_ERQ_ERQ2_1    = 0x1    // The DMA request signal for the corresponding channel is enabled
	DMA_ERQ_ERQ3_Pos  = 0x3    // Position of ERQ3 field.
	DMA_ERQ_ERQ3_Msk  = 0x8    // Bit mask of ERQ3 field.
	DMA_ERQ_ERQ3      = 0x8    // Bit ERQ3.
	DMA_ERQ_ERQ3_0    = 0x0    // The DMA request signal for the corresponding channel is disabled
	DMA_ERQ_ERQ3_1    = 0x1    // The DMA request signal for the corresponding channel is enabled
	DMA_ERQ_ERQ4_Pos  = 0x4    // Position of ERQ4 field.
	DMA_ERQ_ERQ4_Msk  = 0x10   // Bit mask of ERQ4 field.
	DMA_ERQ_ERQ4      = 0x10   // Bit ERQ4.
	DMA_ERQ_ERQ4_0    = 0x0    // The DMA request signal for the corresponding channel is disabled
	DMA_ERQ_ERQ4_1    = 0x1    // The DMA request signal for the corresponding channel is enabled
	DMA_ERQ_ERQ5_Pos  = 0x5    // Position of ERQ5 field.
	DMA_ERQ_ERQ5_Msk  = 0x20   // Bit mask of ERQ5 field.
	DMA_ERQ_ERQ5      = 0x20   // Bit ERQ5.
	DMA_ERQ_ERQ5_0    = 0x0    // The DMA request signal for the corresponding channel is disabled
	DMA_ERQ_ERQ5_1    = 0x1    // The DMA request signal for the corresponding channel is enabled
	DMA_ERQ_ERQ6_Pos  = 0x6    // Position of ERQ6 field.
	DMA_ERQ_ERQ6_Msk  = 0x40   // Bit mask of ERQ6 field.
	DMA_ERQ_ERQ6      = 0x40   // Bit ERQ6.
	DMA_ERQ_ERQ6_0    = 0x0    // The DMA request signal for the corresponding channel is disabled
	DMA_ERQ_ERQ6_1    = 0x1    // The DMA request signal for the corresponding channel is enabled
	DMA_ERQ_ERQ7_Pos  = 0x7    // Position of ERQ7 field.
	DMA_ERQ_ERQ7_Msk  = 0x80   // Bit mask of ERQ7 field.
	DMA_ERQ_ERQ7      = 0x80   // Bit ERQ7.
	DMA_ERQ_ERQ7_0    = 0x0    // The DMA request signal for the corresponding channel is disabled
	DMA_ERQ_ERQ7_1    = 0x1    // The DMA request signal for the corresponding channel is enabled
	DMA_ERQ_ERQ8_Pos  = 0x8    // Position of ERQ8 field.
	DMA_ERQ_ERQ8_Msk  = 0x100  // Bit mask of ERQ8 field.
	DMA_ERQ_ERQ8      = 0x100  // Bit ERQ8.
	DMA_ERQ_ERQ8_0    = 0x0    // The DMA request signal for the corresponding channel is disabled
	DMA_ERQ_ERQ8_1    = 0x1    // The DMA request signal for the corresponding channel is enabled
	DMA_ERQ_ERQ9_Pos  = 0x9    // Position of ERQ9 field.
	DMA_ERQ_ERQ9_Msk  = 0x200  // Bit mask of ERQ9 field.
	DMA_ERQ_ERQ9      = 0x200  // Bit ERQ9.
	DMA_ERQ_ERQ9_0    = 0x0    // The DMA request signal for the corresponding channel is disabled
	DMA_ERQ_ERQ9_1    = 0x1    // The DMA request signal for the corresponding channel is enabled
	DMA_ERQ_ERQ10_Pos = 0xa    // Position of ERQ10 field.
	DMA_ERQ_ERQ10_Msk = 0x400  // Bit mask of ERQ10 field.
	DMA_ERQ_ERQ10     = 0x400  // Bit ERQ10.
	DMA_ERQ_ERQ10_0   = 0x0    // The DMA request signal for the corresponding channel is disabled
	DMA_ERQ_ERQ10_1   = 0x1    // The DMA request signal for the corresponding channel is enabled
	DMA_ERQ_ERQ11_Pos = 0xb    // Position of ERQ11 field.
	DMA_ERQ_ERQ11_Msk = 0x800  // Bit mask of ERQ11 field.
	DMA_ERQ_ERQ11     = 0x800  // Bit ERQ11.
	DMA_ERQ_ERQ11_0   = 0x0    // The DMA request signal for the corresponding channel is disabled
	DMA_ERQ_ERQ11_1   = 0x1    // The DMA request signal for the corresponding channel is enabled
	DMA_ERQ_ERQ12_Pos = 0xc    // Position of ERQ12 field.
	DMA_ERQ_ERQ12_Msk = 0x1000 // Bit mask of ERQ12 field.
	DMA_ERQ_ERQ12     = 0x1000 // Bit ERQ12.
	DMA_ERQ_ERQ12_0   = 0x0    // The DMA request signal for the corresponding channel is disabled
	DMA_ERQ_ERQ12_1   = 0x1    // The DMA request signal for the corresponding channel is enabled
	DMA_ERQ_ERQ13_Pos = 0xd    // Position of ERQ13 field.
	DMA_ERQ_ERQ13_Msk = 0x2000 // Bit mask of ERQ13 field.
	DMA_ERQ_ERQ13     = 0x2000 // Bit ERQ13.
	DMA_ERQ_ERQ13_0   = 0x0    // The DMA request signal for the corresponding channel is disabled
	DMA_ERQ_ERQ13_1   = 0x1    // The DMA request signal for the corresponding channel is enabled
	DMA_ERQ_ERQ14_Pos = 0xe    // Position of ERQ14 field.
	DMA_ERQ_ERQ14_Msk = 0x4000 // Bit mask of ERQ14 field.
	DMA_ERQ_ERQ14     = 0x4000 // Bit ERQ14.
	DMA_ERQ_ERQ14_0   = 0x0    // The DMA request signal for the corresponding channel is disabled
	DMA_ERQ_ERQ14_1   = 0x1    // The DMA request signal for the corresponding channel is enabled
	DMA_ERQ_ERQ15_Pos = 0xf    // Position of ERQ15 field.
	DMA_ERQ_ERQ15_Msk = 0x8000 // Bit mask of ERQ15 field.
	DMA_ERQ_ERQ15     = 0x8000 // Bit ERQ15.
	DMA_ERQ_ERQ15_0   = 0x0    // The DMA request signal for the corresponding channel is disabled
	DMA_ERQ_ERQ15_1   = 0x1    // The DMA request signal for the corresponding channel is enabled

	// EEI: Enable Error Interrupt Register
	DMA_EEI_EEI0_Pos  = 0x0    // Position of EEI0 field.
	DMA_EEI_EEI0_Msk  = 0x1    // Bit mask of EEI0 field.
	DMA_EEI_EEI0      = 0x1    // Bit EEI0.
	DMA_EEI_EEI0_0    = 0x0    // The error signal for corresponding channel does not generate an error interrupt
	DMA_EEI_EEI0_1    = 0x1    // The assertion of the error signal for corresponding channel generates an error interrupt request
	DMA_EEI_EEI1_Pos  = 0x1    // Position of EEI1 field.
	DMA_EEI_EEI1_Msk  = 0x2    // Bit mask of EEI1 field.
	DMA_EEI_EEI1      = 0x2    // Bit EEI1.
	DMA_EEI_EEI1_0    = 0x0    // The error signal for corresponding channel does not generate an error interrupt
	DMA_EEI_EEI1_1    = 0x1    // The assertion of the error signal for corresponding channel generates an error interrupt request
	DMA_EEI_EEI2_Pos  = 0x2    // Position of EEI2 field.
	DMA_EEI_EEI2_Msk  = 0x4    // Bit mask of EEI2 field.
	DMA_EEI_EEI2      = 0x4    // Bit EEI2.
	DMA_EEI_EEI2_0    = 0x0    // The error signal for corresponding channel does not generate an error interrupt
	DMA_EEI_EEI2_1    = 0x1    // The assertion of the error signal for corresponding channel generates an error interrupt request
	DMA_EEI_EEI3_Pos  = 0x3    // Position of EEI3 field.
	DMA_EEI_EEI3_Msk  = 0x8    // Bit mask of EEI3 field.
	DMA_EEI_EEI3      = 0x8    // Bit EEI3.
	DMA_EEI_EEI3_0    = 0x0    // The error signal for corresponding channel does not generate an error interrupt
	DMA_EEI_EEI3_1    = 0x1    // The assertion of the error signal for corresponding channel generates an error interrupt request
	DMA_EEI_EEI4_Pos  = 0x4    // Position of EEI4 field.
	DMA_EEI_EEI4_Msk  = 0x10   // Bit mask of EEI4 field.
	DMA_EEI_EEI4      = 0x10   // Bit EEI4.
	DMA_EEI_EEI4_0    = 0x0    // The error signal for corresponding channel does not generate an error interrupt
	DMA_EEI_EEI4_1    = 0x1    // The assertion of the error signal for corresponding channel generates an error interrupt request
	DMA_EEI_EEI5_Pos  = 0x5    // Position of EEI5 field.
	DMA_EEI_EEI5_Msk  = 0x20   // Bit mask of EEI5 field.
	DMA_EEI_EEI5      = 0x20   // Bit EEI5.
	DMA_EEI_EEI5_0    = 0x0    // The error signal for corresponding channel does not generate an error interrupt
	DMA_EEI_EEI5_1    = 0x1    // The assertion of the error signal for corresponding channel generates an error interrupt request
	DMA_EEI_EEI6_Pos  = 0x6    // Position of EEI6 field.
	DMA_EEI_EEI6_Msk  = 0x40   // Bit mask of EEI6 field.
	DMA_EEI_EEI6      = 0x40   // Bit EEI6.
	DMA_EEI_EEI6_0    = 0x0    // The error signal for corresponding channel does not generate an error interrupt
	DMA_EEI_EEI6_1    = 0x1    // The assertion of the error signal for corresponding channel generates an error interrupt request
	DMA_EEI_EEI7_Pos  = 0x7    // Position of EEI7 field.
	DMA_EEI_EEI7_Msk  = 0x80   // Bit mask of EEI7 field.
	DMA_EEI_EEI7      = 0x80   // Bit EEI7.
	DMA_EEI_EEI7_0    = 0x0    // The error signal for corresponding channel does not generate an error interrupt
	DMA_EEI_EEI7_1    = 0x1    // The assertion of the error signal for corresponding channel generates an error interrupt request
	DMA_EEI_EEI8_Pos  = 0x8    // Position of EEI8 field.
	DMA_EEI_EEI8_Msk  = 0x100  // Bit mask of EEI8 field.
	DMA_EEI_EEI8      = 0x100  // Bit EEI8.
	DMA_EEI_EEI8_0    = 0x0    // The error signal for corresponding channel does not generate an error interrupt
	DMA_EEI_EEI8_1    = 0x1    // The assertion of the error signal for corresponding channel generates an error interrupt request
	DMA_EEI_EEI9_Pos  = 0x9    // Position of EEI9 field.
	DMA_EEI_EEI9_Msk  = 0x200  // Bit mask of EEI9 field.
	DMA_EEI_EEI9      = 0x200  // Bit EEI9.
	DMA_EEI_EEI9_0    = 0x0    // The error signal for corresponding channel does not generate an error interrupt
	DMA_EEI_EEI9_1    = 0x1    // The assertion of the error signal for corresponding channel generates an error interrupt request
	DMA_EEI_EEI10_Pos = 0xa    // Position of EEI10 field.
	DMA_EEI_EEI10_Msk = 0x400  // Bit mask of EEI10 field.
	DMA_EEI_EEI10     = 0x400  // Bit EEI10.
	DMA_EEI_EEI10_0   = 0x0    // The error signal for corresponding channel does not generate an error interrupt
	DMA_EEI_EEI10_1   = 0x1    // The assertion of the error signal for corresponding channel generates an error interrupt request
	DMA_EEI_EEI11_Pos = 0xb    // Position of EEI11 field.
	DMA_EEI_EEI11_Msk = 0x800  // Bit mask of EEI11 field.
	DMA_EEI_EEI11     = 0x800  // Bit EEI11.
	DMA_EEI_EEI11_0   = 0x0    // The error signal for corresponding channel does not generate an error interrupt
	DMA_EEI_EEI11_1   = 0x1    // The assertion of the error signal for corresponding channel generates an error interrupt request
	DMA_EEI_EEI12_Pos = 0xc    // Position of EEI12 field.
	DMA_EEI_EEI12_Msk = 0x1000 // Bit mask of EEI12 field.
	DMA_EEI_EEI12     = 0x1000 // Bit EEI12.
	DMA_EEI_EEI12_0   = 0x0    // The error signal for corresponding channel does not generate an error interrupt
	DMA_EEI_EEI12_1   = 0x1    // The assertion of the error signal for corresponding channel generates an error interrupt request
	DMA_EEI_EEI13_Pos = 0xd    // Position of EEI13 field.
	DMA_EEI_EEI13_Msk = 0x2000 // Bit mask of EEI13 field.
	DMA_EEI_EEI13     = 0x2000 // Bit EEI13.
	DMA_EEI_EEI13_0   = 0x0    // The error signal for corresponding channel does not generate an error interrupt
	DMA_EEI_EEI13_1   = 0x1    // The assertion of the error signal for corresponding channel generates an error interrupt request
	DMA_EEI_EEI14_Pos = 0xe    // Position of EEI14 field.
	DMA_EEI_EEI14_Msk = 0x4000 // Bit mask of EEI14 field.
	DMA_EEI_EEI14     = 0x4000 // Bit EEI14.
	DMA_EEI_EEI14_0   = 0x0    // The error signal for corresponding channel does not generate an error interrupt
	DMA_EEI_EEI14_1   = 0x1    // The assertion of the error signal for corresponding channel generates an error interrupt request
	DMA_EEI_EEI15_Pos = 0xf    // Position of EEI15 field.
	DMA_EEI_EEI15_Msk = 0x8000 // Bit mask of EEI15 field.
	DMA_EEI_EEI15     = 0x8000 // Bit EEI15.
	DMA_EEI_EEI15_0   = 0x0    // The error signal for corresponding channel does not generate an error interrupt
	DMA_EEI_EEI15_1   = 0x1    // The assertion of the error signal for corresponding channel generates an error interrupt request

	// CEEI: Clear Enable Error Interrupt Register
	DMA_CEEI_CEEI_Pos = 0x0  // Position of CEEI field.
	DMA_CEEI_CEEI_Msk = 0xf  // Bit mask of CEEI field.
	DMA_CEEI_CAEE_Pos = 0x6  // Position of CAEE field.
	DMA_CEEI_CAEE_Msk = 0x40 // Bit mask of CAEE field.
	DMA_CEEI_CAEE     = 0x40 // Bit CAEE.
	DMA_CEEI_CAEE_0   = 0x0  // Clear only the EEI bit specified in the CEEI field
	DMA_CEEI_CAEE_1   = 0x1  // Clear all bits in EEI
	DMA_CEEI_NOP_Pos  = 0x7  // Position of NOP field.
	DMA_CEEI_NOP_Msk  = 0x80 // Bit mask of NOP field.
	DMA_CEEI_NOP      = 0x80 // Bit NOP.
	DMA_CEEI_NOP_0    = 0x0  // Normal operation
	DMA_CEEI_NOP_1    = 0x1  // No operation, ignore the other bits in this register

	// SEEI: Set Enable Error Interrupt Register
	DMA_SEEI_SEEI_Pos = 0x0  // Position of SEEI field.
	DMA_SEEI_SEEI_Msk = 0xf  // Bit mask of SEEI field.
	DMA_SEEI_SAEE_Pos = 0x6  // Position of SAEE field.
	DMA_SEEI_SAEE_Msk = 0x40 // Bit mask of SAEE field.
	DMA_SEEI_SAEE     = 0x40 // Bit SAEE.
	DMA_SEEI_SAEE_0   = 0x0  // Set only the EEI bit specified in the SEEI field.
	DMA_SEEI_SAEE_1   = 0x1  // Sets all bits in EEI
	DMA_SEEI_NOP_Pos  = 0x7  // Position of NOP field.
	DMA_SEEI_NOP_Msk  = 0x80 // Bit mask of NOP field.
	DMA_SEEI_NOP      = 0x80 // Bit NOP.
	DMA_SEEI_NOP_0    = 0x0  // Normal operation
	DMA_SEEI_NOP_1    = 0x1  // No operation, ignore the other bits in this register

	// CERQ: Clear Enable Request Register
	DMA_CERQ_CERQ_Pos = 0x0  // Position of CERQ field.
	DMA_CERQ_CERQ_Msk = 0xf  // Bit mask of CERQ field.
	DMA_CERQ_CAER_Pos = 0x6  // Position of CAER field.
	DMA_CERQ_CAER_Msk = 0x40 // Bit mask of CAER field.
	DMA_CERQ_CAER     = 0x40 // Bit CAER.
	DMA_CERQ_CAER_0   = 0x0  // Clear only the ERQ bit specified in the CERQ field
	DMA_CERQ_CAER_1   = 0x1  // Clear all bits in ERQ
	DMA_CERQ_NOP_Pos  = 0x7  // Position of NOP field.
	DMA_CERQ_NOP_Msk  = 0x80 // Bit mask of NOP field.
	DMA_CERQ_NOP      = 0x80 // Bit NOP.
	DMA_CERQ_NOP_0    = 0x0  // Normal operation
	DMA_CERQ_NOP_1    = 0x1  // No operation, ignore the other bits in this register

	// SERQ: Set Enable Request Register
	DMA_SERQ_SERQ_Pos = 0x0  // Position of SERQ field.
	DMA_SERQ_SERQ_Msk = 0xf  // Bit mask of SERQ field.
	DMA_SERQ_SAER_Pos = 0x6  // Position of SAER field.
	DMA_SERQ_SAER_Msk = 0x40 // Bit mask of SAER field.
	DMA_SERQ_SAER     = 0x40 // Bit SAER.
	DMA_SERQ_SAER_0   = 0x0  // Set only the ERQ bit specified in the SERQ field
	DMA_SERQ_SAER_1   = 0x1  // Set all bits in ERQ
	DMA_SERQ_NOP_Pos  = 0x7  // Position of NOP field.
	DMA_SERQ_NOP_Msk  = 0x80 // Bit mask of NOP field.
	DMA_SERQ_NOP      = 0x80 // Bit NOP.
	DMA_SERQ_NOP_0    = 0x0  // Normal operation
	DMA_SERQ_NOP_1    = 0x1  // No operation, ignore the other bits in this register

	// CDNE: Clear DONE Status Bit Register
	DMA_CDNE_CDNE_Pos = 0x0  // Position of CDNE field.
	DMA_CDNE_CDNE_Msk = 0xf  // Bit mask of CDNE field.
	DMA_CDNE_CADN_Pos = 0x6  // Position of CADN field.
	DMA_CDNE_CADN_Msk = 0x40 // Bit mask of CADN field.
	DMA_CDNE_CADN     = 0x40 // Bit CADN.
	DMA_CDNE_CADN_0   = 0x0  // Clears only the TCDn_CSR[DONE] bit specified in the CDNE field
	DMA_CDNE_CADN_1   = 0x1  // Clears all bits in TCDn_CSR[DONE]
	DMA_CDNE_NOP_Pos  = 0x7  // Position of NOP field.
	DMA_CDNE_NOP_Msk  = 0x80 // Bit mask of NOP field.
	DMA_CDNE_NOP      = 0x80 // Bit NOP.
	DMA_CDNE_NOP_0    = 0x0  // Normal operation
	DMA_CDNE_NOP_1    = 0x1  // No operation, ignore the other bits in this register

	// SSRT: Set START Bit Register
	DMA_SSRT_SSRT_Pos = 0x0  // Position of SSRT field.
	DMA_SSRT_SSRT_Msk = 0xf  // Bit mask of SSRT field.
	DMA_SSRT_SAST_Pos = 0x6  // Position of SAST field.
	DMA_SSRT_SAST_Msk = 0x40 // Bit mask of SAST field.
	DMA_SSRT_SAST     = 0x40 // Bit SAST.
	DMA_SSRT_SAST_0   = 0x0  // Set only the TCDn_CSR[START] bit specified in the SSRT field
	DMA_SSRT_SAST_1   = 0x1  // Set all bits in TCDn_CSR[START]
	DMA_SSRT_NOP_Pos  = 0x7  // Position of NOP field.
	DMA_SSRT_NOP_Msk  = 0x80 // Bit mask of NOP field.
	DMA_SSRT_NOP      = 0x80 // Bit NOP.
	DMA_SSRT_NOP_0    = 0x0  // Normal operation
	DMA_SSRT_NOP_1    = 0x1  // No operation, ignore the other bits in this register

	// CERR: Clear Error Register
	DMA_CERR_CERR_Pos = 0x0  // Position of CERR field.
	DMA_CERR_CERR_Msk = 0xf  // Bit mask of CERR field.
	DMA_CERR_CAEI_Pos = 0x6  // Position of CAEI field.
	DMA_CERR_CAEI_Msk = 0x40 // Bit mask of CAEI field.
	DMA_CERR_CAEI     = 0x40 // Bit CAEI.
	DMA_CERR_CAEI_0   = 0x0  // Clear only the ERR bit specified in the CERR field
	DMA_CERR_CAEI_1   = 0x1  // Clear all bits in ERR
	DMA_CERR_NOP_Pos  = 0x7  // Position of NOP field.
	DMA_CERR_NOP_Msk  = 0x80 // Bit mask of NOP field.
	DMA_CERR_NOP      = 0x80 // Bit NOP.
	DMA_CERR_NOP_0    = 0x0  // Normal operation
	DMA_CERR_NOP_1    = 0x1  // No operation, ignore the other bits in this register

	// CINT: Clear Interrupt Request Register
	DMA_CINT_CINT_Pos = 0x0  // Position of CINT field.
	DMA_CINT_CINT_Msk = 0xf  // Bit mask of CINT field.
	DMA_CINT_CAIR_Pos = 0x6  // Position of CAIR field.
	DMA_CINT_CAIR_Msk = 0x40 // Bit mask of CAIR field.
	DMA_CINT_CAIR     = 0x40 // Bit CAIR.
	DMA_CINT_CAIR_0   = 0x0  // Clear only the INT bit specified in the CINT field
	DMA_CINT_CAIR_1   = 0x1  // Clear all bits in INT
	DMA_CINT_NOP_Pos  = 0x7  // Position of NOP field.
	DMA_CINT_NOP_Msk  = 0x80 // Bit mask of NOP field.
	DMA_CINT_NOP      = 0x80 // Bit NOP.
	DMA_CINT_NOP_0    = 0x0  // Normal operation
	DMA_CINT_NOP_1    = 0x1  // No operation, ignore the other bits in this register

	// INT: Interrupt Request Register
	DMA_INT_INT0_Pos  = 0x0    // Position of INT0 field.
	DMA_INT_INT0_Msk  = 0x1    // Bit mask of INT0 field.
	DMA_INT_INT0      = 0x1    // Bit INT0.
	DMA_INT_INT0_0    = 0x0    // The interrupt request for corresponding channel is cleared
	DMA_INT_INT0_1    = 0x1    // The interrupt request for corresponding channel is active
	DMA_INT_INT1_Pos  = 0x1    // Position of INT1 field.
	DMA_INT_INT1_Msk  = 0x2    // Bit mask of INT1 field.
	DMA_INT_INT1      = 0x2    // Bit INT1.
	DMA_INT_INT1_0    = 0x0    // The interrupt request for corresponding channel is cleared
	DMA_INT_INT1_1    = 0x1    // The interrupt request for corresponding channel is active
	DMA_INT_INT2_Pos  = 0x2    // Position of INT2 field.
	DMA_INT_INT2_Msk  = 0x4    // Bit mask of INT2 field.
	DMA_INT_INT2      = 0x4    // Bit INT2.
	DMA_INT_INT2_0    = 0x0    // The interrupt request for corresponding channel is cleared
	DMA_INT_INT2_1    = 0x1    // The interrupt request for corresponding channel is active
	DMA_INT_INT3_Pos  = 0x3    // Position of INT3 field.
	DMA_INT_INT3_Msk  = 0x8    // Bit mask of INT3 field.
	DMA_INT_INT3      = 0x8    // Bit INT3.
	DMA_INT_INT3_0    = 0x0    // The interrupt request for corresponding channel is cleared
	DMA_INT_INT3_1    = 0x1    // The interrupt request for corresponding channel is active
	DMA_INT_INT4_Pos  = 0x4    // Position of INT4 field.
	DMA_INT_INT4_Msk  = 0x10   // Bit mask of INT4 field.
	DMA_INT_INT4      = 0x10   // Bit INT4.
	DMA_INT_INT4_0    = 0x0    // The interrupt request for corresponding channel is cleared
	DMA_INT_INT4_1    = 0x1    // The interrupt request for corresponding channel is active
	DMA_INT_INT5_Pos  = 0x5    // Position of INT5 field.
	DMA_INT_INT5_Msk  = 0x20   // Bit mask of INT5 field.
	DMA_INT_INT5      = 0x20   // Bit INT5.
	DMA_INT_INT5_0    = 0x0    // The interrupt request for corresponding channel is cleared
	DMA_INT_INT5_1    = 0x1    // The interrupt request for corresponding channel is active
	DMA_INT_INT6_Pos  = 0x6    // Position of INT6 field.
	DMA_INT_INT6_Msk  = 0x40   // Bit mask of INT6 field.
	DMA_INT_INT6      = 0x40   // Bit INT6.
	DMA_INT_INT6_0    = 0x0    // The interrupt request for corresponding channel is cleared
	DMA_INT_INT6_1    = 0x1    // The interrupt request for corresponding channel is active
	DMA_INT_INT7_Pos  = 0x7    // Position of INT7 field.
	DMA_INT_INT7_Msk  = 0x80   // Bit mask of INT7 field.
	DMA_INT_INT7      = 0x80   // Bit INT7.
	DMA_INT_INT7_0    = 0x0    // The interrupt request for corresponding channel is cleared
	DMA_INT_INT7_1    = 0x1    // The interrupt request for corresponding channel is active
	DMA_INT_INT8_Pos  = 0x8    // Position of INT8 field.
	DMA_INT_INT8_Msk  = 0x100  // Bit mask of INT8 field.
	DMA_INT_INT8      = 0x100  // Bit INT8.
	DMA_INT_INT8_0    = 0x0    // The interrupt request for corresponding channel is cleared
	DMA_INT_INT8_1    = 0x1    // The interrupt request for corresponding channel is active
	DMA_INT_INT9_Pos  = 0x9    // Position of INT9 field.
	DMA_INT_INT9_Msk  = 0x200  // Bit mask of INT9 field.
	DMA_INT_INT9      = 0x200  // Bit INT9.
	DMA_INT_INT9_0    = 0x0    // The interrupt request for corresponding channel is cleared
	DMA_INT_INT9_1    = 0x1    // The interrupt request for corresponding channel is active
	DMA_INT_INT10_Pos = 0xa    // Position of INT10 field.
	DMA_INT_INT10_Msk = 0x400  // Bit mask of INT10 field.
	DMA_INT_INT10     = 0x400  // Bit INT10.
	DMA_INT_INT10_0   = 0x0    // The interrupt request for corresponding channel is cleared
	DMA_INT_INT10_1   = 0x1    // The interrupt request for corresponding channel is active
	DMA_INT_INT11_Pos = 0xb    // Position of INT11 field.
	DMA_INT_INT11_Msk = 0x800  // Bit mask of INT11 field.
	DMA_INT_INT11     = 0x800  // Bit INT11.
	DMA_INT_INT11_0   = 0x0    // The interrupt request for corresponding channel is cleared
	DMA_INT_INT11_1   = 0x1    // The interrupt request for corresponding channel is active
	DMA_INT_INT12_Pos = 0xc    // Position of INT12 field.
	DMA_INT_INT12_Msk = 0x1000 // Bit mask of INT12 field.
	DMA_INT_INT12     = 0x1000 // Bit INT12.
	DMA_INT_INT12_0   = 0x0    // The interrupt request for corresponding channel is cleared
	DMA_INT_INT12_1   = 0x1    // The interrupt request for corresponding channel is active
	DMA_INT_INT13_Pos = 0xd    // Position of INT13 field.
	DMA_INT_INT13_Msk = 0x2000 // Bit mask of INT13 field.
	DMA_INT_INT13     = 0x2000 // Bit INT13.
	DMA_INT_INT13_0   = 0x0    // The interrupt request for corresponding channel is cleared
	DMA_INT_INT13_1   = 0x1    // The interrupt request for corresponding channel is active
	DMA_INT_INT14_Pos = 0xe    // Position of INT14 field.
	DMA_INT_INT14_Msk = 0x4000 // Bit mask of INT14 field.
	DMA_INT_INT14     = 0x4000 // Bit INT14.
	DMA_INT_INT14_0   = 0x0    // The interrupt request for corresponding channel is cleared
	DMA_INT_INT14_1   = 0x1    // The interrupt request for corresponding channel is active
	DMA_INT_INT15_Pos = 0xf    // Position of INT15 field.
	DMA_INT_INT15_Msk = 0x8000 // Bit mask of INT15 field.
	DMA_INT_INT15     = 0x8000 // Bit INT15.
	DMA_INT_INT15_0   = 0x0    // The interrupt request for corresponding channel is cleared
	DMA_INT_INT15_1   = 0x1    // The interrupt request for corresponding channel is active

	// ERR: Error Register
	DMA_ERR_ERR0_Pos  = 0x0    // Position of ERR0 field.
	DMA_ERR_ERR0_Msk  = 0x1    // Bit mask of ERR0 field.
	DMA_ERR_ERR0      = 0x1    // Bit ERR0.
	DMA_ERR_ERR0_0    = 0x0    // An error in the corresponding channel has not occurred
	DMA_ERR_ERR0_1    = 0x1    // An error in the corresponding channel has occurred
	DMA_ERR_ERR1_Pos  = 0x1    // Position of ERR1 field.
	DMA_ERR_ERR1_Msk  = 0x2    // Bit mask of ERR1 field.
	DMA_ERR_ERR1      = 0x2    // Bit ERR1.
	DMA_ERR_ERR1_0    = 0x0    // An error in the corresponding channel has not occurred
	DMA_ERR_ERR1_1    = 0x1    // An error in the corresponding channel has occurred
	DMA_ERR_ERR2_Pos  = 0x2    // Position of ERR2 field.
	DMA_ERR_ERR2_Msk  = 0x4    // Bit mask of ERR2 field.
	DMA_ERR_ERR2      = 0x4    // Bit ERR2.
	DMA_ERR_ERR2_0    = 0x0    // An error in the corresponding channel has not occurred
	DMA_ERR_ERR2_1    = 0x1    // An error in the corresponding channel has occurred
	DMA_ERR_ERR3_Pos  = 0x3    // Position of ERR3 field.
	DMA_ERR_ERR3_Msk  = 0x8    // Bit mask of ERR3 field.
	DMA_ERR_ERR3      = 0x8    // Bit ERR3.
	DMA_ERR_ERR3_0    = 0x0    // An error in the corresponding channel has not occurred
	DMA_ERR_ERR3_1    = 0x1    // An error in the corresponding channel has occurred
	DMA_ERR_ERR4_Pos  = 0x4    // Position of ERR4 field.
	DMA_ERR_ERR4_Msk  = 0x10   // Bit mask of ERR4 field.
	DMA_ERR_ERR4      = 0x10   // Bit ERR4.
	DMA_ERR_ERR4_0    = 0x0    // An error in the corresponding channel has not occurred
	DMA_ERR_ERR4_1    = 0x1    // An error in the corresponding channel has occurred
	DMA_ERR_ERR5_Pos  = 0x5    // Position of ERR5 field.
	DMA_ERR_ERR5_Msk  = 0x20   // Bit mask of ERR5 field.
	DMA_ERR_ERR5      = 0x20   // Bit ERR5.
	DMA_ERR_ERR5_0    = 0x0    // An error in the corresponding channel has not occurred
	DMA_ERR_ERR5_1    = 0x1    // An error in the corresponding channel has occurred
	DMA_ERR_ERR6_Pos  = 0x6    // Position of ERR6 field.
	DMA_ERR_ERR6_Msk  = 0x40   // Bit mask of ERR6 field.
	DMA_ERR_ERR6      = 0x40   // Bit ERR6.
	DMA_ERR_ERR6_0    = 0x0    // An error in the corresponding channel has not occurred
	DMA_ERR_ERR6_1    = 0x1    // An error in the corresponding channel has occurred
	DMA_ERR_ERR7_Pos  = 0x7    // Position of ERR7 field.
	DMA_ERR_ERR7_Msk  = 0x80   // Bit mask of ERR7 field.
	DMA_ERR_ERR7      = 0x80   // Bit ERR7.
	DMA_ERR_ERR7_0    = 0x0    // An error in the corresponding channel has not occurred
	DMA_ERR_ERR7_1    = 0x1    // An error in the corresponding channel has occurred
	DMA_ERR_ERR8_Pos  = 0x8    // Position of ERR8 field.
	DMA_ERR_ERR8_Msk  = 0x100  // Bit mask of ERR8 field.
	DMA_ERR_ERR8      = 0x100  // Bit ERR8.
	DMA_ERR_ERR8_0    = 0x0    // An error in the corresponding channel has not occurred
	DMA_ERR_ERR8_1    = 0x1    // An error in the corresponding channel has occurred
	DMA_ERR_ERR9_Pos  = 0x9    // Position of ERR9 field.
	DMA_ERR_ERR9_Msk  = 0x200  // Bit mask of ERR9 field.
	DMA_ERR_ERR9      = 0x200  // Bit ERR9.
	DMA_ERR_ERR9_0    = 0x0    // An error in the corresponding channel has not occurred
	DMA_ERR_ERR9_1    = 0x1    // An error in the corresponding channel has occurred
	DMA_ERR_ERR10_Pos = 0xa    // Position of ERR10 field.
	DMA_ERR_ERR10_Msk = 0x400  // Bit mask of ERR10 field.
	DMA_ERR_ERR10     = 0x400  // Bit ERR10.
	DMA_ERR_ERR10_0   = 0x0    // An error in the corresponding channel has not occurred
	DMA_ERR_ERR10_1   = 0x1    // An error in the corresponding channel has occurred
	DMA_ERR_ERR11_Pos = 0xb    // Position of ERR11 field.
	DMA_ERR_ERR11_Msk = 0x800  // Bit mask of ERR11 field.
	DMA_ERR_ERR11     = 0x800  // Bit ERR11.
	DMA_ERR_ERR11_0   = 0x0    // An error in the corresponding channel has not occurred
	DMA_ERR_ERR11_1   = 0x1    // An error in the corresponding channel has occurred
	DMA_ERR_ERR12_Pos = 0xc    // Position of ERR12 field.
	DMA_ERR_ERR12_Msk = 0x1000 // Bit mask of ERR12 field.
	DMA_ERR_ERR12     = 0x1000 // Bit ERR12.
	DMA_ERR_ERR12_0   = 0x0    // An error in the corresponding channel has not occurred
	DMA_ERR_ERR12_1   = 0x1    // An error in the corresponding channel has occurred
	DMA_ERR_ERR13_Pos = 0xd    // Position of ERR13 field.
	DMA_ERR_ERR13_Msk = 0x2000 // Bit mask of ERR13 field.
	DMA_ERR_ERR13     = 0x2000 // Bit ERR13.
	DMA_ERR_ERR13_0   = 0x0    // An error in the corresponding channel has not occurred
	DMA_ERR_ERR13_1   = 0x1    // An error in the corresponding channel has occurred
	DMA_ERR_ERR14_Pos = 0xe    // Position of ERR14 field.
	DMA_ERR_ERR14_Msk = 0x4000 // Bit mask of ERR14 field.
	DMA_ERR_ERR14     = 0x4000 // Bit ERR14.
	DMA_ERR_ERR14_0   = 0x0    // An error in the corresponding channel has not occurred
	DMA_ERR_ERR14_1   = 0x1    // An error in the corresponding channel has occurred
	DMA_ERR_ERR15_Pos = 0xf    // Position of ERR15 field.
	DMA_ERR_ERR15_Msk = 0x8000 // Bit mask of ERR15 field.
	DMA_ERR_ERR15     = 0x8000 // Bit ERR15.
	DMA_ERR_ERR15_0   = 0x0    // An error in the corresponding channel has not occurred
	DMA_ERR_ERR15_1   = 0x1    // An error in the corresponding channel has occurred

	// HRS: Hardware Request Status Register
	DMA_HRS_HRS0_Pos  = 0x0    // Position of HRS0 field.
	DMA_HRS_HRS0_Msk  = 0x1    // Bit mask of HRS0 field.
	DMA_HRS_HRS0      = 0x1    // Bit HRS0.
	DMA_HRS_HRS0_0    = 0x0    // A hardware service request for channel 0 is not present
	DMA_HRS_HRS0_1    = 0x1    // A hardware service request for channel 0 is present
	DMA_HRS_HRS1_Pos  = 0x1    // Position of HRS1 field.
	DMA_HRS_HRS1_Msk  = 0x2    // Bit mask of HRS1 field.
	DMA_HRS_HRS1      = 0x2    // Bit HRS1.
	DMA_HRS_HRS1_0    = 0x0    // A hardware service request for channel 1 is not present
	DMA_HRS_HRS1_1    = 0x1    // A hardware service request for channel 1 is present
	DMA_HRS_HRS2_Pos  = 0x2    // Position of HRS2 field.
	DMA_HRS_HRS2_Msk  = 0x4    // Bit mask of HRS2 field.
	DMA_HRS_HRS2      = 0x4    // Bit HRS2.
	DMA_HRS_HRS2_0    = 0x0    // A hardware service request for channel 2 is not present
	DMA_HRS_HRS2_1    = 0x1    // A hardware service request for channel 2 is present
	DMA_HRS_HRS3_Pos  = 0x3    // Position of HRS3 field.
	DMA_HRS_HRS3_Msk  = 0x8    // Bit mask of HRS3 field.
	DMA_HRS_HRS3      = 0x8    // Bit HRS3.
	DMA_HRS_HRS3_0    = 0x0    // A hardware service request for channel 3 is not present
	DMA_HRS_HRS3_1    = 0x1    // A hardware service request for channel 3 is present
	DMA_HRS_HRS4_Pos  = 0x4    // Position of HRS4 field.
	DMA_HRS_HRS4_Msk  = 0x10   // Bit mask of HRS4 field.
	DMA_HRS_HRS4      = 0x10   // Bit HRS4.
	DMA_HRS_HRS4_0    = 0x0    // A hardware service request for channel 4 is not present
	DMA_HRS_HRS4_1    = 0x1    // A hardware service request for channel 4 is present
	DMA_HRS_HRS5_Pos  = 0x5    // Position of HRS5 field.
	DMA_HRS_HRS5_Msk  = 0x20   // Bit mask of HRS5 field.
	DMA_HRS_HRS5      = 0x20   // Bit HRS5.
	DMA_HRS_HRS5_0    = 0x0    // A hardware service request for channel 5 is not present
	DMA_HRS_HRS5_1    = 0x1    // A hardware service request for channel 5 is present
	DMA_HRS_HRS6_Pos  = 0x6    // Position of HRS6 field.
	DMA_HRS_HRS6_Msk  = 0x40   // Bit mask of HRS6 field.
	DMA_HRS_HRS6      = 0x40   // Bit HRS6.
	DMA_HRS_HRS6_0    = 0x0    // A hardware service request for channel 6 is not present
	DMA_HRS_HRS6_1    = 0x1    // A hardware service request for channel 6 is present
	DMA_HRS_HRS7_Pos  = 0x7    // Position of HRS7 field.
	DMA_HRS_HRS7_Msk  = 0x80   // Bit mask of HRS7 field.
	DMA_HRS_HRS7      = 0x80   // Bit HRS7.
	DMA_HRS_HRS7_0    = 0x0    // A hardware service request for channel 7 is not present
	DMA_HRS_HRS7_1    = 0x1    // A hardware service request for channel 7 is present
	DMA_HRS_HRS8_Pos  = 0x8    // Position of HRS8 field.
	DMA_HRS_HRS8_Msk  = 0x100  // Bit mask of HRS8 field.
	DMA_HRS_HRS8      = 0x100  // Bit HRS8.
	DMA_HRS_HRS8_0    = 0x0    // A hardware service request for channel 8 is not present
	DMA_HRS_HRS8_1    = 0x1    // A hardware service request for channel 8 is present
	DMA_HRS_HRS9_Pos  = 0x9    // Position of HRS9 field.
	DMA_HRS_HRS9_Msk  = 0x200  // Bit mask of HRS9 field.
	DMA_HRS_HRS9      = 0x200  // Bit HRS9.
	DMA_HRS_HRS9_0    = 0x0    // A hardware service request for channel 9 is not present
	DMA_HRS_HRS9_1    = 0x1    // A hardware service request for channel 9 is present
	DMA_HRS_HRS10_Pos = 0xa    // Position of HRS10 field.
	DMA_HRS_HRS10_Msk = 0x400  // Bit mask of HRS10 field.
	DMA_HRS_HRS10     = 0x400  // Bit HRS10.
	DMA_HRS_HRS10_0   = 0x0    // A hardware service request for channel 10 is not present
	DMA_HRS_HRS10_1   = 0x1    // A hardware service request for channel 10 is present
	DMA_HRS_HRS11_Pos = 0xb    // Position of HRS11 field.
	DMA_HRS_HRS11_Msk = 0x800  // Bit mask of HRS11 field.
	DMA_HRS_HRS11     = 0x800  // Bit HRS11.
	DMA_HRS_HRS11_0   = 0x0    // A hardware service request for channel 11 is not present
	DMA_HRS_HRS11_1   = 0x1    // A hardware service request for channel 11 is present
	DMA_HRS_HRS12_Pos = 0xc    // Position of HRS12 field.
	DMA_HRS_HRS12_Msk = 0x1000 // Bit mask of HRS12 field.
	DMA_HRS_HRS12     = 0x1000 // Bit HRS12.
	DMA_HRS_HRS12_0   = 0x0    // A hardware service request for channel 12 is not present
	DMA_HRS_HRS12_1   = 0x1    // A hardware service request for channel 12 is present
	DMA_HRS_HRS13_Pos = 0xd    // Position of HRS13 field.
	DMA_HRS_HRS13_Msk = 0x2000 // Bit mask of HRS13 field.
	DMA_HRS_HRS13     = 0x2000 // Bit HRS13.
	DMA_HRS_HRS13_0   = 0x0    // A hardware service request for channel 13 is not present
	DMA_HRS_HRS13_1   = 0x1    // A hardware service request for channel 13 is present
	DMA_HRS_HRS14_Pos = 0xe    // Position of HRS14 field.
	DMA_HRS_HRS14_Msk = 0x4000 // Bit mask of HRS14 field.
	DMA_HRS_HRS14     = 0x4000 // Bit HRS14.
	DMA_HRS_HRS14_0   = 0x0    // A hardware service request for channel 14 is not present
	DMA_HRS_HRS14_1   = 0x1    // A hardware service request for channel 14 is present
	DMA_HRS_HRS15_Pos = 0xf    // Position of HRS15 field.
	DMA_HRS_HRS15_Msk = 0x8000 // Bit mask of HRS15 field.
	DMA_HRS_HRS15     = 0x8000 // Bit HRS15.
	DMA_HRS_HRS15_0   = 0x0    // A hardware service request for channel 15 is not present
	DMA_HRS_HRS15_1   = 0x1    // A hardware service request for channel 15 is present

	// EARS: Enable Asynchronous Request in Stop Register
	DMA_EARS_EDREQ_0_Pos  = 0x0    // Position of EDREQ_0 field.
	DMA_EARS_EDREQ_0_Msk  = 0x1    // Bit mask of EDREQ_0 field.
	DMA_EARS_EDREQ_0      = 0x1    // Bit EDREQ_0.
	DMA_EARS_EDREQ_0_0    = 0x0    // Disable asynchronous DMA request for channel 0.
	DMA_EARS_EDREQ_0_1    = 0x1    // Enable asynchronous DMA request for channel 0.
	DMA_EARS_EDREQ_1_Pos  = 0x1    // Position of EDREQ_1 field.
	DMA_EARS_EDREQ_1_Msk  = 0x2    // Bit mask of EDREQ_1 field.
	DMA_EARS_EDREQ_1      = 0x2    // Bit EDREQ_1.
	DMA_EARS_EDREQ_1_0    = 0x0    // Disable asynchronous DMA request for channel 1
	DMA_EARS_EDREQ_1_1    = 0x1    // Enable asynchronous DMA request for channel 1.
	DMA_EARS_EDREQ_2_Pos  = 0x2    // Position of EDREQ_2 field.
	DMA_EARS_EDREQ_2_Msk  = 0x4    // Bit mask of EDREQ_2 field.
	DMA_EARS_EDREQ_2      = 0x4    // Bit EDREQ_2.
	DMA_EARS_EDREQ_2_0    = 0x0    // Disable asynchronous DMA request for channel 2.
	DMA_EARS_EDREQ_2_1    = 0x1    // Enable asynchronous DMA request for channel 2.
	DMA_EARS_EDREQ_3_Pos  = 0x3    // Position of EDREQ_3 field.
	DMA_EARS_EDREQ_3_Msk  = 0x8    // Bit mask of EDREQ_3 field.
	DMA_EARS_EDREQ_3      = 0x8    // Bit EDREQ_3.
	DMA_EARS_EDREQ_3_0    = 0x0    // Disable asynchronous DMA request for channel 3.
	DMA_EARS_EDREQ_3_1    = 0x1    // Enable asynchronous DMA request for channel 3.
	DMA_EARS_EDREQ_4_Pos  = 0x4    // Position of EDREQ_4 field.
	DMA_EARS_EDREQ_4_Msk  = 0x10   // Bit mask of EDREQ_4 field.
	DMA_EARS_EDREQ_4      = 0x10   // Bit EDREQ_4.
	DMA_EARS_EDREQ_4_0    = 0x0    // Disable asynchronous DMA request for channel 4.
	DMA_EARS_EDREQ_4_1    = 0x1    // Enable asynchronous DMA request for channel 4.
	DMA_EARS_EDREQ_5_Pos  = 0x5    // Position of EDREQ_5 field.
	DMA_EARS_EDREQ_5_Msk  = 0x20   // Bit mask of EDREQ_5 field.
	DMA_EARS_EDREQ_5      = 0x20   // Bit EDREQ_5.
	DMA_EARS_EDREQ_5_0    = 0x0    // Disable asynchronous DMA request for channel 5.
	DMA_EARS_EDREQ_5_1    = 0x1    // Enable asynchronous DMA request for channel 5.
	DMA_EARS_EDREQ_6_Pos  = 0x6    // Position of EDREQ_6 field.
	DMA_EARS_EDREQ_6_Msk  = 0x40   // Bit mask of EDREQ_6 field.
	DMA_EARS_EDREQ_6      = 0x40   // Bit EDREQ_6.
	DMA_EARS_EDREQ_6_0    = 0x0    // Disable asynchronous DMA request for channel 6.
	DMA_EARS_EDREQ_6_1    = 0x1    // Enable asynchronous DMA request for channel 6.
	DMA_EARS_EDREQ_7_Pos  = 0x7    // Position of EDREQ_7 field.
	DMA_EARS_EDREQ_7_Msk  = 0x80   // Bit mask of EDREQ_7 field.
	DMA_EARS_EDREQ_7      = 0x80   // Bit EDREQ_7.
	DMA_EARS_EDREQ_7_0    = 0x0    // Disable asynchronous DMA request for channel 7.
	DMA_EARS_EDREQ_7_1    = 0x1    // Enable asynchronous DMA request for channel 7.
	DMA_EARS_EDREQ_8_Pos  = 0x8    // Position of EDREQ_8 field.
	DMA_EARS_EDREQ_8_Msk  = 0x100  // Bit mask of EDREQ_8 field.
	DMA_EARS_EDREQ_8      = 0x100  // Bit EDREQ_8.
	DMA_EARS_EDREQ_8_0    = 0x0    // Disable asynchronous DMA request for channel 8.
	DMA_EARS_EDREQ_8_1    = 0x1    // Enable asynchronous DMA request for channel 8.
	DMA_EARS_EDREQ_9_Pos  = 0x9    // Position of EDREQ_9 field.
	DMA_EARS_EDREQ_9_Msk  = 0x200  // Bit mask of EDREQ_9 field.
	DMA_EARS_EDREQ_9      = 0x200  // Bit EDREQ_9.
	DMA_EARS_EDREQ_9_0    = 0x0    // Disable asynchronous DMA request for channel 9.
	DMA_EARS_EDREQ_9_1    = 0x1    // Enable asynchronous DMA request for channel 9.
	DMA_EARS_EDREQ_10_Pos = 0xa    // Position of EDREQ_10 field.
	DMA_EARS_EDREQ_10_Msk = 0x400  // Bit mask of EDREQ_10 field.
	DMA_EARS_EDREQ_10     = 0x400  // Bit EDREQ_10.
	DMA_EARS_EDREQ_10_0   = 0x0    // Disable asynchronous DMA request for channel 10.
	DMA_EARS_EDREQ_10_1   = 0x1    // Enable asynchronous DMA request for channel 10.
	DMA_EARS_EDREQ_11_Pos = 0xb    // Position of EDREQ_11 field.
	DMA_EARS_EDREQ_11_Msk = 0x800  // Bit mask of EDREQ_11 field.
	DMA_EARS_EDREQ_11     = 0x800  // Bit EDREQ_11.
	DMA_EARS_EDREQ_11_0   = 0x0    // Disable asynchronous DMA request for channel 11.
	DMA_EARS_EDREQ_11_1   = 0x1    // Enable asynchronous DMA request for channel 11.
	DMA_EARS_EDREQ_12_Pos = 0xc    // Position of EDREQ_12 field.
	DMA_EARS_EDREQ_12_Msk = 0x1000 // Bit mask of EDREQ_12 field.
	DMA_EARS_EDREQ_12     = 0x1000 // Bit EDREQ_12.
	DMA_EARS_EDREQ_12_0   = 0x0    // Disable asynchronous DMA request for channel 12.
	DMA_EARS_EDREQ_12_1   = 0x1    // Enable asynchronous DMA request for channel 12.
	DMA_EARS_EDREQ_13_Pos = 0xd    // Position of EDREQ_13 field.
	DMA_EARS_EDREQ_13_Msk = 0x2000 // Bit mask of EDREQ_13 field.
	DMA_EARS_EDREQ_13     = 0x2000 // Bit EDREQ_13.
	DMA_EARS_EDREQ_13_0   = 0x0    // Disable asynchronous DMA request for channel 13.
	DMA_EARS_EDREQ_13_1   = 0x1    // Enable asynchronous DMA request for channel 13.
	DMA_EARS_EDREQ_14_Pos = 0xe    // Position of EDREQ_14 field.
	DMA_EARS_EDREQ_14_Msk = 0x4000 // Bit mask of EDREQ_14 field.
	DMA_EARS_EDREQ_14     = 0x4000 // Bit EDREQ_14.
	DMA_EARS_EDREQ_14_0   = 0x0    // Disable asynchronous DMA request for channel 14.
	DMA_EARS_EDREQ_14_1   = 0x1    // Enable asynchronous DMA request for channel 14.
	DMA_EARS_EDREQ_15_Pos = 0xf    // Position of EDREQ_15 field.
	DMA_EARS_EDREQ_15_Msk = 0x8000 // Bit mask of EDREQ_15 field.
	DMA_EARS_EDREQ_15     = 0x8000 // Bit EDREQ_15.
	DMA_EARS_EDREQ_15_0   = 0x0    // Disable asynchronous DMA request for channel 15.
	DMA_EARS_EDREQ_15_1   = 0x1    // Enable asynchronous DMA request for channel 15.

	// DCHPRI3: Channel n Priority Register
	DMA_DCHPRI_CHPRI_Pos = 0x0  // Position of CHPRI field.
	DMA_DCHPRI_CHPRI_Msk = 0xf  // Bit mask of CHPRI field.
	DMA_DCHPRI_DPA_Pos   = 0x6  // Position of DPA field.
	DMA_DCHPRI_DPA_Msk   = 0x40 // Bit mask of DPA field.
	DMA_DCHPRI_DPA       = 0x40 // Bit DPA.
	DMA_DCHPRI_DPA_0     = 0x0  // Channel n can suspend a lower priority channel
	DMA_DCHPRI_DPA_1     = 0x1  // Channel n cannot suspend any channel, regardless of channel priority
	DMA_DCHPRI_ECP_Pos   = 0x7  // Position of ECP field.
	DMA_DCHPRI_ECP_Msk   = 0x80 // Bit mask of ECP field.
	DMA_DCHPRI_ECP       = 0x80 // Bit ECP.
	DMA_DCHPRI_ECP_0     = 0x0  // Channel n cannot be suspended by a higher priority channel's service request
	DMA_DCHPRI_ECP_1     = 0x1  // Channel n can be temporarily suspended by the service request of a higher priority channel

	// TCD0_SADDR: TCD Source Address
	DMA_TCD_SADDR_SADDR_Pos = 0x0        // Position of SADDR field.
	DMA_TCD_SADDR_SADDR_Msk = 0xffffffff // Bit mask of SADDR field.

	// TCD0_SOFF: TCD Signed Source Address Offset
	DMA_TCD_SOFF_SOFF_Pos = 0x0    // Position of SOFF field.
	DMA_TCD_SOFF_SOFF_Msk = 0xffff // Bit mask of SOFF field.

	// TCD0_ATTR: TCD Transfer Attributes
	DMA_TCD_ATTR_DSIZE_Pos = 0x0    // Position of DSIZE field.
	DMA_TCD_ATTR_DSIZE_Msk = 0x7    // Bit mask of DSIZE field.
	DMA_TCD_ATTR_DMOD_Pos  = 0x3    // Position of DMOD field.
	DMA_TCD_ATTR_DMOD_Msk  = 0xf8   // Bit mask of DMOD field.
	DMA_TCD_ATTR_SSIZE_Pos = 0x8    // Position of SSIZE field.
	DMA_TCD_ATTR_SSIZE_Msk = 0x700  // Bit mask of SSIZE field.
	DMA_TCD_ATTR_SSIZE_000 = 0x0    // 8-bit
	DMA_TCD_ATTR_SSIZE_001 = 0x1    // 16-bit
	DMA_TCD_ATTR_SSIZE_010 = 0x2    // 32-bit
	DMA_TCD_ATTR_SSIZE_100 = 0x4    // 16-byte
	DMA_TCD_ATTR_SSIZE_101 = 0x5    // 32-byte
	DMA_TCD_ATTR_SMOD_Pos  = 0xb    // Position of SMOD field.
	DMA_TCD_ATTR_SMOD_Msk  = 0xf800 // Bit mask of SMOD field.
	DMA_TCD_ATTR_SMOD_0    = 0x0    // Source address modulo feature is disabled

	// TCD0_NBYTES_MLNO: TCD Minor Byte Count (Minor Loop Disabled)
	DMA_TCD_NBYTES_MLNO_NBYTES_Pos = 0x0        // Position of NBYTES field.
	DMA_TCD_NBYTES_MLNO_NBYTES_Msk = 0xffffffff // Bit mask of NBYTES field.

	// TCD0_NBYTES_MLOFFNO: TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
	DMA_TCD_NBYTES_MLOFFNO_NBYTES_Pos = 0x0        // Position of NBYTES field.
	DMA_TCD_NBYTES_MLOFFNO_NBYTES_Msk = 0x3fffffff // Bit mask of NBYTES field.
	DMA_TCD_NBYTES_MLOFFNO_DMLOE_Pos  = 0x1e       // Position of DMLOE field.
	DMA_TCD_NBYTES_MLOFFNO_DMLOE_Msk  = 0x40000000 // Bit mask of DMLOE field.
	DMA_TCD_NBYTES_MLOFFNO_DMLOE      = 0x40000000 // Bit DMLOE.
	DMA_TCD_NBYTES_MLOFFNO_DMLOE_0    = 0x0        // The minor loop offset is not applied to the DADDR
	DMA_TCD_NBYTES_MLOFFNO_DMLOE_1    = 0x1        // The minor loop offset is applied to the DADDR
	DMA_TCD_NBYTES_MLOFFNO_SMLOE_Pos  = 0x1f       // Position of SMLOE field.
	DMA_TCD_NBYTES_MLOFFNO_SMLOE_Msk  = 0x80000000 // Bit mask of SMLOE field.
	DMA_TCD_NBYTES_MLOFFNO_SMLOE      = 0x80000000 // Bit SMLOE.
	DMA_TCD_NBYTES_MLOFFNO_SMLOE_0    = 0x0        // The minor loop offset is not applied to the SADDR
	DMA_TCD_NBYTES_MLOFFNO_SMLOE_1    = 0x1        // The minor loop offset is applied to the SADDR

	// TCD0_NBYTES_MLOFFYES: TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
	DMA_TCD_NBYTES_MLOFFYES_NBYTES_Pos = 0x0        // Position of NBYTES field.
	DMA_TCD_NBYTES_MLOFFYES_NBYTES_Msk = 0x3ff      // Bit mask of NBYTES field.
	DMA_TCD_NBYTES_MLOFFYES_MLOFF_Pos  = 0xa        // Position of MLOFF field.
	DMA_TCD_NBYTES_MLOFFYES_MLOFF_Msk  = 0x3ffffc00 // Bit mask of MLOFF field.
	DMA_TCD_NBYTES_MLOFFYES_DMLOE_Pos  = 0x1e       // Position of DMLOE field.
	DMA_TCD_NBYTES_MLOFFYES_DMLOE_Msk  = 0x40000000 // Bit mask of DMLOE field.
	DMA_TCD_NBYTES_MLOFFYES_DMLOE      = 0x40000000 // Bit DMLOE.
	DMA_TCD_NBYTES_MLOFFYES_DMLOE_0    = 0x0        // The minor loop offset is not applied to the DADDR
	DMA_TCD_NBYTES_MLOFFYES_DMLOE_1    = 0x1        // The minor loop offset is applied to the DADDR
	DMA_TCD_NBYTES_MLOFFYES_SMLOE_Pos  = 0x1f       // Position of SMLOE field.
	DMA_TCD_NBYTES_MLOFFYES_SMLOE_Msk  = 0x80000000 // Bit mask of SMLOE field.
	DMA_TCD_NBYTES_MLOFFYES_SMLOE      = 0x80000000 // Bit SMLOE.
	DMA_TCD_NBYTES_MLOFFYES_SMLOE_0    = 0x0        // The minor loop offset is not applied to the SADDR
	DMA_TCD_NBYTES_MLOFFYES_SMLOE_1    = 0x1        // The minor loop offset is applied to the SADDR

	// TCD0_SLAST: TCD Last Source Address Adjustment
	DMA_TCD_SLAST_SLAST_Pos = 0x0        // Position of SLAST field.
	DMA_TCD_SLAST_SLAST_Msk = 0xffffffff // Bit mask of SLAST field.

	// TCD0_DADDR: TCD Destination Address
	DMA_TCD_DADDR_DADDR_Pos = 0x0        // Position of DADDR field.
	DMA_TCD_DADDR_DADDR_Msk = 0xffffffff // Bit mask of DADDR field.

	// TCD0_DOFF: TCD Signed Destination Address Offset
	DMA_TCD_DOFF_DOFF_Pos = 0x0    // Position of DOFF field.
	DMA_TCD_DOFF_DOFF_Msk = 0xffff // Bit mask of DOFF field.

	// TCD0_CITER_ELINKNO: TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
	DMA_TCD_CITER_ELINKNO_CITER_Pos = 0x0    // Position of CITER field.
	DMA_TCD_CITER_ELINKNO_CITER_Msk = 0x7fff // Bit mask of CITER field.
	DMA_TCD_CITER_ELINKNO_ELINK_Pos = 0xf    // Position of ELINK field.
	DMA_TCD_CITER_ELINKNO_ELINK_Msk = 0x8000 // Bit mask of ELINK field.
	DMA_TCD_CITER_ELINKNO_ELINK     = 0x8000 // Bit ELINK.
	DMA_TCD_CITER_ELINKNO_ELINK_0   = 0x0    // The channel-to-channel linking is disabled
	DMA_TCD_CITER_ELINKNO_ELINK_1   = 0x1    // The channel-to-channel linking is enabled

	// TCD0_CITER_ELINKYES: TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
	DMA_TCD_CITER_ELINKYES_CITER_Pos  = 0x0    // Position of CITER field.
	DMA_TCD_CITER_ELINKYES_CITER_Msk  = 0x1ff  // Bit mask of CITER field.
	DMA_TCD_CITER_ELINKYES_LINKCH_Pos = 0x9    // Position of LINKCH field.
	DMA_TCD_CITER_ELINKYES_LINKCH_Msk = 0x1e00 // Bit mask of LINKCH field.
	DMA_TCD_CITER_ELINKYES_ELINK_Pos  = 0xf    // Position of ELINK field.
	DMA_TCD_CITER_ELINKYES_ELINK_Msk  = 0x8000 // Bit mask of ELINK field.
	DMA_TCD_CITER_ELINKYES_ELINK      = 0x8000 // Bit ELINK.
	DMA_TCD_CITER_ELINKYES_ELINK_0    = 0x0    // The channel-to-channel linking is disabled
	DMA_TCD_CITER_ELINKYES_ELINK_1    = 0x1    // The channel-to-channel linking is enabled

	// TCD0_DLASTSGA: TCD Last Destination Address Adjustment/Scatter Gather Address
	DMA_TCD_DLASTSGA_DLASTSGA_Pos = 0x0        // Position of DLASTSGA field.
	DMA_TCD_DLASTSGA_DLASTSGA_Msk = 0xffffffff // Bit mask of DLASTSGA field.

	// TCD0_CSR: TCD Control and Status
	DMA_TCD_CSR_START_Pos       = 0x0    // Position of START field.
	DMA_TCD_CSR_START_Msk       = 0x1    // Bit mask of START field.
	DMA_TCD_CSR_START           = 0x1    // Bit START.
	DMA_TCD_CSR_START_0         = 0x0    // The channel is not explicitly started
	DMA_TCD_CSR_START_1         = 0x1    // The channel is explicitly started via a software initiated service request
	DMA_TCD_CSR_INTMAJOR_Pos    = 0x1    // Position of INTMAJOR field.
	DMA_TCD_CSR_INTMAJOR_Msk    = 0x2    // Bit mask of INTMAJOR field.
	DMA_TCD_CSR_INTMAJOR        = 0x2    // Bit INTMAJOR.
	DMA_TCD_CSR_INTMAJOR_0      = 0x0    // The end-of-major loop interrupt is disabled
	DMA_TCD_CSR_INTMAJOR_1      = 0x1    // The end-of-major loop interrupt is enabled
	DMA_TCD_CSR_INTHALF_Pos     = 0x2    // Position of INTHALF field.
	DMA_TCD_CSR_INTHALF_Msk     = 0x4    // Bit mask of INTHALF field.
	DMA_TCD_CSR_INTHALF         = 0x4    // Bit INTHALF.
	DMA_TCD_CSR_INTHALF_0       = 0x0    // The half-point interrupt is disabled
	DMA_TCD_CSR_INTHALF_1       = 0x1    // The half-point interrupt is enabled
	DMA_TCD_CSR_DREQ_Pos        = 0x3    // Position of DREQ field.
	DMA_TCD_CSR_DREQ_Msk        = 0x8    // Bit mask of DREQ field.
	DMA_TCD_CSR_DREQ            = 0x8    // Bit DREQ.
	DMA_TCD_CSR_DREQ_0          = 0x0    // The channel's ERQ bit is not affected
	DMA_TCD_CSR_DREQ_1          = 0x1    // The channel's ERQ bit is cleared when the major loop is complete
	DMA_TCD_CSR_ESG_Pos         = 0x4    // Position of ESG field.
	DMA_TCD_CSR_ESG_Msk         = 0x10   // Bit mask of ESG field.
	DMA_TCD_CSR_ESG             = 0x10   // Bit ESG.
	DMA_TCD_CSR_ESG_0           = 0x0    // The current channel's TCD is normal format.
	DMA_TCD_CSR_ESG_1           = 0x1    // The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
	DMA_TCD_CSR_MAJORELINK_Pos  = 0x5    // Position of MAJORELINK field.
	DMA_TCD_CSR_MAJORELINK_Msk  = 0x20   // Bit mask of MAJORELINK field.
	DMA_TCD_CSR_MAJORELINK      = 0x20   // Bit MAJORELINK.
	DMA_TCD_CSR_MAJORELINK_0    = 0x0    // The channel-to-channel linking is disabled
	DMA_TCD_CSR_MAJORELINK_1    = 0x1    // The channel-to-channel linking is enabled
	DMA_TCD_CSR_ACTIVE_Pos      = 0x6    // Position of ACTIVE field.
	DMA_TCD_CSR_ACTIVE_Msk      = 0x40   // Bit mask of ACTIVE field.
	DMA_TCD_CSR_ACTIVE          = 0x40   // Bit ACTIVE.
	DMA_TCD_CSR_DONE_Pos        = 0x7    // Position of DONE field.
	DMA_TCD_CSR_DONE_Msk        = 0x80   // Bit mask of DONE field.
	DMA_TCD_CSR_DONE            = 0x80   // Bit DONE.
	DMA_TCD_CSR_MAJORLINKCH_Pos = 0x8    // Position of MAJORLINKCH field.
	DMA_TCD_CSR_MAJORLINKCH_Msk = 0xf00  // Bit mask of MAJORLINKCH field.
	DMA_TCD_CSR_BWC_Pos         = 0xe    // Position of BWC field.
	DMA_TCD_CSR_BWC_Msk         = 0xc000 // Bit mask of BWC field.
	DMA_TCD_CSR_BWC_00          = 0x0    // No eDMA engine stalls
	DMA_TCD_CSR_BWC_10          = 0x2    // eDMA engine stalls for 4 cycles after each r/w
	DMA_TCD_CSR_BWC_11          = 0x3    // eDMA engine stalls for 8 cycles after each r/w

	// TCD0_BITER_ELINKNO: TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
	DMA_TCD_BITER_ELINKNO_BITER_Pos = 0x0    // Position of BITER field.
	DMA_TCD_BITER_ELINKNO_BITER_Msk = 0x7fff // Bit mask of BITER field.
	DMA_TCD_BITER_ELINKNO_ELINK_Pos = 0xf    // Position of ELINK field.
	DMA_TCD_BITER_ELINKNO_ELINK_Msk = 0x8000 // Bit mask of ELINK field.
	DMA_TCD_BITER_ELINKNO_ELINK     = 0x8000 // Bit ELINK.
	DMA_TCD_BITER_ELINKNO_ELINK_0   = 0x0    // The channel-to-channel linking is disabled
	DMA_TCD_BITER_ELINKNO_ELINK_1   = 0x1    // The channel-to-channel linking is enabled

	// TCD0_BITER_ELINKYES: TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
	DMA_TCD_BITER_ELINKYES_BITER_Pos  = 0x0    // Position of BITER field.
	DMA_TCD_BITER_ELINKYES_BITER_Msk  = 0x1ff  // Bit mask of BITER field.
	DMA_TCD_BITER_ELINKYES_LINKCH_Pos = 0x9    // Position of LINKCH field.
	DMA_TCD_BITER_ELINKYES_LINKCH_Msk = 0x1e00 // Bit mask of LINKCH field.
	DMA_TCD_BITER_ELINKYES_ELINK_Pos  = 0xf    // Position of ELINK field.
	DMA_TCD_BITER_ELINKYES_ELINK_Msk  = 0x8000 // Bit mask of ELINK field.
	DMA_TCD_BITER_ELINKYES_ELINK      = 0x8000 // Bit ELINK.
	DMA_TCD_BITER_ELINKYES_ELINK_0    = 0x0    // The channel-to-channel linking is disabled
	DMA_TCD_BITER_ELINKYES_ELINK_1    = 0x1    // The channel-to-channel linking is enabled
)

// Bitfields for FMC: Flash Memory Controller
const (
	// PFAPR: Flash Access Protection Register
	FMC_PFAPR_M0AP_Pos  = 0x0      // Position of M0AP field.
	FMC_PFAPR_M0AP_Msk  = 0x3      // Bit mask of M0AP field.
	FMC_PFAPR_M0AP_00   = 0x0      // No access may be performed by this master
	FMC_PFAPR_M0AP_01   = 0x1      // Only read accesses may be performed by this master
	FMC_PFAPR_M0AP_10   = 0x2      // Only write accesses may be performed by this master
	FMC_PFAPR_M0AP_11   = 0x3      // Both read and write accesses may be performed by this master
	FMC_PFAPR_M1AP_Pos  = 0x2      // Position of M1AP field.
	FMC_PFAPR_M1AP_Msk  = 0xc      // Bit mask of M1AP field.
	FMC_PFAPR_M1AP_00   = 0x0      // No access may be performed by this master
	FMC_PFAPR_M1AP_01   = 0x1      // Only read accesses may be performed by this master
	FMC_PFAPR_M1AP_10   = 0x2      // Only write accesses may be performed by this master
	FMC_PFAPR_M1AP_11   = 0x3      // Both read and write accesses may be performed by this master
	FMC_PFAPR_M2AP_Pos  = 0x4      // Position of M2AP field.
	FMC_PFAPR_M2AP_Msk  = 0x30     // Bit mask of M2AP field.
	FMC_PFAPR_M2AP_00   = 0x0      // No access may be performed by this master
	FMC_PFAPR_M2AP_01   = 0x1      // Only read accesses may be performed by this master
	FMC_PFAPR_M2AP_10   = 0x2      // Only write accesses may be performed by this master
	FMC_PFAPR_M2AP_11   = 0x3      // Both read and write accesses may be performed by this master
	FMC_PFAPR_M3AP_Pos  = 0x6      // Position of M3AP field.
	FMC_PFAPR_M3AP_Msk  = 0xc0     // Bit mask of M3AP field.
	FMC_PFAPR_M3AP_00   = 0x0      // No access may be performed by this master
	FMC_PFAPR_M3AP_01   = 0x1      // Only read accesses may be performed by this master
	FMC_PFAPR_M3AP_10   = 0x2      // Only write accesses may be performed by this master
	FMC_PFAPR_M3AP_11   = 0x3      // Both read and write accesses may be performed by this master
	FMC_PFAPR_M4AP_Pos  = 0x8      // Position of M4AP field.
	FMC_PFAPR_M4AP_Msk  = 0x300    // Bit mask of M4AP field.
	FMC_PFAPR_M4AP_00   = 0x0      // No access may be performed by this master
	FMC_PFAPR_M4AP_01   = 0x1      // Only read accesses may be performed by this master
	FMC_PFAPR_M4AP_10   = 0x2      // Only write accesses may be performed by this master
	FMC_PFAPR_M4AP_11   = 0x3      // Both read and write accesses may be performed by this master
	FMC_PFAPR_M5AP_Pos  = 0xa      // Position of M5AP field.
	FMC_PFAPR_M5AP_Msk  = 0xc00    // Bit mask of M5AP field.
	FMC_PFAPR_M5AP_00   = 0x0      // No access may be performed by this master
	FMC_PFAPR_M5AP_01   = 0x1      // Only read accesses may be performed by this master
	FMC_PFAPR_M5AP_10   = 0x2      // Only write accesses may be performed by this master
	FMC_PFAPR_M5AP_11   = 0x3      // Both read and write accesses may be performed by this master
	FMC_PFAPR_M6AP_Pos  = 0xc      // Position of M6AP field.
	FMC_PFAPR_M6AP_Msk  = 0x3000   // Bit mask of M6AP field.
	FMC_PFAPR_M6AP_00   = 0x0      // No access may be performed by this master
	FMC_PFAPR_M6AP_01   = 0x1      // Only read accesses may be performed by this master
	FMC_PFAPR_M6AP_10   = 0x2      // Only write accesses may be performed by this master
	FMC_PFAPR_M6AP_11   = 0x3      // Both read and write accesses may be performed by this master
	FMC_PFAPR_M7AP_Pos  = 0xe      // Position of M7AP field.
	FMC_PFAPR_M7AP_Msk  = 0xc000   // Bit mask of M7AP field.
	FMC_PFAPR_M7AP_00   = 0x0      // No access may be performed by this master.
	FMC_PFAPR_M7AP_01   = 0x1      // Only read accesses may be performed by this master.
	FMC_PFAPR_M7AP_10   = 0x2      // Only write accesses may be performed by this master.
	FMC_PFAPR_M7AP_11   = 0x3      // Both read and write accesses may be performed by this master.
	FMC_PFAPR_M0PFD_Pos = 0x10     // Position of M0PFD field.
	FMC_PFAPR_M0PFD_Msk = 0x10000  // Bit mask of M0PFD field.
	FMC_PFAPR_M0PFD     = 0x10000  // Bit M0PFD.
	FMC_PFAPR_M0PFD_0   = 0x0      // Prefetching for this master is enabled.
	FMC_PFAPR_M0PFD_1   = 0x1      // Prefetching for this master is disabled.
	FMC_PFAPR_M1PFD_Pos = 0x11     // Position of M1PFD field.
	FMC_PFAPR_M1PFD_Msk = 0x20000  // Bit mask of M1PFD field.
	FMC_PFAPR_M1PFD     = 0x20000  // Bit M1PFD.
	FMC_PFAPR_M1PFD_0   = 0x0      // Prefetching for this master is enabled.
	FMC_PFAPR_M1PFD_1   = 0x1      // Prefetching for this master is disabled.
	FMC_PFAPR_M2PFD_Pos = 0x12     // Position of M2PFD field.
	FMC_PFAPR_M2PFD_Msk = 0x40000  // Bit mask of M2PFD field.
	FMC_PFAPR_M2PFD     = 0x40000  // Bit M2PFD.
	FMC_PFAPR_M2PFD_0   = 0x0      // Prefetching for this master is enabled.
	FMC_PFAPR_M2PFD_1   = 0x1      // Prefetching for this master is disabled.
	FMC_PFAPR_M3PFD_Pos = 0x13     // Position of M3PFD field.
	FMC_PFAPR_M3PFD_Msk = 0x80000  // Bit mask of M3PFD field.
	FMC_PFAPR_M3PFD     = 0x80000  // Bit M3PFD.
	FMC_PFAPR_M3PFD_0   = 0x0      // Prefetching for this master is enabled.
	FMC_PFAPR_M3PFD_1   = 0x1      // Prefetching for this master is disabled.
	FMC_PFAPR_M4PFD_Pos = 0x14     // Position of M4PFD field.
	FMC_PFAPR_M4PFD_Msk = 0x100000 // Bit mask of M4PFD field.
	FMC_PFAPR_M4PFD     = 0x100000 // Bit M4PFD.
	FMC_PFAPR_M4PFD_0   = 0x0      // Prefetching for this master is enabled.
	FMC_PFAPR_M4PFD_1   = 0x1      // Prefetching for this master is disabled.
	FMC_PFAPR_M5PFD_Pos = 0x15     // Position of M5PFD field.
	FMC_PFAPR_M5PFD_Msk = 0x200000 // Bit mask of M5PFD field.
	FMC_PFAPR_M5PFD     = 0x200000 // Bit M5PFD.
	FMC_PFAPR_M5PFD_0   = 0x0      // Prefetching for this master is enabled.
	FMC_PFAPR_M5PFD_1   = 0x1      // Prefetching for this master is disabled.
	FMC_PFAPR_M6PFD_Pos = 0x16     // Position of M6PFD field.
	FMC_PFAPR_M6PFD_Msk = 0x400000 // Bit mask of M6PFD field.
	FMC_PFAPR_M6PFD     = 0x400000 // Bit M6PFD.
	FMC_PFAPR_M6PFD_0   = 0x0      // Prefetching for this master is enabled.
	FMC_PFAPR_M6PFD_1   = 0x1      // Prefetching for this master is disabled.
	FMC_PFAPR_M7PFD_Pos = 0x17     // Position of M7PFD field.
	FMC_PFAPR_M7PFD_Msk = 0x800000 // Bit mask of M7PFD field.
	FMC_PFAPR_M7PFD     = 0x800000 // Bit M7PFD.
	FMC_PFAPR_M7PFD_0   = 0x0      // Prefetching for this master is enabled.
	FMC_PFAPR_M7PFD_1   = 0x1      // Prefetching for this master is disabled.

	// PFB0CR: Flash Bank 0 Control Register
	FMC_PFB0CR_B0SEBE_Pos   = 0x0        // Position of B0SEBE field.
	FMC_PFB0CR_B0SEBE_Msk   = 0x1        // Bit mask of B0SEBE field.
	FMC_PFB0CR_B0SEBE       = 0x1        // Bit B0SEBE.
	FMC_PFB0CR_B0SEBE_0     = 0x0        // Single entry buffer is disabled.
	FMC_PFB0CR_B0SEBE_1     = 0x1        // Single entry buffer is enabled.
	FMC_PFB0CR_B0IPE_Pos    = 0x1        // Position of B0IPE field.
	FMC_PFB0CR_B0IPE_Msk    = 0x2        // Bit mask of B0IPE field.
	FMC_PFB0CR_B0IPE        = 0x2        // Bit B0IPE.
	FMC_PFB0CR_B0IPE_0      = 0x0        // Do not prefetch in response to instruction fetches.
	FMC_PFB0CR_B0IPE_1      = 0x1        // Enable prefetches in response to instruction fetches.
	FMC_PFB0CR_B0DPE_Pos    = 0x2        // Position of B0DPE field.
	FMC_PFB0CR_B0DPE_Msk    = 0x4        // Bit mask of B0DPE field.
	FMC_PFB0CR_B0DPE        = 0x4        // Bit B0DPE.
	FMC_PFB0CR_B0DPE_0      = 0x0        // Do not prefetch in response to data references.
	FMC_PFB0CR_B0DPE_1      = 0x1        // Enable prefetches in response to data references.
	FMC_PFB0CR_B0ICE_Pos    = 0x3        // Position of B0ICE field.
	FMC_PFB0CR_B0ICE_Msk    = 0x8        // Bit mask of B0ICE field.
	FMC_PFB0CR_B0ICE        = 0x8        // Bit B0ICE.
	FMC_PFB0CR_B0ICE_0      = 0x0        // Do not cache instruction fetches.
	FMC_PFB0CR_B0ICE_1      = 0x1        // Cache instruction fetches.
	FMC_PFB0CR_B0DCE_Pos    = 0x4        // Position of B0DCE field.
	FMC_PFB0CR_B0DCE_Msk    = 0x10       // Bit mask of B0DCE field.
	FMC_PFB0CR_B0DCE        = 0x10       // Bit B0DCE.
	FMC_PFB0CR_B0DCE_0      = 0x0        // Do not cache data references.
	FMC_PFB0CR_B0DCE_1      = 0x1        // Cache data references.
	FMC_PFB0CR_CRC_Pos      = 0x5        // Position of CRC field.
	FMC_PFB0CR_CRC_Msk      = 0xe0       // Bit mask of CRC field.
	FMC_PFB0CR_CRC_000      = 0x0        // LRU replacement algorithm per set across all four ways
	FMC_PFB0CR_CRC_010      = 0x2        // Independent LRU with ways [0-1] for ifetches, [2-3] for data
	FMC_PFB0CR_CRC_011      = 0x3        // Independent LRU with ways [0-2] for ifetches, [3] for data
	FMC_PFB0CR_B0MW_Pos     = 0x11       // Position of B0MW field.
	FMC_PFB0CR_B0MW_Msk     = 0x60000    // Bit mask of B0MW field.
	FMC_PFB0CR_B0MW_00      = 0x0        // 32 bits
	FMC_PFB0CR_B0MW_01      = 0x1        // 64 bits
	FMC_PFB0CR_S_B_INV_Pos  = 0x13       // Position of S_B_INV field.
	FMC_PFB0CR_S_B_INV_Msk  = 0x80000    // Bit mask of S_B_INV field.
	FMC_PFB0CR_S_B_INV      = 0x80000    // Bit S_B_INV.
	FMC_PFB0CR_S_B_INV_0    = 0x0        // Speculation buffer and single entry buffer are not affected.
	FMC_PFB0CR_S_B_INV_1    = 0x1        // Invalidate (clear) speculation buffer and single entry buffer.
	FMC_PFB0CR_CINV_WAY_Pos = 0x14       // Position of CINV_WAY field.
	FMC_PFB0CR_CINV_WAY_Msk = 0xf00000   // Bit mask of CINV_WAY field.
	FMC_PFB0CR_CINV_WAY_0   = 0x0        // No cache way invalidation for the corresponding cache
	FMC_PFB0CR_CINV_WAY_1   = 0x1        // Invalidate cache way for the corresponding cache: clear the tag, data, and vld bits of ways selected
	FMC_PFB0CR_CLCK_WAY_Pos = 0x18       // Position of CLCK_WAY field.
	FMC_PFB0CR_CLCK_WAY_Msk = 0xf000000  // Bit mask of CLCK_WAY field.
	FMC_PFB0CR_CLCK_WAY_0   = 0x0        // Cache way is unlocked and may be displaced
	FMC_PFB0CR_CLCK_WAY_1   = 0x1        // Cache way is locked and its contents are not displaced
	FMC_PFB0CR_B0RWSC_Pos   = 0x1c       // Position of B0RWSC field.
	FMC_PFB0CR_B0RWSC_Msk   = 0xf0000000 // Bit mask of B0RWSC field.

	// PFB1CR: Flash Bank 1 Control Register
	FMC_PFB1CR_B1SEBE_Pos = 0x0        // Position of B1SEBE field.
	FMC_PFB1CR_B1SEBE_Msk = 0x1        // Bit mask of B1SEBE field.
	FMC_PFB1CR_B1SEBE     = 0x1        // Bit B1SEBE.
	FMC_PFB1CR_B1SEBE_0   = 0x0        // Single entry buffer is disabled.
	FMC_PFB1CR_B1SEBE_1   = 0x1        // Single entry buffer is enabled.
	FMC_PFB1CR_B1IPE_Pos  = 0x1        // Position of B1IPE field.
	FMC_PFB1CR_B1IPE_Msk  = 0x2        // Bit mask of B1IPE field.
	FMC_PFB1CR_B1IPE      = 0x2        // Bit B1IPE.
	FMC_PFB1CR_B1IPE_0    = 0x0        // Do not prefetch in response to instruction fetches.
	FMC_PFB1CR_B1IPE_1    = 0x1        // Enable prefetches in response to instruction fetches.
	FMC_PFB1CR_B1DPE_Pos  = 0x2        // Position of B1DPE field.
	FMC_PFB1CR_B1DPE_Msk  = 0x4        // Bit mask of B1DPE field.
	FMC_PFB1CR_B1DPE      = 0x4        // Bit B1DPE.
	FMC_PFB1CR_B1DPE_0    = 0x0        // Do not prefetch in response to data references.
	FMC_PFB1CR_B1DPE_1    = 0x1        // Enable prefetches in response to data references.
	FMC_PFB1CR_B1ICE_Pos  = 0x3        // Position of B1ICE field.
	FMC_PFB1CR_B1ICE_Msk  = 0x8        // Bit mask of B1ICE field.
	FMC_PFB1CR_B1ICE      = 0x8        // Bit B1ICE.
	FMC_PFB1CR_B1ICE_0    = 0x0        // Do not cache instruction fetches.
	FMC_PFB1CR_B1ICE_1    = 0x1        // Cache instruction fetches.
	FMC_PFB1CR_B1DCE_Pos  = 0x4        // Position of B1DCE field.
	FMC_PFB1CR_B1DCE_Msk  = 0x10       // Bit mask of B1DCE field.
	FMC_PFB1CR_B1DCE      = 0x10       // Bit B1DCE.
	FMC_PFB1CR_B1DCE_0    = 0x0        // Do not cache data references.
	FMC_PFB1CR_B1DCE_1    = 0x1        // Cache data references.
	FMC_PFB1CR_B1MW_Pos   = 0x11       // Position of B1MW field.
	FMC_PFB1CR_B1MW_Msk   = 0x60000    // Bit mask of B1MW field.
	FMC_PFB1CR_B1MW_00    = 0x0        // 32 bits
	FMC_PFB1CR_B1MW_01    = 0x1        // 64 bits
	FMC_PFB1CR_B1RWSC_Pos = 0x1c       // Position of B1RWSC field.
	FMC_PFB1CR_B1RWSC_Msk = 0xf0000000 // Bit mask of B1RWSC field.

	// TAGVDW0S0: Cache Tag Storage
	FMC_TAGVDW0S_VALID_Pos = 0x0     // Position of VALID field.
	FMC_TAGVDW0S_VALID_Msk = 0x1     // Bit mask of VALID field.
	FMC_TAGVDW0S_VALID     = 0x1     // Bit VALID.
	FMC_TAGVDW0S_TAG_Pos   = 0x5     // Position of TAG field.
	FMC_TAGVDW0S_TAG_Msk   = 0x7ffe0 // Bit mask of TAG field.

	// TAGVDW1S0: Cache Tag Storage
	FMC_TAGVDW1S_VALID_Pos = 0x0     // Position of VALID field.
	FMC_TAGVDW1S_VALID_Msk = 0x1     // Bit mask of VALID field.
	FMC_TAGVDW1S_VALID     = 0x1     // Bit VALID.
	FMC_TAGVDW1S_TAG_Pos   = 0x5     // Position of TAG field.
	FMC_TAGVDW1S_TAG_Msk   = 0x7ffe0 // Bit mask of TAG field.

	// TAGVDW2S0: Cache Tag Storage
	FMC_TAGVDW2S_VALID_Pos = 0x0     // Position of VALID field.
	FMC_TAGVDW2S_VALID_Msk = 0x1     // Bit mask of VALID field.
	FMC_TAGVDW2S_VALID     = 0x1     // Bit VALID.
	FMC_TAGVDW2S_TAG_Pos   = 0x5     // Position of TAG field.
	FMC_TAGVDW2S_TAG_Msk   = 0x7ffe0 // Bit mask of TAG field.

	// TAGVDW3S0: Cache Tag Storage
	FMC_TAGVDW3S_VALID_Pos = 0x0     // Position of VALID field.
	FMC_TAGVDW3S_VALID_Msk = 0x1     // Bit mask of VALID field.
	FMC_TAGVDW3S_VALID     = 0x1     // Bit VALID.
	FMC_TAGVDW3S_TAG_Pos   = 0x5     // Position of TAG field.
	FMC_TAGVDW3S_TAG_Msk   = 0x7ffe0 // Bit mask of TAG field.

	// DATAW0S0U: Cache Data Storage (upper word)
	FMC_DATAW0SU_DATA_Pos = 0x0        // Position of DATA field.
	FMC_DATAW0SU_DATA_Msk = 0xffffffff // Bit mask of DATA field.

	// DATAW0S0L: Cache Data Storage (lower word)
	FMC_DATAW0SL_DATA_Pos = 0x0        // Position of DATA field.
	FMC_DATAW0SL_DATA_Msk = 0xffffffff // Bit mask of DATA field.

	// DATAW1S0U: Cache Data Storage (upper word)
	FMC_DATAW1SU_DATA_Pos = 0x0        // Position of DATA field.
	FMC_DATAW1SU_DATA_Msk = 0xffffffff // Bit mask of DATA field.

	// DATAW1S0L: Cache Data Storage (lower word)
	FMC_DATAW1SL_DATA_Pos = 0x0        // Position of DATA field.
	FMC_DATAW1SL_DATA_Msk = 0xffffffff // Bit mask of DATA field.

	// DATAW2S0U: Cache Data Storage (upper word)
	FMC_DATAW2SU_DATA_Pos = 0x0        // Position of DATA field.
	FMC_DATAW2SU_DATA_Msk = 0xffffffff // Bit mask of DATA field.

	// DATAW2S0L: Cache Data Storage (lower word)
	FMC_DATAW2SL_DATA_Pos = 0x0        // Position of DATA field.
	FMC_DATAW2SL_DATA_Msk = 0xffffffff // Bit mask of DATA field.

	// DATAW3S0U: Cache Data Storage (upper word)
	FMC_DATAW3SU_DATA_Pos = 0x0        // Position of DATA field.
	FMC_DATAW3SU_DATA_Msk = 0xffffffff // Bit mask of DATA field.

	// DATAW3S0L: Cache Data Storage (lower word)
	FMC_DATAW3SL_DATA_Pos = 0x0        // Position of DATA field.
	FMC_DATAW3SL_DATA_Msk = 0xffffffff // Bit mask of DATA field.
)

// Bitfields for FTFA: Flash Memory Interface
const (
	// FSTAT: Flash Status Register
	FTFA_FSTAT_MGSTAT0_Pos  = 0x0  // Position of MGSTAT0 field.
	FTFA_FSTAT_MGSTAT0_Msk  = 0x1  // Bit mask of MGSTAT0 field.
	FTFA_FSTAT_MGSTAT0      = 0x1  // Bit MGSTAT0.
	FTFA_FSTAT_FPVIOL_Pos   = 0x4  // Position of FPVIOL field.
	FTFA_FSTAT_FPVIOL_Msk   = 0x10 // Bit mask of FPVIOL field.
	FTFA_FSTAT_FPVIOL       = 0x10 // Bit FPVIOL.
	FTFA_FSTAT_FPVIOL_0     = 0x0  // No protection violation detected
	FTFA_FSTAT_FPVIOL_1     = 0x1  // Protection violation detected
	FTFA_FSTAT_ACCERR_Pos   = 0x5  // Position of ACCERR field.
	FTFA_FSTAT_ACCERR_Msk   = 0x20 // Bit mask of ACCERR field.
	FTFA_FSTAT_ACCERR       = 0x20 // Bit ACCERR.
	FTFA_FSTAT_ACCERR_0     = 0x0  // No access error detected
	FTFA_FSTAT_ACCERR_1     = 0x1  // Access error detected
	FTFA_FSTAT_RDCOLERR_Pos = 0x6  // Position of RDCOLERR field.
	FTFA_FSTAT_RDCOLERR_Msk = 0x40 // Bit mask of RDCOLERR field.
	FTFA_FSTAT_RDCOLERR     = 0x40 // Bit RDCOLERR.
	FTFA_FSTAT_RDCOLERR_0   = 0x0  // No collision error detected
	FTFA_FSTAT_RDCOLERR_1   = 0x1  // Collision error detected
	FTFA_FSTAT_CCIF_Pos     = 0x7  // Position of CCIF field.
	FTFA_FSTAT_CCIF_Msk     = 0x80 // Bit mask of CCIF field.
	FTFA_FSTAT_CCIF         = 0x80 // Bit CCIF.
	FTFA_FSTAT_CCIF_0       = 0x0  // Flash command in progress
	FTFA_FSTAT_CCIF_1       = 0x1  // Flash command has completed

	// FCNFG: Flash Configuration Register
	FTFA_FCNFG_ERSSUSP_Pos  = 0x4  // Position of ERSSUSP field.
	FTFA_FCNFG_ERSSUSP_Msk  = 0x10 // Bit mask of ERSSUSP field.
	FTFA_FCNFG_ERSSUSP      = 0x10 // Bit ERSSUSP.
	FTFA_FCNFG_ERSSUSP_0    = 0x0  // No suspend requested
	FTFA_FCNFG_ERSSUSP_1    = 0x1  // Suspend the current Erase Flash Sector command execution.
	FTFA_FCNFG_ERSAREQ_Pos  = 0x5  // Position of ERSAREQ field.
	FTFA_FCNFG_ERSAREQ_Msk  = 0x20 // Bit mask of ERSAREQ field.
	FTFA_FCNFG_ERSAREQ      = 0x20 // Bit ERSAREQ.
	FTFA_FCNFG_ERSAREQ_0    = 0x0  // No request or request complete
	FTFA_FCNFG_ERSAREQ_1    = 0x1  // Request to: run the Erase All Blocks command, verify the erased state, program the security byte in the Flash Configuration Field to the unsecure state, and release MCU security by setting the FSEC[SEC] field to the unsecure state.
	FTFA_FCNFG_RDCOLLIE_Pos = 0x6  // Position of RDCOLLIE field.
	FTFA_FCNFG_RDCOLLIE_Msk = 0x40 // Bit mask of RDCOLLIE field.
	FTFA_FCNFG_RDCOLLIE     = 0x40 // Bit RDCOLLIE.
	FTFA_FCNFG_RDCOLLIE_0   = 0x0  // Read collision error interrupt disabled
	FTFA_FCNFG_RDCOLLIE_1   = 0x1  // Read collision error interrupt enabled. An interrupt request is generated whenever a flash memory read collision error is detected (see the description of FSTAT[RDCOLERR]).
	FTFA_FCNFG_CCIE_Pos     = 0x7  // Position of CCIE field.
	FTFA_FCNFG_CCIE_Msk     = 0x80 // Bit mask of CCIE field.
	FTFA_FCNFG_CCIE         = 0x80 // Bit CCIE.
	FTFA_FCNFG_CCIE_0       = 0x0  // Command complete interrupt disabled
	FTFA_FCNFG_CCIE_1       = 0x1  // Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set.

	// FSEC: Flash Security Register
	FTFA_FSEC_SEC_Pos    = 0x0  // Position of SEC field.
	FTFA_FSEC_SEC_Msk    = 0x3  // Bit mask of SEC field.
	FTFA_FSEC_SEC_00     = 0x0  // MCU security status is secure.
	FTFA_FSEC_SEC_01     = 0x1  // MCU security status is secure.
	FTFA_FSEC_SEC_10     = 0x2  // MCU security status is unsecure. (The standard shipping condition of the flash memory module is unsecure.)
	FTFA_FSEC_SEC_11     = 0x3  // MCU security status is secure.
	FTFA_FSEC_FSLACC_Pos = 0x2  // Position of FSLACC field.
	FTFA_FSEC_FSLACC_Msk = 0xc  // Bit mask of FSLACC field.
	FTFA_FSEC_FSLACC_00  = 0x0  // Freescale factory access granted
	FTFA_FSEC_FSLACC_01  = 0x1  // Freescale factory access denied
	FTFA_FSEC_FSLACC_10  = 0x2  // Freescale factory access denied
	FTFA_FSEC_FSLACC_11  = 0x3  // Freescale factory access granted
	FTFA_FSEC_MEEN_Pos   = 0x4  // Position of MEEN field.
	FTFA_FSEC_MEEN_Msk   = 0x30 // Bit mask of MEEN field.
	FTFA_FSEC_MEEN_00    = 0x0  // Mass erase is enabled
	FTFA_FSEC_MEEN_01    = 0x1  // Mass erase is enabled
	FTFA_FSEC_MEEN_10    = 0x2  // Mass erase is disabled
	FTFA_FSEC_MEEN_11    = 0x3  // Mass erase is enabled
	FTFA_FSEC_KEYEN_Pos  = 0x6  // Position of KEYEN field.
	FTFA_FSEC_KEYEN_Msk  = 0xc0 // Bit mask of KEYEN field.
	FTFA_FSEC_KEYEN_00   = 0x0  // Backdoor key access disabled
	FTFA_FSEC_KEYEN_01   = 0x1  // Backdoor key access disabled (preferred KEYEN state to disable backdoor key access)
	FTFA_FSEC_KEYEN_10   = 0x2  // Backdoor key access enabled
	FTFA_FSEC_KEYEN_11   = 0x3  // Backdoor key access disabled

	// FOPT: Flash Option Register
	FTFA_FOPT_OPT_Pos = 0x0  // Position of OPT field.
	FTFA_FOPT_OPT_Msk = 0xff // Bit mask of OPT field.

	// FCCOB3: Flash Common Command Object Registers
	FTFA_FCCOB_CCOBn_Pos = 0x0  // Position of CCOBn field.
	FTFA_FCCOB_CCOBn_Msk = 0xff // Bit mask of CCOBn field.

	// FPROT3: Program Flash Protection Registers
	FTFA_FPROT_PROT_Pos = 0x0  // Position of PROT field.
	FTFA_FPROT_PROT_Msk = 0xff // Bit mask of PROT field.
	FTFA_FPROT_PROT_0   = 0x0  // Program flash region is protected.
	FTFA_FPROT_PROT_1   = 0x1  // Program flash region is not protected

	// XACCH3: Execute-only Access Registers
	FTFA_XACC_XA_Pos = 0x0  // Position of XA field.
	FTFA_XACC_XA_Msk = 0xff // Bit mask of XA field.
	FTFA_XACC_XA_0   = 0x0  // Associated segment is accessible in execute mode only (as an instruction fetch)
	FTFA_XACC_XA_1   = 0x1  // Associated segment is accessible as data or in execute mode

	// SACCH3: Supervisor-only Access Registers
	FTFA_SACC_SA_Pos = 0x0  // Position of SA field.
	FTFA_SACC_SA_Msk = 0xff // Bit mask of SA field.
	FTFA_SACC_SA_0   = 0x0  // Associated segment is accessible in supervisor mode only
	FTFA_SACC_SA_1   = 0x1  // Associated segment is accessible in user or supervisor mode

	// FACSS: Flash Access Segment Size Register
	FTFA_FACSS_SGSIZE_Pos = 0x0  // Position of SGSIZE field.
	FTFA_FACSS_SGSIZE_Msk = 0xff // Bit mask of SGSIZE field.

	// FACSN: Flash Access Segment Number Register
	FTFA_FACSN_NUMSG_Pos     = 0x0  // Position of NUMSG field.
	FTFA_FACSN_NUMSG_Msk     = 0xff // Bit mask of NUMSG field.
	FTFA_FACSN_NUMSG_100000  = 0x20 // Program flash memory is divided into 32 segments (64 Kbytes, 128 Kbytes)
	FTFA_FACSN_NUMSG_101000  = 0x28 // Program flash memory is divided into 40 segments (160 Kbytes)
	FTFA_FACSN_NUMSG_1000000 = 0x40 // Program flash memory is divided into 64 segments (256 Kbytes, 512 Kbytes)
)

// Bitfields for DMAMUX: DMA channel multiplexor
const (
	// CHCFG0: Channel Configuration register
	DMAMUX_CHCFG_SOURCE_Pos = 0x0  // Position of SOURCE field.
	DMAMUX_CHCFG_SOURCE_Msk = 0x3f // Bit mask of SOURCE field.
	DMAMUX_CHCFG_SOURCE_0   = 0x0  // Disable_Signal
	DMAMUX_CHCFG_SOURCE_2   = 0x2  // UART0_Rx_Signal
	DMAMUX_CHCFG_SOURCE_3   = 0x3  // UART0_Tx_Signal
	DMAMUX_CHCFG_SOURCE_4   = 0x4  // UART1_Rx_Signal
	DMAMUX_CHCFG_SOURCE_5   = 0x5  // UART1_Tx_Signal
	DMAMUX_CHCFG_SOURCE_6   = 0x6  // UART2_Rx_Signal
	DMAMUX_CHCFG_SOURCE_7   = 0x7  // UART2_Tx_Signal
	DMAMUX_CHCFG_SOURCE_12  = 0xc  // I2S0_Rx_Signal
	DMAMUX_CHCFG_SOURCE_13  = 0xd  // I2S0_Tx_Signal
	DMAMUX_CHCFG_SOURCE_14  = 0xe  // SPI0_Rx_Signal
	DMAMUX_CHCFG_SOURCE_15  = 0xf  // SPI0_Tx_Signal
	DMAMUX_CHCFG_SOURCE_16  = 0x10 // SPI1_Signal
	DMAMUX_CHCFG_SOURCE_18  = 0x12 // I2C0_Signal
	DMAMUX_CHCFG_SOURCE_19  = 0x13 // I2C1_Signal
	DMAMUX_CHCFG_SOURCE_20  = 0x14 // FTM0_Channel0_Signal
	DMAMUX_CHCFG_SOURCE_21  = 0x15 // FTM0_Channel1_Signal
	DMAMUX_CHCFG_SOURCE_22  = 0x16 // FTM0_Channel2_Signal
	DMAMUX_CHCFG_SOURCE_23  = 0x17 // FTM0_Channel3_Signal
	DMAMUX_CHCFG_SOURCE_24  = 0x18 // FTM0_Channel4_Signal
	DMAMUX_CHCFG_SOURCE_25  = 0x19 // FTM0_Channel5_Signal
	DMAMUX_CHCFG_SOURCE_26  = 0x1a // FTM0_Channel6_Signal
	DMAMUX_CHCFG_SOURCE_27  = 0x1b // FTM0_Channel7_Signal
	DMAMUX_CHCFG_SOURCE_28  = 0x1c // FTM1_Channel0_Signal
	DMAMUX_CHCFG_SOURCE_29  = 0x1d // FTM1_Channel1_Signal
	DMAMUX_CHCFG_SOURCE_30  = 0x1e // FTM2_Channel0_Signal
	DMAMUX_CHCFG_SOURCE_31  = 0x1f // FTM2_Channel1_Signal
	DMAMUX_CHCFG_SOURCE_40  = 0x28 // ADC0_Signal
	DMAMUX_CHCFG_SOURCE_41  = 0x29 // ADC1_Signal
	DMAMUX_CHCFG_SOURCE_42  = 0x2a // CMP0_Signal
	DMAMUX_CHCFG_SOURCE_43  = 0x2b // CMP1_Signal
	DMAMUX_CHCFG_SOURCE_45  = 0x2d // DAC0_Signal
	DMAMUX_CHCFG_SOURCE_48  = 0x30 // PDB_Signal
	DMAMUX_CHCFG_SOURCE_49  = 0x31 // PortA_Signal
	DMAMUX_CHCFG_SOURCE_50  = 0x32 // PortB_Signal
	DMAMUX_CHCFG_SOURCE_51  = 0x33 // PortC_Signal
	DMAMUX_CHCFG_SOURCE_52  = 0x34 // PortD_Signal
	DMAMUX_CHCFG_SOURCE_53  = 0x35 // PortE_Signal
	DMAMUX_CHCFG_SOURCE_58  = 0x3a // LPUART0_Rx_Signal
	DMAMUX_CHCFG_SOURCE_59  = 0x3b // LPUART0_Tx_Signal
	DMAMUX_CHCFG_SOURCE_60  = 0x3c // AlwaysOn60_Signal
	DMAMUX_CHCFG_SOURCE_61  = 0x3d // AlwaysOn61_Signal
	DMAMUX_CHCFG_SOURCE_62  = 0x3e // AlwaysOn62_Signal
	DMAMUX_CHCFG_SOURCE_63  = 0x3f // AlwaysOn63_Signal
	DMAMUX_CHCFG_TRIG_Pos   = 0x6  // Position of TRIG field.
	DMAMUX_CHCFG_TRIG_Msk   = 0x40 // Bit mask of TRIG field.
	DMAMUX_CHCFG_TRIG       = 0x40 // Bit TRIG.
	DMAMUX_CHCFG_TRIG_0     = 0x0  // Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
	DMAMUX_CHCFG_TRIG_1     = 0x1  // Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.
	DMAMUX_CHCFG_ENBL_Pos   = 0x7  // Position of ENBL field.
	DMAMUX_CHCFG_ENBL_Msk   = 0x80 // Bit mask of ENBL field.
	DMAMUX_CHCFG_ENBL       = 0x80 // Bit ENBL.
	DMAMUX_CHCFG_ENBL_0     = 0x0  // DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.
	DMAMUX_CHCFG_ENBL_1     = 0x1  // DMA channel is enabled
)

// Bitfields for ADC0: Analog-to-Digital Converter
const (
	// SC1A: ADC Status and Control Registers 1
	ADC_SC1_ADCH_Pos   = 0x0  // Position of ADCH field.
	ADC_SC1_ADCH_Msk   = 0x1f // Bit mask of ADCH field.
	ADC_SC1_ADCH_00000 = 0x0  // When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input.
	ADC_SC1_ADCH_00001 = 0x1  // When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input.
	ADC_SC1_ADCH_00010 = 0x2  // When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input.
	ADC_SC1_ADCH_00011 = 0x3  // When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input.
	ADC_SC1_ADCH_00100 = 0x4  // When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved.
	ADC_SC1_ADCH_00101 = 0x5  // When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved.
	ADC_SC1_ADCH_00110 = 0x6  // When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved.
	ADC_SC1_ADCH_00111 = 0x7  // When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved.
	ADC_SC1_ADCH_01000 = 0x8  // When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved.
	ADC_SC1_ADCH_01001 = 0x9  // When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved.
	ADC_SC1_ADCH_01010 = 0xa  // When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved.
	ADC_SC1_ADCH_01011 = 0xb  // When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved.
	ADC_SC1_ADCH_01100 = 0xc  // When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved.
	ADC_SC1_ADCH_01101 = 0xd  // When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved.
	ADC_SC1_ADCH_01110 = 0xe  // When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved.
	ADC_SC1_ADCH_01111 = 0xf  // When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved.
	ADC_SC1_ADCH_10000 = 0x10 // When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved.
	ADC_SC1_ADCH_10001 = 0x11 // When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved.
	ADC_SC1_ADCH_10010 = 0x12 // When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved.
	ADC_SC1_ADCH_10011 = 0x13 // When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved.
	ADC_SC1_ADCH_10100 = 0x14 // When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved.
	ADC_SC1_ADCH_10101 = 0x15 // When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved.
	ADC_SC1_ADCH_10110 = 0x16 // When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved.
	ADC_SC1_ADCH_10111 = 0x17 // When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved.
	ADC_SC1_ADCH_11010 = 0x1a // When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor (differential) is selected as input.
	ADC_SC1_ADCH_11011 = 0x1b // When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input.
	ADC_SC1_ADCH_11101 = 0x1d // When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by SC2[REFSEL].
	ADC_SC1_ADCH_11110 = 0x1e // When DIFF=0,VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by SC2[REFSEL].
	ADC_SC1_ADCH_11111 = 0x1f // Module is disabled.
	ADC_SC1_DIFF_Pos   = 0x5  // Position of DIFF field.
	ADC_SC1_DIFF_Msk   = 0x20 // Bit mask of DIFF field.
	ADC_SC1_DIFF       = 0x20 // Bit DIFF.
	ADC_SC1_DIFF_0     = 0x0  // Single-ended conversions and input channels are selected.
	ADC_SC1_DIFF_1     = 0x1  // Differential conversions and input channels are selected.
	ADC_SC1_AIEN_Pos   = 0x6  // Position of AIEN field.
	ADC_SC1_AIEN_Msk   = 0x40 // Bit mask of AIEN field.
	ADC_SC1_AIEN       = 0x40 // Bit AIEN.
	ADC_SC1_AIEN_0     = 0x0  // Conversion complete interrupt is disabled.
	ADC_SC1_AIEN_1     = 0x1  // Conversion complete interrupt is enabled.
	ADC_SC1_COCO_Pos   = 0x7  // Position of COCO field.
	ADC_SC1_COCO_Msk   = 0x80 // Bit mask of COCO field.
	ADC_SC1_COCO       = 0x80 // Bit COCO.
	ADC_SC1_COCO_0     = 0x0  // Conversion is not completed.
	ADC_SC1_COCO_1     = 0x1  // Conversion is completed.

	// CFG1: ADC Configuration Register 1
	ADC_CFG1_ADICLK_Pos = 0x0  // Position of ADICLK field.
	ADC_CFG1_ADICLK_Msk = 0x3  // Bit mask of ADICLK field.
	ADC_CFG1_ADICLK_00  = 0x0  // Bus clock
	ADC_CFG1_ADICLK_01  = 0x1  // Alternate clock 2 (ALTCLK2)
	ADC_CFG1_ADICLK_10  = 0x2  // Alternate clock (ALTCLK)
	ADC_CFG1_ADICLK_11  = 0x3  // Asynchronous clock (ADACK)
	ADC_CFG1_MODE_Pos   = 0x2  // Position of MODE field.
	ADC_CFG1_MODE_Msk   = 0xc  // Bit mask of MODE field.
	ADC_CFG1_MODE_00    = 0x0  // When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2's complement output.
	ADC_CFG1_MODE_01    = 0x1  // When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is differential 13-bit conversion with 2's complement output.
	ADC_CFG1_MODE_10    = 0x2  // When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is differential 11-bit conversion with 2's complement output
	ADC_CFG1_MODE_11    = 0x3  // When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is differential 16-bit conversion with 2's complement output
	ADC_CFG1_ADLSMP_Pos = 0x4  // Position of ADLSMP field.
	ADC_CFG1_ADLSMP_Msk = 0x10 // Bit mask of ADLSMP field.
	ADC_CFG1_ADLSMP     = 0x10 // Bit ADLSMP.
	ADC_CFG1_ADLSMP_0   = 0x0  // Short sample time.
	ADC_CFG1_ADLSMP_1   = 0x1  // Long sample time.
	ADC_CFG1_ADIV_Pos   = 0x5  // Position of ADIV field.
	ADC_CFG1_ADIV_Msk   = 0x60 // Bit mask of ADIV field.
	ADC_CFG1_ADIV_00    = 0x0  // The divide ratio is 1 and the clock rate is input clock.
	ADC_CFG1_ADIV_01    = 0x1  // The divide ratio is 2 and the clock rate is (input clock)/2.
	ADC_CFG1_ADIV_10    = 0x2  // The divide ratio is 4 and the clock rate is (input clock)/4.
	ADC_CFG1_ADIV_11    = 0x3  // The divide ratio is 8 and the clock rate is (input clock)/8.
	ADC_CFG1_ADLPC_Pos  = 0x7  // Position of ADLPC field.
	ADC_CFG1_ADLPC_Msk  = 0x80 // Bit mask of ADLPC field.
	ADC_CFG1_ADLPC      = 0x80 // Bit ADLPC.
	ADC_CFG1_ADLPC_0    = 0x0  // Normal power configuration.
	ADC_CFG1_ADLPC_1    = 0x1  // Low-power configuration. The power is reduced at the expense of maximum clock speed.

	// CFG2: ADC Configuration Register 2
	ADC_CFG2_ADLSTS_Pos  = 0x0  // Position of ADLSTS field.
	ADC_CFG2_ADLSTS_Msk  = 0x3  // Bit mask of ADLSTS field.
	ADC_CFG2_ADLSTS_00   = 0x0  // Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total.
	ADC_CFG2_ADLSTS_01   = 0x1  // 12 extra ADCK cycles; 16 ADCK cycles total sample time.
	ADC_CFG2_ADLSTS_10   = 0x2  // 6 extra ADCK cycles; 10 ADCK cycles total sample time.
	ADC_CFG2_ADLSTS_11   = 0x3  // 2 extra ADCK cycles; 6 ADCK cycles total sample time.
	ADC_CFG2_ADHSC_Pos   = 0x2  // Position of ADHSC field.
	ADC_CFG2_ADHSC_Msk   = 0x4  // Bit mask of ADHSC field.
	ADC_CFG2_ADHSC       = 0x4  // Bit ADHSC.
	ADC_CFG2_ADHSC_0     = 0x0  // Normal conversion sequence selected.
	ADC_CFG2_ADHSC_1     = 0x1  // High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time.
	ADC_CFG2_ADACKEN_Pos = 0x3  // Position of ADACKEN field.
	ADC_CFG2_ADACKEN_Msk = 0x8  // Bit mask of ADACKEN field.
	ADC_CFG2_ADACKEN     = 0x8  // Bit ADACKEN.
	ADC_CFG2_ADACKEN_0   = 0x0  // Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active.
	ADC_CFG2_ADACKEN_1   = 0x1  // Asynchronous clock and clock output is enabled regardless of the state of the ADC.
	ADC_CFG2_MUXSEL_Pos  = 0x4  // Position of MUXSEL field.
	ADC_CFG2_MUXSEL_Msk  = 0x10 // Bit mask of MUXSEL field.
	ADC_CFG2_MUXSEL      = 0x10 // Bit MUXSEL.
	ADC_CFG2_MUXSEL_0    = 0x0  // ADxxa channels are selected.
	ADC_CFG2_MUXSEL_1    = 0x1  // ADxxb channels are selected.

	// RA: ADC Data Result Register
	ADC_R_D_Pos = 0x0    // Position of D field.
	ADC_R_D_Msk = 0xffff // Bit mask of D field.

	// CV1: Compare Value Registers
	ADC_CV_CV_Pos = 0x0    // Position of CV field.
	ADC_CV_CV_Msk = 0xffff // Bit mask of CV field.

	// SC2: Status and Control Register 2
	ADC_SC2_REFSEL_Pos = 0x0  // Position of REFSEL field.
	ADC_SC2_REFSEL_Msk = 0x3  // Bit mask of REFSEL field.
	ADC_SC2_REFSEL_00  = 0x0  // Default voltage reference pin pair, that is, external pins VREFH and VREFL
	ADC_SC2_REFSEL_01  = 0x1  // Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU
	ADC_SC2_DMAEN_Pos  = 0x2  // Position of DMAEN field.
	ADC_SC2_DMAEN_Msk  = 0x4  // Bit mask of DMAEN field.
	ADC_SC2_DMAEN      = 0x4  // Bit DMAEN.
	ADC_SC2_DMAEN_0    = 0x0  // DMA is disabled.
	ADC_SC2_DMAEN_1    = 0x1  // DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any of the SC1n[COCO] flags is asserted.
	ADC_SC2_ACREN_Pos  = 0x3  // Position of ACREN field.
	ADC_SC2_ACREN_Msk  = 0x8  // Bit mask of ACREN field.
	ADC_SC2_ACREN      = 0x8  // Bit ACREN.
	ADC_SC2_ACREN_0    = 0x0  // Range function disabled. Only CV1 is compared.
	ADC_SC2_ACREN_1    = 0x1  // Range function enabled. Both CV1 and CV2 are compared.
	ADC_SC2_ACFGT_Pos  = 0x4  // Position of ACFGT field.
	ADC_SC2_ACFGT_Msk  = 0x10 // Bit mask of ACFGT field.
	ADC_SC2_ACFGT      = 0x10 // Bit ACFGT.
	ADC_SC2_ACFGT_0    = 0x0  // Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality based on the values placed in CV1 and CV2.
	ADC_SC2_ACFGT_1    = 0x1  // Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2.
	ADC_SC2_ACFE_Pos   = 0x5  // Position of ACFE field.
	ADC_SC2_ACFE_Msk   = 0x20 // Bit mask of ACFE field.
	ADC_SC2_ACFE       = 0x20 // Bit ACFE.
	ADC_SC2_ACFE_0     = 0x0  // Compare function disabled.
	ADC_SC2_ACFE_1     = 0x1  // Compare function enabled.
	ADC_SC2_ADTRG_Pos  = 0x6  // Position of ADTRG field.
	ADC_SC2_ADTRG_Msk  = 0x40 // Bit mask of ADTRG field.
	ADC_SC2_ADTRG      = 0x40 // Bit ADTRG.
	ADC_SC2_ADTRG_0    = 0x0  // Software trigger selected.
	ADC_SC2_ADTRG_1    = 0x1  // Hardware trigger selected.
	ADC_SC2_ADACT_Pos  = 0x7  // Position of ADACT field.
	ADC_SC2_ADACT_Msk  = 0x80 // Bit mask of ADACT field.
	ADC_SC2_ADACT      = 0x80 // Bit ADACT.
	ADC_SC2_ADACT_0    = 0x0  // Conversion not in progress.
	ADC_SC2_ADACT_1    = 0x1  // Conversion in progress.

	// SC3: Status and Control Register 3
	ADC_SC3_AVGS_Pos = 0x0  // Position of AVGS field.
	ADC_SC3_AVGS_Msk = 0x3  // Bit mask of AVGS field.
	ADC_SC3_AVGS_00  = 0x0  // 4 samples averaged.
	ADC_SC3_AVGS_01  = 0x1  // 8 samples averaged.
	ADC_SC3_AVGS_10  = 0x2  // 16 samples averaged.
	ADC_SC3_AVGS_11  = 0x3  // 32 samples averaged.
	ADC_SC3_AVGE_Pos = 0x2  // Position of AVGE field.
	ADC_SC3_AVGE_Msk = 0x4  // Bit mask of AVGE field.
	ADC_SC3_AVGE     = 0x4  // Bit AVGE.
	ADC_SC3_AVGE_0   = 0x0  // Hardware average function disabled.
	ADC_SC3_AVGE_1   = 0x1  // Hardware average function enabled.
	ADC_SC3_ADCO_Pos = 0x3  // Position of ADCO field.
	ADC_SC3_ADCO_Msk = 0x8  // Bit mask of ADCO field.
	ADC_SC3_ADCO     = 0x8  // Bit ADCO.
	ADC_SC3_ADCO_0   = 0x0  // One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.
	ADC_SC3_ADCO_1   = 0x1  // Continuous conversions or sets of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.
	ADC_SC3_CALF_Pos = 0x6  // Position of CALF field.
	ADC_SC3_CALF_Msk = 0x40 // Bit mask of CALF field.
	ADC_SC3_CALF     = 0x40 // Bit CALF.
	ADC_SC3_CALF_0   = 0x0  // Calibration completed normally.
	ADC_SC3_CALF_1   = 0x1  // Calibration failed. ADC accuracy specifications are not guaranteed.
	ADC_SC3_CAL_Pos  = 0x7  // Position of CAL field.
	ADC_SC3_CAL_Msk  = 0x80 // Bit mask of CAL field.
	ADC_SC3_CAL      = 0x80 // Bit CAL.

	// OFS: ADC Offset Correction Register
	ADC_OFS_OFS_Pos = 0x0    // Position of OFS field.
	ADC_OFS_OFS_Msk = 0xffff // Bit mask of OFS field.

	// PG: ADC Plus-Side Gain Register
	ADC_PG_PG_Pos = 0x0    // Position of PG field.
	ADC_PG_PG_Msk = 0xffff // Bit mask of PG field.

	// MG: ADC Minus-Side Gain Register
	ADC_MG_MG_Pos = 0x0    // Position of MG field.
	ADC_MG_MG_Msk = 0xffff // Bit mask of MG field.

	// CLPD: ADC Plus-Side General Calibration Value Register
	ADC_CLPD_CLPD_Pos = 0x0  // Position of CLPD field.
	ADC_CLPD_CLPD_Msk = 0x3f // Bit mask of CLPD field.

	// CLPS: ADC Plus-Side General Calibration Value Register
	ADC_CLPS_CLPS_Pos = 0x0  // Position of CLPS field.
	ADC_CLPS_CLPS_Msk = 0x3f // Bit mask of CLPS field.

	// CLP4: ADC Plus-Side General Calibration Value Register
	ADC_CLP4_CLP4_Pos = 0x0   // Position of CLP4 field.
	ADC_CLP4_CLP4_Msk = 0x3ff // Bit mask of CLP4 field.

	// CLP3: ADC Plus-Side General Calibration Value Register
	ADC_CLP3_CLP3_Pos = 0x0   // Position of CLP3 field.
	ADC_CLP3_CLP3_Msk = 0x1ff // Bit mask of CLP3 field.

	// CLP2: ADC Plus-Side General Calibration Value Register
	ADC_CLP2_CLP2_Pos = 0x0  // Position of CLP2 field.
	ADC_CLP2_CLP2_Msk = 0xff // Bit mask of CLP2 field.

	// CLP1: ADC Plus-Side General Calibration Value Register
	ADC_CLP1_CLP1_Pos = 0x0  // Position of CLP1 field.
	ADC_CLP1_CLP1_Msk = 0x7f // Bit mask of CLP1 field.

	// CLP0: ADC Plus-Side General Calibration Value Register
	ADC_CLP0_CLP0_Pos = 0x0  // Position of CLP0 field.
	ADC_CLP0_CLP0_Msk = 0x3f // Bit mask of CLP0 field.

	// CLMD: ADC Minus-Side General Calibration Value Register
	ADC_CLMD_CLMD_Pos = 0x0  // Position of CLMD field.
	ADC_CLMD_CLMD_Msk = 0x3f // Bit mask of CLMD field.

	// CLMS: ADC Minus-Side General Calibration Value Register
	ADC_CLMS_CLMS_Pos = 0x0  // Position of CLMS field.
	ADC_CLMS_CLMS_Msk = 0x3f // Bit mask of CLMS field.

	// CLM4: ADC Minus-Side General Calibration Value Register
	ADC_CLM4_CLM4_Pos = 0x0   // Position of CLM4 field.
	ADC_CLM4_CLM4_Msk = 0x3ff // Bit mask of CLM4 field.

	// CLM3: ADC Minus-Side General Calibration Value Register
	ADC_CLM3_CLM3_Pos = 0x0   // Position of CLM3 field.
	ADC_CLM3_CLM3_Msk = 0x1ff // Bit mask of CLM3 field.

	// CLM2: ADC Minus-Side General Calibration Value Register
	ADC_CLM2_CLM2_Pos = 0x0  // Position of CLM2 field.
	ADC_CLM2_CLM2_Msk = 0xff // Bit mask of CLM2 field.

	// CLM1: ADC Minus-Side General Calibration Value Register
	ADC_CLM1_CLM1_Pos = 0x0  // Position of CLM1 field.
	ADC_CLM1_CLM1_Msk = 0x7f // Bit mask of CLM1 field.

	// CLM0: ADC Minus-Side General Calibration Value Register
	ADC_CLM0_CLM0_Pos = 0x0  // Position of CLM0 field.
	ADC_CLM0_CLM0_Msk = 0x3f // Bit mask of CLM0 field.
)

// Bitfields for RNG: Random Number Generator Accelerator
const (
	// CR: RNGA Control Register
	RNG_CR_GO_Pos   = 0x0  // Position of GO field.
	RNG_CR_GO_Msk   = 0x1  // Bit mask of GO field.
	RNG_CR_GO       = 0x1  // Bit GO.
	RNG_CR_GO_0     = 0x0  // Disabled
	RNG_CR_GO_1     = 0x1  // Enabled
	RNG_CR_HA_Pos   = 0x1  // Position of HA field.
	RNG_CR_HA_Msk   = 0x2  // Bit mask of HA field.
	RNG_CR_HA       = 0x2  // Bit HA.
	RNG_CR_HA_0     = 0x0  // Disabled
	RNG_CR_HA_1     = 0x1  // Enabled
	RNG_CR_INTM_Pos = 0x2  // Position of INTM field.
	RNG_CR_INTM_Msk = 0x4  // Bit mask of INTM field.
	RNG_CR_INTM     = 0x4  // Bit INTM.
	RNG_CR_INTM_0   = 0x0  // Not masked
	RNG_CR_INTM_1   = 0x1  // Masked
	RNG_CR_CLRI_Pos = 0x3  // Position of CLRI field.
	RNG_CR_CLRI_Msk = 0x8  // Bit mask of CLRI field.
	RNG_CR_CLRI     = 0x8  // Bit CLRI.
	RNG_CR_CLRI_0   = 0x0  // Do not clear the interrupt.
	RNG_CR_CLRI_1   = 0x1  // Clear the interrupt. When you write 1 to this field, RNGA then resets the error-interrupt indicator (SR[ERRI]). This bit always reads as 0.
	RNG_CR_SLP_Pos  = 0x4  // Position of SLP field.
	RNG_CR_SLP_Msk  = 0x10 // Bit mask of SLP field.
	RNG_CR_SLP      = 0x10 // Bit SLP.
	RNG_CR_SLP_0    = 0x0  // Normal mode
	RNG_CR_SLP_1    = 0x1  // Sleep (low-power) mode

	// SR: RNGA Status Register
	RNG_SR_SECV_Pos      = 0x0      // Position of SECV field.
	RNG_SR_SECV_Msk      = 0x1      // Bit mask of SECV field.
	RNG_SR_SECV          = 0x1      // Bit SECV.
	RNG_SR_SECV_0        = 0x0      // No security violation
	RNG_SR_SECV_1        = 0x1      // Security violation
	RNG_SR_LRS_Pos       = 0x1      // Position of LRS field.
	RNG_SR_LRS_Msk       = 0x2      // Bit mask of LRS field.
	RNG_SR_LRS           = 0x2      // Bit LRS.
	RNG_SR_LRS_0         = 0x0      // No underflow
	RNG_SR_LRS_1         = 0x1      // Underflow
	RNG_SR_ORU_Pos       = 0x2      // Position of ORU field.
	RNG_SR_ORU_Msk       = 0x4      // Bit mask of ORU field.
	RNG_SR_ORU           = 0x4      // Bit ORU.
	RNG_SR_ORU_0         = 0x0      // No underflow
	RNG_SR_ORU_1         = 0x1      // Underflow
	RNG_SR_ERRI_Pos      = 0x3      // Position of ERRI field.
	RNG_SR_ERRI_Msk      = 0x8      // Bit mask of ERRI field.
	RNG_SR_ERRI          = 0x8      // Bit ERRI.
	RNG_SR_ERRI_0        = 0x0      // No underflow
	RNG_SR_ERRI_1        = 0x1      // Underflow
	RNG_SR_SLP_Pos       = 0x4      // Position of SLP field.
	RNG_SR_SLP_Msk       = 0x10     // Bit mask of SLP field.
	RNG_SR_SLP           = 0x10     // Bit SLP.
	RNG_SR_SLP_0         = 0x0      // Normal mode
	RNG_SR_SLP_1         = 0x1      // Sleep (low-power) mode
	RNG_SR_OREG_LVL_Pos  = 0x8      // Position of OREG_LVL field.
	RNG_SR_OREG_LVL_Msk  = 0xff00   // Bit mask of OREG_LVL field.
	RNG_SR_OREG_LVL_0    = 0x0      // No words (empty)
	RNG_SR_OREG_LVL_1    = 0x1      // One word (valid)
	RNG_SR_OREG_SIZE_Pos = 0x10     // Position of OREG_SIZE field.
	RNG_SR_OREG_SIZE_Msk = 0xff0000 // Bit mask of OREG_SIZE field.
	RNG_SR_OREG_SIZE_1   = 0x1      // One word (this value is fixed)

	// ER: RNGA Entropy Register
	RNG_ER_EXT_ENT_Pos = 0x0        // Position of EXT_ENT field.
	RNG_ER_EXT_ENT_Msk = 0xffffffff // Bit mask of EXT_ENT field.

	// OR: RNGA Output Register
	RNG_OR_RANDOUT_Pos = 0x0        // Position of RANDOUT field.
	RNG_OR_RANDOUT_Msk = 0xffffffff // Bit mask of RANDOUT field.
	RNG_OR_RANDOUT_0   = 0x0        // Invalid data (if you read this field when it is 0 and SR[OREG_LVL] is 0, RNGA then writes 1 to SR[ERRI], SR[ORU], and SR[LRS]; when the error interrupt is not masked (CR[INTM]=0), RNGA also asserts an error interrupt request to the interrupt controller).
)

// Bitfields for LPUART0: Universal Asynchronous Receiver/Transmitter
const (
	// BAUD: LPUART Baud Rate Register
	LPUART0_BAUD_SBR_Pos       = 0x0        // Position of SBR field.
	LPUART0_BAUD_SBR_Msk       = 0x1fff     // Bit mask of SBR field.
	LPUART0_BAUD_SBNS_Pos      = 0xd        // Position of SBNS field.
	LPUART0_BAUD_SBNS_Msk      = 0x2000     // Bit mask of SBNS field.
	LPUART0_BAUD_SBNS          = 0x2000     // Bit SBNS.
	LPUART0_BAUD_SBNS_0        = 0x0        // One stop bit.
	LPUART0_BAUD_SBNS_1        = 0x1        // Two stop bits.
	LPUART0_BAUD_RXEDGIE_Pos   = 0xe        // Position of RXEDGIE field.
	LPUART0_BAUD_RXEDGIE_Msk   = 0x4000     // Bit mask of RXEDGIE field.
	LPUART0_BAUD_RXEDGIE       = 0x4000     // Bit RXEDGIE.
	LPUART0_BAUD_RXEDGIE_0     = 0x0        // Hardware interrupts from LPUART_STAT[RXEDGIF] disabled (use polling).
	LPUART0_BAUD_RXEDGIE_1     = 0x1        // Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1.
	LPUART0_BAUD_LBKDIE_Pos    = 0xf        // Position of LBKDIE field.
	LPUART0_BAUD_LBKDIE_Msk    = 0x8000     // Bit mask of LBKDIE field.
	LPUART0_BAUD_LBKDIE        = 0x8000     // Bit LBKDIE.
	LPUART0_BAUD_LBKDIE_0      = 0x0        // Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling).
	LPUART0_BAUD_LBKDIE_1      = 0x1        // Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1.
	LPUART0_BAUD_RESYNCDIS_Pos = 0x10       // Position of RESYNCDIS field.
	LPUART0_BAUD_RESYNCDIS_Msk = 0x10000    // Bit mask of RESYNCDIS field.
	LPUART0_BAUD_RESYNCDIS     = 0x10000    // Bit RESYNCDIS.
	LPUART0_BAUD_RESYNCDIS_0   = 0x0        // Resynchronization during received data word is supported
	LPUART0_BAUD_RESYNCDIS_1   = 0x1        // Resynchronization during received data word is disabled
	LPUART0_BAUD_BOTHEDGE_Pos  = 0x11       // Position of BOTHEDGE field.
	LPUART0_BAUD_BOTHEDGE_Msk  = 0x20000    // Bit mask of BOTHEDGE field.
	LPUART0_BAUD_BOTHEDGE      = 0x20000    // Bit BOTHEDGE.
	LPUART0_BAUD_BOTHEDGE_0    = 0x0        // Receiver samples input data using the rising edge of the baud rate clock.
	LPUART0_BAUD_BOTHEDGE_1    = 0x1        // Receiver samples input data using the rising and falling edge of the baud rate clock.
	LPUART0_BAUD_MATCFG_Pos    = 0x12       // Position of MATCFG field.
	LPUART0_BAUD_MATCFG_Msk    = 0xc0000    // Bit mask of MATCFG field.
	LPUART0_BAUD_MATCFG_00     = 0x0        // Address Match Wakeup
	LPUART0_BAUD_MATCFG_01     = 0x1        // Idle Match Wakeup
	LPUART0_BAUD_MATCFG_10     = 0x2        // Match On and Match Off
	LPUART0_BAUD_MATCFG_11     = 0x3        // Enables RWU on Data Match and Match On/Off for transmitter CTS input
	LPUART0_BAUD_RDMAE_Pos     = 0x15       // Position of RDMAE field.
	LPUART0_BAUD_RDMAE_Msk     = 0x200000   // Bit mask of RDMAE field.
	LPUART0_BAUD_RDMAE         = 0x200000   // Bit RDMAE.
	LPUART0_BAUD_RDMAE_0       = 0x0        // DMA request disabled.
	LPUART0_BAUD_RDMAE_1       = 0x1        // DMA request enabled.
	LPUART0_BAUD_TDMAE_Pos     = 0x17       // Position of TDMAE field.
	LPUART0_BAUD_TDMAE_Msk     = 0x800000   // Bit mask of TDMAE field.
	LPUART0_BAUD_TDMAE         = 0x800000   // Bit TDMAE.
	LPUART0_BAUD_TDMAE_0       = 0x0        // DMA request disabled.
	LPUART0_BAUD_TDMAE_1       = 0x1        // DMA request enabled.
	LPUART0_BAUD_OSR_Pos       = 0x18       // Position of OSR field.
	LPUART0_BAUD_OSR_Msk       = 0x1f000000 // Bit mask of OSR field.
	LPUART0_BAUD_M10_Pos       = 0x1d       // Position of M10 field.
	LPUART0_BAUD_M10_Msk       = 0x20000000 // Bit mask of M10 field.
	LPUART0_BAUD_M10           = 0x20000000 // Bit M10.
	LPUART0_BAUD_M10_0         = 0x0        // Receiver and transmitter use 8-bit or 9-bit data characters.
	LPUART0_BAUD_M10_1         = 0x1        // Receiver and transmitter use 10-bit data characters.
	LPUART0_BAUD_MAEN2_Pos     = 0x1e       // Position of MAEN2 field.
	LPUART0_BAUD_MAEN2_Msk     = 0x40000000 // Bit mask of MAEN2 field.
	LPUART0_BAUD_MAEN2         = 0x40000000 // Bit MAEN2.
	LPUART0_BAUD_MAEN2_0       = 0x0        // Normal operation.
	LPUART0_BAUD_MAEN2_1       = 0x1        // Enables automatic address matching or data matching mode for MATCH[MA2].
	LPUART0_BAUD_MAEN1_Pos     = 0x1f       // Position of MAEN1 field.
	LPUART0_BAUD_MAEN1_Msk     = 0x80000000 // Bit mask of MAEN1 field.
	LPUART0_BAUD_MAEN1         = 0x80000000 // Bit MAEN1.
	LPUART0_BAUD_MAEN1_0       = 0x0        // Normal operation.
	LPUART0_BAUD_MAEN1_1       = 0x1        // Enables automatic address matching or data matching mode for MATCH[MA1].

	// STAT: LPUART Status Register
	LPUART0_STAT_MA2F_Pos    = 0xe        // Position of MA2F field.
	LPUART0_STAT_MA2F_Msk    = 0x4000     // Bit mask of MA2F field.
	LPUART0_STAT_MA2F        = 0x4000     // Bit MA2F.
	LPUART0_STAT_MA2F_0      = 0x0        // Received data is not equal to MA2
	LPUART0_STAT_MA2F_1      = 0x1        // Received data is equal to MA2
	LPUART0_STAT_MA1F_Pos    = 0xf        // Position of MA1F field.
	LPUART0_STAT_MA1F_Msk    = 0x8000     // Bit mask of MA1F field.
	LPUART0_STAT_MA1F        = 0x8000     // Bit MA1F.
	LPUART0_STAT_MA1F_0      = 0x0        // Received data is not equal to MA1
	LPUART0_STAT_MA1F_1      = 0x1        // Received data is equal to MA1
	LPUART0_STAT_PF_Pos      = 0x10       // Position of PF field.
	LPUART0_STAT_PF_Msk      = 0x10000    // Bit mask of PF field.
	LPUART0_STAT_PF          = 0x10000    // Bit PF.
	LPUART0_STAT_PF_0        = 0x0        // No parity error.
	LPUART0_STAT_PF_1        = 0x1        // Parity error.
	LPUART0_STAT_FE_Pos      = 0x11       // Position of FE field.
	LPUART0_STAT_FE_Msk      = 0x20000    // Bit mask of FE field.
	LPUART0_STAT_FE          = 0x20000    // Bit FE.
	LPUART0_STAT_FE_0        = 0x0        // No framing error detected. This does not guarantee the framing is correct.
	LPUART0_STAT_FE_1        = 0x1        // Framing error.
	LPUART0_STAT_NF_Pos      = 0x12       // Position of NF field.
	LPUART0_STAT_NF_Msk      = 0x40000    // Bit mask of NF field.
	LPUART0_STAT_NF          = 0x40000    // Bit NF.
	LPUART0_STAT_NF_0        = 0x0        // No noise detected.
	LPUART0_STAT_NF_1        = 0x1        // Noise detected in the received character in LPUART_DATA.
	LPUART0_STAT_OR_Pos      = 0x13       // Position of OR field.
	LPUART0_STAT_OR_Msk      = 0x80000    // Bit mask of OR field.
	LPUART0_STAT_OR          = 0x80000    // Bit OR.
	LPUART0_STAT_OR_0        = 0x0        // No overrun.
	LPUART0_STAT_OR_1        = 0x1        // Receive overrun (new LPUART data lost).
	LPUART0_STAT_IDLE_Pos    = 0x14       // Position of IDLE field.
	LPUART0_STAT_IDLE_Msk    = 0x100000   // Bit mask of IDLE field.
	LPUART0_STAT_IDLE        = 0x100000   // Bit IDLE.
	LPUART0_STAT_IDLE_0      = 0x0        // No idle line detected.
	LPUART0_STAT_IDLE_1      = 0x1        // Idle line was detected.
	LPUART0_STAT_RDRF_Pos    = 0x15       // Position of RDRF field.
	LPUART0_STAT_RDRF_Msk    = 0x200000   // Bit mask of RDRF field.
	LPUART0_STAT_RDRF        = 0x200000   // Bit RDRF.
	LPUART0_STAT_RDRF_0      = 0x0        // Receive data buffer empty.
	LPUART0_STAT_RDRF_1      = 0x1        // Receive data buffer full.
	LPUART0_STAT_TC_Pos      = 0x16       // Position of TC field.
	LPUART0_STAT_TC_Msk      = 0x400000   // Bit mask of TC field.
	LPUART0_STAT_TC          = 0x400000   // Bit TC.
	LPUART0_STAT_TC_0        = 0x0        // Transmitter active (sending data, a preamble, or a break).
	LPUART0_STAT_TC_1        = 0x1        // Transmitter idle (transmission activity complete).
	LPUART0_STAT_TDRE_Pos    = 0x17       // Position of TDRE field.
	LPUART0_STAT_TDRE_Msk    = 0x800000   // Bit mask of TDRE field.
	LPUART0_STAT_TDRE        = 0x800000   // Bit TDRE.
	LPUART0_STAT_TDRE_0      = 0x0        // Transmit data buffer full.
	LPUART0_STAT_TDRE_1      = 0x1        // Transmit data buffer empty.
	LPUART0_STAT_RAF_Pos     = 0x18       // Position of RAF field.
	LPUART0_STAT_RAF_Msk     = 0x1000000  // Bit mask of RAF field.
	LPUART0_STAT_RAF         = 0x1000000  // Bit RAF.
	LPUART0_STAT_RAF_0       = 0x0        // LPUART receiver idle waiting for a start bit.
	LPUART0_STAT_RAF_1       = 0x1        // LPUART receiver active (LPUART_RX input not idle).
	LPUART0_STAT_LBKDE_Pos   = 0x19       // Position of LBKDE field.
	LPUART0_STAT_LBKDE_Msk   = 0x2000000  // Bit mask of LBKDE field.
	LPUART0_STAT_LBKDE       = 0x2000000  // Bit LBKDE.
	LPUART0_STAT_LBKDE_0     = 0x0        // Break character is detected at length 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).
	LPUART0_STAT_LBKDE_1     = 0x1        // Break character is detected at length of 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 14 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 15 (if M10 = 1, SNBS = 1).
	LPUART0_STAT_BRK13_Pos   = 0x1a       // Position of BRK13 field.
	LPUART0_STAT_BRK13_Msk   = 0x4000000  // Bit mask of BRK13 field.
	LPUART0_STAT_BRK13       = 0x4000000  // Bit BRK13.
	LPUART0_STAT_BRK13_0     = 0x0        // Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).
	LPUART0_STAT_BRK13_1     = 0x1        // Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1).
	LPUART0_STAT_RWUID_Pos   = 0x1b       // Position of RWUID field.
	LPUART0_STAT_RWUID_Msk   = 0x8000000  // Bit mask of RWUID field.
	LPUART0_STAT_RWUID       = 0x8000000  // Bit RWUID.
	LPUART0_STAT_RWUID_0     = 0x0        // During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not get set when an address does not match.
	LPUART0_STAT_RWUID_1     = 0x1        // During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does get set when an address does not match.
	LPUART0_STAT_RXINV_Pos   = 0x1c       // Position of RXINV field.
	LPUART0_STAT_RXINV_Msk   = 0x10000000 // Bit mask of RXINV field.
	LPUART0_STAT_RXINV       = 0x10000000 // Bit RXINV.
	LPUART0_STAT_RXINV_0     = 0x0        // Receive data not inverted.
	LPUART0_STAT_RXINV_1     = 0x1        // Receive data inverted.
	LPUART0_STAT_MSBF_Pos    = 0x1d       // Position of MSBF field.
	LPUART0_STAT_MSBF_Msk    = 0x20000000 // Bit mask of MSBF field.
	LPUART0_STAT_MSBF        = 0x20000000 // Bit MSBF.
	LPUART0_STAT_MSBF_0      = 0x0        // LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.
	LPUART0_STAT_MSBF_1      = 0x1        // MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE].
	LPUART0_STAT_RXEDGIF_Pos = 0x1e       // Position of RXEDGIF field.
	LPUART0_STAT_RXEDGIF_Msk = 0x40000000 // Bit mask of RXEDGIF field.
	LPUART0_STAT_RXEDGIF     = 0x40000000 // Bit RXEDGIF.
	LPUART0_STAT_RXEDGIF_0   = 0x0        // No active edge on the receive pin has occurred.
	LPUART0_STAT_RXEDGIF_1   = 0x1        // An active edge on the receive pin has occurred.
	LPUART0_STAT_LBKDIF_Pos  = 0x1f       // Position of LBKDIF field.
	LPUART0_STAT_LBKDIF_Msk  = 0x80000000 // Bit mask of LBKDIF field.
	LPUART0_STAT_LBKDIF      = 0x80000000 // Bit LBKDIF.
	LPUART0_STAT_LBKDIF_0    = 0x0        // No LIN break character has been detected.
	LPUART0_STAT_LBKDIF_1    = 0x1        // LIN break character has been detected.

	// CTRL: LPUART Control Register
	LPUART0_CTRL_PT_Pos      = 0x0        // Position of PT field.
	LPUART0_CTRL_PT_Msk      = 0x1        // Bit mask of PT field.
	LPUART0_CTRL_PT          = 0x1        // Bit PT.
	LPUART0_CTRL_PT_0        = 0x0        // Even parity.
	LPUART0_CTRL_PT_1        = 0x1        // Odd parity.
	LPUART0_CTRL_PE_Pos      = 0x1        // Position of PE field.
	LPUART0_CTRL_PE_Msk      = 0x2        // Bit mask of PE field.
	LPUART0_CTRL_PE          = 0x2        // Bit PE.
	LPUART0_CTRL_PE_0        = 0x0        // No hardware parity generation or checking.
	LPUART0_CTRL_PE_1        = 0x1        // Parity enabled.
	LPUART0_CTRL_ILT_Pos     = 0x2        // Position of ILT field.
	LPUART0_CTRL_ILT_Msk     = 0x4        // Bit mask of ILT field.
	LPUART0_CTRL_ILT         = 0x4        // Bit ILT.
	LPUART0_CTRL_ILT_0       = 0x0        // Idle character bit count starts after start bit.
	LPUART0_CTRL_ILT_1       = 0x1        // Idle character bit count starts after stop bit.
	LPUART0_CTRL_WAKE_Pos    = 0x3        // Position of WAKE field.
	LPUART0_CTRL_WAKE_Msk    = 0x8        // Bit mask of WAKE field.
	LPUART0_CTRL_WAKE        = 0x8        // Bit WAKE.
	LPUART0_CTRL_WAKE_0      = 0x0        // Configures RWU for idle-line wakeup.
	LPUART0_CTRL_WAKE_1      = 0x1        // Configures RWU with address-mark wakeup.
	LPUART0_CTRL_M_Pos       = 0x4        // Position of M field.
	LPUART0_CTRL_M_Msk       = 0x10       // Bit mask of M field.
	LPUART0_CTRL_M           = 0x10       // Bit M.
	LPUART0_CTRL_M_0         = 0x0        // Receiver and transmitter use 8-bit data characters.
	LPUART0_CTRL_M_1         = 0x1        // Receiver and transmitter use 9-bit data characters.
	LPUART0_CTRL_RSRC_Pos    = 0x5        // Position of RSRC field.
	LPUART0_CTRL_RSRC_Msk    = 0x20       // Bit mask of RSRC field.
	LPUART0_CTRL_RSRC        = 0x20       // Bit RSRC.
	LPUART0_CTRL_RSRC_0      = 0x0        // Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the LPUART_RX pin.
	LPUART0_CTRL_RSRC_1      = 0x1        // Single-wire LPUART mode where the LPUART_TX pin is connected to the transmitter output and receiver input.
	LPUART0_CTRL_DOZEEN_Pos  = 0x6        // Position of DOZEEN field.
	LPUART0_CTRL_DOZEEN_Msk  = 0x40       // Bit mask of DOZEEN field.
	LPUART0_CTRL_DOZEEN      = 0x40       // Bit DOZEEN.
	LPUART0_CTRL_DOZEEN_0    = 0x0        // LPUART is enabled in Doze mode.
	LPUART0_CTRL_DOZEEN_1    = 0x1        // LPUART is disabled in Doze mode.
	LPUART0_CTRL_LOOPS_Pos   = 0x7        // Position of LOOPS field.
	LPUART0_CTRL_LOOPS_Msk   = 0x80       // Bit mask of LOOPS field.
	LPUART0_CTRL_LOOPS       = 0x80       // Bit LOOPS.
	LPUART0_CTRL_LOOPS_0     = 0x0        // Normal operation - LPUART_RX and LPUART_TX use separate pins.
	LPUART0_CTRL_LOOPS_1     = 0x1        // Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit).
	LPUART0_CTRL_IDLECFG_Pos = 0x8        // Position of IDLECFG field.
	LPUART0_CTRL_IDLECFG_Msk = 0x700      // Bit mask of IDLECFG field.
	LPUART0_CTRL_IDLECFG_000 = 0x0        // 1 idle character
	LPUART0_CTRL_IDLECFG_001 = 0x1        // 2 idle characters
	LPUART0_CTRL_IDLECFG_010 = 0x2        // 4 idle characters
	LPUART0_CTRL_IDLECFG_011 = 0x3        // 8 idle characters
	LPUART0_CTRL_IDLECFG_100 = 0x4        // 16 idle characters
	LPUART0_CTRL_IDLECFG_101 = 0x5        // 32 idle characters
	LPUART0_CTRL_IDLECFG_110 = 0x6        // 64 idle characters
	LPUART0_CTRL_IDLECFG_111 = 0x7        // 128 idle characters
	LPUART0_CTRL_MA2IE_Pos   = 0xe        // Position of MA2IE field.
	LPUART0_CTRL_MA2IE_Msk   = 0x4000     // Bit mask of MA2IE field.
	LPUART0_CTRL_MA2IE       = 0x4000     // Bit MA2IE.
	LPUART0_CTRL_MA2IE_0     = 0x0        // MA2F interrupt disabled
	LPUART0_CTRL_MA2IE_1     = 0x1        // MA2F interrupt enabled
	LPUART0_CTRL_MA1IE_Pos   = 0xf        // Position of MA1IE field.
	LPUART0_CTRL_MA1IE_Msk   = 0x8000     // Bit mask of MA1IE field.
	LPUART0_CTRL_MA1IE       = 0x8000     // Bit MA1IE.
	LPUART0_CTRL_MA1IE_0     = 0x0        // MA1F interrupt disabled
	LPUART0_CTRL_MA1IE_1     = 0x1        // MA1F interrupt enabled
	LPUART0_CTRL_SBK_Pos     = 0x10       // Position of SBK field.
	LPUART0_CTRL_SBK_Msk     = 0x10000    // Bit mask of SBK field.
	LPUART0_CTRL_SBK         = 0x10000    // Bit SBK.
	LPUART0_CTRL_SBK_0       = 0x0        // Normal transmitter operation.
	LPUART0_CTRL_SBK_1       = 0x1        // Queue break character(s) to be sent.
	LPUART0_CTRL_RWU_Pos     = 0x11       // Position of RWU field.
	LPUART0_CTRL_RWU_Msk     = 0x20000    // Bit mask of RWU field.
	LPUART0_CTRL_RWU         = 0x20000    // Bit RWU.
	LPUART0_CTRL_RWU_0       = 0x0        // Normal receiver operation.
	LPUART0_CTRL_RWU_1       = 0x1        // LPUART receiver in standby waiting for wakeup condition.
	LPUART0_CTRL_RE_Pos      = 0x12       // Position of RE field.
	LPUART0_CTRL_RE_Msk      = 0x40000    // Bit mask of RE field.
	LPUART0_CTRL_RE          = 0x40000    // Bit RE.
	LPUART0_CTRL_RE_0        = 0x0        // Receiver disabled.
	LPUART0_CTRL_RE_1        = 0x1        // Receiver enabled.
	LPUART0_CTRL_TE_Pos      = 0x13       // Position of TE field.
	LPUART0_CTRL_TE_Msk      = 0x80000    // Bit mask of TE field.
	LPUART0_CTRL_TE          = 0x80000    // Bit TE.
	LPUART0_CTRL_TE_0        = 0x0        // Transmitter disabled.
	LPUART0_CTRL_TE_1        = 0x1        // Transmitter enabled.
	LPUART0_CTRL_ILIE_Pos    = 0x14       // Position of ILIE field.
	LPUART0_CTRL_ILIE_Msk    = 0x100000   // Bit mask of ILIE field.
	LPUART0_CTRL_ILIE        = 0x100000   // Bit ILIE.
	LPUART0_CTRL_ILIE_0      = 0x0        // Hardware interrupts from IDLE disabled; use polling.
	LPUART0_CTRL_ILIE_1      = 0x1        // Hardware interrupt requested when IDLE flag is 1.
	LPUART0_CTRL_RIE_Pos     = 0x15       // Position of RIE field.
	LPUART0_CTRL_RIE_Msk     = 0x200000   // Bit mask of RIE field.
	LPUART0_CTRL_RIE         = 0x200000   // Bit RIE.
	LPUART0_CTRL_RIE_0       = 0x0        // Hardware interrupts from RDRF disabled; use polling.
	LPUART0_CTRL_RIE_1       = 0x1        // Hardware interrupt requested when RDRF flag is 1.
	LPUART0_CTRL_TCIE_Pos    = 0x16       // Position of TCIE field.
	LPUART0_CTRL_TCIE_Msk    = 0x400000   // Bit mask of TCIE field.
	LPUART0_CTRL_TCIE        = 0x400000   // Bit TCIE.
	LPUART0_CTRL_TCIE_0      = 0x0        // Hardware interrupts from TC disabled; use polling.
	LPUART0_CTRL_TCIE_1      = 0x1        // Hardware interrupt requested when TC flag is 1.
	LPUART0_CTRL_TIE_Pos     = 0x17       // Position of TIE field.
	LPUART0_CTRL_TIE_Msk     = 0x800000   // Bit mask of TIE field.
	LPUART0_CTRL_TIE         = 0x800000   // Bit TIE.
	LPUART0_CTRL_TIE_0       = 0x0        // Hardware interrupts from TDRE disabled; use polling.
	LPUART0_CTRL_TIE_1       = 0x1        // Hardware interrupt requested when TDRE flag is 1.
	LPUART0_CTRL_PEIE_Pos    = 0x18       // Position of PEIE field.
	LPUART0_CTRL_PEIE_Msk    = 0x1000000  // Bit mask of PEIE field.
	LPUART0_CTRL_PEIE        = 0x1000000  // Bit PEIE.
	LPUART0_CTRL_PEIE_0      = 0x0        // PF interrupts disabled; use polling).
	LPUART0_CTRL_PEIE_1      = 0x1        // Hardware interrupt requested when PF is set.
	LPUART0_CTRL_FEIE_Pos    = 0x19       // Position of FEIE field.
	LPUART0_CTRL_FEIE_Msk    = 0x2000000  // Bit mask of FEIE field.
	LPUART0_CTRL_FEIE        = 0x2000000  // Bit FEIE.
	LPUART0_CTRL_FEIE_0      = 0x0        // FE interrupts disabled; use polling.
	LPUART0_CTRL_FEIE_1      = 0x1        // Hardware interrupt requested when FE is set.
	LPUART0_CTRL_NEIE_Pos    = 0x1a       // Position of NEIE field.
	LPUART0_CTRL_NEIE_Msk    = 0x4000000  // Bit mask of NEIE field.
	LPUART0_CTRL_NEIE        = 0x4000000  // Bit NEIE.
	LPUART0_CTRL_NEIE_0      = 0x0        // NF interrupts disabled; use polling.
	LPUART0_CTRL_NEIE_1      = 0x1        // Hardware interrupt requested when NF is set.
	LPUART0_CTRL_ORIE_Pos    = 0x1b       // Position of ORIE field.
	LPUART0_CTRL_ORIE_Msk    = 0x8000000  // Bit mask of ORIE field.
	LPUART0_CTRL_ORIE        = 0x8000000  // Bit ORIE.
	LPUART0_CTRL_ORIE_0      = 0x0        // OR interrupts disabled; use polling.
	LPUART0_CTRL_ORIE_1      = 0x1        // Hardware interrupt requested when OR is set.
	LPUART0_CTRL_TXINV_Pos   = 0x1c       // Position of TXINV field.
	LPUART0_CTRL_TXINV_Msk   = 0x10000000 // Bit mask of TXINV field.
	LPUART0_CTRL_TXINV       = 0x10000000 // Bit TXINV.
	LPUART0_CTRL_TXINV_0     = 0x0        // Transmit data not inverted.
	LPUART0_CTRL_TXINV_1     = 0x1        // Transmit data inverted.
	LPUART0_CTRL_TXDIR_Pos   = 0x1d       // Position of TXDIR field.
	LPUART0_CTRL_TXDIR_Msk   = 0x20000000 // Bit mask of TXDIR field.
	LPUART0_CTRL_TXDIR       = 0x20000000 // Bit TXDIR.
	LPUART0_CTRL_TXDIR_0     = 0x0        // LPUART_TX pin is an input in single-wire mode.
	LPUART0_CTRL_TXDIR_1     = 0x1        // LPUART_TX pin is an output in single-wire mode.
	LPUART0_CTRL_R9T8_Pos    = 0x1e       // Position of R9T8 field.
	LPUART0_CTRL_R9T8_Msk    = 0x40000000 // Bit mask of R9T8 field.
	LPUART0_CTRL_R9T8        = 0x40000000 // Bit R9T8.
	LPUART0_CTRL_R8T9_Pos    = 0x1f       // Position of R8T9 field.
	LPUART0_CTRL_R8T9_Msk    = 0x80000000 // Bit mask of R8T9 field.
	LPUART0_CTRL_R8T9        = 0x80000000 // Bit R8T9.

	// DATA: LPUART Data Register
	LPUART0_DATA_R0T0_Pos    = 0x0    // Position of R0T0 field.
	LPUART0_DATA_R0T0_Msk    = 0x1    // Bit mask of R0T0 field.
	LPUART0_DATA_R0T0        = 0x1    // Bit R0T0.
	LPUART0_DATA_R1T1_Pos    = 0x1    // Position of R1T1 field.
	LPUART0_DATA_R1T1_Msk    = 0x2    // Bit mask of R1T1 field.
	LPUART0_DATA_R1T1        = 0x2    // Bit R1T1.
	LPUART0_DATA_R2T2_Pos    = 0x2    // Position of R2T2 field.
	LPUART0_DATA_R2T2_Msk    = 0x4    // Bit mask of R2T2 field.
	LPUART0_DATA_R2T2        = 0x4    // Bit R2T2.
	LPUART0_DATA_R3T3_Pos    = 0x3    // Position of R3T3 field.
	LPUART0_DATA_R3T3_Msk    = 0x8    // Bit mask of R3T3 field.
	LPUART0_DATA_R3T3        = 0x8    // Bit R3T3.
	LPUART0_DATA_R4T4_Pos    = 0x4    // Position of R4T4 field.
	LPUART0_DATA_R4T4_Msk    = 0x10   // Bit mask of R4T4 field.
	LPUART0_DATA_R4T4        = 0x10   // Bit R4T4.
	LPUART0_DATA_R5T5_Pos    = 0x5    // Position of R5T5 field.
	LPUART0_DATA_R5T5_Msk    = 0x20   // Bit mask of R5T5 field.
	LPUART0_DATA_R5T5        = 0x20   // Bit R5T5.
	LPUART0_DATA_R6T6_Pos    = 0x6    // Position of R6T6 field.
	LPUART0_DATA_R6T6_Msk    = 0x40   // Bit mask of R6T6 field.
	LPUART0_DATA_R6T6        = 0x40   // Bit R6T6.
	LPUART0_DATA_R7T7_Pos    = 0x7    // Position of R7T7 field.
	LPUART0_DATA_R7T7_Msk    = 0x80   // Bit mask of R7T7 field.
	LPUART0_DATA_R7T7        = 0x80   // Bit R7T7.
	LPUART0_DATA_R8T8_Pos    = 0x8    // Position of R8T8 field.
	LPUART0_DATA_R8T8_Msk    = 0x100  // Bit mask of R8T8 field.
	LPUART0_DATA_R8T8        = 0x100  // Bit R8T8.
	LPUART0_DATA_R9T9_Pos    = 0x9    // Position of R9T9 field.
	LPUART0_DATA_R9T9_Msk    = 0x200  // Bit mask of R9T9 field.
	LPUART0_DATA_R9T9        = 0x200  // Bit R9T9.
	LPUART0_DATA_IDLINE_Pos  = 0xb    // Position of IDLINE field.
	LPUART0_DATA_IDLINE_Msk  = 0x800  // Bit mask of IDLINE field.
	LPUART0_DATA_IDLINE      = 0x800  // Bit IDLINE.
	LPUART0_DATA_IDLINE_0    = 0x0    // Receiver was not idle before receiving this character.
	LPUART0_DATA_IDLINE_1    = 0x1    // Receiver was idle before receiving this character.
	LPUART0_DATA_RXEMPT_Pos  = 0xc    // Position of RXEMPT field.
	LPUART0_DATA_RXEMPT_Msk  = 0x1000 // Bit mask of RXEMPT field.
	LPUART0_DATA_RXEMPT      = 0x1000 // Bit RXEMPT.
	LPUART0_DATA_RXEMPT_0    = 0x0    // Receive buffer contains valid data.
	LPUART0_DATA_RXEMPT_1    = 0x1    // Receive buffer is empty, data returned on read is not valid.
	LPUART0_DATA_FRETSC_Pos  = 0xd    // Position of FRETSC field.
	LPUART0_DATA_FRETSC_Msk  = 0x2000 // Bit mask of FRETSC field.
	LPUART0_DATA_FRETSC      = 0x2000 // Bit FRETSC.
	LPUART0_DATA_FRETSC_0    = 0x0    // The dataword was received without a frame error on read, transmit a normal character on write.
	LPUART0_DATA_FRETSC_1    = 0x1    // The dataword was received with a frame error, transmit an idle or break character on transmit.
	LPUART0_DATA_PARITYE_Pos = 0xe    // Position of PARITYE field.
	LPUART0_DATA_PARITYE_Msk = 0x4000 // Bit mask of PARITYE field.
	LPUART0_DATA_PARITYE     = 0x4000 // Bit PARITYE.
	LPUART0_DATA_PARITYE_0   = 0x0    // The dataword was received without a parity error.
	LPUART0_DATA_PARITYE_1   = 0x1    // The dataword was received with a parity error.
	LPUART0_DATA_NOISY_Pos   = 0xf    // Position of NOISY field.
	LPUART0_DATA_NOISY_Msk   = 0x8000 // Bit mask of NOISY field.
	LPUART0_DATA_NOISY       = 0x8000 // Bit NOISY.
	LPUART0_DATA_NOISY_0     = 0x0    // The dataword was received without noise.
	LPUART0_DATA_NOISY_1     = 0x1    // The data was received with noise.

	// MATCH: LPUART Match Address Register
	LPUART0_MATCH_MA1_Pos = 0x0       // Position of MA1 field.
	LPUART0_MATCH_MA1_Msk = 0x3ff     // Bit mask of MA1 field.
	LPUART0_MATCH_MA2_Pos = 0x10      // Position of MA2 field.
	LPUART0_MATCH_MA2_Msk = 0x3ff0000 // Bit mask of MA2 field.

	// MODIR: LPUART Modem IrDA Register
	LPUART0_MODIR_TXCTSE_Pos   = 0x0     // Position of TXCTSE field.
	LPUART0_MODIR_TXCTSE_Msk   = 0x1     // Bit mask of TXCTSE field.
	LPUART0_MODIR_TXCTSE       = 0x1     // Bit TXCTSE.
	LPUART0_MODIR_TXCTSE_0     = 0x0     // CTS has no effect on the transmitter.
	LPUART0_MODIR_TXCTSE_1     = 0x1     // Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission.
	LPUART0_MODIR_TXRTSE_Pos   = 0x1     // Position of TXRTSE field.
	LPUART0_MODIR_TXRTSE_Msk   = 0x2     // Bit mask of TXRTSE field.
	LPUART0_MODIR_TXRTSE       = 0x2     // Bit TXRTSE.
	LPUART0_MODIR_TXRTSE_0     = 0x0     // The transmitter has no effect on RTS.
	LPUART0_MODIR_TXRTSE_1     = 0x1     // When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit.
	LPUART0_MODIR_TXRTSPOL_Pos = 0x2     // Position of TXRTSPOL field.
	LPUART0_MODIR_TXRTSPOL_Msk = 0x4     // Bit mask of TXRTSPOL field.
	LPUART0_MODIR_TXRTSPOL     = 0x4     // Bit TXRTSPOL.
	LPUART0_MODIR_TXRTSPOL_0   = 0x0     // Transmitter RTS is active low.
	LPUART0_MODIR_TXRTSPOL_1   = 0x1     // Transmitter RTS is active high.
	LPUART0_MODIR_RXRTSE_Pos   = 0x3     // Position of RXRTSE field.
	LPUART0_MODIR_RXRTSE_Msk   = 0x8     // Bit mask of RXRTSE field.
	LPUART0_MODIR_RXRTSE       = 0x8     // Bit RXRTSE.
	LPUART0_MODIR_RXRTSE_0     = 0x0     // The receiver has no effect on RTS.
	LPUART0_MODIR_RXRTSE_1     = 0x1     // RTS is deasserted if the receiver data register is full or a start bit has been detected that would cause the receiver data register to become full. RTS is asserted if the receiver data register is not full and has not detected a start bit that would cause the receiver data register to become full.
	LPUART0_MODIR_TXCTSC_Pos   = 0x4     // Position of TXCTSC field.
	LPUART0_MODIR_TXCTSC_Msk   = 0x10    // Bit mask of TXCTSC field.
	LPUART0_MODIR_TXCTSC       = 0x10    // Bit TXCTSC.
	LPUART0_MODIR_TXCTSC_0     = 0x0     // CTS input is sampled at the start of each character.
	LPUART0_MODIR_TXCTSC_1     = 0x1     // CTS input is sampled when the transmitter is idle.
	LPUART0_MODIR_TXCTSSRC_Pos = 0x5     // Position of TXCTSSRC field.
	LPUART0_MODIR_TXCTSSRC_Msk = 0x20    // Bit mask of TXCTSSRC field.
	LPUART0_MODIR_TXCTSSRC     = 0x20    // Bit TXCTSSRC.
	LPUART0_MODIR_TXCTSSRC_0   = 0x0     // CTS input is the LPUART_CTS pin.
	LPUART0_MODIR_TXCTSSRC_1   = 0x1     // CTS input is the inverted Receiver Match result.
	LPUART0_MODIR_TNP_Pos      = 0x10    // Position of TNP field.
	LPUART0_MODIR_TNP_Msk      = 0x30000 // Bit mask of TNP field.
	LPUART0_MODIR_TNP_00       = 0x0     // 1/OSR.
	LPUART0_MODIR_TNP_01       = 0x1     // 2/OSR.
	LPUART0_MODIR_TNP_10       = 0x2     // 3/OSR.
	LPUART0_MODIR_TNP_11       = 0x3     // 4/OSR.
	LPUART0_MODIR_IREN_Pos     = 0x12    // Position of IREN field.
	LPUART0_MODIR_IREN_Msk     = 0x40000 // Bit mask of IREN field.
	LPUART0_MODIR_IREN         = 0x40000 // Bit IREN.
	LPUART0_MODIR_IREN_0       = 0x0     // IR disabled.
	LPUART0_MODIR_IREN_1       = 0x1     // IR enabled.
)

// Bitfields for SPI0: Serial Peripheral Interface
const (
	// MCR: Module Configuration Register
	SPI_MCR_HALT_Pos      = 0x0        // Position of HALT field.
	SPI_MCR_HALT_Msk      = 0x1        // Bit mask of HALT field.
	SPI_MCR_HALT          = 0x1        // Bit HALT.
	SPI_MCR_HALT_0        = 0x0        // Start transfers.
	SPI_MCR_HALT_1        = 0x1        // Stop transfers.
	SPI_MCR_SMPL_PT_Pos   = 0x8        // Position of SMPL_PT field.
	SPI_MCR_SMPL_PT_Msk   = 0x300      // Bit mask of SMPL_PT field.
	SPI_MCR_SMPL_PT_00    = 0x0        // 0 protocol clock cycles between SCK edge and SIN sample
	SPI_MCR_SMPL_PT_01    = 0x1        // 1 protocol clock cycle between SCK edge and SIN sample
	SPI_MCR_SMPL_PT_10    = 0x2        // 2 protocol clock cycles between SCK edge and SIN sample
	SPI_MCR_CLR_RXF_Pos   = 0xa        // Position of CLR_RXF field.
	SPI_MCR_CLR_RXF_Msk   = 0x400      // Bit mask of CLR_RXF field.
	SPI_MCR_CLR_RXF       = 0x400      // Bit CLR_RXF.
	SPI_MCR_CLR_RXF_0     = 0x0        // Do not clear the RX FIFO counter.
	SPI_MCR_CLR_RXF_1     = 0x1        // Clear the RX FIFO counter.
	SPI_MCR_CLR_TXF_Pos   = 0xb        // Position of CLR_TXF field.
	SPI_MCR_CLR_TXF_Msk   = 0x800      // Bit mask of CLR_TXF field.
	SPI_MCR_CLR_TXF       = 0x800      // Bit CLR_TXF.
	SPI_MCR_CLR_TXF_0     = 0x0        // Do not clear the TX FIFO counter.
	SPI_MCR_CLR_TXF_1     = 0x1        // Clear the TX FIFO counter.
	SPI_MCR_DIS_RXF_Pos   = 0xc        // Position of DIS_RXF field.
	SPI_MCR_DIS_RXF_Msk   = 0x1000     // Bit mask of DIS_RXF field.
	SPI_MCR_DIS_RXF       = 0x1000     // Bit DIS_RXF.
	SPI_MCR_DIS_RXF_0     = 0x0        // RX FIFO is enabled.
	SPI_MCR_DIS_RXF_1     = 0x1        // RX FIFO is disabled.
	SPI_MCR_DIS_TXF_Pos   = 0xd        // Position of DIS_TXF field.
	SPI_MCR_DIS_TXF_Msk   = 0x2000     // Bit mask of DIS_TXF field.
	SPI_MCR_DIS_TXF       = 0x2000     // Bit DIS_TXF.
	SPI_MCR_DIS_TXF_0     = 0x0        // TX FIFO is enabled.
	SPI_MCR_DIS_TXF_1     = 0x1        // TX FIFO is disabled.
	SPI_MCR_MDIS_Pos      = 0xe        // Position of MDIS field.
	SPI_MCR_MDIS_Msk      = 0x4000     // Bit mask of MDIS field.
	SPI_MCR_MDIS          = 0x4000     // Bit MDIS.
	SPI_MCR_MDIS_0        = 0x0        // Enables the module clocks.
	SPI_MCR_MDIS_1        = 0x1        // Allows external logic to disable the module clocks.
	SPI_MCR_DOZE_Pos      = 0xf        // Position of DOZE field.
	SPI_MCR_DOZE_Msk      = 0x8000     // Bit mask of DOZE field.
	SPI_MCR_DOZE          = 0x8000     // Bit DOZE.
	SPI_MCR_DOZE_0        = 0x0        // Doze mode has no effect on the module.
	SPI_MCR_DOZE_1        = 0x1        // Doze mode disables the module.
	SPI_MCR_PCSIS_Pos     = 0x10       // Position of PCSIS field.
	SPI_MCR_PCSIS_Msk     = 0x3f0000   // Bit mask of PCSIS field.
	SPI_MCR_PCSIS_0       = 0x0        // The inactive state of PCSx is low.
	SPI_MCR_PCSIS_1       = 0x1        // The inactive state of PCSx is high.
	SPI_MCR_ROOE_Pos      = 0x18       // Position of ROOE field.
	SPI_MCR_ROOE_Msk      = 0x1000000  // Bit mask of ROOE field.
	SPI_MCR_ROOE          = 0x1000000  // Bit ROOE.
	SPI_MCR_ROOE_0        = 0x0        // Incoming data is ignored.
	SPI_MCR_ROOE_1        = 0x1        // Incoming data is shifted into the shift register.
	SPI_MCR_PCSSE_Pos     = 0x19       // Position of PCSSE field.
	SPI_MCR_PCSSE_Msk     = 0x2000000  // Bit mask of PCSSE field.
	SPI_MCR_PCSSE         = 0x2000000  // Bit PCSSE.
	SPI_MCR_PCSSE_0       = 0x0        // PCS5/ PCSS is used as the Peripheral Chip Select[5] signal.
	SPI_MCR_PCSSE_1       = 0x1        // PCS5/ PCSS is used as an active-low PCS Strobe signal.
	SPI_MCR_MTFE_Pos      = 0x1a       // Position of MTFE field.
	SPI_MCR_MTFE_Msk      = 0x4000000  // Bit mask of MTFE field.
	SPI_MCR_MTFE          = 0x4000000  // Bit MTFE.
	SPI_MCR_MTFE_0        = 0x0        // Modified SPI transfer format disabled.
	SPI_MCR_MTFE_1        = 0x1        // Modified SPI transfer format enabled.
	SPI_MCR_FRZ_Pos       = 0x1b       // Position of FRZ field.
	SPI_MCR_FRZ_Msk       = 0x8000000  // Bit mask of FRZ field.
	SPI_MCR_FRZ           = 0x8000000  // Bit FRZ.
	SPI_MCR_FRZ_0         = 0x0        // Do not halt serial transfers in Debug mode.
	SPI_MCR_FRZ_1         = 0x1        // Halt serial transfers in Debug mode.
	SPI_MCR_DCONF_Pos     = 0x1c       // Position of DCONF field.
	SPI_MCR_DCONF_Msk     = 0x30000000 // Bit mask of DCONF field.
	SPI_MCR_DCONF_00      = 0x0        // SPI
	SPI_MCR_CONT_SCKE_Pos = 0x1e       // Position of CONT_SCKE field.
	SPI_MCR_CONT_SCKE_Msk = 0x40000000 // Bit mask of CONT_SCKE field.
	SPI_MCR_CONT_SCKE     = 0x40000000 // Bit CONT_SCKE.
	SPI_MCR_CONT_SCKE_0   = 0x0        // Continuous SCK disabled.
	SPI_MCR_CONT_SCKE_1   = 0x1        // Continuous SCK enabled.
	SPI_MCR_MSTR_Pos      = 0x1f       // Position of MSTR field.
	SPI_MCR_MSTR_Msk      = 0x80000000 // Bit mask of MSTR field.
	SPI_MCR_MSTR          = 0x80000000 // Bit MSTR.
	SPI_MCR_MSTR_0        = 0x0        // Enables Slave mode
	SPI_MCR_MSTR_1        = 0x1        // Enables Master mode

	// TCR: Transfer Count Register
	SPI_TCR_SPI_TCNT_Pos = 0x10       // Position of SPI_TCNT field.
	SPI_TCR_SPI_TCNT_Msk = 0xffff0000 // Bit mask of SPI_TCNT field.

	// CTAR0: Clock and Transfer Attributes Register (In Master Mode)
	SPI_CTAR_BR_Pos     = 0x0        // Position of BR field.
	SPI_CTAR_BR_Msk     = 0xf        // Bit mask of BR field.
	SPI_CTAR_DT_Pos     = 0x4        // Position of DT field.
	SPI_CTAR_DT_Msk     = 0xf0       // Bit mask of DT field.
	SPI_CTAR_ASC_Pos    = 0x8        // Position of ASC field.
	SPI_CTAR_ASC_Msk    = 0xf00      // Bit mask of ASC field.
	SPI_CTAR_CSSCK_Pos  = 0xc        // Position of CSSCK field.
	SPI_CTAR_CSSCK_Msk  = 0xf000     // Bit mask of CSSCK field.
	SPI_CTAR_PBR_Pos    = 0x10       // Position of PBR field.
	SPI_CTAR_PBR_Msk    = 0x30000    // Bit mask of PBR field.
	SPI_CTAR_PBR_00     = 0x0        // Baud Rate Prescaler value is 2.
	SPI_CTAR_PBR_01     = 0x1        // Baud Rate Prescaler value is 3.
	SPI_CTAR_PBR_10     = 0x2        // Baud Rate Prescaler value is 5.
	SPI_CTAR_PBR_11     = 0x3        // Baud Rate Prescaler value is 7.
	SPI_CTAR_PDT_Pos    = 0x12       // Position of PDT field.
	SPI_CTAR_PDT_Msk    = 0xc0000    // Bit mask of PDT field.
	SPI_CTAR_PDT_00     = 0x0        // Delay after Transfer Prescaler value is 1.
	SPI_CTAR_PDT_01     = 0x1        // Delay after Transfer Prescaler value is 3.
	SPI_CTAR_PDT_10     = 0x2        // Delay after Transfer Prescaler value is 5.
	SPI_CTAR_PDT_11     = 0x3        // Delay after Transfer Prescaler value is 7.
	SPI_CTAR_PASC_Pos   = 0x14       // Position of PASC field.
	SPI_CTAR_PASC_Msk   = 0x300000   // Bit mask of PASC field.
	SPI_CTAR_PASC_00    = 0x0        // Delay after Transfer Prescaler value is 1.
	SPI_CTAR_PASC_01    = 0x1        // Delay after Transfer Prescaler value is 3.
	SPI_CTAR_PASC_10    = 0x2        // Delay after Transfer Prescaler value is 5.
	SPI_CTAR_PASC_11    = 0x3        // Delay after Transfer Prescaler value is 7.
	SPI_CTAR_PCSSCK_Pos = 0x16       // Position of PCSSCK field.
	SPI_CTAR_PCSSCK_Msk = 0xc00000   // Bit mask of PCSSCK field.
	SPI_CTAR_PCSSCK_00  = 0x0        // PCS to SCK Prescaler value is 1.
	SPI_CTAR_PCSSCK_01  = 0x1        // PCS to SCK Prescaler value is 3.
	SPI_CTAR_PCSSCK_10  = 0x2        // PCS to SCK Prescaler value is 5.
	SPI_CTAR_PCSSCK_11  = 0x3        // PCS to SCK Prescaler value is 7.
	SPI_CTAR_LSBFE_Pos  = 0x18       // Position of LSBFE field.
	SPI_CTAR_LSBFE_Msk  = 0x1000000  // Bit mask of LSBFE field.
	SPI_CTAR_LSBFE      = 0x1000000  // Bit LSBFE.
	SPI_CTAR_LSBFE_0    = 0x0        // Data is transferred MSB first.
	SPI_CTAR_LSBFE_1    = 0x1        // Data is transferred LSB first.
	SPI_CTAR_CPHA_Pos   = 0x19       // Position of CPHA field.
	SPI_CTAR_CPHA_Msk   = 0x2000000  // Bit mask of CPHA field.
	SPI_CTAR_CPHA       = 0x2000000  // Bit CPHA.
	SPI_CTAR_CPHA_0     = 0x0        // Data is captured on the leading edge of SCK and changed on the following edge.
	SPI_CTAR_CPHA_1     = 0x1        // Data is changed on the leading edge of SCK and captured on the following edge.
	SPI_CTAR_CPOL_Pos   = 0x1a       // Position of CPOL field.
	SPI_CTAR_CPOL_Msk   = 0x4000000  // Bit mask of CPOL field.
	SPI_CTAR_CPOL       = 0x4000000  // Bit CPOL.
	SPI_CTAR_CPOL_0     = 0x0        // The inactive state value of SCK is low.
	SPI_CTAR_CPOL_1     = 0x1        // The inactive state value of SCK is high.
	SPI_CTAR_FMSZ_Pos   = 0x1b       // Position of FMSZ field.
	SPI_CTAR_FMSZ_Msk   = 0x78000000 // Bit mask of FMSZ field.
	SPI_CTAR_DBR_Pos    = 0x1f       // Position of DBR field.
	SPI_CTAR_DBR_Msk    = 0x80000000 // Bit mask of DBR field.
	SPI_CTAR_DBR        = 0x80000000 // Bit DBR.
	SPI_CTAR_DBR_0      = 0x0        // The baud rate is computed normally with a 50/50 duty cycle.
	SPI_CTAR_DBR_1      = 0x1        // The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler.

	// CTAR_SLAVE: Clock and Transfer Attributes Register (In Slave Mode)
	SPI_CTAR_SLAVE_CPHA_Pos = 0x19       // Position of CPHA field.
	SPI_CTAR_SLAVE_CPHA_Msk = 0x2000000  // Bit mask of CPHA field.
	SPI_CTAR_SLAVE_CPHA     = 0x2000000  // Bit CPHA.
	SPI_CTAR_SLAVE_CPHA_0   = 0x0        // Data is captured on the leading edge of SCK and changed on the following edge.
	SPI_CTAR_SLAVE_CPHA_1   = 0x1        // Data is changed on the leading edge of SCK and captured on the following edge.
	SPI_CTAR_SLAVE_CPOL_Pos = 0x1a       // Position of CPOL field.
	SPI_CTAR_SLAVE_CPOL_Msk = 0x4000000  // Bit mask of CPOL field.
	SPI_CTAR_SLAVE_CPOL     = 0x4000000  // Bit CPOL.
	SPI_CTAR_SLAVE_CPOL_0   = 0x0        // The inactive state value of SCK is low.
	SPI_CTAR_SLAVE_CPOL_1   = 0x1        // The inactive state value of SCK is high.
	SPI_CTAR_SLAVE_FMSZ_Pos = 0x1b       // Position of FMSZ field.
	SPI_CTAR_SLAVE_FMSZ_Msk = 0xf8000000 // Bit mask of FMSZ field.

	// SR: Status Register
	SPI_SR_POPNXTPTR_Pos = 0x0        // Position of POPNXTPTR field.
	SPI_SR_POPNXTPTR_Msk = 0xf        // Bit mask of POPNXTPTR field.
	SPI_SR_RXCTR_Pos     = 0x4        // Position of RXCTR field.
	SPI_SR_RXCTR_Msk     = 0xf0       // Bit mask of RXCTR field.
	SPI_SR_TXNXTPTR_Pos  = 0x8        // Position of TXNXTPTR field.
	SPI_SR_TXNXTPTR_Msk  = 0xf00      // Bit mask of TXNXTPTR field.
	SPI_SR_TXCTR_Pos     = 0xc        // Position of TXCTR field.
	SPI_SR_TXCTR_Msk     = 0xf000     // Bit mask of TXCTR field.
	SPI_SR_RFDF_Pos      = 0x11       // Position of RFDF field.
	SPI_SR_RFDF_Msk      = 0x20000    // Bit mask of RFDF field.
	SPI_SR_RFDF          = 0x20000    // Bit RFDF.
	SPI_SR_RFDF_0        = 0x0        // RX FIFO is empty.
	SPI_SR_RFDF_1        = 0x1        // RX FIFO is not empty.
	SPI_SR_RFOF_Pos      = 0x13       // Position of RFOF field.
	SPI_SR_RFOF_Msk      = 0x80000    // Bit mask of RFOF field.
	SPI_SR_RFOF          = 0x80000    // Bit RFOF.
	SPI_SR_RFOF_0        = 0x0        // No Rx FIFO overflow.
	SPI_SR_RFOF_1        = 0x1        // Rx FIFO overflow has occurred.
	SPI_SR_TFFF_Pos      = 0x19       // Position of TFFF field.
	SPI_SR_TFFF_Msk      = 0x2000000  // Bit mask of TFFF field.
	SPI_SR_TFFF          = 0x2000000  // Bit TFFF.
	SPI_SR_TFFF_0        = 0x0        // TX FIFO is full.
	SPI_SR_TFFF_1        = 0x1        // TX FIFO is not full.
	SPI_SR_TFUF_Pos      = 0x1b       // Position of TFUF field.
	SPI_SR_TFUF_Msk      = 0x8000000  // Bit mask of TFUF field.
	SPI_SR_TFUF          = 0x8000000  // Bit TFUF.
	SPI_SR_TFUF_0        = 0x0        // No TX FIFO underflow.
	SPI_SR_TFUF_1        = 0x1        // TX FIFO underflow has occurred.
	SPI_SR_EOQF_Pos      = 0x1c       // Position of EOQF field.
	SPI_SR_EOQF_Msk      = 0x10000000 // Bit mask of EOQF field.
	SPI_SR_EOQF          = 0x10000000 // Bit EOQF.
	SPI_SR_EOQF_0        = 0x0        // EOQ is not set in the executing command.
	SPI_SR_EOQF_1        = 0x1        // EOQ is set in the executing SPI command.
	SPI_SR_TXRXS_Pos     = 0x1e       // Position of TXRXS field.
	SPI_SR_TXRXS_Msk     = 0x40000000 // Bit mask of TXRXS field.
	SPI_SR_TXRXS         = 0x40000000 // Bit TXRXS.
	SPI_SR_TXRXS_0       = 0x0        // Transmit and receive operations are disabled (The module is in Stopped state).
	SPI_SR_TXRXS_1       = 0x1        // Transmit and receive operations are enabled (The module is in Running state).
	SPI_SR_TCF_Pos       = 0x1f       // Position of TCF field.
	SPI_SR_TCF_Msk       = 0x80000000 // Bit mask of TCF field.
	SPI_SR_TCF           = 0x80000000 // Bit TCF.
	SPI_SR_TCF_0         = 0x0        // Transfer not complete.
	SPI_SR_TCF_1         = 0x1        // Transfer complete.

	// RSER: DMA/Interrupt Request Select and Enable Register
	SPI_RSER_RFDF_DIRS_Pos = 0x10       // Position of RFDF_DIRS field.
	SPI_RSER_RFDF_DIRS_Msk = 0x10000    // Bit mask of RFDF_DIRS field.
	SPI_RSER_RFDF_DIRS     = 0x10000    // Bit RFDF_DIRS.
	SPI_RSER_RFDF_DIRS_0   = 0x0        // Interrupt request.
	SPI_RSER_RFDF_DIRS_1   = 0x1        // DMA request.
	SPI_RSER_RFDF_RE_Pos   = 0x11       // Position of RFDF_RE field.
	SPI_RSER_RFDF_RE_Msk   = 0x20000    // Bit mask of RFDF_RE field.
	SPI_RSER_RFDF_RE       = 0x20000    // Bit RFDF_RE.
	SPI_RSER_RFDF_RE_0     = 0x0        // RFDF interrupt or DMA requests are disabled.
	SPI_RSER_RFDF_RE_1     = 0x1        // RFDF interrupt or DMA requests are enabled.
	SPI_RSER_RFOF_RE_Pos   = 0x13       // Position of RFOF_RE field.
	SPI_RSER_RFOF_RE_Msk   = 0x80000    // Bit mask of RFOF_RE field.
	SPI_RSER_RFOF_RE       = 0x80000    // Bit RFOF_RE.
	SPI_RSER_RFOF_RE_0     = 0x0        // RFOF interrupt requests are disabled.
	SPI_RSER_RFOF_RE_1     = 0x1        // RFOF interrupt requests are enabled.
	SPI_RSER_TFFF_DIRS_Pos = 0x18       // Position of TFFF_DIRS field.
	SPI_RSER_TFFF_DIRS_Msk = 0x1000000  // Bit mask of TFFF_DIRS field.
	SPI_RSER_TFFF_DIRS     = 0x1000000  // Bit TFFF_DIRS.
	SPI_RSER_TFFF_DIRS_0   = 0x0        // TFFF flag generates interrupt requests.
	SPI_RSER_TFFF_DIRS_1   = 0x1        // TFFF flag generates DMA requests.
	SPI_RSER_TFFF_RE_Pos   = 0x19       // Position of TFFF_RE field.
	SPI_RSER_TFFF_RE_Msk   = 0x2000000  // Bit mask of TFFF_RE field.
	SPI_RSER_TFFF_RE       = 0x2000000  // Bit TFFF_RE.
	SPI_RSER_TFFF_RE_0     = 0x0        // TFFF interrupts or DMA requests are disabled.
	SPI_RSER_TFFF_RE_1     = 0x1        // TFFF interrupts or DMA requests are enabled.
	SPI_RSER_TFUF_RE_Pos   = 0x1b       // Position of TFUF_RE field.
	SPI_RSER_TFUF_RE_Msk   = 0x8000000  // Bit mask of TFUF_RE field.
	SPI_RSER_TFUF_RE       = 0x8000000  // Bit TFUF_RE.
	SPI_RSER_TFUF_RE_0     = 0x0        // TFUF interrupt requests are disabled.
	SPI_RSER_TFUF_RE_1     = 0x1        // TFUF interrupt requests are enabled.
	SPI_RSER_EOQF_RE_Pos   = 0x1c       // Position of EOQF_RE field.
	SPI_RSER_EOQF_RE_Msk   = 0x10000000 // Bit mask of EOQF_RE field.
	SPI_RSER_EOQF_RE       = 0x10000000 // Bit EOQF_RE.
	SPI_RSER_EOQF_RE_0     = 0x0        // EOQF interrupt requests are disabled.
	SPI_RSER_EOQF_RE_1     = 0x1        // EOQF interrupt requests are enabled.
	SPI_RSER_TCF_RE_Pos    = 0x1f       // Position of TCF_RE field.
	SPI_RSER_TCF_RE_Msk    = 0x80000000 // Bit mask of TCF_RE field.
	SPI_RSER_TCF_RE        = 0x80000000 // Bit TCF_RE.
	SPI_RSER_TCF_RE_0      = 0x0        // TCF interrupt requests are disabled.
	SPI_RSER_TCF_RE_1      = 0x1        // TCF interrupt requests are enabled.

	// PUSHR: PUSH TX FIFO Register In Master Mode
	SPI_PUSHR_TXDATA_Pos = 0x0        // Position of TXDATA field.
	SPI_PUSHR_TXDATA_Msk = 0xffff     // Bit mask of TXDATA field.
	SPI_PUSHR_PCS_Pos    = 0x10       // Position of PCS field.
	SPI_PUSHR_PCS_Msk    = 0x3f0000   // Bit mask of PCS field.
	SPI_PUSHR_PCS_0      = 0x0        // Negate the PCS[x] signal.
	SPI_PUSHR_PCS_1      = 0x1        // Assert the PCS[x] signal.
	SPI_PUSHR_CTCNT_Pos  = 0x1a       // Position of CTCNT field.
	SPI_PUSHR_CTCNT_Msk  = 0x4000000  // Bit mask of CTCNT field.
	SPI_PUSHR_CTCNT      = 0x4000000  // Bit CTCNT.
	SPI_PUSHR_CTCNT_0    = 0x0        // Do not clear the TCR[TCNT] field.
	SPI_PUSHR_CTCNT_1    = 0x1        // Clear the TCR[TCNT] field.
	SPI_PUSHR_EOQ_Pos    = 0x1b       // Position of EOQ field.
	SPI_PUSHR_EOQ_Msk    = 0x8000000  // Bit mask of EOQ field.
	SPI_PUSHR_EOQ        = 0x8000000  // Bit EOQ.
	SPI_PUSHR_EOQ_0      = 0x0        // The SPI data is not the last data to transfer.
	SPI_PUSHR_EOQ_1      = 0x1        // The SPI data is the last data to transfer.
	SPI_PUSHR_CTAS_Pos   = 0x1c       // Position of CTAS field.
	SPI_PUSHR_CTAS_Msk   = 0x70000000 // Bit mask of CTAS field.
	SPI_PUSHR_CTAS_000   = 0x0        // CTAR0
	SPI_PUSHR_CTAS_001   = 0x1        // CTAR1
	SPI_PUSHR_CONT_Pos   = 0x1f       // Position of CONT field.
	SPI_PUSHR_CONT_Msk   = 0x80000000 // Bit mask of CONT field.
	SPI_PUSHR_CONT       = 0x80000000 // Bit CONT.
	SPI_PUSHR_CONT_0     = 0x0        // Return PCSn signals to their inactive state between transfers.
	SPI_PUSHR_CONT_1     = 0x1        // Keep PCSn signals asserted between transfers.

	// PUSHR_SLAVE: PUSH TX FIFO Register In Slave Mode
	SPI_PUSHR_SLAVE_TXDATA_Pos = 0x0        // Position of TXDATA field.
	SPI_PUSHR_SLAVE_TXDATA_Msk = 0xffffffff // Bit mask of TXDATA field.

	// POPR: POP RX FIFO Register
	SPI_POPR_RXDATA_Pos = 0x0        // Position of RXDATA field.
	SPI_POPR_RXDATA_Msk = 0xffffffff // Bit mask of RXDATA field.

	// TXFR0: Transmit FIFO Registers
	SPI_TXFR_TXDATA_Pos       = 0x0        // Position of TXDATA field.
	SPI_TXFR_TXDATA_Msk       = 0xffff     // Bit mask of TXDATA field.
	SPI_TXFR_TXCMD_TXDATA_Pos = 0x10       // Position of TXCMD_TXDATA field.
	SPI_TXFR_TXCMD_TXDATA_Msk = 0xffff0000 // Bit mask of TXCMD_TXDATA field.

	// RXFR0: Receive FIFO Registers
	SPI_RXFR_RXDATA_Pos = 0x0        // Position of RXDATA field.
	SPI_RXFR_RXDATA_Msk = 0xffffffff // Bit mask of RXDATA field.
)

// Bitfields for I2S0: Inter-IC Sound / Synchronous Audio Interface
const (
	// TCSR: SAI Transmit Control Register
	I2S0_TCSR_FRDE_Pos  = 0x0        // Position of FRDE field.
	I2S0_TCSR_FRDE_Msk  = 0x1        // Bit mask of FRDE field.
	I2S0_TCSR_FRDE      = 0x1        // Bit FRDE.
	I2S0_TCSR_FRDE_0    = 0x0        // Disables the DMA request.
	I2S0_TCSR_FRDE_1    = 0x1        // Enables the DMA request.
	I2S0_TCSR_FWDE_Pos  = 0x1        // Position of FWDE field.
	I2S0_TCSR_FWDE_Msk  = 0x2        // Bit mask of FWDE field.
	I2S0_TCSR_FWDE      = 0x2        // Bit FWDE.
	I2S0_TCSR_FWDE_0    = 0x0        // Disables the DMA request.
	I2S0_TCSR_FWDE_1    = 0x1        // Enables the DMA request.
	I2S0_TCSR_FRIE_Pos  = 0x8        // Position of FRIE field.
	I2S0_TCSR_FRIE_Msk  = 0x100      // Bit mask of FRIE field.
	I2S0_TCSR_FRIE      = 0x100      // Bit FRIE.
	I2S0_TCSR_FRIE_0    = 0x0        // Disables the interrupt.
	I2S0_TCSR_FRIE_1    = 0x1        // Enables the interrupt.
	I2S0_TCSR_FWIE_Pos  = 0x9        // Position of FWIE field.
	I2S0_TCSR_FWIE_Msk  = 0x200      // Bit mask of FWIE field.
	I2S0_TCSR_FWIE      = 0x200      // Bit FWIE.
	I2S0_TCSR_FWIE_0    = 0x0        // Disables the interrupt.
	I2S0_TCSR_FWIE_1    = 0x1        // Enables the interrupt.
	I2S0_TCSR_FEIE_Pos  = 0xa        // Position of FEIE field.
	I2S0_TCSR_FEIE_Msk  = 0x400      // Bit mask of FEIE field.
	I2S0_TCSR_FEIE      = 0x400      // Bit FEIE.
	I2S0_TCSR_FEIE_0    = 0x0        // Disables the interrupt.
	I2S0_TCSR_FEIE_1    = 0x1        // Enables the interrupt.
	I2S0_TCSR_SEIE_Pos  = 0xb        // Position of SEIE field.
	I2S0_TCSR_SEIE_Msk  = 0x800      // Bit mask of SEIE field.
	I2S0_TCSR_SEIE      = 0x800      // Bit SEIE.
	I2S0_TCSR_SEIE_0    = 0x0        // Disables interrupt.
	I2S0_TCSR_SEIE_1    = 0x1        // Enables interrupt.
	I2S0_TCSR_WSIE_Pos  = 0xc        // Position of WSIE field.
	I2S0_TCSR_WSIE_Msk  = 0x1000     // Bit mask of WSIE field.
	I2S0_TCSR_WSIE      = 0x1000     // Bit WSIE.
	I2S0_TCSR_WSIE_0    = 0x0        // Disables interrupt.
	I2S0_TCSR_WSIE_1    = 0x1        // Enables interrupt.
	I2S0_TCSR_FRF_Pos   = 0x10       // Position of FRF field.
	I2S0_TCSR_FRF_Msk   = 0x10000    // Bit mask of FRF field.
	I2S0_TCSR_FRF       = 0x10000    // Bit FRF.
	I2S0_TCSR_FRF_0     = 0x0        // Transmit FIFO watermark has not been reached.
	I2S0_TCSR_FRF_1     = 0x1        // Transmit FIFO watermark has been reached.
	I2S0_TCSR_FWF_Pos   = 0x11       // Position of FWF field.
	I2S0_TCSR_FWF_Msk   = 0x20000    // Bit mask of FWF field.
	I2S0_TCSR_FWF       = 0x20000    // Bit FWF.
	I2S0_TCSR_FWF_0     = 0x0        // No enabled transmit FIFO is empty.
	I2S0_TCSR_FWF_1     = 0x1        // Enabled transmit FIFO is empty.
	I2S0_TCSR_FEF_Pos   = 0x12       // Position of FEF field.
	I2S0_TCSR_FEF_Msk   = 0x40000    // Bit mask of FEF field.
	I2S0_TCSR_FEF       = 0x40000    // Bit FEF.
	I2S0_TCSR_FEF_0     = 0x0        // Transmit underrun not detected.
	I2S0_TCSR_FEF_1     = 0x1        // Transmit underrun detected.
	I2S0_TCSR_SEF_Pos   = 0x13       // Position of SEF field.
	I2S0_TCSR_SEF_Msk   = 0x80000    // Bit mask of SEF field.
	I2S0_TCSR_SEF       = 0x80000    // Bit SEF.
	I2S0_TCSR_SEF_0     = 0x0        // Sync error not detected.
	I2S0_TCSR_SEF_1     = 0x1        // Frame sync error detected.
	I2S0_TCSR_WSF_Pos   = 0x14       // Position of WSF field.
	I2S0_TCSR_WSF_Msk   = 0x100000   // Bit mask of WSF field.
	I2S0_TCSR_WSF       = 0x100000   // Bit WSF.
	I2S0_TCSR_WSF_0     = 0x0        // Start of word not detected.
	I2S0_TCSR_WSF_1     = 0x1        // Start of word detected.
	I2S0_TCSR_SR_Pos    = 0x18       // Position of SR field.
	I2S0_TCSR_SR_Msk    = 0x1000000  // Bit mask of SR field.
	I2S0_TCSR_SR        = 0x1000000  // Bit SR.
	I2S0_TCSR_SR_0      = 0x0        // No effect.
	I2S0_TCSR_SR_1      = 0x1        // Software reset.
	I2S0_TCSR_FR_Pos    = 0x19       // Position of FR field.
	I2S0_TCSR_FR_Msk    = 0x2000000  // Bit mask of FR field.
	I2S0_TCSR_FR        = 0x2000000  // Bit FR.
	I2S0_TCSR_FR_0      = 0x0        // No effect.
	I2S0_TCSR_FR_1      = 0x1        // FIFO reset.
	I2S0_TCSR_BCE_Pos   = 0x1c       // Position of BCE field.
	I2S0_TCSR_BCE_Msk   = 0x10000000 // Bit mask of BCE field.
	I2S0_TCSR_BCE       = 0x10000000 // Bit BCE.
	I2S0_TCSR_BCE_0     = 0x0        // Transmit bit clock is disabled.
	I2S0_TCSR_BCE_1     = 0x1        // Transmit bit clock is enabled.
	I2S0_TCSR_DBGE_Pos  = 0x1d       // Position of DBGE field.
	I2S0_TCSR_DBGE_Msk  = 0x20000000 // Bit mask of DBGE field.
	I2S0_TCSR_DBGE      = 0x20000000 // Bit DBGE.
	I2S0_TCSR_DBGE_0    = 0x0        // Transmitter is disabled in Debug mode, after completing the current frame.
	I2S0_TCSR_DBGE_1    = 0x1        // Transmitter is enabled in Debug mode.
	I2S0_TCSR_STOPE_Pos = 0x1e       // Position of STOPE field.
	I2S0_TCSR_STOPE_Msk = 0x40000000 // Bit mask of STOPE field.
	I2S0_TCSR_STOPE     = 0x40000000 // Bit STOPE.
	I2S0_TCSR_STOPE_0   = 0x0        // Transmitter disabled in Stop mode.
	I2S0_TCSR_STOPE_1   = 0x1        // Transmitter enabled in Stop mode.
	I2S0_TCSR_TE_Pos    = 0x1f       // Position of TE field.
	I2S0_TCSR_TE_Msk    = 0x80000000 // Bit mask of TE field.
	I2S0_TCSR_TE        = 0x80000000 // Bit TE.
	I2S0_TCSR_TE_0      = 0x0        // Transmitter is disabled.
	I2S0_TCSR_TE_1      = 0x1        // Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame.

	// TCR1: SAI Transmit Configuration 1 Register
	I2S0_TCR1_TFW_Pos = 0x0 // Position of TFW field.
	I2S0_TCR1_TFW_Msk = 0x7 // Bit mask of TFW field.

	// TCR2: SAI Transmit Configuration 2 Register
	I2S0_TCR2_DIV_Pos  = 0x0        // Position of DIV field.
	I2S0_TCR2_DIV_Msk  = 0xff       // Bit mask of DIV field.
	I2S0_TCR2_BCD_Pos  = 0x18       // Position of BCD field.
	I2S0_TCR2_BCD_Msk  = 0x1000000  // Bit mask of BCD field.
	I2S0_TCR2_BCD      = 0x1000000  // Bit BCD.
	I2S0_TCR2_BCD_0    = 0x0        // Bit clock is generated externally in Slave mode.
	I2S0_TCR2_BCD_1    = 0x1        // Bit clock is generated internally in Master mode.
	I2S0_TCR2_BCP_Pos  = 0x19       // Position of BCP field.
	I2S0_TCR2_BCP_Msk  = 0x2000000  // Bit mask of BCP field.
	I2S0_TCR2_BCP      = 0x2000000  // Bit BCP.
	I2S0_TCR2_BCP_0    = 0x0        // Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge.
	I2S0_TCR2_BCP_1    = 0x1        // Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge.
	I2S0_TCR2_MSEL_Pos = 0x1a       // Position of MSEL field.
	I2S0_TCR2_MSEL_Msk = 0xc000000  // Bit mask of MSEL field.
	I2S0_TCR2_MSEL_00  = 0x0        // Bus Clock selected.
	I2S0_TCR2_MSEL_01  = 0x1        // Master Clock (MCLK) 1 option selected.
	I2S0_TCR2_MSEL_10  = 0x2        // Master Clock (MCLK) 2 option selected.
	I2S0_TCR2_MSEL_11  = 0x3        // Master Clock (MCLK) 3 option selected.
	I2S0_TCR2_BCI_Pos  = 0x1c       // Position of BCI field.
	I2S0_TCR2_BCI_Msk  = 0x10000000 // Bit mask of BCI field.
	I2S0_TCR2_BCI      = 0x10000000 // Bit BCI.
	I2S0_TCR2_BCI_0    = 0x0        // No effect.
	I2S0_TCR2_BCI_1    = 0x1        // Internal logic is clocked as if bit clock was externally generated.
	I2S0_TCR2_BCS_Pos  = 0x1d       // Position of BCS field.
	I2S0_TCR2_BCS_Msk  = 0x20000000 // Bit mask of BCS field.
	I2S0_TCR2_BCS      = 0x20000000 // Bit BCS.
	I2S0_TCR2_BCS_0    = 0x0        // Use the normal bit clock source.
	I2S0_TCR2_BCS_1    = 0x1        // Swap the bit clock source.
	I2S0_TCR2_SYNC_Pos = 0x1e       // Position of SYNC field.
	I2S0_TCR2_SYNC_Msk = 0xc0000000 // Bit mask of SYNC field.
	I2S0_TCR2_SYNC_00  = 0x0        // Asynchronous mode.
	I2S0_TCR2_SYNC_01  = 0x1        // Synchronous with receiver.
	I2S0_TCR2_SYNC_10  = 0x2        // Synchronous with another SAI transmitter.
	I2S0_TCR2_SYNC_11  = 0x3        // Synchronous with another SAI receiver.

	// TCR3: SAI Transmit Configuration 3 Register
	I2S0_TCR3_WDFL_Pos = 0x0     // Position of WDFL field.
	I2S0_TCR3_WDFL_Msk = 0xf     // Bit mask of WDFL field.
	I2S0_TCR3_TCE_Pos  = 0x10    // Position of TCE field.
	I2S0_TCR3_TCE_Msk  = 0x10000 // Bit mask of TCE field.
	I2S0_TCR3_TCE      = 0x10000 // Bit TCE.
	I2S0_TCR3_TCE_0    = 0x0     // Transmit data channel N is disabled.
	I2S0_TCR3_TCE_1    = 0x1     // Transmit data channel N is enabled.

	// TCR4: SAI Transmit Configuration 4 Register
	I2S0_TCR4_FSD_Pos   = 0x0        // Position of FSD field.
	I2S0_TCR4_FSD_Msk   = 0x1        // Bit mask of FSD field.
	I2S0_TCR4_FSD       = 0x1        // Bit FSD.
	I2S0_TCR4_FSD_0     = 0x0        // Frame sync is generated externally in Slave mode.
	I2S0_TCR4_FSD_1     = 0x1        // Frame sync is generated internally in Master mode.
	I2S0_TCR4_FSP_Pos   = 0x1        // Position of FSP field.
	I2S0_TCR4_FSP_Msk   = 0x2        // Bit mask of FSP field.
	I2S0_TCR4_FSP       = 0x2        // Bit FSP.
	I2S0_TCR4_FSP_0     = 0x0        // Frame sync is active high.
	I2S0_TCR4_FSP_1     = 0x1        // Frame sync is active low.
	I2S0_TCR4_ONDEM_Pos = 0x2        // Position of ONDEM field.
	I2S0_TCR4_ONDEM_Msk = 0x4        // Bit mask of ONDEM field.
	I2S0_TCR4_ONDEM     = 0x4        // Bit ONDEM.
	I2S0_TCR4_ONDEM_0   = 0x0        // Internal frame sync is generated continuously.
	I2S0_TCR4_ONDEM_1   = 0x1        // Internal frame sync is generated when the FIFO warning flag is clear.
	I2S0_TCR4_FSE_Pos   = 0x3        // Position of FSE field.
	I2S0_TCR4_FSE_Msk   = 0x8        // Bit mask of FSE field.
	I2S0_TCR4_FSE       = 0x8        // Bit FSE.
	I2S0_TCR4_FSE_0     = 0x0        // Frame sync asserts with the first bit of the frame.
	I2S0_TCR4_FSE_1     = 0x1        // Frame sync asserts one bit before the first bit of the frame.
	I2S0_TCR4_MF_Pos    = 0x4        // Position of MF field.
	I2S0_TCR4_MF_Msk    = 0x10       // Bit mask of MF field.
	I2S0_TCR4_MF        = 0x10       // Bit MF.
	I2S0_TCR4_MF_0      = 0x0        // LSB is transmitted first.
	I2S0_TCR4_MF_1      = 0x1        // MSB is transmitted first.
	I2S0_TCR4_SYWD_Pos  = 0x8        // Position of SYWD field.
	I2S0_TCR4_SYWD_Msk  = 0x1f00     // Bit mask of SYWD field.
	I2S0_TCR4_FRSZ_Pos  = 0x10       // Position of FRSZ field.
	I2S0_TCR4_FRSZ_Msk  = 0xf0000    // Bit mask of FRSZ field.
	I2S0_TCR4_FPACK_Pos = 0x18       // Position of FPACK field.
	I2S0_TCR4_FPACK_Msk = 0x3000000  // Bit mask of FPACK field.
	I2S0_TCR4_FPACK_00  = 0x0        // FIFO packing is disabled
	I2S0_TCR4_FPACK_10  = 0x2        // 8-bit FIFO packing is enabled
	I2S0_TCR4_FPACK_11  = 0x3        // 16-bit FIFO packing is enabled
	I2S0_TCR4_FCONT_Pos = 0x1c       // Position of FCONT field.
	I2S0_TCR4_FCONT_Msk = 0x10000000 // Bit mask of FCONT field.
	I2S0_TCR4_FCONT     = 0x10000000 // Bit FCONT.
	I2S0_TCR4_FCONT_0   = 0x0        // On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
	I2S0_TCR4_FCONT_1   = 0x1        // On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.

	// TCR5: SAI Transmit Configuration 5 Register
	I2S0_TCR5_FBT_Pos = 0x8        // Position of FBT field.
	I2S0_TCR5_FBT_Msk = 0x1f00     // Bit mask of FBT field.
	I2S0_TCR5_W0W_Pos = 0x10       // Position of W0W field.
	I2S0_TCR5_W0W_Msk = 0x1f0000   // Bit mask of W0W field.
	I2S0_TCR5_WNW_Pos = 0x18       // Position of WNW field.
	I2S0_TCR5_WNW_Msk = 0x1f000000 // Bit mask of WNW field.

	// TDR: SAI Transmit Data Register
	I2S0_TDR_TDR_Pos = 0x0        // Position of TDR field.
	I2S0_TDR_TDR_Msk = 0xffffffff // Bit mask of TDR field.

	// TFR: SAI Transmit FIFO Register
	I2S0_TFR_RFP_Pos = 0x0     // Position of RFP field.
	I2S0_TFR_RFP_Msk = 0xf     // Bit mask of RFP field.
	I2S0_TFR_WFP_Pos = 0x10    // Position of WFP field.
	I2S0_TFR_WFP_Msk = 0xf0000 // Bit mask of WFP field.

	// TMR: SAI Transmit Mask Register
	I2S0_TMR_TWM_Pos = 0x0    // Position of TWM field.
	I2S0_TMR_TWM_Msk = 0xffff // Bit mask of TWM field.
	I2S0_TMR_TWM_0   = 0x0    // Word N is enabled.
	I2S0_TMR_TWM_1   = 0x1    // Word N is masked. The transmit data pins are tri-stated when masked.

	// RCSR: SAI Receive Control Register
	I2S0_RCSR_FRDE_Pos  = 0x0        // Position of FRDE field.
	I2S0_RCSR_FRDE_Msk  = 0x1        // Bit mask of FRDE field.
	I2S0_RCSR_FRDE      = 0x1        // Bit FRDE.
	I2S0_RCSR_FRDE_0    = 0x0        // Disables the DMA request.
	I2S0_RCSR_FRDE_1    = 0x1        // Enables the DMA request.
	I2S0_RCSR_FWDE_Pos  = 0x1        // Position of FWDE field.
	I2S0_RCSR_FWDE_Msk  = 0x2        // Bit mask of FWDE field.
	I2S0_RCSR_FWDE      = 0x2        // Bit FWDE.
	I2S0_RCSR_FWDE_0    = 0x0        // Disables the DMA request.
	I2S0_RCSR_FWDE_1    = 0x1        // Enables the DMA request.
	I2S0_RCSR_FRIE_Pos  = 0x8        // Position of FRIE field.
	I2S0_RCSR_FRIE_Msk  = 0x100      // Bit mask of FRIE field.
	I2S0_RCSR_FRIE      = 0x100      // Bit FRIE.
	I2S0_RCSR_FRIE_0    = 0x0        // Disables the interrupt.
	I2S0_RCSR_FRIE_1    = 0x1        // Enables the interrupt.
	I2S0_RCSR_FWIE_Pos  = 0x9        // Position of FWIE field.
	I2S0_RCSR_FWIE_Msk  = 0x200      // Bit mask of FWIE field.
	I2S0_RCSR_FWIE      = 0x200      // Bit FWIE.
	I2S0_RCSR_FWIE_0    = 0x0        // Disables the interrupt.
	I2S0_RCSR_FWIE_1    = 0x1        // Enables the interrupt.
	I2S0_RCSR_FEIE_Pos  = 0xa        // Position of FEIE field.
	I2S0_RCSR_FEIE_Msk  = 0x400      // Bit mask of FEIE field.
	I2S0_RCSR_FEIE      = 0x400      // Bit FEIE.
	I2S0_RCSR_FEIE_0    = 0x0        // Disables the interrupt.
	I2S0_RCSR_FEIE_1    = 0x1        // Enables the interrupt.
	I2S0_RCSR_SEIE_Pos  = 0xb        // Position of SEIE field.
	I2S0_RCSR_SEIE_Msk  = 0x800      // Bit mask of SEIE field.
	I2S0_RCSR_SEIE      = 0x800      // Bit SEIE.
	I2S0_RCSR_SEIE_0    = 0x0        // Disables interrupt.
	I2S0_RCSR_SEIE_1    = 0x1        // Enables interrupt.
	I2S0_RCSR_WSIE_Pos  = 0xc        // Position of WSIE field.
	I2S0_RCSR_WSIE_Msk  = 0x1000     // Bit mask of WSIE field.
	I2S0_RCSR_WSIE      = 0x1000     // Bit WSIE.
	I2S0_RCSR_WSIE_0    = 0x0        // Disables interrupt.
	I2S0_RCSR_WSIE_1    = 0x1        // Enables interrupt.
	I2S0_RCSR_FRF_Pos   = 0x10       // Position of FRF field.
	I2S0_RCSR_FRF_Msk   = 0x10000    // Bit mask of FRF field.
	I2S0_RCSR_FRF       = 0x10000    // Bit FRF.
	I2S0_RCSR_FRF_0     = 0x0        // Receive FIFO watermark not reached.
	I2S0_RCSR_FRF_1     = 0x1        // Receive FIFO watermark has been reached.
	I2S0_RCSR_FWF_Pos   = 0x11       // Position of FWF field.
	I2S0_RCSR_FWF_Msk   = 0x20000    // Bit mask of FWF field.
	I2S0_RCSR_FWF       = 0x20000    // Bit FWF.
	I2S0_RCSR_FWF_0     = 0x0        // No enabled receive FIFO is full.
	I2S0_RCSR_FWF_1     = 0x1        // Enabled receive FIFO is full.
	I2S0_RCSR_FEF_Pos   = 0x12       // Position of FEF field.
	I2S0_RCSR_FEF_Msk   = 0x40000    // Bit mask of FEF field.
	I2S0_RCSR_FEF       = 0x40000    // Bit FEF.
	I2S0_RCSR_FEF_0     = 0x0        // Receive overflow not detected.
	I2S0_RCSR_FEF_1     = 0x1        // Receive overflow detected.
	I2S0_RCSR_SEF_Pos   = 0x13       // Position of SEF field.
	I2S0_RCSR_SEF_Msk   = 0x80000    // Bit mask of SEF field.
	I2S0_RCSR_SEF       = 0x80000    // Bit SEF.
	I2S0_RCSR_SEF_0     = 0x0        // Sync error not detected.
	I2S0_RCSR_SEF_1     = 0x1        // Frame sync error detected.
	I2S0_RCSR_WSF_Pos   = 0x14       // Position of WSF field.
	I2S0_RCSR_WSF_Msk   = 0x100000   // Bit mask of WSF field.
	I2S0_RCSR_WSF       = 0x100000   // Bit WSF.
	I2S0_RCSR_WSF_0     = 0x0        // Start of word not detected.
	I2S0_RCSR_WSF_1     = 0x1        // Start of word detected.
	I2S0_RCSR_SR_Pos    = 0x18       // Position of SR field.
	I2S0_RCSR_SR_Msk    = 0x1000000  // Bit mask of SR field.
	I2S0_RCSR_SR        = 0x1000000  // Bit SR.
	I2S0_RCSR_SR_0      = 0x0        // No effect.
	I2S0_RCSR_SR_1      = 0x1        // Software reset.
	I2S0_RCSR_FR_Pos    = 0x19       // Position of FR field.
	I2S0_RCSR_FR_Msk    = 0x2000000  // Bit mask of FR field.
	I2S0_RCSR_FR        = 0x2000000  // Bit FR.
	I2S0_RCSR_FR_0      = 0x0        // No effect.
	I2S0_RCSR_FR_1      = 0x1        // FIFO reset.
	I2S0_RCSR_BCE_Pos   = 0x1c       // Position of BCE field.
	I2S0_RCSR_BCE_Msk   = 0x10000000 // Bit mask of BCE field.
	I2S0_RCSR_BCE       = 0x10000000 // Bit BCE.
	I2S0_RCSR_BCE_0     = 0x0        // Receive bit clock is disabled.
	I2S0_RCSR_BCE_1     = 0x1        // Receive bit clock is enabled.
	I2S0_RCSR_DBGE_Pos  = 0x1d       // Position of DBGE field.
	I2S0_RCSR_DBGE_Msk  = 0x20000000 // Bit mask of DBGE field.
	I2S0_RCSR_DBGE      = 0x20000000 // Bit DBGE.
	I2S0_RCSR_DBGE_0    = 0x0        // Receiver is disabled in Debug mode, after completing the current frame.
	I2S0_RCSR_DBGE_1    = 0x1        // Receiver is enabled in Debug mode.
	I2S0_RCSR_STOPE_Pos = 0x1e       // Position of STOPE field.
	I2S0_RCSR_STOPE_Msk = 0x40000000 // Bit mask of STOPE field.
	I2S0_RCSR_STOPE     = 0x40000000 // Bit STOPE.
	I2S0_RCSR_STOPE_0   = 0x0        // Receiver disabled in Stop mode.
	I2S0_RCSR_STOPE_1   = 0x1        // Receiver enabled in Stop mode.
	I2S0_RCSR_RE_Pos    = 0x1f       // Position of RE field.
	I2S0_RCSR_RE_Msk    = 0x80000000 // Bit mask of RE field.
	I2S0_RCSR_RE        = 0x80000000 // Bit RE.
	I2S0_RCSR_RE_0      = 0x0        // Receiver is disabled.
	I2S0_RCSR_RE_1      = 0x1        // Receiver is enabled, or receiver has been disabled and has not yet reached end of frame.

	// RCR1: SAI Receive Configuration 1 Register
	I2S0_RCR1_RFW_Pos = 0x0 // Position of RFW field.
	I2S0_RCR1_RFW_Msk = 0x7 // Bit mask of RFW field.

	// RCR2: SAI Receive Configuration 2 Register
	I2S0_RCR2_DIV_Pos  = 0x0        // Position of DIV field.
	I2S0_RCR2_DIV_Msk  = 0xff       // Bit mask of DIV field.
	I2S0_RCR2_BCD_Pos  = 0x18       // Position of BCD field.
	I2S0_RCR2_BCD_Msk  = 0x1000000  // Bit mask of BCD field.
	I2S0_RCR2_BCD      = 0x1000000  // Bit BCD.
	I2S0_RCR2_BCD_0    = 0x0        // Bit clock is generated externally in Slave mode.
	I2S0_RCR2_BCD_1    = 0x1        // Bit clock is generated internally in Master mode.
	I2S0_RCR2_BCP_Pos  = 0x19       // Position of BCP field.
	I2S0_RCR2_BCP_Msk  = 0x2000000  // Bit mask of BCP field.
	I2S0_RCR2_BCP      = 0x2000000  // Bit BCP.
	I2S0_RCR2_BCP_0    = 0x0        // Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge.
	I2S0_RCR2_BCP_1    = 0x1        // Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge.
	I2S0_RCR2_MSEL_Pos = 0x1a       // Position of MSEL field.
	I2S0_RCR2_MSEL_Msk = 0xc000000  // Bit mask of MSEL field.
	I2S0_RCR2_MSEL_00  = 0x0        // Bus Clock selected.
	I2S0_RCR2_MSEL_01  = 0x1        // Master Clock (MCLK) 1 option selected.
	I2S0_RCR2_MSEL_10  = 0x2        // Master Clock (MCLK) 2 option selected.
	I2S0_RCR2_MSEL_11  = 0x3        // Master Clock (MCLK) 3 option selected.
	I2S0_RCR2_BCI_Pos  = 0x1c       // Position of BCI field.
	I2S0_RCR2_BCI_Msk  = 0x10000000 // Bit mask of BCI field.
	I2S0_RCR2_BCI      = 0x10000000 // Bit BCI.
	I2S0_RCR2_BCI_0    = 0x0        // No effect.
	I2S0_RCR2_BCI_1    = 0x1        // Internal logic is clocked as if bit clock was externally generated.
	I2S0_RCR2_BCS_Pos  = 0x1d       // Position of BCS field.
	I2S0_RCR2_BCS_Msk  = 0x20000000 // Bit mask of BCS field.
	I2S0_RCR2_BCS      = 0x20000000 // Bit BCS.
	I2S0_RCR2_BCS_0    = 0x0        // Use the normal bit clock source.
	I2S0_RCR2_BCS_1    = 0x1        // Swap the bit clock source.
	I2S0_RCR2_SYNC_Pos = 0x1e       // Position of SYNC field.
	I2S0_RCR2_SYNC_Msk = 0xc0000000 // Bit mask of SYNC field.
	I2S0_RCR2_SYNC_00  = 0x0        // Asynchronous mode.
	I2S0_RCR2_SYNC_01  = 0x1        // Synchronous with transmitter.
	I2S0_RCR2_SYNC_10  = 0x2        // Synchronous with another SAI receiver.
	I2S0_RCR2_SYNC_11  = 0x3        // Synchronous with another SAI transmitter.

	// RCR3: SAI Receive Configuration 3 Register
	I2S0_RCR3_WDFL_Pos = 0x0     // Position of WDFL field.
	I2S0_RCR3_WDFL_Msk = 0xf     // Bit mask of WDFL field.
	I2S0_RCR3_RCE_Pos  = 0x10    // Position of RCE field.
	I2S0_RCR3_RCE_Msk  = 0x10000 // Bit mask of RCE field.
	I2S0_RCR3_RCE      = 0x10000 // Bit RCE.
	I2S0_RCR3_RCE_0    = 0x0     // Receive data channel N is disabled.
	I2S0_RCR3_RCE_1    = 0x1     // Receive data channel N is enabled.

	// RCR4: SAI Receive Configuration 4 Register
	I2S0_RCR4_FSD_Pos   = 0x0        // Position of FSD field.
	I2S0_RCR4_FSD_Msk   = 0x1        // Bit mask of FSD field.
	I2S0_RCR4_FSD       = 0x1        // Bit FSD.
	I2S0_RCR4_FSD_0     = 0x0        // Frame Sync is generated externally in Slave mode.
	I2S0_RCR4_FSD_1     = 0x1        // Frame Sync is generated internally in Master mode.
	I2S0_RCR4_FSP_Pos   = 0x1        // Position of FSP field.
	I2S0_RCR4_FSP_Msk   = 0x2        // Bit mask of FSP field.
	I2S0_RCR4_FSP       = 0x2        // Bit FSP.
	I2S0_RCR4_FSP_0     = 0x0        // Frame sync is active high.
	I2S0_RCR4_FSP_1     = 0x1        // Frame sync is active low.
	I2S0_RCR4_ONDEM_Pos = 0x2        // Position of ONDEM field.
	I2S0_RCR4_ONDEM_Msk = 0x4        // Bit mask of ONDEM field.
	I2S0_RCR4_ONDEM     = 0x4        // Bit ONDEM.
	I2S0_RCR4_ONDEM_0   = 0x0        // Internal frame sync is generated continuously.
	I2S0_RCR4_ONDEM_1   = 0x1        // Internal frame sync is generated when the FIFO warning flag is clear.
	I2S0_RCR4_FSE_Pos   = 0x3        // Position of FSE field.
	I2S0_RCR4_FSE_Msk   = 0x8        // Bit mask of FSE field.
	I2S0_RCR4_FSE       = 0x8        // Bit FSE.
	I2S0_RCR4_FSE_0     = 0x0        // Frame sync asserts with the first bit of the frame.
	I2S0_RCR4_FSE_1     = 0x1        // Frame sync asserts one bit before the first bit of the frame.
	I2S0_RCR4_MF_Pos    = 0x4        // Position of MF field.
	I2S0_RCR4_MF_Msk    = 0x10       // Bit mask of MF field.
	I2S0_RCR4_MF        = 0x10       // Bit MF.
	I2S0_RCR4_MF_0      = 0x0        // LSB is received first.
	I2S0_RCR4_MF_1      = 0x1        // MSB is received first.
	I2S0_RCR4_SYWD_Pos  = 0x8        // Position of SYWD field.
	I2S0_RCR4_SYWD_Msk  = 0x1f00     // Bit mask of SYWD field.
	I2S0_RCR4_FRSZ_Pos  = 0x10       // Position of FRSZ field.
	I2S0_RCR4_FRSZ_Msk  = 0xf0000    // Bit mask of FRSZ field.
	I2S0_RCR4_FPACK_Pos = 0x18       // Position of FPACK field.
	I2S0_RCR4_FPACK_Msk = 0x3000000  // Bit mask of FPACK field.
	I2S0_RCR4_FPACK_00  = 0x0        // FIFO packing is disabled
	I2S0_RCR4_FPACK_10  = 0x2        // 8-bit FIFO packing is enabled
	I2S0_RCR4_FPACK_11  = 0x3        // 16-bit FIFO packing is enabled
	I2S0_RCR4_FCONT_Pos = 0x1c       // Position of FCONT field.
	I2S0_RCR4_FCONT_Msk = 0x10000000 // Bit mask of FCONT field.
	I2S0_RCR4_FCONT     = 0x10000000 // Bit FCONT.
	I2S0_RCR4_FCONT_0   = 0x0        // On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
	I2S0_RCR4_FCONT_1   = 0x1        // On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.

	// RCR5: SAI Receive Configuration 5 Register
	I2S0_RCR5_FBT_Pos = 0x8        // Position of FBT field.
	I2S0_RCR5_FBT_Msk = 0x1f00     // Bit mask of FBT field.
	I2S0_RCR5_W0W_Pos = 0x10       // Position of W0W field.
	I2S0_RCR5_W0W_Msk = 0x1f0000   // Bit mask of W0W field.
	I2S0_RCR5_WNW_Pos = 0x18       // Position of WNW field.
	I2S0_RCR5_WNW_Msk = 0x1f000000 // Bit mask of WNW field.

	// RDR: SAI Receive Data Register
	I2S0_RDR_RDR_Pos = 0x0        // Position of RDR field.
	I2S0_RDR_RDR_Msk = 0xffffffff // Bit mask of RDR field.

	// RFR: SAI Receive FIFO Register
	I2S0_RFR_RFP_Pos = 0x0     // Position of RFP field.
	I2S0_RFR_RFP_Msk = 0xf     // Bit mask of RFP field.
	I2S0_RFR_WFP_Pos = 0x10    // Position of WFP field.
	I2S0_RFR_WFP_Msk = 0xf0000 // Bit mask of WFP field.

	// RMR: SAI Receive Mask Register
	I2S0_RMR_RWM_Pos = 0x0    // Position of RWM field.
	I2S0_RMR_RWM_Msk = 0xffff // Bit mask of RWM field.
	I2S0_RMR_RWM_0   = 0x0    // Word N is enabled.
	I2S0_RMR_RWM_1   = 0x1    // Word N is masked.

	// MCR: SAI MCLK Control Register
	I2S0_MCR_MICS_Pos = 0x18       // Position of MICS field.
	I2S0_MCR_MICS_Msk = 0x3000000  // Bit mask of MICS field.
	I2S0_MCR_MICS_00  = 0x0        // MCLK divider input clock 0 selected.
	I2S0_MCR_MICS_01  = 0x1        // MCLK divider input clock 1 selected.
	I2S0_MCR_MICS_10  = 0x2        // MCLK divider input clock 2 selected.
	I2S0_MCR_MICS_11  = 0x3        // MCLK divider input clock 3 selected.
	I2S0_MCR_MOE_Pos  = 0x1e       // Position of MOE field.
	I2S0_MCR_MOE_Msk  = 0x40000000 // Bit mask of MOE field.
	I2S0_MCR_MOE      = 0x40000000 // Bit MOE.
	I2S0_MCR_MOE_0    = 0x0        // MCLK signal pin is configured as an input that bypasses the MCLK divider.
	I2S0_MCR_MOE_1    = 0x1        // MCLK signal pin is configured as an output from the MCLK divider and the MCLK divider is enabled.
	I2S0_MCR_DUF_Pos  = 0x1f       // Position of DUF field.
	I2S0_MCR_DUF_Msk  = 0x80000000 // Bit mask of DUF field.
	I2S0_MCR_DUF      = 0x80000000 // Bit DUF.
	I2S0_MCR_DUF_0    = 0x0        // MCLK divider ratio is not being updated currently.
	I2S0_MCR_DUF_1    = 0x1        // MCLK divider ratio is updating on-the-fly. Further updates to the MCLK divider ratio are blocked while this flag remains set.

	// MDR: SAI MCLK Divide Register
	I2S0_MDR_DIVIDE_Pos = 0x0     // Position of DIVIDE field.
	I2S0_MDR_DIVIDE_Msk = 0xfff   // Bit mask of DIVIDE field.
	I2S0_MDR_FRACT_Pos  = 0xc     // Position of FRACT field.
	I2S0_MDR_FRACT_Msk  = 0xff000 // Bit mask of FRACT field.
)

// Bitfields for CRC: Cyclic Redundancy Check
const (
	// DATA: CRC Data register
	CRC_DATA_LL_Pos = 0x0        // Position of LL field.
	CRC_DATA_LL_Msk = 0xff       // Bit mask of LL field.
	CRC_DATA_LU_Pos = 0x8        // Position of LU field.
	CRC_DATA_LU_Msk = 0xff00     // Bit mask of LU field.
	CRC_DATA_HL_Pos = 0x10       // Position of HL field.
	CRC_DATA_HL_Msk = 0xff0000   // Bit mask of HL field.
	CRC_DATA_HU_Pos = 0x18       // Position of HU field.
	CRC_DATA_HU_Msk = 0xff000000 // Bit mask of HU field.

	// DATAL: CRC_DATAL register.
	CRC_DATAL_DATAL_Pos = 0x0    // Position of DATAL field.
	CRC_DATAL_DATAL_Msk = 0xffff // Bit mask of DATAL field.

	// DATALL: CRC_DATALL register.
	CRC_DATALL_DATALL_Pos = 0x0  // Position of DATALL field.
	CRC_DATALL_DATALL_Msk = 0xff // Bit mask of DATALL field.

	// DATALU: CRC_DATALU register.
	CRC_DATALU_DATALU_Pos = 0x0  // Position of DATALU field.
	CRC_DATALU_DATALU_Msk = 0xff // Bit mask of DATALU field.

	// DATAH: CRC_DATAH register.
	CRC_DATAH_DATAH_Pos = 0x0    // Position of DATAH field.
	CRC_DATAH_DATAH_Msk = 0xffff // Bit mask of DATAH field.

	// DATAHL: CRC_DATAHL register.
	CRC_DATAHL_DATAHL_Pos = 0x0  // Position of DATAHL field.
	CRC_DATAHL_DATAHL_Msk = 0xff // Bit mask of DATAHL field.

	// DATAHU: CRC_DATAHU register.
	CRC_DATAHU_DATAHU_Pos = 0x0  // Position of DATAHU field.
	CRC_DATAHU_DATAHU_Msk = 0xff // Bit mask of DATAHU field.

	// GPOLY: CRC Polynomial register
	CRC_GPOLY_LOW_Pos  = 0x0        // Position of LOW field.
	CRC_GPOLY_LOW_Msk  = 0xffff     // Bit mask of LOW field.
	CRC_GPOLY_HIGH_Pos = 0x10       // Position of HIGH field.
	CRC_GPOLY_HIGH_Msk = 0xffff0000 // Bit mask of HIGH field.

	// GPOLYL: CRC_GPOLYL register.
	CRC_GPOLYL_GPOLYL_Pos = 0x0    // Position of GPOLYL field.
	CRC_GPOLYL_GPOLYL_Msk = 0xffff // Bit mask of GPOLYL field.

	// GPOLYLL: CRC_GPOLYLL register.
	CRC_GPOLYLL_GPOLYLL_Pos = 0x0  // Position of GPOLYLL field.
	CRC_GPOLYLL_GPOLYLL_Msk = 0xff // Bit mask of GPOLYLL field.

	// GPOLYLU: CRC_GPOLYLU register.
	CRC_GPOLYLU_GPOLYLU_Pos = 0x0  // Position of GPOLYLU field.
	CRC_GPOLYLU_GPOLYLU_Msk = 0xff // Bit mask of GPOLYLU field.

	// GPOLYH: CRC_GPOLYH register.
	CRC_GPOLYH_GPOLYH_Pos = 0x0    // Position of GPOLYH field.
	CRC_GPOLYH_GPOLYH_Msk = 0xffff // Bit mask of GPOLYH field.

	// GPOLYHL: CRC_GPOLYHL register.
	CRC_GPOLYHL_GPOLYHL_Pos = 0x0  // Position of GPOLYHL field.
	CRC_GPOLYHL_GPOLYHL_Msk = 0xff // Bit mask of GPOLYHL field.

	// GPOLYHU: CRC_GPOLYHU register.
	CRC_GPOLYHU_GPOLYHU_Pos = 0x0  // Position of GPOLYHU field.
	CRC_GPOLYHU_GPOLYHU_Msk = 0xff // Bit mask of GPOLYHU field.

	// CTRL: CRC Control register
	CRC_CTRL_TCRC_Pos = 0x18       // Position of TCRC field.
	CRC_CTRL_TCRC_Msk = 0x1000000  // Bit mask of TCRC field.
	CRC_CTRL_TCRC     = 0x1000000  // Bit TCRC.
	CRC_CTRL_TCRC_0   = 0x0        // 16-bit CRC protocol.
	CRC_CTRL_TCRC_1   = 0x1        // 32-bit CRC protocol.
	CRC_CTRL_WAS_Pos  = 0x19       // Position of WAS field.
	CRC_CTRL_WAS_Msk  = 0x2000000  // Bit mask of WAS field.
	CRC_CTRL_WAS      = 0x2000000  // Bit WAS.
	CRC_CTRL_WAS_0    = 0x0        // Writes to the CRC data register are data values.
	CRC_CTRL_WAS_1    = 0x1        // Writes to the CRC data register are seed values.
	CRC_CTRL_FXOR_Pos = 0x1a       // Position of FXOR field.
	CRC_CTRL_FXOR_Msk = 0x4000000  // Bit mask of FXOR field.
	CRC_CTRL_FXOR     = 0x4000000  // Bit FXOR.
	CRC_CTRL_FXOR_0   = 0x0        // No XOR on reading.
	CRC_CTRL_FXOR_1   = 0x1        // Invert or complement the read value of the CRC Data register.
	CRC_CTRL_TOTR_Pos = 0x1c       // Position of TOTR field.
	CRC_CTRL_TOTR_Msk = 0x30000000 // Bit mask of TOTR field.
	CRC_CTRL_TOTR_00  = 0x0        // No transposition.
	CRC_CTRL_TOTR_01  = 0x1        // Bits in bytes are transposed; bytes are not transposed.
	CRC_CTRL_TOTR_10  = 0x2        // Both bits in bytes and bytes are transposed.
	CRC_CTRL_TOTR_11  = 0x3        // Only bytes are transposed; no bits in a byte are transposed.
	CRC_CTRL_TOT_Pos  = 0x1e       // Position of TOT field.
	CRC_CTRL_TOT_Msk  = 0xc0000000 // Bit mask of TOT field.
	CRC_CTRL_TOT_00   = 0x0        // No transposition.
	CRC_CTRL_TOT_01   = 0x1        // Bits in bytes are transposed; bytes are not transposed.
	CRC_CTRL_TOT_10   = 0x2        // Both bits in bytes and bytes are transposed.
	CRC_CTRL_TOT_11   = 0x3        // Only bytes are transposed; no bits in a byte are transposed.

	// CTRLHU: CRC_CTRLHU register.
	CRC_CTRLHU_TCRC_Pos = 0x0  // Position of TCRC field.
	CRC_CTRLHU_TCRC_Msk = 0x1  // Bit mask of TCRC field.
	CRC_CTRLHU_TCRC     = 0x1  // Bit TCRC.
	CRC_CTRLHU_TCRC_0   = 0x0  // 16-bit CRC protocol.
	CRC_CTRLHU_TCRC_1   = 0x1  // 32-bit CRC protocol.
	CRC_CTRLHU_WAS_Pos  = 0x1  // Position of WAS field.
	CRC_CTRLHU_WAS_Msk  = 0x2  // Bit mask of WAS field.
	CRC_CTRLHU_WAS      = 0x2  // Bit WAS.
	CRC_CTRLHU_WAS_0    = 0x0  // Writes to CRC data register are data values.
	CRC_CTRLHU_WAS_1    = 0x1  // Writes to CRC data reguster are seed values.
	CRC_CTRLHU_FXOR_Pos = 0x2  // Position of FXOR field.
	CRC_CTRLHU_FXOR_Msk = 0x4  // Bit mask of FXOR field.
	CRC_CTRLHU_FXOR     = 0x4  // Bit FXOR.
	CRC_CTRLHU_FXOR_0   = 0x0  // No XOR on reading.
	CRC_CTRLHU_FXOR_1   = 0x1  // Invert or complement the read value of CRC data register.
	CRC_CTRLHU_TOTR_Pos = 0x4  // Position of TOTR field.
	CRC_CTRLHU_TOTR_Msk = 0x30 // Bit mask of TOTR field.
	CRC_CTRLHU_TOTR_00  = 0x0  // No Transposition.
	CRC_CTRLHU_TOTR_01  = 0x1  // Bits in bytes are transposed, bytes are not transposed.
	CRC_CTRLHU_TOTR_10  = 0x2  // Both bits in bytes and bytes are transposed.
	CRC_CTRLHU_TOTR_11  = 0x3  // Only bytes are transposed; no bits in a byte are transposed.
	CRC_CTRLHU_TOT_Pos  = 0x6  // Position of TOT field.
	CRC_CTRLHU_TOT_Msk  = 0xc0 // Bit mask of TOT field.
	CRC_CTRLHU_TOT_00   = 0x0  // No Transposition.
	CRC_CTRLHU_TOT_01   = 0x1  // Bits in bytes are transposed, bytes are not transposed.
	CRC_CTRLHU_TOT_10   = 0x2  // Both bits in bytes and bytes are transposed.
	CRC_CTRLHU_TOT_11   = 0x3  // Only bytes are transposed; no bits in a byte are transposed.
)

// Bitfields for PDB0: Programmable Delay Block
const (
	// SC: Status and Control register
	PDB0_SC_LDOK_Pos      = 0x0     // Position of LDOK field.
	PDB0_SC_LDOK_Msk      = 0x1     // Bit mask of LDOK field.
	PDB0_SC_LDOK          = 0x1     // Bit LDOK.
	PDB0_SC_CONT_Pos      = 0x1     // Position of CONT field.
	PDB0_SC_CONT_Msk      = 0x2     // Bit mask of CONT field.
	PDB0_SC_CONT          = 0x2     // Bit CONT.
	PDB0_SC_CONT_0        = 0x0     // PDB operation in One-Shot mode
	PDB0_SC_CONT_1        = 0x1     // PDB operation in Continuous mode
	PDB0_SC_MULT_Pos      = 0x2     // Position of MULT field.
	PDB0_SC_MULT_Msk      = 0xc     // Bit mask of MULT field.
	PDB0_SC_MULT_00       = 0x0     // Multiplication factor is 1.
	PDB0_SC_MULT_01       = 0x1     // Multiplication factor is 10.
	PDB0_SC_MULT_10       = 0x2     // Multiplication factor is 20.
	PDB0_SC_MULT_11       = 0x3     // Multiplication factor is 40.
	PDB0_SC_PDBIE_Pos     = 0x5     // Position of PDBIE field.
	PDB0_SC_PDBIE_Msk     = 0x20    // Bit mask of PDBIE field.
	PDB0_SC_PDBIE         = 0x20    // Bit PDBIE.
	PDB0_SC_PDBIE_0       = 0x0     // PDB interrupt disabled.
	PDB0_SC_PDBIE_1       = 0x1     // PDB interrupt enabled.
	PDB0_SC_PDBIF_Pos     = 0x6     // Position of PDBIF field.
	PDB0_SC_PDBIF_Msk     = 0x40    // Bit mask of PDBIF field.
	PDB0_SC_PDBIF         = 0x40    // Bit PDBIF.
	PDB0_SC_PDBEN_Pos     = 0x7     // Position of PDBEN field.
	PDB0_SC_PDBEN_Msk     = 0x80    // Bit mask of PDBEN field.
	PDB0_SC_PDBEN         = 0x80    // Bit PDBEN.
	PDB0_SC_PDBEN_0       = 0x0     // PDB disabled. Counter is off.
	PDB0_SC_PDBEN_1       = 0x1     // PDB enabled.
	PDB0_SC_TRGSEL_Pos    = 0x8     // Position of TRGSEL field.
	PDB0_SC_TRGSEL_Msk    = 0xf00   // Bit mask of TRGSEL field.
	PDB0_SC_TRGSEL_0000   = 0x0     // Trigger-In 0 is selected.
	PDB0_SC_TRGSEL_0001   = 0x1     // Trigger-In 1 is selected.
	PDB0_SC_TRGSEL_0010   = 0x2     // Trigger-In 2 is selected.
	PDB0_SC_TRGSEL_0011   = 0x3     // Trigger-In 3 is selected.
	PDB0_SC_TRGSEL_0100   = 0x4     // Trigger-In 4 is selected.
	PDB0_SC_TRGSEL_0101   = 0x5     // Trigger-In 5 is selected.
	PDB0_SC_TRGSEL_0110   = 0x6     // Trigger-In 6 is selected.
	PDB0_SC_TRGSEL_0111   = 0x7     // Trigger-In 7 is selected.
	PDB0_SC_TRGSEL_1000   = 0x8     // Trigger-In 8 is selected.
	PDB0_SC_TRGSEL_1001   = 0x9     // Trigger-In 9 is selected.
	PDB0_SC_TRGSEL_1010   = 0xa     // Trigger-In 10 is selected.
	PDB0_SC_TRGSEL_1011   = 0xb     // Trigger-In 11 is selected.
	PDB0_SC_TRGSEL_1100   = 0xc     // Trigger-In 12 is selected.
	PDB0_SC_TRGSEL_1101   = 0xd     // Trigger-In 13 is selected.
	PDB0_SC_TRGSEL_1110   = 0xe     // Trigger-In 14 is selected.
	PDB0_SC_TRGSEL_1111   = 0xf     // Software trigger is selected.
	PDB0_SC_PRESCALER_Pos = 0xc     // Position of PRESCALER field.
	PDB0_SC_PRESCALER_Msk = 0x7000  // Bit mask of PRESCALER field.
	PDB0_SC_PRESCALER_000 = 0x0     // Counting uses the peripheral clock divided by multiplication factor selected by MULT.
	PDB0_SC_PRESCALER_001 = 0x1     // Counting uses the peripheral clock divided by twice of the multiplication factor selected by MULT.
	PDB0_SC_PRESCALER_010 = 0x2     // Counting uses the peripheral clock divided by four times of the multiplication factor selected by MULT.
	PDB0_SC_PRESCALER_011 = 0x3     // Counting uses the peripheral clock divided by eight times of the multiplication factor selected by MULT.
	PDB0_SC_PRESCALER_100 = 0x4     // Counting uses the peripheral clock divided by 16 times of the multiplication factor selected by MULT.
	PDB0_SC_PRESCALER_101 = 0x5     // Counting uses the peripheral clock divided by 32 times of the multiplication factor selected by MULT.
	PDB0_SC_PRESCALER_110 = 0x6     // Counting uses the peripheral clock divided by 64 times of the multiplication factor selected by MULT.
	PDB0_SC_PRESCALER_111 = 0x7     // Counting uses the peripheral clock divided by 128 times of the multiplication factor selected by MULT.
	PDB0_SC_DMAEN_Pos     = 0xf     // Position of DMAEN field.
	PDB0_SC_DMAEN_Msk     = 0x8000  // Bit mask of DMAEN field.
	PDB0_SC_DMAEN         = 0x8000  // Bit DMAEN.
	PDB0_SC_DMAEN_0       = 0x0     // DMA disabled.
	PDB0_SC_DMAEN_1       = 0x1     // DMA enabled.
	PDB0_SC_SWTRIG_Pos    = 0x10    // Position of SWTRIG field.
	PDB0_SC_SWTRIG_Msk    = 0x10000 // Bit mask of SWTRIG field.
	PDB0_SC_SWTRIG        = 0x10000 // Bit SWTRIG.
	PDB0_SC_PDBEIE_Pos    = 0x11    // Position of PDBEIE field.
	PDB0_SC_PDBEIE_Msk    = 0x20000 // Bit mask of PDBEIE field.
	PDB0_SC_PDBEIE        = 0x20000 // Bit PDBEIE.
	PDB0_SC_PDBEIE_0      = 0x0     // PDB sequence error interrupt disabled.
	PDB0_SC_PDBEIE_1      = 0x1     // PDB sequence error interrupt enabled.
	PDB0_SC_LDMOD_Pos     = 0x12    // Position of LDMOD field.
	PDB0_SC_LDMOD_Msk     = 0xc0000 // Bit mask of LDMOD field.
	PDB0_SC_LDMOD_00      = 0x0     // The internal registers are loaded with the values from their buffers immediately after 1 is written to LDOK.
	PDB0_SC_LDMOD_01      = 0x1     // The internal registers are loaded with the values from their buffers when the PDB counter reaches the MOD register value after 1 is written to LDOK.
	PDB0_SC_LDMOD_10      = 0x2     // The internal registers are loaded with the values from their buffers when a trigger input event is detected after 1 is written to LDOK.
	PDB0_SC_LDMOD_11      = 0x3     // The internal registers are loaded with the values from their buffers when either the PDB counter reaches the MOD register value or a trigger input event is detected, after 1 is written to LDOK.

	// MOD: Modulus register
	PDB0_MOD_MOD_Pos = 0x0    // Position of MOD field.
	PDB0_MOD_MOD_Msk = 0xffff // Bit mask of MOD field.

	// CNT: Counter register
	PDB0_CNT_CNT_Pos = 0x0    // Position of CNT field.
	PDB0_CNT_CNT_Msk = 0xffff // Bit mask of CNT field.

	// IDLY: Interrupt Delay register
	PDB0_IDLY_IDLY_Pos = 0x0    // Position of IDLY field.
	PDB0_IDLY_IDLY_Msk = 0xffff // Bit mask of IDLY field.

	// CH0C1: Channel n Control register 1
	PDB0_CHC1_EN_Pos  = 0x0      // Position of EN field.
	PDB0_CHC1_EN_Msk  = 0xff     // Bit mask of EN field.
	PDB0_CHC1_EN_0    = 0x0      // PDB channel's corresponding pre-trigger disabled.
	PDB0_CHC1_EN_1    = 0x1      // PDB channel's corresponding pre-trigger enabled.
	PDB0_CHC1_TOS_Pos = 0x8      // Position of TOS field.
	PDB0_CHC1_TOS_Msk = 0xff00   // Bit mask of TOS field.
	PDB0_CHC1_TOS_0   = 0x0      // PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1.
	PDB0_CHC1_TOS_1   = 0x1      // PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register and one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1.
	PDB0_CHC1_BB_Pos  = 0x10     // Position of BB field.
	PDB0_CHC1_BB_Msk  = 0xff0000 // Bit mask of BB field.
	PDB0_CHC1_BB_0    = 0x0      // PDB channel's corresponding pre-trigger back-to-back operation disabled.
	PDB0_CHC1_BB_1    = 0x1      // PDB channel's corresponding pre-trigger back-to-back operation enabled.

	// CH0S: Channel n Status register
	PDB0_CHS_ERR_Pos = 0x0      // Position of ERR field.
	PDB0_CHS_ERR_Msk = 0xff     // Bit mask of ERR field.
	PDB0_CHS_ERR_0   = 0x0      // Sequence error not detected on PDB channel's corresponding pre-trigger.
	PDB0_CHS_ERR_1   = 0x1      // Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 0's to clear the sequence error flags.
	PDB0_CHS_CF_Pos  = 0x10     // Position of CF field.
	PDB0_CHS_CF_Msk  = 0xff0000 // Bit mask of CF field.

	// CH0DLY0: Channel n Delay 0 register
	PDB0_CHDLY0_DLY_Pos = 0x0    // Position of DLY field.
	PDB0_CHDLY0_DLY_Msk = 0xffff // Bit mask of DLY field.

	// CH0DLY1: Channel n Delay 1 register
	PDB0_CHDLY1_DLY_Pos = 0x0    // Position of DLY field.
	PDB0_CHDLY1_DLY_Msk = 0xffff // Bit mask of DLY field.

	// DACINTC: DAC Interval Trigger n Control register
	PDB0_DACINTC_TOE_Pos = 0x0 // Position of TOE field.
	PDB0_DACINTC_TOE_Msk = 0x1 // Bit mask of TOE field.
	PDB0_DACINTC_TOE     = 0x1 // Bit TOE.
	PDB0_DACINTC_TOE_0   = 0x0 // DAC interval trigger disabled.
	PDB0_DACINTC_TOE_1   = 0x1 // DAC interval trigger enabled.
	PDB0_DACINTC_EXT_Pos = 0x1 // Position of EXT field.
	PDB0_DACINTC_EXT_Msk = 0x2 // Bit mask of EXT field.
	PDB0_DACINTC_EXT     = 0x2 // Bit EXT.
	PDB0_DACINTC_EXT_0   = 0x0 // DAC external trigger input disabled. DAC interval counter is reset and started counting when a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1.
	PDB0_DACINTC_EXT_1   = 0x1 // DAC external trigger input enabled. DAC interval counter is bypassed and DAC external trigger input triggers the DAC interval trigger.

	// DACINT: DAC Interval n register
	PDB0_DACINT_INT_Pos = 0x0    // Position of INT field.
	PDB0_DACINT_INT_Msk = 0xffff // Bit mask of INT field.

	// POEN: Pulse-Out n Enable register
	PDB0_POEN_POEN_Pos = 0x0  // Position of POEN field.
	PDB0_POEN_POEN_Msk = 0xff // Bit mask of POEN field.
	PDB0_POEN_POEN_0   = 0x0  // PDB Pulse-Out disabled
	PDB0_POEN_POEN_1   = 0x1  // PDB Pulse-Out enabled

	// PO0DLY: Pulse-Out n Delay register
	PDB0_PODLY_DLY2_Pos = 0x0        // Position of DLY2 field.
	PDB0_PODLY_DLY2_Msk = 0xffff     // Bit mask of DLY2 field.
	PDB0_PODLY_DLY1_Pos = 0x10       // Position of DLY1 field.
	PDB0_PODLY_DLY1_Msk = 0xffff0000 // Bit mask of DLY1 field.
)

// Bitfields for PIT: Periodic Interrupt Timer
const (
	// MCR: PIT Module Control Register
	PIT_MCR_FRZ_Pos  = 0x0 // Position of FRZ field.
	PIT_MCR_FRZ_Msk  = 0x1 // Bit mask of FRZ field.
	PIT_MCR_FRZ      = 0x1 // Bit FRZ.
	PIT_MCR_FRZ_0    = 0x0 // Timers continue to run in Debug mode.
	PIT_MCR_FRZ_1    = 0x1 // Timers are stopped in Debug mode.
	PIT_MCR_MDIS_Pos = 0x1 // Position of MDIS field.
	PIT_MCR_MDIS_Msk = 0x2 // Bit mask of MDIS field.
	PIT_MCR_MDIS     = 0x2 // Bit MDIS.
	PIT_MCR_MDIS_0   = 0x0 // Clock for standard PIT timers is enabled.
	PIT_MCR_MDIS_1   = 0x1 // Clock for standard PIT timers is disabled.

	// LDVAL0: Timer Load Value Register
	PIT_LDVAL_TSV_Pos = 0x0        // Position of TSV field.
	PIT_LDVAL_TSV_Msk = 0xffffffff // Bit mask of TSV field.

	// CVAL0: Current Timer Value Register
	PIT_CVAL_TVL_Pos = 0x0        // Position of TVL field.
	PIT_CVAL_TVL_Msk = 0xffffffff // Bit mask of TVL field.

	// TCTRL0: Timer Control Register
	PIT_TCTRL_TEN_Pos = 0x0 // Position of TEN field.
	PIT_TCTRL_TEN_Msk = 0x1 // Bit mask of TEN field.
	PIT_TCTRL_TEN     = 0x1 // Bit TEN.
	PIT_TCTRL_TEN_0   = 0x0 // Timer n is disabled.
	PIT_TCTRL_TEN_1   = 0x1 // Timer n is enabled.
	PIT_TCTRL_TIE_Pos = 0x1 // Position of TIE field.
	PIT_TCTRL_TIE_Msk = 0x2 // Bit mask of TIE field.
	PIT_TCTRL_TIE     = 0x2 // Bit TIE.
	PIT_TCTRL_TIE_0   = 0x0 // Interrupt requests from Timer n are disabled.
	PIT_TCTRL_TIE_1   = 0x1 // Interrupt will be requested whenever TIF is set.
	PIT_TCTRL_CHN_Pos = 0x2 // Position of CHN field.
	PIT_TCTRL_CHN_Msk = 0x4 // Bit mask of CHN field.
	PIT_TCTRL_CHN     = 0x4 // Bit CHN.
	PIT_TCTRL_CHN_0   = 0x0 // Timer is not chained.
	PIT_TCTRL_CHN_1   = 0x1 // Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1.

	// TFLG0: Timer Flag Register
	PIT_TFLG_TIF_Pos = 0x0 // Position of TIF field.
	PIT_TFLG_TIF_Msk = 0x1 // Bit mask of TIF field.
	PIT_TFLG_TIF     = 0x1 // Bit TIF.
	PIT_TFLG_TIF_0   = 0x0 // Timeout has not yet occurred.
	PIT_TFLG_TIF_1   = 0x1 // Timeout has occurred.
)

// Bitfields for FTM0: FlexTimer Module
const (
	// SC: Status And Control
	FTM_SC_PS_Pos    = 0x0  // Position of PS field.
	FTM_SC_PS_Msk    = 0x7  // Bit mask of PS field.
	FTM_SC_PS_000    = 0x0  // Divide by 1
	FTM_SC_PS_001    = 0x1  // Divide by 2
	FTM_SC_PS_010    = 0x2  // Divide by 4
	FTM_SC_PS_011    = 0x3  // Divide by 8
	FTM_SC_PS_100    = 0x4  // Divide by 16
	FTM_SC_PS_101    = 0x5  // Divide by 32
	FTM_SC_PS_110    = 0x6  // Divide by 64
	FTM_SC_PS_111    = 0x7  // Divide by 128
	FTM_SC_CLKS_Pos  = 0x3  // Position of CLKS field.
	FTM_SC_CLKS_Msk  = 0x18 // Bit mask of CLKS field.
	FTM_SC_CLKS_00   = 0x0  // No clock selected. This in effect disables the FTM counter.
	FTM_SC_CLKS_01   = 0x1  // System clock
	FTM_SC_CLKS_10   = 0x2  // Fixed frequency clock
	FTM_SC_CLKS_11   = 0x3  // External clock
	FTM_SC_CPWMS_Pos = 0x5  // Position of CPWMS field.
	FTM_SC_CPWMS_Msk = 0x20 // Bit mask of CPWMS field.
	FTM_SC_CPWMS     = 0x20 // Bit CPWMS.
	FTM_SC_CPWMS_0   = 0x0  // FTM counter operates in Up Counting mode.
	FTM_SC_CPWMS_1   = 0x1  // FTM counter operates in Up-Down Counting mode.
	FTM_SC_TOIE_Pos  = 0x6  // Position of TOIE field.
	FTM_SC_TOIE_Msk  = 0x40 // Bit mask of TOIE field.
	FTM_SC_TOIE      = 0x40 // Bit TOIE.
	FTM_SC_TOIE_0    = 0x0  // Disable TOF interrupts. Use software polling.
	FTM_SC_TOIE_1    = 0x1  // Enable TOF interrupts. An interrupt is generated when TOF equals one.
	FTM_SC_TOF_Pos   = 0x7  // Position of TOF field.
	FTM_SC_TOF_Msk   = 0x80 // Bit mask of TOF field.
	FTM_SC_TOF       = 0x80 // Bit TOF.
	FTM_SC_TOF_0     = 0x0  // FTM counter has not overflowed.
	FTM_SC_TOF_1     = 0x1  // FTM counter has overflowed.

	// CNT: Counter
	FTM_CNT_COUNT_Pos = 0x0    // Position of COUNT field.
	FTM_CNT_COUNT_Msk = 0xffff // Bit mask of COUNT field.

	// MOD: Modulo
	FTM_MOD_MOD_Pos = 0x0    // Position of MOD field.
	FTM_MOD_MOD_Msk = 0xffff // Bit mask of MOD field.

	// C0SC: Channel (n) Status And Control
	FTM_CSC_DMA_Pos   = 0x0  // Position of DMA field.
	FTM_CSC_DMA_Msk   = 0x1  // Bit mask of DMA field.
	FTM_CSC_DMA       = 0x1  // Bit DMA.
	FTM_CSC_DMA_0     = 0x0  // Disable DMA transfers.
	FTM_CSC_DMA_1     = 0x1  // Enable DMA transfers.
	FTM_CSC_ICRST_Pos = 0x1  // Position of ICRST field.
	FTM_CSC_ICRST_Msk = 0x2  // Bit mask of ICRST field.
	FTM_CSC_ICRST     = 0x2  // Bit ICRST.
	FTM_CSC_ICRST_0   = 0x0  // FTM counter is not reset when the selected channel (n) input event is detected.
	FTM_CSC_ICRST_1   = 0x1  // FTM counter is reset when the selected channel (n) input event is detected.
	FTM_CSC_ELSA_Pos  = 0x2  // Position of ELSA field.
	FTM_CSC_ELSA_Msk  = 0x4  // Bit mask of ELSA field.
	FTM_CSC_ELSA      = 0x4  // Bit ELSA.
	FTM_CSC_ELSB_Pos  = 0x3  // Position of ELSB field.
	FTM_CSC_ELSB_Msk  = 0x8  // Bit mask of ELSB field.
	FTM_CSC_ELSB      = 0x8  // Bit ELSB.
	FTM_CSC_MSA_Pos   = 0x4  // Position of MSA field.
	FTM_CSC_MSA_Msk   = 0x10 // Bit mask of MSA field.
	FTM_CSC_MSA       = 0x10 // Bit MSA.
	FTM_CSC_MSB_Pos   = 0x5  // Position of MSB field.
	FTM_CSC_MSB_Msk   = 0x20 // Bit mask of MSB field.
	FTM_CSC_MSB       = 0x20 // Bit MSB.
	FTM_CSC_CHIE_Pos  = 0x6  // Position of CHIE field.
	FTM_CSC_CHIE_Msk  = 0x40 // Bit mask of CHIE field.
	FTM_CSC_CHIE      = 0x40 // Bit CHIE.
	FTM_CSC_CHIE_0    = 0x0  // Disable channel interrupts. Use software polling.
	FTM_CSC_CHIE_1    = 0x1  // Enable channel interrupts.
	FTM_CSC_CHF_Pos   = 0x7  // Position of CHF field.
	FTM_CSC_CHF_Msk   = 0x80 // Bit mask of CHF field.
	FTM_CSC_CHF       = 0x80 // Bit CHF.
	FTM_CSC_CHF_0     = 0x0  // No channel event has occurred.
	FTM_CSC_CHF_1     = 0x1  // A channel event has occurred.

	// C0V: Channel (n) Value
	FTM_CV_VAL_Pos = 0x0    // Position of VAL field.
	FTM_CV_VAL_Msk = 0xffff // Bit mask of VAL field.

	// CNTIN: Counter Initial Value
	FTM_CNTIN_INIT_Pos = 0x0    // Position of INIT field.
	FTM_CNTIN_INIT_Msk = 0xffff // Bit mask of INIT field.

	// STATUS: Capture And Compare Status
	FTM_STATUS_CH0F_Pos = 0x0  // Position of CH0F field.
	FTM_STATUS_CH0F_Msk = 0x1  // Bit mask of CH0F field.
	FTM_STATUS_CH0F     = 0x1  // Bit CH0F.
	FTM_STATUS_CH0F_0   = 0x0  // No channel event has occurred.
	FTM_STATUS_CH0F_1   = 0x1  // A channel event has occurred.
	FTM_STATUS_CH1F_Pos = 0x1  // Position of CH1F field.
	FTM_STATUS_CH1F_Msk = 0x2  // Bit mask of CH1F field.
	FTM_STATUS_CH1F     = 0x2  // Bit CH1F.
	FTM_STATUS_CH1F_0   = 0x0  // No channel event has occurred.
	FTM_STATUS_CH1F_1   = 0x1  // A channel event has occurred.
	FTM_STATUS_CH2F_Pos = 0x2  // Position of CH2F field.
	FTM_STATUS_CH2F_Msk = 0x4  // Bit mask of CH2F field.
	FTM_STATUS_CH2F     = 0x4  // Bit CH2F.
	FTM_STATUS_CH2F_0   = 0x0  // No channel event has occurred.
	FTM_STATUS_CH2F_1   = 0x1  // A channel event has occurred.
	FTM_STATUS_CH3F_Pos = 0x3  // Position of CH3F field.
	FTM_STATUS_CH3F_Msk = 0x8  // Bit mask of CH3F field.
	FTM_STATUS_CH3F     = 0x8  // Bit CH3F.
	FTM_STATUS_CH3F_0   = 0x0  // No channel event has occurred.
	FTM_STATUS_CH3F_1   = 0x1  // A channel event has occurred.
	FTM_STATUS_CH4F_Pos = 0x4  // Position of CH4F field.
	FTM_STATUS_CH4F_Msk = 0x10 // Bit mask of CH4F field.
	FTM_STATUS_CH4F     = 0x10 // Bit CH4F.
	FTM_STATUS_CH4F_0   = 0x0  // No channel event has occurred.
	FTM_STATUS_CH4F_1   = 0x1  // A channel event has occurred.
	FTM_STATUS_CH5F_Pos = 0x5  // Position of CH5F field.
	FTM_STATUS_CH5F_Msk = 0x20 // Bit mask of CH5F field.
	FTM_STATUS_CH5F     = 0x20 // Bit CH5F.
	FTM_STATUS_CH5F_0   = 0x0  // No channel event has occurred.
	FTM_STATUS_CH5F_1   = 0x1  // A channel event has occurred.
	FTM_STATUS_CH6F_Pos = 0x6  // Position of CH6F field.
	FTM_STATUS_CH6F_Msk = 0x40 // Bit mask of CH6F field.
	FTM_STATUS_CH6F     = 0x40 // Bit CH6F.
	FTM_STATUS_CH6F_0   = 0x0  // No channel event has occurred.
	FTM_STATUS_CH6F_1   = 0x1  // A channel event has occurred.
	FTM_STATUS_CH7F_Pos = 0x7  // Position of CH7F field.
	FTM_STATUS_CH7F_Msk = 0x80 // Bit mask of CH7F field.
	FTM_STATUS_CH7F     = 0x80 // Bit CH7F.
	FTM_STATUS_CH7F_0   = 0x0  // No channel event has occurred.
	FTM_STATUS_CH7F_1   = 0x1  // A channel event has occurred.

	// MODE: Features Mode Selection
	FTM_MODE_FTMEN_Pos   = 0x0  // Position of FTMEN field.
	FTM_MODE_FTMEN_Msk   = 0x1  // Bit mask of FTMEN field.
	FTM_MODE_FTMEN       = 0x1  // Bit FTMEN.
	FTM_MODE_FTMEN_0     = 0x0  // Only the TPM-compatible registers (first set of registers) can be used without any restriction. Do not use the FTM-specific registers.
	FTM_MODE_FTMEN_1     = 0x1  // All registers including the FTM-specific registers (second set of registers) are available for use with no restrictions.
	FTM_MODE_INIT_Pos    = 0x1  // Position of INIT field.
	FTM_MODE_INIT_Msk    = 0x2  // Bit mask of INIT field.
	FTM_MODE_INIT        = 0x2  // Bit INIT.
	FTM_MODE_WPDIS_Pos   = 0x2  // Position of WPDIS field.
	FTM_MODE_WPDIS_Msk   = 0x4  // Bit mask of WPDIS field.
	FTM_MODE_WPDIS       = 0x4  // Bit WPDIS.
	FTM_MODE_WPDIS_0     = 0x0  // Write protection is enabled.
	FTM_MODE_WPDIS_1     = 0x1  // Write protection is disabled.
	FTM_MODE_PWMSYNC_Pos = 0x3  // Position of PWMSYNC field.
	FTM_MODE_PWMSYNC_Msk = 0x8  // Bit mask of PWMSYNC field.
	FTM_MODE_PWMSYNC     = 0x8  // Bit PWMSYNC.
	FTM_MODE_PWMSYNC_0   = 0x0  // No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization.
	FTM_MODE_PWMSYNC_1   = 0x1  // Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization.
	FTM_MODE_CAPTEST_Pos = 0x4  // Position of CAPTEST field.
	FTM_MODE_CAPTEST_Msk = 0x10 // Bit mask of CAPTEST field.
	FTM_MODE_CAPTEST     = 0x10 // Bit CAPTEST.
	FTM_MODE_CAPTEST_0   = 0x0  // Capture test mode is disabled.
	FTM_MODE_CAPTEST_1   = 0x1  // Capture test mode is enabled.
	FTM_MODE_FAULTM_Pos  = 0x5  // Position of FAULTM field.
	FTM_MODE_FAULTM_Msk  = 0x60 // Bit mask of FAULTM field.
	FTM_MODE_FAULTM_00   = 0x0  // Fault control is disabled for all channels.
	FTM_MODE_FAULTM_01   = 0x1  // Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing.
	FTM_MODE_FAULTM_10   = 0x2  // Fault control is enabled for all channels, and the selected mode is the manual fault clearing.
	FTM_MODE_FAULTM_11   = 0x3  // Fault control is enabled for all channels, and the selected mode is the automatic fault clearing.
	FTM_MODE_FAULTIE_Pos = 0x7  // Position of FAULTIE field.
	FTM_MODE_FAULTIE_Msk = 0x80 // Bit mask of FAULTIE field.
	FTM_MODE_FAULTIE     = 0x80 // Bit FAULTIE.
	FTM_MODE_FAULTIE_0   = 0x0  // Fault control interrupt is disabled.
	FTM_MODE_FAULTIE_1   = 0x1  // Fault control interrupt is enabled.

	// SYNC: Synchronization
	FTM_SYNC_CNTMIN_Pos  = 0x0  // Position of CNTMIN field.
	FTM_SYNC_CNTMIN_Msk  = 0x1  // Bit mask of CNTMIN field.
	FTM_SYNC_CNTMIN      = 0x1  // Bit CNTMIN.
	FTM_SYNC_CNTMIN_0    = 0x0  // The minimum loading point is disabled.
	FTM_SYNC_CNTMIN_1    = 0x1  // The minimum loading point is enabled.
	FTM_SYNC_CNTMAX_Pos  = 0x1  // Position of CNTMAX field.
	FTM_SYNC_CNTMAX_Msk  = 0x2  // Bit mask of CNTMAX field.
	FTM_SYNC_CNTMAX      = 0x2  // Bit CNTMAX.
	FTM_SYNC_CNTMAX_0    = 0x0  // The maximum loading point is disabled.
	FTM_SYNC_CNTMAX_1    = 0x1  // The maximum loading point is enabled.
	FTM_SYNC_REINIT_Pos  = 0x2  // Position of REINIT field.
	FTM_SYNC_REINIT_Msk  = 0x4  // Bit mask of REINIT field.
	FTM_SYNC_REINIT      = 0x4  // Bit REINIT.
	FTM_SYNC_REINIT_0    = 0x0  // FTM counter continues to count normally.
	FTM_SYNC_REINIT_1    = 0x1  // FTM counter is updated with its initial value when the selected trigger is detected.
	FTM_SYNC_SYNCHOM_Pos = 0x3  // Position of SYNCHOM field.
	FTM_SYNC_SYNCHOM_Msk = 0x8  // Bit mask of SYNCHOM field.
	FTM_SYNC_SYNCHOM     = 0x8  // Bit SYNCHOM.
	FTM_SYNC_SYNCHOM_0   = 0x0  // OUTMASK register is updated with the value of its buffer in all rising edges of the system clock.
	FTM_SYNC_SYNCHOM_1   = 0x1  // OUTMASK register is updated with the value of its buffer only by the PWM synchronization.
	FTM_SYNC_TRIG0_Pos   = 0x4  // Position of TRIG0 field.
	FTM_SYNC_TRIG0_Msk   = 0x10 // Bit mask of TRIG0 field.
	FTM_SYNC_TRIG0       = 0x10 // Bit TRIG0.
	FTM_SYNC_TRIG0_0     = 0x0  // Trigger is disabled.
	FTM_SYNC_TRIG0_1     = 0x1  // Trigger is enabled.
	FTM_SYNC_TRIG1_Pos   = 0x5  // Position of TRIG1 field.
	FTM_SYNC_TRIG1_Msk   = 0x20 // Bit mask of TRIG1 field.
	FTM_SYNC_TRIG1       = 0x20 // Bit TRIG1.
	FTM_SYNC_TRIG1_0     = 0x0  // Trigger is disabled.
	FTM_SYNC_TRIG1_1     = 0x1  // Trigger is enabled.
	FTM_SYNC_TRIG2_Pos   = 0x6  // Position of TRIG2 field.
	FTM_SYNC_TRIG2_Msk   = 0x40 // Bit mask of TRIG2 field.
	FTM_SYNC_TRIG2       = 0x40 // Bit TRIG2.
	FTM_SYNC_TRIG2_0     = 0x0  // Trigger is disabled.
	FTM_SYNC_TRIG2_1     = 0x1  // Trigger is enabled.
	FTM_SYNC_SWSYNC_Pos  = 0x7  // Position of SWSYNC field.
	FTM_SYNC_SWSYNC_Msk  = 0x80 // Bit mask of SWSYNC field.
	FTM_SYNC_SWSYNC      = 0x80 // Bit SWSYNC.
	FTM_SYNC_SWSYNC_0    = 0x0  // Software trigger is not selected.
	FTM_SYNC_SWSYNC_1    = 0x1  // Software trigger is selected.

	// OUTINIT: Initial State For Channels Output
	FTM_OUTINIT_CH0OI_Pos = 0x0  // Position of CH0OI field.
	FTM_OUTINIT_CH0OI_Msk = 0x1  // Bit mask of CH0OI field.
	FTM_OUTINIT_CH0OI     = 0x1  // Bit CH0OI.
	FTM_OUTINIT_CH0OI_0   = 0x0  // The initialization value is 0.
	FTM_OUTINIT_CH0OI_1   = 0x1  // The initialization value is 1.
	FTM_OUTINIT_CH1OI_Pos = 0x1  // Position of CH1OI field.
	FTM_OUTINIT_CH1OI_Msk = 0x2  // Bit mask of CH1OI field.
	FTM_OUTINIT_CH1OI     = 0x2  // Bit CH1OI.
	FTM_OUTINIT_CH1OI_0   = 0x0  // The initialization value is 0.
	FTM_OUTINIT_CH1OI_1   = 0x1  // The initialization value is 1.
	FTM_OUTINIT_CH2OI_Pos = 0x2  // Position of CH2OI field.
	FTM_OUTINIT_CH2OI_Msk = 0x4  // Bit mask of CH2OI field.
	FTM_OUTINIT_CH2OI     = 0x4  // Bit CH2OI.
	FTM_OUTINIT_CH2OI_0   = 0x0  // The initialization value is 0.
	FTM_OUTINIT_CH2OI_1   = 0x1  // The initialization value is 1.
	FTM_OUTINIT_CH3OI_Pos = 0x3  // Position of CH3OI field.
	FTM_OUTINIT_CH3OI_Msk = 0x8  // Bit mask of CH3OI field.
	FTM_OUTINIT_CH3OI     = 0x8  // Bit CH3OI.
	FTM_OUTINIT_CH3OI_0   = 0x0  // The initialization value is 0.
	FTM_OUTINIT_CH3OI_1   = 0x1  // The initialization value is 1.
	FTM_OUTINIT_CH4OI_Pos = 0x4  // Position of CH4OI field.
	FTM_OUTINIT_CH4OI_Msk = 0x10 // Bit mask of CH4OI field.
	FTM_OUTINIT_CH4OI     = 0x10 // Bit CH4OI.
	FTM_OUTINIT_CH4OI_0   = 0x0  // The initialization value is 0.
	FTM_OUTINIT_CH4OI_1   = 0x1  // The initialization value is 1.
	FTM_OUTINIT_CH5OI_Pos = 0x5  // Position of CH5OI field.
	FTM_OUTINIT_CH5OI_Msk = 0x20 // Bit mask of CH5OI field.
	FTM_OUTINIT_CH5OI     = 0x20 // Bit CH5OI.
	FTM_OUTINIT_CH5OI_0   = 0x0  // The initialization value is 0.
	FTM_OUTINIT_CH5OI_1   = 0x1  // The initialization value is 1.
	FTM_OUTINIT_CH6OI_Pos = 0x6  // Position of CH6OI field.
	FTM_OUTINIT_CH6OI_Msk = 0x40 // Bit mask of CH6OI field.
	FTM_OUTINIT_CH6OI     = 0x40 // Bit CH6OI.
	FTM_OUTINIT_CH6OI_0   = 0x0  // The initialization value is 0.
	FTM_OUTINIT_CH6OI_1   = 0x1  // The initialization value is 1.
	FTM_OUTINIT_CH7OI_Pos = 0x7  // Position of CH7OI field.
	FTM_OUTINIT_CH7OI_Msk = 0x80 // Bit mask of CH7OI field.
	FTM_OUTINIT_CH7OI     = 0x80 // Bit CH7OI.
	FTM_OUTINIT_CH7OI_0   = 0x0  // The initialization value is 0.
	FTM_OUTINIT_CH7OI_1   = 0x1  // The initialization value is 1.

	// OUTMASK: Output Mask
	FTM_OUTMASK_CH0OM_Pos = 0x0  // Position of CH0OM field.
	FTM_OUTMASK_CH0OM_Msk = 0x1  // Bit mask of CH0OM field.
	FTM_OUTMASK_CH0OM     = 0x1  // Bit CH0OM.
	FTM_OUTMASK_CH0OM_0   = 0x0  // Channel output is not masked. It continues to operate normally.
	FTM_OUTMASK_CH0OM_1   = 0x1  // Channel output is masked. It is forced to its inactive state.
	FTM_OUTMASK_CH1OM_Pos = 0x1  // Position of CH1OM field.
	FTM_OUTMASK_CH1OM_Msk = 0x2  // Bit mask of CH1OM field.
	FTM_OUTMASK_CH1OM     = 0x2  // Bit CH1OM.
	FTM_OUTMASK_CH1OM_0   = 0x0  // Channel output is not masked. It continues to operate normally.
	FTM_OUTMASK_CH1OM_1   = 0x1  // Channel output is masked. It is forced to its inactive state.
	FTM_OUTMASK_CH2OM_Pos = 0x2  // Position of CH2OM field.
	FTM_OUTMASK_CH2OM_Msk = 0x4  // Bit mask of CH2OM field.
	FTM_OUTMASK_CH2OM     = 0x4  // Bit CH2OM.
	FTM_OUTMASK_CH2OM_0   = 0x0  // Channel output is not masked. It continues to operate normally.
	FTM_OUTMASK_CH2OM_1   = 0x1  // Channel output is masked. It is forced to its inactive state.
	FTM_OUTMASK_CH3OM_Pos = 0x3  // Position of CH3OM field.
	FTM_OUTMASK_CH3OM_Msk = 0x8  // Bit mask of CH3OM field.
	FTM_OUTMASK_CH3OM     = 0x8  // Bit CH3OM.
	FTM_OUTMASK_CH3OM_0   = 0x0  // Channel output is not masked. It continues to operate normally.
	FTM_OUTMASK_CH3OM_1   = 0x1  // Channel output is masked. It is forced to its inactive state.
	FTM_OUTMASK_CH4OM_Pos = 0x4  // Position of CH4OM field.
	FTM_OUTMASK_CH4OM_Msk = 0x10 // Bit mask of CH4OM field.
	FTM_OUTMASK_CH4OM     = 0x10 // Bit CH4OM.
	FTM_OUTMASK_CH4OM_0   = 0x0  // Channel output is not masked. It continues to operate normally.
	FTM_OUTMASK_CH4OM_1   = 0x1  // Channel output is masked. It is forced to its inactive state.
	FTM_OUTMASK_CH5OM_Pos = 0x5  // Position of CH5OM field.
	FTM_OUTMASK_CH5OM_Msk = 0x20 // Bit mask of CH5OM field.
	FTM_OUTMASK_CH5OM     = 0x20 // Bit CH5OM.
	FTM_OUTMASK_CH5OM_0   = 0x0  // Channel output is not masked. It continues to operate normally.
	FTM_OUTMASK_CH5OM_1   = 0x1  // Channel output is masked. It is forced to its inactive state.
	FTM_OUTMASK_CH6OM_Pos = 0x6  // Position of CH6OM field.
	FTM_OUTMASK_CH6OM_Msk = 0x40 // Bit mask of CH6OM field.
	FTM_OUTMASK_CH6OM     = 0x40 // Bit CH6OM.
	FTM_OUTMASK_CH6OM_0   = 0x0  // Channel output is not masked. It continues to operate normally.
	FTM_OUTMASK_CH6OM_1   = 0x1  // Channel output is masked. It is forced to its inactive state.
	FTM_OUTMASK_CH7OM_Pos = 0x7  // Position of CH7OM field.
	FTM_OUTMASK_CH7OM_Msk = 0x80 // Bit mask of CH7OM field.
	FTM_OUTMASK_CH7OM     = 0x80 // Bit CH7OM.
	FTM_OUTMASK_CH7OM_0   = 0x0  // Channel output is not masked. It continues to operate normally.
	FTM_OUTMASK_CH7OM_1   = 0x1  // Channel output is masked. It is forced to its inactive state.

	// COMBINE: Function For Linked Channels
	FTM_COMBINE_COMBINE0_Pos = 0x0        // Position of COMBINE0 field.
	FTM_COMBINE_COMBINE0_Msk = 0x1        // Bit mask of COMBINE0 field.
	FTM_COMBINE_COMBINE0     = 0x1        // Bit COMBINE0.
	FTM_COMBINE_COMBINE0_0   = 0x0        // Channels (n) and (n+1) are independent.
	FTM_COMBINE_COMBINE0_1   = 0x1        // Channels (n) and (n+1) are combined.
	FTM_COMBINE_COMP0_Pos    = 0x1        // Position of COMP0 field.
	FTM_COMBINE_COMP0_Msk    = 0x2        // Bit mask of COMP0 field.
	FTM_COMBINE_COMP0        = 0x2        // Bit COMP0.
	FTM_COMBINE_COMP0_0      = 0x0        // The channel (n+1) output is the same as the channel (n) output.
	FTM_COMBINE_COMP0_1      = 0x1        // The channel (n+1) output is the complement of the channel (n) output.
	FTM_COMBINE_DECAPEN0_Pos = 0x2        // Position of DECAPEN0 field.
	FTM_COMBINE_DECAPEN0_Msk = 0x4        // Bit mask of DECAPEN0 field.
	FTM_COMBINE_DECAPEN0     = 0x4        // Bit DECAPEN0.
	FTM_COMBINE_DECAPEN0_0   = 0x0        // The Dual Edge Capture mode in this pair of channels is disabled.
	FTM_COMBINE_DECAPEN0_1   = 0x1        // The Dual Edge Capture mode in this pair of channels is enabled.
	FTM_COMBINE_DECAP0_Pos   = 0x3        // Position of DECAP0 field.
	FTM_COMBINE_DECAP0_Msk   = 0x8        // Bit mask of DECAP0 field.
	FTM_COMBINE_DECAP0       = 0x8        // Bit DECAP0.
	FTM_COMBINE_DECAP0_0     = 0x0        // The dual edge captures are inactive.
	FTM_COMBINE_DECAP0_1     = 0x1        // The dual edge captures are active.
	FTM_COMBINE_DTEN0_Pos    = 0x4        // Position of DTEN0 field.
	FTM_COMBINE_DTEN0_Msk    = 0x10       // Bit mask of DTEN0 field.
	FTM_COMBINE_DTEN0        = 0x10       // Bit DTEN0.
	FTM_COMBINE_DTEN0_0      = 0x0        // The deadtime insertion in this pair of channels is disabled.
	FTM_COMBINE_DTEN0_1      = 0x1        // The deadtime insertion in this pair of channels is enabled.
	FTM_COMBINE_SYNCEN0_Pos  = 0x5        // Position of SYNCEN0 field.
	FTM_COMBINE_SYNCEN0_Msk  = 0x20       // Bit mask of SYNCEN0 field.
	FTM_COMBINE_SYNCEN0      = 0x20       // Bit SYNCEN0.
	FTM_COMBINE_SYNCEN0_0    = 0x0        // The PWM synchronization in this pair of channels is disabled.
	FTM_COMBINE_SYNCEN0_1    = 0x1        // The PWM synchronization in this pair of channels is enabled.
	FTM_COMBINE_FAULTEN0_Pos = 0x6        // Position of FAULTEN0 field.
	FTM_COMBINE_FAULTEN0_Msk = 0x40       // Bit mask of FAULTEN0 field.
	FTM_COMBINE_FAULTEN0     = 0x40       // Bit FAULTEN0.
	FTM_COMBINE_FAULTEN0_0   = 0x0        // The fault control in this pair of channels is disabled.
	FTM_COMBINE_FAULTEN0_1   = 0x1        // The fault control in this pair of channels is enabled.
	FTM_COMBINE_COMBINE1_Pos = 0x8        // Position of COMBINE1 field.
	FTM_COMBINE_COMBINE1_Msk = 0x100      // Bit mask of COMBINE1 field.
	FTM_COMBINE_COMBINE1     = 0x100      // Bit COMBINE1.
	FTM_COMBINE_COMBINE1_0   = 0x0        // Channels (n) and (n+1) are independent.
	FTM_COMBINE_COMBINE1_1   = 0x1        // Channels (n) and (n+1) are combined.
	FTM_COMBINE_COMP1_Pos    = 0x9        // Position of COMP1 field.
	FTM_COMBINE_COMP1_Msk    = 0x200      // Bit mask of COMP1 field.
	FTM_COMBINE_COMP1        = 0x200      // Bit COMP1.
	FTM_COMBINE_COMP1_0      = 0x0        // The channel (n+1) output is the same as the channel (n) output.
	FTM_COMBINE_COMP1_1      = 0x1        // The channel (n+1) output is the complement of the channel (n) output.
	FTM_COMBINE_DECAPEN1_Pos = 0xa        // Position of DECAPEN1 field.
	FTM_COMBINE_DECAPEN1_Msk = 0x400      // Bit mask of DECAPEN1 field.
	FTM_COMBINE_DECAPEN1     = 0x400      // Bit DECAPEN1.
	FTM_COMBINE_DECAPEN1_0   = 0x0        // The Dual Edge Capture mode in this pair of channels is disabled.
	FTM_COMBINE_DECAPEN1_1   = 0x1        // The Dual Edge Capture mode in this pair of channels is enabled.
	FTM_COMBINE_DECAP1_Pos   = 0xb        // Position of DECAP1 field.
	FTM_COMBINE_DECAP1_Msk   = 0x800      // Bit mask of DECAP1 field.
	FTM_COMBINE_DECAP1       = 0x800      // Bit DECAP1.
	FTM_COMBINE_DECAP1_0     = 0x0        // The dual edge captures are inactive.
	FTM_COMBINE_DECAP1_1     = 0x1        // The dual edge captures are active.
	FTM_COMBINE_DTEN1_Pos    = 0xc        // Position of DTEN1 field.
	FTM_COMBINE_DTEN1_Msk    = 0x1000     // Bit mask of DTEN1 field.
	FTM_COMBINE_DTEN1        = 0x1000     // Bit DTEN1.
	FTM_COMBINE_DTEN1_0      = 0x0        // The deadtime insertion in this pair of channels is disabled.
	FTM_COMBINE_DTEN1_1      = 0x1        // The deadtime insertion in this pair of channels is enabled.
	FTM_COMBINE_SYNCEN1_Pos  = 0xd        // Position of SYNCEN1 field.
	FTM_COMBINE_SYNCEN1_Msk  = 0x2000     // Bit mask of SYNCEN1 field.
	FTM_COMBINE_SYNCEN1      = 0x2000     // Bit SYNCEN1.
	FTM_COMBINE_SYNCEN1_0    = 0x0        // The PWM synchronization in this pair of channels is disabled.
	FTM_COMBINE_SYNCEN1_1    = 0x1        // The PWM synchronization in this pair of channels is enabled.
	FTM_COMBINE_FAULTEN1_Pos = 0xe        // Position of FAULTEN1 field.
	FTM_COMBINE_FAULTEN1_Msk = 0x4000     // Bit mask of FAULTEN1 field.
	FTM_COMBINE_FAULTEN1     = 0x4000     // Bit FAULTEN1.
	FTM_COMBINE_FAULTEN1_0   = 0x0        // The fault control in this pair of channels is disabled.
	FTM_COMBINE_FAULTEN1_1   = 0x1        // The fault control in this pair of channels is enabled.
	FTM_COMBINE_COMBINE2_Pos = 0x10       // Position of COMBINE2 field.
	FTM_COMBINE_COMBINE2_Msk = 0x10000    // Bit mask of COMBINE2 field.
	FTM_COMBINE_COMBINE2     = 0x10000    // Bit COMBINE2.
	FTM_COMBINE_COMBINE2_0   = 0x0        // Channels (n) and (n+1) are independent.
	FTM_COMBINE_COMBINE2_1   = 0x1        // Channels (n) and (n+1) are combined.
	FTM_COMBINE_COMP2_Pos    = 0x11       // Position of COMP2 field.
	FTM_COMBINE_COMP2_Msk    = 0x20000    // Bit mask of COMP2 field.
	FTM_COMBINE_COMP2        = 0x20000    // Bit COMP2.
	FTM_COMBINE_COMP2_0      = 0x0        // The channel (n+1) output is the same as the channel (n) output.
	FTM_COMBINE_COMP2_1      = 0x1        // The channel (n+1) output is the complement of the channel (n) output.
	FTM_COMBINE_DECAPEN2_Pos = 0x12       // Position of DECAPEN2 field.
	FTM_COMBINE_DECAPEN2_Msk = 0x40000    // Bit mask of DECAPEN2 field.
	FTM_COMBINE_DECAPEN2     = 0x40000    // Bit DECAPEN2.
	FTM_COMBINE_DECAPEN2_0   = 0x0        // The Dual Edge Capture mode in this pair of channels is disabled.
	FTM_COMBINE_DECAPEN2_1   = 0x1        // The Dual Edge Capture mode in this pair of channels is enabled.
	FTM_COMBINE_DECAP2_Pos   = 0x13       // Position of DECAP2 field.
	FTM_COMBINE_DECAP2_Msk   = 0x80000    // Bit mask of DECAP2 field.
	FTM_COMBINE_DECAP2       = 0x80000    // Bit DECAP2.
	FTM_COMBINE_DECAP2_0     = 0x0        // The dual edge captures are inactive.
	FTM_COMBINE_DECAP2_1     = 0x1        // The dual edge captures are active.
	FTM_COMBINE_DTEN2_Pos    = 0x14       // Position of DTEN2 field.
	FTM_COMBINE_DTEN2_Msk    = 0x100000   // Bit mask of DTEN2 field.
	FTM_COMBINE_DTEN2        = 0x100000   // Bit DTEN2.
	FTM_COMBINE_DTEN2_0      = 0x0        // The deadtime insertion in this pair of channels is disabled.
	FTM_COMBINE_DTEN2_1      = 0x1        // The deadtime insertion in this pair of channels is enabled.
	FTM_COMBINE_SYNCEN2_Pos  = 0x15       // Position of SYNCEN2 field.
	FTM_COMBINE_SYNCEN2_Msk  = 0x200000   // Bit mask of SYNCEN2 field.
	FTM_COMBINE_SYNCEN2      = 0x200000   // Bit SYNCEN2.
	FTM_COMBINE_SYNCEN2_0    = 0x0        // The PWM synchronization in this pair of channels is disabled.
	FTM_COMBINE_SYNCEN2_1    = 0x1        // The PWM synchronization in this pair of channels is enabled.
	FTM_COMBINE_FAULTEN2_Pos = 0x16       // Position of FAULTEN2 field.
	FTM_COMBINE_FAULTEN2_Msk = 0x400000   // Bit mask of FAULTEN2 field.
	FTM_COMBINE_FAULTEN2     = 0x400000   // Bit FAULTEN2.
	FTM_COMBINE_FAULTEN2_0   = 0x0        // The fault control in this pair of channels is disabled.
	FTM_COMBINE_FAULTEN2_1   = 0x1        // The fault control in this pair of channels is enabled.
	FTM_COMBINE_COMBINE3_Pos = 0x18       // Position of COMBINE3 field.
	FTM_COMBINE_COMBINE3_Msk = 0x1000000  // Bit mask of COMBINE3 field.
	FTM_COMBINE_COMBINE3     = 0x1000000  // Bit COMBINE3.
	FTM_COMBINE_COMBINE3_0   = 0x0        // Channels (n) and (n+1) are independent.
	FTM_COMBINE_COMBINE3_1   = 0x1        // Channels (n) and (n+1) are combined.
	FTM_COMBINE_COMP3_Pos    = 0x19       // Position of COMP3 field.
	FTM_COMBINE_COMP3_Msk    = 0x2000000  // Bit mask of COMP3 field.
	FTM_COMBINE_COMP3        = 0x2000000  // Bit COMP3.
	FTM_COMBINE_COMP3_0      = 0x0        // The channel (n+1) output is the same as the channel (n) output.
	FTM_COMBINE_COMP3_1      = 0x1        // The channel (n+1) output is the complement of the channel (n) output.
	FTM_COMBINE_DECAPEN3_Pos = 0x1a       // Position of DECAPEN3 field.
	FTM_COMBINE_DECAPEN3_Msk = 0x4000000  // Bit mask of DECAPEN3 field.
	FTM_COMBINE_DECAPEN3     = 0x4000000  // Bit DECAPEN3.
	FTM_COMBINE_DECAPEN3_0   = 0x0        // The Dual Edge Capture mode in this pair of channels is disabled.
	FTM_COMBINE_DECAPEN3_1   = 0x1        // The Dual Edge Capture mode in this pair of channels is enabled.
	FTM_COMBINE_DECAP3_Pos   = 0x1b       // Position of DECAP3 field.
	FTM_COMBINE_DECAP3_Msk   = 0x8000000  // Bit mask of DECAP3 field.
	FTM_COMBINE_DECAP3       = 0x8000000  // Bit DECAP3.
	FTM_COMBINE_DECAP3_0     = 0x0        // The dual edge captures are inactive.
	FTM_COMBINE_DECAP3_1     = 0x1        // The dual edge captures are active.
	FTM_COMBINE_DTEN3_Pos    = 0x1c       // Position of DTEN3 field.
	FTM_COMBINE_DTEN3_Msk    = 0x10000000 // Bit mask of DTEN3 field.
	FTM_COMBINE_DTEN3        = 0x10000000 // Bit DTEN3.
	FTM_COMBINE_DTEN3_0      = 0x0        // The deadtime insertion in this pair of channels is disabled.
	FTM_COMBINE_DTEN3_1      = 0x1        // The deadtime insertion in this pair of channels is enabled.
	FTM_COMBINE_SYNCEN3_Pos  = 0x1d       // Position of SYNCEN3 field.
	FTM_COMBINE_SYNCEN3_Msk  = 0x20000000 // Bit mask of SYNCEN3 field.
	FTM_COMBINE_SYNCEN3      = 0x20000000 // Bit SYNCEN3.
	FTM_COMBINE_SYNCEN3_0    = 0x0        // The PWM synchronization in this pair of channels is disabled.
	FTM_COMBINE_SYNCEN3_1    = 0x1        // The PWM synchronization in this pair of channels is enabled.
	FTM_COMBINE_FAULTEN3_Pos = 0x1e       // Position of FAULTEN3 field.
	FTM_COMBINE_FAULTEN3_Msk = 0x40000000 // Bit mask of FAULTEN3 field.
	FTM_COMBINE_FAULTEN3     = 0x40000000 // Bit FAULTEN3.
	FTM_COMBINE_FAULTEN3_0   = 0x0        // The fault control in this pair of channels is disabled.
	FTM_COMBINE_FAULTEN3_1   = 0x1        // The fault control in this pair of channels is enabled.

	// DEADTIME: Deadtime Insertion Control
	FTM_DEADTIME_DTVAL_Pos = 0x0  // Position of DTVAL field.
	FTM_DEADTIME_DTVAL_Msk = 0x3f // Bit mask of DTVAL field.
	FTM_DEADTIME_DTPS_Pos  = 0x6  // Position of DTPS field.
	FTM_DEADTIME_DTPS_Msk  = 0xc0 // Bit mask of DTPS field.
	FTM_DEADTIME_DTPS_10   = 0x2  // Divide the system clock by 4.
	FTM_DEADTIME_DTPS_11   = 0x3  // Divide the system clock by 16.

	// EXTTRIG: FTM External Trigger
	FTM_EXTTRIG_CH2TRIG_Pos    = 0x0  // Position of CH2TRIG field.
	FTM_EXTTRIG_CH2TRIG_Msk    = 0x1  // Bit mask of CH2TRIG field.
	FTM_EXTTRIG_CH2TRIG        = 0x1  // Bit CH2TRIG.
	FTM_EXTTRIG_CH2TRIG_0      = 0x0  // The generation of the channel trigger is disabled.
	FTM_EXTTRIG_CH2TRIG_1      = 0x1  // The generation of the channel trigger is enabled.
	FTM_EXTTRIG_CH3TRIG_Pos    = 0x1  // Position of CH3TRIG field.
	FTM_EXTTRIG_CH3TRIG_Msk    = 0x2  // Bit mask of CH3TRIG field.
	FTM_EXTTRIG_CH3TRIG        = 0x2  // Bit CH3TRIG.
	FTM_EXTTRIG_CH3TRIG_0      = 0x0  // The generation of the channel trigger is disabled.
	FTM_EXTTRIG_CH3TRIG_1      = 0x1  // The generation of the channel trigger is enabled.
	FTM_EXTTRIG_CH4TRIG_Pos    = 0x2  // Position of CH4TRIG field.
	FTM_EXTTRIG_CH4TRIG_Msk    = 0x4  // Bit mask of CH4TRIG field.
	FTM_EXTTRIG_CH4TRIG        = 0x4  // Bit CH4TRIG.
	FTM_EXTTRIG_CH4TRIG_0      = 0x0  // The generation of the channel trigger is disabled.
	FTM_EXTTRIG_CH4TRIG_1      = 0x1  // The generation of the channel trigger is enabled.
	FTM_EXTTRIG_CH5TRIG_Pos    = 0x3  // Position of CH5TRIG field.
	FTM_EXTTRIG_CH5TRIG_Msk    = 0x8  // Bit mask of CH5TRIG field.
	FTM_EXTTRIG_CH5TRIG        = 0x8  // Bit CH5TRIG.
	FTM_EXTTRIG_CH5TRIG_0      = 0x0  // The generation of the channel trigger is disabled.
	FTM_EXTTRIG_CH5TRIG_1      = 0x1  // The generation of the channel trigger is enabled.
	FTM_EXTTRIG_CH0TRIG_Pos    = 0x4  // Position of CH0TRIG field.
	FTM_EXTTRIG_CH0TRIG_Msk    = 0x10 // Bit mask of CH0TRIG field.
	FTM_EXTTRIG_CH0TRIG        = 0x10 // Bit CH0TRIG.
	FTM_EXTTRIG_CH0TRIG_0      = 0x0  // The generation of the channel trigger is disabled.
	FTM_EXTTRIG_CH0TRIG_1      = 0x1  // The generation of the channel trigger is enabled.
	FTM_EXTTRIG_CH1TRIG_Pos    = 0x5  // Position of CH1TRIG field.
	FTM_EXTTRIG_CH1TRIG_Msk    = 0x20 // Bit mask of CH1TRIG field.
	FTM_EXTTRIG_CH1TRIG        = 0x20 // Bit CH1TRIG.
	FTM_EXTTRIG_CH1TRIG_0      = 0x0  // The generation of the channel trigger is disabled.
	FTM_EXTTRIG_CH1TRIG_1      = 0x1  // The generation of the channel trigger is enabled.
	FTM_EXTTRIG_INITTRIGEN_Pos = 0x6  // Position of INITTRIGEN field.
	FTM_EXTTRIG_INITTRIGEN_Msk = 0x40 // Bit mask of INITTRIGEN field.
	FTM_EXTTRIG_INITTRIGEN     = 0x40 // Bit INITTRIGEN.
	FTM_EXTTRIG_INITTRIGEN_0   = 0x0  // The generation of initialization trigger is disabled.
	FTM_EXTTRIG_INITTRIGEN_1   = 0x1  // The generation of initialization trigger is enabled.
	FTM_EXTTRIG_TRIGF_Pos      = 0x7  // Position of TRIGF field.
	FTM_EXTTRIG_TRIGF_Msk      = 0x80 // Bit mask of TRIGF field.
	FTM_EXTTRIG_TRIGF          = 0x80 // Bit TRIGF.
	FTM_EXTTRIG_TRIGF_0        = 0x0  // No channel trigger was generated.
	FTM_EXTTRIG_TRIGF_1        = 0x1  // A channel trigger was generated.

	// POL: Channels Polarity
	FTM_POL_POL0_Pos = 0x0  // Position of POL0 field.
	FTM_POL_POL0_Msk = 0x1  // Bit mask of POL0 field.
	FTM_POL_POL0     = 0x1  // Bit POL0.
	FTM_POL_POL0_0   = 0x0  // The channel polarity is active high.
	FTM_POL_POL0_1   = 0x1  // The channel polarity is active low.
	FTM_POL_POL1_Pos = 0x1  // Position of POL1 field.
	FTM_POL_POL1_Msk = 0x2  // Bit mask of POL1 field.
	FTM_POL_POL1     = 0x2  // Bit POL1.
	FTM_POL_POL1_0   = 0x0  // The channel polarity is active high.
	FTM_POL_POL1_1   = 0x1  // The channel polarity is active low.
	FTM_POL_POL2_Pos = 0x2  // Position of POL2 field.
	FTM_POL_POL2_Msk = 0x4  // Bit mask of POL2 field.
	FTM_POL_POL2     = 0x4  // Bit POL2.
	FTM_POL_POL2_0   = 0x0  // The channel polarity is active high.
	FTM_POL_POL2_1   = 0x1  // The channel polarity is active low.
	FTM_POL_POL3_Pos = 0x3  // Position of POL3 field.
	FTM_POL_POL3_Msk = 0x8  // Bit mask of POL3 field.
	FTM_POL_POL3     = 0x8  // Bit POL3.
	FTM_POL_POL3_0   = 0x0  // The channel polarity is active high.
	FTM_POL_POL3_1   = 0x1  // The channel polarity is active low.
	FTM_POL_POL4_Pos = 0x4  // Position of POL4 field.
	FTM_POL_POL4_Msk = 0x10 // Bit mask of POL4 field.
	FTM_POL_POL4     = 0x10 // Bit POL4.
	FTM_POL_POL4_0   = 0x0  // The channel polarity is active high.
	FTM_POL_POL4_1   = 0x1  // The channel polarity is active low.
	FTM_POL_POL5_Pos = 0x5  // Position of POL5 field.
	FTM_POL_POL5_Msk = 0x20 // Bit mask of POL5 field.
	FTM_POL_POL5     = 0x20 // Bit POL5.
	FTM_POL_POL5_0   = 0x0  // The channel polarity is active high.
	FTM_POL_POL5_1   = 0x1  // The channel polarity is active low.
	FTM_POL_POL6_Pos = 0x6  // Position of POL6 field.
	FTM_POL_POL6_Msk = 0x40 // Bit mask of POL6 field.
	FTM_POL_POL6     = 0x40 // Bit POL6.
	FTM_POL_POL6_0   = 0x0  // The channel polarity is active high.
	FTM_POL_POL6_1   = 0x1  // The channel polarity is active low.
	FTM_POL_POL7_Pos = 0x7  // Position of POL7 field.
	FTM_POL_POL7_Msk = 0x80 // Bit mask of POL7 field.
	FTM_POL_POL7     = 0x80 // Bit POL7.
	FTM_POL_POL7_0   = 0x0  // The channel polarity is active high.
	FTM_POL_POL7_1   = 0x1  // The channel polarity is active low.

	// FMS: Fault Mode Status
	FTM_FMS_FAULTF0_Pos = 0x0  // Position of FAULTF0 field.
	FTM_FMS_FAULTF0_Msk = 0x1  // Bit mask of FAULTF0 field.
	FTM_FMS_FAULTF0     = 0x1  // Bit FAULTF0.
	FTM_FMS_FAULTF0_0   = 0x0  // No fault condition was detected at the fault input.
	FTM_FMS_FAULTF0_1   = 0x1  // A fault condition was detected at the fault input.
	FTM_FMS_FAULTF1_Pos = 0x1  // Position of FAULTF1 field.
	FTM_FMS_FAULTF1_Msk = 0x2  // Bit mask of FAULTF1 field.
	FTM_FMS_FAULTF1     = 0x2  // Bit FAULTF1.
	FTM_FMS_FAULTF1_0   = 0x0  // No fault condition was detected at the fault input.
	FTM_FMS_FAULTF1_1   = 0x1  // A fault condition was detected at the fault input.
	FTM_FMS_FAULTF2_Pos = 0x2  // Position of FAULTF2 field.
	FTM_FMS_FAULTF2_Msk = 0x4  // Bit mask of FAULTF2 field.
	FTM_FMS_FAULTF2     = 0x4  // Bit FAULTF2.
	FTM_FMS_FAULTF2_0   = 0x0  // No fault condition was detected at the fault input.
	FTM_FMS_FAULTF2_1   = 0x1  // A fault condition was detected at the fault input.
	FTM_FMS_FAULTF3_Pos = 0x3  // Position of FAULTF3 field.
	FTM_FMS_FAULTF3_Msk = 0x8  // Bit mask of FAULTF3 field.
	FTM_FMS_FAULTF3     = 0x8  // Bit FAULTF3.
	FTM_FMS_FAULTF3_0   = 0x0  // No fault condition was detected at the fault input.
	FTM_FMS_FAULTF3_1   = 0x1  // A fault condition was detected at the fault input.
	FTM_FMS_FAULTIN_Pos = 0x5  // Position of FAULTIN field.
	FTM_FMS_FAULTIN_Msk = 0x20 // Bit mask of FAULTIN field.
	FTM_FMS_FAULTIN     = 0x20 // Bit FAULTIN.
	FTM_FMS_FAULTIN_0   = 0x0  // The logic OR of the enabled fault inputs is 0.
	FTM_FMS_FAULTIN_1   = 0x1  // The logic OR of the enabled fault inputs is 1.
	FTM_FMS_WPEN_Pos    = 0x6  // Position of WPEN field.
	FTM_FMS_WPEN_Msk    = 0x40 // Bit mask of WPEN field.
	FTM_FMS_WPEN        = 0x40 // Bit WPEN.
	FTM_FMS_WPEN_0      = 0x0  // Write protection is disabled. Write protected bits can be written.
	FTM_FMS_WPEN_1      = 0x1  // Write protection is enabled. Write protected bits cannot be written.
	FTM_FMS_FAULTF_Pos  = 0x7  // Position of FAULTF field.
	FTM_FMS_FAULTF_Msk  = 0x80 // Bit mask of FAULTF field.
	FTM_FMS_FAULTF      = 0x80 // Bit FAULTF.
	FTM_FMS_FAULTF_0    = 0x0  // No fault condition was detected.
	FTM_FMS_FAULTF_1    = 0x1  // A fault condition was detected.

	// FILTER: Input Capture Filter Control
	FTM_FILTER_CH0FVAL_Pos = 0x0    // Position of CH0FVAL field.
	FTM_FILTER_CH0FVAL_Msk = 0xf    // Bit mask of CH0FVAL field.
	FTM_FILTER_CH1FVAL_Pos = 0x4    // Position of CH1FVAL field.
	FTM_FILTER_CH1FVAL_Msk = 0xf0   // Bit mask of CH1FVAL field.
	FTM_FILTER_CH2FVAL_Pos = 0x8    // Position of CH2FVAL field.
	FTM_FILTER_CH2FVAL_Msk = 0xf00  // Bit mask of CH2FVAL field.
	FTM_FILTER_CH3FVAL_Pos = 0xc    // Position of CH3FVAL field.
	FTM_FILTER_CH3FVAL_Msk = 0xf000 // Bit mask of CH3FVAL field.

	// FLTCTRL: Fault Control
	FTM_FLTCTRL_FAULT0EN_Pos = 0x0   // Position of FAULT0EN field.
	FTM_FLTCTRL_FAULT0EN_Msk = 0x1   // Bit mask of FAULT0EN field.
	FTM_FLTCTRL_FAULT0EN     = 0x1   // Bit FAULT0EN.
	FTM_FLTCTRL_FAULT0EN_0   = 0x0   // Fault input is disabled.
	FTM_FLTCTRL_FAULT0EN_1   = 0x1   // Fault input is enabled.
	FTM_FLTCTRL_FAULT1EN_Pos = 0x1   // Position of FAULT1EN field.
	FTM_FLTCTRL_FAULT1EN_Msk = 0x2   // Bit mask of FAULT1EN field.
	FTM_FLTCTRL_FAULT1EN     = 0x2   // Bit FAULT1EN.
	FTM_FLTCTRL_FAULT1EN_0   = 0x0   // Fault input is disabled.
	FTM_FLTCTRL_FAULT1EN_1   = 0x1   // Fault input is enabled.
	FTM_FLTCTRL_FAULT2EN_Pos = 0x2   // Position of FAULT2EN field.
	FTM_FLTCTRL_FAULT2EN_Msk = 0x4   // Bit mask of FAULT2EN field.
	FTM_FLTCTRL_FAULT2EN     = 0x4   // Bit FAULT2EN.
	FTM_FLTCTRL_FAULT2EN_0   = 0x0   // Fault input is disabled.
	FTM_FLTCTRL_FAULT2EN_1   = 0x1   // Fault input is enabled.
	FTM_FLTCTRL_FAULT3EN_Pos = 0x3   // Position of FAULT3EN field.
	FTM_FLTCTRL_FAULT3EN_Msk = 0x8   // Bit mask of FAULT3EN field.
	FTM_FLTCTRL_FAULT3EN     = 0x8   // Bit FAULT3EN.
	FTM_FLTCTRL_FAULT3EN_0   = 0x0   // Fault input is disabled.
	FTM_FLTCTRL_FAULT3EN_1   = 0x1   // Fault input is enabled.
	FTM_FLTCTRL_FFLTR0EN_Pos = 0x4   // Position of FFLTR0EN field.
	FTM_FLTCTRL_FFLTR0EN_Msk = 0x10  // Bit mask of FFLTR0EN field.
	FTM_FLTCTRL_FFLTR0EN     = 0x10  // Bit FFLTR0EN.
	FTM_FLTCTRL_FFLTR0EN_0   = 0x0   // Fault input filter is disabled.
	FTM_FLTCTRL_FFLTR0EN_1   = 0x1   // Fault input filter is enabled.
	FTM_FLTCTRL_FFLTR1EN_Pos = 0x5   // Position of FFLTR1EN field.
	FTM_FLTCTRL_FFLTR1EN_Msk = 0x20  // Bit mask of FFLTR1EN field.
	FTM_FLTCTRL_FFLTR1EN     = 0x20  // Bit FFLTR1EN.
	FTM_FLTCTRL_FFLTR1EN_0   = 0x0   // Fault input filter is disabled.
	FTM_FLTCTRL_FFLTR1EN_1   = 0x1   // Fault input filter is enabled.
	FTM_FLTCTRL_FFLTR2EN_Pos = 0x6   // Position of FFLTR2EN field.
	FTM_FLTCTRL_FFLTR2EN_Msk = 0x40  // Bit mask of FFLTR2EN field.
	FTM_FLTCTRL_FFLTR2EN     = 0x40  // Bit FFLTR2EN.
	FTM_FLTCTRL_FFLTR2EN_0   = 0x0   // Fault input filter is disabled.
	FTM_FLTCTRL_FFLTR2EN_1   = 0x1   // Fault input filter is enabled.
	FTM_FLTCTRL_FFLTR3EN_Pos = 0x7   // Position of FFLTR3EN field.
	FTM_FLTCTRL_FFLTR3EN_Msk = 0x80  // Bit mask of FFLTR3EN field.
	FTM_FLTCTRL_FFLTR3EN     = 0x80  // Bit FFLTR3EN.
	FTM_FLTCTRL_FFLTR3EN_0   = 0x0   // Fault input filter is disabled.
	FTM_FLTCTRL_FFLTR3EN_1   = 0x1   // Fault input filter is enabled.
	FTM_FLTCTRL_FFVAL_Pos    = 0x8   // Position of FFVAL field.
	FTM_FLTCTRL_FFVAL_Msk    = 0xf00 // Bit mask of FFVAL field.

	// QDCTRL: Quadrature Decoder Control And Status
	FTM_QDCTRL_QUADEN_Pos    = 0x0  // Position of QUADEN field.
	FTM_QDCTRL_QUADEN_Msk    = 0x1  // Bit mask of QUADEN field.
	FTM_QDCTRL_QUADEN        = 0x1  // Bit QUADEN.
	FTM_QDCTRL_QUADEN_0      = 0x0  // Quadrature Decoder mode is disabled.
	FTM_QDCTRL_QUADEN_1      = 0x1  // Quadrature Decoder mode is enabled.
	FTM_QDCTRL_TOFDIR_Pos    = 0x1  // Position of TOFDIR field.
	FTM_QDCTRL_TOFDIR_Msk    = 0x2  // Bit mask of TOFDIR field.
	FTM_QDCTRL_TOFDIR        = 0x2  // Bit TOFDIR.
	FTM_QDCTRL_TOFDIR_0      = 0x0  // TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register).
	FTM_QDCTRL_TOFDIR_1      = 0x1  // TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register).
	FTM_QDCTRL_QUADIR_Pos    = 0x2  // Position of QUADIR field.
	FTM_QDCTRL_QUADIR_Msk    = 0x4  // Bit mask of QUADIR field.
	FTM_QDCTRL_QUADIR        = 0x4  // Bit QUADIR.
	FTM_QDCTRL_QUADIR_0      = 0x0  // Counting direction is decreasing (FTM counter decrement).
	FTM_QDCTRL_QUADIR_1      = 0x1  // Counting direction is increasing (FTM counter increment).
	FTM_QDCTRL_QUADMODE_Pos  = 0x3  // Position of QUADMODE field.
	FTM_QDCTRL_QUADMODE_Msk  = 0x8  // Bit mask of QUADMODE field.
	FTM_QDCTRL_QUADMODE      = 0x8  // Bit QUADMODE.
	FTM_QDCTRL_QUADMODE_0    = 0x0  // Phase A and phase B encoding mode.
	FTM_QDCTRL_QUADMODE_1    = 0x1  // Count and direction encoding mode.
	FTM_QDCTRL_PHBPOL_Pos    = 0x4  // Position of PHBPOL field.
	FTM_QDCTRL_PHBPOL_Msk    = 0x10 // Bit mask of PHBPOL field.
	FTM_QDCTRL_PHBPOL        = 0x10 // Bit PHBPOL.
	FTM_QDCTRL_PHBPOL_0      = 0x0  // Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal.
	FTM_QDCTRL_PHBPOL_1      = 0x1  // Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal.
	FTM_QDCTRL_PHAPOL_Pos    = 0x5  // Position of PHAPOL field.
	FTM_QDCTRL_PHAPOL_Msk    = 0x20 // Bit mask of PHAPOL field.
	FTM_QDCTRL_PHAPOL        = 0x20 // Bit PHAPOL.
	FTM_QDCTRL_PHAPOL_0      = 0x0  // Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal.
	FTM_QDCTRL_PHAPOL_1      = 0x1  // Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal.
	FTM_QDCTRL_PHBFLTREN_Pos = 0x6  // Position of PHBFLTREN field.
	FTM_QDCTRL_PHBFLTREN_Msk = 0x40 // Bit mask of PHBFLTREN field.
	FTM_QDCTRL_PHBFLTREN     = 0x40 // Bit PHBFLTREN.
	FTM_QDCTRL_PHBFLTREN_0   = 0x0  // Phase B input filter is disabled.
	FTM_QDCTRL_PHBFLTREN_1   = 0x1  // Phase B input filter is enabled.
	FTM_QDCTRL_PHAFLTREN_Pos = 0x7  // Position of PHAFLTREN field.
	FTM_QDCTRL_PHAFLTREN_Msk = 0x80 // Bit mask of PHAFLTREN field.
	FTM_QDCTRL_PHAFLTREN     = 0x80 // Bit PHAFLTREN.
	FTM_QDCTRL_PHAFLTREN_0   = 0x0  // Phase A input filter is disabled.
	FTM_QDCTRL_PHAFLTREN_1   = 0x1  // Phase A input filter is enabled.

	// CONF: Configuration
	FTM_CONF_NUMTOF_Pos  = 0x0   // Position of NUMTOF field.
	FTM_CONF_NUMTOF_Msk  = 0x1f  // Bit mask of NUMTOF field.
	FTM_CONF_BDMMODE_Pos = 0x6   // Position of BDMMODE field.
	FTM_CONF_BDMMODE_Msk = 0xc0  // Bit mask of BDMMODE field.
	FTM_CONF_GTBEEN_Pos  = 0x9   // Position of GTBEEN field.
	FTM_CONF_GTBEEN_Msk  = 0x200 // Bit mask of GTBEEN field.
	FTM_CONF_GTBEEN      = 0x200 // Bit GTBEEN.
	FTM_CONF_GTBEEN_0    = 0x0   // Use of an external global time base is disabled.
	FTM_CONF_GTBEEN_1    = 0x1   // Use of an external global time base is enabled.
	FTM_CONF_GTBEOUT_Pos = 0xa   // Position of GTBEOUT field.
	FTM_CONF_GTBEOUT_Msk = 0x400 // Bit mask of GTBEOUT field.
	FTM_CONF_GTBEOUT     = 0x400 // Bit GTBEOUT.
	FTM_CONF_GTBEOUT_0   = 0x0   // A global time base signal generation is disabled.
	FTM_CONF_GTBEOUT_1   = 0x1   // A global time base signal generation is enabled.

	// FLTPOL: FTM Fault Input Polarity
	FTM_FLTPOL_FLT0POL_Pos = 0x0 // Position of FLT0POL field.
	FTM_FLTPOL_FLT0POL_Msk = 0x1 // Bit mask of FLT0POL field.
	FTM_FLTPOL_FLT0POL     = 0x1 // Bit FLT0POL.
	FTM_FLTPOL_FLT0POL_0   = 0x0 // The fault input polarity is active high. A 1 at the fault input indicates a fault.
	FTM_FLTPOL_FLT0POL_1   = 0x1 // The fault input polarity is active low. A 0 at the fault input indicates a fault.
	FTM_FLTPOL_FLT1POL_Pos = 0x1 // Position of FLT1POL field.
	FTM_FLTPOL_FLT1POL_Msk = 0x2 // Bit mask of FLT1POL field.
	FTM_FLTPOL_FLT1POL     = 0x2 // Bit FLT1POL.
	FTM_FLTPOL_FLT1POL_0   = 0x0 // The fault input polarity is active high. A 1 at the fault input indicates a fault.
	FTM_FLTPOL_FLT1POL_1   = 0x1 // The fault input polarity is active low. A 0 at the fault input indicates a fault.
	FTM_FLTPOL_FLT2POL_Pos = 0x2 // Position of FLT2POL field.
	FTM_FLTPOL_FLT2POL_Msk = 0x4 // Bit mask of FLT2POL field.
	FTM_FLTPOL_FLT2POL     = 0x4 // Bit FLT2POL.
	FTM_FLTPOL_FLT2POL_0   = 0x0 // The fault input polarity is active high. A 1 at the fault input indicates a fault.
	FTM_FLTPOL_FLT2POL_1   = 0x1 // The fault input polarity is active low. A 0 at the fault input indicates a fault.
	FTM_FLTPOL_FLT3POL_Pos = 0x3 // Position of FLT3POL field.
	FTM_FLTPOL_FLT3POL_Msk = 0x8 // Bit mask of FLT3POL field.
	FTM_FLTPOL_FLT3POL     = 0x8 // Bit FLT3POL.
	FTM_FLTPOL_FLT3POL_0   = 0x0 // The fault input polarity is active high. A 1 at the fault input indicates a fault.
	FTM_FLTPOL_FLT3POL_1   = 0x1 // The fault input polarity is active low. A 0 at the fault input indicates a fault.

	// SYNCONF: Synchronization Configuration
	FTM_SYNCONF_HWTRIGMODE_Pos = 0x0      // Position of HWTRIGMODE field.
	FTM_SYNCONF_HWTRIGMODE_Msk = 0x1      // Bit mask of HWTRIGMODE field.
	FTM_SYNCONF_HWTRIGMODE     = 0x1      // Bit HWTRIGMODE.
	FTM_SYNCONF_HWTRIGMODE_0   = 0x0      // FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.
	FTM_SYNCONF_HWTRIGMODE_1   = 0x1      // FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.
	FTM_SYNCONF_CNTINC_Pos     = 0x2      // Position of CNTINC field.
	FTM_SYNCONF_CNTINC_Msk     = 0x4      // Bit mask of CNTINC field.
	FTM_SYNCONF_CNTINC         = 0x4      // Bit CNTINC.
	FTM_SYNCONF_CNTINC_0       = 0x0      // CNTIN register is updated with its buffer value at all rising edges of system clock.
	FTM_SYNCONF_CNTINC_1       = 0x1      // CNTIN register is updated with its buffer value by the PWM synchronization.
	FTM_SYNCONF_INVC_Pos       = 0x4      // Position of INVC field.
	FTM_SYNCONF_INVC_Msk       = 0x10     // Bit mask of INVC field.
	FTM_SYNCONF_INVC           = 0x10     // Bit INVC.
	FTM_SYNCONF_INVC_0         = 0x0      // INVCTRL register is updated with its buffer value at all rising edges of system clock.
	FTM_SYNCONF_INVC_1         = 0x1      // INVCTRL register is updated with its buffer value by the PWM synchronization.
	FTM_SYNCONF_SWOC_Pos       = 0x5      // Position of SWOC field.
	FTM_SYNCONF_SWOC_Msk       = 0x20     // Bit mask of SWOC field.
	FTM_SYNCONF_SWOC           = 0x20     // Bit SWOC.
	FTM_SYNCONF_SWOC_0         = 0x0      // SWOCTRL register is updated with its buffer value at all rising edges of system clock.
	FTM_SYNCONF_SWOC_1         = 0x1      // SWOCTRL register is updated with its buffer value by the PWM synchronization.
	FTM_SYNCONF_SYNCMODE_Pos   = 0x7      // Position of SYNCMODE field.
	FTM_SYNCONF_SYNCMODE_Msk   = 0x80     // Bit mask of SYNCMODE field.
	FTM_SYNCONF_SYNCMODE       = 0x80     // Bit SYNCMODE.
	FTM_SYNCONF_SYNCMODE_0     = 0x0      // Legacy PWM synchronization is selected.
	FTM_SYNCONF_SYNCMODE_1     = 0x1      // Enhanced PWM synchronization is selected.
	FTM_SYNCONF_SWRSTCNT_Pos   = 0x8      // Position of SWRSTCNT field.
	FTM_SYNCONF_SWRSTCNT_Msk   = 0x100    // Bit mask of SWRSTCNT field.
	FTM_SYNCONF_SWRSTCNT       = 0x100    // Bit SWRSTCNT.
	FTM_SYNCONF_SWRSTCNT_0     = 0x0      // The software trigger does not activate the FTM counter synchronization.
	FTM_SYNCONF_SWRSTCNT_1     = 0x1      // The software trigger activates the FTM counter synchronization.
	FTM_SYNCONF_SWWRBUF_Pos    = 0x9      // Position of SWWRBUF field.
	FTM_SYNCONF_SWWRBUF_Msk    = 0x200    // Bit mask of SWWRBUF field.
	FTM_SYNCONF_SWWRBUF        = 0x200    // Bit SWWRBUF.
	FTM_SYNCONF_SWWRBUF_0      = 0x0      // The software trigger does not activate MOD, CNTIN, and CV registers synchronization.
	FTM_SYNCONF_SWWRBUF_1      = 0x1      // The software trigger activates MOD, CNTIN, and CV registers synchronization.
	FTM_SYNCONF_SWOM_Pos       = 0xa      // Position of SWOM field.
	FTM_SYNCONF_SWOM_Msk       = 0x400    // Bit mask of SWOM field.
	FTM_SYNCONF_SWOM           = 0x400    // Bit SWOM.
	FTM_SYNCONF_SWOM_0         = 0x0      // The software trigger does not activate the OUTMASK register synchronization.
	FTM_SYNCONF_SWOM_1         = 0x1      // The software trigger activates the OUTMASK register synchronization.
	FTM_SYNCONF_SWINVC_Pos     = 0xb      // Position of SWINVC field.
	FTM_SYNCONF_SWINVC_Msk     = 0x800    // Bit mask of SWINVC field.
	FTM_SYNCONF_SWINVC         = 0x800    // Bit SWINVC.
	FTM_SYNCONF_SWINVC_0       = 0x0      // The software trigger does not activate the INVCTRL register synchronization.
	FTM_SYNCONF_SWINVC_1       = 0x1      // The software trigger activates the INVCTRL register synchronization.
	FTM_SYNCONF_SWSOC_Pos      = 0xc      // Position of SWSOC field.
	FTM_SYNCONF_SWSOC_Msk      = 0x1000   // Bit mask of SWSOC field.
	FTM_SYNCONF_SWSOC          = 0x1000   // Bit SWSOC.
	FTM_SYNCONF_SWSOC_0        = 0x0      // The software trigger does not activate the SWOCTRL register synchronization.
	FTM_SYNCONF_SWSOC_1        = 0x1      // The software trigger activates the SWOCTRL register synchronization.
	FTM_SYNCONF_HWRSTCNT_Pos   = 0x10     // Position of HWRSTCNT field.
	FTM_SYNCONF_HWRSTCNT_Msk   = 0x10000  // Bit mask of HWRSTCNT field.
	FTM_SYNCONF_HWRSTCNT       = 0x10000  // Bit HWRSTCNT.
	FTM_SYNCONF_HWRSTCNT_0     = 0x0      // A hardware trigger does not activate the FTM counter synchronization.
	FTM_SYNCONF_HWRSTCNT_1     = 0x1      // A hardware trigger activates the FTM counter synchronization.
	FTM_SYNCONF_HWWRBUF_Pos    = 0x11     // Position of HWWRBUF field.
	FTM_SYNCONF_HWWRBUF_Msk    = 0x20000  // Bit mask of HWWRBUF field.
	FTM_SYNCONF_HWWRBUF        = 0x20000  // Bit HWWRBUF.
	FTM_SYNCONF_HWWRBUF_0      = 0x0      // A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization.
	FTM_SYNCONF_HWWRBUF_1      = 0x1      // A hardware trigger activates MOD, CNTIN, and CV registers synchronization.
	FTM_SYNCONF_HWOM_Pos       = 0x12     // Position of HWOM field.
	FTM_SYNCONF_HWOM_Msk       = 0x40000  // Bit mask of HWOM field.
	FTM_SYNCONF_HWOM           = 0x40000  // Bit HWOM.
	FTM_SYNCONF_HWOM_0         = 0x0      // A hardware trigger does not activate the OUTMASK register synchronization.
	FTM_SYNCONF_HWOM_1         = 0x1      // A hardware trigger activates the OUTMASK register synchronization.
	FTM_SYNCONF_HWINVC_Pos     = 0x13     // Position of HWINVC field.
	FTM_SYNCONF_HWINVC_Msk     = 0x80000  // Bit mask of HWINVC field.
	FTM_SYNCONF_HWINVC         = 0x80000  // Bit HWINVC.
	FTM_SYNCONF_HWINVC_0       = 0x0      // A hardware trigger does not activate the INVCTRL register synchronization.
	FTM_SYNCONF_HWINVC_1       = 0x1      // A hardware trigger activates the INVCTRL register synchronization.
	FTM_SYNCONF_HWSOC_Pos      = 0x14     // Position of HWSOC field.
	FTM_SYNCONF_HWSOC_Msk      = 0x100000 // Bit mask of HWSOC field.
	FTM_SYNCONF_HWSOC          = 0x100000 // Bit HWSOC.
	FTM_SYNCONF_HWSOC_0        = 0x0      // A hardware trigger does not activate the SWOCTRL register synchronization.
	FTM_SYNCONF_HWSOC_1        = 0x1      // A hardware trigger activates the SWOCTRL register synchronization.

	// INVCTRL: FTM Inverting Control
	FTM_INVCTRL_INV0EN_Pos = 0x0 // Position of INV0EN field.
	FTM_INVCTRL_INV0EN_Msk = 0x1 // Bit mask of INV0EN field.
	FTM_INVCTRL_INV0EN     = 0x1 // Bit INV0EN.
	FTM_INVCTRL_INV0EN_0   = 0x0 // Inverting is disabled.
	FTM_INVCTRL_INV0EN_1   = 0x1 // Inverting is enabled.
	FTM_INVCTRL_INV1EN_Pos = 0x1 // Position of INV1EN field.
	FTM_INVCTRL_INV1EN_Msk = 0x2 // Bit mask of INV1EN field.
	FTM_INVCTRL_INV1EN     = 0x2 // Bit INV1EN.
	FTM_INVCTRL_INV1EN_0   = 0x0 // Inverting is disabled.
	FTM_INVCTRL_INV1EN_1   = 0x1 // Inverting is enabled.
	FTM_INVCTRL_INV2EN_Pos = 0x2 // Position of INV2EN field.
	FTM_INVCTRL_INV2EN_Msk = 0x4 // Bit mask of INV2EN field.
	FTM_INVCTRL_INV2EN     = 0x4 // Bit INV2EN.
	FTM_INVCTRL_INV2EN_0   = 0x0 // Inverting is disabled.
	FTM_INVCTRL_INV2EN_1   = 0x1 // Inverting is enabled.
	FTM_INVCTRL_INV3EN_Pos = 0x3 // Position of INV3EN field.
	FTM_INVCTRL_INV3EN_Msk = 0x8 // Bit mask of INV3EN field.
	FTM_INVCTRL_INV3EN     = 0x8 // Bit INV3EN.
	FTM_INVCTRL_INV3EN_0   = 0x0 // Inverting is disabled.
	FTM_INVCTRL_INV3EN_1   = 0x1 // Inverting is enabled.

	// SWOCTRL: FTM Software Output Control
	FTM_SWOCTRL_CH0OC_Pos  = 0x0    // Position of CH0OC field.
	FTM_SWOCTRL_CH0OC_Msk  = 0x1    // Bit mask of CH0OC field.
	FTM_SWOCTRL_CH0OC      = 0x1    // Bit CH0OC.
	FTM_SWOCTRL_CH0OC_0    = 0x0    // The channel output is not affected by software output control.
	FTM_SWOCTRL_CH0OC_1    = 0x1    // The channel output is affected by software output control.
	FTM_SWOCTRL_CH1OC_Pos  = 0x1    // Position of CH1OC field.
	FTM_SWOCTRL_CH1OC_Msk  = 0x2    // Bit mask of CH1OC field.
	FTM_SWOCTRL_CH1OC      = 0x2    // Bit CH1OC.
	FTM_SWOCTRL_CH1OC_0    = 0x0    // The channel output is not affected by software output control.
	FTM_SWOCTRL_CH1OC_1    = 0x1    // The channel output is affected by software output control.
	FTM_SWOCTRL_CH2OC_Pos  = 0x2    // Position of CH2OC field.
	FTM_SWOCTRL_CH2OC_Msk  = 0x4    // Bit mask of CH2OC field.
	FTM_SWOCTRL_CH2OC      = 0x4    // Bit CH2OC.
	FTM_SWOCTRL_CH2OC_0    = 0x0    // The channel output is not affected by software output control.
	FTM_SWOCTRL_CH2OC_1    = 0x1    // The channel output is affected by software output control.
	FTM_SWOCTRL_CH3OC_Pos  = 0x3    // Position of CH3OC field.
	FTM_SWOCTRL_CH3OC_Msk  = 0x8    // Bit mask of CH3OC field.
	FTM_SWOCTRL_CH3OC      = 0x8    // Bit CH3OC.
	FTM_SWOCTRL_CH3OC_0    = 0x0    // The channel output is not affected by software output control.
	FTM_SWOCTRL_CH3OC_1    = 0x1    // The channel output is affected by software output control.
	FTM_SWOCTRL_CH4OC_Pos  = 0x4    // Position of CH4OC field.
	FTM_SWOCTRL_CH4OC_Msk  = 0x10   // Bit mask of CH4OC field.
	FTM_SWOCTRL_CH4OC      = 0x10   // Bit CH4OC.
	FTM_SWOCTRL_CH4OC_0    = 0x0    // The channel output is not affected by software output control.
	FTM_SWOCTRL_CH4OC_1    = 0x1    // The channel output is affected by software output control.
	FTM_SWOCTRL_CH5OC_Pos  = 0x5    // Position of CH5OC field.
	FTM_SWOCTRL_CH5OC_Msk  = 0x20   // Bit mask of CH5OC field.
	FTM_SWOCTRL_CH5OC      = 0x20   // Bit CH5OC.
	FTM_SWOCTRL_CH5OC_0    = 0x0    // The channel output is not affected by software output control.
	FTM_SWOCTRL_CH5OC_1    = 0x1    // The channel output is affected by software output control.
	FTM_SWOCTRL_CH6OC_Pos  = 0x6    // Position of CH6OC field.
	FTM_SWOCTRL_CH6OC_Msk  = 0x40   // Bit mask of CH6OC field.
	FTM_SWOCTRL_CH6OC      = 0x40   // Bit CH6OC.
	FTM_SWOCTRL_CH6OC_0    = 0x0    // The channel output is not affected by software output control.
	FTM_SWOCTRL_CH6OC_1    = 0x1    // The channel output is affected by software output control.
	FTM_SWOCTRL_CH7OC_Pos  = 0x7    // Position of CH7OC field.
	FTM_SWOCTRL_CH7OC_Msk  = 0x80   // Bit mask of CH7OC field.
	FTM_SWOCTRL_CH7OC      = 0x80   // Bit CH7OC.
	FTM_SWOCTRL_CH7OC_0    = 0x0    // The channel output is not affected by software output control.
	FTM_SWOCTRL_CH7OC_1    = 0x1    // The channel output is affected by software output control.
	FTM_SWOCTRL_CH0OCV_Pos = 0x8    // Position of CH0OCV field.
	FTM_SWOCTRL_CH0OCV_Msk = 0x100  // Bit mask of CH0OCV field.
	FTM_SWOCTRL_CH0OCV     = 0x100  // Bit CH0OCV.
	FTM_SWOCTRL_CH0OCV_0   = 0x0    // The software output control forces 0 to the channel output.
	FTM_SWOCTRL_CH0OCV_1   = 0x1    // The software output control forces 1 to the channel output.
	FTM_SWOCTRL_CH1OCV_Pos = 0x9    // Position of CH1OCV field.
	FTM_SWOCTRL_CH1OCV_Msk = 0x200  // Bit mask of CH1OCV field.
	FTM_SWOCTRL_CH1OCV     = 0x200  // Bit CH1OCV.
	FTM_SWOCTRL_CH1OCV_0   = 0x0    // The software output control forces 0 to the channel output.
	FTM_SWOCTRL_CH1OCV_1   = 0x1    // The software output control forces 1 to the channel output.
	FTM_SWOCTRL_CH2OCV_Pos = 0xa    // Position of CH2OCV field.
	FTM_SWOCTRL_CH2OCV_Msk = 0x400  // Bit mask of CH2OCV field.
	FTM_SWOCTRL_CH2OCV     = 0x400  // Bit CH2OCV.
	FTM_SWOCTRL_CH2OCV_0   = 0x0    // The software output control forces 0 to the channel output.
	FTM_SWOCTRL_CH2OCV_1   = 0x1    // The software output control forces 1 to the channel output.
	FTM_SWOCTRL_CH3OCV_Pos = 0xb    // Position of CH3OCV field.
	FTM_SWOCTRL_CH3OCV_Msk = 0x800  // Bit mask of CH3OCV field.
	FTM_SWOCTRL_CH3OCV     = 0x800  // Bit CH3OCV.
	FTM_SWOCTRL_CH3OCV_0   = 0x0    // The software output control forces 0 to the channel output.
	FTM_SWOCTRL_CH3OCV_1   = 0x1    // The software output control forces 1 to the channel output.
	FTM_SWOCTRL_CH4OCV_Pos = 0xc    // Position of CH4OCV field.
	FTM_SWOCTRL_CH4OCV_Msk = 0x1000 // Bit mask of CH4OCV field.
	FTM_SWOCTRL_CH4OCV     = 0x1000 // Bit CH4OCV.
	FTM_SWOCTRL_CH4OCV_0   = 0x0    // The software output control forces 0 to the channel output.
	FTM_SWOCTRL_CH4OCV_1   = 0x1    // The software output control forces 1 to the channel output.
	FTM_SWOCTRL_CH5OCV_Pos = 0xd    // Position of CH5OCV field.
	FTM_SWOCTRL_CH5OCV_Msk = 0x2000 // Bit mask of CH5OCV field.
	FTM_SWOCTRL_CH5OCV     = 0x2000 // Bit CH5OCV.
	FTM_SWOCTRL_CH5OCV_0   = 0x0    // The software output control forces 0 to the channel output.
	FTM_SWOCTRL_CH5OCV_1   = 0x1    // The software output control forces 1 to the channel output.
	FTM_SWOCTRL_CH6OCV_Pos = 0xe    // Position of CH6OCV field.
	FTM_SWOCTRL_CH6OCV_Msk = 0x4000 // Bit mask of CH6OCV field.
	FTM_SWOCTRL_CH6OCV     = 0x4000 // Bit CH6OCV.
	FTM_SWOCTRL_CH6OCV_0   = 0x0    // The software output control forces 0 to the channel output.
	FTM_SWOCTRL_CH6OCV_1   = 0x1    // The software output control forces 1 to the channel output.
	FTM_SWOCTRL_CH7OCV_Pos = 0xf    // Position of CH7OCV field.
	FTM_SWOCTRL_CH7OCV_Msk = 0x8000 // Bit mask of CH7OCV field.
	FTM_SWOCTRL_CH7OCV     = 0x8000 // Bit CH7OCV.
	FTM_SWOCTRL_CH7OCV_0   = 0x0    // The software output control forces 0 to the channel output.
	FTM_SWOCTRL_CH7OCV_1   = 0x1    // The software output control forces 1 to the channel output.

	// PWMLOAD: FTM PWM Load
	FTM_PWMLOAD_CH0SEL_Pos = 0x0   // Position of CH0SEL field.
	FTM_PWMLOAD_CH0SEL_Msk = 0x1   // Bit mask of CH0SEL field.
	FTM_PWMLOAD_CH0SEL     = 0x1   // Bit CH0SEL.
	FTM_PWMLOAD_CH0SEL_0   = 0x0   // Do not include the channel in the matching process.
	FTM_PWMLOAD_CH0SEL_1   = 0x1   // Include the channel in the matching process.
	FTM_PWMLOAD_CH1SEL_Pos = 0x1   // Position of CH1SEL field.
	FTM_PWMLOAD_CH1SEL_Msk = 0x2   // Bit mask of CH1SEL field.
	FTM_PWMLOAD_CH1SEL     = 0x2   // Bit CH1SEL.
	FTM_PWMLOAD_CH1SEL_0   = 0x0   // Do not include the channel in the matching process.
	FTM_PWMLOAD_CH1SEL_1   = 0x1   // Include the channel in the matching process.
	FTM_PWMLOAD_CH2SEL_Pos = 0x2   // Position of CH2SEL field.
	FTM_PWMLOAD_CH2SEL_Msk = 0x4   // Bit mask of CH2SEL field.
	FTM_PWMLOAD_CH2SEL     = 0x4   // Bit CH2SEL.
	FTM_PWMLOAD_CH2SEL_0   = 0x0   // Do not include the channel in the matching process.
	FTM_PWMLOAD_CH2SEL_1   = 0x1   // Include the channel in the matching process.
	FTM_PWMLOAD_CH3SEL_Pos = 0x3   // Position of CH3SEL field.
	FTM_PWMLOAD_CH3SEL_Msk = 0x8   // Bit mask of CH3SEL field.
	FTM_PWMLOAD_CH3SEL     = 0x8   // Bit CH3SEL.
	FTM_PWMLOAD_CH3SEL_0   = 0x0   // Do not include the channel in the matching process.
	FTM_PWMLOAD_CH3SEL_1   = 0x1   // Include the channel in the matching process.
	FTM_PWMLOAD_CH4SEL_Pos = 0x4   // Position of CH4SEL field.
	FTM_PWMLOAD_CH4SEL_Msk = 0x10  // Bit mask of CH4SEL field.
	FTM_PWMLOAD_CH4SEL     = 0x10  // Bit CH4SEL.
	FTM_PWMLOAD_CH4SEL_0   = 0x0   // Do not include the channel in the matching process.
	FTM_PWMLOAD_CH4SEL_1   = 0x1   // Include the channel in the matching process.
	FTM_PWMLOAD_CH5SEL_Pos = 0x5   // Position of CH5SEL field.
	FTM_PWMLOAD_CH5SEL_Msk = 0x20  // Bit mask of CH5SEL field.
	FTM_PWMLOAD_CH5SEL     = 0x20  // Bit CH5SEL.
	FTM_PWMLOAD_CH5SEL_0   = 0x0   // Do not include the channel in the matching process.
	FTM_PWMLOAD_CH5SEL_1   = 0x1   // Include the channel in the matching process.
	FTM_PWMLOAD_CH6SEL_Pos = 0x6   // Position of CH6SEL field.
	FTM_PWMLOAD_CH6SEL_Msk = 0x40  // Bit mask of CH6SEL field.
	FTM_PWMLOAD_CH6SEL     = 0x40  // Bit CH6SEL.
	FTM_PWMLOAD_CH6SEL_0   = 0x0   // Do not include the channel in the matching process.
	FTM_PWMLOAD_CH6SEL_1   = 0x1   // Include the channel in the matching process.
	FTM_PWMLOAD_CH7SEL_Pos = 0x7   // Position of CH7SEL field.
	FTM_PWMLOAD_CH7SEL_Msk = 0x80  // Bit mask of CH7SEL field.
	FTM_PWMLOAD_CH7SEL     = 0x80  // Bit CH7SEL.
	FTM_PWMLOAD_CH7SEL_0   = 0x0   // Do not include the channel in the matching process.
	FTM_PWMLOAD_CH7SEL_1   = 0x1   // Include the channel in the matching process.
	FTM_PWMLOAD_LDOK_Pos   = 0x9   // Position of LDOK field.
	FTM_PWMLOAD_LDOK_Msk   = 0x200 // Bit mask of LDOK field.
	FTM_PWMLOAD_LDOK       = 0x200 // Bit LDOK.
	FTM_PWMLOAD_LDOK_0     = 0x0   // Loading updated values is disabled.
	FTM_PWMLOAD_LDOK_1     = 0x1   // Loading updated values is enabled.
)

// Bitfields for RTC: Secure Real Time Clock
const (
	// TSR: RTC Time Seconds Register
	RTC_TSR_TSR_Pos = 0x0        // Position of TSR field.
	RTC_TSR_TSR_Msk = 0xffffffff // Bit mask of TSR field.

	// TPR: RTC Time Prescaler Register
	RTC_TPR_TPR_Pos = 0x0    // Position of TPR field.
	RTC_TPR_TPR_Msk = 0xffff // Bit mask of TPR field.

	// TAR: RTC Time Alarm Register
	RTC_TAR_TAR_Pos = 0x0        // Position of TAR field.
	RTC_TAR_TAR_Msk = 0xffffffff // Bit mask of TAR field.

	// TCR: RTC Time Compensation Register
	RTC_TCR_TCR_Pos      = 0x0        // Position of TCR field.
	RTC_TCR_TCR_Msk      = 0xff       // Bit mask of TCR field.
	RTC_TCR_TCR_10000000 = 0x80       // Time Prescaler Register overflows every 32896 clock cycles.
	RTC_TCR_TCR_11111111 = 0xff       // Time Prescaler Register overflows every 32769 clock cycles.
	RTC_TCR_TCR_0        = 0x0        // Time Prescaler Register overflows every 32768 clock cycles.
	RTC_TCR_TCR_1        = 0x1        // Time Prescaler Register overflows every 32767 clock cycles.
	RTC_TCR_TCR_1111111  = 0x7f       // Time Prescaler Register overflows every 32641 clock cycles.
	RTC_TCR_CIR_Pos      = 0x8        // Position of CIR field.
	RTC_TCR_CIR_Msk      = 0xff00     // Bit mask of CIR field.
	RTC_TCR_TCV_Pos      = 0x10       // Position of TCV field.
	RTC_TCR_TCV_Msk      = 0xff0000   // Bit mask of TCV field.
	RTC_TCR_CIC_Pos      = 0x18       // Position of CIC field.
	RTC_TCR_CIC_Msk      = 0xff000000 // Bit mask of CIC field.

	// CR: RTC Control Register
	RTC_CR_SWR_Pos   = 0x0    // Position of SWR field.
	RTC_CR_SWR_Msk   = 0x1    // Bit mask of SWR field.
	RTC_CR_SWR       = 0x1    // Bit SWR.
	RTC_CR_SWR_0     = 0x0    // No effect.
	RTC_CR_SWR_1     = 0x1    // Resets all RTC registers except for the SWR bit and the RTC_WAR and RTC_RAR registers . The SWR bit is cleared by VBAT POR and by software explicitly clearing it.
	RTC_CR_WPE_Pos   = 0x1    // Position of WPE field.
	RTC_CR_WPE_Msk   = 0x2    // Bit mask of WPE field.
	RTC_CR_WPE       = 0x2    // Bit WPE.
	RTC_CR_WPE_0     = 0x0    // Wakeup pin is disabled.
	RTC_CR_WPE_1     = 0x1    // Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt asserts or the wakeup pin is turned on.
	RTC_CR_SUP_Pos   = 0x2    // Position of SUP field.
	RTC_CR_SUP_Msk   = 0x4    // Bit mask of SUP field.
	RTC_CR_SUP       = 0x4    // Bit SUP.
	RTC_CR_SUP_0     = 0x0    // Non-supervisor mode write accesses are not supported and generate a bus error.
	RTC_CR_SUP_1     = 0x1    // Non-supervisor mode write accesses are supported.
	RTC_CR_UM_Pos    = 0x3    // Position of UM field.
	RTC_CR_UM_Msk    = 0x8    // Bit mask of UM field.
	RTC_CR_UM        = 0x8    // Bit UM.
	RTC_CR_UM_0      = 0x0    // Registers cannot be written when locked.
	RTC_CR_UM_1      = 0x1    // Registers can be written when locked under limited conditions.
	RTC_CR_WPS_Pos   = 0x4    // Position of WPS field.
	RTC_CR_WPS_Msk   = 0x10   // Bit mask of WPS field.
	RTC_CR_WPS       = 0x10   // Bit WPS.
	RTC_CR_WPS_0     = 0x0    // Wakeup pin asserts (active low, open drain) if the RTC interrupt asserts or the wakeup pin is turned on.
	RTC_CR_WPS_1     = 0x1    // Wakeup pin instead outputs the RTC 32kHz clock, provided the wakeup pin is turned on and the 32kHz clock is output to other peripherals.
	RTC_CR_OSCE_Pos  = 0x8    // Position of OSCE field.
	RTC_CR_OSCE_Msk  = 0x100  // Bit mask of OSCE field.
	RTC_CR_OSCE      = 0x100  // Bit OSCE.
	RTC_CR_OSCE_0    = 0x0    // 32.768 kHz oscillator is disabled.
	RTC_CR_OSCE_1    = 0x1    // 32.768 kHz oscillator is enabled. After setting this bit, wait the oscillator startup time before enabling the time counter to allow the 32.768 kHz clock time to stabilize.
	RTC_CR_CLKO_Pos  = 0x9    // Position of CLKO field.
	RTC_CR_CLKO_Msk  = 0x200  // Bit mask of CLKO field.
	RTC_CR_CLKO      = 0x200  // Bit CLKO.
	RTC_CR_CLKO_0    = 0x0    // The 32 kHz clock is output to other peripherals.
	RTC_CR_CLKO_1    = 0x1    // The 32 kHz clock is not output to other peripherals.
	RTC_CR_SC16P_Pos = 0xa    // Position of SC16P field.
	RTC_CR_SC16P_Msk = 0x400  // Bit mask of SC16P field.
	RTC_CR_SC16P     = 0x400  // Bit SC16P.
	RTC_CR_SC16P_0   = 0x0    // Disable the load.
	RTC_CR_SC16P_1   = 0x1    // Enable the additional load.
	RTC_CR_SC8P_Pos  = 0xb    // Position of SC8P field.
	RTC_CR_SC8P_Msk  = 0x800  // Bit mask of SC8P field.
	RTC_CR_SC8P      = 0x800  // Bit SC8P.
	RTC_CR_SC8P_0    = 0x0    // Disable the load.
	RTC_CR_SC8P_1    = 0x1    // Enable the additional load.
	RTC_CR_SC4P_Pos  = 0xc    // Position of SC4P field.
	RTC_CR_SC4P_Msk  = 0x1000 // Bit mask of SC4P field.
	RTC_CR_SC4P      = 0x1000 // Bit SC4P.
	RTC_CR_SC4P_0    = 0x0    // Disable the load.
	RTC_CR_SC4P_1    = 0x1    // Enable the additional load.
	RTC_CR_SC2P_Pos  = 0xd    // Position of SC2P field.
	RTC_CR_SC2P_Msk  = 0x2000 // Bit mask of SC2P field.
	RTC_CR_SC2P      = 0x2000 // Bit SC2P.
	RTC_CR_SC2P_0    = 0x0    // Disable the load.
	RTC_CR_SC2P_1    = 0x1    // Enable the additional load.

	// SR: RTC Status Register
	RTC_SR_TIF_Pos = 0x0  // Position of TIF field.
	RTC_SR_TIF_Msk = 0x1  // Bit mask of TIF field.
	RTC_SR_TIF     = 0x1  // Bit TIF.
	RTC_SR_TIF_0   = 0x0  // Time is valid.
	RTC_SR_TIF_1   = 0x1  // Time is invalid and time counter is read as zero.
	RTC_SR_TOF_Pos = 0x1  // Position of TOF field.
	RTC_SR_TOF_Msk = 0x2  // Bit mask of TOF field.
	RTC_SR_TOF     = 0x2  // Bit TOF.
	RTC_SR_TOF_0   = 0x0  // Time overflow has not occurred.
	RTC_SR_TOF_1   = 0x1  // Time overflow has occurred and time counter is read as zero.
	RTC_SR_TAF_Pos = 0x2  // Position of TAF field.
	RTC_SR_TAF_Msk = 0x4  // Bit mask of TAF field.
	RTC_SR_TAF     = 0x4  // Bit TAF.
	RTC_SR_TAF_0   = 0x0  // Time alarm has not occurred.
	RTC_SR_TAF_1   = 0x1  // Time alarm has occurred.
	RTC_SR_TCE_Pos = 0x4  // Position of TCE field.
	RTC_SR_TCE_Msk = 0x10 // Bit mask of TCE field.
	RTC_SR_TCE     = 0x10 // Bit TCE.
	RTC_SR_TCE_0   = 0x0  // Time counter is disabled.
	RTC_SR_TCE_1   = 0x1  // Time counter is enabled.

	// LR: RTC Lock Register
	RTC_LR_TCL_Pos = 0x3  // Position of TCL field.
	RTC_LR_TCL_Msk = 0x8  // Bit mask of TCL field.
	RTC_LR_TCL     = 0x8  // Bit TCL.
	RTC_LR_TCL_0   = 0x0  // Time Compensation Register is locked and writes are ignored.
	RTC_LR_TCL_1   = 0x1  // Time Compensation Register is not locked and writes complete as normal.
	RTC_LR_CRL_Pos = 0x4  // Position of CRL field.
	RTC_LR_CRL_Msk = 0x10 // Bit mask of CRL field.
	RTC_LR_CRL     = 0x10 // Bit CRL.
	RTC_LR_CRL_0   = 0x0  // Control Register is locked and writes are ignored.
	RTC_LR_CRL_1   = 0x1  // Control Register is not locked and writes complete as normal.
	RTC_LR_SRL_Pos = 0x5  // Position of SRL field.
	RTC_LR_SRL_Msk = 0x20 // Bit mask of SRL field.
	RTC_LR_SRL     = 0x20 // Bit SRL.
	RTC_LR_SRL_0   = 0x0  // Status Register is locked and writes are ignored.
	RTC_LR_SRL_1   = 0x1  // Status Register is not locked and writes complete as normal.
	RTC_LR_LRL_Pos = 0x6  // Position of LRL field.
	RTC_LR_LRL_Msk = 0x40 // Bit mask of LRL field.
	RTC_LR_LRL     = 0x40 // Bit LRL.
	RTC_LR_LRL_0   = 0x0  // Lock Register is locked and writes are ignored.
	RTC_LR_LRL_1   = 0x1  // Lock Register is not locked and writes complete as normal.

	// IER: RTC Interrupt Enable Register
	RTC_IER_TIIE_Pos = 0x0  // Position of TIIE field.
	RTC_IER_TIIE_Msk = 0x1  // Bit mask of TIIE field.
	RTC_IER_TIIE     = 0x1  // Bit TIIE.
	RTC_IER_TIIE_0   = 0x0  // Time invalid flag does not generate an interrupt.
	RTC_IER_TIIE_1   = 0x1  // Time invalid flag does generate an interrupt.
	RTC_IER_TOIE_Pos = 0x1  // Position of TOIE field.
	RTC_IER_TOIE_Msk = 0x2  // Bit mask of TOIE field.
	RTC_IER_TOIE     = 0x2  // Bit TOIE.
	RTC_IER_TOIE_0   = 0x0  // Time overflow flag does not generate an interrupt.
	RTC_IER_TOIE_1   = 0x1  // Time overflow flag does generate an interrupt.
	RTC_IER_TAIE_Pos = 0x2  // Position of TAIE field.
	RTC_IER_TAIE_Msk = 0x4  // Bit mask of TAIE field.
	RTC_IER_TAIE     = 0x4  // Bit TAIE.
	RTC_IER_TAIE_0   = 0x0  // Time alarm flag does not generate an interrupt.
	RTC_IER_TAIE_1   = 0x1  // Time alarm flag does generate an interrupt.
	RTC_IER_TSIE_Pos = 0x4  // Position of TSIE field.
	RTC_IER_TSIE_Msk = 0x10 // Bit mask of TSIE field.
	RTC_IER_TSIE     = 0x10 // Bit TSIE.
	RTC_IER_TSIE_0   = 0x0  // Seconds interrupt is disabled.
	RTC_IER_TSIE_1   = 0x1  // Seconds interrupt is enabled.
	RTC_IER_WPON_Pos = 0x7  // Position of WPON field.
	RTC_IER_WPON_Msk = 0x80 // Bit mask of WPON field.
	RTC_IER_WPON     = 0x80 // Bit WPON.
	RTC_IER_WPON_0   = 0x0  // No effect.
	RTC_IER_WPON_1   = 0x1  // If the wakeup pin is enabled, then the wakeup pin will assert.

	// WAR: RTC Write Access Register
	RTC_WAR_TSRW_Pos = 0x0  // Position of TSRW field.
	RTC_WAR_TSRW_Msk = 0x1  // Bit mask of TSRW field.
	RTC_WAR_TSRW     = 0x1  // Bit TSRW.
	RTC_WAR_TSRW_0   = 0x0  // Writes to the Time Seconds Register are ignored.
	RTC_WAR_TSRW_1   = 0x1  // Writes to the Time Seconds Register complete as normal.
	RTC_WAR_TPRW_Pos = 0x1  // Position of TPRW field.
	RTC_WAR_TPRW_Msk = 0x2  // Bit mask of TPRW field.
	RTC_WAR_TPRW     = 0x2  // Bit TPRW.
	RTC_WAR_TPRW_0   = 0x0  // Writes to the Time Prescaler Register are ignored.
	RTC_WAR_TPRW_1   = 0x1  // Writes to the Time Prescaler Register complete as normal.
	RTC_WAR_TARW_Pos = 0x2  // Position of TARW field.
	RTC_WAR_TARW_Msk = 0x4  // Bit mask of TARW field.
	RTC_WAR_TARW     = 0x4  // Bit TARW.
	RTC_WAR_TARW_0   = 0x0  // Writes to the Time Alarm Register are ignored.
	RTC_WAR_TARW_1   = 0x1  // Writes to the Time Alarm Register complete as normal.
	RTC_WAR_TCRW_Pos = 0x3  // Position of TCRW field.
	RTC_WAR_TCRW_Msk = 0x8  // Bit mask of TCRW field.
	RTC_WAR_TCRW     = 0x8  // Bit TCRW.
	RTC_WAR_TCRW_0   = 0x0  // Writes to the Time Compensation Register are ignored.
	RTC_WAR_TCRW_1   = 0x1  // Writes to the Time Compensation Register complete as normal.
	RTC_WAR_CRW_Pos  = 0x4  // Position of CRW field.
	RTC_WAR_CRW_Msk  = 0x10 // Bit mask of CRW field.
	RTC_WAR_CRW      = 0x10 // Bit CRW.
	RTC_WAR_CRW_0    = 0x0  // Writes to the Control Register are ignored.
	RTC_WAR_CRW_1    = 0x1  // Writes to the Control Register complete as normal.
	RTC_WAR_SRW_Pos  = 0x5  // Position of SRW field.
	RTC_WAR_SRW_Msk  = 0x20 // Bit mask of SRW field.
	RTC_WAR_SRW      = 0x20 // Bit SRW.
	RTC_WAR_SRW_0    = 0x0  // Writes to the Status Register are ignored.
	RTC_WAR_SRW_1    = 0x1  // Writes to the Status Register complete as normal.
	RTC_WAR_LRW_Pos  = 0x6  // Position of LRW field.
	RTC_WAR_LRW_Msk  = 0x40 // Bit mask of LRW field.
	RTC_WAR_LRW      = 0x40 // Bit LRW.
	RTC_WAR_LRW_0    = 0x0  // Writes to the Lock Register are ignored.
	RTC_WAR_LRW_1    = 0x1  // Writes to the Lock Register complete as normal.
	RTC_WAR_IERW_Pos = 0x7  // Position of IERW field.
	RTC_WAR_IERW_Msk = 0x80 // Bit mask of IERW field.
	RTC_WAR_IERW     = 0x80 // Bit IERW.
	RTC_WAR_IERW_0   = 0x0  // Writes to the Interupt Enable Register are ignored.
	RTC_WAR_IERW_1   = 0x1  // Writes to the Interrupt Enable Register complete as normal.

	// RAR: RTC Read Access Register
	RTC_RAR_TSRR_Pos = 0x0  // Position of TSRR field.
	RTC_RAR_TSRR_Msk = 0x1  // Bit mask of TSRR field.
	RTC_RAR_TSRR     = 0x1  // Bit TSRR.
	RTC_RAR_TSRR_0   = 0x0  // Reads to the Time Seconds Register are ignored.
	RTC_RAR_TSRR_1   = 0x1  // Reads to the Time Seconds Register complete as normal.
	RTC_RAR_TPRR_Pos = 0x1  // Position of TPRR field.
	RTC_RAR_TPRR_Msk = 0x2  // Bit mask of TPRR field.
	RTC_RAR_TPRR     = 0x2  // Bit TPRR.
	RTC_RAR_TPRR_0   = 0x0  // Reads to the Time Pprescaler Register are ignored.
	RTC_RAR_TPRR_1   = 0x1  // Reads to the Time Prescaler Register complete as normal.
	RTC_RAR_TARR_Pos = 0x2  // Position of TARR field.
	RTC_RAR_TARR_Msk = 0x4  // Bit mask of TARR field.
	RTC_RAR_TARR     = 0x4  // Bit TARR.
	RTC_RAR_TARR_0   = 0x0  // Reads to the Time Alarm Register are ignored.
	RTC_RAR_TARR_1   = 0x1  // Reads to the Time Alarm Register complete as normal.
	RTC_RAR_TCRR_Pos = 0x3  // Position of TCRR field.
	RTC_RAR_TCRR_Msk = 0x8  // Bit mask of TCRR field.
	RTC_RAR_TCRR     = 0x8  // Bit TCRR.
	RTC_RAR_TCRR_0   = 0x0  // Reads to the Time Compensation Register are ignored.
	RTC_RAR_TCRR_1   = 0x1  // Reads to the Time Compensation Register complete as normal.
	RTC_RAR_CRR_Pos  = 0x4  // Position of CRR field.
	RTC_RAR_CRR_Msk  = 0x10 // Bit mask of CRR field.
	RTC_RAR_CRR      = 0x10 // Bit CRR.
	RTC_RAR_CRR_0    = 0x0  // Reads to the Control Register are ignored.
	RTC_RAR_CRR_1    = 0x1  // Reads to the Control Register complete as normal.
	RTC_RAR_SRR_Pos  = 0x5  // Position of SRR field.
	RTC_RAR_SRR_Msk  = 0x20 // Bit mask of SRR field.
	RTC_RAR_SRR      = 0x20 // Bit SRR.
	RTC_RAR_SRR_0    = 0x0  // Reads to the Status Register are ignored.
	RTC_RAR_SRR_1    = 0x1  // Reads to the Status Register complete as normal.
	RTC_RAR_LRR_Pos  = 0x6  // Position of LRR field.
	RTC_RAR_LRR_Msk  = 0x40 // Bit mask of LRR field.
	RTC_RAR_LRR      = 0x40 // Bit LRR.
	RTC_RAR_LRR_0    = 0x0  // Reads to the Lock Register are ignored.
	RTC_RAR_LRR_1    = 0x1  // Reads to the Lock Register complete as normal.
	RTC_RAR_IERR_Pos = 0x7  // Position of IERR field.
	RTC_RAR_IERR_Msk = 0x80 // Bit mask of IERR field.
	RTC_RAR_IERR     = 0x80 // Bit IERR.
	RTC_RAR_IERR_0   = 0x0  // Reads to the Interrupt Enable Register are ignored.
	RTC_RAR_IERR_1   = 0x1  // Reads to the Interrupt Enable Register complete as normal.
)

// Bitfields for RFVBAT: VBAT register file
const (
	// REG0: VBAT register file register
	RFVBAT_REG_LL_Pos = 0x0        // Position of LL field.
	RFVBAT_REG_LL_Msk = 0xff       // Bit mask of LL field.
	RFVBAT_REG_LH_Pos = 0x8        // Position of LH field.
	RFVBAT_REG_LH_Msk = 0xff00     // Bit mask of LH field.
	RFVBAT_REG_HL_Pos = 0x10       // Position of HL field.
	RFVBAT_REG_HL_Msk = 0xff0000   // Bit mask of HL field.
	RFVBAT_REG_HH_Pos = 0x18       // Position of HH field.
	RFVBAT_REG_HH_Msk = 0xff000000 // Bit mask of HH field.
)

// Bitfields for DAC0: 12-Bit Digital-to-Analog Converter
const (
	// DAT0L: DAC Data Low Register
	DAC0_DATL_DATA0_Pos = 0x0  // Position of DATA0 field.
	DAC0_DATL_DATA0_Msk = 0xff // Bit mask of DATA0 field.

	// DAT0H: DAC Data High Register
	DAC0_DATH_DATA1_Pos = 0x0 // Position of DATA1 field.
	DAC0_DATH_DATA1_Msk = 0xf // Bit mask of DATA1 field.

	// SR: DAC Status Register
	DAC0_SR_DACBFRPBF_Pos = 0x0 // Position of DACBFRPBF field.
	DAC0_SR_DACBFRPBF_Msk = 0x1 // Bit mask of DACBFRPBF field.
	DAC0_SR_DACBFRPBF     = 0x1 // Bit DACBFRPBF.
	DAC0_SR_DACBFRPBF_0   = 0x0 // The DAC buffer read pointer is not equal to C2[DACBFUP].
	DAC0_SR_DACBFRPBF_1   = 0x1 // The DAC buffer read pointer is equal to C2[DACBFUP].
	DAC0_SR_DACBFRPTF_Pos = 0x1 // Position of DACBFRPTF field.
	DAC0_SR_DACBFRPTF_Msk = 0x2 // Bit mask of DACBFRPTF field.
	DAC0_SR_DACBFRPTF     = 0x2 // Bit DACBFRPTF.
	DAC0_SR_DACBFRPTF_0   = 0x0 // The DAC buffer read pointer is not zero.
	DAC0_SR_DACBFRPTF_1   = 0x1 // The DAC buffer read pointer is zero.
	DAC0_SR_DACBFWMF_Pos  = 0x2 // Position of DACBFWMF field.
	DAC0_SR_DACBFWMF_Msk  = 0x4 // Bit mask of DACBFWMF field.
	DAC0_SR_DACBFWMF      = 0x4 // Bit DACBFWMF.
	DAC0_SR_DACBFWMF_0    = 0x0 // The DAC buffer read pointer has not reached the watermark level.
	DAC0_SR_DACBFWMF_1    = 0x1 // The DAC buffer read pointer has reached the watermark level.

	// C0: DAC Control Register
	DAC0_C0_DACBBIEN_Pos  = 0x0  // Position of DACBBIEN field.
	DAC0_C0_DACBBIEN_Msk  = 0x1  // Bit mask of DACBBIEN field.
	DAC0_C0_DACBBIEN      = 0x1  // Bit DACBBIEN.
	DAC0_C0_DACBBIEN_0    = 0x0  // The DAC buffer read pointer bottom flag interrupt is disabled.
	DAC0_C0_DACBBIEN_1    = 0x1  // The DAC buffer read pointer bottom flag interrupt is enabled.
	DAC0_C0_DACBTIEN_Pos  = 0x1  // Position of DACBTIEN field.
	DAC0_C0_DACBTIEN_Msk  = 0x2  // Bit mask of DACBTIEN field.
	DAC0_C0_DACBTIEN      = 0x2  // Bit DACBTIEN.
	DAC0_C0_DACBTIEN_0    = 0x0  // The DAC buffer read pointer top flag interrupt is disabled.
	DAC0_C0_DACBTIEN_1    = 0x1  // The DAC buffer read pointer top flag interrupt is enabled.
	DAC0_C0_DACBWIEN_Pos  = 0x2  // Position of DACBWIEN field.
	DAC0_C0_DACBWIEN_Msk  = 0x4  // Bit mask of DACBWIEN field.
	DAC0_C0_DACBWIEN      = 0x4  // Bit DACBWIEN.
	DAC0_C0_DACBWIEN_0    = 0x0  // The DAC buffer watermark interrupt is disabled.
	DAC0_C0_DACBWIEN_1    = 0x1  // The DAC buffer watermark interrupt is enabled.
	DAC0_C0_LPEN_Pos      = 0x3  // Position of LPEN field.
	DAC0_C0_LPEN_Msk      = 0x8  // Bit mask of LPEN field.
	DAC0_C0_LPEN          = 0x8  // Bit LPEN.
	DAC0_C0_LPEN_0        = 0x0  // High-Power mode
	DAC0_C0_LPEN_1        = 0x1  // Low-Power mode
	DAC0_C0_DACSWTRG_Pos  = 0x4  // Position of DACSWTRG field.
	DAC0_C0_DACSWTRG_Msk  = 0x10 // Bit mask of DACSWTRG field.
	DAC0_C0_DACSWTRG      = 0x10 // Bit DACSWTRG.
	DAC0_C0_DACSWTRG_0    = 0x0  // The DAC soft trigger is not valid.
	DAC0_C0_DACSWTRG_1    = 0x1  // The DAC soft trigger is valid.
	DAC0_C0_DACTRGSEL_Pos = 0x5  // Position of DACTRGSEL field.
	DAC0_C0_DACTRGSEL_Msk = 0x20 // Bit mask of DACTRGSEL field.
	DAC0_C0_DACTRGSEL     = 0x20 // Bit DACTRGSEL.
	DAC0_C0_DACTRGSEL_0   = 0x0  // The DAC hardware trigger is selected.
	DAC0_C0_DACTRGSEL_1   = 0x1  // The DAC software trigger is selected.
	DAC0_C0_DACRFS_Pos    = 0x6  // Position of DACRFS field.
	DAC0_C0_DACRFS_Msk    = 0x40 // Bit mask of DACRFS field.
	DAC0_C0_DACRFS        = 0x40 // Bit DACRFS.
	DAC0_C0_DACRFS_0      = 0x0  // The DAC selects DACREF_1 as the reference voltage.
	DAC0_C0_DACRFS_1      = 0x1  // The DAC selects DACREF_2 as the reference voltage.
	DAC0_C0_DACEN_Pos     = 0x7  // Position of DACEN field.
	DAC0_C0_DACEN_Msk     = 0x80 // Bit mask of DACEN field.
	DAC0_C0_DACEN         = 0x80 // Bit DACEN.
	DAC0_C0_DACEN_0       = 0x0  // The DAC system is disabled.
	DAC0_C0_DACEN_1       = 0x1  // The DAC system is enabled.

	// C1: DAC Control Register 1
	DAC0_C1_DACBFEN_Pos = 0x0  // Position of DACBFEN field.
	DAC0_C1_DACBFEN_Msk = 0x1  // Bit mask of DACBFEN field.
	DAC0_C1_DACBFEN     = 0x1  // Bit DACBFEN.
	DAC0_C1_DACBFEN_0   = 0x0  // Buffer read pointer is disabled. The converted data is always the first word of the buffer.
	DAC0_C1_DACBFEN_1   = 0x1  // Buffer read pointer is enabled. The converted data is the word that the read pointer points to. It means converted data can be from any word of the buffer.
	DAC0_C1_DACBFMD_Pos = 0x1  // Position of DACBFMD field.
	DAC0_C1_DACBFMD_Msk = 0x6  // Bit mask of DACBFMD field.
	DAC0_C1_DACBFMD_00  = 0x0  // Normal mode
	DAC0_C1_DACBFMD_01  = 0x1  // Swing mode
	DAC0_C1_DACBFMD_10  = 0x2  // One-Time Scan mode
	DAC0_C1_DACBFMD_11  = 0x3  // FIFO mode
	DAC0_C1_DACBFWM_Pos = 0x3  // Position of DACBFWM field.
	DAC0_C1_DACBFWM_Msk = 0x18 // Bit mask of DACBFWM field.
	DAC0_C1_DACBFWM_00  = 0x0  // In normal mode, 1 word . In FIFO mode, 2 or less than 2 data remaining in FIFO will set watermark status bit.
	DAC0_C1_DACBFWM_01  = 0x1  // In normal mode, 2 words . In FIFO mode, Max/4 or less than Max/4 data remaining in FIFO will set watermark status bit.
	DAC0_C1_DACBFWM_10  = 0x2  // In normal mode, 3 words . In FIFO mode, Max/2 or less than Max/2 data remaining in FIFO will set watermark status bit.
	DAC0_C1_DACBFWM_11  = 0x3  // In normal mode, 4 words . In FIFO mode, Max-2 or less than Max-2 data remaining in FIFO will set watermark status bit.
	DAC0_C1_DMAEN_Pos   = 0x7  // Position of DMAEN field.
	DAC0_C1_DMAEN_Msk   = 0x80 // Bit mask of DMAEN field.
	DAC0_C1_DMAEN       = 0x80 // Bit DMAEN.
	DAC0_C1_DMAEN_0     = 0x0  // DMA is disabled.
	DAC0_C1_DMAEN_1     = 0x1  // DMA is enabled. When DMA is enabled, the DMA request will be generated by original interrupts. The interrupts will not be presented on this module at the same time.

	// C2: DAC Control Register 2
	DAC0_C2_DACBFUP_Pos = 0x0  // Position of DACBFUP field.
	DAC0_C2_DACBFUP_Msk = 0xf  // Bit mask of DACBFUP field.
	DAC0_C2_DACBFRP_Pos = 0x4  // Position of DACBFRP field.
	DAC0_C2_DACBFRP_Msk = 0xf0 // Bit mask of DACBFRP field.
)

// Bitfields for LPTMR0: Low Power Timer
const (
	// CSR: Low Power Timer Control Status Register
	LPTMR0_CSR_TEN_Pos = 0x0  // Position of TEN field.
	LPTMR0_CSR_TEN_Msk = 0x1  // Bit mask of TEN field.
	LPTMR0_CSR_TEN     = 0x1  // Bit TEN.
	LPTMR0_CSR_TEN_0   = 0x0  // LPTMR is disabled and internal logic is reset.
	LPTMR0_CSR_TEN_1   = 0x1  // LPTMR is enabled.
	LPTMR0_CSR_TMS_Pos = 0x1  // Position of TMS field.
	LPTMR0_CSR_TMS_Msk = 0x2  // Bit mask of TMS field.
	LPTMR0_CSR_TMS     = 0x2  // Bit TMS.
	LPTMR0_CSR_TMS_0   = 0x0  // Time Counter mode.
	LPTMR0_CSR_TMS_1   = 0x1  // Pulse Counter mode.
	LPTMR0_CSR_TFC_Pos = 0x2  // Position of TFC field.
	LPTMR0_CSR_TFC_Msk = 0x4  // Bit mask of TFC field.
	LPTMR0_CSR_TFC     = 0x4  // Bit TFC.
	LPTMR0_CSR_TFC_0   = 0x0  // CNR is reset whenever TCF is set.
	LPTMR0_CSR_TFC_1   = 0x1  // CNR is reset on overflow.
	LPTMR0_CSR_TPP_Pos = 0x3  // Position of TPP field.
	LPTMR0_CSR_TPP_Msk = 0x8  // Bit mask of TPP field.
	LPTMR0_CSR_TPP     = 0x8  // Bit TPP.
	LPTMR0_CSR_TPP_0   = 0x0  // Pulse Counter input source is active-high, and the CNR will increment on the rising-edge.
	LPTMR0_CSR_TPP_1   = 0x1  // Pulse Counter input source is active-low, and the CNR will increment on the falling-edge.
	LPTMR0_CSR_TPS_Pos = 0x4  // Position of TPS field.
	LPTMR0_CSR_TPS_Msk = 0x30 // Bit mask of TPS field.
	LPTMR0_CSR_TPS_00  = 0x0  // Pulse counter input 0 is selected.
	LPTMR0_CSR_TPS_01  = 0x1  // Pulse counter input 1 is selected.
	LPTMR0_CSR_TPS_10  = 0x2  // Pulse counter input 2 is selected.
	LPTMR0_CSR_TPS_11  = 0x3  // Pulse counter input 3 is selected.
	LPTMR0_CSR_TIE_Pos = 0x6  // Position of TIE field.
	LPTMR0_CSR_TIE_Msk = 0x40 // Bit mask of TIE field.
	LPTMR0_CSR_TIE     = 0x40 // Bit TIE.
	LPTMR0_CSR_TIE_0   = 0x0  // Timer interrupt disabled.
	LPTMR0_CSR_TIE_1   = 0x1  // Timer interrupt enabled.
	LPTMR0_CSR_TCF_Pos = 0x7  // Position of TCF field.
	LPTMR0_CSR_TCF_Msk = 0x80 // Bit mask of TCF field.
	LPTMR0_CSR_TCF     = 0x80 // Bit TCF.
	LPTMR0_CSR_TCF_0   = 0x0  // The value of CNR is not equal to CMR and increments.
	LPTMR0_CSR_TCF_1   = 0x1  // The value of CNR is equal to CMR and increments.

	// PSR: Low Power Timer Prescale Register
	LPTMR0_PSR_PCS_Pos       = 0x0  // Position of PCS field.
	LPTMR0_PSR_PCS_Msk       = 0x3  // Bit mask of PCS field.
	LPTMR0_PSR_PCS_00        = 0x0  // Prescaler/glitch filter clock 0 selected.
	LPTMR0_PSR_PCS_01        = 0x1  // Prescaler/glitch filter clock 1 selected.
	LPTMR0_PSR_PCS_10        = 0x2  // Prescaler/glitch filter clock 2 selected.
	LPTMR0_PSR_PCS_11        = 0x3  // Prescaler/glitch filter clock 3 selected.
	LPTMR0_PSR_PBYP_Pos      = 0x2  // Position of PBYP field.
	LPTMR0_PSR_PBYP_Msk      = 0x4  // Bit mask of PBYP field.
	LPTMR0_PSR_PBYP          = 0x4  // Bit PBYP.
	LPTMR0_PSR_PBYP_0        = 0x0  // Prescaler/glitch filter is enabled.
	LPTMR0_PSR_PBYP_1        = 0x1  // Prescaler/glitch filter is bypassed.
	LPTMR0_PSR_PRESCALE_Pos  = 0x3  // Position of PRESCALE field.
	LPTMR0_PSR_PRESCALE_Msk  = 0x78 // Bit mask of PRESCALE field.
	LPTMR0_PSR_PRESCALE_0000 = 0x0  // Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration.
	LPTMR0_PSR_PRESCALE_0001 = 0x1  // Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges.
	LPTMR0_PSR_PRESCALE_0010 = 0x2  // Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges.
	LPTMR0_PSR_PRESCALE_0011 = 0x3  // Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges.
	LPTMR0_PSR_PRESCALE_0100 = 0x4  // Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges.
	LPTMR0_PSR_PRESCALE_0101 = 0x5  // Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges.
	LPTMR0_PSR_PRESCALE_0110 = 0x6  // Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges.
	LPTMR0_PSR_PRESCALE_0111 = 0x7  // Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges.
	LPTMR0_PSR_PRESCALE_1000 = 0x8  // Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges.
	LPTMR0_PSR_PRESCALE_1001 = 0x9  // Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges.
	LPTMR0_PSR_PRESCALE_1010 = 0xa  // Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges.
	LPTMR0_PSR_PRESCALE_1011 = 0xb  // Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges.
	LPTMR0_PSR_PRESCALE_1100 = 0xc  // Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges.
	LPTMR0_PSR_PRESCALE_1101 = 0xd  // Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges.
	LPTMR0_PSR_PRESCALE_1110 = 0xe  // Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges.
	LPTMR0_PSR_PRESCALE_1111 = 0xf  // Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges.

	// CMR: Low Power Timer Compare Register
	LPTMR0_CMR_COMPARE_Pos = 0x0    // Position of COMPARE field.
	LPTMR0_CMR_COMPARE_Msk = 0xffff // Bit mask of COMPARE field.

	// CNR: Low Power Timer Counter Register
	LPTMR0_CNR_COUNTER_Pos = 0x0    // Position of COUNTER field.
	LPTMR0_CNR_COUNTER_Msk = 0xffff // Bit mask of COUNTER field.
)

// Bitfields for RFSYS: System register file
const (
	// REG0: Register file register
	RFSYS_REG_LL_Pos = 0x0        // Position of LL field.
	RFSYS_REG_LL_Msk = 0xff       // Bit mask of LL field.
	RFSYS_REG_LH_Pos = 0x8        // Position of LH field.
	RFSYS_REG_LH_Msk = 0xff00     // Bit mask of LH field.
	RFSYS_REG_HL_Pos = 0x10       // Position of HL field.
	RFSYS_REG_HL_Msk = 0xff0000   // Bit mask of HL field.
	RFSYS_REG_HH_Pos = 0x18       // Position of HH field.
	RFSYS_REG_HH_Msk = 0xff000000 // Bit mask of HH field.
)

// Bitfields for SIM: System Integration Module
const (
	// SOPT1: System Options Register 1
	SIM_SOPT1_RAMSIZE_Pos   = 0xc        // Position of RAMSIZE field.
	SIM_SOPT1_RAMSIZE_Msk   = 0xf000     // Bit mask of RAMSIZE field.
	SIM_SOPT1_RAMSIZE_0001  = 0x1        // 8 KB
	SIM_SOPT1_RAMSIZE_0011  = 0x3        // 16 KB
	SIM_SOPT1_RAMSIZE_0100  = 0x4        // 24 KB
	SIM_SOPT1_RAMSIZE_0101  = 0x5        // 32 KB
	SIM_SOPT1_RAMSIZE_0110  = 0x6        // 48 KB
	SIM_SOPT1_RAMSIZE_0111  = 0x7        // 64 KB
	SIM_SOPT1_RAMSIZE_1000  = 0x8        // 96 KB
	SIM_SOPT1_RAMSIZE_1001  = 0x9        // 128 KB
	SIM_SOPT1_RAMSIZE_1011  = 0xb        // 256 KB
	SIM_SOPT1_OSC32KOUT_Pos = 0x10       // Position of OSC32KOUT field.
	SIM_SOPT1_OSC32KOUT_Msk = 0x30000    // Bit mask of OSC32KOUT field.
	SIM_SOPT1_OSC32KOUT_00  = 0x0        // ERCLK32K is not output.
	SIM_SOPT1_OSC32KOUT_01  = 0x1        // ERCLK32K is output on PTE0.
	SIM_SOPT1_OSC32KOUT_10  = 0x2        // ERCLK32K is output on PTE26.
	SIM_SOPT1_OSC32KSEL_Pos = 0x12       // Position of OSC32KSEL field.
	SIM_SOPT1_OSC32KSEL_Msk = 0xc0000    // Bit mask of OSC32KSEL field.
	SIM_SOPT1_OSC32KSEL_00  = 0x0        // System oscillator (OSC32KCLK)
	SIM_SOPT1_OSC32KSEL_10  = 0x2        // RTC 32.768kHz oscillator
	SIM_SOPT1_OSC32KSEL_11  = 0x3        // LPO 1 kHz
	SIM_SOPT1_USBVSTBY_Pos  = 0x1d       // Position of USBVSTBY field.
	SIM_SOPT1_USBVSTBY_Msk  = 0x20000000 // Bit mask of USBVSTBY field.
	SIM_SOPT1_USBVSTBY      = 0x20000000 // Bit USBVSTBY.
	SIM_SOPT1_USBVSTBY_0    = 0x0        // USB voltage regulator not in standby during VLPR and VLPW modes.
	SIM_SOPT1_USBVSTBY_1    = 0x1        // USB voltage regulator in standby during VLPR and VLPW modes.
	SIM_SOPT1_USBSSTBY_Pos  = 0x1e       // Position of USBSSTBY field.
	SIM_SOPT1_USBSSTBY_Msk  = 0x40000000 // Bit mask of USBSSTBY field.
	SIM_SOPT1_USBSSTBY      = 0x40000000 // Bit USBSSTBY.
	SIM_SOPT1_USBSSTBY_0    = 0x0        // USB voltage regulator not in standby during Stop, VLPS, LLS and VLLS modes.
	SIM_SOPT1_USBSSTBY_1    = 0x1        // USB voltage regulator in standby during Stop, VLPS, LLS and VLLS modes.
	SIM_SOPT1_USBREGEN_Pos  = 0x1f       // Position of USBREGEN field.
	SIM_SOPT1_USBREGEN_Msk  = 0x80000000 // Bit mask of USBREGEN field.
	SIM_SOPT1_USBREGEN      = 0x80000000 // Bit USBREGEN.
	SIM_SOPT1_USBREGEN_0    = 0x0        // USB voltage regulator is disabled.
	SIM_SOPT1_USBREGEN_1    = 0x1        // USB voltage regulator is enabled.

	// SOPT1CFG: SOPT1 Configuration Register
	SIM_SOPT1CFG_URWE_Pos  = 0x18      // Position of URWE field.
	SIM_SOPT1CFG_URWE_Msk  = 0x1000000 // Bit mask of URWE field.
	SIM_SOPT1CFG_URWE      = 0x1000000 // Bit URWE.
	SIM_SOPT1CFG_URWE_0    = 0x0       // SOPT1 USBREGEN cannot be written.
	SIM_SOPT1CFG_URWE_1    = 0x1       // SOPT1 USBREGEN can be written.
	SIM_SOPT1CFG_UVSWE_Pos = 0x19      // Position of UVSWE field.
	SIM_SOPT1CFG_UVSWE_Msk = 0x2000000 // Bit mask of UVSWE field.
	SIM_SOPT1CFG_UVSWE     = 0x2000000 // Bit UVSWE.
	SIM_SOPT1CFG_UVSWE_0   = 0x0       // SOPT1 USBVSTBY cannot be written.
	SIM_SOPT1CFG_UVSWE_1   = 0x1       // SOPT1 USBVSTBY can be written.
	SIM_SOPT1CFG_USSWE_Pos = 0x1a      // Position of USSWE field.
	SIM_SOPT1CFG_USSWE_Msk = 0x4000000 // Bit mask of USSWE field.
	SIM_SOPT1CFG_USSWE     = 0x4000000 // Bit USSWE.
	SIM_SOPT1CFG_USSWE_0   = 0x0       // SOPT1 USBSSTBY cannot be written.
	SIM_SOPT1CFG_USSWE_1   = 0x1       // SOPT1 USBSSTBY can be written.

	// SOPT2: System Options Register 2
	SIM_SOPT2_RTCCLKOUTSEL_Pos = 0x4       // Position of RTCCLKOUTSEL field.
	SIM_SOPT2_RTCCLKOUTSEL_Msk = 0x10      // Bit mask of RTCCLKOUTSEL field.
	SIM_SOPT2_RTCCLKOUTSEL     = 0x10      // Bit RTCCLKOUTSEL.
	SIM_SOPT2_RTCCLKOUTSEL_0   = 0x0       // RTC 1 Hz clock is output on the RTC_CLKOUT pin.
	SIM_SOPT2_RTCCLKOUTSEL_1   = 0x1       // RTC 32.768kHz clock is output on the RTC_CLKOUT pin.
	SIM_SOPT2_CLKOUTSEL_Pos    = 0x5       // Position of CLKOUTSEL field.
	SIM_SOPT2_CLKOUTSEL_Msk    = 0xe0      // Bit mask of CLKOUTSEL field.
	SIM_SOPT2_CLKOUTSEL_010    = 0x2       // Flash clock
	SIM_SOPT2_CLKOUTSEL_011    = 0x3       // LPO clock (1 kHz)
	SIM_SOPT2_CLKOUTSEL_100    = 0x4       // MCGIRCLK
	SIM_SOPT2_CLKOUTSEL_101    = 0x5       // RTC 32.768kHz clock
	SIM_SOPT2_CLKOUTSEL_110    = 0x6       // OSCERCLK0
	SIM_SOPT2_CLKOUTSEL_111    = 0x7       // IRC 48 MHz clock
	SIM_SOPT2_TRACECLKSEL_Pos  = 0xc       // Position of TRACECLKSEL field.
	SIM_SOPT2_TRACECLKSEL_Msk  = 0x1000    // Bit mask of TRACECLKSEL field.
	SIM_SOPT2_TRACECLKSEL      = 0x1000    // Bit TRACECLKSEL.
	SIM_SOPT2_TRACECLKSEL_0    = 0x0       // MCGOUTCLK
	SIM_SOPT2_TRACECLKSEL_1    = 0x1       // Core/system clock
	SIM_SOPT2_PLLFLLSEL_Pos    = 0x10      // Position of PLLFLLSEL field.
	SIM_SOPT2_PLLFLLSEL_Msk    = 0x30000   // Bit mask of PLLFLLSEL field.
	SIM_SOPT2_PLLFLLSEL_00     = 0x0       // MCGFLLCLK clock
	SIM_SOPT2_PLLFLLSEL_01     = 0x1       // MCGPLLCLK clock
	SIM_SOPT2_PLLFLLSEL_11     = 0x3       // IRC48 MHz clock
	SIM_SOPT2_USBSRC_Pos       = 0x12      // Position of USBSRC field.
	SIM_SOPT2_USBSRC_Msk       = 0x40000   // Bit mask of USBSRC field.
	SIM_SOPT2_USBSRC           = 0x40000   // Bit USBSRC.
	SIM_SOPT2_USBSRC_0         = 0x0       // External bypass clock (USB_CLKIN).
	SIM_SOPT2_USBSRC_1         = 0x1       // MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by SOPT2[PLLFLLSEL], and then divided by the USB fractional divider as configured by SIM_CLKDIV2[USBFRAC, USBDIV].
	SIM_SOPT2_LPUARTSRC_Pos    = 0x1a      // Position of LPUARTSRC field.
	SIM_SOPT2_LPUARTSRC_Msk    = 0xc000000 // Bit mask of LPUARTSRC field.
	SIM_SOPT2_LPUARTSRC_00     = 0x0       // Clock disabled
	SIM_SOPT2_LPUARTSRC_01     = 0x1       // MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by SOPT2[PLLFLLSEL].
	SIM_SOPT2_LPUARTSRC_10     = 0x2       // OSCERCLK clock
	SIM_SOPT2_LPUARTSRC_11     = 0x3       // MCGIRCLK clock

	// SOPT4: System Options Register 4
	SIM_SOPT4_FTM0FLT0_Pos    = 0x0        // Position of FTM0FLT0 field.
	SIM_SOPT4_FTM0FLT0_Msk    = 0x1        // Bit mask of FTM0FLT0 field.
	SIM_SOPT4_FTM0FLT0        = 0x1        // Bit FTM0FLT0.
	SIM_SOPT4_FTM0FLT0_0      = 0x0        // FTM0_FLT0 pin
	SIM_SOPT4_FTM0FLT0_1      = 0x1        // CMP0 out
	SIM_SOPT4_FTM0FLT1_Pos    = 0x1        // Position of FTM0FLT1 field.
	SIM_SOPT4_FTM0FLT1_Msk    = 0x2        // Bit mask of FTM0FLT1 field.
	SIM_SOPT4_FTM0FLT1        = 0x2        // Bit FTM0FLT1.
	SIM_SOPT4_FTM0FLT1_0      = 0x0        // FTM0_FLT1 pin
	SIM_SOPT4_FTM0FLT1_1      = 0x1        // CMP1 out
	SIM_SOPT4_FTM1FLT0_Pos    = 0x4        // Position of FTM1FLT0 field.
	SIM_SOPT4_FTM1FLT0_Msk    = 0x10       // Bit mask of FTM1FLT0 field.
	SIM_SOPT4_FTM1FLT0        = 0x10       // Bit FTM1FLT0.
	SIM_SOPT4_FTM1FLT0_0      = 0x0        // FTM1_FLT0 pin
	SIM_SOPT4_FTM1FLT0_1      = 0x1        // CMP0 out
	SIM_SOPT4_FTM2FLT0_Pos    = 0x8        // Position of FTM2FLT0 field.
	SIM_SOPT4_FTM2FLT0_Msk    = 0x100      // Bit mask of FTM2FLT0 field.
	SIM_SOPT4_FTM2FLT0        = 0x100      // Bit FTM2FLT0.
	SIM_SOPT4_FTM2FLT0_0      = 0x0        // FTM2_FLT0 pin
	SIM_SOPT4_FTM2FLT0_1      = 0x1        // CMP0 out
	SIM_SOPT4_FTM1CH0SRC_Pos  = 0x12       // Position of FTM1CH0SRC field.
	SIM_SOPT4_FTM1CH0SRC_Msk  = 0xc0000    // Bit mask of FTM1CH0SRC field.
	SIM_SOPT4_FTM1CH0SRC_00   = 0x0        // FTM1_CH0 signal
	SIM_SOPT4_FTM1CH0SRC_01   = 0x1        // CMP0 output
	SIM_SOPT4_FTM1CH0SRC_10   = 0x2        // CMP1 output
	SIM_SOPT4_FTM1CH0SRC_11   = 0x3        // USB start of frame pulse
	SIM_SOPT4_FTM2CH0SRC_Pos  = 0x14       // Position of FTM2CH0SRC field.
	SIM_SOPT4_FTM2CH0SRC_Msk  = 0x300000   // Bit mask of FTM2CH0SRC field.
	SIM_SOPT4_FTM2CH0SRC_00   = 0x0        // FTM2_CH0 signal
	SIM_SOPT4_FTM2CH0SRC_01   = 0x1        // CMP0 output
	SIM_SOPT4_FTM2CH0SRC_10   = 0x2        // CMP1 output
	SIM_SOPT4_FTM2CH1SRC_Pos  = 0x16       // Position of FTM2CH1SRC field.
	SIM_SOPT4_FTM2CH1SRC_Msk  = 0x400000   // Bit mask of FTM2CH1SRC field.
	SIM_SOPT4_FTM2CH1SRC      = 0x400000   // Bit FTM2CH1SRC.
	SIM_SOPT4_FTM2CH1SRC_0    = 0x0        // FTM2_CH1 signal
	SIM_SOPT4_FTM2CH1SRC_1    = 0x1        // Exclusive OR of FTM2_CH1, FTM2_CH0 and FTM1_CH1.
	SIM_SOPT4_FTM0CLKSEL_Pos  = 0x18       // Position of FTM0CLKSEL field.
	SIM_SOPT4_FTM0CLKSEL_Msk  = 0x1000000  // Bit mask of FTM0CLKSEL field.
	SIM_SOPT4_FTM0CLKSEL      = 0x1000000  // Bit FTM0CLKSEL.
	SIM_SOPT4_FTM0CLKSEL_0    = 0x0        // FTM_CLK0 pin
	SIM_SOPT4_FTM0CLKSEL_1    = 0x1        // FTM_CLK1 pin
	SIM_SOPT4_FTM1CLKSEL_Pos  = 0x19       // Position of FTM1CLKSEL field.
	SIM_SOPT4_FTM1CLKSEL_Msk  = 0x2000000  // Bit mask of FTM1CLKSEL field.
	SIM_SOPT4_FTM1CLKSEL      = 0x2000000  // Bit FTM1CLKSEL.
	SIM_SOPT4_FTM1CLKSEL_0    = 0x0        // FTM_CLK0 pin
	SIM_SOPT4_FTM1CLKSEL_1    = 0x1        // FTM_CLK1 pin
	SIM_SOPT4_FTM2CLKSEL_Pos  = 0x1a       // Position of FTM2CLKSEL field.
	SIM_SOPT4_FTM2CLKSEL_Msk  = 0x4000000  // Bit mask of FTM2CLKSEL field.
	SIM_SOPT4_FTM2CLKSEL      = 0x4000000  // Bit FTM2CLKSEL.
	SIM_SOPT4_FTM2CLKSEL_0    = 0x0        // FTM2 external clock driven by FTM_CLK0 pin.
	SIM_SOPT4_FTM2CLKSEL_1    = 0x1        // FTM2 external clock driven by FTM_CLK1 pin.
	SIM_SOPT4_FTM0TRG0SRC_Pos = 0x1c       // Position of FTM0TRG0SRC field.
	SIM_SOPT4_FTM0TRG0SRC_Msk = 0x10000000 // Bit mask of FTM0TRG0SRC field.
	SIM_SOPT4_FTM0TRG0SRC     = 0x10000000 // Bit FTM0TRG0SRC.
	SIM_SOPT4_FTM0TRG0SRC_0   = 0x0        // HSCMP0 output drives FTM0 hardware trigger 0
	SIM_SOPT4_FTM0TRG0SRC_1   = 0x1        // FTM1 channel match drives FTM0 hardware trigger 0
	SIM_SOPT4_FTM0TRG1SRC_Pos = 0x1d       // Position of FTM0TRG1SRC field.
	SIM_SOPT4_FTM0TRG1SRC_Msk = 0x20000000 // Bit mask of FTM0TRG1SRC field.
	SIM_SOPT4_FTM0TRG1SRC     = 0x20000000 // Bit FTM0TRG1SRC.
	SIM_SOPT4_FTM0TRG1SRC_0   = 0x0        // PDB output trigger 1 drives FTM0 hardware trigger 1
	SIM_SOPT4_FTM0TRG1SRC_1   = 0x1        // FTM2 channel match drives FTM0 hardware trigger 1

	// SOPT5: System Options Register 5
	SIM_SOPT5_UART0TXSRC_Pos   = 0x0     // Position of UART0TXSRC field.
	SIM_SOPT5_UART0TXSRC_Msk   = 0x3     // Bit mask of UART0TXSRC field.
	SIM_SOPT5_UART0TXSRC_00    = 0x0     // UART0_TX pin
	SIM_SOPT5_UART0TXSRC_01    = 0x1     // UART0_TX pin modulated with FTM1 channel 0 output
	SIM_SOPT5_UART0TXSRC_10    = 0x2     // UART0_TX pin modulated with FTM2 channel 0 output
	SIM_SOPT5_UART0RXSRC_Pos   = 0x2     // Position of UART0RXSRC field.
	SIM_SOPT5_UART0RXSRC_Msk   = 0xc     // Bit mask of UART0RXSRC field.
	SIM_SOPT5_UART0RXSRC_00    = 0x0     // UART0_RX pin
	SIM_SOPT5_UART0RXSRC_01    = 0x1     // CMP0
	SIM_SOPT5_UART0RXSRC_10    = 0x2     // CMP1
	SIM_SOPT5_UART1TXSRC_Pos   = 0x4     // Position of UART1TXSRC field.
	SIM_SOPT5_UART1TXSRC_Msk   = 0x30    // Bit mask of UART1TXSRC field.
	SIM_SOPT5_UART1TXSRC_00    = 0x0     // UART1_TX pin
	SIM_SOPT5_UART1TXSRC_01    = 0x1     // UART1_TX pin modulated with FTM1 channel 0 output
	SIM_SOPT5_UART1TXSRC_10    = 0x2     // UART1_TX pin modulated with FTM2 channel 0 output
	SIM_SOPT5_UART1RXSRC_Pos   = 0x6     // Position of UART1RXSRC field.
	SIM_SOPT5_UART1RXSRC_Msk   = 0xc0    // Bit mask of UART1RXSRC field.
	SIM_SOPT5_UART1RXSRC_00    = 0x0     // UART1_RX pin
	SIM_SOPT5_UART1RXSRC_01    = 0x1     // CMP0
	SIM_SOPT5_UART1RXSRC_10    = 0x2     // CMP1
	SIM_SOPT5_LPUART0RXSRC_Pos = 0x12    // Position of LPUART0RXSRC field.
	SIM_SOPT5_LPUART0RXSRC_Msk = 0xc0000 // Bit mask of LPUART0RXSRC field.
	SIM_SOPT5_LPUART0RXSRC_00  = 0x0     // LPUART0_RX pin
	SIM_SOPT5_LPUART0RXSRC_01  = 0x1     // CMP0 output
	SIM_SOPT5_LPUART0RXSRC_10  = 0x2     // CMP1 output

	// SOPT7: System Options Register 7
	SIM_SOPT7_ADC0TRGSEL_Pos    = 0x0    // Position of ADC0TRGSEL field.
	SIM_SOPT7_ADC0TRGSEL_Msk    = 0xf    // Bit mask of ADC0TRGSEL field.
	SIM_SOPT7_ADC0TRGSEL_0000   = 0x0    // PDB external trigger pin input (PDB0_EXTRG)
	SIM_SOPT7_ADC0TRGSEL_0001   = 0x1    // High speed comparator 0 output
	SIM_SOPT7_ADC0TRGSEL_0010   = 0x2    // High speed comparator 1 output
	SIM_SOPT7_ADC0TRGSEL_0100   = 0x4    // PIT trigger 0
	SIM_SOPT7_ADC0TRGSEL_0101   = 0x5    // PIT trigger 1
	SIM_SOPT7_ADC0TRGSEL_0110   = 0x6    // PIT trigger 2
	SIM_SOPT7_ADC0TRGSEL_0111   = 0x7    // PIT trigger 3
	SIM_SOPT7_ADC0TRGSEL_1000   = 0x8    // FTM0 trigger
	SIM_SOPT7_ADC0TRGSEL_1001   = 0x9    // FTM1 trigger
	SIM_SOPT7_ADC0TRGSEL_1010   = 0xa    // FTM2 trigger
	SIM_SOPT7_ADC0TRGSEL_1100   = 0xc    // RTC alarm
	SIM_SOPT7_ADC0TRGSEL_1101   = 0xd    // RTC seconds
	SIM_SOPT7_ADC0TRGSEL_1110   = 0xe    // Low-power timer (LPTMR) trigger
	SIM_SOPT7_ADC0PRETRGSEL_Pos = 0x4    // Position of ADC0PRETRGSEL field.
	SIM_SOPT7_ADC0PRETRGSEL_Msk = 0x10   // Bit mask of ADC0PRETRGSEL field.
	SIM_SOPT7_ADC0PRETRGSEL     = 0x10   // Bit ADC0PRETRGSEL.
	SIM_SOPT7_ADC0PRETRGSEL_0   = 0x0    // Pre-trigger A
	SIM_SOPT7_ADC0PRETRGSEL_1   = 0x1    // Pre-trigger B
	SIM_SOPT7_ADC0ALTTRGEN_Pos  = 0x7    // Position of ADC0ALTTRGEN field.
	SIM_SOPT7_ADC0ALTTRGEN_Msk  = 0x80   // Bit mask of ADC0ALTTRGEN field.
	SIM_SOPT7_ADC0ALTTRGEN      = 0x80   // Bit ADC0ALTTRGEN.
	SIM_SOPT7_ADC0ALTTRGEN_0    = 0x0    // PDB trigger selected for ADC0.
	SIM_SOPT7_ADC0ALTTRGEN_1    = 0x1    // Alternate trigger selected for ADC0.
	SIM_SOPT7_ADC1TRGSEL_Pos    = 0x8    // Position of ADC1TRGSEL field.
	SIM_SOPT7_ADC1TRGSEL_Msk    = 0xf00  // Bit mask of ADC1TRGSEL field.
	SIM_SOPT7_ADC1TRGSEL_0000   = 0x0    // PDB external trigger pin input (PDB0_EXTRG)
	SIM_SOPT7_ADC1TRGSEL_0001   = 0x1    // High speed comparator 0 output
	SIM_SOPT7_ADC1TRGSEL_0010   = 0x2    // High speed comparator 1 output
	SIM_SOPT7_ADC1TRGSEL_0100   = 0x4    // PIT trigger 0
	SIM_SOPT7_ADC1TRGSEL_0101   = 0x5    // PIT trigger 1
	SIM_SOPT7_ADC1TRGSEL_0110   = 0x6    // PIT trigger 2
	SIM_SOPT7_ADC1TRGSEL_0111   = 0x7    // PIT trigger 3
	SIM_SOPT7_ADC1TRGSEL_1000   = 0x8    // FTM0 trigger
	SIM_SOPT7_ADC1TRGSEL_1001   = 0x9    // FTM1 trigger
	SIM_SOPT7_ADC1TRGSEL_1010   = 0xa    // FTM2 trigger
	SIM_SOPT7_ADC1TRGSEL_1100   = 0xc    // RTC alarm
	SIM_SOPT7_ADC1TRGSEL_1101   = 0xd    // RTC seconds
	SIM_SOPT7_ADC1TRGSEL_1110   = 0xe    // Low-power timer (LPTMR) trigger
	SIM_SOPT7_ADC1PRETRGSEL_Pos = 0xc    // Position of ADC1PRETRGSEL field.
	SIM_SOPT7_ADC1PRETRGSEL_Msk = 0x1000 // Bit mask of ADC1PRETRGSEL field.
	SIM_SOPT7_ADC1PRETRGSEL     = 0x1000 // Bit ADC1PRETRGSEL.
	SIM_SOPT7_ADC1PRETRGSEL_0   = 0x0    // Pre-trigger A selected for ADC1.
	SIM_SOPT7_ADC1PRETRGSEL_1   = 0x1    // Pre-trigger B selected for ADC1.
	SIM_SOPT7_ADC1ALTTRGEN_Pos  = 0xf    // Position of ADC1ALTTRGEN field.
	SIM_SOPT7_ADC1ALTTRGEN_Msk  = 0x8000 // Bit mask of ADC1ALTTRGEN field.
	SIM_SOPT7_ADC1ALTTRGEN      = 0x8000 // Bit ADC1ALTTRGEN.
	SIM_SOPT7_ADC1ALTTRGEN_0    = 0x0    // PDB trigger selected for ADC1
	SIM_SOPT7_ADC1ALTTRGEN_1    = 0x1    // Alternate trigger selected for ADC1 as defined by ADC1TRGSEL.

	// SOPT8: System Options Register 8
	SIM_SOPT8_FTM0SYNCBIT_Pos = 0x0      // Position of FTM0SYNCBIT field.
	SIM_SOPT8_FTM0SYNCBIT_Msk = 0x1      // Bit mask of FTM0SYNCBIT field.
	SIM_SOPT8_FTM0SYNCBIT     = 0x1      // Bit FTM0SYNCBIT.
	SIM_SOPT8_FTM0SYNCBIT_0   = 0x0      // No effect
	SIM_SOPT8_FTM0SYNCBIT_1   = 0x1      // Write 1 to assert the TRIG0 input to FTM0, software must clear this bit to allow other trigger sources to assert.
	SIM_SOPT8_FTM1SYNCBIT_Pos = 0x1      // Position of FTM1SYNCBIT field.
	SIM_SOPT8_FTM1SYNCBIT_Msk = 0x2      // Bit mask of FTM1SYNCBIT field.
	SIM_SOPT8_FTM1SYNCBIT     = 0x2      // Bit FTM1SYNCBIT.
	SIM_SOPT8_FTM1SYNCBIT_0   = 0x0      // No effect.
	SIM_SOPT8_FTM1SYNCBIT_1   = 0x1      // Write 1 to assert the TRIG0 input to FTM1, software must clear this bit to allow other trigger sources to assert.
	SIM_SOPT8_FTM2SYNCBIT_Pos = 0x2      // Position of FTM2SYNCBIT field.
	SIM_SOPT8_FTM2SYNCBIT_Msk = 0x4      // Bit mask of FTM2SYNCBIT field.
	SIM_SOPT8_FTM2SYNCBIT     = 0x4      // Bit FTM2SYNCBIT.
	SIM_SOPT8_FTM2SYNCBIT_0   = 0x0      // No effect.
	SIM_SOPT8_FTM2SYNCBIT_1   = 0x1      // Write 1 to assert the TRIG0 input to FTM2, software must clear this bit to allow other trigger sources to assert.
	SIM_SOPT8_FTM0OCH0SRC_Pos = 0x10     // Position of FTM0OCH0SRC field.
	SIM_SOPT8_FTM0OCH0SRC_Msk = 0x10000  // Bit mask of FTM0OCH0SRC field.
	SIM_SOPT8_FTM0OCH0SRC     = 0x10000  // Bit FTM0OCH0SRC.
	SIM_SOPT8_FTM0OCH0SRC_0   = 0x0      // FTM0_CH0 pin is output of FTM0 channel 0 output
	SIM_SOPT8_FTM0OCH0SRC_1   = 0x1      // FTM0_CH0 pin is output of FTM0 channel 0 output, modulated by FTM1 channel 1 output
	SIM_SOPT8_FTM0OCH1SRC_Pos = 0x11     // Position of FTM0OCH1SRC field.
	SIM_SOPT8_FTM0OCH1SRC_Msk = 0x20000  // Bit mask of FTM0OCH1SRC field.
	SIM_SOPT8_FTM0OCH1SRC     = 0x20000  // Bit FTM0OCH1SRC.
	SIM_SOPT8_FTM0OCH1SRC_0   = 0x0      // FTM0_CH1 pin is output of FTM0 channel 1 output
	SIM_SOPT8_FTM0OCH1SRC_1   = 0x1      // FTM0_CH1 pin is output of FTM0 channel 1 output, modulated by FTM1 channel 1 output
	SIM_SOPT8_FTM0OCH2SRC_Pos = 0x12     // Position of FTM0OCH2SRC field.
	SIM_SOPT8_FTM0OCH2SRC_Msk = 0x40000  // Bit mask of FTM0OCH2SRC field.
	SIM_SOPT8_FTM0OCH2SRC     = 0x40000  // Bit FTM0OCH2SRC.
	SIM_SOPT8_FTM0OCH2SRC_0   = 0x0      // FTM0_CH2 pin is output of FTM0 channel 2 output
	SIM_SOPT8_FTM0OCH2SRC_1   = 0x1      // FTM0_CH2 pin is output of FTM0 channel 2 output, modulated by FTM1 channel 1 output
	SIM_SOPT8_FTM0OCH3SRC_Pos = 0x13     // Position of FTM0OCH3SRC field.
	SIM_SOPT8_FTM0OCH3SRC_Msk = 0x80000  // Bit mask of FTM0OCH3SRC field.
	SIM_SOPT8_FTM0OCH3SRC     = 0x80000  // Bit FTM0OCH3SRC.
	SIM_SOPT8_FTM0OCH3SRC_0   = 0x0      // FTM0_CH3 pin is output of FTM0 channel 3 output
	SIM_SOPT8_FTM0OCH3SRC_1   = 0x1      // FTM0_CH3 pin is output of FTM0 channel 3 output, modulated by FTM1 channel 1 output
	SIM_SOPT8_FTM0OCH4SRC_Pos = 0x14     // Position of FTM0OCH4SRC field.
	SIM_SOPT8_FTM0OCH4SRC_Msk = 0x100000 // Bit mask of FTM0OCH4SRC field.
	SIM_SOPT8_FTM0OCH4SRC     = 0x100000 // Bit FTM0OCH4SRC.
	SIM_SOPT8_FTM0OCH4SRC_0   = 0x0      // FTM0_CH4 pin is output of FTM0 channel 4 output
	SIM_SOPT8_FTM0OCH4SRC_1   = 0x1      // FTM0_CH4 pin is output of FTM0 channel 4 output, modulated by FTM1 channel 1 output
	SIM_SOPT8_FTM0OCH5SRC_Pos = 0x15     // Position of FTM0OCH5SRC field.
	SIM_SOPT8_FTM0OCH5SRC_Msk = 0x200000 // Bit mask of FTM0OCH5SRC field.
	SIM_SOPT8_FTM0OCH5SRC     = 0x200000 // Bit FTM0OCH5SRC.
	SIM_SOPT8_FTM0OCH5SRC_0   = 0x0      // FTM0_CH5 pin is output of FTM0 channel 5 output
	SIM_SOPT8_FTM0OCH5SRC_1   = 0x1      // FTM0_CH5 pin is output of FTM0 channel 5 output, modulated by FTM1 channel 1 output
	SIM_SOPT8_FTM0OCH6SRC_Pos = 0x16     // Position of FTM0OCH6SRC field.
	SIM_SOPT8_FTM0OCH6SRC_Msk = 0x400000 // Bit mask of FTM0OCH6SRC field.
	SIM_SOPT8_FTM0OCH6SRC     = 0x400000 // Bit FTM0OCH6SRC.
	SIM_SOPT8_FTM0OCH6SRC_0   = 0x0      // FTM0_CH6 pin is output of FTM0 channel 6 output
	SIM_SOPT8_FTM0OCH6SRC_1   = 0x1      // FTM0_CH6 pin is output of FTM0 channel 6 output, modulated by FTM1 channel 1 output
	SIM_SOPT8_FTM0OCH7SRC_Pos = 0x17     // Position of FTM0OCH7SRC field.
	SIM_SOPT8_FTM0OCH7SRC_Msk = 0x800000 // Bit mask of FTM0OCH7SRC field.
	SIM_SOPT8_FTM0OCH7SRC     = 0x800000 // Bit FTM0OCH7SRC.
	SIM_SOPT8_FTM0OCH7SRC_0   = 0x0      // FTM0_CH7 pin is output of FTM0 channel 7 output
	SIM_SOPT8_FTM0OCH7SRC_1   = 0x1      // FTM0_CH7 pin is output of FTM0 channel 7 output, modulated by FTM1 channel 1 output

	// SDID: System Device Identification Register
	SIM_SDID_PINID_Pos     = 0x0        // Position of PINID field.
	SIM_SDID_PINID_Msk     = 0xf        // Bit mask of PINID field.
	SIM_SDID_PINID_0010    = 0x2        // 32-pin
	SIM_SDID_PINID_0100    = 0x4        // 48-pin
	SIM_SDID_PINID_0101    = 0x5        // 64-pin
	SIM_SDID_PINID_0110    = 0x6        // 80-pin
	SIM_SDID_PINID_0111    = 0x7        // 81-pin or 121-pin
	SIM_SDID_PINID_1000    = 0x8        // 100-pin
	SIM_SDID_PINID_1001    = 0x9        // 121-pin
	SIM_SDID_PINID_1010    = 0xa        // 144-pin
	SIM_SDID_PINID_1011    = 0xb        // Custom pinout (WLCSP)
	SIM_SDID_PINID_1100    = 0xc        // 169-pin
	SIM_SDID_PINID_1110    = 0xe        // 256-pin
	SIM_SDID_FAMID_Pos     = 0x4        // Position of FAMID field.
	SIM_SDID_FAMID_Msk     = 0x70       // Bit mask of FAMID field.
	SIM_SDID_FAMID_000     = 0x0        // K1x Family (without tamper)
	SIM_SDID_FAMID_001     = 0x1        // K2x Family (without tamper)
	SIM_SDID_FAMID_010     = 0x2        // K3x Family or K1x/K6x Family (with tamper)
	SIM_SDID_FAMID_011     = 0x3        // K4x Family or K2x Family (with tamper)
	SIM_SDID_FAMID_100     = 0x4        // K6x Family (without tamper)
	SIM_SDID_FAMID_101     = 0x5        // K7x Family
	SIM_SDID_DIEID_Pos     = 0x7        // Position of DIEID field.
	SIM_SDID_DIEID_Msk     = 0xf80      // Bit mask of DIEID field.
	SIM_SDID_REVID_Pos     = 0xc        // Position of REVID field.
	SIM_SDID_REVID_Msk     = 0xf000     // Bit mask of REVID field.
	SIM_SDID_SERIESID_Pos  = 0x14       // Position of SERIESID field.
	SIM_SDID_SERIESID_Msk  = 0xf00000   // Bit mask of SERIESID field.
	SIM_SDID_SERIESID_0000 = 0x0        // Kinetis K series
	SIM_SDID_SERIESID_0001 = 0x1        // Kinetis L series
	SIM_SDID_SERIESID_0101 = 0x5        // Kinetis W series
	SIM_SDID_SERIESID_0110 = 0x6        // Kinetis V series
	SIM_SDID_SUBFAMID_Pos  = 0x18       // Position of SUBFAMID field.
	SIM_SDID_SUBFAMID_Msk  = 0xf000000  // Bit mask of SUBFAMID field.
	SIM_SDID_SUBFAMID_0000 = 0x0        // Kx0 Subfamily
	SIM_SDID_SUBFAMID_0001 = 0x1        // Kx1 Subfamily (tamper detect)
	SIM_SDID_SUBFAMID_0010 = 0x2        // Kx2 Subfamily
	SIM_SDID_SUBFAMID_0011 = 0x3        // Kx3 Subfamily (tamper detect)
	SIM_SDID_SUBFAMID_0100 = 0x4        // Kx4 Subfamily
	SIM_SDID_SUBFAMID_0101 = 0x5        // Kx5 Subfamily (tamper detect)
	SIM_SDID_SUBFAMID_0110 = 0x6        // Kx6 Subfamily
	SIM_SDID_FAMILYID_Pos  = 0x1c       // Position of FAMILYID field.
	SIM_SDID_FAMILYID_Msk  = 0xf0000000 // Bit mask of FAMILYID field.
	SIM_SDID_FAMILYID_0001 = 0x1        // K1x Family
	SIM_SDID_FAMILYID_0010 = 0x2        // K2x Family
	SIM_SDID_FAMILYID_0011 = 0x3        // K3x Family
	SIM_SDID_FAMILYID_0100 = 0x4        // K4x Family
	SIM_SDID_FAMILYID_0110 = 0x6        // K6x Family
	SIM_SDID_FAMILYID_0111 = 0x7        // K7x Family

	// SCGC4: System Clock Gating Control Register 4
	SIM_SCGC4_EWM_Pos    = 0x1      // Position of EWM field.
	SIM_SCGC4_EWM_Msk    = 0x2      // Bit mask of EWM field.
	SIM_SCGC4_EWM        = 0x2      // Bit EWM.
	SIM_SCGC4_EWM_0      = 0x0      // Clock disabled
	SIM_SCGC4_EWM_1      = 0x1      // Clock enabled
	SIM_SCGC4_I2C0_Pos   = 0x6      // Position of I2C0 field.
	SIM_SCGC4_I2C0_Msk   = 0x40     // Bit mask of I2C0 field.
	SIM_SCGC4_I2C0       = 0x40     // Bit I2C0.
	SIM_SCGC4_I2C0_0     = 0x0      // Clock disabled
	SIM_SCGC4_I2C0_1     = 0x1      // Clock enabled
	SIM_SCGC4_I2C1_Pos   = 0x7      // Position of I2C1 field.
	SIM_SCGC4_I2C1_Msk   = 0x80     // Bit mask of I2C1 field.
	SIM_SCGC4_I2C1       = 0x80     // Bit I2C1.
	SIM_SCGC4_I2C1_0     = 0x0      // Clock disabled
	SIM_SCGC4_I2C1_1     = 0x1      // Clock enabled
	SIM_SCGC4_UART0_Pos  = 0xa      // Position of UART0 field.
	SIM_SCGC4_UART0_Msk  = 0x400    // Bit mask of UART0 field.
	SIM_SCGC4_UART0      = 0x400    // Bit UART0.
	SIM_SCGC4_UART0_0    = 0x0      // Clock disabled
	SIM_SCGC4_UART0_1    = 0x1      // Clock enabled
	SIM_SCGC4_UART1_Pos  = 0xb      // Position of UART1 field.
	SIM_SCGC4_UART1_Msk  = 0x800    // Bit mask of UART1 field.
	SIM_SCGC4_UART1      = 0x800    // Bit UART1.
	SIM_SCGC4_UART1_0    = 0x0      // Clock disabled
	SIM_SCGC4_UART1_1    = 0x1      // Clock enabled
	SIM_SCGC4_UART2_Pos  = 0xc      // Position of UART2 field.
	SIM_SCGC4_UART2_Msk  = 0x1000   // Bit mask of UART2 field.
	SIM_SCGC4_UART2      = 0x1000   // Bit UART2.
	SIM_SCGC4_UART2_0    = 0x0      // Clock disabled
	SIM_SCGC4_UART2_1    = 0x1      // Clock enabled
	SIM_SCGC4_USBOTG_Pos = 0x12     // Position of USBOTG field.
	SIM_SCGC4_USBOTG_Msk = 0x40000  // Bit mask of USBOTG field.
	SIM_SCGC4_USBOTG     = 0x40000  // Bit USBOTG.
	SIM_SCGC4_USBOTG_0   = 0x0      // Clock disabled
	SIM_SCGC4_USBOTG_1   = 0x1      // Clock enabled
	SIM_SCGC4_CMP_Pos    = 0x13     // Position of CMP field.
	SIM_SCGC4_CMP_Msk    = 0x80000  // Bit mask of CMP field.
	SIM_SCGC4_CMP        = 0x80000  // Bit CMP.
	SIM_SCGC4_CMP_0      = 0x0      // Clock disabled
	SIM_SCGC4_CMP_1      = 0x1      // Clock enabled
	SIM_SCGC4_VREF_Pos   = 0x14     // Position of VREF field.
	SIM_SCGC4_VREF_Msk   = 0x100000 // Bit mask of VREF field.
	SIM_SCGC4_VREF       = 0x100000 // Bit VREF.
	SIM_SCGC4_VREF_0     = 0x0      // Clock disabled
	SIM_SCGC4_VREF_1     = 0x1      // Clock enabled

	// SCGC5: System Clock Gating Control Register 5
	SIM_SCGC5_LPTMR_Pos = 0x0    // Position of LPTMR field.
	SIM_SCGC5_LPTMR_Msk = 0x1    // Bit mask of LPTMR field.
	SIM_SCGC5_LPTMR     = 0x1    // Bit LPTMR.
	SIM_SCGC5_LPTMR_0   = 0x0    // Access disabled
	SIM_SCGC5_LPTMR_1   = 0x1    // Access enabled
	SIM_SCGC5_PORTA_Pos = 0x9    // Position of PORTA field.
	SIM_SCGC5_PORTA_Msk = 0x200  // Bit mask of PORTA field.
	SIM_SCGC5_PORTA     = 0x200  // Bit PORTA.
	SIM_SCGC5_PORTA_0   = 0x0    // Clock disabled
	SIM_SCGC5_PORTA_1   = 0x1    // Clock enabled
	SIM_SCGC5_PORTB_Pos = 0xa    // Position of PORTB field.
	SIM_SCGC5_PORTB_Msk = 0x400  // Bit mask of PORTB field.
	SIM_SCGC5_PORTB     = 0x400  // Bit PORTB.
	SIM_SCGC5_PORTB_0   = 0x0    // Clock disabled
	SIM_SCGC5_PORTB_1   = 0x1    // Clock enabled
	SIM_SCGC5_PORTC_Pos = 0xb    // Position of PORTC field.
	SIM_SCGC5_PORTC_Msk = 0x800  // Bit mask of PORTC field.
	SIM_SCGC5_PORTC     = 0x800  // Bit PORTC.
	SIM_SCGC5_PORTC_0   = 0x0    // Clock disabled
	SIM_SCGC5_PORTC_1   = 0x1    // Clock enabled
	SIM_SCGC5_PORTD_Pos = 0xc    // Position of PORTD field.
	SIM_SCGC5_PORTD_Msk = 0x1000 // Bit mask of PORTD field.
	SIM_SCGC5_PORTD     = 0x1000 // Bit PORTD.
	SIM_SCGC5_PORTD_0   = 0x0    // Clock disabled
	SIM_SCGC5_PORTD_1   = 0x1    // Clock enabled
	SIM_SCGC5_PORTE_Pos = 0xd    // Position of PORTE field.
	SIM_SCGC5_PORTE_Msk = 0x2000 // Bit mask of PORTE field.
	SIM_SCGC5_PORTE     = 0x2000 // Bit PORTE.
	SIM_SCGC5_PORTE_0   = 0x0    // Clock disabled
	SIM_SCGC5_PORTE_1   = 0x1    // Clock enabled

	// SCGC6: System Clock Gating Control Register 6
	SIM_SCGC6_FTF_Pos     = 0x0        // Position of FTF field.
	SIM_SCGC6_FTF_Msk     = 0x1        // Bit mask of FTF field.
	SIM_SCGC6_FTF         = 0x1        // Bit FTF.
	SIM_SCGC6_FTF_0       = 0x0        // Clock disabled
	SIM_SCGC6_FTF_1       = 0x1        // Clock enabled
	SIM_SCGC6_DMAMUX_Pos  = 0x1        // Position of DMAMUX field.
	SIM_SCGC6_DMAMUX_Msk  = 0x2        // Bit mask of DMAMUX field.
	SIM_SCGC6_DMAMUX      = 0x2        // Bit DMAMUX.
	SIM_SCGC6_DMAMUX_0    = 0x0        // Clock disabled
	SIM_SCGC6_DMAMUX_1    = 0x1        // Clock enabled
	SIM_SCGC6_ADC1_Pos    = 0x7        // Position of ADC1 field.
	SIM_SCGC6_ADC1_Msk    = 0x80       // Bit mask of ADC1 field.
	SIM_SCGC6_ADC1        = 0x80       // Bit ADC1.
	SIM_SCGC6_ADC1_0      = 0x0        // Clock disabled
	SIM_SCGC6_ADC1_1      = 0x1        // Clock enabled
	SIM_SCGC6_RNGA_Pos    = 0x9        // Position of RNGA field.
	SIM_SCGC6_RNGA_Msk    = 0x200      // Bit mask of RNGA field.
	SIM_SCGC6_RNGA        = 0x200      // Bit RNGA.
	SIM_SCGC6_LPUART0_Pos = 0xa        // Position of LPUART0 field.
	SIM_SCGC6_LPUART0_Msk = 0x400      // Bit mask of LPUART0 field.
	SIM_SCGC6_LPUART0     = 0x400      // Bit LPUART0.
	SIM_SCGC6_LPUART0_0   = 0x0        // Clock disabled
	SIM_SCGC6_LPUART0_1   = 0x1        // Clock enabled
	SIM_SCGC6_SPI0_Pos    = 0xc        // Position of SPI0 field.
	SIM_SCGC6_SPI0_Msk    = 0x1000     // Bit mask of SPI0 field.
	SIM_SCGC6_SPI0        = 0x1000     // Bit SPI0.
	SIM_SCGC6_SPI0_0      = 0x0        // Clock disabled
	SIM_SCGC6_SPI0_1      = 0x1        // Clock enabled
	SIM_SCGC6_SPI1_Pos    = 0xd        // Position of SPI1 field.
	SIM_SCGC6_SPI1_Msk    = 0x2000     // Bit mask of SPI1 field.
	SIM_SCGC6_SPI1        = 0x2000     // Bit SPI1.
	SIM_SCGC6_SPI1_0      = 0x0        // Clock disabled
	SIM_SCGC6_SPI1_1      = 0x1        // Clock enabled
	SIM_SCGC6_I2S_Pos     = 0xf        // Position of I2S field.
	SIM_SCGC6_I2S_Msk     = 0x8000     // Bit mask of I2S field.
	SIM_SCGC6_I2S         = 0x8000     // Bit I2S.
	SIM_SCGC6_I2S_0       = 0x0        // Clock disabled
	SIM_SCGC6_I2S_1       = 0x1        // Clock enabled
	SIM_SCGC6_CRC_Pos     = 0x12       // Position of CRC field.
	SIM_SCGC6_CRC_Msk     = 0x40000    // Bit mask of CRC field.
	SIM_SCGC6_CRC         = 0x40000    // Bit CRC.
	SIM_SCGC6_CRC_0       = 0x0        // Clock disabled
	SIM_SCGC6_CRC_1       = 0x1        // Clock enabled
	SIM_SCGC6_PDB_Pos     = 0x16       // Position of PDB field.
	SIM_SCGC6_PDB_Msk     = 0x400000   // Bit mask of PDB field.
	SIM_SCGC6_PDB         = 0x400000   // Bit PDB.
	SIM_SCGC6_PDB_0       = 0x0        // Clock disabled
	SIM_SCGC6_PDB_1       = 0x1        // Clock enabled
	SIM_SCGC6_PIT_Pos     = 0x17       // Position of PIT field.
	SIM_SCGC6_PIT_Msk     = 0x800000   // Bit mask of PIT field.
	SIM_SCGC6_PIT         = 0x800000   // Bit PIT.
	SIM_SCGC6_PIT_0       = 0x0        // Clock disabled
	SIM_SCGC6_PIT_1       = 0x1        // Clock enabled
	SIM_SCGC6_FTM0_Pos    = 0x18       // Position of FTM0 field.
	SIM_SCGC6_FTM0_Msk    = 0x1000000  // Bit mask of FTM0 field.
	SIM_SCGC6_FTM0        = 0x1000000  // Bit FTM0.
	SIM_SCGC6_FTM0_0      = 0x0        // Clock disabled
	SIM_SCGC6_FTM0_1      = 0x1        // Clock enabled
	SIM_SCGC6_FTM1_Pos    = 0x19       // Position of FTM1 field.
	SIM_SCGC6_FTM1_Msk    = 0x2000000  // Bit mask of FTM1 field.
	SIM_SCGC6_FTM1        = 0x2000000  // Bit FTM1.
	SIM_SCGC6_FTM1_0      = 0x0        // Clock disabled
	SIM_SCGC6_FTM1_1      = 0x1        // Clock enabled
	SIM_SCGC6_FTM2_Pos    = 0x1a       // Position of FTM2 field.
	SIM_SCGC6_FTM2_Msk    = 0x4000000  // Bit mask of FTM2 field.
	SIM_SCGC6_FTM2        = 0x4000000  // Bit FTM2.
	SIM_SCGC6_FTM2_0      = 0x0        // Clock disabled
	SIM_SCGC6_FTM2_1      = 0x1        // Clock enabled
	SIM_SCGC6_ADC0_Pos    = 0x1b       // Position of ADC0 field.
	SIM_SCGC6_ADC0_Msk    = 0x8000000  // Bit mask of ADC0 field.
	SIM_SCGC6_ADC0        = 0x8000000  // Bit ADC0.
	SIM_SCGC6_ADC0_0      = 0x0        // Clock disabled
	SIM_SCGC6_ADC0_1      = 0x1        // Clock enabled
	SIM_SCGC6_RTC_Pos     = 0x1d       // Position of RTC field.
	SIM_SCGC6_RTC_Msk     = 0x20000000 // Bit mask of RTC field.
	SIM_SCGC6_RTC         = 0x20000000 // Bit RTC.
	SIM_SCGC6_RTC_0       = 0x0        // Access and interrupts disabled
	SIM_SCGC6_RTC_1       = 0x1        // Access and interrupts enabled
	SIM_SCGC6_DAC0_Pos    = 0x1f       // Position of DAC0 field.
	SIM_SCGC6_DAC0_Msk    = 0x80000000 // Bit mask of DAC0 field.
	SIM_SCGC6_DAC0        = 0x80000000 // Bit DAC0.
	SIM_SCGC6_DAC0_0      = 0x0        // Clock disabled
	SIM_SCGC6_DAC0_1      = 0x1        // Clock enabled

	// SCGC7: System Clock Gating Control Register 7
	SIM_SCGC7_DMA_Pos = 0x1 // Position of DMA field.
	SIM_SCGC7_DMA_Msk = 0x2 // Bit mask of DMA field.
	SIM_SCGC7_DMA     = 0x2 // Bit DMA.
	SIM_SCGC7_DMA_0   = 0x0 // Clock disabled
	SIM_SCGC7_DMA_1   = 0x1 // Clock enabled

	// CLKDIV1: System Clock Divider Register 1
	SIM_CLKDIV1_OUTDIV4_Pos  = 0x10       // Position of OUTDIV4 field.
	SIM_CLKDIV1_OUTDIV4_Msk  = 0xf0000    // Bit mask of OUTDIV4 field.
	SIM_CLKDIV1_OUTDIV4_0000 = 0x0        // Divide-by-1.
	SIM_CLKDIV1_OUTDIV4_0001 = 0x1        // Divide-by-2.
	SIM_CLKDIV1_OUTDIV4_0010 = 0x2        // Divide-by-3.
	SIM_CLKDIV1_OUTDIV4_0011 = 0x3        // Divide-by-4.
	SIM_CLKDIV1_OUTDIV4_0100 = 0x4        // Divide-by-5.
	SIM_CLKDIV1_OUTDIV4_0101 = 0x5        // Divide-by-6.
	SIM_CLKDIV1_OUTDIV4_0110 = 0x6        // Divide-by-7.
	SIM_CLKDIV1_OUTDIV4_0111 = 0x7        // Divide-by-8.
	SIM_CLKDIV1_OUTDIV4_1000 = 0x8        // Divide-by-9.
	SIM_CLKDIV1_OUTDIV4_1001 = 0x9        // Divide-by-10.
	SIM_CLKDIV1_OUTDIV4_1010 = 0xa        // Divide-by-11.
	SIM_CLKDIV1_OUTDIV4_1011 = 0xb        // Divide-by-12.
	SIM_CLKDIV1_OUTDIV4_1100 = 0xc        // Divide-by-13.
	SIM_CLKDIV1_OUTDIV4_1101 = 0xd        // Divide-by-14.
	SIM_CLKDIV1_OUTDIV4_1110 = 0xe        // Divide-by-15.
	SIM_CLKDIV1_OUTDIV4_1111 = 0xf        // Divide-by-16.
	SIM_CLKDIV1_OUTDIV2_Pos  = 0x18       // Position of OUTDIV2 field.
	SIM_CLKDIV1_OUTDIV2_Msk  = 0xf000000  // Bit mask of OUTDIV2 field.
	SIM_CLKDIV1_OUTDIV2_0000 = 0x0        // Divide-by-1.
	SIM_CLKDIV1_OUTDIV2_0001 = 0x1        // Divide-by-2.
	SIM_CLKDIV1_OUTDIV2_0010 = 0x2        // Divide-by-3.
	SIM_CLKDIV1_OUTDIV2_0011 = 0x3        // Divide-by-4.
	SIM_CLKDIV1_OUTDIV2_0100 = 0x4        // Divide-by-5.
	SIM_CLKDIV1_OUTDIV2_0101 = 0x5        // Divide-by-6.
	SIM_CLKDIV1_OUTDIV2_0110 = 0x6        // Divide-by-7.
	SIM_CLKDIV1_OUTDIV2_0111 = 0x7        // Divide-by-8.
	SIM_CLKDIV1_OUTDIV2_1000 = 0x8        // Divide-by-9.
	SIM_CLKDIV1_OUTDIV2_1001 = 0x9        // Divide-by-10.
	SIM_CLKDIV1_OUTDIV2_1010 = 0xa        // Divide-by-11.
	SIM_CLKDIV1_OUTDIV2_1011 = 0xb        // Divide-by-12.
	SIM_CLKDIV1_OUTDIV2_1100 = 0xc        // Divide-by-13.
	SIM_CLKDIV1_OUTDIV2_1101 = 0xd        // Divide-by-14.
	SIM_CLKDIV1_OUTDIV2_1110 = 0xe        // Divide-by-15.
	SIM_CLKDIV1_OUTDIV2_1111 = 0xf        // Divide-by-16.
	SIM_CLKDIV1_OUTDIV1_Pos  = 0x1c       // Position of OUTDIV1 field.
	SIM_CLKDIV1_OUTDIV1_Msk  = 0xf0000000 // Bit mask of OUTDIV1 field.
	SIM_CLKDIV1_OUTDIV1_0000 = 0x0        // Divide-by-1.
	SIM_CLKDIV1_OUTDIV1_0001 = 0x1        // Divide-by-2.
	SIM_CLKDIV1_OUTDIV1_0010 = 0x2        // Divide-by-3.
	SIM_CLKDIV1_OUTDIV1_0011 = 0x3        // Divide-by-4.
	SIM_CLKDIV1_OUTDIV1_0100 = 0x4        // Divide-by-5.
	SIM_CLKDIV1_OUTDIV1_0101 = 0x5        // Divide-by-6.
	SIM_CLKDIV1_OUTDIV1_0110 = 0x6        // Divide-by-7.
	SIM_CLKDIV1_OUTDIV1_0111 = 0x7        // Divide-by-8.
	SIM_CLKDIV1_OUTDIV1_1000 = 0x8        // Divide-by-9.
	SIM_CLKDIV1_OUTDIV1_1001 = 0x9        // Divide-by-10.
	SIM_CLKDIV1_OUTDIV1_1010 = 0xa        // Divide-by-11.
	SIM_CLKDIV1_OUTDIV1_1011 = 0xb        // Divide-by-12.
	SIM_CLKDIV1_OUTDIV1_1100 = 0xc        // Divide-by-13.
	SIM_CLKDIV1_OUTDIV1_1101 = 0xd        // Divide-by-14.
	SIM_CLKDIV1_OUTDIV1_1110 = 0xe        // Divide-by-15.
	SIM_CLKDIV1_OUTDIV1_1111 = 0xf        // Divide-by-16.

	// CLKDIV2: System Clock Divider Register 2
	SIM_CLKDIV2_USBFRAC_Pos = 0x0 // Position of USBFRAC field.
	SIM_CLKDIV2_USBFRAC_Msk = 0x1 // Bit mask of USBFRAC field.
	SIM_CLKDIV2_USBFRAC     = 0x1 // Bit USBFRAC.
	SIM_CLKDIV2_USBDIV_Pos  = 0x1 // Position of USBDIV field.
	SIM_CLKDIV2_USBDIV_Msk  = 0xe // Bit mask of USBDIV field.

	// FCFG1: Flash Configuration Register 1
	SIM_FCFG1_FLASHDIS_Pos  = 0x0       // Position of FLASHDIS field.
	SIM_FCFG1_FLASHDIS_Msk  = 0x1       // Bit mask of FLASHDIS field.
	SIM_FCFG1_FLASHDIS      = 0x1       // Bit FLASHDIS.
	SIM_FCFG1_FLASHDIS_0    = 0x0       // Flash is enabled
	SIM_FCFG1_FLASHDIS_1    = 0x1       // Flash is disabled
	SIM_FCFG1_FLASHDOZE_Pos = 0x1       // Position of FLASHDOZE field.
	SIM_FCFG1_FLASHDOZE_Msk = 0x2       // Bit mask of FLASHDOZE field.
	SIM_FCFG1_FLASHDOZE     = 0x2       // Bit FLASHDOZE.
	SIM_FCFG1_FLASHDOZE_0   = 0x0       // Flash remains enabled during Wait mode
	SIM_FCFG1_FLASHDOZE_1   = 0x1       // Flash is disabled for the duration of Wait mode
	SIM_FCFG1_PFSIZE_Pos    = 0x18      // Position of PFSIZE field.
	SIM_FCFG1_PFSIZE_Msk    = 0xf000000 // Bit mask of PFSIZE field.
	SIM_FCFG1_PFSIZE_0011   = 0x3       // 32 KB of program flash memory
	SIM_FCFG1_PFSIZE_0101   = 0x5       // 64 KB of program flash memory
	SIM_FCFG1_PFSIZE_0111   = 0x7       // 128 KB of program flash memory
	SIM_FCFG1_PFSIZE_1001   = 0x9       // 256 KB of program flash memory
	SIM_FCFG1_PFSIZE_1011   = 0xb       // 512 KB of program flash memory
	SIM_FCFG1_PFSIZE_1101   = 0xd       // 1024 KB of program flash memory
	SIM_FCFG1_PFSIZE_1111   = 0xf       // 256 KB of program flash memory

	// FCFG2: Flash Configuration Register 2
	SIM_FCFG2_MAXADDR1_Pos = 0x10       // Position of MAXADDR1 field.
	SIM_FCFG2_MAXADDR1_Msk = 0x7f0000   // Bit mask of MAXADDR1 field.
	SIM_FCFG2_MAXADDR0_Pos = 0x18       // Position of MAXADDR0 field.
	SIM_FCFG2_MAXADDR0_Msk = 0x7f000000 // Bit mask of MAXADDR0 field.

	// UIDH: Unique Identification Register High
	SIM_UIDH_UID_Pos = 0x0        // Position of UID field.
	SIM_UIDH_UID_Msk = 0xffffffff // Bit mask of UID field.

	// UIDMH: Unique Identification Register Mid-High
	SIM_UIDMH_UID_Pos = 0x0        // Position of UID field.
	SIM_UIDMH_UID_Msk = 0xffffffff // Bit mask of UID field.

	// UIDML: Unique Identification Register Mid Low
	SIM_UIDML_UID_Pos = 0x0        // Position of UID field.
	SIM_UIDML_UID_Msk = 0xffffffff // Bit mask of UID field.

	// UIDL: Unique Identification Register Low
	SIM_UIDL_UID_Pos = 0x0        // Position of UID field.
	SIM_UIDL_UID_Msk = 0xffffffff // Bit mask of UID field.
)

// Bitfields for PORTA: Pin Control and Interrupts
const (
	// PCR0: Pin Control Register n
	PORT_PCR0_PS_Pos    = 0x0       // Position of PS field.
	PORT_PCR0_PS_Msk    = 0x1       // Bit mask of PS field.
	PORT_PCR0_PS        = 0x1       // Bit PS.
	PORT_PCR0_PS_0      = 0x0       // Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR0_PS_1      = 0x1       // Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR0_PE_Pos    = 0x1       // Position of PE field.
	PORT_PCR0_PE_Msk    = 0x2       // Bit mask of PE field.
	PORT_PCR0_PE        = 0x2       // Bit PE.
	PORT_PCR0_PE_0      = 0x0       // Internal pullup or pulldown resistor is not enabled on the corresponding pin.
	PORT_PCR0_PE_1      = 0x1       // Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
	PORT_PCR0_SRE_Pos   = 0x2       // Position of SRE field.
	PORT_PCR0_SRE_Msk   = 0x4       // Bit mask of SRE field.
	PORT_PCR0_SRE       = 0x4       // Bit SRE.
	PORT_PCR0_SRE_0     = 0x0       // Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR0_SRE_1     = 0x1       // Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR0_PFE_Pos   = 0x4       // Position of PFE field.
	PORT_PCR0_PFE_Msk   = 0x10      // Bit mask of PFE field.
	PORT_PCR0_PFE       = 0x10      // Bit PFE.
	PORT_PCR0_PFE_0     = 0x0       // Passive input filter is disabled on the corresponding pin.
	PORT_PCR0_PFE_1     = 0x1       // Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
	PORT_PCR0_ODE_Pos   = 0x5       // Position of ODE field.
	PORT_PCR0_ODE_Msk   = 0x20      // Bit mask of ODE field.
	PORT_PCR0_ODE       = 0x20      // Bit ODE.
	PORT_PCR0_ODE_0     = 0x0       // Open drain output is disabled on the corresponding pin.
	PORT_PCR0_ODE_1     = 0x1       // Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR0_DSE_Pos   = 0x6       // Position of DSE field.
	PORT_PCR0_DSE_Msk   = 0x40      // Bit mask of DSE field.
	PORT_PCR0_DSE       = 0x40      // Bit DSE.
	PORT_PCR0_DSE_0     = 0x0       // Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR0_DSE_1     = 0x1       // High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR0_MUX_Pos   = 0x8       // Position of MUX field.
	PORT_PCR0_MUX_Msk   = 0x700     // Bit mask of MUX field.
	PORT_PCR0_MUX_000   = 0x0       // Pin disabled (analog).
	PORT_PCR0_MUX_001   = 0x1       // Alternative 1 (GPIO).
	PORT_PCR0_MUX_010   = 0x2       // Alternative 2 (chip-specific).
	PORT_PCR0_MUX_011   = 0x3       // Alternative 3 (chip-specific).
	PORT_PCR0_MUX_100   = 0x4       // Alternative 4 (chip-specific).
	PORT_PCR0_MUX_101   = 0x5       // Alternative 5 (chip-specific).
	PORT_PCR0_MUX_110   = 0x6       // Alternative 6 (chip-specific).
	PORT_PCR0_MUX_111   = 0x7       // Alternative 7 (chip-specific).
	PORT_PCR0_LK_Pos    = 0xf       // Position of LK field.
	PORT_PCR0_LK_Msk    = 0x8000    // Bit mask of LK field.
	PORT_PCR0_LK        = 0x8000    // Bit LK.
	PORT_PCR0_LK_0      = 0x0       // Pin Control Register fields [15:0] are not locked.
	PORT_PCR0_LK_1      = 0x1       // Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
	PORT_PCR0_IRQC_Pos  = 0x10      // Position of IRQC field.
	PORT_PCR0_IRQC_Msk  = 0xf0000   // Bit mask of IRQC field.
	PORT_PCR0_IRQC_0000 = 0x0       // Interrupt/DMA request disabled.
	PORT_PCR0_IRQC_0001 = 0x1       // DMA request on rising edge.
	PORT_PCR0_IRQC_0010 = 0x2       // DMA request on falling edge.
	PORT_PCR0_IRQC_0011 = 0x3       // DMA request on either edge.
	PORT_PCR0_IRQC_1000 = 0x8       // Interrupt when logic 0.
	PORT_PCR0_IRQC_1001 = 0x9       // Interrupt on rising-edge.
	PORT_PCR0_IRQC_1010 = 0xa       // Interrupt on falling-edge.
	PORT_PCR0_IRQC_1011 = 0xb       // Interrupt on either edge.
	PORT_PCR0_IRQC_1100 = 0xc       // Interrupt when logic 1.
	PORT_PCR0_ISF_Pos   = 0x18      // Position of ISF field.
	PORT_PCR0_ISF_Msk   = 0x1000000 // Bit mask of ISF field.
	PORT_PCR0_ISF       = 0x1000000 // Bit ISF.
	PORT_PCR0_ISF_0     = 0x0       // Configured interrupt is not detected.
	PORT_PCR0_ISF_1     = 0x1       // Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

	// PCR1: Pin Control Register n
	PORT_PCR1_PS_Pos    = 0x0       // Position of PS field.
	PORT_PCR1_PS_Msk    = 0x1       // Bit mask of PS field.
	PORT_PCR1_PS        = 0x1       // Bit PS.
	PORT_PCR1_PS_0      = 0x0       // Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR1_PS_1      = 0x1       // Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR1_PE_Pos    = 0x1       // Position of PE field.
	PORT_PCR1_PE_Msk    = 0x2       // Bit mask of PE field.
	PORT_PCR1_PE        = 0x2       // Bit PE.
	PORT_PCR1_PE_0      = 0x0       // Internal pullup or pulldown resistor is not enabled on the corresponding pin.
	PORT_PCR1_PE_1      = 0x1       // Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
	PORT_PCR1_SRE_Pos   = 0x2       // Position of SRE field.
	PORT_PCR1_SRE_Msk   = 0x4       // Bit mask of SRE field.
	PORT_PCR1_SRE       = 0x4       // Bit SRE.
	PORT_PCR1_SRE_0     = 0x0       // Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR1_SRE_1     = 0x1       // Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR1_PFE_Pos   = 0x4       // Position of PFE field.
	PORT_PCR1_PFE_Msk   = 0x10      // Bit mask of PFE field.
	PORT_PCR1_PFE       = 0x10      // Bit PFE.
	PORT_PCR1_PFE_0     = 0x0       // Passive input filter is disabled on the corresponding pin.
	PORT_PCR1_PFE_1     = 0x1       // Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
	PORT_PCR1_ODE_Pos   = 0x5       // Position of ODE field.
	PORT_PCR1_ODE_Msk   = 0x20      // Bit mask of ODE field.
	PORT_PCR1_ODE       = 0x20      // Bit ODE.
	PORT_PCR1_ODE_0     = 0x0       // Open drain output is disabled on the corresponding pin.
	PORT_PCR1_ODE_1     = 0x1       // Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR1_DSE_Pos   = 0x6       // Position of DSE field.
	PORT_PCR1_DSE_Msk   = 0x40      // Bit mask of DSE field.
	PORT_PCR1_DSE       = 0x40      // Bit DSE.
	PORT_PCR1_DSE_0     = 0x0       // Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR1_DSE_1     = 0x1       // High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR1_MUX_Pos   = 0x8       // Position of MUX field.
	PORT_PCR1_MUX_Msk   = 0x700     // Bit mask of MUX field.
	PORT_PCR1_MUX_000   = 0x0       // Pin disabled (analog).
	PORT_PCR1_MUX_001   = 0x1       // Alternative 1 (GPIO).
	PORT_PCR1_MUX_010   = 0x2       // Alternative 2 (chip-specific).
	PORT_PCR1_MUX_011   = 0x3       // Alternative 3 (chip-specific).
	PORT_PCR1_MUX_100   = 0x4       // Alternative 4 (chip-specific).
	PORT_PCR1_MUX_101   = 0x5       // Alternative 5 (chip-specific).
	PORT_PCR1_MUX_110   = 0x6       // Alternative 6 (chip-specific).
	PORT_PCR1_MUX_111   = 0x7       // Alternative 7 (chip-specific).
	PORT_PCR1_LK_Pos    = 0xf       // Position of LK field.
	PORT_PCR1_LK_Msk    = 0x8000    // Bit mask of LK field.
	PORT_PCR1_LK        = 0x8000    // Bit LK.
	PORT_PCR1_LK_0      = 0x0       // Pin Control Register fields [15:0] are not locked.
	PORT_PCR1_LK_1      = 0x1       // Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
	PORT_PCR1_IRQC_Pos  = 0x10      // Position of IRQC field.
	PORT_PCR1_IRQC_Msk  = 0xf0000   // Bit mask of IRQC field.
	PORT_PCR1_IRQC_0000 = 0x0       // Interrupt/DMA request disabled.
	PORT_PCR1_IRQC_0001 = 0x1       // DMA request on rising edge.
	PORT_PCR1_IRQC_0010 = 0x2       // DMA request on falling edge.
	PORT_PCR1_IRQC_0011 = 0x3       // DMA request on either edge.
	PORT_PCR1_IRQC_1000 = 0x8       // Interrupt when logic 0.
	PORT_PCR1_IRQC_1001 = 0x9       // Interrupt on rising-edge.
	PORT_PCR1_IRQC_1010 = 0xa       // Interrupt on falling-edge.
	PORT_PCR1_IRQC_1011 = 0xb       // Interrupt on either edge.
	PORT_PCR1_IRQC_1100 = 0xc       // Interrupt when logic 1.
	PORT_PCR1_ISF_Pos   = 0x18      // Position of ISF field.
	PORT_PCR1_ISF_Msk   = 0x1000000 // Bit mask of ISF field.
	PORT_PCR1_ISF       = 0x1000000 // Bit ISF.
	PORT_PCR1_ISF_0     = 0x0       // Configured interrupt is not detected.
	PORT_PCR1_ISF_1     = 0x1       // Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

	// PCR2: Pin Control Register n
	PORT_PCR2_PS_Pos    = 0x0       // Position of PS field.
	PORT_PCR2_PS_Msk    = 0x1       // Bit mask of PS field.
	PORT_PCR2_PS        = 0x1       // Bit PS.
	PORT_PCR2_PS_0      = 0x0       // Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR2_PS_1      = 0x1       // Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR2_PE_Pos    = 0x1       // Position of PE field.
	PORT_PCR2_PE_Msk    = 0x2       // Bit mask of PE field.
	PORT_PCR2_PE        = 0x2       // Bit PE.
	PORT_PCR2_PE_0      = 0x0       // Internal pullup or pulldown resistor is not enabled on the corresponding pin.
	PORT_PCR2_PE_1      = 0x1       // Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
	PORT_PCR2_SRE_Pos   = 0x2       // Position of SRE field.
	PORT_PCR2_SRE_Msk   = 0x4       // Bit mask of SRE field.
	PORT_PCR2_SRE       = 0x4       // Bit SRE.
	PORT_PCR2_SRE_0     = 0x0       // Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR2_SRE_1     = 0x1       // Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR2_PFE_Pos   = 0x4       // Position of PFE field.
	PORT_PCR2_PFE_Msk   = 0x10      // Bit mask of PFE field.
	PORT_PCR2_PFE       = 0x10      // Bit PFE.
	PORT_PCR2_PFE_0     = 0x0       // Passive input filter is disabled on the corresponding pin.
	PORT_PCR2_PFE_1     = 0x1       // Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
	PORT_PCR2_ODE_Pos   = 0x5       // Position of ODE field.
	PORT_PCR2_ODE_Msk   = 0x20      // Bit mask of ODE field.
	PORT_PCR2_ODE       = 0x20      // Bit ODE.
	PORT_PCR2_ODE_0     = 0x0       // Open drain output is disabled on the corresponding pin.
	PORT_PCR2_ODE_1     = 0x1       // Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR2_DSE_Pos   = 0x6       // Position of DSE field.
	PORT_PCR2_DSE_Msk   = 0x40      // Bit mask of DSE field.
	PORT_PCR2_DSE       = 0x40      // Bit DSE.
	PORT_PCR2_DSE_0     = 0x0       // Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR2_DSE_1     = 0x1       // High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR2_MUX_Pos   = 0x8       // Position of MUX field.
	PORT_PCR2_MUX_Msk   = 0x700     // Bit mask of MUX field.
	PORT_PCR2_MUX_000   = 0x0       // Pin disabled (analog).
	PORT_PCR2_MUX_001   = 0x1       // Alternative 1 (GPIO).
	PORT_PCR2_MUX_010   = 0x2       // Alternative 2 (chip-specific).
	PORT_PCR2_MUX_011   = 0x3       // Alternative 3 (chip-specific).
	PORT_PCR2_MUX_100   = 0x4       // Alternative 4 (chip-specific).
	PORT_PCR2_MUX_101   = 0x5       // Alternative 5 (chip-specific).
	PORT_PCR2_MUX_110   = 0x6       // Alternative 6 (chip-specific).
	PORT_PCR2_MUX_111   = 0x7       // Alternative 7 (chip-specific).
	PORT_PCR2_LK_Pos    = 0xf       // Position of LK field.
	PORT_PCR2_LK_Msk    = 0x8000    // Bit mask of LK field.
	PORT_PCR2_LK        = 0x8000    // Bit LK.
	PORT_PCR2_LK_0      = 0x0       // Pin Control Register fields [15:0] are not locked.
	PORT_PCR2_LK_1      = 0x1       // Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
	PORT_PCR2_IRQC_Pos  = 0x10      // Position of IRQC field.
	PORT_PCR2_IRQC_Msk  = 0xf0000   // Bit mask of IRQC field.
	PORT_PCR2_IRQC_0000 = 0x0       // Interrupt/DMA request disabled.
	PORT_PCR2_IRQC_0001 = 0x1       // DMA request on rising edge.
	PORT_PCR2_IRQC_0010 = 0x2       // DMA request on falling edge.
	PORT_PCR2_IRQC_0011 = 0x3       // DMA request on either edge.
	PORT_PCR2_IRQC_1000 = 0x8       // Interrupt when logic 0.
	PORT_PCR2_IRQC_1001 = 0x9       // Interrupt on rising-edge.
	PORT_PCR2_IRQC_1010 = 0xa       // Interrupt on falling-edge.
	PORT_PCR2_IRQC_1011 = 0xb       // Interrupt on either edge.
	PORT_PCR2_IRQC_1100 = 0xc       // Interrupt when logic 1.
	PORT_PCR2_ISF_Pos   = 0x18      // Position of ISF field.
	PORT_PCR2_ISF_Msk   = 0x1000000 // Bit mask of ISF field.
	PORT_PCR2_ISF       = 0x1000000 // Bit ISF.
	PORT_PCR2_ISF_0     = 0x0       // Configured interrupt is not detected.
	PORT_PCR2_ISF_1     = 0x1       // Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

	// PCR3: Pin Control Register n
	PORT_PCR3_PS_Pos    = 0x0       // Position of PS field.
	PORT_PCR3_PS_Msk    = 0x1       // Bit mask of PS field.
	PORT_PCR3_PS        = 0x1       // Bit PS.
	PORT_PCR3_PS_0      = 0x0       // Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR3_PS_1      = 0x1       // Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR3_PE_Pos    = 0x1       // Position of PE field.
	PORT_PCR3_PE_Msk    = 0x2       // Bit mask of PE field.
	PORT_PCR3_PE        = 0x2       // Bit PE.
	PORT_PCR3_PE_0      = 0x0       // Internal pullup or pulldown resistor is not enabled on the corresponding pin.
	PORT_PCR3_PE_1      = 0x1       // Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
	PORT_PCR3_SRE_Pos   = 0x2       // Position of SRE field.
	PORT_PCR3_SRE_Msk   = 0x4       // Bit mask of SRE field.
	PORT_PCR3_SRE       = 0x4       // Bit SRE.
	PORT_PCR3_SRE_0     = 0x0       // Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR3_SRE_1     = 0x1       // Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR3_PFE_Pos   = 0x4       // Position of PFE field.
	PORT_PCR3_PFE_Msk   = 0x10      // Bit mask of PFE field.
	PORT_PCR3_PFE       = 0x10      // Bit PFE.
	PORT_PCR3_PFE_0     = 0x0       // Passive input filter is disabled on the corresponding pin.
	PORT_PCR3_PFE_1     = 0x1       // Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
	PORT_PCR3_ODE_Pos   = 0x5       // Position of ODE field.
	PORT_PCR3_ODE_Msk   = 0x20      // Bit mask of ODE field.
	PORT_PCR3_ODE       = 0x20      // Bit ODE.
	PORT_PCR3_ODE_0     = 0x0       // Open drain output is disabled on the corresponding pin.
	PORT_PCR3_ODE_1     = 0x1       // Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR3_DSE_Pos   = 0x6       // Position of DSE field.
	PORT_PCR3_DSE_Msk   = 0x40      // Bit mask of DSE field.
	PORT_PCR3_DSE       = 0x40      // Bit DSE.
	PORT_PCR3_DSE_0     = 0x0       // Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR3_DSE_1     = 0x1       // High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR3_MUX_Pos   = 0x8       // Position of MUX field.
	PORT_PCR3_MUX_Msk   = 0x700     // Bit mask of MUX field.
	PORT_PCR3_MUX_000   = 0x0       // Pin disabled (analog).
	PORT_PCR3_MUX_001   = 0x1       // Alternative 1 (GPIO).
	PORT_PCR3_MUX_010   = 0x2       // Alternative 2 (chip-specific).
	PORT_PCR3_MUX_011   = 0x3       // Alternative 3 (chip-specific).
	PORT_PCR3_MUX_100   = 0x4       // Alternative 4 (chip-specific).
	PORT_PCR3_MUX_101   = 0x5       // Alternative 5 (chip-specific).
	PORT_PCR3_MUX_110   = 0x6       // Alternative 6 (chip-specific).
	PORT_PCR3_MUX_111   = 0x7       // Alternative 7 (chip-specific).
	PORT_PCR3_LK_Pos    = 0xf       // Position of LK field.
	PORT_PCR3_LK_Msk    = 0x8000    // Bit mask of LK field.
	PORT_PCR3_LK        = 0x8000    // Bit LK.
	PORT_PCR3_LK_0      = 0x0       // Pin Control Register fields [15:0] are not locked.
	PORT_PCR3_LK_1      = 0x1       // Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
	PORT_PCR3_IRQC_Pos  = 0x10      // Position of IRQC field.
	PORT_PCR3_IRQC_Msk  = 0xf0000   // Bit mask of IRQC field.
	PORT_PCR3_IRQC_0000 = 0x0       // Interrupt/DMA request disabled.
	PORT_PCR3_IRQC_0001 = 0x1       // DMA request on rising edge.
	PORT_PCR3_IRQC_0010 = 0x2       // DMA request on falling edge.
	PORT_PCR3_IRQC_0011 = 0x3       // DMA request on either edge.
	PORT_PCR3_IRQC_1000 = 0x8       // Interrupt when logic 0.
	PORT_PCR3_IRQC_1001 = 0x9       // Interrupt on rising-edge.
	PORT_PCR3_IRQC_1010 = 0xa       // Interrupt on falling-edge.
	PORT_PCR3_IRQC_1011 = 0xb       // Interrupt on either edge.
	PORT_PCR3_IRQC_1100 = 0xc       // Interrupt when logic 1.
	PORT_PCR3_ISF_Pos   = 0x18      // Position of ISF field.
	PORT_PCR3_ISF_Msk   = 0x1000000 // Bit mask of ISF field.
	PORT_PCR3_ISF       = 0x1000000 // Bit ISF.
	PORT_PCR3_ISF_0     = 0x0       // Configured interrupt is not detected.
	PORT_PCR3_ISF_1     = 0x1       // Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

	// PCR4: Pin Control Register n
	PORT_PCR4_PS_Pos    = 0x0       // Position of PS field.
	PORT_PCR4_PS_Msk    = 0x1       // Bit mask of PS field.
	PORT_PCR4_PS        = 0x1       // Bit PS.
	PORT_PCR4_PS_0      = 0x0       // Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR4_PS_1      = 0x1       // Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR4_PE_Pos    = 0x1       // Position of PE field.
	PORT_PCR4_PE_Msk    = 0x2       // Bit mask of PE field.
	PORT_PCR4_PE        = 0x2       // Bit PE.
	PORT_PCR4_PE_0      = 0x0       // Internal pullup or pulldown resistor is not enabled on the corresponding pin.
	PORT_PCR4_PE_1      = 0x1       // Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
	PORT_PCR4_SRE_Pos   = 0x2       // Position of SRE field.
	PORT_PCR4_SRE_Msk   = 0x4       // Bit mask of SRE field.
	PORT_PCR4_SRE       = 0x4       // Bit SRE.
	PORT_PCR4_SRE_0     = 0x0       // Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR4_SRE_1     = 0x1       // Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR4_PFE_Pos   = 0x4       // Position of PFE field.
	PORT_PCR4_PFE_Msk   = 0x10      // Bit mask of PFE field.
	PORT_PCR4_PFE       = 0x10      // Bit PFE.
	PORT_PCR4_PFE_0     = 0x0       // Passive input filter is disabled on the corresponding pin.
	PORT_PCR4_PFE_1     = 0x1       // Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
	PORT_PCR4_ODE_Pos   = 0x5       // Position of ODE field.
	PORT_PCR4_ODE_Msk   = 0x20      // Bit mask of ODE field.
	PORT_PCR4_ODE       = 0x20      // Bit ODE.
	PORT_PCR4_ODE_0     = 0x0       // Open drain output is disabled on the corresponding pin.
	PORT_PCR4_ODE_1     = 0x1       // Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR4_DSE_Pos   = 0x6       // Position of DSE field.
	PORT_PCR4_DSE_Msk   = 0x40      // Bit mask of DSE field.
	PORT_PCR4_DSE       = 0x40      // Bit DSE.
	PORT_PCR4_DSE_0     = 0x0       // Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR4_DSE_1     = 0x1       // High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR4_MUX_Pos   = 0x8       // Position of MUX field.
	PORT_PCR4_MUX_Msk   = 0x700     // Bit mask of MUX field.
	PORT_PCR4_MUX_000   = 0x0       // Pin disabled (analog).
	PORT_PCR4_MUX_001   = 0x1       // Alternative 1 (GPIO).
	PORT_PCR4_MUX_010   = 0x2       // Alternative 2 (chip-specific).
	PORT_PCR4_MUX_011   = 0x3       // Alternative 3 (chip-specific).
	PORT_PCR4_MUX_100   = 0x4       // Alternative 4 (chip-specific).
	PORT_PCR4_MUX_101   = 0x5       // Alternative 5 (chip-specific).
	PORT_PCR4_MUX_110   = 0x6       // Alternative 6 (chip-specific).
	PORT_PCR4_MUX_111   = 0x7       // Alternative 7 (chip-specific).
	PORT_PCR4_LK_Pos    = 0xf       // Position of LK field.
	PORT_PCR4_LK_Msk    = 0x8000    // Bit mask of LK field.
	PORT_PCR4_LK        = 0x8000    // Bit LK.
	PORT_PCR4_LK_0      = 0x0       // Pin Control Register fields [15:0] are not locked.
	PORT_PCR4_LK_1      = 0x1       // Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
	PORT_PCR4_IRQC_Pos  = 0x10      // Position of IRQC field.
	PORT_PCR4_IRQC_Msk  = 0xf0000   // Bit mask of IRQC field.
	PORT_PCR4_IRQC_0000 = 0x0       // Interrupt/DMA request disabled.
	PORT_PCR4_IRQC_0001 = 0x1       // DMA request on rising edge.
	PORT_PCR4_IRQC_0010 = 0x2       // DMA request on falling edge.
	PORT_PCR4_IRQC_0011 = 0x3       // DMA request on either edge.
	PORT_PCR4_IRQC_1000 = 0x8       // Interrupt when logic 0.
	PORT_PCR4_IRQC_1001 = 0x9       // Interrupt on rising-edge.
	PORT_PCR4_IRQC_1010 = 0xa       // Interrupt on falling-edge.
	PORT_PCR4_IRQC_1011 = 0xb       // Interrupt on either edge.
	PORT_PCR4_IRQC_1100 = 0xc       // Interrupt when logic 1.
	PORT_PCR4_ISF_Pos   = 0x18      // Position of ISF field.
	PORT_PCR4_ISF_Msk   = 0x1000000 // Bit mask of ISF field.
	PORT_PCR4_ISF       = 0x1000000 // Bit ISF.
	PORT_PCR4_ISF_0     = 0x0       // Configured interrupt is not detected.
	PORT_PCR4_ISF_1     = 0x1       // Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

	// PCR5: Pin Control Register n
	PORT_PCR5_PS_Pos    = 0x0       // Position of PS field.
	PORT_PCR5_PS_Msk    = 0x1       // Bit mask of PS field.
	PORT_PCR5_PS        = 0x1       // Bit PS.
	PORT_PCR5_PS_0      = 0x0       // Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR5_PS_1      = 0x1       // Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR5_PE_Pos    = 0x1       // Position of PE field.
	PORT_PCR5_PE_Msk    = 0x2       // Bit mask of PE field.
	PORT_PCR5_PE        = 0x2       // Bit PE.
	PORT_PCR5_PE_0      = 0x0       // Internal pullup or pulldown resistor is not enabled on the corresponding pin.
	PORT_PCR5_PE_1      = 0x1       // Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
	PORT_PCR5_SRE_Pos   = 0x2       // Position of SRE field.
	PORT_PCR5_SRE_Msk   = 0x4       // Bit mask of SRE field.
	PORT_PCR5_SRE       = 0x4       // Bit SRE.
	PORT_PCR5_SRE_0     = 0x0       // Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR5_SRE_1     = 0x1       // Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR5_PFE_Pos   = 0x4       // Position of PFE field.
	PORT_PCR5_PFE_Msk   = 0x10      // Bit mask of PFE field.
	PORT_PCR5_PFE       = 0x10      // Bit PFE.
	PORT_PCR5_PFE_0     = 0x0       // Passive input filter is disabled on the corresponding pin.
	PORT_PCR5_PFE_1     = 0x1       // Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
	PORT_PCR5_ODE_Pos   = 0x5       // Position of ODE field.
	PORT_PCR5_ODE_Msk   = 0x20      // Bit mask of ODE field.
	PORT_PCR5_ODE       = 0x20      // Bit ODE.
	PORT_PCR5_ODE_0     = 0x0       // Open drain output is disabled on the corresponding pin.
	PORT_PCR5_ODE_1     = 0x1       // Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR5_DSE_Pos   = 0x6       // Position of DSE field.
	PORT_PCR5_DSE_Msk   = 0x40      // Bit mask of DSE field.
	PORT_PCR5_DSE       = 0x40      // Bit DSE.
	PORT_PCR5_DSE_0     = 0x0       // Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR5_DSE_1     = 0x1       // High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR5_MUX_Pos   = 0x8       // Position of MUX field.
	PORT_PCR5_MUX_Msk   = 0x700     // Bit mask of MUX field.
	PORT_PCR5_MUX_000   = 0x0       // Pin disabled (analog).
	PORT_PCR5_MUX_001   = 0x1       // Alternative 1 (GPIO).
	PORT_PCR5_MUX_010   = 0x2       // Alternative 2 (chip-specific).
	PORT_PCR5_MUX_011   = 0x3       // Alternative 3 (chip-specific).
	PORT_PCR5_MUX_100   = 0x4       // Alternative 4 (chip-specific).
	PORT_PCR5_MUX_101   = 0x5       // Alternative 5 (chip-specific).
	PORT_PCR5_MUX_110   = 0x6       // Alternative 6 (chip-specific).
	PORT_PCR5_MUX_111   = 0x7       // Alternative 7 (chip-specific).
	PORT_PCR5_LK_Pos    = 0xf       // Position of LK field.
	PORT_PCR5_LK_Msk    = 0x8000    // Bit mask of LK field.
	PORT_PCR5_LK        = 0x8000    // Bit LK.
	PORT_PCR5_LK_0      = 0x0       // Pin Control Register fields [15:0] are not locked.
	PORT_PCR5_LK_1      = 0x1       // Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
	PORT_PCR5_IRQC_Pos  = 0x10      // Position of IRQC field.
	PORT_PCR5_IRQC_Msk  = 0xf0000   // Bit mask of IRQC field.
	PORT_PCR5_IRQC_0000 = 0x0       // Interrupt/DMA request disabled.
	PORT_PCR5_IRQC_0001 = 0x1       // DMA request on rising edge.
	PORT_PCR5_IRQC_0010 = 0x2       // DMA request on falling edge.
	PORT_PCR5_IRQC_0011 = 0x3       // DMA request on either edge.
	PORT_PCR5_IRQC_1000 = 0x8       // Interrupt when logic 0.
	PORT_PCR5_IRQC_1001 = 0x9       // Interrupt on rising-edge.
	PORT_PCR5_IRQC_1010 = 0xa       // Interrupt on falling-edge.
	PORT_PCR5_IRQC_1011 = 0xb       // Interrupt on either edge.
	PORT_PCR5_IRQC_1100 = 0xc       // Interrupt when logic 1.
	PORT_PCR5_ISF_Pos   = 0x18      // Position of ISF field.
	PORT_PCR5_ISF_Msk   = 0x1000000 // Bit mask of ISF field.
	PORT_PCR5_ISF       = 0x1000000 // Bit ISF.
	PORT_PCR5_ISF_0     = 0x0       // Configured interrupt is not detected.
	PORT_PCR5_ISF_1     = 0x1       // Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

	// PCR6: Pin Control Register n
	PORT_PCR6_PS_Pos    = 0x0       // Position of PS field.
	PORT_PCR6_PS_Msk    = 0x1       // Bit mask of PS field.
	PORT_PCR6_PS        = 0x1       // Bit PS.
	PORT_PCR6_PS_0      = 0x0       // Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR6_PS_1      = 0x1       // Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR6_PE_Pos    = 0x1       // Position of PE field.
	PORT_PCR6_PE_Msk    = 0x2       // Bit mask of PE field.
	PORT_PCR6_PE        = 0x2       // Bit PE.
	PORT_PCR6_PE_0      = 0x0       // Internal pullup or pulldown resistor is not enabled on the corresponding pin.
	PORT_PCR6_PE_1      = 0x1       // Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
	PORT_PCR6_SRE_Pos   = 0x2       // Position of SRE field.
	PORT_PCR6_SRE_Msk   = 0x4       // Bit mask of SRE field.
	PORT_PCR6_SRE       = 0x4       // Bit SRE.
	PORT_PCR6_SRE_0     = 0x0       // Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR6_SRE_1     = 0x1       // Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR6_PFE_Pos   = 0x4       // Position of PFE field.
	PORT_PCR6_PFE_Msk   = 0x10      // Bit mask of PFE field.
	PORT_PCR6_PFE       = 0x10      // Bit PFE.
	PORT_PCR6_PFE_0     = 0x0       // Passive input filter is disabled on the corresponding pin.
	PORT_PCR6_PFE_1     = 0x1       // Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
	PORT_PCR6_ODE_Pos   = 0x5       // Position of ODE field.
	PORT_PCR6_ODE_Msk   = 0x20      // Bit mask of ODE field.
	PORT_PCR6_ODE       = 0x20      // Bit ODE.
	PORT_PCR6_ODE_0     = 0x0       // Open drain output is disabled on the corresponding pin.
	PORT_PCR6_ODE_1     = 0x1       // Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR6_DSE_Pos   = 0x6       // Position of DSE field.
	PORT_PCR6_DSE_Msk   = 0x40      // Bit mask of DSE field.
	PORT_PCR6_DSE       = 0x40      // Bit DSE.
	PORT_PCR6_DSE_0     = 0x0       // Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR6_DSE_1     = 0x1       // High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR6_MUX_Pos   = 0x8       // Position of MUX field.
	PORT_PCR6_MUX_Msk   = 0x700     // Bit mask of MUX field.
	PORT_PCR6_MUX_000   = 0x0       // Pin disabled (analog).
	PORT_PCR6_MUX_001   = 0x1       // Alternative 1 (GPIO).
	PORT_PCR6_MUX_010   = 0x2       // Alternative 2 (chip-specific).
	PORT_PCR6_MUX_011   = 0x3       // Alternative 3 (chip-specific).
	PORT_PCR6_MUX_100   = 0x4       // Alternative 4 (chip-specific).
	PORT_PCR6_MUX_101   = 0x5       // Alternative 5 (chip-specific).
	PORT_PCR6_MUX_110   = 0x6       // Alternative 6 (chip-specific).
	PORT_PCR6_MUX_111   = 0x7       // Alternative 7 (chip-specific).
	PORT_PCR6_LK_Pos    = 0xf       // Position of LK field.
	PORT_PCR6_LK_Msk    = 0x8000    // Bit mask of LK field.
	PORT_PCR6_LK        = 0x8000    // Bit LK.
	PORT_PCR6_LK_0      = 0x0       // Pin Control Register fields [15:0] are not locked.
	PORT_PCR6_LK_1      = 0x1       // Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
	PORT_PCR6_IRQC_Pos  = 0x10      // Position of IRQC field.
	PORT_PCR6_IRQC_Msk  = 0xf0000   // Bit mask of IRQC field.
	PORT_PCR6_IRQC_0000 = 0x0       // Interrupt/DMA request disabled.
	PORT_PCR6_IRQC_0001 = 0x1       // DMA request on rising edge.
	PORT_PCR6_IRQC_0010 = 0x2       // DMA request on falling edge.
	PORT_PCR6_IRQC_0011 = 0x3       // DMA request on either edge.
	PORT_PCR6_IRQC_1000 = 0x8       // Interrupt when logic 0.
	PORT_PCR6_IRQC_1001 = 0x9       // Interrupt on rising-edge.
	PORT_PCR6_IRQC_1010 = 0xa       // Interrupt on falling-edge.
	PORT_PCR6_IRQC_1011 = 0xb       // Interrupt on either edge.
	PORT_PCR6_IRQC_1100 = 0xc       // Interrupt when logic 1.
	PORT_PCR6_ISF_Pos   = 0x18      // Position of ISF field.
	PORT_PCR6_ISF_Msk   = 0x1000000 // Bit mask of ISF field.
	PORT_PCR6_ISF       = 0x1000000 // Bit ISF.
	PORT_PCR6_ISF_0     = 0x0       // Configured interrupt is not detected.
	PORT_PCR6_ISF_1     = 0x1       // Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

	// PCR7: Pin Control Register n
	PORT_PCR7_PS_Pos    = 0x0       // Position of PS field.
	PORT_PCR7_PS_Msk    = 0x1       // Bit mask of PS field.
	PORT_PCR7_PS        = 0x1       // Bit PS.
	PORT_PCR7_PS_0      = 0x0       // Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR7_PS_1      = 0x1       // Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR7_PE_Pos    = 0x1       // Position of PE field.
	PORT_PCR7_PE_Msk    = 0x2       // Bit mask of PE field.
	PORT_PCR7_PE        = 0x2       // Bit PE.
	PORT_PCR7_PE_0      = 0x0       // Internal pullup or pulldown resistor is not enabled on the corresponding pin.
	PORT_PCR7_PE_1      = 0x1       // Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
	PORT_PCR7_SRE_Pos   = 0x2       // Position of SRE field.
	PORT_PCR7_SRE_Msk   = 0x4       // Bit mask of SRE field.
	PORT_PCR7_SRE       = 0x4       // Bit SRE.
	PORT_PCR7_SRE_0     = 0x0       // Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR7_SRE_1     = 0x1       // Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR7_PFE_Pos   = 0x4       // Position of PFE field.
	PORT_PCR7_PFE_Msk   = 0x10      // Bit mask of PFE field.
	PORT_PCR7_PFE       = 0x10      // Bit PFE.
	PORT_PCR7_PFE_0     = 0x0       // Passive input filter is disabled on the corresponding pin.
	PORT_PCR7_PFE_1     = 0x1       // Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
	PORT_PCR7_ODE_Pos   = 0x5       // Position of ODE field.
	PORT_PCR7_ODE_Msk   = 0x20      // Bit mask of ODE field.
	PORT_PCR7_ODE       = 0x20      // Bit ODE.
	PORT_PCR7_ODE_0     = 0x0       // Open drain output is disabled on the corresponding pin.
	PORT_PCR7_ODE_1     = 0x1       // Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR7_DSE_Pos   = 0x6       // Position of DSE field.
	PORT_PCR7_DSE_Msk   = 0x40      // Bit mask of DSE field.
	PORT_PCR7_DSE       = 0x40      // Bit DSE.
	PORT_PCR7_DSE_0     = 0x0       // Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR7_DSE_1     = 0x1       // High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR7_MUX_Pos   = 0x8       // Position of MUX field.
	PORT_PCR7_MUX_Msk   = 0x700     // Bit mask of MUX field.
	PORT_PCR7_MUX_000   = 0x0       // Pin disabled (analog).
	PORT_PCR7_MUX_001   = 0x1       // Alternative 1 (GPIO).
	PORT_PCR7_MUX_010   = 0x2       // Alternative 2 (chip-specific).
	PORT_PCR7_MUX_011   = 0x3       // Alternative 3 (chip-specific).
	PORT_PCR7_MUX_100   = 0x4       // Alternative 4 (chip-specific).
	PORT_PCR7_MUX_101   = 0x5       // Alternative 5 (chip-specific).
	PORT_PCR7_MUX_110   = 0x6       // Alternative 6 (chip-specific).
	PORT_PCR7_MUX_111   = 0x7       // Alternative 7 (chip-specific).
	PORT_PCR7_LK_Pos    = 0xf       // Position of LK field.
	PORT_PCR7_LK_Msk    = 0x8000    // Bit mask of LK field.
	PORT_PCR7_LK        = 0x8000    // Bit LK.
	PORT_PCR7_LK_0      = 0x0       // Pin Control Register fields [15:0] are not locked.
	PORT_PCR7_LK_1      = 0x1       // Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
	PORT_PCR7_IRQC_Pos  = 0x10      // Position of IRQC field.
	PORT_PCR7_IRQC_Msk  = 0xf0000   // Bit mask of IRQC field.
	PORT_PCR7_IRQC_0000 = 0x0       // Interrupt/DMA request disabled.
	PORT_PCR7_IRQC_0001 = 0x1       // DMA request on rising edge.
	PORT_PCR7_IRQC_0010 = 0x2       // DMA request on falling edge.
	PORT_PCR7_IRQC_0011 = 0x3       // DMA request on either edge.
	PORT_PCR7_IRQC_1000 = 0x8       // Interrupt when logic 0.
	PORT_PCR7_IRQC_1001 = 0x9       // Interrupt on rising-edge.
	PORT_PCR7_IRQC_1010 = 0xa       // Interrupt on falling-edge.
	PORT_PCR7_IRQC_1011 = 0xb       // Interrupt on either edge.
	PORT_PCR7_IRQC_1100 = 0xc       // Interrupt when logic 1.
	PORT_PCR7_ISF_Pos   = 0x18      // Position of ISF field.
	PORT_PCR7_ISF_Msk   = 0x1000000 // Bit mask of ISF field.
	PORT_PCR7_ISF       = 0x1000000 // Bit ISF.
	PORT_PCR7_ISF_0     = 0x0       // Configured interrupt is not detected.
	PORT_PCR7_ISF_1     = 0x1       // Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

	// PCR8: Pin Control Register n
	PORT_PCR8_PS_Pos    = 0x0       // Position of PS field.
	PORT_PCR8_PS_Msk    = 0x1       // Bit mask of PS field.
	PORT_PCR8_PS        = 0x1       // Bit PS.
	PORT_PCR8_PS_0      = 0x0       // Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR8_PS_1      = 0x1       // Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR8_PE_Pos    = 0x1       // Position of PE field.
	PORT_PCR8_PE_Msk    = 0x2       // Bit mask of PE field.
	PORT_PCR8_PE        = 0x2       // Bit PE.
	PORT_PCR8_PE_0      = 0x0       // Internal pullup or pulldown resistor is not enabled on the corresponding pin.
	PORT_PCR8_PE_1      = 0x1       // Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
	PORT_PCR8_SRE_Pos   = 0x2       // Position of SRE field.
	PORT_PCR8_SRE_Msk   = 0x4       // Bit mask of SRE field.
	PORT_PCR8_SRE       = 0x4       // Bit SRE.
	PORT_PCR8_SRE_0     = 0x0       // Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR8_SRE_1     = 0x1       // Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR8_PFE_Pos   = 0x4       // Position of PFE field.
	PORT_PCR8_PFE_Msk   = 0x10      // Bit mask of PFE field.
	PORT_PCR8_PFE       = 0x10      // Bit PFE.
	PORT_PCR8_PFE_0     = 0x0       // Passive input filter is disabled on the corresponding pin.
	PORT_PCR8_PFE_1     = 0x1       // Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
	PORT_PCR8_ODE_Pos   = 0x5       // Position of ODE field.
	PORT_PCR8_ODE_Msk   = 0x20      // Bit mask of ODE field.
	PORT_PCR8_ODE       = 0x20      // Bit ODE.
	PORT_PCR8_ODE_0     = 0x0       // Open drain output is disabled on the corresponding pin.
	PORT_PCR8_ODE_1     = 0x1       // Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR8_DSE_Pos   = 0x6       // Position of DSE field.
	PORT_PCR8_DSE_Msk   = 0x40      // Bit mask of DSE field.
	PORT_PCR8_DSE       = 0x40      // Bit DSE.
	PORT_PCR8_DSE_0     = 0x0       // Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR8_DSE_1     = 0x1       // High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR8_MUX_Pos   = 0x8       // Position of MUX field.
	PORT_PCR8_MUX_Msk   = 0x700     // Bit mask of MUX field.
	PORT_PCR8_MUX_000   = 0x0       // Pin disabled (analog).
	PORT_PCR8_MUX_001   = 0x1       // Alternative 1 (GPIO).
	PORT_PCR8_MUX_010   = 0x2       // Alternative 2 (chip-specific).
	PORT_PCR8_MUX_011   = 0x3       // Alternative 3 (chip-specific).
	PORT_PCR8_MUX_100   = 0x4       // Alternative 4 (chip-specific).
	PORT_PCR8_MUX_101   = 0x5       // Alternative 5 (chip-specific).
	PORT_PCR8_MUX_110   = 0x6       // Alternative 6 (chip-specific).
	PORT_PCR8_MUX_111   = 0x7       // Alternative 7 (chip-specific).
	PORT_PCR8_LK_Pos    = 0xf       // Position of LK field.
	PORT_PCR8_LK_Msk    = 0x8000    // Bit mask of LK field.
	PORT_PCR8_LK        = 0x8000    // Bit LK.
	PORT_PCR8_LK_0      = 0x0       // Pin Control Register fields [15:0] are not locked.
	PORT_PCR8_LK_1      = 0x1       // Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
	PORT_PCR8_IRQC_Pos  = 0x10      // Position of IRQC field.
	PORT_PCR8_IRQC_Msk  = 0xf0000   // Bit mask of IRQC field.
	PORT_PCR8_IRQC_0000 = 0x0       // Interrupt/DMA request disabled.
	PORT_PCR8_IRQC_0001 = 0x1       // DMA request on rising edge.
	PORT_PCR8_IRQC_0010 = 0x2       // DMA request on falling edge.
	PORT_PCR8_IRQC_0011 = 0x3       // DMA request on either edge.
	PORT_PCR8_IRQC_1000 = 0x8       // Interrupt when logic 0.
	PORT_PCR8_IRQC_1001 = 0x9       // Interrupt on rising-edge.
	PORT_PCR8_IRQC_1010 = 0xa       // Interrupt on falling-edge.
	PORT_PCR8_IRQC_1011 = 0xb       // Interrupt on either edge.
	PORT_PCR8_IRQC_1100 = 0xc       // Interrupt when logic 1.
	PORT_PCR8_ISF_Pos   = 0x18      // Position of ISF field.
	PORT_PCR8_ISF_Msk   = 0x1000000 // Bit mask of ISF field.
	PORT_PCR8_ISF       = 0x1000000 // Bit ISF.
	PORT_PCR8_ISF_0     = 0x0       // Configured interrupt is not detected.
	PORT_PCR8_ISF_1     = 0x1       // Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

	// PCR9: Pin Control Register n
	PORT_PCR9_PS_Pos    = 0x0       // Position of PS field.
	PORT_PCR9_PS_Msk    = 0x1       // Bit mask of PS field.
	PORT_PCR9_PS        = 0x1       // Bit PS.
	PORT_PCR9_PS_0      = 0x0       // Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR9_PS_1      = 0x1       // Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR9_PE_Pos    = 0x1       // Position of PE field.
	PORT_PCR9_PE_Msk    = 0x2       // Bit mask of PE field.
	PORT_PCR9_PE        = 0x2       // Bit PE.
	PORT_PCR9_PE_0      = 0x0       // Internal pullup or pulldown resistor is not enabled on the corresponding pin.
	PORT_PCR9_PE_1      = 0x1       // Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
	PORT_PCR9_SRE_Pos   = 0x2       // Position of SRE field.
	PORT_PCR9_SRE_Msk   = 0x4       // Bit mask of SRE field.
	PORT_PCR9_SRE       = 0x4       // Bit SRE.
	PORT_PCR9_SRE_0     = 0x0       // Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR9_SRE_1     = 0x1       // Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR9_PFE_Pos   = 0x4       // Position of PFE field.
	PORT_PCR9_PFE_Msk   = 0x10      // Bit mask of PFE field.
	PORT_PCR9_PFE       = 0x10      // Bit PFE.
	PORT_PCR9_PFE_0     = 0x0       // Passive input filter is disabled on the corresponding pin.
	PORT_PCR9_PFE_1     = 0x1       // Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
	PORT_PCR9_ODE_Pos   = 0x5       // Position of ODE field.
	PORT_PCR9_ODE_Msk   = 0x20      // Bit mask of ODE field.
	PORT_PCR9_ODE       = 0x20      // Bit ODE.
	PORT_PCR9_ODE_0     = 0x0       // Open drain output is disabled on the corresponding pin.
	PORT_PCR9_ODE_1     = 0x1       // Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR9_DSE_Pos   = 0x6       // Position of DSE field.
	PORT_PCR9_DSE_Msk   = 0x40      // Bit mask of DSE field.
	PORT_PCR9_DSE       = 0x40      // Bit DSE.
	PORT_PCR9_DSE_0     = 0x0       // Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR9_DSE_1     = 0x1       // High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR9_MUX_Pos   = 0x8       // Position of MUX field.
	PORT_PCR9_MUX_Msk   = 0x700     // Bit mask of MUX field.
	PORT_PCR9_MUX_000   = 0x0       // Pin disabled (analog).
	PORT_PCR9_MUX_001   = 0x1       // Alternative 1 (GPIO).
	PORT_PCR9_MUX_010   = 0x2       // Alternative 2 (chip-specific).
	PORT_PCR9_MUX_011   = 0x3       // Alternative 3 (chip-specific).
	PORT_PCR9_MUX_100   = 0x4       // Alternative 4 (chip-specific).
	PORT_PCR9_MUX_101   = 0x5       // Alternative 5 (chip-specific).
	PORT_PCR9_MUX_110   = 0x6       // Alternative 6 (chip-specific).
	PORT_PCR9_MUX_111   = 0x7       // Alternative 7 (chip-specific).
	PORT_PCR9_LK_Pos    = 0xf       // Position of LK field.
	PORT_PCR9_LK_Msk    = 0x8000    // Bit mask of LK field.
	PORT_PCR9_LK        = 0x8000    // Bit LK.
	PORT_PCR9_LK_0      = 0x0       // Pin Control Register fields [15:0] are not locked.
	PORT_PCR9_LK_1      = 0x1       // Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
	PORT_PCR9_IRQC_Pos  = 0x10      // Position of IRQC field.
	PORT_PCR9_IRQC_Msk  = 0xf0000   // Bit mask of IRQC field.
	PORT_PCR9_IRQC_0000 = 0x0       // Interrupt/DMA request disabled.
	PORT_PCR9_IRQC_0001 = 0x1       // DMA request on rising edge.
	PORT_PCR9_IRQC_0010 = 0x2       // DMA request on falling edge.
	PORT_PCR9_IRQC_0011 = 0x3       // DMA request on either edge.
	PORT_PCR9_IRQC_1000 = 0x8       // Interrupt when logic 0.
	PORT_PCR9_IRQC_1001 = 0x9       // Interrupt on rising-edge.
	PORT_PCR9_IRQC_1010 = 0xa       // Interrupt on falling-edge.
	PORT_PCR9_IRQC_1011 = 0xb       // Interrupt on either edge.
	PORT_PCR9_IRQC_1100 = 0xc       // Interrupt when logic 1.
	PORT_PCR9_ISF_Pos   = 0x18      // Position of ISF field.
	PORT_PCR9_ISF_Msk   = 0x1000000 // Bit mask of ISF field.
	PORT_PCR9_ISF       = 0x1000000 // Bit ISF.
	PORT_PCR9_ISF_0     = 0x0       // Configured interrupt is not detected.
	PORT_PCR9_ISF_1     = 0x1       // Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

	// PCR10: Pin Control Register n
	PORT_PCR10_PS_Pos    = 0x0       // Position of PS field.
	PORT_PCR10_PS_Msk    = 0x1       // Bit mask of PS field.
	PORT_PCR10_PS        = 0x1       // Bit PS.
	PORT_PCR10_PS_0      = 0x0       // Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR10_PS_1      = 0x1       // Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR10_PE_Pos    = 0x1       // Position of PE field.
	PORT_PCR10_PE_Msk    = 0x2       // Bit mask of PE field.
	PORT_PCR10_PE        = 0x2       // Bit PE.
	PORT_PCR10_PE_0      = 0x0       // Internal pullup or pulldown resistor is not enabled on the corresponding pin.
	PORT_PCR10_PE_1      = 0x1       // Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
	PORT_PCR10_SRE_Pos   = 0x2       // Position of SRE field.
	PORT_PCR10_SRE_Msk   = 0x4       // Bit mask of SRE field.
	PORT_PCR10_SRE       = 0x4       // Bit SRE.
	PORT_PCR10_SRE_0     = 0x0       // Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR10_SRE_1     = 0x1       // Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR10_PFE_Pos   = 0x4       // Position of PFE field.
	PORT_PCR10_PFE_Msk   = 0x10      // Bit mask of PFE field.
	PORT_PCR10_PFE       = 0x10      // Bit PFE.
	PORT_PCR10_PFE_0     = 0x0       // Passive input filter is disabled on the corresponding pin.
	PORT_PCR10_PFE_1     = 0x1       // Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
	PORT_PCR10_ODE_Pos   = 0x5       // Position of ODE field.
	PORT_PCR10_ODE_Msk   = 0x20      // Bit mask of ODE field.
	PORT_PCR10_ODE       = 0x20      // Bit ODE.
	PORT_PCR10_ODE_0     = 0x0       // Open drain output is disabled on the corresponding pin.
	PORT_PCR10_ODE_1     = 0x1       // Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR10_DSE_Pos   = 0x6       // Position of DSE field.
	PORT_PCR10_DSE_Msk   = 0x40      // Bit mask of DSE field.
	PORT_PCR10_DSE       = 0x40      // Bit DSE.
	PORT_PCR10_DSE_0     = 0x0       // Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR10_DSE_1     = 0x1       // High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR10_MUX_Pos   = 0x8       // Position of MUX field.
	PORT_PCR10_MUX_Msk   = 0x700     // Bit mask of MUX field.
	PORT_PCR10_MUX_000   = 0x0       // Pin disabled (analog).
	PORT_PCR10_MUX_001   = 0x1       // Alternative 1 (GPIO).
	PORT_PCR10_MUX_010   = 0x2       // Alternative 2 (chip-specific).
	PORT_PCR10_MUX_011   = 0x3       // Alternative 3 (chip-specific).
	PORT_PCR10_MUX_100   = 0x4       // Alternative 4 (chip-specific).
	PORT_PCR10_MUX_101   = 0x5       // Alternative 5 (chip-specific).
	PORT_PCR10_MUX_110   = 0x6       // Alternative 6 (chip-specific).
	PORT_PCR10_MUX_111   = 0x7       // Alternative 7 (chip-specific).
	PORT_PCR10_LK_Pos    = 0xf       // Position of LK field.
	PORT_PCR10_LK_Msk    = 0x8000    // Bit mask of LK field.
	PORT_PCR10_LK        = 0x8000    // Bit LK.
	PORT_PCR10_LK_0      = 0x0       // Pin Control Register fields [15:0] are not locked.
	PORT_PCR10_LK_1      = 0x1       // Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
	PORT_PCR10_IRQC_Pos  = 0x10      // Position of IRQC field.
	PORT_PCR10_IRQC_Msk  = 0xf0000   // Bit mask of IRQC field.
	PORT_PCR10_IRQC_0000 = 0x0       // Interrupt/DMA request disabled.
	PORT_PCR10_IRQC_0001 = 0x1       // DMA request on rising edge.
	PORT_PCR10_IRQC_0010 = 0x2       // DMA request on falling edge.
	PORT_PCR10_IRQC_0011 = 0x3       // DMA request on either edge.
	PORT_PCR10_IRQC_1000 = 0x8       // Interrupt when logic 0.
	PORT_PCR10_IRQC_1001 = 0x9       // Interrupt on rising-edge.
	PORT_PCR10_IRQC_1010 = 0xa       // Interrupt on falling-edge.
	PORT_PCR10_IRQC_1011 = 0xb       // Interrupt on either edge.
	PORT_PCR10_IRQC_1100 = 0xc       // Interrupt when logic 1.
	PORT_PCR10_ISF_Pos   = 0x18      // Position of ISF field.
	PORT_PCR10_ISF_Msk   = 0x1000000 // Bit mask of ISF field.
	PORT_PCR10_ISF       = 0x1000000 // Bit ISF.
	PORT_PCR10_ISF_0     = 0x0       // Configured interrupt is not detected.
	PORT_PCR10_ISF_1     = 0x1       // Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

	// PCR11: Pin Control Register n
	PORT_PCR11_PS_Pos    = 0x0       // Position of PS field.
	PORT_PCR11_PS_Msk    = 0x1       // Bit mask of PS field.
	PORT_PCR11_PS        = 0x1       // Bit PS.
	PORT_PCR11_PS_0      = 0x0       // Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR11_PS_1      = 0x1       // Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR11_PE_Pos    = 0x1       // Position of PE field.
	PORT_PCR11_PE_Msk    = 0x2       // Bit mask of PE field.
	PORT_PCR11_PE        = 0x2       // Bit PE.
	PORT_PCR11_PE_0      = 0x0       // Internal pullup or pulldown resistor is not enabled on the corresponding pin.
	PORT_PCR11_PE_1      = 0x1       // Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
	PORT_PCR11_SRE_Pos   = 0x2       // Position of SRE field.
	PORT_PCR11_SRE_Msk   = 0x4       // Bit mask of SRE field.
	PORT_PCR11_SRE       = 0x4       // Bit SRE.
	PORT_PCR11_SRE_0     = 0x0       // Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR11_SRE_1     = 0x1       // Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR11_PFE_Pos   = 0x4       // Position of PFE field.
	PORT_PCR11_PFE_Msk   = 0x10      // Bit mask of PFE field.
	PORT_PCR11_PFE       = 0x10      // Bit PFE.
	PORT_PCR11_PFE_0     = 0x0       // Passive input filter is disabled on the corresponding pin.
	PORT_PCR11_PFE_1     = 0x1       // Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
	PORT_PCR11_ODE_Pos   = 0x5       // Position of ODE field.
	PORT_PCR11_ODE_Msk   = 0x20      // Bit mask of ODE field.
	PORT_PCR11_ODE       = 0x20      // Bit ODE.
	PORT_PCR11_ODE_0     = 0x0       // Open drain output is disabled on the corresponding pin.
	PORT_PCR11_ODE_1     = 0x1       // Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR11_DSE_Pos   = 0x6       // Position of DSE field.
	PORT_PCR11_DSE_Msk   = 0x40      // Bit mask of DSE field.
	PORT_PCR11_DSE       = 0x40      // Bit DSE.
	PORT_PCR11_DSE_0     = 0x0       // Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR11_DSE_1     = 0x1       // High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR11_MUX_Pos   = 0x8       // Position of MUX field.
	PORT_PCR11_MUX_Msk   = 0x700     // Bit mask of MUX field.
	PORT_PCR11_MUX_000   = 0x0       // Pin disabled (analog).
	PORT_PCR11_MUX_001   = 0x1       // Alternative 1 (GPIO).
	PORT_PCR11_MUX_010   = 0x2       // Alternative 2 (chip-specific).
	PORT_PCR11_MUX_011   = 0x3       // Alternative 3 (chip-specific).
	PORT_PCR11_MUX_100   = 0x4       // Alternative 4 (chip-specific).
	PORT_PCR11_MUX_101   = 0x5       // Alternative 5 (chip-specific).
	PORT_PCR11_MUX_110   = 0x6       // Alternative 6 (chip-specific).
	PORT_PCR11_MUX_111   = 0x7       // Alternative 7 (chip-specific).
	PORT_PCR11_LK_Pos    = 0xf       // Position of LK field.
	PORT_PCR11_LK_Msk    = 0x8000    // Bit mask of LK field.
	PORT_PCR11_LK        = 0x8000    // Bit LK.
	PORT_PCR11_LK_0      = 0x0       // Pin Control Register fields [15:0] are not locked.
	PORT_PCR11_LK_1      = 0x1       // Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
	PORT_PCR11_IRQC_Pos  = 0x10      // Position of IRQC field.
	PORT_PCR11_IRQC_Msk  = 0xf0000   // Bit mask of IRQC field.
	PORT_PCR11_IRQC_0000 = 0x0       // Interrupt/DMA request disabled.
	PORT_PCR11_IRQC_0001 = 0x1       // DMA request on rising edge.
	PORT_PCR11_IRQC_0010 = 0x2       // DMA request on falling edge.
	PORT_PCR11_IRQC_0011 = 0x3       // DMA request on either edge.
	PORT_PCR11_IRQC_1000 = 0x8       // Interrupt when logic 0.
	PORT_PCR11_IRQC_1001 = 0x9       // Interrupt on rising-edge.
	PORT_PCR11_IRQC_1010 = 0xa       // Interrupt on falling-edge.
	PORT_PCR11_IRQC_1011 = 0xb       // Interrupt on either edge.
	PORT_PCR11_IRQC_1100 = 0xc       // Interrupt when logic 1.
	PORT_PCR11_ISF_Pos   = 0x18      // Position of ISF field.
	PORT_PCR11_ISF_Msk   = 0x1000000 // Bit mask of ISF field.
	PORT_PCR11_ISF       = 0x1000000 // Bit ISF.
	PORT_PCR11_ISF_0     = 0x0       // Configured interrupt is not detected.
	PORT_PCR11_ISF_1     = 0x1       // Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

	// PCR12: Pin Control Register n
	PORT_PCR12_PS_Pos    = 0x0       // Position of PS field.
	PORT_PCR12_PS_Msk    = 0x1       // Bit mask of PS field.
	PORT_PCR12_PS        = 0x1       // Bit PS.
	PORT_PCR12_PS_0      = 0x0       // Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR12_PS_1      = 0x1       // Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR12_PE_Pos    = 0x1       // Position of PE field.
	PORT_PCR12_PE_Msk    = 0x2       // Bit mask of PE field.
	PORT_PCR12_PE        = 0x2       // Bit PE.
	PORT_PCR12_PE_0      = 0x0       // Internal pullup or pulldown resistor is not enabled on the corresponding pin.
	PORT_PCR12_PE_1      = 0x1       // Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
	PORT_PCR12_SRE_Pos   = 0x2       // Position of SRE field.
	PORT_PCR12_SRE_Msk   = 0x4       // Bit mask of SRE field.
	PORT_PCR12_SRE       = 0x4       // Bit SRE.
	PORT_PCR12_SRE_0     = 0x0       // Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR12_SRE_1     = 0x1       // Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR12_PFE_Pos   = 0x4       // Position of PFE field.
	PORT_PCR12_PFE_Msk   = 0x10      // Bit mask of PFE field.
	PORT_PCR12_PFE       = 0x10      // Bit PFE.
	PORT_PCR12_PFE_0     = 0x0       // Passive input filter is disabled on the corresponding pin.
	PORT_PCR12_PFE_1     = 0x1       // Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
	PORT_PCR12_ODE_Pos   = 0x5       // Position of ODE field.
	PORT_PCR12_ODE_Msk   = 0x20      // Bit mask of ODE field.
	PORT_PCR12_ODE       = 0x20      // Bit ODE.
	PORT_PCR12_ODE_0     = 0x0       // Open drain output is disabled on the corresponding pin.
	PORT_PCR12_ODE_1     = 0x1       // Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR12_DSE_Pos   = 0x6       // Position of DSE field.
	PORT_PCR12_DSE_Msk   = 0x40      // Bit mask of DSE field.
	PORT_PCR12_DSE       = 0x40      // Bit DSE.
	PORT_PCR12_DSE_0     = 0x0       // Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR12_DSE_1     = 0x1       // High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR12_MUX_Pos   = 0x8       // Position of MUX field.
	PORT_PCR12_MUX_Msk   = 0x700     // Bit mask of MUX field.
	PORT_PCR12_MUX_000   = 0x0       // Pin disabled (analog).
	PORT_PCR12_MUX_001   = 0x1       // Alternative 1 (GPIO).
	PORT_PCR12_MUX_010   = 0x2       // Alternative 2 (chip-specific).
	PORT_PCR12_MUX_011   = 0x3       // Alternative 3 (chip-specific).
	PORT_PCR12_MUX_100   = 0x4       // Alternative 4 (chip-specific).
	PORT_PCR12_MUX_101   = 0x5       // Alternative 5 (chip-specific).
	PORT_PCR12_MUX_110   = 0x6       // Alternative 6 (chip-specific).
	PORT_PCR12_MUX_111   = 0x7       // Alternative 7 (chip-specific).
	PORT_PCR12_LK_Pos    = 0xf       // Position of LK field.
	PORT_PCR12_LK_Msk    = 0x8000    // Bit mask of LK field.
	PORT_PCR12_LK        = 0x8000    // Bit LK.
	PORT_PCR12_LK_0      = 0x0       // Pin Control Register fields [15:0] are not locked.
	PORT_PCR12_LK_1      = 0x1       // Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
	PORT_PCR12_IRQC_Pos  = 0x10      // Position of IRQC field.
	PORT_PCR12_IRQC_Msk  = 0xf0000   // Bit mask of IRQC field.
	PORT_PCR12_IRQC_0000 = 0x0       // Interrupt/DMA request disabled.
	PORT_PCR12_IRQC_0001 = 0x1       // DMA request on rising edge.
	PORT_PCR12_IRQC_0010 = 0x2       // DMA request on falling edge.
	PORT_PCR12_IRQC_0011 = 0x3       // DMA request on either edge.
	PORT_PCR12_IRQC_1000 = 0x8       // Interrupt when logic 0.
	PORT_PCR12_IRQC_1001 = 0x9       // Interrupt on rising-edge.
	PORT_PCR12_IRQC_1010 = 0xa       // Interrupt on falling-edge.
	PORT_PCR12_IRQC_1011 = 0xb       // Interrupt on either edge.
	PORT_PCR12_IRQC_1100 = 0xc       // Interrupt when logic 1.
	PORT_PCR12_ISF_Pos   = 0x18      // Position of ISF field.
	PORT_PCR12_ISF_Msk   = 0x1000000 // Bit mask of ISF field.
	PORT_PCR12_ISF       = 0x1000000 // Bit ISF.
	PORT_PCR12_ISF_0     = 0x0       // Configured interrupt is not detected.
	PORT_PCR12_ISF_1     = 0x1       // Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

	// PCR13: Pin Control Register n
	PORT_PCR13_PS_Pos    = 0x0       // Position of PS field.
	PORT_PCR13_PS_Msk    = 0x1       // Bit mask of PS field.
	PORT_PCR13_PS        = 0x1       // Bit PS.
	PORT_PCR13_PS_0      = 0x0       // Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR13_PS_1      = 0x1       // Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR13_PE_Pos    = 0x1       // Position of PE field.
	PORT_PCR13_PE_Msk    = 0x2       // Bit mask of PE field.
	PORT_PCR13_PE        = 0x2       // Bit PE.
	PORT_PCR13_PE_0      = 0x0       // Internal pullup or pulldown resistor is not enabled on the corresponding pin.
	PORT_PCR13_PE_1      = 0x1       // Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
	PORT_PCR13_SRE_Pos   = 0x2       // Position of SRE field.
	PORT_PCR13_SRE_Msk   = 0x4       // Bit mask of SRE field.
	PORT_PCR13_SRE       = 0x4       // Bit SRE.
	PORT_PCR13_SRE_0     = 0x0       // Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR13_SRE_1     = 0x1       // Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR13_PFE_Pos   = 0x4       // Position of PFE field.
	PORT_PCR13_PFE_Msk   = 0x10      // Bit mask of PFE field.
	PORT_PCR13_PFE       = 0x10      // Bit PFE.
	PORT_PCR13_PFE_0     = 0x0       // Passive input filter is disabled on the corresponding pin.
	PORT_PCR13_PFE_1     = 0x1       // Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
	PORT_PCR13_ODE_Pos   = 0x5       // Position of ODE field.
	PORT_PCR13_ODE_Msk   = 0x20      // Bit mask of ODE field.
	PORT_PCR13_ODE       = 0x20      // Bit ODE.
	PORT_PCR13_ODE_0     = 0x0       // Open drain output is disabled on the corresponding pin.
	PORT_PCR13_ODE_1     = 0x1       // Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR13_DSE_Pos   = 0x6       // Position of DSE field.
	PORT_PCR13_DSE_Msk   = 0x40      // Bit mask of DSE field.
	PORT_PCR13_DSE       = 0x40      // Bit DSE.
	PORT_PCR13_DSE_0     = 0x0       // Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR13_DSE_1     = 0x1       // High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR13_MUX_Pos   = 0x8       // Position of MUX field.
	PORT_PCR13_MUX_Msk   = 0x700     // Bit mask of MUX field.
	PORT_PCR13_MUX_000   = 0x0       // Pin disabled (analog).
	PORT_PCR13_MUX_001   = 0x1       // Alternative 1 (GPIO).
	PORT_PCR13_MUX_010   = 0x2       // Alternative 2 (chip-specific).
	PORT_PCR13_MUX_011   = 0x3       // Alternative 3 (chip-specific).
	PORT_PCR13_MUX_100   = 0x4       // Alternative 4 (chip-specific).
	PORT_PCR13_MUX_101   = 0x5       // Alternative 5 (chip-specific).
	PORT_PCR13_MUX_110   = 0x6       // Alternative 6 (chip-specific).
	PORT_PCR13_MUX_111   = 0x7       // Alternative 7 (chip-specific).
	PORT_PCR13_LK_Pos    = 0xf       // Position of LK field.
	PORT_PCR13_LK_Msk    = 0x8000    // Bit mask of LK field.
	PORT_PCR13_LK        = 0x8000    // Bit LK.
	PORT_PCR13_LK_0      = 0x0       // Pin Control Register fields [15:0] are not locked.
	PORT_PCR13_LK_1      = 0x1       // Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
	PORT_PCR13_IRQC_Pos  = 0x10      // Position of IRQC field.
	PORT_PCR13_IRQC_Msk  = 0xf0000   // Bit mask of IRQC field.
	PORT_PCR13_IRQC_0000 = 0x0       // Interrupt/DMA request disabled.
	PORT_PCR13_IRQC_0001 = 0x1       // DMA request on rising edge.
	PORT_PCR13_IRQC_0010 = 0x2       // DMA request on falling edge.
	PORT_PCR13_IRQC_0011 = 0x3       // DMA request on either edge.
	PORT_PCR13_IRQC_1000 = 0x8       // Interrupt when logic 0.
	PORT_PCR13_IRQC_1001 = 0x9       // Interrupt on rising-edge.
	PORT_PCR13_IRQC_1010 = 0xa       // Interrupt on falling-edge.
	PORT_PCR13_IRQC_1011 = 0xb       // Interrupt on either edge.
	PORT_PCR13_IRQC_1100 = 0xc       // Interrupt when logic 1.
	PORT_PCR13_ISF_Pos   = 0x18      // Position of ISF field.
	PORT_PCR13_ISF_Msk   = 0x1000000 // Bit mask of ISF field.
	PORT_PCR13_ISF       = 0x1000000 // Bit ISF.
	PORT_PCR13_ISF_0     = 0x0       // Configured interrupt is not detected.
	PORT_PCR13_ISF_1     = 0x1       // Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

	// PCR14: Pin Control Register n
	PORT_PCR14_PS_Pos    = 0x0       // Position of PS field.
	PORT_PCR14_PS_Msk    = 0x1       // Bit mask of PS field.
	PORT_PCR14_PS        = 0x1       // Bit PS.
	PORT_PCR14_PS_0      = 0x0       // Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR14_PS_1      = 0x1       // Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR14_PE_Pos    = 0x1       // Position of PE field.
	PORT_PCR14_PE_Msk    = 0x2       // Bit mask of PE field.
	PORT_PCR14_PE        = 0x2       // Bit PE.
	PORT_PCR14_PE_0      = 0x0       // Internal pullup or pulldown resistor is not enabled on the corresponding pin.
	PORT_PCR14_PE_1      = 0x1       // Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
	PORT_PCR14_SRE_Pos   = 0x2       // Position of SRE field.
	PORT_PCR14_SRE_Msk   = 0x4       // Bit mask of SRE field.
	PORT_PCR14_SRE       = 0x4       // Bit SRE.
	PORT_PCR14_SRE_0     = 0x0       // Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR14_SRE_1     = 0x1       // Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR14_PFE_Pos   = 0x4       // Position of PFE field.
	PORT_PCR14_PFE_Msk   = 0x10      // Bit mask of PFE field.
	PORT_PCR14_PFE       = 0x10      // Bit PFE.
	PORT_PCR14_PFE_0     = 0x0       // Passive input filter is disabled on the corresponding pin.
	PORT_PCR14_PFE_1     = 0x1       // Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
	PORT_PCR14_ODE_Pos   = 0x5       // Position of ODE field.
	PORT_PCR14_ODE_Msk   = 0x20      // Bit mask of ODE field.
	PORT_PCR14_ODE       = 0x20      // Bit ODE.
	PORT_PCR14_ODE_0     = 0x0       // Open drain output is disabled on the corresponding pin.
	PORT_PCR14_ODE_1     = 0x1       // Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR14_DSE_Pos   = 0x6       // Position of DSE field.
	PORT_PCR14_DSE_Msk   = 0x40      // Bit mask of DSE field.
	PORT_PCR14_DSE       = 0x40      // Bit DSE.
	PORT_PCR14_DSE_0     = 0x0       // Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR14_DSE_1     = 0x1       // High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR14_MUX_Pos   = 0x8       // Position of MUX field.
	PORT_PCR14_MUX_Msk   = 0x700     // Bit mask of MUX field.
	PORT_PCR14_MUX_000   = 0x0       // Pin disabled (analog).
	PORT_PCR14_MUX_001   = 0x1       // Alternative 1 (GPIO).
	PORT_PCR14_MUX_010   = 0x2       // Alternative 2 (chip-specific).
	PORT_PCR14_MUX_011   = 0x3       // Alternative 3 (chip-specific).
	PORT_PCR14_MUX_100   = 0x4       // Alternative 4 (chip-specific).
	PORT_PCR14_MUX_101   = 0x5       // Alternative 5 (chip-specific).
	PORT_PCR14_MUX_110   = 0x6       // Alternative 6 (chip-specific).
	PORT_PCR14_MUX_111   = 0x7       // Alternative 7 (chip-specific).
	PORT_PCR14_LK_Pos    = 0xf       // Position of LK field.
	PORT_PCR14_LK_Msk    = 0x8000    // Bit mask of LK field.
	PORT_PCR14_LK        = 0x8000    // Bit LK.
	PORT_PCR14_LK_0      = 0x0       // Pin Control Register fields [15:0] are not locked.
	PORT_PCR14_LK_1      = 0x1       // Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
	PORT_PCR14_IRQC_Pos  = 0x10      // Position of IRQC field.
	PORT_PCR14_IRQC_Msk  = 0xf0000   // Bit mask of IRQC field.
	PORT_PCR14_IRQC_0000 = 0x0       // Interrupt/DMA request disabled.
	PORT_PCR14_IRQC_0001 = 0x1       // DMA request on rising edge.
	PORT_PCR14_IRQC_0010 = 0x2       // DMA request on falling edge.
	PORT_PCR14_IRQC_0011 = 0x3       // DMA request on either edge.
	PORT_PCR14_IRQC_1000 = 0x8       // Interrupt when logic 0.
	PORT_PCR14_IRQC_1001 = 0x9       // Interrupt on rising-edge.
	PORT_PCR14_IRQC_1010 = 0xa       // Interrupt on falling-edge.
	PORT_PCR14_IRQC_1011 = 0xb       // Interrupt on either edge.
	PORT_PCR14_IRQC_1100 = 0xc       // Interrupt when logic 1.
	PORT_PCR14_ISF_Pos   = 0x18      // Position of ISF field.
	PORT_PCR14_ISF_Msk   = 0x1000000 // Bit mask of ISF field.
	PORT_PCR14_ISF       = 0x1000000 // Bit ISF.
	PORT_PCR14_ISF_0     = 0x0       // Configured interrupt is not detected.
	PORT_PCR14_ISF_1     = 0x1       // Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

	// PCR15: Pin Control Register n
	PORT_PCR15_PS_Pos    = 0x0       // Position of PS field.
	PORT_PCR15_PS_Msk    = 0x1       // Bit mask of PS field.
	PORT_PCR15_PS        = 0x1       // Bit PS.
	PORT_PCR15_PS_0      = 0x0       // Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR15_PS_1      = 0x1       // Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR15_PE_Pos    = 0x1       // Position of PE field.
	PORT_PCR15_PE_Msk    = 0x2       // Bit mask of PE field.
	PORT_PCR15_PE        = 0x2       // Bit PE.
	PORT_PCR15_PE_0      = 0x0       // Internal pullup or pulldown resistor is not enabled on the corresponding pin.
	PORT_PCR15_PE_1      = 0x1       // Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
	PORT_PCR15_SRE_Pos   = 0x2       // Position of SRE field.
	PORT_PCR15_SRE_Msk   = 0x4       // Bit mask of SRE field.
	PORT_PCR15_SRE       = 0x4       // Bit SRE.
	PORT_PCR15_SRE_0     = 0x0       // Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR15_SRE_1     = 0x1       // Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR15_PFE_Pos   = 0x4       // Position of PFE field.
	PORT_PCR15_PFE_Msk   = 0x10      // Bit mask of PFE field.
	PORT_PCR15_PFE       = 0x10      // Bit PFE.
	PORT_PCR15_PFE_0     = 0x0       // Passive input filter is disabled on the corresponding pin.
	PORT_PCR15_PFE_1     = 0x1       // Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
	PORT_PCR15_ODE_Pos   = 0x5       // Position of ODE field.
	PORT_PCR15_ODE_Msk   = 0x20      // Bit mask of ODE field.
	PORT_PCR15_ODE       = 0x20      // Bit ODE.
	PORT_PCR15_ODE_0     = 0x0       // Open drain output is disabled on the corresponding pin.
	PORT_PCR15_ODE_1     = 0x1       // Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR15_DSE_Pos   = 0x6       // Position of DSE field.
	PORT_PCR15_DSE_Msk   = 0x40      // Bit mask of DSE field.
	PORT_PCR15_DSE       = 0x40      // Bit DSE.
	PORT_PCR15_DSE_0     = 0x0       // Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR15_DSE_1     = 0x1       // High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR15_MUX_Pos   = 0x8       // Position of MUX field.
	PORT_PCR15_MUX_Msk   = 0x700     // Bit mask of MUX field.
	PORT_PCR15_MUX_000   = 0x0       // Pin disabled (analog).
	PORT_PCR15_MUX_001   = 0x1       // Alternative 1 (GPIO).
	PORT_PCR15_MUX_010   = 0x2       // Alternative 2 (chip-specific).
	PORT_PCR15_MUX_011   = 0x3       // Alternative 3 (chip-specific).
	PORT_PCR15_MUX_100   = 0x4       // Alternative 4 (chip-specific).
	PORT_PCR15_MUX_101   = 0x5       // Alternative 5 (chip-specific).
	PORT_PCR15_MUX_110   = 0x6       // Alternative 6 (chip-specific).
	PORT_PCR15_MUX_111   = 0x7       // Alternative 7 (chip-specific).
	PORT_PCR15_LK_Pos    = 0xf       // Position of LK field.
	PORT_PCR15_LK_Msk    = 0x8000    // Bit mask of LK field.
	PORT_PCR15_LK        = 0x8000    // Bit LK.
	PORT_PCR15_LK_0      = 0x0       // Pin Control Register fields [15:0] are not locked.
	PORT_PCR15_LK_1      = 0x1       // Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
	PORT_PCR15_IRQC_Pos  = 0x10      // Position of IRQC field.
	PORT_PCR15_IRQC_Msk  = 0xf0000   // Bit mask of IRQC field.
	PORT_PCR15_IRQC_0000 = 0x0       // Interrupt/DMA request disabled.
	PORT_PCR15_IRQC_0001 = 0x1       // DMA request on rising edge.
	PORT_PCR15_IRQC_0010 = 0x2       // DMA request on falling edge.
	PORT_PCR15_IRQC_0011 = 0x3       // DMA request on either edge.
	PORT_PCR15_IRQC_1000 = 0x8       // Interrupt when logic 0.
	PORT_PCR15_IRQC_1001 = 0x9       // Interrupt on rising-edge.
	PORT_PCR15_IRQC_1010 = 0xa       // Interrupt on falling-edge.
	PORT_PCR15_IRQC_1011 = 0xb       // Interrupt on either edge.
	PORT_PCR15_IRQC_1100 = 0xc       // Interrupt when logic 1.
	PORT_PCR15_ISF_Pos   = 0x18      // Position of ISF field.
	PORT_PCR15_ISF_Msk   = 0x1000000 // Bit mask of ISF field.
	PORT_PCR15_ISF       = 0x1000000 // Bit ISF.
	PORT_PCR15_ISF_0     = 0x0       // Configured interrupt is not detected.
	PORT_PCR15_ISF_1     = 0x1       // Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

	// PCR16: Pin Control Register n
	PORT_PCR16_PS_Pos    = 0x0       // Position of PS field.
	PORT_PCR16_PS_Msk    = 0x1       // Bit mask of PS field.
	PORT_PCR16_PS        = 0x1       // Bit PS.
	PORT_PCR16_PS_0      = 0x0       // Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR16_PS_1      = 0x1       // Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR16_PE_Pos    = 0x1       // Position of PE field.
	PORT_PCR16_PE_Msk    = 0x2       // Bit mask of PE field.
	PORT_PCR16_PE        = 0x2       // Bit PE.
	PORT_PCR16_PE_0      = 0x0       // Internal pullup or pulldown resistor is not enabled on the corresponding pin.
	PORT_PCR16_PE_1      = 0x1       // Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
	PORT_PCR16_SRE_Pos   = 0x2       // Position of SRE field.
	PORT_PCR16_SRE_Msk   = 0x4       // Bit mask of SRE field.
	PORT_PCR16_SRE       = 0x4       // Bit SRE.
	PORT_PCR16_SRE_0     = 0x0       // Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR16_SRE_1     = 0x1       // Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR16_PFE_Pos   = 0x4       // Position of PFE field.
	PORT_PCR16_PFE_Msk   = 0x10      // Bit mask of PFE field.
	PORT_PCR16_PFE       = 0x10      // Bit PFE.
	PORT_PCR16_PFE_0     = 0x0       // Passive input filter is disabled on the corresponding pin.
	PORT_PCR16_PFE_1     = 0x1       // Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
	PORT_PCR16_ODE_Pos   = 0x5       // Position of ODE field.
	PORT_PCR16_ODE_Msk   = 0x20      // Bit mask of ODE field.
	PORT_PCR16_ODE       = 0x20      // Bit ODE.
	PORT_PCR16_ODE_0     = 0x0       // Open drain output is disabled on the corresponding pin.
	PORT_PCR16_ODE_1     = 0x1       // Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR16_DSE_Pos   = 0x6       // Position of DSE field.
	PORT_PCR16_DSE_Msk   = 0x40      // Bit mask of DSE field.
	PORT_PCR16_DSE       = 0x40      // Bit DSE.
	PORT_PCR16_DSE_0     = 0x0       // Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR16_DSE_1     = 0x1       // High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR16_MUX_Pos   = 0x8       // Position of MUX field.
	PORT_PCR16_MUX_Msk   = 0x700     // Bit mask of MUX field.
	PORT_PCR16_MUX_000   = 0x0       // Pin disabled (analog).
	PORT_PCR16_MUX_001   = 0x1       // Alternative 1 (GPIO).
	PORT_PCR16_MUX_010   = 0x2       // Alternative 2 (chip-specific).
	PORT_PCR16_MUX_011   = 0x3       // Alternative 3 (chip-specific).
	PORT_PCR16_MUX_100   = 0x4       // Alternative 4 (chip-specific).
	PORT_PCR16_MUX_101   = 0x5       // Alternative 5 (chip-specific).
	PORT_PCR16_MUX_110   = 0x6       // Alternative 6 (chip-specific).
	PORT_PCR16_MUX_111   = 0x7       // Alternative 7 (chip-specific).
	PORT_PCR16_LK_Pos    = 0xf       // Position of LK field.
	PORT_PCR16_LK_Msk    = 0x8000    // Bit mask of LK field.
	PORT_PCR16_LK        = 0x8000    // Bit LK.
	PORT_PCR16_LK_0      = 0x0       // Pin Control Register fields [15:0] are not locked.
	PORT_PCR16_LK_1      = 0x1       // Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
	PORT_PCR16_IRQC_Pos  = 0x10      // Position of IRQC field.
	PORT_PCR16_IRQC_Msk  = 0xf0000   // Bit mask of IRQC field.
	PORT_PCR16_IRQC_0000 = 0x0       // Interrupt/DMA request disabled.
	PORT_PCR16_IRQC_0001 = 0x1       // DMA request on rising edge.
	PORT_PCR16_IRQC_0010 = 0x2       // DMA request on falling edge.
	PORT_PCR16_IRQC_0011 = 0x3       // DMA request on either edge.
	PORT_PCR16_IRQC_1000 = 0x8       // Interrupt when logic 0.
	PORT_PCR16_IRQC_1001 = 0x9       // Interrupt on rising-edge.
	PORT_PCR16_IRQC_1010 = 0xa       // Interrupt on falling-edge.
	PORT_PCR16_IRQC_1011 = 0xb       // Interrupt on either edge.
	PORT_PCR16_IRQC_1100 = 0xc       // Interrupt when logic 1.
	PORT_PCR16_ISF_Pos   = 0x18      // Position of ISF field.
	PORT_PCR16_ISF_Msk   = 0x1000000 // Bit mask of ISF field.
	PORT_PCR16_ISF       = 0x1000000 // Bit ISF.
	PORT_PCR16_ISF_0     = 0x0       // Configured interrupt is not detected.
	PORT_PCR16_ISF_1     = 0x1       // Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

	// PCR17: Pin Control Register n
	PORT_PCR17_PS_Pos    = 0x0       // Position of PS field.
	PORT_PCR17_PS_Msk    = 0x1       // Bit mask of PS field.
	PORT_PCR17_PS        = 0x1       // Bit PS.
	PORT_PCR17_PS_0      = 0x0       // Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR17_PS_1      = 0x1       // Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR17_PE_Pos    = 0x1       // Position of PE field.
	PORT_PCR17_PE_Msk    = 0x2       // Bit mask of PE field.
	PORT_PCR17_PE        = 0x2       // Bit PE.
	PORT_PCR17_PE_0      = 0x0       // Internal pullup or pulldown resistor is not enabled on the corresponding pin.
	PORT_PCR17_PE_1      = 0x1       // Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
	PORT_PCR17_SRE_Pos   = 0x2       // Position of SRE field.
	PORT_PCR17_SRE_Msk   = 0x4       // Bit mask of SRE field.
	PORT_PCR17_SRE       = 0x4       // Bit SRE.
	PORT_PCR17_SRE_0     = 0x0       // Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR17_SRE_1     = 0x1       // Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR17_PFE_Pos   = 0x4       // Position of PFE field.
	PORT_PCR17_PFE_Msk   = 0x10      // Bit mask of PFE field.
	PORT_PCR17_PFE       = 0x10      // Bit PFE.
	PORT_PCR17_PFE_0     = 0x0       // Passive input filter is disabled on the corresponding pin.
	PORT_PCR17_PFE_1     = 0x1       // Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
	PORT_PCR17_ODE_Pos   = 0x5       // Position of ODE field.
	PORT_PCR17_ODE_Msk   = 0x20      // Bit mask of ODE field.
	PORT_PCR17_ODE       = 0x20      // Bit ODE.
	PORT_PCR17_ODE_0     = 0x0       // Open drain output is disabled on the corresponding pin.
	PORT_PCR17_ODE_1     = 0x1       // Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR17_DSE_Pos   = 0x6       // Position of DSE field.
	PORT_PCR17_DSE_Msk   = 0x40      // Bit mask of DSE field.
	PORT_PCR17_DSE       = 0x40      // Bit DSE.
	PORT_PCR17_DSE_0     = 0x0       // Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR17_DSE_1     = 0x1       // High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR17_MUX_Pos   = 0x8       // Position of MUX field.
	PORT_PCR17_MUX_Msk   = 0x700     // Bit mask of MUX field.
	PORT_PCR17_MUX_000   = 0x0       // Pin disabled (analog).
	PORT_PCR17_MUX_001   = 0x1       // Alternative 1 (GPIO).
	PORT_PCR17_MUX_010   = 0x2       // Alternative 2 (chip-specific).
	PORT_PCR17_MUX_011   = 0x3       // Alternative 3 (chip-specific).
	PORT_PCR17_MUX_100   = 0x4       // Alternative 4 (chip-specific).
	PORT_PCR17_MUX_101   = 0x5       // Alternative 5 (chip-specific).
	PORT_PCR17_MUX_110   = 0x6       // Alternative 6 (chip-specific).
	PORT_PCR17_MUX_111   = 0x7       // Alternative 7 (chip-specific).
	PORT_PCR17_LK_Pos    = 0xf       // Position of LK field.
	PORT_PCR17_LK_Msk    = 0x8000    // Bit mask of LK field.
	PORT_PCR17_LK        = 0x8000    // Bit LK.
	PORT_PCR17_LK_0      = 0x0       // Pin Control Register fields [15:0] are not locked.
	PORT_PCR17_LK_1      = 0x1       // Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
	PORT_PCR17_IRQC_Pos  = 0x10      // Position of IRQC field.
	PORT_PCR17_IRQC_Msk  = 0xf0000   // Bit mask of IRQC field.
	PORT_PCR17_IRQC_0000 = 0x0       // Interrupt/DMA request disabled.
	PORT_PCR17_IRQC_0001 = 0x1       // DMA request on rising edge.
	PORT_PCR17_IRQC_0010 = 0x2       // DMA request on falling edge.
	PORT_PCR17_IRQC_0011 = 0x3       // DMA request on either edge.
	PORT_PCR17_IRQC_1000 = 0x8       // Interrupt when logic 0.
	PORT_PCR17_IRQC_1001 = 0x9       // Interrupt on rising-edge.
	PORT_PCR17_IRQC_1010 = 0xa       // Interrupt on falling-edge.
	PORT_PCR17_IRQC_1011 = 0xb       // Interrupt on either edge.
	PORT_PCR17_IRQC_1100 = 0xc       // Interrupt when logic 1.
	PORT_PCR17_ISF_Pos   = 0x18      // Position of ISF field.
	PORT_PCR17_ISF_Msk   = 0x1000000 // Bit mask of ISF field.
	PORT_PCR17_ISF       = 0x1000000 // Bit ISF.
	PORT_PCR17_ISF_0     = 0x0       // Configured interrupt is not detected.
	PORT_PCR17_ISF_1     = 0x1       // Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

	// PCR18: Pin Control Register n
	PORT_PCR18_PS_Pos    = 0x0       // Position of PS field.
	PORT_PCR18_PS_Msk    = 0x1       // Bit mask of PS field.
	PORT_PCR18_PS        = 0x1       // Bit PS.
	PORT_PCR18_PS_0      = 0x0       // Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR18_PS_1      = 0x1       // Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR18_PE_Pos    = 0x1       // Position of PE field.
	PORT_PCR18_PE_Msk    = 0x2       // Bit mask of PE field.
	PORT_PCR18_PE        = 0x2       // Bit PE.
	PORT_PCR18_PE_0      = 0x0       // Internal pullup or pulldown resistor is not enabled on the corresponding pin.
	PORT_PCR18_PE_1      = 0x1       // Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
	PORT_PCR18_SRE_Pos   = 0x2       // Position of SRE field.
	PORT_PCR18_SRE_Msk   = 0x4       // Bit mask of SRE field.
	PORT_PCR18_SRE       = 0x4       // Bit SRE.
	PORT_PCR18_SRE_0     = 0x0       // Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR18_SRE_1     = 0x1       // Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR18_PFE_Pos   = 0x4       // Position of PFE field.
	PORT_PCR18_PFE_Msk   = 0x10      // Bit mask of PFE field.
	PORT_PCR18_PFE       = 0x10      // Bit PFE.
	PORT_PCR18_PFE_0     = 0x0       // Passive input filter is disabled on the corresponding pin.
	PORT_PCR18_PFE_1     = 0x1       // Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
	PORT_PCR18_ODE_Pos   = 0x5       // Position of ODE field.
	PORT_PCR18_ODE_Msk   = 0x20      // Bit mask of ODE field.
	PORT_PCR18_ODE       = 0x20      // Bit ODE.
	PORT_PCR18_ODE_0     = 0x0       // Open drain output is disabled on the corresponding pin.
	PORT_PCR18_ODE_1     = 0x1       // Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR18_DSE_Pos   = 0x6       // Position of DSE field.
	PORT_PCR18_DSE_Msk   = 0x40      // Bit mask of DSE field.
	PORT_PCR18_DSE       = 0x40      // Bit DSE.
	PORT_PCR18_DSE_0     = 0x0       // Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR18_DSE_1     = 0x1       // High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR18_MUX_Pos   = 0x8       // Position of MUX field.
	PORT_PCR18_MUX_Msk   = 0x700     // Bit mask of MUX field.
	PORT_PCR18_MUX_000   = 0x0       // Pin disabled (analog).
	PORT_PCR18_MUX_001   = 0x1       // Alternative 1 (GPIO).
	PORT_PCR18_MUX_010   = 0x2       // Alternative 2 (chip-specific).
	PORT_PCR18_MUX_011   = 0x3       // Alternative 3 (chip-specific).
	PORT_PCR18_MUX_100   = 0x4       // Alternative 4 (chip-specific).
	PORT_PCR18_MUX_101   = 0x5       // Alternative 5 (chip-specific).
	PORT_PCR18_MUX_110   = 0x6       // Alternative 6 (chip-specific).
	PORT_PCR18_MUX_111   = 0x7       // Alternative 7 (chip-specific).
	PORT_PCR18_LK_Pos    = 0xf       // Position of LK field.
	PORT_PCR18_LK_Msk    = 0x8000    // Bit mask of LK field.
	PORT_PCR18_LK        = 0x8000    // Bit LK.
	PORT_PCR18_LK_0      = 0x0       // Pin Control Register fields [15:0] are not locked.
	PORT_PCR18_LK_1      = 0x1       // Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
	PORT_PCR18_IRQC_Pos  = 0x10      // Position of IRQC field.
	PORT_PCR18_IRQC_Msk  = 0xf0000   // Bit mask of IRQC field.
	PORT_PCR18_IRQC_0000 = 0x0       // Interrupt/DMA request disabled.
	PORT_PCR18_IRQC_0001 = 0x1       // DMA request on rising edge.
	PORT_PCR18_IRQC_0010 = 0x2       // DMA request on falling edge.
	PORT_PCR18_IRQC_0011 = 0x3       // DMA request on either edge.
	PORT_PCR18_IRQC_1000 = 0x8       // Interrupt when logic 0.
	PORT_PCR18_IRQC_1001 = 0x9       // Interrupt on rising-edge.
	PORT_PCR18_IRQC_1010 = 0xa       // Interrupt on falling-edge.
	PORT_PCR18_IRQC_1011 = 0xb       // Interrupt on either edge.
	PORT_PCR18_IRQC_1100 = 0xc       // Interrupt when logic 1.
	PORT_PCR18_ISF_Pos   = 0x18      // Position of ISF field.
	PORT_PCR18_ISF_Msk   = 0x1000000 // Bit mask of ISF field.
	PORT_PCR18_ISF       = 0x1000000 // Bit ISF.
	PORT_PCR18_ISF_0     = 0x0       // Configured interrupt is not detected.
	PORT_PCR18_ISF_1     = 0x1       // Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

	// PCR19: Pin Control Register n
	PORT_PCR19_PS_Pos    = 0x0       // Position of PS field.
	PORT_PCR19_PS_Msk    = 0x1       // Bit mask of PS field.
	PORT_PCR19_PS        = 0x1       // Bit PS.
	PORT_PCR19_PS_0      = 0x0       // Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR19_PS_1      = 0x1       // Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR19_PE_Pos    = 0x1       // Position of PE field.
	PORT_PCR19_PE_Msk    = 0x2       // Bit mask of PE field.
	PORT_PCR19_PE        = 0x2       // Bit PE.
	PORT_PCR19_PE_0      = 0x0       // Internal pullup or pulldown resistor is not enabled on the corresponding pin.
	PORT_PCR19_PE_1      = 0x1       // Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
	PORT_PCR19_SRE_Pos   = 0x2       // Position of SRE field.
	PORT_PCR19_SRE_Msk   = 0x4       // Bit mask of SRE field.
	PORT_PCR19_SRE       = 0x4       // Bit SRE.
	PORT_PCR19_SRE_0     = 0x0       // Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR19_SRE_1     = 0x1       // Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR19_PFE_Pos   = 0x4       // Position of PFE field.
	PORT_PCR19_PFE_Msk   = 0x10      // Bit mask of PFE field.
	PORT_PCR19_PFE       = 0x10      // Bit PFE.
	PORT_PCR19_PFE_0     = 0x0       // Passive input filter is disabled on the corresponding pin.
	PORT_PCR19_PFE_1     = 0x1       // Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
	PORT_PCR19_ODE_Pos   = 0x5       // Position of ODE field.
	PORT_PCR19_ODE_Msk   = 0x20      // Bit mask of ODE field.
	PORT_PCR19_ODE       = 0x20      // Bit ODE.
	PORT_PCR19_ODE_0     = 0x0       // Open drain output is disabled on the corresponding pin.
	PORT_PCR19_ODE_1     = 0x1       // Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR19_DSE_Pos   = 0x6       // Position of DSE field.
	PORT_PCR19_DSE_Msk   = 0x40      // Bit mask of DSE field.
	PORT_PCR19_DSE       = 0x40      // Bit DSE.
	PORT_PCR19_DSE_0     = 0x0       // Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR19_DSE_1     = 0x1       // High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR19_MUX_Pos   = 0x8       // Position of MUX field.
	PORT_PCR19_MUX_Msk   = 0x700     // Bit mask of MUX field.
	PORT_PCR19_MUX_000   = 0x0       // Pin disabled (analog).
	PORT_PCR19_MUX_001   = 0x1       // Alternative 1 (GPIO).
	PORT_PCR19_MUX_010   = 0x2       // Alternative 2 (chip-specific).
	PORT_PCR19_MUX_011   = 0x3       // Alternative 3 (chip-specific).
	PORT_PCR19_MUX_100   = 0x4       // Alternative 4 (chip-specific).
	PORT_PCR19_MUX_101   = 0x5       // Alternative 5 (chip-specific).
	PORT_PCR19_MUX_110   = 0x6       // Alternative 6 (chip-specific).
	PORT_PCR19_MUX_111   = 0x7       // Alternative 7 (chip-specific).
	PORT_PCR19_LK_Pos    = 0xf       // Position of LK field.
	PORT_PCR19_LK_Msk    = 0x8000    // Bit mask of LK field.
	PORT_PCR19_LK        = 0x8000    // Bit LK.
	PORT_PCR19_LK_0      = 0x0       // Pin Control Register fields [15:0] are not locked.
	PORT_PCR19_LK_1      = 0x1       // Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
	PORT_PCR19_IRQC_Pos  = 0x10      // Position of IRQC field.
	PORT_PCR19_IRQC_Msk  = 0xf0000   // Bit mask of IRQC field.
	PORT_PCR19_IRQC_0000 = 0x0       // Interrupt/DMA request disabled.
	PORT_PCR19_IRQC_0001 = 0x1       // DMA request on rising edge.
	PORT_PCR19_IRQC_0010 = 0x2       // DMA request on falling edge.
	PORT_PCR19_IRQC_0011 = 0x3       // DMA request on either edge.
	PORT_PCR19_IRQC_1000 = 0x8       // Interrupt when logic 0.
	PORT_PCR19_IRQC_1001 = 0x9       // Interrupt on rising-edge.
	PORT_PCR19_IRQC_1010 = 0xa       // Interrupt on falling-edge.
	PORT_PCR19_IRQC_1011 = 0xb       // Interrupt on either edge.
	PORT_PCR19_IRQC_1100 = 0xc       // Interrupt when logic 1.
	PORT_PCR19_ISF_Pos   = 0x18      // Position of ISF field.
	PORT_PCR19_ISF_Msk   = 0x1000000 // Bit mask of ISF field.
	PORT_PCR19_ISF       = 0x1000000 // Bit ISF.
	PORT_PCR19_ISF_0     = 0x0       // Configured interrupt is not detected.
	PORT_PCR19_ISF_1     = 0x1       // Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

	// PCR20: Pin Control Register n
	PORT_PCR20_PS_Pos    = 0x0       // Position of PS field.
	PORT_PCR20_PS_Msk    = 0x1       // Bit mask of PS field.
	PORT_PCR20_PS        = 0x1       // Bit PS.
	PORT_PCR20_PS_0      = 0x0       // Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR20_PS_1      = 0x1       // Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR20_PE_Pos    = 0x1       // Position of PE field.
	PORT_PCR20_PE_Msk    = 0x2       // Bit mask of PE field.
	PORT_PCR20_PE        = 0x2       // Bit PE.
	PORT_PCR20_PE_0      = 0x0       // Internal pullup or pulldown resistor is not enabled on the corresponding pin.
	PORT_PCR20_PE_1      = 0x1       // Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
	PORT_PCR20_SRE_Pos   = 0x2       // Position of SRE field.
	PORT_PCR20_SRE_Msk   = 0x4       // Bit mask of SRE field.
	PORT_PCR20_SRE       = 0x4       // Bit SRE.
	PORT_PCR20_SRE_0     = 0x0       // Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR20_SRE_1     = 0x1       // Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR20_PFE_Pos   = 0x4       // Position of PFE field.
	PORT_PCR20_PFE_Msk   = 0x10      // Bit mask of PFE field.
	PORT_PCR20_PFE       = 0x10      // Bit PFE.
	PORT_PCR20_PFE_0     = 0x0       // Passive input filter is disabled on the corresponding pin.
	PORT_PCR20_PFE_1     = 0x1       // Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
	PORT_PCR20_ODE_Pos   = 0x5       // Position of ODE field.
	PORT_PCR20_ODE_Msk   = 0x20      // Bit mask of ODE field.
	PORT_PCR20_ODE       = 0x20      // Bit ODE.
	PORT_PCR20_ODE_0     = 0x0       // Open drain output is disabled on the corresponding pin.
	PORT_PCR20_ODE_1     = 0x1       // Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR20_DSE_Pos   = 0x6       // Position of DSE field.
	PORT_PCR20_DSE_Msk   = 0x40      // Bit mask of DSE field.
	PORT_PCR20_DSE       = 0x40      // Bit DSE.
	PORT_PCR20_DSE_0     = 0x0       // Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR20_DSE_1     = 0x1       // High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR20_MUX_Pos   = 0x8       // Position of MUX field.
	PORT_PCR20_MUX_Msk   = 0x700     // Bit mask of MUX field.
	PORT_PCR20_MUX_000   = 0x0       // Pin disabled (analog).
	PORT_PCR20_MUX_001   = 0x1       // Alternative 1 (GPIO).
	PORT_PCR20_MUX_010   = 0x2       // Alternative 2 (chip-specific).
	PORT_PCR20_MUX_011   = 0x3       // Alternative 3 (chip-specific).
	PORT_PCR20_MUX_100   = 0x4       // Alternative 4 (chip-specific).
	PORT_PCR20_MUX_101   = 0x5       // Alternative 5 (chip-specific).
	PORT_PCR20_MUX_110   = 0x6       // Alternative 6 (chip-specific).
	PORT_PCR20_MUX_111   = 0x7       // Alternative 7 (chip-specific).
	PORT_PCR20_LK_Pos    = 0xf       // Position of LK field.
	PORT_PCR20_LK_Msk    = 0x8000    // Bit mask of LK field.
	PORT_PCR20_LK        = 0x8000    // Bit LK.
	PORT_PCR20_LK_0      = 0x0       // Pin Control Register fields [15:0] are not locked.
	PORT_PCR20_LK_1      = 0x1       // Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
	PORT_PCR20_IRQC_Pos  = 0x10      // Position of IRQC field.
	PORT_PCR20_IRQC_Msk  = 0xf0000   // Bit mask of IRQC field.
	PORT_PCR20_IRQC_0000 = 0x0       // Interrupt/DMA request disabled.
	PORT_PCR20_IRQC_0001 = 0x1       // DMA request on rising edge.
	PORT_PCR20_IRQC_0010 = 0x2       // DMA request on falling edge.
	PORT_PCR20_IRQC_0011 = 0x3       // DMA request on either edge.
	PORT_PCR20_IRQC_1000 = 0x8       // Interrupt when logic 0.
	PORT_PCR20_IRQC_1001 = 0x9       // Interrupt on rising-edge.
	PORT_PCR20_IRQC_1010 = 0xa       // Interrupt on falling-edge.
	PORT_PCR20_IRQC_1011 = 0xb       // Interrupt on either edge.
	PORT_PCR20_IRQC_1100 = 0xc       // Interrupt when logic 1.
	PORT_PCR20_ISF_Pos   = 0x18      // Position of ISF field.
	PORT_PCR20_ISF_Msk   = 0x1000000 // Bit mask of ISF field.
	PORT_PCR20_ISF       = 0x1000000 // Bit ISF.
	PORT_PCR20_ISF_0     = 0x0       // Configured interrupt is not detected.
	PORT_PCR20_ISF_1     = 0x1       // Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

	// PCR21: Pin Control Register n
	PORT_PCR21_PS_Pos    = 0x0       // Position of PS field.
	PORT_PCR21_PS_Msk    = 0x1       // Bit mask of PS field.
	PORT_PCR21_PS        = 0x1       // Bit PS.
	PORT_PCR21_PS_0      = 0x0       // Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR21_PS_1      = 0x1       // Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR21_PE_Pos    = 0x1       // Position of PE field.
	PORT_PCR21_PE_Msk    = 0x2       // Bit mask of PE field.
	PORT_PCR21_PE        = 0x2       // Bit PE.
	PORT_PCR21_PE_0      = 0x0       // Internal pullup or pulldown resistor is not enabled on the corresponding pin.
	PORT_PCR21_PE_1      = 0x1       // Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
	PORT_PCR21_SRE_Pos   = 0x2       // Position of SRE field.
	PORT_PCR21_SRE_Msk   = 0x4       // Bit mask of SRE field.
	PORT_PCR21_SRE       = 0x4       // Bit SRE.
	PORT_PCR21_SRE_0     = 0x0       // Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR21_SRE_1     = 0x1       // Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR21_PFE_Pos   = 0x4       // Position of PFE field.
	PORT_PCR21_PFE_Msk   = 0x10      // Bit mask of PFE field.
	PORT_PCR21_PFE       = 0x10      // Bit PFE.
	PORT_PCR21_PFE_0     = 0x0       // Passive input filter is disabled on the corresponding pin.
	PORT_PCR21_PFE_1     = 0x1       // Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
	PORT_PCR21_ODE_Pos   = 0x5       // Position of ODE field.
	PORT_PCR21_ODE_Msk   = 0x20      // Bit mask of ODE field.
	PORT_PCR21_ODE       = 0x20      // Bit ODE.
	PORT_PCR21_ODE_0     = 0x0       // Open drain output is disabled on the corresponding pin.
	PORT_PCR21_ODE_1     = 0x1       // Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR21_DSE_Pos   = 0x6       // Position of DSE field.
	PORT_PCR21_DSE_Msk   = 0x40      // Bit mask of DSE field.
	PORT_PCR21_DSE       = 0x40      // Bit DSE.
	PORT_PCR21_DSE_0     = 0x0       // Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR21_DSE_1     = 0x1       // High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR21_MUX_Pos   = 0x8       // Position of MUX field.
	PORT_PCR21_MUX_Msk   = 0x700     // Bit mask of MUX field.
	PORT_PCR21_MUX_000   = 0x0       // Pin disabled (analog).
	PORT_PCR21_MUX_001   = 0x1       // Alternative 1 (GPIO).
	PORT_PCR21_MUX_010   = 0x2       // Alternative 2 (chip-specific).
	PORT_PCR21_MUX_011   = 0x3       // Alternative 3 (chip-specific).
	PORT_PCR21_MUX_100   = 0x4       // Alternative 4 (chip-specific).
	PORT_PCR21_MUX_101   = 0x5       // Alternative 5 (chip-specific).
	PORT_PCR21_MUX_110   = 0x6       // Alternative 6 (chip-specific).
	PORT_PCR21_MUX_111   = 0x7       // Alternative 7 (chip-specific).
	PORT_PCR21_LK_Pos    = 0xf       // Position of LK field.
	PORT_PCR21_LK_Msk    = 0x8000    // Bit mask of LK field.
	PORT_PCR21_LK        = 0x8000    // Bit LK.
	PORT_PCR21_LK_0      = 0x0       // Pin Control Register fields [15:0] are not locked.
	PORT_PCR21_LK_1      = 0x1       // Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
	PORT_PCR21_IRQC_Pos  = 0x10      // Position of IRQC field.
	PORT_PCR21_IRQC_Msk  = 0xf0000   // Bit mask of IRQC field.
	PORT_PCR21_IRQC_0000 = 0x0       // Interrupt/DMA request disabled.
	PORT_PCR21_IRQC_0001 = 0x1       // DMA request on rising edge.
	PORT_PCR21_IRQC_0010 = 0x2       // DMA request on falling edge.
	PORT_PCR21_IRQC_0011 = 0x3       // DMA request on either edge.
	PORT_PCR21_IRQC_1000 = 0x8       // Interrupt when logic 0.
	PORT_PCR21_IRQC_1001 = 0x9       // Interrupt on rising-edge.
	PORT_PCR21_IRQC_1010 = 0xa       // Interrupt on falling-edge.
	PORT_PCR21_IRQC_1011 = 0xb       // Interrupt on either edge.
	PORT_PCR21_IRQC_1100 = 0xc       // Interrupt when logic 1.
	PORT_PCR21_ISF_Pos   = 0x18      // Position of ISF field.
	PORT_PCR21_ISF_Msk   = 0x1000000 // Bit mask of ISF field.
	PORT_PCR21_ISF       = 0x1000000 // Bit ISF.
	PORT_PCR21_ISF_0     = 0x0       // Configured interrupt is not detected.
	PORT_PCR21_ISF_1     = 0x1       // Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

	// PCR22: Pin Control Register n
	PORT_PCR22_PS_Pos    = 0x0       // Position of PS field.
	PORT_PCR22_PS_Msk    = 0x1       // Bit mask of PS field.
	PORT_PCR22_PS        = 0x1       // Bit PS.
	PORT_PCR22_PS_0      = 0x0       // Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR22_PS_1      = 0x1       // Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR22_PE_Pos    = 0x1       // Position of PE field.
	PORT_PCR22_PE_Msk    = 0x2       // Bit mask of PE field.
	PORT_PCR22_PE        = 0x2       // Bit PE.
	PORT_PCR22_PE_0      = 0x0       // Internal pullup or pulldown resistor is not enabled on the corresponding pin.
	PORT_PCR22_PE_1      = 0x1       // Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
	PORT_PCR22_SRE_Pos   = 0x2       // Position of SRE field.
	PORT_PCR22_SRE_Msk   = 0x4       // Bit mask of SRE field.
	PORT_PCR22_SRE       = 0x4       // Bit SRE.
	PORT_PCR22_SRE_0     = 0x0       // Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR22_SRE_1     = 0x1       // Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR22_PFE_Pos   = 0x4       // Position of PFE field.
	PORT_PCR22_PFE_Msk   = 0x10      // Bit mask of PFE field.
	PORT_PCR22_PFE       = 0x10      // Bit PFE.
	PORT_PCR22_PFE_0     = 0x0       // Passive input filter is disabled on the corresponding pin.
	PORT_PCR22_PFE_1     = 0x1       // Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
	PORT_PCR22_ODE_Pos   = 0x5       // Position of ODE field.
	PORT_PCR22_ODE_Msk   = 0x20      // Bit mask of ODE field.
	PORT_PCR22_ODE       = 0x20      // Bit ODE.
	PORT_PCR22_ODE_0     = 0x0       // Open drain output is disabled on the corresponding pin.
	PORT_PCR22_ODE_1     = 0x1       // Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR22_DSE_Pos   = 0x6       // Position of DSE field.
	PORT_PCR22_DSE_Msk   = 0x40      // Bit mask of DSE field.
	PORT_PCR22_DSE       = 0x40      // Bit DSE.
	PORT_PCR22_DSE_0     = 0x0       // Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR22_DSE_1     = 0x1       // High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR22_MUX_Pos   = 0x8       // Position of MUX field.
	PORT_PCR22_MUX_Msk   = 0x700     // Bit mask of MUX field.
	PORT_PCR22_MUX_000   = 0x0       // Pin disabled (analog).
	PORT_PCR22_MUX_001   = 0x1       // Alternative 1 (GPIO).
	PORT_PCR22_MUX_010   = 0x2       // Alternative 2 (chip-specific).
	PORT_PCR22_MUX_011   = 0x3       // Alternative 3 (chip-specific).
	PORT_PCR22_MUX_100   = 0x4       // Alternative 4 (chip-specific).
	PORT_PCR22_MUX_101   = 0x5       // Alternative 5 (chip-specific).
	PORT_PCR22_MUX_110   = 0x6       // Alternative 6 (chip-specific).
	PORT_PCR22_MUX_111   = 0x7       // Alternative 7 (chip-specific).
	PORT_PCR22_LK_Pos    = 0xf       // Position of LK field.
	PORT_PCR22_LK_Msk    = 0x8000    // Bit mask of LK field.
	PORT_PCR22_LK        = 0x8000    // Bit LK.
	PORT_PCR22_LK_0      = 0x0       // Pin Control Register fields [15:0] are not locked.
	PORT_PCR22_LK_1      = 0x1       // Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
	PORT_PCR22_IRQC_Pos  = 0x10      // Position of IRQC field.
	PORT_PCR22_IRQC_Msk  = 0xf0000   // Bit mask of IRQC field.
	PORT_PCR22_IRQC_0000 = 0x0       // Interrupt/DMA request disabled.
	PORT_PCR22_IRQC_0001 = 0x1       // DMA request on rising edge.
	PORT_PCR22_IRQC_0010 = 0x2       // DMA request on falling edge.
	PORT_PCR22_IRQC_0011 = 0x3       // DMA request on either edge.
	PORT_PCR22_IRQC_1000 = 0x8       // Interrupt when logic 0.
	PORT_PCR22_IRQC_1001 = 0x9       // Interrupt on rising-edge.
	PORT_PCR22_IRQC_1010 = 0xa       // Interrupt on falling-edge.
	PORT_PCR22_IRQC_1011 = 0xb       // Interrupt on either edge.
	PORT_PCR22_IRQC_1100 = 0xc       // Interrupt when logic 1.
	PORT_PCR22_ISF_Pos   = 0x18      // Position of ISF field.
	PORT_PCR22_ISF_Msk   = 0x1000000 // Bit mask of ISF field.
	PORT_PCR22_ISF       = 0x1000000 // Bit ISF.
	PORT_PCR22_ISF_0     = 0x0       // Configured interrupt is not detected.
	PORT_PCR22_ISF_1     = 0x1       // Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

	// PCR23: Pin Control Register n
	PORT_PCR23_PS_Pos    = 0x0       // Position of PS field.
	PORT_PCR23_PS_Msk    = 0x1       // Bit mask of PS field.
	PORT_PCR23_PS        = 0x1       // Bit PS.
	PORT_PCR23_PS_0      = 0x0       // Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR23_PS_1      = 0x1       // Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR23_PE_Pos    = 0x1       // Position of PE field.
	PORT_PCR23_PE_Msk    = 0x2       // Bit mask of PE field.
	PORT_PCR23_PE        = 0x2       // Bit PE.
	PORT_PCR23_PE_0      = 0x0       // Internal pullup or pulldown resistor is not enabled on the corresponding pin.
	PORT_PCR23_PE_1      = 0x1       // Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
	PORT_PCR23_SRE_Pos   = 0x2       // Position of SRE field.
	PORT_PCR23_SRE_Msk   = 0x4       // Bit mask of SRE field.
	PORT_PCR23_SRE       = 0x4       // Bit SRE.
	PORT_PCR23_SRE_0     = 0x0       // Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR23_SRE_1     = 0x1       // Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR23_PFE_Pos   = 0x4       // Position of PFE field.
	PORT_PCR23_PFE_Msk   = 0x10      // Bit mask of PFE field.
	PORT_PCR23_PFE       = 0x10      // Bit PFE.
	PORT_PCR23_PFE_0     = 0x0       // Passive input filter is disabled on the corresponding pin.
	PORT_PCR23_PFE_1     = 0x1       // Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
	PORT_PCR23_ODE_Pos   = 0x5       // Position of ODE field.
	PORT_PCR23_ODE_Msk   = 0x20      // Bit mask of ODE field.
	PORT_PCR23_ODE       = 0x20      // Bit ODE.
	PORT_PCR23_ODE_0     = 0x0       // Open drain output is disabled on the corresponding pin.
	PORT_PCR23_ODE_1     = 0x1       // Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR23_DSE_Pos   = 0x6       // Position of DSE field.
	PORT_PCR23_DSE_Msk   = 0x40      // Bit mask of DSE field.
	PORT_PCR23_DSE       = 0x40      // Bit DSE.
	PORT_PCR23_DSE_0     = 0x0       // Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR23_DSE_1     = 0x1       // High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR23_MUX_Pos   = 0x8       // Position of MUX field.
	PORT_PCR23_MUX_Msk   = 0x700     // Bit mask of MUX field.
	PORT_PCR23_MUX_000   = 0x0       // Pin disabled (analog).
	PORT_PCR23_MUX_001   = 0x1       // Alternative 1 (GPIO).
	PORT_PCR23_MUX_010   = 0x2       // Alternative 2 (chip-specific).
	PORT_PCR23_MUX_011   = 0x3       // Alternative 3 (chip-specific).
	PORT_PCR23_MUX_100   = 0x4       // Alternative 4 (chip-specific).
	PORT_PCR23_MUX_101   = 0x5       // Alternative 5 (chip-specific).
	PORT_PCR23_MUX_110   = 0x6       // Alternative 6 (chip-specific).
	PORT_PCR23_MUX_111   = 0x7       // Alternative 7 (chip-specific).
	PORT_PCR23_LK_Pos    = 0xf       // Position of LK field.
	PORT_PCR23_LK_Msk    = 0x8000    // Bit mask of LK field.
	PORT_PCR23_LK        = 0x8000    // Bit LK.
	PORT_PCR23_LK_0      = 0x0       // Pin Control Register fields [15:0] are not locked.
	PORT_PCR23_LK_1      = 0x1       // Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
	PORT_PCR23_IRQC_Pos  = 0x10      // Position of IRQC field.
	PORT_PCR23_IRQC_Msk  = 0xf0000   // Bit mask of IRQC field.
	PORT_PCR23_IRQC_0000 = 0x0       // Interrupt/DMA request disabled.
	PORT_PCR23_IRQC_0001 = 0x1       // DMA request on rising edge.
	PORT_PCR23_IRQC_0010 = 0x2       // DMA request on falling edge.
	PORT_PCR23_IRQC_0011 = 0x3       // DMA request on either edge.
	PORT_PCR23_IRQC_1000 = 0x8       // Interrupt when logic 0.
	PORT_PCR23_IRQC_1001 = 0x9       // Interrupt on rising-edge.
	PORT_PCR23_IRQC_1010 = 0xa       // Interrupt on falling-edge.
	PORT_PCR23_IRQC_1011 = 0xb       // Interrupt on either edge.
	PORT_PCR23_IRQC_1100 = 0xc       // Interrupt when logic 1.
	PORT_PCR23_ISF_Pos   = 0x18      // Position of ISF field.
	PORT_PCR23_ISF_Msk   = 0x1000000 // Bit mask of ISF field.
	PORT_PCR23_ISF       = 0x1000000 // Bit ISF.
	PORT_PCR23_ISF_0     = 0x0       // Configured interrupt is not detected.
	PORT_PCR23_ISF_1     = 0x1       // Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

	// PCR24: Pin Control Register n
	PORT_PCR24_PS_Pos    = 0x0       // Position of PS field.
	PORT_PCR24_PS_Msk    = 0x1       // Bit mask of PS field.
	PORT_PCR24_PS        = 0x1       // Bit PS.
	PORT_PCR24_PS_0      = 0x0       // Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR24_PS_1      = 0x1       // Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR24_PE_Pos    = 0x1       // Position of PE field.
	PORT_PCR24_PE_Msk    = 0x2       // Bit mask of PE field.
	PORT_PCR24_PE        = 0x2       // Bit PE.
	PORT_PCR24_PE_0      = 0x0       // Internal pullup or pulldown resistor is not enabled on the corresponding pin.
	PORT_PCR24_PE_1      = 0x1       // Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
	PORT_PCR24_SRE_Pos   = 0x2       // Position of SRE field.
	PORT_PCR24_SRE_Msk   = 0x4       // Bit mask of SRE field.
	PORT_PCR24_SRE       = 0x4       // Bit SRE.
	PORT_PCR24_SRE_0     = 0x0       // Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR24_SRE_1     = 0x1       // Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR24_PFE_Pos   = 0x4       // Position of PFE field.
	PORT_PCR24_PFE_Msk   = 0x10      // Bit mask of PFE field.
	PORT_PCR24_PFE       = 0x10      // Bit PFE.
	PORT_PCR24_PFE_0     = 0x0       // Passive input filter is disabled on the corresponding pin.
	PORT_PCR24_PFE_1     = 0x1       // Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
	PORT_PCR24_ODE_Pos   = 0x5       // Position of ODE field.
	PORT_PCR24_ODE_Msk   = 0x20      // Bit mask of ODE field.
	PORT_PCR24_ODE       = 0x20      // Bit ODE.
	PORT_PCR24_ODE_0     = 0x0       // Open drain output is disabled on the corresponding pin.
	PORT_PCR24_ODE_1     = 0x1       // Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR24_DSE_Pos   = 0x6       // Position of DSE field.
	PORT_PCR24_DSE_Msk   = 0x40      // Bit mask of DSE field.
	PORT_PCR24_DSE       = 0x40      // Bit DSE.
	PORT_PCR24_DSE_0     = 0x0       // Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR24_DSE_1     = 0x1       // High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR24_MUX_Pos   = 0x8       // Position of MUX field.
	PORT_PCR24_MUX_Msk   = 0x700     // Bit mask of MUX field.
	PORT_PCR24_MUX_000   = 0x0       // Pin disabled (analog).
	PORT_PCR24_MUX_001   = 0x1       // Alternative 1 (GPIO).
	PORT_PCR24_MUX_010   = 0x2       // Alternative 2 (chip-specific).
	PORT_PCR24_MUX_011   = 0x3       // Alternative 3 (chip-specific).
	PORT_PCR24_MUX_100   = 0x4       // Alternative 4 (chip-specific).
	PORT_PCR24_MUX_101   = 0x5       // Alternative 5 (chip-specific).
	PORT_PCR24_MUX_110   = 0x6       // Alternative 6 (chip-specific).
	PORT_PCR24_MUX_111   = 0x7       // Alternative 7 (chip-specific).
	PORT_PCR24_LK_Pos    = 0xf       // Position of LK field.
	PORT_PCR24_LK_Msk    = 0x8000    // Bit mask of LK field.
	PORT_PCR24_LK        = 0x8000    // Bit LK.
	PORT_PCR24_LK_0      = 0x0       // Pin Control Register fields [15:0] are not locked.
	PORT_PCR24_LK_1      = 0x1       // Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
	PORT_PCR24_IRQC_Pos  = 0x10      // Position of IRQC field.
	PORT_PCR24_IRQC_Msk  = 0xf0000   // Bit mask of IRQC field.
	PORT_PCR24_IRQC_0000 = 0x0       // Interrupt/DMA request disabled.
	PORT_PCR24_IRQC_0001 = 0x1       // DMA request on rising edge.
	PORT_PCR24_IRQC_0010 = 0x2       // DMA request on falling edge.
	PORT_PCR24_IRQC_0011 = 0x3       // DMA request on either edge.
	PORT_PCR24_IRQC_1000 = 0x8       // Interrupt when logic 0.
	PORT_PCR24_IRQC_1001 = 0x9       // Interrupt on rising-edge.
	PORT_PCR24_IRQC_1010 = 0xa       // Interrupt on falling-edge.
	PORT_PCR24_IRQC_1011 = 0xb       // Interrupt on either edge.
	PORT_PCR24_IRQC_1100 = 0xc       // Interrupt when logic 1.
	PORT_PCR24_ISF_Pos   = 0x18      // Position of ISF field.
	PORT_PCR24_ISF_Msk   = 0x1000000 // Bit mask of ISF field.
	PORT_PCR24_ISF       = 0x1000000 // Bit ISF.
	PORT_PCR24_ISF_0     = 0x0       // Configured interrupt is not detected.
	PORT_PCR24_ISF_1     = 0x1       // Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

	// PCR25: Pin Control Register n
	PORT_PCR25_PS_Pos    = 0x0       // Position of PS field.
	PORT_PCR25_PS_Msk    = 0x1       // Bit mask of PS field.
	PORT_PCR25_PS        = 0x1       // Bit PS.
	PORT_PCR25_PS_0      = 0x0       // Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR25_PS_1      = 0x1       // Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR25_PE_Pos    = 0x1       // Position of PE field.
	PORT_PCR25_PE_Msk    = 0x2       // Bit mask of PE field.
	PORT_PCR25_PE        = 0x2       // Bit PE.
	PORT_PCR25_PE_0      = 0x0       // Internal pullup or pulldown resistor is not enabled on the corresponding pin.
	PORT_PCR25_PE_1      = 0x1       // Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
	PORT_PCR25_SRE_Pos   = 0x2       // Position of SRE field.
	PORT_PCR25_SRE_Msk   = 0x4       // Bit mask of SRE field.
	PORT_PCR25_SRE       = 0x4       // Bit SRE.
	PORT_PCR25_SRE_0     = 0x0       // Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR25_SRE_1     = 0x1       // Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR25_PFE_Pos   = 0x4       // Position of PFE field.
	PORT_PCR25_PFE_Msk   = 0x10      // Bit mask of PFE field.
	PORT_PCR25_PFE       = 0x10      // Bit PFE.
	PORT_PCR25_PFE_0     = 0x0       // Passive input filter is disabled on the corresponding pin.
	PORT_PCR25_PFE_1     = 0x1       // Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
	PORT_PCR25_ODE_Pos   = 0x5       // Position of ODE field.
	PORT_PCR25_ODE_Msk   = 0x20      // Bit mask of ODE field.
	PORT_PCR25_ODE       = 0x20      // Bit ODE.
	PORT_PCR25_ODE_0     = 0x0       // Open drain output is disabled on the corresponding pin.
	PORT_PCR25_ODE_1     = 0x1       // Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR25_DSE_Pos   = 0x6       // Position of DSE field.
	PORT_PCR25_DSE_Msk   = 0x40      // Bit mask of DSE field.
	PORT_PCR25_DSE       = 0x40      // Bit DSE.
	PORT_PCR25_DSE_0     = 0x0       // Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR25_DSE_1     = 0x1       // High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR25_MUX_Pos   = 0x8       // Position of MUX field.
	PORT_PCR25_MUX_Msk   = 0x700     // Bit mask of MUX field.
	PORT_PCR25_MUX_000   = 0x0       // Pin disabled (analog).
	PORT_PCR25_MUX_001   = 0x1       // Alternative 1 (GPIO).
	PORT_PCR25_MUX_010   = 0x2       // Alternative 2 (chip-specific).
	PORT_PCR25_MUX_011   = 0x3       // Alternative 3 (chip-specific).
	PORT_PCR25_MUX_100   = 0x4       // Alternative 4 (chip-specific).
	PORT_PCR25_MUX_101   = 0x5       // Alternative 5 (chip-specific).
	PORT_PCR25_MUX_110   = 0x6       // Alternative 6 (chip-specific).
	PORT_PCR25_MUX_111   = 0x7       // Alternative 7 (chip-specific).
	PORT_PCR25_LK_Pos    = 0xf       // Position of LK field.
	PORT_PCR25_LK_Msk    = 0x8000    // Bit mask of LK field.
	PORT_PCR25_LK        = 0x8000    // Bit LK.
	PORT_PCR25_LK_0      = 0x0       // Pin Control Register fields [15:0] are not locked.
	PORT_PCR25_LK_1      = 0x1       // Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
	PORT_PCR25_IRQC_Pos  = 0x10      // Position of IRQC field.
	PORT_PCR25_IRQC_Msk  = 0xf0000   // Bit mask of IRQC field.
	PORT_PCR25_IRQC_0000 = 0x0       // Interrupt/DMA request disabled.
	PORT_PCR25_IRQC_0001 = 0x1       // DMA request on rising edge.
	PORT_PCR25_IRQC_0010 = 0x2       // DMA request on falling edge.
	PORT_PCR25_IRQC_0011 = 0x3       // DMA request on either edge.
	PORT_PCR25_IRQC_1000 = 0x8       // Interrupt when logic 0.
	PORT_PCR25_IRQC_1001 = 0x9       // Interrupt on rising-edge.
	PORT_PCR25_IRQC_1010 = 0xa       // Interrupt on falling-edge.
	PORT_PCR25_IRQC_1011 = 0xb       // Interrupt on either edge.
	PORT_PCR25_IRQC_1100 = 0xc       // Interrupt when logic 1.
	PORT_PCR25_ISF_Pos   = 0x18      // Position of ISF field.
	PORT_PCR25_ISF_Msk   = 0x1000000 // Bit mask of ISF field.
	PORT_PCR25_ISF       = 0x1000000 // Bit ISF.
	PORT_PCR25_ISF_0     = 0x0       // Configured interrupt is not detected.
	PORT_PCR25_ISF_1     = 0x1       // Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

	// PCR26: Pin Control Register n
	PORT_PCR26_PS_Pos    = 0x0       // Position of PS field.
	PORT_PCR26_PS_Msk    = 0x1       // Bit mask of PS field.
	PORT_PCR26_PS        = 0x1       // Bit PS.
	PORT_PCR26_PS_0      = 0x0       // Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR26_PS_1      = 0x1       // Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR26_PE_Pos    = 0x1       // Position of PE field.
	PORT_PCR26_PE_Msk    = 0x2       // Bit mask of PE field.
	PORT_PCR26_PE        = 0x2       // Bit PE.
	PORT_PCR26_PE_0      = 0x0       // Internal pullup or pulldown resistor is not enabled on the corresponding pin.
	PORT_PCR26_PE_1      = 0x1       // Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
	PORT_PCR26_SRE_Pos   = 0x2       // Position of SRE field.
	PORT_PCR26_SRE_Msk   = 0x4       // Bit mask of SRE field.
	PORT_PCR26_SRE       = 0x4       // Bit SRE.
	PORT_PCR26_SRE_0     = 0x0       // Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR26_SRE_1     = 0x1       // Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR26_PFE_Pos   = 0x4       // Position of PFE field.
	PORT_PCR26_PFE_Msk   = 0x10      // Bit mask of PFE field.
	PORT_PCR26_PFE       = 0x10      // Bit PFE.
	PORT_PCR26_PFE_0     = 0x0       // Passive input filter is disabled on the corresponding pin.
	PORT_PCR26_PFE_1     = 0x1       // Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
	PORT_PCR26_ODE_Pos   = 0x5       // Position of ODE field.
	PORT_PCR26_ODE_Msk   = 0x20      // Bit mask of ODE field.
	PORT_PCR26_ODE       = 0x20      // Bit ODE.
	PORT_PCR26_ODE_0     = 0x0       // Open drain output is disabled on the corresponding pin.
	PORT_PCR26_ODE_1     = 0x1       // Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR26_DSE_Pos   = 0x6       // Position of DSE field.
	PORT_PCR26_DSE_Msk   = 0x40      // Bit mask of DSE field.
	PORT_PCR26_DSE       = 0x40      // Bit DSE.
	PORT_PCR26_DSE_0     = 0x0       // Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR26_DSE_1     = 0x1       // High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR26_MUX_Pos   = 0x8       // Position of MUX field.
	PORT_PCR26_MUX_Msk   = 0x700     // Bit mask of MUX field.
	PORT_PCR26_MUX_000   = 0x0       // Pin disabled (analog).
	PORT_PCR26_MUX_001   = 0x1       // Alternative 1 (GPIO).
	PORT_PCR26_MUX_010   = 0x2       // Alternative 2 (chip-specific).
	PORT_PCR26_MUX_011   = 0x3       // Alternative 3 (chip-specific).
	PORT_PCR26_MUX_100   = 0x4       // Alternative 4 (chip-specific).
	PORT_PCR26_MUX_101   = 0x5       // Alternative 5 (chip-specific).
	PORT_PCR26_MUX_110   = 0x6       // Alternative 6 (chip-specific).
	PORT_PCR26_MUX_111   = 0x7       // Alternative 7 (chip-specific).
	PORT_PCR26_LK_Pos    = 0xf       // Position of LK field.
	PORT_PCR26_LK_Msk    = 0x8000    // Bit mask of LK field.
	PORT_PCR26_LK        = 0x8000    // Bit LK.
	PORT_PCR26_LK_0      = 0x0       // Pin Control Register fields [15:0] are not locked.
	PORT_PCR26_LK_1      = 0x1       // Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
	PORT_PCR26_IRQC_Pos  = 0x10      // Position of IRQC field.
	PORT_PCR26_IRQC_Msk  = 0xf0000   // Bit mask of IRQC field.
	PORT_PCR26_IRQC_0000 = 0x0       // Interrupt/DMA request disabled.
	PORT_PCR26_IRQC_0001 = 0x1       // DMA request on rising edge.
	PORT_PCR26_IRQC_0010 = 0x2       // DMA request on falling edge.
	PORT_PCR26_IRQC_0011 = 0x3       // DMA request on either edge.
	PORT_PCR26_IRQC_1000 = 0x8       // Interrupt when logic 0.
	PORT_PCR26_IRQC_1001 = 0x9       // Interrupt on rising-edge.
	PORT_PCR26_IRQC_1010 = 0xa       // Interrupt on falling-edge.
	PORT_PCR26_IRQC_1011 = 0xb       // Interrupt on either edge.
	PORT_PCR26_IRQC_1100 = 0xc       // Interrupt when logic 1.
	PORT_PCR26_ISF_Pos   = 0x18      // Position of ISF field.
	PORT_PCR26_ISF_Msk   = 0x1000000 // Bit mask of ISF field.
	PORT_PCR26_ISF       = 0x1000000 // Bit ISF.
	PORT_PCR26_ISF_0     = 0x0       // Configured interrupt is not detected.
	PORT_PCR26_ISF_1     = 0x1       // Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

	// PCR27: Pin Control Register n
	PORT_PCR27_PS_Pos    = 0x0       // Position of PS field.
	PORT_PCR27_PS_Msk    = 0x1       // Bit mask of PS field.
	PORT_PCR27_PS        = 0x1       // Bit PS.
	PORT_PCR27_PS_0      = 0x0       // Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR27_PS_1      = 0x1       // Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR27_PE_Pos    = 0x1       // Position of PE field.
	PORT_PCR27_PE_Msk    = 0x2       // Bit mask of PE field.
	PORT_PCR27_PE        = 0x2       // Bit PE.
	PORT_PCR27_PE_0      = 0x0       // Internal pullup or pulldown resistor is not enabled on the corresponding pin.
	PORT_PCR27_PE_1      = 0x1       // Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
	PORT_PCR27_SRE_Pos   = 0x2       // Position of SRE field.
	PORT_PCR27_SRE_Msk   = 0x4       // Bit mask of SRE field.
	PORT_PCR27_SRE       = 0x4       // Bit SRE.
	PORT_PCR27_SRE_0     = 0x0       // Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR27_SRE_1     = 0x1       // Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR27_PFE_Pos   = 0x4       // Position of PFE field.
	PORT_PCR27_PFE_Msk   = 0x10      // Bit mask of PFE field.
	PORT_PCR27_PFE       = 0x10      // Bit PFE.
	PORT_PCR27_PFE_0     = 0x0       // Passive input filter is disabled on the corresponding pin.
	PORT_PCR27_PFE_1     = 0x1       // Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
	PORT_PCR27_ODE_Pos   = 0x5       // Position of ODE field.
	PORT_PCR27_ODE_Msk   = 0x20      // Bit mask of ODE field.
	PORT_PCR27_ODE       = 0x20      // Bit ODE.
	PORT_PCR27_ODE_0     = 0x0       // Open drain output is disabled on the corresponding pin.
	PORT_PCR27_ODE_1     = 0x1       // Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR27_DSE_Pos   = 0x6       // Position of DSE field.
	PORT_PCR27_DSE_Msk   = 0x40      // Bit mask of DSE field.
	PORT_PCR27_DSE       = 0x40      // Bit DSE.
	PORT_PCR27_DSE_0     = 0x0       // Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR27_DSE_1     = 0x1       // High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR27_MUX_Pos   = 0x8       // Position of MUX field.
	PORT_PCR27_MUX_Msk   = 0x700     // Bit mask of MUX field.
	PORT_PCR27_MUX_000   = 0x0       // Pin disabled (analog).
	PORT_PCR27_MUX_001   = 0x1       // Alternative 1 (GPIO).
	PORT_PCR27_MUX_010   = 0x2       // Alternative 2 (chip-specific).
	PORT_PCR27_MUX_011   = 0x3       // Alternative 3 (chip-specific).
	PORT_PCR27_MUX_100   = 0x4       // Alternative 4 (chip-specific).
	PORT_PCR27_MUX_101   = 0x5       // Alternative 5 (chip-specific).
	PORT_PCR27_MUX_110   = 0x6       // Alternative 6 (chip-specific).
	PORT_PCR27_MUX_111   = 0x7       // Alternative 7 (chip-specific).
	PORT_PCR27_LK_Pos    = 0xf       // Position of LK field.
	PORT_PCR27_LK_Msk    = 0x8000    // Bit mask of LK field.
	PORT_PCR27_LK        = 0x8000    // Bit LK.
	PORT_PCR27_LK_0      = 0x0       // Pin Control Register fields [15:0] are not locked.
	PORT_PCR27_LK_1      = 0x1       // Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
	PORT_PCR27_IRQC_Pos  = 0x10      // Position of IRQC field.
	PORT_PCR27_IRQC_Msk  = 0xf0000   // Bit mask of IRQC field.
	PORT_PCR27_IRQC_0000 = 0x0       // Interrupt/DMA request disabled.
	PORT_PCR27_IRQC_0001 = 0x1       // DMA request on rising edge.
	PORT_PCR27_IRQC_0010 = 0x2       // DMA request on falling edge.
	PORT_PCR27_IRQC_0011 = 0x3       // DMA request on either edge.
	PORT_PCR27_IRQC_1000 = 0x8       // Interrupt when logic 0.
	PORT_PCR27_IRQC_1001 = 0x9       // Interrupt on rising-edge.
	PORT_PCR27_IRQC_1010 = 0xa       // Interrupt on falling-edge.
	PORT_PCR27_IRQC_1011 = 0xb       // Interrupt on either edge.
	PORT_PCR27_IRQC_1100 = 0xc       // Interrupt when logic 1.
	PORT_PCR27_ISF_Pos   = 0x18      // Position of ISF field.
	PORT_PCR27_ISF_Msk   = 0x1000000 // Bit mask of ISF field.
	PORT_PCR27_ISF       = 0x1000000 // Bit ISF.
	PORT_PCR27_ISF_0     = 0x0       // Configured interrupt is not detected.
	PORT_PCR27_ISF_1     = 0x1       // Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

	// PCR28: Pin Control Register n
	PORT_PCR28_PS_Pos    = 0x0       // Position of PS field.
	PORT_PCR28_PS_Msk    = 0x1       // Bit mask of PS field.
	PORT_PCR28_PS        = 0x1       // Bit PS.
	PORT_PCR28_PS_0      = 0x0       // Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR28_PS_1      = 0x1       // Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR28_PE_Pos    = 0x1       // Position of PE field.
	PORT_PCR28_PE_Msk    = 0x2       // Bit mask of PE field.
	PORT_PCR28_PE        = 0x2       // Bit PE.
	PORT_PCR28_PE_0      = 0x0       // Internal pullup or pulldown resistor is not enabled on the corresponding pin.
	PORT_PCR28_PE_1      = 0x1       // Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
	PORT_PCR28_SRE_Pos   = 0x2       // Position of SRE field.
	PORT_PCR28_SRE_Msk   = 0x4       // Bit mask of SRE field.
	PORT_PCR28_SRE       = 0x4       // Bit SRE.
	PORT_PCR28_SRE_0     = 0x0       // Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR28_SRE_1     = 0x1       // Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR28_PFE_Pos   = 0x4       // Position of PFE field.
	PORT_PCR28_PFE_Msk   = 0x10      // Bit mask of PFE field.
	PORT_PCR28_PFE       = 0x10      // Bit PFE.
	PORT_PCR28_PFE_0     = 0x0       // Passive input filter is disabled on the corresponding pin.
	PORT_PCR28_PFE_1     = 0x1       // Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
	PORT_PCR28_ODE_Pos   = 0x5       // Position of ODE field.
	PORT_PCR28_ODE_Msk   = 0x20      // Bit mask of ODE field.
	PORT_PCR28_ODE       = 0x20      // Bit ODE.
	PORT_PCR28_ODE_0     = 0x0       // Open drain output is disabled on the corresponding pin.
	PORT_PCR28_ODE_1     = 0x1       // Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR28_DSE_Pos   = 0x6       // Position of DSE field.
	PORT_PCR28_DSE_Msk   = 0x40      // Bit mask of DSE field.
	PORT_PCR28_DSE       = 0x40      // Bit DSE.
	PORT_PCR28_DSE_0     = 0x0       // Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR28_DSE_1     = 0x1       // High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR28_MUX_Pos   = 0x8       // Position of MUX field.
	PORT_PCR28_MUX_Msk   = 0x700     // Bit mask of MUX field.
	PORT_PCR28_MUX_000   = 0x0       // Pin disabled (analog).
	PORT_PCR28_MUX_001   = 0x1       // Alternative 1 (GPIO).
	PORT_PCR28_MUX_010   = 0x2       // Alternative 2 (chip-specific).
	PORT_PCR28_MUX_011   = 0x3       // Alternative 3 (chip-specific).
	PORT_PCR28_MUX_100   = 0x4       // Alternative 4 (chip-specific).
	PORT_PCR28_MUX_101   = 0x5       // Alternative 5 (chip-specific).
	PORT_PCR28_MUX_110   = 0x6       // Alternative 6 (chip-specific).
	PORT_PCR28_MUX_111   = 0x7       // Alternative 7 (chip-specific).
	PORT_PCR28_LK_Pos    = 0xf       // Position of LK field.
	PORT_PCR28_LK_Msk    = 0x8000    // Bit mask of LK field.
	PORT_PCR28_LK        = 0x8000    // Bit LK.
	PORT_PCR28_LK_0      = 0x0       // Pin Control Register fields [15:0] are not locked.
	PORT_PCR28_LK_1      = 0x1       // Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
	PORT_PCR28_IRQC_Pos  = 0x10      // Position of IRQC field.
	PORT_PCR28_IRQC_Msk  = 0xf0000   // Bit mask of IRQC field.
	PORT_PCR28_IRQC_0000 = 0x0       // Interrupt/DMA request disabled.
	PORT_PCR28_IRQC_0001 = 0x1       // DMA request on rising edge.
	PORT_PCR28_IRQC_0010 = 0x2       // DMA request on falling edge.
	PORT_PCR28_IRQC_0011 = 0x3       // DMA request on either edge.
	PORT_PCR28_IRQC_1000 = 0x8       // Interrupt when logic 0.
	PORT_PCR28_IRQC_1001 = 0x9       // Interrupt on rising-edge.
	PORT_PCR28_IRQC_1010 = 0xa       // Interrupt on falling-edge.
	PORT_PCR28_IRQC_1011 = 0xb       // Interrupt on either edge.
	PORT_PCR28_IRQC_1100 = 0xc       // Interrupt when logic 1.
	PORT_PCR28_ISF_Pos   = 0x18      // Position of ISF field.
	PORT_PCR28_ISF_Msk   = 0x1000000 // Bit mask of ISF field.
	PORT_PCR28_ISF       = 0x1000000 // Bit ISF.
	PORT_PCR28_ISF_0     = 0x0       // Configured interrupt is not detected.
	PORT_PCR28_ISF_1     = 0x1       // Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

	// PCR29: Pin Control Register n
	PORT_PCR29_PS_Pos    = 0x0       // Position of PS field.
	PORT_PCR29_PS_Msk    = 0x1       // Bit mask of PS field.
	PORT_PCR29_PS        = 0x1       // Bit PS.
	PORT_PCR29_PS_0      = 0x0       // Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR29_PS_1      = 0x1       // Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR29_PE_Pos    = 0x1       // Position of PE field.
	PORT_PCR29_PE_Msk    = 0x2       // Bit mask of PE field.
	PORT_PCR29_PE        = 0x2       // Bit PE.
	PORT_PCR29_PE_0      = 0x0       // Internal pullup or pulldown resistor is not enabled on the corresponding pin.
	PORT_PCR29_PE_1      = 0x1       // Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
	PORT_PCR29_SRE_Pos   = 0x2       // Position of SRE field.
	PORT_PCR29_SRE_Msk   = 0x4       // Bit mask of SRE field.
	PORT_PCR29_SRE       = 0x4       // Bit SRE.
	PORT_PCR29_SRE_0     = 0x0       // Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR29_SRE_1     = 0x1       // Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR29_PFE_Pos   = 0x4       // Position of PFE field.
	PORT_PCR29_PFE_Msk   = 0x10      // Bit mask of PFE field.
	PORT_PCR29_PFE       = 0x10      // Bit PFE.
	PORT_PCR29_PFE_0     = 0x0       // Passive input filter is disabled on the corresponding pin.
	PORT_PCR29_PFE_1     = 0x1       // Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
	PORT_PCR29_ODE_Pos   = 0x5       // Position of ODE field.
	PORT_PCR29_ODE_Msk   = 0x20      // Bit mask of ODE field.
	PORT_PCR29_ODE       = 0x20      // Bit ODE.
	PORT_PCR29_ODE_0     = 0x0       // Open drain output is disabled on the corresponding pin.
	PORT_PCR29_ODE_1     = 0x1       // Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR29_DSE_Pos   = 0x6       // Position of DSE field.
	PORT_PCR29_DSE_Msk   = 0x40      // Bit mask of DSE field.
	PORT_PCR29_DSE       = 0x40      // Bit DSE.
	PORT_PCR29_DSE_0     = 0x0       // Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR29_DSE_1     = 0x1       // High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR29_MUX_Pos   = 0x8       // Position of MUX field.
	PORT_PCR29_MUX_Msk   = 0x700     // Bit mask of MUX field.
	PORT_PCR29_MUX_000   = 0x0       // Pin disabled (analog).
	PORT_PCR29_MUX_001   = 0x1       // Alternative 1 (GPIO).
	PORT_PCR29_MUX_010   = 0x2       // Alternative 2 (chip-specific).
	PORT_PCR29_MUX_011   = 0x3       // Alternative 3 (chip-specific).
	PORT_PCR29_MUX_100   = 0x4       // Alternative 4 (chip-specific).
	PORT_PCR29_MUX_101   = 0x5       // Alternative 5 (chip-specific).
	PORT_PCR29_MUX_110   = 0x6       // Alternative 6 (chip-specific).
	PORT_PCR29_MUX_111   = 0x7       // Alternative 7 (chip-specific).
	PORT_PCR29_LK_Pos    = 0xf       // Position of LK field.
	PORT_PCR29_LK_Msk    = 0x8000    // Bit mask of LK field.
	PORT_PCR29_LK        = 0x8000    // Bit LK.
	PORT_PCR29_LK_0      = 0x0       // Pin Control Register fields [15:0] are not locked.
	PORT_PCR29_LK_1      = 0x1       // Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
	PORT_PCR29_IRQC_Pos  = 0x10      // Position of IRQC field.
	PORT_PCR29_IRQC_Msk  = 0xf0000   // Bit mask of IRQC field.
	PORT_PCR29_IRQC_0000 = 0x0       // Interrupt/DMA request disabled.
	PORT_PCR29_IRQC_0001 = 0x1       // DMA request on rising edge.
	PORT_PCR29_IRQC_0010 = 0x2       // DMA request on falling edge.
	PORT_PCR29_IRQC_0011 = 0x3       // DMA request on either edge.
	PORT_PCR29_IRQC_1000 = 0x8       // Interrupt when logic 0.
	PORT_PCR29_IRQC_1001 = 0x9       // Interrupt on rising-edge.
	PORT_PCR29_IRQC_1010 = 0xa       // Interrupt on falling-edge.
	PORT_PCR29_IRQC_1011 = 0xb       // Interrupt on either edge.
	PORT_PCR29_IRQC_1100 = 0xc       // Interrupt when logic 1.
	PORT_PCR29_ISF_Pos   = 0x18      // Position of ISF field.
	PORT_PCR29_ISF_Msk   = 0x1000000 // Bit mask of ISF field.
	PORT_PCR29_ISF       = 0x1000000 // Bit ISF.
	PORT_PCR29_ISF_0     = 0x0       // Configured interrupt is not detected.
	PORT_PCR29_ISF_1     = 0x1       // Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

	// PCR30: Pin Control Register n
	PORT_PCR30_PS_Pos    = 0x0       // Position of PS field.
	PORT_PCR30_PS_Msk    = 0x1       // Bit mask of PS field.
	PORT_PCR30_PS        = 0x1       // Bit PS.
	PORT_PCR30_PS_0      = 0x0       // Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR30_PS_1      = 0x1       // Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR30_PE_Pos    = 0x1       // Position of PE field.
	PORT_PCR30_PE_Msk    = 0x2       // Bit mask of PE field.
	PORT_PCR30_PE        = 0x2       // Bit PE.
	PORT_PCR30_PE_0      = 0x0       // Internal pullup or pulldown resistor is not enabled on the corresponding pin.
	PORT_PCR30_PE_1      = 0x1       // Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
	PORT_PCR30_SRE_Pos   = 0x2       // Position of SRE field.
	PORT_PCR30_SRE_Msk   = 0x4       // Bit mask of SRE field.
	PORT_PCR30_SRE       = 0x4       // Bit SRE.
	PORT_PCR30_SRE_0     = 0x0       // Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR30_SRE_1     = 0x1       // Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR30_PFE_Pos   = 0x4       // Position of PFE field.
	PORT_PCR30_PFE_Msk   = 0x10      // Bit mask of PFE field.
	PORT_PCR30_PFE       = 0x10      // Bit PFE.
	PORT_PCR30_PFE_0     = 0x0       // Passive input filter is disabled on the corresponding pin.
	PORT_PCR30_PFE_1     = 0x1       // Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
	PORT_PCR30_ODE_Pos   = 0x5       // Position of ODE field.
	PORT_PCR30_ODE_Msk   = 0x20      // Bit mask of ODE field.
	PORT_PCR30_ODE       = 0x20      // Bit ODE.
	PORT_PCR30_ODE_0     = 0x0       // Open drain output is disabled on the corresponding pin.
	PORT_PCR30_ODE_1     = 0x1       // Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR30_DSE_Pos   = 0x6       // Position of DSE field.
	PORT_PCR30_DSE_Msk   = 0x40      // Bit mask of DSE field.
	PORT_PCR30_DSE       = 0x40      // Bit DSE.
	PORT_PCR30_DSE_0     = 0x0       // Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR30_DSE_1     = 0x1       // High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR30_MUX_Pos   = 0x8       // Position of MUX field.
	PORT_PCR30_MUX_Msk   = 0x700     // Bit mask of MUX field.
	PORT_PCR30_MUX_000   = 0x0       // Pin disabled (analog).
	PORT_PCR30_MUX_001   = 0x1       // Alternative 1 (GPIO).
	PORT_PCR30_MUX_010   = 0x2       // Alternative 2 (chip-specific).
	PORT_PCR30_MUX_011   = 0x3       // Alternative 3 (chip-specific).
	PORT_PCR30_MUX_100   = 0x4       // Alternative 4 (chip-specific).
	PORT_PCR30_MUX_101   = 0x5       // Alternative 5 (chip-specific).
	PORT_PCR30_MUX_110   = 0x6       // Alternative 6 (chip-specific).
	PORT_PCR30_MUX_111   = 0x7       // Alternative 7 (chip-specific).
	PORT_PCR30_LK_Pos    = 0xf       // Position of LK field.
	PORT_PCR30_LK_Msk    = 0x8000    // Bit mask of LK field.
	PORT_PCR30_LK        = 0x8000    // Bit LK.
	PORT_PCR30_LK_0      = 0x0       // Pin Control Register fields [15:0] are not locked.
	PORT_PCR30_LK_1      = 0x1       // Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
	PORT_PCR30_IRQC_Pos  = 0x10      // Position of IRQC field.
	PORT_PCR30_IRQC_Msk  = 0xf0000   // Bit mask of IRQC field.
	PORT_PCR30_IRQC_0000 = 0x0       // Interrupt/DMA request disabled.
	PORT_PCR30_IRQC_0001 = 0x1       // DMA request on rising edge.
	PORT_PCR30_IRQC_0010 = 0x2       // DMA request on falling edge.
	PORT_PCR30_IRQC_0011 = 0x3       // DMA request on either edge.
	PORT_PCR30_IRQC_1000 = 0x8       // Interrupt when logic 0.
	PORT_PCR30_IRQC_1001 = 0x9       // Interrupt on rising-edge.
	PORT_PCR30_IRQC_1010 = 0xa       // Interrupt on falling-edge.
	PORT_PCR30_IRQC_1011 = 0xb       // Interrupt on either edge.
	PORT_PCR30_IRQC_1100 = 0xc       // Interrupt when logic 1.
	PORT_PCR30_ISF_Pos   = 0x18      // Position of ISF field.
	PORT_PCR30_ISF_Msk   = 0x1000000 // Bit mask of ISF field.
	PORT_PCR30_ISF       = 0x1000000 // Bit ISF.
	PORT_PCR30_ISF_0     = 0x0       // Configured interrupt is not detected.
	PORT_PCR30_ISF_1     = 0x1       // Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

	// PCR31: Pin Control Register n
	PORT_PCR31_PS_Pos    = 0x0       // Position of PS field.
	PORT_PCR31_PS_Msk    = 0x1       // Bit mask of PS field.
	PORT_PCR31_PS        = 0x1       // Bit PS.
	PORT_PCR31_PS_0      = 0x0       // Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR31_PS_1      = 0x1       // Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
	PORT_PCR31_PE_Pos    = 0x1       // Position of PE field.
	PORT_PCR31_PE_Msk    = 0x2       // Bit mask of PE field.
	PORT_PCR31_PE        = 0x2       // Bit PE.
	PORT_PCR31_PE_0      = 0x0       // Internal pullup or pulldown resistor is not enabled on the corresponding pin.
	PORT_PCR31_PE_1      = 0x1       // Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
	PORT_PCR31_SRE_Pos   = 0x2       // Position of SRE field.
	PORT_PCR31_SRE_Msk   = 0x4       // Bit mask of SRE field.
	PORT_PCR31_SRE       = 0x4       // Bit SRE.
	PORT_PCR31_SRE_0     = 0x0       // Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR31_SRE_1     = 0x1       // Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR31_PFE_Pos   = 0x4       // Position of PFE field.
	PORT_PCR31_PFE_Msk   = 0x10      // Bit mask of PFE field.
	PORT_PCR31_PFE       = 0x10      // Bit PFE.
	PORT_PCR31_PFE_0     = 0x0       // Passive input filter is disabled on the corresponding pin.
	PORT_PCR31_PFE_1     = 0x1       // Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
	PORT_PCR31_ODE_Pos   = 0x5       // Position of ODE field.
	PORT_PCR31_ODE_Msk   = 0x20      // Bit mask of ODE field.
	PORT_PCR31_ODE       = 0x20      // Bit ODE.
	PORT_PCR31_ODE_0     = 0x0       // Open drain output is disabled on the corresponding pin.
	PORT_PCR31_ODE_1     = 0x1       // Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
	PORT_PCR31_DSE_Pos   = 0x6       // Position of DSE field.
	PORT_PCR31_DSE_Msk   = 0x40      // Bit mask of DSE field.
	PORT_PCR31_DSE       = 0x40      // Bit DSE.
	PORT_PCR31_DSE_0     = 0x0       // Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR31_DSE_1     = 0x1       // High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
	PORT_PCR31_MUX_Pos   = 0x8       // Position of MUX field.
	PORT_PCR31_MUX_Msk   = 0x700     // Bit mask of MUX field.
	PORT_PCR31_MUX_000   = 0x0       // Pin disabled (analog).
	PORT_PCR31_MUX_001   = 0x1       // Alternative 1 (GPIO).
	PORT_PCR31_MUX_010   = 0x2       // Alternative 2 (chip-specific).
	PORT_PCR31_MUX_011   = 0x3       // Alternative 3 (chip-specific).
	PORT_PCR31_MUX_100   = 0x4       // Alternative 4 (chip-specific).
	PORT_PCR31_MUX_101   = 0x5       // Alternative 5 (chip-specific).
	PORT_PCR31_MUX_110   = 0x6       // Alternative 6 (chip-specific).
	PORT_PCR31_MUX_111   = 0x7       // Alternative 7 (chip-specific).
	PORT_PCR31_LK_Pos    = 0xf       // Position of LK field.
	PORT_PCR31_LK_Msk    = 0x8000    // Bit mask of LK field.
	PORT_PCR31_LK        = 0x8000    // Bit LK.
	PORT_PCR31_LK_0      = 0x0       // Pin Control Register fields [15:0] are not locked.
	PORT_PCR31_LK_1      = 0x1       // Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
	PORT_PCR31_IRQC_Pos  = 0x10      // Position of IRQC field.
	PORT_PCR31_IRQC_Msk  = 0xf0000   // Bit mask of IRQC field.
	PORT_PCR31_IRQC_0000 = 0x0       // Interrupt/DMA request disabled.
	PORT_PCR31_IRQC_0001 = 0x1       // DMA request on rising edge.
	PORT_PCR31_IRQC_0010 = 0x2       // DMA request on falling edge.
	PORT_PCR31_IRQC_0011 = 0x3       // DMA request on either edge.
	PORT_PCR31_IRQC_1000 = 0x8       // Interrupt when logic 0.
	PORT_PCR31_IRQC_1001 = 0x9       // Interrupt on rising-edge.
	PORT_PCR31_IRQC_1010 = 0xa       // Interrupt on falling-edge.
	PORT_PCR31_IRQC_1011 = 0xb       // Interrupt on either edge.
	PORT_PCR31_IRQC_1100 = 0xc       // Interrupt when logic 1.
	PORT_PCR31_ISF_Pos   = 0x18      // Position of ISF field.
	PORT_PCR31_ISF_Msk   = 0x1000000 // Bit mask of ISF field.
	PORT_PCR31_ISF       = 0x1000000 // Bit ISF.
	PORT_PCR31_ISF_0     = 0x0       // Configured interrupt is not detected.
	PORT_PCR31_ISF_1     = 0x1       // Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.

	// GPCLR: Global Pin Control Low Register
	PORT_GPCLR_GPWD_Pos = 0x0        // Position of GPWD field.
	PORT_GPCLR_GPWD_Msk = 0xffff     // Bit mask of GPWD field.
	PORT_GPCLR_GPWE_Pos = 0x10       // Position of GPWE field.
	PORT_GPCLR_GPWE_Msk = 0xffff0000 // Bit mask of GPWE field.
	PORT_GPCLR_GPWE_0   = 0x0        // Corresponding Pin Control Register is not updated with the value in GPWD.
	PORT_GPCLR_GPWE_1   = 0x1        // Corresponding Pin Control Register is updated with the value in GPWD.

	// GPCHR: Global Pin Control High Register
	PORT_GPCHR_GPWD_Pos = 0x0        // Position of GPWD field.
	PORT_GPCHR_GPWD_Msk = 0xffff     // Bit mask of GPWD field.
	PORT_GPCHR_GPWE_Pos = 0x10       // Position of GPWE field.
	PORT_GPCHR_GPWE_Msk = 0xffff0000 // Bit mask of GPWE field.
	PORT_GPCHR_GPWE_0   = 0x0        // Corresponding Pin Control Register is not updated with the value in GPWD.
	PORT_GPCHR_GPWE_1   = 0x1        // Corresponding Pin Control Register is updated with the value in GPWD.

	// ISFR: Interrupt Status Flag Register
	PORT_ISFR_ISF_Pos = 0x0        // Position of ISF field.
	PORT_ISFR_ISF_Msk = 0xffffffff // Bit mask of ISF field.
	PORT_ISFR_ISF_0   = 0x0        // Configured interrupt is not detected.
	PORT_ISFR_ISF_1   = 0x1        // Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
)

// Bitfields for WDOG: Generation 2008 Watchdog Timer
const (
	// STCTRLH: Watchdog Status and Control Register High
	WDOG_STCTRLH_WDOGEN_Pos      = 0x0    // Position of WDOGEN field.
	WDOG_STCTRLH_WDOGEN_Msk      = 0x1    // Bit mask of WDOGEN field.
	WDOG_STCTRLH_WDOGEN          = 0x1    // Bit WDOGEN.
	WDOG_STCTRLH_WDOGEN_0        = 0x0    // WDOG is disabled.
	WDOG_STCTRLH_WDOGEN_1        = 0x1    // WDOG is enabled.
	WDOG_STCTRLH_CLKSRC_Pos      = 0x1    // Position of CLKSRC field.
	WDOG_STCTRLH_CLKSRC_Msk      = 0x2    // Bit mask of CLKSRC field.
	WDOG_STCTRLH_CLKSRC          = 0x2    // Bit CLKSRC.
	WDOG_STCTRLH_CLKSRC_0        = 0x0    // WDOG clock sourced from LPO .
	WDOG_STCTRLH_CLKSRC_1        = 0x1    // WDOG clock sourced from alternate clock source.
	WDOG_STCTRLH_IRQRSTEN_Pos    = 0x2    // Position of IRQRSTEN field.
	WDOG_STCTRLH_IRQRSTEN_Msk    = 0x4    // Bit mask of IRQRSTEN field.
	WDOG_STCTRLH_IRQRSTEN        = 0x4    // Bit IRQRSTEN.
	WDOG_STCTRLH_IRQRSTEN_0      = 0x0    // WDOG time-out generates reset only.
	WDOG_STCTRLH_IRQRSTEN_1      = 0x1    // WDOG time-out initially generates an interrupt. After WCT, it generates a reset.
	WDOG_STCTRLH_WINEN_Pos       = 0x3    // Position of WINEN field.
	WDOG_STCTRLH_WINEN_Msk       = 0x8    // Bit mask of WINEN field.
	WDOG_STCTRLH_WINEN           = 0x8    // Bit WINEN.
	WDOG_STCTRLH_WINEN_0         = 0x0    // Windowing mode is disabled.
	WDOG_STCTRLH_WINEN_1         = 0x1    // Windowing mode is enabled.
	WDOG_STCTRLH_ALLOWUPDATE_Pos = 0x4    // Position of ALLOWUPDATE field.
	WDOG_STCTRLH_ALLOWUPDATE_Msk = 0x10   // Bit mask of ALLOWUPDATE field.
	WDOG_STCTRLH_ALLOWUPDATE     = 0x10   // Bit ALLOWUPDATE.
	WDOG_STCTRLH_ALLOWUPDATE_0   = 0x0    // No further updates allowed to WDOG write-once registers.
	WDOG_STCTRLH_ALLOWUPDATE_1   = 0x1    // WDOG write-once registers can be unlocked for updating.
	WDOG_STCTRLH_DBGEN_Pos       = 0x5    // Position of DBGEN field.
	WDOG_STCTRLH_DBGEN_Msk       = 0x20   // Bit mask of DBGEN field.
	WDOG_STCTRLH_DBGEN           = 0x20   // Bit DBGEN.
	WDOG_STCTRLH_DBGEN_0         = 0x0    // WDOG is disabled in CPU Debug mode.
	WDOG_STCTRLH_DBGEN_1         = 0x1    // WDOG is enabled in CPU Debug mode.
	WDOG_STCTRLH_STOPEN_Pos      = 0x6    // Position of STOPEN field.
	WDOG_STCTRLH_STOPEN_Msk      = 0x40   // Bit mask of STOPEN field.
	WDOG_STCTRLH_STOPEN          = 0x40   // Bit STOPEN.
	WDOG_STCTRLH_STOPEN_0        = 0x0    // WDOG is disabled in CPU Stop mode.
	WDOG_STCTRLH_STOPEN_1        = 0x1    // WDOG is enabled in CPU Stop mode.
	WDOG_STCTRLH_WAITEN_Pos      = 0x7    // Position of WAITEN field.
	WDOG_STCTRLH_WAITEN_Msk      = 0x80   // Bit mask of WAITEN field.
	WDOG_STCTRLH_WAITEN          = 0x80   // Bit WAITEN.
	WDOG_STCTRLH_WAITEN_0        = 0x0    // WDOG is disabled in CPU Wait mode.
	WDOG_STCTRLH_WAITEN_1        = 0x1    // WDOG is enabled in CPU Wait mode.
	WDOG_STCTRLH_TESTWDOG_Pos    = 0xa    // Position of TESTWDOG field.
	WDOG_STCTRLH_TESTWDOG_Msk    = 0x400  // Bit mask of TESTWDOG field.
	WDOG_STCTRLH_TESTWDOG        = 0x400  // Bit TESTWDOG.
	WDOG_STCTRLH_TESTSEL_Pos     = 0xb    // Position of TESTSEL field.
	WDOG_STCTRLH_TESTSEL_Msk     = 0x800  // Bit mask of TESTSEL field.
	WDOG_STCTRLH_TESTSEL         = 0x800  // Bit TESTSEL.
	WDOG_STCTRLH_TESTSEL_0       = 0x0    // Quick test. The timer runs in normal operation. You can load a small time-out value to do a quick test.
	WDOG_STCTRLH_TESTSEL_1       = 0x1    // Byte test. Puts the timer in the byte test mode where individual bytes of the timer are enabled for operation and are compared for time-out against the corresponding byte of the programmed time-out value. Select the byte through BYTESEL[1:0] for testing.
	WDOG_STCTRLH_BYTESEL_Pos     = 0xc    // Position of BYTESEL field.
	WDOG_STCTRLH_BYTESEL_Msk     = 0x3000 // Bit mask of BYTESEL field.
	WDOG_STCTRLH_BYTESEL_00      = 0x0    // Byte 0 selected
	WDOG_STCTRLH_BYTESEL_01      = 0x1    // Byte 1 selected
	WDOG_STCTRLH_BYTESEL_10      = 0x2    // Byte 2 selected
	WDOG_STCTRLH_BYTESEL_11      = 0x3    // Byte 3 selected
	WDOG_STCTRLH_DISTESTWDOG_Pos = 0xe    // Position of DISTESTWDOG field.
	WDOG_STCTRLH_DISTESTWDOG_Msk = 0x4000 // Bit mask of DISTESTWDOG field.
	WDOG_STCTRLH_DISTESTWDOG     = 0x4000 // Bit DISTESTWDOG.
	WDOG_STCTRLH_DISTESTWDOG_0   = 0x0    // WDOG functional test mode is not disabled.
	WDOG_STCTRLH_DISTESTWDOG_1   = 0x1    // WDOG functional test mode is disabled permanently until reset.

	// STCTRLL: Watchdog Status and Control Register Low
	WDOG_STCTRLL_INTFLG_Pos = 0xf    // Position of INTFLG field.
	WDOG_STCTRLL_INTFLG_Msk = 0x8000 // Bit mask of INTFLG field.
	WDOG_STCTRLL_INTFLG     = 0x8000 // Bit INTFLG.

	// TOVALH: Watchdog Time-out Value Register High
	WDOG_TOVALH_TOVALHIGH_Pos = 0x0    // Position of TOVALHIGH field.
	WDOG_TOVALH_TOVALHIGH_Msk = 0xffff // Bit mask of TOVALHIGH field.

	// TOVALL: Watchdog Time-out Value Register Low
	WDOG_TOVALL_TOVALLOW_Pos = 0x0    // Position of TOVALLOW field.
	WDOG_TOVALL_TOVALLOW_Msk = 0xffff // Bit mask of TOVALLOW field.

	// WINH: Watchdog Window Register High
	WDOG_WINH_WINHIGH_Pos = 0x0    // Position of WINHIGH field.
	WDOG_WINH_WINHIGH_Msk = 0xffff // Bit mask of WINHIGH field.

	// WINL: Watchdog Window Register Low
	WDOG_WINL_WINLOW_Pos = 0x0    // Position of WINLOW field.
	WDOG_WINL_WINLOW_Msk = 0xffff // Bit mask of WINLOW field.

	// REFRESH: Watchdog Refresh register
	WDOG_REFRESH_WDOGREFRESH_Pos = 0x0    // Position of WDOGREFRESH field.
	WDOG_REFRESH_WDOGREFRESH_Msk = 0xffff // Bit mask of WDOGREFRESH field.

	// UNLOCK: Watchdog Unlock register
	WDOG_UNLOCK_WDOGUNLOCK_Pos = 0x0    // Position of WDOGUNLOCK field.
	WDOG_UNLOCK_WDOGUNLOCK_Msk = 0xffff // Bit mask of WDOGUNLOCK field.

	// TMROUTH: Watchdog Timer Output Register High
	WDOG_TMROUTH_TIMEROUTHIGH_Pos = 0x0    // Position of TIMEROUTHIGH field.
	WDOG_TMROUTH_TIMEROUTHIGH_Msk = 0xffff // Bit mask of TIMEROUTHIGH field.

	// TMROUTL: Watchdog Timer Output Register Low
	WDOG_TMROUTL_TIMEROUTLOW_Pos = 0x0    // Position of TIMEROUTLOW field.
	WDOG_TMROUTL_TIMEROUTLOW_Msk = 0xffff // Bit mask of TIMEROUTLOW field.

	// RSTCNT: Watchdog Reset Count register
	WDOG_RSTCNT_RSTCNT_Pos = 0x0    // Position of RSTCNT field.
	WDOG_RSTCNT_RSTCNT_Msk = 0xffff // Bit mask of RSTCNT field.

	// PRESC: Watchdog Prescaler register
	WDOG_PRESC_PRESCVAL_Pos = 0x8   // Position of PRESCVAL field.
	WDOG_PRESC_PRESCVAL_Msk = 0x700 // Bit mask of PRESCVAL field.
)

// Bitfields for EWM: External Watchdog Monitor
const (
	// CTRL: Control Register
	EWM_CTRL_EWMEN_Pos = 0x0 // Position of EWMEN field.
	EWM_CTRL_EWMEN_Msk = 0x1 // Bit mask of EWMEN field.
	EWM_CTRL_EWMEN     = 0x1 // Bit EWMEN.
	EWM_CTRL_ASSIN_Pos = 0x1 // Position of ASSIN field.
	EWM_CTRL_ASSIN_Msk = 0x2 // Bit mask of ASSIN field.
	EWM_CTRL_ASSIN     = 0x2 // Bit ASSIN.
	EWM_CTRL_INEN_Pos  = 0x2 // Position of INEN field.
	EWM_CTRL_INEN_Msk  = 0x4 // Bit mask of INEN field.
	EWM_CTRL_INEN      = 0x4 // Bit INEN.
	EWM_CTRL_INTEN_Pos = 0x3 // Position of INTEN field.
	EWM_CTRL_INTEN_Msk = 0x8 // Bit mask of INTEN field.
	EWM_CTRL_INTEN     = 0x8 // Bit INTEN.

	// SERV: Service Register
	EWM_SERV_SERVICE_Pos = 0x0  // Position of SERVICE field.
	EWM_SERV_SERVICE_Msk = 0xff // Bit mask of SERVICE field.

	// CMPL: Compare Low Register
	EWM_CMPL_COMPAREL_Pos = 0x0  // Position of COMPAREL field.
	EWM_CMPL_COMPAREL_Msk = 0xff // Bit mask of COMPAREL field.

	// CMPH: Compare High Register
	EWM_CMPH_COMPAREH_Pos = 0x0  // Position of COMPAREH field.
	EWM_CMPH_COMPAREH_Msk = 0xff // Bit mask of COMPAREH field.

	// CLKPRESCALER: Clock Prescaler Register
	EWM_CLKPRESCALER_CLK_DIV_Pos = 0x0  // Position of CLK_DIV field.
	EWM_CLKPRESCALER_CLK_DIV_Msk = 0xff // Bit mask of CLK_DIV field.
)

// Bitfields for MCG: Multipurpose Clock Generator module
const (
	// C1: MCG Control 1 Register
	MCG_C1_IREFSTEN_Pos = 0x0  // Position of IREFSTEN field.
	MCG_C1_IREFSTEN_Msk = 0x1  // Bit mask of IREFSTEN field.
	MCG_C1_IREFSTEN     = 0x1  // Bit IREFSTEN.
	MCG_C1_IREFSTEN_0   = 0x0  // Internal reference clock is disabled in Stop mode.
	MCG_C1_IREFSTEN_1   = 0x1  // Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode.
	MCG_C1_IRCLKEN_Pos  = 0x1  // Position of IRCLKEN field.
	MCG_C1_IRCLKEN_Msk  = 0x2  // Bit mask of IRCLKEN field.
	MCG_C1_IRCLKEN      = 0x2  // Bit IRCLKEN.
	MCG_C1_IRCLKEN_0    = 0x0  // MCGIRCLK inactive.
	MCG_C1_IRCLKEN_1    = 0x1  // MCGIRCLK active.
	MCG_C1_IREFS_Pos    = 0x2  // Position of IREFS field.
	MCG_C1_IREFS_Msk    = 0x4  // Bit mask of IREFS field.
	MCG_C1_IREFS        = 0x4  // Bit IREFS.
	MCG_C1_IREFS_0      = 0x0  // External reference clock is selected.
	MCG_C1_IREFS_1      = 0x1  // The slow internal reference clock is selected.
	MCG_C1_FRDIV_Pos    = 0x3  // Position of FRDIV field.
	MCG_C1_FRDIV_Msk    = 0x38 // Bit mask of FRDIV field.
	MCG_C1_FRDIV_000    = 0x0  // If RANGE = 0 or OSCSEL=1 , Divide Factor is 1; for all other RANGE values, Divide Factor is 32.
	MCG_C1_FRDIV_001    = 0x1  // If RANGE = 0 or OSCSEL=1 , Divide Factor is 2; for all other RANGE values, Divide Factor is 64.
	MCG_C1_FRDIV_010    = 0x2  // If RANGE = 0 or OSCSEL=1 , Divide Factor is 4; for all other RANGE values, Divide Factor is 128.
	MCG_C1_FRDIV_011    = 0x3  // If RANGE = 0 or OSCSEL=1 , Divide Factor is 8; for all other RANGE values, Divide Factor is 256.
	MCG_C1_FRDIV_100    = 0x4  // If RANGE = 0 or OSCSEL=1 , Divide Factor is 16; for all other RANGE values, Divide Factor is 512.
	MCG_C1_FRDIV_101    = 0x5  // If RANGE = 0 or OSCSEL=1 , Divide Factor is 32; for all other RANGE values, Divide Factor is 1024.
	MCG_C1_FRDIV_110    = 0x6  // If RANGE = 0 or OSCSEL=1 , Divide Factor is 64; for all other RANGE values, Divide Factor is 1280 .
	MCG_C1_FRDIV_111    = 0x7  // If RANGE = 0 or OSCSEL=1 , Divide Factor is 128; for all other RANGE values, Divide Factor is 1536 .
	MCG_C1_CLKS_Pos     = 0x6  // Position of CLKS field.
	MCG_C1_CLKS_Msk     = 0xc0 // Bit mask of CLKS field.
	MCG_C1_CLKS_00      = 0x0  // Encoding 0 - Output of FLL or PLL is selected (depends on PLLS control bit).
	MCG_C1_CLKS_01      = 0x1  // Encoding 1 - Internal reference clock is selected.
	MCG_C1_CLKS_10      = 0x2  // Encoding 2 - External reference clock is selected.
	MCG_C1_CLKS_11      = 0x3  // Encoding 3 - Reserved.

	// C2: MCG Control 2 Register
	MCG_C2_IRCS_Pos    = 0x0  // Position of IRCS field.
	MCG_C2_IRCS_Msk    = 0x1  // Bit mask of IRCS field.
	MCG_C2_IRCS        = 0x1  // Bit IRCS.
	MCG_C2_IRCS_0      = 0x0  // Slow internal reference clock selected.
	MCG_C2_IRCS_1      = 0x1  // Fast internal reference clock selected.
	MCG_C2_LP_Pos      = 0x1  // Position of LP field.
	MCG_C2_LP_Msk      = 0x2  // Bit mask of LP field.
	MCG_C2_LP          = 0x2  // Bit LP.
	MCG_C2_LP_0        = 0x0  // FLL or PLL is not disabled in bypass modes.
	MCG_C2_LP_1        = 0x1  // FLL or PLL is disabled in bypass modes (lower power)
	MCG_C2_EREFS_Pos   = 0x2  // Position of EREFS field.
	MCG_C2_EREFS_Msk   = 0x4  // Bit mask of EREFS field.
	MCG_C2_EREFS       = 0x4  // Bit EREFS.
	MCG_C2_EREFS_0     = 0x0  // External reference clock requested.
	MCG_C2_EREFS_1     = 0x1  // Oscillator requested.
	MCG_C2_HGO_Pos     = 0x3  // Position of HGO field.
	MCG_C2_HGO_Msk     = 0x8  // Bit mask of HGO field.
	MCG_C2_HGO         = 0x8  // Bit HGO.
	MCG_C2_HGO_0       = 0x0  // Configure crystal oscillator for low-power operation.
	MCG_C2_HGO_1       = 0x1  // Configure crystal oscillator for high-gain operation.
	MCG_C2_RANGE_Pos   = 0x4  // Position of RANGE field.
	MCG_C2_RANGE_Msk   = 0x30 // Bit mask of RANGE field.
	MCG_C2_RANGE_00    = 0x0  // Encoding 0 - Low frequency range selected for the crystal oscillator .
	MCG_C2_RANGE_01    = 0x1  // Encoding 1 - High frequency range selected for the crystal oscillator .
	MCG_C2_FCFTRIM_Pos = 0x6  // Position of FCFTRIM field.
	MCG_C2_FCFTRIM_Msk = 0x40 // Bit mask of FCFTRIM field.
	MCG_C2_FCFTRIM     = 0x40 // Bit FCFTRIM.
	MCG_C2_LOCRE0_Pos  = 0x7  // Position of LOCRE0 field.
	MCG_C2_LOCRE0_Msk  = 0x80 // Bit mask of LOCRE0 field.
	MCG_C2_LOCRE0      = 0x80 // Bit LOCRE0.
	MCG_C2_LOCRE0_0    = 0x0  // Interrupt request is generated on a loss of OSC0 external reference clock.
	MCG_C2_LOCRE0_1    = 0x1  // Generate a reset request on a loss of OSC0 external reference clock.

	// C3: MCG Control 3 Register
	MCG_C3_SCTRIM_Pos = 0x0  // Position of SCTRIM field.
	MCG_C3_SCTRIM_Msk = 0xff // Bit mask of SCTRIM field.

	// C4: MCG Control 4 Register
	MCG_C4_SCFTRIM_Pos  = 0x0  // Position of SCFTRIM field.
	MCG_C4_SCFTRIM_Msk  = 0x1  // Bit mask of SCFTRIM field.
	MCG_C4_SCFTRIM      = 0x1  // Bit SCFTRIM.
	MCG_C4_FCTRIM_Pos   = 0x1  // Position of FCTRIM field.
	MCG_C4_FCTRIM_Msk   = 0x1e // Bit mask of FCTRIM field.
	MCG_C4_DRST_DRS_Pos = 0x5  // Position of DRST_DRS field.
	MCG_C4_DRST_DRS_Msk = 0x60 // Bit mask of DRST_DRS field.
	MCG_C4_DRST_DRS_00  = 0x0  // Encoding 0 - Low range (reset default).
	MCG_C4_DRST_DRS_01  = 0x1  // Encoding 1 - Mid range.
	MCG_C4_DRST_DRS_10  = 0x2  // Encoding 2 - Mid-high range.
	MCG_C4_DRST_DRS_11  = 0x3  // Encoding 3 - High range.
	MCG_C4_DMX32_Pos    = 0x7  // Position of DMX32 field.
	MCG_C4_DMX32_Msk    = 0x80 // Bit mask of DMX32 field.
	MCG_C4_DMX32        = 0x80 // Bit DMX32.
	MCG_C4_DMX32_0      = 0x0  // DCO has a default range of 25%.
	MCG_C4_DMX32_1      = 0x1  // DCO is fine-tuned for maximum frequency with 32.768 kHz reference.

	// C5: MCG Control 5 Register
	MCG_C5_PRDIV0_Pos    = 0x0  // Position of PRDIV0 field.
	MCG_C5_PRDIV0_Msk    = 0x1f // Bit mask of PRDIV0 field.
	MCG_C5_PRDIV0_0      = 0x0  // Divide Factor is 1
	MCG_C5_PRDIV0_1      = 0x1  // Divide Factor is 2
	MCG_C5_PRDIV0_2      = 0x2  // Divide Factor is 3
	MCG_C5_PRDIV0_3      = 0x3  // Divide Factor is 4
	MCG_C5_PRDIV0_4      = 0x4  // Divide Factor is 5
	MCG_C5_PRDIV0_5      = 0x5  // Divide Factor is 6
	MCG_C5_PRDIV0_6      = 0x6  // Divide Factor is 7
	MCG_C5_PRDIV0_7      = 0x7  // Divide Factor is 8
	MCG_C5_PRDIV0_8      = 0x8  // Divide Factor is 9
	MCG_C5_PRDIV0_9      = 0x9  // Divide Factor is 10
	MCG_C5_PRDIV0_10     = 0xa  // Divide Factor is 11
	MCG_C5_PRDIV0_11     = 0xb  // Divide Factor is 12
	MCG_C5_PRDIV0_12     = 0xc  // Divide Factor is 13
	MCG_C5_PRDIV0_13     = 0xd  // Divide Factor is 14
	MCG_C5_PRDIV0_14     = 0xe  // Divide Factor is 15
	MCG_C5_PRDIV0_15     = 0xf  // Divide Factor is 16
	MCG_C5_PRDIV0_16     = 0x10 // Divide Factor is 17
	MCG_C5_PRDIV0_17     = 0x11 // Divide Factor is 18
	MCG_C5_PRDIV0_18     = 0x12 // Divide Factor is 19
	MCG_C5_PRDIV0_19     = 0x13 // Divide Factor is 20
	MCG_C5_PRDIV0_20     = 0x14 // Divide Factor is 21
	MCG_C5_PRDIV0_21     = 0x15 // Divide Factor is 22
	MCG_C5_PRDIV0_22     = 0x16 // Divide Factor is 23
	MCG_C5_PRDIV0_23     = 0x17 // Divide Factor is 24
	MCG_C5_PRDIV0_24     = 0x18 // Divide Factor is 25
	MCG_C5_PRDIV0_25     = 0x19 // Divide Factor is 26
	MCG_C5_PRDIV0_26     = 0x1a // Divide Factor is 27
	MCG_C5_PRDIV0_27     = 0x1b // Divide Factor is 28
	MCG_C5_PRDIV0_28     = 0x1c // Divide Factor is 29
	MCG_C5_PRDIV0_29     = 0x1d // Divide Factor is 30
	MCG_C5_PRDIV0_30     = 0x1e // Divide Factor is 31
	MCG_C5_PRDIV0_31     = 0x1f // Divide Factor is 32
	MCG_C5_PLLSTEN0_Pos  = 0x5  // Position of PLLSTEN0 field.
	MCG_C5_PLLSTEN0_Msk  = 0x20 // Bit mask of PLLSTEN0 field.
	MCG_C5_PLLSTEN0      = 0x20 // Bit PLLSTEN0.
	MCG_C5_PLLSTEN0_0    = 0x0  // MCGPLLCLK is disabled in any of the Stop modes.
	MCG_C5_PLLSTEN0_1    = 0x1  // MCGPLLCLK is enabled if system is in Normal Stop mode.
	MCG_C5_PLLCLKEN0_Pos = 0x6  // Position of PLLCLKEN0 field.
	MCG_C5_PLLCLKEN0_Msk = 0x40 // Bit mask of PLLCLKEN0 field.
	MCG_C5_PLLCLKEN0     = 0x40 // Bit PLLCLKEN0.
	MCG_C5_PLLCLKEN0_0   = 0x0  // MCGPLLCLK is inactive.
	MCG_C5_PLLCLKEN0_1   = 0x1  // MCGPLLCLK is active.

	// C6: MCG Control 6 Register
	MCG_C6_VDIV0_Pos  = 0x0  // Position of VDIV0 field.
	MCG_C6_VDIV0_Msk  = 0x1f // Bit mask of VDIV0 field.
	MCG_C6_VDIV0_0    = 0x0  // Multiply Factor is 24
	MCG_C6_VDIV0_1    = 0x1  // Multiply Factor is 25
	MCG_C6_VDIV0_2    = 0x2  // Multiply Factor is 26
	MCG_C6_VDIV0_3    = 0x3  // Multiply Factor is 27
	MCG_C6_VDIV0_4    = 0x4  // Multiply Factor is 28
	MCG_C6_VDIV0_5    = 0x5  // Multiply Factor is 29
	MCG_C6_VDIV0_6    = 0x6  // Multiply Factor is 30
	MCG_C6_VDIV0_7    = 0x7  // Multiply Factor is 31
	MCG_C6_VDIV0_8    = 0x8  // Multiply Factor is 32
	MCG_C6_VDIV0_9    = 0x9  // Multiply Factor is 33
	MCG_C6_VDIV0_10   = 0xa  // Multiply Factor is 34
	MCG_C6_VDIV0_11   = 0xb  // Multiply Factor is 35
	MCG_C6_VDIV0_12   = 0xc  // Multiply Factor is 36
	MCG_C6_VDIV0_13   = 0xd  // Multiply Factor is 37
	MCG_C6_VDIV0_14   = 0xe  // Multiply Factor is 38
	MCG_C6_VDIV0_15   = 0xf  // Multiply Factor is 39
	MCG_C6_VDIV0_16   = 0x10 // Multiply Factor is 40
	MCG_C6_VDIV0_17   = 0x11 // Multiply Factor is 41
	MCG_C6_VDIV0_18   = 0x12 // Multiply Factor is 42
	MCG_C6_VDIV0_19   = 0x13 // Multiply Factor is 43
	MCG_C6_VDIV0_20   = 0x14 // Multiply Factor is 44
	MCG_C6_VDIV0_21   = 0x15 // Multiply Factor is 45
	MCG_C6_VDIV0_22   = 0x16 // Multiply Factor is 46
	MCG_C6_VDIV0_23   = 0x17 // Multiply Factor is 47
	MCG_C6_VDIV0_24   = 0x18 // Multiply Factor is 48
	MCG_C6_VDIV0_25   = 0x19 // Multiply Factor is 49
	MCG_C6_VDIV0_26   = 0x1a // Multiply Factor is 50
	MCG_C6_VDIV0_27   = 0x1b // Multiply Factor is 51
	MCG_C6_VDIV0_28   = 0x1c // Multiply Factor is 52
	MCG_C6_VDIV0_29   = 0x1d // Multiply Factor is 53
	MCG_C6_VDIV0_30   = 0x1e // Multiply Factor is 54
	MCG_C6_VDIV0_31   = 0x1f // Multiply Factor is 55
	MCG_C6_CME0_Pos   = 0x5  // Position of CME0 field.
	MCG_C6_CME0_Msk   = 0x20 // Bit mask of CME0 field.
	MCG_C6_CME0       = 0x20 // Bit CME0.
	MCG_C6_CME0_0     = 0x0  // External clock monitor is disabled for OSC0.
	MCG_C6_CME0_1     = 0x1  // External clock monitor is enabled for OSC0.
	MCG_C6_PLLS_Pos   = 0x6  // Position of PLLS field.
	MCG_C6_PLLS_Msk   = 0x40 // Bit mask of PLLS field.
	MCG_C6_PLLS       = 0x40 // Bit PLLS.
	MCG_C6_PLLS_0     = 0x0  // FLL is selected.
	MCG_C6_PLLS_1     = 0x1  // PLL is selected (PRDIV 0 need to be programmed to the correct divider to generate a PLL reference clock in the range of 2-4 MHz prior to setting the PLLS bit).
	MCG_C6_LOLIE0_Pos = 0x7  // Position of LOLIE0 field.
	MCG_C6_LOLIE0_Msk = 0x80 // Bit mask of LOLIE0 field.
	MCG_C6_LOLIE0     = 0x80 // Bit LOLIE0.
	MCG_C6_LOLIE0_0   = 0x0  // No interrupt request is generated on loss of lock.
	MCG_C6_LOLIE0_1   = 0x1  // Generate an interrupt request on loss of lock.

	// S: MCG Status Register
	MCG_S_IRCST_Pos    = 0x0  // Position of IRCST field.
	MCG_S_IRCST_Msk    = 0x1  // Bit mask of IRCST field.
	MCG_S_IRCST        = 0x1  // Bit IRCST.
	MCG_S_IRCST_0      = 0x0  // Source of internal reference clock is the slow clock (32 kHz IRC).
	MCG_S_IRCST_1      = 0x1  // Source of internal reference clock is the fast clock (4 MHz IRC).
	MCG_S_OSCINIT0_Pos = 0x1  // Position of OSCINIT0 field.
	MCG_S_OSCINIT0_Msk = 0x2  // Bit mask of OSCINIT0 field.
	MCG_S_OSCINIT0     = 0x2  // Bit OSCINIT0.
	MCG_S_CLKST_Pos    = 0x2  // Position of CLKST field.
	MCG_S_CLKST_Msk    = 0xc  // Bit mask of CLKST field.
	MCG_S_CLKST_00     = 0x0  // Encoding 0 - Output of the FLL is selected (reset default).
	MCG_S_CLKST_01     = 0x1  // Encoding 1 - Internal reference clock is selected.
	MCG_S_CLKST_10     = 0x2  // Encoding 2 - External reference clock is selected.
	MCG_S_CLKST_11     = 0x3  // Encoding 3 - Output of the PLL is selected.
	MCG_S_IREFST_Pos   = 0x4  // Position of IREFST field.
	MCG_S_IREFST_Msk   = 0x10 // Bit mask of IREFST field.
	MCG_S_IREFST       = 0x10 // Bit IREFST.
	MCG_S_IREFST_0     = 0x0  // Source of FLL reference clock is the external reference clock.
	MCG_S_IREFST_1     = 0x1  // Source of FLL reference clock is the internal reference clock.
	MCG_S_PLLST_Pos    = 0x5  // Position of PLLST field.
	MCG_S_PLLST_Msk    = 0x20 // Bit mask of PLLST field.
	MCG_S_PLLST        = 0x20 // Bit PLLST.
	MCG_S_PLLST_0      = 0x0  // Source of PLLS clock is FLL clock.
	MCG_S_PLLST_1      = 0x1  // Source of PLLS clock is PLL output clock.
	MCG_S_LOCK0_Pos    = 0x6  // Position of LOCK0 field.
	MCG_S_LOCK0_Msk    = 0x40 // Bit mask of LOCK0 field.
	MCG_S_LOCK0        = 0x40 // Bit LOCK0.
	MCG_S_LOCK0_0      = 0x0  // PLL is currently unlocked.
	MCG_S_LOCK0_1      = 0x1  // PLL is currently locked.
	MCG_S_LOLS0_Pos    = 0x7  // Position of LOLS0 field.
	MCG_S_LOLS0_Msk    = 0x80 // Bit mask of LOLS0 field.
	MCG_S_LOLS0        = 0x80 // Bit LOLS0.
	MCG_S_LOLS0_0      = 0x0  // PLL has not lost lock since LOLS 0 was last cleared.
	MCG_S_LOLS0_1      = 0x1  // PLL has lost lock since LOLS 0 was last cleared.

	// SC: MCG Status and Control Register
	MCG_SC_LOCS0_Pos    = 0x0  // Position of LOCS0 field.
	MCG_SC_LOCS0_Msk    = 0x1  // Bit mask of LOCS0 field.
	MCG_SC_LOCS0        = 0x1  // Bit LOCS0.
	MCG_SC_LOCS0_0      = 0x0  // Loss of OSC0 has not occurred.
	MCG_SC_LOCS0_1      = 0x1  // Loss of OSC0 has occurred.
	MCG_SC_FCRDIV_Pos   = 0x1  // Position of FCRDIV field.
	MCG_SC_FCRDIV_Msk   = 0xe  // Bit mask of FCRDIV field.
	MCG_SC_FCRDIV_000   = 0x0  // Divide Factor is 1
	MCG_SC_FCRDIV_001   = 0x1  // Divide Factor is 2.
	MCG_SC_FCRDIV_010   = 0x2  // Divide Factor is 4.
	MCG_SC_FCRDIV_011   = 0x3  // Divide Factor is 8.
	MCG_SC_FCRDIV_100   = 0x4  // Divide Factor is 16
	MCG_SC_FCRDIV_101   = 0x5  // Divide Factor is 32
	MCG_SC_FCRDIV_110   = 0x6  // Divide Factor is 64
	MCG_SC_FCRDIV_111   = 0x7  // Divide Factor is 128.
	MCG_SC_FLTPRSRV_Pos = 0x4  // Position of FLTPRSRV field.
	MCG_SC_FLTPRSRV_Msk = 0x10 // Bit mask of FLTPRSRV field.
	MCG_SC_FLTPRSRV     = 0x10 // Bit FLTPRSRV.
	MCG_SC_FLTPRSRV_0   = 0x0  // FLL filter and FLL frequency will reset on changes to currect clock mode.
	MCG_SC_FLTPRSRV_1   = 0x1  // Fll filter and FLL frequency retain their previous values during new clock mode change.
	MCG_SC_ATMF_Pos     = 0x5  // Position of ATMF field.
	MCG_SC_ATMF_Msk     = 0x20 // Bit mask of ATMF field.
	MCG_SC_ATMF         = 0x20 // Bit ATMF.
	MCG_SC_ATMF_0       = 0x0  // Automatic Trim Machine completed normally.
	MCG_SC_ATMF_1       = 0x1  // Automatic Trim Machine failed.
	MCG_SC_ATMS_Pos     = 0x6  // Position of ATMS field.
	MCG_SC_ATMS_Msk     = 0x40 // Bit mask of ATMS field.
	MCG_SC_ATMS         = 0x40 // Bit ATMS.
	MCG_SC_ATMS_0       = 0x0  // 32 kHz Internal Reference Clock selected.
	MCG_SC_ATMS_1       = 0x1  // 4 MHz Internal Reference Clock selected.
	MCG_SC_ATME_Pos     = 0x7  // Position of ATME field.
	MCG_SC_ATME_Msk     = 0x80 // Bit mask of ATME field.
	MCG_SC_ATME         = 0x80 // Bit ATME.
	MCG_SC_ATME_0       = 0x0  // Auto Trim Machine disabled.
	MCG_SC_ATME_1       = 0x1  // Auto Trim Machine enabled.

	// ATCVH: MCG Auto Trim Compare Value High Register
	MCG_ATCVH_ATCVH_Pos = 0x0  // Position of ATCVH field.
	MCG_ATCVH_ATCVH_Msk = 0xff // Bit mask of ATCVH field.

	// ATCVL: MCG Auto Trim Compare Value Low Register
	MCG_ATCVL_ATCVL_Pos = 0x0  // Position of ATCVL field.
	MCG_ATCVL_ATCVL_Msk = 0xff // Bit mask of ATCVL field.

	// C7: MCG Control 7 Register
	MCG_C7_OSCSEL_Pos = 0x0 // Position of OSCSEL field.
	MCG_C7_OSCSEL_Msk = 0x3 // Bit mask of OSCSEL field.
	MCG_C7_OSCSEL_00  = 0x0 // Selects Oscillator (OSCCLK0).
	MCG_C7_OSCSEL_01  = 0x1 // Selects 32 kHz RTC Oscillator.
	MCG_C7_OSCSEL_10  = 0x2 // Selects Oscillator (OSCCLK1).

	// C8: MCG Control 8 Register
	MCG_C8_LOCS1_Pos  = 0x0  // Position of LOCS1 field.
	MCG_C8_LOCS1_Msk  = 0x1  // Bit mask of LOCS1 field.
	MCG_C8_LOCS1      = 0x1  // Bit LOCS1.
	MCG_C8_LOCS1_0    = 0x0  // Loss of RTC has not occur.
	MCG_C8_LOCS1_1    = 0x1  // Loss of RTC has occur
	MCG_C8_CME1_Pos   = 0x5  // Position of CME1 field.
	MCG_C8_CME1_Msk   = 0x20 // Bit mask of CME1 field.
	MCG_C8_CME1       = 0x20 // Bit CME1.
	MCG_C8_CME1_0     = 0x0  // External clock monitor is disabled for RTC clock.
	MCG_C8_CME1_1     = 0x1  // External clock monitor is enabled for RTC clock.
	MCG_C8_LOLRE_Pos  = 0x6  // Position of LOLRE field.
	MCG_C8_LOLRE_Msk  = 0x40 // Bit mask of LOLRE field.
	MCG_C8_LOLRE      = 0x40 // Bit LOLRE.
	MCG_C8_LOLRE_0    = 0x0  // Interrupt request is generated on a PLL loss of lock indication. The PLL loss of lock interrupt enable bit must also be set to generate the interrupt request.
	MCG_C8_LOLRE_1    = 0x1  // Generate a reset request on a PLL loss of lock indication.
	MCG_C8_LOCRE1_Pos = 0x7  // Position of LOCRE1 field.
	MCG_C8_LOCRE1_Msk = 0x80 // Bit mask of LOCRE1 field.
	MCG_C8_LOCRE1     = 0x80 // Bit LOCRE1.
	MCG_C8_LOCRE1_0   = 0x0  // Interrupt request is generated on a loss of RTC external reference clock.
	MCG_C8_LOCRE1_1   = 0x1  // Generate a reset request on a loss of RTC external reference clock
)

// Bitfields for OSC: Oscillator
const (
	// CR: OSC Control Register
	OSC_CR_SC16P_Pos    = 0x0  // Position of SC16P field.
	OSC_CR_SC16P_Msk    = 0x1  // Bit mask of SC16P field.
	OSC_CR_SC16P        = 0x1  // Bit SC16P.
	OSC_CR_SC16P_0      = 0x0  // Disable the selection.
	OSC_CR_SC16P_1      = 0x1  // Add 16 pF capacitor to the oscillator load.
	OSC_CR_SC8P_Pos     = 0x1  // Position of SC8P field.
	OSC_CR_SC8P_Msk     = 0x2  // Bit mask of SC8P field.
	OSC_CR_SC8P         = 0x2  // Bit SC8P.
	OSC_CR_SC8P_0       = 0x0  // Disable the selection.
	OSC_CR_SC8P_1       = 0x1  // Add 8 pF capacitor to the oscillator load.
	OSC_CR_SC4P_Pos     = 0x2  // Position of SC4P field.
	OSC_CR_SC4P_Msk     = 0x4  // Bit mask of SC4P field.
	OSC_CR_SC4P         = 0x4  // Bit SC4P.
	OSC_CR_SC4P_0       = 0x0  // Disable the selection.
	OSC_CR_SC4P_1       = 0x1  // Add 4 pF capacitor to the oscillator load.
	OSC_CR_SC2P_Pos     = 0x3  // Position of SC2P field.
	OSC_CR_SC2P_Msk     = 0x8  // Bit mask of SC2P field.
	OSC_CR_SC2P         = 0x8  // Bit SC2P.
	OSC_CR_SC2P_0       = 0x0  // Disable the selection.
	OSC_CR_SC2P_1       = 0x1  // Add 2 pF capacitor to the oscillator load.
	OSC_CR_EREFSTEN_Pos = 0x5  // Position of EREFSTEN field.
	OSC_CR_EREFSTEN_Msk = 0x20 // Bit mask of EREFSTEN field.
	OSC_CR_EREFSTEN     = 0x20 // Bit EREFSTEN.
	OSC_CR_EREFSTEN_0   = 0x0  // External reference clock is disabled in Stop mode.
	OSC_CR_EREFSTEN_1   = 0x1  // External reference clock stays enabled in Stop mode if ERCLKEN is set before entering Stop mode.
	OSC_CR_ERCLKEN_Pos  = 0x7  // Position of ERCLKEN field.
	OSC_CR_ERCLKEN_Msk  = 0x80 // Bit mask of ERCLKEN field.
	OSC_CR_ERCLKEN      = 0x80 // Bit ERCLKEN.
	OSC_CR_ERCLKEN_0    = 0x0  // External reference clock is inactive.
	OSC_CR_ERCLKEN_1    = 0x1  // External reference clock is enabled.

	// DIV: OSC_DIV
	OSC_DIV_ERPS_Pos = 0x6  // Position of ERPS field.
	OSC_DIV_ERPS_Msk = 0xc0 // Bit mask of ERPS field.
	OSC_DIV_ERPS_00  = 0x0  // The divisor ratio is 1.
	OSC_DIV_ERPS_01  = 0x1  // The divisor ratio is 2.
	OSC_DIV_ERPS_10  = 0x2  // The divisor ratio is 4.
	OSC_DIV_ERPS_11  = 0x3  // The divisor ratio is 8.
)

// Bitfields for I2C0: Inter-Integrated Circuit
const (
	// A1: I2C Address Register 1
	I2C_A1_AD_Pos = 0x1  // Position of AD field.
	I2C_A1_AD_Msk = 0xfe // Bit mask of AD field.

	// F: I2C Frequency Divider register
	I2C_F_ICR_Pos  = 0x0  // Position of ICR field.
	I2C_F_ICR_Msk  = 0x3f // Bit mask of ICR field.
	I2C_F_MULT_Pos = 0x6  // Position of MULT field.
	I2C_F_MULT_Msk = 0xc0 // Bit mask of MULT field.
	I2C_F_MULT_00  = 0x0  // mul = 1
	I2C_F_MULT_01  = 0x1  // mul = 2
	I2C_F_MULT_10  = 0x2  // mul = 4

	// C1: I2C Control Register 1
	I2C_C1_DMAEN_Pos = 0x0  // Position of DMAEN field.
	I2C_C1_DMAEN_Msk = 0x1  // Bit mask of DMAEN field.
	I2C_C1_DMAEN     = 0x1  // Bit DMAEN.
	I2C_C1_DMAEN_0   = 0x0  // All DMA signalling disabled.
	I2C_C1_DMAEN_1   = 0x1  // DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request: a data byte is received, and either address or data is transmitted. (ACK/NACK is automatic) the first byte received matches the A1 register or is a general call address. If any address matching occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known from master to slave, then it is not required to check S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted.
	I2C_C1_WUEN_Pos  = 0x1  // Position of WUEN field.
	I2C_C1_WUEN_Msk  = 0x2  // Bit mask of WUEN field.
	I2C_C1_WUEN      = 0x2  // Bit WUEN.
	I2C_C1_WUEN_0    = 0x0  // Normal operation. No interrupt generated when address matching in low power mode.
	I2C_C1_WUEN_1    = 0x1  // Enables the wakeup function in low power mode.
	I2C_C1_RSTA_Pos  = 0x2  // Position of RSTA field.
	I2C_C1_RSTA_Msk  = 0x4  // Bit mask of RSTA field.
	I2C_C1_RSTA      = 0x4  // Bit RSTA.
	I2C_C1_TXAK_Pos  = 0x3  // Position of TXAK field.
	I2C_C1_TXAK_Msk  = 0x8  // Bit mask of TXAK field.
	I2C_C1_TXAK      = 0x8  // Bit TXAK.
	I2C_C1_TXAK_0    = 0x0  // An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set).
	I2C_C1_TXAK_1    = 0x1  // No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set).
	I2C_C1_TX_Pos    = 0x4  // Position of TX field.
	I2C_C1_TX_Msk    = 0x10 // Bit mask of TX field.
	I2C_C1_TX        = 0x10 // Bit TX.
	I2C_C1_TX_0      = 0x0  // Receive
	I2C_C1_TX_1      = 0x1  // Transmit
	I2C_C1_MST_Pos   = 0x5  // Position of MST field.
	I2C_C1_MST_Msk   = 0x20 // Bit mask of MST field.
	I2C_C1_MST       = 0x20 // Bit MST.
	I2C_C1_MST_0     = 0x0  // Slave mode
	I2C_C1_MST_1     = 0x1  // Master mode
	I2C_C1_IICIE_Pos = 0x6  // Position of IICIE field.
	I2C_C1_IICIE_Msk = 0x40 // Bit mask of IICIE field.
	I2C_C1_IICIE     = 0x40 // Bit IICIE.
	I2C_C1_IICIE_0   = 0x0  // Disabled
	I2C_C1_IICIE_1   = 0x1  // Enabled
	I2C_C1_IICEN_Pos = 0x7  // Position of IICEN field.
	I2C_C1_IICEN_Msk = 0x80 // Bit mask of IICEN field.
	I2C_C1_IICEN     = 0x80 // Bit IICEN.
	I2C_C1_IICEN_0   = 0x0  // Disabled
	I2C_C1_IICEN_1   = 0x1  // Enabled

	// S: I2C Status register
	I2C_S_RXAK_Pos  = 0x0  // Position of RXAK field.
	I2C_S_RXAK_Msk  = 0x1  // Bit mask of RXAK field.
	I2C_S_RXAK      = 0x1  // Bit RXAK.
	I2C_S_RXAK_0    = 0x0  // Acknowledge signal was received after the completion of one byte of data transmission on the bus
	I2C_S_RXAK_1    = 0x1  // No acknowledge signal detected
	I2C_S_IICIF_Pos = 0x1  // Position of IICIF field.
	I2C_S_IICIF_Msk = 0x2  // Bit mask of IICIF field.
	I2C_S_IICIF     = 0x2  // Bit IICIF.
	I2C_S_IICIF_0   = 0x0  // No interrupt pending
	I2C_S_IICIF_1   = 0x1  // Interrupt pending
	I2C_S_SRW_Pos   = 0x2  // Position of SRW field.
	I2C_S_SRW_Msk   = 0x4  // Bit mask of SRW field.
	I2C_S_SRW       = 0x4  // Bit SRW.
	I2C_S_SRW_0     = 0x0  // Slave receive, master writing to slave
	I2C_S_SRW_1     = 0x1  // Slave transmit, master reading from slave
	I2C_S_RAM_Pos   = 0x3  // Position of RAM field.
	I2C_S_RAM_Msk   = 0x8  // Bit mask of RAM field.
	I2C_S_RAM       = 0x8  // Bit RAM.
	I2C_S_RAM_0     = 0x0  // Not addressed
	I2C_S_RAM_1     = 0x1  // Addressed as a slave
	I2C_S_ARBL_Pos  = 0x4  // Position of ARBL field.
	I2C_S_ARBL_Msk  = 0x10 // Bit mask of ARBL field.
	I2C_S_ARBL      = 0x10 // Bit ARBL.
	I2C_S_ARBL_0    = 0x0  // Standard bus operation.
	I2C_S_ARBL_1    = 0x1  // Loss of arbitration.
	I2C_S_BUSY_Pos  = 0x5  // Position of BUSY field.
	I2C_S_BUSY_Msk  = 0x20 // Bit mask of BUSY field.
	I2C_S_BUSY      = 0x20 // Bit BUSY.
	I2C_S_BUSY_0    = 0x0  // Bus is idle
	I2C_S_BUSY_1    = 0x1  // Bus is busy
	I2C_S_IAAS_Pos  = 0x6  // Position of IAAS field.
	I2C_S_IAAS_Msk  = 0x40 // Bit mask of IAAS field.
	I2C_S_IAAS      = 0x40 // Bit IAAS.
	I2C_S_IAAS_0    = 0x0  // Not addressed
	I2C_S_IAAS_1    = 0x1  // Addressed as a slave
	I2C_S_TCF_Pos   = 0x7  // Position of TCF field.
	I2C_S_TCF_Msk   = 0x80 // Bit mask of TCF field.
	I2C_S_TCF       = 0x80 // Bit TCF.
	I2C_S_TCF_0     = 0x0  // Transfer in progress
	I2C_S_TCF_1     = 0x1  // Transfer complete

	// D: I2C Data I/O register
	I2C_D_DATA_Pos = 0x0  // Position of DATA field.
	I2C_D_DATA_Msk = 0xff // Bit mask of DATA field.

	// C2: I2C Control Register 2
	I2C_C2_AD_Pos    = 0x0  // Position of AD field.
	I2C_C2_AD_Msk    = 0x7  // Bit mask of AD field.
	I2C_C2_RMEN_Pos  = 0x3  // Position of RMEN field.
	I2C_C2_RMEN_Msk  = 0x8  // Bit mask of RMEN field.
	I2C_C2_RMEN      = 0x8  // Bit RMEN.
	I2C_C2_RMEN_0    = 0x0  // Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA registers.
	I2C_C2_RMEN_1    = 0x1  // Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers.
	I2C_C2_SBRC_Pos  = 0x4  // Position of SBRC field.
	I2C_C2_SBRC_Msk  = 0x10 // Bit mask of SBRC field.
	I2C_C2_SBRC      = 0x10 // Bit SBRC.
	I2C_C2_SBRC_0    = 0x0  // The slave baud rate follows the master baud rate and clock stretching may occur
	I2C_C2_SBRC_1    = 0x1  // Slave baud rate is independent of the master baud rate
	I2C_C2_HDRS_Pos  = 0x5  // Position of HDRS field.
	I2C_C2_HDRS_Msk  = 0x20 // Bit mask of HDRS field.
	I2C_C2_HDRS      = 0x20 // Bit HDRS.
	I2C_C2_HDRS_0    = 0x0  // Normal drive mode
	I2C_C2_HDRS_1    = 0x1  // High drive mode
	I2C_C2_ADEXT_Pos = 0x6  // Position of ADEXT field.
	I2C_C2_ADEXT_Msk = 0x40 // Bit mask of ADEXT field.
	I2C_C2_ADEXT     = 0x40 // Bit ADEXT.
	I2C_C2_ADEXT_0   = 0x0  // 7-bit address scheme
	I2C_C2_ADEXT_1   = 0x1  // 10-bit address scheme
	I2C_C2_GCAEN_Pos = 0x7  // Position of GCAEN field.
	I2C_C2_GCAEN_Msk = 0x80 // Bit mask of GCAEN field.
	I2C_C2_GCAEN     = 0x80 // Bit GCAEN.
	I2C_C2_GCAEN_0   = 0x0  // Disabled
	I2C_C2_GCAEN_1   = 0x1  // Enabled

	// FLT: I2C Programmable Input Glitch Filter register
	I2C_FLT_FLT_Pos    = 0x0  // Position of FLT field.
	I2C_FLT_FLT_Msk    = 0xf  // Bit mask of FLT field.
	I2C_FLT_FLT_0      = 0x0  // No filter/bypass
	I2C_FLT_STARTF_Pos = 0x4  // Position of STARTF field.
	I2C_FLT_STARTF_Msk = 0x10 // Bit mask of STARTF field.
	I2C_FLT_STARTF     = 0x10 // Bit STARTF.
	I2C_FLT_STARTF_0   = 0x0  // No start happens on I2C bus
	I2C_FLT_STARTF_1   = 0x1  // Start detected on I2C bus
	I2C_FLT_SSIE_Pos   = 0x5  // Position of SSIE field.
	I2C_FLT_SSIE_Msk   = 0x20 // Bit mask of SSIE field.
	I2C_FLT_SSIE       = 0x20 // Bit SSIE.
	I2C_FLT_SSIE_0     = 0x0  // Stop or start detection interrupt is disabled
	I2C_FLT_SSIE_1     = 0x1  // Stop or start detection interrupt is enabled
	I2C_FLT_STOPF_Pos  = 0x6  // Position of STOPF field.
	I2C_FLT_STOPF_Msk  = 0x40 // Bit mask of STOPF field.
	I2C_FLT_STOPF      = 0x40 // Bit STOPF.
	I2C_FLT_STOPF_0    = 0x0  // No stop happens on I2C bus
	I2C_FLT_STOPF_1    = 0x1  // Stop detected on I2C bus
	I2C_FLT_SHEN_Pos   = 0x7  // Position of SHEN field.
	I2C_FLT_SHEN_Msk   = 0x80 // Bit mask of SHEN field.
	I2C_FLT_SHEN       = 0x80 // Bit SHEN.
	I2C_FLT_SHEN_0     = 0x0  // Stop holdoff is disabled. The MCU's entry to stop mode is not gated.
	I2C_FLT_SHEN_1     = 0x1  // Stop holdoff is enabled.

	// RA: I2C Range Address register
	I2C_RA_RAD_Pos = 0x1  // Position of RAD field.
	I2C_RA_RAD_Msk = 0xfe // Bit mask of RAD field.

	// SMB: I2C SMBus Control and Status register
	I2C_SMB_SHTF2IE_Pos = 0x0  // Position of SHTF2IE field.
	I2C_SMB_SHTF2IE_Msk = 0x1  // Bit mask of SHTF2IE field.
	I2C_SMB_SHTF2IE     = 0x1  // Bit SHTF2IE.
	I2C_SMB_SHTF2IE_0   = 0x0  // SHTF2 interrupt is disabled
	I2C_SMB_SHTF2IE_1   = 0x1  // SHTF2 interrupt is enabled
	I2C_SMB_SHTF2_Pos   = 0x1  // Position of SHTF2 field.
	I2C_SMB_SHTF2_Msk   = 0x2  // Bit mask of SHTF2 field.
	I2C_SMB_SHTF2       = 0x2  // Bit SHTF2.
	I2C_SMB_SHTF2_0     = 0x0  // No SCL high and SDA low timeout occurs
	I2C_SMB_SHTF2_1     = 0x1  // SCL high and SDA low timeout occurs
	I2C_SMB_SHTF1_Pos   = 0x2  // Position of SHTF1 field.
	I2C_SMB_SHTF1_Msk   = 0x4  // Bit mask of SHTF1 field.
	I2C_SMB_SHTF1       = 0x4  // Bit SHTF1.
	I2C_SMB_SHTF1_0     = 0x0  // No SCL high and SDA high timeout occurs
	I2C_SMB_SHTF1_1     = 0x1  // SCL high and SDA high timeout occurs
	I2C_SMB_SLTF_Pos    = 0x3  // Position of SLTF field.
	I2C_SMB_SLTF_Msk    = 0x8  // Bit mask of SLTF field.
	I2C_SMB_SLTF        = 0x8  // Bit SLTF.
	I2C_SMB_SLTF_0      = 0x0  // No low timeout occurs
	I2C_SMB_SLTF_1      = 0x1  // Low timeout occurs
	I2C_SMB_TCKSEL_Pos  = 0x4  // Position of TCKSEL field.
	I2C_SMB_TCKSEL_Msk  = 0x10 // Bit mask of TCKSEL field.
	I2C_SMB_TCKSEL      = 0x10 // Bit TCKSEL.
	I2C_SMB_TCKSEL_0    = 0x0  // Timeout counter counts at the frequency of the I2C module clock / 64
	I2C_SMB_TCKSEL_1    = 0x1  // Timeout counter counts at the frequency of the I2C module clock
	I2C_SMB_SIICAEN_Pos = 0x5  // Position of SIICAEN field.
	I2C_SMB_SIICAEN_Msk = 0x20 // Bit mask of SIICAEN field.
	I2C_SMB_SIICAEN     = 0x20 // Bit SIICAEN.
	I2C_SMB_SIICAEN_0   = 0x0  // I2C address register 2 matching is disabled
	I2C_SMB_SIICAEN_1   = 0x1  // I2C address register 2 matching is enabled
	I2C_SMB_ALERTEN_Pos = 0x6  // Position of ALERTEN field.
	I2C_SMB_ALERTEN_Msk = 0x40 // Bit mask of ALERTEN field.
	I2C_SMB_ALERTEN     = 0x40 // Bit ALERTEN.
	I2C_SMB_ALERTEN_0   = 0x0  // SMBus alert response address matching is disabled
	I2C_SMB_ALERTEN_1   = 0x1  // SMBus alert response address matching is enabled
	I2C_SMB_FACK_Pos    = 0x7  // Position of FACK field.
	I2C_SMB_FACK_Msk    = 0x80 // Bit mask of FACK field.
	I2C_SMB_FACK        = 0x80 // Bit FACK.
	I2C_SMB_FACK_0      = 0x0  // An ACK or NACK is sent on the following receiving data byte
	I2C_SMB_FACK_1      = 0x1  // Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK.

	// A2: I2C Address Register 2
	I2C_A2_SAD_Pos = 0x1  // Position of SAD field.
	I2C_A2_SAD_Msk = 0xfe // Bit mask of SAD field.

	// SLTH: I2C SCL Low Timeout Register High
	I2C_SLTH_SSLT_Pos = 0x0  // Position of SSLT field.
	I2C_SLTH_SSLT_Msk = 0xff // Bit mask of SSLT field.

	// SLTL: I2C SCL Low Timeout Register Low
	I2C_SLTL_SSLT_Pos = 0x0  // Position of SSLT field.
	I2C_SLTL_SSLT_Msk = 0xff // Bit mask of SSLT field.
)

// Bitfields for UART0: Serial Communication Interface
const (
	// BDH: UART Baud Rate Registers: High
	UART_BDH_SBR_Pos     = 0x0  // Position of SBR field.
	UART_BDH_SBR_Msk     = 0x1f // Bit mask of SBR field.
	UART_BDH_RXEDGIE_Pos = 0x6  // Position of RXEDGIE field.
	UART_BDH_RXEDGIE_Msk = 0x40 // Bit mask of RXEDGIE field.
	UART_BDH_RXEDGIE     = 0x40 // Bit RXEDGIE.
	UART_BDH_RXEDGIE_0   = 0x0  // Hardware interrupts from RXEDGIF disabled using polling.
	UART_BDH_RXEDGIE_1   = 0x1  // RXEDGIF interrupt request enabled.
	UART_BDH_LBKDIE_Pos  = 0x7  // Position of LBKDIE field.
	UART_BDH_LBKDIE_Msk  = 0x80 // Bit mask of LBKDIE field.
	UART_BDH_LBKDIE      = 0x80 // Bit LBKDIE.
	UART_BDH_LBKDIE_0    = 0x0  // LBKDIF interrupt requests disabled.
	UART_BDH_LBKDIE_1    = 0x1  // LBKDIF interrupt requests enabled.

	// BDL: UART Baud Rate Registers: Low
	UART_BDL_SBR_Pos = 0x0  // Position of SBR field.
	UART_BDL_SBR_Msk = 0xff // Bit mask of SBR field.

	// C1: UART Control Register 1
	UART_C1_PT_Pos       = 0x0  // Position of PT field.
	UART_C1_PT_Msk       = 0x1  // Bit mask of PT field.
	UART_C1_PT           = 0x1  // Bit PT.
	UART_C1_PT_0         = 0x0  // Even parity.
	UART_C1_PT_1         = 0x1  // Odd parity.
	UART_C1_PE_Pos       = 0x1  // Position of PE field.
	UART_C1_PE_Msk       = 0x2  // Bit mask of PE field.
	UART_C1_PE           = 0x2  // Bit PE.
	UART_C1_PE_0         = 0x0  // Parity function disabled.
	UART_C1_PE_1         = 0x1  // Parity function enabled.
	UART_C1_ILT_Pos      = 0x2  // Position of ILT field.
	UART_C1_ILT_Msk      = 0x4  // Bit mask of ILT field.
	UART_C1_ILT          = 0x4  // Bit ILT.
	UART_C1_ILT_0        = 0x0  // Idle character bit count starts after start bit.
	UART_C1_ILT_1        = 0x1  // Idle character bit count starts after stop bit.
	UART_C1_WAKE_Pos     = 0x3  // Position of WAKE field.
	UART_C1_WAKE_Msk     = 0x8  // Bit mask of WAKE field.
	UART_C1_WAKE         = 0x8  // Bit WAKE.
	UART_C1_WAKE_0       = 0x0  // Idle line wakeup.
	UART_C1_WAKE_1       = 0x1  // Address mark wakeup.
	UART_C1_M_Pos        = 0x4  // Position of M field.
	UART_C1_M_Msk        = 0x10 // Bit mask of M field.
	UART_C1_M            = 0x10 // Bit M.
	UART_C1_M_0          = 0x0  // Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop.
	UART_C1_M_1          = 0x1  // Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop.
	UART_C1_RSRC_Pos     = 0x5  // Position of RSRC field.
	UART_C1_RSRC_Msk     = 0x20 // Bit mask of RSRC field.
	UART_C1_RSRC         = 0x20 // Bit RSRC.
	UART_C1_RSRC_0       = 0x0  // Selects internal loop back mode. The receiver input is internally connected to transmitter output.
	UART_C1_RSRC_1       = 0x1  // Single wire UART mode where the receiver input is connected to the transmit pin input signal.
	UART_C1_UARTSWAI_Pos = 0x6  // Position of UARTSWAI field.
	UART_C1_UARTSWAI_Msk = 0x40 // Bit mask of UARTSWAI field.
	UART_C1_UARTSWAI     = 0x40 // Bit UARTSWAI.
	UART_C1_UARTSWAI_0   = 0x0  // UART clock continues to run in Wait mode.
	UART_C1_UARTSWAI_1   = 0x1  // UART clock freezes while CPU is in Wait mode.
	UART_C1_LOOPS_Pos    = 0x7  // Position of LOOPS field.
	UART_C1_LOOPS_Msk    = 0x80 // Bit mask of LOOPS field.
	UART_C1_LOOPS        = 0x80 // Bit LOOPS.
	UART_C1_LOOPS_0      = 0x0  // Normal operation.
	UART_C1_LOOPS_1      = 0x1  // Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by RSRC.

	// C2: UART Control Register 2
	UART_C2_SBK_Pos  = 0x0  // Position of SBK field.
	UART_C2_SBK_Msk  = 0x1  // Bit mask of SBK field.
	UART_C2_SBK      = 0x1  // Bit SBK.
	UART_C2_SBK_0    = 0x0  // Normal transmitter operation.
	UART_C2_SBK_1    = 0x1  // Queue break characters to be sent.
	UART_C2_RWU_Pos  = 0x1  // Position of RWU field.
	UART_C2_RWU_Msk  = 0x2  // Bit mask of RWU field.
	UART_C2_RWU      = 0x2  // Bit RWU.
	UART_C2_RWU_0    = 0x0  // Normal operation.
	UART_C2_RWU_1    = 0x1  // RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU.
	UART_C2_RE_Pos   = 0x2  // Position of RE field.
	UART_C2_RE_Msk   = 0x4  // Bit mask of RE field.
	UART_C2_RE       = 0x4  // Bit RE.
	UART_C2_RE_0     = 0x0  // Receiver off.
	UART_C2_RE_1     = 0x1  // Receiver on.
	UART_C2_TE_Pos   = 0x3  // Position of TE field.
	UART_C2_TE_Msk   = 0x8  // Bit mask of TE field.
	UART_C2_TE       = 0x8  // Bit TE.
	UART_C2_TE_0     = 0x0  // Transmitter off.
	UART_C2_TE_1     = 0x1  // Transmitter on.
	UART_C2_ILIE_Pos = 0x4  // Position of ILIE field.
	UART_C2_ILIE_Msk = 0x10 // Bit mask of ILIE field.
	UART_C2_ILIE     = 0x10 // Bit ILIE.
	UART_C2_ILIE_0   = 0x0  // IDLE interrupt requests disabled.
	UART_C2_ILIE_1   = 0x1  // IDLE interrupt requests enabled.
	UART_C2_RIE_Pos  = 0x5  // Position of RIE field.
	UART_C2_RIE_Msk  = 0x20 // Bit mask of RIE field.
	UART_C2_RIE      = 0x20 // Bit RIE.
	UART_C2_RIE_0    = 0x0  // RDRF interrupt and DMA transfer requests disabled.
	UART_C2_RIE_1    = 0x1  // RDRF interrupt or DMA transfer requests enabled.
	UART_C2_TCIE_Pos = 0x6  // Position of TCIE field.
	UART_C2_TCIE_Msk = 0x40 // Bit mask of TCIE field.
	UART_C2_TCIE     = 0x40 // Bit TCIE.
	UART_C2_TCIE_0   = 0x0  // TC interrupt requests disabled.
	UART_C2_TCIE_1   = 0x1  // TC interrupt requests enabled.
	UART_C2_TIE_Pos  = 0x7  // Position of TIE field.
	UART_C2_TIE_Msk  = 0x80 // Bit mask of TIE field.
	UART_C2_TIE      = 0x80 // Bit TIE.
	UART_C2_TIE_0    = 0x0  // TDRE interrupt and DMA transfer requests disabled.
	UART_C2_TIE_1    = 0x1  // TDRE interrupt or DMA transfer requests enabled.

	// S1: UART Status Register 1
	UART_S1_PF_Pos   = 0x0  // Position of PF field.
	UART_S1_PF_Msk   = 0x1  // Bit mask of PF field.
	UART_S1_PF       = 0x1  // Bit PF.
	UART_S1_PF_0     = 0x0  // No parity error detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1, then there may be data in the receive buffer what was received with a parity error.
	UART_S1_PF_1     = 0x1  // At least one dataword was received with a parity error since the last time this flag was cleared.
	UART_S1_FE_Pos   = 0x1  // Position of FE field.
	UART_S1_FE_Msk   = 0x2  // Bit mask of FE field.
	UART_S1_FE       = 0x2  // Bit FE.
	UART_S1_FE_0     = 0x0  // No framing error detected.
	UART_S1_FE_1     = 0x1  // Framing error.
	UART_S1_NF_Pos   = 0x2  // Position of NF field.
	UART_S1_NF_Msk   = 0x4  // Bit mask of NF field.
	UART_S1_NF       = 0x4  // Bit NF.
	UART_S1_NF_0     = 0x0  // No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise.
	UART_S1_NF_1     = 0x1  // At least one dataword was received with noise detected since the last time the flag was cleared.
	UART_S1_OR_Pos   = 0x3  // Position of OR field.
	UART_S1_OR_Msk   = 0x8  // Bit mask of OR field.
	UART_S1_OR       = 0x8  // Bit OR.
	UART_S1_OR_0     = 0x0  // No overrun has occurred since the last time the flag was cleared.
	UART_S1_OR_1     = 0x1  // Overrun has occurred or the overrun flag has not been cleared since the last overrun occured.
	UART_S1_IDLE_Pos = 0x4  // Position of IDLE field.
	UART_S1_IDLE_Msk = 0x10 // Bit mask of IDLE field.
	UART_S1_IDLE     = 0x10 // Bit IDLE.
	UART_S1_IDLE_0   = 0x0  // Receiver input is either active now or has never become active since the IDLE flag was last cleared.
	UART_S1_IDLE_1   = 0x1  // Receiver input has become idle or the flag has not been cleared since it last asserted.
	UART_S1_RDRF_Pos = 0x5  // Position of RDRF field.
	UART_S1_RDRF_Msk = 0x20 // Bit mask of RDRF field.
	UART_S1_RDRF     = 0x20 // Bit RDRF.
	UART_S1_RDRF_0   = 0x0  // The number of datawords in the receive buffer is less than the number indicated by RXWATER.
	UART_S1_RDRF_1   = 0x1  // The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared.
	UART_S1_TC_Pos   = 0x6  // Position of TC field.
	UART_S1_TC_Msk   = 0x40 // Bit mask of TC field.
	UART_S1_TC       = 0x40 // Bit TC.
	UART_S1_TC_0     = 0x0  // Transmitter active (sending data, a preamble, or a break).
	UART_S1_TC_1     = 0x1  // Transmitter idle (transmission activity complete).
	UART_S1_TDRE_Pos = 0x7  // Position of TDRE field.
	UART_S1_TDRE_Msk = 0x80 // Bit mask of TDRE field.
	UART_S1_TDRE     = 0x80 // Bit TDRE.
	UART_S1_TDRE_0   = 0x0  // The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER].
	UART_S1_TDRE_1   = 0x1  // The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared.

	// S2: UART Status Register 2
	UART_S2_RAF_Pos     = 0x0  // Position of RAF field.
	UART_S2_RAF_Msk     = 0x1  // Bit mask of RAF field.
	UART_S2_RAF         = 0x1  // Bit RAF.
	UART_S2_RAF_0       = 0x0  // UART receiver idle/inactive waiting for a start bit.
	UART_S2_RAF_1       = 0x1  // UART receiver active, RxD input not idle.
	UART_S2_LBKDE_Pos   = 0x1  // Position of LBKDE field.
	UART_S2_LBKDE_Msk   = 0x2  // Bit mask of LBKDE field.
	UART_S2_LBKDE       = 0x2  // Bit LBKDE.
	UART_S2_LBKDE_0     = 0x0  // Break character detection is disabled.
	UART_S2_LBKDE_1     = 0x1  // Break character is detected at length of 11 bit times if C1[M] = 0 or 12 bits time if C1[M] = 1.
	UART_S2_BRK13_Pos   = 0x2  // Position of BRK13 field.
	UART_S2_BRK13_Msk   = 0x4  // Bit mask of BRK13 field.
	UART_S2_BRK13       = 0x4  // Bit BRK13.
	UART_S2_BRK13_0     = 0x0  // Break character is 10, 11, or 12 bits long.
	UART_S2_BRK13_1     = 0x1  // Break character is 13 or 14 bits long.
	UART_S2_RWUID_Pos   = 0x3  // Position of RWUID field.
	UART_S2_RWUID_Msk   = 0x8  // Bit mask of RWUID field.
	UART_S2_RWUID       = 0x8  // Bit RWUID.
	UART_S2_RWUID_0     = 0x0  // S1[IDLE] is not set upon detection of an idle character.
	UART_S2_RWUID_1     = 0x1  // S1[IDLE] is set upon detection of an idle character.
	UART_S2_RXINV_Pos   = 0x4  // Position of RXINV field.
	UART_S2_RXINV_Msk   = 0x10 // Bit mask of RXINV field.
	UART_S2_RXINV       = 0x10 // Bit RXINV.
	UART_S2_RXINV_0     = 0x0  // Receive data is not inverted.
	UART_S2_RXINV_1     = 0x1  // Receive data is inverted.
	UART_S2_MSBF_Pos    = 0x5  // Position of MSBF field.
	UART_S2_MSBF_Msk    = 0x20 // Bit mask of MSBF field.
	UART_S2_MSBF        = 0x20 // Bit MSBF.
	UART_S2_MSBF_0      = 0x0  // LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.
	UART_S2_MSBF_1      = 0x1  // MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit, depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7, or bit6, depending on the setting of C1[M] and C1[PE].
	UART_S2_RXEDGIF_Pos = 0x6  // Position of RXEDGIF field.
	UART_S2_RXEDGIF_Msk = 0x40 // Bit mask of RXEDGIF field.
	UART_S2_RXEDGIF     = 0x40 // Bit RXEDGIF.
	UART_S2_RXEDGIF_0   = 0x0  // No active edge on the receive pin has occurred.
	UART_S2_RXEDGIF_1   = 0x1  // An active edge on the receive pin has occurred.
	UART_S2_LBKDIF_Pos  = 0x7  // Position of LBKDIF field.
	UART_S2_LBKDIF_Msk  = 0x80 // Bit mask of LBKDIF field.
	UART_S2_LBKDIF      = 0x80 // Bit LBKDIF.
	UART_S2_LBKDIF_0    = 0x0  // No LIN break character detected.
	UART_S2_LBKDIF_1    = 0x1  // LIN break character detected.

	// C3: UART Control Register 3
	UART_C3_PEIE_Pos  = 0x0  // Position of PEIE field.
	UART_C3_PEIE_Msk  = 0x1  // Bit mask of PEIE field.
	UART_C3_PEIE      = 0x1  // Bit PEIE.
	UART_C3_PEIE_0    = 0x0  // PF interrupt requests are disabled.
	UART_C3_PEIE_1    = 0x1  // PF interrupt requests are enabled.
	UART_C3_FEIE_Pos  = 0x1  // Position of FEIE field.
	UART_C3_FEIE_Msk  = 0x2  // Bit mask of FEIE field.
	UART_C3_FEIE      = 0x2  // Bit FEIE.
	UART_C3_FEIE_0    = 0x0  // FE interrupt requests are disabled.
	UART_C3_FEIE_1    = 0x1  // FE interrupt requests are enabled.
	UART_C3_NEIE_Pos  = 0x2  // Position of NEIE field.
	UART_C3_NEIE_Msk  = 0x4  // Bit mask of NEIE field.
	UART_C3_NEIE      = 0x4  // Bit NEIE.
	UART_C3_NEIE_0    = 0x0  // NF interrupt requests are disabled.
	UART_C3_NEIE_1    = 0x1  // NF interrupt requests are enabled.
	UART_C3_ORIE_Pos  = 0x3  // Position of ORIE field.
	UART_C3_ORIE_Msk  = 0x8  // Bit mask of ORIE field.
	UART_C3_ORIE      = 0x8  // Bit ORIE.
	UART_C3_ORIE_0    = 0x0  // OR interrupts are disabled.
	UART_C3_ORIE_1    = 0x1  // OR interrupt requests are enabled.
	UART_C3_TXINV_Pos = 0x4  // Position of TXINV field.
	UART_C3_TXINV_Msk = 0x10 // Bit mask of TXINV field.
	UART_C3_TXINV     = 0x10 // Bit TXINV.
	UART_C3_TXINV_0   = 0x0  // Transmit data is not inverted.
	UART_C3_TXINV_1   = 0x1  // Transmit data is inverted.
	UART_C3_TXDIR_Pos = 0x5  // Position of TXDIR field.
	UART_C3_TXDIR_Msk = 0x20 // Bit mask of TXDIR field.
	UART_C3_TXDIR     = 0x20 // Bit TXDIR.
	UART_C3_TXDIR_0   = 0x0  // TXD pin is an input in single wire mode.
	UART_C3_TXDIR_1   = 0x1  // TXD pin is an output in single wire mode.
	UART_C3_T8_Pos    = 0x6  // Position of T8 field.
	UART_C3_T8_Msk    = 0x40 // Bit mask of T8 field.
	UART_C3_T8        = 0x40 // Bit T8.
	UART_C3_R8_Pos    = 0x7  // Position of R8 field.
	UART_C3_R8_Msk    = 0x80 // Bit mask of R8 field.
	UART_C3_R8        = 0x80 // Bit R8.

	// D: UART Data Register
	UART_D_RT_Pos = 0x0  // Position of RT field.
	UART_D_RT_Msk = 0xff // Bit mask of RT field.

	// MA1: UART Match Address Registers 1
	UART_MA1_MA_Pos = 0x0  // Position of MA field.
	UART_MA1_MA_Msk = 0xff // Bit mask of MA field.

	// MA2: UART Match Address Registers 2
	UART_MA2_MA_Pos = 0x0  // Position of MA field.
	UART_MA2_MA_Msk = 0xff // Bit mask of MA field.

	// C4: UART Control Register 4
	UART_C4_BRFA_Pos  = 0x0  // Position of BRFA field.
	UART_C4_BRFA_Msk  = 0x1f // Bit mask of BRFA field.
	UART_C4_M10_Pos   = 0x5  // Position of M10 field.
	UART_C4_M10_Msk   = 0x20 // Bit mask of M10 field.
	UART_C4_M10       = 0x20 // Bit M10.
	UART_C4_M10_0     = 0x0  // The parity bit is the ninth bit in the serial transmission.
	UART_C4_M10_1     = 0x1  // The parity bit is the tenth bit in the serial transmission.
	UART_C4_MAEN2_Pos = 0x6  // Position of MAEN2 field.
	UART_C4_MAEN2_Msk = 0x40 // Bit mask of MAEN2 field.
	UART_C4_MAEN2     = 0x40 // Bit MAEN2.
	UART_C4_MAEN2_0   = 0x0  // All data received is transferred to the data buffer if MAEN1 is cleared.
	UART_C4_MAEN2_1   = 0x1  // All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If a match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled.
	UART_C4_MAEN1_Pos = 0x7  // Position of MAEN1 field.
	UART_C4_MAEN1_Msk = 0x80 // Bit mask of MAEN1 field.
	UART_C4_MAEN1     = 0x80 // Bit MAEN1.
	UART_C4_MAEN1_0   = 0x0  // All data received is transferred to the data buffer if MAEN2 is cleared.
	UART_C4_MAEN1_1   = 0x1  // All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled.

	// C5: UART Control Register 5
	UART_C5_RDMAS_Pos = 0x5  // Position of RDMAS field.
	UART_C5_RDMAS_Msk = 0x20 // Bit mask of RDMAS field.
	UART_C5_RDMAS     = 0x20 // Bit RDMAS.
	UART_C5_RDMAS_0   = 0x0  // If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service.
	UART_C5_RDMAS_1   = 0x1  // If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer.
	UART_C5_TDMAS_Pos = 0x7  // Position of TDMAS field.
	UART_C5_TDMAS_Msk = 0x80 // Bit mask of TDMAS field.
	UART_C5_TDMAS     = 0x80 // Bit TDMAS.
	UART_C5_TDMAS_0   = 0x0  // If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service.
	UART_C5_TDMAS_1   = 0x1  // If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer.

	// ED: UART Extended Data Register
	UART_ED_PARITYE_Pos = 0x6  // Position of PARITYE field.
	UART_ED_PARITYE_Msk = 0x40 // Bit mask of PARITYE field.
	UART_ED_PARITYE     = 0x40 // Bit PARITYE.
	UART_ED_PARITYE_0   = 0x0  // The dataword was received without a parity error.
	UART_ED_PARITYE_1   = 0x1  // The dataword was received with a parity error.
	UART_ED_NOISY_Pos   = 0x7  // Position of NOISY field.
	UART_ED_NOISY_Msk   = 0x80 // Bit mask of NOISY field.
	UART_ED_NOISY       = 0x80 // Bit NOISY.
	UART_ED_NOISY_0     = 0x0  // The dataword was received without noise.
	UART_ED_NOISY_1     = 0x1  // The data was received with noise.

	// MODEM: UART Modem Register
	UART_MODEM_TXCTSE_Pos   = 0x0 // Position of TXCTSE field.
	UART_MODEM_TXCTSE_Msk   = 0x1 // Bit mask of TXCTSE field.
	UART_MODEM_TXCTSE       = 0x1 // Bit TXCTSE.
	UART_MODEM_TXCTSE_0     = 0x0 // CTS has no effect on the transmitter.
	UART_MODEM_TXCTSE_1     = 0x1 // Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission.
	UART_MODEM_TXRTSE_Pos   = 0x1 // Position of TXRTSE field.
	UART_MODEM_TXRTSE_Msk   = 0x2 // Bit mask of TXRTSE field.
	UART_MODEM_TXRTSE       = 0x2 // Bit TXRTSE.
	UART_MODEM_TXRTSE_0     = 0x0 // The transmitter has no effect on RTS.
	UART_MODEM_TXRTSE_1     = 0x1 // When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. (FIFO) (FIFO)
	UART_MODEM_TXRTSPOL_Pos = 0x2 // Position of TXRTSPOL field.
	UART_MODEM_TXRTSPOL_Msk = 0x4 // Bit mask of TXRTSPOL field.
	UART_MODEM_TXRTSPOL     = 0x4 // Bit TXRTSPOL.
	UART_MODEM_TXRTSPOL_0   = 0x0 // Transmitter RTS is active low.
	UART_MODEM_TXRTSPOL_1   = 0x1 // Transmitter RTS is active high.
	UART_MODEM_RXRTSE_Pos   = 0x3 // Position of RXRTSE field.
	UART_MODEM_RXRTSE_Msk   = 0x8 // Bit mask of RXRTSE field.
	UART_MODEM_RXRTSE       = 0x8 // Bit RXRTSE.
	UART_MODEM_RXRTSE_0     = 0x0 // The receiver has no effect on RTS.
	UART_MODEM_RXRTSE_1     = 0x1 // RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER].

	// IR: UART Infrared Register
	UART_IR_TNP_Pos  = 0x0 // Position of TNP field.
	UART_IR_TNP_Msk  = 0x3 // Bit mask of TNP field.
	UART_IR_TNP_00   = 0x0 // 3/16.
	UART_IR_TNP_01   = 0x1 // 1/16.
	UART_IR_TNP_10   = 0x2 // 1/32.
	UART_IR_TNP_11   = 0x3 // 1/4.
	UART_IR_IREN_Pos = 0x2 // Position of IREN field.
	UART_IR_IREN_Msk = 0x4 // Bit mask of IREN field.
	UART_IR_IREN     = 0x4 // Bit IREN.
	UART_IR_IREN_0   = 0x0 // IR disabled.
	UART_IR_IREN_1   = 0x1 // IR enabled.

	// PFIFO: UART FIFO Parameters
	UART_PFIFO_RXFIFOSIZE_Pos = 0x0  // Position of RXFIFOSIZE field.
	UART_PFIFO_RXFIFOSIZE_Msk = 0x7  // Bit mask of RXFIFOSIZE field.
	UART_PFIFO_RXFIFOSIZE_000 = 0x0  // Receive FIFO/Buffer depth = 1 dataword.
	UART_PFIFO_RXFIFOSIZE_001 = 0x1  // Receive FIFO/Buffer depth = 4 datawords.
	UART_PFIFO_RXFIFOSIZE_010 = 0x2  // Receive FIFO/Buffer depth = 8 datawords.
	UART_PFIFO_RXFIFOSIZE_011 = 0x3  // Receive FIFO/Buffer depth = 16 datawords.
	UART_PFIFO_RXFIFOSIZE_100 = 0x4  // Receive FIFO/Buffer depth = 32 datawords.
	UART_PFIFO_RXFIFOSIZE_101 = 0x5  // Receive FIFO/Buffer depth = 64 datawords.
	UART_PFIFO_RXFIFOSIZE_110 = 0x6  // Receive FIFO/Buffer depth = 128 datawords.
	UART_PFIFO_RXFE_Pos       = 0x3  // Position of RXFE field.
	UART_PFIFO_RXFE_Msk       = 0x8  // Bit mask of RXFE field.
	UART_PFIFO_RXFE           = 0x8  // Bit RXFE.
	UART_PFIFO_RXFE_0         = 0x0  // Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)
	UART_PFIFO_RXFE_1         = 0x1  // Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.
	UART_PFIFO_TXFIFOSIZE_Pos = 0x4  // Position of TXFIFOSIZE field.
	UART_PFIFO_TXFIFOSIZE_Msk = 0x70 // Bit mask of TXFIFOSIZE field.
	UART_PFIFO_TXFIFOSIZE_000 = 0x0  // Transmit FIFO/Buffer depth = 1 dataword.
	UART_PFIFO_TXFIFOSIZE_001 = 0x1  // Transmit FIFO/Buffer depth = 4 datawords.
	UART_PFIFO_TXFIFOSIZE_010 = 0x2  // Transmit FIFO/Buffer depth = 8 datawords.
	UART_PFIFO_TXFIFOSIZE_011 = 0x3  // Transmit FIFO/Buffer depth = 16 datawords.
	UART_PFIFO_TXFIFOSIZE_100 = 0x4  // Transmit FIFO/Buffer depth = 32 datawords.
	UART_PFIFO_TXFIFOSIZE_101 = 0x5  // Transmit FIFO/Buffer depth = 64 datawords.
	UART_PFIFO_TXFIFOSIZE_110 = 0x6  // Transmit FIFO/Buffer depth = 128 datawords.
	UART_PFIFO_TXFE_Pos       = 0x7  // Position of TXFE field.
	UART_PFIFO_TXFE_Msk       = 0x80 // Bit mask of TXFE field.
	UART_PFIFO_TXFE           = 0x80 // Bit TXFE.
	UART_PFIFO_TXFE_0         = 0x0  // Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).
	UART_PFIFO_TXFE_1         = 0x1  // Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.

	// CFIFO: UART FIFO Control Register
	UART_CFIFO_RXUFE_Pos   = 0x0  // Position of RXUFE field.
	UART_CFIFO_RXUFE_Msk   = 0x1  // Bit mask of RXUFE field.
	UART_CFIFO_RXUFE       = 0x1  // Bit RXUFE.
	UART_CFIFO_RXUFE_0     = 0x0  // RXUF flag does not generate an interrupt to the host.
	UART_CFIFO_RXUFE_1     = 0x1  // RXUF flag generates an interrupt to the host.
	UART_CFIFO_TXOFE_Pos   = 0x1  // Position of TXOFE field.
	UART_CFIFO_TXOFE_Msk   = 0x2  // Bit mask of TXOFE field.
	UART_CFIFO_TXOFE       = 0x2  // Bit TXOFE.
	UART_CFIFO_TXOFE_0     = 0x0  // TXOF flag does not generate an interrupt to the host.
	UART_CFIFO_TXOFE_1     = 0x1  // TXOF flag generates an interrupt to the host.
	UART_CFIFO_RXOFE_Pos   = 0x2  // Position of RXOFE field.
	UART_CFIFO_RXOFE_Msk   = 0x4  // Bit mask of RXOFE field.
	UART_CFIFO_RXOFE       = 0x4  // Bit RXOFE.
	UART_CFIFO_RXOFE_0     = 0x0  // RXOF flag does not generate an interrupt to the host.
	UART_CFIFO_RXOFE_1     = 0x1  // RXOF flag generates an interrupt to the host.
	UART_CFIFO_RXFLUSH_Pos = 0x6  // Position of RXFLUSH field.
	UART_CFIFO_RXFLUSH_Msk = 0x40 // Bit mask of RXFLUSH field.
	UART_CFIFO_RXFLUSH     = 0x40 // Bit RXFLUSH.
	UART_CFIFO_RXFLUSH_0   = 0x0  // No flush operation occurs.
	UART_CFIFO_RXFLUSH_1   = 0x1  // All data in the receive FIFO/buffer is cleared out.
	UART_CFIFO_TXFLUSH_Pos = 0x7  // Position of TXFLUSH field.
	UART_CFIFO_TXFLUSH_Msk = 0x80 // Bit mask of TXFLUSH field.
	UART_CFIFO_TXFLUSH     = 0x80 // Bit TXFLUSH.
	UART_CFIFO_TXFLUSH_0   = 0x0  // No flush operation occurs.
	UART_CFIFO_TXFLUSH_1   = 0x1  // All data in the transmit FIFO/Buffer is cleared out.

	// SFIFO: UART FIFO Status Register
	UART_SFIFO_RXUF_Pos   = 0x0  // Position of RXUF field.
	UART_SFIFO_RXUF_Msk   = 0x1  // Bit mask of RXUF field.
	UART_SFIFO_RXUF       = 0x1  // Bit RXUF.
	UART_SFIFO_RXUF_0     = 0x0  // No receive buffer underflow has occurred since the last time the flag was cleared.
	UART_SFIFO_RXUF_1     = 0x1  // At least one receive buffer underflow has occurred since the last time the flag was cleared.
	UART_SFIFO_TXOF_Pos   = 0x1  // Position of TXOF field.
	UART_SFIFO_TXOF_Msk   = 0x2  // Bit mask of TXOF field.
	UART_SFIFO_TXOF       = 0x2  // Bit TXOF.
	UART_SFIFO_TXOF_0     = 0x0  // No transmit buffer overflow has occurred since the last time the flag was cleared.
	UART_SFIFO_TXOF_1     = 0x1  // At least one transmit buffer overflow has occurred since the last time the flag was cleared.
	UART_SFIFO_RXOF_Pos   = 0x2  // Position of RXOF field.
	UART_SFIFO_RXOF_Msk   = 0x4  // Bit mask of RXOF field.
	UART_SFIFO_RXOF       = 0x4  // Bit RXOF.
	UART_SFIFO_RXOF_0     = 0x0  // No receive buffer overflow has occurred since the last time the flag was cleared.
	UART_SFIFO_RXOF_1     = 0x1  // At least one receive buffer overflow has occurred since the last time the flag was cleared.
	UART_SFIFO_RXEMPT_Pos = 0x6  // Position of RXEMPT field.
	UART_SFIFO_RXEMPT_Msk = 0x40 // Bit mask of RXEMPT field.
	UART_SFIFO_RXEMPT     = 0x40 // Bit RXEMPT.
	UART_SFIFO_RXEMPT_0   = 0x0  // Receive buffer is not empty.
	UART_SFIFO_RXEMPT_1   = 0x1  // Receive buffer is empty.
	UART_SFIFO_TXEMPT_Pos = 0x7  // Position of TXEMPT field.
	UART_SFIFO_TXEMPT_Msk = 0x80 // Bit mask of TXEMPT field.
	UART_SFIFO_TXEMPT     = 0x80 // Bit TXEMPT.
	UART_SFIFO_TXEMPT_0   = 0x0  // Transmit buffer is not empty.
	UART_SFIFO_TXEMPT_1   = 0x1  // Transmit buffer is empty.

	// TWFIFO: UART FIFO Transmit Watermark
	UART_TWFIFO_TXWATER_Pos = 0x0  // Position of TXWATER field.
	UART_TWFIFO_TXWATER_Msk = 0xff // Bit mask of TXWATER field.

	// TCFIFO: UART FIFO Transmit Count
	UART_TCFIFO_TXCOUNT_Pos = 0x0  // Position of TXCOUNT field.
	UART_TCFIFO_TXCOUNT_Msk = 0xff // Bit mask of TXCOUNT field.

	// RWFIFO: UART FIFO Receive Watermark
	UART_RWFIFO_RXWATER_Pos = 0x0  // Position of RXWATER field.
	UART_RWFIFO_RXWATER_Msk = 0xff // Bit mask of RXWATER field.

	// RCFIFO: UART FIFO Receive Count
	UART_RCFIFO_RXCOUNT_Pos = 0x0  // Position of RXCOUNT field.
	UART_RCFIFO_RXCOUNT_Msk = 0xff // Bit mask of RXCOUNT field.

	// C7816: UART 7816 Control Register
	UART_C7816_ISO_7816E_Pos = 0x0  // Position of ISO_7816E field.
	UART_C7816_ISO_7816E_Msk = 0x1  // Bit mask of ISO_7816E field.
	UART_C7816_ISO_7816E     = 0x1  // Bit ISO_7816E.
	UART_C7816_ISO_7816E_0   = 0x0  // ISO-7816 functionality is turned off/not enabled.
	UART_C7816_ISO_7816E_1   = 0x1  // ISO-7816 functionality is turned on/enabled.
	UART_C7816_TTYPE_Pos     = 0x1  // Position of TTYPE field.
	UART_C7816_TTYPE_Msk     = 0x2  // Bit mask of TTYPE field.
	UART_C7816_TTYPE         = 0x2  // Bit TTYPE.
	UART_C7816_TTYPE_0       = 0x0  // T = 0 per the ISO-7816 specification.
	UART_C7816_TTYPE_1       = 0x1  // T = 1 per the ISO-7816 specification.
	UART_C7816_INIT_Pos      = 0x2  // Position of INIT field.
	UART_C7816_INIT_Msk      = 0x4  // Bit mask of INIT field.
	UART_C7816_INIT          = 0x4  // Bit INIT.
	UART_C7816_INIT_0        = 0x0  // Normal operating mode. Receiver does not seek to identify initial character.
	UART_C7816_INIT_1        = 0x1  // Receiver searches for initial character.
	UART_C7816_ANACK_Pos     = 0x3  // Position of ANACK field.
	UART_C7816_ANACK_Msk     = 0x8  // Bit mask of ANACK field.
	UART_C7816_ANACK         = 0x8  // Bit ANACK.
	UART_C7816_ANACK_0       = 0x0  // No NACK is automatically generated.
	UART_C7816_ANACK_1       = 0x1  // A NACK is automatically generated if a parity error is detected or if an invalid initial character is detected.
	UART_C7816_ONACK_Pos     = 0x4  // Position of ONACK field.
	UART_C7816_ONACK_Msk     = 0x10 // Bit mask of ONACK field.
	UART_C7816_ONACK         = 0x10 // Bit ONACK.
	UART_C7816_ONACK_0       = 0x0  // The received data does not generate a NACK when the receipt of the data results in an overflow event.
	UART_C7816_ONACK_1       = 0x1  // If the receiver buffer overflows, a NACK is automatically sent on a received character.

	// IE7816: UART 7816 Interrupt Enable Register
	UART_IE7816_RXTE_Pos   = 0x0  // Position of RXTE field.
	UART_IE7816_RXTE_Msk   = 0x1  // Bit mask of RXTE field.
	UART_IE7816_RXTE       = 0x1  // Bit RXTE.
	UART_IE7816_RXTE_0     = 0x0  // The assertion of IS7816[RXT] does not result in the generation of an interrupt.
	UART_IE7816_RXTE_1     = 0x1  // The assertion of IS7816[RXT] results in the generation of an interrupt.
	UART_IE7816_TXTE_Pos   = 0x1  // Position of TXTE field.
	UART_IE7816_TXTE_Msk   = 0x2  // Bit mask of TXTE field.
	UART_IE7816_TXTE       = 0x2  // Bit TXTE.
	UART_IE7816_TXTE_0     = 0x0  // The assertion of IS7816[TXT] does not result in the generation of an interrupt.
	UART_IE7816_TXTE_1     = 0x1  // The assertion of IS7816[TXT] results in the generation of an interrupt.
	UART_IE7816_GTVE_Pos   = 0x2  // Position of GTVE field.
	UART_IE7816_GTVE_Msk   = 0x4  // Bit mask of GTVE field.
	UART_IE7816_GTVE       = 0x4  // Bit GTVE.
	UART_IE7816_GTVE_0     = 0x0  // The assertion of IS7816[GTV] does not result in the generation of an interrupt.
	UART_IE7816_GTVE_1     = 0x1  // The assertion of IS7816[GTV] results in the generation of an interrupt.
	UART_IE7816_ADTE_Pos   = 0x3  // Position of ADTE field.
	UART_IE7816_ADTE_Msk   = 0x8  // Bit mask of ADTE field.
	UART_IE7816_ADTE       = 0x8  // Bit ADTE.
	UART_IE7816_ADTE_0     = 0x0  // The assertion of IS7816[ADT] does not result in the generation of an interrupt.
	UART_IE7816_ADTE_1     = 0x1  // The assertion of IS7816[ADT] results in the generation of an interrupt.
	UART_IE7816_INITDE_Pos = 0x4  // Position of INITDE field.
	UART_IE7816_INITDE_Msk = 0x10 // Bit mask of INITDE field.
	UART_IE7816_INITDE     = 0x10 // Bit INITDE.
	UART_IE7816_INITDE_0   = 0x0  // The assertion of IS7816[INITD] does not result in the generation of an interrupt.
	UART_IE7816_INITDE_1   = 0x1  // The assertion of IS7816[INITD] results in the generation of an interrupt.
	UART_IE7816_BWTE_Pos   = 0x5  // Position of BWTE field.
	UART_IE7816_BWTE_Msk   = 0x20 // Bit mask of BWTE field.
	UART_IE7816_BWTE       = 0x20 // Bit BWTE.
	UART_IE7816_BWTE_0     = 0x0  // The assertion of IS7816[BWT] does not result in the generation of an interrupt.
	UART_IE7816_BWTE_1     = 0x1  // The assertion of IS7816[BWT] results in the generation of an interrupt.
	UART_IE7816_CWTE_Pos   = 0x6  // Position of CWTE field.
	UART_IE7816_CWTE_Msk   = 0x40 // Bit mask of CWTE field.
	UART_IE7816_CWTE       = 0x40 // Bit CWTE.
	UART_IE7816_CWTE_0     = 0x0  // The assertion of IS7816[CWT] does not result in the generation of an interrupt.
	UART_IE7816_CWTE_1     = 0x1  // The assertion of IS7816[CWT] results in the generation of an interrupt.
	UART_IE7816_WTE_Pos    = 0x7  // Position of WTE field.
	UART_IE7816_WTE_Msk    = 0x80 // Bit mask of WTE field.
	UART_IE7816_WTE        = 0x80 // Bit WTE.
	UART_IE7816_WTE_0      = 0x0  // The assertion of IS7816[WT] does not result in the generation of an interrupt.
	UART_IE7816_WTE_1      = 0x1  // The assertion of IS7816[WT] results in the generation of an interrupt.

	// IS7816: UART 7816 Interrupt Status Register
	UART_IS7816_RXT_Pos   = 0x0  // Position of RXT field.
	UART_IS7816_RXT_Msk   = 0x1  // Bit mask of RXT field.
	UART_IS7816_RXT       = 0x1  // Bit RXT.
	UART_IS7816_RXT_0     = 0x0  // The number of consecutive NACKS generated as a result of parity errors and buffer overruns is less than or equal to the value in ET7816[RXTHRESHOLD].
	UART_IS7816_RXT_1     = 0x1  // The number of consecutive NACKS generated as a result of parity errors and buffer overruns is greater than the value in ET7816[RXTHRESHOLD].
	UART_IS7816_TXT_Pos   = 0x1  // Position of TXT field.
	UART_IS7816_TXT_Msk   = 0x2  // Bit mask of TXT field.
	UART_IS7816_TXT       = 0x2  // Bit TXT.
	UART_IS7816_TXT_0     = 0x0  // The number of retries and corresponding NACKS does not exceed the value in ET7816[TXTHRESHOLD].
	UART_IS7816_TXT_1     = 0x1  // The number of retries and corresponding NACKS exceeds the value in ET7816[TXTHRESHOLD].
	UART_IS7816_GTV_Pos   = 0x2  // Position of GTV field.
	UART_IS7816_GTV_Msk   = 0x4  // Bit mask of GTV field.
	UART_IS7816_GTV       = 0x4  // Bit GTV.
	UART_IS7816_GTV_0     = 0x0  // A guard time (GT, CGT, or BGT) has not been violated.
	UART_IS7816_GTV_1     = 0x1  // A guard time (GT, CGT, or BGT) has been violated.
	UART_IS7816_ADT_Pos   = 0x3  // Position of ADT field.
	UART_IS7816_ADT_Msk   = 0x8  // Bit mask of ADT field.
	UART_IS7816_ADT       = 0x8  // Bit ADT.
	UART_IS7816_ADT_0     = 0x0  // ATR Duration time (ADT) has not been violated.
	UART_IS7816_ADT_1     = 0x1  // ATR Duration time (ADT) has been violated.
	UART_IS7816_INITD_Pos = 0x4  // Position of INITD field.
	UART_IS7816_INITD_Msk = 0x10 // Bit mask of INITD field.
	UART_IS7816_INITD     = 0x10 // Bit INITD.
	UART_IS7816_INITD_0   = 0x0  // A valid initial character has not been received.
	UART_IS7816_INITD_1   = 0x1  // A valid initial character has been received.
	UART_IS7816_BWT_Pos   = 0x5  // Position of BWT field.
	UART_IS7816_BWT_Msk   = 0x20 // Bit mask of BWT field.
	UART_IS7816_BWT       = 0x20 // Bit BWT.
	UART_IS7816_BWT_0     = 0x0  // Block wait time (BWT) has not been violated.
	UART_IS7816_BWT_1     = 0x1  // Block wait time (BWT) has been violated.
	UART_IS7816_CWT_Pos   = 0x6  // Position of CWT field.
	UART_IS7816_CWT_Msk   = 0x40 // Bit mask of CWT field.
	UART_IS7816_CWT       = 0x40 // Bit CWT.
	UART_IS7816_CWT_0     = 0x0  // Character wait time (CWT) has not been violated.
	UART_IS7816_CWT_1     = 0x1  // Character wait time (CWT) has been violated.
	UART_IS7816_WT_Pos    = 0x7  // Position of WT field.
	UART_IS7816_WT_Msk    = 0x80 // Bit mask of WT field.
	UART_IS7816_WT        = 0x80 // Bit WT.
	UART_IS7816_WT_0      = 0x0  // Wait time (WT) has not been violated.
	UART_IS7816_WT_1      = 0x1  // Wait time (WT) has been violated.

	// WP7816: UART 7816 Wait Parameter Register
	UART_WP7816_WTX_Pos = 0x0  // Position of WTX field.
	UART_WP7816_WTX_Msk = 0xff // Bit mask of WTX field.

	// WN7816: UART 7816 Wait N Register
	UART_WN7816_GTN_Pos = 0x0  // Position of GTN field.
	UART_WN7816_GTN_Msk = 0xff // Bit mask of GTN field.

	// WF7816: UART 7816 Wait FD Register
	UART_WF7816_GTFD_Pos = 0x0  // Position of GTFD field.
	UART_WF7816_GTFD_Msk = 0xff // Bit mask of GTFD field.

	// ET7816: UART 7816 Error Threshold Register
	UART_ET7816_RXTHRESHOLD_Pos = 0x0  // Position of RXTHRESHOLD field.
	UART_ET7816_RXTHRESHOLD_Msk = 0xf  // Bit mask of RXTHRESHOLD field.
	UART_ET7816_TXTHRESHOLD_Pos = 0x4  // Position of TXTHRESHOLD field.
	UART_ET7816_TXTHRESHOLD_Msk = 0xf0 // Bit mask of TXTHRESHOLD field.
	UART_ET7816_TXTHRESHOLD_0   = 0x0  // TXT asserts on the first NACK that is received.
	UART_ET7816_TXTHRESHOLD_1   = 0x1  // TXT asserts on the second NACK that is received.

	// TL7816: UART 7816 Transmit Length Register
	UART_TL7816_TLEN_Pos = 0x0  // Position of TLEN field.
	UART_TL7816_TLEN_Msk = 0xff // Bit mask of TLEN field.

	// AP7816A_T0: UART 7816 ATR Duration Timer Register A
	UART_AP7816A_T0_ADTI_H_Pos = 0x0  // Position of ADTI_H field.
	UART_AP7816A_T0_ADTI_H_Msk = 0xff // Bit mask of ADTI_H field.

	// AP7816B_T0: UART 7816 ATR Duration Timer Register B
	UART_AP7816B_T0_ADTI_L_Pos = 0x0  // Position of ADTI_L field.
	UART_AP7816B_T0_ADTI_L_Msk = 0xff // Bit mask of ADTI_L field.

	// WP7816A_T0: UART 7816 Wait Parameter Register A
	UART_WP7816A_T0_WI_H_Pos = 0x0  // Position of WI_H field.
	UART_WP7816A_T0_WI_H_Msk = 0xff // Bit mask of WI_H field.

	// WP7816A_T1: UART 7816 Wait Parameter Register A
	UART_WP7816A_T1_BWI_H_Pos = 0x0  // Position of BWI_H field.
	UART_WP7816A_T1_BWI_H_Msk = 0xff // Bit mask of BWI_H field.

	// WP7816B_T0: UART 7816 Wait Parameter Register B
	UART_WP7816B_T0_WI_L_Pos = 0x0  // Position of WI_L field.
	UART_WP7816B_T0_WI_L_Msk = 0xff // Bit mask of WI_L field.

	// WP7816B_T1: UART 7816 Wait Parameter Register B
	UART_WP7816B_T1_BWI_L_Pos = 0x0  // Position of BWI_L field.
	UART_WP7816B_T1_BWI_L_Msk = 0xff // Bit mask of BWI_L field.

	// WGP7816_T1: UART 7816 Wait and Guard Parameter Register
	UART_WGP7816_T1_BGI_Pos  = 0x0  // Position of BGI field.
	UART_WGP7816_T1_BGI_Msk  = 0xf  // Bit mask of BGI field.
	UART_WGP7816_T1_CWI1_Pos = 0x4  // Position of CWI1 field.
	UART_WGP7816_T1_CWI1_Msk = 0xf0 // Bit mask of CWI1 field.

	// WP7816C_T1: UART 7816 Wait Parameter Register C
	UART_WP7816C_T1_CWI2_Pos = 0x0  // Position of CWI2 field.
	UART_WP7816C_T1_CWI2_Msk = 0x1f // Bit mask of CWI2 field.
)

// Bitfields for USB0: Universal Serial Bus, OTG Capable Controller
const (
	// PERID: Peripheral ID register
	USB0_PERID_ID_Pos = 0x0  // Position of ID field.
	USB0_PERID_ID_Msk = 0x3f // Bit mask of ID field.

	// IDCOMP: Peripheral ID Complement register
	USB0_IDCOMP_NID_Pos = 0x0  // Position of NID field.
	USB0_IDCOMP_NID_Msk = 0x3f // Bit mask of NID field.

	// REV: Peripheral Revision register
	USB0_REV_REV_Pos = 0x0  // Position of REV field.
	USB0_REV_REV_Msk = 0xff // Bit mask of REV field.

	// ADDINFO: Peripheral Additional Info register
	USB0_ADDINFO_IEHOST_Pos = 0x0 // Position of IEHOST field.
	USB0_ADDINFO_IEHOST_Msk = 0x1 // Bit mask of IEHOST field.
	USB0_ADDINFO_IEHOST     = 0x1 // Bit IEHOST.

	// OTGISTAT: OTG Interrupt Status register
	USB0_OTGISTAT_AVBUSCHG_Pos       = 0x0  // Position of AVBUSCHG field.
	USB0_OTGISTAT_AVBUSCHG_Msk       = 0x1  // Bit mask of AVBUSCHG field.
	USB0_OTGISTAT_AVBUSCHG           = 0x1  // Bit AVBUSCHG.
	USB0_OTGISTAT_B_SESS_CHG_Pos     = 0x2  // Position of B_SESS_CHG field.
	USB0_OTGISTAT_B_SESS_CHG_Msk     = 0x4  // Bit mask of B_SESS_CHG field.
	USB0_OTGISTAT_B_SESS_CHG         = 0x4  // Bit B_SESS_CHG.
	USB0_OTGISTAT_SESSVLDCHG_Pos     = 0x3  // Position of SESSVLDCHG field.
	USB0_OTGISTAT_SESSVLDCHG_Msk     = 0x8  // Bit mask of SESSVLDCHG field.
	USB0_OTGISTAT_SESSVLDCHG         = 0x8  // Bit SESSVLDCHG.
	USB0_OTGISTAT_LINE_STATE_CHG_Pos = 0x5  // Position of LINE_STATE_CHG field.
	USB0_OTGISTAT_LINE_STATE_CHG_Msk = 0x20 // Bit mask of LINE_STATE_CHG field.
	USB0_OTGISTAT_LINE_STATE_CHG     = 0x20 // Bit LINE_STATE_CHG.
	USB0_OTGISTAT_ONEMSEC_Pos        = 0x6  // Position of ONEMSEC field.
	USB0_OTGISTAT_ONEMSEC_Msk        = 0x40 // Bit mask of ONEMSEC field.
	USB0_OTGISTAT_ONEMSEC            = 0x40 // Bit ONEMSEC.
	USB0_OTGISTAT_IDCHG_Pos          = 0x7  // Position of IDCHG field.
	USB0_OTGISTAT_IDCHG_Msk          = 0x80 // Bit mask of IDCHG field.
	USB0_OTGISTAT_IDCHG              = 0x80 // Bit IDCHG.

	// OTGICR: OTG Interrupt Control register
	USB0_OTGICR_AVBUSEN_Pos     = 0x0  // Position of AVBUSEN field.
	USB0_OTGICR_AVBUSEN_Msk     = 0x1  // Bit mask of AVBUSEN field.
	USB0_OTGICR_AVBUSEN         = 0x1  // Bit AVBUSEN.
	USB0_OTGICR_AVBUSEN_0       = 0x0  // Disables the AVBUSCHG interrupt.
	USB0_OTGICR_AVBUSEN_1       = 0x1  // Enables the AVBUSCHG interrupt.
	USB0_OTGICR_BSESSEN_Pos     = 0x2  // Position of BSESSEN field.
	USB0_OTGICR_BSESSEN_Msk     = 0x4  // Bit mask of BSESSEN field.
	USB0_OTGICR_BSESSEN         = 0x4  // Bit BSESSEN.
	USB0_OTGICR_BSESSEN_0       = 0x0  // Disables the B_SESS_CHG interrupt.
	USB0_OTGICR_BSESSEN_1       = 0x1  // Enables the B_SESS_CHG interrupt.
	USB0_OTGICR_SESSVLDEN_Pos   = 0x3  // Position of SESSVLDEN field.
	USB0_OTGICR_SESSVLDEN_Msk   = 0x8  // Bit mask of SESSVLDEN field.
	USB0_OTGICR_SESSVLDEN       = 0x8  // Bit SESSVLDEN.
	USB0_OTGICR_SESSVLDEN_0     = 0x0  // Disables the SESSVLDCHG interrupt.
	USB0_OTGICR_SESSVLDEN_1     = 0x1  // Enables the SESSVLDCHG interrupt.
	USB0_OTGICR_LINESTATEEN_Pos = 0x5  // Position of LINESTATEEN field.
	USB0_OTGICR_LINESTATEEN_Msk = 0x20 // Bit mask of LINESTATEEN field.
	USB0_OTGICR_LINESTATEEN     = 0x20 // Bit LINESTATEEN.
	USB0_OTGICR_LINESTATEEN_0   = 0x0  // Disables the LINE_STAT_CHG interrupt.
	USB0_OTGICR_LINESTATEEN_1   = 0x1  // Enables the LINE_STAT_CHG interrupt.
	USB0_OTGICR_ONEMSECEN_Pos   = 0x6  // Position of ONEMSECEN field.
	USB0_OTGICR_ONEMSECEN_Msk   = 0x40 // Bit mask of ONEMSECEN field.
	USB0_OTGICR_ONEMSECEN       = 0x40 // Bit ONEMSECEN.
	USB0_OTGICR_ONEMSECEN_0     = 0x0  // Diables the 1ms timer interrupt.
	USB0_OTGICR_ONEMSECEN_1     = 0x1  // Enables the 1ms timer interrupt.
	USB0_OTGICR_IDEN_Pos        = 0x7  // Position of IDEN field.
	USB0_OTGICR_IDEN_Msk        = 0x80 // Bit mask of IDEN field.
	USB0_OTGICR_IDEN            = 0x80 // Bit IDEN.
	USB0_OTGICR_IDEN_0          = 0x0  // The ID interrupt is disabled
	USB0_OTGICR_IDEN_1          = 0x1  // The ID interrupt is enabled

	// OTGSTAT: OTG Status register
	USB0_OTGSTAT_AVBUSVLD_Pos        = 0x0  // Position of AVBUSVLD field.
	USB0_OTGSTAT_AVBUSVLD_Msk        = 0x1  // Bit mask of AVBUSVLD field.
	USB0_OTGSTAT_AVBUSVLD            = 0x1  // Bit AVBUSVLD.
	USB0_OTGSTAT_AVBUSVLD_0          = 0x0  // The VBUS voltage is below the A VBUS Valid threshold.
	USB0_OTGSTAT_AVBUSVLD_1          = 0x1  // The VBUS voltage is above the A VBUS Valid threshold.
	USB0_OTGSTAT_BSESSEND_Pos        = 0x2  // Position of BSESSEND field.
	USB0_OTGSTAT_BSESSEND_Msk        = 0x4  // Bit mask of BSESSEND field.
	USB0_OTGSTAT_BSESSEND            = 0x4  // Bit BSESSEND.
	USB0_OTGSTAT_BSESSEND_0          = 0x0  // The VBUS voltage is above the B session end threshold.
	USB0_OTGSTAT_BSESSEND_1          = 0x1  // The VBUS voltage is below the B session end threshold.
	USB0_OTGSTAT_SESS_VLD_Pos        = 0x3  // Position of SESS_VLD field.
	USB0_OTGSTAT_SESS_VLD_Msk        = 0x8  // Bit mask of SESS_VLD field.
	USB0_OTGSTAT_SESS_VLD            = 0x8  // Bit SESS_VLD.
	USB0_OTGSTAT_SESS_VLD_0          = 0x0  // The VBUS voltage is below the B session valid threshold
	USB0_OTGSTAT_SESS_VLD_1          = 0x1  // The VBUS voltage is above the B session valid threshold.
	USB0_OTGSTAT_LINESTATESTABLE_Pos = 0x5  // Position of LINESTATESTABLE field.
	USB0_OTGSTAT_LINESTATESTABLE_Msk = 0x20 // Bit mask of LINESTATESTABLE field.
	USB0_OTGSTAT_LINESTATESTABLE     = 0x20 // Bit LINESTATESTABLE.
	USB0_OTGSTAT_LINESTATESTABLE_0   = 0x0  // The LINE_STAT_CHG bit is not yet stable.
	USB0_OTGSTAT_LINESTATESTABLE_1   = 0x1  // The LINE_STAT_CHG bit has been debounced and is stable.
	USB0_OTGSTAT_ONEMSECEN_Pos       = 0x6  // Position of ONEMSECEN field.
	USB0_OTGSTAT_ONEMSECEN_Msk       = 0x40 // Bit mask of ONEMSECEN field.
	USB0_OTGSTAT_ONEMSECEN           = 0x40 // Bit ONEMSECEN.
	USB0_OTGSTAT_ID_Pos              = 0x7  // Position of ID field.
	USB0_OTGSTAT_ID_Msk              = 0x80 // Bit mask of ID field.
	USB0_OTGSTAT_ID                  = 0x80 // Bit ID.
	USB0_OTGSTAT_ID_0                = 0x0  // Indicates a Type A cable is plugged into the USB connector.
	USB0_OTGSTAT_ID_1                = 0x1  // Indicates no cable is attached or a Type B cable is plugged into the USB connector.

	// OTGCTL: OTG Control register
	USB0_OTGCTL_OTGEN_Pos  = 0x2  // Position of OTGEN field.
	USB0_OTGCTL_OTGEN_Msk  = 0x4  // Bit mask of OTGEN field.
	USB0_OTGCTL_OTGEN      = 0x4  // Bit OTGEN.
	USB0_OTGCTL_OTGEN_0    = 0x0  // If USB_EN is 1 and HOST_MODE is 0 in the Control Register (CTL), then the D+ Data Line pull-up resistors are enabled. If HOST_MODE is 1 the D+ and D- Data Line pull-down resistors are engaged.
	USB0_OTGCTL_OTGEN_1    = 0x1  // The pull-up and pull-down controls in this register are used.
	USB0_OTGCTL_DMLOW_Pos  = 0x4  // Position of DMLOW field.
	USB0_OTGCTL_DMLOW_Msk  = 0x10 // Bit mask of DMLOW field.
	USB0_OTGCTL_DMLOW      = 0x10 // Bit DMLOW.
	USB0_OTGCTL_DMLOW_0    = 0x0  // D- pulldown resistor is not enabled.
	USB0_OTGCTL_DMLOW_1    = 0x1  // D- pulldown resistor is enabled.
	USB0_OTGCTL_DPLOW_Pos  = 0x5  // Position of DPLOW field.
	USB0_OTGCTL_DPLOW_Msk  = 0x20 // Bit mask of DPLOW field.
	USB0_OTGCTL_DPLOW      = 0x20 // Bit DPLOW.
	USB0_OTGCTL_DPLOW_0    = 0x0  // D+ pulldown resistor is not enabled.
	USB0_OTGCTL_DPLOW_1    = 0x1  // D+ pulldown resistor is enabled.
	USB0_OTGCTL_DPHIGH_Pos = 0x7  // Position of DPHIGH field.
	USB0_OTGCTL_DPHIGH_Msk = 0x80 // Bit mask of DPHIGH field.
	USB0_OTGCTL_DPHIGH     = 0x80 // Bit DPHIGH.
	USB0_OTGCTL_DPHIGH_0   = 0x0  // D+ pullup resistor is not enabled
	USB0_OTGCTL_DPHIGH_1   = 0x1  // D+ pullup resistor is enabled

	// ISTAT: Interrupt Status register
	USB0_ISTAT_USBRST_Pos = 0x0  // Position of USBRST field.
	USB0_ISTAT_USBRST_Msk = 0x1  // Bit mask of USBRST field.
	USB0_ISTAT_USBRST     = 0x1  // Bit USBRST.
	USB0_ISTAT_ERROR_Pos  = 0x1  // Position of ERROR field.
	USB0_ISTAT_ERROR_Msk  = 0x2  // Bit mask of ERROR field.
	USB0_ISTAT_ERROR      = 0x2  // Bit ERROR.
	USB0_ISTAT_SOFTOK_Pos = 0x2  // Position of SOFTOK field.
	USB0_ISTAT_SOFTOK_Msk = 0x4  // Bit mask of SOFTOK field.
	USB0_ISTAT_SOFTOK     = 0x4  // Bit SOFTOK.
	USB0_ISTAT_TOKDNE_Pos = 0x3  // Position of TOKDNE field.
	USB0_ISTAT_TOKDNE_Msk = 0x8  // Bit mask of TOKDNE field.
	USB0_ISTAT_TOKDNE     = 0x8  // Bit TOKDNE.
	USB0_ISTAT_SLEEP_Pos  = 0x4  // Position of SLEEP field.
	USB0_ISTAT_SLEEP_Msk  = 0x10 // Bit mask of SLEEP field.
	USB0_ISTAT_SLEEP      = 0x10 // Bit SLEEP.
	USB0_ISTAT_RESUME_Pos = 0x5  // Position of RESUME field.
	USB0_ISTAT_RESUME_Msk = 0x20 // Bit mask of RESUME field.
	USB0_ISTAT_RESUME     = 0x20 // Bit RESUME.
	USB0_ISTAT_ATTACH_Pos = 0x6  // Position of ATTACH field.
	USB0_ISTAT_ATTACH_Msk = 0x40 // Bit mask of ATTACH field.
	USB0_ISTAT_ATTACH     = 0x40 // Bit ATTACH.
	USB0_ISTAT_STALL_Pos  = 0x7  // Position of STALL field.
	USB0_ISTAT_STALL_Msk  = 0x80 // Bit mask of STALL field.
	USB0_ISTAT_STALL      = 0x80 // Bit STALL.

	// INTEN: Interrupt Enable register
	USB0_INTEN_USBRSTEN_Pos = 0x0  // Position of USBRSTEN field.
	USB0_INTEN_USBRSTEN_Msk = 0x1  // Bit mask of USBRSTEN field.
	USB0_INTEN_USBRSTEN     = 0x1  // Bit USBRSTEN.
	USB0_INTEN_USBRSTEN_0   = 0x0  // Disables the USBRST interrupt.
	USB0_INTEN_USBRSTEN_1   = 0x1  // Enables the USBRST interrupt.
	USB0_INTEN_ERROREN_Pos  = 0x1  // Position of ERROREN field.
	USB0_INTEN_ERROREN_Msk  = 0x2  // Bit mask of ERROREN field.
	USB0_INTEN_ERROREN      = 0x2  // Bit ERROREN.
	USB0_INTEN_ERROREN_0    = 0x0  // Disables the ERROR interrupt.
	USB0_INTEN_ERROREN_1    = 0x1  // Enables the ERROR interrupt.
	USB0_INTEN_SOFTOKEN_Pos = 0x2  // Position of SOFTOKEN field.
	USB0_INTEN_SOFTOKEN_Msk = 0x4  // Bit mask of SOFTOKEN field.
	USB0_INTEN_SOFTOKEN     = 0x4  // Bit SOFTOKEN.
	USB0_INTEN_SOFTOKEN_0   = 0x0  // Disbles the SOFTOK interrupt.
	USB0_INTEN_SOFTOKEN_1   = 0x1  // Enables the SOFTOK interrupt.
	USB0_INTEN_TOKDNEEN_Pos = 0x3  // Position of TOKDNEEN field.
	USB0_INTEN_TOKDNEEN_Msk = 0x8  // Bit mask of TOKDNEEN field.
	USB0_INTEN_TOKDNEEN     = 0x8  // Bit TOKDNEEN.
	USB0_INTEN_TOKDNEEN_0   = 0x0  // Disables the TOKDNE interrupt.
	USB0_INTEN_TOKDNEEN_1   = 0x1  // Enables the TOKDNE interrupt.
	USB0_INTEN_SLEEPEN_Pos  = 0x4  // Position of SLEEPEN field.
	USB0_INTEN_SLEEPEN_Msk  = 0x10 // Bit mask of SLEEPEN field.
	USB0_INTEN_SLEEPEN      = 0x10 // Bit SLEEPEN.
	USB0_INTEN_SLEEPEN_0    = 0x0  // Disables the SLEEP interrupt.
	USB0_INTEN_SLEEPEN_1    = 0x1  // Enables the SLEEP interrupt.
	USB0_INTEN_RESUMEEN_Pos = 0x5  // Position of RESUMEEN field.
	USB0_INTEN_RESUMEEN_Msk = 0x20 // Bit mask of RESUMEEN field.
	USB0_INTEN_RESUMEEN     = 0x20 // Bit RESUMEEN.
	USB0_INTEN_RESUMEEN_0   = 0x0  // Disables the RESUME interrupt.
	USB0_INTEN_RESUMEEN_1   = 0x1  // Enables the RESUME interrupt.
	USB0_INTEN_ATTACHEN_Pos = 0x6  // Position of ATTACHEN field.
	USB0_INTEN_ATTACHEN_Msk = 0x40 // Bit mask of ATTACHEN field.
	USB0_INTEN_ATTACHEN     = 0x40 // Bit ATTACHEN.
	USB0_INTEN_ATTACHEN_0   = 0x0  // Disables the ATTACH interrupt.
	USB0_INTEN_ATTACHEN_1   = 0x1  // Enables the ATTACH interrupt.
	USB0_INTEN_STALLEN_Pos  = 0x7  // Position of STALLEN field.
	USB0_INTEN_STALLEN_Msk  = 0x80 // Bit mask of STALLEN field.
	USB0_INTEN_STALLEN      = 0x80 // Bit STALLEN.
	USB0_INTEN_STALLEN_0    = 0x0  // Diasbles the STALL interrupt.
	USB0_INTEN_STALLEN_1    = 0x1  // Enables the STALL interrupt.

	// ERRSTAT: Error Interrupt Status register
	USB0_ERRSTAT_PIDERR_Pos  = 0x0  // Position of PIDERR field.
	USB0_ERRSTAT_PIDERR_Msk  = 0x1  // Bit mask of PIDERR field.
	USB0_ERRSTAT_PIDERR      = 0x1  // Bit PIDERR.
	USB0_ERRSTAT_CRC5EOF_Pos = 0x1  // Position of CRC5EOF field.
	USB0_ERRSTAT_CRC5EOF_Msk = 0x2  // Bit mask of CRC5EOF field.
	USB0_ERRSTAT_CRC5EOF     = 0x2  // Bit CRC5EOF.
	USB0_ERRSTAT_CRC16_Pos   = 0x2  // Position of CRC16 field.
	USB0_ERRSTAT_CRC16_Msk   = 0x4  // Bit mask of CRC16 field.
	USB0_ERRSTAT_CRC16       = 0x4  // Bit CRC16.
	USB0_ERRSTAT_DFN8_Pos    = 0x3  // Position of DFN8 field.
	USB0_ERRSTAT_DFN8_Msk    = 0x8  // Bit mask of DFN8 field.
	USB0_ERRSTAT_DFN8        = 0x8  // Bit DFN8.
	USB0_ERRSTAT_BTOERR_Pos  = 0x4  // Position of BTOERR field.
	USB0_ERRSTAT_BTOERR_Msk  = 0x10 // Bit mask of BTOERR field.
	USB0_ERRSTAT_BTOERR      = 0x10 // Bit BTOERR.
	USB0_ERRSTAT_DMAERR_Pos  = 0x5  // Position of DMAERR field.
	USB0_ERRSTAT_DMAERR_Msk  = 0x20 // Bit mask of DMAERR field.
	USB0_ERRSTAT_DMAERR      = 0x20 // Bit DMAERR.
	USB0_ERRSTAT_BTSERR_Pos  = 0x7  // Position of BTSERR field.
	USB0_ERRSTAT_BTSERR_Msk  = 0x80 // Bit mask of BTSERR field.
	USB0_ERRSTAT_BTSERR      = 0x80 // Bit BTSERR.

	// ERREN: Error Interrupt Enable register
	USB0_ERREN_PIDERREN_Pos  = 0x0  // Position of PIDERREN field.
	USB0_ERREN_PIDERREN_Msk  = 0x1  // Bit mask of PIDERREN field.
	USB0_ERREN_PIDERREN      = 0x1  // Bit PIDERREN.
	USB0_ERREN_PIDERREN_0    = 0x0  // Disables the PIDERR interrupt.
	USB0_ERREN_PIDERREN_1    = 0x1  // Enters the PIDERR interrupt.
	USB0_ERREN_CRC5EOFEN_Pos = 0x1  // Position of CRC5EOFEN field.
	USB0_ERREN_CRC5EOFEN_Msk = 0x2  // Bit mask of CRC5EOFEN field.
	USB0_ERREN_CRC5EOFEN     = 0x2  // Bit CRC5EOFEN.
	USB0_ERREN_CRC5EOFEN_0   = 0x0  // Disables the CRC5/EOF interrupt.
	USB0_ERREN_CRC5EOFEN_1   = 0x1  // Enables the CRC5/EOF interrupt.
	USB0_ERREN_CRC16EN_Pos   = 0x2  // Position of CRC16EN field.
	USB0_ERREN_CRC16EN_Msk   = 0x4  // Bit mask of CRC16EN field.
	USB0_ERREN_CRC16EN       = 0x4  // Bit CRC16EN.
	USB0_ERREN_CRC16EN_0     = 0x0  // Disables the CRC16 interrupt.
	USB0_ERREN_CRC16EN_1     = 0x1  // Enables the CRC16 interrupt.
	USB0_ERREN_DFN8EN_Pos    = 0x3  // Position of DFN8EN field.
	USB0_ERREN_DFN8EN_Msk    = 0x8  // Bit mask of DFN8EN field.
	USB0_ERREN_DFN8EN        = 0x8  // Bit DFN8EN.
	USB0_ERREN_DFN8EN_0      = 0x0  // Disables the DFN8 interrupt.
	USB0_ERREN_DFN8EN_1      = 0x1  // Enables the DFN8 interrupt.
	USB0_ERREN_BTOERREN_Pos  = 0x4  // Position of BTOERREN field.
	USB0_ERREN_BTOERREN_Msk  = 0x10 // Bit mask of BTOERREN field.
	USB0_ERREN_BTOERREN      = 0x10 // Bit BTOERREN.
	USB0_ERREN_BTOERREN_0    = 0x0  // Disables the BTOERR interrupt.
	USB0_ERREN_BTOERREN_1    = 0x1  // Enables the BTOERR interrupt.
	USB0_ERREN_DMAERREN_Pos  = 0x5  // Position of DMAERREN field.
	USB0_ERREN_DMAERREN_Msk  = 0x20 // Bit mask of DMAERREN field.
	USB0_ERREN_DMAERREN      = 0x20 // Bit DMAERREN.
	USB0_ERREN_DMAERREN_0    = 0x0  // Disables the DMAERR interrupt.
	USB0_ERREN_DMAERREN_1    = 0x1  // Enables the DMAERR interrupt.
	USB0_ERREN_BTSERREN_Pos  = 0x7  // Position of BTSERREN field.
	USB0_ERREN_BTSERREN_Msk  = 0x80 // Bit mask of BTSERREN field.
	USB0_ERREN_BTSERREN      = 0x80 // Bit BTSERREN.
	USB0_ERREN_BTSERREN_0    = 0x0  // Disables the BTSERR interrupt.
	USB0_ERREN_BTSERREN_1    = 0x1  // Enables the BTSERR interrupt.

	// STAT: Status register
	USB0_STAT_ODD_Pos  = 0x2  // Position of ODD field.
	USB0_STAT_ODD_Msk  = 0x4  // Bit mask of ODD field.
	USB0_STAT_ODD      = 0x4  // Bit ODD.
	USB0_STAT_TX_Pos   = 0x3  // Position of TX field.
	USB0_STAT_TX_Msk   = 0x8  // Bit mask of TX field.
	USB0_STAT_TX       = 0x8  // Bit TX.
	USB0_STAT_TX_0     = 0x0  // The most recent transaction was a receive operation.
	USB0_STAT_TX_1     = 0x1  // The most recent transaction was a transmit operation.
	USB0_STAT_ENDP_Pos = 0x4  // Position of ENDP field.
	USB0_STAT_ENDP_Msk = 0xf0 // Bit mask of ENDP field.

	// CTL: Control register
	USB0_CTL_USBENSOFEN_Pos         = 0x0  // Position of USBENSOFEN field.
	USB0_CTL_USBENSOFEN_Msk         = 0x1  // Bit mask of USBENSOFEN field.
	USB0_CTL_USBENSOFEN             = 0x1  // Bit USBENSOFEN.
	USB0_CTL_USBENSOFEN_0           = 0x0  // Disables the USB Module.
	USB0_CTL_USBENSOFEN_1           = 0x1  // Enables the USB Module.
	USB0_CTL_ODDRST_Pos             = 0x1  // Position of ODDRST field.
	USB0_CTL_ODDRST_Msk             = 0x2  // Bit mask of ODDRST field.
	USB0_CTL_ODDRST                 = 0x2  // Bit ODDRST.
	USB0_CTL_RESUME_Pos             = 0x2  // Position of RESUME field.
	USB0_CTL_RESUME_Msk             = 0x4  // Bit mask of RESUME field.
	USB0_CTL_RESUME                 = 0x4  // Bit RESUME.
	USB0_CTL_HOSTMODEEN_Pos         = 0x3  // Position of HOSTMODEEN field.
	USB0_CTL_HOSTMODEEN_Msk         = 0x8  // Bit mask of HOSTMODEEN field.
	USB0_CTL_HOSTMODEEN             = 0x8  // Bit HOSTMODEEN.
	USB0_CTL_RESET_Pos              = 0x4  // Position of RESET field.
	USB0_CTL_RESET_Msk              = 0x10 // Bit mask of RESET field.
	USB0_CTL_RESET                  = 0x10 // Bit RESET.
	USB0_CTL_TXSUSPENDTOKENBUSY_Pos = 0x5  // Position of TXSUSPENDTOKENBUSY field.
	USB0_CTL_TXSUSPENDTOKENBUSY_Msk = 0x20 // Bit mask of TXSUSPENDTOKENBUSY field.
	USB0_CTL_TXSUSPENDTOKENBUSY     = 0x20 // Bit TXSUSPENDTOKENBUSY.
	USB0_CTL_SE0_Pos                = 0x6  // Position of SE0 field.
	USB0_CTL_SE0_Msk                = 0x40 // Bit mask of SE0 field.
	USB0_CTL_SE0                    = 0x40 // Bit SE0.
	USB0_CTL_JSTATE_Pos             = 0x7  // Position of JSTATE field.
	USB0_CTL_JSTATE_Msk             = 0x80 // Bit mask of JSTATE field.
	USB0_CTL_JSTATE                 = 0x80 // Bit JSTATE.

	// ADDR: Address register
	USB0_ADDR_ADDR_Pos = 0x0  // Position of ADDR field.
	USB0_ADDR_ADDR_Msk = 0x7f // Bit mask of ADDR field.
	USB0_ADDR_LSEN_Pos = 0x7  // Position of LSEN field.
	USB0_ADDR_LSEN_Msk = 0x80 // Bit mask of LSEN field.
	USB0_ADDR_LSEN     = 0x80 // Bit LSEN.

	// BDTPAGE1: BDT Page register 1
	USB0_BDTPAGE1_BDTBA_Pos = 0x1  // Position of BDTBA field.
	USB0_BDTPAGE1_BDTBA_Msk = 0xfe // Bit mask of BDTBA field.

	// FRMNUML: Frame Number register Low
	USB0_FRMNUML_FRM_Pos = 0x0  // Position of FRM field.
	USB0_FRMNUML_FRM_Msk = 0xff // Bit mask of FRM field.

	// FRMNUMH: Frame Number register High
	USB0_FRMNUMH_FRM_Pos = 0x0 // Position of FRM field.
	USB0_FRMNUMH_FRM_Msk = 0x7 // Bit mask of FRM field.

	// TOKEN: Token register
	USB0_TOKEN_TOKENENDPT_Pos = 0x0  // Position of TOKENENDPT field.
	USB0_TOKEN_TOKENENDPT_Msk = 0xf  // Bit mask of TOKENENDPT field.
	USB0_TOKEN_TOKENPID_Pos   = 0x4  // Position of TOKENPID field.
	USB0_TOKEN_TOKENPID_Msk   = 0xf0 // Bit mask of TOKENPID field.
	USB0_TOKEN_TOKENPID_0001  = 0x1  // OUT Token. USB Module performs an OUT (TX) transaction.
	USB0_TOKEN_TOKENPID_1001  = 0x9  // IN Token. USB Module performs an In (RX) transaction.
	USB0_TOKEN_TOKENPID_1101  = 0xd  // SETUP Token. USB Module performs a SETUP (TX) transaction

	// SOFTHLD: SOF Threshold register
	USB0_SOFTHLD_CNT_Pos = 0x0  // Position of CNT field.
	USB0_SOFTHLD_CNT_Msk = 0xff // Bit mask of CNT field.

	// BDTPAGE2: BDT Page Register 2
	USB0_BDTPAGE2_BDTBA_Pos = 0x0  // Position of BDTBA field.
	USB0_BDTPAGE2_BDTBA_Msk = 0xff // Bit mask of BDTBA field.

	// BDTPAGE3: BDT Page Register 3
	USB0_BDTPAGE3_BDTBA_Pos = 0x0  // Position of BDTBA field.
	USB0_BDTPAGE3_BDTBA_Msk = 0xff // Bit mask of BDTBA field.

	// ENDPT0: Endpoint Control register
	USB0_ENDPT_EPHSHK_Pos    = 0x0  // Position of EPHSHK field.
	USB0_ENDPT_EPHSHK_Msk    = 0x1  // Bit mask of EPHSHK field.
	USB0_ENDPT_EPHSHK        = 0x1  // Bit EPHSHK.
	USB0_ENDPT_EPSTALL_Pos   = 0x1  // Position of EPSTALL field.
	USB0_ENDPT_EPSTALL_Msk   = 0x2  // Bit mask of EPSTALL field.
	USB0_ENDPT_EPSTALL       = 0x2  // Bit EPSTALL.
	USB0_ENDPT_EPTXEN_Pos    = 0x2  // Position of EPTXEN field.
	USB0_ENDPT_EPTXEN_Msk    = 0x4  // Bit mask of EPTXEN field.
	USB0_ENDPT_EPTXEN        = 0x4  // Bit EPTXEN.
	USB0_ENDPT_EPRXEN_Pos    = 0x3  // Position of EPRXEN field.
	USB0_ENDPT_EPRXEN_Msk    = 0x8  // Bit mask of EPRXEN field.
	USB0_ENDPT_EPRXEN        = 0x8  // Bit EPRXEN.
	USB0_ENDPT_EPCTLDIS_Pos  = 0x4  // Position of EPCTLDIS field.
	USB0_ENDPT_EPCTLDIS_Msk  = 0x10 // Bit mask of EPCTLDIS field.
	USB0_ENDPT_EPCTLDIS      = 0x10 // Bit EPCTLDIS.
	USB0_ENDPT_RETRYDIS_Pos  = 0x6  // Position of RETRYDIS field.
	USB0_ENDPT_RETRYDIS_Msk  = 0x40 // Bit mask of RETRYDIS field.
	USB0_ENDPT_RETRYDIS      = 0x40 // Bit RETRYDIS.
	USB0_ENDPT_HOSTWOHUB_Pos = 0x7  // Position of HOSTWOHUB field.
	USB0_ENDPT_HOSTWOHUB_Msk = 0x80 // Bit mask of HOSTWOHUB field.
	USB0_ENDPT_HOSTWOHUB     = 0x80 // Bit HOSTWOHUB.

	// USBCTRL: USB Control register
	USB0_USBCTRL_PDE_Pos  = 0x6  // Position of PDE field.
	USB0_USBCTRL_PDE_Msk  = 0x40 // Bit mask of PDE field.
	USB0_USBCTRL_PDE      = 0x40 // Bit PDE.
	USB0_USBCTRL_PDE_0    = 0x0  // Weak pulldowns are disabled on D+ and D-.
	USB0_USBCTRL_PDE_1    = 0x1  // Weak pulldowns are enabled on D+ and D-.
	USB0_USBCTRL_SUSP_Pos = 0x7  // Position of SUSP field.
	USB0_USBCTRL_SUSP_Msk = 0x80 // Bit mask of SUSP field.
	USB0_USBCTRL_SUSP     = 0x80 // Bit SUSP.
	USB0_USBCTRL_SUSP_0   = 0x0  // USB transceiver is not in suspend state.
	USB0_USBCTRL_SUSP_1   = 0x1  // USB transceiver is in suspend state.

	// OBSERVE: USB OTG Observe register
	USB0_OBSERVE_DMPD_Pos = 0x4  // Position of DMPD field.
	USB0_OBSERVE_DMPD_Msk = 0x10 // Bit mask of DMPD field.
	USB0_OBSERVE_DMPD     = 0x10 // Bit DMPD.
	USB0_OBSERVE_DMPD_0   = 0x0  // D- pulldown disabled.
	USB0_OBSERVE_DMPD_1   = 0x1  // D- pulldown enabled.
	USB0_OBSERVE_DPPD_Pos = 0x6  // Position of DPPD field.
	USB0_OBSERVE_DPPD_Msk = 0x40 // Bit mask of DPPD field.
	USB0_OBSERVE_DPPD     = 0x40 // Bit DPPD.
	USB0_OBSERVE_DPPD_0   = 0x0  // D+ pulldown disabled.
	USB0_OBSERVE_DPPD_1   = 0x1  // D+ pulldown enabled.
	USB0_OBSERVE_DPPU_Pos = 0x7  // Position of DPPU field.
	USB0_OBSERVE_DPPU_Msk = 0x80 // Bit mask of DPPU field.
	USB0_OBSERVE_DPPU     = 0x80 // Bit DPPU.
	USB0_OBSERVE_DPPU_0   = 0x0  // D+ pullup disabled.
	USB0_OBSERVE_DPPU_1   = 0x1  // D+ pullup enabled.

	// CONTROL: USB OTG Control register
	USB0_CONTROL_DPPULLUPNONOTG_Pos = 0x4  // Position of DPPULLUPNONOTG field.
	USB0_CONTROL_DPPULLUPNONOTG_Msk = 0x10 // Bit mask of DPPULLUPNONOTG field.
	USB0_CONTROL_DPPULLUPNONOTG     = 0x10 // Bit DPPULLUPNONOTG.
	USB0_CONTROL_DPPULLUPNONOTG_0   = 0x0  // DP Pullup in non-OTG device mode is not enabled.
	USB0_CONTROL_DPPULLUPNONOTG_1   = 0x1  // DP Pullup in non-OTG device mode is enabled.

	// USBTRC0: USB Transceiver Control register 0
	USB0_USBTRC0_USB_RESUME_INT_Pos       = 0x0  // Position of USB_RESUME_INT field.
	USB0_USBTRC0_USB_RESUME_INT_Msk       = 0x1  // Bit mask of USB_RESUME_INT field.
	USB0_USBTRC0_USB_RESUME_INT           = 0x1  // Bit USB_RESUME_INT.
	USB0_USBTRC0_USB_RESUME_INT_0         = 0x0  // No interrupt was generated.
	USB0_USBTRC0_USB_RESUME_INT_1         = 0x1  // Interrupt was generated because of the USB asynchronous interrupt.
	USB0_USBTRC0_SYNC_DET_Pos             = 0x1  // Position of SYNC_DET field.
	USB0_USBTRC0_SYNC_DET_Msk             = 0x2  // Bit mask of SYNC_DET field.
	USB0_USBTRC0_SYNC_DET                 = 0x2  // Bit SYNC_DET.
	USB0_USBTRC0_SYNC_DET_0               = 0x0  // Synchronous interrupt has not been detected.
	USB0_USBTRC0_SYNC_DET_1               = 0x1  // Synchronous interrupt has been detected.
	USB0_USBTRC0_USB_CLK_RECOVERY_INT_Pos = 0x2  // Position of USB_CLK_RECOVERY_INT field.
	USB0_USBTRC0_USB_CLK_RECOVERY_INT_Msk = 0x4  // Bit mask of USB_CLK_RECOVERY_INT field.
	USB0_USBTRC0_USB_CLK_RECOVERY_INT     = 0x4  // Bit USB_CLK_RECOVERY_INT.
	USB0_USBTRC0_USBRESMEN_Pos            = 0x5  // Position of USBRESMEN field.
	USB0_USBTRC0_USBRESMEN_Msk            = 0x20 // Bit mask of USBRESMEN field.
	USB0_USBTRC0_USBRESMEN                = 0x20 // Bit USBRESMEN.
	USB0_USBTRC0_USBRESMEN_0              = 0x0  // USB asynchronous wakeup from suspend mode disabled.
	USB0_USBTRC0_USBRESMEN_1              = 0x1  // USB asynchronous wakeup from suspend mode enabled. The asynchronous resume interrupt differs from the synchronous resume interrupt in that it asynchronously detects K-state using the unfiltered state of the D+ and D- pins. This interrupt should only be enabled when the Transceiver is suspended.
	USB0_USBTRC0_USBRESET_Pos             = 0x7  // Position of USBRESET field.
	USB0_USBTRC0_USBRESET_Msk             = 0x80 // Bit mask of USBRESET field.
	USB0_USBTRC0_USBRESET                 = 0x80 // Bit USBRESET.
	USB0_USBTRC0_USBRESET_0               = 0x0  // Normal USB module operation.
	USB0_USBTRC0_USBRESET_1               = 0x1  // Returns the USB module to its reset state.

	// USBFRMADJUST: Frame Adjust Register
	USB0_USBFRMADJUST_ADJ_Pos = 0x0  // Position of ADJ field.
	USB0_USBFRMADJUST_ADJ_Msk = 0xff // Bit mask of ADJ field.

	// CLK_RECOVER_CTRL: USB Clock recovery control
	USB0_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_Pos    = 0x5  // Position of RESTART_IFRTRIM_EN field.
	USB0_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_Msk    = 0x20 // Bit mask of RESTART_IFRTRIM_EN field.
	USB0_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN        = 0x20 // Bit RESTART_IFRTRIM_EN.
	USB0_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_0      = 0x0  // Trim fine adjustment always works based on the previous updated trim fine value (default)
	USB0_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_1      = 0x1  // Trim fine restarts from the IFR trim value whenever bus_reset/bus_resume is detected or module enable is desasserted
	USB0_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_Pos = 0x6  // Position of RESET_RESUME_ROUGH_EN field.
	USB0_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_Msk = 0x40 // Bit mask of RESET_RESUME_ROUGH_EN field.
	USB0_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN     = 0x40 // Bit RESET_RESUME_ROUGH_EN.
	USB0_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_0   = 0x0  // Always works in tracking phase after the 1st time rough to track transition (default)
	USB0_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_1   = 0x1  // Go back to rough stage whenever bus reset or bus resume occurs
	USB0_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_Pos      = 0x7  // Position of CLOCK_RECOVER_EN field.
	USB0_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_Msk      = 0x80 // Bit mask of CLOCK_RECOVER_EN field.
	USB0_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN          = 0x80 // Bit CLOCK_RECOVER_EN.
	USB0_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_0        = 0x0  // Disable clock recovery block (default)
	USB0_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_1        = 0x1  // Enable clock recovery block

	// CLK_RECOVER_IRC_EN: IRC48M oscillator enable register
	USB0_CLK_RECOVER_IRC_EN_REG_EN_Pos = 0x0 // Position of REG_EN field.
	USB0_CLK_RECOVER_IRC_EN_REG_EN_Msk = 0x1 // Bit mask of REG_EN field.
	USB0_CLK_RECOVER_IRC_EN_REG_EN     = 0x1 // Bit REG_EN.
	USB0_CLK_RECOVER_IRC_EN_REG_EN_0   = 0x0 // IRC48M local regulator is disabled
	USB0_CLK_RECOVER_IRC_EN_REG_EN_1   = 0x1 // IRC48M local regulator is enabled (default)
	USB0_CLK_RECOVER_IRC_EN_IRC_EN_Pos = 0x1 // Position of IRC_EN field.
	USB0_CLK_RECOVER_IRC_EN_IRC_EN_Msk = 0x2 // Bit mask of IRC_EN field.
	USB0_CLK_RECOVER_IRC_EN_IRC_EN     = 0x2 // Bit IRC_EN.
	USB0_CLK_RECOVER_IRC_EN_IRC_EN_0   = 0x0 // Disable the IRC48M module (default)
	USB0_CLK_RECOVER_IRC_EN_IRC_EN_1   = 0x1 // Enable the IRC48M module

	// CLK_RECOVER_INT_STATUS: Clock recovery separated interrupt status
	USB0_CLK_RECOVER_INT_STATUS_OVF_ERROR_Pos = 0x4  // Position of OVF_ERROR field.
	USB0_CLK_RECOVER_INT_STATUS_OVF_ERROR_Msk = 0x10 // Bit mask of OVF_ERROR field.
	USB0_CLK_RECOVER_INT_STATUS_OVF_ERROR     = 0x10 // Bit OVF_ERROR.
	USB0_CLK_RECOVER_INT_STATUS_OVF_ERROR_0   = 0x0  // No interrupt is reported
	USB0_CLK_RECOVER_INT_STATUS_OVF_ERROR_1   = 0x1  // Unmasked interrupt has been generated
)

// Bitfields for CMP0: High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)
const (
	// CR0: CMP Control Register 0
	CMP_CR0_HYSTCTR_Pos    = 0x0  // Position of HYSTCTR field.
	CMP_CR0_HYSTCTR_Msk    = 0x3  // Bit mask of HYSTCTR field.
	CMP_CR0_HYSTCTR_00     = 0x0  // Level 0
	CMP_CR0_HYSTCTR_01     = 0x1  // Level 1
	CMP_CR0_HYSTCTR_10     = 0x2  // Level 2
	CMP_CR0_HYSTCTR_11     = 0x3  // Level 3
	CMP_CR0_FILTER_CNT_Pos = 0x4  // Position of FILTER_CNT field.
	CMP_CR0_FILTER_CNT_Msk = 0x70 // Bit mask of FILTER_CNT field.
	CMP_CR0_FILTER_CNT_000 = 0x0  // Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA.
	CMP_CR0_FILTER_CNT_001 = 0x1  // One sample must agree. The comparator output is simply sampled.
	CMP_CR0_FILTER_CNT_010 = 0x2  // 2 consecutive samples must agree.
	CMP_CR0_FILTER_CNT_011 = 0x3  // 3 consecutive samples must agree.
	CMP_CR0_FILTER_CNT_100 = 0x4  // 4 consecutive samples must agree.
	CMP_CR0_FILTER_CNT_101 = 0x5  // 5 consecutive samples must agree.
	CMP_CR0_FILTER_CNT_110 = 0x6  // 6 consecutive samples must agree.
	CMP_CR0_FILTER_CNT_111 = 0x7  // 7 consecutive samples must agree.

	// CR1: CMP Control Register 1
	CMP_CR1_EN_Pos    = 0x0  // Position of EN field.
	CMP_CR1_EN_Msk    = 0x1  // Bit mask of EN field.
	CMP_CR1_EN        = 0x1  // Bit EN.
	CMP_CR1_EN_0      = 0x0  // Analog Comparator is disabled.
	CMP_CR1_EN_1      = 0x1  // Analog Comparator is enabled.
	CMP_CR1_OPE_Pos   = 0x1  // Position of OPE field.
	CMP_CR1_OPE_Msk   = 0x2  // Bit mask of OPE field.
	CMP_CR1_OPE       = 0x2  // Bit OPE.
	CMP_CR1_OPE_0     = 0x0  // CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect.
	CMP_CR1_OPE_1     = 0x1  // CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect.
	CMP_CR1_COS_Pos   = 0x2  // Position of COS field.
	CMP_CR1_COS_Msk   = 0x4  // Bit mask of COS field.
	CMP_CR1_COS       = 0x4  // Bit COS.
	CMP_CR1_COS_0     = 0x0  // Set the filtered comparator output (CMPO) to equal COUT.
	CMP_CR1_COS_1     = 0x1  // Set the unfiltered comparator output (CMPO) to equal COUTA.
	CMP_CR1_INV_Pos   = 0x3  // Position of INV field.
	CMP_CR1_INV_Msk   = 0x8  // Bit mask of INV field.
	CMP_CR1_INV       = 0x8  // Bit INV.
	CMP_CR1_INV_0     = 0x0  // Does not invert the comparator output.
	CMP_CR1_INV_1     = 0x1  // Inverts the comparator output.
	CMP_CR1_PMODE_Pos = 0x4  // Position of PMODE field.
	CMP_CR1_PMODE_Msk = 0x10 // Bit mask of PMODE field.
	CMP_CR1_PMODE     = 0x10 // Bit PMODE.
	CMP_CR1_PMODE_0   = 0x0  // Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption.
	CMP_CR1_PMODE_1   = 0x1  // High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption.
	CMP_CR1_TRIGM_Pos = 0x5  // Position of TRIGM field.
	CMP_CR1_TRIGM_Msk = 0x20 // Bit mask of TRIGM field.
	CMP_CR1_TRIGM     = 0x20 // Bit TRIGM.
	CMP_CR1_TRIGM_0   = 0x0  // Trigger mode is disabled.
	CMP_CR1_TRIGM_1   = 0x1  // Trigger mode is enabled.
	CMP_CR1_WE_Pos    = 0x6  // Position of WE field.
	CMP_CR1_WE_Msk    = 0x40 // Bit mask of WE field.
	CMP_CR1_WE        = 0x40 // Bit WE.
	CMP_CR1_WE_0      = 0x0  // Windowing mode is not selected.
	CMP_CR1_WE_1      = 0x1  // Windowing mode is selected.
	CMP_CR1_SE_Pos    = 0x7  // Position of SE field.
	CMP_CR1_SE_Msk    = 0x80 // Bit mask of SE field.
	CMP_CR1_SE        = 0x80 // Bit SE.
	CMP_CR1_SE_0      = 0x0  // Sampling mode is not selected.
	CMP_CR1_SE_1      = 0x1  // Sampling mode is selected.

	// FPR: CMP Filter Period Register
	CMP_FPR_FILT_PER_Pos = 0x0  // Position of FILT_PER field.
	CMP_FPR_FILT_PER_Msk = 0xff // Bit mask of FILT_PER field.

	// SCR: CMP Status and Control Register
	CMP_SCR_COUT_Pos  = 0x0  // Position of COUT field.
	CMP_SCR_COUT_Msk  = 0x1  // Bit mask of COUT field.
	CMP_SCR_COUT      = 0x1  // Bit COUT.
	CMP_SCR_CFF_Pos   = 0x1  // Position of CFF field.
	CMP_SCR_CFF_Msk   = 0x2  // Bit mask of CFF field.
	CMP_SCR_CFF       = 0x2  // Bit CFF.
	CMP_SCR_CFF_0     = 0x0  // Falling-edge on COUT has not been detected.
	CMP_SCR_CFF_1     = 0x1  // Falling-edge on COUT has occurred.
	CMP_SCR_CFR_Pos   = 0x2  // Position of CFR field.
	CMP_SCR_CFR_Msk   = 0x4  // Bit mask of CFR field.
	CMP_SCR_CFR       = 0x4  // Bit CFR.
	CMP_SCR_CFR_0     = 0x0  // Rising-edge on COUT has not been detected.
	CMP_SCR_CFR_1     = 0x1  // Rising-edge on COUT has occurred.
	CMP_SCR_IEF_Pos   = 0x3  // Position of IEF field.
	CMP_SCR_IEF_Msk   = 0x8  // Bit mask of IEF field.
	CMP_SCR_IEF       = 0x8  // Bit IEF.
	CMP_SCR_IEF_0     = 0x0  // Interrupt is disabled.
	CMP_SCR_IEF_1     = 0x1  // Interrupt is enabled.
	CMP_SCR_IER_Pos   = 0x4  // Position of IER field.
	CMP_SCR_IER_Msk   = 0x10 // Bit mask of IER field.
	CMP_SCR_IER       = 0x10 // Bit IER.
	CMP_SCR_IER_0     = 0x0  // Interrupt is disabled.
	CMP_SCR_IER_1     = 0x1  // Interrupt is enabled.
	CMP_SCR_DMAEN_Pos = 0x6  // Position of DMAEN field.
	CMP_SCR_DMAEN_Msk = 0x40 // Bit mask of DMAEN field.
	CMP_SCR_DMAEN     = 0x40 // Bit DMAEN.
	CMP_SCR_DMAEN_0   = 0x0  // DMA is disabled.
	CMP_SCR_DMAEN_1   = 0x1  // DMA is enabled.

	// DACCR: DAC Control Register
	CMP_DACCR_VOSEL_Pos = 0x0  // Position of VOSEL field.
	CMP_DACCR_VOSEL_Msk = 0x3f // Bit mask of VOSEL field.
	CMP_DACCR_VRSEL_Pos = 0x6  // Position of VRSEL field.
	CMP_DACCR_VRSEL_Msk = 0x40 // Bit mask of VRSEL field.
	CMP_DACCR_VRSEL     = 0x40 // Bit VRSEL.
	CMP_DACCR_VRSEL_0   = 0x0  // V is selected as resistor ladder network supply reference V. in1 in
	CMP_DACCR_VRSEL_1   = 0x1  // V is selected as resistor ladder network supply reference V. in2 in
	CMP_DACCR_DACEN_Pos = 0x7  // Position of DACEN field.
	CMP_DACCR_DACEN_Msk = 0x80 // Bit mask of DACEN field.
	CMP_DACCR_DACEN     = 0x80 // Bit DACEN.
	CMP_DACCR_DACEN_0   = 0x0  // DAC is disabled.
	CMP_DACCR_DACEN_1   = 0x1  // DAC is enabled.

	// MUXCR: MUX Control Register
	CMP_MUXCR_MSEL_Pos = 0x0  // Position of MSEL field.
	CMP_MUXCR_MSEL_Msk = 0x7  // Bit mask of MSEL field.
	CMP_MUXCR_MSEL_000 = 0x0  // IN0
	CMP_MUXCR_MSEL_001 = 0x1  // IN1
	CMP_MUXCR_MSEL_010 = 0x2  // IN2
	CMP_MUXCR_MSEL_011 = 0x3  // IN3
	CMP_MUXCR_MSEL_100 = 0x4  // IN4
	CMP_MUXCR_MSEL_101 = 0x5  // IN5
	CMP_MUXCR_MSEL_110 = 0x6  // IN6
	CMP_MUXCR_MSEL_111 = 0x7  // IN7
	CMP_MUXCR_PSEL_Pos = 0x3  // Position of PSEL field.
	CMP_MUXCR_PSEL_Msk = 0x38 // Bit mask of PSEL field.
	CMP_MUXCR_PSEL_000 = 0x0  // IN0
	CMP_MUXCR_PSEL_001 = 0x1  // IN1
	CMP_MUXCR_PSEL_010 = 0x2  // IN2
	CMP_MUXCR_PSEL_011 = 0x3  // IN3
	CMP_MUXCR_PSEL_100 = 0x4  // IN4
	CMP_MUXCR_PSEL_101 = 0x5  // IN5
	CMP_MUXCR_PSEL_110 = 0x6  // IN6
	CMP_MUXCR_PSEL_111 = 0x7  // IN7
)

// Bitfields for VREF: Voltage Reference
const (
	// TRM: VREF Trim Register
	VREF_TRM_TRIM_Pos    = 0x0  // Position of TRIM field.
	VREF_TRM_TRIM_Msk    = 0x3f // Bit mask of TRIM field.
	VREF_TRM_TRIM_000000 = 0x0  // Min
	VREF_TRM_TRIM_111111 = 0x3f // Max
	VREF_TRM_CHOPEN_Pos  = 0x6  // Position of CHOPEN field.
	VREF_TRM_CHOPEN_Msk  = 0x40 // Bit mask of CHOPEN field.
	VREF_TRM_CHOPEN      = 0x40 // Bit CHOPEN.
	VREF_TRM_CHOPEN_0    = 0x0  // Chop oscillator is disabled.
	VREF_TRM_CHOPEN_1    = 0x1  // Chop oscillator is enabled.

	// SC: VREF Status and Control Register
	VREF_SC_MODE_LV_Pos = 0x0  // Position of MODE_LV field.
	VREF_SC_MODE_LV_Msk = 0x3  // Bit mask of MODE_LV field.
	VREF_SC_MODE_LV_00  = 0x0  // Bandgap on only, for stabilization and startup
	VREF_SC_MODE_LV_01  = 0x1  // High power buffer mode enabled
	VREF_SC_MODE_LV_10  = 0x2  // Low-power buffer mode enabled
	VREF_SC_VREFST_Pos  = 0x2  // Position of VREFST field.
	VREF_SC_VREFST_Msk  = 0x4  // Bit mask of VREFST field.
	VREF_SC_VREFST      = 0x4  // Bit VREFST.
	VREF_SC_VREFST_0    = 0x0  // The module is disabled or not stable.
	VREF_SC_VREFST_1    = 0x1  // The module is stable.
	VREF_SC_ICOMPEN_Pos = 0x5  // Position of ICOMPEN field.
	VREF_SC_ICOMPEN_Msk = 0x20 // Bit mask of ICOMPEN field.
	VREF_SC_ICOMPEN     = 0x20 // Bit ICOMPEN.
	VREF_SC_ICOMPEN_0   = 0x0  // Disabled
	VREF_SC_ICOMPEN_1   = 0x1  // Enabled
	VREF_SC_REGEN_Pos   = 0x6  // Position of REGEN field.
	VREF_SC_REGEN_Msk   = 0x40 // Bit mask of REGEN field.
	VREF_SC_REGEN       = 0x40 // Bit REGEN.
	VREF_SC_REGEN_0     = 0x0  // Internal 1.75 V regulator is disabled.
	VREF_SC_REGEN_1     = 0x1  // Internal 1.75 V regulator is enabled.
	VREF_SC_VREFEN_Pos  = 0x7  // Position of VREFEN field.
	VREF_SC_VREFEN_Msk  = 0x80 // Bit mask of VREFEN field.
	VREF_SC_VREFEN      = 0x80 // Bit VREFEN.
	VREF_SC_VREFEN_0    = 0x0  // The module is disabled.
	VREF_SC_VREFEN_1    = 0x1  // The module is enabled.
)

// Bitfields for LLWU: Low leakage wakeup unit
const (
	// PE1: LLWU Pin Enable 1 register
	LLWU_PE1_WUPE0_Pos = 0x0  // Position of WUPE0 field.
	LLWU_PE1_WUPE0_Msk = 0x3  // Bit mask of WUPE0 field.
	LLWU_PE1_WUPE0_00  = 0x0  // External input pin disabled as wakeup input
	LLWU_PE1_WUPE0_01  = 0x1  // External input pin enabled with rising edge detection
	LLWU_PE1_WUPE0_10  = 0x2  // External input pin enabled with falling edge detection
	LLWU_PE1_WUPE0_11  = 0x3  // External input pin enabled with any change detection
	LLWU_PE1_WUPE1_Pos = 0x2  // Position of WUPE1 field.
	LLWU_PE1_WUPE1_Msk = 0xc  // Bit mask of WUPE1 field.
	LLWU_PE1_WUPE1_00  = 0x0  // External input pin disabled as wakeup input
	LLWU_PE1_WUPE1_01  = 0x1  // External input pin enabled with rising edge detection
	LLWU_PE1_WUPE1_10  = 0x2  // External input pin enabled with falling edge detection
	LLWU_PE1_WUPE1_11  = 0x3  // External input pin enabled with any change detection
	LLWU_PE1_WUPE2_Pos = 0x4  // Position of WUPE2 field.
	LLWU_PE1_WUPE2_Msk = 0x30 // Bit mask of WUPE2 field.
	LLWU_PE1_WUPE2_00  = 0x0  // External input pin disabled as wakeup input
	LLWU_PE1_WUPE2_01  = 0x1  // External input pin enabled with rising edge detection
	LLWU_PE1_WUPE2_10  = 0x2  // External input pin enabled with falling edge detection
	LLWU_PE1_WUPE2_11  = 0x3  // External input pin enabled with any change detection
	LLWU_PE1_WUPE3_Pos = 0x6  // Position of WUPE3 field.
	LLWU_PE1_WUPE3_Msk = 0xc0 // Bit mask of WUPE3 field.
	LLWU_PE1_WUPE3_00  = 0x0  // External input pin disabled as wakeup input
	LLWU_PE1_WUPE3_01  = 0x1  // External input pin enabled with rising edge detection
	LLWU_PE1_WUPE3_10  = 0x2  // External input pin enabled with falling edge detection
	LLWU_PE1_WUPE3_11  = 0x3  // External input pin enabled with any change detection

	// PE2: LLWU Pin Enable 2 register
	LLWU_PE2_WUPE4_Pos = 0x0  // Position of WUPE4 field.
	LLWU_PE2_WUPE4_Msk = 0x3  // Bit mask of WUPE4 field.
	LLWU_PE2_WUPE4_00  = 0x0  // External input pin disabled as wakeup input
	LLWU_PE2_WUPE4_01  = 0x1  // External input pin enabled with rising edge detection
	LLWU_PE2_WUPE4_10  = 0x2  // External input pin enabled with falling edge detection
	LLWU_PE2_WUPE4_11  = 0x3  // External input pin enabled with any change detection
	LLWU_PE2_WUPE5_Pos = 0x2  // Position of WUPE5 field.
	LLWU_PE2_WUPE5_Msk = 0xc  // Bit mask of WUPE5 field.
	LLWU_PE2_WUPE5_00  = 0x0  // External input pin disabled as wakeup input
	LLWU_PE2_WUPE5_01  = 0x1  // External input pin enabled with rising edge detection
	LLWU_PE2_WUPE5_10  = 0x2  // External input pin enabled with falling edge detection
	LLWU_PE2_WUPE5_11  = 0x3  // External input pin enabled with any change detection
	LLWU_PE2_WUPE6_Pos = 0x4  // Position of WUPE6 field.
	LLWU_PE2_WUPE6_Msk = 0x30 // Bit mask of WUPE6 field.
	LLWU_PE2_WUPE6_00  = 0x0  // External input pin disabled as wakeup input
	LLWU_PE2_WUPE6_01  = 0x1  // External input pin enabled with rising edge detection
	LLWU_PE2_WUPE6_10  = 0x2  // External input pin enabled with falling edge detection
	LLWU_PE2_WUPE6_11  = 0x3  // External input pin enabled with any change detection
	LLWU_PE2_WUPE7_Pos = 0x6  // Position of WUPE7 field.
	LLWU_PE2_WUPE7_Msk = 0xc0 // Bit mask of WUPE7 field.
	LLWU_PE2_WUPE7_00  = 0x0  // External input pin disabled as wakeup input
	LLWU_PE2_WUPE7_01  = 0x1  // External input pin enabled with rising edge detection
	LLWU_PE2_WUPE7_10  = 0x2  // External input pin enabled with falling edge detection
	LLWU_PE2_WUPE7_11  = 0x3  // External input pin enabled with any change detection

	// PE3: LLWU Pin Enable 3 register
	LLWU_PE3_WUPE8_Pos  = 0x0  // Position of WUPE8 field.
	LLWU_PE3_WUPE8_Msk  = 0x3  // Bit mask of WUPE8 field.
	LLWU_PE3_WUPE8_00   = 0x0  // External input pin disabled as wakeup input
	LLWU_PE3_WUPE8_01   = 0x1  // External input pin enabled with rising edge detection
	LLWU_PE3_WUPE8_10   = 0x2  // External input pin enabled with falling edge detection
	LLWU_PE3_WUPE8_11   = 0x3  // External input pin enabled with any change detection
	LLWU_PE3_WUPE9_Pos  = 0x2  // Position of WUPE9 field.
	LLWU_PE3_WUPE9_Msk  = 0xc  // Bit mask of WUPE9 field.
	LLWU_PE3_WUPE9_00   = 0x0  // External input pin disabled as wakeup input
	LLWU_PE3_WUPE9_01   = 0x1  // External input pin enabled with rising edge detection
	LLWU_PE3_WUPE9_10   = 0x2  // External input pin enabled with falling edge detection
	LLWU_PE3_WUPE9_11   = 0x3  // External input pin enabled with any change detection
	LLWU_PE3_WUPE10_Pos = 0x4  // Position of WUPE10 field.
	LLWU_PE3_WUPE10_Msk = 0x30 // Bit mask of WUPE10 field.
	LLWU_PE3_WUPE10_00  = 0x0  // External input pin disabled as wakeup input
	LLWU_PE3_WUPE10_01  = 0x1  // External input pin enabled with rising edge detection
	LLWU_PE3_WUPE10_10  = 0x2  // External input pin enabled with falling edge detection
	LLWU_PE3_WUPE10_11  = 0x3  // External input pin enabled with any change detection
	LLWU_PE3_WUPE11_Pos = 0x6  // Position of WUPE11 field.
	LLWU_PE3_WUPE11_Msk = 0xc0 // Bit mask of WUPE11 field.
	LLWU_PE3_WUPE11_00  = 0x0  // External input pin disabled as wakeup input
	LLWU_PE3_WUPE11_01  = 0x1  // External input pin enabled with rising edge detection
	LLWU_PE3_WUPE11_10  = 0x2  // External input pin enabled with falling edge detection
	LLWU_PE3_WUPE11_11  = 0x3  // External input pin enabled with any change detection

	// PE4: LLWU Pin Enable 4 register
	LLWU_PE4_WUPE12_Pos = 0x0  // Position of WUPE12 field.
	LLWU_PE4_WUPE12_Msk = 0x3  // Bit mask of WUPE12 field.
	LLWU_PE4_WUPE12_00  = 0x0  // External input pin disabled as wakeup input
	LLWU_PE4_WUPE12_01  = 0x1  // External input pin enabled with rising edge detection
	LLWU_PE4_WUPE12_10  = 0x2  // External input pin enabled with falling edge detection
	LLWU_PE4_WUPE12_11  = 0x3  // External input pin enabled with any change detection
	LLWU_PE4_WUPE13_Pos = 0x2  // Position of WUPE13 field.
	LLWU_PE4_WUPE13_Msk = 0xc  // Bit mask of WUPE13 field.
	LLWU_PE4_WUPE13_00  = 0x0  // External input pin disabled as wakeup input
	LLWU_PE4_WUPE13_01  = 0x1  // External input pin enabled with rising edge detection
	LLWU_PE4_WUPE13_10  = 0x2  // External input pin enabled with falling edge detection
	LLWU_PE4_WUPE13_11  = 0x3  // External input pin enabled with any change detection
	LLWU_PE4_WUPE14_Pos = 0x4  // Position of WUPE14 field.
	LLWU_PE4_WUPE14_Msk = 0x30 // Bit mask of WUPE14 field.
	LLWU_PE4_WUPE14_00  = 0x0  // External input pin disabled as wakeup input
	LLWU_PE4_WUPE14_01  = 0x1  // External input pin enabled with rising edge detection
	LLWU_PE4_WUPE14_10  = 0x2  // External input pin enabled with falling edge detection
	LLWU_PE4_WUPE14_11  = 0x3  // External input pin enabled with any change detection
	LLWU_PE4_WUPE15_Pos = 0x6  // Position of WUPE15 field.
	LLWU_PE4_WUPE15_Msk = 0xc0 // Bit mask of WUPE15 field.
	LLWU_PE4_WUPE15_00  = 0x0  // External input pin disabled as wakeup input
	LLWU_PE4_WUPE15_01  = 0x1  // External input pin enabled with rising edge detection
	LLWU_PE4_WUPE15_10  = 0x2  // External input pin enabled with falling edge detection
	LLWU_PE4_WUPE15_11  = 0x3  // External input pin enabled with any change detection

	// ME: LLWU Module Enable register
	LLWU_ME_WUME0_Pos = 0x0  // Position of WUME0 field.
	LLWU_ME_WUME0_Msk = 0x1  // Bit mask of WUME0 field.
	LLWU_ME_WUME0     = 0x1  // Bit WUME0.
	LLWU_ME_WUME0_0   = 0x0  // Internal module flag not used as wakeup source
	LLWU_ME_WUME0_1   = 0x1  // Internal module flag used as wakeup source
	LLWU_ME_WUME1_Pos = 0x1  // Position of WUME1 field.
	LLWU_ME_WUME1_Msk = 0x2  // Bit mask of WUME1 field.
	LLWU_ME_WUME1     = 0x2  // Bit WUME1.
	LLWU_ME_WUME1_0   = 0x0  // Internal module flag not used as wakeup source
	LLWU_ME_WUME1_1   = 0x1  // Internal module flag used as wakeup source
	LLWU_ME_WUME2_Pos = 0x2  // Position of WUME2 field.
	LLWU_ME_WUME2_Msk = 0x4  // Bit mask of WUME2 field.
	LLWU_ME_WUME2     = 0x4  // Bit WUME2.
	LLWU_ME_WUME2_0   = 0x0  // Internal module flag not used as wakeup source
	LLWU_ME_WUME2_1   = 0x1  // Internal module flag used as wakeup source
	LLWU_ME_WUME3_Pos = 0x3  // Position of WUME3 field.
	LLWU_ME_WUME3_Msk = 0x8  // Bit mask of WUME3 field.
	LLWU_ME_WUME3     = 0x8  // Bit WUME3.
	LLWU_ME_WUME3_0   = 0x0  // Internal module flag not used as wakeup source
	LLWU_ME_WUME3_1   = 0x1  // Internal module flag used as wakeup source
	LLWU_ME_WUME4_Pos = 0x4  // Position of WUME4 field.
	LLWU_ME_WUME4_Msk = 0x10 // Bit mask of WUME4 field.
	LLWU_ME_WUME4     = 0x10 // Bit WUME4.
	LLWU_ME_WUME4_0   = 0x0  // Internal module flag not used as wakeup source
	LLWU_ME_WUME4_1   = 0x1  // Internal module flag used as wakeup source
	LLWU_ME_WUME5_Pos = 0x5  // Position of WUME5 field.
	LLWU_ME_WUME5_Msk = 0x20 // Bit mask of WUME5 field.
	LLWU_ME_WUME5     = 0x20 // Bit WUME5.
	LLWU_ME_WUME5_0   = 0x0  // Internal module flag not used as wakeup source
	LLWU_ME_WUME5_1   = 0x1  // Internal module flag used as wakeup source
	LLWU_ME_WUME6_Pos = 0x6  // Position of WUME6 field.
	LLWU_ME_WUME6_Msk = 0x40 // Bit mask of WUME6 field.
	LLWU_ME_WUME6     = 0x40 // Bit WUME6.
	LLWU_ME_WUME6_0   = 0x0  // Internal module flag not used as wakeup source
	LLWU_ME_WUME6_1   = 0x1  // Internal module flag used as wakeup source
	LLWU_ME_WUME7_Pos = 0x7  // Position of WUME7 field.
	LLWU_ME_WUME7_Msk = 0x80 // Bit mask of WUME7 field.
	LLWU_ME_WUME7     = 0x80 // Bit WUME7.
	LLWU_ME_WUME7_0   = 0x0  // Internal module flag not used as wakeup source
	LLWU_ME_WUME7_1   = 0x1  // Internal module flag used as wakeup source

	// F1: LLWU Flag 1 register
	LLWU_F1_WUF0_Pos = 0x0  // Position of WUF0 field.
	LLWU_F1_WUF0_Msk = 0x1  // Bit mask of WUF0 field.
	LLWU_F1_WUF0     = 0x1  // Bit WUF0.
	LLWU_F1_WUF0_0   = 0x0  // LLWU_P0 input was not a wakeup source
	LLWU_F1_WUF0_1   = 0x1  // LLWU_P0 input was a wakeup source
	LLWU_F1_WUF1_Pos = 0x1  // Position of WUF1 field.
	LLWU_F1_WUF1_Msk = 0x2  // Bit mask of WUF1 field.
	LLWU_F1_WUF1     = 0x2  // Bit WUF1.
	LLWU_F1_WUF1_0   = 0x0  // LLWU_P1 input was not a wakeup source
	LLWU_F1_WUF1_1   = 0x1  // LLWU_P1 input was a wakeup source
	LLWU_F1_WUF2_Pos = 0x2  // Position of WUF2 field.
	LLWU_F1_WUF2_Msk = 0x4  // Bit mask of WUF2 field.
	LLWU_F1_WUF2     = 0x4  // Bit WUF2.
	LLWU_F1_WUF2_0   = 0x0  // LLWU_P2 input was not a wakeup source
	LLWU_F1_WUF2_1   = 0x1  // LLWU_P2 input was a wakeup source
	LLWU_F1_WUF3_Pos = 0x3  // Position of WUF3 field.
	LLWU_F1_WUF3_Msk = 0x8  // Bit mask of WUF3 field.
	LLWU_F1_WUF3     = 0x8  // Bit WUF3.
	LLWU_F1_WUF3_0   = 0x0  // LLWU_P3 input was not a wake-up source
	LLWU_F1_WUF3_1   = 0x1  // LLWU_P3 input was a wake-up source
	LLWU_F1_WUF4_Pos = 0x4  // Position of WUF4 field.
	LLWU_F1_WUF4_Msk = 0x10 // Bit mask of WUF4 field.
	LLWU_F1_WUF4     = 0x10 // Bit WUF4.
	LLWU_F1_WUF4_0   = 0x0  // LLWU_P4 input was not a wakeup source
	LLWU_F1_WUF4_1   = 0x1  // LLWU_P4 input was a wakeup source
	LLWU_F1_WUF5_Pos = 0x5  // Position of WUF5 field.
	LLWU_F1_WUF5_Msk = 0x20 // Bit mask of WUF5 field.
	LLWU_F1_WUF5     = 0x20 // Bit WUF5.
	LLWU_F1_WUF5_0   = 0x0  // LLWU_P5 input was not a wakeup source
	LLWU_F1_WUF5_1   = 0x1  // LLWU_P5 input was a wakeup source
	LLWU_F1_WUF6_Pos = 0x6  // Position of WUF6 field.
	LLWU_F1_WUF6_Msk = 0x40 // Bit mask of WUF6 field.
	LLWU_F1_WUF6     = 0x40 // Bit WUF6.
	LLWU_F1_WUF6_0   = 0x0  // LLWU_P6 input was not a wakeup source
	LLWU_F1_WUF6_1   = 0x1  // LLWU_P6 input was a wakeup source
	LLWU_F1_WUF7_Pos = 0x7  // Position of WUF7 field.
	LLWU_F1_WUF7_Msk = 0x80 // Bit mask of WUF7 field.
	LLWU_F1_WUF7     = 0x80 // Bit WUF7.
	LLWU_F1_WUF7_0   = 0x0  // LLWU_P7 input was not a wakeup source
	LLWU_F1_WUF7_1   = 0x1  // LLWU_P7 input was a wakeup source

	// F2: LLWU Flag 2 register
	LLWU_F2_WUF8_Pos  = 0x0  // Position of WUF8 field.
	LLWU_F2_WUF8_Msk  = 0x1  // Bit mask of WUF8 field.
	LLWU_F2_WUF8      = 0x1  // Bit WUF8.
	LLWU_F2_WUF8_0    = 0x0  // LLWU_P8 input was not a wakeup source
	LLWU_F2_WUF8_1    = 0x1  // LLWU_P8 input was a wakeup source
	LLWU_F2_WUF9_Pos  = 0x1  // Position of WUF9 field.
	LLWU_F2_WUF9_Msk  = 0x2  // Bit mask of WUF9 field.
	LLWU_F2_WUF9      = 0x2  // Bit WUF9.
	LLWU_F2_WUF9_0    = 0x0  // LLWU_P9 input was not a wakeup source
	LLWU_F2_WUF9_1    = 0x1  // LLWU_P9 input was a wakeup source
	LLWU_F2_WUF10_Pos = 0x2  // Position of WUF10 field.
	LLWU_F2_WUF10_Msk = 0x4  // Bit mask of WUF10 field.
	LLWU_F2_WUF10     = 0x4  // Bit WUF10.
	LLWU_F2_WUF10_0   = 0x0  // LLWU_P10 input was not a wakeup source
	LLWU_F2_WUF10_1   = 0x1  // LLWU_P10 input was a wakeup source
	LLWU_F2_WUF11_Pos = 0x3  // Position of WUF11 field.
	LLWU_F2_WUF11_Msk = 0x8  // Bit mask of WUF11 field.
	LLWU_F2_WUF11     = 0x8  // Bit WUF11.
	LLWU_F2_WUF11_0   = 0x0  // LLWU_P11 input was not a wakeup source
	LLWU_F2_WUF11_1   = 0x1  // LLWU_P11 input was a wakeup source
	LLWU_F2_WUF12_Pos = 0x4  // Position of WUF12 field.
	LLWU_F2_WUF12_Msk = 0x10 // Bit mask of WUF12 field.
	LLWU_F2_WUF12     = 0x10 // Bit WUF12.
	LLWU_F2_WUF12_0   = 0x0  // LLWU_P12 input was not a wakeup source
	LLWU_F2_WUF12_1   = 0x1  // LLWU_P12 input was a wakeup source
	LLWU_F2_WUF13_Pos = 0x5  // Position of WUF13 field.
	LLWU_F2_WUF13_Msk = 0x20 // Bit mask of WUF13 field.
	LLWU_F2_WUF13     = 0x20 // Bit WUF13.
	LLWU_F2_WUF13_0   = 0x0  // LLWU_P13 input was not a wakeup source
	LLWU_F2_WUF13_1   = 0x1  // LLWU_P13 input was a wakeup source
	LLWU_F2_WUF14_Pos = 0x6  // Position of WUF14 field.
	LLWU_F2_WUF14_Msk = 0x40 // Bit mask of WUF14 field.
	LLWU_F2_WUF14     = 0x40 // Bit WUF14.
	LLWU_F2_WUF14_0   = 0x0  // LLWU_P14 input was not a wakeup source
	LLWU_F2_WUF14_1   = 0x1  // LLWU_P14 input was a wakeup source
	LLWU_F2_WUF15_Pos = 0x7  // Position of WUF15 field.
	LLWU_F2_WUF15_Msk = 0x80 // Bit mask of WUF15 field.
	LLWU_F2_WUF15     = 0x80 // Bit WUF15.
	LLWU_F2_WUF15_0   = 0x0  // LLWU_P15 input was not a wakeup source
	LLWU_F2_WUF15_1   = 0x1  // LLWU_P15 input was a wakeup source

	// F3: LLWU Flag 3 register
	LLWU_F3_MWUF0_Pos = 0x0  // Position of MWUF0 field.
	LLWU_F3_MWUF0_Msk = 0x1  // Bit mask of MWUF0 field.
	LLWU_F3_MWUF0     = 0x1  // Bit MWUF0.
	LLWU_F3_MWUF0_0   = 0x0  // Module 0 input was not a wakeup source
	LLWU_F3_MWUF0_1   = 0x1  // Module 0 input was a wakeup source
	LLWU_F3_MWUF1_Pos = 0x1  // Position of MWUF1 field.
	LLWU_F3_MWUF1_Msk = 0x2  // Bit mask of MWUF1 field.
	LLWU_F3_MWUF1     = 0x2  // Bit MWUF1.
	LLWU_F3_MWUF1_0   = 0x0  // Module 1 input was not a wakeup source
	LLWU_F3_MWUF1_1   = 0x1  // Module 1 input was a wakeup source
	LLWU_F3_MWUF2_Pos = 0x2  // Position of MWUF2 field.
	LLWU_F3_MWUF2_Msk = 0x4  // Bit mask of MWUF2 field.
	LLWU_F3_MWUF2     = 0x4  // Bit MWUF2.
	LLWU_F3_MWUF2_0   = 0x0  // Module 2 input was not a wakeup source
	LLWU_F3_MWUF2_1   = 0x1  // Module 2 input was a wakeup source
	LLWU_F3_MWUF3_Pos = 0x3  // Position of MWUF3 field.
	LLWU_F3_MWUF3_Msk = 0x8  // Bit mask of MWUF3 field.
	LLWU_F3_MWUF3     = 0x8  // Bit MWUF3.
	LLWU_F3_MWUF3_0   = 0x0  // Module 3 input was not a wakeup source
	LLWU_F3_MWUF3_1   = 0x1  // Module 3 input was a wakeup source
	LLWU_F3_MWUF4_Pos = 0x4  // Position of MWUF4 field.
	LLWU_F3_MWUF4_Msk = 0x10 // Bit mask of MWUF4 field.
	LLWU_F3_MWUF4     = 0x10 // Bit MWUF4.
	LLWU_F3_MWUF4_0   = 0x0  // Module 4 input was not a wakeup source
	LLWU_F3_MWUF4_1   = 0x1  // Module 4 input was a wakeup source
	LLWU_F3_MWUF5_Pos = 0x5  // Position of MWUF5 field.
	LLWU_F3_MWUF5_Msk = 0x20 // Bit mask of MWUF5 field.
	LLWU_F3_MWUF5     = 0x20 // Bit MWUF5.
	LLWU_F3_MWUF5_0   = 0x0  // Module 5 input was not a wakeup source
	LLWU_F3_MWUF5_1   = 0x1  // Module 5 input was a wakeup source
	LLWU_F3_MWUF6_Pos = 0x6  // Position of MWUF6 field.
	LLWU_F3_MWUF6_Msk = 0x40 // Bit mask of MWUF6 field.
	LLWU_F3_MWUF6     = 0x40 // Bit MWUF6.
	LLWU_F3_MWUF6_0   = 0x0  // Module 6 input was not a wakeup source
	LLWU_F3_MWUF6_1   = 0x1  // Module 6 input was a wakeup source
	LLWU_F3_MWUF7_Pos = 0x7  // Position of MWUF7 field.
	LLWU_F3_MWUF7_Msk = 0x80 // Bit mask of MWUF7 field.
	LLWU_F3_MWUF7     = 0x80 // Bit MWUF7.
	LLWU_F3_MWUF7_0   = 0x0  // Module 7 input was not a wakeup source
	LLWU_F3_MWUF7_1   = 0x1  // Module 7 input was a wakeup source

	// FILT1: LLWU Pin Filter 1 register
	LLWU_FILT1_FILTSEL_Pos  = 0x0  // Position of FILTSEL field.
	LLWU_FILT1_FILTSEL_Msk  = 0xf  // Bit mask of FILTSEL field.
	LLWU_FILT1_FILTSEL_0000 = 0x0  // Select LLWU_P0 for filter
	LLWU_FILT1_FILTSEL_1111 = 0xf  // Select LLWU_P15 for filter
	LLWU_FILT1_FILTE_Pos    = 0x5  // Position of FILTE field.
	LLWU_FILT1_FILTE_Msk    = 0x60 // Bit mask of FILTE field.
	LLWU_FILT1_FILTE_00     = 0x0  // Filter disabled
	LLWU_FILT1_FILTE_01     = 0x1  // Filter posedge detect enabled
	LLWU_FILT1_FILTE_10     = 0x2  // Filter negedge detect enabled
	LLWU_FILT1_FILTE_11     = 0x3  // Filter any edge detect enabled
	LLWU_FILT1_FILTF_Pos    = 0x7  // Position of FILTF field.
	LLWU_FILT1_FILTF_Msk    = 0x80 // Bit mask of FILTF field.
	LLWU_FILT1_FILTF        = 0x80 // Bit FILTF.
	LLWU_FILT1_FILTF_0      = 0x0  // Pin Filter 1 was not a wakeup source
	LLWU_FILT1_FILTF_1      = 0x1  // Pin Filter 1 was a wakeup source

	// FILT2: LLWU Pin Filter 2 register
	LLWU_FILT2_FILTSEL_Pos  = 0x0  // Position of FILTSEL field.
	LLWU_FILT2_FILTSEL_Msk  = 0xf  // Bit mask of FILTSEL field.
	LLWU_FILT2_FILTSEL_0000 = 0x0  // Select LLWU_P0 for filter
	LLWU_FILT2_FILTSEL_1111 = 0xf  // Select LLWU_P15 for filter
	LLWU_FILT2_FILTE_Pos    = 0x5  // Position of FILTE field.
	LLWU_FILT2_FILTE_Msk    = 0x60 // Bit mask of FILTE field.
	LLWU_FILT2_FILTE_00     = 0x0  // Filter disabled
	LLWU_FILT2_FILTE_01     = 0x1  // Filter posedge detect enabled
	LLWU_FILT2_FILTE_10     = 0x2  // Filter negedge detect enabled
	LLWU_FILT2_FILTE_11     = 0x3  // Filter any edge detect enabled
	LLWU_FILT2_FILTF_Pos    = 0x7  // Position of FILTF field.
	LLWU_FILT2_FILTF_Msk    = 0x80 // Bit mask of FILTF field.
	LLWU_FILT2_FILTF        = 0x80 // Bit FILTF.
	LLWU_FILT2_FILTF_0      = 0x0  // Pin Filter 2 was not a wakeup source
	LLWU_FILT2_FILTF_1      = 0x1  // Pin Filter 2 was a wakeup source
)

// Bitfields for PMC: Power Management Controller
const (
	// LVDSC1: Low Voltage Detect Status And Control 1 register
	PMC_LVDSC1_LVDV_Pos   = 0x0  // Position of LVDV field.
	PMC_LVDSC1_LVDV_Msk   = 0x3  // Bit mask of LVDV field.
	PMC_LVDSC1_LVDV_00    = 0x0  // Low trip point selected (V LVD = V LVDL )
	PMC_LVDSC1_LVDV_01    = 0x1  // High trip point selected (V LVD = V LVDH )
	PMC_LVDSC1_LVDRE_Pos  = 0x4  // Position of LVDRE field.
	PMC_LVDSC1_LVDRE_Msk  = 0x10 // Bit mask of LVDRE field.
	PMC_LVDSC1_LVDRE      = 0x10 // Bit LVDRE.
	PMC_LVDSC1_LVDRE_0    = 0x0  // LVDF does not generate hardware resets
	PMC_LVDSC1_LVDRE_1    = 0x1  // Force an MCU reset when LVDF = 1
	PMC_LVDSC1_LVDIE_Pos  = 0x5  // Position of LVDIE field.
	PMC_LVDSC1_LVDIE_Msk  = 0x20 // Bit mask of LVDIE field.
	PMC_LVDSC1_LVDIE      = 0x20 // Bit LVDIE.
	PMC_LVDSC1_LVDIE_0    = 0x0  // Hardware interrupt disabled (use polling)
	PMC_LVDSC1_LVDIE_1    = 0x1  // Request a hardware interrupt when LVDF = 1
	PMC_LVDSC1_LVDACK_Pos = 0x6  // Position of LVDACK field.
	PMC_LVDSC1_LVDACK_Msk = 0x40 // Bit mask of LVDACK field.
	PMC_LVDSC1_LVDACK     = 0x40 // Bit LVDACK.
	PMC_LVDSC1_LVDF_Pos   = 0x7  // Position of LVDF field.
	PMC_LVDSC1_LVDF_Msk   = 0x80 // Bit mask of LVDF field.
	PMC_LVDSC1_LVDF       = 0x80 // Bit LVDF.
	PMC_LVDSC1_LVDF_0     = 0x0  // Low-voltage event not detected
	PMC_LVDSC1_LVDF_1     = 0x1  // Low-voltage event detected

	// LVDSC2: Low Voltage Detect Status And Control 2 register
	PMC_LVDSC2_LVWV_Pos   = 0x0  // Position of LVWV field.
	PMC_LVDSC2_LVWV_Msk   = 0x3  // Bit mask of LVWV field.
	PMC_LVDSC2_LVWV_00    = 0x0  // Low trip point selected (VLVW = VLVW1)
	PMC_LVDSC2_LVWV_01    = 0x1  // Mid 1 trip point selected (VLVW = VLVW2)
	PMC_LVDSC2_LVWV_10    = 0x2  // Mid 2 trip point selected (VLVW = VLVW3)
	PMC_LVDSC2_LVWV_11    = 0x3  // High trip point selected (VLVW = VLVW4)
	PMC_LVDSC2_LVWIE_Pos  = 0x5  // Position of LVWIE field.
	PMC_LVDSC2_LVWIE_Msk  = 0x20 // Bit mask of LVWIE field.
	PMC_LVDSC2_LVWIE      = 0x20 // Bit LVWIE.
	PMC_LVDSC2_LVWIE_0    = 0x0  // Hardware interrupt disabled (use polling)
	PMC_LVDSC2_LVWIE_1    = 0x1  // Request a hardware interrupt when LVWF = 1
	PMC_LVDSC2_LVWACK_Pos = 0x6  // Position of LVWACK field.
	PMC_LVDSC2_LVWACK_Msk = 0x40 // Bit mask of LVWACK field.
	PMC_LVDSC2_LVWACK     = 0x40 // Bit LVWACK.
	PMC_LVDSC2_LVWF_Pos   = 0x7  // Position of LVWF field.
	PMC_LVDSC2_LVWF_Msk   = 0x80 // Bit mask of LVWF field.
	PMC_LVDSC2_LVWF       = 0x80 // Bit LVWF.
	PMC_LVDSC2_LVWF_0     = 0x0  // Low-voltage warning event not detected
	PMC_LVDSC2_LVWF_1     = 0x1  // Low-voltage warning event detected

	// REGSC: Regulator Status And Control register
	PMC_REGSC_BGBE_Pos   = 0x0  // Position of BGBE field.
	PMC_REGSC_BGBE_Msk   = 0x1  // Bit mask of BGBE field.
	PMC_REGSC_BGBE       = 0x1  // Bit BGBE.
	PMC_REGSC_BGBE_0     = 0x0  // Bandgap buffer not enabled
	PMC_REGSC_BGBE_1     = 0x1  // Bandgap buffer enabled
	PMC_REGSC_REGONS_Pos = 0x2  // Position of REGONS field.
	PMC_REGSC_REGONS_Msk = 0x4  // Bit mask of REGONS field.
	PMC_REGSC_REGONS     = 0x4  // Bit REGONS.
	PMC_REGSC_REGONS_0   = 0x0  // Regulator is in stop regulation or in transition to/from it
	PMC_REGSC_REGONS_1   = 0x1  // Regulator is in run regulation
	PMC_REGSC_ACKISO_Pos = 0x3  // Position of ACKISO field.
	PMC_REGSC_ACKISO_Msk = 0x8  // Bit mask of ACKISO field.
	PMC_REGSC_ACKISO     = 0x8  // Bit ACKISO.
	PMC_REGSC_ACKISO_0   = 0x0  // Peripherals and I/O pads are in normal run state.
	PMC_REGSC_ACKISO_1   = 0x1  // Certain peripherals and I/O pads are in an isolated and latched state.
	PMC_REGSC_BGEN_Pos   = 0x4  // Position of BGEN field.
	PMC_REGSC_BGEN_Msk   = 0x10 // Bit mask of BGEN field.
	PMC_REGSC_BGEN       = 0x10 // Bit BGEN.
	PMC_REGSC_BGEN_0     = 0x0  // Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes.
	PMC_REGSC_BGEN_1     = 0x1  // Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes.
)

// Bitfields for SMC: System Mode Controller
const (
	// PMPROT: Power Mode Protection register
	SMC_PMPROT_AVLLS_Pos  = 0x1  // Position of AVLLS field.
	SMC_PMPROT_AVLLS_Msk  = 0x2  // Bit mask of AVLLS field.
	SMC_PMPROT_AVLLS      = 0x2  // Bit AVLLS.
	SMC_PMPROT_AVLLS_0    = 0x0  // Any VLLSx mode is not allowed
	SMC_PMPROT_AVLLS_1    = 0x1  // Any VLLSx mode is allowed
	SMC_PMPROT_ALLS_Pos   = 0x3  // Position of ALLS field.
	SMC_PMPROT_ALLS_Msk   = 0x8  // Bit mask of ALLS field.
	SMC_PMPROT_ALLS       = 0x8  // Bit ALLS.
	SMC_PMPROT_ALLS_0     = 0x0  // Any LLSx mode is not allowed
	SMC_PMPROT_ALLS_1     = 0x1  // Any LLSx mode is allowed
	SMC_PMPROT_AVLP_Pos   = 0x5  // Position of AVLP field.
	SMC_PMPROT_AVLP_Msk   = 0x20 // Bit mask of AVLP field.
	SMC_PMPROT_AVLP       = 0x20 // Bit AVLP.
	SMC_PMPROT_AVLP_0     = 0x0  // VLPR, VLPW, and VLPS are not allowed.
	SMC_PMPROT_AVLP_1     = 0x1  // VLPR, VLPW, and VLPS are allowed.
	SMC_PMPROT_AHSRUN_Pos = 0x7  // Position of AHSRUN field.
	SMC_PMPROT_AHSRUN_Msk = 0x80 // Bit mask of AHSRUN field.
	SMC_PMPROT_AHSRUN     = 0x80 // Bit AHSRUN.
	SMC_PMPROT_AHSRUN_0   = 0x0  // HSRUN is not allowed
	SMC_PMPROT_AHSRUN_1   = 0x1  // HSRUN is allowed

	// PMCTRL: Power Mode Control register
	SMC_PMCTRL_STOPM_Pos = 0x0  // Position of STOPM field.
	SMC_PMCTRL_STOPM_Msk = 0x7  // Bit mask of STOPM field.
	SMC_PMCTRL_STOPM_000 = 0x0  // Normal Stop (STOP)
	SMC_PMCTRL_STOPM_010 = 0x2  // Very-Low-Power Stop (VLPS)
	SMC_PMCTRL_STOPM_011 = 0x3  // Low-Leakage Stop (LLSx)
	SMC_PMCTRL_STOPM_100 = 0x4  // Very-Low-Leakage Stop (VLLSx)
	SMC_PMCTRL_STOPM_110 = 0x6  // Reseved
	SMC_PMCTRL_STOPA_Pos = 0x3  // Position of STOPA field.
	SMC_PMCTRL_STOPA_Msk = 0x8  // Bit mask of STOPA field.
	SMC_PMCTRL_STOPA     = 0x8  // Bit STOPA.
	SMC_PMCTRL_STOPA_0   = 0x0  // The previous stop mode entry was successsful.
	SMC_PMCTRL_STOPA_1   = 0x1  // The previous stop mode entry was aborted.
	SMC_PMCTRL_RUNM_Pos  = 0x5  // Position of RUNM field.
	SMC_PMCTRL_RUNM_Msk  = 0x60 // Bit mask of RUNM field.
	SMC_PMCTRL_RUNM_00   = 0x0  // Normal Run mode (RUN)
	SMC_PMCTRL_RUNM_10   = 0x2  // Very-Low-Power Run mode (VLPR)
	SMC_PMCTRL_RUNM_11   = 0x3  // High Speed Run mode (HSRUN)

	// STOPCTRL: Stop Control Register
	SMC_STOPCTRL_LLSM_Pos   = 0x0  // Position of LLSM field.
	SMC_STOPCTRL_LLSM_Msk   = 0x7  // Bit mask of LLSM field.
	SMC_STOPCTRL_LLSM_000   = 0x0  // VLLS0if PMCTRL[STOPM]=VLLSx, Reserved if PMCTRL[STOPM]=LLSx
	SMC_STOPCTRL_LLSM_001   = 0x1  // VLLS1if PMCTRL[STOPM]=VLLSx, Reserved if PMCTRL[STOPM]=LLSx
	SMC_STOPCTRL_LLSM_010   = 0x2  // VLLS2if PMCTRL[STOPM]=VLLSx, LLS2 if PMCTRL[STOPM]=LLSx
	SMC_STOPCTRL_LLSM_011   = 0x3  // VLLS3if PMCTRL[STOPM]=VLLSx, LLS3 if PMCTRL[STOPM]=LLSx
	SMC_STOPCTRL_PORPO_Pos  = 0x5  // Position of PORPO field.
	SMC_STOPCTRL_PORPO_Msk  = 0x20 // Bit mask of PORPO field.
	SMC_STOPCTRL_PORPO      = 0x20 // Bit PORPO.
	SMC_STOPCTRL_PORPO_0    = 0x0  // POR detect circuit is enabled in VLLS0
	SMC_STOPCTRL_PORPO_1    = 0x1  // POR detect circuit is disabled in VLLS0
	SMC_STOPCTRL_PSTOPO_Pos = 0x6  // Position of PSTOPO field.
	SMC_STOPCTRL_PSTOPO_Msk = 0xc0 // Bit mask of PSTOPO field.
	SMC_STOPCTRL_PSTOPO_00  = 0x0  // STOP - Normal Stop mode
	SMC_STOPCTRL_PSTOPO_01  = 0x1  // PSTOP1 - Partial Stop with both system and bus clocks disabled
	SMC_STOPCTRL_PSTOPO_10  = 0x2  // PSTOP2 - Partial Stop with system clock disabled and bus clock enabled

	// PMSTAT: Power Mode Status register
	SMC_PMSTAT_PMSTAT_Pos = 0x0  // Position of PMSTAT field.
	SMC_PMSTAT_PMSTAT_Msk = 0xff // Bit mask of PMSTAT field.
)

// Bitfields for RCM: Reset Control Module
const (
	// SRS0: System Reset Status Register 0
	RCM_SRS0_WAKEUP_Pos = 0x0  // Position of WAKEUP field.
	RCM_SRS0_WAKEUP_Msk = 0x1  // Bit mask of WAKEUP field.
	RCM_SRS0_WAKEUP     = 0x1  // Bit WAKEUP.
	RCM_SRS0_WAKEUP_0   = 0x0  // Reset not caused by LLWU module wakeup source
	RCM_SRS0_WAKEUP_1   = 0x1  // Reset caused by LLWU module wakeup source
	RCM_SRS0_LVD_Pos    = 0x1  // Position of LVD field.
	RCM_SRS0_LVD_Msk    = 0x2  // Bit mask of LVD field.
	RCM_SRS0_LVD        = 0x2  // Bit LVD.
	RCM_SRS0_LVD_0      = 0x0  // Reset not caused by LVD trip or POR
	RCM_SRS0_LVD_1      = 0x1  // Reset caused by LVD trip or POR
	RCM_SRS0_LOC_Pos    = 0x2  // Position of LOC field.
	RCM_SRS0_LOC_Msk    = 0x4  // Bit mask of LOC field.
	RCM_SRS0_LOC        = 0x4  // Bit LOC.
	RCM_SRS0_LOC_0      = 0x0  // Reset not caused by a loss of external clock.
	RCM_SRS0_LOC_1      = 0x1  // Reset caused by a loss of external clock.
	RCM_SRS0_LOL_Pos    = 0x3  // Position of LOL field.
	RCM_SRS0_LOL_Msk    = 0x8  // Bit mask of LOL field.
	RCM_SRS0_LOL        = 0x8  // Bit LOL.
	RCM_SRS0_LOL_0      = 0x0  // Reset not caused by a loss of lock in the PLL
	RCM_SRS0_LOL_1      = 0x1  // Reset caused by a loss of lock in the PLL
	RCM_SRS0_WDOG_Pos   = 0x5  // Position of WDOG field.
	RCM_SRS0_WDOG_Msk   = 0x20 // Bit mask of WDOG field.
	RCM_SRS0_WDOG       = 0x20 // Bit WDOG.
	RCM_SRS0_WDOG_0     = 0x0  // Reset not caused by watchdog timeout
	RCM_SRS0_WDOG_1     = 0x1  // Reset caused by watchdog timeout
	RCM_SRS0_PIN_Pos    = 0x6  // Position of PIN field.
	RCM_SRS0_PIN_Msk    = 0x40 // Bit mask of PIN field.
	RCM_SRS0_PIN        = 0x40 // Bit PIN.
	RCM_SRS0_PIN_0      = 0x0  // Reset not caused by external reset pin
	RCM_SRS0_PIN_1      = 0x1  // Reset caused by external reset pin
	RCM_SRS0_POR_Pos    = 0x7  // Position of POR field.
	RCM_SRS0_POR_Msk    = 0x80 // Bit mask of POR field.
	RCM_SRS0_POR        = 0x80 // Bit POR.
	RCM_SRS0_POR_0      = 0x0  // Reset not caused by POR
	RCM_SRS0_POR_1      = 0x1  // Reset caused by POR

	// SRS1: System Reset Status Register 1
	RCM_SRS1_JTAG_Pos    = 0x0  // Position of JTAG field.
	RCM_SRS1_JTAG_Msk    = 0x1  // Bit mask of JTAG field.
	RCM_SRS1_JTAG        = 0x1  // Bit JTAG.
	RCM_SRS1_JTAG_0      = 0x0  // Reset not caused by JTAG
	RCM_SRS1_JTAG_1      = 0x1  // Reset caused by JTAG
	RCM_SRS1_LOCKUP_Pos  = 0x1  // Position of LOCKUP field.
	RCM_SRS1_LOCKUP_Msk  = 0x2  // Bit mask of LOCKUP field.
	RCM_SRS1_LOCKUP      = 0x2  // Bit LOCKUP.
	RCM_SRS1_LOCKUP_0    = 0x0  // Reset not caused by core LOCKUP event
	RCM_SRS1_LOCKUP_1    = 0x1  // Reset caused by core LOCKUP event
	RCM_SRS1_SW_Pos      = 0x2  // Position of SW field.
	RCM_SRS1_SW_Msk      = 0x4  // Bit mask of SW field.
	RCM_SRS1_SW          = 0x4  // Bit SW.
	RCM_SRS1_SW_0        = 0x0  // Reset not caused by software setting of SYSRESETREQ bit
	RCM_SRS1_SW_1        = 0x1  // Reset caused by software setting of SYSRESETREQ bit
	RCM_SRS1_MDM_AP_Pos  = 0x3  // Position of MDM_AP field.
	RCM_SRS1_MDM_AP_Msk  = 0x8  // Bit mask of MDM_AP field.
	RCM_SRS1_MDM_AP      = 0x8  // Bit MDM_AP.
	RCM_SRS1_MDM_AP_0    = 0x0  // Reset not caused by host debugger system setting of the System Reset Request bit
	RCM_SRS1_MDM_AP_1    = 0x1  // Reset caused by host debugger system setting of the System Reset Request bit
	RCM_SRS1_EZPT_Pos    = 0x4  // Position of EZPT field.
	RCM_SRS1_EZPT_Msk    = 0x10 // Bit mask of EZPT field.
	RCM_SRS1_EZPT        = 0x10 // Bit EZPT.
	RCM_SRS1_EZPT_0      = 0x0  // Reset not caused by EzPort receiving the RESET command while the device is in EzPort mode
	RCM_SRS1_EZPT_1      = 0x1  // Reset caused by EzPort receiving the RESET command while the device is in EzPort mode
	RCM_SRS1_SACKERR_Pos = 0x5  // Position of SACKERR field.
	RCM_SRS1_SACKERR_Msk = 0x20 // Bit mask of SACKERR field.
	RCM_SRS1_SACKERR     = 0x20 // Bit SACKERR.
	RCM_SRS1_SACKERR_0   = 0x0  // Reset not caused by peripheral failure to acknowledge attempt to enter stop mode
	RCM_SRS1_SACKERR_1   = 0x1  // Reset caused by peripheral failure to acknowledge attempt to enter stop mode

	// RPFC: Reset Pin Filter Control register
	RCM_RPFC_RSTFLTSRW_Pos = 0x0 // Position of RSTFLTSRW field.
	RCM_RPFC_RSTFLTSRW_Msk = 0x3 // Bit mask of RSTFLTSRW field.
	RCM_RPFC_RSTFLTSRW_00  = 0x0 // All filtering disabled
	RCM_RPFC_RSTFLTSRW_01  = 0x1 // Bus clock filter enabled for normal operation
	RCM_RPFC_RSTFLTSRW_10  = 0x2 // LPO clock filter enabled for normal operation
	RCM_RPFC_RSTFLTSS_Pos  = 0x2 // Position of RSTFLTSS field.
	RCM_RPFC_RSTFLTSS_Msk  = 0x4 // Bit mask of RSTFLTSS field.
	RCM_RPFC_RSTFLTSS      = 0x4 // Bit RSTFLTSS.
	RCM_RPFC_RSTFLTSS_0    = 0x0 // All filtering disabled
	RCM_RPFC_RSTFLTSS_1    = 0x1 // LPO clock filter enabled

	// RPFW: Reset Pin Filter Width register
	RCM_RPFW_RSTFLTSEL_Pos   = 0x0  // Position of RSTFLTSEL field.
	RCM_RPFW_RSTFLTSEL_Msk   = 0x1f // Bit mask of RSTFLTSEL field.
	RCM_RPFW_RSTFLTSEL_00000 = 0x0  // Bus clock filter count is 1
	RCM_RPFW_RSTFLTSEL_00001 = 0x1  // Bus clock filter count is 2
	RCM_RPFW_RSTFLTSEL_00010 = 0x2  // Bus clock filter count is 3
	RCM_RPFW_RSTFLTSEL_00011 = 0x3  // Bus clock filter count is 4
	RCM_RPFW_RSTFLTSEL_00100 = 0x4  // Bus clock filter count is 5
	RCM_RPFW_RSTFLTSEL_00101 = 0x5  // Bus clock filter count is 6
	RCM_RPFW_RSTFLTSEL_00110 = 0x6  // Bus clock filter count is 7
	RCM_RPFW_RSTFLTSEL_00111 = 0x7  // Bus clock filter count is 8
	RCM_RPFW_RSTFLTSEL_01000 = 0x8  // Bus clock filter count is 9
	RCM_RPFW_RSTFLTSEL_01001 = 0x9  // Bus clock filter count is 10
	RCM_RPFW_RSTFLTSEL_01010 = 0xa  // Bus clock filter count is 11
	RCM_RPFW_RSTFLTSEL_01011 = 0xb  // Bus clock filter count is 12
	RCM_RPFW_RSTFLTSEL_01100 = 0xc  // Bus clock filter count is 13
	RCM_RPFW_RSTFLTSEL_01101 = 0xd  // Bus clock filter count is 14
	RCM_RPFW_RSTFLTSEL_01110 = 0xe  // Bus clock filter count is 15
	RCM_RPFW_RSTFLTSEL_01111 = 0xf  // Bus clock filter count is 16
	RCM_RPFW_RSTFLTSEL_10000 = 0x10 // Bus clock filter count is 17
	RCM_RPFW_RSTFLTSEL_10001 = 0x11 // Bus clock filter count is 18
	RCM_RPFW_RSTFLTSEL_10010 = 0x12 // Bus clock filter count is 19
	RCM_RPFW_RSTFLTSEL_10011 = 0x13 // Bus clock filter count is 20
	RCM_RPFW_RSTFLTSEL_10100 = 0x14 // Bus clock filter count is 21
	RCM_RPFW_RSTFLTSEL_10101 = 0x15 // Bus clock filter count is 22
	RCM_RPFW_RSTFLTSEL_10110 = 0x16 // Bus clock filter count is 23
	RCM_RPFW_RSTFLTSEL_10111 = 0x17 // Bus clock filter count is 24
	RCM_RPFW_RSTFLTSEL_11000 = 0x18 // Bus clock filter count is 25
	RCM_RPFW_RSTFLTSEL_11001 = 0x19 // Bus clock filter count is 26
	RCM_RPFW_RSTFLTSEL_11010 = 0x1a // Bus clock filter count is 27
	RCM_RPFW_RSTFLTSEL_11011 = 0x1b // Bus clock filter count is 28
	RCM_RPFW_RSTFLTSEL_11100 = 0x1c // Bus clock filter count is 29
	RCM_RPFW_RSTFLTSEL_11101 = 0x1d // Bus clock filter count is 30
	RCM_RPFW_RSTFLTSEL_11110 = 0x1e // Bus clock filter count is 31
	RCM_RPFW_RSTFLTSEL_11111 = 0x1f // Bus clock filter count is 32

	// MR: Mode Register
	RCM_MR_EZP_MS_Pos = 0x1 // Position of EZP_MS field.
	RCM_MR_EZP_MS_Msk = 0x2 // Bit mask of EZP_MS field.
	RCM_MR_EZP_MS     = 0x2 // Bit EZP_MS.
	RCM_MR_EZP_MS_0   = 0x0 // Pin deasserted (logic 1)
	RCM_MR_EZP_MS_1   = 0x1 // Pin asserted (logic 0)

	// SSRS0: Sticky System Reset Status Register 0
	RCM_SSRS0_SWAKEUP_Pos = 0x0  // Position of SWAKEUP field.
	RCM_SSRS0_SWAKEUP_Msk = 0x1  // Bit mask of SWAKEUP field.
	RCM_SSRS0_SWAKEUP     = 0x1  // Bit SWAKEUP.
	RCM_SSRS0_SWAKEUP_0   = 0x0  // Reset not caused by LLWU module wakeup source
	RCM_SSRS0_SWAKEUP_1   = 0x1  // Reset caused by LLWU module wakeup source
	RCM_SSRS0_SLVD_Pos    = 0x1  // Position of SLVD field.
	RCM_SSRS0_SLVD_Msk    = 0x2  // Bit mask of SLVD field.
	RCM_SSRS0_SLVD        = 0x2  // Bit SLVD.
	RCM_SSRS0_SLVD_0      = 0x0  // Reset not caused by LVD trip or POR
	RCM_SSRS0_SLVD_1      = 0x1  // Reset caused by LVD trip or POR
	RCM_SSRS0_SLOC_Pos    = 0x2  // Position of SLOC field.
	RCM_SSRS0_SLOC_Msk    = 0x4  // Bit mask of SLOC field.
	RCM_SSRS0_SLOC        = 0x4  // Bit SLOC.
	RCM_SSRS0_SLOC_0      = 0x0  // Reset not caused by a loss of external clock.
	RCM_SSRS0_SLOC_1      = 0x1  // Reset caused by a loss of external clock.
	RCM_SSRS0_SLOL_Pos    = 0x3  // Position of SLOL field.
	RCM_SSRS0_SLOL_Msk    = 0x8  // Bit mask of SLOL field.
	RCM_SSRS0_SLOL        = 0x8  // Bit SLOL.
	RCM_SSRS0_SLOL_0      = 0x0  // Reset not caused by a loss of lock in the PLL
	RCM_SSRS0_SLOL_1      = 0x1  // Reset caused by a loss of lock in the PLL
	RCM_SSRS0_SWDOG_Pos   = 0x5  // Position of SWDOG field.
	RCM_SSRS0_SWDOG_Msk   = 0x20 // Bit mask of SWDOG field.
	RCM_SSRS0_SWDOG       = 0x20 // Bit SWDOG.
	RCM_SSRS0_SWDOG_0     = 0x0  // Reset not caused by watchdog timeout
	RCM_SSRS0_SWDOG_1     = 0x1  // Reset caused by watchdog timeout
	RCM_SSRS0_SPIN_Pos    = 0x6  // Position of SPIN field.
	RCM_SSRS0_SPIN_Msk    = 0x40 // Bit mask of SPIN field.
	RCM_SSRS0_SPIN        = 0x40 // Bit SPIN.
	RCM_SSRS0_SPIN_0      = 0x0  // Reset not caused by external reset pin
	RCM_SSRS0_SPIN_1      = 0x1  // Reset caused by external reset pin
	RCM_SSRS0_SPOR_Pos    = 0x7  // Position of SPOR field.
	RCM_SSRS0_SPOR_Msk    = 0x80 // Bit mask of SPOR field.
	RCM_SSRS0_SPOR        = 0x80 // Bit SPOR.
	RCM_SSRS0_SPOR_0      = 0x0  // Reset not caused by POR
	RCM_SSRS0_SPOR_1      = 0x1  // Reset caused by POR

	// SSRS1: Sticky System Reset Status Register 1
	RCM_SSRS1_SJTAG_Pos    = 0x0  // Position of SJTAG field.
	RCM_SSRS1_SJTAG_Msk    = 0x1  // Bit mask of SJTAG field.
	RCM_SSRS1_SJTAG        = 0x1  // Bit SJTAG.
	RCM_SSRS1_SJTAG_0      = 0x0  // Reset not caused by JTAG
	RCM_SSRS1_SJTAG_1      = 0x1  // Reset caused by JTAG
	RCM_SSRS1_SLOCKUP_Pos  = 0x1  // Position of SLOCKUP field.
	RCM_SSRS1_SLOCKUP_Msk  = 0x2  // Bit mask of SLOCKUP field.
	RCM_SSRS1_SLOCKUP      = 0x2  // Bit SLOCKUP.
	RCM_SSRS1_SLOCKUP_0    = 0x0  // Reset not caused by core LOCKUP event
	RCM_SSRS1_SLOCKUP_1    = 0x1  // Reset caused by core LOCKUP event
	RCM_SSRS1_SSW_Pos      = 0x2  // Position of SSW field.
	RCM_SSRS1_SSW_Msk      = 0x4  // Bit mask of SSW field.
	RCM_SSRS1_SSW          = 0x4  // Bit SSW.
	RCM_SSRS1_SSW_0        = 0x0  // Reset not caused by software setting of SYSRESETREQ bit
	RCM_SSRS1_SSW_1        = 0x1  // Reset caused by software setting of SYSRESETREQ bit
	RCM_SSRS1_SMDM_AP_Pos  = 0x3  // Position of SMDM_AP field.
	RCM_SSRS1_SMDM_AP_Msk  = 0x8  // Bit mask of SMDM_AP field.
	RCM_SSRS1_SMDM_AP      = 0x8  // Bit SMDM_AP.
	RCM_SSRS1_SMDM_AP_0    = 0x0  // Reset not caused by host debugger system setting of the System Reset Request bit
	RCM_SSRS1_SMDM_AP_1    = 0x1  // Reset caused by host debugger system setting of the System Reset Request bit
	RCM_SSRS1_SEZPT_Pos    = 0x4  // Position of SEZPT field.
	RCM_SSRS1_SEZPT_Msk    = 0x10 // Bit mask of SEZPT field.
	RCM_SSRS1_SEZPT        = 0x10 // Bit SEZPT.
	RCM_SSRS1_SEZPT_0      = 0x0  // Reset not caused by EzPort receiving the RESET command while the device is in EzPort mode
	RCM_SSRS1_SEZPT_1      = 0x1  // Reset caused by EzPort receiving the RESET command while the device is in EzPort mode
	RCM_SSRS1_SSACKERR_Pos = 0x5  // Position of SSACKERR field.
	RCM_SSRS1_SSACKERR_Msk = 0x20 // Bit mask of SSACKERR field.
	RCM_SSRS1_SSACKERR     = 0x20 // Bit SSACKERR.
	RCM_SSRS1_SSACKERR_0   = 0x0  // Reset not caused by peripheral failure to acknowledge attempt to enter stop mode
	RCM_SSRS1_SSACKERR_1   = 0x1  // Reset caused by peripheral failure to acknowledge attempt to enter stop mode
)

// Bitfields for GPIOA: General Purpose Input/Output
const (
	// PDOR: Port Data Output Register
	GPIO_PDOR_PDO_Pos = 0x0        // Position of PDO field.
	GPIO_PDOR_PDO_Msk = 0xffffffff // Bit mask of PDO field.
	GPIO_PDOR_PDO_0   = 0x0        // Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
	GPIO_PDOR_PDO_1   = 0x1        // Logic level 1 is driven on pin, provided pin is configured for general-purpose output.

	// PSOR: Port Set Output Register
	GPIO_PSOR_PTSO_Pos = 0x0        // Position of PTSO field.
	GPIO_PSOR_PTSO_Msk = 0xffffffff // Bit mask of PTSO field.
	GPIO_PSOR_PTSO_0   = 0x0        // Corresponding bit in PDORn does not change.
	GPIO_PSOR_PTSO_1   = 0x1        // Corresponding bit in PDORn is set to logic 1.

	// PCOR: Port Clear Output Register
	GPIO_PCOR_PTCO_Pos = 0x0        // Position of PTCO field.
	GPIO_PCOR_PTCO_Msk = 0xffffffff // Bit mask of PTCO field.
	GPIO_PCOR_PTCO_0   = 0x0        // Corresponding bit in PDORn does not change.
	GPIO_PCOR_PTCO_1   = 0x1        // Corresponding bit in PDORn is cleared to logic 0.

	// PTOR: Port Toggle Output Register
	GPIO_PTOR_PTTO_Pos = 0x0        // Position of PTTO field.
	GPIO_PTOR_PTTO_Msk = 0xffffffff // Bit mask of PTTO field.
	GPIO_PTOR_PTTO_0   = 0x0        // Corresponding bit in PDORn does not change.
	GPIO_PTOR_PTTO_1   = 0x1        // Corresponding bit in PDORn is set to the inverse of its existing logic state.

	// PDIR: Port Data Input Register
	GPIO_PDIR_PDI_Pos = 0x0        // Position of PDI field.
	GPIO_PDIR_PDI_Msk = 0xffffffff // Bit mask of PDI field.
	GPIO_PDIR_PDI_0   = 0x0        // Pin logic level is logic 0, or is not configured for use by digital function.
	GPIO_PDIR_PDI_1   = 0x1        // Pin logic level is logic 1.

	// PDDR: Port Data Direction Register
	GPIO_PDDR_PDD_Pos = 0x0        // Position of PDD field.
	GPIO_PDDR_PDD_Msk = 0xffffffff // Bit mask of PDD field.
	GPIO_PDDR_PDD_0   = 0x0        // Pin is configured as general-purpose input, for the GPIO function.
	GPIO_PDDR_PDD_1   = 0x1        // Pin is configured as general-purpose output, for the GPIO function.
)

// Bitfields for SystemControl: System Control Block
const (
	// ACTLR: Auxiliary Control Register,
	SystemControl_ACTLR_DISMCYCINT_Pos = 0x0 // Position of DISMCYCINT field.
	SystemControl_ACTLR_DISMCYCINT_Msk = 0x1 // Bit mask of DISMCYCINT field.
	SystemControl_ACTLR_DISMCYCINT     = 0x1 // Bit DISMCYCINT.
	SystemControl_ACTLR_DISDEFWBUF_Pos = 0x1 // Position of DISDEFWBUF field.
	SystemControl_ACTLR_DISDEFWBUF_Msk = 0x2 // Bit mask of DISDEFWBUF field.
	SystemControl_ACTLR_DISDEFWBUF     = 0x2 // Bit DISDEFWBUF.
	SystemControl_ACTLR_DISFOLD_Pos    = 0x2 // Position of DISFOLD field.
	SystemControl_ACTLR_DISFOLD_Msk    = 0x4 // Bit mask of DISFOLD field.
	SystemControl_ACTLR_DISFOLD        = 0x4 // Bit DISFOLD.

	// CPUID: CPUID Base Register
	SystemControl_CPUID_REVISION_Pos    = 0x0        // Position of REVISION field.
	SystemControl_CPUID_REVISION_Msk    = 0xf        // Bit mask of REVISION field.
	SystemControl_CPUID_PARTNO_Pos      = 0x4        // Position of PARTNO field.
	SystemControl_CPUID_PARTNO_Msk      = 0xfff0     // Bit mask of PARTNO field.
	SystemControl_CPUID_VARIANT_Pos     = 0x14       // Position of VARIANT field.
	SystemControl_CPUID_VARIANT_Msk     = 0xf00000   // Bit mask of VARIANT field.
	SystemControl_CPUID_IMPLEMENTER_Pos = 0x18       // Position of IMPLEMENTER field.
	SystemControl_CPUID_IMPLEMENTER_Msk = 0xff000000 // Bit mask of IMPLEMENTER field.

	// ICSR: Interrupt Control and State Register
	SystemControl_ICSR_VECTACTIVE_Pos  = 0x0        // Position of VECTACTIVE field.
	SystemControl_ICSR_VECTACTIVE_Msk  = 0x1ff      // Bit mask of VECTACTIVE field.
	SystemControl_ICSR_RETTOBASE_Pos   = 0xb        // Position of RETTOBASE field.
	SystemControl_ICSR_RETTOBASE_Msk   = 0x800      // Bit mask of RETTOBASE field.
	SystemControl_ICSR_RETTOBASE       = 0x800      // Bit RETTOBASE.
	SystemControl_ICSR_RETTOBASE_0     = 0x0        // there are preempted active exceptions to execute
	SystemControl_ICSR_RETTOBASE_1     = 0x1        // there are no active exceptions, or the currently-executing exception is the only active exception
	SystemControl_ICSR_VECTPENDING_Pos = 0xc        // Position of VECTPENDING field.
	SystemControl_ICSR_VECTPENDING_Msk = 0x3f000    // Bit mask of VECTPENDING field.
	SystemControl_ICSR_ISRPENDING_Pos  = 0x16       // Position of ISRPENDING field.
	SystemControl_ICSR_ISRPENDING_Msk  = 0x400000   // Bit mask of ISRPENDING field.
	SystemControl_ICSR_ISRPENDING      = 0x400000   // Bit ISRPENDING.
	SystemControl_ICSR_ISRPREEMPT_Pos  = 0x17       // Position of ISRPREEMPT field.
	SystemControl_ICSR_ISRPREEMPT_Msk  = 0x800000   // Bit mask of ISRPREEMPT field.
	SystemControl_ICSR_ISRPREEMPT      = 0x800000   // Bit ISRPREEMPT.
	SystemControl_ICSR_ISRPREEMPT_0    = 0x0        // Will not service
	SystemControl_ICSR_ISRPREEMPT_1    = 0x1        // Will service a pending exception
	SystemControl_ICSR_PENDSTCLR_Pos   = 0x19       // Position of PENDSTCLR field.
	SystemControl_ICSR_PENDSTCLR_Msk   = 0x2000000  // Bit mask of PENDSTCLR field.
	SystemControl_ICSR_PENDSTCLR       = 0x2000000  // Bit PENDSTCLR.
	SystemControl_ICSR_PENDSTCLR_0     = 0x0        // no effect
	SystemControl_ICSR_PENDSTCLR_1     = 0x1        // removes the pending state from the SysTick exception
	SystemControl_ICSR_PENDSTSET_Pos   = 0x1a       // Position of PENDSTSET field.
	SystemControl_ICSR_PENDSTSET_Msk   = 0x4000000  // Bit mask of PENDSTSET field.
	SystemControl_ICSR_PENDSTSET       = 0x4000000  // Bit PENDSTSET.
	SystemControl_ICSR_PENDSTSET_0     = 0x0        // write: no effect; read: SysTick exception is not pending
	SystemControl_ICSR_PENDSTSET_1     = 0x1        // write: changes SysTick exception state to pending; read: SysTick exception is pending
	SystemControl_ICSR_PENDSVCLR_Pos   = 0x1b       // Position of PENDSVCLR field.
	SystemControl_ICSR_PENDSVCLR_Msk   = 0x8000000  // Bit mask of PENDSVCLR field.
	SystemControl_ICSR_PENDSVCLR       = 0x8000000  // Bit PENDSVCLR.
	SystemControl_ICSR_PENDSVCLR_0     = 0x0        // no effect
	SystemControl_ICSR_PENDSVCLR_1     = 0x1        // removes the pending state from the PendSV exception
	SystemControl_ICSR_PENDSVSET_Pos   = 0x1c       // Position of PENDSVSET field.
	SystemControl_ICSR_PENDSVSET_Msk   = 0x10000000 // Bit mask of PENDSVSET field.
	SystemControl_ICSR_PENDSVSET       = 0x10000000 // Bit PENDSVSET.
	SystemControl_ICSR_PENDSVSET_0     = 0x0        // write: no effect; read: PendSV exception is not pending
	SystemControl_ICSR_PENDSVSET_1     = 0x1        // write: changes PendSV exception state to pending; read: PendSV exception is pending
	SystemControl_ICSR_NMIPENDSET_Pos  = 0x1f       // Position of NMIPENDSET field.
	SystemControl_ICSR_NMIPENDSET_Msk  = 0x80000000 // Bit mask of NMIPENDSET field.
	SystemControl_ICSR_NMIPENDSET      = 0x80000000 // Bit NMIPENDSET.
	SystemControl_ICSR_NMIPENDSET_0    = 0x0        // write: no effect; read: NMI exception is not pending
	SystemControl_ICSR_NMIPENDSET_1    = 0x1        // write: changes NMI exception state to pending; read: NMI exception is pending

	// VTOR: Vector Table Offset Register
	SystemControl_VTOR_TBLOFF_Pos = 0x7        // Position of TBLOFF field.
	SystemControl_VTOR_TBLOFF_Msk = 0xffffff80 // Bit mask of TBLOFF field.

	// AIRCR: Application Interrupt and Reset Control Register
	SystemControl_AIRCR_VECTRESET_Pos     = 0x0        // Position of VECTRESET field.
	SystemControl_AIRCR_VECTRESET_Msk     = 0x1        // Bit mask of VECTRESET field.
	SystemControl_AIRCR_VECTRESET         = 0x1        // Bit VECTRESET.
	SystemControl_AIRCR_VECTCLRACTIVE_Pos = 0x1        // Position of VECTCLRACTIVE field.
	SystemControl_AIRCR_VECTCLRACTIVE_Msk = 0x2        // Bit mask of VECTCLRACTIVE field.
	SystemControl_AIRCR_VECTCLRACTIVE     = 0x2        // Bit VECTCLRACTIVE.
	SystemControl_AIRCR_SYSRESETREQ_Pos   = 0x2        // Position of SYSRESETREQ field.
	SystemControl_AIRCR_SYSRESETREQ_Msk   = 0x4        // Bit mask of SYSRESETREQ field.
	SystemControl_AIRCR_SYSRESETREQ       = 0x4        // Bit SYSRESETREQ.
	SystemControl_AIRCR_SYSRESETREQ_0     = 0x0        // no system reset request
	SystemControl_AIRCR_SYSRESETREQ_1     = 0x1        // asserts a signal to the outer system that requests a reset
	SystemControl_AIRCR_PRIGROUP_Pos      = 0x8        // Position of PRIGROUP field.
	SystemControl_AIRCR_PRIGROUP_Msk      = 0x700      // Bit mask of PRIGROUP field.
	SystemControl_AIRCR_ENDIANNESS_Pos    = 0xf        // Position of ENDIANNESS field.
	SystemControl_AIRCR_ENDIANNESS_Msk    = 0x8000     // Bit mask of ENDIANNESS field.
	SystemControl_AIRCR_ENDIANNESS        = 0x8000     // Bit ENDIANNESS.
	SystemControl_AIRCR_ENDIANNESS_0      = 0x0        // Little-endian
	SystemControl_AIRCR_ENDIANNESS_1      = 0x1        // Big-endian
	SystemControl_AIRCR_VECTKEY_Pos       = 0x10       // Position of VECTKEY field.
	SystemControl_AIRCR_VECTKEY_Msk       = 0xffff0000 // Bit mask of VECTKEY field.

	// SCR: System Control Register
	SystemControl_SCR_SLEEPONEXIT_Pos = 0x1  // Position of SLEEPONEXIT field.
	SystemControl_SCR_SLEEPONEXIT_Msk = 0x2  // Bit mask of SLEEPONEXIT field.
	SystemControl_SCR_SLEEPONEXIT     = 0x2  // Bit SLEEPONEXIT.
	SystemControl_SCR_SLEEPONEXIT_0   = 0x0  // o not sleep when returning to Thread mode
	SystemControl_SCR_SLEEPONEXIT_1   = 0x1  // enter sleep, or deep sleep, on return from an ISR
	SystemControl_SCR_SLEEPDEEP_Pos   = 0x2  // Position of SLEEPDEEP field.
	SystemControl_SCR_SLEEPDEEP_Msk   = 0x4  // Bit mask of SLEEPDEEP field.
	SystemControl_SCR_SLEEPDEEP       = 0x4  // Bit SLEEPDEEP.
	SystemControl_SCR_SLEEPDEEP_0     = 0x0  // sleep
	SystemControl_SCR_SLEEPDEEP_1     = 0x1  // deep sleep
	SystemControl_SCR_SEVONPEND_Pos   = 0x4  // Position of SEVONPEND field.
	SystemControl_SCR_SEVONPEND_Msk   = 0x10 // Bit mask of SEVONPEND field.
	SystemControl_SCR_SEVONPEND       = 0x10 // Bit SEVONPEND.
	SystemControl_SCR_SEVONPEND_0     = 0x0  // only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded
	SystemControl_SCR_SEVONPEND_1     = 0x1  // enabled events and all interrupts, including disabled interrupts, can wakeup the processor

	// CCR: Configuration and Control Register
	SystemControl_CCR_NONBASETHRDENA_Pos = 0x0   // Position of NONBASETHRDENA field.
	SystemControl_CCR_NONBASETHRDENA_Msk = 0x1   // Bit mask of NONBASETHRDENA field.
	SystemControl_CCR_NONBASETHRDENA     = 0x1   // Bit NONBASETHRDENA.
	SystemControl_CCR_NONBASETHRDENA_0   = 0x0   // processor can enter Thread mode only when no exception is active
	SystemControl_CCR_NONBASETHRDENA_1   = 0x1   // processor can enter Thread mode from any level under the control of an EXC_RETURN value
	SystemControl_CCR_USERSETMPEND_Pos   = 0x1   // Position of USERSETMPEND field.
	SystemControl_CCR_USERSETMPEND_Msk   = 0x2   // Bit mask of USERSETMPEND field.
	SystemControl_CCR_USERSETMPEND       = 0x2   // Bit USERSETMPEND.
	SystemControl_CCR_USERSETMPEND_0     = 0x0   // disable
	SystemControl_CCR_USERSETMPEND_1     = 0x1   // enable
	SystemControl_CCR_UNALIGN_TRP_Pos    = 0x3   // Position of UNALIGN_TRP field.
	SystemControl_CCR_UNALIGN_TRP_Msk    = 0x8   // Bit mask of UNALIGN_TRP field.
	SystemControl_CCR_UNALIGN_TRP        = 0x8   // Bit UNALIGN_TRP.
	SystemControl_CCR_UNALIGN_TRP_0      = 0x0   // do not trap unaligned halfword and word accesses
	SystemControl_CCR_UNALIGN_TRP_1      = 0x1   // trap unaligned halfword and word accesses
	SystemControl_CCR_DIV_0_TRP_Pos      = 0x4   // Position of DIV_0_TRP field.
	SystemControl_CCR_DIV_0_TRP_Msk      = 0x10  // Bit mask of DIV_0_TRP field.
	SystemControl_CCR_DIV_0_TRP          = 0x10  // Bit DIV_0_TRP.
	SystemControl_CCR_DIV_0_TRP_0        = 0x0   // do not trap divide by 0
	SystemControl_CCR_DIV_0_TRP_1        = 0x1   // trap divide by 0
	SystemControl_CCR_BFHFNMIGN_Pos      = 0x8   // Position of BFHFNMIGN field.
	SystemControl_CCR_BFHFNMIGN_Msk      = 0x100 // Bit mask of BFHFNMIGN field.
	SystemControl_CCR_BFHFNMIGN          = 0x100 // Bit BFHFNMIGN.
	SystemControl_CCR_BFHFNMIGN_0        = 0x0   // data bus faults caused by load and store instructions cause a lock-up
	SystemControl_CCR_BFHFNMIGN_1        = 0x1   // handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions
	SystemControl_CCR_STKALIGN_Pos       = 0x9   // Position of STKALIGN field.
	SystemControl_CCR_STKALIGN_Msk       = 0x200 // Bit mask of STKALIGN field.
	SystemControl_CCR_STKALIGN           = 0x200 // Bit STKALIGN.
	SystemControl_CCR_STKALIGN_0         = 0x0   // 4-byte aligned
	SystemControl_CCR_STKALIGN_1         = 0x1   // 8-byte aligned

	// SHPR1: System Handler Priority Register 1
	SystemControl_SHPR1_PRI_4_Pos = 0x0      // Position of PRI_4 field.
	SystemControl_SHPR1_PRI_4_Msk = 0xff     // Bit mask of PRI_4 field.
	SystemControl_SHPR1_PRI_5_Pos = 0x8      // Position of PRI_5 field.
	SystemControl_SHPR1_PRI_5_Msk = 0xff00   // Bit mask of PRI_5 field.
	SystemControl_SHPR1_PRI_6_Pos = 0x10     // Position of PRI_6 field.
	SystemControl_SHPR1_PRI_6_Msk = 0xff0000 // Bit mask of PRI_6 field.

	// SHPR2: System Handler Priority Register 2
	SystemControl_SHPR2_PRI_11_Pos = 0x18       // Position of PRI_11 field.
	SystemControl_SHPR2_PRI_11_Msk = 0xff000000 // Bit mask of PRI_11 field.

	// SHPR3: System Handler Priority Register 3
	SystemControl_SHPR3_PRI_14_Pos = 0x10       // Position of PRI_14 field.
	SystemControl_SHPR3_PRI_14_Msk = 0xff0000   // Bit mask of PRI_14 field.
	SystemControl_SHPR3_PRI_15_Pos = 0x18       // Position of PRI_15 field.
	SystemControl_SHPR3_PRI_15_Msk = 0xff000000 // Bit mask of PRI_15 field.

	// SHCSR: System Handler Control and State Register
	SystemControl_SHCSR_MEMFAULTACT_Pos    = 0x0     // Position of MEMFAULTACT field.
	SystemControl_SHCSR_MEMFAULTACT_Msk    = 0x1     // Bit mask of MEMFAULTACT field.
	SystemControl_SHCSR_MEMFAULTACT        = 0x1     // Bit MEMFAULTACT.
	SystemControl_SHCSR_MEMFAULTACT_0      = 0x0     // exception is not active
	SystemControl_SHCSR_MEMFAULTACT_1      = 0x1     // exception is active
	SystemControl_SHCSR_BUSFAULTACT_Pos    = 0x1     // Position of BUSFAULTACT field.
	SystemControl_SHCSR_BUSFAULTACT_Msk    = 0x2     // Bit mask of BUSFAULTACT field.
	SystemControl_SHCSR_BUSFAULTACT        = 0x2     // Bit BUSFAULTACT.
	SystemControl_SHCSR_BUSFAULTACT_0      = 0x0     // exception is not active
	SystemControl_SHCSR_BUSFAULTACT_1      = 0x1     // exception is active
	SystemControl_SHCSR_USGFAULTACT_Pos    = 0x3     // Position of USGFAULTACT field.
	SystemControl_SHCSR_USGFAULTACT_Msk    = 0x8     // Bit mask of USGFAULTACT field.
	SystemControl_SHCSR_USGFAULTACT        = 0x8     // Bit USGFAULTACT.
	SystemControl_SHCSR_USGFAULTACT_0      = 0x0     // exception is not active
	SystemControl_SHCSR_USGFAULTACT_1      = 0x1     // exception is active
	SystemControl_SHCSR_SVCALLACT_Pos      = 0x7     // Position of SVCALLACT field.
	SystemControl_SHCSR_SVCALLACT_Msk      = 0x80    // Bit mask of SVCALLACT field.
	SystemControl_SHCSR_SVCALLACT          = 0x80    // Bit SVCALLACT.
	SystemControl_SHCSR_SVCALLACT_0        = 0x0     // exception is not active
	SystemControl_SHCSR_SVCALLACT_1        = 0x1     // exception is active
	SystemControl_SHCSR_MONITORACT_Pos     = 0x8     // Position of MONITORACT field.
	SystemControl_SHCSR_MONITORACT_Msk     = 0x100   // Bit mask of MONITORACT field.
	SystemControl_SHCSR_MONITORACT         = 0x100   // Bit MONITORACT.
	SystemControl_SHCSR_MONITORACT_0       = 0x0     // exception is not active
	SystemControl_SHCSR_MONITORACT_1       = 0x1     // exception is active
	SystemControl_SHCSR_PENDSVACT_Pos      = 0xa     // Position of PENDSVACT field.
	SystemControl_SHCSR_PENDSVACT_Msk      = 0x400   // Bit mask of PENDSVACT field.
	SystemControl_SHCSR_PENDSVACT          = 0x400   // Bit PENDSVACT.
	SystemControl_SHCSR_PENDSVACT_0        = 0x0     // exception is not active
	SystemControl_SHCSR_PENDSVACT_1        = 0x1     // exception is active
	SystemControl_SHCSR_SYSTICKACT_Pos     = 0xb     // Position of SYSTICKACT field.
	SystemControl_SHCSR_SYSTICKACT_Msk     = 0x800   // Bit mask of SYSTICKACT field.
	SystemControl_SHCSR_SYSTICKACT         = 0x800   // Bit SYSTICKACT.
	SystemControl_SHCSR_SYSTICKACT_0       = 0x0     // exception is not active
	SystemControl_SHCSR_SYSTICKACT_1       = 0x1     // exception is active
	SystemControl_SHCSR_USGFAULTPENDED_Pos = 0xc     // Position of USGFAULTPENDED field.
	SystemControl_SHCSR_USGFAULTPENDED_Msk = 0x1000  // Bit mask of USGFAULTPENDED field.
	SystemControl_SHCSR_USGFAULTPENDED     = 0x1000  // Bit USGFAULTPENDED.
	SystemControl_SHCSR_USGFAULTPENDED_0   = 0x0     // exception is not pending
	SystemControl_SHCSR_USGFAULTPENDED_1   = 0x1     // exception is pending
	SystemControl_SHCSR_MEMFAULTPENDED_Pos = 0xd     // Position of MEMFAULTPENDED field.
	SystemControl_SHCSR_MEMFAULTPENDED_Msk = 0x2000  // Bit mask of MEMFAULTPENDED field.
	SystemControl_SHCSR_MEMFAULTPENDED     = 0x2000  // Bit MEMFAULTPENDED.
	SystemControl_SHCSR_MEMFAULTPENDED_0   = 0x0     // exception is not pending
	SystemControl_SHCSR_MEMFAULTPENDED_1   = 0x1     // exception is pending
	SystemControl_SHCSR_BUSFAULTPENDED_Pos = 0xe     // Position of BUSFAULTPENDED field.
	SystemControl_SHCSR_BUSFAULTPENDED_Msk = 0x4000  // Bit mask of BUSFAULTPENDED field.
	SystemControl_SHCSR_BUSFAULTPENDED     = 0x4000  // Bit BUSFAULTPENDED.
	SystemControl_SHCSR_BUSFAULTPENDED_0   = 0x0     // exception is not pending
	SystemControl_SHCSR_BUSFAULTPENDED_1   = 0x1     // exception is pending
	SystemControl_SHCSR_SVCALLPENDED_Pos   = 0xf     // Position of SVCALLPENDED field.
	SystemControl_SHCSR_SVCALLPENDED_Msk   = 0x8000  // Bit mask of SVCALLPENDED field.
	SystemControl_SHCSR_SVCALLPENDED       = 0x8000  // Bit SVCALLPENDED.
	SystemControl_SHCSR_SVCALLPENDED_0     = 0x0     // exception is not pending
	SystemControl_SHCSR_SVCALLPENDED_1     = 0x1     // exception is pending
	SystemControl_SHCSR_MEMFAULTENA_Pos    = 0x10    // Position of MEMFAULTENA field.
	SystemControl_SHCSR_MEMFAULTENA_Msk    = 0x10000 // Bit mask of MEMFAULTENA field.
	SystemControl_SHCSR_MEMFAULTENA        = 0x10000 // Bit MEMFAULTENA.
	SystemControl_SHCSR_MEMFAULTENA_0      = 0x0     // disable the exception
	SystemControl_SHCSR_MEMFAULTENA_1      = 0x1     // enable the exception
	SystemControl_SHCSR_BUSFAULTENA_Pos    = 0x11    // Position of BUSFAULTENA field.
	SystemControl_SHCSR_BUSFAULTENA_Msk    = 0x20000 // Bit mask of BUSFAULTENA field.
	SystemControl_SHCSR_BUSFAULTENA        = 0x20000 // Bit BUSFAULTENA.
	SystemControl_SHCSR_BUSFAULTENA_0      = 0x0     // disable the exception
	SystemControl_SHCSR_BUSFAULTENA_1      = 0x1     // enable the exception
	SystemControl_SHCSR_USGFAULTENA_Pos    = 0x12    // Position of USGFAULTENA field.
	SystemControl_SHCSR_USGFAULTENA_Msk    = 0x40000 // Bit mask of USGFAULTENA field.
	SystemControl_SHCSR_USGFAULTENA        = 0x40000 // Bit USGFAULTENA.
	SystemControl_SHCSR_USGFAULTENA_0      = 0x0     // disable the exception
	SystemControl_SHCSR_USGFAULTENA_1      = 0x1     // enable the exception

	// CFSR: Configurable Fault Status Registers
	SystemControl_CFSR_IACCVIOL_Pos    = 0x0       // Position of IACCVIOL field.
	SystemControl_CFSR_IACCVIOL_Msk    = 0x1       // Bit mask of IACCVIOL field.
	SystemControl_CFSR_IACCVIOL        = 0x1       // Bit IACCVIOL.
	SystemControl_CFSR_IACCVIOL_0      = 0x0       // no instruction access violation fault
	SystemControl_CFSR_IACCVIOL_1      = 0x1       // the processor attempted an instruction fetch from a location that does not permit execution
	SystemControl_CFSR_DACCVIOL_Pos    = 0x1       // Position of DACCVIOL field.
	SystemControl_CFSR_DACCVIOL_Msk    = 0x2       // Bit mask of DACCVIOL field.
	SystemControl_CFSR_DACCVIOL        = 0x2       // Bit DACCVIOL.
	SystemControl_CFSR_DACCVIOL_0      = 0x0       // no data access violation fault
	SystemControl_CFSR_DACCVIOL_1      = 0x1       // the processor attempted a load or store at a location that does not permit the operation
	SystemControl_CFSR_MUNSTKERR_Pos   = 0x3       // Position of MUNSTKERR field.
	SystemControl_CFSR_MUNSTKERR_Msk   = 0x8       // Bit mask of MUNSTKERR field.
	SystemControl_CFSR_MUNSTKERR       = 0x8       // Bit MUNSTKERR.
	SystemControl_CFSR_MUNSTKERR_0     = 0x0       // no unstacking fault
	SystemControl_CFSR_MUNSTKERR_1     = 0x1       // unstack for an exception return has caused one or more access violations
	SystemControl_CFSR_MSTKERR_Pos     = 0x4       // Position of MSTKERR field.
	SystemControl_CFSR_MSTKERR_Msk     = 0x10      // Bit mask of MSTKERR field.
	SystemControl_CFSR_MSTKERR         = 0x10      // Bit MSTKERR.
	SystemControl_CFSR_MSTKERR_0       = 0x0       // no stacking fault
	SystemControl_CFSR_MSTKERR_1       = 0x1       // stacking for an exception entry has caused one or more access violations
	SystemControl_CFSR_MLSPERR_Pos     = 0x5       // Position of MLSPERR field.
	SystemControl_CFSR_MLSPERR_Msk     = 0x20      // Bit mask of MLSPERR field.
	SystemControl_CFSR_MLSPERR         = 0x20      // Bit MLSPERR.
	SystemControl_CFSR_MLSPERR_0       = 0x0       // No MemManage fault occurred during floating-point lazy state preservation
	SystemControl_CFSR_MLSPERR_1       = 0x1       // A MemManage fault occurred during floating-point lazy state preservation
	SystemControl_CFSR_MMARVALID_Pos   = 0x7       // Position of MMARVALID field.
	SystemControl_CFSR_MMARVALID_Msk   = 0x80      // Bit mask of MMARVALID field.
	SystemControl_CFSR_MMARVALID       = 0x80      // Bit MMARVALID.
	SystemControl_CFSR_MMARVALID_0     = 0x0       // value in MMAR is not a valid fault address
	SystemControl_CFSR_MMARVALID_1     = 0x1       // MMAR holds a valid fault address
	SystemControl_CFSR_IBUSERR_Pos     = 0x8       // Position of IBUSERR field.
	SystemControl_CFSR_IBUSERR_Msk     = 0x100     // Bit mask of IBUSERR field.
	SystemControl_CFSR_IBUSERR         = 0x100     // Bit IBUSERR.
	SystemControl_CFSR_IBUSERR_0       = 0x0       // no instruction bus error
	SystemControl_CFSR_IBUSERR_1       = 0x1       // instruction bus error
	SystemControl_CFSR_PRECISERR_Pos   = 0x9       // Position of PRECISERR field.
	SystemControl_CFSR_PRECISERR_Msk   = 0x200     // Bit mask of PRECISERR field.
	SystemControl_CFSR_PRECISERR       = 0x200     // Bit PRECISERR.
	SystemControl_CFSR_PRECISERR_0     = 0x0       // no precise data bus error
	SystemControl_CFSR_PRECISERR_1     = 0x1       // a data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault
	SystemControl_CFSR_IMPRECISERR_Pos = 0xa       // Position of IMPRECISERR field.
	SystemControl_CFSR_IMPRECISERR_Msk = 0x400     // Bit mask of IMPRECISERR field.
	SystemControl_CFSR_IMPRECISERR     = 0x400     // Bit IMPRECISERR.
	SystemControl_CFSR_IMPRECISERR_0   = 0x0       // no imprecise data bus error
	SystemControl_CFSR_IMPRECISERR_1   = 0x1       // a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error
	SystemControl_CFSR_UNSTKERR_Pos    = 0xb       // Position of UNSTKERR field.
	SystemControl_CFSR_UNSTKERR_Msk    = 0x800     // Bit mask of UNSTKERR field.
	SystemControl_CFSR_UNSTKERR        = 0x800     // Bit UNSTKERR.
	SystemControl_CFSR_UNSTKERR_0      = 0x0       // no unstacking fault
	SystemControl_CFSR_UNSTKERR_1      = 0x1       // unstack for an exception return has caused one or more BusFaults
	SystemControl_CFSR_STKERR_Pos      = 0xc       // Position of STKERR field.
	SystemControl_CFSR_STKERR_Msk      = 0x1000    // Bit mask of STKERR field.
	SystemControl_CFSR_STKERR          = 0x1000    // Bit STKERR.
	SystemControl_CFSR_STKERR_0        = 0x0       // no stacking fault
	SystemControl_CFSR_STKERR_1        = 0x1       // stacking for an exception entry has caused one or more BusFaults
	SystemControl_CFSR_LSPERR_Pos      = 0xd       // Position of LSPERR field.
	SystemControl_CFSR_LSPERR_Msk      = 0x2000    // Bit mask of LSPERR field.
	SystemControl_CFSR_LSPERR          = 0x2000    // Bit LSPERR.
	SystemControl_CFSR_LSPERR_0        = 0x0       // No bus fault occurred during floating-point lazy state preservation
	SystemControl_CFSR_LSPERR_1        = 0x1       // A bus fault occurred during floating-point lazy state preservation
	SystemControl_CFSR_BFARVALID_Pos   = 0xf       // Position of BFARVALID field.
	SystemControl_CFSR_BFARVALID_Msk   = 0x8000    // Bit mask of BFARVALID field.
	SystemControl_CFSR_BFARVALID       = 0x8000    // Bit BFARVALID.
	SystemControl_CFSR_BFARVALID_0     = 0x0       // value in BFAR is not a valid fault address
	SystemControl_CFSR_BFARVALID_1     = 0x1       // BFAR holds a valid fault address
	SystemControl_CFSR_UNDEFINSTR_Pos  = 0x10      // Position of UNDEFINSTR field.
	SystemControl_CFSR_UNDEFINSTR_Msk  = 0x10000   // Bit mask of UNDEFINSTR field.
	SystemControl_CFSR_UNDEFINSTR      = 0x10000   // Bit UNDEFINSTR.
	SystemControl_CFSR_UNDEFINSTR_0    = 0x0       // no undefined instruction UsageFault
	SystemControl_CFSR_UNDEFINSTR_1    = 0x1       // the processor has attempted to execute an undefined instruction
	SystemControl_CFSR_INVSTATE_Pos    = 0x11      // Position of INVSTATE field.
	SystemControl_CFSR_INVSTATE_Msk    = 0x20000   // Bit mask of INVSTATE field.
	SystemControl_CFSR_INVSTATE        = 0x20000   // Bit INVSTATE.
	SystemControl_CFSR_INVSTATE_0      = 0x0       // no invalid state UsageFault
	SystemControl_CFSR_INVSTATE_1      = 0x1       // the processor has attempted to execute an instruction that makes illegal use of the EPSR
	SystemControl_CFSR_INVPC_Pos       = 0x12      // Position of INVPC field.
	SystemControl_CFSR_INVPC_Msk       = 0x40000   // Bit mask of INVPC field.
	SystemControl_CFSR_INVPC           = 0x40000   // Bit INVPC.
	SystemControl_CFSR_INVPC_0         = 0x0       // no invalid PC load UsageFault
	SystemControl_CFSR_INVPC_1         = 0x1       // the processor has attempted an illegal load of EXC_RETURN to the PC
	SystemControl_CFSR_NOCP_Pos        = 0x13      // Position of NOCP field.
	SystemControl_CFSR_NOCP_Msk        = 0x80000   // Bit mask of NOCP field.
	SystemControl_CFSR_NOCP            = 0x80000   // Bit NOCP.
	SystemControl_CFSR_NOCP_0          = 0x0       // no UsageFault caused by attempting to access a coprocessor
	SystemControl_CFSR_NOCP_1          = 0x1       // the processor has attempted to access a coprocessor
	SystemControl_CFSR_UNALIGNED_Pos   = 0x18      // Position of UNALIGNED field.
	SystemControl_CFSR_UNALIGNED_Msk   = 0x1000000 // Bit mask of UNALIGNED field.
	SystemControl_CFSR_UNALIGNED       = 0x1000000 // Bit UNALIGNED.
	SystemControl_CFSR_UNALIGNED_0     = 0x0       // no unaligned access fault, or unaligned access trapping not enabled
	SystemControl_CFSR_UNALIGNED_1     = 0x1       // the processor has made an unaligned memory access
	SystemControl_CFSR_DIVBYZERO_Pos   = 0x19      // Position of DIVBYZERO field.
	SystemControl_CFSR_DIVBYZERO_Msk   = 0x2000000 // Bit mask of DIVBYZERO field.
	SystemControl_CFSR_DIVBYZERO       = 0x2000000 // Bit DIVBYZERO.
	SystemControl_CFSR_DIVBYZERO_0     = 0x0       // no divide by zero fault, or divide by zero trapping not enabled
	SystemControl_CFSR_DIVBYZERO_1     = 0x1       // the processor has executed an SDIV or UDIV instruction with a divisor of 0

	// HFSR: HardFault Status register
	SystemControl_HFSR_VECTTBL_Pos  = 0x1        // Position of VECTTBL field.
	SystemControl_HFSR_VECTTBL_Msk  = 0x2        // Bit mask of VECTTBL field.
	SystemControl_HFSR_VECTTBL      = 0x2        // Bit VECTTBL.
	SystemControl_HFSR_VECTTBL_0    = 0x0        // no BusFault on vector table read
	SystemControl_HFSR_VECTTBL_1    = 0x1        // BusFault on vector table read
	SystemControl_HFSR_FORCED_Pos   = 0x1e       // Position of FORCED field.
	SystemControl_HFSR_FORCED_Msk   = 0x40000000 // Bit mask of FORCED field.
	SystemControl_HFSR_FORCED       = 0x40000000 // Bit FORCED.
	SystemControl_HFSR_FORCED_0     = 0x0        // no forced HardFault
	SystemControl_HFSR_FORCED_1     = 0x1        // forced HardFault
	SystemControl_HFSR_DEBUGEVT_Pos = 0x1f       // Position of DEBUGEVT field.
	SystemControl_HFSR_DEBUGEVT_Msk = 0x80000000 // Bit mask of DEBUGEVT field.
	SystemControl_HFSR_DEBUGEVT     = 0x80000000 // Bit DEBUGEVT.

	// DFSR: Debug Fault Status Register
	SystemControl_DFSR_HALTED_Pos   = 0x0  // Position of HALTED field.
	SystemControl_DFSR_HALTED_Msk   = 0x1  // Bit mask of HALTED field.
	SystemControl_DFSR_HALTED       = 0x1  // Bit HALTED.
	SystemControl_DFSR_HALTED_0     = 0x0  // No active halt request debug event
	SystemControl_DFSR_HALTED_1     = 0x1  // Halt request debug event active
	SystemControl_DFSR_BKPT_Pos     = 0x1  // Position of BKPT field.
	SystemControl_DFSR_BKPT_Msk     = 0x2  // Bit mask of BKPT field.
	SystemControl_DFSR_BKPT         = 0x2  // Bit BKPT.
	SystemControl_DFSR_BKPT_0       = 0x0  // No current breakpoint debug event
	SystemControl_DFSR_BKPT_1       = 0x1  // At least one current breakpoint debug event
	SystemControl_DFSR_DWTTRAP_Pos  = 0x2  // Position of DWTTRAP field.
	SystemControl_DFSR_DWTTRAP_Msk  = 0x4  // Bit mask of DWTTRAP field.
	SystemControl_DFSR_DWTTRAP      = 0x4  // Bit DWTTRAP.
	SystemControl_DFSR_DWTTRAP_0    = 0x0  // No current debug events generated by the DWT
	SystemControl_DFSR_DWTTRAP_1    = 0x1  // At least one current debug event generated by the DWT
	SystemControl_DFSR_VCATCH_Pos   = 0x3  // Position of VCATCH field.
	SystemControl_DFSR_VCATCH_Msk   = 0x8  // Bit mask of VCATCH field.
	SystemControl_DFSR_VCATCH       = 0x8  // Bit VCATCH.
	SystemControl_DFSR_VCATCH_0     = 0x0  // No Vector catch triggered
	SystemControl_DFSR_VCATCH_1     = 0x1  // Vector catch triggered
	SystemControl_DFSR_EXTERNAL_Pos = 0x4  // Position of EXTERNAL field.
	SystemControl_DFSR_EXTERNAL_Msk = 0x10 // Bit mask of EXTERNAL field.
	SystemControl_DFSR_EXTERNAL     = 0x10 // Bit EXTERNAL.
	SystemControl_DFSR_EXTERNAL_0   = 0x0  // No EDBGRQ debug event
	SystemControl_DFSR_EXTERNAL_1   = 0x1  // EDBGRQ debug event

	// MMFAR: MemManage Address Register
	SystemControl_MMFAR_ADDRESS_Pos = 0x0        // Position of ADDRESS field.
	SystemControl_MMFAR_ADDRESS_Msk = 0xffffffff // Bit mask of ADDRESS field.

	// BFAR: BusFault Address Register
	SystemControl_BFAR_ADDRESS_Pos = 0x0        // Position of ADDRESS field.
	SystemControl_BFAR_ADDRESS_Msk = 0xffffffff // Bit mask of ADDRESS field.

	// AFSR: Auxiliary Fault Status Register
	SystemControl_AFSR_AUXFAULT_Pos = 0x0        // Position of AUXFAULT field.
	SystemControl_AFSR_AUXFAULT_Msk = 0xffffffff // Bit mask of AUXFAULT field.

	// CPACR: Coprocessor Access Control Register
	SystemControl_CPACR_CP10_Pos = 0x14     // Position of CP10 field.
	SystemControl_CPACR_CP10_Msk = 0x300000 // Bit mask of CP10 field.
	SystemControl_CPACR_CP10_00  = 0x0      // Access denied. Any attempted access generates a NOCP UsageFault
	SystemControl_CPACR_CP10_01  = 0x1      // Privileged access only. An unprivileged access generates a NOCP fault.
	SystemControl_CPACR_CP10_10  = 0x2      // Reserved. The result of any access is UNPREDICTABLE.
	SystemControl_CPACR_CP10_11  = 0x3      // Full access.
	SystemControl_CPACR_CP11_Pos = 0x16     // Position of CP11 field.
	SystemControl_CPACR_CP11_Msk = 0xc00000 // Bit mask of CP11 field.
	SystemControl_CPACR_CP11_00  = 0x0      // Access denied. Any attempted access generates a NOCP UsageFault
	SystemControl_CPACR_CP11_01  = 0x1      // Privileged access only. An unprivileged access generates a NOCP fault.
	SystemControl_CPACR_CP11_10  = 0x2      // Reserved. The result of any access is UNPREDICTABLE.
	SystemControl_CPACR_CP11_11  = 0x3      // Full access.

	// FPCCR: Floating-point Context Control Register
	SystemControl_FPCCR_LSPACT_Pos = 0x0        // Position of LSPACT field.
	SystemControl_FPCCR_LSPACT_Msk = 0x1        // Bit mask of LSPACT field.
	SystemControl_FPCCR_LSPACT     = 0x1        // Bit LSPACT.
	SystemControl_FPCCR_LSPACT_0   = 0x0        // Lazy state preservation is not active.
	SystemControl_FPCCR_LSPACT_1   = 0x1        // Lazy state preservation is active. floating-point stack frame has been allocated but saving state to it has been deferred.
	SystemControl_FPCCR_USER_Pos   = 0x1        // Position of USER field.
	SystemControl_FPCCR_USER_Msk   = 0x2        // Bit mask of USER field.
	SystemControl_FPCCR_USER       = 0x2        // Bit USER.
	SystemControl_FPCCR_USER_0     = 0x0        // Privilege level was not user when the floating-point stack frame was allocated.
	SystemControl_FPCCR_USER_1     = 0x1        // Privilege level was user when the floating-point stack frame was allocated.
	SystemControl_FPCCR_THREAD_Pos = 0x3        // Position of THREAD field.
	SystemControl_FPCCR_THREAD_Msk = 0x8        // Bit mask of THREAD field.
	SystemControl_FPCCR_THREAD     = 0x8        // Bit THREAD.
	SystemControl_FPCCR_THREAD_0   = 0x0        // Mode was not Thread Mode when the floating-point stack frame was allocated.
	SystemControl_FPCCR_THREAD_1   = 0x1        // Mode was Thread Mode when the floating-point stack frame was allocated.
	SystemControl_FPCCR_HFRDY_Pos  = 0x4        // Position of HFRDY field.
	SystemControl_FPCCR_HFRDY_Msk  = 0x10       // Bit mask of HFRDY field.
	SystemControl_FPCCR_HFRDY      = 0x10       // Bit HFRDY.
	SystemControl_FPCCR_HFRDY_0    = 0x0        // Priority did not permit setting the HardFault handler to the pending state when the floating-point stack frame was allocated.
	SystemControl_FPCCR_HFRDY_1    = 0x1        // Priority permitted setting the HardFault handler to the pending state when the floating-point stack frame was allocated.
	SystemControl_FPCCR_MMRDY_Pos  = 0x5        // Position of MMRDY field.
	SystemControl_FPCCR_MMRDY_Msk  = 0x20       // Bit mask of MMRDY field.
	SystemControl_FPCCR_MMRDY      = 0x20       // Bit MMRDY.
	SystemControl_FPCCR_MMRDY_0    = 0x0        // MemManage is disabled or priority did not permit setting the MemManage handler to the pending state when the floating-point stack frame was allocated.
	SystemControl_FPCCR_MMRDY_1    = 0x1        // MemManage is enabled and priority permitted setting the MemManage handler to the pending state when the floating-point stack frame was allocated.
	SystemControl_FPCCR_BFRDY_Pos  = 0x6        // Position of BFRDY field.
	SystemControl_FPCCR_BFRDY_Msk  = 0x40       // Bit mask of BFRDY field.
	SystemControl_FPCCR_BFRDY      = 0x40       // Bit BFRDY.
	SystemControl_FPCCR_BFRDY_0    = 0x0        // BusFault is disabled or priority did not permit setting the BusFault handler to the pending state when the floating-point stack frame was allocated.
	SystemControl_FPCCR_BFRDY_1    = 0x1        // BusFault is disabled or priority did not permit setting the BusFault handler to the pending state when the floating-point stack frame was allocated.
	SystemControl_FPCCR_MONRDY_Pos = 0x8        // Position of MONRDY field.
	SystemControl_FPCCR_MONRDY_Msk = 0x100      // Bit mask of MONRDY field.
	SystemControl_FPCCR_MONRDY     = 0x100      // Bit MONRDY.
	SystemControl_FPCCR_MONRDY_0   = 0x0        // DebugMonitor is disabled or priority did not permit setting MON_PEND when the floating-point stack frame was allocated.
	SystemControl_FPCCR_MONRDY_1   = 0x1        // DebugMonitor is enabled and priority permits setting MON_PEND when the floating-point stack frame was allocated.
	SystemControl_FPCCR_LSPEN_Pos  = 0x1e       // Position of LSPEN field.
	SystemControl_FPCCR_LSPEN_Msk  = 0x40000000 // Bit mask of LSPEN field.
	SystemControl_FPCCR_LSPEN      = 0x40000000 // Bit LSPEN.
	SystemControl_FPCCR_LSPEN_0    = 0x0        // Disable automatic lazy state preservation for floating-point context.
	SystemControl_FPCCR_LSPEN_1    = 0x1        // Enable automatic lazy state preservation for floating-point context.
	SystemControl_FPCCR_ASPEN_Pos  = 0x1f       // Position of ASPEN field.
	SystemControl_FPCCR_ASPEN_Msk  = 0x80000000 // Bit mask of ASPEN field.
	SystemControl_FPCCR_ASPEN      = 0x80000000 // Bit ASPEN.
	SystemControl_FPCCR_ASPEN_0    = 0x0        // Disable CONTROL2 setting on execution of a floating-point instruction.
	SystemControl_FPCCR_ASPEN_1    = 0x1        // Enable CONTROL2 setting on execution of a floating-point instruction.

	// FPCAR: Floating-point Context Address Register
	SystemControl_FPCAR_ADDRESS_Pos = 0x3        // Position of ADDRESS field.
	SystemControl_FPCAR_ADDRESS_Msk = 0xfffffff8 // Bit mask of ADDRESS field.

	// FPDSCR: Floating-point Default Status Control Register
	SystemControl_FPDSCR_RMode_Pos = 0x16      // Position of RMode field.
	SystemControl_FPDSCR_RMode_Msk = 0xc00000  // Bit mask of RMode field.
	SystemControl_FPDSCR_RMode_00  = 0x0       // Round to Nearest (RN) mode
	SystemControl_FPDSCR_RMode_01  = 0x1       // Round towards Plus Infinity (RP) mode.
	SystemControl_FPDSCR_RMode_10  = 0x2       // Round towards Minus Infinity (RM) mode.
	SystemControl_FPDSCR_RMode_11  = 0x3       // Round towards Zero (RZ) mode.
	SystemControl_FPDSCR_FZ_Pos    = 0x18      // Position of FZ field.
	SystemControl_FPDSCR_FZ_Msk    = 0x1000000 // Bit mask of FZ field.
	SystemControl_FPDSCR_FZ        = 0x1000000 // Bit FZ.
	SystemControl_FPDSCR_FZ_0      = 0x0       // Flush-to-zero mode disabled. Behavior of the floating-point system is fully compliant with the IEEE 754 standard.
	SystemControl_FPDSCR_FZ_1      = 0x1       // Flush-to-zero mode enabled.
	SystemControl_FPDSCR_DN_Pos    = 0x19      // Position of DN field.
	SystemControl_FPDSCR_DN_Msk    = 0x2000000 // Bit mask of DN field.
	SystemControl_FPDSCR_DN        = 0x2000000 // Bit DN.
	SystemControl_FPDSCR_DN_0      = 0x0       // NaN operands propagate through to the output of a floating-point operation.
	SystemControl_FPDSCR_DN_1      = 0x1       // Any operation involving one or more NaNs returns the Default NaN.
	SystemControl_FPDSCR_AHP_Pos   = 0x1a      // Position of AHP field.
	SystemControl_FPDSCR_AHP_Msk   = 0x4000000 // Bit mask of AHP field.
	SystemControl_FPDSCR_AHP       = 0x4000000 // Bit AHP.
	SystemControl_FPDSCR_AHP_0     = 0x0       // IEEE half-precision format selected.
	SystemControl_FPDSCR_AHP_1     = 0x1       // Alternative half-precision format selected.
)

// Bitfields for SysTick: System timer
const (
	// CSR: SysTick Control and Status Register
	SysTick_CSR_ENABLE_Pos    = 0x0     // Position of ENABLE field.
	SysTick_CSR_ENABLE_Msk    = 0x1     // Bit mask of ENABLE field.
	SysTick_CSR_ENABLE        = 0x1     // Bit ENABLE.
	SysTick_CSR_ENABLE_0      = 0x0     // counter disabled
	SysTick_CSR_ENABLE_1      = 0x1     // counter enabled
	SysTick_CSR_TICKINT_Pos   = 0x1     // Position of TICKINT field.
	SysTick_CSR_TICKINT_Msk   = 0x2     // Bit mask of TICKINT field.
	SysTick_CSR_TICKINT       = 0x2     // Bit TICKINT.
	SysTick_CSR_TICKINT_0     = 0x0     // counting down to 0 does not assert the SysTick exception request
	SysTick_CSR_TICKINT_1     = 0x1     // counting down to 0 asserts the SysTick exception request
	SysTick_CSR_CLKSOURCE_Pos = 0x2     // Position of CLKSOURCE field.
	SysTick_CSR_CLKSOURCE_Msk = 0x4     // Bit mask of CLKSOURCE field.
	SysTick_CSR_CLKSOURCE     = 0x4     // Bit CLKSOURCE.
	SysTick_CSR_CLKSOURCE_0   = 0x0     // external clock
	SysTick_CSR_CLKSOURCE_1   = 0x1     // processor clock
	SysTick_CSR_COUNTFLAG_Pos = 0x10    // Position of COUNTFLAG field.
	SysTick_CSR_COUNTFLAG_Msk = 0x10000 // Bit mask of COUNTFLAG field.
	SysTick_CSR_COUNTFLAG     = 0x10000 // Bit COUNTFLAG.

	// RVR: SysTick Reload Value Register
	SysTick_RVR_RELOAD_Pos = 0x0      // Position of RELOAD field.
	SysTick_RVR_RELOAD_Msk = 0xffffff // Bit mask of RELOAD field.

	// CVR: SysTick Current Value Register
	SysTick_CVR_CURRENT_Pos = 0x0      // Position of CURRENT field.
	SysTick_CVR_CURRENT_Msk = 0xffffff // Bit mask of CURRENT field.

	// CALIB: SysTick Calibration Value Register
	SysTick_CALIB_TENMS_Pos = 0x0        // Position of TENMS field.
	SysTick_CALIB_TENMS_Msk = 0xffffff   // Bit mask of TENMS field.
	SysTick_CALIB_SKEW_Pos  = 0x1e       // Position of SKEW field.
	SysTick_CALIB_SKEW_Msk  = 0x40000000 // Bit mask of SKEW field.
	SysTick_CALIB_SKEW      = 0x40000000 // Bit SKEW.
	SysTick_CALIB_SKEW_0    = 0x0        // 10ms calibration value is exact
	SysTick_CALIB_SKEW_1    = 0x1        // 10ms calibration value is inexact, because of the clock frequency
	SysTick_CALIB_NOREF_Pos = 0x1f       // Position of NOREF field.
	SysTick_CALIB_NOREF_Msk = 0x80000000 // Bit mask of NOREF field.
	SysTick_CALIB_NOREF     = 0x80000000 // Bit NOREF.
	SysTick_CALIB_NOREF_0   = 0x0        // The reference clock is provided
	SysTick_CALIB_NOREF_1   = 0x1        // The reference clock is not provided
)

// Bitfields for NVIC: Nested Vectored Interrupt Controller
const (
	// NVICISER0: Interrupt Set Enable Register n
	NVIC_NVICISER0_SETENA_Pos = 0x0        // Position of SETENA field.
	NVIC_NVICISER0_SETENA_Msk = 0xffffffff // Bit mask of SETENA field.

	// NVICISER1: Interrupt Set Enable Register n
	NVIC_NVICISER1_SETENA_Pos = 0x0        // Position of SETENA field.
	NVIC_NVICISER1_SETENA_Msk = 0xffffffff // Bit mask of SETENA field.

	// NVICISER2: Interrupt Set Enable Register n
	NVIC_NVICISER2_SETENA_Pos = 0x0        // Position of SETENA field.
	NVIC_NVICISER2_SETENA_Msk = 0xffffffff // Bit mask of SETENA field.

	// NVICISER3: Interrupt Set Enable Register n
	NVIC_NVICISER3_SETENA_Pos = 0x0        // Position of SETENA field.
	NVIC_NVICISER3_SETENA_Msk = 0xffffffff // Bit mask of SETENA field.

	// NVICICER0: Interrupt Clear Enable Register n
	NVIC_NVICICER0_CLRENA_Pos = 0x0        // Position of CLRENA field.
	NVIC_NVICICER0_CLRENA_Msk = 0xffffffff // Bit mask of CLRENA field.

	// NVICICER1: Interrupt Clear Enable Register n
	NVIC_NVICICER1_CLRENA_Pos = 0x0        // Position of CLRENA field.
	NVIC_NVICICER1_CLRENA_Msk = 0xffffffff // Bit mask of CLRENA field.

	// NVICICER2: Interrupt Clear Enable Register n
	NVIC_NVICICER2_CLRENA_Pos = 0x0        // Position of CLRENA field.
	NVIC_NVICICER2_CLRENA_Msk = 0xffffffff // Bit mask of CLRENA field.

	// NVICICER3: Interrupt Clear Enable Register n
	NVIC_NVICICER3_CLRENA_Pos = 0x0        // Position of CLRENA field.
	NVIC_NVICICER3_CLRENA_Msk = 0xffffffff // Bit mask of CLRENA field.

	// NVICISPR0: Interrupt Set Pending Register n
	NVIC_NVICISPR0_SETPEND_Pos = 0x0        // Position of SETPEND field.
	NVIC_NVICISPR0_SETPEND_Msk = 0xffffffff // Bit mask of SETPEND field.

	// NVICISPR1: Interrupt Set Pending Register n
	NVIC_NVICISPR1_SETPEND_Pos = 0x0        // Position of SETPEND field.
	NVIC_NVICISPR1_SETPEND_Msk = 0xffffffff // Bit mask of SETPEND field.

	// NVICISPR2: Interrupt Set Pending Register n
	NVIC_NVICISPR2_SETPEND_Pos = 0x0        // Position of SETPEND field.
	NVIC_NVICISPR2_SETPEND_Msk = 0xffffffff // Bit mask of SETPEND field.

	// NVICISPR3: Interrupt Set Pending Register n
	NVIC_NVICISPR3_SETPEND_Pos = 0x0        // Position of SETPEND field.
	NVIC_NVICISPR3_SETPEND_Msk = 0xffffffff // Bit mask of SETPEND field.

	// NVICICPR0: Interrupt Clear Pending Register n
	NVIC_NVICICPR0_CLRPEND_Pos = 0x0        // Position of CLRPEND field.
	NVIC_NVICICPR0_CLRPEND_Msk = 0xffffffff // Bit mask of CLRPEND field.

	// NVICICPR1: Interrupt Clear Pending Register n
	NVIC_NVICICPR1_CLRPEND_Pos = 0x0        // Position of CLRPEND field.
	NVIC_NVICICPR1_CLRPEND_Msk = 0xffffffff // Bit mask of CLRPEND field.

	// NVICICPR2: Interrupt Clear Pending Register n
	NVIC_NVICICPR2_CLRPEND_Pos = 0x0        // Position of CLRPEND field.
	NVIC_NVICICPR2_CLRPEND_Msk = 0xffffffff // Bit mask of CLRPEND field.

	// NVICICPR3: Interrupt Clear Pending Register n
	NVIC_NVICICPR3_CLRPEND_Pos = 0x0        // Position of CLRPEND field.
	NVIC_NVICICPR3_CLRPEND_Msk = 0xffffffff // Bit mask of CLRPEND field.

	// NVICIABR0: Interrupt Active bit Register n
	NVIC_NVICIABR0_ACTIVE_Pos = 0x0        // Position of ACTIVE field.
	NVIC_NVICIABR0_ACTIVE_Msk = 0xffffffff // Bit mask of ACTIVE field.

	// NVICIABR1: Interrupt Active bit Register n
	NVIC_NVICIABR1_ACTIVE_Pos = 0x0        // Position of ACTIVE field.
	NVIC_NVICIABR1_ACTIVE_Msk = 0xffffffff // Bit mask of ACTIVE field.

	// NVICIABR2: Interrupt Active bit Register n
	NVIC_NVICIABR2_ACTIVE_Pos = 0x0        // Position of ACTIVE field.
	NVIC_NVICIABR2_ACTIVE_Msk = 0xffffffff // Bit mask of ACTIVE field.

	// NVICIABR3: Interrupt Active bit Register n
	NVIC_NVICIABR3_ACTIVE_Pos = 0x0        // Position of ACTIVE field.
	NVIC_NVICIABR3_ACTIVE_Msk = 0xffffffff // Bit mask of ACTIVE field.

	// NVICIP0: Interrupt Priority Register n
	NVIC_NVICIP0_PRI0_Pos = 0x0  // Position of PRI0 field.
	NVIC_NVICIP0_PRI0_Msk = 0xff // Bit mask of PRI0 field.

	// NVICIP1: Interrupt Priority Register n
	NVIC_NVICIP1_PRI1_Pos = 0x0  // Position of PRI1 field.
	NVIC_NVICIP1_PRI1_Msk = 0xff // Bit mask of PRI1 field.

	// NVICIP2: Interrupt Priority Register n
	NVIC_NVICIP2_PRI2_Pos = 0x0  // Position of PRI2 field.
	NVIC_NVICIP2_PRI2_Msk = 0xff // Bit mask of PRI2 field.

	// NVICIP3: Interrupt Priority Register n
	NVIC_NVICIP3_PRI3_Pos = 0x0  // Position of PRI3 field.
	NVIC_NVICIP3_PRI3_Msk = 0xff // Bit mask of PRI3 field.

	// NVICIP4: Interrupt Priority Register n
	NVIC_NVICIP4_PRI4_Pos = 0x0  // Position of PRI4 field.
	NVIC_NVICIP4_PRI4_Msk = 0xff // Bit mask of PRI4 field.

	// NVICIP5: Interrupt Priority Register n
	NVIC_NVICIP5_PRI5_Pos = 0x0  // Position of PRI5 field.
	NVIC_NVICIP5_PRI5_Msk = 0xff // Bit mask of PRI5 field.

	// NVICIP6: Interrupt Priority Register n
	NVIC_NVICIP6_PRI6_Pos = 0x0  // Position of PRI6 field.
	NVIC_NVICIP6_PRI6_Msk = 0xff // Bit mask of PRI6 field.

	// NVICIP7: Interrupt Priority Register n
	NVIC_NVICIP7_PRI7_Pos = 0x0  // Position of PRI7 field.
	NVIC_NVICIP7_PRI7_Msk = 0xff // Bit mask of PRI7 field.

	// NVICIP8: Interrupt Priority Register n
	NVIC_NVICIP8_PRI8_Pos = 0x0  // Position of PRI8 field.
	NVIC_NVICIP8_PRI8_Msk = 0xff // Bit mask of PRI8 field.

	// NVICIP9: Interrupt Priority Register n
	NVIC_NVICIP9_PRI9_Pos = 0x0  // Position of PRI9 field.
	NVIC_NVICIP9_PRI9_Msk = 0xff // Bit mask of PRI9 field.

	// NVICIP10: Interrupt Priority Register n
	NVIC_NVICIP10_PRI10_Pos = 0x0  // Position of PRI10 field.
	NVIC_NVICIP10_PRI10_Msk = 0xff // Bit mask of PRI10 field.

	// NVICIP11: Interrupt Priority Register n
	NVIC_NVICIP11_PRI11_Pos = 0x0  // Position of PRI11 field.
	NVIC_NVICIP11_PRI11_Msk = 0xff // Bit mask of PRI11 field.

	// NVICIP12: Interrupt Priority Register n
	NVIC_NVICIP12_PRI12_Pos = 0x0  // Position of PRI12 field.
	NVIC_NVICIP12_PRI12_Msk = 0xff // Bit mask of PRI12 field.

	// NVICIP13: Interrupt Priority Register n
	NVIC_NVICIP13_PRI13_Pos = 0x0  // Position of PRI13 field.
	NVIC_NVICIP13_PRI13_Msk = 0xff // Bit mask of PRI13 field.

	// NVICIP14: Interrupt Priority Register n
	NVIC_NVICIP14_PRI14_Pos = 0x0  // Position of PRI14 field.
	NVIC_NVICIP14_PRI14_Msk = 0xff // Bit mask of PRI14 field.

	// NVICIP15: Interrupt Priority Register n
	NVIC_NVICIP15_PRI15_Pos = 0x0  // Position of PRI15 field.
	NVIC_NVICIP15_PRI15_Msk = 0xff // Bit mask of PRI15 field.

	// NVICIP16: Interrupt Priority Register n
	NVIC_NVICIP16_PRI16_Pos = 0x0  // Position of PRI16 field.
	NVIC_NVICIP16_PRI16_Msk = 0xff // Bit mask of PRI16 field.

	// NVICIP17: Interrupt Priority Register n
	NVIC_NVICIP17_PRI17_Pos = 0x0  // Position of PRI17 field.
	NVIC_NVICIP17_PRI17_Msk = 0xff // Bit mask of PRI17 field.

	// NVICIP18: Interrupt Priority Register n
	NVIC_NVICIP18_PRI18_Pos = 0x0  // Position of PRI18 field.
	NVIC_NVICIP18_PRI18_Msk = 0xff // Bit mask of PRI18 field.

	// NVICIP19: Interrupt Priority Register n
	NVIC_NVICIP19_PRI19_Pos = 0x0  // Position of PRI19 field.
	NVIC_NVICIP19_PRI19_Msk = 0xff // Bit mask of PRI19 field.

	// NVICIP20: Interrupt Priority Register n
	NVIC_NVICIP20_PRI20_Pos = 0x0  // Position of PRI20 field.
	NVIC_NVICIP20_PRI20_Msk = 0xff // Bit mask of PRI20 field.

	// NVICIP21: Interrupt Priority Register n
	NVIC_NVICIP21_PRI21_Pos = 0x0  // Position of PRI21 field.
	NVIC_NVICIP21_PRI21_Msk = 0xff // Bit mask of PRI21 field.

	// NVICIP22: Interrupt Priority Register n
	NVIC_NVICIP22_PRI22_Pos = 0x0  // Position of PRI22 field.
	NVIC_NVICIP22_PRI22_Msk = 0xff // Bit mask of PRI22 field.

	// NVICIP23: Interrupt Priority Register n
	NVIC_NVICIP23_PRI23_Pos = 0x0  // Position of PRI23 field.
	NVIC_NVICIP23_PRI23_Msk = 0xff // Bit mask of PRI23 field.

	// NVICIP24: Interrupt Priority Register n
	NVIC_NVICIP24_PRI24_Pos = 0x0  // Position of PRI24 field.
	NVIC_NVICIP24_PRI24_Msk = 0xff // Bit mask of PRI24 field.

	// NVICIP25: Interrupt Priority Register n
	NVIC_NVICIP25_PRI25_Pos = 0x0  // Position of PRI25 field.
	NVIC_NVICIP25_PRI25_Msk = 0xff // Bit mask of PRI25 field.

	// NVICIP26: Interrupt Priority Register n
	NVIC_NVICIP26_PRI26_Pos = 0x0  // Position of PRI26 field.
	NVIC_NVICIP26_PRI26_Msk = 0xff // Bit mask of PRI26 field.

	// NVICIP27: Interrupt Priority Register n
	NVIC_NVICIP27_PRI27_Pos = 0x0  // Position of PRI27 field.
	NVIC_NVICIP27_PRI27_Msk = 0xff // Bit mask of PRI27 field.

	// NVICIP28: Interrupt Priority Register n
	NVIC_NVICIP28_PRI28_Pos = 0x0  // Position of PRI28 field.
	NVIC_NVICIP28_PRI28_Msk = 0xff // Bit mask of PRI28 field.

	// NVICIP29: Interrupt Priority Register n
	NVIC_NVICIP29_PRI29_Pos = 0x0  // Position of PRI29 field.
	NVIC_NVICIP29_PRI29_Msk = 0xff // Bit mask of PRI29 field.

	// NVICIP30: Interrupt Priority Register n
	NVIC_NVICIP30_PRI30_Pos = 0x0  // Position of PRI30 field.
	NVIC_NVICIP30_PRI30_Msk = 0xff // Bit mask of PRI30 field.

	// NVICIP31: Interrupt Priority Register n
	NVIC_NVICIP31_PRI31_Pos = 0x0  // Position of PRI31 field.
	NVIC_NVICIP31_PRI31_Msk = 0xff // Bit mask of PRI31 field.

	// NVICIP32: Interrupt Priority Register n
	NVIC_NVICIP32_PRI32_Pos = 0x0  // Position of PRI32 field.
	NVIC_NVICIP32_PRI32_Msk = 0xff // Bit mask of PRI32 field.

	// NVICIP33: Interrupt Priority Register n
	NVIC_NVICIP33_PRI33_Pos = 0x0  // Position of PRI33 field.
	NVIC_NVICIP33_PRI33_Msk = 0xff // Bit mask of PRI33 field.

	// NVICIP34: Interrupt Priority Register n
	NVIC_NVICIP34_PRI34_Pos = 0x0  // Position of PRI34 field.
	NVIC_NVICIP34_PRI34_Msk = 0xff // Bit mask of PRI34 field.

	// NVICIP35: Interrupt Priority Register n
	NVIC_NVICIP35_PRI35_Pos = 0x0  // Position of PRI35 field.
	NVIC_NVICIP35_PRI35_Msk = 0xff // Bit mask of PRI35 field.

	// NVICIP36: Interrupt Priority Register n
	NVIC_NVICIP36_PRI36_Pos = 0x0  // Position of PRI36 field.
	NVIC_NVICIP36_PRI36_Msk = 0xff // Bit mask of PRI36 field.

	// NVICIP37: Interrupt Priority Register n
	NVIC_NVICIP37_PRI37_Pos = 0x0  // Position of PRI37 field.
	NVIC_NVICIP37_PRI37_Msk = 0xff // Bit mask of PRI37 field.

	// NVICIP38: Interrupt Priority Register n
	NVIC_NVICIP38_PRI38_Pos = 0x0  // Position of PRI38 field.
	NVIC_NVICIP38_PRI38_Msk = 0xff // Bit mask of PRI38 field.

	// NVICIP39: Interrupt Priority Register n
	NVIC_NVICIP39_PRI39_Pos = 0x0  // Position of PRI39 field.
	NVIC_NVICIP39_PRI39_Msk = 0xff // Bit mask of PRI39 field.

	// NVICIP40: Interrupt Priority Register n
	NVIC_NVICIP40_PRI40_Pos = 0x0  // Position of PRI40 field.
	NVIC_NVICIP40_PRI40_Msk = 0xff // Bit mask of PRI40 field.

	// NVICIP41: Interrupt Priority Register n
	NVIC_NVICIP41_PRI41_Pos = 0x0  // Position of PRI41 field.
	NVIC_NVICIP41_PRI41_Msk = 0xff // Bit mask of PRI41 field.

	// NVICIP42: Interrupt Priority Register n
	NVIC_NVICIP42_PRI42_Pos = 0x0  // Position of PRI42 field.
	NVIC_NVICIP42_PRI42_Msk = 0xff // Bit mask of PRI42 field.

	// NVICIP43: Interrupt Priority Register n
	NVIC_NVICIP43_PRI43_Pos = 0x0  // Position of PRI43 field.
	NVIC_NVICIP43_PRI43_Msk = 0xff // Bit mask of PRI43 field.

	// NVICIP44: Interrupt Priority Register n
	NVIC_NVICIP44_PRI44_Pos = 0x0  // Position of PRI44 field.
	NVIC_NVICIP44_PRI44_Msk = 0xff // Bit mask of PRI44 field.

	// NVICIP45: Interrupt Priority Register n
	NVIC_NVICIP45_PRI45_Pos = 0x0  // Position of PRI45 field.
	NVIC_NVICIP45_PRI45_Msk = 0xff // Bit mask of PRI45 field.

	// NVICIP46: Interrupt Priority Register n
	NVIC_NVICIP46_PRI46_Pos = 0x0  // Position of PRI46 field.
	NVIC_NVICIP46_PRI46_Msk = 0xff // Bit mask of PRI46 field.

	// NVICIP47: Interrupt Priority Register n
	NVIC_NVICIP47_PRI47_Pos = 0x0  // Position of PRI47 field.
	NVIC_NVICIP47_PRI47_Msk = 0xff // Bit mask of PRI47 field.

	// NVICIP48: Interrupt Priority Register n
	NVIC_NVICIP48_PRI48_Pos = 0x0  // Position of PRI48 field.
	NVIC_NVICIP48_PRI48_Msk = 0xff // Bit mask of PRI48 field.

	// NVICIP49: Interrupt Priority Register n
	NVIC_NVICIP49_PRI49_Pos = 0x0  // Position of PRI49 field.
	NVIC_NVICIP49_PRI49_Msk = 0xff // Bit mask of PRI49 field.

	// NVICIP50: Interrupt Priority Register n
	NVIC_NVICIP50_PRI50_Pos = 0x0  // Position of PRI50 field.
	NVIC_NVICIP50_PRI50_Msk = 0xff // Bit mask of PRI50 field.

	// NVICIP51: Interrupt Priority Register n
	NVIC_NVICIP51_PRI51_Pos = 0x0  // Position of PRI51 field.
	NVIC_NVICIP51_PRI51_Msk = 0xff // Bit mask of PRI51 field.

	// NVICIP52: Interrupt Priority Register n
	NVIC_NVICIP52_PRI52_Pos = 0x0  // Position of PRI52 field.
	NVIC_NVICIP52_PRI52_Msk = 0xff // Bit mask of PRI52 field.

	// NVICIP53: Interrupt Priority Register n
	NVIC_NVICIP53_PRI53_Pos = 0x0  // Position of PRI53 field.
	NVIC_NVICIP53_PRI53_Msk = 0xff // Bit mask of PRI53 field.

	// NVICIP54: Interrupt Priority Register n
	NVIC_NVICIP54_PRI54_Pos = 0x0  // Position of PRI54 field.
	NVIC_NVICIP54_PRI54_Msk = 0xff // Bit mask of PRI54 field.

	// NVICIP55: Interrupt Priority Register n
	NVIC_NVICIP55_PRI55_Pos = 0x0  // Position of PRI55 field.
	NVIC_NVICIP55_PRI55_Msk = 0xff // Bit mask of PRI55 field.

	// NVICIP56: Interrupt Priority Register n
	NVIC_NVICIP56_PRI56_Pos = 0x0  // Position of PRI56 field.
	NVIC_NVICIP56_PRI56_Msk = 0xff // Bit mask of PRI56 field.

	// NVICIP57: Interrupt Priority Register n
	NVIC_NVICIP57_PRI57_Pos = 0x0  // Position of PRI57 field.
	NVIC_NVICIP57_PRI57_Msk = 0xff // Bit mask of PRI57 field.

	// NVICIP58: Interrupt Priority Register n
	NVIC_NVICIP58_PRI58_Pos = 0x0  // Position of PRI58 field.
	NVIC_NVICIP58_PRI58_Msk = 0xff // Bit mask of PRI58 field.

	// NVICIP59: Interrupt Priority Register n
	NVIC_NVICIP59_PRI59_Pos = 0x0  // Position of PRI59 field.
	NVIC_NVICIP59_PRI59_Msk = 0xff // Bit mask of PRI59 field.

	// NVICIP60: Interrupt Priority Register n
	NVIC_NVICIP60_PRI60_Pos = 0x0  // Position of PRI60 field.
	NVIC_NVICIP60_PRI60_Msk = 0xff // Bit mask of PRI60 field.

	// NVICIP61: Interrupt Priority Register n
	NVIC_NVICIP61_PRI61_Pos = 0x0  // Position of PRI61 field.
	NVIC_NVICIP61_PRI61_Msk = 0xff // Bit mask of PRI61 field.

	// NVICIP62: Interrupt Priority Register n
	NVIC_NVICIP62_PRI62_Pos = 0x0  // Position of PRI62 field.
	NVIC_NVICIP62_PRI62_Msk = 0xff // Bit mask of PRI62 field.

	// NVICIP63: Interrupt Priority Register n
	NVIC_NVICIP63_PRI63_Pos = 0x0  // Position of PRI63 field.
	NVIC_NVICIP63_PRI63_Msk = 0xff // Bit mask of PRI63 field.

	// NVICIP64: Interrupt Priority Register n
	NVIC_NVICIP64_PRI64_Pos = 0x0  // Position of PRI64 field.
	NVIC_NVICIP64_PRI64_Msk = 0xff // Bit mask of PRI64 field.

	// NVICIP65: Interrupt Priority Register n
	NVIC_NVICIP65_PRI65_Pos = 0x0  // Position of PRI65 field.
	NVIC_NVICIP65_PRI65_Msk = 0xff // Bit mask of PRI65 field.

	// NVICIP66: Interrupt Priority Register n
	NVIC_NVICIP66_PRI66_Pos = 0x0  // Position of PRI66 field.
	NVIC_NVICIP66_PRI66_Msk = 0xff // Bit mask of PRI66 field.

	// NVICIP67: Interrupt Priority Register n
	NVIC_NVICIP67_PRI67_Pos = 0x0  // Position of PRI67 field.
	NVIC_NVICIP67_PRI67_Msk = 0xff // Bit mask of PRI67 field.

	// NVICIP68: Interrupt Priority Register n
	NVIC_NVICIP68_PRI68_Pos = 0x0  // Position of PRI68 field.
	NVIC_NVICIP68_PRI68_Msk = 0xff // Bit mask of PRI68 field.

	// NVICIP69: Interrupt Priority Register n
	NVIC_NVICIP69_PRI69_Pos = 0x0  // Position of PRI69 field.
	NVIC_NVICIP69_PRI69_Msk = 0xff // Bit mask of PRI69 field.

	// NVICIP70: Interrupt Priority Register n
	NVIC_NVICIP70_PRI70_Pos = 0x0  // Position of PRI70 field.
	NVIC_NVICIP70_PRI70_Msk = 0xff // Bit mask of PRI70 field.

	// NVICIP71: Interrupt Priority Register n
	NVIC_NVICIP71_PRI71_Pos = 0x0  // Position of PRI71 field.
	NVIC_NVICIP71_PRI71_Msk = 0xff // Bit mask of PRI71 field.

	// NVICIP72: Interrupt Priority Register n
	NVIC_NVICIP72_PRI72_Pos = 0x0  // Position of PRI72 field.
	NVIC_NVICIP72_PRI72_Msk = 0xff // Bit mask of PRI72 field.

	// NVICIP73: Interrupt Priority Register n
	NVIC_NVICIP73_PRI73_Pos = 0x0  // Position of PRI73 field.
	NVIC_NVICIP73_PRI73_Msk = 0xff // Bit mask of PRI73 field.

	// NVICIP74: Interrupt Priority Register n
	NVIC_NVICIP74_PRI74_Pos = 0x0  // Position of PRI74 field.
	NVIC_NVICIP74_PRI74_Msk = 0xff // Bit mask of PRI74 field.

	// NVICIP75: Interrupt Priority Register n
	NVIC_NVICIP75_PRI75_Pos = 0x0  // Position of PRI75 field.
	NVIC_NVICIP75_PRI75_Msk = 0xff // Bit mask of PRI75 field.

	// NVICIP76: Interrupt Priority Register n
	NVIC_NVICIP76_PRI76_Pos = 0x0  // Position of PRI76 field.
	NVIC_NVICIP76_PRI76_Msk = 0xff // Bit mask of PRI76 field.

	// NVICIP77: Interrupt Priority Register n
	NVIC_NVICIP77_PRI77_Pos = 0x0  // Position of PRI77 field.
	NVIC_NVICIP77_PRI77_Msk = 0xff // Bit mask of PRI77 field.

	// NVICIP78: Interrupt Priority Register n
	NVIC_NVICIP78_PRI78_Pos = 0x0  // Position of PRI78 field.
	NVIC_NVICIP78_PRI78_Msk = 0xff // Bit mask of PRI78 field.

	// NVICIP79: Interrupt Priority Register n
	NVIC_NVICIP79_PRI79_Pos = 0x0  // Position of PRI79 field.
	NVIC_NVICIP79_PRI79_Msk = 0xff // Bit mask of PRI79 field.

	// NVICIP80: Interrupt Priority Register n
	NVIC_NVICIP80_PRI80_Pos = 0x0  // Position of PRI80 field.
	NVIC_NVICIP80_PRI80_Msk = 0xff // Bit mask of PRI80 field.

	// NVICIP81: Interrupt Priority Register n
	NVIC_NVICIP81_PRI81_Pos = 0x0  // Position of PRI81 field.
	NVIC_NVICIP81_PRI81_Msk = 0xff // Bit mask of PRI81 field.

	// NVICIP82: Interrupt Priority Register n
	NVIC_NVICIP82_PRI82_Pos = 0x0  // Position of PRI82 field.
	NVIC_NVICIP82_PRI82_Msk = 0xff // Bit mask of PRI82 field.

	// NVICIP83: Interrupt Priority Register n
	NVIC_NVICIP83_PRI83_Pos = 0x0  // Position of PRI83 field.
	NVIC_NVICIP83_PRI83_Msk = 0xff // Bit mask of PRI83 field.

	// NVICIP84: Interrupt Priority Register n
	NVIC_NVICIP84_PRI84_Pos = 0x0  // Position of PRI84 field.
	NVIC_NVICIP84_PRI84_Msk = 0xff // Bit mask of PRI84 field.

	// NVICIP85: Interrupt Priority Register n
	NVIC_NVICIP85_PRI85_Pos = 0x0  // Position of PRI85 field.
	NVIC_NVICIP85_PRI85_Msk = 0xff // Bit mask of PRI85 field.

	// NVICIP86: Interrupt Priority Register n
	NVIC_NVICIP86_PRI86_Pos = 0x0  // Position of PRI86 field.
	NVIC_NVICIP86_PRI86_Msk = 0xff // Bit mask of PRI86 field.

	// NVICIP87: Interrupt Priority Register n
	NVIC_NVICIP87_PRI87_Pos = 0x0  // Position of PRI87 field.
	NVIC_NVICIP87_PRI87_Msk = 0xff // Bit mask of PRI87 field.

	// NVICIP88: Interrupt Priority Register n
	NVIC_NVICIP88_PRI88_Pos = 0x0  // Position of PRI88 field.
	NVIC_NVICIP88_PRI88_Msk = 0xff // Bit mask of PRI88 field.

	// NVICIP89: Interrupt Priority Register n
	NVIC_NVICIP89_PRI89_Pos = 0x0  // Position of PRI89 field.
	NVIC_NVICIP89_PRI89_Msk = 0xff // Bit mask of PRI89 field.

	// NVICIP90: Interrupt Priority Register n
	NVIC_NVICIP90_PRI90_Pos = 0x0  // Position of PRI90 field.
	NVIC_NVICIP90_PRI90_Msk = 0xff // Bit mask of PRI90 field.

	// NVICIP91: Interrupt Priority Register n
	NVIC_NVICIP91_PRI91_Pos = 0x0  // Position of PRI91 field.
	NVIC_NVICIP91_PRI91_Msk = 0xff // Bit mask of PRI91 field.

	// NVICIP92: Interrupt Priority Register n
	NVIC_NVICIP92_PRI92_Pos = 0x0  // Position of PRI92 field.
	NVIC_NVICIP92_PRI92_Msk = 0xff // Bit mask of PRI92 field.

	// NVICIP93: Interrupt Priority Register n
	NVIC_NVICIP93_PRI93_Pos = 0x0  // Position of PRI93 field.
	NVIC_NVICIP93_PRI93_Msk = 0xff // Bit mask of PRI93 field.

	// NVICIP94: Interrupt Priority Register n
	NVIC_NVICIP94_PRI94_Pos = 0x0  // Position of PRI94 field.
	NVIC_NVICIP94_PRI94_Msk = 0xff // Bit mask of PRI94 field.

	// NVICIP95: Interrupt Priority Register n
	NVIC_NVICIP95_PRI95_Pos = 0x0  // Position of PRI95 field.
	NVIC_NVICIP95_PRI95_Msk = 0xff // Bit mask of PRI95 field.

	// NVICIP96: Interrupt Priority Register n
	NVIC_NVICIP96_PRI96_Pos = 0x0  // Position of PRI96 field.
	NVIC_NVICIP96_PRI96_Msk = 0xff // Bit mask of PRI96 field.

	// NVICIP97: Interrupt Priority Register n
	NVIC_NVICIP97_PRI97_Pos = 0x0  // Position of PRI97 field.
	NVIC_NVICIP97_PRI97_Msk = 0xff // Bit mask of PRI97 field.

	// NVICIP98: Interrupt Priority Register n
	NVIC_NVICIP98_PRI98_Pos = 0x0  // Position of PRI98 field.
	NVIC_NVICIP98_PRI98_Msk = 0xff // Bit mask of PRI98 field.

	// NVICIP99: Interrupt Priority Register n
	NVIC_NVICIP99_PRI99_Pos = 0x0  // Position of PRI99 field.
	NVIC_NVICIP99_PRI99_Msk = 0xff // Bit mask of PRI99 field.

	// NVICIP100: Interrupt Priority Register n
	NVIC_NVICIP100_PRI100_Pos = 0x0  // Position of PRI100 field.
	NVIC_NVICIP100_PRI100_Msk = 0xff // Bit mask of PRI100 field.

	// NVICIP101: Interrupt Priority Register n
	NVIC_NVICIP101_PRI101_Pos = 0x0  // Position of PRI101 field.
	NVIC_NVICIP101_PRI101_Msk = 0xff // Bit mask of PRI101 field.

	// NVICIP102: Interrupt Priority Register n
	NVIC_NVICIP102_PRI102_Pos = 0x0  // Position of PRI102 field.
	NVIC_NVICIP102_PRI102_Msk = 0xff // Bit mask of PRI102 field.

	// NVICIP103: Interrupt Priority Register n
	NVIC_NVICIP103_PRI103_Pos = 0x0  // Position of PRI103 field.
	NVIC_NVICIP103_PRI103_Msk = 0xff // Bit mask of PRI103 field.

	// NVICIP104: Interrupt Priority Register n
	NVIC_NVICIP104_PRI104_Pos = 0x0  // Position of PRI104 field.
	NVIC_NVICIP104_PRI104_Msk = 0xff // Bit mask of PRI104 field.

	// NVICIP105: Interrupt Priority Register n
	NVIC_NVICIP105_PRI105_Pos = 0x0  // Position of PRI105 field.
	NVIC_NVICIP105_PRI105_Msk = 0xff // Bit mask of PRI105 field.

	// NVICSTIR: Software Trigger Interrupt Register
	NVIC_NVICSTIR_INTID_Pos = 0x0   // Position of INTID field.
	NVIC_NVICSTIR_INTID_Msk = 0x1ff // Bit mask of INTID field.
)

// Bitfields for MCM: Core Platform Miscellaneous Control Module
const (
	// PLASC: Crossbar Switch (AXBS) Slave Configuration
	MCM_PLASC_ASC_Pos = 0x0  // Position of ASC field.
	MCM_PLASC_ASC_Msk = 0xff // Bit mask of ASC field.
	MCM_PLASC_ASC_0   = 0x0  // A bus slave connection to AXBS input port n is absent
	MCM_PLASC_ASC_1   = 0x1  // A bus slave connection to AXBS input port n is present

	// PLAMC: Crossbar Switch (AXBS) Master Configuration
	MCM_PLAMC_AMC_Pos = 0x0  // Position of AMC field.
	MCM_PLAMC_AMC_Msk = 0xff // Bit mask of AMC field.
	MCM_PLAMC_AMC_0   = 0x0  // A bus master connection to AXBS input port n is absent
	MCM_PLAMC_AMC_1   = 0x1  // A bus master connection to AXBS input port n is present

	// PLACR: Crossbar Switch (AXBS) Control Register
	MCM_PLACR_ARB_Pos = 0x9   // Position of ARB field.
	MCM_PLACR_ARB_Msk = 0x200 // Bit mask of ARB field.
	MCM_PLACR_ARB     = 0x200 // Bit ARB.
	MCM_PLACR_ARB_0   = 0x0   // Fixed-priority arbitration for the crossbar masters
	MCM_PLACR_ARB_1   = 0x1   // Round-robin arbitration for the crossbar masters

	// ISCR: Interrupt Status and Control Register
	MCM_ISCR_FIOC_Pos  = 0x8        // Position of FIOC field.
	MCM_ISCR_FIOC_Msk  = 0x100      // Bit mask of FIOC field.
	MCM_ISCR_FIOC      = 0x100      // Bit FIOC.
	MCM_ISCR_FIOC_0    = 0x0        // No interrupt
	MCM_ISCR_FIOC_1    = 0x1        // Interrupt occurred
	MCM_ISCR_FDZC_Pos  = 0x9        // Position of FDZC field.
	MCM_ISCR_FDZC_Msk  = 0x200      // Bit mask of FDZC field.
	MCM_ISCR_FDZC      = 0x200      // Bit FDZC.
	MCM_ISCR_FDZC_0    = 0x0        // No interrupt
	MCM_ISCR_FDZC_1    = 0x1        // Interrupt occurred
	MCM_ISCR_FOFC_Pos  = 0xa        // Position of FOFC field.
	MCM_ISCR_FOFC_Msk  = 0x400      // Bit mask of FOFC field.
	MCM_ISCR_FOFC      = 0x400      // Bit FOFC.
	MCM_ISCR_FOFC_0    = 0x0        // No interrupt
	MCM_ISCR_FOFC_1    = 0x1        // Interrupt occurred
	MCM_ISCR_FUFC_Pos  = 0xb        // Position of FUFC field.
	MCM_ISCR_FUFC_Msk  = 0x800      // Bit mask of FUFC field.
	MCM_ISCR_FUFC      = 0x800      // Bit FUFC.
	MCM_ISCR_FUFC_0    = 0x0        // No interrupt
	MCM_ISCR_FUFC_1    = 0x1        // Interrupt occurred
	MCM_ISCR_FIXC_Pos  = 0xc        // Position of FIXC field.
	MCM_ISCR_FIXC_Msk  = 0x1000     // Bit mask of FIXC field.
	MCM_ISCR_FIXC      = 0x1000     // Bit FIXC.
	MCM_ISCR_FIXC_0    = 0x0        // No interrupt
	MCM_ISCR_FIXC_1    = 0x1        // Interrupt occurred
	MCM_ISCR_FIDC_Pos  = 0xf        // Position of FIDC field.
	MCM_ISCR_FIDC_Msk  = 0x8000     // Bit mask of FIDC field.
	MCM_ISCR_FIDC      = 0x8000     // Bit FIDC.
	MCM_ISCR_FIDC_0    = 0x0        // No interrupt
	MCM_ISCR_FIDC_1    = 0x1        // Interrupt occurred
	MCM_ISCR_FIOCE_Pos = 0x18       // Position of FIOCE field.
	MCM_ISCR_FIOCE_Msk = 0x1000000  // Bit mask of FIOCE field.
	MCM_ISCR_FIOCE     = 0x1000000  // Bit FIOCE.
	MCM_ISCR_FIOCE_0   = 0x0        // Disable interrupt
	MCM_ISCR_FIOCE_1   = 0x1        // Enable interrupt
	MCM_ISCR_FDZCE_Pos = 0x19       // Position of FDZCE field.
	MCM_ISCR_FDZCE_Msk = 0x2000000  // Bit mask of FDZCE field.
	MCM_ISCR_FDZCE     = 0x2000000  // Bit FDZCE.
	MCM_ISCR_FDZCE_0   = 0x0        // Disable interrupt
	MCM_ISCR_FDZCE_1   = 0x1        // Enable interrupt
	MCM_ISCR_FOFCE_Pos = 0x1a       // Position of FOFCE field.
	MCM_ISCR_FOFCE_Msk = 0x4000000  // Bit mask of FOFCE field.
	MCM_ISCR_FOFCE     = 0x4000000  // Bit FOFCE.
	MCM_ISCR_FOFCE_0   = 0x0        // Disable interrupt
	MCM_ISCR_FOFCE_1   = 0x1        // Enable interrupt
	MCM_ISCR_FUFCE_Pos = 0x1b       // Position of FUFCE field.
	MCM_ISCR_FUFCE_Msk = 0x8000000  // Bit mask of FUFCE field.
	MCM_ISCR_FUFCE     = 0x8000000  // Bit FUFCE.
	MCM_ISCR_FUFCE_0   = 0x0        // Disable interrupt
	MCM_ISCR_FUFCE_1   = 0x1        // Enable interrupt
	MCM_ISCR_FIXCE_Pos = 0x1c       // Position of FIXCE field.
	MCM_ISCR_FIXCE_Msk = 0x10000000 // Bit mask of FIXCE field.
	MCM_ISCR_FIXCE     = 0x10000000 // Bit FIXCE.
	MCM_ISCR_FIXCE_0   = 0x0        // Disable interrupt
	MCM_ISCR_FIXCE_1   = 0x1        // Enable interrupt
	MCM_ISCR_FIDCE_Pos = 0x1f       // Position of FIDCE field.
	MCM_ISCR_FIDCE_Msk = 0x80000000 // Bit mask of FIDCE field.
	MCM_ISCR_FIDCE     = 0x80000000 // Bit FIDCE.
	MCM_ISCR_FIDCE_0   = 0x0        // Disable interrupt
	MCM_ISCR_FIDCE_1   = 0x1        // Enable interrupt

	// CPO: Compute Operation Control Register
	MCM_CPO_CPOREQ_Pos = 0x0 // Position of CPOREQ field.
	MCM_CPO_CPOREQ_Msk = 0x1 // Bit mask of CPOREQ field.
	MCM_CPO_CPOREQ     = 0x1 // Bit CPOREQ.
	MCM_CPO_CPOREQ_0   = 0x0 // Request is cleared.
	MCM_CPO_CPOREQ_1   = 0x1 // Request Compute Operation.
	MCM_CPO_CPOACK_Pos = 0x1 // Position of CPOACK field.
	MCM_CPO_CPOACK_Msk = 0x2 // Bit mask of CPOACK field.
	MCM_CPO_CPOACK     = 0x2 // Bit CPOACK.
	MCM_CPO_CPOACK_0   = 0x0 // Compute operation entry has not completed or compute operation exit has completed.
	MCM_CPO_CPOACK_1   = 0x1 // Compute operation entry has completed or compute operation exit has not completed.
	MCM_CPO_CPOWOI_Pos = 0x2 // Position of CPOWOI field.
	MCM_CPO_CPOWOI_Msk = 0x4 // Bit mask of CPOWOI field.
	MCM_CPO_CPOWOI     = 0x4 // Bit CPOWOI.
	MCM_CPO_CPOWOI_0   = 0x0 // No effect.
	MCM_CPO_CPOWOI_1   = 0x1 // When set, the CPOREQ is cleared on any interrupt or exception vector fetch.
)
