// Automatically generated file. DO NOT EDIT.
// Generated by gen-device-svd.go from STM32H753x.svd, see https://github.com/posborne/cmsis-svd/tree/master/data/STMicro

// +build stm32,stm32h753x

// STM32H753x
//

package stm32

import (
	"runtime/interrupt"
	"runtime/volatile"
	"unsafe"
)

// Some information about this device.
const (
	DEVICE = "STM32H753x"
)

// Interrupt numbers.
const (
	IRQ_WWDG1                  = 0   // WWDG
	IRQ_PVD_PVM                = 1   // External interrupt/event controller
	IRQ_RTC_TAMP_STAMP_CSS_LSE = 2   // RTC
	IRQ_RTC_WKUP               = 3   // RTC
	IRQ_FLASH                  = 4   // Flash
	IRQ_RCC                    = 5   // Reset and clock control
	IRQ_EXTI0                  = 6   // External interrupt/event controller
	IRQ_EXTI1                  = 7   // External interrupt/event controller
	IRQ_EXTI2                  = 8   // External interrupt/event controller
	IRQ_EXTI3                  = 9   // External interrupt/event controller
	IRQ_EXTI4                  = 10  // External interrupt/event controller
	IRQ_DMA_STR0               = 11  // DMA controller
	IRQ_DMA_STR1               = 12  // DMA controller
	IRQ_DMA_STR2               = 13  //
	IRQ_DMA_STR3               = 14  //
	IRQ_DMA_STR4               = 15  //
	IRQ_DMA_STR5               = 16  //
	IRQ_DMA_STR6               = 17  //
	IRQ_ADC1_2                 = 18  //
	IRQ_FDCAN1_IT0             = 19  // FDCAN1
	IRQ_FDCAN2_IT0             = 20  //
	IRQ_FDCAN1_IT1             = 21  // FDCAN1
	IRQ_FDCAN2_IT1             = 22  //
	IRQ_EXTI9_5                = 23  // External interrupt/event controller
	IRQ_TIM1_BRK               = 24  // Advanced-timers
	IRQ_TIM1_UP                = 25  // Advanced-timers
	IRQ_TIM1_TRG_COM           = 26  // Advanced-timers
	IRQ_TIM_CC                 = 27  // Advanced-timers
	IRQ_TIM2                   = 28  // General purpose timers
	IRQ_TIM3                   = 29  //
	IRQ_TIM4                   = 30  //
	IRQ_I2C1_EV                = 31  // I2C
	IRQ_I2C1_ER                = 32  // I2C
	IRQ_I2C2_EV                = 33  //
	IRQ_I2C2_ER                = 34  //
	IRQ_SPI1                   = 35  // Serial peripheral interface
	IRQ_SPI2                   = 36  //
	IRQ_USART1                 = 37  //
	IRQ_USART2                 = 38  //
	IRQ_USART3                 = 39  //
	IRQ_EXTI15_10              = 40  // External interrupt/event controller
	IRQ_RTC_ALARM              = 41  // External interrupt/event controller
	IRQ_TIM8_BRK_TIM12         = 43  //
	IRQ_TIM8_UP_TIM13          = 44  //
	IRQ_TIM8_TRG_COM_TIM14     = 45  //
	IRQ_TIM8_CC                = 46  //
	IRQ_DMA1_STR7              = 47  // DMA controller
	IRQ_FMC                    = 48  // FMC
	IRQ_SDMMC1                 = 49  // SDMMC1
	IRQ_TIM5                   = 50  //
	IRQ_SPI3                   = 51  //
	IRQ_UART4                  = 52  //
	IRQ_UART5                  = 53  //
	IRQ_TIM6_DAC               = 54  // Basic timers
	IRQ_TIM7                   = 55  //
	IRQ_DMA2_STR0              = 56  //
	IRQ_DMA2_STR1              = 57  //
	IRQ_DMA2_STR2              = 58  //
	IRQ_DMA2_STR3              = 59  //
	IRQ_DMA2_STR4              = 60  //
	IRQ_ETH                    = 61  // Ethernet: media access control (MAC)
	IRQ_ETH_WKUP               = 62  //
	IRQ_FDCAN_CAL              = 63  // FDCAN1
	IRQ_DMA2_STR5              = 68  //
	IRQ_DMA2_STR6              = 69  //
	IRQ_DMA2_STR7              = 70  //
	IRQ_USART6                 = 71  //
	IRQ_I2C3_EV                = 72  //
	IRQ_I2C3_ER                = 73  //
	IRQ_OTG_HS_EP1_OUT         = 74  //
	IRQ_OTG_HS_EP1_IN          = 75  //
	IRQ_OTG_HS_WKUP            = 76  //
	IRQ_OTG_HS                 = 77  //
	IRQ_DCMI                   = 78  // Digital camera interface
	IRQ_CRYP                   = 79  // Cryptographic processor
	IRQ_HASH_RNG               = 80  // Hash processor
	IRQ_FPU                    = 81  // Floting point unit
	IRQ_UART7                  = 82  //
	IRQ_UART8                  = 83  //
	IRQ_SPI4                   = 84  //
	IRQ_SPI5                   = 85  //
	IRQ_SPI6                   = 86  //
	IRQ_SAI1                   = 87  //
	IRQ_LTDC                   = 88  // LCD-TFT Controller
	IRQ_LTDC_ER                = 89  // LCD-TFT Controller
	IRQ_DMA2D                  = 90  // DMA2D
	IRQ_SAI2                   = 91  //
	IRQ_QUADSPI                = 92  // QUADSPI
	IRQ_LPTIM1                 = 93  // Low power timer
	IRQ_CEC                    = 94  // CEC
	IRQ_I2C4_EV                = 95  //
	IRQ_I2C4_ER                = 96  //
	IRQ_SPDIF                  = 97  // Receiver Interface
	IRQ_OTG_FS_EP1_OUT         = 98  //
	IRQ_OTG_FS_EP1_IN          = 99  //
	IRQ_OTG_FS_WKUP            = 100 //
	IRQ_OTG_FS                 = 101 // USB 1 on the go high speed
	IRQ_DMAMUX1_OV             = 102 // DMAMUX
	IRQ_HRTIM1_MST             = 103 // High Resolution Timer: TIMA
	IRQ_HRTIM1_TIMA            = 104 // High Resolution Timer: TIMB
	IRQ_HRTIM_TIMB             = 105 // High Resolution Timer: TIMC
	IRQ_HRTIM1_TIMC            = 106 // High Resolution Timer: TIMD
	IRQ_HRTIM1_TIMD            = 107 // High Resolution Timer: TIME
	IRQ_HRTIM_TIME             = 108 // High Resolution Timer: Common functions
	IRQ_HRTIM1_FLT             = 109 // High Resolution Timer: TIMA
	IRQ_DFSDM1_FLT0            = 110 // Digital filter for sigma delta modulators
	IRQ_DFSDM1_FLT1            = 111 // Digital filter for sigma delta modulators
	IRQ_DFSDM1_FLT2            = 112 // Digital filter for sigma delta modulators
	IRQ_DFSDM1_FLT3            = 113 // Digital filter for sigma delta modulators
	IRQ_SAI3                   = 114 //
	IRQ_SWPMI1                 = 115 // General purpose timers
	IRQ_TIM15                  = 116 // General purpose timers
	IRQ_TIM16                  = 117 // General-purpose-timers
	IRQ_TIM17                  = 118 // General-purpose-timers
	IRQ_MDIOS_WKUP             = 119 // Management data input/output slave
	IRQ_MDIOS                  = 120 // Management data input/output slave
	IRQ_JPEG                   = 121 // JPEG
	IRQ_MDMA                   = 122 // MDMA
	IRQ_SDMMC                  = 124 // SDMMC1
	IRQ_HSEM0                  = 125 // HSEM
	IRQ_ADC3                   = 127 // Analog to Digital Converter
	IRQ_DMAMUX2_OVR            = 128 // DMAMUX
	IRQ_BDMA_CH1               = 129 // BDMA
	IRQ_BDMA_CH2               = 130 // BDMA
	IRQ_BDMA_CH3               = 131 // BDMA
	IRQ_BDMA_CH4               = 132 // BDMA
	IRQ_BDMA_CH5               = 133 // BDMA
	IRQ_BDMA_CH6               = 134 // BDMA
	IRQ_BDMA_CH7               = 135 // BDMA
	IRQ_BDMA_CH8               = 136 // BDMA
	IRQ_COMP                   = 137 // COMP1
	IRQ_LPTIM2                 = 138 //
	IRQ_LPTIM3                 = 139 // Low power timer
	IRQ_LPTIM4                 = 140 //
	IRQ_LPTIM5                 = 141 //
	IRQ_LPUART                 = 142 // LPUART1
	IRQ_WWDG1_RST              = 143 // WWDG
	IRQ_CRS                    = 144 // CRS
	IRQ_SAI4                   = 146 // SAI
	IRQ_WKUP                   = 149 // DELAY_Block_SDMMC1
	IRQ_max                    = 149 // Highest interrupt number on this device.
)

// Map interrupt numbers to function names.
// These aren't real calls, they're removed by the compiler.
var (
	_ = interrupt.Register(IRQ_WWDG1, "WWDG1_IRQHandler")
	_ = interrupt.Register(IRQ_PVD_PVM, "PVD_PVM_IRQHandler")
	_ = interrupt.Register(IRQ_RTC_TAMP_STAMP_CSS_LSE, "RTC_TAMP_STAMP_CSS_LSE_IRQHandler")
	_ = interrupt.Register(IRQ_RTC_WKUP, "RTC_WKUP_IRQHandler")
	_ = interrupt.Register(IRQ_FLASH, "FLASH_IRQHandler")
	_ = interrupt.Register(IRQ_RCC, "RCC_IRQHandler")
	_ = interrupt.Register(IRQ_EXTI0, "EXTI0_IRQHandler")
	_ = interrupt.Register(IRQ_EXTI1, "EXTI1_IRQHandler")
	_ = interrupt.Register(IRQ_EXTI2, "EXTI2_IRQHandler")
	_ = interrupt.Register(IRQ_EXTI3, "EXTI3_IRQHandler")
	_ = interrupt.Register(IRQ_EXTI4, "EXTI4_IRQHandler")
	_ = interrupt.Register(IRQ_DMA_STR0, "DMA_STR0_IRQHandler")
	_ = interrupt.Register(IRQ_DMA_STR1, "DMA_STR1_IRQHandler")
	_ = interrupt.Register(IRQ_DMA_STR2, "DMA_STR2_IRQHandler")
	_ = interrupt.Register(IRQ_DMA_STR3, "DMA_STR3_IRQHandler")
	_ = interrupt.Register(IRQ_DMA_STR4, "DMA_STR4_IRQHandler")
	_ = interrupt.Register(IRQ_DMA_STR5, "DMA_STR5_IRQHandler")
	_ = interrupt.Register(IRQ_DMA_STR6, "DMA_STR6_IRQHandler")
	_ = interrupt.Register(IRQ_ADC1_2, "ADC1_2_IRQHandler")
	_ = interrupt.Register(IRQ_FDCAN1_IT0, "FDCAN1_IT0_IRQHandler")
	_ = interrupt.Register(IRQ_FDCAN2_IT0, "FDCAN2_IT0_IRQHandler")
	_ = interrupt.Register(IRQ_FDCAN1_IT1, "FDCAN1_IT1_IRQHandler")
	_ = interrupt.Register(IRQ_FDCAN2_IT1, "FDCAN2_IT1_IRQHandler")
	_ = interrupt.Register(IRQ_EXTI9_5, "EXTI9_5_IRQHandler")
	_ = interrupt.Register(IRQ_TIM1_BRK, "TIM1_BRK_IRQHandler")
	_ = interrupt.Register(IRQ_TIM1_UP, "TIM1_UP_IRQHandler")
	_ = interrupt.Register(IRQ_TIM1_TRG_COM, "TIM1_TRG_COM_IRQHandler")
	_ = interrupt.Register(IRQ_TIM_CC, "TIM_CC_IRQHandler")
	_ = interrupt.Register(IRQ_TIM2, "TIM2_IRQHandler")
	_ = interrupt.Register(IRQ_TIM3, "TIM3_IRQHandler")
	_ = interrupt.Register(IRQ_TIM4, "TIM4_IRQHandler")
	_ = interrupt.Register(IRQ_I2C1_EV, "I2C1_EV_IRQHandler")
	_ = interrupt.Register(IRQ_I2C1_ER, "I2C1_ER_IRQHandler")
	_ = interrupt.Register(IRQ_I2C2_EV, "I2C2_EV_IRQHandler")
	_ = interrupt.Register(IRQ_I2C2_ER, "I2C2_ER_IRQHandler")
	_ = interrupt.Register(IRQ_SPI1, "SPI1_IRQHandler")
	_ = interrupt.Register(IRQ_SPI2, "SPI2_IRQHandler")
	_ = interrupt.Register(IRQ_USART1, "USART1_IRQHandler")
	_ = interrupt.Register(IRQ_USART2, "USART2_IRQHandler")
	_ = interrupt.Register(IRQ_USART3, "USART3_IRQHandler")
	_ = interrupt.Register(IRQ_EXTI15_10, "EXTI15_10_IRQHandler")
	_ = interrupt.Register(IRQ_RTC_ALARM, "RTC_ALARM_IRQHandler")
	_ = interrupt.Register(IRQ_TIM8_BRK_TIM12, "TIM8_BRK_TIM12_IRQHandler")
	_ = interrupt.Register(IRQ_TIM8_UP_TIM13, "TIM8_UP_TIM13_IRQHandler")
	_ = interrupt.Register(IRQ_TIM8_TRG_COM_TIM14, "TIM8_TRG_COM_TIM14_IRQHandler")
	_ = interrupt.Register(IRQ_TIM8_CC, "TIM8_CC_IRQHandler")
	_ = interrupt.Register(IRQ_DMA1_STR7, "DMA1_STR7_IRQHandler")
	_ = interrupt.Register(IRQ_FMC, "FMC_IRQHandler")
	_ = interrupt.Register(IRQ_SDMMC1, "SDMMC1_IRQHandler")
	_ = interrupt.Register(IRQ_TIM5, "TIM5_IRQHandler")
	_ = interrupt.Register(IRQ_SPI3, "SPI3_IRQHandler")
	_ = interrupt.Register(IRQ_UART4, "UART4_IRQHandler")
	_ = interrupt.Register(IRQ_UART5, "UART5_IRQHandler")
	_ = interrupt.Register(IRQ_TIM6_DAC, "TIM6_DAC_IRQHandler")
	_ = interrupt.Register(IRQ_TIM7, "TIM7_IRQHandler")
	_ = interrupt.Register(IRQ_DMA2_STR0, "DMA2_STR0_IRQHandler")
	_ = interrupt.Register(IRQ_DMA2_STR1, "DMA2_STR1_IRQHandler")
	_ = interrupt.Register(IRQ_DMA2_STR2, "DMA2_STR2_IRQHandler")
	_ = interrupt.Register(IRQ_DMA2_STR3, "DMA2_STR3_IRQHandler")
	_ = interrupt.Register(IRQ_DMA2_STR4, "DMA2_STR4_IRQHandler")
	_ = interrupt.Register(IRQ_ETH, "ETH_IRQHandler")
	_ = interrupt.Register(IRQ_ETH_WKUP, "ETH_WKUP_IRQHandler")
	_ = interrupt.Register(IRQ_FDCAN_CAL, "FDCAN_CAL_IRQHandler")
	_ = interrupt.Register(IRQ_DMA2_STR5, "DMA2_STR5_IRQHandler")
	_ = interrupt.Register(IRQ_DMA2_STR6, "DMA2_STR6_IRQHandler")
	_ = interrupt.Register(IRQ_DMA2_STR7, "DMA2_STR7_IRQHandler")
	_ = interrupt.Register(IRQ_USART6, "USART6_IRQHandler")
	_ = interrupt.Register(IRQ_I2C3_EV, "I2C3_EV_IRQHandler")
	_ = interrupt.Register(IRQ_I2C3_ER, "I2C3_ER_IRQHandler")
	_ = interrupt.Register(IRQ_OTG_HS_EP1_OUT, "OTG_HS_EP1_OUT_IRQHandler")
	_ = interrupt.Register(IRQ_OTG_HS_EP1_IN, "OTG_HS_EP1_IN_IRQHandler")
	_ = interrupt.Register(IRQ_OTG_HS_WKUP, "OTG_HS_WKUP_IRQHandler")
	_ = interrupt.Register(IRQ_OTG_HS, "OTG_HS_IRQHandler")
	_ = interrupt.Register(IRQ_DCMI, "DCMI_IRQHandler")
	_ = interrupt.Register(IRQ_CRYP, "CRYP_IRQHandler")
	_ = interrupt.Register(IRQ_HASH_RNG, "HASH_RNG_IRQHandler")
	_ = interrupt.Register(IRQ_FPU, "FPU_IRQHandler")
	_ = interrupt.Register(IRQ_UART7, "UART7_IRQHandler")
	_ = interrupt.Register(IRQ_UART8, "UART8_IRQHandler")
	_ = interrupt.Register(IRQ_SPI4, "SPI4_IRQHandler")
	_ = interrupt.Register(IRQ_SPI5, "SPI5_IRQHandler")
	_ = interrupt.Register(IRQ_SPI6, "SPI6_IRQHandler")
	_ = interrupt.Register(IRQ_SAI1, "SAI1_IRQHandler")
	_ = interrupt.Register(IRQ_LTDC, "LTDC_IRQHandler")
	_ = interrupt.Register(IRQ_LTDC_ER, "LTDC_ER_IRQHandler")
	_ = interrupt.Register(IRQ_DMA2D, "DMA2D_IRQHandler")
	_ = interrupt.Register(IRQ_SAI2, "SAI2_IRQHandler")
	_ = interrupt.Register(IRQ_QUADSPI, "QUADSPI_IRQHandler")
	_ = interrupt.Register(IRQ_LPTIM1, "LPTIM1_IRQHandler")
	_ = interrupt.Register(IRQ_CEC, "CEC_IRQHandler")
	_ = interrupt.Register(IRQ_I2C4_EV, "I2C4_EV_IRQHandler")
	_ = interrupt.Register(IRQ_I2C4_ER, "I2C4_ER_IRQHandler")
	_ = interrupt.Register(IRQ_SPDIF, "SPDIF_IRQHandler")
	_ = interrupt.Register(IRQ_OTG_FS_EP1_OUT, "OTG_FS_EP1_OUT_IRQHandler")
	_ = interrupt.Register(IRQ_OTG_FS_EP1_IN, "OTG_FS_EP1_IN_IRQHandler")
	_ = interrupt.Register(IRQ_OTG_FS_WKUP, "OTG_FS_WKUP_IRQHandler")
	_ = interrupt.Register(IRQ_OTG_FS, "OTG_FS_IRQHandler")
	_ = interrupt.Register(IRQ_DMAMUX1_OV, "DMAMUX1_OV_IRQHandler")
	_ = interrupt.Register(IRQ_HRTIM1_MST, "HRTIM1_MST_IRQHandler")
	_ = interrupt.Register(IRQ_HRTIM1_TIMA, "HRTIM1_TIMA_IRQHandler")
	_ = interrupt.Register(IRQ_HRTIM_TIMB, "HRTIM_TIMB_IRQHandler")
	_ = interrupt.Register(IRQ_HRTIM1_TIMC, "HRTIM1_TIMC_IRQHandler")
	_ = interrupt.Register(IRQ_HRTIM1_TIMD, "HRTIM1_TIMD_IRQHandler")
	_ = interrupt.Register(IRQ_HRTIM_TIME, "HRTIM_TIME_IRQHandler")
	_ = interrupt.Register(IRQ_HRTIM1_FLT, "HRTIM1_FLT_IRQHandler")
	_ = interrupt.Register(IRQ_DFSDM1_FLT0, "DFSDM1_FLT0_IRQHandler")
	_ = interrupt.Register(IRQ_DFSDM1_FLT1, "DFSDM1_FLT1_IRQHandler")
	_ = interrupt.Register(IRQ_DFSDM1_FLT2, "DFSDM1_FLT2_IRQHandler")
	_ = interrupt.Register(IRQ_DFSDM1_FLT3, "DFSDM1_FLT3_IRQHandler")
	_ = interrupt.Register(IRQ_SAI3, "SAI3_IRQHandler")
	_ = interrupt.Register(IRQ_SWPMI1, "SWPMI1_IRQHandler")
	_ = interrupt.Register(IRQ_TIM15, "TIM15_IRQHandler")
	_ = interrupt.Register(IRQ_TIM16, "TIM16_IRQHandler")
	_ = interrupt.Register(IRQ_TIM17, "TIM17_IRQHandler")
	_ = interrupt.Register(IRQ_MDIOS_WKUP, "MDIOS_WKUP_IRQHandler")
	_ = interrupt.Register(IRQ_MDIOS, "MDIOS_IRQHandler")
	_ = interrupt.Register(IRQ_JPEG, "JPEG_IRQHandler")
	_ = interrupt.Register(IRQ_MDMA, "MDMA_IRQHandler")
	_ = interrupt.Register(IRQ_SDMMC, "SDMMC_IRQHandler")
	_ = interrupt.Register(IRQ_HSEM0, "HSEM0_IRQHandler")
	_ = interrupt.Register(IRQ_ADC3, "ADC3_IRQHandler")
	_ = interrupt.Register(IRQ_DMAMUX2_OVR, "DMAMUX2_OVR_IRQHandler")
	_ = interrupt.Register(IRQ_BDMA_CH1, "BDMA_CH1_IRQHandler")
	_ = interrupt.Register(IRQ_BDMA_CH2, "BDMA_CH2_IRQHandler")
	_ = interrupt.Register(IRQ_BDMA_CH3, "BDMA_CH3_IRQHandler")
	_ = interrupt.Register(IRQ_BDMA_CH4, "BDMA_CH4_IRQHandler")
	_ = interrupt.Register(IRQ_BDMA_CH5, "BDMA_CH5_IRQHandler")
	_ = interrupt.Register(IRQ_BDMA_CH6, "BDMA_CH6_IRQHandler")
	_ = interrupt.Register(IRQ_BDMA_CH7, "BDMA_CH7_IRQHandler")
	_ = interrupt.Register(IRQ_BDMA_CH8, "BDMA_CH8_IRQHandler")
	_ = interrupt.Register(IRQ_COMP, "COMP_IRQHandler")
	_ = interrupt.Register(IRQ_LPTIM2, "LPTIM2_IRQHandler")
	_ = interrupt.Register(IRQ_LPTIM3, "LPTIM3_IRQHandler")
	_ = interrupt.Register(IRQ_LPTIM4, "LPTIM4_IRQHandler")
	_ = interrupt.Register(IRQ_LPTIM5, "LPTIM5_IRQHandler")
	_ = interrupt.Register(IRQ_LPUART, "LPUART_IRQHandler")
	_ = interrupt.Register(IRQ_WWDG1_RST, "WWDG1_RST_IRQHandler")
	_ = interrupt.Register(IRQ_CRS, "CRS_IRQHandler")
	_ = interrupt.Register(IRQ_SAI4, "SAI4_IRQHandler")
	_ = interrupt.Register(IRQ_WKUP, "WKUP_IRQHandler")
)

// Peripherals.
var (
	COMP1               = (*COMP1_Type)(unsafe.Pointer(uintptr(0x58003800)))      // COMP1
	CRS                 = (*CRS_Type)(unsafe.Pointer(uintptr(0x40008400)))        // CRS
	DAC                 = (*DAC_Type)(unsafe.Pointer(uintptr(0x40007400)))        // DAC
	BDMA                = (*BDMA_Type)(unsafe.Pointer(uintptr(0x58025400)))       // BDMA
	DMA2D               = (*DMA2D_Type)(unsafe.Pointer(uintptr(0x52001000)))      // DMA2D
	DMAMUX2             = (*DMAMUX_Type)(unsafe.Pointer(uintptr(0x58025800)))     // DMAMUX
	FMC                 = (*FMC_Type)(unsafe.Pointer(uintptr(0x52004000)))        // FMC
	CEC                 = (*CEC_Type)(unsafe.Pointer(uintptr(0x40006c00)))        // CEC
	HSEM                = (*HSEM_Type)(unsafe.Pointer(uintptr(0x58026400)))       // HSEM
	I2C1                = (*I2C_Type)(unsafe.Pointer(uintptr(0x40005400)))        // I2C
	GPIOA               = (*GPIO_Type)(unsafe.Pointer(uintptr(0x58020000)))       // GPIO
	JPEG                = (*JPEG_Type)(unsafe.Pointer(uintptr(0x52003000)))       // JPEG
	MDMA                = (*MDMA_Type)(unsafe.Pointer(uintptr(0x52000000)))       // MDMA
	QUADSPI             = (*QUADSPI_Type)(unsafe.Pointer(uintptr(0x52005000)))    // QUADSPI
	RNG                 = (*RNG_Type)(unsafe.Pointer(uintptr(0x48021800)))        // RNG
	RTC                 = (*RTC_Type)(unsafe.Pointer(uintptr(0x58004000)))        // RTC
	SAI4                = (*SAI_Type)(unsafe.Pointer(uintptr(0x58005400)))        // SAI
	SDMMC1              = (*SDMMC_Type)(unsafe.Pointer(uintptr(0x52007000)))      // SDMMC1
	VREFBUF             = (*VREFBUF_Type)(unsafe.Pointer(uintptr(0x58003c00)))    // VREFBUF
	IWDG                = (*IWDG_Type)(unsafe.Pointer(uintptr(0x58004800)))       // IWDG
	WWDG                = (*WWDG_Type)(unsafe.Pointer(uintptr(0x50003000)))       // WWDG
	PWR                 = (*PWR_Type)(unsafe.Pointer(uintptr(0x58024800)))        // PWR
	SPI1                = (*SPI_Type)(unsafe.Pointer(uintptr(0x40013000)))        // Serial peripheral interface
	LTDC                = (*LTDC_Type)(unsafe.Pointer(uintptr(0x50001000)))       // LCD-TFT Controller
	SPDIFRX             = (*SPDIFRX_Type)(unsafe.Pointer(uintptr(0x40004000)))    // Receiver Interface
	ADC3                = (*ADC_Type)(unsafe.Pointer(uintptr(0x58026000)))        // Analog to Digital Converter
	ADC3_Common         = (*ADC_Type)(unsafe.Pointer(uintptr(0x58026300)))        // Analog-to-Digital Converter
	DMAMUX1             = (*DMAMUX_Type)(unsafe.Pointer(uintptr(0x40020800)))     // DMAMUX
	CRC                 = (*CRC_Type)(unsafe.Pointer(uintptr(0x58024c00)))        // Cryptographic processor
	RCC                 = (*RCC_Type)(unsafe.Pointer(uintptr(0x58024400)))        // Reset and clock control
	LPTIM1              = (*LPTIM_Type)(unsafe.Pointer(uintptr(0x40002400)))      // Low power timer
	LPTIM3              = (*LPTIM_Type)(unsafe.Pointer(uintptr(0x58002800)))      // Low power timer
	LPUART1             = (*LPUART_Type)(unsafe.Pointer(uintptr(0x58000c00)))     // LPUART1
	SYSCFG              = (*SYSCFG_Type)(unsafe.Pointer(uintptr(0x58000400)))     // System configuration controller
	EXTI                = (*EXTI_Type)(unsafe.Pointer(uintptr(0x58000000)))       // External interrupt/event controller
	DELAY_Block_SDMMC1  = (*DLYB_Type)(unsafe.Pointer(uintptr(0x52008000)))       // DELAY_Block_SDMMC1
	Flash               = (*Flash_Type)(unsafe.Pointer(uintptr(0x52002000)))      // Flash
	AXI                 = (*AXI_Type)(unsafe.Pointer(uintptr(0x51000000)))        // AXI interconnect registers
	HASH                = (*HASH_Type)(unsafe.Pointer(uintptr(0x48021400)))       // Hash processor
	CRYP                = (*CRYP_Type)(unsafe.Pointer(uintptr(0x48021000)))       // Cryptographic processor
	DCMI                = (*DCMI_Type)(unsafe.Pointer(uintptr(0x48020000)))       // Digital camera interface
	OTG1_HS_GLOBAL      = (*USB_OTG_HS_Type)(unsafe.Pointer(uintptr(0x40040000))) // USB 1 on the go high speed
	OTG1_HS_HOST        = (*USB_OTG_HS_Type)(unsafe.Pointer(uintptr(0x40040400))) // USB 1 on the go high speed
	OTG1_HS_DEVICE      = (*USB_OTG_HS_Type)(unsafe.Pointer(uintptr(0x40040800))) // USB 1 on the go high speed
	OTG1_HS_PWRCLK      = (*USB_OTG_HS_Type)(unsafe.Pointer(uintptr(0x40040e00))) // USB 1 on the go high speed
	Ethernet_DMA        = (*Ethernet_Type)(unsafe.Pointer(uintptr(0x40029000)))   // Ethernet: DMA mode register (DMA)
	Ethernet_MTL        = (*Ethernet_Type)(unsafe.Pointer(uintptr(0x40028c00)))   // Ethernet: MTL mode register (MTL)
	Ethernet_MAC        = (*Ethernet_Type)(unsafe.Pointer(uintptr(0x40028000)))   // Ethernet: media access control (MAC)
	DMA1                = (*DMA_Type)(unsafe.Pointer(uintptr(0x40020000)))        // DMA controller
	HRTIM_Master        = (*HRTIM_Type)(unsafe.Pointer(uintptr(0x40017400)))      // High Resolution Timer: Master Timers
	HRTIM_TIMA          = (*HRTIM_Type)(unsafe.Pointer(uintptr(0x40017480)))      // High Resolution Timer: TIMA
	HRTIM_TIMB          = (*HRTIM_Type)(unsafe.Pointer(uintptr(0x40017500)))      // High Resolution Timer: TIMB
	HRTIM_TIMC          = (*HRTIM_Type)(unsafe.Pointer(uintptr(0x40017580)))      // High Resolution Timer: TIMC
	HRTIM_TIMD          = (*HRTIM_Type)(unsafe.Pointer(uintptr(0x40017600)))      // High Resolution Timer: TIMD
	HRTIM_TIME          = (*HRTIM_Type)(unsafe.Pointer(uintptr(0x40017680)))      // High Resolution Timer: TIME
	HRTIM_Common        = (*HRTIM_Type)(unsafe.Pointer(uintptr(0x40017780)))      // High Resolution Timer: Common functions
	DFSDM               = (*DFSDM_Type)(unsafe.Pointer(uintptr(0x40017000)))      // Digital filter for sigma delta modulators
	TIM16               = (*TIMs_Type)(unsafe.Pointer(uintptr(0x40014400)))       // General-purpose-timers
	TIM17               = (*TIMs_Type)(unsafe.Pointer(uintptr(0x40014800)))       // General-purpose-timers
	TIM15               = (*TIMs_Type)(unsafe.Pointer(uintptr(0x40014000)))       // General purpose timers
	USART1              = (*USART_Type)(unsafe.Pointer(uintptr(0x40011000)))      // Universal synchronous asynchronous receiver transmitter
	TIM1                = (*TIM_Type)(unsafe.Pointer(uintptr(0x40010000)))        // Advanced-timers
	FDCAN1              = (*FDCAN_Type)(unsafe.Pointer(uintptr(0x4000a000)))      // FDCAN1
	CAN_CCU             = (*FDCAN_Type)(unsafe.Pointer(uintptr(0x4000a800)))      // CCU registers
	MDIOS               = (*MDIOS_Type)(unsafe.Pointer(uintptr(0x40009400)))      // Management data input/output slave
	OPAMP               = (*OPAMP_Type)(unsafe.Pointer(uintptr(0x40009000)))      // Operational amplifiers
	SWPMI               = (*SWPMI_Type)(unsafe.Pointer(uintptr(0x40008800)))      // Single Wire Protocol Master Interface
	TIM2                = (*TIM_Type)(unsafe.Pointer(uintptr(0x40000000)))        // General purpose timers
	TIM6                = (*TIM_Type)(unsafe.Pointer(uintptr(0x40001000)))        // Basic timers
	NVIC                = (*NVIC_Type)(unsafe.Pointer(uintptr(0xe000e100)))       // Nested Vectored Interrupt Controller
	MPU                 = (*MPU_Type)(unsafe.Pointer(uintptr(0xe000ed90)))        // Memory protection unit
	STK                 = (*STK_Type)(unsafe.Pointer(uintptr(0xe000e010)))        // SysTick timer
	NVIC_STIR           = (*NVIC_Type)(unsafe.Pointer(uintptr(0xe000ef00)))       // Nested vectored interrupt controller
	FPU_CPACR           = (*FPU_Type)(unsafe.Pointer(uintptr(0xe000ed88)))        // Floating point unit CPACR
	SCB_ACTRL           = (*SCB_Type)(unsafe.Pointer(uintptr(0xe000e008)))        // System control block ACTLR
	FPU                 = (*FPU_Type)(unsafe.Pointer(uintptr(0xe000ef34)))        // Floting point unit
	SCB                 = (*SCB_Type)(unsafe.Pointer(uintptr(0xe000ed00)))        // System control block
	PF                  = (*PF_Type)(unsafe.Pointer(uintptr(0xe000ed78)))         // Processor features
	AC                  = (*AC_Type)(unsafe.Pointer(uintptr(0xe000ef90)))         // Access control
	I2C2                = (*I2C_Type)(unsafe.Pointer(uintptr(0x40005800)))        // I2C
	I2C3                = (*I2C_Type)(unsafe.Pointer(uintptr(0x40005c00)))        // I2C
	I2C4                = (*I2C_Type)(unsafe.Pointer(uintptr(0x58001c00)))        // I2C
	GPIOB               = (*GPIO_Type)(unsafe.Pointer(uintptr(0x58020400)))       // GPIO
	GPIOC               = (*GPIO_Type)(unsafe.Pointer(uintptr(0x58020800)))       // GPIO
	GPIOD               = (*GPIO_Type)(unsafe.Pointer(uintptr(0x58020c00)))       // GPIO
	GPIOE               = (*GPIO_Type)(unsafe.Pointer(uintptr(0x58021000)))       // GPIO
	GPIOF               = (*GPIO_Type)(unsafe.Pointer(uintptr(0x58021400)))       // GPIO
	GPIOG               = (*GPIO_Type)(unsafe.Pointer(uintptr(0x58021800)))       // GPIO
	GPIOH               = (*GPIO_Type)(unsafe.Pointer(uintptr(0x58021c00)))       // GPIO
	GPIOI               = (*GPIO_Type)(unsafe.Pointer(uintptr(0x58022000)))       // GPIO
	GPIOJ               = (*GPIO_Type)(unsafe.Pointer(uintptr(0x58022400)))       // GPIO
	GPIOK               = (*GPIO_Type)(unsafe.Pointer(uintptr(0x58022800)))       // GPIO
	SAI1                = (*SAI_Type)(unsafe.Pointer(uintptr(0x40015800)))        // SAI
	SAI2                = (*SAI_Type)(unsafe.Pointer(uintptr(0x40015c00)))        // SAI
	SAI3                = (*SAI_Type)(unsafe.Pointer(uintptr(0x40016000)))        // SAI
	SDMMC2              = (*SDMMC_Type)(unsafe.Pointer(uintptr(0x48022400)))      // SDMMC1
	SPI2                = (*SPI_Type)(unsafe.Pointer(uintptr(0x40003800)))        // Serial peripheral interface
	SPI3                = (*SPI_Type)(unsafe.Pointer(uintptr(0x40003c00)))        // Serial peripheral interface
	SPI4                = (*SPI_Type)(unsafe.Pointer(uintptr(0x40013400)))        // Serial peripheral interface
	SPI5                = (*SPI_Type)(unsafe.Pointer(uintptr(0x40015000)))        // Serial peripheral interface
	SPI6                = (*SPI_Type)(unsafe.Pointer(uintptr(0x58001400)))        // Serial peripheral interface
	ADC1                = (*ADC_Type)(unsafe.Pointer(uintptr(0x40022000)))        // Analog to Digital Converter
	ADC2                = (*ADC_Type)(unsafe.Pointer(uintptr(0x40022100)))        // Analog to Digital Converter
	ADC12_Common        = (*ADC_Type)(unsafe.Pointer(uintptr(0x40022300)))        // Analog-to-Digital Converter
	LPTIM2              = (*LPTIM_Type)(unsafe.Pointer(uintptr(0x58002400)))      // Low power timer
	LPTIM4              = (*LPTIM_Type)(unsafe.Pointer(uintptr(0x58002c00)))      // Low power timer
	LPTIM5              = (*LPTIM_Type)(unsafe.Pointer(uintptr(0x58003000)))      // Low power timer
	DELAY_Block_QUADSPI = (*DLYB_Type)(unsafe.Pointer(uintptr(0x52006000)))       // DELAY_Block_SDMMC1
	DELAY_Block_SDMMC2  = (*DLYB_Type)(unsafe.Pointer(uintptr(0x48022800)))       // DELAY_Block_SDMMC1
	OTG2_HS_GLOBAL      = (*USB_OTG_HS_Type)(unsafe.Pointer(uintptr(0x40080000))) // USB 1 on the go high speed
	OTG2_HS_HOST        = (*USB_OTG_HS_Type)(unsafe.Pointer(uintptr(0x40080400))) // USB 1 on the go high speed
	OTG2_HS_DEVICE      = (*USB_OTG_HS_Type)(unsafe.Pointer(uintptr(0x40080800))) // USB 1 on the go high speed
	OTG2_HS_PWRCLK      = (*USB_OTG_HS_Type)(unsafe.Pointer(uintptr(0x40080e00))) // USB 1 on the go high speed
	DMA2                = (*DMA_Type)(unsafe.Pointer(uintptr(0x40020400)))        // DMA controller
	USART2              = (*USART_Type)(unsafe.Pointer(uintptr(0x40004400)))      // Universal synchronous asynchronous receiver transmitter
	USART3              = (*USART_Type)(unsafe.Pointer(uintptr(0x40004800)))      // Universal synchronous asynchronous receiver transmitter
	UART4               = (*USART_Type)(unsafe.Pointer(uintptr(0x40004c00)))      // Universal synchronous asynchronous receiver transmitter
	UART5               = (*USART_Type)(unsafe.Pointer(uintptr(0x40005000)))      // Universal synchronous asynchronous receiver transmitter
	USART6              = (*USART_Type)(unsafe.Pointer(uintptr(0x40011400)))      // Universal synchronous asynchronous receiver transmitter
	UART7               = (*USART_Type)(unsafe.Pointer(uintptr(0x40007800)))      // Universal synchronous asynchronous receiver transmitter
	UART8               = (*USART_Type)(unsafe.Pointer(uintptr(0x40007c00)))      // Universal synchronous asynchronous receiver transmitter
	TIM8                = (*TIM_Type)(unsafe.Pointer(uintptr(0x40010400)))        // Advanced-timers
	FDCAN2              = (*FDCAN_Type)(unsafe.Pointer(uintptr(0x4000a400)))      // FDCAN1
	TIM3                = (*TIM_Type)(unsafe.Pointer(uintptr(0x40000400)))        // General purpose timers
	TIM4                = (*TIM_Type)(unsafe.Pointer(uintptr(0x40000800)))        // General purpose timers
	TIM5                = (*TIM_Type)(unsafe.Pointer(uintptr(0x40000c00)))        // General purpose timers
	TIM12               = (*TIM_Type)(unsafe.Pointer(uintptr(0x40001800)))        // General purpose timers
	TIM13               = (*TIM_Type)(unsafe.Pointer(uintptr(0x40001c00)))        // General purpose timers
	TIM14               = (*TIM_Type)(unsafe.Pointer(uintptr(0x40002000)))        // General purpose timers
	TIM7                = (*TIM_Type)(unsafe.Pointer(uintptr(0x40001400)))        // Basic timers
)

// COMP1
type COMP1_Type struct {
	SR    volatile.Register32 // 0x0
	ICFR  volatile.Register32 // 0x4
	OR    volatile.Register32 // 0x8
	CFGR1 volatile.Register32 // 0xC
	CFGR2 volatile.Register32 // 0x10
}

// CRS
type CRS_Type struct {
	CR   volatile.Register32 // 0x0
	CFGR volatile.Register32 // 0x4
	ISR  volatile.Register32 // 0x8
	ICR  volatile.Register32 // 0xC
}

// DAC
type DAC_Type struct {
	CR      volatile.Register32 // 0x0
	SWTRGR  volatile.Register32 // 0x4
	DHR12R1 volatile.Register32 // 0x8
	DHR12L1 volatile.Register32 // 0xC
	DHR8R1  volatile.Register32 // 0x10
	DHR12R2 volatile.Register32 // 0x14
	DHR12L2 volatile.Register32 // 0x18
	DHR8R2  volatile.Register32 // 0x1C
	DHR12RD volatile.Register32 // 0x20
	DHR12LD volatile.Register32 // 0x24
	DHR8RD  volatile.Register32 // 0x28
	DOR1    volatile.Register32 // 0x2C
	DOR2    volatile.Register32 // 0x30
	SR      volatile.Register32 // 0x34
	CCR     volatile.Register32 // 0x38
	MCR     volatile.Register32 // 0x3C
	SHSR1   volatile.Register32 // 0x40
	SHSR2   volatile.Register32 // 0x44
	SHHR    volatile.Register32 // 0x48
	SHRR    volatile.Register32 // 0x4C
}

// BDMA
type BDMA_Type struct {
	ISR    volatile.Register32 // 0x0
	IFCR   volatile.Register32 // 0x4
	CCR1   volatile.Register32 // 0x8
	CNDTR1 volatile.Register32 // 0xC
	CPAR1  volatile.Register32 // 0x10
	CMAR1  volatile.Register32 // 0x14
	_      [4]byte
	CCR2   volatile.Register32 // 0x1C
	CNDTR2 volatile.Register32 // 0x20
	CPAR2  volatile.Register32 // 0x24
	CMAR2  volatile.Register32 // 0x28
	_      [4]byte
	CCR3   volatile.Register32 // 0x30
	CNDTR3 volatile.Register32 // 0x34
	CPAR3  volatile.Register32 // 0x38
	CMAR3  volatile.Register32 // 0x3C
	_      [4]byte
	CCR4   volatile.Register32 // 0x44
	CNDTR4 volatile.Register32 // 0x48
	CPAR4  volatile.Register32 // 0x4C
	CMAR4  volatile.Register32 // 0x50
	_      [4]byte
	CCR5   volatile.Register32 // 0x58
	CNDTR5 volatile.Register32 // 0x5C
	CPAR5  volatile.Register32 // 0x60
	CMAR5  volatile.Register32 // 0x64
	_      [4]byte
	CCR6   volatile.Register32 // 0x6C
	CNDTR6 volatile.Register32 // 0x70
	CPAR6  volatile.Register32 // 0x74
	CMAR6  volatile.Register32 // 0x78
	_      [4]byte
	CCR7   volatile.Register32 // 0x80
	CNDTR7 volatile.Register32 // 0x84
	CPAR7  volatile.Register32 // 0x88
	CMAR7  volatile.Register32 // 0x8C
	_      [4]byte
	CCR8   volatile.Register32 // 0x94
	CNDTR8 volatile.Register32 // 0x98
	CPAR8  volatile.Register32 // 0x9C
	CMAR8  volatile.Register32 // 0xA0
}

// DMA2D
type DMA2D_Type struct {
	CR      volatile.Register32 // 0x0
	ISR     volatile.Register32 // 0x4
	IFCR    volatile.Register32 // 0x8
	FGMAR   volatile.Register32 // 0xC
	FGOR    volatile.Register32 // 0x10
	BGMAR   volatile.Register32 // 0x14
	BGOR    volatile.Register32 // 0x18
	FGPFCCR volatile.Register32 // 0x1C
	FGCOLR  volatile.Register32 // 0x20
	BGPFCCR volatile.Register32 // 0x24
	BGCOLR  volatile.Register32 // 0x28
	FGCMAR  volatile.Register32 // 0x2C
	BGCMAR  volatile.Register32 // 0x30
	OPFCCR  volatile.Register32 // 0x34
	OCOLR   volatile.Register32 // 0x38
	OMAR    volatile.Register32 // 0x3C
	OOR     volatile.Register32 // 0x40
	NLR     volatile.Register32 // 0x44
	LWR     volatile.Register32 // 0x48
	AMTCR   volatile.Register32 // 0x4C
}

// DMAMUX
type DMAMUX_Type struct {
	C0CR  volatile.Register32 // 0x0
	C1CR  volatile.Register32 // 0x4
	C2CR  volatile.Register32 // 0x8
	C3CR  volatile.Register32 // 0xC
	C4CR  volatile.Register32 // 0x10
	C5CR  volatile.Register32 // 0x14
	C6CR  volatile.Register32 // 0x18
	C7CR  volatile.Register32 // 0x1C
	_     [96]byte
	CSR   volatile.Register32 // 0x80
	CFR   volatile.Register32 // 0x84
	_     [120]byte
	RG0CR volatile.Register32 // 0x100
	RG1CR volatile.Register32 // 0x104
	RG2CR volatile.Register32 // 0x108
	RG3CR volatile.Register32 // 0x10C
	RG4CR volatile.Register32 // 0x110
	RG5CR volatile.Register32 // 0x114
	RG6CR volatile.Register32 // 0x118
	RG7CR volatile.Register32 // 0x11C
	_     [32]byte
	RGSR  volatile.Register32 // 0x140
	RGCFR volatile.Register32 // 0x144
}

// FMC
type FMC_Type struct {
	BCR1  volatile.Register32 // 0x0
	BTR1  volatile.Register32 // 0x4
	BCR2  volatile.Register32 // 0x8
	BTR2  volatile.Register32 // 0xC
	BCR3  volatile.Register32 // 0x10
	BTR3  volatile.Register32 // 0x14
	BCR4  volatile.Register32 // 0x18
	BTR4  volatile.Register32 // 0x1C
	_     [96]byte
	PCR   volatile.Register32 // 0x80
	SR    volatile.Register32 // 0x84
	PMEM  volatile.Register32 // 0x88
	PATT  volatile.Register32 // 0x8C
	_     [4]byte
	ECCR  volatile.Register32 // 0x94
	_     [108]byte
	BWTR1 volatile.Register32 // 0x104
	_     [4]byte
	BWTR2 volatile.Register32 // 0x10C
	_     [4]byte
	BWTR3 volatile.Register32 // 0x114
	_     [4]byte
	BWTR4 volatile.Register32 // 0x11C
	_     [32]byte
	SDCR1 volatile.Register32 // 0x140
	SDCR2 volatile.Register32 // 0x144
	SDTR1 volatile.Register32 // 0x148
	SDTR2 volatile.Register32 // 0x14C
	SDCMR volatile.Register32 // 0x150
	SDRTR volatile.Register32 // 0x154
	SDSR  volatile.Register32 // 0x158
}

// CEC
type CEC_Type struct {
	CR   volatile.Register32 // 0x0
	CFGR volatile.Register32 // 0x4
	TXDR volatile.Register32 // 0x8
	RXDR volatile.Register32 // 0xC
	ISR  volatile.Register32 // 0x10
	IER  volatile.Register32 // 0x14
}

// HSEM
type HSEM_Type struct {
	HSEM_R0    volatile.Register32 // 0x0
	HSEM_R1    volatile.Register32 // 0x4
	HSEM_R2    volatile.Register32 // 0x8
	HSEM_R3    volatile.Register32 // 0xC
	HSEM_R4    volatile.Register32 // 0x10
	HSEM_R5    volatile.Register32 // 0x14
	HSEM_R6    volatile.Register32 // 0x18
	HSEM_R7    volatile.Register32 // 0x1C
	HSEM_R8    volatile.Register32 // 0x20
	HSEM_R9    volatile.Register32 // 0x24
	HSEM_R10   volatile.Register32 // 0x28
	HSEM_R11   volatile.Register32 // 0x2C
	HSEM_R12   volatile.Register32 // 0x30
	HSEM_R13   volatile.Register32 // 0x34
	HSEM_R14   volatile.Register32 // 0x38
	HSEM_R15   volatile.Register32 // 0x3C
	HSEM_R16   volatile.Register32 // 0x40
	HSEM_R17   volatile.Register32 // 0x44
	HSEM_R18   volatile.Register32 // 0x48
	HSEM_R19   volatile.Register32 // 0x4C
	HSEM_R20   volatile.Register32 // 0x50
	HSEM_R21   volatile.Register32 // 0x54
	HSEM_R22   volatile.Register32 // 0x58
	HSEM_R23   volatile.Register32 // 0x5C
	HSEM_R24   volatile.Register32 // 0x60
	HSEM_R25   volatile.Register32 // 0x64
	HSEM_R26   volatile.Register32 // 0x68
	HSEM_R27   volatile.Register32 // 0x6C
	HSEM_R28   volatile.Register32 // 0x70
	HSEM_R29   volatile.Register32 // 0x74
	HSEM_R30   volatile.Register32 // 0x78
	HSEM_R31   volatile.Register32 // 0x7C
	HSEM_RLR0  volatile.Register32 // 0x80
	HSEM_RLR1  volatile.Register32 // 0x84
	HSEM_RLR2  volatile.Register32 // 0x88
	HSEM_RLR3  volatile.Register32 // 0x8C
	HSEM_RLR4  volatile.Register32 // 0x90
	HSEM_RLR5  volatile.Register32 // 0x94
	HSEM_RLR6  volatile.Register32 // 0x98
	HSEM_RLR7  volatile.Register32 // 0x9C
	HSEM_RLR8  volatile.Register32 // 0xA0
	HSEM_RLR9  volatile.Register32 // 0xA4
	HSEM_RLR10 volatile.Register32 // 0xA8
	HSEM_RLR11 volatile.Register32 // 0xAC
	HSEM_RLR12 volatile.Register32 // 0xB0
	HSEM_RLR13 volatile.Register32 // 0xB4
	HSEM_RLR14 volatile.Register32 // 0xB8
	HSEM_RLR15 volatile.Register32 // 0xBC
	HSEM_RLR16 volatile.Register32 // 0xC0
	HSEM_RLR17 volatile.Register32 // 0xC4
	HSEM_RLR18 volatile.Register32 // 0xC8
	HSEM_RLR19 volatile.Register32 // 0xCC
	HSEM_RLR20 volatile.Register32 // 0xD0
	HSEM_RLR21 volatile.Register32 // 0xD4
	HSEM_RLR22 volatile.Register32 // 0xD8
	HSEM_RLR23 volatile.Register32 // 0xDC
	HSEM_RLR24 volatile.Register32 // 0xE0
	HSEM_RLR25 volatile.Register32 // 0xE4
	HSEM_RLR26 volatile.Register32 // 0xE8
	HSEM_RLR27 volatile.Register32 // 0xEC
	HSEM_RLR28 volatile.Register32 // 0xF0
	HSEM_RLR29 volatile.Register32 // 0xF4
	HSEM_RLR30 volatile.Register32 // 0xF8
	HSEM_RLR31 volatile.Register32 // 0xFC
	HSEM_IER   volatile.Register32 // 0x100
	HSEM_ICR   volatile.Register32 // 0x104
	HSEM_ISR   volatile.Register32 // 0x108
	HSEM_MISR  volatile.Register32 // 0x10C
	_          [48]byte
	HSEM_CR    volatile.Register32 // 0x140
	HSEM_KEYR  volatile.Register32 // 0x144
}

// I2C
type I2C_Type struct {
	CR1      volatile.Register32 // 0x0
	CR2      volatile.Register32 // 0x4
	OAR1     volatile.Register32 // 0x8
	OAR2     volatile.Register32 // 0xC
	TIMINGR  volatile.Register32 // 0x10
	TIMEOUTR volatile.Register32 // 0x14
	ISR      volatile.Register32 // 0x18
	ICR      volatile.Register32 // 0x1C
	PECR     volatile.Register32 // 0x20
	RXDR     volatile.Register32 // 0x24
	TXDR     volatile.Register32 // 0x28
}

// GPIO
type GPIO_Type struct {
	MODER   volatile.Register32 // 0x0
	OTYPER  volatile.Register32 // 0x4
	OSPEEDR volatile.Register32 // 0x8
	PUPDR   volatile.Register32 // 0xC
	IDR     volatile.Register32 // 0x10
	ODR     volatile.Register32 // 0x14
	BSRR    volatile.Register32 // 0x18
	LCKR    volatile.Register32 // 0x1C
	AFRL    volatile.Register32 // 0x20
	AFRH    volatile.Register32 // 0x24
}

// JPEG
type JPEG_Type struct {
	CONFR0  volatile.Register32 // 0x0
	CONFR1  volatile.Register32 // 0x4
	CONFR2  volatile.Register32 // 0x8
	CONFR3  volatile.Register32 // 0xC
	CONFRN1 volatile.Register32 // 0x10
	CONFRN2 volatile.Register32 // 0x14
	CONFRN3 volatile.Register32 // 0x18
	CONFRN4 volatile.Register32 // 0x1C
	_       [16]byte
	CR      volatile.Register32 // 0x30
	SR      volatile.Register32 // 0x34
	CFR     volatile.Register32 // 0x38
	_       [4]byte
	DIR     volatile.Register32 // 0x40
	DOR     volatile.Register32 // 0x44
}

// MDMA
type MDMA_Type struct {
	MDMA_GISR0    volatile.Register32 // 0x0
	_             [60]byte
	MDMA_C0ISR    volatile.Register32 // 0x40
	MDMA_C0IFCR   volatile.Register32 // 0x44
	MDMA_C0ESR    volatile.Register32 // 0x48
	MDMA_C0CR     volatile.Register32 // 0x4C
	MDMA_C0TCR    volatile.Register32 // 0x50
	MDMA_C0BNDTR  volatile.Register32 // 0x54
	MDMA_C0SAR    volatile.Register32 // 0x58
	MDMA_C0DAR    volatile.Register32 // 0x5C
	MDMA_C0BRUR   volatile.Register32 // 0x60
	MDMA_C0LAR    volatile.Register32 // 0x64
	MDMA_C0TBR    volatile.Register32 // 0x68
	_             [4]byte
	MDMA_C0MAR    volatile.Register32 // 0x70
	MDMA_C0MDR    volatile.Register32 // 0x74
	_             [8]byte
	MDMA_C1ISR    volatile.Register32 // 0x80
	MDMA_C1IFCR   volatile.Register32 // 0x84
	MDMA_C1ESR    volatile.Register32 // 0x88
	MDMA_C1CR     volatile.Register32 // 0x8C
	MDMA_C1TCR    volatile.Register32 // 0x90
	MDMA_C1BNDTR  volatile.Register32 // 0x94
	MDMA_C1SAR    volatile.Register32 // 0x98
	MDMA_C1DAR    volatile.Register32 // 0x9C
	MDMA_C1BRUR   volatile.Register32 // 0xA0
	MDMA_C1LAR    volatile.Register32 // 0xA4
	MDMA_C1TBR    volatile.Register32 // 0xA8
	_             [4]byte
	MDMA_C1MAR    volatile.Register32 // 0xB0
	MDMA_C1MDR    volatile.Register32 // 0xB4
	_             [8]byte
	MDMA_C2ISR    volatile.Register32 // 0xC0
	MDMA_C2IFCR   volatile.Register32 // 0xC4
	MDMA_C2ESR    volatile.Register32 // 0xC8
	MDMA_C2CR     volatile.Register32 // 0xCC
	MDMA_C2TCR    volatile.Register32 // 0xD0
	MDMA_C2BNDTR  volatile.Register32 // 0xD4
	MDMA_C2SAR    volatile.Register32 // 0xD8
	MDMA_C2DAR    volatile.Register32 // 0xDC
	MDMA_C2BRUR   volatile.Register32 // 0xE0
	MDMA_C2LAR    volatile.Register32 // 0xE4
	MDMA_C2TBR    volatile.Register32 // 0xE8
	_             [4]byte
	MDMA_C2MAR    volatile.Register32 // 0xF0
	MDMA_C2MDR    volatile.Register32 // 0xF4
	_             [8]byte
	MDMA_C3ISR    volatile.Register32 // 0x100
	MDMA_C3IFCR   volatile.Register32 // 0x104
	MDMA_C3ESR    volatile.Register32 // 0x108
	MDMA_C3CR     volatile.Register32 // 0x10C
	MDMA_C3TCR    volatile.Register32 // 0x110
	MDMA_C3BNDTR  volatile.Register32 // 0x114
	MDMA_C3SAR    volatile.Register32 // 0x118
	MDMA_C3DAR    volatile.Register32 // 0x11C
	MDMA_C3BRUR   volatile.Register32 // 0x120
	MDMA_C3LAR    volatile.Register32 // 0x124
	MDMA_C3TBR    volatile.Register32 // 0x128
	_             [4]byte
	MDMA_C3MAR    volatile.Register32 // 0x130
	MDMA_C3MDR    volatile.Register32 // 0x134
	_             [8]byte
	MDMA_C4ISR    volatile.Register32 // 0x140
	MDMA_C4IFCR   volatile.Register32 // 0x144
	MDMA_C4ESR    volatile.Register32 // 0x148
	MDMA_C4CR     volatile.Register32 // 0x14C
	MDMA_C4TCR    volatile.Register32 // 0x150
	MDMA_C4BNDTR  volatile.Register32 // 0x154
	MDMA_C4SAR    volatile.Register32 // 0x158
	MDMA_C4DAR    volatile.Register32 // 0x15C
	MDMA_C4BRUR   volatile.Register32 // 0x160
	MDMA_C4LAR    volatile.Register32 // 0x164
	MDMA_C4TBR    volatile.Register32 // 0x168
	_             [4]byte
	MDMA_C4MAR    volatile.Register32 // 0x170
	MDMA_C4MDR    volatile.Register32 // 0x174
	_             [8]byte
	MDMA_C5ISR    volatile.Register32 // 0x180
	MDMA_C5IFCR   volatile.Register32 // 0x184
	MDMA_C5ESR    volatile.Register32 // 0x188
	MDMA_C5CR     volatile.Register32 // 0x18C
	MDMA_C5TCR    volatile.Register32 // 0x190
	MDMA_C5BNDTR  volatile.Register32 // 0x194
	MDMA_C5SAR    volatile.Register32 // 0x198
	MDMA_C5DAR    volatile.Register32 // 0x19C
	MDMA_C5BRUR   volatile.Register32 // 0x1A0
	MDMA_C5LAR    volatile.Register32 // 0x1A4
	MDMA_C5TBR    volatile.Register32 // 0x1A8
	_             [4]byte
	MDMA_C5MAR    volatile.Register32 // 0x1B0
	MDMA_C5MDR    volatile.Register32 // 0x1B4
	_             [8]byte
	MDMA_C6ISR    volatile.Register32 // 0x1C0
	MDMA_C6IFCR   volatile.Register32 // 0x1C4
	MDMA_C6ESR    volatile.Register32 // 0x1C8
	MDMA_C6CR     volatile.Register32 // 0x1CC
	MDMA_C6TCR    volatile.Register32 // 0x1D0
	MDMA_C6BNDTR  volatile.Register32 // 0x1D4
	MDMA_C6SAR    volatile.Register32 // 0x1D8
	MDMA_C6DAR    volatile.Register32 // 0x1DC
	MDMA_C6BRUR   volatile.Register32 // 0x1E0
	MDMA_C6LAR    volatile.Register32 // 0x1E4
	MDMA_C6TBR    volatile.Register32 // 0x1E8
	_             [4]byte
	MDMA_C6MAR    volatile.Register32 // 0x1F0
	MDMA_C6MDR    volatile.Register32 // 0x1F4
	_             [8]byte
	MDMA_C7ISR    volatile.Register32 // 0x200
	MDMA_C7IFCR   volatile.Register32 // 0x204
	MDMA_C7ESR    volatile.Register32 // 0x208
	MDMA_C7CR     volatile.Register32 // 0x20C
	MDMA_C7TCR    volatile.Register32 // 0x210
	MDMA_C7BNDTR  volatile.Register32 // 0x214
	MDMA_C7SAR    volatile.Register32 // 0x218
	MDMA_C7DAR    volatile.Register32 // 0x21C
	MDMA_C7BRUR   volatile.Register32 // 0x220
	MDMA_C7LAR    volatile.Register32 // 0x224
	MDMA_C7TBR    volatile.Register32 // 0x228
	_             [4]byte
	MDMA_C7MAR    volatile.Register32 // 0x230
	MDMA_C7MDR    volatile.Register32 // 0x234
	_             [8]byte
	MDMA_C8ISR    volatile.Register32 // 0x240
	MDMA_C8IFCR   volatile.Register32 // 0x244
	MDMA_C8ESR    volatile.Register32 // 0x248
	MDMA_C8CR     volatile.Register32 // 0x24C
	MDMA_C8TCR    volatile.Register32 // 0x250
	MDMA_C8BNDTR  volatile.Register32 // 0x254
	MDMA_C8SAR    volatile.Register32 // 0x258
	MDMA_C8DAR    volatile.Register32 // 0x25C
	MDMA_C8BRUR   volatile.Register32 // 0x260
	MDMA_C8LAR    volatile.Register32 // 0x264
	MDMA_C8TBR    volatile.Register32 // 0x268
	_             [4]byte
	MDMA_C8MAR    volatile.Register32 // 0x270
	MDMA_C8MDR    volatile.Register32 // 0x274
	_             [8]byte
	MDMA_C9ISR    volatile.Register32 // 0x280
	MDMA_C9IFCR   volatile.Register32 // 0x284
	MDMA_C9ESR    volatile.Register32 // 0x288
	MDMA_C9CR     volatile.Register32 // 0x28C
	MDMA_C9TCR    volatile.Register32 // 0x290
	MDMA_C9BNDTR  volatile.Register32 // 0x294
	MDMA_C9SAR    volatile.Register32 // 0x298
	MDMA_C9DAR    volatile.Register32 // 0x29C
	MDMA_C9BRUR   volatile.Register32 // 0x2A0
	MDMA_C9LAR    volatile.Register32 // 0x2A4
	MDMA_C9TBR    volatile.Register32 // 0x2A8
	_             [4]byte
	MDMA_C9MAR    volatile.Register32 // 0x2B0
	MDMA_C9MDR    volatile.Register32 // 0x2B4
	_             [8]byte
	MDMA_C10ISR   volatile.Register32 // 0x2C0
	MDMA_C10IFCR  volatile.Register32 // 0x2C4
	MDMA_C10ESR   volatile.Register32 // 0x2C8
	MDMA_C10CR    volatile.Register32 // 0x2CC
	MDMA_C10TCR   volatile.Register32 // 0x2D0
	MDMA_C10BNDTR volatile.Register32 // 0x2D4
	MDMA_C10SAR   volatile.Register32 // 0x2D8
	MDMA_C10DAR   volatile.Register32 // 0x2DC
	MDMA_C10BRUR  volatile.Register32 // 0x2E0
	MDMA_C10LAR   volatile.Register32 // 0x2E4
	MDMA_C10TBR   volatile.Register32 // 0x2E8
	_             [4]byte
	MDMA_C10MAR   volatile.Register32 // 0x2F0
	MDMA_C10MDR   volatile.Register32 // 0x2F4
	_             [8]byte
	MDMA_C11ISR   volatile.Register32 // 0x300
	MDMA_C11IFCR  volatile.Register32 // 0x304
	MDMA_C11ESR   volatile.Register32 // 0x308
	MDMA_C11CR    volatile.Register32 // 0x30C
	MDMA_C11TCR   volatile.Register32 // 0x310
	MDMA_C11BNDTR volatile.Register32 // 0x314
	MDMA_C11SAR   volatile.Register32 // 0x318
	MDMA_C11DAR   volatile.Register32 // 0x31C
	MDMA_C11BRUR  volatile.Register32 // 0x320
	MDMA_C11LAR   volatile.Register32 // 0x324
	MDMA_C11TBR   volatile.Register32 // 0x328
	_             [4]byte
	MDMA_C11MAR   volatile.Register32 // 0x330
	MDMA_C11MDR   volatile.Register32 // 0x334
	_             [8]byte
	MDMA_C12ISR   volatile.Register32 // 0x340
	MDMA_C12IFCR  volatile.Register32 // 0x344
	MDMA_C12ESR   volatile.Register32 // 0x348
	MDMA_C12CR    volatile.Register32 // 0x34C
	MDMA_C12TCR   volatile.Register32 // 0x350
	MDMA_C12BNDTR volatile.Register32 // 0x354
	MDMA_C12SAR   volatile.Register32 // 0x358
	MDMA_C12DAR   volatile.Register32 // 0x35C
	MDMA_C12BRUR  volatile.Register32 // 0x360
	MDMA_C12LAR   volatile.Register32 // 0x364
	MDMA_C12TBR   volatile.Register32 // 0x368
	_             [4]byte
	MDMA_C12MAR   volatile.Register32 // 0x370
	MDMA_C12MDR   volatile.Register32 // 0x374
	_             [8]byte
	MDMA_C13ISR   volatile.Register32 // 0x380
	MDMA_C13IFCR  volatile.Register32 // 0x384
	MDMA_C13ESR   volatile.Register32 // 0x388
	MDMA_C13CR    volatile.Register32 // 0x38C
	MDMA_C13TCR   volatile.Register32 // 0x390
	MDMA_C13BNDTR volatile.Register32 // 0x394
	MDMA_C13SAR   volatile.Register32 // 0x398
	MDMA_C13DAR   volatile.Register32 // 0x39C
	MDMA_C13BRUR  volatile.Register32 // 0x3A0
	MDMA_C13LAR   volatile.Register32 // 0x3A4
	MDMA_C13TBR   volatile.Register32 // 0x3A8
	_             [4]byte
	MDMA_C13MAR   volatile.Register32 // 0x3B0
	MDMA_C13MDR   volatile.Register32 // 0x3B4
	_             [8]byte
	MDMA_C14ISR   volatile.Register32 // 0x3C0
	MDMA_C14IFCR  volatile.Register32 // 0x3C4
	MDMA_C14ESR   volatile.Register32 // 0x3C8
	MDMA_C14CR    volatile.Register32 // 0x3CC
	MDMA_C14TCR   volatile.Register32 // 0x3D0
	MDMA_C14BNDTR volatile.Register32 // 0x3D4
	MDMA_C14SAR   volatile.Register32 // 0x3D8
	MDMA_C14DAR   volatile.Register32 // 0x3DC
	MDMA_C14BRUR  volatile.Register32 // 0x3E0
	MDMA_C14LAR   volatile.Register32 // 0x3E4
	MDMA_C14TBR   volatile.Register32 // 0x3E8
	_             [4]byte
	MDMA_C14MAR   volatile.Register32 // 0x3F0
	MDMA_C14MDR   volatile.Register32 // 0x3F4
	_             [8]byte
	MDMA_C15ISR   volatile.Register32 // 0x400
	MDMA_C15IFCR  volatile.Register32 // 0x404
	MDMA_C15ESR   volatile.Register32 // 0x408
	MDMA_C15CR    volatile.Register32 // 0x40C
	MDMA_C15TCR   volatile.Register32 // 0x410
	MDMA_C15BNDTR volatile.Register32 // 0x414
	MDMA_C15SAR   volatile.Register32 // 0x418
	MDMA_C15DAR   volatile.Register32 // 0x41C
	MDMA_C15BRUR  volatile.Register32 // 0x420
	MDMA_C15LAR   volatile.Register32 // 0x424
	MDMA_C15TBR   volatile.Register32 // 0x428
	_             [4]byte
	MDMA_C15MAR   volatile.Register32 // 0x430
	MDMA_C15MDR   volatile.Register32 // 0x434
}

// QUADSPI
type QUADSPI_Type struct {
	CR    volatile.Register32 // 0x0
	DCR   volatile.Register32 // 0x4
	SR    volatile.Register32 // 0x8
	FCR   volatile.Register32 // 0xC
	DLR   volatile.Register32 // 0x10
	CCR   volatile.Register32 // 0x14
	AR    volatile.Register32 // 0x18
	ABR   volatile.Register32 // 0x1C
	DR    volatile.Register32 // 0x20
	PSMKR volatile.Register32 // 0x24
	PSMAR volatile.Register32 // 0x28
	PIR   volatile.Register32 // 0x2C
	LPTR  volatile.Register32 // 0x30
}

// RNG
type RNG_Type struct {
	CR volatile.Register32 // 0x0
	SR volatile.Register32 // 0x4
	DR volatile.Register32 // 0x8
}

// RTC
type RTC_Type struct {
	RTC_TR       volatile.Register32 // 0x0
	RTC_DR       volatile.Register32 // 0x4
	RTC_CR       volatile.Register32 // 0x8
	RTC_ISR      volatile.Register32 // 0xC
	RTC_PRER     volatile.Register32 // 0x10
	RTC_WUTR     volatile.Register32 // 0x14
	_            [4]byte
	RTC_ALRMAR   volatile.Register32 // 0x1C
	RTC_ALRMBR   volatile.Register32 // 0x20
	RTC_WPR      volatile.Register32 // 0x24
	RTC_SSR      volatile.Register32 // 0x28
	RTC_SHIFTR   volatile.Register32 // 0x2C
	RTC_TSTR     volatile.Register32 // 0x30
	RTC_TSDR     volatile.Register32 // 0x34
	RTC_TSSSR    volatile.Register32 // 0x38
	RTC_CALR     volatile.Register32 // 0x3C
	RTC_TAMPCR   volatile.Register32 // 0x40
	RTC_ALRMASSR volatile.Register32 // 0x44
	RTC_ALRMBSSR volatile.Register32 // 0x48
	RTC_OR       volatile.Register32 // 0x4C
	RTC_BKP0R    volatile.Register32 // 0x50
	RTC_BKP1R    volatile.Register32 // 0x54
	RTC_BKP2R    volatile.Register32 // 0x58
	RTC_BKP3R    volatile.Register32 // 0x5C
	RTC_BKP4R    volatile.Register32 // 0x60
	RTC_BKP5R    volatile.Register32 // 0x64
	RTC_BKP6R    volatile.Register32 // 0x68
	RTC_BKP7R    volatile.Register32 // 0x6C
	RTC_BKP8R    volatile.Register32 // 0x70
	RTC_BKP9R    volatile.Register32 // 0x74
	RTC_BKP10R   volatile.Register32 // 0x78
	RTC_BKP11R   volatile.Register32 // 0x7C
	RTC_BKP12R   volatile.Register32 // 0x80
	RTC_BKP13R   volatile.Register32 // 0x84
	RTC_BKP14R   volatile.Register32 // 0x88
	RTC_BKP15R   volatile.Register32 // 0x8C
	RTC_BKP16R   volatile.Register32 // 0x90
	RTC_BKP17R   volatile.Register32 // 0x94
	RTC_BKP18R   volatile.Register32 // 0x98
	RTC_BKP19R   volatile.Register32 // 0x9C
	RTC_BKP20R   volatile.Register32 // 0xA0
	RTC_BKP21R   volatile.Register32 // 0xA4
	RTC_BKP22R   volatile.Register32 // 0xA8
	RTC_BKP23R   volatile.Register32 // 0xAC
	RTC_BKP24R   volatile.Register32 // 0xB0
	RTC_BKP25R   volatile.Register32 // 0xB4
	RTC_BKP26R   volatile.Register32 // 0xB8
	RTC_BKP27R   volatile.Register32 // 0xBC
	RTC_BKP28R   volatile.Register32 // 0xC0
	RTC_BKP29R   volatile.Register32 // 0xC4
	RTC_BKP30R   volatile.Register32 // 0xC8
	RTC_BKP31R   volatile.Register32 // 0xCC
}

// SAI
type SAI_Type struct {
	SAI_GCR    volatile.Register32 // 0x0
	SAI_ACR1   volatile.Register32 // 0x4
	SAI_ACR2   volatile.Register32 // 0x8
	SAI_AFRCR  volatile.Register32 // 0xC
	SAI_ASLOTR volatile.Register32 // 0x10
	SAI_AIM    volatile.Register32 // 0x14
	SAI_ASR    volatile.Register32 // 0x18
	SAI_ACLRFR volatile.Register32 // 0x1C
	SAI_ADR    volatile.Register32 // 0x20
	SAI_BCR1   volatile.Register32 // 0x24
	SAI_BCR2   volatile.Register32 // 0x28
	SAI_BFRCR  volatile.Register32 // 0x2C
	SAI_BSLOTR volatile.Register32 // 0x30
	SAI_BIM    volatile.Register32 // 0x34
	SAI_BSR    volatile.Register32 // 0x38
	SAI_BCLRFR volatile.Register32 // 0x3C
	SAI_BDR    volatile.Register32 // 0x40
	SAI_PDMCR  volatile.Register32 // 0x44
	SAI_PDMDLY volatile.Register32 // 0x48
}

// SDMMC1
type SDMMC_Type struct {
	POWER      volatile.Register32 // 0x0
	CLKCR      volatile.Register32 // 0x4
	ARGR       volatile.Register32 // 0x8
	CMDR       volatile.Register32 // 0xC
	RESPCMDR   volatile.Register32 // 0x10
	RESP1R     volatile.Register32 // 0x14
	RESP2R     volatile.Register32 // 0x18
	RESP3R     volatile.Register32 // 0x1C
	RESP4R     volatile.Register32 // 0x20
	DTIMER     volatile.Register32 // 0x24
	DLENR      volatile.Register32 // 0x28
	DCTRL      volatile.Register32 // 0x2C
	DCNTR      volatile.Register32 // 0x30
	STAR       volatile.Register32 // 0x34
	ICR        volatile.Register32 // 0x38
	MASKR      volatile.Register32 // 0x3C
	ACKTIMER   volatile.Register32 // 0x40
	_          [12]byte
	IDMACTRLR  volatile.Register32 // 0x50
	IDMABSIZER volatile.Register32 // 0x54
	IDMABASE0R volatile.Register32 // 0x58
	IDMABASE1R volatile.Register32 // 0x5C
	_          [32]byte
	FIFOR      volatile.Register32 // 0x80
	_          [880]byte
	VER        volatile.Register32 // 0x3F4
	ID         volatile.Register32 // 0x3F8
}

// VREFBUF
type VREFBUF_Type struct {
	CSR volatile.Register32 // 0x0
	CCR volatile.Register32 // 0x4
}

// IWDG
type IWDG_Type struct {
	KR   volatile.Register32 // 0x0
	PR   volatile.Register32 // 0x4
	RLR  volatile.Register32 // 0x8
	SR   volatile.Register32 // 0xC
	WINR volatile.Register32 // 0x10
}

// WWDG
type WWDG_Type struct {
	CR  volatile.Register32 // 0x0
	CFR volatile.Register32 // 0x4
	SR  volatile.Register32 // 0x8
}

// PWR
type PWR_Type struct {
	CR1     volatile.Register32 // 0x0
	CSR1    volatile.Register32 // 0x4
	CR2     volatile.Register32 // 0x8
	CR3     volatile.Register32 // 0xC
	CPUCR   volatile.Register32 // 0x10
	_       [4]byte
	D3CR    volatile.Register32 // 0x18
	_       [4]byte
	WKUPCR  volatile.Register32 // 0x20
	WKUPFR  volatile.Register32 // 0x24
	WKUPEPR volatile.Register32 // 0x28
}

// Serial peripheral interface
type SPI_Type struct {
	CR1     volatile.Register32 // 0x0
	CR2     volatile.Register32 // 0x4
	CFG1    volatile.Register32 // 0x8
	CFG2    volatile.Register32 // 0xC
	IER     volatile.Register32 // 0x10
	SR      volatile.Register32 // 0x14
	IFCR    volatile.Register32 // 0x18
	_       [4]byte
	TXDR    volatile.Register32 // 0x20
	_       [12]byte
	RXDR    volatile.Register32 // 0x30
	_       [12]byte
	CRCPOLY volatile.Register32 // 0x40
	TXCRC   volatile.Register32 // 0x44
	RXCRC   volatile.Register32 // 0x48
	UDRDR   volatile.Register32 // 0x4C
	CGFR    volatile.Register32 // 0x50
}

// LCD-TFT Controller
type LTDC_Type struct {
	_        [8]byte
	SSCR     volatile.Register32 // 0x8
	BPCR     volatile.Register32 // 0xC
	AWCR     volatile.Register32 // 0x10
	TWCR     volatile.Register32 // 0x14
	GCR      volatile.Register32 // 0x18
	_        [8]byte
	SRCR     volatile.Register32 // 0x24
	_        [4]byte
	BCCR     volatile.Register32 // 0x2C
	_        [4]byte
	IER      volatile.Register32 // 0x34
	ISR      volatile.Register32 // 0x38
	ICR      volatile.Register32 // 0x3C
	LIPCR    volatile.Register32 // 0x40
	CPSR     volatile.Register32 // 0x44
	CDSR     volatile.Register32 // 0x48
	_        [56]byte
	L1CR     volatile.Register32 // 0x84
	L1WHPCR  volatile.Register32 // 0x88
	L1WVPCR  volatile.Register32 // 0x8C
	L1CKCR   volatile.Register32 // 0x90
	L1PFCR   volatile.Register32 // 0x94
	L1CACR   volatile.Register32 // 0x98
	L1DCCR   volatile.Register32 // 0x9C
	L1BFCR   volatile.Register32 // 0xA0
	_        [8]byte
	L1CFBAR  volatile.Register32 // 0xAC
	L1CFBLR  volatile.Register32 // 0xB0
	L1CFBLNR volatile.Register32 // 0xB4
	_        [12]byte
	L1CLUTWR volatile.Register32 // 0xC4
	_        [60]byte
	L2CR     volatile.Register32 // 0x104
	L2WHPCR  volatile.Register32 // 0x108
	L2WVPCR  volatile.Register32 // 0x10C
	L2CKCR   volatile.Register32 // 0x110
	L2PFCR   volatile.Register32 // 0x114
	L2CACR   volatile.Register32 // 0x118
	L2DCCR   volatile.Register32 // 0x11C
	L2BFCR   volatile.Register32 // 0x120
	_        [8]byte
	L2CFBAR  volatile.Register32 // 0x12C
	L2CFBLR  volatile.Register32 // 0x130
	L2CFBLNR volatile.Register32 // 0x134
	_        [12]byte
	L2CLUTWR volatile.Register32 // 0x144
}

// Receiver Interface
type SPDIFRX_Type struct {
	CR    volatile.Register32 // 0x0
	IMR   volatile.Register32 // 0x4
	SR    volatile.Register32 // 0x8
	IFCR  volatile.Register32 // 0xC
	DR_00 volatile.Register32 // 0x10
	CSR   volatile.Register32 // 0x14
	DIR   volatile.Register32 // 0x18
	_     [984]byte
	VERR  volatile.Register32 // 0x3F4
	IDR   volatile.Register32 // 0x3F8
	SIDR  volatile.Register32 // 0x3FC
}

// Analog to Digital Converter
type ADC_Type struct {
	ISR      volatile.Register32 // 0x0
	IER      volatile.Register32 // 0x4
	CR       volatile.Register32 // 0x8
	CFGR     volatile.Register32 // 0xC
	CFGR2    volatile.Register32 // 0x10
	SMPR1    volatile.Register32 // 0x14
	SMPR2    volatile.Register32 // 0x18
	PCSEL    volatile.Register32 // 0x1C
	LTR1     volatile.Register32 // 0x20
	LHTR1    volatile.Register32 // 0x24
	_        [8]byte
	SQR1     volatile.Register32 // 0x30
	SQR2     volatile.Register32 // 0x34
	SQR3     volatile.Register32 // 0x38
	SQR4     volatile.Register32 // 0x3C
	DR       volatile.Register32 // 0x40
	_        [8]byte
	JSQR     volatile.Register32 // 0x4C
	_        [16]byte
	OFR1     volatile.Register32 // 0x60
	OFR2     volatile.Register32 // 0x64
	OFR3     volatile.Register32 // 0x68
	OFR4     volatile.Register32 // 0x6C
	_        [16]byte
	JDR1     volatile.Register32 // 0x80
	JDR2     volatile.Register32 // 0x84
	JDR3     volatile.Register32 // 0x88
	JDR4     volatile.Register32 // 0x8C
	_        [16]byte
	AWD2CR   volatile.Register32 // 0xA0
	AWD3CR   volatile.Register32 // 0xA4
	_        [8]byte
	LTR2     volatile.Register32 // 0xB0
	HTR2     volatile.Register32 // 0xB4
	LTR3     volatile.Register32 // 0xB8
	HTR3     volatile.Register32 // 0xBC
	DIFSEL   volatile.Register32 // 0xC0
	CALFACT  volatile.Register32 // 0xC4
	CALFACT2 volatile.Register32 // 0xC8
}

// Cryptographic processor
type CRC_Type struct {
	DR   volatile.Register32 // 0x0
	IDR  volatile.Register32 // 0x4
	CR   volatile.Register32 // 0x8
	INIT volatile.Register32 // 0xC
	POL  volatile.Register32 // 0x10
}

// Reset and clock control
type RCC_Type struct {
	CR            volatile.Register32 // 0x0
	ICSCR         volatile.Register32 // 0x4
	CRRCR         volatile.Register32 // 0x8
	_             [4]byte
	CFGR          volatile.Register32 // 0x10
	_             [4]byte
	D1CFGR        volatile.Register32 // 0x18
	D2CFGR        volatile.Register32 // 0x1C
	D3CFGR        volatile.Register32 // 0x20
	_             [4]byte
	PLLCKSELR     volatile.Register32 // 0x28
	PLLCFGR       volatile.Register32 // 0x2C
	PLL1DIVR      volatile.Register32 // 0x30
	PLL1FRACR     volatile.Register32 // 0x34
	PLL2DIVR      volatile.Register32 // 0x38
	PLL2FRACR     volatile.Register32 // 0x3C
	PLL3DIVR      volatile.Register32 // 0x40
	PLL3FRACR     volatile.Register32 // 0x44
	_             [4]byte
	D1CCIPR       volatile.Register32 // 0x4C
	D2CCIP1R      volatile.Register32 // 0x50
	D2CCIP2R      volatile.Register32 // 0x54
	D3CCIPR       volatile.Register32 // 0x58
	_             [4]byte
	CIER          volatile.Register32 // 0x60
	CIFR          volatile.Register32 // 0x64
	CICR          volatile.Register32 // 0x68
	_             [4]byte
	BDCR          volatile.Register32 // 0x70
	CSR           volatile.Register32 // 0x74
	_             [4]byte
	AHB3RSTR      volatile.Register32 // 0x7C
	AHB1RSTR      volatile.Register32 // 0x80
	AHB2RSTR      volatile.Register32 // 0x84
	AHB4RSTR      volatile.Register32 // 0x88
	APB3RSTR      volatile.Register32 // 0x8C
	APB1LRSTR     volatile.Register32 // 0x90
	APB1HRSTR     volatile.Register32 // 0x94
	APB2RSTR      volatile.Register32 // 0x98
	APB4RSTR      volatile.Register32 // 0x9C
	GCR           volatile.Register32 // 0xA0
	_             [4]byte
	D3AMR         volatile.Register32 // 0xA8
	_             [36]byte
	RSR           volatile.Register32 // 0xD0
	AHB3ENR       volatile.Register32 // 0xD4
	AHB1ENR       volatile.Register32 // 0xD8
	AHB2ENR       volatile.Register32 // 0xDC
	AHB4ENR       volatile.Register32 // 0xE0
	APB3ENR       volatile.Register32 // 0xE4
	APB1LENR      volatile.Register32 // 0xE8
	APB1HENR      volatile.Register32 // 0xEC
	APB2ENR       volatile.Register32 // 0xF0
	APB4ENR       volatile.Register32 // 0xF4
	_             [4]byte
	AHB3LPENR     volatile.Register32 // 0xFC
	AHB1LPENR     volatile.Register32 // 0x100
	AHB2LPENR     volatile.Register32 // 0x104
	AHB4LPENR     volatile.Register32 // 0x108
	APB3LPENR     volatile.Register32 // 0x10C
	APB1LLPENR    volatile.Register32 // 0x110
	APB1HLPENR    volatile.Register32 // 0x114
	APB2LPENR     volatile.Register32 // 0x118
	APB4LPENR     volatile.Register32 // 0x11C
	_             [16]byte
	C1_RSR        volatile.Register32 // 0x130
	C1_AHB3ENR    volatile.Register32 // 0x134
	C1_AHB1ENR    volatile.Register32 // 0x138
	C1_AHB2ENR    volatile.Register32 // 0x13C
	C1_AHB4ENR    volatile.Register32 // 0x140
	C1_APB3ENR    volatile.Register32 // 0x144
	C1_APB1LENR   volatile.Register32 // 0x148
	C1_APB1HENR   volatile.Register32 // 0x14C
	C1_APB2ENR    volatile.Register32 // 0x150
	C1_APB4ENR    volatile.Register32 // 0x154
	_             [4]byte
	C1_AHB3LPENR  volatile.Register32 // 0x15C
	C1_AHB1LPENR  volatile.Register32 // 0x160
	C1_AHB2LPENR  volatile.Register32 // 0x164
	C1_AHB4LPENR  volatile.Register32 // 0x168
	C1_APB3LPENR  volatile.Register32 // 0x16C
	C1_APB1LLPENR volatile.Register32 // 0x170
	C1_APB1HLPENR volatile.Register32 // 0x174
	C1_APB2LPENR  volatile.Register32 // 0x178
	C1_APB4LPENR  volatile.Register32 // 0x17C
}

// Low power timer
type LPTIM_Type struct {
	ISR   volatile.Register32 // 0x0
	ICR   volatile.Register32 // 0x4
	IER   volatile.Register32 // 0x8
	CFGR  volatile.Register32 // 0xC
	CR    volatile.Register32 // 0x10
	CMP   volatile.Register32 // 0x14
	ARR   volatile.Register32 // 0x18
	CNT   volatile.Register32 // 0x1C
	_     [4]byte
	CFGR2 volatile.Register32 // 0x24
}

// LPUART1
type LPUART_Type struct {
	CR1   volatile.Register32 // 0x0
	CR2   volatile.Register32 // 0x4
	CR3   volatile.Register32 // 0x8
	BRR   volatile.Register32 // 0xC
	GTPR  volatile.Register32 // 0x10
	RTOR  volatile.Register32 // 0x14
	RQR   volatile.Register32 // 0x18
	ISR   volatile.Register32 // 0x1C
	ICR   volatile.Register32 // 0x20
	RDR   volatile.Register32 // 0x24
	TDR   volatile.Register32 // 0x28
	PRESC volatile.Register32 // 0x2C
}

// System configuration controller
type SYSCFG_Type struct {
	_       [4]byte
	PMCR    volatile.Register32 // 0x4
	EXTICR1 volatile.Register32 // 0x8
	EXTICR2 volatile.Register32 // 0xC
	EXTICR3 volatile.Register32 // 0x10
	EXTICR4 volatile.Register32 // 0x14
	_       [8]byte
	CCCSR   volatile.Register32 // 0x20
	CCVR    volatile.Register32 // 0x24
	CCCR    volatile.Register32 // 0x28
	PWRCR   volatile.Register32 // 0x2C
	_       [244]byte
	PKGR    volatile.Register32 // 0x124
	_       [472]byte
	UR0     volatile.Register32 // 0x300
	_       [4]byte
	UR2     volatile.Register32 // 0x308
	UR3     volatile.Register32 // 0x30C
	UR4     volatile.Register32 // 0x310
	UR5     volatile.Register32 // 0x314
	UR6     volatile.Register32 // 0x318
	UR7     volatile.Register32 // 0x31C
	UR8     volatile.Register32 // 0x320
	UR9     volatile.Register32 // 0x324
	UR10    volatile.Register32 // 0x328
	UR11    volatile.Register32 // 0x32C
	UR12    volatile.Register32 // 0x330
	UR13    volatile.Register32 // 0x334
	UR14    volatile.Register32 // 0x338
	UR15    volatile.Register32 // 0x33C
	UR16    volatile.Register32 // 0x340
	UR17    volatile.Register32 // 0x344
}

// External interrupt/event controller
type EXTI_Type struct {
	RTSR1   volatile.Register32 // 0x0
	FTSR1   volatile.Register32 // 0x4
	SWIER1  volatile.Register32 // 0x8
	D3PMR1  volatile.Register32 // 0xC
	D3PCR1L volatile.Register32 // 0x10
	D3PCR1H volatile.Register32 // 0x14
	_       [8]byte
	RTSR2   volatile.Register32 // 0x20
	FTSR2   volatile.Register32 // 0x24
	SWIER2  volatile.Register32 // 0x28
	D3PMR2  volatile.Register32 // 0x2C
	D3PCR2L volatile.Register32 // 0x30
	D3PCR2H volatile.Register32 // 0x34
	_       [8]byte
	RTSR3   volatile.Register32 // 0x40
	FTSR3   volatile.Register32 // 0x44
	SWIER3  volatile.Register32 // 0x48
	D3PMR3  volatile.Register32 // 0x4C
	_       [4]byte
	D3PCR3H volatile.Register32 // 0x54
	_       [40]byte
	CPUIMR1 volatile.Register32 // 0x80
	CPUEMR1 volatile.Register32 // 0x84
	CPUPR1  volatile.Register32 // 0x88
	_       [4]byte
	CPUIMR2 volatile.Register32 // 0x90
	CPUEMR2 volatile.Register32 // 0x94
	CPUPR2  volatile.Register32 // 0x98
	_       [4]byte
	CPUIMR3 volatile.Register32 // 0xA0
	CPUEMR3 volatile.Register32 // 0xA4
	CPUPR3  volatile.Register32 // 0xA8
}

// DELAY_Block_SDMMC1
type DLYB_Type struct {
	CR   volatile.Register32 // 0x0
	CFGR volatile.Register32 // 0x4
}

// Flash
type Flash_Type struct {
	ACR        volatile.Register32 // 0x0
	KEYR1      volatile.Register32 // 0x4
	OPTKEYR    volatile.Register32 // 0x8
	CR1        volatile.Register32 // 0xC
	SR1        volatile.Register32 // 0x10
	CCR1       volatile.Register32 // 0x14
	OPTCR      volatile.Register32 // 0x18
	OPTSR_CUR  volatile.Register32 // 0x1C
	OPTSR_PRG  volatile.Register32 // 0x20
	OPTCCR     volatile.Register32 // 0x24
	PRAR_CUR1  volatile.Register32 // 0x28
	PRAR_PRG1  volatile.Register32 // 0x2C
	SCAR_CUR1  volatile.Register32 // 0x30
	SCAR_PRG1  volatile.Register32 // 0x34
	WPSN_CUR1R volatile.Register32 // 0x38
	WPSN_PRG1R volatile.Register32 // 0x3C
	BOOT_CURR  volatile.Register32 // 0x40
	BOOT_PRGR  volatile.Register32 // 0x44
	_          [8]byte
	CRCCR1     volatile.Register32 // 0x50
	CRCSADD1R  volatile.Register32 // 0x54
	CRCEADD1R  volatile.Register32 // 0x58
	CRCDATAR   volatile.Register32 // 0x5C
	ECC_FA1R   volatile.Register32 // 0x60
	_          [156]byte
	ACR_       volatile.Register32 // 0x100
	KEYR2      volatile.Register32 // 0x104
	OPTKEYR_   volatile.Register32 // 0x108
	CR2        volatile.Register32 // 0x10C
	SR2        volatile.Register32 // 0x110
	CCR2       volatile.Register32 // 0x114
	OPTCR_     volatile.Register32 // 0x118
	OPTSR_CUR_ volatile.Register32 // 0x11C
	OPTSR_PRG_ volatile.Register32 // 0x120
	OPTCCR_    volatile.Register32 // 0x124
	PRAR_CUR2  volatile.Register32 // 0x128
	_          [4]byte
	SCAR_CUR2  volatile.Register32 // 0x130
	SCAR_PRG2  volatile.Register32 // 0x134
	WPSN_CUR2R volatile.Register32 // 0x138
	WPSN_PRG2R volatile.Register32 // 0x13C
	_          [16]byte
	CRCCR2     volatile.Register32 // 0x150
	CRCSADD2R  volatile.Register32 // 0x154
	CRCEADD2R  volatile.Register32 // 0x158
	_          [4]byte
	ECC_FA2R   volatile.Register32 // 0x160
}

// AXI interconnect registers
type AXI_Type struct {
	_                       [8144]byte
	AXI_PERIPH_ID_4         volatile.Register32 // 0x1FD0
	_                       [12]byte
	AXI_PERIPH_ID_0         volatile.Register32 // 0x1FE0
	AXI_PERIPH_ID_1         volatile.Register32 // 0x1FE4
	AXI_PERIPH_ID_2         volatile.Register32 // 0x1FE8
	AXI_PERIPH_ID_3         volatile.Register32 // 0x1FEC
	AXI_COMP_ID_0           volatile.Register32 // 0x1FF0
	AXI_COMP_ID_1           volatile.Register32 // 0x1FF4
	AXI_COMP_ID_2           volatile.Register32 // 0x1FF8
	AXI_COMP_ID_3           volatile.Register32 // 0x1FFC
	_                       [8]byte
	AXI_TARG1_FN_MOD_ISS_BM volatile.Register32 // 0x2008
	_                       [24]byte
	AXI_TARG1_FN_MOD2       volatile.Register32 // 0x2024
	_                       [4]byte
	AXI_TARG1_FN_MOD_LB     volatile.Register32 // 0x202C
	_                       [216]byte
	AXI_TARG1_FN_MOD        volatile.Register32 // 0x2108
	_                       [3836]byte
	AXI_TARG2_FN_MOD_ISS_BM volatile.Register32 // 0x3008
	_                       [24]byte
	AXI_TARG2_FN_MOD2       volatile.Register32 // 0x3024
	_                       [4]byte
	AXI_TARG2_FN_MOD_LB     volatile.Register32 // 0x302C
	_                       [216]byte
	AXI_TARG2_FN_MOD        volatile.Register32 // 0x3108
	_                       [3836]byte
	AXI_TARG3_FN_MOD_ISS_BM volatile.Register32 // 0x4008
	_                       [4092]byte
	AXI_TARG4_FN_MOD_ISS_BM volatile.Register32 // 0x5008
	_                       [4092]byte
	AXI_TARG5_FN_MOD_ISS_BM volatile.Register32 // 0x6008
	_                       [4092]byte
	AXI_TARG6_FN_MOD_ISS_BM volatile.Register32 // 0x7008
	_                       [4096]byte
	AXI_TARG7_FN_MOD_ISS_BM volatile.Register32 // 0x800C
	_                       [20]byte
	AXI_TARG7_FN_MOD2       volatile.Register32 // 0x8024
	_                       [224]byte
	AXI_TARG7_FN_MOD        volatile.Register32 // 0x8108
	_                       [237336]byte
	AXI_INI1_FN_MOD2        volatile.Register32 // 0x42024
	AXI_INI1_FN_MOD_AHB     volatile.Register32 // 0x42028
	_                       [212]byte
	AXI_INI1_READ_QOS       volatile.Register32 // 0x42100
	AXI_INI1_WRITE_QOS      volatile.Register32 // 0x42104
	AXI_INI1_FN_MOD         volatile.Register32 // 0x42108
	_                       [4084]byte
	AXI_INI2_READ_QOS       volatile.Register32 // 0x43100
	AXI_INI2_WRITE_QOS      volatile.Register32 // 0x43104
	AXI_INI2_FN_MOD         volatile.Register32 // 0x43108
	_                       [3864]byte
	AXI_INI3_FN_MOD2        volatile.Register32 // 0x44024
	AXI_INI3_FN_MOD_AHB     volatile.Register32 // 0x44028
	_                       [212]byte
	AXI_INI3_READ_QOS       volatile.Register32 // 0x44100
	AXI_INI3_WRITE_QOS      volatile.Register32 // 0x44104
	AXI_INI3_FN_MOD         volatile.Register32 // 0x44108
	_                       [4084]byte
	AXI_INI4_READ_QOS       volatile.Register32 // 0x45100
	AXI_INI4_WRITE_QOS      volatile.Register32 // 0x45104
	AXI_INI4_FN_MOD         volatile.Register32 // 0x45108
	_                       [4084]byte
	AXI_INI5_READ_QOS       volatile.Register32 // 0x46100
	AXI_INI5_WRITE_QOS      volatile.Register32 // 0x46104
	AXI_INI5_FN_MOD         volatile.Register32 // 0x46108
	_                       [4084]byte
	AXI_INI6_READ_QOS       volatile.Register32 // 0x47100
	AXI_INI6_WRITE_QOS      volatile.Register32 // 0x47104
	AXI_INI6_FN_MOD         volatile.Register32 // 0x47108
}

// Hash processor
type HASH_Type struct {
	CR       volatile.Register32 // 0x0
	DIN      volatile.Register32 // 0x4
	STR      volatile.Register32 // 0x8
	HR0      volatile.Register32 // 0xC
	HR1      volatile.Register32 // 0x10
	HR2      volatile.Register32 // 0x14
	HR3      volatile.Register32 // 0x18
	HR4      volatile.Register32 // 0x1C
	IMR      volatile.Register32 // 0x20
	SR       volatile.Register32 // 0x24
	_        [208]byte
	CSR0     volatile.Register32 // 0xF8
	CSR1     volatile.Register32 // 0xFC
	CSR2     volatile.Register32 // 0x100
	CSR3     volatile.Register32 // 0x104
	CSR4     volatile.Register32 // 0x108
	CSR5     volatile.Register32 // 0x10C
	CSR6     volatile.Register32 // 0x110
	CSR7     volatile.Register32 // 0x114
	CSR8     volatile.Register32 // 0x118
	CSR9     volatile.Register32 // 0x11C
	CSR10    volatile.Register32 // 0x120
	CSR11    volatile.Register32 // 0x124
	CSR12    volatile.Register32 // 0x128
	CSR13    volatile.Register32 // 0x12C
	CSR14    volatile.Register32 // 0x130
	CSR15    volatile.Register32 // 0x134
	CSR16    volatile.Register32 // 0x138
	CSR17    volatile.Register32 // 0x13C
	CSR18    volatile.Register32 // 0x140
	CSR19    volatile.Register32 // 0x144
	CSR20    volatile.Register32 // 0x148
	CSR21    volatile.Register32 // 0x14C
	CSR22    volatile.Register32 // 0x150
	CSR23    volatile.Register32 // 0x154
	CSR24    volatile.Register32 // 0x158
	CSR25    volatile.Register32 // 0x15C
	CSR26    volatile.Register32 // 0x160
	CSR27    volatile.Register32 // 0x164
	CSR28    volatile.Register32 // 0x168
	CSR29    volatile.Register32 // 0x16C
	CSR30    volatile.Register32 // 0x170
	CSR31    volatile.Register32 // 0x174
	CSR32    volatile.Register32 // 0x178
	CSR33    volatile.Register32 // 0x17C
	CSR34    volatile.Register32 // 0x180
	CSR35    volatile.Register32 // 0x184
	CSR36    volatile.Register32 // 0x188
	CSR37    volatile.Register32 // 0x18C
	CSR38    volatile.Register32 // 0x190
	CSR39    volatile.Register32 // 0x194
	CSR40    volatile.Register32 // 0x198
	CSR41    volatile.Register32 // 0x19C
	CSR42    volatile.Register32 // 0x1A0
	CSR43    volatile.Register32 // 0x1A4
	CSR44    volatile.Register32 // 0x1A8
	CSR45    volatile.Register32 // 0x1AC
	CSR46    volatile.Register32 // 0x1B0
	CSR47    volatile.Register32 // 0x1B4
	CSR48    volatile.Register32 // 0x1B8
	CSR49    volatile.Register32 // 0x1BC
	CSR50    volatile.Register32 // 0x1C0
	CSR51    volatile.Register32 // 0x1C4
	CSR52    volatile.Register32 // 0x1C8
	CSR53    volatile.Register32 // 0x1CC
	_        [320]byte
	HASH_HR0 volatile.Register32 // 0x310
	HASH_HR1 volatile.Register32 // 0x314
	HASH_HR2 volatile.Register32 // 0x318
	HASH_HR3 volatile.Register32 // 0x31C
	HASH_HR4 volatile.Register32 // 0x320
	HASH_HR5 volatile.Register32 // 0x324
	HASH_HR6 volatile.Register32 // 0x328
	HASH_HR7 volatile.Register32 // 0x32C
}

// Cryptographic processor
type CRYP_Type struct {
	CR         volatile.Register32 // 0x0
	SR         volatile.Register32 // 0x4
	DIN        volatile.Register32 // 0x8
	DOUT       volatile.Register32 // 0xC
	DMACR      volatile.Register32 // 0x10
	IMSCR      volatile.Register32 // 0x14
	RISR       volatile.Register32 // 0x18
	MISR       volatile.Register32 // 0x1C
	K0LR       volatile.Register32 // 0x20
	K0RR       volatile.Register32 // 0x24
	K1LR       volatile.Register32 // 0x28
	K1RR       volatile.Register32 // 0x2C
	K2LR       volatile.Register32 // 0x30
	K2RR       volatile.Register32 // 0x34
	K3LR       volatile.Register32 // 0x38
	K3RR       volatile.Register32 // 0x3C
	IV0LR      volatile.Register32 // 0x40
	IV0RR      volatile.Register32 // 0x44
	IV1LR      volatile.Register32 // 0x48
	IV1RR      volatile.Register32 // 0x4C
	CSGCMCCM0R volatile.Register32 // 0x50
	CSGCMCCM1R volatile.Register32 // 0x54
	CSGCMCCM2R volatile.Register32 // 0x58
	CSGCMCCM3R volatile.Register32 // 0x5C
	CSGCMCCM4R volatile.Register32 // 0x60
	CSGCMCCM5R volatile.Register32 // 0x64
	CSGCMCCM6R volatile.Register32 // 0x68
	CSGCMCCM7R volatile.Register32 // 0x6C
	CSGCM0R    volatile.Register32 // 0x70
	CSGCM1R    volatile.Register32 // 0x74
	CSGCM2R    volatile.Register32 // 0x78
	CSGCM3R    volatile.Register32 // 0x7C
	CSGCM4R    volatile.Register32 // 0x80
	CSGCM5R    volatile.Register32 // 0x84
	CSGCM6R    volatile.Register32 // 0x88
	CSGCM7R    volatile.Register32 // 0x8C
}

// Digital camera interface
type DCMI_Type struct {
	CR     volatile.Register32 // 0x0
	SR     volatile.Register32 // 0x4
	RIS    volatile.Register32 // 0x8
	IER    volatile.Register32 // 0xC
	MIS    volatile.Register32 // 0x10
	ICR    volatile.Register32 // 0x14
	ESCR   volatile.Register32 // 0x18
	ESUR   volatile.Register32 // 0x1C
	CWSTRT volatile.Register32 // 0x20
	CWSIZE volatile.Register32 // 0x24
	DR     volatile.Register32 // 0x28
}

// USB 1 on the go high speed
type USB_OTG_HS_Type struct {
	OTG_HS_GOTGCTL        volatile.Register32 // 0x0
	OTG_HS_GOTGINT        volatile.Register32 // 0x4
	OTG_HS_GAHBCFG        volatile.Register32 // 0x8
	OTG_HS_GUSBCFG        volatile.Register32 // 0xC
	OTG_HS_GRSTCTL        volatile.Register32 // 0x10
	OTG_HS_GINTSTS        volatile.Register32 // 0x14
	OTG_HS_GINTMSK        volatile.Register32 // 0x18
	OTG_HS_GRXSTSR_Host   volatile.Register32 // 0x1C
	OTG_HS_GRXSTSP_Host   volatile.Register32 // 0x20
	OTG_HS_GRXFSIZ        volatile.Register32 // 0x24
	OTG_HS_HNPTXFSIZ_Host volatile.Register32 // 0x28
	OTG_HS_GNPTXSTS       volatile.Register32 // 0x2C
	_                     [8]byte
	OTG_HS_GCCFG          volatile.Register32 // 0x38
	OTG_HS_CID            volatile.Register32 // 0x3C
	_                     [20]byte
	OTG_HS_GLPMCFG        volatile.Register32 // 0x54
	_                     [168]byte
	OTG_HS_HPTXFSIZ       volatile.Register32 // 0x100
	OTG_HS_DIEPTXF1       volatile.Register32 // 0x104
	OTG_HS_DIEPTXF2       volatile.Register32 // 0x108
	_                     [16]byte
	OTG_HS_DIEPTXF3       volatile.Register32 // 0x11C
	OTG_HS_DIEPTXF4       volatile.Register32 // 0x120
	OTG_HS_DIEPTXF5       volatile.Register32 // 0x124
	OTG_HS_DIEPTXF6       volatile.Register32 // 0x128
	OTG_HS_DIEPTXF7       volatile.Register32 // 0x12C
}

// Ethernet: DMA mode register (DMA)
type Ethernet_Type struct {
	DMAMR      volatile.Register32 // 0x0
	DMASBMR    volatile.Register32 // 0x4
	DMAISR     volatile.Register32 // 0x8
	DMADSR     volatile.Register32 // 0xC
	_          [240]byte
	DMACCR     volatile.Register32 // 0x100
	DMACTxCR   volatile.Register32 // 0x104
	DMACRxCR   volatile.Register32 // 0x108
	_          [8]byte
	DMACTxDLAR volatile.Register32 // 0x114
	_          [4]byte
	DMACRxDLAR volatile.Register32 // 0x11C
	DMACTxDTPR volatile.Register32 // 0x120
	_          [4]byte
	DMACRxDTPR volatile.Register32 // 0x128
	DMACTxRLR  volatile.Register32 // 0x12C
	DMACRxRLR  volatile.Register32 // 0x130
	DMACIER    volatile.Register32 // 0x134
	DMACRxIWTR volatile.Register32 // 0x138
	_          [8]byte
	DMACCATxDR volatile.Register32 // 0x144
	_          [4]byte
	DMACCARxDR volatile.Register32 // 0x14C
	_          [4]byte
	DMACCATxBR volatile.Register32 // 0x154
	_          [4]byte
	DMACCARxBR volatile.Register32 // 0x15C
	DMACSR     volatile.Register32 // 0x160
	_          [8]byte
	DMACMFCR   volatile.Register32 // 0x16C
}

// DMA controller
type DMA_Type struct {
	LISR   volatile.Register32 // 0x0
	HISR   volatile.Register32 // 0x4
	LIFCR  volatile.Register32 // 0x8
	HIFCR  volatile.Register32 // 0xC
	S0CR   volatile.Register32 // 0x10
	S0NDTR volatile.Register32 // 0x14
	S0PAR  volatile.Register32 // 0x18
	S0M0AR volatile.Register32 // 0x1C
	S0M1AR volatile.Register32 // 0x20
	S0FCR  volatile.Register32 // 0x24
	S1CR   volatile.Register32 // 0x28
	S1NDTR volatile.Register32 // 0x2C
	S1PAR  volatile.Register32 // 0x30
	S1M0AR volatile.Register32 // 0x34
	S1M1AR volatile.Register32 // 0x38
	S1FCR  volatile.Register32 // 0x3C
	S2CR   volatile.Register32 // 0x40
	S2NDTR volatile.Register32 // 0x44
	S2PAR  volatile.Register32 // 0x48
	S2M0AR volatile.Register32 // 0x4C
	S2M1AR volatile.Register32 // 0x50
	S2FCR  volatile.Register32 // 0x54
	S3CR   volatile.Register32 // 0x58
	S3NDTR volatile.Register32 // 0x5C
	S3PAR  volatile.Register32 // 0x60
	S3M0AR volatile.Register32 // 0x64
	S3M1AR volatile.Register32 // 0x68
	S3FCR  volatile.Register32 // 0x6C
	S4CR   volatile.Register32 // 0x70
	S4NDTR volatile.Register32 // 0x74
	S4PAR  volatile.Register32 // 0x78
	S4M0AR volatile.Register32 // 0x7C
	S4M1AR volatile.Register32 // 0x80
	S4FCR  volatile.Register32 // 0x84
	S5CR   volatile.Register32 // 0x88
	S5NDTR volatile.Register32 // 0x8C
	S5PAR  volatile.Register32 // 0x90
	S5M0AR volatile.Register32 // 0x94
	S5M1AR volatile.Register32 // 0x98
	S5FCR  volatile.Register32 // 0x9C
	S6CR   volatile.Register32 // 0xA0
	S6NDTR volatile.Register32 // 0xA4
	S6PAR  volatile.Register32 // 0xA8
	S6M0AR volatile.Register32 // 0xAC
	S6M1AR volatile.Register32 // 0xB0
	S6FCR  volatile.Register32 // 0xB4
	S7CR   volatile.Register32 // 0xB8
	S7NDTR volatile.Register32 // 0xBC
	S7PAR  volatile.Register32 // 0xC0
	S7M0AR volatile.Register32 // 0xC4
	S7M1AR volatile.Register32 // 0xC8
	S7FCR  volatile.Register32 // 0xCC
}

// High Resolution Timer: Master Timers
type HRTIM_Type struct {
	MCR    volatile.Register32 // 0x0
	MISR   volatile.Register32 // 0x4
	MICR   volatile.Register32 // 0x8
	MDIER4 volatile.Register32 // 0xC
	MCNTR  volatile.Register32 // 0x10
	MPER   volatile.Register32 // 0x14
	MREP   volatile.Register32 // 0x18
	MCMP1R volatile.Register32 // 0x1C
	_      [4]byte
	MCMP2R volatile.Register32 // 0x24
	MCMP3R volatile.Register32 // 0x28
	MCMP4R volatile.Register32 // 0x2C
}

// Digital filter for sigma delta modulators
type DFSDM_Type struct {
	DFSDM_CHCFG0R1  volatile.Register32 // 0x0
	DFSDM_CHCFG1R1  volatile.Register32 // 0x4
	DFSDM_CHCFG2R1  volatile.Register32 // 0x8
	DFSDM_CHCFG3R1  volatile.Register32 // 0xC
	DFSDM_CHCFG4R1  volatile.Register32 // 0x10
	DFSDM_CHCFG5R1  volatile.Register32 // 0x14
	DFSDM_CHCFG6R1  volatile.Register32 // 0x18
	DFSDM_CHCFG7R1  volatile.Register32 // 0x1C
	DFSDM_CHCFG0R2  volatile.Register32 // 0x20
	DFSDM_CHCFG1R2  volatile.Register32 // 0x24
	DFSDM_CHCFG2R2  volatile.Register32 // 0x28
	DFSDM_CHCFG3R2  volatile.Register32 // 0x2C
	DFSDM_CHCFG4R2  volatile.Register32 // 0x30
	DFSDM_CHCFG5R2  volatile.Register32 // 0x34
	DFSDM_CHCFG6R2  volatile.Register32 // 0x38
	DFSDM_CHCFG7R2  volatile.Register32 // 0x3C
	DFSDM_AWSCD0R   volatile.Register32 // 0x40
	DFSDM_AWSCD1R   volatile.Register32 // 0x44
	DFSDM_AWSCD2R   volatile.Register32 // 0x48
	DFSDM_AWSCD3R   volatile.Register32 // 0x4C
	DFSDM_AWSCD4R   volatile.Register32 // 0x50
	DFSDM_AWSCD5R   volatile.Register32 // 0x54
	DFSDM_AWSCD6R   volatile.Register32 // 0x58
	DFSDM_AWSCD7R   volatile.Register32 // 0x5C
	DFSDM_CHWDAT0R  volatile.Register32 // 0x60
	DFSDM_CHWDAT1R  volatile.Register32 // 0x64
	DFSDM_CHWDAT2R  volatile.Register32 // 0x68
	DFSDM_CHWDAT3R  volatile.Register32 // 0x6C
	DFSDM_CHWDAT4R  volatile.Register32 // 0x70
	DFSDM_CHWDAT5R  volatile.Register32 // 0x74
	DFSDM_CHWDAT6R  volatile.Register32 // 0x78
	DFSDM_CHWDAT7R  volatile.Register32 // 0x7C
	DFSDM_CHDATIN0R volatile.Register32 // 0x80
	DFSDM_CHDATIN1R volatile.Register32 // 0x84
	DFSDM_CHDATIN2R volatile.Register32 // 0x88
	DFSDM_CHDATIN3R volatile.Register32 // 0x8C
	DFSDM_CHDATIN4R volatile.Register32 // 0x90
	DFSDM_CHDATIN5R volatile.Register32 // 0x94
	DFSDM_CHDATIN6R volatile.Register32 // 0x98
	DFSDM_CHDATIN7R volatile.Register32 // 0x9C
	DFSDM0_CR1      volatile.Register32 // 0xA0
	DFSDM1_CR1      volatile.Register32 // 0xA4
	DFSDM2_CR1      volatile.Register32 // 0xA8
	DFSDM3_CR1      volatile.Register32 // 0xAC
	DFSDM0_CR2      volatile.Register32 // 0xB0
	DFSDM1_CR2      volatile.Register32 // 0xB4
	DFSDM2_CR2      volatile.Register32 // 0xB8
	DFSDM3_CR2      volatile.Register32 // 0xBC
	DFSDM0_ISR      volatile.Register32 // 0xC0
	DFSDM1_ISR      volatile.Register32 // 0xC4
	DFSDM2_ISR      volatile.Register32 // 0xC8
	DFSDM3_ISR      volatile.Register32 // 0xCC
	DFSDM0_ICR      volatile.Register32 // 0xD0
	DFSDM1_ICR      volatile.Register32 // 0xD4
	DFSDM2_ICR      volatile.Register32 // 0xD8
	DFSDM3_ICR      volatile.Register32 // 0xDC
	DFSDM0_JCHGR    volatile.Register32 // 0xE0
	DFSDM1_JCHGR    volatile.Register32 // 0xE4
	DFSDM2_JCHGR    volatile.Register32 // 0xE8
	DFSDM3_JCHGR    volatile.Register32 // 0xEC
	DFSDM0_FCR      volatile.Register32 // 0xF0
	DFSDM1_FCR      volatile.Register32 // 0xF4
	DFSDM2_FCR      volatile.Register32 // 0xF8
	DFSDM3_FCR      volatile.Register32 // 0xFC
	DFSDM0_JDATAR   volatile.Register32 // 0x100
	DFSDM1_JDATAR   volatile.Register32 // 0x104
	DFSDM2_JDATAR   volatile.Register32 // 0x108
	DFSDM3_JDATAR   volatile.Register32 // 0x10C
	DFSDM0_RDATAR   volatile.Register32 // 0x110
	DFSDM1_RDATAR   volatile.Register32 // 0x114
	DFSDM2_RDATAR   volatile.Register32 // 0x118
	DFSDM3_RDATAR   volatile.Register32 // 0x11C
	DFSDM0_AWHTR    volatile.Register32 // 0x120
	DFSDM1_AWHTR    volatile.Register32 // 0x124
	DFSDM2_AWHTR    volatile.Register32 // 0x128
	DFSDM3_AWHTR    volatile.Register32 // 0x12C
	DFSDM0_AWLTR    volatile.Register32 // 0x130
	DFSDM1_AWLTR    volatile.Register32 // 0x134
	DFSDM2_AWLTR    volatile.Register32 // 0x138
	DFSDM3_AWLTR    volatile.Register32 // 0x13C
	DFSDM0_AWSR     volatile.Register32 // 0x140
	DFSDM1_AWSR     volatile.Register32 // 0x144
	DFSDM2_AWSR     volatile.Register32 // 0x148
	DFSDM3_AWSR     volatile.Register32 // 0x14C
	DFSDM0_AWCFR    volatile.Register32 // 0x150
	DFSDM1_AWCFR    volatile.Register32 // 0x154
	DFSDM2_AWCFR    volatile.Register32 // 0x158
	DFSDM3_AWCFR    volatile.Register32 // 0x15C
	DFSDM0_EXMAX    volatile.Register32 // 0x160
	DFSDM1_EXMAX    volatile.Register32 // 0x164
	DFSDM2_EXMAX    volatile.Register32 // 0x168
	DFSDM3_EXMAX    volatile.Register32 // 0x16C
	DFSDM0_EXMIN    volatile.Register32 // 0x170
	DFSDM1_EXMIN    volatile.Register32 // 0x174
	DFSDM2_EXMIN    volatile.Register32 // 0x178
	DFSDM3_EXMIN    volatile.Register32 // 0x17C
	DFSDM0_CNVTIMR  volatile.Register32 // 0x180
	DFSDM1_CNVTIMR  volatile.Register32 // 0x184
	DFSDM2_CNVTIMR  volatile.Register32 // 0x188
	DFSDM3_CNVTIMR  volatile.Register32 // 0x18C
}

// General-purpose-timers
type TIMs_Type struct {
	CR1          volatile.Register32 // 0x0
	CR2          volatile.Register32 // 0x4
	_            [4]byte
	DIER         volatile.Register32 // 0xC
	SR           volatile.Register32 // 0x10
	EGR          volatile.Register32 // 0x14
	CCMR1_Output volatile.Register32 // 0x18
	_            [4]byte
	CCER         volatile.Register32 // 0x20
	CNT          volatile.Register32 // 0x24
	PSC          volatile.Register32 // 0x28
	ARR          volatile.Register32 // 0x2C
	RCR          volatile.Register32 // 0x30
	CCR1         volatile.Register32 // 0x34
	_            [12]byte
	BDTR         volatile.Register32 // 0x44
	DCR          volatile.Register32 // 0x48
	DMAR         volatile.Register32 // 0x4C
	_            [16]byte
	TIM16_AF1    volatile.Register32 // 0x60
	_            [4]byte
	TIM16_TISEL  volatile.Register32 // 0x68
}

// Universal synchronous asynchronous receiver transmitter
type USART_Type struct {
	CR1   volatile.Register32 // 0x0
	CR2   volatile.Register32 // 0x4
	CR3   volatile.Register32 // 0x8
	BRR   volatile.Register32 // 0xC
	GTPR  volatile.Register32 // 0x10
	RTOR  volatile.Register32 // 0x14
	RQR   volatile.Register32 // 0x18
	ISR   volatile.Register32 // 0x1C
	ICR   volatile.Register32 // 0x20
	RDR   volatile.Register32 // 0x24
	TDR   volatile.Register32 // 0x28
	PRESC volatile.Register32 // 0x2C
}

// Advanced-timers
type TIM_Type struct {
	CR1          volatile.Register32 // 0x0
	CR2          volatile.Register32 // 0x4
	SMCR         volatile.Register32 // 0x8
	DIER         volatile.Register32 // 0xC
	SR           volatile.Register32 // 0x10
	EGR          volatile.Register32 // 0x14
	CCMR1_Output volatile.Register32 // 0x18
	CCMR2_Output volatile.Register32 // 0x1C
	CCER         volatile.Register32 // 0x20
	CNT          volatile.Register32 // 0x24
	PSC          volatile.Register32 // 0x28
	ARR          volatile.Register32 // 0x2C
	RCR          volatile.Register32 // 0x30
	CCR1         volatile.Register32 // 0x34
	CCR2         volatile.Register32 // 0x38
	CCR3         volatile.Register32 // 0x3C
	CCR4         volatile.Register32 // 0x40
	BDTR         volatile.Register32 // 0x44
	DCR          volatile.Register32 // 0x48
	DMAR         volatile.Register32 // 0x4C
	_            [4]byte
	CCMR3_Output volatile.Register32 // 0x54
	CCR5         volatile.Register32 // 0x58
	CRR6         volatile.Register32 // 0x5C
	AF1          volatile.Register32 // 0x60
	AF2          volatile.Register32 // 0x64
	TISEL        volatile.Register32 // 0x68
}

// FDCAN1
type FDCAN_Type struct {
	FDCAN_CREL   volatile.Register32 // 0x0
	FDCAN_ENDN   volatile.Register32 // 0x4
	_            [4]byte
	FDCAN_DBTP   volatile.Register32 // 0xC
	FDCAN_TEST   volatile.Register32 // 0x10
	FDCAN_RWD    volatile.Register32 // 0x14
	FDCAN_CCCR   volatile.Register32 // 0x18
	FDCAN_NBTP   volatile.Register32 // 0x1C
	FDCAN_TSCC   volatile.Register32 // 0x20
	FDCAN_TSCV   volatile.Register32 // 0x24
	FDCAN_TOCC   volatile.Register32 // 0x28
	FDCAN_TOCV   volatile.Register32 // 0x2C
	_            [16]byte
	FDCAN_ECR    volatile.Register32 // 0x40
	FDCAN_PSR    volatile.Register32 // 0x44
	FDCAN_TDCR   volatile.Register32 // 0x48
	_            [4]byte
	FDCAN_IR     volatile.Register32 // 0x50
	FDCAN_IE     volatile.Register32 // 0x54
	FDCAN_ILS    volatile.Register32 // 0x58
	FDCAN_ILE    volatile.Register32 // 0x5C
	_            [32]byte
	FDCAN_GFC    volatile.Register32 // 0x80
	FDCAN_SIDFC  volatile.Register32 // 0x84
	FDCAN_XIDFC  volatile.Register32 // 0x88
	_            [4]byte
	FDCAN_XIDAM  volatile.Register32 // 0x90
	FDCAN_HPMS   volatile.Register32 // 0x94
	FDCAN_NDAT1  volatile.Register32 // 0x98
	FDCAN_NDAT2  volatile.Register32 // 0x9C
	FDCAN_RXF0C  volatile.Register32 // 0xA0
	FDCAN_RXF0S  volatile.Register32 // 0xA4
	FDCAN_RXF0A  volatile.Register32 // 0xA8
	FDCAN_RXBC   volatile.Register32 // 0xAC
	FDCAN_RXF1C  volatile.Register32 // 0xB0
	FDCAN_RXF1S  volatile.Register32 // 0xB4
	FDCAN_RXF1A  volatile.Register32 // 0xB8
	FDCAN_RXESC  volatile.Register32 // 0xBC
	FDCAN_TXBC   volatile.Register32 // 0xC0
	FDCAN_TXFQS  volatile.Register32 // 0xC4
	FDCAN_TXESC  volatile.Register32 // 0xC8
	FDCAN_TXBRP  volatile.Register32 // 0xCC
	FDCAN_TXBAR  volatile.Register32 // 0xD0
	FDCAN_TXBCR  volatile.Register32 // 0xD4
	FDCAN_TXBTO  volatile.Register32 // 0xD8
	FDCAN_TXBCF  volatile.Register32 // 0xDC
	FDCAN_TXBTIE volatile.Register32 // 0xE0
	FDCAN_TXBCIE volatile.Register32 // 0xE4
	_            [8]byte
	FDCAN_TXEFC  volatile.Register32 // 0xF0
	FDCAN_TXEFS  volatile.Register32 // 0xF4
	FDCAN_TXEFA  volatile.Register32 // 0xF8
	_            [4]byte
	FDCAN_TTTMC  volatile.Register32 // 0x100
	FDCAN_TTRMC  volatile.Register32 // 0x104
	FDCAN_TTOCF  volatile.Register32 // 0x108
	FDCAN_TTMLM  volatile.Register32 // 0x10C
	FDCAN_TURCF  volatile.Register32 // 0x110
	FDCAN_TTOCN  volatile.Register32 // 0x114
	CAN_TTGTP    volatile.Register32 // 0x118
	FDCAN_TTTMK  volatile.Register32 // 0x11C
	FDCAN_TTIR   volatile.Register32 // 0x120
	FDCAN_TTIE   volatile.Register32 // 0x124
	FDCAN_TTILS  volatile.Register32 // 0x128
	FDCAN_TTOST  volatile.Register32 // 0x12C
	FDCAN_TURNA  volatile.Register32 // 0x130
	FDCAN_TTLGT  volatile.Register32 // 0x134
	FDCAN_TTCTC  volatile.Register32 // 0x138
	FDCAN_TTCPT  volatile.Register32 // 0x13C
	FDCAN_TTCSM  volatile.Register32 // 0x140
	_            [444]byte
	FDCAN_TTTS   volatile.Register32 // 0x300
}

// Management data input/output slave
type MDIOS_Type struct {
	CR      volatile.Register32 // 0x0
	WRFR    volatile.Register32 // 0x4
	CWRFR   volatile.Register32 // 0x8
	RDFR    volatile.Register32 // 0xC
	CRDFR   volatile.Register32 // 0x10
	SR      volatile.Register32 // 0x14
	CLRFR   volatile.Register32 // 0x18
	DINR0   volatile.Register32 // 0x1C
	DINR1   volatile.Register32 // 0x20
	DINR2   volatile.Register32 // 0x24
	DINR3   volatile.Register32 // 0x28
	DINR4   volatile.Register32 // 0x2C
	DINR5   volatile.Register32 // 0x30
	DINR6   volatile.Register32 // 0x34
	DINR7   volatile.Register32 // 0x38
	DINR8   volatile.Register32 // 0x3C
	DINR9   volatile.Register32 // 0x40
	DINR10  volatile.Register32 // 0x44
	DINR11  volatile.Register32 // 0x48
	DINR12  volatile.Register32 // 0x4C
	DINR13  volatile.Register32 // 0x50
	DINR14  volatile.Register32 // 0x54
	DINR15  volatile.Register32 // 0x58
	DINR16  volatile.Register32 // 0x5C
	DINR17  volatile.Register32 // 0x60
	DINR18  volatile.Register32 // 0x64
	DINR19  volatile.Register32 // 0x68
	DINR20  volatile.Register32 // 0x6C
	DINR21  volatile.Register32 // 0x70
	DINR22  volatile.Register32 // 0x74
	DINR23  volatile.Register32 // 0x78
	DINR24  volatile.Register32 // 0x7C
	DINR25  volatile.Register32 // 0x80
	DINR26  volatile.Register32 // 0x84
	DINR27  volatile.Register32 // 0x88
	DINR28  volatile.Register32 // 0x8C
	DINR29  volatile.Register32 // 0x90
	DINR30  volatile.Register32 // 0x94
	DINR31  volatile.Register32 // 0x98
	DOUTR0  volatile.Register32 // 0x9C
	DOUTR1  volatile.Register32 // 0xA0
	DOUTR2  volatile.Register32 // 0xA4
	DOUTR3  volatile.Register32 // 0xA8
	DOUTR4  volatile.Register32 // 0xAC
	DOUTR5  volatile.Register32 // 0xB0
	DOUTR6  volatile.Register32 // 0xB4
	DOUTR7  volatile.Register32 // 0xB8
	DOUTR8  volatile.Register32 // 0xBC
	DOUTR9  volatile.Register32 // 0xC0
	DOUTR10 volatile.Register32 // 0xC4
	DOUTR11 volatile.Register32 // 0xC8
	DOUTR12 volatile.Register32 // 0xCC
	DOUTR13 volatile.Register32 // 0xD0
	DOUTR14 volatile.Register32 // 0xD4
	DOUTR15 volatile.Register32 // 0xD8
	DOUTR16 volatile.Register32 // 0xDC
	DOUTR17 volatile.Register32 // 0xE0
	DOUTR18 volatile.Register32 // 0xE4
	DOUTR19 volatile.Register32 // 0xE8
	DOUTR20 volatile.Register32 // 0xEC
	DOUTR21 volatile.Register32 // 0xF0
	DOUTR22 volatile.Register32 // 0xF4
	DOUTR23 volatile.Register32 // 0xF8
	DOUTR24 volatile.Register32 // 0xFC
	DOUTR25 volatile.Register32 // 0x100
	DOUTR26 volatile.Register32 // 0x104
	DOUTR27 volatile.Register32 // 0x108
	DOUTR28 volatile.Register32 // 0x10C
	DOUTR29 volatile.Register32 // 0x110
	DOUTR30 volatile.Register32 // 0x114
	DOUTR31 volatile.Register32 // 0x118
}

// Operational amplifiers
type OPAMP_Type struct {
	OPAMP1_CSR   volatile.Register32 // 0x0
	OPAMP1_OTR   volatile.Register32 // 0x4
	OPAMP1_HSOTR volatile.Register32 // 0x8
	_            [4]byte
	OPAMP2_CSR   volatile.Register32 // 0x10
	OPAMP2_OTR   volatile.Register32 // 0x14
	OPAMP2_HSOTR volatile.Register32 // 0x18
}

// Single Wire Protocol Master Interface
type SWPMI_Type struct {
	CR  volatile.Register32 // 0x0
	BRR volatile.Register32 // 0x4
	_   [4]byte
	ISR volatile.Register32 // 0xC
	ICR volatile.Register32 // 0x10
	IER volatile.Register32 // 0x14
	RFL volatile.Register32 // 0x18
	TDR volatile.Register32 // 0x1C
	RDR volatile.Register32 // 0x20
	OR  volatile.Register32 // 0x24
}

// Nested Vectored Interrupt Controller
type NVIC_Type struct {
	ISER0 volatile.Register32 // 0x0
	ISER1 volatile.Register32 // 0x4
	ISER2 volatile.Register32 // 0x8
	ISER3 volatile.Register32 // 0xC
	ISER4 volatile.Register32 // 0x10
	_     [108]byte
	ICER0 volatile.Register32 // 0x80
	ICER1 volatile.Register32 // 0x84
	ICER2 volatile.Register32 // 0x88
	ICER3 volatile.Register32 // 0x8C
	ICER4 volatile.Register32 // 0x90
	_     [108]byte
	ISPR0 volatile.Register32 // 0x100
	ISPR1 volatile.Register32 // 0x104
	ISPR2 volatile.Register32 // 0x108
	ISPR3 volatile.Register32 // 0x10C
	ISPR4 volatile.Register32 // 0x110
	_     [108]byte
	ICPR0 volatile.Register32 // 0x180
	ICPR1 volatile.Register32 // 0x184
	ICPR2 volatile.Register32 // 0x188
	_     [52]byte
	ICPR3 volatile.Register32 // 0x1C0
	ICPR4 volatile.Register32 // 0x1C4
	_     [56]byte
	IABR0 volatile.Register32 // 0x200
	IABR1 volatile.Register32 // 0x204
	IABR2 volatile.Register32 // 0x208
	IABR3 volatile.Register32 // 0x20C
	IABR4 volatile.Register32 // 0x210
	_     [236]byte
	IPR0  volatile.Register32 // 0x300
	IPR1  volatile.Register32 // 0x304
	IPR2  volatile.Register32 // 0x308
	IPR3  volatile.Register32 // 0x30C
	IPR4  volatile.Register32 // 0x310
	IPR5  volatile.Register32 // 0x314
	IPR6  volatile.Register32 // 0x318
	IPR7  volatile.Register32 // 0x31C
	IPR8  volatile.Register32 // 0x320
	IPR9  volatile.Register32 // 0x324
	IPR10 volatile.Register32 // 0x328
	IPR11 volatile.Register32 // 0x32C
	IPR12 volatile.Register32 // 0x330
	IPR13 volatile.Register32 // 0x334
	IPR14 volatile.Register32 // 0x338
	IPR15 volatile.Register32 // 0x33C
	IPR16 volatile.Register32 // 0x340
	IPR17 volatile.Register32 // 0x344
	IPR18 volatile.Register32 // 0x348
	IPR19 volatile.Register32 // 0x34C
	IPR20 volatile.Register32 // 0x350
	IPR21 volatile.Register32 // 0x354
	IPR22 volatile.Register32 // 0x358
	IPR23 volatile.Register32 // 0x35C
	IPR24 volatile.Register32 // 0x360
	IPR25 volatile.Register32 // 0x364
	IPR26 volatile.Register32 // 0x368
	IPR27 volatile.Register32 // 0x36C
	IPR28 volatile.Register32 // 0x370
	IPR29 volatile.Register32 // 0x374
	IPR30 volatile.Register32 // 0x378
	IPR31 volatile.Register32 // 0x37C
	IPR32 volatile.Register32 // 0x380
	IPR33 volatile.Register32 // 0x384
	IPR34 volatile.Register32 // 0x388
	IPR35 volatile.Register32 // 0x38C
	IPR36 volatile.Register32 // 0x390
	IPR37 volatile.Register32 // 0x394
	IPR38 volatile.Register32 // 0x398
	IPR39 volatile.Register32 // 0x39C
}

// Memory protection unit
type MPU_Type struct {
	MPU_TYPER volatile.Register32 // 0x0
	MPU_CTRL  volatile.Register32 // 0x4
	MPU_RNR   volatile.Register32 // 0x8
	MPU_RBAR  volatile.Register32 // 0xC
	MPU_RASR  volatile.Register32 // 0x10
}

// SysTick timer
type STK_Type struct {
	CSR   volatile.Register32 // 0x0
	RVR   volatile.Register32 // 0x4
	CVR   volatile.Register32 // 0x8
	CALIB volatile.Register32 // 0xC
}

// Floating point unit CPACR
type FPU_Type struct {
	CPACR volatile.Register32 // 0x0
}

// System control block ACTLR
type SCB_Type struct {
	ACTRL volatile.Register32 // 0x0
}

// Processor features
type PF_Type struct {
	CLIDR  volatile.Register32 // 0x0
	CTR    volatile.Register32 // 0x4
	CCSIDR volatile.Register32 // 0x8
}

// Access control
type AC_Type struct {
	ITCMCR volatile.Register32 // 0x0
	DTCMCR volatile.Register32 // 0x4
	AHBPCR volatile.Register32 // 0x8
	CACR   volatile.Register32 // 0xC
	AHBSCR volatile.Register32 // 0x10
	_      [4]byte
	ABFSR  volatile.Register32 // 0x18
}

// Bitfields for COMP1: COMP1
const (
	// SR: Comparator status register
	COMP1_SR_C1VAL_Pos = 0x0     // Position of C1VAL field.
	COMP1_SR_C1VAL_Msk = 0x1     // Bit mask of C1VAL field.
	COMP1_SR_C1VAL     = 0x1     // Bit C1VAL.
	COMP1_SR_C2VAL_Pos = 0x1     // Position of C2VAL field.
	COMP1_SR_C2VAL_Msk = 0x2     // Bit mask of C2VAL field.
	COMP1_SR_C2VAL     = 0x2     // Bit C2VAL.
	COMP1_SR_C1IF_Pos  = 0x10    // Position of C1IF field.
	COMP1_SR_C1IF_Msk  = 0x10000 // Bit mask of C1IF field.
	COMP1_SR_C1IF      = 0x10000 // Bit C1IF.
	COMP1_SR_C2IF_Pos  = 0x11    // Position of C2IF field.
	COMP1_SR_C2IF_Msk  = 0x20000 // Bit mask of C2IF field.
	COMP1_SR_C2IF      = 0x20000 // Bit C2IF.

	// ICFR: Comparator interrupt clear flag           register
	COMP1_ICFR_CC1IF_Pos = 0x10    // Position of CC1IF field.
	COMP1_ICFR_CC1IF_Msk = 0x10000 // Bit mask of CC1IF field.
	COMP1_ICFR_CC1IF     = 0x10000 // Bit CC1IF.
	COMP1_ICFR_CC2IF_Pos = 0x11    // Position of CC2IF field.
	COMP1_ICFR_CC2IF_Msk = 0x20000 // Bit mask of CC2IF field.
	COMP1_ICFR_CC2IF     = 0x20000 // Bit CC2IF.

	// OR: Comparator option register
	COMP1_OR_AFOP_Pos = 0x0        // Position of AFOP field.
	COMP1_OR_AFOP_Msk = 0x7ff      // Bit mask of AFOP field.
	COMP1_OR_OR_Pos   = 0xb        // Position of OR field.
	COMP1_OR_OR_Msk   = 0xfffff800 // Bit mask of OR field.

	// CFGR1: Comparator configuration register           1
	COMP1_CFGR1_EN_Pos       = 0x0        // Position of EN field.
	COMP1_CFGR1_EN_Msk       = 0x1        // Bit mask of EN field.
	COMP1_CFGR1_EN           = 0x1        // Bit EN.
	COMP1_CFGR1_BRGEN_Pos    = 0x1        // Position of BRGEN field.
	COMP1_CFGR1_BRGEN_Msk    = 0x2        // Bit mask of BRGEN field.
	COMP1_CFGR1_BRGEN        = 0x2        // Bit BRGEN.
	COMP1_CFGR1_SCALEN_Pos   = 0x2        // Position of SCALEN field.
	COMP1_CFGR1_SCALEN_Msk   = 0x4        // Bit mask of SCALEN field.
	COMP1_CFGR1_SCALEN       = 0x4        // Bit SCALEN.
	COMP1_CFGR1_POLARITY_Pos = 0x3        // Position of POLARITY field.
	COMP1_CFGR1_POLARITY_Msk = 0x8        // Bit mask of POLARITY field.
	COMP1_CFGR1_POLARITY     = 0x8        // Bit POLARITY.
	COMP1_CFGR1_ITEN_Pos     = 0x6        // Position of ITEN field.
	COMP1_CFGR1_ITEN_Msk     = 0x40       // Bit mask of ITEN field.
	COMP1_CFGR1_ITEN         = 0x40       // Bit ITEN.
	COMP1_CFGR1_HYST_Pos     = 0x8        // Position of HYST field.
	COMP1_CFGR1_HYST_Msk     = 0x300      // Bit mask of HYST field.
	COMP1_CFGR1_PWRMODE_Pos  = 0xc        // Position of PWRMODE field.
	COMP1_CFGR1_PWRMODE_Msk  = 0x3000     // Bit mask of PWRMODE field.
	COMP1_CFGR1_INMSEL_Pos   = 0x10       // Position of INMSEL field.
	COMP1_CFGR1_INMSEL_Msk   = 0x70000    // Bit mask of INMSEL field.
	COMP1_CFGR1_INPSEL_Pos   = 0x14       // Position of INPSEL field.
	COMP1_CFGR1_INPSEL_Msk   = 0x100000   // Bit mask of INPSEL field.
	COMP1_CFGR1_INPSEL       = 0x100000   // Bit INPSEL.
	COMP1_CFGR1_BLANKING_Pos = 0x18       // Position of BLANKING field.
	COMP1_CFGR1_BLANKING_Msk = 0xf000000  // Bit mask of BLANKING field.
	COMP1_CFGR1_LOCK_Pos     = 0x1f       // Position of LOCK field.
	COMP1_CFGR1_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	COMP1_CFGR1_LOCK         = 0x80000000 // Bit LOCK.

	// CFGR2: Comparator configuration register           2
	COMP1_CFGR2_EN_Pos       = 0x0        // Position of EN field.
	COMP1_CFGR2_EN_Msk       = 0x1        // Bit mask of EN field.
	COMP1_CFGR2_EN           = 0x1        // Bit EN.
	COMP1_CFGR2_BRGEN_Pos    = 0x1        // Position of BRGEN field.
	COMP1_CFGR2_BRGEN_Msk    = 0x2        // Bit mask of BRGEN field.
	COMP1_CFGR2_BRGEN        = 0x2        // Bit BRGEN.
	COMP1_CFGR2_SCALEN_Pos   = 0x2        // Position of SCALEN field.
	COMP1_CFGR2_SCALEN_Msk   = 0x4        // Bit mask of SCALEN field.
	COMP1_CFGR2_SCALEN       = 0x4        // Bit SCALEN.
	COMP1_CFGR2_POLARITY_Pos = 0x3        // Position of POLARITY field.
	COMP1_CFGR2_POLARITY_Msk = 0x8        // Bit mask of POLARITY field.
	COMP1_CFGR2_POLARITY     = 0x8        // Bit POLARITY.
	COMP1_CFGR2_WINMODE_Pos  = 0x4        // Position of WINMODE field.
	COMP1_CFGR2_WINMODE_Msk  = 0x10       // Bit mask of WINMODE field.
	COMP1_CFGR2_WINMODE      = 0x10       // Bit WINMODE.
	COMP1_CFGR2_ITEN_Pos     = 0x6        // Position of ITEN field.
	COMP1_CFGR2_ITEN_Msk     = 0x40       // Bit mask of ITEN field.
	COMP1_CFGR2_ITEN         = 0x40       // Bit ITEN.
	COMP1_CFGR2_HYST_Pos     = 0x8        // Position of HYST field.
	COMP1_CFGR2_HYST_Msk     = 0x300      // Bit mask of HYST field.
	COMP1_CFGR2_PWRMODE_Pos  = 0xc        // Position of PWRMODE field.
	COMP1_CFGR2_PWRMODE_Msk  = 0x3000     // Bit mask of PWRMODE field.
	COMP1_CFGR2_INMSEL_Pos   = 0x10       // Position of INMSEL field.
	COMP1_CFGR2_INMSEL_Msk   = 0x70000    // Bit mask of INMSEL field.
	COMP1_CFGR2_INPSEL_Pos   = 0x14       // Position of INPSEL field.
	COMP1_CFGR2_INPSEL_Msk   = 0x100000   // Bit mask of INPSEL field.
	COMP1_CFGR2_INPSEL       = 0x100000   // Bit INPSEL.
	COMP1_CFGR2_BLANKING_Pos = 0x18       // Position of BLANKING field.
	COMP1_CFGR2_BLANKING_Msk = 0xf000000  // Bit mask of BLANKING field.
	COMP1_CFGR2_LOCK_Pos     = 0x1f       // Position of LOCK field.
	COMP1_CFGR2_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	COMP1_CFGR2_LOCK         = 0x80000000 // Bit LOCK.
)

// Bitfields for CRS: CRS
const (
	// CR: CRS control register
	CRS_CR_SYNCOKIE_Pos   = 0x0    // Position of SYNCOKIE field.
	CRS_CR_SYNCOKIE_Msk   = 0x1    // Bit mask of SYNCOKIE field.
	CRS_CR_SYNCOKIE       = 0x1    // Bit SYNCOKIE.
	CRS_CR_SYNCWARNIE_Pos = 0x1    // Position of SYNCWARNIE field.
	CRS_CR_SYNCWARNIE_Msk = 0x2    // Bit mask of SYNCWARNIE field.
	CRS_CR_SYNCWARNIE     = 0x2    // Bit SYNCWARNIE.
	CRS_CR_ERRIE_Pos      = 0x2    // Position of ERRIE field.
	CRS_CR_ERRIE_Msk      = 0x4    // Bit mask of ERRIE field.
	CRS_CR_ERRIE          = 0x4    // Bit ERRIE.
	CRS_CR_ESYNCIE_Pos    = 0x3    // Position of ESYNCIE field.
	CRS_CR_ESYNCIE_Msk    = 0x8    // Bit mask of ESYNCIE field.
	CRS_CR_ESYNCIE        = 0x8    // Bit ESYNCIE.
	CRS_CR_CEN_Pos        = 0x5    // Position of CEN field.
	CRS_CR_CEN_Msk        = 0x20   // Bit mask of CEN field.
	CRS_CR_CEN            = 0x20   // Bit CEN.
	CRS_CR_AUTOTRIMEN_Pos = 0x6    // Position of AUTOTRIMEN field.
	CRS_CR_AUTOTRIMEN_Msk = 0x40   // Bit mask of AUTOTRIMEN field.
	CRS_CR_AUTOTRIMEN     = 0x40   // Bit AUTOTRIMEN.
	CRS_CR_SWSYNC_Pos     = 0x7    // Position of SWSYNC field.
	CRS_CR_SWSYNC_Msk     = 0x80   // Bit mask of SWSYNC field.
	CRS_CR_SWSYNC         = 0x80   // Bit SWSYNC.
	CRS_CR_TRIM_Pos       = 0x8    // Position of TRIM field.
	CRS_CR_TRIM_Msk       = 0x3f00 // Bit mask of TRIM field.

	// CFGR: This register can be written only when the           frequency error counter is disabled (CEN bit is cleared           in CRS_CR). When the counter is enabled, this register is           write-protected.
	CRS_CFGR_RELOAD_Pos  = 0x0        // Position of RELOAD field.
	CRS_CFGR_RELOAD_Msk  = 0xffff     // Bit mask of RELOAD field.
	CRS_CFGR_FELIM_Pos   = 0x10       // Position of FELIM field.
	CRS_CFGR_FELIM_Msk   = 0xff0000   // Bit mask of FELIM field.
	CRS_CFGR_SYNCDIV_Pos = 0x18       // Position of SYNCDIV field.
	CRS_CFGR_SYNCDIV_Msk = 0x7000000  // Bit mask of SYNCDIV field.
	CRS_CFGR_SYNCSRC_Pos = 0x1c       // Position of SYNCSRC field.
	CRS_CFGR_SYNCSRC_Msk = 0x30000000 // Bit mask of SYNCSRC field.
	CRS_CFGR_SYNCPOL_Pos = 0x1f       // Position of SYNCPOL field.
	CRS_CFGR_SYNCPOL_Msk = 0x80000000 // Bit mask of SYNCPOL field.
	CRS_CFGR_SYNCPOL     = 0x80000000 // Bit SYNCPOL.

	// ISR: CRS interrupt and status           register
	CRS_ISR_SYNCOKF_Pos   = 0x0        // Position of SYNCOKF field.
	CRS_ISR_SYNCOKF_Msk   = 0x1        // Bit mask of SYNCOKF field.
	CRS_ISR_SYNCOKF       = 0x1        // Bit SYNCOKF.
	CRS_ISR_SYNCWARNF_Pos = 0x1        // Position of SYNCWARNF field.
	CRS_ISR_SYNCWARNF_Msk = 0x2        // Bit mask of SYNCWARNF field.
	CRS_ISR_SYNCWARNF     = 0x2        // Bit SYNCWARNF.
	CRS_ISR_ERRF_Pos      = 0x2        // Position of ERRF field.
	CRS_ISR_ERRF_Msk      = 0x4        // Bit mask of ERRF field.
	CRS_ISR_ERRF          = 0x4        // Bit ERRF.
	CRS_ISR_ESYNCF_Pos    = 0x3        // Position of ESYNCF field.
	CRS_ISR_ESYNCF_Msk    = 0x8        // Bit mask of ESYNCF field.
	CRS_ISR_ESYNCF        = 0x8        // Bit ESYNCF.
	CRS_ISR_SYNCERR_Pos   = 0x8        // Position of SYNCERR field.
	CRS_ISR_SYNCERR_Msk   = 0x100      // Bit mask of SYNCERR field.
	CRS_ISR_SYNCERR       = 0x100      // Bit SYNCERR.
	CRS_ISR_SYNCMISS_Pos  = 0x9        // Position of SYNCMISS field.
	CRS_ISR_SYNCMISS_Msk  = 0x200      // Bit mask of SYNCMISS field.
	CRS_ISR_SYNCMISS      = 0x200      // Bit SYNCMISS.
	CRS_ISR_TRIMOVF_Pos   = 0xa        // Position of TRIMOVF field.
	CRS_ISR_TRIMOVF_Msk   = 0x400      // Bit mask of TRIMOVF field.
	CRS_ISR_TRIMOVF       = 0x400      // Bit TRIMOVF.
	CRS_ISR_FEDIR_Pos     = 0xf        // Position of FEDIR field.
	CRS_ISR_FEDIR_Msk     = 0x8000     // Bit mask of FEDIR field.
	CRS_ISR_FEDIR         = 0x8000     // Bit FEDIR.
	CRS_ISR_FECAP_Pos     = 0x10       // Position of FECAP field.
	CRS_ISR_FECAP_Msk     = 0xffff0000 // Bit mask of FECAP field.

	// ICR: CRS interrupt flag clear           register
	CRS_ICR_SYNCOKC_Pos   = 0x0 // Position of SYNCOKC field.
	CRS_ICR_SYNCOKC_Msk   = 0x1 // Bit mask of SYNCOKC field.
	CRS_ICR_SYNCOKC       = 0x1 // Bit SYNCOKC.
	CRS_ICR_SYNCWARNC_Pos = 0x1 // Position of SYNCWARNC field.
	CRS_ICR_SYNCWARNC_Msk = 0x2 // Bit mask of SYNCWARNC field.
	CRS_ICR_SYNCWARNC     = 0x2 // Bit SYNCWARNC.
	CRS_ICR_ERRC_Pos      = 0x2 // Position of ERRC field.
	CRS_ICR_ERRC_Msk      = 0x4 // Bit mask of ERRC field.
	CRS_ICR_ERRC          = 0x4 // Bit ERRC.
	CRS_ICR_ESYNCC_Pos    = 0x3 // Position of ESYNCC field.
	CRS_ICR_ESYNCC_Msk    = 0x8 // Bit mask of ESYNCC field.
	CRS_ICR_ESYNCC        = 0x8 // Bit ESYNCC.
)

// Bitfields for DAC: DAC
const (
	// CR: DAC control register
	DAC_CR_EN1_Pos       = 0x0        // Position of EN1 field.
	DAC_CR_EN1_Msk       = 0x1        // Bit mask of EN1 field.
	DAC_CR_EN1           = 0x1        // Bit EN1.
	DAC_CR_TEN1_Pos      = 0x1        // Position of TEN1 field.
	DAC_CR_TEN1_Msk      = 0x2        // Bit mask of TEN1 field.
	DAC_CR_TEN1          = 0x2        // Bit TEN1.
	DAC_CR_TSEL1_Pos     = 0x2        // Position of TSEL1 field.
	DAC_CR_TSEL1_Msk     = 0x1c       // Bit mask of TSEL1 field.
	DAC_CR_WAVE1_Pos     = 0x6        // Position of WAVE1 field.
	DAC_CR_WAVE1_Msk     = 0xc0       // Bit mask of WAVE1 field.
	DAC_CR_MAMP1_Pos     = 0x8        // Position of MAMP1 field.
	DAC_CR_MAMP1_Msk     = 0xf00      // Bit mask of MAMP1 field.
	DAC_CR_DMAEN1_Pos    = 0xc        // Position of DMAEN1 field.
	DAC_CR_DMAEN1_Msk    = 0x1000     // Bit mask of DMAEN1 field.
	DAC_CR_DMAEN1        = 0x1000     // Bit DMAEN1.
	DAC_CR_DMAUDRIE1_Pos = 0xd        // Position of DMAUDRIE1 field.
	DAC_CR_DMAUDRIE1_Msk = 0x2000     // Bit mask of DMAUDRIE1 field.
	DAC_CR_DMAUDRIE1     = 0x2000     // Bit DMAUDRIE1.
	DAC_CR_CEN1_Pos      = 0xe        // Position of CEN1 field.
	DAC_CR_CEN1_Msk      = 0x4000     // Bit mask of CEN1 field.
	DAC_CR_CEN1          = 0x4000     // Bit CEN1.
	DAC_CR_EN2_Pos       = 0x10       // Position of EN2 field.
	DAC_CR_EN2_Msk       = 0x10000    // Bit mask of EN2 field.
	DAC_CR_EN2           = 0x10000    // Bit EN2.
	DAC_CR_TEN2_Pos      = 0x11       // Position of TEN2 field.
	DAC_CR_TEN2_Msk      = 0x20000    // Bit mask of TEN2 field.
	DAC_CR_TEN2          = 0x20000    // Bit TEN2.
	DAC_CR_TSEL2_Pos     = 0x12       // Position of TSEL2 field.
	DAC_CR_TSEL2_Msk     = 0x1c0000   // Bit mask of TSEL2 field.
	DAC_CR_WAVE2_Pos     = 0x16       // Position of WAVE2 field.
	DAC_CR_WAVE2_Msk     = 0xc00000   // Bit mask of WAVE2 field.
	DAC_CR_MAMP2_Pos     = 0x18       // Position of MAMP2 field.
	DAC_CR_MAMP2_Msk     = 0xf000000  // Bit mask of MAMP2 field.
	DAC_CR_DMAEN2_Pos    = 0x1c       // Position of DMAEN2 field.
	DAC_CR_DMAEN2_Msk    = 0x10000000 // Bit mask of DMAEN2 field.
	DAC_CR_DMAEN2        = 0x10000000 // Bit DMAEN2.
	DAC_CR_DMAUDRIE2_Pos = 0x1d       // Position of DMAUDRIE2 field.
	DAC_CR_DMAUDRIE2_Msk = 0x20000000 // Bit mask of DMAUDRIE2 field.
	DAC_CR_DMAUDRIE2     = 0x20000000 // Bit DMAUDRIE2.
	DAC_CR_CEN2_Pos      = 0x1e       // Position of CEN2 field.
	DAC_CR_CEN2_Msk      = 0x40000000 // Bit mask of CEN2 field.
	DAC_CR_CEN2          = 0x40000000 // Bit CEN2.

	// SWTRGR: DAC software trigger register
	DAC_SWTRGR_SWTRIG1_Pos = 0x0 // Position of SWTRIG1 field.
	DAC_SWTRGR_SWTRIG1_Msk = 0x1 // Bit mask of SWTRIG1 field.
	DAC_SWTRGR_SWTRIG1     = 0x1 // Bit SWTRIG1.
	DAC_SWTRGR_SWTRIG2_Pos = 0x1 // Position of SWTRIG2 field.
	DAC_SWTRGR_SWTRIG2_Msk = 0x2 // Bit mask of SWTRIG2 field.
	DAC_SWTRGR_SWTRIG2     = 0x2 // Bit SWTRIG2.

	// DHR12R1: DAC channel1 12-bit right-aligned data           holding register
	DAC_DHR12R1_DACC1DHR_Pos = 0x0   // Position of DACC1DHR field.
	DAC_DHR12R1_DACC1DHR_Msk = 0xfff // Bit mask of DACC1DHR field.

	// DHR12L1: DAC channel1 12-bit left aligned data           holding register
	DAC_DHR12L1_DACC1DHR_Pos = 0x4    // Position of DACC1DHR field.
	DAC_DHR12L1_DACC1DHR_Msk = 0xfff0 // Bit mask of DACC1DHR field.

	// DHR8R1: DAC channel1 8-bit right aligned data           holding register
	DAC_DHR8R1_DACC1DHR_Pos = 0x0  // Position of DACC1DHR field.
	DAC_DHR8R1_DACC1DHR_Msk = 0xff // Bit mask of DACC1DHR field.

	// DHR12R2: DAC channel2 12-bit right aligned data           holding register
	DAC_DHR12R2_DACC2DHR_Pos = 0x0   // Position of DACC2DHR field.
	DAC_DHR12R2_DACC2DHR_Msk = 0xfff // Bit mask of DACC2DHR field.

	// DHR12L2: DAC channel2 12-bit left aligned data           holding register
	DAC_DHR12L2_DACC2DHR_Pos = 0x4    // Position of DACC2DHR field.
	DAC_DHR12L2_DACC2DHR_Msk = 0xfff0 // Bit mask of DACC2DHR field.

	// DHR8R2: DAC channel2 8-bit right-aligned data           holding register
	DAC_DHR8R2_DACC2DHR_Pos = 0x0  // Position of DACC2DHR field.
	DAC_DHR8R2_DACC2DHR_Msk = 0xff // Bit mask of DACC2DHR field.

	// DHR12RD: Dual DAC 12-bit right-aligned data holding           register
	DAC_DHR12RD_DACC1DHR_Pos = 0x0       // Position of DACC1DHR field.
	DAC_DHR12RD_DACC1DHR_Msk = 0xfff     // Bit mask of DACC1DHR field.
	DAC_DHR12RD_DACC2DHR_Pos = 0x10      // Position of DACC2DHR field.
	DAC_DHR12RD_DACC2DHR_Msk = 0xfff0000 // Bit mask of DACC2DHR field.

	// DHR12LD: DUAL DAC 12-bit left aligned data holding           register
	DAC_DHR12LD_DACC1DHR_Pos = 0x4        // Position of DACC1DHR field.
	DAC_DHR12LD_DACC1DHR_Msk = 0xfff0     // Bit mask of DACC1DHR field.
	DAC_DHR12LD_DACC2DHR_Pos = 0x14       // Position of DACC2DHR field.
	DAC_DHR12LD_DACC2DHR_Msk = 0xfff00000 // Bit mask of DACC2DHR field.

	// DHR8RD: DUAL DAC 8-bit right aligned data holding           register
	DAC_DHR8RD_DACC1DHR_Pos = 0x0    // Position of DACC1DHR field.
	DAC_DHR8RD_DACC1DHR_Msk = 0xff   // Bit mask of DACC1DHR field.
	DAC_DHR8RD_DACC2DHR_Pos = 0x8    // Position of DACC2DHR field.
	DAC_DHR8RD_DACC2DHR_Msk = 0xff00 // Bit mask of DACC2DHR field.

	// DOR1: DAC channel1 data output           register
	DAC_DOR1_DACC1DOR_Pos = 0x0   // Position of DACC1DOR field.
	DAC_DOR1_DACC1DOR_Msk = 0xfff // Bit mask of DACC1DOR field.

	// DOR2: DAC channel2 data output           register
	DAC_DOR2_DACC2DOR_Pos = 0x0   // Position of DACC2DOR field.
	DAC_DOR2_DACC2DOR_Msk = 0xfff // Bit mask of DACC2DOR field.

	// SR: DAC status register
	DAC_SR_DMAUDR1_Pos   = 0xd        // Position of DMAUDR1 field.
	DAC_SR_DMAUDR1_Msk   = 0x2000     // Bit mask of DMAUDR1 field.
	DAC_SR_DMAUDR1       = 0x2000     // Bit DMAUDR1.
	DAC_SR_CAL_FLAG1_Pos = 0xe        // Position of CAL_FLAG1 field.
	DAC_SR_CAL_FLAG1_Msk = 0x4000     // Bit mask of CAL_FLAG1 field.
	DAC_SR_CAL_FLAG1     = 0x4000     // Bit CAL_FLAG1.
	DAC_SR_BWST1_Pos     = 0xf        // Position of BWST1 field.
	DAC_SR_BWST1_Msk     = 0x8000     // Bit mask of BWST1 field.
	DAC_SR_BWST1         = 0x8000     // Bit BWST1.
	DAC_SR_DMAUDR2_Pos   = 0x1d       // Position of DMAUDR2 field.
	DAC_SR_DMAUDR2_Msk   = 0x20000000 // Bit mask of DMAUDR2 field.
	DAC_SR_DMAUDR2       = 0x20000000 // Bit DMAUDR2.
	DAC_SR_CAL_FLAG2_Pos = 0x1e       // Position of CAL_FLAG2 field.
	DAC_SR_CAL_FLAG2_Msk = 0x40000000 // Bit mask of CAL_FLAG2 field.
	DAC_SR_CAL_FLAG2     = 0x40000000 // Bit CAL_FLAG2.
	DAC_SR_BWST2_Pos     = 0x1f       // Position of BWST2 field.
	DAC_SR_BWST2_Msk     = 0x80000000 // Bit mask of BWST2 field.
	DAC_SR_BWST2         = 0x80000000 // Bit BWST2.

	// CCR: DAC calibration control           register
	DAC_CCR_OTRIM1_Pos = 0x0      // Position of OTRIM1 field.
	DAC_CCR_OTRIM1_Msk = 0x1f     // Bit mask of OTRIM1 field.
	DAC_CCR_OTRIM2_Pos = 0x10     // Position of OTRIM2 field.
	DAC_CCR_OTRIM2_Msk = 0x1f0000 // Bit mask of OTRIM2 field.

	// MCR: DAC mode control register
	DAC_MCR_MODE1_Pos = 0x0     // Position of MODE1 field.
	DAC_MCR_MODE1_Msk = 0x7     // Bit mask of MODE1 field.
	DAC_MCR_MODE2_Pos = 0x10    // Position of MODE2 field.
	DAC_MCR_MODE2_Msk = 0x70000 // Bit mask of MODE2 field.

	// SHSR1: DAC Sample and Hold sample time register           1
	DAC_SHSR1_TSAMPLE1_Pos = 0x0   // Position of TSAMPLE1 field.
	DAC_SHSR1_TSAMPLE1_Msk = 0x3ff // Bit mask of TSAMPLE1 field.

	// SHSR2: DAC Sample and Hold sample time register           2
	DAC_SHSR2_TSAMPLE2_Pos = 0x0   // Position of TSAMPLE2 field.
	DAC_SHSR2_TSAMPLE2_Msk = 0x3ff // Bit mask of TSAMPLE2 field.

	// SHHR: DAC Sample and Hold hold time           register
	DAC_SHHR_THOLD1_Pos = 0x0       // Position of THOLD1 field.
	DAC_SHHR_THOLD1_Msk = 0x3ff     // Bit mask of THOLD1 field.
	DAC_SHHR_THOLD2_Pos = 0x10      // Position of THOLD2 field.
	DAC_SHHR_THOLD2_Msk = 0x3ff0000 // Bit mask of THOLD2 field.

	// SHRR: DAC Sample and Hold refresh time           register
	DAC_SHRR_TREFRESH1_Pos = 0x0      // Position of TREFRESH1 field.
	DAC_SHRR_TREFRESH1_Msk = 0xff     // Bit mask of TREFRESH1 field.
	DAC_SHRR_TREFRESH2_Pos = 0x10     // Position of TREFRESH2 field.
	DAC_SHRR_TREFRESH2_Msk = 0xff0000 // Bit mask of TREFRESH2 field.
)

// Bitfields for BDMA: BDMA
const (
	// ISR: DMA interrupt status register
	BDMA_ISR_GIF1_Pos  = 0x0        // Position of GIF1 field.
	BDMA_ISR_GIF1_Msk  = 0x1        // Bit mask of GIF1 field.
	BDMA_ISR_GIF1      = 0x1        // Bit GIF1.
	BDMA_ISR_TCIF1_Pos = 0x1        // Position of TCIF1 field.
	BDMA_ISR_TCIF1_Msk = 0x2        // Bit mask of TCIF1 field.
	BDMA_ISR_TCIF1     = 0x2        // Bit TCIF1.
	BDMA_ISR_HTIF1_Pos = 0x2        // Position of HTIF1 field.
	BDMA_ISR_HTIF1_Msk = 0x4        // Bit mask of HTIF1 field.
	BDMA_ISR_HTIF1     = 0x4        // Bit HTIF1.
	BDMA_ISR_TEIF1_Pos = 0x3        // Position of TEIF1 field.
	BDMA_ISR_TEIF1_Msk = 0x8        // Bit mask of TEIF1 field.
	BDMA_ISR_TEIF1     = 0x8        // Bit TEIF1.
	BDMA_ISR_GIF2_Pos  = 0x4        // Position of GIF2 field.
	BDMA_ISR_GIF2_Msk  = 0x10       // Bit mask of GIF2 field.
	BDMA_ISR_GIF2      = 0x10       // Bit GIF2.
	BDMA_ISR_TCIF2_Pos = 0x5        // Position of TCIF2 field.
	BDMA_ISR_TCIF2_Msk = 0x20       // Bit mask of TCIF2 field.
	BDMA_ISR_TCIF2     = 0x20       // Bit TCIF2.
	BDMA_ISR_HTIF2_Pos = 0x6        // Position of HTIF2 field.
	BDMA_ISR_HTIF2_Msk = 0x40       // Bit mask of HTIF2 field.
	BDMA_ISR_HTIF2     = 0x40       // Bit HTIF2.
	BDMA_ISR_TEIF2_Pos = 0x7        // Position of TEIF2 field.
	BDMA_ISR_TEIF2_Msk = 0x80       // Bit mask of TEIF2 field.
	BDMA_ISR_TEIF2     = 0x80       // Bit TEIF2.
	BDMA_ISR_GIF3_Pos  = 0x8        // Position of GIF3 field.
	BDMA_ISR_GIF3_Msk  = 0x100      // Bit mask of GIF3 field.
	BDMA_ISR_GIF3      = 0x100      // Bit GIF3.
	BDMA_ISR_TCIF3_Pos = 0x9        // Position of TCIF3 field.
	BDMA_ISR_TCIF3_Msk = 0x200      // Bit mask of TCIF3 field.
	BDMA_ISR_TCIF3     = 0x200      // Bit TCIF3.
	BDMA_ISR_HTIF3_Pos = 0xa        // Position of HTIF3 field.
	BDMA_ISR_HTIF3_Msk = 0x400      // Bit mask of HTIF3 field.
	BDMA_ISR_HTIF3     = 0x400      // Bit HTIF3.
	BDMA_ISR_TEIF3_Pos = 0xb        // Position of TEIF3 field.
	BDMA_ISR_TEIF3_Msk = 0x800      // Bit mask of TEIF3 field.
	BDMA_ISR_TEIF3     = 0x800      // Bit TEIF3.
	BDMA_ISR_GIF4_Pos  = 0xc        // Position of GIF4 field.
	BDMA_ISR_GIF4_Msk  = 0x1000     // Bit mask of GIF4 field.
	BDMA_ISR_GIF4      = 0x1000     // Bit GIF4.
	BDMA_ISR_TCIF4_Pos = 0xd        // Position of TCIF4 field.
	BDMA_ISR_TCIF4_Msk = 0x2000     // Bit mask of TCIF4 field.
	BDMA_ISR_TCIF4     = 0x2000     // Bit TCIF4.
	BDMA_ISR_HTIF4_Pos = 0xe        // Position of HTIF4 field.
	BDMA_ISR_HTIF4_Msk = 0x4000     // Bit mask of HTIF4 field.
	BDMA_ISR_HTIF4     = 0x4000     // Bit HTIF4.
	BDMA_ISR_TEIF4_Pos = 0xf        // Position of TEIF4 field.
	BDMA_ISR_TEIF4_Msk = 0x8000     // Bit mask of TEIF4 field.
	BDMA_ISR_TEIF4     = 0x8000     // Bit TEIF4.
	BDMA_ISR_GIF5_Pos  = 0x10       // Position of GIF5 field.
	BDMA_ISR_GIF5_Msk  = 0x10000    // Bit mask of GIF5 field.
	BDMA_ISR_GIF5      = 0x10000    // Bit GIF5.
	BDMA_ISR_TCIF5_Pos = 0x11       // Position of TCIF5 field.
	BDMA_ISR_TCIF5_Msk = 0x20000    // Bit mask of TCIF5 field.
	BDMA_ISR_TCIF5     = 0x20000    // Bit TCIF5.
	BDMA_ISR_HTIF5_Pos = 0x12       // Position of HTIF5 field.
	BDMA_ISR_HTIF5_Msk = 0x40000    // Bit mask of HTIF5 field.
	BDMA_ISR_HTIF5     = 0x40000    // Bit HTIF5.
	BDMA_ISR_TEIF5_Pos = 0x13       // Position of TEIF5 field.
	BDMA_ISR_TEIF5_Msk = 0x80000    // Bit mask of TEIF5 field.
	BDMA_ISR_TEIF5     = 0x80000    // Bit TEIF5.
	BDMA_ISR_GIF6_Pos  = 0x14       // Position of GIF6 field.
	BDMA_ISR_GIF6_Msk  = 0x100000   // Bit mask of GIF6 field.
	BDMA_ISR_GIF6      = 0x100000   // Bit GIF6.
	BDMA_ISR_TCIF6_Pos = 0x15       // Position of TCIF6 field.
	BDMA_ISR_TCIF6_Msk = 0x200000   // Bit mask of TCIF6 field.
	BDMA_ISR_TCIF6     = 0x200000   // Bit TCIF6.
	BDMA_ISR_HTIF6_Pos = 0x16       // Position of HTIF6 field.
	BDMA_ISR_HTIF6_Msk = 0x400000   // Bit mask of HTIF6 field.
	BDMA_ISR_HTIF6     = 0x400000   // Bit HTIF6.
	BDMA_ISR_TEIF6_Pos = 0x17       // Position of TEIF6 field.
	BDMA_ISR_TEIF6_Msk = 0x800000   // Bit mask of TEIF6 field.
	BDMA_ISR_TEIF6     = 0x800000   // Bit TEIF6.
	BDMA_ISR_GIF7_Pos  = 0x18       // Position of GIF7 field.
	BDMA_ISR_GIF7_Msk  = 0x1000000  // Bit mask of GIF7 field.
	BDMA_ISR_GIF7      = 0x1000000  // Bit GIF7.
	BDMA_ISR_TCIF7_Pos = 0x19       // Position of TCIF7 field.
	BDMA_ISR_TCIF7_Msk = 0x2000000  // Bit mask of TCIF7 field.
	BDMA_ISR_TCIF7     = 0x2000000  // Bit TCIF7.
	BDMA_ISR_HTIF7_Pos = 0x1a       // Position of HTIF7 field.
	BDMA_ISR_HTIF7_Msk = 0x4000000  // Bit mask of HTIF7 field.
	BDMA_ISR_HTIF7     = 0x4000000  // Bit HTIF7.
	BDMA_ISR_TEIF7_Pos = 0x1b       // Position of TEIF7 field.
	BDMA_ISR_TEIF7_Msk = 0x8000000  // Bit mask of TEIF7 field.
	BDMA_ISR_TEIF7     = 0x8000000  // Bit TEIF7.
	BDMA_ISR_GIF8_Pos  = 0x1c       // Position of GIF8 field.
	BDMA_ISR_GIF8_Msk  = 0x10000000 // Bit mask of GIF8 field.
	BDMA_ISR_GIF8      = 0x10000000 // Bit GIF8.
	BDMA_ISR_TCIF8_Pos = 0x1d       // Position of TCIF8 field.
	BDMA_ISR_TCIF8_Msk = 0x20000000 // Bit mask of TCIF8 field.
	BDMA_ISR_TCIF8     = 0x20000000 // Bit TCIF8.
	BDMA_ISR_HTIF8_Pos = 0x1e       // Position of HTIF8 field.
	BDMA_ISR_HTIF8_Msk = 0x40000000 // Bit mask of HTIF8 field.
	BDMA_ISR_HTIF8     = 0x40000000 // Bit HTIF8.
	BDMA_ISR_TEIF8_Pos = 0x1f       // Position of TEIF8 field.
	BDMA_ISR_TEIF8_Msk = 0x80000000 // Bit mask of TEIF8 field.
	BDMA_ISR_TEIF8     = 0x80000000 // Bit TEIF8.

	// IFCR: DMA interrupt flag clear           register
	BDMA_IFCR_CGIF1_Pos  = 0x0        // Position of CGIF1 field.
	BDMA_IFCR_CGIF1_Msk  = 0x1        // Bit mask of CGIF1 field.
	BDMA_IFCR_CGIF1      = 0x1        // Bit CGIF1.
	BDMA_IFCR_CTCIF1_Pos = 0x1        // Position of CTCIF1 field.
	BDMA_IFCR_CTCIF1_Msk = 0x2        // Bit mask of CTCIF1 field.
	BDMA_IFCR_CTCIF1     = 0x2        // Bit CTCIF1.
	BDMA_IFCR_CHTIF1_Pos = 0x2        // Position of CHTIF1 field.
	BDMA_IFCR_CHTIF1_Msk = 0x4        // Bit mask of CHTIF1 field.
	BDMA_IFCR_CHTIF1     = 0x4        // Bit CHTIF1.
	BDMA_IFCR_CTEIF1_Pos = 0x3        // Position of CTEIF1 field.
	BDMA_IFCR_CTEIF1_Msk = 0x8        // Bit mask of CTEIF1 field.
	BDMA_IFCR_CTEIF1     = 0x8        // Bit CTEIF1.
	BDMA_IFCR_CGIF2_Pos  = 0x4        // Position of CGIF2 field.
	BDMA_IFCR_CGIF2_Msk  = 0x10       // Bit mask of CGIF2 field.
	BDMA_IFCR_CGIF2      = 0x10       // Bit CGIF2.
	BDMA_IFCR_CTCIF2_Pos = 0x5        // Position of CTCIF2 field.
	BDMA_IFCR_CTCIF2_Msk = 0x20       // Bit mask of CTCIF2 field.
	BDMA_IFCR_CTCIF2     = 0x20       // Bit CTCIF2.
	BDMA_IFCR_CHTIF2_Pos = 0x6        // Position of CHTIF2 field.
	BDMA_IFCR_CHTIF2_Msk = 0x40       // Bit mask of CHTIF2 field.
	BDMA_IFCR_CHTIF2     = 0x40       // Bit CHTIF2.
	BDMA_IFCR_CTEIF2_Pos = 0x7        // Position of CTEIF2 field.
	BDMA_IFCR_CTEIF2_Msk = 0x80       // Bit mask of CTEIF2 field.
	BDMA_IFCR_CTEIF2     = 0x80       // Bit CTEIF2.
	BDMA_IFCR_CGIF3_Pos  = 0x8        // Position of CGIF3 field.
	BDMA_IFCR_CGIF3_Msk  = 0x100      // Bit mask of CGIF3 field.
	BDMA_IFCR_CGIF3      = 0x100      // Bit CGIF3.
	BDMA_IFCR_CTCIF3_Pos = 0x9        // Position of CTCIF3 field.
	BDMA_IFCR_CTCIF3_Msk = 0x200      // Bit mask of CTCIF3 field.
	BDMA_IFCR_CTCIF3     = 0x200      // Bit CTCIF3.
	BDMA_IFCR_CHTIF3_Pos = 0xa        // Position of CHTIF3 field.
	BDMA_IFCR_CHTIF3_Msk = 0x400      // Bit mask of CHTIF3 field.
	BDMA_IFCR_CHTIF3     = 0x400      // Bit CHTIF3.
	BDMA_IFCR_CTEIF3_Pos = 0xb        // Position of CTEIF3 field.
	BDMA_IFCR_CTEIF3_Msk = 0x800      // Bit mask of CTEIF3 field.
	BDMA_IFCR_CTEIF3     = 0x800      // Bit CTEIF3.
	BDMA_IFCR_CGIF4_Pos  = 0xc        // Position of CGIF4 field.
	BDMA_IFCR_CGIF4_Msk  = 0x1000     // Bit mask of CGIF4 field.
	BDMA_IFCR_CGIF4      = 0x1000     // Bit CGIF4.
	BDMA_IFCR_CTCIF4_Pos = 0xd        // Position of CTCIF4 field.
	BDMA_IFCR_CTCIF4_Msk = 0x2000     // Bit mask of CTCIF4 field.
	BDMA_IFCR_CTCIF4     = 0x2000     // Bit CTCIF4.
	BDMA_IFCR_CHTIF4_Pos = 0xe        // Position of CHTIF4 field.
	BDMA_IFCR_CHTIF4_Msk = 0x4000     // Bit mask of CHTIF4 field.
	BDMA_IFCR_CHTIF4     = 0x4000     // Bit CHTIF4.
	BDMA_IFCR_CTEIF4_Pos = 0xf        // Position of CTEIF4 field.
	BDMA_IFCR_CTEIF4_Msk = 0x8000     // Bit mask of CTEIF4 field.
	BDMA_IFCR_CTEIF4     = 0x8000     // Bit CTEIF4.
	BDMA_IFCR_CGIF5_Pos  = 0x10       // Position of CGIF5 field.
	BDMA_IFCR_CGIF5_Msk  = 0x10000    // Bit mask of CGIF5 field.
	BDMA_IFCR_CGIF5      = 0x10000    // Bit CGIF5.
	BDMA_IFCR_CTCIF5_Pos = 0x11       // Position of CTCIF5 field.
	BDMA_IFCR_CTCIF5_Msk = 0x20000    // Bit mask of CTCIF5 field.
	BDMA_IFCR_CTCIF5     = 0x20000    // Bit CTCIF5.
	BDMA_IFCR_CHTIF5_Pos = 0x12       // Position of CHTIF5 field.
	BDMA_IFCR_CHTIF5_Msk = 0x40000    // Bit mask of CHTIF5 field.
	BDMA_IFCR_CHTIF5     = 0x40000    // Bit CHTIF5.
	BDMA_IFCR_CTEIF5_Pos = 0x13       // Position of CTEIF5 field.
	BDMA_IFCR_CTEIF5_Msk = 0x80000    // Bit mask of CTEIF5 field.
	BDMA_IFCR_CTEIF5     = 0x80000    // Bit CTEIF5.
	BDMA_IFCR_CGIF6_Pos  = 0x14       // Position of CGIF6 field.
	BDMA_IFCR_CGIF6_Msk  = 0x100000   // Bit mask of CGIF6 field.
	BDMA_IFCR_CGIF6      = 0x100000   // Bit CGIF6.
	BDMA_IFCR_CTCIF6_Pos = 0x15       // Position of CTCIF6 field.
	BDMA_IFCR_CTCIF6_Msk = 0x200000   // Bit mask of CTCIF6 field.
	BDMA_IFCR_CTCIF6     = 0x200000   // Bit CTCIF6.
	BDMA_IFCR_CHTIF6_Pos = 0x16       // Position of CHTIF6 field.
	BDMA_IFCR_CHTIF6_Msk = 0x400000   // Bit mask of CHTIF6 field.
	BDMA_IFCR_CHTIF6     = 0x400000   // Bit CHTIF6.
	BDMA_IFCR_CTEIF6_Pos = 0x17       // Position of CTEIF6 field.
	BDMA_IFCR_CTEIF6_Msk = 0x800000   // Bit mask of CTEIF6 field.
	BDMA_IFCR_CTEIF6     = 0x800000   // Bit CTEIF6.
	BDMA_IFCR_CGIF7_Pos  = 0x18       // Position of CGIF7 field.
	BDMA_IFCR_CGIF7_Msk  = 0x1000000  // Bit mask of CGIF7 field.
	BDMA_IFCR_CGIF7      = 0x1000000  // Bit CGIF7.
	BDMA_IFCR_CTCIF7_Pos = 0x19       // Position of CTCIF7 field.
	BDMA_IFCR_CTCIF7_Msk = 0x2000000  // Bit mask of CTCIF7 field.
	BDMA_IFCR_CTCIF7     = 0x2000000  // Bit CTCIF7.
	BDMA_IFCR_CHTIF7_Pos = 0x1a       // Position of CHTIF7 field.
	BDMA_IFCR_CHTIF7_Msk = 0x4000000  // Bit mask of CHTIF7 field.
	BDMA_IFCR_CHTIF7     = 0x4000000  // Bit CHTIF7.
	BDMA_IFCR_CTEIF7_Pos = 0x1b       // Position of CTEIF7 field.
	BDMA_IFCR_CTEIF7_Msk = 0x8000000  // Bit mask of CTEIF7 field.
	BDMA_IFCR_CTEIF7     = 0x8000000  // Bit CTEIF7.
	BDMA_IFCR_CGIF8_Pos  = 0x1c       // Position of CGIF8 field.
	BDMA_IFCR_CGIF8_Msk  = 0x10000000 // Bit mask of CGIF8 field.
	BDMA_IFCR_CGIF8      = 0x10000000 // Bit CGIF8.
	BDMA_IFCR_CTCIF8_Pos = 0x1d       // Position of CTCIF8 field.
	BDMA_IFCR_CTCIF8_Msk = 0x20000000 // Bit mask of CTCIF8 field.
	BDMA_IFCR_CTCIF8     = 0x20000000 // Bit CTCIF8.
	BDMA_IFCR_CHTIF8_Pos = 0x1e       // Position of CHTIF8 field.
	BDMA_IFCR_CHTIF8_Msk = 0x40000000 // Bit mask of CHTIF8 field.
	BDMA_IFCR_CHTIF8     = 0x40000000 // Bit CHTIF8.
	BDMA_IFCR_CTEIF8_Pos = 0x1f       // Position of CTEIF8 field.
	BDMA_IFCR_CTEIF8_Msk = 0x80000000 // Bit mask of CTEIF8 field.
	BDMA_IFCR_CTEIF8     = 0x80000000 // Bit CTEIF8.

	// CCR1: DMA channel x configuration           register
	BDMA_CCR1_EN_Pos      = 0x0    // Position of EN field.
	BDMA_CCR1_EN_Msk      = 0x1    // Bit mask of EN field.
	BDMA_CCR1_EN          = 0x1    // Bit EN.
	BDMA_CCR1_TCIE_Pos    = 0x1    // Position of TCIE field.
	BDMA_CCR1_TCIE_Msk    = 0x2    // Bit mask of TCIE field.
	BDMA_CCR1_TCIE        = 0x2    // Bit TCIE.
	BDMA_CCR1_HTIE_Pos    = 0x2    // Position of HTIE field.
	BDMA_CCR1_HTIE_Msk    = 0x4    // Bit mask of HTIE field.
	BDMA_CCR1_HTIE        = 0x4    // Bit HTIE.
	BDMA_CCR1_TEIE_Pos    = 0x3    // Position of TEIE field.
	BDMA_CCR1_TEIE_Msk    = 0x8    // Bit mask of TEIE field.
	BDMA_CCR1_TEIE        = 0x8    // Bit TEIE.
	BDMA_CCR1_DIR_Pos     = 0x4    // Position of DIR field.
	BDMA_CCR1_DIR_Msk     = 0x10   // Bit mask of DIR field.
	BDMA_CCR1_DIR         = 0x10   // Bit DIR.
	BDMA_CCR1_CIRC_Pos    = 0x5    // Position of CIRC field.
	BDMA_CCR1_CIRC_Msk    = 0x20   // Bit mask of CIRC field.
	BDMA_CCR1_CIRC        = 0x20   // Bit CIRC.
	BDMA_CCR1_PINC_Pos    = 0x6    // Position of PINC field.
	BDMA_CCR1_PINC_Msk    = 0x40   // Bit mask of PINC field.
	BDMA_CCR1_PINC        = 0x40   // Bit PINC.
	BDMA_CCR1_MINC_Pos    = 0x7    // Position of MINC field.
	BDMA_CCR1_MINC_Msk    = 0x80   // Bit mask of MINC field.
	BDMA_CCR1_MINC        = 0x80   // Bit MINC.
	BDMA_CCR1_PSIZE_Pos   = 0x8    // Position of PSIZE field.
	BDMA_CCR1_PSIZE_Msk   = 0x300  // Bit mask of PSIZE field.
	BDMA_CCR1_MSIZE_Pos   = 0xa    // Position of MSIZE field.
	BDMA_CCR1_MSIZE_Msk   = 0xc00  // Bit mask of MSIZE field.
	BDMA_CCR1_PL_Pos      = 0xc    // Position of PL field.
	BDMA_CCR1_PL_Msk      = 0x3000 // Bit mask of PL field.
	BDMA_CCR1_MEM2MEM_Pos = 0xe    // Position of MEM2MEM field.
	BDMA_CCR1_MEM2MEM_Msk = 0x4000 // Bit mask of MEM2MEM field.
	BDMA_CCR1_MEM2MEM     = 0x4000 // Bit MEM2MEM.

	// CNDTR1: DMA channel x number of data           register
	BDMA_CNDTR1_NDT_Pos = 0x0    // Position of NDT field.
	BDMA_CNDTR1_NDT_Msk = 0xffff // Bit mask of NDT field.

	// CPAR1: This register must not be written when the           channel is enabled.
	BDMA_CPAR1_PA_Pos = 0x0        // Position of PA field.
	BDMA_CPAR1_PA_Msk = 0xffffffff // Bit mask of PA field.

	// CMAR1: This register must not be written when the           channel is enabled.
	BDMA_CMAR1_MA_Pos = 0x0        // Position of MA field.
	BDMA_CMAR1_MA_Msk = 0xffffffff // Bit mask of MA field.

	// CCR2: DMA channel x configuration           register
	BDMA_CCR2_EN_Pos      = 0x0    // Position of EN field.
	BDMA_CCR2_EN_Msk      = 0x1    // Bit mask of EN field.
	BDMA_CCR2_EN          = 0x1    // Bit EN.
	BDMA_CCR2_TCIE_Pos    = 0x1    // Position of TCIE field.
	BDMA_CCR2_TCIE_Msk    = 0x2    // Bit mask of TCIE field.
	BDMA_CCR2_TCIE        = 0x2    // Bit TCIE.
	BDMA_CCR2_HTIE_Pos    = 0x2    // Position of HTIE field.
	BDMA_CCR2_HTIE_Msk    = 0x4    // Bit mask of HTIE field.
	BDMA_CCR2_HTIE        = 0x4    // Bit HTIE.
	BDMA_CCR2_TEIE_Pos    = 0x3    // Position of TEIE field.
	BDMA_CCR2_TEIE_Msk    = 0x8    // Bit mask of TEIE field.
	BDMA_CCR2_TEIE        = 0x8    // Bit TEIE.
	BDMA_CCR2_DIR_Pos     = 0x4    // Position of DIR field.
	BDMA_CCR2_DIR_Msk     = 0x10   // Bit mask of DIR field.
	BDMA_CCR2_DIR         = 0x10   // Bit DIR.
	BDMA_CCR2_CIRC_Pos    = 0x5    // Position of CIRC field.
	BDMA_CCR2_CIRC_Msk    = 0x20   // Bit mask of CIRC field.
	BDMA_CCR2_CIRC        = 0x20   // Bit CIRC.
	BDMA_CCR2_PINC_Pos    = 0x6    // Position of PINC field.
	BDMA_CCR2_PINC_Msk    = 0x40   // Bit mask of PINC field.
	BDMA_CCR2_PINC        = 0x40   // Bit PINC.
	BDMA_CCR2_MINC_Pos    = 0x7    // Position of MINC field.
	BDMA_CCR2_MINC_Msk    = 0x80   // Bit mask of MINC field.
	BDMA_CCR2_MINC        = 0x80   // Bit MINC.
	BDMA_CCR2_PSIZE_Pos   = 0x8    // Position of PSIZE field.
	BDMA_CCR2_PSIZE_Msk   = 0x300  // Bit mask of PSIZE field.
	BDMA_CCR2_MSIZE_Pos   = 0xa    // Position of MSIZE field.
	BDMA_CCR2_MSIZE_Msk   = 0xc00  // Bit mask of MSIZE field.
	BDMA_CCR2_PL_Pos      = 0xc    // Position of PL field.
	BDMA_CCR2_PL_Msk      = 0x3000 // Bit mask of PL field.
	BDMA_CCR2_MEM2MEM_Pos = 0xe    // Position of MEM2MEM field.
	BDMA_CCR2_MEM2MEM_Msk = 0x4000 // Bit mask of MEM2MEM field.
	BDMA_CCR2_MEM2MEM     = 0x4000 // Bit MEM2MEM.

	// CNDTR2: DMA channel x number of data           register
	BDMA_CNDTR2_NDT_Pos = 0x0    // Position of NDT field.
	BDMA_CNDTR2_NDT_Msk = 0xffff // Bit mask of NDT field.

	// CPAR2: This register must not be written when the           channel is enabled.
	BDMA_CPAR2_PA_Pos = 0x0        // Position of PA field.
	BDMA_CPAR2_PA_Msk = 0xffffffff // Bit mask of PA field.

	// CMAR2: This register must not be written when the           channel is enabled.
	BDMA_CMAR2_MA_Pos = 0x0        // Position of MA field.
	BDMA_CMAR2_MA_Msk = 0xffffffff // Bit mask of MA field.

	// CCR3: DMA channel x configuration           register
	BDMA_CCR3_EN_Pos      = 0x0    // Position of EN field.
	BDMA_CCR3_EN_Msk      = 0x1    // Bit mask of EN field.
	BDMA_CCR3_EN          = 0x1    // Bit EN.
	BDMA_CCR3_TCIE_Pos    = 0x1    // Position of TCIE field.
	BDMA_CCR3_TCIE_Msk    = 0x2    // Bit mask of TCIE field.
	BDMA_CCR3_TCIE        = 0x2    // Bit TCIE.
	BDMA_CCR3_HTIE_Pos    = 0x2    // Position of HTIE field.
	BDMA_CCR3_HTIE_Msk    = 0x4    // Bit mask of HTIE field.
	BDMA_CCR3_HTIE        = 0x4    // Bit HTIE.
	BDMA_CCR3_TEIE_Pos    = 0x3    // Position of TEIE field.
	BDMA_CCR3_TEIE_Msk    = 0x8    // Bit mask of TEIE field.
	BDMA_CCR3_TEIE        = 0x8    // Bit TEIE.
	BDMA_CCR3_DIR_Pos     = 0x4    // Position of DIR field.
	BDMA_CCR3_DIR_Msk     = 0x10   // Bit mask of DIR field.
	BDMA_CCR3_DIR         = 0x10   // Bit DIR.
	BDMA_CCR3_CIRC_Pos    = 0x5    // Position of CIRC field.
	BDMA_CCR3_CIRC_Msk    = 0x20   // Bit mask of CIRC field.
	BDMA_CCR3_CIRC        = 0x20   // Bit CIRC.
	BDMA_CCR3_PINC_Pos    = 0x6    // Position of PINC field.
	BDMA_CCR3_PINC_Msk    = 0x40   // Bit mask of PINC field.
	BDMA_CCR3_PINC        = 0x40   // Bit PINC.
	BDMA_CCR3_MINC_Pos    = 0x7    // Position of MINC field.
	BDMA_CCR3_MINC_Msk    = 0x80   // Bit mask of MINC field.
	BDMA_CCR3_MINC        = 0x80   // Bit MINC.
	BDMA_CCR3_PSIZE_Pos   = 0x8    // Position of PSIZE field.
	BDMA_CCR3_PSIZE_Msk   = 0x300  // Bit mask of PSIZE field.
	BDMA_CCR3_MSIZE_Pos   = 0xa    // Position of MSIZE field.
	BDMA_CCR3_MSIZE_Msk   = 0xc00  // Bit mask of MSIZE field.
	BDMA_CCR3_PL_Pos      = 0xc    // Position of PL field.
	BDMA_CCR3_PL_Msk      = 0x3000 // Bit mask of PL field.
	BDMA_CCR3_MEM2MEM_Pos = 0xe    // Position of MEM2MEM field.
	BDMA_CCR3_MEM2MEM_Msk = 0x4000 // Bit mask of MEM2MEM field.
	BDMA_CCR3_MEM2MEM     = 0x4000 // Bit MEM2MEM.

	// CNDTR3: DMA channel x number of data           register
	BDMA_CNDTR3_NDT_Pos = 0x0    // Position of NDT field.
	BDMA_CNDTR3_NDT_Msk = 0xffff // Bit mask of NDT field.

	// CPAR3: This register must not be written when the           channel is enabled.
	BDMA_CPAR3_PA_Pos = 0x0        // Position of PA field.
	BDMA_CPAR3_PA_Msk = 0xffffffff // Bit mask of PA field.

	// CMAR3: This register must not be written when the           channel is enabled.
	BDMA_CMAR3_MA_Pos = 0x0        // Position of MA field.
	BDMA_CMAR3_MA_Msk = 0xffffffff // Bit mask of MA field.

	// CCR4: DMA channel x configuration           register
	BDMA_CCR4_EN_Pos      = 0x0    // Position of EN field.
	BDMA_CCR4_EN_Msk      = 0x1    // Bit mask of EN field.
	BDMA_CCR4_EN          = 0x1    // Bit EN.
	BDMA_CCR4_TCIE_Pos    = 0x1    // Position of TCIE field.
	BDMA_CCR4_TCIE_Msk    = 0x2    // Bit mask of TCIE field.
	BDMA_CCR4_TCIE        = 0x2    // Bit TCIE.
	BDMA_CCR4_HTIE_Pos    = 0x2    // Position of HTIE field.
	BDMA_CCR4_HTIE_Msk    = 0x4    // Bit mask of HTIE field.
	BDMA_CCR4_HTIE        = 0x4    // Bit HTIE.
	BDMA_CCR4_TEIE_Pos    = 0x3    // Position of TEIE field.
	BDMA_CCR4_TEIE_Msk    = 0x8    // Bit mask of TEIE field.
	BDMA_CCR4_TEIE        = 0x8    // Bit TEIE.
	BDMA_CCR4_DIR_Pos     = 0x4    // Position of DIR field.
	BDMA_CCR4_DIR_Msk     = 0x10   // Bit mask of DIR field.
	BDMA_CCR4_DIR         = 0x10   // Bit DIR.
	BDMA_CCR4_CIRC_Pos    = 0x5    // Position of CIRC field.
	BDMA_CCR4_CIRC_Msk    = 0x20   // Bit mask of CIRC field.
	BDMA_CCR4_CIRC        = 0x20   // Bit CIRC.
	BDMA_CCR4_PINC_Pos    = 0x6    // Position of PINC field.
	BDMA_CCR4_PINC_Msk    = 0x40   // Bit mask of PINC field.
	BDMA_CCR4_PINC        = 0x40   // Bit PINC.
	BDMA_CCR4_MINC_Pos    = 0x7    // Position of MINC field.
	BDMA_CCR4_MINC_Msk    = 0x80   // Bit mask of MINC field.
	BDMA_CCR4_MINC        = 0x80   // Bit MINC.
	BDMA_CCR4_PSIZE_Pos   = 0x8    // Position of PSIZE field.
	BDMA_CCR4_PSIZE_Msk   = 0x300  // Bit mask of PSIZE field.
	BDMA_CCR4_MSIZE_Pos   = 0xa    // Position of MSIZE field.
	BDMA_CCR4_MSIZE_Msk   = 0xc00  // Bit mask of MSIZE field.
	BDMA_CCR4_PL_Pos      = 0xc    // Position of PL field.
	BDMA_CCR4_PL_Msk      = 0x3000 // Bit mask of PL field.
	BDMA_CCR4_MEM2MEM_Pos = 0xe    // Position of MEM2MEM field.
	BDMA_CCR4_MEM2MEM_Msk = 0x4000 // Bit mask of MEM2MEM field.
	BDMA_CCR4_MEM2MEM     = 0x4000 // Bit MEM2MEM.

	// CNDTR4: DMA channel x number of data           register
	BDMA_CNDTR4_NDT_Pos = 0x0    // Position of NDT field.
	BDMA_CNDTR4_NDT_Msk = 0xffff // Bit mask of NDT field.

	// CPAR4: This register must not be written when the           channel is enabled.
	BDMA_CPAR4_PA_Pos = 0x0        // Position of PA field.
	BDMA_CPAR4_PA_Msk = 0xffffffff // Bit mask of PA field.

	// CMAR4: This register must not be written when the           channel is enabled.
	BDMA_CMAR4_MA_Pos = 0x0        // Position of MA field.
	BDMA_CMAR4_MA_Msk = 0xffffffff // Bit mask of MA field.

	// CCR5: DMA channel x configuration           register
	BDMA_CCR5_EN_Pos      = 0x0    // Position of EN field.
	BDMA_CCR5_EN_Msk      = 0x1    // Bit mask of EN field.
	BDMA_CCR5_EN          = 0x1    // Bit EN.
	BDMA_CCR5_TCIE_Pos    = 0x1    // Position of TCIE field.
	BDMA_CCR5_TCIE_Msk    = 0x2    // Bit mask of TCIE field.
	BDMA_CCR5_TCIE        = 0x2    // Bit TCIE.
	BDMA_CCR5_HTIE_Pos    = 0x2    // Position of HTIE field.
	BDMA_CCR5_HTIE_Msk    = 0x4    // Bit mask of HTIE field.
	BDMA_CCR5_HTIE        = 0x4    // Bit HTIE.
	BDMA_CCR5_TEIE_Pos    = 0x3    // Position of TEIE field.
	BDMA_CCR5_TEIE_Msk    = 0x8    // Bit mask of TEIE field.
	BDMA_CCR5_TEIE        = 0x8    // Bit TEIE.
	BDMA_CCR5_DIR_Pos     = 0x4    // Position of DIR field.
	BDMA_CCR5_DIR_Msk     = 0x10   // Bit mask of DIR field.
	BDMA_CCR5_DIR         = 0x10   // Bit DIR.
	BDMA_CCR5_CIRC_Pos    = 0x5    // Position of CIRC field.
	BDMA_CCR5_CIRC_Msk    = 0x20   // Bit mask of CIRC field.
	BDMA_CCR5_CIRC        = 0x20   // Bit CIRC.
	BDMA_CCR5_PINC_Pos    = 0x6    // Position of PINC field.
	BDMA_CCR5_PINC_Msk    = 0x40   // Bit mask of PINC field.
	BDMA_CCR5_PINC        = 0x40   // Bit PINC.
	BDMA_CCR5_MINC_Pos    = 0x7    // Position of MINC field.
	BDMA_CCR5_MINC_Msk    = 0x80   // Bit mask of MINC field.
	BDMA_CCR5_MINC        = 0x80   // Bit MINC.
	BDMA_CCR5_PSIZE_Pos   = 0x8    // Position of PSIZE field.
	BDMA_CCR5_PSIZE_Msk   = 0x300  // Bit mask of PSIZE field.
	BDMA_CCR5_MSIZE_Pos   = 0xa    // Position of MSIZE field.
	BDMA_CCR5_MSIZE_Msk   = 0xc00  // Bit mask of MSIZE field.
	BDMA_CCR5_PL_Pos      = 0xc    // Position of PL field.
	BDMA_CCR5_PL_Msk      = 0x3000 // Bit mask of PL field.
	BDMA_CCR5_MEM2MEM_Pos = 0xe    // Position of MEM2MEM field.
	BDMA_CCR5_MEM2MEM_Msk = 0x4000 // Bit mask of MEM2MEM field.
	BDMA_CCR5_MEM2MEM     = 0x4000 // Bit MEM2MEM.

	// CNDTR5: DMA channel x number of data           register
	BDMA_CNDTR5_NDT_Pos = 0x0    // Position of NDT field.
	BDMA_CNDTR5_NDT_Msk = 0xffff // Bit mask of NDT field.

	// CPAR5: This register must not be written when the           channel is enabled.
	BDMA_CPAR5_PA_Pos = 0x0        // Position of PA field.
	BDMA_CPAR5_PA_Msk = 0xffffffff // Bit mask of PA field.

	// CMAR5: This register must not be written when the           channel is enabled.
	BDMA_CMAR5_MA_Pos = 0x0        // Position of MA field.
	BDMA_CMAR5_MA_Msk = 0xffffffff // Bit mask of MA field.

	// CCR6: DMA channel x configuration           register
	BDMA_CCR6_EN_Pos      = 0x0    // Position of EN field.
	BDMA_CCR6_EN_Msk      = 0x1    // Bit mask of EN field.
	BDMA_CCR6_EN          = 0x1    // Bit EN.
	BDMA_CCR6_TCIE_Pos    = 0x1    // Position of TCIE field.
	BDMA_CCR6_TCIE_Msk    = 0x2    // Bit mask of TCIE field.
	BDMA_CCR6_TCIE        = 0x2    // Bit TCIE.
	BDMA_CCR6_HTIE_Pos    = 0x2    // Position of HTIE field.
	BDMA_CCR6_HTIE_Msk    = 0x4    // Bit mask of HTIE field.
	BDMA_CCR6_HTIE        = 0x4    // Bit HTIE.
	BDMA_CCR6_TEIE_Pos    = 0x3    // Position of TEIE field.
	BDMA_CCR6_TEIE_Msk    = 0x8    // Bit mask of TEIE field.
	BDMA_CCR6_TEIE        = 0x8    // Bit TEIE.
	BDMA_CCR6_DIR_Pos     = 0x4    // Position of DIR field.
	BDMA_CCR6_DIR_Msk     = 0x10   // Bit mask of DIR field.
	BDMA_CCR6_DIR         = 0x10   // Bit DIR.
	BDMA_CCR6_CIRC_Pos    = 0x5    // Position of CIRC field.
	BDMA_CCR6_CIRC_Msk    = 0x20   // Bit mask of CIRC field.
	BDMA_CCR6_CIRC        = 0x20   // Bit CIRC.
	BDMA_CCR6_PINC_Pos    = 0x6    // Position of PINC field.
	BDMA_CCR6_PINC_Msk    = 0x40   // Bit mask of PINC field.
	BDMA_CCR6_PINC        = 0x40   // Bit PINC.
	BDMA_CCR6_MINC_Pos    = 0x7    // Position of MINC field.
	BDMA_CCR6_MINC_Msk    = 0x80   // Bit mask of MINC field.
	BDMA_CCR6_MINC        = 0x80   // Bit MINC.
	BDMA_CCR6_PSIZE_Pos   = 0x8    // Position of PSIZE field.
	BDMA_CCR6_PSIZE_Msk   = 0x300  // Bit mask of PSIZE field.
	BDMA_CCR6_MSIZE_Pos   = 0xa    // Position of MSIZE field.
	BDMA_CCR6_MSIZE_Msk   = 0xc00  // Bit mask of MSIZE field.
	BDMA_CCR6_PL_Pos      = 0xc    // Position of PL field.
	BDMA_CCR6_PL_Msk      = 0x3000 // Bit mask of PL field.
	BDMA_CCR6_MEM2MEM_Pos = 0xe    // Position of MEM2MEM field.
	BDMA_CCR6_MEM2MEM_Msk = 0x4000 // Bit mask of MEM2MEM field.
	BDMA_CCR6_MEM2MEM     = 0x4000 // Bit MEM2MEM.

	// CNDTR6: DMA channel x number of data           register
	BDMA_CNDTR6_NDT_Pos = 0x0    // Position of NDT field.
	BDMA_CNDTR6_NDT_Msk = 0xffff // Bit mask of NDT field.

	// CPAR6: This register must not be written when the           channel is enabled.
	BDMA_CPAR6_PA_Pos = 0x0        // Position of PA field.
	BDMA_CPAR6_PA_Msk = 0xffffffff // Bit mask of PA field.

	// CMAR6: This register must not be written when the           channel is enabled.
	BDMA_CMAR6_MA_Pos = 0x0        // Position of MA field.
	BDMA_CMAR6_MA_Msk = 0xffffffff // Bit mask of MA field.

	// CCR7: DMA channel x configuration           register
	BDMA_CCR7_EN_Pos      = 0x0    // Position of EN field.
	BDMA_CCR7_EN_Msk      = 0x1    // Bit mask of EN field.
	BDMA_CCR7_EN          = 0x1    // Bit EN.
	BDMA_CCR7_TCIE_Pos    = 0x1    // Position of TCIE field.
	BDMA_CCR7_TCIE_Msk    = 0x2    // Bit mask of TCIE field.
	BDMA_CCR7_TCIE        = 0x2    // Bit TCIE.
	BDMA_CCR7_HTIE_Pos    = 0x2    // Position of HTIE field.
	BDMA_CCR7_HTIE_Msk    = 0x4    // Bit mask of HTIE field.
	BDMA_CCR7_HTIE        = 0x4    // Bit HTIE.
	BDMA_CCR7_TEIE_Pos    = 0x3    // Position of TEIE field.
	BDMA_CCR7_TEIE_Msk    = 0x8    // Bit mask of TEIE field.
	BDMA_CCR7_TEIE        = 0x8    // Bit TEIE.
	BDMA_CCR7_DIR_Pos     = 0x4    // Position of DIR field.
	BDMA_CCR7_DIR_Msk     = 0x10   // Bit mask of DIR field.
	BDMA_CCR7_DIR         = 0x10   // Bit DIR.
	BDMA_CCR7_CIRC_Pos    = 0x5    // Position of CIRC field.
	BDMA_CCR7_CIRC_Msk    = 0x20   // Bit mask of CIRC field.
	BDMA_CCR7_CIRC        = 0x20   // Bit CIRC.
	BDMA_CCR7_PINC_Pos    = 0x6    // Position of PINC field.
	BDMA_CCR7_PINC_Msk    = 0x40   // Bit mask of PINC field.
	BDMA_CCR7_PINC        = 0x40   // Bit PINC.
	BDMA_CCR7_MINC_Pos    = 0x7    // Position of MINC field.
	BDMA_CCR7_MINC_Msk    = 0x80   // Bit mask of MINC field.
	BDMA_CCR7_MINC        = 0x80   // Bit MINC.
	BDMA_CCR7_PSIZE_Pos   = 0x8    // Position of PSIZE field.
	BDMA_CCR7_PSIZE_Msk   = 0x300  // Bit mask of PSIZE field.
	BDMA_CCR7_MSIZE_Pos   = 0xa    // Position of MSIZE field.
	BDMA_CCR7_MSIZE_Msk   = 0xc00  // Bit mask of MSIZE field.
	BDMA_CCR7_PL_Pos      = 0xc    // Position of PL field.
	BDMA_CCR7_PL_Msk      = 0x3000 // Bit mask of PL field.
	BDMA_CCR7_MEM2MEM_Pos = 0xe    // Position of MEM2MEM field.
	BDMA_CCR7_MEM2MEM_Msk = 0x4000 // Bit mask of MEM2MEM field.
	BDMA_CCR7_MEM2MEM     = 0x4000 // Bit MEM2MEM.

	// CNDTR7: DMA channel x number of data           register
	BDMA_CNDTR7_NDT_Pos = 0x0    // Position of NDT field.
	BDMA_CNDTR7_NDT_Msk = 0xffff // Bit mask of NDT field.

	// CPAR7: This register must not be written when the           channel is enabled.
	BDMA_CPAR7_PA_Pos = 0x0        // Position of PA field.
	BDMA_CPAR7_PA_Msk = 0xffffffff // Bit mask of PA field.

	// CMAR7: This register must not be written when the           channel is enabled.
	BDMA_CMAR7_MA_Pos = 0x0        // Position of MA field.
	BDMA_CMAR7_MA_Msk = 0xffffffff // Bit mask of MA field.

	// CCR8: DMA channel x configuration           register
	BDMA_CCR8_EN_Pos      = 0x0    // Position of EN field.
	BDMA_CCR8_EN_Msk      = 0x1    // Bit mask of EN field.
	BDMA_CCR8_EN          = 0x1    // Bit EN.
	BDMA_CCR8_TCIE_Pos    = 0x1    // Position of TCIE field.
	BDMA_CCR8_TCIE_Msk    = 0x2    // Bit mask of TCIE field.
	BDMA_CCR8_TCIE        = 0x2    // Bit TCIE.
	BDMA_CCR8_HTIE_Pos    = 0x2    // Position of HTIE field.
	BDMA_CCR8_HTIE_Msk    = 0x4    // Bit mask of HTIE field.
	BDMA_CCR8_HTIE        = 0x4    // Bit HTIE.
	BDMA_CCR8_TEIE_Pos    = 0x3    // Position of TEIE field.
	BDMA_CCR8_TEIE_Msk    = 0x8    // Bit mask of TEIE field.
	BDMA_CCR8_TEIE        = 0x8    // Bit TEIE.
	BDMA_CCR8_DIR_Pos     = 0x4    // Position of DIR field.
	BDMA_CCR8_DIR_Msk     = 0x10   // Bit mask of DIR field.
	BDMA_CCR8_DIR         = 0x10   // Bit DIR.
	BDMA_CCR8_CIRC_Pos    = 0x5    // Position of CIRC field.
	BDMA_CCR8_CIRC_Msk    = 0x20   // Bit mask of CIRC field.
	BDMA_CCR8_CIRC        = 0x20   // Bit CIRC.
	BDMA_CCR8_PINC_Pos    = 0x6    // Position of PINC field.
	BDMA_CCR8_PINC_Msk    = 0x40   // Bit mask of PINC field.
	BDMA_CCR8_PINC        = 0x40   // Bit PINC.
	BDMA_CCR8_MINC_Pos    = 0x7    // Position of MINC field.
	BDMA_CCR8_MINC_Msk    = 0x80   // Bit mask of MINC field.
	BDMA_CCR8_MINC        = 0x80   // Bit MINC.
	BDMA_CCR8_PSIZE_Pos   = 0x8    // Position of PSIZE field.
	BDMA_CCR8_PSIZE_Msk   = 0x300  // Bit mask of PSIZE field.
	BDMA_CCR8_MSIZE_Pos   = 0xa    // Position of MSIZE field.
	BDMA_CCR8_MSIZE_Msk   = 0xc00  // Bit mask of MSIZE field.
	BDMA_CCR8_PL_Pos      = 0xc    // Position of PL field.
	BDMA_CCR8_PL_Msk      = 0x3000 // Bit mask of PL field.
	BDMA_CCR8_MEM2MEM_Pos = 0xe    // Position of MEM2MEM field.
	BDMA_CCR8_MEM2MEM_Msk = 0x4000 // Bit mask of MEM2MEM field.
	BDMA_CCR8_MEM2MEM     = 0x4000 // Bit MEM2MEM.

	// CNDTR8: DMA channel x number of data           register
	BDMA_CNDTR8_NDT_Pos = 0x0    // Position of NDT field.
	BDMA_CNDTR8_NDT_Msk = 0xffff // Bit mask of NDT field.

	// CPAR8: This register must not be written when the           channel is enabled.
	BDMA_CPAR8_PA_Pos = 0x0        // Position of PA field.
	BDMA_CPAR8_PA_Msk = 0xffffffff // Bit mask of PA field.

	// CMAR8: This register must not be written when the           channel is enabled.
	BDMA_CMAR8_MA_Pos = 0x0        // Position of MA field.
	BDMA_CMAR8_MA_Msk = 0xffffffff // Bit mask of MA field.
)

// Bitfields for DMA2D: DMA2D
const (
	// CR: DMA2D control register
	DMA2D_CR_START_Pos = 0x0     // Position of START field.
	DMA2D_CR_START_Msk = 0x1     // Bit mask of START field.
	DMA2D_CR_START     = 0x1     // Bit START.
	DMA2D_CR_SUSP_Pos  = 0x1     // Position of SUSP field.
	DMA2D_CR_SUSP_Msk  = 0x2     // Bit mask of SUSP field.
	DMA2D_CR_SUSP      = 0x2     // Bit SUSP.
	DMA2D_CR_ABORT_Pos = 0x2     // Position of ABORT field.
	DMA2D_CR_ABORT_Msk = 0x4     // Bit mask of ABORT field.
	DMA2D_CR_ABORT     = 0x4     // Bit ABORT.
	DMA2D_CR_TEIE_Pos  = 0x8     // Position of TEIE field.
	DMA2D_CR_TEIE_Msk  = 0x100   // Bit mask of TEIE field.
	DMA2D_CR_TEIE      = 0x100   // Bit TEIE.
	DMA2D_CR_TCIE_Pos  = 0x9     // Position of TCIE field.
	DMA2D_CR_TCIE_Msk  = 0x200   // Bit mask of TCIE field.
	DMA2D_CR_TCIE      = 0x200   // Bit TCIE.
	DMA2D_CR_TWIE_Pos  = 0xa     // Position of TWIE field.
	DMA2D_CR_TWIE_Msk  = 0x400   // Bit mask of TWIE field.
	DMA2D_CR_TWIE      = 0x400   // Bit TWIE.
	DMA2D_CR_CAEIE_Pos = 0xb     // Position of CAEIE field.
	DMA2D_CR_CAEIE_Msk = 0x800   // Bit mask of CAEIE field.
	DMA2D_CR_CAEIE     = 0x800   // Bit CAEIE.
	DMA2D_CR_CTCIE_Pos = 0xc     // Position of CTCIE field.
	DMA2D_CR_CTCIE_Msk = 0x1000  // Bit mask of CTCIE field.
	DMA2D_CR_CTCIE     = 0x1000  // Bit CTCIE.
	DMA2D_CR_CEIE_Pos  = 0xd     // Position of CEIE field.
	DMA2D_CR_CEIE_Msk  = 0x2000  // Bit mask of CEIE field.
	DMA2D_CR_CEIE      = 0x2000  // Bit CEIE.
	DMA2D_CR_MODE_Pos  = 0x10    // Position of MODE field.
	DMA2D_CR_MODE_Msk  = 0x30000 // Bit mask of MODE field.

	// ISR: DMA2D Interrupt Status           Register
	DMA2D_ISR_TEIF_Pos  = 0x0  // Position of TEIF field.
	DMA2D_ISR_TEIF_Msk  = 0x1  // Bit mask of TEIF field.
	DMA2D_ISR_TEIF      = 0x1  // Bit TEIF.
	DMA2D_ISR_TCIF_Pos  = 0x1  // Position of TCIF field.
	DMA2D_ISR_TCIF_Msk  = 0x2  // Bit mask of TCIF field.
	DMA2D_ISR_TCIF      = 0x2  // Bit TCIF.
	DMA2D_ISR_TWIF_Pos  = 0x2  // Position of TWIF field.
	DMA2D_ISR_TWIF_Msk  = 0x4  // Bit mask of TWIF field.
	DMA2D_ISR_TWIF      = 0x4  // Bit TWIF.
	DMA2D_ISR_CAEIF_Pos = 0x3  // Position of CAEIF field.
	DMA2D_ISR_CAEIF_Msk = 0x8  // Bit mask of CAEIF field.
	DMA2D_ISR_CAEIF     = 0x8  // Bit CAEIF.
	DMA2D_ISR_CTCIF_Pos = 0x4  // Position of CTCIF field.
	DMA2D_ISR_CTCIF_Msk = 0x10 // Bit mask of CTCIF field.
	DMA2D_ISR_CTCIF     = 0x10 // Bit CTCIF.
	DMA2D_ISR_CEIF_Pos  = 0x5  // Position of CEIF field.
	DMA2D_ISR_CEIF_Msk  = 0x20 // Bit mask of CEIF field.
	DMA2D_ISR_CEIF      = 0x20 // Bit CEIF.

	// IFCR: DMA2D interrupt flag clear           register
	DMA2D_IFCR_CTEIF_Pos  = 0x0  // Position of CTEIF field.
	DMA2D_IFCR_CTEIF_Msk  = 0x1  // Bit mask of CTEIF field.
	DMA2D_IFCR_CTEIF      = 0x1  // Bit CTEIF.
	DMA2D_IFCR_CTCIF_Pos  = 0x1  // Position of CTCIF field.
	DMA2D_IFCR_CTCIF_Msk  = 0x2  // Bit mask of CTCIF field.
	DMA2D_IFCR_CTCIF      = 0x2  // Bit CTCIF.
	DMA2D_IFCR_CTWIF_Pos  = 0x2  // Position of CTWIF field.
	DMA2D_IFCR_CTWIF_Msk  = 0x4  // Bit mask of CTWIF field.
	DMA2D_IFCR_CTWIF      = 0x4  // Bit CTWIF.
	DMA2D_IFCR_CAECIF_Pos = 0x3  // Position of CAECIF field.
	DMA2D_IFCR_CAECIF_Msk = 0x8  // Bit mask of CAECIF field.
	DMA2D_IFCR_CAECIF     = 0x8  // Bit CAECIF.
	DMA2D_IFCR_CCTCIF_Pos = 0x4  // Position of CCTCIF field.
	DMA2D_IFCR_CCTCIF_Msk = 0x10 // Bit mask of CCTCIF field.
	DMA2D_IFCR_CCTCIF     = 0x10 // Bit CCTCIF.
	DMA2D_IFCR_CCEIF_Pos  = 0x5  // Position of CCEIF field.
	DMA2D_IFCR_CCEIF_Msk  = 0x20 // Bit mask of CCEIF field.
	DMA2D_IFCR_CCEIF      = 0x20 // Bit CCEIF.

	// FGMAR: DMA2D foreground memory address           register
	DMA2D_FGMAR_MA_Pos = 0x0        // Position of MA field.
	DMA2D_FGMAR_MA_Msk = 0xffffffff // Bit mask of MA field.

	// FGOR: DMA2D foreground offset           register
	DMA2D_FGOR_LO_Pos = 0x0    // Position of LO field.
	DMA2D_FGOR_LO_Msk = 0x3fff // Bit mask of LO field.

	// BGMAR: DMA2D background memory address           register
	DMA2D_BGMAR_MA_Pos = 0x0        // Position of MA field.
	DMA2D_BGMAR_MA_Msk = 0xffffffff // Bit mask of MA field.

	// BGOR: DMA2D background offset           register
	DMA2D_BGOR_LO_Pos = 0x0    // Position of LO field.
	DMA2D_BGOR_LO_Msk = 0x3fff // Bit mask of LO field.

	// FGPFCCR: DMA2D foreground PFC control           register
	DMA2D_FGPFCCR_CM_Pos    = 0x0        // Position of CM field.
	DMA2D_FGPFCCR_CM_Msk    = 0xf        // Bit mask of CM field.
	DMA2D_FGPFCCR_CCM_Pos   = 0x4        // Position of CCM field.
	DMA2D_FGPFCCR_CCM_Msk   = 0x10       // Bit mask of CCM field.
	DMA2D_FGPFCCR_CCM       = 0x10       // Bit CCM.
	DMA2D_FGPFCCR_START_Pos = 0x5        // Position of START field.
	DMA2D_FGPFCCR_START_Msk = 0x20       // Bit mask of START field.
	DMA2D_FGPFCCR_START     = 0x20       // Bit START.
	DMA2D_FGPFCCR_CS_Pos    = 0x8        // Position of CS field.
	DMA2D_FGPFCCR_CS_Msk    = 0xff00     // Bit mask of CS field.
	DMA2D_FGPFCCR_AM_Pos    = 0x10       // Position of AM field.
	DMA2D_FGPFCCR_AM_Msk    = 0x30000    // Bit mask of AM field.
	DMA2D_FGPFCCR_CSS_Pos   = 0x12       // Position of CSS field.
	DMA2D_FGPFCCR_CSS_Msk   = 0xc0000    // Bit mask of CSS field.
	DMA2D_FGPFCCR_AI_Pos    = 0x14       // Position of AI field.
	DMA2D_FGPFCCR_AI_Msk    = 0x100000   // Bit mask of AI field.
	DMA2D_FGPFCCR_AI        = 0x100000   // Bit AI.
	DMA2D_FGPFCCR_RBS_Pos   = 0x15       // Position of RBS field.
	DMA2D_FGPFCCR_RBS_Msk   = 0x200000   // Bit mask of RBS field.
	DMA2D_FGPFCCR_RBS       = 0x200000   // Bit RBS.
	DMA2D_FGPFCCR_ALPHA_Pos = 0x18       // Position of ALPHA field.
	DMA2D_FGPFCCR_ALPHA_Msk = 0xff000000 // Bit mask of ALPHA field.

	// FGCOLR: DMA2D foreground color           register
	DMA2D_FGCOLR_BLUE_Pos  = 0x0      // Position of BLUE field.
	DMA2D_FGCOLR_BLUE_Msk  = 0xff     // Bit mask of BLUE field.
	DMA2D_FGCOLR_GREEN_Pos = 0x8      // Position of GREEN field.
	DMA2D_FGCOLR_GREEN_Msk = 0xff00   // Bit mask of GREEN field.
	DMA2D_FGCOLR_RED_Pos   = 0x10     // Position of RED field.
	DMA2D_FGCOLR_RED_Msk   = 0xff0000 // Bit mask of RED field.

	// BGPFCCR: DMA2D background PFC control           register
	DMA2D_BGPFCCR_CM_Pos    = 0x0        // Position of CM field.
	DMA2D_BGPFCCR_CM_Msk    = 0xf        // Bit mask of CM field.
	DMA2D_BGPFCCR_CCM_Pos   = 0x4        // Position of CCM field.
	DMA2D_BGPFCCR_CCM_Msk   = 0x10       // Bit mask of CCM field.
	DMA2D_BGPFCCR_CCM       = 0x10       // Bit CCM.
	DMA2D_BGPFCCR_START_Pos = 0x5        // Position of START field.
	DMA2D_BGPFCCR_START_Msk = 0x20       // Bit mask of START field.
	DMA2D_BGPFCCR_START     = 0x20       // Bit START.
	DMA2D_BGPFCCR_CS_Pos    = 0x8        // Position of CS field.
	DMA2D_BGPFCCR_CS_Msk    = 0xff00     // Bit mask of CS field.
	DMA2D_BGPFCCR_AM_Pos    = 0x10       // Position of AM field.
	DMA2D_BGPFCCR_AM_Msk    = 0x30000    // Bit mask of AM field.
	DMA2D_BGPFCCR_AI_Pos    = 0x14       // Position of AI field.
	DMA2D_BGPFCCR_AI_Msk    = 0x100000   // Bit mask of AI field.
	DMA2D_BGPFCCR_AI        = 0x100000   // Bit AI.
	DMA2D_BGPFCCR_RBS_Pos   = 0x15       // Position of RBS field.
	DMA2D_BGPFCCR_RBS_Msk   = 0x200000   // Bit mask of RBS field.
	DMA2D_BGPFCCR_RBS       = 0x200000   // Bit RBS.
	DMA2D_BGPFCCR_ALPHA_Pos = 0x18       // Position of ALPHA field.
	DMA2D_BGPFCCR_ALPHA_Msk = 0xff000000 // Bit mask of ALPHA field.

	// BGCOLR: DMA2D background color           register
	DMA2D_BGCOLR_BLUE_Pos  = 0x0      // Position of BLUE field.
	DMA2D_BGCOLR_BLUE_Msk  = 0xff     // Bit mask of BLUE field.
	DMA2D_BGCOLR_GREEN_Pos = 0x8      // Position of GREEN field.
	DMA2D_BGCOLR_GREEN_Msk = 0xff00   // Bit mask of GREEN field.
	DMA2D_BGCOLR_RED_Pos   = 0x10     // Position of RED field.
	DMA2D_BGCOLR_RED_Msk   = 0xff0000 // Bit mask of RED field.

	// FGCMAR: DMA2D foreground CLUT memory address           register
	DMA2D_FGCMAR_MA_Pos = 0x0        // Position of MA field.
	DMA2D_FGCMAR_MA_Msk = 0xffffffff // Bit mask of MA field.

	// BGCMAR: DMA2D background CLUT memory address           register
	DMA2D_BGCMAR_MA_Pos = 0x0        // Position of MA field.
	DMA2D_BGCMAR_MA_Msk = 0xffffffff // Bit mask of MA field.

	// OPFCCR: DMA2D output PFC control           register
	DMA2D_OPFCCR_CM_Pos  = 0x0      // Position of CM field.
	DMA2D_OPFCCR_CM_Msk  = 0x7      // Bit mask of CM field.
	DMA2D_OPFCCR_AI_Pos  = 0x14     // Position of AI field.
	DMA2D_OPFCCR_AI_Msk  = 0x100000 // Bit mask of AI field.
	DMA2D_OPFCCR_AI      = 0x100000 // Bit AI.
	DMA2D_OPFCCR_RBS_Pos = 0x15     // Position of RBS field.
	DMA2D_OPFCCR_RBS_Msk = 0x200000 // Bit mask of RBS field.
	DMA2D_OPFCCR_RBS     = 0x200000 // Bit RBS.

	// OCOLR: DMA2D output color register
	DMA2D_OCOLR_BLUE_Pos  = 0x0        // Position of BLUE field.
	DMA2D_OCOLR_BLUE_Msk  = 0xff       // Bit mask of BLUE field.
	DMA2D_OCOLR_GREEN_Pos = 0x8        // Position of GREEN field.
	DMA2D_OCOLR_GREEN_Msk = 0xff00     // Bit mask of GREEN field.
	DMA2D_OCOLR_RED_Pos   = 0x10       // Position of RED field.
	DMA2D_OCOLR_RED_Msk   = 0xff0000   // Bit mask of RED field.
	DMA2D_OCOLR_ALPHA_Pos = 0x18       // Position of ALPHA field.
	DMA2D_OCOLR_ALPHA_Msk = 0xff000000 // Bit mask of ALPHA field.

	// OMAR: DMA2D output memory address           register
	DMA2D_OMAR_MA_Pos = 0x0        // Position of MA field.
	DMA2D_OMAR_MA_Msk = 0xffffffff // Bit mask of MA field.

	// OOR: DMA2D output offset register
	DMA2D_OOR_LO_Pos = 0x0    // Position of LO field.
	DMA2D_OOR_LO_Msk = 0x3fff // Bit mask of LO field.

	// NLR: DMA2D number of line register
	DMA2D_NLR_NL_Pos = 0x0        // Position of NL field.
	DMA2D_NLR_NL_Msk = 0xffff     // Bit mask of NL field.
	DMA2D_NLR_PL_Pos = 0x10       // Position of PL field.
	DMA2D_NLR_PL_Msk = 0x3fff0000 // Bit mask of PL field.

	// LWR: DMA2D line watermark register
	DMA2D_LWR_LW_Pos = 0x0    // Position of LW field.
	DMA2D_LWR_LW_Msk = 0xffff // Bit mask of LW field.

	// AMTCR: DMA2D AXI master timer configuration           register
	DMA2D_AMTCR_EN_Pos = 0x0    // Position of EN field.
	DMA2D_AMTCR_EN_Msk = 0x1    // Bit mask of EN field.
	DMA2D_AMTCR_EN     = 0x1    // Bit EN.
	DMA2D_AMTCR_DT_Pos = 0x8    // Position of DT field.
	DMA2D_AMTCR_DT_Msk = 0xff00 // Bit mask of DT field.
)

// Bitfields for DMAMUX2: DMAMUX
const (
	// C0CR: DMAMux - DMA request line multiplexer           channel x control register
	DMAMUX_C0CR_DMAREQ_ID_Pos = 0x0        // Position of DMAREQ_ID field.
	DMAMUX_C0CR_DMAREQ_ID_Msk = 0xff       // Bit mask of DMAREQ_ID field.
	DMAMUX_C0CR_SOIE_Pos      = 0x8        // Position of SOIE field.
	DMAMUX_C0CR_SOIE_Msk      = 0x100      // Bit mask of SOIE field.
	DMAMUX_C0CR_SOIE          = 0x100      // Bit SOIE.
	DMAMUX_C0CR_EGE_Pos       = 0x9        // Position of EGE field.
	DMAMUX_C0CR_EGE_Msk       = 0x200      // Bit mask of EGE field.
	DMAMUX_C0CR_EGE           = 0x200      // Bit EGE.
	DMAMUX_C0CR_SE_Pos        = 0x10       // Position of SE field.
	DMAMUX_C0CR_SE_Msk        = 0x10000    // Bit mask of SE field.
	DMAMUX_C0CR_SE            = 0x10000    // Bit SE.
	DMAMUX_C0CR_SPOL_Pos      = 0x11       // Position of SPOL field.
	DMAMUX_C0CR_SPOL_Msk      = 0x60000    // Bit mask of SPOL field.
	DMAMUX_C0CR_NBREQ_Pos     = 0x13       // Position of NBREQ field.
	DMAMUX_C0CR_NBREQ_Msk     = 0xf80000   // Bit mask of NBREQ field.
	DMAMUX_C0CR_SYNC_ID_Pos   = 0x18       // Position of SYNC_ID field.
	DMAMUX_C0CR_SYNC_ID_Msk   = 0x1f000000 // Bit mask of SYNC_ID field.

	// C1CR: DMAMux - DMA request line multiplexer           channel x control register
	DMAMUX_C1CR_DMAREQ_ID_Pos = 0x0        // Position of DMAREQ_ID field.
	DMAMUX_C1CR_DMAREQ_ID_Msk = 0xff       // Bit mask of DMAREQ_ID field.
	DMAMUX_C1CR_SOIE_Pos      = 0x8        // Position of SOIE field.
	DMAMUX_C1CR_SOIE_Msk      = 0x100      // Bit mask of SOIE field.
	DMAMUX_C1CR_SOIE          = 0x100      // Bit SOIE.
	DMAMUX_C1CR_EGE_Pos       = 0x9        // Position of EGE field.
	DMAMUX_C1CR_EGE_Msk       = 0x200      // Bit mask of EGE field.
	DMAMUX_C1CR_EGE           = 0x200      // Bit EGE.
	DMAMUX_C1CR_SE_Pos        = 0x10       // Position of SE field.
	DMAMUX_C1CR_SE_Msk        = 0x10000    // Bit mask of SE field.
	DMAMUX_C1CR_SE            = 0x10000    // Bit SE.
	DMAMUX_C1CR_SPOL_Pos      = 0x11       // Position of SPOL field.
	DMAMUX_C1CR_SPOL_Msk      = 0x60000    // Bit mask of SPOL field.
	DMAMUX_C1CR_NBREQ_Pos     = 0x13       // Position of NBREQ field.
	DMAMUX_C1CR_NBREQ_Msk     = 0xf80000   // Bit mask of NBREQ field.
	DMAMUX_C1CR_SYNC_ID_Pos   = 0x18       // Position of SYNC_ID field.
	DMAMUX_C1CR_SYNC_ID_Msk   = 0x1f000000 // Bit mask of SYNC_ID field.

	// C2CR: DMAMux - DMA request line multiplexer           channel x control register
	DMAMUX_C2CR_DMAREQ_ID_Pos = 0x0        // Position of DMAREQ_ID field.
	DMAMUX_C2CR_DMAREQ_ID_Msk = 0xff       // Bit mask of DMAREQ_ID field.
	DMAMUX_C2CR_SOIE_Pos      = 0x8        // Position of SOIE field.
	DMAMUX_C2CR_SOIE_Msk      = 0x100      // Bit mask of SOIE field.
	DMAMUX_C2CR_SOIE          = 0x100      // Bit SOIE.
	DMAMUX_C2CR_EGE_Pos       = 0x9        // Position of EGE field.
	DMAMUX_C2CR_EGE_Msk       = 0x200      // Bit mask of EGE field.
	DMAMUX_C2CR_EGE           = 0x200      // Bit EGE.
	DMAMUX_C2CR_SE_Pos        = 0x10       // Position of SE field.
	DMAMUX_C2CR_SE_Msk        = 0x10000    // Bit mask of SE field.
	DMAMUX_C2CR_SE            = 0x10000    // Bit SE.
	DMAMUX_C2CR_SPOL_Pos      = 0x11       // Position of SPOL field.
	DMAMUX_C2CR_SPOL_Msk      = 0x60000    // Bit mask of SPOL field.
	DMAMUX_C2CR_NBREQ_Pos     = 0x13       // Position of NBREQ field.
	DMAMUX_C2CR_NBREQ_Msk     = 0xf80000   // Bit mask of NBREQ field.
	DMAMUX_C2CR_SYNC_ID_Pos   = 0x18       // Position of SYNC_ID field.
	DMAMUX_C2CR_SYNC_ID_Msk   = 0x1f000000 // Bit mask of SYNC_ID field.

	// C3CR: DMAMux - DMA request line multiplexer           channel x control register
	DMAMUX_C3CR_DMAREQ_ID_Pos = 0x0        // Position of DMAREQ_ID field.
	DMAMUX_C3CR_DMAREQ_ID_Msk = 0xff       // Bit mask of DMAREQ_ID field.
	DMAMUX_C3CR_SOIE_Pos      = 0x8        // Position of SOIE field.
	DMAMUX_C3CR_SOIE_Msk      = 0x100      // Bit mask of SOIE field.
	DMAMUX_C3CR_SOIE          = 0x100      // Bit SOIE.
	DMAMUX_C3CR_EGE_Pos       = 0x9        // Position of EGE field.
	DMAMUX_C3CR_EGE_Msk       = 0x200      // Bit mask of EGE field.
	DMAMUX_C3CR_EGE           = 0x200      // Bit EGE.
	DMAMUX_C3CR_SE_Pos        = 0x10       // Position of SE field.
	DMAMUX_C3CR_SE_Msk        = 0x10000    // Bit mask of SE field.
	DMAMUX_C3CR_SE            = 0x10000    // Bit SE.
	DMAMUX_C3CR_SPOL_Pos      = 0x11       // Position of SPOL field.
	DMAMUX_C3CR_SPOL_Msk      = 0x60000    // Bit mask of SPOL field.
	DMAMUX_C3CR_NBREQ_Pos     = 0x13       // Position of NBREQ field.
	DMAMUX_C3CR_NBREQ_Msk     = 0xf80000   // Bit mask of NBREQ field.
	DMAMUX_C3CR_SYNC_ID_Pos   = 0x18       // Position of SYNC_ID field.
	DMAMUX_C3CR_SYNC_ID_Msk   = 0x1f000000 // Bit mask of SYNC_ID field.

	// C4CR: DMAMux - DMA request line multiplexer           channel x control register
	DMAMUX_C4CR_DMAREQ_ID_Pos = 0x0        // Position of DMAREQ_ID field.
	DMAMUX_C4CR_DMAREQ_ID_Msk = 0xff       // Bit mask of DMAREQ_ID field.
	DMAMUX_C4CR_SOIE_Pos      = 0x8        // Position of SOIE field.
	DMAMUX_C4CR_SOIE_Msk      = 0x100      // Bit mask of SOIE field.
	DMAMUX_C4CR_SOIE          = 0x100      // Bit SOIE.
	DMAMUX_C4CR_EGE_Pos       = 0x9        // Position of EGE field.
	DMAMUX_C4CR_EGE_Msk       = 0x200      // Bit mask of EGE field.
	DMAMUX_C4CR_EGE           = 0x200      // Bit EGE.
	DMAMUX_C4CR_SE_Pos        = 0x10       // Position of SE field.
	DMAMUX_C4CR_SE_Msk        = 0x10000    // Bit mask of SE field.
	DMAMUX_C4CR_SE            = 0x10000    // Bit SE.
	DMAMUX_C4CR_SPOL_Pos      = 0x11       // Position of SPOL field.
	DMAMUX_C4CR_SPOL_Msk      = 0x60000    // Bit mask of SPOL field.
	DMAMUX_C4CR_NBREQ_Pos     = 0x13       // Position of NBREQ field.
	DMAMUX_C4CR_NBREQ_Msk     = 0xf80000   // Bit mask of NBREQ field.
	DMAMUX_C4CR_SYNC_ID_Pos   = 0x18       // Position of SYNC_ID field.
	DMAMUX_C4CR_SYNC_ID_Msk   = 0x1f000000 // Bit mask of SYNC_ID field.

	// C5CR: DMAMux - DMA request line multiplexer           channel x control register
	DMAMUX_C5CR_DMAREQ_ID_Pos = 0x0        // Position of DMAREQ_ID field.
	DMAMUX_C5CR_DMAREQ_ID_Msk = 0xff       // Bit mask of DMAREQ_ID field.
	DMAMUX_C5CR_SOIE_Pos      = 0x8        // Position of SOIE field.
	DMAMUX_C5CR_SOIE_Msk      = 0x100      // Bit mask of SOIE field.
	DMAMUX_C5CR_SOIE          = 0x100      // Bit SOIE.
	DMAMUX_C5CR_EGE_Pos       = 0x9        // Position of EGE field.
	DMAMUX_C5CR_EGE_Msk       = 0x200      // Bit mask of EGE field.
	DMAMUX_C5CR_EGE           = 0x200      // Bit EGE.
	DMAMUX_C5CR_SE_Pos        = 0x10       // Position of SE field.
	DMAMUX_C5CR_SE_Msk        = 0x10000    // Bit mask of SE field.
	DMAMUX_C5CR_SE            = 0x10000    // Bit SE.
	DMAMUX_C5CR_SPOL_Pos      = 0x11       // Position of SPOL field.
	DMAMUX_C5CR_SPOL_Msk      = 0x60000    // Bit mask of SPOL field.
	DMAMUX_C5CR_NBREQ_Pos     = 0x13       // Position of NBREQ field.
	DMAMUX_C5CR_NBREQ_Msk     = 0xf80000   // Bit mask of NBREQ field.
	DMAMUX_C5CR_SYNC_ID_Pos   = 0x18       // Position of SYNC_ID field.
	DMAMUX_C5CR_SYNC_ID_Msk   = 0x1f000000 // Bit mask of SYNC_ID field.

	// C6CR: DMAMux - DMA request line multiplexer           channel x control register
	DMAMUX_C6CR_DMAREQ_ID_Pos = 0x0        // Position of DMAREQ_ID field.
	DMAMUX_C6CR_DMAREQ_ID_Msk = 0xff       // Bit mask of DMAREQ_ID field.
	DMAMUX_C6CR_SOIE_Pos      = 0x8        // Position of SOIE field.
	DMAMUX_C6CR_SOIE_Msk      = 0x100      // Bit mask of SOIE field.
	DMAMUX_C6CR_SOIE          = 0x100      // Bit SOIE.
	DMAMUX_C6CR_EGE_Pos       = 0x9        // Position of EGE field.
	DMAMUX_C6CR_EGE_Msk       = 0x200      // Bit mask of EGE field.
	DMAMUX_C6CR_EGE           = 0x200      // Bit EGE.
	DMAMUX_C6CR_SE_Pos        = 0x10       // Position of SE field.
	DMAMUX_C6CR_SE_Msk        = 0x10000    // Bit mask of SE field.
	DMAMUX_C6CR_SE            = 0x10000    // Bit SE.
	DMAMUX_C6CR_SPOL_Pos      = 0x11       // Position of SPOL field.
	DMAMUX_C6CR_SPOL_Msk      = 0x60000    // Bit mask of SPOL field.
	DMAMUX_C6CR_NBREQ_Pos     = 0x13       // Position of NBREQ field.
	DMAMUX_C6CR_NBREQ_Msk     = 0xf80000   // Bit mask of NBREQ field.
	DMAMUX_C6CR_SYNC_ID_Pos   = 0x18       // Position of SYNC_ID field.
	DMAMUX_C6CR_SYNC_ID_Msk   = 0x1f000000 // Bit mask of SYNC_ID field.

	// C7CR: DMAMux - DMA request line multiplexer           channel x control register
	DMAMUX_C7CR_DMAREQ_ID_Pos = 0x0        // Position of DMAREQ_ID field.
	DMAMUX_C7CR_DMAREQ_ID_Msk = 0xff       // Bit mask of DMAREQ_ID field.
	DMAMUX_C7CR_SOIE_Pos      = 0x8        // Position of SOIE field.
	DMAMUX_C7CR_SOIE_Msk      = 0x100      // Bit mask of SOIE field.
	DMAMUX_C7CR_SOIE          = 0x100      // Bit SOIE.
	DMAMUX_C7CR_EGE_Pos       = 0x9        // Position of EGE field.
	DMAMUX_C7CR_EGE_Msk       = 0x200      // Bit mask of EGE field.
	DMAMUX_C7CR_EGE           = 0x200      // Bit EGE.
	DMAMUX_C7CR_SE_Pos        = 0x10       // Position of SE field.
	DMAMUX_C7CR_SE_Msk        = 0x10000    // Bit mask of SE field.
	DMAMUX_C7CR_SE            = 0x10000    // Bit SE.
	DMAMUX_C7CR_SPOL_Pos      = 0x11       // Position of SPOL field.
	DMAMUX_C7CR_SPOL_Msk      = 0x60000    // Bit mask of SPOL field.
	DMAMUX_C7CR_NBREQ_Pos     = 0x13       // Position of NBREQ field.
	DMAMUX_C7CR_NBREQ_Msk     = 0xf80000   // Bit mask of NBREQ field.
	DMAMUX_C7CR_SYNC_ID_Pos   = 0x18       // Position of SYNC_ID field.
	DMAMUX_C7CR_SYNC_ID_Msk   = 0x1f000000 // Bit mask of SYNC_ID field.

	// CSR: DMAMUX request line multiplexer interrupt           channel status register
	DMAMUX_CSR_SOF_Pos = 0x0    // Position of SOF field.
	DMAMUX_CSR_SOF_Msk = 0xffff // Bit mask of SOF field.

	// CFR: DMAMUX request line multiplexer interrupt           clear flag register
	DMAMUX_CFR_CSOF_Pos = 0x0    // Position of CSOF field.
	DMAMUX_CFR_CSOF_Msk = 0xffff // Bit mask of CSOF field.

	// RG0CR: DMAMux - DMA request generator channel x           control register
	DMAMUX_RG0CR_SIG_ID_Pos = 0x0      // Position of SIG_ID field.
	DMAMUX_RG0CR_SIG_ID_Msk = 0x1f     // Bit mask of SIG_ID field.
	DMAMUX_RG0CR_OIE_Pos    = 0x8      // Position of OIE field.
	DMAMUX_RG0CR_OIE_Msk    = 0x100    // Bit mask of OIE field.
	DMAMUX_RG0CR_OIE        = 0x100    // Bit OIE.
	DMAMUX_RG0CR_GE_Pos     = 0x10     // Position of GE field.
	DMAMUX_RG0CR_GE_Msk     = 0x10000  // Bit mask of GE field.
	DMAMUX_RG0CR_GE         = 0x10000  // Bit GE.
	DMAMUX_RG0CR_GPOL_Pos   = 0x11     // Position of GPOL field.
	DMAMUX_RG0CR_GPOL_Msk   = 0x60000  // Bit mask of GPOL field.
	DMAMUX_RG0CR_GNBREQ_Pos = 0x13     // Position of GNBREQ field.
	DMAMUX_RG0CR_GNBREQ_Msk = 0xf80000 // Bit mask of GNBREQ field.

	// RG1CR: DMAMux - DMA request generator channel x           control register
	DMAMUX_RG1CR_SIG_ID_Pos = 0x0      // Position of SIG_ID field.
	DMAMUX_RG1CR_SIG_ID_Msk = 0x1f     // Bit mask of SIG_ID field.
	DMAMUX_RG1CR_OIE_Pos    = 0x8      // Position of OIE field.
	DMAMUX_RG1CR_OIE_Msk    = 0x100    // Bit mask of OIE field.
	DMAMUX_RG1CR_OIE        = 0x100    // Bit OIE.
	DMAMUX_RG1CR_GE_Pos     = 0x10     // Position of GE field.
	DMAMUX_RG1CR_GE_Msk     = 0x10000  // Bit mask of GE field.
	DMAMUX_RG1CR_GE         = 0x10000  // Bit GE.
	DMAMUX_RG1CR_GPOL_Pos   = 0x11     // Position of GPOL field.
	DMAMUX_RG1CR_GPOL_Msk   = 0x60000  // Bit mask of GPOL field.
	DMAMUX_RG1CR_GNBREQ_Pos = 0x13     // Position of GNBREQ field.
	DMAMUX_RG1CR_GNBREQ_Msk = 0xf80000 // Bit mask of GNBREQ field.

	// RG2CR: DMAMux - DMA request generator channel x           control register
	DMAMUX_RG2CR_SIG_ID_Pos = 0x0      // Position of SIG_ID field.
	DMAMUX_RG2CR_SIG_ID_Msk = 0x1f     // Bit mask of SIG_ID field.
	DMAMUX_RG2CR_OIE_Pos    = 0x8      // Position of OIE field.
	DMAMUX_RG2CR_OIE_Msk    = 0x100    // Bit mask of OIE field.
	DMAMUX_RG2CR_OIE        = 0x100    // Bit OIE.
	DMAMUX_RG2CR_GE_Pos     = 0x10     // Position of GE field.
	DMAMUX_RG2CR_GE_Msk     = 0x10000  // Bit mask of GE field.
	DMAMUX_RG2CR_GE         = 0x10000  // Bit GE.
	DMAMUX_RG2CR_GPOL_Pos   = 0x11     // Position of GPOL field.
	DMAMUX_RG2CR_GPOL_Msk   = 0x60000  // Bit mask of GPOL field.
	DMAMUX_RG2CR_GNBREQ_Pos = 0x13     // Position of GNBREQ field.
	DMAMUX_RG2CR_GNBREQ_Msk = 0xf80000 // Bit mask of GNBREQ field.

	// RG3CR: DMAMux - DMA request generator channel x           control register
	DMAMUX_RG3CR_SIG_ID_Pos = 0x0      // Position of SIG_ID field.
	DMAMUX_RG3CR_SIG_ID_Msk = 0x1f     // Bit mask of SIG_ID field.
	DMAMUX_RG3CR_OIE_Pos    = 0x8      // Position of OIE field.
	DMAMUX_RG3CR_OIE_Msk    = 0x100    // Bit mask of OIE field.
	DMAMUX_RG3CR_OIE        = 0x100    // Bit OIE.
	DMAMUX_RG3CR_GE_Pos     = 0x10     // Position of GE field.
	DMAMUX_RG3CR_GE_Msk     = 0x10000  // Bit mask of GE field.
	DMAMUX_RG3CR_GE         = 0x10000  // Bit GE.
	DMAMUX_RG3CR_GPOL_Pos   = 0x11     // Position of GPOL field.
	DMAMUX_RG3CR_GPOL_Msk   = 0x60000  // Bit mask of GPOL field.
	DMAMUX_RG3CR_GNBREQ_Pos = 0x13     // Position of GNBREQ field.
	DMAMUX_RG3CR_GNBREQ_Msk = 0xf80000 // Bit mask of GNBREQ field.

	// RG4CR: DMAMux - DMA request generator channel x           control register
	DMAMUX_RG4CR_SIG_ID_Pos = 0x0      // Position of SIG_ID field.
	DMAMUX_RG4CR_SIG_ID_Msk = 0x1f     // Bit mask of SIG_ID field.
	DMAMUX_RG4CR_OIE_Pos    = 0x8      // Position of OIE field.
	DMAMUX_RG4CR_OIE_Msk    = 0x100    // Bit mask of OIE field.
	DMAMUX_RG4CR_OIE        = 0x100    // Bit OIE.
	DMAMUX_RG4CR_GE_Pos     = 0x10     // Position of GE field.
	DMAMUX_RG4CR_GE_Msk     = 0x10000  // Bit mask of GE field.
	DMAMUX_RG4CR_GE         = 0x10000  // Bit GE.
	DMAMUX_RG4CR_GPOL_Pos   = 0x11     // Position of GPOL field.
	DMAMUX_RG4CR_GPOL_Msk   = 0x60000  // Bit mask of GPOL field.
	DMAMUX_RG4CR_GNBREQ_Pos = 0x13     // Position of GNBREQ field.
	DMAMUX_RG4CR_GNBREQ_Msk = 0xf80000 // Bit mask of GNBREQ field.

	// RG5CR: DMAMux - DMA request generator channel x           control register
	DMAMUX_RG5CR_SIG_ID_Pos = 0x0      // Position of SIG_ID field.
	DMAMUX_RG5CR_SIG_ID_Msk = 0x1f     // Bit mask of SIG_ID field.
	DMAMUX_RG5CR_OIE_Pos    = 0x8      // Position of OIE field.
	DMAMUX_RG5CR_OIE_Msk    = 0x100    // Bit mask of OIE field.
	DMAMUX_RG5CR_OIE        = 0x100    // Bit OIE.
	DMAMUX_RG5CR_GE_Pos     = 0x10     // Position of GE field.
	DMAMUX_RG5CR_GE_Msk     = 0x10000  // Bit mask of GE field.
	DMAMUX_RG5CR_GE         = 0x10000  // Bit GE.
	DMAMUX_RG5CR_GPOL_Pos   = 0x11     // Position of GPOL field.
	DMAMUX_RG5CR_GPOL_Msk   = 0x60000  // Bit mask of GPOL field.
	DMAMUX_RG5CR_GNBREQ_Pos = 0x13     // Position of GNBREQ field.
	DMAMUX_RG5CR_GNBREQ_Msk = 0xf80000 // Bit mask of GNBREQ field.

	// RG6CR: DMAMux - DMA request generator channel x           control register
	DMAMUX_RG6CR_SIG_ID_Pos = 0x0      // Position of SIG_ID field.
	DMAMUX_RG6CR_SIG_ID_Msk = 0x1f     // Bit mask of SIG_ID field.
	DMAMUX_RG6CR_OIE_Pos    = 0x8      // Position of OIE field.
	DMAMUX_RG6CR_OIE_Msk    = 0x100    // Bit mask of OIE field.
	DMAMUX_RG6CR_OIE        = 0x100    // Bit OIE.
	DMAMUX_RG6CR_GE_Pos     = 0x10     // Position of GE field.
	DMAMUX_RG6CR_GE_Msk     = 0x10000  // Bit mask of GE field.
	DMAMUX_RG6CR_GE         = 0x10000  // Bit GE.
	DMAMUX_RG6CR_GPOL_Pos   = 0x11     // Position of GPOL field.
	DMAMUX_RG6CR_GPOL_Msk   = 0x60000  // Bit mask of GPOL field.
	DMAMUX_RG6CR_GNBREQ_Pos = 0x13     // Position of GNBREQ field.
	DMAMUX_RG6CR_GNBREQ_Msk = 0xf80000 // Bit mask of GNBREQ field.

	// RG7CR: DMAMux - DMA request generator channel x           control register
	DMAMUX_RG7CR_SIG_ID_Pos = 0x0      // Position of SIG_ID field.
	DMAMUX_RG7CR_SIG_ID_Msk = 0x1f     // Bit mask of SIG_ID field.
	DMAMUX_RG7CR_OIE_Pos    = 0x8      // Position of OIE field.
	DMAMUX_RG7CR_OIE_Msk    = 0x100    // Bit mask of OIE field.
	DMAMUX_RG7CR_OIE        = 0x100    // Bit OIE.
	DMAMUX_RG7CR_GE_Pos     = 0x10     // Position of GE field.
	DMAMUX_RG7CR_GE_Msk     = 0x10000  // Bit mask of GE field.
	DMAMUX_RG7CR_GE         = 0x10000  // Bit GE.
	DMAMUX_RG7CR_GPOL_Pos   = 0x11     // Position of GPOL field.
	DMAMUX_RG7CR_GPOL_Msk   = 0x60000  // Bit mask of GPOL field.
	DMAMUX_RG7CR_GNBREQ_Pos = 0x13     // Position of GNBREQ field.
	DMAMUX_RG7CR_GNBREQ_Msk = 0xf80000 // Bit mask of GNBREQ field.

	// RGSR: DMAMux - DMA request generator status           register
	DMAMUX_RGSR_OF_Pos = 0x0  // Position of OF field.
	DMAMUX_RGSR_OF_Msk = 0xff // Bit mask of OF field.

	// RGCFR: DMAMux - DMA request generator clear flag           register
	DMAMUX_RGCFR_COF_Pos = 0x0  // Position of COF field.
	DMAMUX_RGCFR_COF_Msk = 0xff // Bit mask of COF field.
)

// Bitfields for FMC: FMC
const (
	// BCR1: This register contains the control           information of each memory bank, used for SRAMs, PSRAM           and NOR Flash memories.
	FMC_BCR1_MBKEN_Pos     = 0x0        // Position of MBKEN field.
	FMC_BCR1_MBKEN_Msk     = 0x1        // Bit mask of MBKEN field.
	FMC_BCR1_MBKEN         = 0x1        // Bit MBKEN.
	FMC_BCR1_MUXEN_Pos     = 0x1        // Position of MUXEN field.
	FMC_BCR1_MUXEN_Msk     = 0x2        // Bit mask of MUXEN field.
	FMC_BCR1_MUXEN         = 0x2        // Bit MUXEN.
	FMC_BCR1_MTYP_Pos      = 0x2        // Position of MTYP field.
	FMC_BCR1_MTYP_Msk      = 0xc        // Bit mask of MTYP field.
	FMC_BCR1_MWID_Pos      = 0x4        // Position of MWID field.
	FMC_BCR1_MWID_Msk      = 0x30       // Bit mask of MWID field.
	FMC_BCR1_FACCEN_Pos    = 0x6        // Position of FACCEN field.
	FMC_BCR1_FACCEN_Msk    = 0x40       // Bit mask of FACCEN field.
	FMC_BCR1_FACCEN        = 0x40       // Bit FACCEN.
	FMC_BCR1_BURSTEN_Pos   = 0x8        // Position of BURSTEN field.
	FMC_BCR1_BURSTEN_Msk   = 0x100      // Bit mask of BURSTEN field.
	FMC_BCR1_BURSTEN       = 0x100      // Bit BURSTEN.
	FMC_BCR1_WAITPOL_Pos   = 0x9        // Position of WAITPOL field.
	FMC_BCR1_WAITPOL_Msk   = 0x200      // Bit mask of WAITPOL field.
	FMC_BCR1_WAITPOL       = 0x200      // Bit WAITPOL.
	FMC_BCR1_WAITCFG_Pos   = 0xb        // Position of WAITCFG field.
	FMC_BCR1_WAITCFG_Msk   = 0x800      // Bit mask of WAITCFG field.
	FMC_BCR1_WAITCFG       = 0x800      // Bit WAITCFG.
	FMC_BCR1_WREN_Pos      = 0xc        // Position of WREN field.
	FMC_BCR1_WREN_Msk      = 0x1000     // Bit mask of WREN field.
	FMC_BCR1_WREN          = 0x1000     // Bit WREN.
	FMC_BCR1_WAITEN_Pos    = 0xd        // Position of WAITEN field.
	FMC_BCR1_WAITEN_Msk    = 0x2000     // Bit mask of WAITEN field.
	FMC_BCR1_WAITEN        = 0x2000     // Bit WAITEN.
	FMC_BCR1_EXTMOD_Pos    = 0xe        // Position of EXTMOD field.
	FMC_BCR1_EXTMOD_Msk    = 0x4000     // Bit mask of EXTMOD field.
	FMC_BCR1_EXTMOD        = 0x4000     // Bit EXTMOD.
	FMC_BCR1_ASYNCWAIT_Pos = 0xf        // Position of ASYNCWAIT field.
	FMC_BCR1_ASYNCWAIT_Msk = 0x8000     // Bit mask of ASYNCWAIT field.
	FMC_BCR1_ASYNCWAIT     = 0x8000     // Bit ASYNCWAIT.
	FMC_BCR1_CPSIZE_Pos    = 0x10       // Position of CPSIZE field.
	FMC_BCR1_CPSIZE_Msk    = 0x70000    // Bit mask of CPSIZE field.
	FMC_BCR1_CBURSTRW_Pos  = 0x13       // Position of CBURSTRW field.
	FMC_BCR1_CBURSTRW_Msk  = 0x80000    // Bit mask of CBURSTRW field.
	FMC_BCR1_CBURSTRW      = 0x80000    // Bit CBURSTRW.
	FMC_BCR1_CCLKEN_Pos    = 0x14       // Position of CCLKEN field.
	FMC_BCR1_CCLKEN_Msk    = 0x100000   // Bit mask of CCLKEN field.
	FMC_BCR1_CCLKEN        = 0x100000   // Bit CCLKEN.
	FMC_BCR1_WFDIS_Pos     = 0x15       // Position of WFDIS field.
	FMC_BCR1_WFDIS_Msk     = 0x200000   // Bit mask of WFDIS field.
	FMC_BCR1_WFDIS         = 0x200000   // Bit WFDIS.
	FMC_BCR1_BMAP_Pos      = 0x18       // Position of BMAP field.
	FMC_BCR1_BMAP_Msk      = 0x3000000  // Bit mask of BMAP field.
	FMC_BCR1_FMCEN_Pos     = 0x1f       // Position of FMCEN field.
	FMC_BCR1_FMCEN_Msk     = 0x80000000 // Bit mask of FMCEN field.
	FMC_BCR1_FMCEN         = 0x80000000 // Bit FMCEN.

	// BTR1: This register contains the control           information of each memory bank, used for SRAMs, PSRAM           and NOR Flash memories.If the EXTMOD bit is set in the           FMC_BCRx register, then this register is partitioned for           write and read access, that is, 2 registers are           available: one to configure read accesses (this register)           and one to configure write accesses (FMC_BWTRx           registers).
	FMC_BTR1_ADDSET_Pos  = 0x0        // Position of ADDSET field.
	FMC_BTR1_ADDSET_Msk  = 0xf        // Bit mask of ADDSET field.
	FMC_BTR1_ADDHLD_Pos  = 0x4        // Position of ADDHLD field.
	FMC_BTR1_ADDHLD_Msk  = 0xf0       // Bit mask of ADDHLD field.
	FMC_BTR1_DATAST_Pos  = 0x8        // Position of DATAST field.
	FMC_BTR1_DATAST_Msk  = 0xff00     // Bit mask of DATAST field.
	FMC_BTR1_BUSTURN_Pos = 0x10       // Position of BUSTURN field.
	FMC_BTR1_BUSTURN_Msk = 0xf0000    // Bit mask of BUSTURN field.
	FMC_BTR1_CLKDIV_Pos  = 0x14       // Position of CLKDIV field.
	FMC_BTR1_CLKDIV_Msk  = 0xf00000   // Bit mask of CLKDIV field.
	FMC_BTR1_DATLAT_Pos  = 0x18       // Position of DATLAT field.
	FMC_BTR1_DATLAT_Msk  = 0xf000000  // Bit mask of DATLAT field.
	FMC_BTR1_ACCMOD_Pos  = 0x1c       // Position of ACCMOD field.
	FMC_BTR1_ACCMOD_Msk  = 0x30000000 // Bit mask of ACCMOD field.

	// BCR2: This register contains the control           information of each memory bank, used for SRAMs, PSRAM           and NOR Flash memories.
	FMC_BCR2_MBKEN_Pos     = 0x0        // Position of MBKEN field.
	FMC_BCR2_MBKEN_Msk     = 0x1        // Bit mask of MBKEN field.
	FMC_BCR2_MBKEN         = 0x1        // Bit MBKEN.
	FMC_BCR2_MUXEN_Pos     = 0x1        // Position of MUXEN field.
	FMC_BCR2_MUXEN_Msk     = 0x2        // Bit mask of MUXEN field.
	FMC_BCR2_MUXEN         = 0x2        // Bit MUXEN.
	FMC_BCR2_MTYP_Pos      = 0x2        // Position of MTYP field.
	FMC_BCR2_MTYP_Msk      = 0xc        // Bit mask of MTYP field.
	FMC_BCR2_MWID_Pos      = 0x4        // Position of MWID field.
	FMC_BCR2_MWID_Msk      = 0x30       // Bit mask of MWID field.
	FMC_BCR2_FACCEN_Pos    = 0x6        // Position of FACCEN field.
	FMC_BCR2_FACCEN_Msk    = 0x40       // Bit mask of FACCEN field.
	FMC_BCR2_FACCEN        = 0x40       // Bit FACCEN.
	FMC_BCR2_BURSTEN_Pos   = 0x8        // Position of BURSTEN field.
	FMC_BCR2_BURSTEN_Msk   = 0x100      // Bit mask of BURSTEN field.
	FMC_BCR2_BURSTEN       = 0x100      // Bit BURSTEN.
	FMC_BCR2_WAITPOL_Pos   = 0x9        // Position of WAITPOL field.
	FMC_BCR2_WAITPOL_Msk   = 0x200      // Bit mask of WAITPOL field.
	FMC_BCR2_WAITPOL       = 0x200      // Bit WAITPOL.
	FMC_BCR2_WAITCFG_Pos   = 0xb        // Position of WAITCFG field.
	FMC_BCR2_WAITCFG_Msk   = 0x800      // Bit mask of WAITCFG field.
	FMC_BCR2_WAITCFG       = 0x800      // Bit WAITCFG.
	FMC_BCR2_WREN_Pos      = 0xc        // Position of WREN field.
	FMC_BCR2_WREN_Msk      = 0x1000     // Bit mask of WREN field.
	FMC_BCR2_WREN          = 0x1000     // Bit WREN.
	FMC_BCR2_WAITEN_Pos    = 0xd        // Position of WAITEN field.
	FMC_BCR2_WAITEN_Msk    = 0x2000     // Bit mask of WAITEN field.
	FMC_BCR2_WAITEN        = 0x2000     // Bit WAITEN.
	FMC_BCR2_EXTMOD_Pos    = 0xe        // Position of EXTMOD field.
	FMC_BCR2_EXTMOD_Msk    = 0x4000     // Bit mask of EXTMOD field.
	FMC_BCR2_EXTMOD        = 0x4000     // Bit EXTMOD.
	FMC_BCR2_ASYNCWAIT_Pos = 0xf        // Position of ASYNCWAIT field.
	FMC_BCR2_ASYNCWAIT_Msk = 0x8000     // Bit mask of ASYNCWAIT field.
	FMC_BCR2_ASYNCWAIT     = 0x8000     // Bit ASYNCWAIT.
	FMC_BCR2_CPSIZE_Pos    = 0x10       // Position of CPSIZE field.
	FMC_BCR2_CPSIZE_Msk    = 0x70000    // Bit mask of CPSIZE field.
	FMC_BCR2_CBURSTRW_Pos  = 0x13       // Position of CBURSTRW field.
	FMC_BCR2_CBURSTRW_Msk  = 0x80000    // Bit mask of CBURSTRW field.
	FMC_BCR2_CBURSTRW      = 0x80000    // Bit CBURSTRW.
	FMC_BCR2_CCLKEN_Pos    = 0x14       // Position of CCLKEN field.
	FMC_BCR2_CCLKEN_Msk    = 0x100000   // Bit mask of CCLKEN field.
	FMC_BCR2_CCLKEN        = 0x100000   // Bit CCLKEN.
	FMC_BCR2_WFDIS_Pos     = 0x15       // Position of WFDIS field.
	FMC_BCR2_WFDIS_Msk     = 0x200000   // Bit mask of WFDIS field.
	FMC_BCR2_WFDIS         = 0x200000   // Bit WFDIS.
	FMC_BCR2_BMAP_Pos      = 0x18       // Position of BMAP field.
	FMC_BCR2_BMAP_Msk      = 0x3000000  // Bit mask of BMAP field.
	FMC_BCR2_FMCEN_Pos     = 0x1f       // Position of FMCEN field.
	FMC_BCR2_FMCEN_Msk     = 0x80000000 // Bit mask of FMCEN field.
	FMC_BCR2_FMCEN         = 0x80000000 // Bit FMCEN.

	// BTR2: This register contains the control           information of each memory bank, used for SRAMs, PSRAM           and NOR Flash memories.If the EXTMOD bit is set in the           FMC_BCRx register, then this register is partitioned for           write and read access, that is, 2 registers are           available: one to configure read accesses (this register)           and one to configure write accesses (FMC_BWTRx           registers).
	FMC_BTR2_ADDSET_Pos  = 0x0        // Position of ADDSET field.
	FMC_BTR2_ADDSET_Msk  = 0xf        // Bit mask of ADDSET field.
	FMC_BTR2_ADDHLD_Pos  = 0x4        // Position of ADDHLD field.
	FMC_BTR2_ADDHLD_Msk  = 0xf0       // Bit mask of ADDHLD field.
	FMC_BTR2_DATAST_Pos  = 0x8        // Position of DATAST field.
	FMC_BTR2_DATAST_Msk  = 0xff00     // Bit mask of DATAST field.
	FMC_BTR2_BUSTURN_Pos = 0x10       // Position of BUSTURN field.
	FMC_BTR2_BUSTURN_Msk = 0xf0000    // Bit mask of BUSTURN field.
	FMC_BTR2_CLKDIV_Pos  = 0x14       // Position of CLKDIV field.
	FMC_BTR2_CLKDIV_Msk  = 0xf00000   // Bit mask of CLKDIV field.
	FMC_BTR2_DATLAT_Pos  = 0x18       // Position of DATLAT field.
	FMC_BTR2_DATLAT_Msk  = 0xf000000  // Bit mask of DATLAT field.
	FMC_BTR2_ACCMOD_Pos  = 0x1c       // Position of ACCMOD field.
	FMC_BTR2_ACCMOD_Msk  = 0x30000000 // Bit mask of ACCMOD field.

	// BCR3: This register contains the control           information of each memory bank, used for SRAMs, PSRAM           and NOR Flash memories.
	FMC_BCR3_MBKEN_Pos     = 0x0        // Position of MBKEN field.
	FMC_BCR3_MBKEN_Msk     = 0x1        // Bit mask of MBKEN field.
	FMC_BCR3_MBKEN         = 0x1        // Bit MBKEN.
	FMC_BCR3_MUXEN_Pos     = 0x1        // Position of MUXEN field.
	FMC_BCR3_MUXEN_Msk     = 0x2        // Bit mask of MUXEN field.
	FMC_BCR3_MUXEN         = 0x2        // Bit MUXEN.
	FMC_BCR3_MTYP_Pos      = 0x2        // Position of MTYP field.
	FMC_BCR3_MTYP_Msk      = 0xc        // Bit mask of MTYP field.
	FMC_BCR3_MWID_Pos      = 0x4        // Position of MWID field.
	FMC_BCR3_MWID_Msk      = 0x30       // Bit mask of MWID field.
	FMC_BCR3_FACCEN_Pos    = 0x6        // Position of FACCEN field.
	FMC_BCR3_FACCEN_Msk    = 0x40       // Bit mask of FACCEN field.
	FMC_BCR3_FACCEN        = 0x40       // Bit FACCEN.
	FMC_BCR3_BURSTEN_Pos   = 0x8        // Position of BURSTEN field.
	FMC_BCR3_BURSTEN_Msk   = 0x100      // Bit mask of BURSTEN field.
	FMC_BCR3_BURSTEN       = 0x100      // Bit BURSTEN.
	FMC_BCR3_WAITPOL_Pos   = 0x9        // Position of WAITPOL field.
	FMC_BCR3_WAITPOL_Msk   = 0x200      // Bit mask of WAITPOL field.
	FMC_BCR3_WAITPOL       = 0x200      // Bit WAITPOL.
	FMC_BCR3_WAITCFG_Pos   = 0xb        // Position of WAITCFG field.
	FMC_BCR3_WAITCFG_Msk   = 0x800      // Bit mask of WAITCFG field.
	FMC_BCR3_WAITCFG       = 0x800      // Bit WAITCFG.
	FMC_BCR3_WREN_Pos      = 0xc        // Position of WREN field.
	FMC_BCR3_WREN_Msk      = 0x1000     // Bit mask of WREN field.
	FMC_BCR3_WREN          = 0x1000     // Bit WREN.
	FMC_BCR3_WAITEN_Pos    = 0xd        // Position of WAITEN field.
	FMC_BCR3_WAITEN_Msk    = 0x2000     // Bit mask of WAITEN field.
	FMC_BCR3_WAITEN        = 0x2000     // Bit WAITEN.
	FMC_BCR3_EXTMOD_Pos    = 0xe        // Position of EXTMOD field.
	FMC_BCR3_EXTMOD_Msk    = 0x4000     // Bit mask of EXTMOD field.
	FMC_BCR3_EXTMOD        = 0x4000     // Bit EXTMOD.
	FMC_BCR3_ASYNCWAIT_Pos = 0xf        // Position of ASYNCWAIT field.
	FMC_BCR3_ASYNCWAIT_Msk = 0x8000     // Bit mask of ASYNCWAIT field.
	FMC_BCR3_ASYNCWAIT     = 0x8000     // Bit ASYNCWAIT.
	FMC_BCR3_CPSIZE_Pos    = 0x10       // Position of CPSIZE field.
	FMC_BCR3_CPSIZE_Msk    = 0x70000    // Bit mask of CPSIZE field.
	FMC_BCR3_CBURSTRW_Pos  = 0x13       // Position of CBURSTRW field.
	FMC_BCR3_CBURSTRW_Msk  = 0x80000    // Bit mask of CBURSTRW field.
	FMC_BCR3_CBURSTRW      = 0x80000    // Bit CBURSTRW.
	FMC_BCR3_CCLKEN_Pos    = 0x14       // Position of CCLKEN field.
	FMC_BCR3_CCLKEN_Msk    = 0x100000   // Bit mask of CCLKEN field.
	FMC_BCR3_CCLKEN        = 0x100000   // Bit CCLKEN.
	FMC_BCR3_WFDIS_Pos     = 0x15       // Position of WFDIS field.
	FMC_BCR3_WFDIS_Msk     = 0x200000   // Bit mask of WFDIS field.
	FMC_BCR3_WFDIS         = 0x200000   // Bit WFDIS.
	FMC_BCR3_BMAP_Pos      = 0x18       // Position of BMAP field.
	FMC_BCR3_BMAP_Msk      = 0x3000000  // Bit mask of BMAP field.
	FMC_BCR3_FMCEN_Pos     = 0x1f       // Position of FMCEN field.
	FMC_BCR3_FMCEN_Msk     = 0x80000000 // Bit mask of FMCEN field.
	FMC_BCR3_FMCEN         = 0x80000000 // Bit FMCEN.

	// BTR3: This register contains the control           information of each memory bank, used for SRAMs, PSRAM           and NOR Flash memories.If the EXTMOD bit is set in the           FMC_BCRx register, then this register is partitioned for           write and read access, that is, 2 registers are           available: one to configure read accesses (this register)           and one to configure write accesses (FMC_BWTRx           registers).
	FMC_BTR3_ADDSET_Pos  = 0x0        // Position of ADDSET field.
	FMC_BTR3_ADDSET_Msk  = 0xf        // Bit mask of ADDSET field.
	FMC_BTR3_ADDHLD_Pos  = 0x4        // Position of ADDHLD field.
	FMC_BTR3_ADDHLD_Msk  = 0xf0       // Bit mask of ADDHLD field.
	FMC_BTR3_DATAST_Pos  = 0x8        // Position of DATAST field.
	FMC_BTR3_DATAST_Msk  = 0xff00     // Bit mask of DATAST field.
	FMC_BTR3_BUSTURN_Pos = 0x10       // Position of BUSTURN field.
	FMC_BTR3_BUSTURN_Msk = 0xf0000    // Bit mask of BUSTURN field.
	FMC_BTR3_CLKDIV_Pos  = 0x14       // Position of CLKDIV field.
	FMC_BTR3_CLKDIV_Msk  = 0xf00000   // Bit mask of CLKDIV field.
	FMC_BTR3_DATLAT_Pos  = 0x18       // Position of DATLAT field.
	FMC_BTR3_DATLAT_Msk  = 0xf000000  // Bit mask of DATLAT field.
	FMC_BTR3_ACCMOD_Pos  = 0x1c       // Position of ACCMOD field.
	FMC_BTR3_ACCMOD_Msk  = 0x30000000 // Bit mask of ACCMOD field.

	// BCR4: This register contains the control           information of each memory bank, used for SRAMs, PSRAM           and NOR Flash memories.
	FMC_BCR4_MBKEN_Pos     = 0x0        // Position of MBKEN field.
	FMC_BCR4_MBKEN_Msk     = 0x1        // Bit mask of MBKEN field.
	FMC_BCR4_MBKEN         = 0x1        // Bit MBKEN.
	FMC_BCR4_MUXEN_Pos     = 0x1        // Position of MUXEN field.
	FMC_BCR4_MUXEN_Msk     = 0x2        // Bit mask of MUXEN field.
	FMC_BCR4_MUXEN         = 0x2        // Bit MUXEN.
	FMC_BCR4_MTYP_Pos      = 0x2        // Position of MTYP field.
	FMC_BCR4_MTYP_Msk      = 0xc        // Bit mask of MTYP field.
	FMC_BCR4_MWID_Pos      = 0x4        // Position of MWID field.
	FMC_BCR4_MWID_Msk      = 0x30       // Bit mask of MWID field.
	FMC_BCR4_FACCEN_Pos    = 0x6        // Position of FACCEN field.
	FMC_BCR4_FACCEN_Msk    = 0x40       // Bit mask of FACCEN field.
	FMC_BCR4_FACCEN        = 0x40       // Bit FACCEN.
	FMC_BCR4_BURSTEN_Pos   = 0x8        // Position of BURSTEN field.
	FMC_BCR4_BURSTEN_Msk   = 0x100      // Bit mask of BURSTEN field.
	FMC_BCR4_BURSTEN       = 0x100      // Bit BURSTEN.
	FMC_BCR4_WAITPOL_Pos   = 0x9        // Position of WAITPOL field.
	FMC_BCR4_WAITPOL_Msk   = 0x200      // Bit mask of WAITPOL field.
	FMC_BCR4_WAITPOL       = 0x200      // Bit WAITPOL.
	FMC_BCR4_WAITCFG_Pos   = 0xb        // Position of WAITCFG field.
	FMC_BCR4_WAITCFG_Msk   = 0x800      // Bit mask of WAITCFG field.
	FMC_BCR4_WAITCFG       = 0x800      // Bit WAITCFG.
	FMC_BCR4_WREN_Pos      = 0xc        // Position of WREN field.
	FMC_BCR4_WREN_Msk      = 0x1000     // Bit mask of WREN field.
	FMC_BCR4_WREN          = 0x1000     // Bit WREN.
	FMC_BCR4_WAITEN_Pos    = 0xd        // Position of WAITEN field.
	FMC_BCR4_WAITEN_Msk    = 0x2000     // Bit mask of WAITEN field.
	FMC_BCR4_WAITEN        = 0x2000     // Bit WAITEN.
	FMC_BCR4_EXTMOD_Pos    = 0xe        // Position of EXTMOD field.
	FMC_BCR4_EXTMOD_Msk    = 0x4000     // Bit mask of EXTMOD field.
	FMC_BCR4_EXTMOD        = 0x4000     // Bit EXTMOD.
	FMC_BCR4_ASYNCWAIT_Pos = 0xf        // Position of ASYNCWAIT field.
	FMC_BCR4_ASYNCWAIT_Msk = 0x8000     // Bit mask of ASYNCWAIT field.
	FMC_BCR4_ASYNCWAIT     = 0x8000     // Bit ASYNCWAIT.
	FMC_BCR4_CPSIZE_Pos    = 0x10       // Position of CPSIZE field.
	FMC_BCR4_CPSIZE_Msk    = 0x70000    // Bit mask of CPSIZE field.
	FMC_BCR4_CBURSTRW_Pos  = 0x13       // Position of CBURSTRW field.
	FMC_BCR4_CBURSTRW_Msk  = 0x80000    // Bit mask of CBURSTRW field.
	FMC_BCR4_CBURSTRW      = 0x80000    // Bit CBURSTRW.
	FMC_BCR4_CCLKEN_Pos    = 0x14       // Position of CCLKEN field.
	FMC_BCR4_CCLKEN_Msk    = 0x100000   // Bit mask of CCLKEN field.
	FMC_BCR4_CCLKEN        = 0x100000   // Bit CCLKEN.
	FMC_BCR4_WFDIS_Pos     = 0x15       // Position of WFDIS field.
	FMC_BCR4_WFDIS_Msk     = 0x200000   // Bit mask of WFDIS field.
	FMC_BCR4_WFDIS         = 0x200000   // Bit WFDIS.
	FMC_BCR4_BMAP_Pos      = 0x18       // Position of BMAP field.
	FMC_BCR4_BMAP_Msk      = 0x3000000  // Bit mask of BMAP field.
	FMC_BCR4_FMCEN_Pos     = 0x1f       // Position of FMCEN field.
	FMC_BCR4_FMCEN_Msk     = 0x80000000 // Bit mask of FMCEN field.
	FMC_BCR4_FMCEN         = 0x80000000 // Bit FMCEN.

	// BTR4: This register contains the control           information of each memory bank, used for SRAMs, PSRAM           and NOR Flash memories.If the EXTMOD bit is set in the           FMC_BCRx register, then this register is partitioned for           write and read access, that is, 2 registers are           available: one to configure read accesses (this register)           and one to configure write accesses (FMC_BWTRx           registers).
	FMC_BTR4_ADDSET_Pos  = 0x0        // Position of ADDSET field.
	FMC_BTR4_ADDSET_Msk  = 0xf        // Bit mask of ADDSET field.
	FMC_BTR4_ADDHLD_Pos  = 0x4        // Position of ADDHLD field.
	FMC_BTR4_ADDHLD_Msk  = 0xf0       // Bit mask of ADDHLD field.
	FMC_BTR4_DATAST_Pos  = 0x8        // Position of DATAST field.
	FMC_BTR4_DATAST_Msk  = 0xff00     // Bit mask of DATAST field.
	FMC_BTR4_BUSTURN_Pos = 0x10       // Position of BUSTURN field.
	FMC_BTR4_BUSTURN_Msk = 0xf0000    // Bit mask of BUSTURN field.
	FMC_BTR4_CLKDIV_Pos  = 0x14       // Position of CLKDIV field.
	FMC_BTR4_CLKDIV_Msk  = 0xf00000   // Bit mask of CLKDIV field.
	FMC_BTR4_DATLAT_Pos  = 0x18       // Position of DATLAT field.
	FMC_BTR4_DATLAT_Msk  = 0xf000000  // Bit mask of DATLAT field.
	FMC_BTR4_ACCMOD_Pos  = 0x1c       // Position of ACCMOD field.
	FMC_BTR4_ACCMOD_Msk  = 0x30000000 // Bit mask of ACCMOD field.

	// PCR: NAND Flash control registers
	FMC_PCR_PWAITEN_Pos = 0x1     // Position of PWAITEN field.
	FMC_PCR_PWAITEN_Msk = 0x2     // Bit mask of PWAITEN field.
	FMC_PCR_PWAITEN     = 0x2     // Bit PWAITEN.
	FMC_PCR_PBKEN_Pos   = 0x2     // Position of PBKEN field.
	FMC_PCR_PBKEN_Msk   = 0x4     // Bit mask of PBKEN field.
	FMC_PCR_PBKEN       = 0x4     // Bit PBKEN.
	FMC_PCR_PWID_Pos    = 0x4     // Position of PWID field.
	FMC_PCR_PWID_Msk    = 0x30    // Bit mask of PWID field.
	FMC_PCR_ECCEN_Pos   = 0x6     // Position of ECCEN field.
	FMC_PCR_ECCEN_Msk   = 0x40    // Bit mask of ECCEN field.
	FMC_PCR_ECCEN       = 0x40    // Bit ECCEN.
	FMC_PCR_TCLR_Pos    = 0x9     // Position of TCLR field.
	FMC_PCR_TCLR_Msk    = 0x1e00  // Bit mask of TCLR field.
	FMC_PCR_TAR_Pos     = 0xd     // Position of TAR field.
	FMC_PCR_TAR_Msk     = 0x1e000 // Bit mask of TAR field.
	FMC_PCR_ECCPS_Pos   = 0x11    // Position of ECCPS field.
	FMC_PCR_ECCPS_Msk   = 0xe0000 // Bit mask of ECCPS field.

	// SR: This register contains information about the           FIFO status and interrupt. The FMC features a FIFO that           is used when writing to memories to transfer up to 16           words of data.This is used to quickly write to the FIFO           and free the AXI bus for transactions to peripherals           other than the FMC, while the FMC is draining its FIFO           into the memory. One of these register bits indicates the           status of the FIFO, for ECC purposes.The ECC is           calculated while the data are written to the memory. To           read the correct ECC, the software must consequently wait           until the FIFO is empty.
	FMC_SR_IRS_Pos   = 0x0  // Position of IRS field.
	FMC_SR_IRS_Msk   = 0x1  // Bit mask of IRS field.
	FMC_SR_IRS       = 0x1  // Bit IRS.
	FMC_SR_ILS_Pos   = 0x1  // Position of ILS field.
	FMC_SR_ILS_Msk   = 0x2  // Bit mask of ILS field.
	FMC_SR_ILS       = 0x2  // Bit ILS.
	FMC_SR_IFS_Pos   = 0x2  // Position of IFS field.
	FMC_SR_IFS_Msk   = 0x4  // Bit mask of IFS field.
	FMC_SR_IFS       = 0x4  // Bit IFS.
	FMC_SR_IREN_Pos  = 0x3  // Position of IREN field.
	FMC_SR_IREN_Msk  = 0x8  // Bit mask of IREN field.
	FMC_SR_IREN      = 0x8  // Bit IREN.
	FMC_SR_ILEN_Pos  = 0x4  // Position of ILEN field.
	FMC_SR_ILEN_Msk  = 0x10 // Bit mask of ILEN field.
	FMC_SR_ILEN      = 0x10 // Bit ILEN.
	FMC_SR_IFEN_Pos  = 0x5  // Position of IFEN field.
	FMC_SR_IFEN_Msk  = 0x20 // Bit mask of IFEN field.
	FMC_SR_IFEN      = 0x20 // Bit IFEN.
	FMC_SR_FEMPT_Pos = 0x6  // Position of FEMPT field.
	FMC_SR_FEMPT_Msk = 0x40 // Bit mask of FEMPT field.
	FMC_SR_FEMPT     = 0x40 // Bit FEMPT.

	// PMEM: The FMC_PMEM read/write register contains           the timing information for NAND Flash memory bank. This           information is used to access either the common memory           space of the NAND Flash for command, address write access           and data read/write access.
	FMC_PMEM_MEMSET_Pos  = 0x0        // Position of MEMSET field.
	FMC_PMEM_MEMSET_Msk  = 0xff       // Bit mask of MEMSET field.
	FMC_PMEM_MEMWAIT_Pos = 0x8        // Position of MEMWAIT field.
	FMC_PMEM_MEMWAIT_Msk = 0xff00     // Bit mask of MEMWAIT field.
	FMC_PMEM_MEMHOLD_Pos = 0x10       // Position of MEMHOLD field.
	FMC_PMEM_MEMHOLD_Msk = 0xff0000   // Bit mask of MEMHOLD field.
	FMC_PMEM_MEMHIZ_Pos  = 0x18       // Position of MEMHIZ field.
	FMC_PMEM_MEMHIZ_Msk  = 0xff000000 // Bit mask of MEMHIZ field.

	// PATT: The FMC_PATT read/write register contains           the timing information for NAND Flash memory bank. It is           used for 8-bit accesses to the attribute memory space of           the NAND Flash for the last address write access if the           timing must differ from that of previous accesses (for           Ready/Busy management, refer to Section20.8.5: NAND Flash           prewait feature).
	FMC_PATT_ATTSET_Pos  = 0x0        // Position of ATTSET field.
	FMC_PATT_ATTSET_Msk  = 0xff       // Bit mask of ATTSET field.
	FMC_PATT_ATTWAIT_Pos = 0x8        // Position of ATTWAIT field.
	FMC_PATT_ATTWAIT_Msk = 0xff00     // Bit mask of ATTWAIT field.
	FMC_PATT_ATTHOLD_Pos = 0x10       // Position of ATTHOLD field.
	FMC_PATT_ATTHOLD_Msk = 0xff0000   // Bit mask of ATTHOLD field.
	FMC_PATT_ATTHIZ_Pos  = 0x18       // Position of ATTHIZ field.
	FMC_PATT_ATTHIZ_Msk  = 0xff000000 // Bit mask of ATTHIZ field.

	// ECCR: This register contain the current error           correction code value computed by the ECC computation           modules of the FMC NAND controller. When the CPU           reads/writes the data from a NAND Flash memory page at           the correct address (refer to Section20.8.6: Computation           of the error correction code (ECC) in NAND Flash memory),           the data read/written from/to the NAND Flash memory are           processed automatically by the ECC computation module.           When X bytes have been read (according to the ECCPS field           in the FMC_PCR registers), the CPU must read the computed           ECC value from the FMC_ECC registers. It then verifies if           these computed parity data are the same as the parity           value recorded in the spare area, to determine whether a           page is valid, and, to correct it otherwise. The FMC_ECCR           register should be cleared after being read by setting           the ECCEN bit to 0. To compute a new data block, the           ECCEN bit must be set to 1.
	FMC_ECCR_ECC_Pos = 0x0        // Position of ECC field.
	FMC_ECCR_ECC_Msk = 0xffffffff // Bit mask of ECC field.

	// BWTR1: This register contains the control           information of each memory bank. It is used for SRAMs,           PSRAMs and NOR Flash memories. When the EXTMOD bit is set           in the FMC_BCRx register, then this register is active           for write access.
	FMC_BWTR1_ADDSET_Pos  = 0x0        // Position of ADDSET field.
	FMC_BWTR1_ADDSET_Msk  = 0xf        // Bit mask of ADDSET field.
	FMC_BWTR1_ADDHLD_Pos  = 0x4        // Position of ADDHLD field.
	FMC_BWTR1_ADDHLD_Msk  = 0xf0       // Bit mask of ADDHLD field.
	FMC_BWTR1_DATAST_Pos  = 0x8        // Position of DATAST field.
	FMC_BWTR1_DATAST_Msk  = 0xff00     // Bit mask of DATAST field.
	FMC_BWTR1_BUSTURN_Pos = 0x10       // Position of BUSTURN field.
	FMC_BWTR1_BUSTURN_Msk = 0xf0000    // Bit mask of BUSTURN field.
	FMC_BWTR1_ACCMOD_Pos  = 0x1c       // Position of ACCMOD field.
	FMC_BWTR1_ACCMOD_Msk  = 0x30000000 // Bit mask of ACCMOD field.

	// BWTR2: This register contains the control           information of each memory bank. It is used for SRAMs,           PSRAMs and NOR Flash memories. When the EXTMOD bit is set           in the FMC_BCRx register, then this register is active           for write access.
	FMC_BWTR2_ADDSET_Pos  = 0x0        // Position of ADDSET field.
	FMC_BWTR2_ADDSET_Msk  = 0xf        // Bit mask of ADDSET field.
	FMC_BWTR2_ADDHLD_Pos  = 0x4        // Position of ADDHLD field.
	FMC_BWTR2_ADDHLD_Msk  = 0xf0       // Bit mask of ADDHLD field.
	FMC_BWTR2_DATAST_Pos  = 0x8        // Position of DATAST field.
	FMC_BWTR2_DATAST_Msk  = 0xff00     // Bit mask of DATAST field.
	FMC_BWTR2_BUSTURN_Pos = 0x10       // Position of BUSTURN field.
	FMC_BWTR2_BUSTURN_Msk = 0xf0000    // Bit mask of BUSTURN field.
	FMC_BWTR2_ACCMOD_Pos  = 0x1c       // Position of ACCMOD field.
	FMC_BWTR2_ACCMOD_Msk  = 0x30000000 // Bit mask of ACCMOD field.

	// BWTR3: This register contains the control           information of each memory bank. It is used for SRAMs,           PSRAMs and NOR Flash memories. When the EXTMOD bit is set           in the FMC_BCRx register, then this register is active           for write access.
	FMC_BWTR3_ADDSET_Pos  = 0x0        // Position of ADDSET field.
	FMC_BWTR3_ADDSET_Msk  = 0xf        // Bit mask of ADDSET field.
	FMC_BWTR3_ADDHLD_Pos  = 0x4        // Position of ADDHLD field.
	FMC_BWTR3_ADDHLD_Msk  = 0xf0       // Bit mask of ADDHLD field.
	FMC_BWTR3_DATAST_Pos  = 0x8        // Position of DATAST field.
	FMC_BWTR3_DATAST_Msk  = 0xff00     // Bit mask of DATAST field.
	FMC_BWTR3_BUSTURN_Pos = 0x10       // Position of BUSTURN field.
	FMC_BWTR3_BUSTURN_Msk = 0xf0000    // Bit mask of BUSTURN field.
	FMC_BWTR3_ACCMOD_Pos  = 0x1c       // Position of ACCMOD field.
	FMC_BWTR3_ACCMOD_Msk  = 0x30000000 // Bit mask of ACCMOD field.

	// BWTR4: This register contains the control           information of each memory bank. It is used for SRAMs,           PSRAMs and NOR Flash memories. When the EXTMOD bit is set           in the FMC_BCRx register, then this register is active           for write access.
	FMC_BWTR4_ADDSET_Pos  = 0x0        // Position of ADDSET field.
	FMC_BWTR4_ADDSET_Msk  = 0xf        // Bit mask of ADDSET field.
	FMC_BWTR4_ADDHLD_Pos  = 0x4        // Position of ADDHLD field.
	FMC_BWTR4_ADDHLD_Msk  = 0xf0       // Bit mask of ADDHLD field.
	FMC_BWTR4_DATAST_Pos  = 0x8        // Position of DATAST field.
	FMC_BWTR4_DATAST_Msk  = 0xff00     // Bit mask of DATAST field.
	FMC_BWTR4_BUSTURN_Pos = 0x10       // Position of BUSTURN field.
	FMC_BWTR4_BUSTURN_Msk = 0xf0000    // Bit mask of BUSTURN field.
	FMC_BWTR4_ACCMOD_Pos  = 0x1c       // Position of ACCMOD field.
	FMC_BWTR4_ACCMOD_Msk  = 0x30000000 // Bit mask of ACCMOD field.

	// SDCR1: This register contains the control           parameters for each SDRAM memory bank
	FMC_SDCR1_NC_Pos     = 0x0    // Position of NC field.
	FMC_SDCR1_NC_Msk     = 0x3    // Bit mask of NC field.
	FMC_SDCR1_NR_Pos     = 0x2    // Position of NR field.
	FMC_SDCR1_NR_Msk     = 0xc    // Bit mask of NR field.
	FMC_SDCR1_MWID_Pos   = 0x4    // Position of MWID field.
	FMC_SDCR1_MWID_Msk   = 0x30   // Bit mask of MWID field.
	FMC_SDCR1_NB_Pos     = 0x6    // Position of NB field.
	FMC_SDCR1_NB_Msk     = 0x40   // Bit mask of NB field.
	FMC_SDCR1_NB         = 0x40   // Bit NB.
	FMC_SDCR1_CAS_Pos    = 0x7    // Position of CAS field.
	FMC_SDCR1_CAS_Msk    = 0x180  // Bit mask of CAS field.
	FMC_SDCR1_WP_Pos     = 0x9    // Position of WP field.
	FMC_SDCR1_WP_Msk     = 0x200  // Bit mask of WP field.
	FMC_SDCR1_WP         = 0x200  // Bit WP.
	FMC_SDCR1_SDCLK_Pos  = 0xa    // Position of SDCLK field.
	FMC_SDCR1_SDCLK_Msk  = 0xc00  // Bit mask of SDCLK field.
	FMC_SDCR1_RBURST_Pos = 0xc    // Position of RBURST field.
	FMC_SDCR1_RBURST_Msk = 0x1000 // Bit mask of RBURST field.
	FMC_SDCR1_RBURST     = 0x1000 // Bit RBURST.
	FMC_SDCR1_RPIPE_Pos  = 0xd    // Position of RPIPE field.
	FMC_SDCR1_RPIPE_Msk  = 0x6000 // Bit mask of RPIPE field.

	// SDCR2: This register contains the control           parameters for each SDRAM memory bank
	FMC_SDCR2_NC_Pos     = 0x0    // Position of NC field.
	FMC_SDCR2_NC_Msk     = 0x3    // Bit mask of NC field.
	FMC_SDCR2_NR_Pos     = 0x2    // Position of NR field.
	FMC_SDCR2_NR_Msk     = 0xc    // Bit mask of NR field.
	FMC_SDCR2_MWID_Pos   = 0x4    // Position of MWID field.
	FMC_SDCR2_MWID_Msk   = 0x30   // Bit mask of MWID field.
	FMC_SDCR2_NB_Pos     = 0x6    // Position of NB field.
	FMC_SDCR2_NB_Msk     = 0x40   // Bit mask of NB field.
	FMC_SDCR2_NB         = 0x40   // Bit NB.
	FMC_SDCR2_CAS_Pos    = 0x7    // Position of CAS field.
	FMC_SDCR2_CAS_Msk    = 0x180  // Bit mask of CAS field.
	FMC_SDCR2_WP_Pos     = 0x9    // Position of WP field.
	FMC_SDCR2_WP_Msk     = 0x200  // Bit mask of WP field.
	FMC_SDCR2_WP         = 0x200  // Bit WP.
	FMC_SDCR2_SDCLK_Pos  = 0xa    // Position of SDCLK field.
	FMC_SDCR2_SDCLK_Msk  = 0xc00  // Bit mask of SDCLK field.
	FMC_SDCR2_RBURST_Pos = 0xc    // Position of RBURST field.
	FMC_SDCR2_RBURST_Msk = 0x1000 // Bit mask of RBURST field.
	FMC_SDCR2_RBURST     = 0x1000 // Bit RBURST.
	FMC_SDCR2_RPIPE_Pos  = 0xd    // Position of RPIPE field.
	FMC_SDCR2_RPIPE_Msk  = 0x6000 // Bit mask of RPIPE field.

	// SDTR1: This register contains the timing parameters           of each SDRAM bank
	FMC_SDTR1_TMRD_Pos = 0x0       // Position of TMRD field.
	FMC_SDTR1_TMRD_Msk = 0xf       // Bit mask of TMRD field.
	FMC_SDTR1_TXSR_Pos = 0x4       // Position of TXSR field.
	FMC_SDTR1_TXSR_Msk = 0xf0      // Bit mask of TXSR field.
	FMC_SDTR1_TRAS_Pos = 0x8       // Position of TRAS field.
	FMC_SDTR1_TRAS_Msk = 0xf00     // Bit mask of TRAS field.
	FMC_SDTR1_TRC_Pos  = 0xc       // Position of TRC field.
	FMC_SDTR1_TRC_Msk  = 0xf000    // Bit mask of TRC field.
	FMC_SDTR1_TWR_Pos  = 0x10      // Position of TWR field.
	FMC_SDTR1_TWR_Msk  = 0xf0000   // Bit mask of TWR field.
	FMC_SDTR1_TRP_Pos  = 0x14      // Position of TRP field.
	FMC_SDTR1_TRP_Msk  = 0xf00000  // Bit mask of TRP field.
	FMC_SDTR1_TRCD_Pos = 0x18      // Position of TRCD field.
	FMC_SDTR1_TRCD_Msk = 0xf000000 // Bit mask of TRCD field.

	// SDTR2: This register contains the timing parameters           of each SDRAM bank
	FMC_SDTR2_TMRD_Pos = 0x0       // Position of TMRD field.
	FMC_SDTR2_TMRD_Msk = 0xf       // Bit mask of TMRD field.
	FMC_SDTR2_TXSR_Pos = 0x4       // Position of TXSR field.
	FMC_SDTR2_TXSR_Msk = 0xf0      // Bit mask of TXSR field.
	FMC_SDTR2_TRAS_Pos = 0x8       // Position of TRAS field.
	FMC_SDTR2_TRAS_Msk = 0xf00     // Bit mask of TRAS field.
	FMC_SDTR2_TRC_Pos  = 0xc       // Position of TRC field.
	FMC_SDTR2_TRC_Msk  = 0xf000    // Bit mask of TRC field.
	FMC_SDTR2_TWR_Pos  = 0x10      // Position of TWR field.
	FMC_SDTR2_TWR_Msk  = 0xf0000   // Bit mask of TWR field.
	FMC_SDTR2_TRP_Pos  = 0x14      // Position of TRP field.
	FMC_SDTR2_TRP_Msk  = 0xf00000  // Bit mask of TRP field.
	FMC_SDTR2_TRCD_Pos = 0x18      // Position of TRCD field.
	FMC_SDTR2_TRCD_Msk = 0xf000000 // Bit mask of TRCD field.

	// SDCMR: This register contains the command issued           when the SDRAM device is accessed. This register is used           to initialize the SDRAM device, and to activate the           Self-refresh and the Power-down modes. As soon as the           MODE field is written, the command will be issued only to           one or to both SDRAM banks according to CTB1 and CTB2           command bits. This register is the same for both SDRAM           banks.
	FMC_SDCMR_MODE_Pos = 0x0      // Position of MODE field.
	FMC_SDCMR_MODE_Msk = 0x7      // Bit mask of MODE field.
	FMC_SDCMR_CTB2_Pos = 0x3      // Position of CTB2 field.
	FMC_SDCMR_CTB2_Msk = 0x8      // Bit mask of CTB2 field.
	FMC_SDCMR_CTB2     = 0x8      // Bit CTB2.
	FMC_SDCMR_CTB1_Pos = 0x4      // Position of CTB1 field.
	FMC_SDCMR_CTB1_Msk = 0x10     // Bit mask of CTB1 field.
	FMC_SDCMR_CTB1     = 0x10     // Bit CTB1.
	FMC_SDCMR_NRFS_Pos = 0x5      // Position of NRFS field.
	FMC_SDCMR_NRFS_Msk = 0x1e0    // Bit mask of NRFS field.
	FMC_SDCMR_MRD_Pos  = 0x9      // Position of MRD field.
	FMC_SDCMR_MRD_Msk  = 0x7ffe00 // Bit mask of MRD field.

	// SDRTR: This register sets the refresh rate in           number of SDCLK clock cycles between the refresh cycles           by configuring the Refresh Timer Count value.Examplewhere           64 ms is the SDRAM refresh period.The refresh rate must           be increased by 20 SDRAM clock cycles (as in the above           example) to obtain a safe margin if an internal refresh           request occurs when a read request has been accepted. It           corresponds to a COUNT value of 0000111000000 (448). This           13-bit field is loaded into a timer which is decremented           using the SDRAM clock. This timer generates a refresh           pulse when zero is reached. The COUNT value must be set           at least to 41 SDRAM clock cycles.As soon as the           FMC_SDRTR register is programmed, the timer starts           counting. If the value programmed in the register is 0,           no refresh is carried out. This register must not be           reprogrammed after the initialization procedure to avoid           modifying the refresh rate.Each time a refresh pulse is           generated, this 13-bit COUNT field is reloaded into the           counter.If a memory access is in progress, the           Auto-refresh request is delayed. However, if the memory           access and Auto-refresh requests are generated           simultaneously, the Auto-refresh takes precedence. If the           memory access occurs during a refresh operation, the           request is buffered to be processed when the refresh is           complete.This register is common to SDRAM bank 1 and bank           2.
	FMC_SDRTR_CRE_Pos   = 0x0    // Position of CRE field.
	FMC_SDRTR_CRE_Msk   = 0x1    // Bit mask of CRE field.
	FMC_SDRTR_CRE       = 0x1    // Bit CRE.
	FMC_SDRTR_COUNT_Pos = 0x1    // Position of COUNT field.
	FMC_SDRTR_COUNT_Msk = 0x3ffe // Bit mask of COUNT field.
	FMC_SDRTR_REIE_Pos  = 0xe    // Position of REIE field.
	FMC_SDRTR_REIE_Msk  = 0x4000 // Bit mask of REIE field.
	FMC_SDRTR_REIE      = 0x4000 // Bit REIE.

	// SDSR: SDRAM Status register
	FMC_SDSR_RE_Pos     = 0x0  // Position of RE field.
	FMC_SDSR_RE_Msk     = 0x1  // Bit mask of RE field.
	FMC_SDSR_RE         = 0x1  // Bit RE.
	FMC_SDSR_MODES1_Pos = 0x1  // Position of MODES1 field.
	FMC_SDSR_MODES1_Msk = 0x6  // Bit mask of MODES1 field.
	FMC_SDSR_MODES2_Pos = 0x3  // Position of MODES2 field.
	FMC_SDSR_MODES2_Msk = 0x18 // Bit mask of MODES2 field.
)

// Bitfields for CEC: CEC
const (
	// CR: CEC control register
	CEC_CR_CECEN_Pos = 0x0 // Position of CECEN field.
	CEC_CR_CECEN_Msk = 0x1 // Bit mask of CECEN field.
	CEC_CR_CECEN     = 0x1 // Bit CECEN.
	CEC_CR_TXSOM_Pos = 0x1 // Position of TXSOM field.
	CEC_CR_TXSOM_Msk = 0x2 // Bit mask of TXSOM field.
	CEC_CR_TXSOM     = 0x2 // Bit TXSOM.
	CEC_CR_TXEOM_Pos = 0x2 // Position of TXEOM field.
	CEC_CR_TXEOM_Msk = 0x4 // Bit mask of TXEOM field.
	CEC_CR_TXEOM     = 0x4 // Bit TXEOM.

	// CFGR: This register is used to configure the           HDMI-CEC controller. It is mandatory to write CEC_CFGR           only when CECEN=0.
	CEC_CFGR_SFT_Pos      = 0x0        // Position of SFT field.
	CEC_CFGR_SFT_Msk      = 0x7        // Bit mask of SFT field.
	CEC_CFGR_RXTOL_Pos    = 0x3        // Position of RXTOL field.
	CEC_CFGR_RXTOL_Msk    = 0x8        // Bit mask of RXTOL field.
	CEC_CFGR_RXTOL        = 0x8        // Bit RXTOL.
	CEC_CFGR_BRESTP_Pos   = 0x4        // Position of BRESTP field.
	CEC_CFGR_BRESTP_Msk   = 0x10       // Bit mask of BRESTP field.
	CEC_CFGR_BRESTP       = 0x10       // Bit BRESTP.
	CEC_CFGR_BREGEN_Pos   = 0x5        // Position of BREGEN field.
	CEC_CFGR_BREGEN_Msk   = 0x20       // Bit mask of BREGEN field.
	CEC_CFGR_BREGEN       = 0x20       // Bit BREGEN.
	CEC_CFGR_LBPEGEN_Pos  = 0x6        // Position of LBPEGEN field.
	CEC_CFGR_LBPEGEN_Msk  = 0x40       // Bit mask of LBPEGEN field.
	CEC_CFGR_LBPEGEN      = 0x40       // Bit LBPEGEN.
	CEC_CFGR_BRDNOGEN_Pos = 0x7        // Position of BRDNOGEN field.
	CEC_CFGR_BRDNOGEN_Msk = 0x80       // Bit mask of BRDNOGEN field.
	CEC_CFGR_BRDNOGEN     = 0x80       // Bit BRDNOGEN.
	CEC_CFGR_SFTOPT_Pos   = 0x8        // Position of SFTOPT field.
	CEC_CFGR_SFTOPT_Msk   = 0x100      // Bit mask of SFTOPT field.
	CEC_CFGR_SFTOPT       = 0x100      // Bit SFTOPT.
	CEC_CFGR_OAR_Pos      = 0x10       // Position of OAR field.
	CEC_CFGR_OAR_Msk      = 0x7fff0000 // Bit mask of OAR field.
	CEC_CFGR_LSTN_Pos     = 0x1f       // Position of LSTN field.
	CEC_CFGR_LSTN_Msk     = 0x80000000 // Bit mask of LSTN field.
	CEC_CFGR_LSTN         = 0x80000000 // Bit LSTN.

	// TXDR: CEC Tx data register
	CEC_TXDR_TXD_Pos = 0x0  // Position of TXD field.
	CEC_TXDR_TXD_Msk = 0xff // Bit mask of TXD field.

	// RXDR: CEC Rx Data Register
	CEC_RXDR_RXD_Pos = 0x0  // Position of RXD field.
	CEC_RXDR_RXD_Msk = 0xff // Bit mask of RXD field.

	// ISR: CEC Interrupt and Status           Register
	CEC_ISR_RXBR_Pos   = 0x0    // Position of RXBR field.
	CEC_ISR_RXBR_Msk   = 0x1    // Bit mask of RXBR field.
	CEC_ISR_RXBR       = 0x1    // Bit RXBR.
	CEC_ISR_RXEND_Pos  = 0x1    // Position of RXEND field.
	CEC_ISR_RXEND_Msk  = 0x2    // Bit mask of RXEND field.
	CEC_ISR_RXEND      = 0x2    // Bit RXEND.
	CEC_ISR_RXOVR_Pos  = 0x2    // Position of RXOVR field.
	CEC_ISR_RXOVR_Msk  = 0x4    // Bit mask of RXOVR field.
	CEC_ISR_RXOVR      = 0x4    // Bit RXOVR.
	CEC_ISR_BRE_Pos    = 0x3    // Position of BRE field.
	CEC_ISR_BRE_Msk    = 0x8    // Bit mask of BRE field.
	CEC_ISR_BRE        = 0x8    // Bit BRE.
	CEC_ISR_SBPE_Pos   = 0x4    // Position of SBPE field.
	CEC_ISR_SBPE_Msk   = 0x10   // Bit mask of SBPE field.
	CEC_ISR_SBPE       = 0x10   // Bit SBPE.
	CEC_ISR_LBPE_Pos   = 0x5    // Position of LBPE field.
	CEC_ISR_LBPE_Msk   = 0x20   // Bit mask of LBPE field.
	CEC_ISR_LBPE       = 0x20   // Bit LBPE.
	CEC_ISR_RXACKE_Pos = 0x6    // Position of RXACKE field.
	CEC_ISR_RXACKE_Msk = 0x40   // Bit mask of RXACKE field.
	CEC_ISR_RXACKE     = 0x40   // Bit RXACKE.
	CEC_ISR_ARBLST_Pos = 0x7    // Position of ARBLST field.
	CEC_ISR_ARBLST_Msk = 0x80   // Bit mask of ARBLST field.
	CEC_ISR_ARBLST     = 0x80   // Bit ARBLST.
	CEC_ISR_TXBR_Pos   = 0x8    // Position of TXBR field.
	CEC_ISR_TXBR_Msk   = 0x100  // Bit mask of TXBR field.
	CEC_ISR_TXBR       = 0x100  // Bit TXBR.
	CEC_ISR_TXEND_Pos  = 0x9    // Position of TXEND field.
	CEC_ISR_TXEND_Msk  = 0x200  // Bit mask of TXEND field.
	CEC_ISR_TXEND      = 0x200  // Bit TXEND.
	CEC_ISR_TXUDR_Pos  = 0xa    // Position of TXUDR field.
	CEC_ISR_TXUDR_Msk  = 0x400  // Bit mask of TXUDR field.
	CEC_ISR_TXUDR      = 0x400  // Bit TXUDR.
	CEC_ISR_TXERR_Pos  = 0xb    // Position of TXERR field.
	CEC_ISR_TXERR_Msk  = 0x800  // Bit mask of TXERR field.
	CEC_ISR_TXERR      = 0x800  // Bit TXERR.
	CEC_ISR_TXACKE_Pos = 0xc    // Position of TXACKE field.
	CEC_ISR_TXACKE_Msk = 0x1000 // Bit mask of TXACKE field.
	CEC_ISR_TXACKE     = 0x1000 // Bit TXACKE.

	// IER: CEC interrupt enable register
	CEC_IER_RXBRIE_Pos   = 0x0    // Position of RXBRIE field.
	CEC_IER_RXBRIE_Msk   = 0x1    // Bit mask of RXBRIE field.
	CEC_IER_RXBRIE       = 0x1    // Bit RXBRIE.
	CEC_IER_RXENDIE_Pos  = 0x1    // Position of RXENDIE field.
	CEC_IER_RXENDIE_Msk  = 0x2    // Bit mask of RXENDIE field.
	CEC_IER_RXENDIE      = 0x2    // Bit RXENDIE.
	CEC_IER_RXOVRIE_Pos  = 0x2    // Position of RXOVRIE field.
	CEC_IER_RXOVRIE_Msk  = 0x4    // Bit mask of RXOVRIE field.
	CEC_IER_RXOVRIE      = 0x4    // Bit RXOVRIE.
	CEC_IER_BREIE_Pos    = 0x3    // Position of BREIE field.
	CEC_IER_BREIE_Msk    = 0x8    // Bit mask of BREIE field.
	CEC_IER_BREIE        = 0x8    // Bit BREIE.
	CEC_IER_SBPEIE_Pos   = 0x4    // Position of SBPEIE field.
	CEC_IER_SBPEIE_Msk   = 0x10   // Bit mask of SBPEIE field.
	CEC_IER_SBPEIE       = 0x10   // Bit SBPEIE.
	CEC_IER_LBPEIE_Pos   = 0x5    // Position of LBPEIE field.
	CEC_IER_LBPEIE_Msk   = 0x20   // Bit mask of LBPEIE field.
	CEC_IER_LBPEIE       = 0x20   // Bit LBPEIE.
	CEC_IER_RXACKIE_Pos  = 0x6    // Position of RXACKIE field.
	CEC_IER_RXACKIE_Msk  = 0x40   // Bit mask of RXACKIE field.
	CEC_IER_RXACKIE      = 0x40   // Bit RXACKIE.
	CEC_IER_ARBLSTIE_Pos = 0x7    // Position of ARBLSTIE field.
	CEC_IER_ARBLSTIE_Msk = 0x80   // Bit mask of ARBLSTIE field.
	CEC_IER_ARBLSTIE     = 0x80   // Bit ARBLSTIE.
	CEC_IER_TXBRIE_Pos   = 0x8    // Position of TXBRIE field.
	CEC_IER_TXBRIE_Msk   = 0x100  // Bit mask of TXBRIE field.
	CEC_IER_TXBRIE       = 0x100  // Bit TXBRIE.
	CEC_IER_TXENDIE_Pos  = 0x9    // Position of TXENDIE field.
	CEC_IER_TXENDIE_Msk  = 0x200  // Bit mask of TXENDIE field.
	CEC_IER_TXENDIE      = 0x200  // Bit TXENDIE.
	CEC_IER_TXUDRIE_Pos  = 0xa    // Position of TXUDRIE field.
	CEC_IER_TXUDRIE_Msk  = 0x400  // Bit mask of TXUDRIE field.
	CEC_IER_TXUDRIE      = 0x400  // Bit TXUDRIE.
	CEC_IER_TXERRIE_Pos  = 0xb    // Position of TXERRIE field.
	CEC_IER_TXERRIE_Msk  = 0x800  // Bit mask of TXERRIE field.
	CEC_IER_TXERRIE      = 0x800  // Bit TXERRIE.
	CEC_IER_TXACKIE_Pos  = 0xc    // Position of TXACKIE field.
	CEC_IER_TXACKIE_Msk  = 0x1000 // Bit mask of TXACKIE field.
	CEC_IER_TXACKIE      = 0x1000 // Bit TXACKIE.
)

// Bitfields for HSEM: HSEM
const (
	// HSEM_R0: HSEM register HSEM_R0 HSEM_R31
	HSEM_HSEM_R0_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_R0_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_R0_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_R0_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_R0_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_R0_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_R0_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_R1: HSEM register HSEM_R0 HSEM_R31
	HSEM_HSEM_R1_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_R1_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_R1_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_R1_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_R1_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_R1_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_R1_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_R2: HSEM register HSEM_R0 HSEM_R31
	HSEM_HSEM_R2_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_R2_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_R2_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_R2_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_R2_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_R2_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_R2_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_R3: HSEM register HSEM_R0 HSEM_R31
	HSEM_HSEM_R3_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_R3_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_R3_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_R3_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_R3_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_R3_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_R3_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_R4: HSEM register HSEM_R0 HSEM_R31
	HSEM_HSEM_R4_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_R4_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_R4_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_R4_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_R4_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_R4_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_R4_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_R5: HSEM register HSEM_R0 HSEM_R31
	HSEM_HSEM_R5_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_R5_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_R5_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_R5_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_R5_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_R5_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_R5_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_R6: HSEM register HSEM_R0 HSEM_R31
	HSEM_HSEM_R6_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_R6_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_R6_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_R6_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_R6_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_R6_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_R6_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_R7: HSEM register HSEM_R0 HSEM_R31
	HSEM_HSEM_R7_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_R7_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_R7_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_R7_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_R7_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_R7_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_R7_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_R8: HSEM register HSEM_R0 HSEM_R31
	HSEM_HSEM_R8_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_R8_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_R8_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_R8_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_R8_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_R8_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_R8_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_R9: HSEM register HSEM_R0 HSEM_R31
	HSEM_HSEM_R9_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_R9_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_R9_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_R9_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_R9_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_R9_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_R9_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_R10: HSEM register HSEM_R0 HSEM_R31
	HSEM_HSEM_R10_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_R10_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_R10_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_R10_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_R10_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_R10_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_R10_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_R11: HSEM register HSEM_R0 HSEM_R31
	HSEM_HSEM_R11_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_R11_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_R11_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_R11_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_R11_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_R11_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_R11_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_R12: HSEM register HSEM_R0 HSEM_R31
	HSEM_HSEM_R12_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_R12_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_R12_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_R12_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_R12_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_R12_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_R12_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_R13: HSEM register HSEM_R0 HSEM_R31
	HSEM_HSEM_R13_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_R13_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_R13_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_R13_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_R13_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_R13_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_R13_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_R14: HSEM register HSEM_R0 HSEM_R31
	HSEM_HSEM_R14_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_R14_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_R14_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_R14_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_R14_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_R14_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_R14_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_R15: HSEM register HSEM_R0 HSEM_R31
	HSEM_HSEM_R15_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_R15_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_R15_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_R15_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_R15_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_R15_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_R15_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_R16: HSEM register HSEM_R0 HSEM_R31
	HSEM_HSEM_R16_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_R16_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_R16_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_R16_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_R16_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_R16_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_R16_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_R17: HSEM register HSEM_R0 HSEM_R31
	HSEM_HSEM_R17_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_R17_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_R17_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_R17_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_R17_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_R17_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_R17_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_R18: HSEM register HSEM_R0 HSEM_R31
	HSEM_HSEM_R18_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_R18_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_R18_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_R18_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_R18_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_R18_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_R18_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_R19: HSEM register HSEM_R0 HSEM_R31
	HSEM_HSEM_R19_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_R19_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_R19_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_R19_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_R19_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_R19_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_R19_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_R20: HSEM register HSEM_R0 HSEM_R31
	HSEM_HSEM_R20_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_R20_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_R20_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_R20_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_R20_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_R20_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_R20_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_R21: HSEM register HSEM_R0 HSEM_R31
	HSEM_HSEM_R21_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_R21_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_R21_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_R21_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_R21_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_R21_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_R21_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_R22: HSEM register HSEM_R0 HSEM_R31
	HSEM_HSEM_R22_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_R22_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_R22_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_R22_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_R22_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_R22_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_R22_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_R23: HSEM register HSEM_R0 HSEM_R31
	HSEM_HSEM_R23_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_R23_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_R23_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_R23_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_R23_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_R23_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_R23_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_R24: HSEM register HSEM_R0 HSEM_R31
	HSEM_HSEM_R24_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_R24_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_R24_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_R24_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_R24_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_R24_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_R24_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_R25: HSEM register HSEM_R0 HSEM_R31
	HSEM_HSEM_R25_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_R25_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_R25_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_R25_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_R25_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_R25_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_R25_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_R26: HSEM register HSEM_R0 HSEM_R31
	HSEM_HSEM_R26_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_R26_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_R26_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_R26_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_R26_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_R26_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_R26_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_R27: HSEM register HSEM_R0 HSEM_R31
	HSEM_HSEM_R27_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_R27_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_R27_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_R27_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_R27_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_R27_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_R27_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_R28: HSEM register HSEM_R0 HSEM_R31
	HSEM_HSEM_R28_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_R28_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_R28_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_R28_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_R28_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_R28_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_R28_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_R29: HSEM register HSEM_R0 HSEM_R31
	HSEM_HSEM_R29_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_R29_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_R29_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_R29_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_R29_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_R29_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_R29_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_R30: HSEM register HSEM_R0 HSEM_R31
	HSEM_HSEM_R30_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_R30_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_R30_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_R30_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_R30_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_R30_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_R30_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_R31: HSEM register HSEM_R0 HSEM_R31
	HSEM_HSEM_R31_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_R31_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_R31_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_R31_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_R31_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_R31_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_R31_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_RLR0: HSEM Read lock register
	HSEM_HSEM_RLR0_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_RLR0_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_RLR0_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_RLR0_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_RLR0_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_RLR0_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_RLR0_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_RLR1: HSEM Read lock register
	HSEM_HSEM_RLR1_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_RLR1_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_RLR1_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_RLR1_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_RLR1_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_RLR1_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_RLR1_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_RLR2: HSEM Read lock register
	HSEM_HSEM_RLR2_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_RLR2_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_RLR2_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_RLR2_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_RLR2_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_RLR2_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_RLR2_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_RLR3: HSEM Read lock register
	HSEM_HSEM_RLR3_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_RLR3_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_RLR3_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_RLR3_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_RLR3_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_RLR3_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_RLR3_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_RLR4: HSEM Read lock register
	HSEM_HSEM_RLR4_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_RLR4_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_RLR4_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_RLR4_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_RLR4_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_RLR4_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_RLR4_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_RLR5: HSEM Read lock register
	HSEM_HSEM_RLR5_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_RLR5_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_RLR5_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_RLR5_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_RLR5_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_RLR5_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_RLR5_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_RLR6: HSEM Read lock register
	HSEM_HSEM_RLR6_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_RLR6_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_RLR6_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_RLR6_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_RLR6_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_RLR6_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_RLR6_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_RLR7: HSEM Read lock register
	HSEM_HSEM_RLR7_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_RLR7_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_RLR7_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_RLR7_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_RLR7_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_RLR7_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_RLR7_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_RLR8: HSEM Read lock register
	HSEM_HSEM_RLR8_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_RLR8_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_RLR8_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_RLR8_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_RLR8_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_RLR8_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_RLR8_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_RLR9: HSEM Read lock register
	HSEM_HSEM_RLR9_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_RLR9_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_RLR9_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_RLR9_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_RLR9_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_RLR9_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_RLR9_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_RLR10: HSEM Read lock register
	HSEM_HSEM_RLR10_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_RLR10_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_RLR10_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_RLR10_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_RLR10_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_RLR10_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_RLR10_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_RLR11: HSEM Read lock register
	HSEM_HSEM_RLR11_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_RLR11_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_RLR11_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_RLR11_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_RLR11_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_RLR11_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_RLR11_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_RLR12: HSEM Read lock register
	HSEM_HSEM_RLR12_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_RLR12_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_RLR12_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_RLR12_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_RLR12_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_RLR12_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_RLR12_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_RLR13: HSEM Read lock register
	HSEM_HSEM_RLR13_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_RLR13_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_RLR13_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_RLR13_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_RLR13_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_RLR13_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_RLR13_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_RLR14: HSEM Read lock register
	HSEM_HSEM_RLR14_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_RLR14_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_RLR14_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_RLR14_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_RLR14_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_RLR14_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_RLR14_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_RLR15: HSEM Read lock register
	HSEM_HSEM_RLR15_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_RLR15_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_RLR15_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_RLR15_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_RLR15_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_RLR15_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_RLR15_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_RLR16: HSEM Read lock register
	HSEM_HSEM_RLR16_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_RLR16_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_RLR16_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_RLR16_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_RLR16_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_RLR16_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_RLR16_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_RLR17: HSEM Read lock register
	HSEM_HSEM_RLR17_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_RLR17_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_RLR17_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_RLR17_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_RLR17_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_RLR17_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_RLR17_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_RLR18: HSEM Read lock register
	HSEM_HSEM_RLR18_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_RLR18_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_RLR18_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_RLR18_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_RLR18_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_RLR18_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_RLR18_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_RLR19: HSEM Read lock register
	HSEM_HSEM_RLR19_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_RLR19_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_RLR19_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_RLR19_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_RLR19_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_RLR19_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_RLR19_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_RLR20: HSEM Read lock register
	HSEM_HSEM_RLR20_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_RLR20_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_RLR20_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_RLR20_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_RLR20_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_RLR20_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_RLR20_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_RLR21: HSEM Read lock register
	HSEM_HSEM_RLR21_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_RLR21_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_RLR21_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_RLR21_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_RLR21_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_RLR21_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_RLR21_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_RLR22: HSEM Read lock register
	HSEM_HSEM_RLR22_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_RLR22_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_RLR22_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_RLR22_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_RLR22_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_RLR22_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_RLR22_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_RLR23: HSEM Read lock register
	HSEM_HSEM_RLR23_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_RLR23_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_RLR23_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_RLR23_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_RLR23_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_RLR23_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_RLR23_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_RLR24: HSEM Read lock register
	HSEM_HSEM_RLR24_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_RLR24_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_RLR24_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_RLR24_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_RLR24_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_RLR24_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_RLR24_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_RLR25: HSEM Read lock register
	HSEM_HSEM_RLR25_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_RLR25_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_RLR25_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_RLR25_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_RLR25_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_RLR25_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_RLR25_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_RLR26: HSEM Read lock register
	HSEM_HSEM_RLR26_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_RLR26_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_RLR26_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_RLR26_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_RLR26_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_RLR26_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_RLR26_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_RLR27: HSEM Read lock register
	HSEM_HSEM_RLR27_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_RLR27_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_RLR27_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_RLR27_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_RLR27_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_RLR27_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_RLR27_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_RLR28: HSEM Read lock register
	HSEM_HSEM_RLR28_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_RLR28_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_RLR28_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_RLR28_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_RLR28_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_RLR28_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_RLR28_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_RLR29: HSEM Read lock register
	HSEM_HSEM_RLR29_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_RLR29_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_RLR29_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_RLR29_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_RLR29_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_RLR29_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_RLR29_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_RLR30: HSEM Read lock register
	HSEM_HSEM_RLR30_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_RLR30_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_RLR30_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_RLR30_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_RLR30_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_RLR30_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_RLR30_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_RLR31: HSEM Read lock register
	HSEM_HSEM_RLR31_PROCID_Pos   = 0x0        // Position of PROCID field.
	HSEM_HSEM_RLR31_PROCID_Msk   = 0xff       // Bit mask of PROCID field.
	HSEM_HSEM_RLR31_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_RLR31_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_RLR31_LOCK_Pos     = 0x1f       // Position of LOCK field.
	HSEM_HSEM_RLR31_LOCK_Msk     = 0x80000000 // Bit mask of LOCK field.
	HSEM_HSEM_RLR31_LOCK         = 0x80000000 // Bit LOCK.

	// HSEM_IER: HSEM Interrupt enable register
	HSEM_HSEM_IER_ISEM0_Pos  = 0x0        // Position of ISEM0 field.
	HSEM_HSEM_IER_ISEM0_Msk  = 0x1        // Bit mask of ISEM0 field.
	HSEM_HSEM_IER_ISEM0      = 0x1        // Bit ISEM0.
	HSEM_HSEM_IER_ISEM1_Pos  = 0x1        // Position of ISEM1 field.
	HSEM_HSEM_IER_ISEM1_Msk  = 0x2        // Bit mask of ISEM1 field.
	HSEM_HSEM_IER_ISEM1      = 0x2        // Bit ISEM1.
	HSEM_HSEM_IER_ISEM2_Pos  = 0x2        // Position of ISEM2 field.
	HSEM_HSEM_IER_ISEM2_Msk  = 0x4        // Bit mask of ISEM2 field.
	HSEM_HSEM_IER_ISEM2      = 0x4        // Bit ISEM2.
	HSEM_HSEM_IER_ISEM3_Pos  = 0x3        // Position of ISEM3 field.
	HSEM_HSEM_IER_ISEM3_Msk  = 0x8        // Bit mask of ISEM3 field.
	HSEM_HSEM_IER_ISEM3      = 0x8        // Bit ISEM3.
	HSEM_HSEM_IER_ISEM4_Pos  = 0x4        // Position of ISEM4 field.
	HSEM_HSEM_IER_ISEM4_Msk  = 0x10       // Bit mask of ISEM4 field.
	HSEM_HSEM_IER_ISEM4      = 0x10       // Bit ISEM4.
	HSEM_HSEM_IER_ISEM5_Pos  = 0x5        // Position of ISEM5 field.
	HSEM_HSEM_IER_ISEM5_Msk  = 0x20       // Bit mask of ISEM5 field.
	HSEM_HSEM_IER_ISEM5      = 0x20       // Bit ISEM5.
	HSEM_HSEM_IER_ISEM6_Pos  = 0x6        // Position of ISEM6 field.
	HSEM_HSEM_IER_ISEM6_Msk  = 0x40       // Bit mask of ISEM6 field.
	HSEM_HSEM_IER_ISEM6      = 0x40       // Bit ISEM6.
	HSEM_HSEM_IER_ISEM7_Pos  = 0x7        // Position of ISEM7 field.
	HSEM_HSEM_IER_ISEM7_Msk  = 0x80       // Bit mask of ISEM7 field.
	HSEM_HSEM_IER_ISEM7      = 0x80       // Bit ISEM7.
	HSEM_HSEM_IER_ISEM8_Pos  = 0x8        // Position of ISEM8 field.
	HSEM_HSEM_IER_ISEM8_Msk  = 0x100      // Bit mask of ISEM8 field.
	HSEM_HSEM_IER_ISEM8      = 0x100      // Bit ISEM8.
	HSEM_HSEM_IER_ISEM9_Pos  = 0x9        // Position of ISEM9 field.
	HSEM_HSEM_IER_ISEM9_Msk  = 0x200      // Bit mask of ISEM9 field.
	HSEM_HSEM_IER_ISEM9      = 0x200      // Bit ISEM9.
	HSEM_HSEM_IER_ISEM10_Pos = 0xa        // Position of ISEM10 field.
	HSEM_HSEM_IER_ISEM10_Msk = 0x400      // Bit mask of ISEM10 field.
	HSEM_HSEM_IER_ISEM10     = 0x400      // Bit ISEM10.
	HSEM_HSEM_IER_ISEM11_Pos = 0xb        // Position of ISEM11 field.
	HSEM_HSEM_IER_ISEM11_Msk = 0x800      // Bit mask of ISEM11 field.
	HSEM_HSEM_IER_ISEM11     = 0x800      // Bit ISEM11.
	HSEM_HSEM_IER_ISEM12_Pos = 0xc        // Position of ISEM12 field.
	HSEM_HSEM_IER_ISEM12_Msk = 0x1000     // Bit mask of ISEM12 field.
	HSEM_HSEM_IER_ISEM12     = 0x1000     // Bit ISEM12.
	HSEM_HSEM_IER_ISEM13_Pos = 0xd        // Position of ISEM13 field.
	HSEM_HSEM_IER_ISEM13_Msk = 0x2000     // Bit mask of ISEM13 field.
	HSEM_HSEM_IER_ISEM13     = 0x2000     // Bit ISEM13.
	HSEM_HSEM_IER_ISEM14_Pos = 0xe        // Position of ISEM14 field.
	HSEM_HSEM_IER_ISEM14_Msk = 0x4000     // Bit mask of ISEM14 field.
	HSEM_HSEM_IER_ISEM14     = 0x4000     // Bit ISEM14.
	HSEM_HSEM_IER_ISEM15_Pos = 0xf        // Position of ISEM15 field.
	HSEM_HSEM_IER_ISEM15_Msk = 0x8000     // Bit mask of ISEM15 field.
	HSEM_HSEM_IER_ISEM15     = 0x8000     // Bit ISEM15.
	HSEM_HSEM_IER_ISEM16_Pos = 0x10       // Position of ISEM16 field.
	HSEM_HSEM_IER_ISEM16_Msk = 0x10000    // Bit mask of ISEM16 field.
	HSEM_HSEM_IER_ISEM16     = 0x10000    // Bit ISEM16.
	HSEM_HSEM_IER_ISEM17_Pos = 0x11       // Position of ISEM17 field.
	HSEM_HSEM_IER_ISEM17_Msk = 0x20000    // Bit mask of ISEM17 field.
	HSEM_HSEM_IER_ISEM17     = 0x20000    // Bit ISEM17.
	HSEM_HSEM_IER_ISEM18_Pos = 0x12       // Position of ISEM18 field.
	HSEM_HSEM_IER_ISEM18_Msk = 0x40000    // Bit mask of ISEM18 field.
	HSEM_HSEM_IER_ISEM18     = 0x40000    // Bit ISEM18.
	HSEM_HSEM_IER_ISEM19_Pos = 0x13       // Position of ISEM19 field.
	HSEM_HSEM_IER_ISEM19_Msk = 0x80000    // Bit mask of ISEM19 field.
	HSEM_HSEM_IER_ISEM19     = 0x80000    // Bit ISEM19.
	HSEM_HSEM_IER_ISEM20_Pos = 0x14       // Position of ISEM20 field.
	HSEM_HSEM_IER_ISEM20_Msk = 0x100000   // Bit mask of ISEM20 field.
	HSEM_HSEM_IER_ISEM20     = 0x100000   // Bit ISEM20.
	HSEM_HSEM_IER_ISEM21_Pos = 0x15       // Position of ISEM21 field.
	HSEM_HSEM_IER_ISEM21_Msk = 0x200000   // Bit mask of ISEM21 field.
	HSEM_HSEM_IER_ISEM21     = 0x200000   // Bit ISEM21.
	HSEM_HSEM_IER_ISEM22_Pos = 0x16       // Position of ISEM22 field.
	HSEM_HSEM_IER_ISEM22_Msk = 0x400000   // Bit mask of ISEM22 field.
	HSEM_HSEM_IER_ISEM22     = 0x400000   // Bit ISEM22.
	HSEM_HSEM_IER_ISEM23_Pos = 0x17       // Position of ISEM23 field.
	HSEM_HSEM_IER_ISEM23_Msk = 0x800000   // Bit mask of ISEM23 field.
	HSEM_HSEM_IER_ISEM23     = 0x800000   // Bit ISEM23.
	HSEM_HSEM_IER_ISEM24_Pos = 0x18       // Position of ISEM24 field.
	HSEM_HSEM_IER_ISEM24_Msk = 0x1000000  // Bit mask of ISEM24 field.
	HSEM_HSEM_IER_ISEM24     = 0x1000000  // Bit ISEM24.
	HSEM_HSEM_IER_ISEM25_Pos = 0x19       // Position of ISEM25 field.
	HSEM_HSEM_IER_ISEM25_Msk = 0x2000000  // Bit mask of ISEM25 field.
	HSEM_HSEM_IER_ISEM25     = 0x2000000  // Bit ISEM25.
	HSEM_HSEM_IER_ISEM26_Pos = 0x1a       // Position of ISEM26 field.
	HSEM_HSEM_IER_ISEM26_Msk = 0x4000000  // Bit mask of ISEM26 field.
	HSEM_HSEM_IER_ISEM26     = 0x4000000  // Bit ISEM26.
	HSEM_HSEM_IER_ISEM27_Pos = 0x1b       // Position of ISEM27 field.
	HSEM_HSEM_IER_ISEM27_Msk = 0x8000000  // Bit mask of ISEM27 field.
	HSEM_HSEM_IER_ISEM27     = 0x8000000  // Bit ISEM27.
	HSEM_HSEM_IER_ISEM28_Pos = 0x1c       // Position of ISEM28 field.
	HSEM_HSEM_IER_ISEM28_Msk = 0x10000000 // Bit mask of ISEM28 field.
	HSEM_HSEM_IER_ISEM28     = 0x10000000 // Bit ISEM28.
	HSEM_HSEM_IER_ISEM29_Pos = 0x1d       // Position of ISEM29 field.
	HSEM_HSEM_IER_ISEM29_Msk = 0x20000000 // Bit mask of ISEM29 field.
	HSEM_HSEM_IER_ISEM29     = 0x20000000 // Bit ISEM29.
	HSEM_HSEM_IER_ISEM30_Pos = 0x1e       // Position of ISEM30 field.
	HSEM_HSEM_IER_ISEM30_Msk = 0x40000000 // Bit mask of ISEM30 field.
	HSEM_HSEM_IER_ISEM30     = 0x40000000 // Bit ISEM30.
	HSEM_HSEM_IER_ISEM31_Pos = 0x1f       // Position of ISEM31 field.
	HSEM_HSEM_IER_ISEM31_Msk = 0x80000000 // Bit mask of ISEM31 field.
	HSEM_HSEM_IER_ISEM31     = 0x80000000 // Bit ISEM31.

	// HSEM_ICR: HSEM Interrupt clear register
	HSEM_HSEM_ICR_ISEM0_Pos  = 0x0        // Position of ISEM0 field.
	HSEM_HSEM_ICR_ISEM0_Msk  = 0x1        // Bit mask of ISEM0 field.
	HSEM_HSEM_ICR_ISEM0      = 0x1        // Bit ISEM0.
	HSEM_HSEM_ICR_ISEM1_Pos  = 0x1        // Position of ISEM1 field.
	HSEM_HSEM_ICR_ISEM1_Msk  = 0x2        // Bit mask of ISEM1 field.
	HSEM_HSEM_ICR_ISEM1      = 0x2        // Bit ISEM1.
	HSEM_HSEM_ICR_ISEM2_Pos  = 0x2        // Position of ISEM2 field.
	HSEM_HSEM_ICR_ISEM2_Msk  = 0x4        // Bit mask of ISEM2 field.
	HSEM_HSEM_ICR_ISEM2      = 0x4        // Bit ISEM2.
	HSEM_HSEM_ICR_ISEM3_Pos  = 0x3        // Position of ISEM3 field.
	HSEM_HSEM_ICR_ISEM3_Msk  = 0x8        // Bit mask of ISEM3 field.
	HSEM_HSEM_ICR_ISEM3      = 0x8        // Bit ISEM3.
	HSEM_HSEM_ICR_ISEM4_Pos  = 0x4        // Position of ISEM4 field.
	HSEM_HSEM_ICR_ISEM4_Msk  = 0x10       // Bit mask of ISEM4 field.
	HSEM_HSEM_ICR_ISEM4      = 0x10       // Bit ISEM4.
	HSEM_HSEM_ICR_ISEM5_Pos  = 0x5        // Position of ISEM5 field.
	HSEM_HSEM_ICR_ISEM5_Msk  = 0x20       // Bit mask of ISEM5 field.
	HSEM_HSEM_ICR_ISEM5      = 0x20       // Bit ISEM5.
	HSEM_HSEM_ICR_ISEM6_Pos  = 0x6        // Position of ISEM6 field.
	HSEM_HSEM_ICR_ISEM6_Msk  = 0x40       // Bit mask of ISEM6 field.
	HSEM_HSEM_ICR_ISEM6      = 0x40       // Bit ISEM6.
	HSEM_HSEM_ICR_ISEM7_Pos  = 0x7        // Position of ISEM7 field.
	HSEM_HSEM_ICR_ISEM7_Msk  = 0x80       // Bit mask of ISEM7 field.
	HSEM_HSEM_ICR_ISEM7      = 0x80       // Bit ISEM7.
	HSEM_HSEM_ICR_ISEM8_Pos  = 0x8        // Position of ISEM8 field.
	HSEM_HSEM_ICR_ISEM8_Msk  = 0x100      // Bit mask of ISEM8 field.
	HSEM_HSEM_ICR_ISEM8      = 0x100      // Bit ISEM8.
	HSEM_HSEM_ICR_ISEM9_Pos  = 0x9        // Position of ISEM9 field.
	HSEM_HSEM_ICR_ISEM9_Msk  = 0x200      // Bit mask of ISEM9 field.
	HSEM_HSEM_ICR_ISEM9      = 0x200      // Bit ISEM9.
	HSEM_HSEM_ICR_ISEM10_Pos = 0xa        // Position of ISEM10 field.
	HSEM_HSEM_ICR_ISEM10_Msk = 0x400      // Bit mask of ISEM10 field.
	HSEM_HSEM_ICR_ISEM10     = 0x400      // Bit ISEM10.
	HSEM_HSEM_ICR_ISEM11_Pos = 0xb        // Position of ISEM11 field.
	HSEM_HSEM_ICR_ISEM11_Msk = 0x800      // Bit mask of ISEM11 field.
	HSEM_HSEM_ICR_ISEM11     = 0x800      // Bit ISEM11.
	HSEM_HSEM_ICR_ISEM12_Pos = 0xc        // Position of ISEM12 field.
	HSEM_HSEM_ICR_ISEM12_Msk = 0x1000     // Bit mask of ISEM12 field.
	HSEM_HSEM_ICR_ISEM12     = 0x1000     // Bit ISEM12.
	HSEM_HSEM_ICR_ISEM13_Pos = 0xd        // Position of ISEM13 field.
	HSEM_HSEM_ICR_ISEM13_Msk = 0x2000     // Bit mask of ISEM13 field.
	HSEM_HSEM_ICR_ISEM13     = 0x2000     // Bit ISEM13.
	HSEM_HSEM_ICR_ISEM14_Pos = 0xe        // Position of ISEM14 field.
	HSEM_HSEM_ICR_ISEM14_Msk = 0x4000     // Bit mask of ISEM14 field.
	HSEM_HSEM_ICR_ISEM14     = 0x4000     // Bit ISEM14.
	HSEM_HSEM_ICR_ISEM15_Pos = 0xf        // Position of ISEM15 field.
	HSEM_HSEM_ICR_ISEM15_Msk = 0x8000     // Bit mask of ISEM15 field.
	HSEM_HSEM_ICR_ISEM15     = 0x8000     // Bit ISEM15.
	HSEM_HSEM_ICR_ISEM16_Pos = 0x10       // Position of ISEM16 field.
	HSEM_HSEM_ICR_ISEM16_Msk = 0x10000    // Bit mask of ISEM16 field.
	HSEM_HSEM_ICR_ISEM16     = 0x10000    // Bit ISEM16.
	HSEM_HSEM_ICR_ISEM17_Pos = 0x11       // Position of ISEM17 field.
	HSEM_HSEM_ICR_ISEM17_Msk = 0x20000    // Bit mask of ISEM17 field.
	HSEM_HSEM_ICR_ISEM17     = 0x20000    // Bit ISEM17.
	HSEM_HSEM_ICR_ISEM18_Pos = 0x12       // Position of ISEM18 field.
	HSEM_HSEM_ICR_ISEM18_Msk = 0x40000    // Bit mask of ISEM18 field.
	HSEM_HSEM_ICR_ISEM18     = 0x40000    // Bit ISEM18.
	HSEM_HSEM_ICR_ISEM19_Pos = 0x13       // Position of ISEM19 field.
	HSEM_HSEM_ICR_ISEM19_Msk = 0x80000    // Bit mask of ISEM19 field.
	HSEM_HSEM_ICR_ISEM19     = 0x80000    // Bit ISEM19.
	HSEM_HSEM_ICR_ISEM20_Pos = 0x14       // Position of ISEM20 field.
	HSEM_HSEM_ICR_ISEM20_Msk = 0x100000   // Bit mask of ISEM20 field.
	HSEM_HSEM_ICR_ISEM20     = 0x100000   // Bit ISEM20.
	HSEM_HSEM_ICR_ISEM21_Pos = 0x15       // Position of ISEM21 field.
	HSEM_HSEM_ICR_ISEM21_Msk = 0x200000   // Bit mask of ISEM21 field.
	HSEM_HSEM_ICR_ISEM21     = 0x200000   // Bit ISEM21.
	HSEM_HSEM_ICR_ISEM22_Pos = 0x16       // Position of ISEM22 field.
	HSEM_HSEM_ICR_ISEM22_Msk = 0x400000   // Bit mask of ISEM22 field.
	HSEM_HSEM_ICR_ISEM22     = 0x400000   // Bit ISEM22.
	HSEM_HSEM_ICR_ISEM23_Pos = 0x17       // Position of ISEM23 field.
	HSEM_HSEM_ICR_ISEM23_Msk = 0x800000   // Bit mask of ISEM23 field.
	HSEM_HSEM_ICR_ISEM23     = 0x800000   // Bit ISEM23.
	HSEM_HSEM_ICR_ISEM24_Pos = 0x18       // Position of ISEM24 field.
	HSEM_HSEM_ICR_ISEM24_Msk = 0x1000000  // Bit mask of ISEM24 field.
	HSEM_HSEM_ICR_ISEM24     = 0x1000000  // Bit ISEM24.
	HSEM_HSEM_ICR_ISEM25_Pos = 0x19       // Position of ISEM25 field.
	HSEM_HSEM_ICR_ISEM25_Msk = 0x2000000  // Bit mask of ISEM25 field.
	HSEM_HSEM_ICR_ISEM25     = 0x2000000  // Bit ISEM25.
	HSEM_HSEM_ICR_ISEM26_Pos = 0x1a       // Position of ISEM26 field.
	HSEM_HSEM_ICR_ISEM26_Msk = 0x4000000  // Bit mask of ISEM26 field.
	HSEM_HSEM_ICR_ISEM26     = 0x4000000  // Bit ISEM26.
	HSEM_HSEM_ICR_ISEM27_Pos = 0x1b       // Position of ISEM27 field.
	HSEM_HSEM_ICR_ISEM27_Msk = 0x8000000  // Bit mask of ISEM27 field.
	HSEM_HSEM_ICR_ISEM27     = 0x8000000  // Bit ISEM27.
	HSEM_HSEM_ICR_ISEM28_Pos = 0x1c       // Position of ISEM28 field.
	HSEM_HSEM_ICR_ISEM28_Msk = 0x10000000 // Bit mask of ISEM28 field.
	HSEM_HSEM_ICR_ISEM28     = 0x10000000 // Bit ISEM28.
	HSEM_HSEM_ICR_ISEM29_Pos = 0x1d       // Position of ISEM29 field.
	HSEM_HSEM_ICR_ISEM29_Msk = 0x20000000 // Bit mask of ISEM29 field.
	HSEM_HSEM_ICR_ISEM29     = 0x20000000 // Bit ISEM29.
	HSEM_HSEM_ICR_ISEM30_Pos = 0x1e       // Position of ISEM30 field.
	HSEM_HSEM_ICR_ISEM30_Msk = 0x40000000 // Bit mask of ISEM30 field.
	HSEM_HSEM_ICR_ISEM30     = 0x40000000 // Bit ISEM30.
	HSEM_HSEM_ICR_ISEM31_Pos = 0x1f       // Position of ISEM31 field.
	HSEM_HSEM_ICR_ISEM31_Msk = 0x80000000 // Bit mask of ISEM31 field.
	HSEM_HSEM_ICR_ISEM31     = 0x80000000 // Bit ISEM31.

	// HSEM_ISR: HSEM Interrupt status register
	HSEM_HSEM_ISR_ISEM0_Pos  = 0x0        // Position of ISEM0 field.
	HSEM_HSEM_ISR_ISEM0_Msk  = 0x1        // Bit mask of ISEM0 field.
	HSEM_HSEM_ISR_ISEM0      = 0x1        // Bit ISEM0.
	HSEM_HSEM_ISR_ISEM1_Pos  = 0x1        // Position of ISEM1 field.
	HSEM_HSEM_ISR_ISEM1_Msk  = 0x2        // Bit mask of ISEM1 field.
	HSEM_HSEM_ISR_ISEM1      = 0x2        // Bit ISEM1.
	HSEM_HSEM_ISR_ISEM2_Pos  = 0x2        // Position of ISEM2 field.
	HSEM_HSEM_ISR_ISEM2_Msk  = 0x4        // Bit mask of ISEM2 field.
	HSEM_HSEM_ISR_ISEM2      = 0x4        // Bit ISEM2.
	HSEM_HSEM_ISR_ISEM3_Pos  = 0x3        // Position of ISEM3 field.
	HSEM_HSEM_ISR_ISEM3_Msk  = 0x8        // Bit mask of ISEM3 field.
	HSEM_HSEM_ISR_ISEM3      = 0x8        // Bit ISEM3.
	HSEM_HSEM_ISR_ISEM4_Pos  = 0x4        // Position of ISEM4 field.
	HSEM_HSEM_ISR_ISEM4_Msk  = 0x10       // Bit mask of ISEM4 field.
	HSEM_HSEM_ISR_ISEM4      = 0x10       // Bit ISEM4.
	HSEM_HSEM_ISR_ISEM5_Pos  = 0x5        // Position of ISEM5 field.
	HSEM_HSEM_ISR_ISEM5_Msk  = 0x20       // Bit mask of ISEM5 field.
	HSEM_HSEM_ISR_ISEM5      = 0x20       // Bit ISEM5.
	HSEM_HSEM_ISR_ISEM6_Pos  = 0x6        // Position of ISEM6 field.
	HSEM_HSEM_ISR_ISEM6_Msk  = 0x40       // Bit mask of ISEM6 field.
	HSEM_HSEM_ISR_ISEM6      = 0x40       // Bit ISEM6.
	HSEM_HSEM_ISR_ISEM7_Pos  = 0x7        // Position of ISEM7 field.
	HSEM_HSEM_ISR_ISEM7_Msk  = 0x80       // Bit mask of ISEM7 field.
	HSEM_HSEM_ISR_ISEM7      = 0x80       // Bit ISEM7.
	HSEM_HSEM_ISR_ISEM8_Pos  = 0x8        // Position of ISEM8 field.
	HSEM_HSEM_ISR_ISEM8_Msk  = 0x100      // Bit mask of ISEM8 field.
	HSEM_HSEM_ISR_ISEM8      = 0x100      // Bit ISEM8.
	HSEM_HSEM_ISR_ISEM9_Pos  = 0x9        // Position of ISEM9 field.
	HSEM_HSEM_ISR_ISEM9_Msk  = 0x200      // Bit mask of ISEM9 field.
	HSEM_HSEM_ISR_ISEM9      = 0x200      // Bit ISEM9.
	HSEM_HSEM_ISR_ISEM10_Pos = 0xa        // Position of ISEM10 field.
	HSEM_HSEM_ISR_ISEM10_Msk = 0x400      // Bit mask of ISEM10 field.
	HSEM_HSEM_ISR_ISEM10     = 0x400      // Bit ISEM10.
	HSEM_HSEM_ISR_ISEM11_Pos = 0xb        // Position of ISEM11 field.
	HSEM_HSEM_ISR_ISEM11_Msk = 0x800      // Bit mask of ISEM11 field.
	HSEM_HSEM_ISR_ISEM11     = 0x800      // Bit ISEM11.
	HSEM_HSEM_ISR_ISEM12_Pos = 0xc        // Position of ISEM12 field.
	HSEM_HSEM_ISR_ISEM12_Msk = 0x1000     // Bit mask of ISEM12 field.
	HSEM_HSEM_ISR_ISEM12     = 0x1000     // Bit ISEM12.
	HSEM_HSEM_ISR_ISEM13_Pos = 0xd        // Position of ISEM13 field.
	HSEM_HSEM_ISR_ISEM13_Msk = 0x2000     // Bit mask of ISEM13 field.
	HSEM_HSEM_ISR_ISEM13     = 0x2000     // Bit ISEM13.
	HSEM_HSEM_ISR_ISEM14_Pos = 0xe        // Position of ISEM14 field.
	HSEM_HSEM_ISR_ISEM14_Msk = 0x4000     // Bit mask of ISEM14 field.
	HSEM_HSEM_ISR_ISEM14     = 0x4000     // Bit ISEM14.
	HSEM_HSEM_ISR_ISEM15_Pos = 0xf        // Position of ISEM15 field.
	HSEM_HSEM_ISR_ISEM15_Msk = 0x8000     // Bit mask of ISEM15 field.
	HSEM_HSEM_ISR_ISEM15     = 0x8000     // Bit ISEM15.
	HSEM_HSEM_ISR_ISEM16_Pos = 0x10       // Position of ISEM16 field.
	HSEM_HSEM_ISR_ISEM16_Msk = 0x10000    // Bit mask of ISEM16 field.
	HSEM_HSEM_ISR_ISEM16     = 0x10000    // Bit ISEM16.
	HSEM_HSEM_ISR_ISEM17_Pos = 0x11       // Position of ISEM17 field.
	HSEM_HSEM_ISR_ISEM17_Msk = 0x20000    // Bit mask of ISEM17 field.
	HSEM_HSEM_ISR_ISEM17     = 0x20000    // Bit ISEM17.
	HSEM_HSEM_ISR_ISEM18_Pos = 0x12       // Position of ISEM18 field.
	HSEM_HSEM_ISR_ISEM18_Msk = 0x40000    // Bit mask of ISEM18 field.
	HSEM_HSEM_ISR_ISEM18     = 0x40000    // Bit ISEM18.
	HSEM_HSEM_ISR_ISEM19_Pos = 0x13       // Position of ISEM19 field.
	HSEM_HSEM_ISR_ISEM19_Msk = 0x80000    // Bit mask of ISEM19 field.
	HSEM_HSEM_ISR_ISEM19     = 0x80000    // Bit ISEM19.
	HSEM_HSEM_ISR_ISEM20_Pos = 0x14       // Position of ISEM20 field.
	HSEM_HSEM_ISR_ISEM20_Msk = 0x100000   // Bit mask of ISEM20 field.
	HSEM_HSEM_ISR_ISEM20     = 0x100000   // Bit ISEM20.
	HSEM_HSEM_ISR_ISEM21_Pos = 0x15       // Position of ISEM21 field.
	HSEM_HSEM_ISR_ISEM21_Msk = 0x200000   // Bit mask of ISEM21 field.
	HSEM_HSEM_ISR_ISEM21     = 0x200000   // Bit ISEM21.
	HSEM_HSEM_ISR_ISEM22_Pos = 0x16       // Position of ISEM22 field.
	HSEM_HSEM_ISR_ISEM22_Msk = 0x400000   // Bit mask of ISEM22 field.
	HSEM_HSEM_ISR_ISEM22     = 0x400000   // Bit ISEM22.
	HSEM_HSEM_ISR_ISEM23_Pos = 0x17       // Position of ISEM23 field.
	HSEM_HSEM_ISR_ISEM23_Msk = 0x800000   // Bit mask of ISEM23 field.
	HSEM_HSEM_ISR_ISEM23     = 0x800000   // Bit ISEM23.
	HSEM_HSEM_ISR_ISEM24_Pos = 0x18       // Position of ISEM24 field.
	HSEM_HSEM_ISR_ISEM24_Msk = 0x1000000  // Bit mask of ISEM24 field.
	HSEM_HSEM_ISR_ISEM24     = 0x1000000  // Bit ISEM24.
	HSEM_HSEM_ISR_ISEM25_Pos = 0x19       // Position of ISEM25 field.
	HSEM_HSEM_ISR_ISEM25_Msk = 0x2000000  // Bit mask of ISEM25 field.
	HSEM_HSEM_ISR_ISEM25     = 0x2000000  // Bit ISEM25.
	HSEM_HSEM_ISR_ISEM26_Pos = 0x1a       // Position of ISEM26 field.
	HSEM_HSEM_ISR_ISEM26_Msk = 0x4000000  // Bit mask of ISEM26 field.
	HSEM_HSEM_ISR_ISEM26     = 0x4000000  // Bit ISEM26.
	HSEM_HSEM_ISR_ISEM27_Pos = 0x1b       // Position of ISEM27 field.
	HSEM_HSEM_ISR_ISEM27_Msk = 0x8000000  // Bit mask of ISEM27 field.
	HSEM_HSEM_ISR_ISEM27     = 0x8000000  // Bit ISEM27.
	HSEM_HSEM_ISR_ISEM28_Pos = 0x1c       // Position of ISEM28 field.
	HSEM_HSEM_ISR_ISEM28_Msk = 0x10000000 // Bit mask of ISEM28 field.
	HSEM_HSEM_ISR_ISEM28     = 0x10000000 // Bit ISEM28.
	HSEM_HSEM_ISR_ISEM29_Pos = 0x1d       // Position of ISEM29 field.
	HSEM_HSEM_ISR_ISEM29_Msk = 0x20000000 // Bit mask of ISEM29 field.
	HSEM_HSEM_ISR_ISEM29     = 0x20000000 // Bit ISEM29.
	HSEM_HSEM_ISR_ISEM30_Pos = 0x1e       // Position of ISEM30 field.
	HSEM_HSEM_ISR_ISEM30_Msk = 0x40000000 // Bit mask of ISEM30 field.
	HSEM_HSEM_ISR_ISEM30     = 0x40000000 // Bit ISEM30.
	HSEM_HSEM_ISR_ISEM31_Pos = 0x1f       // Position of ISEM31 field.
	HSEM_HSEM_ISR_ISEM31_Msk = 0x80000000 // Bit mask of ISEM31 field.
	HSEM_HSEM_ISR_ISEM31     = 0x80000000 // Bit ISEM31.

	// HSEM_MISR: HSEM Masked interrupt status           register
	HSEM_HSEM_MISR_ISEM0_Pos  = 0x0        // Position of ISEM0 field.
	HSEM_HSEM_MISR_ISEM0_Msk  = 0x1        // Bit mask of ISEM0 field.
	HSEM_HSEM_MISR_ISEM0      = 0x1        // Bit ISEM0.
	HSEM_HSEM_MISR_ISEM1_Pos  = 0x1        // Position of ISEM1 field.
	HSEM_HSEM_MISR_ISEM1_Msk  = 0x2        // Bit mask of ISEM1 field.
	HSEM_HSEM_MISR_ISEM1      = 0x2        // Bit ISEM1.
	HSEM_HSEM_MISR_ISEM2_Pos  = 0x2        // Position of ISEM2 field.
	HSEM_HSEM_MISR_ISEM2_Msk  = 0x4        // Bit mask of ISEM2 field.
	HSEM_HSEM_MISR_ISEM2      = 0x4        // Bit ISEM2.
	HSEM_HSEM_MISR_ISEM3_Pos  = 0x3        // Position of ISEM3 field.
	HSEM_HSEM_MISR_ISEM3_Msk  = 0x8        // Bit mask of ISEM3 field.
	HSEM_HSEM_MISR_ISEM3      = 0x8        // Bit ISEM3.
	HSEM_HSEM_MISR_ISEM4_Pos  = 0x4        // Position of ISEM4 field.
	HSEM_HSEM_MISR_ISEM4_Msk  = 0x10       // Bit mask of ISEM4 field.
	HSEM_HSEM_MISR_ISEM4      = 0x10       // Bit ISEM4.
	HSEM_HSEM_MISR_ISEM5_Pos  = 0x5        // Position of ISEM5 field.
	HSEM_HSEM_MISR_ISEM5_Msk  = 0x20       // Bit mask of ISEM5 field.
	HSEM_HSEM_MISR_ISEM5      = 0x20       // Bit ISEM5.
	HSEM_HSEM_MISR_ISEM6_Pos  = 0x6        // Position of ISEM6 field.
	HSEM_HSEM_MISR_ISEM6_Msk  = 0x40       // Bit mask of ISEM6 field.
	HSEM_HSEM_MISR_ISEM6      = 0x40       // Bit ISEM6.
	HSEM_HSEM_MISR_ISEM7_Pos  = 0x7        // Position of ISEM7 field.
	HSEM_HSEM_MISR_ISEM7_Msk  = 0x80       // Bit mask of ISEM7 field.
	HSEM_HSEM_MISR_ISEM7      = 0x80       // Bit ISEM7.
	HSEM_HSEM_MISR_ISEM8_Pos  = 0x8        // Position of ISEM8 field.
	HSEM_HSEM_MISR_ISEM8_Msk  = 0x100      // Bit mask of ISEM8 field.
	HSEM_HSEM_MISR_ISEM8      = 0x100      // Bit ISEM8.
	HSEM_HSEM_MISR_ISEM9_Pos  = 0x9        // Position of ISEM9 field.
	HSEM_HSEM_MISR_ISEM9_Msk  = 0x200      // Bit mask of ISEM9 field.
	HSEM_HSEM_MISR_ISEM9      = 0x200      // Bit ISEM9.
	HSEM_HSEM_MISR_ISEM10_Pos = 0xa        // Position of ISEM10 field.
	HSEM_HSEM_MISR_ISEM10_Msk = 0x400      // Bit mask of ISEM10 field.
	HSEM_HSEM_MISR_ISEM10     = 0x400      // Bit ISEM10.
	HSEM_HSEM_MISR_ISEM11_Pos = 0xb        // Position of ISEM11 field.
	HSEM_HSEM_MISR_ISEM11_Msk = 0x800      // Bit mask of ISEM11 field.
	HSEM_HSEM_MISR_ISEM11     = 0x800      // Bit ISEM11.
	HSEM_HSEM_MISR_ISEM12_Pos = 0xc        // Position of ISEM12 field.
	HSEM_HSEM_MISR_ISEM12_Msk = 0x1000     // Bit mask of ISEM12 field.
	HSEM_HSEM_MISR_ISEM12     = 0x1000     // Bit ISEM12.
	HSEM_HSEM_MISR_ISEM13_Pos = 0xd        // Position of ISEM13 field.
	HSEM_HSEM_MISR_ISEM13_Msk = 0x2000     // Bit mask of ISEM13 field.
	HSEM_HSEM_MISR_ISEM13     = 0x2000     // Bit ISEM13.
	HSEM_HSEM_MISR_ISEM14_Pos = 0xe        // Position of ISEM14 field.
	HSEM_HSEM_MISR_ISEM14_Msk = 0x4000     // Bit mask of ISEM14 field.
	HSEM_HSEM_MISR_ISEM14     = 0x4000     // Bit ISEM14.
	HSEM_HSEM_MISR_ISEM15_Pos = 0xf        // Position of ISEM15 field.
	HSEM_HSEM_MISR_ISEM15_Msk = 0x8000     // Bit mask of ISEM15 field.
	HSEM_HSEM_MISR_ISEM15     = 0x8000     // Bit ISEM15.
	HSEM_HSEM_MISR_ISEM16_Pos = 0x10       // Position of ISEM16 field.
	HSEM_HSEM_MISR_ISEM16_Msk = 0x10000    // Bit mask of ISEM16 field.
	HSEM_HSEM_MISR_ISEM16     = 0x10000    // Bit ISEM16.
	HSEM_HSEM_MISR_ISEM17_Pos = 0x11       // Position of ISEM17 field.
	HSEM_HSEM_MISR_ISEM17_Msk = 0x20000    // Bit mask of ISEM17 field.
	HSEM_HSEM_MISR_ISEM17     = 0x20000    // Bit ISEM17.
	HSEM_HSEM_MISR_ISEM18_Pos = 0x12       // Position of ISEM18 field.
	HSEM_HSEM_MISR_ISEM18_Msk = 0x40000    // Bit mask of ISEM18 field.
	HSEM_HSEM_MISR_ISEM18     = 0x40000    // Bit ISEM18.
	HSEM_HSEM_MISR_ISEM19_Pos = 0x13       // Position of ISEM19 field.
	HSEM_HSEM_MISR_ISEM19_Msk = 0x80000    // Bit mask of ISEM19 field.
	HSEM_HSEM_MISR_ISEM19     = 0x80000    // Bit ISEM19.
	HSEM_HSEM_MISR_ISEM20_Pos = 0x14       // Position of ISEM20 field.
	HSEM_HSEM_MISR_ISEM20_Msk = 0x100000   // Bit mask of ISEM20 field.
	HSEM_HSEM_MISR_ISEM20     = 0x100000   // Bit ISEM20.
	HSEM_HSEM_MISR_ISEM21_Pos = 0x15       // Position of ISEM21 field.
	HSEM_HSEM_MISR_ISEM21_Msk = 0x200000   // Bit mask of ISEM21 field.
	HSEM_HSEM_MISR_ISEM21     = 0x200000   // Bit ISEM21.
	HSEM_HSEM_MISR_ISEM22_Pos = 0x16       // Position of ISEM22 field.
	HSEM_HSEM_MISR_ISEM22_Msk = 0x400000   // Bit mask of ISEM22 field.
	HSEM_HSEM_MISR_ISEM22     = 0x400000   // Bit ISEM22.
	HSEM_HSEM_MISR_ISEM23_Pos = 0x17       // Position of ISEM23 field.
	HSEM_HSEM_MISR_ISEM23_Msk = 0x800000   // Bit mask of ISEM23 field.
	HSEM_HSEM_MISR_ISEM23     = 0x800000   // Bit ISEM23.
	HSEM_HSEM_MISR_ISEM24_Pos = 0x18       // Position of ISEM24 field.
	HSEM_HSEM_MISR_ISEM24_Msk = 0x1000000  // Bit mask of ISEM24 field.
	HSEM_HSEM_MISR_ISEM24     = 0x1000000  // Bit ISEM24.
	HSEM_HSEM_MISR_ISEM25_Pos = 0x19       // Position of ISEM25 field.
	HSEM_HSEM_MISR_ISEM25_Msk = 0x2000000  // Bit mask of ISEM25 field.
	HSEM_HSEM_MISR_ISEM25     = 0x2000000  // Bit ISEM25.
	HSEM_HSEM_MISR_ISEM26_Pos = 0x1a       // Position of ISEM26 field.
	HSEM_HSEM_MISR_ISEM26_Msk = 0x4000000  // Bit mask of ISEM26 field.
	HSEM_HSEM_MISR_ISEM26     = 0x4000000  // Bit ISEM26.
	HSEM_HSEM_MISR_ISEM27_Pos = 0x1b       // Position of ISEM27 field.
	HSEM_HSEM_MISR_ISEM27_Msk = 0x8000000  // Bit mask of ISEM27 field.
	HSEM_HSEM_MISR_ISEM27     = 0x8000000  // Bit ISEM27.
	HSEM_HSEM_MISR_ISEM28_Pos = 0x1c       // Position of ISEM28 field.
	HSEM_HSEM_MISR_ISEM28_Msk = 0x10000000 // Bit mask of ISEM28 field.
	HSEM_HSEM_MISR_ISEM28     = 0x10000000 // Bit ISEM28.
	HSEM_HSEM_MISR_ISEM29_Pos = 0x1d       // Position of ISEM29 field.
	HSEM_HSEM_MISR_ISEM29_Msk = 0x20000000 // Bit mask of ISEM29 field.
	HSEM_HSEM_MISR_ISEM29     = 0x20000000 // Bit ISEM29.
	HSEM_HSEM_MISR_ISEM30_Pos = 0x1e       // Position of ISEM30 field.
	HSEM_HSEM_MISR_ISEM30_Msk = 0x40000000 // Bit mask of ISEM30 field.
	HSEM_HSEM_MISR_ISEM30     = 0x40000000 // Bit ISEM30.
	HSEM_HSEM_MISR_ISEM31_Pos = 0x1f       // Position of ISEM31 field.
	HSEM_HSEM_MISR_ISEM31_Msk = 0x80000000 // Bit mask of ISEM31 field.
	HSEM_HSEM_MISR_ISEM31     = 0x80000000 // Bit ISEM31.

	// HSEM_CR: HSEM Clear register
	HSEM_HSEM_CR_MASTERID_Pos = 0x8        // Position of MASTERID field.
	HSEM_HSEM_CR_MASTERID_Msk = 0xff00     // Bit mask of MASTERID field.
	HSEM_HSEM_CR_KEY_Pos      = 0x10       // Position of KEY field.
	HSEM_HSEM_CR_KEY_Msk      = 0xffff0000 // Bit mask of KEY field.

	// HSEM_KEYR: HSEM Interrupt clear register
	HSEM_HSEM_KEYR_KEY_Pos = 0x10       // Position of KEY field.
	HSEM_HSEM_KEYR_KEY_Msk = 0xffff0000 // Bit mask of KEY field.
)

// Bitfields for I2C1: I2C
const (
	// CR1: Access: No wait states, except if a write           access occurs while a write access to this register is           ongoing. In this case, wait states are inserted in the           second write access until the previous one is completed.           The latency of the second write access can be up to 2 x           PCLK1 + 6 x I2CCLK.
	I2C_CR1_PE_Pos        = 0x0      // Position of PE field.
	I2C_CR1_PE_Msk        = 0x1      // Bit mask of PE field.
	I2C_CR1_PE            = 0x1      // Bit PE.
	I2C_CR1_TXIE_Pos      = 0x1      // Position of TXIE field.
	I2C_CR1_TXIE_Msk      = 0x2      // Bit mask of TXIE field.
	I2C_CR1_TXIE          = 0x2      // Bit TXIE.
	I2C_CR1_RXIE_Pos      = 0x2      // Position of RXIE field.
	I2C_CR1_RXIE_Msk      = 0x4      // Bit mask of RXIE field.
	I2C_CR1_RXIE          = 0x4      // Bit RXIE.
	I2C_CR1_ADDRIE_Pos    = 0x3      // Position of ADDRIE field.
	I2C_CR1_ADDRIE_Msk    = 0x8      // Bit mask of ADDRIE field.
	I2C_CR1_ADDRIE        = 0x8      // Bit ADDRIE.
	I2C_CR1_NACKIE_Pos    = 0x4      // Position of NACKIE field.
	I2C_CR1_NACKIE_Msk    = 0x10     // Bit mask of NACKIE field.
	I2C_CR1_NACKIE        = 0x10     // Bit NACKIE.
	I2C_CR1_STOPIE_Pos    = 0x5      // Position of STOPIE field.
	I2C_CR1_STOPIE_Msk    = 0x20     // Bit mask of STOPIE field.
	I2C_CR1_STOPIE        = 0x20     // Bit STOPIE.
	I2C_CR1_TCIE_Pos      = 0x6      // Position of TCIE field.
	I2C_CR1_TCIE_Msk      = 0x40     // Bit mask of TCIE field.
	I2C_CR1_TCIE          = 0x40     // Bit TCIE.
	I2C_CR1_ERRIE_Pos     = 0x7      // Position of ERRIE field.
	I2C_CR1_ERRIE_Msk     = 0x80     // Bit mask of ERRIE field.
	I2C_CR1_ERRIE         = 0x80     // Bit ERRIE.
	I2C_CR1_DNF_Pos       = 0x8      // Position of DNF field.
	I2C_CR1_DNF_Msk       = 0xf00    // Bit mask of DNF field.
	I2C_CR1_ANFOFF_Pos    = 0xc      // Position of ANFOFF field.
	I2C_CR1_ANFOFF_Msk    = 0x1000   // Bit mask of ANFOFF field.
	I2C_CR1_ANFOFF        = 0x1000   // Bit ANFOFF.
	I2C_CR1_TXDMAEN_Pos   = 0xe      // Position of TXDMAEN field.
	I2C_CR1_TXDMAEN_Msk   = 0x4000   // Bit mask of TXDMAEN field.
	I2C_CR1_TXDMAEN       = 0x4000   // Bit TXDMAEN.
	I2C_CR1_RXDMAEN_Pos   = 0xf      // Position of RXDMAEN field.
	I2C_CR1_RXDMAEN_Msk   = 0x8000   // Bit mask of RXDMAEN field.
	I2C_CR1_RXDMAEN       = 0x8000   // Bit RXDMAEN.
	I2C_CR1_SBC_Pos       = 0x10     // Position of SBC field.
	I2C_CR1_SBC_Msk       = 0x10000  // Bit mask of SBC field.
	I2C_CR1_SBC           = 0x10000  // Bit SBC.
	I2C_CR1_NOSTRETCH_Pos = 0x11     // Position of NOSTRETCH field.
	I2C_CR1_NOSTRETCH_Msk = 0x20000  // Bit mask of NOSTRETCH field.
	I2C_CR1_NOSTRETCH     = 0x20000  // Bit NOSTRETCH.
	I2C_CR1_WUPEN_Pos     = 0x12     // Position of WUPEN field.
	I2C_CR1_WUPEN_Msk     = 0x40000  // Bit mask of WUPEN field.
	I2C_CR1_WUPEN         = 0x40000  // Bit WUPEN.
	I2C_CR1_GCEN_Pos      = 0x13     // Position of GCEN field.
	I2C_CR1_GCEN_Msk      = 0x80000  // Bit mask of GCEN field.
	I2C_CR1_GCEN          = 0x80000  // Bit GCEN.
	I2C_CR1_SMBHEN_Pos    = 0x14     // Position of SMBHEN field.
	I2C_CR1_SMBHEN_Msk    = 0x100000 // Bit mask of SMBHEN field.
	I2C_CR1_SMBHEN        = 0x100000 // Bit SMBHEN.
	I2C_CR1_SMBDEN_Pos    = 0x15     // Position of SMBDEN field.
	I2C_CR1_SMBDEN_Msk    = 0x200000 // Bit mask of SMBDEN field.
	I2C_CR1_SMBDEN        = 0x200000 // Bit SMBDEN.
	I2C_CR1_ALERTEN_Pos   = 0x16     // Position of ALERTEN field.
	I2C_CR1_ALERTEN_Msk   = 0x400000 // Bit mask of ALERTEN field.
	I2C_CR1_ALERTEN       = 0x400000 // Bit ALERTEN.
	I2C_CR1_PECEN_Pos     = 0x17     // Position of PECEN field.
	I2C_CR1_PECEN_Msk     = 0x800000 // Bit mask of PECEN field.
	I2C_CR1_PECEN         = 0x800000 // Bit PECEN.

	// CR2: Access: No wait states, except if a write           access occurs while a write access to this register is           ongoing. In this case, wait states are inserted in the           second write access until the previous one is completed.           The latency of the second write access can be up to 2 x           PCLK1 + 6 x I2CCLK.
	I2C_CR2_SADD0_Pos   = 0x0       // Position of SADD0 field.
	I2C_CR2_SADD0_Msk   = 0x1       // Bit mask of SADD0 field.
	I2C_CR2_SADD0       = 0x1       // Bit SADD0.
	I2C_CR2_SADD1_Pos   = 0x1       // Position of SADD1 field.
	I2C_CR2_SADD1_Msk   = 0x2       // Bit mask of SADD1 field.
	I2C_CR2_SADD1       = 0x2       // Bit SADD1.
	I2C_CR2_SADD2_Pos   = 0x2       // Position of SADD2 field.
	I2C_CR2_SADD2_Msk   = 0x4       // Bit mask of SADD2 field.
	I2C_CR2_SADD2       = 0x4       // Bit SADD2.
	I2C_CR2_SADD3_Pos   = 0x3       // Position of SADD3 field.
	I2C_CR2_SADD3_Msk   = 0x8       // Bit mask of SADD3 field.
	I2C_CR2_SADD3       = 0x8       // Bit SADD3.
	I2C_CR2_SADD4_Pos   = 0x4       // Position of SADD4 field.
	I2C_CR2_SADD4_Msk   = 0x10      // Bit mask of SADD4 field.
	I2C_CR2_SADD4       = 0x10      // Bit SADD4.
	I2C_CR2_SADD5_Pos   = 0x5       // Position of SADD5 field.
	I2C_CR2_SADD5_Msk   = 0x20      // Bit mask of SADD5 field.
	I2C_CR2_SADD5       = 0x20      // Bit SADD5.
	I2C_CR2_SADD6_Pos   = 0x6       // Position of SADD6 field.
	I2C_CR2_SADD6_Msk   = 0x40      // Bit mask of SADD6 field.
	I2C_CR2_SADD6       = 0x40      // Bit SADD6.
	I2C_CR2_SADD7_Pos   = 0x7       // Position of SADD7 field.
	I2C_CR2_SADD7_Msk   = 0x80      // Bit mask of SADD7 field.
	I2C_CR2_SADD7       = 0x80      // Bit SADD7.
	I2C_CR2_SADD8_Pos   = 0x8       // Position of SADD8 field.
	I2C_CR2_SADD8_Msk   = 0x100     // Bit mask of SADD8 field.
	I2C_CR2_SADD8       = 0x100     // Bit SADD8.
	I2C_CR2_SADD9_Pos   = 0x9       // Position of SADD9 field.
	I2C_CR2_SADD9_Msk   = 0x200     // Bit mask of SADD9 field.
	I2C_CR2_SADD9       = 0x200     // Bit SADD9.
	I2C_CR2_RD_WRN_Pos  = 0xa       // Position of RD_WRN field.
	I2C_CR2_RD_WRN_Msk  = 0x400     // Bit mask of RD_WRN field.
	I2C_CR2_RD_WRN      = 0x400     // Bit RD_WRN.
	I2C_CR2_ADD10_Pos   = 0xb       // Position of ADD10 field.
	I2C_CR2_ADD10_Msk   = 0x800     // Bit mask of ADD10 field.
	I2C_CR2_ADD10       = 0x800     // Bit ADD10.
	I2C_CR2_HEAD10R_Pos = 0xc       // Position of HEAD10R field.
	I2C_CR2_HEAD10R_Msk = 0x1000    // Bit mask of HEAD10R field.
	I2C_CR2_HEAD10R     = 0x1000    // Bit HEAD10R.
	I2C_CR2_START_Pos   = 0xd       // Position of START field.
	I2C_CR2_START_Msk   = 0x2000    // Bit mask of START field.
	I2C_CR2_START       = 0x2000    // Bit START.
	I2C_CR2_STOP_Pos    = 0xe       // Position of STOP field.
	I2C_CR2_STOP_Msk    = 0x4000    // Bit mask of STOP field.
	I2C_CR2_STOP        = 0x4000    // Bit STOP.
	I2C_CR2_NACK_Pos    = 0xf       // Position of NACK field.
	I2C_CR2_NACK_Msk    = 0x8000    // Bit mask of NACK field.
	I2C_CR2_NACK        = 0x8000    // Bit NACK.
	I2C_CR2_NBYTES_Pos  = 0x10      // Position of NBYTES field.
	I2C_CR2_NBYTES_Msk  = 0xff0000  // Bit mask of NBYTES field.
	I2C_CR2_RELOAD_Pos  = 0x18      // Position of RELOAD field.
	I2C_CR2_RELOAD_Msk  = 0x1000000 // Bit mask of RELOAD field.
	I2C_CR2_RELOAD      = 0x1000000 // Bit RELOAD.
	I2C_CR2_AUTOEND_Pos = 0x19      // Position of AUTOEND field.
	I2C_CR2_AUTOEND_Msk = 0x2000000 // Bit mask of AUTOEND field.
	I2C_CR2_AUTOEND     = 0x2000000 // Bit AUTOEND.
	I2C_CR2_PECBYTE_Pos = 0x1a      // Position of PECBYTE field.
	I2C_CR2_PECBYTE_Msk = 0x4000000 // Bit mask of PECBYTE field.
	I2C_CR2_PECBYTE     = 0x4000000 // Bit PECBYTE.

	// OAR1: Access: No wait states, except if a write           access occurs while a write access to this register is           ongoing. In this case, wait states are inserted in the           second write access until the previous one is completed.           The latency of the second write access can be up to 2 x           PCLK1 + 6 x I2CCLK.
	I2C_OAR1_OA1_Pos     = 0x0    // Position of OA1 field.
	I2C_OAR1_OA1_Msk     = 0x3ff  // Bit mask of OA1 field.
	I2C_OAR1_OA1MODE_Pos = 0xa    // Position of OA1MODE field.
	I2C_OAR1_OA1MODE_Msk = 0x400  // Bit mask of OA1MODE field.
	I2C_OAR1_OA1MODE     = 0x400  // Bit OA1MODE.
	I2C_OAR1_OA1EN_Pos   = 0xf    // Position of OA1EN field.
	I2C_OAR1_OA1EN_Msk   = 0x8000 // Bit mask of OA1EN field.
	I2C_OAR1_OA1EN       = 0x8000 // Bit OA1EN.

	// OAR2: Access: No wait states, except if a write           access occurs while a write access to this register is           ongoing. In this case, wait states are inserted in the           second write access until the previous one is completed.           The latency of the second write access can be up to 2 x           PCLK1 + 6 x I2CCLK.
	I2C_OAR2_OA2_Pos    = 0x1    // Position of OA2 field.
	I2C_OAR2_OA2_Msk    = 0xfe   // Bit mask of OA2 field.
	I2C_OAR2_OA2MSK_Pos = 0x8    // Position of OA2MSK field.
	I2C_OAR2_OA2MSK_Msk = 0x700  // Bit mask of OA2MSK field.
	I2C_OAR2_OA2EN_Pos  = 0xf    // Position of OA2EN field.
	I2C_OAR2_OA2EN_Msk  = 0x8000 // Bit mask of OA2EN field.
	I2C_OAR2_OA2EN      = 0x8000 // Bit OA2EN.

	// TIMINGR: Access: No wait states
	I2C_TIMINGR_SCLL_Pos   = 0x0        // Position of SCLL field.
	I2C_TIMINGR_SCLL_Msk   = 0xff       // Bit mask of SCLL field.
	I2C_TIMINGR_SCLH_Pos   = 0x8        // Position of SCLH field.
	I2C_TIMINGR_SCLH_Msk   = 0xff00     // Bit mask of SCLH field.
	I2C_TIMINGR_SDADEL_Pos = 0x10       // Position of SDADEL field.
	I2C_TIMINGR_SDADEL_Msk = 0xf0000    // Bit mask of SDADEL field.
	I2C_TIMINGR_SCLDEL_Pos = 0x14       // Position of SCLDEL field.
	I2C_TIMINGR_SCLDEL_Msk = 0xf00000   // Bit mask of SCLDEL field.
	I2C_TIMINGR_PRESC_Pos  = 0x1c       // Position of PRESC field.
	I2C_TIMINGR_PRESC_Msk  = 0xf0000000 // Bit mask of PRESC field.

	// TIMEOUTR: Access: No wait states, except if a write           access occurs while a write access to this register is           ongoing. In this case, wait states are inserted in the           second write access until the previous one is completed.           The latency of the second write access can be up to 2 x           PCLK1 + 6 x I2CCLK.
	I2C_TIMEOUTR_TIMEOUTA_Pos = 0x0        // Position of TIMEOUTA field.
	I2C_TIMEOUTR_TIMEOUTA_Msk = 0xfff      // Bit mask of TIMEOUTA field.
	I2C_TIMEOUTR_TIDLE_Pos    = 0xc        // Position of TIDLE field.
	I2C_TIMEOUTR_TIDLE_Msk    = 0x1000     // Bit mask of TIDLE field.
	I2C_TIMEOUTR_TIDLE        = 0x1000     // Bit TIDLE.
	I2C_TIMEOUTR_TIMOUTEN_Pos = 0xf        // Position of TIMOUTEN field.
	I2C_TIMEOUTR_TIMOUTEN_Msk = 0x8000     // Bit mask of TIMOUTEN field.
	I2C_TIMEOUTR_TIMOUTEN     = 0x8000     // Bit TIMOUTEN.
	I2C_TIMEOUTR_TIMEOUTB_Pos = 0x10       // Position of TIMEOUTB field.
	I2C_TIMEOUTR_TIMEOUTB_Msk = 0xfff0000  // Bit mask of TIMEOUTB field.
	I2C_TIMEOUTR_TEXTEN_Pos   = 0x1f       // Position of TEXTEN field.
	I2C_TIMEOUTR_TEXTEN_Msk   = 0x80000000 // Bit mask of TEXTEN field.
	I2C_TIMEOUTR_TEXTEN       = 0x80000000 // Bit TEXTEN.

	// ISR: Access: No wait states
	I2C_ISR_TXE_Pos     = 0x0      // Position of TXE field.
	I2C_ISR_TXE_Msk     = 0x1      // Bit mask of TXE field.
	I2C_ISR_TXE         = 0x1      // Bit TXE.
	I2C_ISR_TXIS_Pos    = 0x1      // Position of TXIS field.
	I2C_ISR_TXIS_Msk    = 0x2      // Bit mask of TXIS field.
	I2C_ISR_TXIS        = 0x2      // Bit TXIS.
	I2C_ISR_RXNE_Pos    = 0x2      // Position of RXNE field.
	I2C_ISR_RXNE_Msk    = 0x4      // Bit mask of RXNE field.
	I2C_ISR_RXNE        = 0x4      // Bit RXNE.
	I2C_ISR_ADDR_Pos    = 0x3      // Position of ADDR field.
	I2C_ISR_ADDR_Msk    = 0x8      // Bit mask of ADDR field.
	I2C_ISR_ADDR        = 0x8      // Bit ADDR.
	I2C_ISR_NACKF_Pos   = 0x4      // Position of NACKF field.
	I2C_ISR_NACKF_Msk   = 0x10     // Bit mask of NACKF field.
	I2C_ISR_NACKF       = 0x10     // Bit NACKF.
	I2C_ISR_STOPF_Pos   = 0x5      // Position of STOPF field.
	I2C_ISR_STOPF_Msk   = 0x20     // Bit mask of STOPF field.
	I2C_ISR_STOPF       = 0x20     // Bit STOPF.
	I2C_ISR_TC_Pos      = 0x6      // Position of TC field.
	I2C_ISR_TC_Msk      = 0x40     // Bit mask of TC field.
	I2C_ISR_TC          = 0x40     // Bit TC.
	I2C_ISR_TCR_Pos     = 0x7      // Position of TCR field.
	I2C_ISR_TCR_Msk     = 0x80     // Bit mask of TCR field.
	I2C_ISR_TCR         = 0x80     // Bit TCR.
	I2C_ISR_BERR_Pos    = 0x8      // Position of BERR field.
	I2C_ISR_BERR_Msk    = 0x100    // Bit mask of BERR field.
	I2C_ISR_BERR        = 0x100    // Bit BERR.
	I2C_ISR_ARLO_Pos    = 0x9      // Position of ARLO field.
	I2C_ISR_ARLO_Msk    = 0x200    // Bit mask of ARLO field.
	I2C_ISR_ARLO        = 0x200    // Bit ARLO.
	I2C_ISR_OVR_Pos     = 0xa      // Position of OVR field.
	I2C_ISR_OVR_Msk     = 0x400    // Bit mask of OVR field.
	I2C_ISR_OVR         = 0x400    // Bit OVR.
	I2C_ISR_PECERR_Pos  = 0xb      // Position of PECERR field.
	I2C_ISR_PECERR_Msk  = 0x800    // Bit mask of PECERR field.
	I2C_ISR_PECERR      = 0x800    // Bit PECERR.
	I2C_ISR_TIMEOUT_Pos = 0xc      // Position of TIMEOUT field.
	I2C_ISR_TIMEOUT_Msk = 0x1000   // Bit mask of TIMEOUT field.
	I2C_ISR_TIMEOUT     = 0x1000   // Bit TIMEOUT.
	I2C_ISR_ALERT_Pos   = 0xd      // Position of ALERT field.
	I2C_ISR_ALERT_Msk   = 0x2000   // Bit mask of ALERT field.
	I2C_ISR_ALERT       = 0x2000   // Bit ALERT.
	I2C_ISR_BUSY_Pos    = 0xf      // Position of BUSY field.
	I2C_ISR_BUSY_Msk    = 0x8000   // Bit mask of BUSY field.
	I2C_ISR_BUSY        = 0x8000   // Bit BUSY.
	I2C_ISR_DIR_Pos     = 0x10     // Position of DIR field.
	I2C_ISR_DIR_Msk     = 0x10000  // Bit mask of DIR field.
	I2C_ISR_DIR         = 0x10000  // Bit DIR.
	I2C_ISR_ADDCODE_Pos = 0x11     // Position of ADDCODE field.
	I2C_ISR_ADDCODE_Msk = 0xfe0000 // Bit mask of ADDCODE field.

	// ICR: Access: No wait states
	I2C_ICR_ADDRCF_Pos   = 0x3    // Position of ADDRCF field.
	I2C_ICR_ADDRCF_Msk   = 0x8    // Bit mask of ADDRCF field.
	I2C_ICR_ADDRCF       = 0x8    // Bit ADDRCF.
	I2C_ICR_NACKCF_Pos   = 0x4    // Position of NACKCF field.
	I2C_ICR_NACKCF_Msk   = 0x10   // Bit mask of NACKCF field.
	I2C_ICR_NACKCF       = 0x10   // Bit NACKCF.
	I2C_ICR_STOPCF_Pos   = 0x5    // Position of STOPCF field.
	I2C_ICR_STOPCF_Msk   = 0x20   // Bit mask of STOPCF field.
	I2C_ICR_STOPCF       = 0x20   // Bit STOPCF.
	I2C_ICR_BERRCF_Pos   = 0x8    // Position of BERRCF field.
	I2C_ICR_BERRCF_Msk   = 0x100  // Bit mask of BERRCF field.
	I2C_ICR_BERRCF       = 0x100  // Bit BERRCF.
	I2C_ICR_ARLOCF_Pos   = 0x9    // Position of ARLOCF field.
	I2C_ICR_ARLOCF_Msk   = 0x200  // Bit mask of ARLOCF field.
	I2C_ICR_ARLOCF       = 0x200  // Bit ARLOCF.
	I2C_ICR_OVRCF_Pos    = 0xa    // Position of OVRCF field.
	I2C_ICR_OVRCF_Msk    = 0x400  // Bit mask of OVRCF field.
	I2C_ICR_OVRCF        = 0x400  // Bit OVRCF.
	I2C_ICR_PECCF_Pos    = 0xb    // Position of PECCF field.
	I2C_ICR_PECCF_Msk    = 0x800  // Bit mask of PECCF field.
	I2C_ICR_PECCF        = 0x800  // Bit PECCF.
	I2C_ICR_TIMOUTCF_Pos = 0xc    // Position of TIMOUTCF field.
	I2C_ICR_TIMOUTCF_Msk = 0x1000 // Bit mask of TIMOUTCF field.
	I2C_ICR_TIMOUTCF     = 0x1000 // Bit TIMOUTCF.
	I2C_ICR_ALERTCF_Pos  = 0xd    // Position of ALERTCF field.
	I2C_ICR_ALERTCF_Msk  = 0x2000 // Bit mask of ALERTCF field.
	I2C_ICR_ALERTCF      = 0x2000 // Bit ALERTCF.

	// PECR: Access: No wait states
	I2C_PECR_PEC_Pos = 0x0  // Position of PEC field.
	I2C_PECR_PEC_Msk = 0xff // Bit mask of PEC field.

	// RXDR: Access: No wait states
	I2C_RXDR_RXDATA_Pos = 0x0  // Position of RXDATA field.
	I2C_RXDR_RXDATA_Msk = 0xff // Bit mask of RXDATA field.

	// TXDR: Access: No wait states
	I2C_TXDR_TXDATA_Pos = 0x0  // Position of TXDATA field.
	I2C_TXDR_TXDATA_Msk = 0xff // Bit mask of TXDATA field.
)

// Bitfields for GPIOA: GPIO
const (
	// MODER: GPIO port mode register
	GPIO_MODER_MODE0_Pos  = 0x0        // Position of MODE0 field.
	GPIO_MODER_MODE0_Msk  = 0x3        // Bit mask of MODE0 field.
	GPIO_MODER_MODE1_Pos  = 0x2        // Position of MODE1 field.
	GPIO_MODER_MODE1_Msk  = 0xc        // Bit mask of MODE1 field.
	GPIO_MODER_MODE2_Pos  = 0x4        // Position of MODE2 field.
	GPIO_MODER_MODE2_Msk  = 0x30       // Bit mask of MODE2 field.
	GPIO_MODER_MODE3_Pos  = 0x6        // Position of MODE3 field.
	GPIO_MODER_MODE3_Msk  = 0xc0       // Bit mask of MODE3 field.
	GPIO_MODER_MODE4_Pos  = 0x8        // Position of MODE4 field.
	GPIO_MODER_MODE4_Msk  = 0x300      // Bit mask of MODE4 field.
	GPIO_MODER_MODE5_Pos  = 0xa        // Position of MODE5 field.
	GPIO_MODER_MODE5_Msk  = 0xc00      // Bit mask of MODE5 field.
	GPIO_MODER_MODE6_Pos  = 0xc        // Position of MODE6 field.
	GPIO_MODER_MODE6_Msk  = 0x3000     // Bit mask of MODE6 field.
	GPIO_MODER_MODE7_Pos  = 0xe        // Position of MODE7 field.
	GPIO_MODER_MODE7_Msk  = 0xc000     // Bit mask of MODE7 field.
	GPIO_MODER_MODE8_Pos  = 0x10       // Position of MODE8 field.
	GPIO_MODER_MODE8_Msk  = 0x30000    // Bit mask of MODE8 field.
	GPIO_MODER_MODE9_Pos  = 0x12       // Position of MODE9 field.
	GPIO_MODER_MODE9_Msk  = 0xc0000    // Bit mask of MODE9 field.
	GPIO_MODER_MODE10_Pos = 0x14       // Position of MODE10 field.
	GPIO_MODER_MODE10_Msk = 0x300000   // Bit mask of MODE10 field.
	GPIO_MODER_MODE11_Pos = 0x16       // Position of MODE11 field.
	GPIO_MODER_MODE11_Msk = 0xc00000   // Bit mask of MODE11 field.
	GPIO_MODER_MODE12_Pos = 0x18       // Position of MODE12 field.
	GPIO_MODER_MODE12_Msk = 0x3000000  // Bit mask of MODE12 field.
	GPIO_MODER_MODE13_Pos = 0x1a       // Position of MODE13 field.
	GPIO_MODER_MODE13_Msk = 0xc000000  // Bit mask of MODE13 field.
	GPIO_MODER_MODE14_Pos = 0x1c       // Position of MODE14 field.
	GPIO_MODER_MODE14_Msk = 0x30000000 // Bit mask of MODE14 field.
	GPIO_MODER_MODE15_Pos = 0x1e       // Position of MODE15 field.
	GPIO_MODER_MODE15_Msk = 0xc0000000 // Bit mask of MODE15 field.

	// OTYPER: GPIO port output type register
	GPIO_OTYPER_OT0_Pos  = 0x0    // Position of OT0 field.
	GPIO_OTYPER_OT0_Msk  = 0x1    // Bit mask of OT0 field.
	GPIO_OTYPER_OT0      = 0x1    // Bit OT0.
	GPIO_OTYPER_OT1_Pos  = 0x1    // Position of OT1 field.
	GPIO_OTYPER_OT1_Msk  = 0x2    // Bit mask of OT1 field.
	GPIO_OTYPER_OT1      = 0x2    // Bit OT1.
	GPIO_OTYPER_OT2_Pos  = 0x2    // Position of OT2 field.
	GPIO_OTYPER_OT2_Msk  = 0x4    // Bit mask of OT2 field.
	GPIO_OTYPER_OT2      = 0x4    // Bit OT2.
	GPIO_OTYPER_OT3_Pos  = 0x3    // Position of OT3 field.
	GPIO_OTYPER_OT3_Msk  = 0x8    // Bit mask of OT3 field.
	GPIO_OTYPER_OT3      = 0x8    // Bit OT3.
	GPIO_OTYPER_OT4_Pos  = 0x4    // Position of OT4 field.
	GPIO_OTYPER_OT4_Msk  = 0x10   // Bit mask of OT4 field.
	GPIO_OTYPER_OT4      = 0x10   // Bit OT4.
	GPIO_OTYPER_OT5_Pos  = 0x5    // Position of OT5 field.
	GPIO_OTYPER_OT5_Msk  = 0x20   // Bit mask of OT5 field.
	GPIO_OTYPER_OT5      = 0x20   // Bit OT5.
	GPIO_OTYPER_OT6_Pos  = 0x6    // Position of OT6 field.
	GPIO_OTYPER_OT6_Msk  = 0x40   // Bit mask of OT6 field.
	GPIO_OTYPER_OT6      = 0x40   // Bit OT6.
	GPIO_OTYPER_OT7_Pos  = 0x7    // Position of OT7 field.
	GPIO_OTYPER_OT7_Msk  = 0x80   // Bit mask of OT7 field.
	GPIO_OTYPER_OT7      = 0x80   // Bit OT7.
	GPIO_OTYPER_OT8_Pos  = 0x8    // Position of OT8 field.
	GPIO_OTYPER_OT8_Msk  = 0x100  // Bit mask of OT8 field.
	GPIO_OTYPER_OT8      = 0x100  // Bit OT8.
	GPIO_OTYPER_OT9_Pos  = 0x9    // Position of OT9 field.
	GPIO_OTYPER_OT9_Msk  = 0x200  // Bit mask of OT9 field.
	GPIO_OTYPER_OT9      = 0x200  // Bit OT9.
	GPIO_OTYPER_OT10_Pos = 0xa    // Position of OT10 field.
	GPIO_OTYPER_OT10_Msk = 0x400  // Bit mask of OT10 field.
	GPIO_OTYPER_OT10     = 0x400  // Bit OT10.
	GPIO_OTYPER_OT11_Pos = 0xb    // Position of OT11 field.
	GPIO_OTYPER_OT11_Msk = 0x800  // Bit mask of OT11 field.
	GPIO_OTYPER_OT11     = 0x800  // Bit OT11.
	GPIO_OTYPER_OT12_Pos = 0xc    // Position of OT12 field.
	GPIO_OTYPER_OT12_Msk = 0x1000 // Bit mask of OT12 field.
	GPIO_OTYPER_OT12     = 0x1000 // Bit OT12.
	GPIO_OTYPER_OT13_Pos = 0xd    // Position of OT13 field.
	GPIO_OTYPER_OT13_Msk = 0x2000 // Bit mask of OT13 field.
	GPIO_OTYPER_OT13     = 0x2000 // Bit OT13.
	GPIO_OTYPER_OT14_Pos = 0xe    // Position of OT14 field.
	GPIO_OTYPER_OT14_Msk = 0x4000 // Bit mask of OT14 field.
	GPIO_OTYPER_OT14     = 0x4000 // Bit OT14.
	GPIO_OTYPER_OT15_Pos = 0xf    // Position of OT15 field.
	GPIO_OTYPER_OT15_Msk = 0x8000 // Bit mask of OT15 field.
	GPIO_OTYPER_OT15     = 0x8000 // Bit OT15.

	// OSPEEDR: GPIO port output speed           register
	GPIO_OSPEEDR_OSPEED0_Pos  = 0x0        // Position of OSPEED0 field.
	GPIO_OSPEEDR_OSPEED0_Msk  = 0x3        // Bit mask of OSPEED0 field.
	GPIO_OSPEEDR_OSPEED1_Pos  = 0x2        // Position of OSPEED1 field.
	GPIO_OSPEEDR_OSPEED1_Msk  = 0xc        // Bit mask of OSPEED1 field.
	GPIO_OSPEEDR_OSPEED2_Pos  = 0x4        // Position of OSPEED2 field.
	GPIO_OSPEEDR_OSPEED2_Msk  = 0x30       // Bit mask of OSPEED2 field.
	GPIO_OSPEEDR_OSPEED3_Pos  = 0x6        // Position of OSPEED3 field.
	GPIO_OSPEEDR_OSPEED3_Msk  = 0xc0       // Bit mask of OSPEED3 field.
	GPIO_OSPEEDR_OSPEED4_Pos  = 0x8        // Position of OSPEED4 field.
	GPIO_OSPEEDR_OSPEED4_Msk  = 0x300      // Bit mask of OSPEED4 field.
	GPIO_OSPEEDR_OSPEED5_Pos  = 0xa        // Position of OSPEED5 field.
	GPIO_OSPEEDR_OSPEED5_Msk  = 0xc00      // Bit mask of OSPEED5 field.
	GPIO_OSPEEDR_OSPEED6_Pos  = 0xc        // Position of OSPEED6 field.
	GPIO_OSPEEDR_OSPEED6_Msk  = 0x3000     // Bit mask of OSPEED6 field.
	GPIO_OSPEEDR_OSPEED7_Pos  = 0xe        // Position of OSPEED7 field.
	GPIO_OSPEEDR_OSPEED7_Msk  = 0xc000     // Bit mask of OSPEED7 field.
	GPIO_OSPEEDR_OSPEED8_Pos  = 0x10       // Position of OSPEED8 field.
	GPIO_OSPEEDR_OSPEED8_Msk  = 0x30000    // Bit mask of OSPEED8 field.
	GPIO_OSPEEDR_OSPEED9_Pos  = 0x12       // Position of OSPEED9 field.
	GPIO_OSPEEDR_OSPEED9_Msk  = 0xc0000    // Bit mask of OSPEED9 field.
	GPIO_OSPEEDR_OSPEED10_Pos = 0x14       // Position of OSPEED10 field.
	GPIO_OSPEEDR_OSPEED10_Msk = 0x300000   // Bit mask of OSPEED10 field.
	GPIO_OSPEEDR_OSPEED11_Pos = 0x16       // Position of OSPEED11 field.
	GPIO_OSPEEDR_OSPEED11_Msk = 0xc00000   // Bit mask of OSPEED11 field.
	GPIO_OSPEEDR_OSPEED12_Pos = 0x18       // Position of OSPEED12 field.
	GPIO_OSPEEDR_OSPEED12_Msk = 0x3000000  // Bit mask of OSPEED12 field.
	GPIO_OSPEEDR_OSPEED13_Pos = 0x1a       // Position of OSPEED13 field.
	GPIO_OSPEEDR_OSPEED13_Msk = 0xc000000  // Bit mask of OSPEED13 field.
	GPIO_OSPEEDR_OSPEED14_Pos = 0x1c       // Position of OSPEED14 field.
	GPIO_OSPEEDR_OSPEED14_Msk = 0x30000000 // Bit mask of OSPEED14 field.
	GPIO_OSPEEDR_OSPEED15_Pos = 0x1e       // Position of OSPEED15 field.
	GPIO_OSPEEDR_OSPEED15_Msk = 0xc0000000 // Bit mask of OSPEED15 field.

	// PUPDR: GPIO port pull-up/pull-down           register
	GPIO_PUPDR_PUPD0_Pos  = 0x0        // Position of PUPD0 field.
	GPIO_PUPDR_PUPD0_Msk  = 0x3        // Bit mask of PUPD0 field.
	GPIO_PUPDR_PUPD1_Pos  = 0x2        // Position of PUPD1 field.
	GPIO_PUPDR_PUPD1_Msk  = 0xc        // Bit mask of PUPD1 field.
	GPIO_PUPDR_PUPD2_Pos  = 0x4        // Position of PUPD2 field.
	GPIO_PUPDR_PUPD2_Msk  = 0x30       // Bit mask of PUPD2 field.
	GPIO_PUPDR_PUPD3_Pos  = 0x6        // Position of PUPD3 field.
	GPIO_PUPDR_PUPD3_Msk  = 0xc0       // Bit mask of PUPD3 field.
	GPIO_PUPDR_PUPD4_Pos  = 0x8        // Position of PUPD4 field.
	GPIO_PUPDR_PUPD4_Msk  = 0x300      // Bit mask of PUPD4 field.
	GPIO_PUPDR_PUPD5_Pos  = 0xa        // Position of PUPD5 field.
	GPIO_PUPDR_PUPD5_Msk  = 0xc00      // Bit mask of PUPD5 field.
	GPIO_PUPDR_PUPD6_Pos  = 0xc        // Position of PUPD6 field.
	GPIO_PUPDR_PUPD6_Msk  = 0x3000     // Bit mask of PUPD6 field.
	GPIO_PUPDR_PUPD7_Pos  = 0xe        // Position of PUPD7 field.
	GPIO_PUPDR_PUPD7_Msk  = 0xc000     // Bit mask of PUPD7 field.
	GPIO_PUPDR_PUPD8_Pos  = 0x10       // Position of PUPD8 field.
	GPIO_PUPDR_PUPD8_Msk  = 0x30000    // Bit mask of PUPD8 field.
	GPIO_PUPDR_PUPD9_Pos  = 0x12       // Position of PUPD9 field.
	GPIO_PUPDR_PUPD9_Msk  = 0xc0000    // Bit mask of PUPD9 field.
	GPIO_PUPDR_PUPD10_Pos = 0x14       // Position of PUPD10 field.
	GPIO_PUPDR_PUPD10_Msk = 0x300000   // Bit mask of PUPD10 field.
	GPIO_PUPDR_PUPD11_Pos = 0x16       // Position of PUPD11 field.
	GPIO_PUPDR_PUPD11_Msk = 0xc00000   // Bit mask of PUPD11 field.
	GPIO_PUPDR_PUPD12_Pos = 0x18       // Position of PUPD12 field.
	GPIO_PUPDR_PUPD12_Msk = 0x3000000  // Bit mask of PUPD12 field.
	GPIO_PUPDR_PUPD13_Pos = 0x1a       // Position of PUPD13 field.
	GPIO_PUPDR_PUPD13_Msk = 0xc000000  // Bit mask of PUPD13 field.
	GPIO_PUPDR_PUPD14_Pos = 0x1c       // Position of PUPD14 field.
	GPIO_PUPDR_PUPD14_Msk = 0x30000000 // Bit mask of PUPD14 field.
	GPIO_PUPDR_PUPD15_Pos = 0x1e       // Position of PUPD15 field.
	GPIO_PUPDR_PUPD15_Msk = 0xc0000000 // Bit mask of PUPD15 field.

	// IDR: GPIO port input data register
	GPIO_IDR_ID0_Pos  = 0x0    // Position of ID0 field.
	GPIO_IDR_ID0_Msk  = 0x1    // Bit mask of ID0 field.
	GPIO_IDR_ID0      = 0x1    // Bit ID0.
	GPIO_IDR_ID1_Pos  = 0x1    // Position of ID1 field.
	GPIO_IDR_ID1_Msk  = 0x2    // Bit mask of ID1 field.
	GPIO_IDR_ID1      = 0x2    // Bit ID1.
	GPIO_IDR_ID2_Pos  = 0x2    // Position of ID2 field.
	GPIO_IDR_ID2_Msk  = 0x4    // Bit mask of ID2 field.
	GPIO_IDR_ID2      = 0x4    // Bit ID2.
	GPIO_IDR_ID3_Pos  = 0x3    // Position of ID3 field.
	GPIO_IDR_ID3_Msk  = 0x8    // Bit mask of ID3 field.
	GPIO_IDR_ID3      = 0x8    // Bit ID3.
	GPIO_IDR_ID4_Pos  = 0x4    // Position of ID4 field.
	GPIO_IDR_ID4_Msk  = 0x10   // Bit mask of ID4 field.
	GPIO_IDR_ID4      = 0x10   // Bit ID4.
	GPIO_IDR_ID5_Pos  = 0x5    // Position of ID5 field.
	GPIO_IDR_ID5_Msk  = 0x20   // Bit mask of ID5 field.
	GPIO_IDR_ID5      = 0x20   // Bit ID5.
	GPIO_IDR_ID6_Pos  = 0x6    // Position of ID6 field.
	GPIO_IDR_ID6_Msk  = 0x40   // Bit mask of ID6 field.
	GPIO_IDR_ID6      = 0x40   // Bit ID6.
	GPIO_IDR_ID7_Pos  = 0x7    // Position of ID7 field.
	GPIO_IDR_ID7_Msk  = 0x80   // Bit mask of ID7 field.
	GPIO_IDR_ID7      = 0x80   // Bit ID7.
	GPIO_IDR_ID8_Pos  = 0x8    // Position of ID8 field.
	GPIO_IDR_ID8_Msk  = 0x100  // Bit mask of ID8 field.
	GPIO_IDR_ID8      = 0x100  // Bit ID8.
	GPIO_IDR_ID9_Pos  = 0x9    // Position of ID9 field.
	GPIO_IDR_ID9_Msk  = 0x200  // Bit mask of ID9 field.
	GPIO_IDR_ID9      = 0x200  // Bit ID9.
	GPIO_IDR_ID10_Pos = 0xa    // Position of ID10 field.
	GPIO_IDR_ID10_Msk = 0x400  // Bit mask of ID10 field.
	GPIO_IDR_ID10     = 0x400  // Bit ID10.
	GPIO_IDR_ID11_Pos = 0xb    // Position of ID11 field.
	GPIO_IDR_ID11_Msk = 0x800  // Bit mask of ID11 field.
	GPIO_IDR_ID11     = 0x800  // Bit ID11.
	GPIO_IDR_ID12_Pos = 0xc    // Position of ID12 field.
	GPIO_IDR_ID12_Msk = 0x1000 // Bit mask of ID12 field.
	GPIO_IDR_ID12     = 0x1000 // Bit ID12.
	GPIO_IDR_ID13_Pos = 0xd    // Position of ID13 field.
	GPIO_IDR_ID13_Msk = 0x2000 // Bit mask of ID13 field.
	GPIO_IDR_ID13     = 0x2000 // Bit ID13.
	GPIO_IDR_ID14_Pos = 0xe    // Position of ID14 field.
	GPIO_IDR_ID14_Msk = 0x4000 // Bit mask of ID14 field.
	GPIO_IDR_ID14     = 0x4000 // Bit ID14.
	GPIO_IDR_ID15_Pos = 0xf    // Position of ID15 field.
	GPIO_IDR_ID15_Msk = 0x8000 // Bit mask of ID15 field.
	GPIO_IDR_ID15     = 0x8000 // Bit ID15.

	// ODR: GPIO port output data register
	GPIO_ODR_OD0_Pos  = 0x0    // Position of OD0 field.
	GPIO_ODR_OD0_Msk  = 0x1    // Bit mask of OD0 field.
	GPIO_ODR_OD0      = 0x1    // Bit OD0.
	GPIO_ODR_OD1_Pos  = 0x1    // Position of OD1 field.
	GPIO_ODR_OD1_Msk  = 0x2    // Bit mask of OD1 field.
	GPIO_ODR_OD1      = 0x2    // Bit OD1.
	GPIO_ODR_OD2_Pos  = 0x2    // Position of OD2 field.
	GPIO_ODR_OD2_Msk  = 0x4    // Bit mask of OD2 field.
	GPIO_ODR_OD2      = 0x4    // Bit OD2.
	GPIO_ODR_OD3_Pos  = 0x3    // Position of OD3 field.
	GPIO_ODR_OD3_Msk  = 0x8    // Bit mask of OD3 field.
	GPIO_ODR_OD3      = 0x8    // Bit OD3.
	GPIO_ODR_OD4_Pos  = 0x4    // Position of OD4 field.
	GPIO_ODR_OD4_Msk  = 0x10   // Bit mask of OD4 field.
	GPIO_ODR_OD4      = 0x10   // Bit OD4.
	GPIO_ODR_OD5_Pos  = 0x5    // Position of OD5 field.
	GPIO_ODR_OD5_Msk  = 0x20   // Bit mask of OD5 field.
	GPIO_ODR_OD5      = 0x20   // Bit OD5.
	GPIO_ODR_OD6_Pos  = 0x6    // Position of OD6 field.
	GPIO_ODR_OD6_Msk  = 0x40   // Bit mask of OD6 field.
	GPIO_ODR_OD6      = 0x40   // Bit OD6.
	GPIO_ODR_OD7_Pos  = 0x7    // Position of OD7 field.
	GPIO_ODR_OD7_Msk  = 0x80   // Bit mask of OD7 field.
	GPIO_ODR_OD7      = 0x80   // Bit OD7.
	GPIO_ODR_OD8_Pos  = 0x8    // Position of OD8 field.
	GPIO_ODR_OD8_Msk  = 0x100  // Bit mask of OD8 field.
	GPIO_ODR_OD8      = 0x100  // Bit OD8.
	GPIO_ODR_OD9_Pos  = 0x9    // Position of OD9 field.
	GPIO_ODR_OD9_Msk  = 0x200  // Bit mask of OD9 field.
	GPIO_ODR_OD9      = 0x200  // Bit OD9.
	GPIO_ODR_OD10_Pos = 0xa    // Position of OD10 field.
	GPIO_ODR_OD10_Msk = 0x400  // Bit mask of OD10 field.
	GPIO_ODR_OD10     = 0x400  // Bit OD10.
	GPIO_ODR_OD11_Pos = 0xb    // Position of OD11 field.
	GPIO_ODR_OD11_Msk = 0x800  // Bit mask of OD11 field.
	GPIO_ODR_OD11     = 0x800  // Bit OD11.
	GPIO_ODR_OD12_Pos = 0xc    // Position of OD12 field.
	GPIO_ODR_OD12_Msk = 0x1000 // Bit mask of OD12 field.
	GPIO_ODR_OD12     = 0x1000 // Bit OD12.
	GPIO_ODR_OD13_Pos = 0xd    // Position of OD13 field.
	GPIO_ODR_OD13_Msk = 0x2000 // Bit mask of OD13 field.
	GPIO_ODR_OD13     = 0x2000 // Bit OD13.
	GPIO_ODR_OD14_Pos = 0xe    // Position of OD14 field.
	GPIO_ODR_OD14_Msk = 0x4000 // Bit mask of OD14 field.
	GPIO_ODR_OD14     = 0x4000 // Bit OD14.
	GPIO_ODR_OD15_Pos = 0xf    // Position of OD15 field.
	GPIO_ODR_OD15_Msk = 0x8000 // Bit mask of OD15 field.
	GPIO_ODR_OD15     = 0x8000 // Bit OD15.

	// BSRR: GPIO port bit set/reset           register
	GPIO_BSRR_BS0_Pos  = 0x0        // Position of BS0 field.
	GPIO_BSRR_BS0_Msk  = 0x1        // Bit mask of BS0 field.
	GPIO_BSRR_BS0      = 0x1        // Bit BS0.
	GPIO_BSRR_BS1_Pos  = 0x1        // Position of BS1 field.
	GPIO_BSRR_BS1_Msk  = 0x2        // Bit mask of BS1 field.
	GPIO_BSRR_BS1      = 0x2        // Bit BS1.
	GPIO_BSRR_BS2_Pos  = 0x2        // Position of BS2 field.
	GPIO_BSRR_BS2_Msk  = 0x4        // Bit mask of BS2 field.
	GPIO_BSRR_BS2      = 0x4        // Bit BS2.
	GPIO_BSRR_BS3_Pos  = 0x3        // Position of BS3 field.
	GPIO_BSRR_BS3_Msk  = 0x8        // Bit mask of BS3 field.
	GPIO_BSRR_BS3      = 0x8        // Bit BS3.
	GPIO_BSRR_BS4_Pos  = 0x4        // Position of BS4 field.
	GPIO_BSRR_BS4_Msk  = 0x10       // Bit mask of BS4 field.
	GPIO_BSRR_BS4      = 0x10       // Bit BS4.
	GPIO_BSRR_BS5_Pos  = 0x5        // Position of BS5 field.
	GPIO_BSRR_BS5_Msk  = 0x20       // Bit mask of BS5 field.
	GPIO_BSRR_BS5      = 0x20       // Bit BS5.
	GPIO_BSRR_BS6_Pos  = 0x6        // Position of BS6 field.
	GPIO_BSRR_BS6_Msk  = 0x40       // Bit mask of BS6 field.
	GPIO_BSRR_BS6      = 0x40       // Bit BS6.
	GPIO_BSRR_BS7_Pos  = 0x7        // Position of BS7 field.
	GPIO_BSRR_BS7_Msk  = 0x80       // Bit mask of BS7 field.
	GPIO_BSRR_BS7      = 0x80       // Bit BS7.
	GPIO_BSRR_BS8_Pos  = 0x8        // Position of BS8 field.
	GPIO_BSRR_BS8_Msk  = 0x100      // Bit mask of BS8 field.
	GPIO_BSRR_BS8      = 0x100      // Bit BS8.
	GPIO_BSRR_BS9_Pos  = 0x9        // Position of BS9 field.
	GPIO_BSRR_BS9_Msk  = 0x200      // Bit mask of BS9 field.
	GPIO_BSRR_BS9      = 0x200      // Bit BS9.
	GPIO_BSRR_BS10_Pos = 0xa        // Position of BS10 field.
	GPIO_BSRR_BS10_Msk = 0x400      // Bit mask of BS10 field.
	GPIO_BSRR_BS10     = 0x400      // Bit BS10.
	GPIO_BSRR_BS11_Pos = 0xb        // Position of BS11 field.
	GPIO_BSRR_BS11_Msk = 0x800      // Bit mask of BS11 field.
	GPIO_BSRR_BS11     = 0x800      // Bit BS11.
	GPIO_BSRR_BS12_Pos = 0xc        // Position of BS12 field.
	GPIO_BSRR_BS12_Msk = 0x1000     // Bit mask of BS12 field.
	GPIO_BSRR_BS12     = 0x1000     // Bit BS12.
	GPIO_BSRR_BS13_Pos = 0xd        // Position of BS13 field.
	GPIO_BSRR_BS13_Msk = 0x2000     // Bit mask of BS13 field.
	GPIO_BSRR_BS13     = 0x2000     // Bit BS13.
	GPIO_BSRR_BS14_Pos = 0xe        // Position of BS14 field.
	GPIO_BSRR_BS14_Msk = 0x4000     // Bit mask of BS14 field.
	GPIO_BSRR_BS14     = 0x4000     // Bit BS14.
	GPIO_BSRR_BS15_Pos = 0xf        // Position of BS15 field.
	GPIO_BSRR_BS15_Msk = 0x8000     // Bit mask of BS15 field.
	GPIO_BSRR_BS15     = 0x8000     // Bit BS15.
	GPIO_BSRR_BR0_Pos  = 0x10       // Position of BR0 field.
	GPIO_BSRR_BR0_Msk  = 0x10000    // Bit mask of BR0 field.
	GPIO_BSRR_BR0      = 0x10000    // Bit BR0.
	GPIO_BSRR_BR1_Pos  = 0x11       // Position of BR1 field.
	GPIO_BSRR_BR1_Msk  = 0x20000    // Bit mask of BR1 field.
	GPIO_BSRR_BR1      = 0x20000    // Bit BR1.
	GPIO_BSRR_BR2_Pos  = 0x12       // Position of BR2 field.
	GPIO_BSRR_BR2_Msk  = 0x40000    // Bit mask of BR2 field.
	GPIO_BSRR_BR2      = 0x40000    // Bit BR2.
	GPIO_BSRR_BR3_Pos  = 0x13       // Position of BR3 field.
	GPIO_BSRR_BR3_Msk  = 0x80000    // Bit mask of BR3 field.
	GPIO_BSRR_BR3      = 0x80000    // Bit BR3.
	GPIO_BSRR_BR4_Pos  = 0x14       // Position of BR4 field.
	GPIO_BSRR_BR4_Msk  = 0x100000   // Bit mask of BR4 field.
	GPIO_BSRR_BR4      = 0x100000   // Bit BR4.
	GPIO_BSRR_BR5_Pos  = 0x15       // Position of BR5 field.
	GPIO_BSRR_BR5_Msk  = 0x200000   // Bit mask of BR5 field.
	GPIO_BSRR_BR5      = 0x200000   // Bit BR5.
	GPIO_BSRR_BR6_Pos  = 0x16       // Position of BR6 field.
	GPIO_BSRR_BR6_Msk  = 0x400000   // Bit mask of BR6 field.
	GPIO_BSRR_BR6      = 0x400000   // Bit BR6.
	GPIO_BSRR_BR7_Pos  = 0x17       // Position of BR7 field.
	GPIO_BSRR_BR7_Msk  = 0x800000   // Bit mask of BR7 field.
	GPIO_BSRR_BR7      = 0x800000   // Bit BR7.
	GPIO_BSRR_BR8_Pos  = 0x18       // Position of BR8 field.
	GPIO_BSRR_BR8_Msk  = 0x1000000  // Bit mask of BR8 field.
	GPIO_BSRR_BR8      = 0x1000000  // Bit BR8.
	GPIO_BSRR_BR9_Pos  = 0x19       // Position of BR9 field.
	GPIO_BSRR_BR9_Msk  = 0x2000000  // Bit mask of BR9 field.
	GPIO_BSRR_BR9      = 0x2000000  // Bit BR9.
	GPIO_BSRR_BR10_Pos = 0x1a       // Position of BR10 field.
	GPIO_BSRR_BR10_Msk = 0x4000000  // Bit mask of BR10 field.
	GPIO_BSRR_BR10     = 0x4000000  // Bit BR10.
	GPIO_BSRR_BR11_Pos = 0x1b       // Position of BR11 field.
	GPIO_BSRR_BR11_Msk = 0x8000000  // Bit mask of BR11 field.
	GPIO_BSRR_BR11     = 0x8000000  // Bit BR11.
	GPIO_BSRR_BR12_Pos = 0x1c       // Position of BR12 field.
	GPIO_BSRR_BR12_Msk = 0x10000000 // Bit mask of BR12 field.
	GPIO_BSRR_BR12     = 0x10000000 // Bit BR12.
	GPIO_BSRR_BR13_Pos = 0x1d       // Position of BR13 field.
	GPIO_BSRR_BR13_Msk = 0x20000000 // Bit mask of BR13 field.
	GPIO_BSRR_BR13     = 0x20000000 // Bit BR13.
	GPIO_BSRR_BR14_Pos = 0x1e       // Position of BR14 field.
	GPIO_BSRR_BR14_Msk = 0x40000000 // Bit mask of BR14 field.
	GPIO_BSRR_BR14     = 0x40000000 // Bit BR14.
	GPIO_BSRR_BR15_Pos = 0x1f       // Position of BR15 field.
	GPIO_BSRR_BR15_Msk = 0x80000000 // Bit mask of BR15 field.
	GPIO_BSRR_BR15     = 0x80000000 // Bit BR15.

	// LCKR: This register is used to lock the           configuration of the port bits when a correct write           sequence is applied to bit 16 (LCKK). The value of bits           [15:0] is used to lock the configuration of the GPIO.           During the write sequence, the value of LCKR[15:0] must           not change. When the LOCK sequence has been applied on a           port bit, the value of this port bit can no longer be           modified until the next MCU reset or peripheral reset.A           specific write sequence is used to write to the           GPIOx_LCKR register. Only word access (32-bit long) is           allowed during this locking sequence.Each lock bit           freezes a specific configuration register (control and           alternate function registers).
	GPIO_LCKR_LCK0_Pos  = 0x0     // Position of LCK0 field.
	GPIO_LCKR_LCK0_Msk  = 0x1     // Bit mask of LCK0 field.
	GPIO_LCKR_LCK0      = 0x1     // Bit LCK0.
	GPIO_LCKR_LCK1_Pos  = 0x1     // Position of LCK1 field.
	GPIO_LCKR_LCK1_Msk  = 0x2     // Bit mask of LCK1 field.
	GPIO_LCKR_LCK1      = 0x2     // Bit LCK1.
	GPIO_LCKR_LCK2_Pos  = 0x2     // Position of LCK2 field.
	GPIO_LCKR_LCK2_Msk  = 0x4     // Bit mask of LCK2 field.
	GPIO_LCKR_LCK2      = 0x4     // Bit LCK2.
	GPIO_LCKR_LCK3_Pos  = 0x3     // Position of LCK3 field.
	GPIO_LCKR_LCK3_Msk  = 0x8     // Bit mask of LCK3 field.
	GPIO_LCKR_LCK3      = 0x8     // Bit LCK3.
	GPIO_LCKR_LCK4_Pos  = 0x4     // Position of LCK4 field.
	GPIO_LCKR_LCK4_Msk  = 0x10    // Bit mask of LCK4 field.
	GPIO_LCKR_LCK4      = 0x10    // Bit LCK4.
	GPIO_LCKR_LCK5_Pos  = 0x5     // Position of LCK5 field.
	GPIO_LCKR_LCK5_Msk  = 0x20    // Bit mask of LCK5 field.
	GPIO_LCKR_LCK5      = 0x20    // Bit LCK5.
	GPIO_LCKR_LCK6_Pos  = 0x6     // Position of LCK6 field.
	GPIO_LCKR_LCK6_Msk  = 0x40    // Bit mask of LCK6 field.
	GPIO_LCKR_LCK6      = 0x40    // Bit LCK6.
	GPIO_LCKR_LCK7_Pos  = 0x7     // Position of LCK7 field.
	GPIO_LCKR_LCK7_Msk  = 0x80    // Bit mask of LCK7 field.
	GPIO_LCKR_LCK7      = 0x80    // Bit LCK7.
	GPIO_LCKR_LCK8_Pos  = 0x8     // Position of LCK8 field.
	GPIO_LCKR_LCK8_Msk  = 0x100   // Bit mask of LCK8 field.
	GPIO_LCKR_LCK8      = 0x100   // Bit LCK8.
	GPIO_LCKR_LCK9_Pos  = 0x9     // Position of LCK9 field.
	GPIO_LCKR_LCK9_Msk  = 0x200   // Bit mask of LCK9 field.
	GPIO_LCKR_LCK9      = 0x200   // Bit LCK9.
	GPIO_LCKR_LCK10_Pos = 0xa     // Position of LCK10 field.
	GPIO_LCKR_LCK10_Msk = 0x400   // Bit mask of LCK10 field.
	GPIO_LCKR_LCK10     = 0x400   // Bit LCK10.
	GPIO_LCKR_LCK11_Pos = 0xb     // Position of LCK11 field.
	GPIO_LCKR_LCK11_Msk = 0x800   // Bit mask of LCK11 field.
	GPIO_LCKR_LCK11     = 0x800   // Bit LCK11.
	GPIO_LCKR_LCK12_Pos = 0xc     // Position of LCK12 field.
	GPIO_LCKR_LCK12_Msk = 0x1000  // Bit mask of LCK12 field.
	GPIO_LCKR_LCK12     = 0x1000  // Bit LCK12.
	GPIO_LCKR_LCK13_Pos = 0xd     // Position of LCK13 field.
	GPIO_LCKR_LCK13_Msk = 0x2000  // Bit mask of LCK13 field.
	GPIO_LCKR_LCK13     = 0x2000  // Bit LCK13.
	GPIO_LCKR_LCK14_Pos = 0xe     // Position of LCK14 field.
	GPIO_LCKR_LCK14_Msk = 0x4000  // Bit mask of LCK14 field.
	GPIO_LCKR_LCK14     = 0x4000  // Bit LCK14.
	GPIO_LCKR_LCK15_Pos = 0xf     // Position of LCK15 field.
	GPIO_LCKR_LCK15_Msk = 0x8000  // Bit mask of LCK15 field.
	GPIO_LCKR_LCK15     = 0x8000  // Bit LCK15.
	GPIO_LCKR_LCKK_Pos  = 0x10    // Position of LCKK field.
	GPIO_LCKR_LCKK_Msk  = 0x10000 // Bit mask of LCKK field.
	GPIO_LCKR_LCKK      = 0x10000 // Bit LCKK.

	// AFRL: GPIO alternate function low           register
	GPIO_AFRL_AFSEL0_Pos = 0x0        // Position of AFSEL0 field.
	GPIO_AFRL_AFSEL0_Msk = 0xf        // Bit mask of AFSEL0 field.
	GPIO_AFRL_AFSEL1_Pos = 0x4        // Position of AFSEL1 field.
	GPIO_AFRL_AFSEL1_Msk = 0xf0       // Bit mask of AFSEL1 field.
	GPIO_AFRL_AFSEL2_Pos = 0x8        // Position of AFSEL2 field.
	GPIO_AFRL_AFSEL2_Msk = 0xf00      // Bit mask of AFSEL2 field.
	GPIO_AFRL_AFSEL3_Pos = 0xc        // Position of AFSEL3 field.
	GPIO_AFRL_AFSEL3_Msk = 0xf000     // Bit mask of AFSEL3 field.
	GPIO_AFRL_AFSEL4_Pos = 0x10       // Position of AFSEL4 field.
	GPIO_AFRL_AFSEL4_Msk = 0xf0000    // Bit mask of AFSEL4 field.
	GPIO_AFRL_AFSEL5_Pos = 0x14       // Position of AFSEL5 field.
	GPIO_AFRL_AFSEL5_Msk = 0xf00000   // Bit mask of AFSEL5 field.
	GPIO_AFRL_AFSEL6_Pos = 0x18       // Position of AFSEL6 field.
	GPIO_AFRL_AFSEL6_Msk = 0xf000000  // Bit mask of AFSEL6 field.
	GPIO_AFRL_AFSEL7_Pos = 0x1c       // Position of AFSEL7 field.
	GPIO_AFRL_AFSEL7_Msk = 0xf0000000 // Bit mask of AFSEL7 field.

	// AFRH: GPIO alternate function high           register
	GPIO_AFRH_AFSEL8_Pos  = 0x0        // Position of AFSEL8 field.
	GPIO_AFRH_AFSEL8_Msk  = 0xf        // Bit mask of AFSEL8 field.
	GPIO_AFRH_AFSEL9_Pos  = 0x4        // Position of AFSEL9 field.
	GPIO_AFRH_AFSEL9_Msk  = 0xf0       // Bit mask of AFSEL9 field.
	GPIO_AFRH_AFSEL10_Pos = 0x8        // Position of AFSEL10 field.
	GPIO_AFRH_AFSEL10_Msk = 0xf00      // Bit mask of AFSEL10 field.
	GPIO_AFRH_AFSEL11_Pos = 0xc        // Position of AFSEL11 field.
	GPIO_AFRH_AFSEL11_Msk = 0xf000     // Bit mask of AFSEL11 field.
	GPIO_AFRH_AFSEL12_Pos = 0x10       // Position of AFSEL12 field.
	GPIO_AFRH_AFSEL12_Msk = 0xf0000    // Bit mask of AFSEL12 field.
	GPIO_AFRH_AFSEL13_Pos = 0x14       // Position of AFSEL13 field.
	GPIO_AFRH_AFSEL13_Msk = 0xf00000   // Bit mask of AFSEL13 field.
	GPIO_AFRH_AFSEL14_Pos = 0x18       // Position of AFSEL14 field.
	GPIO_AFRH_AFSEL14_Msk = 0xf000000  // Bit mask of AFSEL14 field.
	GPIO_AFRH_AFSEL15_Pos = 0x1c       // Position of AFSEL15 field.
	GPIO_AFRH_AFSEL15_Msk = 0xf0000000 // Bit mask of AFSEL15 field.
)

// Bitfields for JPEG: JPEG
const (
	// CONFR0: JPEG codec control register
	JPEG_CONFR0_START_Pos = 0x0 // Position of START field.
	JPEG_CONFR0_START_Msk = 0x1 // Bit mask of START field.
	JPEG_CONFR0_START     = 0x1 // Bit START.

	// CONFR1: JPEG codec configuration register           1
	JPEG_CONFR1_NF_Pos         = 0x0        // Position of NF field.
	JPEG_CONFR1_NF_Msk         = 0x3        // Bit mask of NF field.
	JPEG_CONFR1_DE_Pos         = 0x3        // Position of DE field.
	JPEG_CONFR1_DE_Msk         = 0x8        // Bit mask of DE field.
	JPEG_CONFR1_DE             = 0x8        // Bit DE.
	JPEG_CONFR1_COLORSPACE_Pos = 0x4        // Position of COLORSPACE field.
	JPEG_CONFR1_COLORSPACE_Msk = 0x30       // Bit mask of COLORSPACE field.
	JPEG_CONFR1_NS_Pos         = 0x6        // Position of NS field.
	JPEG_CONFR1_NS_Msk         = 0xc0       // Bit mask of NS field.
	JPEG_CONFR1_HDR_Pos        = 0x8        // Position of HDR field.
	JPEG_CONFR1_HDR_Msk        = 0x100      // Bit mask of HDR field.
	JPEG_CONFR1_HDR            = 0x100      // Bit HDR.
	JPEG_CONFR1_YSIZE_Pos      = 0x10       // Position of YSIZE field.
	JPEG_CONFR1_YSIZE_Msk      = 0xffff0000 // Bit mask of YSIZE field.

	// CONFR2: JPEG codec configuration register           2
	JPEG_CONFR2_NMCU_Pos = 0x0       // Position of NMCU field.
	JPEG_CONFR2_NMCU_Msk = 0x3ffffff // Bit mask of NMCU field.

	// CONFR3: JPEG codec configuration register           3
	JPEG_CONFR3_XSIZE_Pos = 0x10       // Position of XSIZE field.
	JPEG_CONFR3_XSIZE_Msk = 0xffff0000 // Bit mask of XSIZE field.

	// CONFRN1: JPEG codec configuration register           4-7
	JPEG_CONFRN1_HD_Pos  = 0x0    // Position of HD field.
	JPEG_CONFRN1_HD_Msk  = 0x1    // Bit mask of HD field.
	JPEG_CONFRN1_HD      = 0x1    // Bit HD.
	JPEG_CONFRN1_HA_Pos  = 0x1    // Position of HA field.
	JPEG_CONFRN1_HA_Msk  = 0x2    // Bit mask of HA field.
	JPEG_CONFRN1_HA      = 0x2    // Bit HA.
	JPEG_CONFRN1_QT_Pos  = 0x2    // Position of QT field.
	JPEG_CONFRN1_QT_Msk  = 0xc    // Bit mask of QT field.
	JPEG_CONFRN1_NB_Pos  = 0x4    // Position of NB field.
	JPEG_CONFRN1_NB_Msk  = 0xf0   // Bit mask of NB field.
	JPEG_CONFRN1_VSF_Pos = 0x8    // Position of VSF field.
	JPEG_CONFRN1_VSF_Msk = 0xf00  // Bit mask of VSF field.
	JPEG_CONFRN1_HSF_Pos = 0xc    // Position of HSF field.
	JPEG_CONFRN1_HSF_Msk = 0xf000 // Bit mask of HSF field.

	// CONFRN2: JPEG codec configuration register           4-7
	JPEG_CONFRN2_HD_Pos  = 0x0    // Position of HD field.
	JPEG_CONFRN2_HD_Msk  = 0x1    // Bit mask of HD field.
	JPEG_CONFRN2_HD      = 0x1    // Bit HD.
	JPEG_CONFRN2_HA_Pos  = 0x1    // Position of HA field.
	JPEG_CONFRN2_HA_Msk  = 0x2    // Bit mask of HA field.
	JPEG_CONFRN2_HA      = 0x2    // Bit HA.
	JPEG_CONFRN2_QT_Pos  = 0x2    // Position of QT field.
	JPEG_CONFRN2_QT_Msk  = 0xc    // Bit mask of QT field.
	JPEG_CONFRN2_NB_Pos  = 0x4    // Position of NB field.
	JPEG_CONFRN2_NB_Msk  = 0xf0   // Bit mask of NB field.
	JPEG_CONFRN2_VSF_Pos = 0x8    // Position of VSF field.
	JPEG_CONFRN2_VSF_Msk = 0xf00  // Bit mask of VSF field.
	JPEG_CONFRN2_HSF_Pos = 0xc    // Position of HSF field.
	JPEG_CONFRN2_HSF_Msk = 0xf000 // Bit mask of HSF field.

	// CONFRN3: JPEG codec configuration register           4-7
	JPEG_CONFRN3_HD_Pos  = 0x0    // Position of HD field.
	JPEG_CONFRN3_HD_Msk  = 0x1    // Bit mask of HD field.
	JPEG_CONFRN3_HD      = 0x1    // Bit HD.
	JPEG_CONFRN3_HA_Pos  = 0x1    // Position of HA field.
	JPEG_CONFRN3_HA_Msk  = 0x2    // Bit mask of HA field.
	JPEG_CONFRN3_HA      = 0x2    // Bit HA.
	JPEG_CONFRN3_QT_Pos  = 0x2    // Position of QT field.
	JPEG_CONFRN3_QT_Msk  = 0xc    // Bit mask of QT field.
	JPEG_CONFRN3_NB_Pos  = 0x4    // Position of NB field.
	JPEG_CONFRN3_NB_Msk  = 0xf0   // Bit mask of NB field.
	JPEG_CONFRN3_VSF_Pos = 0x8    // Position of VSF field.
	JPEG_CONFRN3_VSF_Msk = 0xf00  // Bit mask of VSF field.
	JPEG_CONFRN3_HSF_Pos = 0xc    // Position of HSF field.
	JPEG_CONFRN3_HSF_Msk = 0xf000 // Bit mask of HSF field.

	// CONFRN4: JPEG codec configuration register           4-7
	JPEG_CONFRN4_HD_Pos  = 0x0    // Position of HD field.
	JPEG_CONFRN4_HD_Msk  = 0x1    // Bit mask of HD field.
	JPEG_CONFRN4_HD      = 0x1    // Bit HD.
	JPEG_CONFRN4_HA_Pos  = 0x1    // Position of HA field.
	JPEG_CONFRN4_HA_Msk  = 0x2    // Bit mask of HA field.
	JPEG_CONFRN4_HA      = 0x2    // Bit HA.
	JPEG_CONFRN4_QT_Pos  = 0x2    // Position of QT field.
	JPEG_CONFRN4_QT_Msk  = 0xc    // Bit mask of QT field.
	JPEG_CONFRN4_NB_Pos  = 0x4    // Position of NB field.
	JPEG_CONFRN4_NB_Msk  = 0xf0   // Bit mask of NB field.
	JPEG_CONFRN4_VSF_Pos = 0x8    // Position of VSF field.
	JPEG_CONFRN4_VSF_Msk = 0xf00  // Bit mask of VSF field.
	JPEG_CONFRN4_HSF_Pos = 0xc    // Position of HSF field.
	JPEG_CONFRN4_HSF_Msk = 0xf000 // Bit mask of HSF field.

	// CR: JPEG control register
	JPEG_CR_JCEN_Pos   = 0x0    // Position of JCEN field.
	JPEG_CR_JCEN_Msk   = 0x1    // Bit mask of JCEN field.
	JPEG_CR_JCEN       = 0x1    // Bit JCEN.
	JPEG_CR_IFTIE_Pos  = 0x1    // Position of IFTIE field.
	JPEG_CR_IFTIE_Msk  = 0x2    // Bit mask of IFTIE field.
	JPEG_CR_IFTIE      = 0x2    // Bit IFTIE.
	JPEG_CR_IFNFIE_Pos = 0x2    // Position of IFNFIE field.
	JPEG_CR_IFNFIE_Msk = 0x4    // Bit mask of IFNFIE field.
	JPEG_CR_IFNFIE     = 0x4    // Bit IFNFIE.
	JPEG_CR_OFTIE_Pos  = 0x3    // Position of OFTIE field.
	JPEG_CR_OFTIE_Msk  = 0x8    // Bit mask of OFTIE field.
	JPEG_CR_OFTIE      = 0x8    // Bit OFTIE.
	JPEG_CR_OFNEIE_Pos = 0x4    // Position of OFNEIE field.
	JPEG_CR_OFNEIE_Msk = 0x10   // Bit mask of OFNEIE field.
	JPEG_CR_OFNEIE     = 0x10   // Bit OFNEIE.
	JPEG_CR_EOCIE_Pos  = 0x5    // Position of EOCIE field.
	JPEG_CR_EOCIE_Msk  = 0x20   // Bit mask of EOCIE field.
	JPEG_CR_EOCIE      = 0x20   // Bit EOCIE.
	JPEG_CR_HPDIE_Pos  = 0x6    // Position of HPDIE field.
	JPEG_CR_HPDIE_Msk  = 0x40   // Bit mask of HPDIE field.
	JPEG_CR_HPDIE      = 0x40   // Bit HPDIE.
	JPEG_CR_IDMAEN_Pos = 0xb    // Position of IDMAEN field.
	JPEG_CR_IDMAEN_Msk = 0x800  // Bit mask of IDMAEN field.
	JPEG_CR_IDMAEN     = 0x800  // Bit IDMAEN.
	JPEG_CR_ODMAEN_Pos = 0xc    // Position of ODMAEN field.
	JPEG_CR_ODMAEN_Msk = 0x1000 // Bit mask of ODMAEN field.
	JPEG_CR_ODMAEN     = 0x1000 // Bit ODMAEN.
	JPEG_CR_IFF_Pos    = 0xd    // Position of IFF field.
	JPEG_CR_IFF_Msk    = 0x2000 // Bit mask of IFF field.
	JPEG_CR_IFF        = 0x2000 // Bit IFF.
	JPEG_CR_OFF_Pos    = 0xe    // Position of OFF field.
	JPEG_CR_OFF_Msk    = 0x4000 // Bit mask of OFF field.
	JPEG_CR_OFF        = 0x4000 // Bit OFF.

	// SR: JPEG status register
	JPEG_SR_IFTF_Pos  = 0x1  // Position of IFTF field.
	JPEG_SR_IFTF_Msk  = 0x2  // Bit mask of IFTF field.
	JPEG_SR_IFTF      = 0x2  // Bit IFTF.
	JPEG_SR_IFNFF_Pos = 0x2  // Position of IFNFF field.
	JPEG_SR_IFNFF_Msk = 0x4  // Bit mask of IFNFF field.
	JPEG_SR_IFNFF     = 0x4  // Bit IFNFF.
	JPEG_SR_OFTF_Pos  = 0x3  // Position of OFTF field.
	JPEG_SR_OFTF_Msk  = 0x8  // Bit mask of OFTF field.
	JPEG_SR_OFTF      = 0x8  // Bit OFTF.
	JPEG_SR_OFNEF_Pos = 0x4  // Position of OFNEF field.
	JPEG_SR_OFNEF_Msk = 0x10 // Bit mask of OFNEF field.
	JPEG_SR_OFNEF     = 0x10 // Bit OFNEF.
	JPEG_SR_EOCF_Pos  = 0x5  // Position of EOCF field.
	JPEG_SR_EOCF_Msk  = 0x20 // Bit mask of EOCF field.
	JPEG_SR_EOCF      = 0x20 // Bit EOCF.
	JPEG_SR_HPDF_Pos  = 0x6  // Position of HPDF field.
	JPEG_SR_HPDF_Msk  = 0x40 // Bit mask of HPDF field.
	JPEG_SR_HPDF      = 0x40 // Bit HPDF.
	JPEG_SR_COF_Pos   = 0x7  // Position of COF field.
	JPEG_SR_COF_Msk   = 0x80 // Bit mask of COF field.
	JPEG_SR_COF       = 0x80 // Bit COF.

	// CFR: JPEG clear flag register
	JPEG_CFR_CEOCF_Pos = 0x5  // Position of CEOCF field.
	JPEG_CFR_CEOCF_Msk = 0x20 // Bit mask of CEOCF field.
	JPEG_CFR_CEOCF     = 0x20 // Bit CEOCF.
	JPEG_CFR_CHPDF_Pos = 0x6  // Position of CHPDF field.
	JPEG_CFR_CHPDF_Msk = 0x40 // Bit mask of CHPDF field.
	JPEG_CFR_CHPDF     = 0x40 // Bit CHPDF.

	// DIR: JPEG data input register
	JPEG_DIR_DATAIN_Pos = 0x0        // Position of DATAIN field.
	JPEG_DIR_DATAIN_Msk = 0xffffffff // Bit mask of DATAIN field.

	// DOR: JPEG data output register
	JPEG_DOR_DATAOUT_Pos = 0x0        // Position of DATAOUT field.
	JPEG_DOR_DATAOUT_Msk = 0xffffffff // Bit mask of DATAOUT field.
)

// Bitfields for MDMA: MDMA
const (
	// MDMA_GISR0: MDMA Global Interrupt/Status           Register
	MDMA_MDMA_GISR0_GIF0_Pos  = 0x0    // Position of GIF0 field.
	MDMA_MDMA_GISR0_GIF0_Msk  = 0x1    // Bit mask of GIF0 field.
	MDMA_MDMA_GISR0_GIF0      = 0x1    // Bit GIF0.
	MDMA_MDMA_GISR0_GIF1_Pos  = 0x1    // Position of GIF1 field.
	MDMA_MDMA_GISR0_GIF1_Msk  = 0x2    // Bit mask of GIF1 field.
	MDMA_MDMA_GISR0_GIF1      = 0x2    // Bit GIF1.
	MDMA_MDMA_GISR0_GIF2_Pos  = 0x2    // Position of GIF2 field.
	MDMA_MDMA_GISR0_GIF2_Msk  = 0x4    // Bit mask of GIF2 field.
	MDMA_MDMA_GISR0_GIF2      = 0x4    // Bit GIF2.
	MDMA_MDMA_GISR0_GIF3_Pos  = 0x3    // Position of GIF3 field.
	MDMA_MDMA_GISR0_GIF3_Msk  = 0x8    // Bit mask of GIF3 field.
	MDMA_MDMA_GISR0_GIF3      = 0x8    // Bit GIF3.
	MDMA_MDMA_GISR0_GIF4_Pos  = 0x4    // Position of GIF4 field.
	MDMA_MDMA_GISR0_GIF4_Msk  = 0x10   // Bit mask of GIF4 field.
	MDMA_MDMA_GISR0_GIF4      = 0x10   // Bit GIF4.
	MDMA_MDMA_GISR0_GIF5_Pos  = 0x5    // Position of GIF5 field.
	MDMA_MDMA_GISR0_GIF5_Msk  = 0x20   // Bit mask of GIF5 field.
	MDMA_MDMA_GISR0_GIF5      = 0x20   // Bit GIF5.
	MDMA_MDMA_GISR0_GIF6_Pos  = 0x6    // Position of GIF6 field.
	MDMA_MDMA_GISR0_GIF6_Msk  = 0x40   // Bit mask of GIF6 field.
	MDMA_MDMA_GISR0_GIF6      = 0x40   // Bit GIF6.
	MDMA_MDMA_GISR0_GIF7_Pos  = 0x7    // Position of GIF7 field.
	MDMA_MDMA_GISR0_GIF7_Msk  = 0x80   // Bit mask of GIF7 field.
	MDMA_MDMA_GISR0_GIF7      = 0x80   // Bit GIF7.
	MDMA_MDMA_GISR0_GIF8_Pos  = 0x8    // Position of GIF8 field.
	MDMA_MDMA_GISR0_GIF8_Msk  = 0x100  // Bit mask of GIF8 field.
	MDMA_MDMA_GISR0_GIF8      = 0x100  // Bit GIF8.
	MDMA_MDMA_GISR0_GIF9_Pos  = 0x9    // Position of GIF9 field.
	MDMA_MDMA_GISR0_GIF9_Msk  = 0x200  // Bit mask of GIF9 field.
	MDMA_MDMA_GISR0_GIF9      = 0x200  // Bit GIF9.
	MDMA_MDMA_GISR0_GIF10_Pos = 0xa    // Position of GIF10 field.
	MDMA_MDMA_GISR0_GIF10_Msk = 0x400  // Bit mask of GIF10 field.
	MDMA_MDMA_GISR0_GIF10     = 0x400  // Bit GIF10.
	MDMA_MDMA_GISR0_GIF11_Pos = 0xb    // Position of GIF11 field.
	MDMA_MDMA_GISR0_GIF11_Msk = 0x800  // Bit mask of GIF11 field.
	MDMA_MDMA_GISR0_GIF11     = 0x800  // Bit GIF11.
	MDMA_MDMA_GISR0_GIF12_Pos = 0xc    // Position of GIF12 field.
	MDMA_MDMA_GISR0_GIF12_Msk = 0x1000 // Bit mask of GIF12 field.
	MDMA_MDMA_GISR0_GIF12     = 0x1000 // Bit GIF12.
	MDMA_MDMA_GISR0_GIF13_Pos = 0xd    // Position of GIF13 field.
	MDMA_MDMA_GISR0_GIF13_Msk = 0x2000 // Bit mask of GIF13 field.
	MDMA_MDMA_GISR0_GIF13     = 0x2000 // Bit GIF13.
	MDMA_MDMA_GISR0_GIF14_Pos = 0xe    // Position of GIF14 field.
	MDMA_MDMA_GISR0_GIF14_Msk = 0x4000 // Bit mask of GIF14 field.
	MDMA_MDMA_GISR0_GIF14     = 0x4000 // Bit GIF14.
	MDMA_MDMA_GISR0_GIF15_Pos = 0xf    // Position of GIF15 field.
	MDMA_MDMA_GISR0_GIF15_Msk = 0x8000 // Bit mask of GIF15 field.
	MDMA_MDMA_GISR0_GIF15     = 0x8000 // Bit GIF15.

	// MDMA_C0ISR: MDMA channel x interrupt/status           register
	MDMA_MDMA_C0ISR_TEIF0_Pos  = 0x0     // Position of TEIF0 field.
	MDMA_MDMA_C0ISR_TEIF0_Msk  = 0x1     // Bit mask of TEIF0 field.
	MDMA_MDMA_C0ISR_TEIF0      = 0x1     // Bit TEIF0.
	MDMA_MDMA_C0ISR_CTCIF0_Pos = 0x1     // Position of CTCIF0 field.
	MDMA_MDMA_C0ISR_CTCIF0_Msk = 0x2     // Bit mask of CTCIF0 field.
	MDMA_MDMA_C0ISR_CTCIF0     = 0x2     // Bit CTCIF0.
	MDMA_MDMA_C0ISR_BRTIF0_Pos = 0x2     // Position of BRTIF0 field.
	MDMA_MDMA_C0ISR_BRTIF0_Msk = 0x4     // Bit mask of BRTIF0 field.
	MDMA_MDMA_C0ISR_BRTIF0     = 0x4     // Bit BRTIF0.
	MDMA_MDMA_C0ISR_BTIF0_Pos  = 0x3     // Position of BTIF0 field.
	MDMA_MDMA_C0ISR_BTIF0_Msk  = 0x8     // Bit mask of BTIF0 field.
	MDMA_MDMA_C0ISR_BTIF0      = 0x8     // Bit BTIF0.
	MDMA_MDMA_C0ISR_TCIF0_Pos  = 0x4     // Position of TCIF0 field.
	MDMA_MDMA_C0ISR_TCIF0_Msk  = 0x10    // Bit mask of TCIF0 field.
	MDMA_MDMA_C0ISR_TCIF0      = 0x10    // Bit TCIF0.
	MDMA_MDMA_C0ISR_CRQA0_Pos  = 0x10    // Position of CRQA0 field.
	MDMA_MDMA_C0ISR_CRQA0_Msk  = 0x10000 // Bit mask of CRQA0 field.
	MDMA_MDMA_C0ISR_CRQA0      = 0x10000 // Bit CRQA0.

	// MDMA_C0IFCR: MDMA channel x interrupt flag clear           register
	MDMA_MDMA_C0IFCR_CTEIF0_Pos  = 0x0  // Position of CTEIF0 field.
	MDMA_MDMA_C0IFCR_CTEIF0_Msk  = 0x1  // Bit mask of CTEIF0 field.
	MDMA_MDMA_C0IFCR_CTEIF0      = 0x1  // Bit CTEIF0.
	MDMA_MDMA_C0IFCR_CCTCIF0_Pos = 0x1  // Position of CCTCIF0 field.
	MDMA_MDMA_C0IFCR_CCTCIF0_Msk = 0x2  // Bit mask of CCTCIF0 field.
	MDMA_MDMA_C0IFCR_CCTCIF0     = 0x2  // Bit CCTCIF0.
	MDMA_MDMA_C0IFCR_CBRTIF0_Pos = 0x2  // Position of CBRTIF0 field.
	MDMA_MDMA_C0IFCR_CBRTIF0_Msk = 0x4  // Bit mask of CBRTIF0 field.
	MDMA_MDMA_C0IFCR_CBRTIF0     = 0x4  // Bit CBRTIF0.
	MDMA_MDMA_C0IFCR_CBTIF0_Pos  = 0x3  // Position of CBTIF0 field.
	MDMA_MDMA_C0IFCR_CBTIF0_Msk  = 0x8  // Bit mask of CBTIF0 field.
	MDMA_MDMA_C0IFCR_CBTIF0      = 0x8  // Bit CBTIF0.
	MDMA_MDMA_C0IFCR_CLTCIF0_Pos = 0x4  // Position of CLTCIF0 field.
	MDMA_MDMA_C0IFCR_CLTCIF0_Msk = 0x10 // Bit mask of CLTCIF0 field.
	MDMA_MDMA_C0IFCR_CLTCIF0     = 0x10 // Bit CLTCIF0.

	// MDMA_C0ESR: MDMA Channel x error status           register
	MDMA_MDMA_C0ESR_TEA_Pos  = 0x0   // Position of TEA field.
	MDMA_MDMA_C0ESR_TEA_Msk  = 0x7f  // Bit mask of TEA field.
	MDMA_MDMA_C0ESR_TED_Pos  = 0x7   // Position of TED field.
	MDMA_MDMA_C0ESR_TED_Msk  = 0x80  // Bit mask of TED field.
	MDMA_MDMA_C0ESR_TED      = 0x80  // Bit TED.
	MDMA_MDMA_C0ESR_TELD_Pos = 0x8   // Position of TELD field.
	MDMA_MDMA_C0ESR_TELD_Msk = 0x100 // Bit mask of TELD field.
	MDMA_MDMA_C0ESR_TELD     = 0x100 // Bit TELD.
	MDMA_MDMA_C0ESR_TEMD_Pos = 0x9   // Position of TEMD field.
	MDMA_MDMA_C0ESR_TEMD_Msk = 0x200 // Bit mask of TEMD field.
	MDMA_MDMA_C0ESR_TEMD     = 0x200 // Bit TEMD.
	MDMA_MDMA_C0ESR_ASE_Pos  = 0xa   // Position of ASE field.
	MDMA_MDMA_C0ESR_ASE_Msk  = 0x400 // Bit mask of ASE field.
	MDMA_MDMA_C0ESR_ASE      = 0x400 // Bit ASE.
	MDMA_MDMA_C0ESR_BSE_Pos  = 0xb   // Position of BSE field.
	MDMA_MDMA_C0ESR_BSE_Msk  = 0x800 // Bit mask of BSE field.
	MDMA_MDMA_C0ESR_BSE      = 0x800 // Bit BSE.

	// MDMA_C0CR: This register is used to control the           concerned channel.
	MDMA_MDMA_C0CR_EN_Pos    = 0x0     // Position of EN field.
	MDMA_MDMA_C0CR_EN_Msk    = 0x1     // Bit mask of EN field.
	MDMA_MDMA_C0CR_EN        = 0x1     // Bit EN.
	MDMA_MDMA_C0CR_TEIE_Pos  = 0x1     // Position of TEIE field.
	MDMA_MDMA_C0CR_TEIE_Msk  = 0x2     // Bit mask of TEIE field.
	MDMA_MDMA_C0CR_TEIE      = 0x2     // Bit TEIE.
	MDMA_MDMA_C0CR_CTCIE_Pos = 0x2     // Position of CTCIE field.
	MDMA_MDMA_C0CR_CTCIE_Msk = 0x4     // Bit mask of CTCIE field.
	MDMA_MDMA_C0CR_CTCIE     = 0x4     // Bit CTCIE.
	MDMA_MDMA_C0CR_BRTIE_Pos = 0x3     // Position of BRTIE field.
	MDMA_MDMA_C0CR_BRTIE_Msk = 0x8     // Bit mask of BRTIE field.
	MDMA_MDMA_C0CR_BRTIE     = 0x8     // Bit BRTIE.
	MDMA_MDMA_C0CR_BTIE_Pos  = 0x4     // Position of BTIE field.
	MDMA_MDMA_C0CR_BTIE_Msk  = 0x10    // Bit mask of BTIE field.
	MDMA_MDMA_C0CR_BTIE      = 0x10    // Bit BTIE.
	MDMA_MDMA_C0CR_TCIE_Pos  = 0x5     // Position of TCIE field.
	MDMA_MDMA_C0CR_TCIE_Msk  = 0x20    // Bit mask of TCIE field.
	MDMA_MDMA_C0CR_TCIE      = 0x20    // Bit TCIE.
	MDMA_MDMA_C0CR_PL_Pos    = 0x6     // Position of PL field.
	MDMA_MDMA_C0CR_PL_Msk    = 0xc0    // Bit mask of PL field.
	MDMA_MDMA_C0CR_BEX_Pos   = 0xc     // Position of BEX field.
	MDMA_MDMA_C0CR_BEX_Msk   = 0x1000  // Bit mask of BEX field.
	MDMA_MDMA_C0CR_BEX       = 0x1000  // Bit BEX.
	MDMA_MDMA_C0CR_HEX_Pos   = 0xd     // Position of HEX field.
	MDMA_MDMA_C0CR_HEX_Msk   = 0x2000  // Bit mask of HEX field.
	MDMA_MDMA_C0CR_HEX       = 0x2000  // Bit HEX.
	MDMA_MDMA_C0CR_WEX_Pos   = 0xe     // Position of WEX field.
	MDMA_MDMA_C0CR_WEX_Msk   = 0x4000  // Bit mask of WEX field.
	MDMA_MDMA_C0CR_WEX       = 0x4000  // Bit WEX.
	MDMA_MDMA_C0CR_SWRQ_Pos  = 0x10    // Position of SWRQ field.
	MDMA_MDMA_C0CR_SWRQ_Msk  = 0x10000 // Bit mask of SWRQ field.
	MDMA_MDMA_C0CR_SWRQ      = 0x10000 // Bit SWRQ.

	// MDMA_C0TCR: This register is used to configure the           concerned channel.
	MDMA_MDMA_C0TCR_SINC_Pos   = 0x0        // Position of SINC field.
	MDMA_MDMA_C0TCR_SINC_Msk   = 0x3        // Bit mask of SINC field.
	MDMA_MDMA_C0TCR_DINC_Pos   = 0x2        // Position of DINC field.
	MDMA_MDMA_C0TCR_DINC_Msk   = 0xc        // Bit mask of DINC field.
	MDMA_MDMA_C0TCR_SSIZE_Pos  = 0x4        // Position of SSIZE field.
	MDMA_MDMA_C0TCR_SSIZE_Msk  = 0x30       // Bit mask of SSIZE field.
	MDMA_MDMA_C0TCR_DSIZE_Pos  = 0x6        // Position of DSIZE field.
	MDMA_MDMA_C0TCR_DSIZE_Msk  = 0xc0       // Bit mask of DSIZE field.
	MDMA_MDMA_C0TCR_SINCOS_Pos = 0x8        // Position of SINCOS field.
	MDMA_MDMA_C0TCR_SINCOS_Msk = 0x300      // Bit mask of SINCOS field.
	MDMA_MDMA_C0TCR_DINCOS_Pos = 0xa        // Position of DINCOS field.
	MDMA_MDMA_C0TCR_DINCOS_Msk = 0xc00      // Bit mask of DINCOS field.
	MDMA_MDMA_C0TCR_SBURST_Pos = 0xc        // Position of SBURST field.
	MDMA_MDMA_C0TCR_SBURST_Msk = 0x7000     // Bit mask of SBURST field.
	MDMA_MDMA_C0TCR_DBURST_Pos = 0xf        // Position of DBURST field.
	MDMA_MDMA_C0TCR_DBURST_Msk = 0x38000    // Bit mask of DBURST field.
	MDMA_MDMA_C0TCR_TLEN_Pos   = 0x12       // Position of TLEN field.
	MDMA_MDMA_C0TCR_TLEN_Msk   = 0x1fc0000  // Bit mask of TLEN field.
	MDMA_MDMA_C0TCR_PKE_Pos    = 0x19       // Position of PKE field.
	MDMA_MDMA_C0TCR_PKE_Msk    = 0x2000000  // Bit mask of PKE field.
	MDMA_MDMA_C0TCR_PKE        = 0x2000000  // Bit PKE.
	MDMA_MDMA_C0TCR_PAM_Pos    = 0x1a       // Position of PAM field.
	MDMA_MDMA_C0TCR_PAM_Msk    = 0xc000000  // Bit mask of PAM field.
	MDMA_MDMA_C0TCR_TRGM_Pos   = 0x1c       // Position of TRGM field.
	MDMA_MDMA_C0TCR_TRGM_Msk   = 0x30000000 // Bit mask of TRGM field.
	MDMA_MDMA_C0TCR_SWRM_Pos   = 0x1e       // Position of SWRM field.
	MDMA_MDMA_C0TCR_SWRM_Msk   = 0x40000000 // Bit mask of SWRM field.
	MDMA_MDMA_C0TCR_SWRM       = 0x40000000 // Bit SWRM.
	MDMA_MDMA_C0TCR_BWM_Pos    = 0x1f       // Position of BWM field.
	MDMA_MDMA_C0TCR_BWM_Msk    = 0x80000000 // Bit mask of BWM field.
	MDMA_MDMA_C0TCR_BWM        = 0x80000000 // Bit BWM.

	// MDMA_C0BNDTR: MDMA Channel x block number of data           register
	MDMA_MDMA_C0BNDTR_BNDT_Pos  = 0x0        // Position of BNDT field.
	MDMA_MDMA_C0BNDTR_BNDT_Msk  = 0x1ffff    // Bit mask of BNDT field.
	MDMA_MDMA_C0BNDTR_BRSUM_Pos = 0x12       // Position of BRSUM field.
	MDMA_MDMA_C0BNDTR_BRSUM_Msk = 0x40000    // Bit mask of BRSUM field.
	MDMA_MDMA_C0BNDTR_BRSUM     = 0x40000    // Bit BRSUM.
	MDMA_MDMA_C0BNDTR_BRDUM_Pos = 0x13       // Position of BRDUM field.
	MDMA_MDMA_C0BNDTR_BRDUM_Msk = 0x80000    // Bit mask of BRDUM field.
	MDMA_MDMA_C0BNDTR_BRDUM     = 0x80000    // Bit BRDUM.
	MDMA_MDMA_C0BNDTR_BRC_Pos   = 0x14       // Position of BRC field.
	MDMA_MDMA_C0BNDTR_BRC_Msk   = 0xfff00000 // Bit mask of BRC field.

	// MDMA_C0SAR: MDMA channel x source address           register
	MDMA_MDMA_C0SAR_SAR_Pos = 0x0        // Position of SAR field.
	MDMA_MDMA_C0SAR_SAR_Msk = 0xffffffff // Bit mask of SAR field.

	// MDMA_C0DAR: MDMA channel x destination address           register
	MDMA_MDMA_C0DAR_DAR_Pos = 0x0        // Position of DAR field.
	MDMA_MDMA_C0DAR_DAR_Msk = 0xffffffff // Bit mask of DAR field.

	// MDMA_C0BRUR: MDMA channel x Block Repeat address Update           register
	MDMA_MDMA_C0BRUR_SUV_Pos = 0x0        // Position of SUV field.
	MDMA_MDMA_C0BRUR_SUV_Msk = 0xffff     // Bit mask of SUV field.
	MDMA_MDMA_C0BRUR_DUV_Pos = 0x10       // Position of DUV field.
	MDMA_MDMA_C0BRUR_DUV_Msk = 0xffff0000 // Bit mask of DUV field.

	// MDMA_C0LAR: MDMA channel x Link Address           register
	MDMA_MDMA_C0LAR_LAR_Pos = 0x0        // Position of LAR field.
	MDMA_MDMA_C0LAR_LAR_Msk = 0xffffffff // Bit mask of LAR field.

	// MDMA_C0TBR: MDMA channel x Trigger and Bus selection           Register
	MDMA_MDMA_C0TBR_TSEL_Pos = 0x0     // Position of TSEL field.
	MDMA_MDMA_C0TBR_TSEL_Msk = 0x3f    // Bit mask of TSEL field.
	MDMA_MDMA_C0TBR_SBUS_Pos = 0x10    // Position of SBUS field.
	MDMA_MDMA_C0TBR_SBUS_Msk = 0x10000 // Bit mask of SBUS field.
	MDMA_MDMA_C0TBR_SBUS     = 0x10000 // Bit SBUS.
	MDMA_MDMA_C0TBR_DBUS_Pos = 0x11    // Position of DBUS field.
	MDMA_MDMA_C0TBR_DBUS_Msk = 0x20000 // Bit mask of DBUS field.
	MDMA_MDMA_C0TBR_DBUS     = 0x20000 // Bit DBUS.

	// MDMA_C0MAR: MDMA channel x Mask address           register
	MDMA_MDMA_C0MAR_MAR_Pos = 0x0        // Position of MAR field.
	MDMA_MDMA_C0MAR_MAR_Msk = 0xffffffff // Bit mask of MAR field.

	// MDMA_C0MDR: MDMA channel x Mask Data           register
	MDMA_MDMA_C0MDR_MDR_Pos = 0x0        // Position of MDR field.
	MDMA_MDMA_C0MDR_MDR_Msk = 0xffffffff // Bit mask of MDR field.

	// MDMA_C1ISR: MDMA channel x interrupt/status           register
	MDMA_MDMA_C1ISR_TEIF1_Pos  = 0x0     // Position of TEIF1 field.
	MDMA_MDMA_C1ISR_TEIF1_Msk  = 0x1     // Bit mask of TEIF1 field.
	MDMA_MDMA_C1ISR_TEIF1      = 0x1     // Bit TEIF1.
	MDMA_MDMA_C1ISR_CTCIF1_Pos = 0x1     // Position of CTCIF1 field.
	MDMA_MDMA_C1ISR_CTCIF1_Msk = 0x2     // Bit mask of CTCIF1 field.
	MDMA_MDMA_C1ISR_CTCIF1     = 0x2     // Bit CTCIF1.
	MDMA_MDMA_C1ISR_BRTIF1_Pos = 0x2     // Position of BRTIF1 field.
	MDMA_MDMA_C1ISR_BRTIF1_Msk = 0x4     // Bit mask of BRTIF1 field.
	MDMA_MDMA_C1ISR_BRTIF1     = 0x4     // Bit BRTIF1.
	MDMA_MDMA_C1ISR_BTIF1_Pos  = 0x3     // Position of BTIF1 field.
	MDMA_MDMA_C1ISR_BTIF1_Msk  = 0x8     // Bit mask of BTIF1 field.
	MDMA_MDMA_C1ISR_BTIF1      = 0x8     // Bit BTIF1.
	MDMA_MDMA_C1ISR_TCIF1_Pos  = 0x4     // Position of TCIF1 field.
	MDMA_MDMA_C1ISR_TCIF1_Msk  = 0x10    // Bit mask of TCIF1 field.
	MDMA_MDMA_C1ISR_TCIF1      = 0x10    // Bit TCIF1.
	MDMA_MDMA_C1ISR_CRQA1_Pos  = 0x10    // Position of CRQA1 field.
	MDMA_MDMA_C1ISR_CRQA1_Msk  = 0x10000 // Bit mask of CRQA1 field.
	MDMA_MDMA_C1ISR_CRQA1      = 0x10000 // Bit CRQA1.

	// MDMA_C1IFCR: MDMA channel x interrupt flag clear           register
	MDMA_MDMA_C1IFCR_CTEIF1_Pos  = 0x0  // Position of CTEIF1 field.
	MDMA_MDMA_C1IFCR_CTEIF1_Msk  = 0x1  // Bit mask of CTEIF1 field.
	MDMA_MDMA_C1IFCR_CTEIF1      = 0x1  // Bit CTEIF1.
	MDMA_MDMA_C1IFCR_CCTCIF1_Pos = 0x1  // Position of CCTCIF1 field.
	MDMA_MDMA_C1IFCR_CCTCIF1_Msk = 0x2  // Bit mask of CCTCIF1 field.
	MDMA_MDMA_C1IFCR_CCTCIF1     = 0x2  // Bit CCTCIF1.
	MDMA_MDMA_C1IFCR_CBRTIF1_Pos = 0x2  // Position of CBRTIF1 field.
	MDMA_MDMA_C1IFCR_CBRTIF1_Msk = 0x4  // Bit mask of CBRTIF1 field.
	MDMA_MDMA_C1IFCR_CBRTIF1     = 0x4  // Bit CBRTIF1.
	MDMA_MDMA_C1IFCR_CBTIF1_Pos  = 0x3  // Position of CBTIF1 field.
	MDMA_MDMA_C1IFCR_CBTIF1_Msk  = 0x8  // Bit mask of CBTIF1 field.
	MDMA_MDMA_C1IFCR_CBTIF1      = 0x8  // Bit CBTIF1.
	MDMA_MDMA_C1IFCR_CLTCIF1_Pos = 0x4  // Position of CLTCIF1 field.
	MDMA_MDMA_C1IFCR_CLTCIF1_Msk = 0x10 // Bit mask of CLTCIF1 field.
	MDMA_MDMA_C1IFCR_CLTCIF1     = 0x10 // Bit CLTCIF1.

	// MDMA_C1ESR: MDMA Channel x error status           register
	MDMA_MDMA_C1ESR_TEA_Pos  = 0x0   // Position of TEA field.
	MDMA_MDMA_C1ESR_TEA_Msk  = 0x7f  // Bit mask of TEA field.
	MDMA_MDMA_C1ESR_TED_Pos  = 0x7   // Position of TED field.
	MDMA_MDMA_C1ESR_TED_Msk  = 0x80  // Bit mask of TED field.
	MDMA_MDMA_C1ESR_TED      = 0x80  // Bit TED.
	MDMA_MDMA_C1ESR_TELD_Pos = 0x8   // Position of TELD field.
	MDMA_MDMA_C1ESR_TELD_Msk = 0x100 // Bit mask of TELD field.
	MDMA_MDMA_C1ESR_TELD     = 0x100 // Bit TELD.
	MDMA_MDMA_C1ESR_TEMD_Pos = 0x9   // Position of TEMD field.
	MDMA_MDMA_C1ESR_TEMD_Msk = 0x200 // Bit mask of TEMD field.
	MDMA_MDMA_C1ESR_TEMD     = 0x200 // Bit TEMD.
	MDMA_MDMA_C1ESR_ASE_Pos  = 0xa   // Position of ASE field.
	MDMA_MDMA_C1ESR_ASE_Msk  = 0x400 // Bit mask of ASE field.
	MDMA_MDMA_C1ESR_ASE      = 0x400 // Bit ASE.
	MDMA_MDMA_C1ESR_BSE_Pos  = 0xb   // Position of BSE field.
	MDMA_MDMA_C1ESR_BSE_Msk  = 0x800 // Bit mask of BSE field.
	MDMA_MDMA_C1ESR_BSE      = 0x800 // Bit BSE.

	// MDMA_C1CR: This register is used to control the           concerned channel.
	MDMA_MDMA_C1CR_EN_Pos    = 0x0     // Position of EN field.
	MDMA_MDMA_C1CR_EN_Msk    = 0x1     // Bit mask of EN field.
	MDMA_MDMA_C1CR_EN        = 0x1     // Bit EN.
	MDMA_MDMA_C1CR_TEIE_Pos  = 0x1     // Position of TEIE field.
	MDMA_MDMA_C1CR_TEIE_Msk  = 0x2     // Bit mask of TEIE field.
	MDMA_MDMA_C1CR_TEIE      = 0x2     // Bit TEIE.
	MDMA_MDMA_C1CR_CTCIE_Pos = 0x2     // Position of CTCIE field.
	MDMA_MDMA_C1CR_CTCIE_Msk = 0x4     // Bit mask of CTCIE field.
	MDMA_MDMA_C1CR_CTCIE     = 0x4     // Bit CTCIE.
	MDMA_MDMA_C1CR_BRTIE_Pos = 0x3     // Position of BRTIE field.
	MDMA_MDMA_C1CR_BRTIE_Msk = 0x8     // Bit mask of BRTIE field.
	MDMA_MDMA_C1CR_BRTIE     = 0x8     // Bit BRTIE.
	MDMA_MDMA_C1CR_BTIE_Pos  = 0x4     // Position of BTIE field.
	MDMA_MDMA_C1CR_BTIE_Msk  = 0x10    // Bit mask of BTIE field.
	MDMA_MDMA_C1CR_BTIE      = 0x10    // Bit BTIE.
	MDMA_MDMA_C1CR_TCIE_Pos  = 0x5     // Position of TCIE field.
	MDMA_MDMA_C1CR_TCIE_Msk  = 0x20    // Bit mask of TCIE field.
	MDMA_MDMA_C1CR_TCIE      = 0x20    // Bit TCIE.
	MDMA_MDMA_C1CR_PL_Pos    = 0x6     // Position of PL field.
	MDMA_MDMA_C1CR_PL_Msk    = 0xc0    // Bit mask of PL field.
	MDMA_MDMA_C1CR_BEX_Pos   = 0xc     // Position of BEX field.
	MDMA_MDMA_C1CR_BEX_Msk   = 0x1000  // Bit mask of BEX field.
	MDMA_MDMA_C1CR_BEX       = 0x1000  // Bit BEX.
	MDMA_MDMA_C1CR_HEX_Pos   = 0xd     // Position of HEX field.
	MDMA_MDMA_C1CR_HEX_Msk   = 0x2000  // Bit mask of HEX field.
	MDMA_MDMA_C1CR_HEX       = 0x2000  // Bit HEX.
	MDMA_MDMA_C1CR_WEX_Pos   = 0xe     // Position of WEX field.
	MDMA_MDMA_C1CR_WEX_Msk   = 0x4000  // Bit mask of WEX field.
	MDMA_MDMA_C1CR_WEX       = 0x4000  // Bit WEX.
	MDMA_MDMA_C1CR_SWRQ_Pos  = 0x10    // Position of SWRQ field.
	MDMA_MDMA_C1CR_SWRQ_Msk  = 0x10000 // Bit mask of SWRQ field.
	MDMA_MDMA_C1CR_SWRQ      = 0x10000 // Bit SWRQ.

	// MDMA_C1TCR: This register is used to configure the           concerned channel.
	MDMA_MDMA_C1TCR_SINC_Pos   = 0x0        // Position of SINC field.
	MDMA_MDMA_C1TCR_SINC_Msk   = 0x3        // Bit mask of SINC field.
	MDMA_MDMA_C1TCR_DINC_Pos   = 0x2        // Position of DINC field.
	MDMA_MDMA_C1TCR_DINC_Msk   = 0xc        // Bit mask of DINC field.
	MDMA_MDMA_C1TCR_SSIZE_Pos  = 0x4        // Position of SSIZE field.
	MDMA_MDMA_C1TCR_SSIZE_Msk  = 0x30       // Bit mask of SSIZE field.
	MDMA_MDMA_C1TCR_DSIZE_Pos  = 0x6        // Position of DSIZE field.
	MDMA_MDMA_C1TCR_DSIZE_Msk  = 0xc0       // Bit mask of DSIZE field.
	MDMA_MDMA_C1TCR_SINCOS_Pos = 0x8        // Position of SINCOS field.
	MDMA_MDMA_C1TCR_SINCOS_Msk = 0x300      // Bit mask of SINCOS field.
	MDMA_MDMA_C1TCR_DINCOS_Pos = 0xa        // Position of DINCOS field.
	MDMA_MDMA_C1TCR_DINCOS_Msk = 0xc00      // Bit mask of DINCOS field.
	MDMA_MDMA_C1TCR_SBURST_Pos = 0xc        // Position of SBURST field.
	MDMA_MDMA_C1TCR_SBURST_Msk = 0x7000     // Bit mask of SBURST field.
	MDMA_MDMA_C1TCR_DBURST_Pos = 0xf        // Position of DBURST field.
	MDMA_MDMA_C1TCR_DBURST_Msk = 0x38000    // Bit mask of DBURST field.
	MDMA_MDMA_C1TCR_TLEN_Pos   = 0x12       // Position of TLEN field.
	MDMA_MDMA_C1TCR_TLEN_Msk   = 0x1fc0000  // Bit mask of TLEN field.
	MDMA_MDMA_C1TCR_PKE_Pos    = 0x19       // Position of PKE field.
	MDMA_MDMA_C1TCR_PKE_Msk    = 0x2000000  // Bit mask of PKE field.
	MDMA_MDMA_C1TCR_PKE        = 0x2000000  // Bit PKE.
	MDMA_MDMA_C1TCR_PAM_Pos    = 0x1a       // Position of PAM field.
	MDMA_MDMA_C1TCR_PAM_Msk    = 0xc000000  // Bit mask of PAM field.
	MDMA_MDMA_C1TCR_TRGM_Pos   = 0x1c       // Position of TRGM field.
	MDMA_MDMA_C1TCR_TRGM_Msk   = 0x30000000 // Bit mask of TRGM field.
	MDMA_MDMA_C1TCR_SWRM_Pos   = 0x1e       // Position of SWRM field.
	MDMA_MDMA_C1TCR_SWRM_Msk   = 0x40000000 // Bit mask of SWRM field.
	MDMA_MDMA_C1TCR_SWRM       = 0x40000000 // Bit SWRM.
	MDMA_MDMA_C1TCR_BWM_Pos    = 0x1f       // Position of BWM field.
	MDMA_MDMA_C1TCR_BWM_Msk    = 0x80000000 // Bit mask of BWM field.
	MDMA_MDMA_C1TCR_BWM        = 0x80000000 // Bit BWM.

	// MDMA_C1BNDTR: MDMA Channel x block number of data           register
	MDMA_MDMA_C1BNDTR_BNDT_Pos  = 0x0        // Position of BNDT field.
	MDMA_MDMA_C1BNDTR_BNDT_Msk  = 0x1ffff    // Bit mask of BNDT field.
	MDMA_MDMA_C1BNDTR_BRSUM_Pos = 0x12       // Position of BRSUM field.
	MDMA_MDMA_C1BNDTR_BRSUM_Msk = 0x40000    // Bit mask of BRSUM field.
	MDMA_MDMA_C1BNDTR_BRSUM     = 0x40000    // Bit BRSUM.
	MDMA_MDMA_C1BNDTR_BRDUM_Pos = 0x13       // Position of BRDUM field.
	MDMA_MDMA_C1BNDTR_BRDUM_Msk = 0x80000    // Bit mask of BRDUM field.
	MDMA_MDMA_C1BNDTR_BRDUM     = 0x80000    // Bit BRDUM.
	MDMA_MDMA_C1BNDTR_BRC_Pos   = 0x14       // Position of BRC field.
	MDMA_MDMA_C1BNDTR_BRC_Msk   = 0xfff00000 // Bit mask of BRC field.

	// MDMA_C1SAR: MDMA channel x source address           register
	MDMA_MDMA_C1SAR_SAR_Pos = 0x0        // Position of SAR field.
	MDMA_MDMA_C1SAR_SAR_Msk = 0xffffffff // Bit mask of SAR field.

	// MDMA_C1DAR: MDMA channel x destination address           register
	MDMA_MDMA_C1DAR_DAR_Pos = 0x0        // Position of DAR field.
	MDMA_MDMA_C1DAR_DAR_Msk = 0xffffffff // Bit mask of DAR field.

	// MDMA_C1BRUR: MDMA channel x Block Repeat address Update           register
	MDMA_MDMA_C1BRUR_SUV_Pos = 0x0        // Position of SUV field.
	MDMA_MDMA_C1BRUR_SUV_Msk = 0xffff     // Bit mask of SUV field.
	MDMA_MDMA_C1BRUR_DUV_Pos = 0x10       // Position of DUV field.
	MDMA_MDMA_C1BRUR_DUV_Msk = 0xffff0000 // Bit mask of DUV field.

	// MDMA_C1LAR: MDMA channel x Link Address           register
	MDMA_MDMA_C1LAR_LAR_Pos = 0x0        // Position of LAR field.
	MDMA_MDMA_C1LAR_LAR_Msk = 0xffffffff // Bit mask of LAR field.

	// MDMA_C1TBR: MDMA channel x Trigger and Bus selection           Register
	MDMA_MDMA_C1TBR_TSEL_Pos = 0x0     // Position of TSEL field.
	MDMA_MDMA_C1TBR_TSEL_Msk = 0x3f    // Bit mask of TSEL field.
	MDMA_MDMA_C1TBR_SBUS_Pos = 0x10    // Position of SBUS field.
	MDMA_MDMA_C1TBR_SBUS_Msk = 0x10000 // Bit mask of SBUS field.
	MDMA_MDMA_C1TBR_SBUS     = 0x10000 // Bit SBUS.
	MDMA_MDMA_C1TBR_DBUS_Pos = 0x11    // Position of DBUS field.
	MDMA_MDMA_C1TBR_DBUS_Msk = 0x20000 // Bit mask of DBUS field.
	MDMA_MDMA_C1TBR_DBUS     = 0x20000 // Bit DBUS.

	// MDMA_C1MAR: MDMA channel x Mask address           register
	MDMA_MDMA_C1MAR_MAR_Pos = 0x0        // Position of MAR field.
	MDMA_MDMA_C1MAR_MAR_Msk = 0xffffffff // Bit mask of MAR field.

	// MDMA_C1MDR: MDMA channel x Mask Data           register
	MDMA_MDMA_C1MDR_MDR_Pos = 0x0        // Position of MDR field.
	MDMA_MDMA_C1MDR_MDR_Msk = 0xffffffff // Bit mask of MDR field.

	// MDMA_C2ISR: MDMA channel x interrupt/status           register
	MDMA_MDMA_C2ISR_TEIF2_Pos  = 0x0     // Position of TEIF2 field.
	MDMA_MDMA_C2ISR_TEIF2_Msk  = 0x1     // Bit mask of TEIF2 field.
	MDMA_MDMA_C2ISR_TEIF2      = 0x1     // Bit TEIF2.
	MDMA_MDMA_C2ISR_CTCIF2_Pos = 0x1     // Position of CTCIF2 field.
	MDMA_MDMA_C2ISR_CTCIF2_Msk = 0x2     // Bit mask of CTCIF2 field.
	MDMA_MDMA_C2ISR_CTCIF2     = 0x2     // Bit CTCIF2.
	MDMA_MDMA_C2ISR_BRTIF2_Pos = 0x2     // Position of BRTIF2 field.
	MDMA_MDMA_C2ISR_BRTIF2_Msk = 0x4     // Bit mask of BRTIF2 field.
	MDMA_MDMA_C2ISR_BRTIF2     = 0x4     // Bit BRTIF2.
	MDMA_MDMA_C2ISR_BTIF2_Pos  = 0x3     // Position of BTIF2 field.
	MDMA_MDMA_C2ISR_BTIF2_Msk  = 0x8     // Bit mask of BTIF2 field.
	MDMA_MDMA_C2ISR_BTIF2      = 0x8     // Bit BTIF2.
	MDMA_MDMA_C2ISR_TCIF2_Pos  = 0x4     // Position of TCIF2 field.
	MDMA_MDMA_C2ISR_TCIF2_Msk  = 0x10    // Bit mask of TCIF2 field.
	MDMA_MDMA_C2ISR_TCIF2      = 0x10    // Bit TCIF2.
	MDMA_MDMA_C2ISR_CRQA2_Pos  = 0x10    // Position of CRQA2 field.
	MDMA_MDMA_C2ISR_CRQA2_Msk  = 0x10000 // Bit mask of CRQA2 field.
	MDMA_MDMA_C2ISR_CRQA2      = 0x10000 // Bit CRQA2.

	// MDMA_C2IFCR: MDMA channel x interrupt flag clear           register
	MDMA_MDMA_C2IFCR_CTEIF2_Pos  = 0x0  // Position of CTEIF2 field.
	MDMA_MDMA_C2IFCR_CTEIF2_Msk  = 0x1  // Bit mask of CTEIF2 field.
	MDMA_MDMA_C2IFCR_CTEIF2      = 0x1  // Bit CTEIF2.
	MDMA_MDMA_C2IFCR_CCTCIF2_Pos = 0x1  // Position of CCTCIF2 field.
	MDMA_MDMA_C2IFCR_CCTCIF2_Msk = 0x2  // Bit mask of CCTCIF2 field.
	MDMA_MDMA_C2IFCR_CCTCIF2     = 0x2  // Bit CCTCIF2.
	MDMA_MDMA_C2IFCR_CBRTIF2_Pos = 0x2  // Position of CBRTIF2 field.
	MDMA_MDMA_C2IFCR_CBRTIF2_Msk = 0x4  // Bit mask of CBRTIF2 field.
	MDMA_MDMA_C2IFCR_CBRTIF2     = 0x4  // Bit CBRTIF2.
	MDMA_MDMA_C2IFCR_CBTIF2_Pos  = 0x3  // Position of CBTIF2 field.
	MDMA_MDMA_C2IFCR_CBTIF2_Msk  = 0x8  // Bit mask of CBTIF2 field.
	MDMA_MDMA_C2IFCR_CBTIF2      = 0x8  // Bit CBTIF2.
	MDMA_MDMA_C2IFCR_CLTCIF2_Pos = 0x4  // Position of CLTCIF2 field.
	MDMA_MDMA_C2IFCR_CLTCIF2_Msk = 0x10 // Bit mask of CLTCIF2 field.
	MDMA_MDMA_C2IFCR_CLTCIF2     = 0x10 // Bit CLTCIF2.

	// MDMA_C2ESR: MDMA Channel x error status           register
	MDMA_MDMA_C2ESR_TEA_Pos  = 0x0   // Position of TEA field.
	MDMA_MDMA_C2ESR_TEA_Msk  = 0x7f  // Bit mask of TEA field.
	MDMA_MDMA_C2ESR_TED_Pos  = 0x7   // Position of TED field.
	MDMA_MDMA_C2ESR_TED_Msk  = 0x80  // Bit mask of TED field.
	MDMA_MDMA_C2ESR_TED      = 0x80  // Bit TED.
	MDMA_MDMA_C2ESR_TELD_Pos = 0x8   // Position of TELD field.
	MDMA_MDMA_C2ESR_TELD_Msk = 0x100 // Bit mask of TELD field.
	MDMA_MDMA_C2ESR_TELD     = 0x100 // Bit TELD.
	MDMA_MDMA_C2ESR_TEMD_Pos = 0x9   // Position of TEMD field.
	MDMA_MDMA_C2ESR_TEMD_Msk = 0x200 // Bit mask of TEMD field.
	MDMA_MDMA_C2ESR_TEMD     = 0x200 // Bit TEMD.
	MDMA_MDMA_C2ESR_ASE_Pos  = 0xa   // Position of ASE field.
	MDMA_MDMA_C2ESR_ASE_Msk  = 0x400 // Bit mask of ASE field.
	MDMA_MDMA_C2ESR_ASE      = 0x400 // Bit ASE.
	MDMA_MDMA_C2ESR_BSE_Pos  = 0xb   // Position of BSE field.
	MDMA_MDMA_C2ESR_BSE_Msk  = 0x800 // Bit mask of BSE field.
	MDMA_MDMA_C2ESR_BSE      = 0x800 // Bit BSE.

	// MDMA_C2CR: This register is used to control the           concerned channel.
	MDMA_MDMA_C2CR_EN_Pos    = 0x0     // Position of EN field.
	MDMA_MDMA_C2CR_EN_Msk    = 0x1     // Bit mask of EN field.
	MDMA_MDMA_C2CR_EN        = 0x1     // Bit EN.
	MDMA_MDMA_C2CR_TEIE_Pos  = 0x1     // Position of TEIE field.
	MDMA_MDMA_C2CR_TEIE_Msk  = 0x2     // Bit mask of TEIE field.
	MDMA_MDMA_C2CR_TEIE      = 0x2     // Bit TEIE.
	MDMA_MDMA_C2CR_CTCIE_Pos = 0x2     // Position of CTCIE field.
	MDMA_MDMA_C2CR_CTCIE_Msk = 0x4     // Bit mask of CTCIE field.
	MDMA_MDMA_C2CR_CTCIE     = 0x4     // Bit CTCIE.
	MDMA_MDMA_C2CR_BRTIE_Pos = 0x3     // Position of BRTIE field.
	MDMA_MDMA_C2CR_BRTIE_Msk = 0x8     // Bit mask of BRTIE field.
	MDMA_MDMA_C2CR_BRTIE     = 0x8     // Bit BRTIE.
	MDMA_MDMA_C2CR_BTIE_Pos  = 0x4     // Position of BTIE field.
	MDMA_MDMA_C2CR_BTIE_Msk  = 0x10    // Bit mask of BTIE field.
	MDMA_MDMA_C2CR_BTIE      = 0x10    // Bit BTIE.
	MDMA_MDMA_C2CR_TCIE_Pos  = 0x5     // Position of TCIE field.
	MDMA_MDMA_C2CR_TCIE_Msk  = 0x20    // Bit mask of TCIE field.
	MDMA_MDMA_C2CR_TCIE      = 0x20    // Bit TCIE.
	MDMA_MDMA_C2CR_PL_Pos    = 0x6     // Position of PL field.
	MDMA_MDMA_C2CR_PL_Msk    = 0xc0    // Bit mask of PL field.
	MDMA_MDMA_C2CR_BEX_Pos   = 0xc     // Position of BEX field.
	MDMA_MDMA_C2CR_BEX_Msk   = 0x1000  // Bit mask of BEX field.
	MDMA_MDMA_C2CR_BEX       = 0x1000  // Bit BEX.
	MDMA_MDMA_C2CR_HEX_Pos   = 0xd     // Position of HEX field.
	MDMA_MDMA_C2CR_HEX_Msk   = 0x2000  // Bit mask of HEX field.
	MDMA_MDMA_C2CR_HEX       = 0x2000  // Bit HEX.
	MDMA_MDMA_C2CR_WEX_Pos   = 0xe     // Position of WEX field.
	MDMA_MDMA_C2CR_WEX_Msk   = 0x4000  // Bit mask of WEX field.
	MDMA_MDMA_C2CR_WEX       = 0x4000  // Bit WEX.
	MDMA_MDMA_C2CR_SWRQ_Pos  = 0x10    // Position of SWRQ field.
	MDMA_MDMA_C2CR_SWRQ_Msk  = 0x10000 // Bit mask of SWRQ field.
	MDMA_MDMA_C2CR_SWRQ      = 0x10000 // Bit SWRQ.

	// MDMA_C2TCR: This register is used to configure the           concerned channel.
	MDMA_MDMA_C2TCR_SINC_Pos   = 0x0        // Position of SINC field.
	MDMA_MDMA_C2TCR_SINC_Msk   = 0x3        // Bit mask of SINC field.
	MDMA_MDMA_C2TCR_DINC_Pos   = 0x2        // Position of DINC field.
	MDMA_MDMA_C2TCR_DINC_Msk   = 0xc        // Bit mask of DINC field.
	MDMA_MDMA_C2TCR_SSIZE_Pos  = 0x4        // Position of SSIZE field.
	MDMA_MDMA_C2TCR_SSIZE_Msk  = 0x30       // Bit mask of SSIZE field.
	MDMA_MDMA_C2TCR_DSIZE_Pos  = 0x6        // Position of DSIZE field.
	MDMA_MDMA_C2TCR_DSIZE_Msk  = 0xc0       // Bit mask of DSIZE field.
	MDMA_MDMA_C2TCR_SINCOS_Pos = 0x8        // Position of SINCOS field.
	MDMA_MDMA_C2TCR_SINCOS_Msk = 0x300      // Bit mask of SINCOS field.
	MDMA_MDMA_C2TCR_DINCOS_Pos = 0xa        // Position of DINCOS field.
	MDMA_MDMA_C2TCR_DINCOS_Msk = 0xc00      // Bit mask of DINCOS field.
	MDMA_MDMA_C2TCR_SBURST_Pos = 0xc        // Position of SBURST field.
	MDMA_MDMA_C2TCR_SBURST_Msk = 0x7000     // Bit mask of SBURST field.
	MDMA_MDMA_C2TCR_DBURST_Pos = 0xf        // Position of DBURST field.
	MDMA_MDMA_C2TCR_DBURST_Msk = 0x38000    // Bit mask of DBURST field.
	MDMA_MDMA_C2TCR_TLEN_Pos   = 0x12       // Position of TLEN field.
	MDMA_MDMA_C2TCR_TLEN_Msk   = 0x1fc0000  // Bit mask of TLEN field.
	MDMA_MDMA_C2TCR_PKE_Pos    = 0x19       // Position of PKE field.
	MDMA_MDMA_C2TCR_PKE_Msk    = 0x2000000  // Bit mask of PKE field.
	MDMA_MDMA_C2TCR_PKE        = 0x2000000  // Bit PKE.
	MDMA_MDMA_C2TCR_PAM_Pos    = 0x1a       // Position of PAM field.
	MDMA_MDMA_C2TCR_PAM_Msk    = 0xc000000  // Bit mask of PAM field.
	MDMA_MDMA_C2TCR_TRGM_Pos   = 0x1c       // Position of TRGM field.
	MDMA_MDMA_C2TCR_TRGM_Msk   = 0x30000000 // Bit mask of TRGM field.
	MDMA_MDMA_C2TCR_SWRM_Pos   = 0x1e       // Position of SWRM field.
	MDMA_MDMA_C2TCR_SWRM_Msk   = 0x40000000 // Bit mask of SWRM field.
	MDMA_MDMA_C2TCR_SWRM       = 0x40000000 // Bit SWRM.
	MDMA_MDMA_C2TCR_BWM_Pos    = 0x1f       // Position of BWM field.
	MDMA_MDMA_C2TCR_BWM_Msk    = 0x80000000 // Bit mask of BWM field.
	MDMA_MDMA_C2TCR_BWM        = 0x80000000 // Bit BWM.

	// MDMA_C2BNDTR: MDMA Channel x block number of data           register
	MDMA_MDMA_C2BNDTR_BNDT_Pos  = 0x0        // Position of BNDT field.
	MDMA_MDMA_C2BNDTR_BNDT_Msk  = 0x1ffff    // Bit mask of BNDT field.
	MDMA_MDMA_C2BNDTR_BRSUM_Pos = 0x12       // Position of BRSUM field.
	MDMA_MDMA_C2BNDTR_BRSUM_Msk = 0x40000    // Bit mask of BRSUM field.
	MDMA_MDMA_C2BNDTR_BRSUM     = 0x40000    // Bit BRSUM.
	MDMA_MDMA_C2BNDTR_BRDUM_Pos = 0x13       // Position of BRDUM field.
	MDMA_MDMA_C2BNDTR_BRDUM_Msk = 0x80000    // Bit mask of BRDUM field.
	MDMA_MDMA_C2BNDTR_BRDUM     = 0x80000    // Bit BRDUM.
	MDMA_MDMA_C2BNDTR_BRC_Pos   = 0x14       // Position of BRC field.
	MDMA_MDMA_C2BNDTR_BRC_Msk   = 0xfff00000 // Bit mask of BRC field.

	// MDMA_C2SAR: MDMA channel x source address           register
	MDMA_MDMA_C2SAR_SAR_Pos = 0x0        // Position of SAR field.
	MDMA_MDMA_C2SAR_SAR_Msk = 0xffffffff // Bit mask of SAR field.

	// MDMA_C2DAR: MDMA channel x destination address           register
	MDMA_MDMA_C2DAR_DAR_Pos = 0x0        // Position of DAR field.
	MDMA_MDMA_C2DAR_DAR_Msk = 0xffffffff // Bit mask of DAR field.

	// MDMA_C2BRUR: MDMA channel x Block Repeat address Update           register
	MDMA_MDMA_C2BRUR_SUV_Pos = 0x0        // Position of SUV field.
	MDMA_MDMA_C2BRUR_SUV_Msk = 0xffff     // Bit mask of SUV field.
	MDMA_MDMA_C2BRUR_DUV_Pos = 0x10       // Position of DUV field.
	MDMA_MDMA_C2BRUR_DUV_Msk = 0xffff0000 // Bit mask of DUV field.

	// MDMA_C2LAR: MDMA channel x Link Address           register
	MDMA_MDMA_C2LAR_LAR_Pos = 0x0        // Position of LAR field.
	MDMA_MDMA_C2LAR_LAR_Msk = 0xffffffff // Bit mask of LAR field.

	// MDMA_C2TBR: MDMA channel x Trigger and Bus selection           Register
	MDMA_MDMA_C2TBR_TSEL_Pos = 0x0     // Position of TSEL field.
	MDMA_MDMA_C2TBR_TSEL_Msk = 0x3f    // Bit mask of TSEL field.
	MDMA_MDMA_C2TBR_SBUS_Pos = 0x10    // Position of SBUS field.
	MDMA_MDMA_C2TBR_SBUS_Msk = 0x10000 // Bit mask of SBUS field.
	MDMA_MDMA_C2TBR_SBUS     = 0x10000 // Bit SBUS.
	MDMA_MDMA_C2TBR_DBUS_Pos = 0x11    // Position of DBUS field.
	MDMA_MDMA_C2TBR_DBUS_Msk = 0x20000 // Bit mask of DBUS field.
	MDMA_MDMA_C2TBR_DBUS     = 0x20000 // Bit DBUS.

	// MDMA_C2MAR: MDMA channel x Mask address           register
	MDMA_MDMA_C2MAR_MAR_Pos = 0x0        // Position of MAR field.
	MDMA_MDMA_C2MAR_MAR_Msk = 0xffffffff // Bit mask of MAR field.

	// MDMA_C2MDR: MDMA channel x Mask Data           register
	MDMA_MDMA_C2MDR_MDR_Pos = 0x0        // Position of MDR field.
	MDMA_MDMA_C2MDR_MDR_Msk = 0xffffffff // Bit mask of MDR field.

	// MDMA_C3ISR: MDMA channel x interrupt/status           register
	MDMA_MDMA_C3ISR_TEIF3_Pos  = 0x0     // Position of TEIF3 field.
	MDMA_MDMA_C3ISR_TEIF3_Msk  = 0x1     // Bit mask of TEIF3 field.
	MDMA_MDMA_C3ISR_TEIF3      = 0x1     // Bit TEIF3.
	MDMA_MDMA_C3ISR_CTCIF3_Pos = 0x1     // Position of CTCIF3 field.
	MDMA_MDMA_C3ISR_CTCIF3_Msk = 0x2     // Bit mask of CTCIF3 field.
	MDMA_MDMA_C3ISR_CTCIF3     = 0x2     // Bit CTCIF3.
	MDMA_MDMA_C3ISR_BRTIF3_Pos = 0x2     // Position of BRTIF3 field.
	MDMA_MDMA_C3ISR_BRTIF3_Msk = 0x4     // Bit mask of BRTIF3 field.
	MDMA_MDMA_C3ISR_BRTIF3     = 0x4     // Bit BRTIF3.
	MDMA_MDMA_C3ISR_BTIF3_Pos  = 0x3     // Position of BTIF3 field.
	MDMA_MDMA_C3ISR_BTIF3_Msk  = 0x8     // Bit mask of BTIF3 field.
	MDMA_MDMA_C3ISR_BTIF3      = 0x8     // Bit BTIF3.
	MDMA_MDMA_C3ISR_TCIF3_Pos  = 0x4     // Position of TCIF3 field.
	MDMA_MDMA_C3ISR_TCIF3_Msk  = 0x10    // Bit mask of TCIF3 field.
	MDMA_MDMA_C3ISR_TCIF3      = 0x10    // Bit TCIF3.
	MDMA_MDMA_C3ISR_CRQA3_Pos  = 0x10    // Position of CRQA3 field.
	MDMA_MDMA_C3ISR_CRQA3_Msk  = 0x10000 // Bit mask of CRQA3 field.
	MDMA_MDMA_C3ISR_CRQA3      = 0x10000 // Bit CRQA3.

	// MDMA_C3IFCR: MDMA channel x interrupt flag clear           register
	MDMA_MDMA_C3IFCR_CTEIF3_Pos  = 0x0  // Position of CTEIF3 field.
	MDMA_MDMA_C3IFCR_CTEIF3_Msk  = 0x1  // Bit mask of CTEIF3 field.
	MDMA_MDMA_C3IFCR_CTEIF3      = 0x1  // Bit CTEIF3.
	MDMA_MDMA_C3IFCR_CCTCIF3_Pos = 0x1  // Position of CCTCIF3 field.
	MDMA_MDMA_C3IFCR_CCTCIF3_Msk = 0x2  // Bit mask of CCTCIF3 field.
	MDMA_MDMA_C3IFCR_CCTCIF3     = 0x2  // Bit CCTCIF3.
	MDMA_MDMA_C3IFCR_CBRTIF3_Pos = 0x2  // Position of CBRTIF3 field.
	MDMA_MDMA_C3IFCR_CBRTIF3_Msk = 0x4  // Bit mask of CBRTIF3 field.
	MDMA_MDMA_C3IFCR_CBRTIF3     = 0x4  // Bit CBRTIF3.
	MDMA_MDMA_C3IFCR_CBTIF3_Pos  = 0x3  // Position of CBTIF3 field.
	MDMA_MDMA_C3IFCR_CBTIF3_Msk  = 0x8  // Bit mask of CBTIF3 field.
	MDMA_MDMA_C3IFCR_CBTIF3      = 0x8  // Bit CBTIF3.
	MDMA_MDMA_C3IFCR_CLTCIF3_Pos = 0x4  // Position of CLTCIF3 field.
	MDMA_MDMA_C3IFCR_CLTCIF3_Msk = 0x10 // Bit mask of CLTCIF3 field.
	MDMA_MDMA_C3IFCR_CLTCIF3     = 0x10 // Bit CLTCIF3.

	// MDMA_C3ESR: MDMA Channel x error status           register
	MDMA_MDMA_C3ESR_TEA_Pos  = 0x0   // Position of TEA field.
	MDMA_MDMA_C3ESR_TEA_Msk  = 0x7f  // Bit mask of TEA field.
	MDMA_MDMA_C3ESR_TED_Pos  = 0x7   // Position of TED field.
	MDMA_MDMA_C3ESR_TED_Msk  = 0x80  // Bit mask of TED field.
	MDMA_MDMA_C3ESR_TED      = 0x80  // Bit TED.
	MDMA_MDMA_C3ESR_TELD_Pos = 0x8   // Position of TELD field.
	MDMA_MDMA_C3ESR_TELD_Msk = 0x100 // Bit mask of TELD field.
	MDMA_MDMA_C3ESR_TELD     = 0x100 // Bit TELD.
	MDMA_MDMA_C3ESR_TEMD_Pos = 0x9   // Position of TEMD field.
	MDMA_MDMA_C3ESR_TEMD_Msk = 0x200 // Bit mask of TEMD field.
	MDMA_MDMA_C3ESR_TEMD     = 0x200 // Bit TEMD.
	MDMA_MDMA_C3ESR_ASE_Pos  = 0xa   // Position of ASE field.
	MDMA_MDMA_C3ESR_ASE_Msk  = 0x400 // Bit mask of ASE field.
	MDMA_MDMA_C3ESR_ASE      = 0x400 // Bit ASE.
	MDMA_MDMA_C3ESR_BSE_Pos  = 0xb   // Position of BSE field.
	MDMA_MDMA_C3ESR_BSE_Msk  = 0x800 // Bit mask of BSE field.
	MDMA_MDMA_C3ESR_BSE      = 0x800 // Bit BSE.

	// MDMA_C3CR: This register is used to control the           concerned channel.
	MDMA_MDMA_C3CR_EN_Pos    = 0x0     // Position of EN field.
	MDMA_MDMA_C3CR_EN_Msk    = 0x1     // Bit mask of EN field.
	MDMA_MDMA_C3CR_EN        = 0x1     // Bit EN.
	MDMA_MDMA_C3CR_TEIE_Pos  = 0x1     // Position of TEIE field.
	MDMA_MDMA_C3CR_TEIE_Msk  = 0x2     // Bit mask of TEIE field.
	MDMA_MDMA_C3CR_TEIE      = 0x2     // Bit TEIE.
	MDMA_MDMA_C3CR_CTCIE_Pos = 0x2     // Position of CTCIE field.
	MDMA_MDMA_C3CR_CTCIE_Msk = 0x4     // Bit mask of CTCIE field.
	MDMA_MDMA_C3CR_CTCIE     = 0x4     // Bit CTCIE.
	MDMA_MDMA_C3CR_BRTIE_Pos = 0x3     // Position of BRTIE field.
	MDMA_MDMA_C3CR_BRTIE_Msk = 0x8     // Bit mask of BRTIE field.
	MDMA_MDMA_C3CR_BRTIE     = 0x8     // Bit BRTIE.
	MDMA_MDMA_C3CR_BTIE_Pos  = 0x4     // Position of BTIE field.
	MDMA_MDMA_C3CR_BTIE_Msk  = 0x10    // Bit mask of BTIE field.
	MDMA_MDMA_C3CR_BTIE      = 0x10    // Bit BTIE.
	MDMA_MDMA_C3CR_TCIE_Pos  = 0x5     // Position of TCIE field.
	MDMA_MDMA_C3CR_TCIE_Msk  = 0x20    // Bit mask of TCIE field.
	MDMA_MDMA_C3CR_TCIE      = 0x20    // Bit TCIE.
	MDMA_MDMA_C3CR_PL_Pos    = 0x6     // Position of PL field.
	MDMA_MDMA_C3CR_PL_Msk    = 0xc0    // Bit mask of PL field.
	MDMA_MDMA_C3CR_BEX_Pos   = 0xc     // Position of BEX field.
	MDMA_MDMA_C3CR_BEX_Msk   = 0x1000  // Bit mask of BEX field.
	MDMA_MDMA_C3CR_BEX       = 0x1000  // Bit BEX.
	MDMA_MDMA_C3CR_HEX_Pos   = 0xd     // Position of HEX field.
	MDMA_MDMA_C3CR_HEX_Msk   = 0x2000  // Bit mask of HEX field.
	MDMA_MDMA_C3CR_HEX       = 0x2000  // Bit HEX.
	MDMA_MDMA_C3CR_WEX_Pos   = 0xe     // Position of WEX field.
	MDMA_MDMA_C3CR_WEX_Msk   = 0x4000  // Bit mask of WEX field.
	MDMA_MDMA_C3CR_WEX       = 0x4000  // Bit WEX.
	MDMA_MDMA_C3CR_SWRQ_Pos  = 0x10    // Position of SWRQ field.
	MDMA_MDMA_C3CR_SWRQ_Msk  = 0x10000 // Bit mask of SWRQ field.
	MDMA_MDMA_C3CR_SWRQ      = 0x10000 // Bit SWRQ.

	// MDMA_C3TCR: This register is used to configure the           concerned channel.
	MDMA_MDMA_C3TCR_SINC_Pos   = 0x0        // Position of SINC field.
	MDMA_MDMA_C3TCR_SINC_Msk   = 0x3        // Bit mask of SINC field.
	MDMA_MDMA_C3TCR_DINC_Pos   = 0x2        // Position of DINC field.
	MDMA_MDMA_C3TCR_DINC_Msk   = 0xc        // Bit mask of DINC field.
	MDMA_MDMA_C3TCR_SSIZE_Pos  = 0x4        // Position of SSIZE field.
	MDMA_MDMA_C3TCR_SSIZE_Msk  = 0x30       // Bit mask of SSIZE field.
	MDMA_MDMA_C3TCR_DSIZE_Pos  = 0x6        // Position of DSIZE field.
	MDMA_MDMA_C3TCR_DSIZE_Msk  = 0xc0       // Bit mask of DSIZE field.
	MDMA_MDMA_C3TCR_SINCOS_Pos = 0x8        // Position of SINCOS field.
	MDMA_MDMA_C3TCR_SINCOS_Msk = 0x300      // Bit mask of SINCOS field.
	MDMA_MDMA_C3TCR_DINCOS_Pos = 0xa        // Position of DINCOS field.
	MDMA_MDMA_C3TCR_DINCOS_Msk = 0xc00      // Bit mask of DINCOS field.
	MDMA_MDMA_C3TCR_SBURST_Pos = 0xc        // Position of SBURST field.
	MDMA_MDMA_C3TCR_SBURST_Msk = 0x7000     // Bit mask of SBURST field.
	MDMA_MDMA_C3TCR_DBURST_Pos = 0xf        // Position of DBURST field.
	MDMA_MDMA_C3TCR_DBURST_Msk = 0x38000    // Bit mask of DBURST field.
	MDMA_MDMA_C3TCR_TLEN_Pos   = 0x12       // Position of TLEN field.
	MDMA_MDMA_C3TCR_TLEN_Msk   = 0x1fc0000  // Bit mask of TLEN field.
	MDMA_MDMA_C3TCR_PKE_Pos    = 0x19       // Position of PKE field.
	MDMA_MDMA_C3TCR_PKE_Msk    = 0x2000000  // Bit mask of PKE field.
	MDMA_MDMA_C3TCR_PKE        = 0x2000000  // Bit PKE.
	MDMA_MDMA_C3TCR_PAM_Pos    = 0x1a       // Position of PAM field.
	MDMA_MDMA_C3TCR_PAM_Msk    = 0xc000000  // Bit mask of PAM field.
	MDMA_MDMA_C3TCR_TRGM_Pos   = 0x1c       // Position of TRGM field.
	MDMA_MDMA_C3TCR_TRGM_Msk   = 0x30000000 // Bit mask of TRGM field.
	MDMA_MDMA_C3TCR_SWRM_Pos   = 0x1e       // Position of SWRM field.
	MDMA_MDMA_C3TCR_SWRM_Msk   = 0x40000000 // Bit mask of SWRM field.
	MDMA_MDMA_C3TCR_SWRM       = 0x40000000 // Bit SWRM.
	MDMA_MDMA_C3TCR_BWM_Pos    = 0x1f       // Position of BWM field.
	MDMA_MDMA_C3TCR_BWM_Msk    = 0x80000000 // Bit mask of BWM field.
	MDMA_MDMA_C3TCR_BWM        = 0x80000000 // Bit BWM.

	// MDMA_C3BNDTR: MDMA Channel x block number of data           register
	MDMA_MDMA_C3BNDTR_BNDT_Pos  = 0x0        // Position of BNDT field.
	MDMA_MDMA_C3BNDTR_BNDT_Msk  = 0x1ffff    // Bit mask of BNDT field.
	MDMA_MDMA_C3BNDTR_BRSUM_Pos = 0x12       // Position of BRSUM field.
	MDMA_MDMA_C3BNDTR_BRSUM_Msk = 0x40000    // Bit mask of BRSUM field.
	MDMA_MDMA_C3BNDTR_BRSUM     = 0x40000    // Bit BRSUM.
	MDMA_MDMA_C3BNDTR_BRDUM_Pos = 0x13       // Position of BRDUM field.
	MDMA_MDMA_C3BNDTR_BRDUM_Msk = 0x80000    // Bit mask of BRDUM field.
	MDMA_MDMA_C3BNDTR_BRDUM     = 0x80000    // Bit BRDUM.
	MDMA_MDMA_C3BNDTR_BRC_Pos   = 0x14       // Position of BRC field.
	MDMA_MDMA_C3BNDTR_BRC_Msk   = 0xfff00000 // Bit mask of BRC field.

	// MDMA_C3SAR: MDMA channel x source address           register
	MDMA_MDMA_C3SAR_SAR_Pos = 0x0        // Position of SAR field.
	MDMA_MDMA_C3SAR_SAR_Msk = 0xffffffff // Bit mask of SAR field.

	// MDMA_C3DAR: MDMA channel x destination address           register
	MDMA_MDMA_C3DAR_DAR_Pos = 0x0        // Position of DAR field.
	MDMA_MDMA_C3DAR_DAR_Msk = 0xffffffff // Bit mask of DAR field.

	// MDMA_C3BRUR: MDMA channel x Block Repeat address Update           register
	MDMA_MDMA_C3BRUR_SUV_Pos = 0x0        // Position of SUV field.
	MDMA_MDMA_C3BRUR_SUV_Msk = 0xffff     // Bit mask of SUV field.
	MDMA_MDMA_C3BRUR_DUV_Pos = 0x10       // Position of DUV field.
	MDMA_MDMA_C3BRUR_DUV_Msk = 0xffff0000 // Bit mask of DUV field.

	// MDMA_C3LAR: MDMA channel x Link Address           register
	MDMA_MDMA_C3LAR_LAR_Pos = 0x0        // Position of LAR field.
	MDMA_MDMA_C3LAR_LAR_Msk = 0xffffffff // Bit mask of LAR field.

	// MDMA_C3TBR: MDMA channel x Trigger and Bus selection           Register
	MDMA_MDMA_C3TBR_TSEL_Pos = 0x0     // Position of TSEL field.
	MDMA_MDMA_C3TBR_TSEL_Msk = 0x3f    // Bit mask of TSEL field.
	MDMA_MDMA_C3TBR_SBUS_Pos = 0x10    // Position of SBUS field.
	MDMA_MDMA_C3TBR_SBUS_Msk = 0x10000 // Bit mask of SBUS field.
	MDMA_MDMA_C3TBR_SBUS     = 0x10000 // Bit SBUS.
	MDMA_MDMA_C3TBR_DBUS_Pos = 0x11    // Position of DBUS field.
	MDMA_MDMA_C3TBR_DBUS_Msk = 0x20000 // Bit mask of DBUS field.
	MDMA_MDMA_C3TBR_DBUS     = 0x20000 // Bit DBUS.

	// MDMA_C3MAR: MDMA channel x Mask address           register
	MDMA_MDMA_C3MAR_MAR_Pos = 0x0        // Position of MAR field.
	MDMA_MDMA_C3MAR_MAR_Msk = 0xffffffff // Bit mask of MAR field.

	// MDMA_C3MDR: MDMA channel x Mask Data           register
	MDMA_MDMA_C3MDR_MDR_Pos = 0x0        // Position of MDR field.
	MDMA_MDMA_C3MDR_MDR_Msk = 0xffffffff // Bit mask of MDR field.

	// MDMA_C4ISR: MDMA channel x interrupt/status           register
	MDMA_MDMA_C4ISR_TEIF4_Pos  = 0x0     // Position of TEIF4 field.
	MDMA_MDMA_C4ISR_TEIF4_Msk  = 0x1     // Bit mask of TEIF4 field.
	MDMA_MDMA_C4ISR_TEIF4      = 0x1     // Bit TEIF4.
	MDMA_MDMA_C4ISR_CTCIF4_Pos = 0x1     // Position of CTCIF4 field.
	MDMA_MDMA_C4ISR_CTCIF4_Msk = 0x2     // Bit mask of CTCIF4 field.
	MDMA_MDMA_C4ISR_CTCIF4     = 0x2     // Bit CTCIF4.
	MDMA_MDMA_C4ISR_BRTIF4_Pos = 0x2     // Position of BRTIF4 field.
	MDMA_MDMA_C4ISR_BRTIF4_Msk = 0x4     // Bit mask of BRTIF4 field.
	MDMA_MDMA_C4ISR_BRTIF4     = 0x4     // Bit BRTIF4.
	MDMA_MDMA_C4ISR_BTIF4_Pos  = 0x3     // Position of BTIF4 field.
	MDMA_MDMA_C4ISR_BTIF4_Msk  = 0x8     // Bit mask of BTIF4 field.
	MDMA_MDMA_C4ISR_BTIF4      = 0x8     // Bit BTIF4.
	MDMA_MDMA_C4ISR_TCIF4_Pos  = 0x4     // Position of TCIF4 field.
	MDMA_MDMA_C4ISR_TCIF4_Msk  = 0x10    // Bit mask of TCIF4 field.
	MDMA_MDMA_C4ISR_TCIF4      = 0x10    // Bit TCIF4.
	MDMA_MDMA_C4ISR_CRQA4_Pos  = 0x10    // Position of CRQA4 field.
	MDMA_MDMA_C4ISR_CRQA4_Msk  = 0x10000 // Bit mask of CRQA4 field.
	MDMA_MDMA_C4ISR_CRQA4      = 0x10000 // Bit CRQA4.

	// MDMA_C4IFCR: MDMA channel x interrupt flag clear           register
	MDMA_MDMA_C4IFCR_CTEIF4_Pos  = 0x0  // Position of CTEIF4 field.
	MDMA_MDMA_C4IFCR_CTEIF4_Msk  = 0x1  // Bit mask of CTEIF4 field.
	MDMA_MDMA_C4IFCR_CTEIF4      = 0x1  // Bit CTEIF4.
	MDMA_MDMA_C4IFCR_CCTCIF4_Pos = 0x1  // Position of CCTCIF4 field.
	MDMA_MDMA_C4IFCR_CCTCIF4_Msk = 0x2  // Bit mask of CCTCIF4 field.
	MDMA_MDMA_C4IFCR_CCTCIF4     = 0x2  // Bit CCTCIF4.
	MDMA_MDMA_C4IFCR_CBRTIF4_Pos = 0x2  // Position of CBRTIF4 field.
	MDMA_MDMA_C4IFCR_CBRTIF4_Msk = 0x4  // Bit mask of CBRTIF4 field.
	MDMA_MDMA_C4IFCR_CBRTIF4     = 0x4  // Bit CBRTIF4.
	MDMA_MDMA_C4IFCR_CBTIF4_Pos  = 0x3  // Position of CBTIF4 field.
	MDMA_MDMA_C4IFCR_CBTIF4_Msk  = 0x8  // Bit mask of CBTIF4 field.
	MDMA_MDMA_C4IFCR_CBTIF4      = 0x8  // Bit CBTIF4.
	MDMA_MDMA_C4IFCR_CLTCIF4_Pos = 0x4  // Position of CLTCIF4 field.
	MDMA_MDMA_C4IFCR_CLTCIF4_Msk = 0x10 // Bit mask of CLTCIF4 field.
	MDMA_MDMA_C4IFCR_CLTCIF4     = 0x10 // Bit CLTCIF4.

	// MDMA_C4ESR: MDMA Channel x error status           register
	MDMA_MDMA_C4ESR_TEA_Pos  = 0x0   // Position of TEA field.
	MDMA_MDMA_C4ESR_TEA_Msk  = 0x7f  // Bit mask of TEA field.
	MDMA_MDMA_C4ESR_TED_Pos  = 0x7   // Position of TED field.
	MDMA_MDMA_C4ESR_TED_Msk  = 0x80  // Bit mask of TED field.
	MDMA_MDMA_C4ESR_TED      = 0x80  // Bit TED.
	MDMA_MDMA_C4ESR_TELD_Pos = 0x8   // Position of TELD field.
	MDMA_MDMA_C4ESR_TELD_Msk = 0x100 // Bit mask of TELD field.
	MDMA_MDMA_C4ESR_TELD     = 0x100 // Bit TELD.
	MDMA_MDMA_C4ESR_TEMD_Pos = 0x9   // Position of TEMD field.
	MDMA_MDMA_C4ESR_TEMD_Msk = 0x200 // Bit mask of TEMD field.
	MDMA_MDMA_C4ESR_TEMD     = 0x200 // Bit TEMD.
	MDMA_MDMA_C4ESR_ASE_Pos  = 0xa   // Position of ASE field.
	MDMA_MDMA_C4ESR_ASE_Msk  = 0x400 // Bit mask of ASE field.
	MDMA_MDMA_C4ESR_ASE      = 0x400 // Bit ASE.
	MDMA_MDMA_C4ESR_BSE_Pos  = 0xb   // Position of BSE field.
	MDMA_MDMA_C4ESR_BSE_Msk  = 0x800 // Bit mask of BSE field.
	MDMA_MDMA_C4ESR_BSE      = 0x800 // Bit BSE.

	// MDMA_C4CR: This register is used to control the           concerned channel.
	MDMA_MDMA_C4CR_EN_Pos    = 0x0     // Position of EN field.
	MDMA_MDMA_C4CR_EN_Msk    = 0x1     // Bit mask of EN field.
	MDMA_MDMA_C4CR_EN        = 0x1     // Bit EN.
	MDMA_MDMA_C4CR_TEIE_Pos  = 0x1     // Position of TEIE field.
	MDMA_MDMA_C4CR_TEIE_Msk  = 0x2     // Bit mask of TEIE field.
	MDMA_MDMA_C4CR_TEIE      = 0x2     // Bit TEIE.
	MDMA_MDMA_C4CR_CTCIE_Pos = 0x2     // Position of CTCIE field.
	MDMA_MDMA_C4CR_CTCIE_Msk = 0x4     // Bit mask of CTCIE field.
	MDMA_MDMA_C4CR_CTCIE     = 0x4     // Bit CTCIE.
	MDMA_MDMA_C4CR_BRTIE_Pos = 0x3     // Position of BRTIE field.
	MDMA_MDMA_C4CR_BRTIE_Msk = 0x8     // Bit mask of BRTIE field.
	MDMA_MDMA_C4CR_BRTIE     = 0x8     // Bit BRTIE.
	MDMA_MDMA_C4CR_BTIE_Pos  = 0x4     // Position of BTIE field.
	MDMA_MDMA_C4CR_BTIE_Msk  = 0x10    // Bit mask of BTIE field.
	MDMA_MDMA_C4CR_BTIE      = 0x10    // Bit BTIE.
	MDMA_MDMA_C4CR_TCIE_Pos  = 0x5     // Position of TCIE field.
	MDMA_MDMA_C4CR_TCIE_Msk  = 0x20    // Bit mask of TCIE field.
	MDMA_MDMA_C4CR_TCIE      = 0x20    // Bit TCIE.
	MDMA_MDMA_C4CR_PL_Pos    = 0x6     // Position of PL field.
	MDMA_MDMA_C4CR_PL_Msk    = 0xc0    // Bit mask of PL field.
	MDMA_MDMA_C4CR_BEX_Pos   = 0xc     // Position of BEX field.
	MDMA_MDMA_C4CR_BEX_Msk   = 0x1000  // Bit mask of BEX field.
	MDMA_MDMA_C4CR_BEX       = 0x1000  // Bit BEX.
	MDMA_MDMA_C4CR_HEX_Pos   = 0xd     // Position of HEX field.
	MDMA_MDMA_C4CR_HEX_Msk   = 0x2000  // Bit mask of HEX field.
	MDMA_MDMA_C4CR_HEX       = 0x2000  // Bit HEX.
	MDMA_MDMA_C4CR_WEX_Pos   = 0xe     // Position of WEX field.
	MDMA_MDMA_C4CR_WEX_Msk   = 0x4000  // Bit mask of WEX field.
	MDMA_MDMA_C4CR_WEX       = 0x4000  // Bit WEX.
	MDMA_MDMA_C4CR_SWRQ_Pos  = 0x10    // Position of SWRQ field.
	MDMA_MDMA_C4CR_SWRQ_Msk  = 0x10000 // Bit mask of SWRQ field.
	MDMA_MDMA_C4CR_SWRQ      = 0x10000 // Bit SWRQ.

	// MDMA_C4TCR: This register is used to configure the           concerned channel.
	MDMA_MDMA_C4TCR_SINC_Pos   = 0x0        // Position of SINC field.
	MDMA_MDMA_C4TCR_SINC_Msk   = 0x3        // Bit mask of SINC field.
	MDMA_MDMA_C4TCR_DINC_Pos   = 0x2        // Position of DINC field.
	MDMA_MDMA_C4TCR_DINC_Msk   = 0xc        // Bit mask of DINC field.
	MDMA_MDMA_C4TCR_SSIZE_Pos  = 0x4        // Position of SSIZE field.
	MDMA_MDMA_C4TCR_SSIZE_Msk  = 0x30       // Bit mask of SSIZE field.
	MDMA_MDMA_C4TCR_DSIZE_Pos  = 0x6        // Position of DSIZE field.
	MDMA_MDMA_C4TCR_DSIZE_Msk  = 0xc0       // Bit mask of DSIZE field.
	MDMA_MDMA_C4TCR_SINCOS_Pos = 0x8        // Position of SINCOS field.
	MDMA_MDMA_C4TCR_SINCOS_Msk = 0x300      // Bit mask of SINCOS field.
	MDMA_MDMA_C4TCR_DINCOS_Pos = 0xa        // Position of DINCOS field.
	MDMA_MDMA_C4TCR_DINCOS_Msk = 0xc00      // Bit mask of DINCOS field.
	MDMA_MDMA_C4TCR_SBURST_Pos = 0xc        // Position of SBURST field.
	MDMA_MDMA_C4TCR_SBURST_Msk = 0x7000     // Bit mask of SBURST field.
	MDMA_MDMA_C4TCR_DBURST_Pos = 0xf        // Position of DBURST field.
	MDMA_MDMA_C4TCR_DBURST_Msk = 0x38000    // Bit mask of DBURST field.
	MDMA_MDMA_C4TCR_TLEN_Pos   = 0x12       // Position of TLEN field.
	MDMA_MDMA_C4TCR_TLEN_Msk   = 0x1fc0000  // Bit mask of TLEN field.
	MDMA_MDMA_C4TCR_PKE_Pos    = 0x19       // Position of PKE field.
	MDMA_MDMA_C4TCR_PKE_Msk    = 0x2000000  // Bit mask of PKE field.
	MDMA_MDMA_C4TCR_PKE        = 0x2000000  // Bit PKE.
	MDMA_MDMA_C4TCR_PAM_Pos    = 0x1a       // Position of PAM field.
	MDMA_MDMA_C4TCR_PAM_Msk    = 0xc000000  // Bit mask of PAM field.
	MDMA_MDMA_C4TCR_TRGM_Pos   = 0x1c       // Position of TRGM field.
	MDMA_MDMA_C4TCR_TRGM_Msk   = 0x30000000 // Bit mask of TRGM field.
	MDMA_MDMA_C4TCR_SWRM_Pos   = 0x1e       // Position of SWRM field.
	MDMA_MDMA_C4TCR_SWRM_Msk   = 0x40000000 // Bit mask of SWRM field.
	MDMA_MDMA_C4TCR_SWRM       = 0x40000000 // Bit SWRM.
	MDMA_MDMA_C4TCR_BWM_Pos    = 0x1f       // Position of BWM field.
	MDMA_MDMA_C4TCR_BWM_Msk    = 0x80000000 // Bit mask of BWM field.
	MDMA_MDMA_C4TCR_BWM        = 0x80000000 // Bit BWM.

	// MDMA_C4BNDTR: MDMA Channel x block number of data           register
	MDMA_MDMA_C4BNDTR_BNDT_Pos  = 0x0        // Position of BNDT field.
	MDMA_MDMA_C4BNDTR_BNDT_Msk  = 0x1ffff    // Bit mask of BNDT field.
	MDMA_MDMA_C4BNDTR_BRSUM_Pos = 0x12       // Position of BRSUM field.
	MDMA_MDMA_C4BNDTR_BRSUM_Msk = 0x40000    // Bit mask of BRSUM field.
	MDMA_MDMA_C4BNDTR_BRSUM     = 0x40000    // Bit BRSUM.
	MDMA_MDMA_C4BNDTR_BRDUM_Pos = 0x13       // Position of BRDUM field.
	MDMA_MDMA_C4BNDTR_BRDUM_Msk = 0x80000    // Bit mask of BRDUM field.
	MDMA_MDMA_C4BNDTR_BRDUM     = 0x80000    // Bit BRDUM.
	MDMA_MDMA_C4BNDTR_BRC_Pos   = 0x14       // Position of BRC field.
	MDMA_MDMA_C4BNDTR_BRC_Msk   = 0xfff00000 // Bit mask of BRC field.

	// MDMA_C4SAR: MDMA channel x source address           register
	MDMA_MDMA_C4SAR_SAR_Pos = 0x0        // Position of SAR field.
	MDMA_MDMA_C4SAR_SAR_Msk = 0xffffffff // Bit mask of SAR field.

	// MDMA_C4DAR: MDMA channel x destination address           register
	MDMA_MDMA_C4DAR_DAR_Pos = 0x0        // Position of DAR field.
	MDMA_MDMA_C4DAR_DAR_Msk = 0xffffffff // Bit mask of DAR field.

	// MDMA_C4BRUR: MDMA channel x Block Repeat address Update           register
	MDMA_MDMA_C4BRUR_SUV_Pos = 0x0        // Position of SUV field.
	MDMA_MDMA_C4BRUR_SUV_Msk = 0xffff     // Bit mask of SUV field.
	MDMA_MDMA_C4BRUR_DUV_Pos = 0x10       // Position of DUV field.
	MDMA_MDMA_C4BRUR_DUV_Msk = 0xffff0000 // Bit mask of DUV field.

	// MDMA_C4LAR: MDMA channel x Link Address           register
	MDMA_MDMA_C4LAR_LAR_Pos = 0x0        // Position of LAR field.
	MDMA_MDMA_C4LAR_LAR_Msk = 0xffffffff // Bit mask of LAR field.

	// MDMA_C4TBR: MDMA channel x Trigger and Bus selection           Register
	MDMA_MDMA_C4TBR_TSEL_Pos = 0x0     // Position of TSEL field.
	MDMA_MDMA_C4TBR_TSEL_Msk = 0x3f    // Bit mask of TSEL field.
	MDMA_MDMA_C4TBR_SBUS_Pos = 0x10    // Position of SBUS field.
	MDMA_MDMA_C4TBR_SBUS_Msk = 0x10000 // Bit mask of SBUS field.
	MDMA_MDMA_C4TBR_SBUS     = 0x10000 // Bit SBUS.
	MDMA_MDMA_C4TBR_DBUS_Pos = 0x11    // Position of DBUS field.
	MDMA_MDMA_C4TBR_DBUS_Msk = 0x20000 // Bit mask of DBUS field.
	MDMA_MDMA_C4TBR_DBUS     = 0x20000 // Bit DBUS.

	// MDMA_C4MAR: MDMA channel x Mask address           register
	MDMA_MDMA_C4MAR_MAR_Pos = 0x0        // Position of MAR field.
	MDMA_MDMA_C4MAR_MAR_Msk = 0xffffffff // Bit mask of MAR field.

	// MDMA_C4MDR: MDMA channel x Mask Data           register
	MDMA_MDMA_C4MDR_MDR_Pos = 0x0        // Position of MDR field.
	MDMA_MDMA_C4MDR_MDR_Msk = 0xffffffff // Bit mask of MDR field.

	// MDMA_C5ISR: MDMA channel x interrupt/status           register
	MDMA_MDMA_C5ISR_TEIF5_Pos  = 0x0     // Position of TEIF5 field.
	MDMA_MDMA_C5ISR_TEIF5_Msk  = 0x1     // Bit mask of TEIF5 field.
	MDMA_MDMA_C5ISR_TEIF5      = 0x1     // Bit TEIF5.
	MDMA_MDMA_C5ISR_CTCIF5_Pos = 0x1     // Position of CTCIF5 field.
	MDMA_MDMA_C5ISR_CTCIF5_Msk = 0x2     // Bit mask of CTCIF5 field.
	MDMA_MDMA_C5ISR_CTCIF5     = 0x2     // Bit CTCIF5.
	MDMA_MDMA_C5ISR_BRTIF5_Pos = 0x2     // Position of BRTIF5 field.
	MDMA_MDMA_C5ISR_BRTIF5_Msk = 0x4     // Bit mask of BRTIF5 field.
	MDMA_MDMA_C5ISR_BRTIF5     = 0x4     // Bit BRTIF5.
	MDMA_MDMA_C5ISR_BTIF5_Pos  = 0x3     // Position of BTIF5 field.
	MDMA_MDMA_C5ISR_BTIF5_Msk  = 0x8     // Bit mask of BTIF5 field.
	MDMA_MDMA_C5ISR_BTIF5      = 0x8     // Bit BTIF5.
	MDMA_MDMA_C5ISR_TCIF5_Pos  = 0x4     // Position of TCIF5 field.
	MDMA_MDMA_C5ISR_TCIF5_Msk  = 0x10    // Bit mask of TCIF5 field.
	MDMA_MDMA_C5ISR_TCIF5      = 0x10    // Bit TCIF5.
	MDMA_MDMA_C5ISR_CRQA5_Pos  = 0x10    // Position of CRQA5 field.
	MDMA_MDMA_C5ISR_CRQA5_Msk  = 0x10000 // Bit mask of CRQA5 field.
	MDMA_MDMA_C5ISR_CRQA5      = 0x10000 // Bit CRQA5.

	// MDMA_C5IFCR: MDMA channel x interrupt flag clear           register
	MDMA_MDMA_C5IFCR_CTEIF5_Pos  = 0x0  // Position of CTEIF5 field.
	MDMA_MDMA_C5IFCR_CTEIF5_Msk  = 0x1  // Bit mask of CTEIF5 field.
	MDMA_MDMA_C5IFCR_CTEIF5      = 0x1  // Bit CTEIF5.
	MDMA_MDMA_C5IFCR_CCTCIF5_Pos = 0x1  // Position of CCTCIF5 field.
	MDMA_MDMA_C5IFCR_CCTCIF5_Msk = 0x2  // Bit mask of CCTCIF5 field.
	MDMA_MDMA_C5IFCR_CCTCIF5     = 0x2  // Bit CCTCIF5.
	MDMA_MDMA_C5IFCR_CBRTIF5_Pos = 0x2  // Position of CBRTIF5 field.
	MDMA_MDMA_C5IFCR_CBRTIF5_Msk = 0x4  // Bit mask of CBRTIF5 field.
	MDMA_MDMA_C5IFCR_CBRTIF5     = 0x4  // Bit CBRTIF5.
	MDMA_MDMA_C5IFCR_CBTIF5_Pos  = 0x3  // Position of CBTIF5 field.
	MDMA_MDMA_C5IFCR_CBTIF5_Msk  = 0x8  // Bit mask of CBTIF5 field.
	MDMA_MDMA_C5IFCR_CBTIF5      = 0x8  // Bit CBTIF5.
	MDMA_MDMA_C5IFCR_CLTCIF5_Pos = 0x4  // Position of CLTCIF5 field.
	MDMA_MDMA_C5IFCR_CLTCIF5_Msk = 0x10 // Bit mask of CLTCIF5 field.
	MDMA_MDMA_C5IFCR_CLTCIF5     = 0x10 // Bit CLTCIF5.

	// MDMA_C5ESR: MDMA Channel x error status           register
	MDMA_MDMA_C5ESR_TEA_Pos  = 0x0   // Position of TEA field.
	MDMA_MDMA_C5ESR_TEA_Msk  = 0x7f  // Bit mask of TEA field.
	MDMA_MDMA_C5ESR_TED_Pos  = 0x7   // Position of TED field.
	MDMA_MDMA_C5ESR_TED_Msk  = 0x80  // Bit mask of TED field.
	MDMA_MDMA_C5ESR_TED      = 0x80  // Bit TED.
	MDMA_MDMA_C5ESR_TELD_Pos = 0x8   // Position of TELD field.
	MDMA_MDMA_C5ESR_TELD_Msk = 0x100 // Bit mask of TELD field.
	MDMA_MDMA_C5ESR_TELD     = 0x100 // Bit TELD.
	MDMA_MDMA_C5ESR_TEMD_Pos = 0x9   // Position of TEMD field.
	MDMA_MDMA_C5ESR_TEMD_Msk = 0x200 // Bit mask of TEMD field.
	MDMA_MDMA_C5ESR_TEMD     = 0x200 // Bit TEMD.
	MDMA_MDMA_C5ESR_ASE_Pos  = 0xa   // Position of ASE field.
	MDMA_MDMA_C5ESR_ASE_Msk  = 0x400 // Bit mask of ASE field.
	MDMA_MDMA_C5ESR_ASE      = 0x400 // Bit ASE.
	MDMA_MDMA_C5ESR_BSE_Pos  = 0xb   // Position of BSE field.
	MDMA_MDMA_C5ESR_BSE_Msk  = 0x800 // Bit mask of BSE field.
	MDMA_MDMA_C5ESR_BSE      = 0x800 // Bit BSE.

	// MDMA_C5CR: This register is used to control the           concerned channel.
	MDMA_MDMA_C5CR_EN_Pos    = 0x0     // Position of EN field.
	MDMA_MDMA_C5CR_EN_Msk    = 0x1     // Bit mask of EN field.
	MDMA_MDMA_C5CR_EN        = 0x1     // Bit EN.
	MDMA_MDMA_C5CR_TEIE_Pos  = 0x1     // Position of TEIE field.
	MDMA_MDMA_C5CR_TEIE_Msk  = 0x2     // Bit mask of TEIE field.
	MDMA_MDMA_C5CR_TEIE      = 0x2     // Bit TEIE.
	MDMA_MDMA_C5CR_CTCIE_Pos = 0x2     // Position of CTCIE field.
	MDMA_MDMA_C5CR_CTCIE_Msk = 0x4     // Bit mask of CTCIE field.
	MDMA_MDMA_C5CR_CTCIE     = 0x4     // Bit CTCIE.
	MDMA_MDMA_C5CR_BRTIE_Pos = 0x3     // Position of BRTIE field.
	MDMA_MDMA_C5CR_BRTIE_Msk = 0x8     // Bit mask of BRTIE field.
	MDMA_MDMA_C5CR_BRTIE     = 0x8     // Bit BRTIE.
	MDMA_MDMA_C5CR_BTIE_Pos  = 0x4     // Position of BTIE field.
	MDMA_MDMA_C5CR_BTIE_Msk  = 0x10    // Bit mask of BTIE field.
	MDMA_MDMA_C5CR_BTIE      = 0x10    // Bit BTIE.
	MDMA_MDMA_C5CR_TCIE_Pos  = 0x5     // Position of TCIE field.
	MDMA_MDMA_C5CR_TCIE_Msk  = 0x20    // Bit mask of TCIE field.
	MDMA_MDMA_C5CR_TCIE      = 0x20    // Bit TCIE.
	MDMA_MDMA_C5CR_PL_Pos    = 0x6     // Position of PL field.
	MDMA_MDMA_C5CR_PL_Msk    = 0xc0    // Bit mask of PL field.
	MDMA_MDMA_C5CR_BEX_Pos   = 0xc     // Position of BEX field.
	MDMA_MDMA_C5CR_BEX_Msk   = 0x1000  // Bit mask of BEX field.
	MDMA_MDMA_C5CR_BEX       = 0x1000  // Bit BEX.
	MDMA_MDMA_C5CR_HEX_Pos   = 0xd     // Position of HEX field.
	MDMA_MDMA_C5CR_HEX_Msk   = 0x2000  // Bit mask of HEX field.
	MDMA_MDMA_C5CR_HEX       = 0x2000  // Bit HEX.
	MDMA_MDMA_C5CR_WEX_Pos   = 0xe     // Position of WEX field.
	MDMA_MDMA_C5CR_WEX_Msk   = 0x4000  // Bit mask of WEX field.
	MDMA_MDMA_C5CR_WEX       = 0x4000  // Bit WEX.
	MDMA_MDMA_C5CR_SWRQ_Pos  = 0x10    // Position of SWRQ field.
	MDMA_MDMA_C5CR_SWRQ_Msk  = 0x10000 // Bit mask of SWRQ field.
	MDMA_MDMA_C5CR_SWRQ      = 0x10000 // Bit SWRQ.

	// MDMA_C5TCR: This register is used to configure the           concerned channel.
	MDMA_MDMA_C5TCR_SINC_Pos   = 0x0        // Position of SINC field.
	MDMA_MDMA_C5TCR_SINC_Msk   = 0x3        // Bit mask of SINC field.
	MDMA_MDMA_C5TCR_DINC_Pos   = 0x2        // Position of DINC field.
	MDMA_MDMA_C5TCR_DINC_Msk   = 0xc        // Bit mask of DINC field.
	MDMA_MDMA_C5TCR_SSIZE_Pos  = 0x4        // Position of SSIZE field.
	MDMA_MDMA_C5TCR_SSIZE_Msk  = 0x30       // Bit mask of SSIZE field.
	MDMA_MDMA_C5TCR_DSIZE_Pos  = 0x6        // Position of DSIZE field.
	MDMA_MDMA_C5TCR_DSIZE_Msk  = 0xc0       // Bit mask of DSIZE field.
	MDMA_MDMA_C5TCR_SINCOS_Pos = 0x8        // Position of SINCOS field.
	MDMA_MDMA_C5TCR_SINCOS_Msk = 0x300      // Bit mask of SINCOS field.
	MDMA_MDMA_C5TCR_DINCOS_Pos = 0xa        // Position of DINCOS field.
	MDMA_MDMA_C5TCR_DINCOS_Msk = 0xc00      // Bit mask of DINCOS field.
	MDMA_MDMA_C5TCR_SBURST_Pos = 0xc        // Position of SBURST field.
	MDMA_MDMA_C5TCR_SBURST_Msk = 0x7000     // Bit mask of SBURST field.
	MDMA_MDMA_C5TCR_DBURST_Pos = 0xf        // Position of DBURST field.
	MDMA_MDMA_C5TCR_DBURST_Msk = 0x38000    // Bit mask of DBURST field.
	MDMA_MDMA_C5TCR_TLEN_Pos   = 0x12       // Position of TLEN field.
	MDMA_MDMA_C5TCR_TLEN_Msk   = 0x1fc0000  // Bit mask of TLEN field.
	MDMA_MDMA_C5TCR_PKE_Pos    = 0x19       // Position of PKE field.
	MDMA_MDMA_C5TCR_PKE_Msk    = 0x2000000  // Bit mask of PKE field.
	MDMA_MDMA_C5TCR_PKE        = 0x2000000  // Bit PKE.
	MDMA_MDMA_C5TCR_PAM_Pos    = 0x1a       // Position of PAM field.
	MDMA_MDMA_C5TCR_PAM_Msk    = 0xc000000  // Bit mask of PAM field.
	MDMA_MDMA_C5TCR_TRGM_Pos   = 0x1c       // Position of TRGM field.
	MDMA_MDMA_C5TCR_TRGM_Msk   = 0x30000000 // Bit mask of TRGM field.
	MDMA_MDMA_C5TCR_SWRM_Pos   = 0x1e       // Position of SWRM field.
	MDMA_MDMA_C5TCR_SWRM_Msk   = 0x40000000 // Bit mask of SWRM field.
	MDMA_MDMA_C5TCR_SWRM       = 0x40000000 // Bit SWRM.
	MDMA_MDMA_C5TCR_BWM_Pos    = 0x1f       // Position of BWM field.
	MDMA_MDMA_C5TCR_BWM_Msk    = 0x80000000 // Bit mask of BWM field.
	MDMA_MDMA_C5TCR_BWM        = 0x80000000 // Bit BWM.

	// MDMA_C5BNDTR: MDMA Channel x block number of data           register
	MDMA_MDMA_C5BNDTR_BNDT_Pos  = 0x0        // Position of BNDT field.
	MDMA_MDMA_C5BNDTR_BNDT_Msk  = 0x1ffff    // Bit mask of BNDT field.
	MDMA_MDMA_C5BNDTR_BRSUM_Pos = 0x12       // Position of BRSUM field.
	MDMA_MDMA_C5BNDTR_BRSUM_Msk = 0x40000    // Bit mask of BRSUM field.
	MDMA_MDMA_C5BNDTR_BRSUM     = 0x40000    // Bit BRSUM.
	MDMA_MDMA_C5BNDTR_BRDUM_Pos = 0x13       // Position of BRDUM field.
	MDMA_MDMA_C5BNDTR_BRDUM_Msk = 0x80000    // Bit mask of BRDUM field.
	MDMA_MDMA_C5BNDTR_BRDUM     = 0x80000    // Bit BRDUM.
	MDMA_MDMA_C5BNDTR_BRC_Pos   = 0x14       // Position of BRC field.
	MDMA_MDMA_C5BNDTR_BRC_Msk   = 0xfff00000 // Bit mask of BRC field.

	// MDMA_C5SAR: MDMA channel x source address           register
	MDMA_MDMA_C5SAR_SAR_Pos = 0x0        // Position of SAR field.
	MDMA_MDMA_C5SAR_SAR_Msk = 0xffffffff // Bit mask of SAR field.

	// MDMA_C5DAR: MDMA channel x destination address           register
	MDMA_MDMA_C5DAR_DAR_Pos = 0x0        // Position of DAR field.
	MDMA_MDMA_C5DAR_DAR_Msk = 0xffffffff // Bit mask of DAR field.

	// MDMA_C5BRUR: MDMA channel x Block Repeat address Update           register
	MDMA_MDMA_C5BRUR_SUV_Pos = 0x0        // Position of SUV field.
	MDMA_MDMA_C5BRUR_SUV_Msk = 0xffff     // Bit mask of SUV field.
	MDMA_MDMA_C5BRUR_DUV_Pos = 0x10       // Position of DUV field.
	MDMA_MDMA_C5BRUR_DUV_Msk = 0xffff0000 // Bit mask of DUV field.

	// MDMA_C5LAR: MDMA channel x Link Address           register
	MDMA_MDMA_C5LAR_LAR_Pos = 0x0        // Position of LAR field.
	MDMA_MDMA_C5LAR_LAR_Msk = 0xffffffff // Bit mask of LAR field.

	// MDMA_C5TBR: MDMA channel x Trigger and Bus selection           Register
	MDMA_MDMA_C5TBR_TSEL_Pos = 0x0     // Position of TSEL field.
	MDMA_MDMA_C5TBR_TSEL_Msk = 0x3f    // Bit mask of TSEL field.
	MDMA_MDMA_C5TBR_SBUS_Pos = 0x10    // Position of SBUS field.
	MDMA_MDMA_C5TBR_SBUS_Msk = 0x10000 // Bit mask of SBUS field.
	MDMA_MDMA_C5TBR_SBUS     = 0x10000 // Bit SBUS.
	MDMA_MDMA_C5TBR_DBUS_Pos = 0x11    // Position of DBUS field.
	MDMA_MDMA_C5TBR_DBUS_Msk = 0x20000 // Bit mask of DBUS field.
	MDMA_MDMA_C5TBR_DBUS     = 0x20000 // Bit DBUS.

	// MDMA_C5MAR: MDMA channel x Mask address           register
	MDMA_MDMA_C5MAR_MAR_Pos = 0x0        // Position of MAR field.
	MDMA_MDMA_C5MAR_MAR_Msk = 0xffffffff // Bit mask of MAR field.

	// MDMA_C5MDR: MDMA channel x Mask Data           register
	MDMA_MDMA_C5MDR_MDR_Pos = 0x0        // Position of MDR field.
	MDMA_MDMA_C5MDR_MDR_Msk = 0xffffffff // Bit mask of MDR field.

	// MDMA_C6ISR: MDMA channel x interrupt/status           register
	MDMA_MDMA_C6ISR_TEIF6_Pos  = 0x0     // Position of TEIF6 field.
	MDMA_MDMA_C6ISR_TEIF6_Msk  = 0x1     // Bit mask of TEIF6 field.
	MDMA_MDMA_C6ISR_TEIF6      = 0x1     // Bit TEIF6.
	MDMA_MDMA_C6ISR_CTCIF6_Pos = 0x1     // Position of CTCIF6 field.
	MDMA_MDMA_C6ISR_CTCIF6_Msk = 0x2     // Bit mask of CTCIF6 field.
	MDMA_MDMA_C6ISR_CTCIF6     = 0x2     // Bit CTCIF6.
	MDMA_MDMA_C6ISR_BRTIF6_Pos = 0x2     // Position of BRTIF6 field.
	MDMA_MDMA_C6ISR_BRTIF6_Msk = 0x4     // Bit mask of BRTIF6 field.
	MDMA_MDMA_C6ISR_BRTIF6     = 0x4     // Bit BRTIF6.
	MDMA_MDMA_C6ISR_BTIF6_Pos  = 0x3     // Position of BTIF6 field.
	MDMA_MDMA_C6ISR_BTIF6_Msk  = 0x8     // Bit mask of BTIF6 field.
	MDMA_MDMA_C6ISR_BTIF6      = 0x8     // Bit BTIF6.
	MDMA_MDMA_C6ISR_TCIF6_Pos  = 0x4     // Position of TCIF6 field.
	MDMA_MDMA_C6ISR_TCIF6_Msk  = 0x10    // Bit mask of TCIF6 field.
	MDMA_MDMA_C6ISR_TCIF6      = 0x10    // Bit TCIF6.
	MDMA_MDMA_C6ISR_CRQA6_Pos  = 0x10    // Position of CRQA6 field.
	MDMA_MDMA_C6ISR_CRQA6_Msk  = 0x10000 // Bit mask of CRQA6 field.
	MDMA_MDMA_C6ISR_CRQA6      = 0x10000 // Bit CRQA6.

	// MDMA_C6IFCR: MDMA channel x interrupt flag clear           register
	MDMA_MDMA_C6IFCR_CTEIF6_Pos  = 0x0  // Position of CTEIF6 field.
	MDMA_MDMA_C6IFCR_CTEIF6_Msk  = 0x1  // Bit mask of CTEIF6 field.
	MDMA_MDMA_C6IFCR_CTEIF6      = 0x1  // Bit CTEIF6.
	MDMA_MDMA_C6IFCR_CCTCIF6_Pos = 0x1  // Position of CCTCIF6 field.
	MDMA_MDMA_C6IFCR_CCTCIF6_Msk = 0x2  // Bit mask of CCTCIF6 field.
	MDMA_MDMA_C6IFCR_CCTCIF6     = 0x2  // Bit CCTCIF6.
	MDMA_MDMA_C6IFCR_CBRTIF6_Pos = 0x2  // Position of CBRTIF6 field.
	MDMA_MDMA_C6IFCR_CBRTIF6_Msk = 0x4  // Bit mask of CBRTIF6 field.
	MDMA_MDMA_C6IFCR_CBRTIF6     = 0x4  // Bit CBRTIF6.
	MDMA_MDMA_C6IFCR_CBTIF6_Pos  = 0x3  // Position of CBTIF6 field.
	MDMA_MDMA_C6IFCR_CBTIF6_Msk  = 0x8  // Bit mask of CBTIF6 field.
	MDMA_MDMA_C6IFCR_CBTIF6      = 0x8  // Bit CBTIF6.
	MDMA_MDMA_C6IFCR_CLTCIF6_Pos = 0x4  // Position of CLTCIF6 field.
	MDMA_MDMA_C6IFCR_CLTCIF6_Msk = 0x10 // Bit mask of CLTCIF6 field.
	MDMA_MDMA_C6IFCR_CLTCIF6     = 0x10 // Bit CLTCIF6.

	// MDMA_C6ESR: MDMA Channel x error status           register
	MDMA_MDMA_C6ESR_TEA_Pos  = 0x0   // Position of TEA field.
	MDMA_MDMA_C6ESR_TEA_Msk  = 0x7f  // Bit mask of TEA field.
	MDMA_MDMA_C6ESR_TED_Pos  = 0x7   // Position of TED field.
	MDMA_MDMA_C6ESR_TED_Msk  = 0x80  // Bit mask of TED field.
	MDMA_MDMA_C6ESR_TED      = 0x80  // Bit TED.
	MDMA_MDMA_C6ESR_TELD_Pos = 0x8   // Position of TELD field.
	MDMA_MDMA_C6ESR_TELD_Msk = 0x100 // Bit mask of TELD field.
	MDMA_MDMA_C6ESR_TELD     = 0x100 // Bit TELD.
	MDMA_MDMA_C6ESR_TEMD_Pos = 0x9   // Position of TEMD field.
	MDMA_MDMA_C6ESR_TEMD_Msk = 0x200 // Bit mask of TEMD field.
	MDMA_MDMA_C6ESR_TEMD     = 0x200 // Bit TEMD.
	MDMA_MDMA_C6ESR_ASE_Pos  = 0xa   // Position of ASE field.
	MDMA_MDMA_C6ESR_ASE_Msk  = 0x400 // Bit mask of ASE field.
	MDMA_MDMA_C6ESR_ASE      = 0x400 // Bit ASE.
	MDMA_MDMA_C6ESR_BSE_Pos  = 0xb   // Position of BSE field.
	MDMA_MDMA_C6ESR_BSE_Msk  = 0x800 // Bit mask of BSE field.
	MDMA_MDMA_C6ESR_BSE      = 0x800 // Bit BSE.

	// MDMA_C6CR: This register is used to control the           concerned channel.
	MDMA_MDMA_C6CR_EN_Pos    = 0x0     // Position of EN field.
	MDMA_MDMA_C6CR_EN_Msk    = 0x1     // Bit mask of EN field.
	MDMA_MDMA_C6CR_EN        = 0x1     // Bit EN.
	MDMA_MDMA_C6CR_TEIE_Pos  = 0x1     // Position of TEIE field.
	MDMA_MDMA_C6CR_TEIE_Msk  = 0x2     // Bit mask of TEIE field.
	MDMA_MDMA_C6CR_TEIE      = 0x2     // Bit TEIE.
	MDMA_MDMA_C6CR_CTCIE_Pos = 0x2     // Position of CTCIE field.
	MDMA_MDMA_C6CR_CTCIE_Msk = 0x4     // Bit mask of CTCIE field.
	MDMA_MDMA_C6CR_CTCIE     = 0x4     // Bit CTCIE.
	MDMA_MDMA_C6CR_BRTIE_Pos = 0x3     // Position of BRTIE field.
	MDMA_MDMA_C6CR_BRTIE_Msk = 0x8     // Bit mask of BRTIE field.
	MDMA_MDMA_C6CR_BRTIE     = 0x8     // Bit BRTIE.
	MDMA_MDMA_C6CR_BTIE_Pos  = 0x4     // Position of BTIE field.
	MDMA_MDMA_C6CR_BTIE_Msk  = 0x10    // Bit mask of BTIE field.
	MDMA_MDMA_C6CR_BTIE      = 0x10    // Bit BTIE.
	MDMA_MDMA_C6CR_TCIE_Pos  = 0x5     // Position of TCIE field.
	MDMA_MDMA_C6CR_TCIE_Msk  = 0x20    // Bit mask of TCIE field.
	MDMA_MDMA_C6CR_TCIE      = 0x20    // Bit TCIE.
	MDMA_MDMA_C6CR_PL_Pos    = 0x6     // Position of PL field.
	MDMA_MDMA_C6CR_PL_Msk    = 0xc0    // Bit mask of PL field.
	MDMA_MDMA_C6CR_BEX_Pos   = 0xc     // Position of BEX field.
	MDMA_MDMA_C6CR_BEX_Msk   = 0x1000  // Bit mask of BEX field.
	MDMA_MDMA_C6CR_BEX       = 0x1000  // Bit BEX.
	MDMA_MDMA_C6CR_HEX_Pos   = 0xd     // Position of HEX field.
	MDMA_MDMA_C6CR_HEX_Msk   = 0x2000  // Bit mask of HEX field.
	MDMA_MDMA_C6CR_HEX       = 0x2000  // Bit HEX.
	MDMA_MDMA_C6CR_WEX_Pos   = 0xe     // Position of WEX field.
	MDMA_MDMA_C6CR_WEX_Msk   = 0x4000  // Bit mask of WEX field.
	MDMA_MDMA_C6CR_WEX       = 0x4000  // Bit WEX.
	MDMA_MDMA_C6CR_SWRQ_Pos  = 0x10    // Position of SWRQ field.
	MDMA_MDMA_C6CR_SWRQ_Msk  = 0x10000 // Bit mask of SWRQ field.
	MDMA_MDMA_C6CR_SWRQ      = 0x10000 // Bit SWRQ.

	// MDMA_C6TCR: This register is used to configure the           concerned channel.
	MDMA_MDMA_C6TCR_SINC_Pos   = 0x0        // Position of SINC field.
	MDMA_MDMA_C6TCR_SINC_Msk   = 0x3        // Bit mask of SINC field.
	MDMA_MDMA_C6TCR_DINC_Pos   = 0x2        // Position of DINC field.
	MDMA_MDMA_C6TCR_DINC_Msk   = 0xc        // Bit mask of DINC field.
	MDMA_MDMA_C6TCR_SSIZE_Pos  = 0x4        // Position of SSIZE field.
	MDMA_MDMA_C6TCR_SSIZE_Msk  = 0x30       // Bit mask of SSIZE field.
	MDMA_MDMA_C6TCR_DSIZE_Pos  = 0x6        // Position of DSIZE field.
	MDMA_MDMA_C6TCR_DSIZE_Msk  = 0xc0       // Bit mask of DSIZE field.
	MDMA_MDMA_C6TCR_SINCOS_Pos = 0x8        // Position of SINCOS field.
	MDMA_MDMA_C6TCR_SINCOS_Msk = 0x300      // Bit mask of SINCOS field.
	MDMA_MDMA_C6TCR_DINCOS_Pos = 0xa        // Position of DINCOS field.
	MDMA_MDMA_C6TCR_DINCOS_Msk = 0xc00      // Bit mask of DINCOS field.
	MDMA_MDMA_C6TCR_SBURST_Pos = 0xc        // Position of SBURST field.
	MDMA_MDMA_C6TCR_SBURST_Msk = 0x7000     // Bit mask of SBURST field.
	MDMA_MDMA_C6TCR_DBURST_Pos = 0xf        // Position of DBURST field.
	MDMA_MDMA_C6TCR_DBURST_Msk = 0x38000    // Bit mask of DBURST field.
	MDMA_MDMA_C6TCR_TLEN_Pos   = 0x12       // Position of TLEN field.
	MDMA_MDMA_C6TCR_TLEN_Msk   = 0x1fc0000  // Bit mask of TLEN field.
	MDMA_MDMA_C6TCR_PKE_Pos    = 0x19       // Position of PKE field.
	MDMA_MDMA_C6TCR_PKE_Msk    = 0x2000000  // Bit mask of PKE field.
	MDMA_MDMA_C6TCR_PKE        = 0x2000000  // Bit PKE.
	MDMA_MDMA_C6TCR_PAM_Pos    = 0x1a       // Position of PAM field.
	MDMA_MDMA_C6TCR_PAM_Msk    = 0xc000000  // Bit mask of PAM field.
	MDMA_MDMA_C6TCR_TRGM_Pos   = 0x1c       // Position of TRGM field.
	MDMA_MDMA_C6TCR_TRGM_Msk   = 0x30000000 // Bit mask of TRGM field.
	MDMA_MDMA_C6TCR_SWRM_Pos   = 0x1e       // Position of SWRM field.
	MDMA_MDMA_C6TCR_SWRM_Msk   = 0x40000000 // Bit mask of SWRM field.
	MDMA_MDMA_C6TCR_SWRM       = 0x40000000 // Bit SWRM.
	MDMA_MDMA_C6TCR_BWM_Pos    = 0x1f       // Position of BWM field.
	MDMA_MDMA_C6TCR_BWM_Msk    = 0x80000000 // Bit mask of BWM field.
	MDMA_MDMA_C6TCR_BWM        = 0x80000000 // Bit BWM.

	// MDMA_C6BNDTR: MDMA Channel x block number of data           register
	MDMA_MDMA_C6BNDTR_BNDT_Pos  = 0x0        // Position of BNDT field.
	MDMA_MDMA_C6BNDTR_BNDT_Msk  = 0x1ffff    // Bit mask of BNDT field.
	MDMA_MDMA_C6BNDTR_BRSUM_Pos = 0x12       // Position of BRSUM field.
	MDMA_MDMA_C6BNDTR_BRSUM_Msk = 0x40000    // Bit mask of BRSUM field.
	MDMA_MDMA_C6BNDTR_BRSUM     = 0x40000    // Bit BRSUM.
	MDMA_MDMA_C6BNDTR_BRDUM_Pos = 0x13       // Position of BRDUM field.
	MDMA_MDMA_C6BNDTR_BRDUM_Msk = 0x80000    // Bit mask of BRDUM field.
	MDMA_MDMA_C6BNDTR_BRDUM     = 0x80000    // Bit BRDUM.
	MDMA_MDMA_C6BNDTR_BRC_Pos   = 0x14       // Position of BRC field.
	MDMA_MDMA_C6BNDTR_BRC_Msk   = 0xfff00000 // Bit mask of BRC field.

	// MDMA_C6SAR: MDMA channel x source address           register
	MDMA_MDMA_C6SAR_SAR_Pos = 0x0        // Position of SAR field.
	MDMA_MDMA_C6SAR_SAR_Msk = 0xffffffff // Bit mask of SAR field.

	// MDMA_C6DAR: MDMA channel x destination address           register
	MDMA_MDMA_C6DAR_DAR_Pos = 0x0        // Position of DAR field.
	MDMA_MDMA_C6DAR_DAR_Msk = 0xffffffff // Bit mask of DAR field.

	// MDMA_C6BRUR: MDMA channel x Block Repeat address Update           register
	MDMA_MDMA_C6BRUR_SUV_Pos = 0x0        // Position of SUV field.
	MDMA_MDMA_C6BRUR_SUV_Msk = 0xffff     // Bit mask of SUV field.
	MDMA_MDMA_C6BRUR_DUV_Pos = 0x10       // Position of DUV field.
	MDMA_MDMA_C6BRUR_DUV_Msk = 0xffff0000 // Bit mask of DUV field.

	// MDMA_C6LAR: MDMA channel x Link Address           register
	MDMA_MDMA_C6LAR_LAR_Pos = 0x0        // Position of LAR field.
	MDMA_MDMA_C6LAR_LAR_Msk = 0xffffffff // Bit mask of LAR field.

	// MDMA_C6TBR: MDMA channel x Trigger and Bus selection           Register
	MDMA_MDMA_C6TBR_TSEL_Pos = 0x0     // Position of TSEL field.
	MDMA_MDMA_C6TBR_TSEL_Msk = 0x3f    // Bit mask of TSEL field.
	MDMA_MDMA_C6TBR_SBUS_Pos = 0x10    // Position of SBUS field.
	MDMA_MDMA_C6TBR_SBUS_Msk = 0x10000 // Bit mask of SBUS field.
	MDMA_MDMA_C6TBR_SBUS     = 0x10000 // Bit SBUS.
	MDMA_MDMA_C6TBR_DBUS_Pos = 0x11    // Position of DBUS field.
	MDMA_MDMA_C6TBR_DBUS_Msk = 0x20000 // Bit mask of DBUS field.
	MDMA_MDMA_C6TBR_DBUS     = 0x20000 // Bit DBUS.

	// MDMA_C6MAR: MDMA channel x Mask address           register
	MDMA_MDMA_C6MAR_MAR_Pos = 0x0        // Position of MAR field.
	MDMA_MDMA_C6MAR_MAR_Msk = 0xffffffff // Bit mask of MAR field.

	// MDMA_C6MDR: MDMA channel x Mask Data           register
	MDMA_MDMA_C6MDR_MDR_Pos = 0x0        // Position of MDR field.
	MDMA_MDMA_C6MDR_MDR_Msk = 0xffffffff // Bit mask of MDR field.

	// MDMA_C7ISR: MDMA channel x interrupt/status           register
	MDMA_MDMA_C7ISR_TEIF7_Pos  = 0x0     // Position of TEIF7 field.
	MDMA_MDMA_C7ISR_TEIF7_Msk  = 0x1     // Bit mask of TEIF7 field.
	MDMA_MDMA_C7ISR_TEIF7      = 0x1     // Bit TEIF7.
	MDMA_MDMA_C7ISR_CTCIF7_Pos = 0x1     // Position of CTCIF7 field.
	MDMA_MDMA_C7ISR_CTCIF7_Msk = 0x2     // Bit mask of CTCIF7 field.
	MDMA_MDMA_C7ISR_CTCIF7     = 0x2     // Bit CTCIF7.
	MDMA_MDMA_C7ISR_BRTIF7_Pos = 0x2     // Position of BRTIF7 field.
	MDMA_MDMA_C7ISR_BRTIF7_Msk = 0x4     // Bit mask of BRTIF7 field.
	MDMA_MDMA_C7ISR_BRTIF7     = 0x4     // Bit BRTIF7.
	MDMA_MDMA_C7ISR_BTIF7_Pos  = 0x3     // Position of BTIF7 field.
	MDMA_MDMA_C7ISR_BTIF7_Msk  = 0x8     // Bit mask of BTIF7 field.
	MDMA_MDMA_C7ISR_BTIF7      = 0x8     // Bit BTIF7.
	MDMA_MDMA_C7ISR_TCIF7_Pos  = 0x4     // Position of TCIF7 field.
	MDMA_MDMA_C7ISR_TCIF7_Msk  = 0x10    // Bit mask of TCIF7 field.
	MDMA_MDMA_C7ISR_TCIF7      = 0x10    // Bit TCIF7.
	MDMA_MDMA_C7ISR_CRQA7_Pos  = 0x10    // Position of CRQA7 field.
	MDMA_MDMA_C7ISR_CRQA7_Msk  = 0x10000 // Bit mask of CRQA7 field.
	MDMA_MDMA_C7ISR_CRQA7      = 0x10000 // Bit CRQA7.

	// MDMA_C7IFCR: MDMA channel x interrupt flag clear           register
	MDMA_MDMA_C7IFCR_CTEIF7_Pos  = 0x0  // Position of CTEIF7 field.
	MDMA_MDMA_C7IFCR_CTEIF7_Msk  = 0x1  // Bit mask of CTEIF7 field.
	MDMA_MDMA_C7IFCR_CTEIF7      = 0x1  // Bit CTEIF7.
	MDMA_MDMA_C7IFCR_CCTCIF7_Pos = 0x1  // Position of CCTCIF7 field.
	MDMA_MDMA_C7IFCR_CCTCIF7_Msk = 0x2  // Bit mask of CCTCIF7 field.
	MDMA_MDMA_C7IFCR_CCTCIF7     = 0x2  // Bit CCTCIF7.
	MDMA_MDMA_C7IFCR_CBRTIF7_Pos = 0x2  // Position of CBRTIF7 field.
	MDMA_MDMA_C7IFCR_CBRTIF7_Msk = 0x4  // Bit mask of CBRTIF7 field.
	MDMA_MDMA_C7IFCR_CBRTIF7     = 0x4  // Bit CBRTIF7.
	MDMA_MDMA_C7IFCR_CBTIF7_Pos  = 0x3  // Position of CBTIF7 field.
	MDMA_MDMA_C7IFCR_CBTIF7_Msk  = 0x8  // Bit mask of CBTIF7 field.
	MDMA_MDMA_C7IFCR_CBTIF7      = 0x8  // Bit CBTIF7.
	MDMA_MDMA_C7IFCR_CLTCIF7_Pos = 0x4  // Position of CLTCIF7 field.
	MDMA_MDMA_C7IFCR_CLTCIF7_Msk = 0x10 // Bit mask of CLTCIF7 field.
	MDMA_MDMA_C7IFCR_CLTCIF7     = 0x10 // Bit CLTCIF7.

	// MDMA_C7ESR: MDMA Channel x error status           register
	MDMA_MDMA_C7ESR_TEA_Pos  = 0x0   // Position of TEA field.
	MDMA_MDMA_C7ESR_TEA_Msk  = 0x7f  // Bit mask of TEA field.
	MDMA_MDMA_C7ESR_TED_Pos  = 0x7   // Position of TED field.
	MDMA_MDMA_C7ESR_TED_Msk  = 0x80  // Bit mask of TED field.
	MDMA_MDMA_C7ESR_TED      = 0x80  // Bit TED.
	MDMA_MDMA_C7ESR_TELD_Pos = 0x8   // Position of TELD field.
	MDMA_MDMA_C7ESR_TELD_Msk = 0x100 // Bit mask of TELD field.
	MDMA_MDMA_C7ESR_TELD     = 0x100 // Bit TELD.
	MDMA_MDMA_C7ESR_TEMD_Pos = 0x9   // Position of TEMD field.
	MDMA_MDMA_C7ESR_TEMD_Msk = 0x200 // Bit mask of TEMD field.
	MDMA_MDMA_C7ESR_TEMD     = 0x200 // Bit TEMD.
	MDMA_MDMA_C7ESR_ASE_Pos  = 0xa   // Position of ASE field.
	MDMA_MDMA_C7ESR_ASE_Msk  = 0x400 // Bit mask of ASE field.
	MDMA_MDMA_C7ESR_ASE      = 0x400 // Bit ASE.
	MDMA_MDMA_C7ESR_BSE_Pos  = 0xb   // Position of BSE field.
	MDMA_MDMA_C7ESR_BSE_Msk  = 0x800 // Bit mask of BSE field.
	MDMA_MDMA_C7ESR_BSE      = 0x800 // Bit BSE.

	// MDMA_C7CR: This register is used to control the           concerned channel.
	MDMA_MDMA_C7CR_EN_Pos    = 0x0     // Position of EN field.
	MDMA_MDMA_C7CR_EN_Msk    = 0x1     // Bit mask of EN field.
	MDMA_MDMA_C7CR_EN        = 0x1     // Bit EN.
	MDMA_MDMA_C7CR_TEIE_Pos  = 0x1     // Position of TEIE field.
	MDMA_MDMA_C7CR_TEIE_Msk  = 0x2     // Bit mask of TEIE field.
	MDMA_MDMA_C7CR_TEIE      = 0x2     // Bit TEIE.
	MDMA_MDMA_C7CR_CTCIE_Pos = 0x2     // Position of CTCIE field.
	MDMA_MDMA_C7CR_CTCIE_Msk = 0x4     // Bit mask of CTCIE field.
	MDMA_MDMA_C7CR_CTCIE     = 0x4     // Bit CTCIE.
	MDMA_MDMA_C7CR_BRTIE_Pos = 0x3     // Position of BRTIE field.
	MDMA_MDMA_C7CR_BRTIE_Msk = 0x8     // Bit mask of BRTIE field.
	MDMA_MDMA_C7CR_BRTIE     = 0x8     // Bit BRTIE.
	MDMA_MDMA_C7CR_BTIE_Pos  = 0x4     // Position of BTIE field.
	MDMA_MDMA_C7CR_BTIE_Msk  = 0x10    // Bit mask of BTIE field.
	MDMA_MDMA_C7CR_BTIE      = 0x10    // Bit BTIE.
	MDMA_MDMA_C7CR_TCIE_Pos  = 0x5     // Position of TCIE field.
	MDMA_MDMA_C7CR_TCIE_Msk  = 0x20    // Bit mask of TCIE field.
	MDMA_MDMA_C7CR_TCIE      = 0x20    // Bit TCIE.
	MDMA_MDMA_C7CR_PL_Pos    = 0x6     // Position of PL field.
	MDMA_MDMA_C7CR_PL_Msk    = 0xc0    // Bit mask of PL field.
	MDMA_MDMA_C7CR_BEX_Pos   = 0xc     // Position of BEX field.
	MDMA_MDMA_C7CR_BEX_Msk   = 0x1000  // Bit mask of BEX field.
	MDMA_MDMA_C7CR_BEX       = 0x1000  // Bit BEX.
	MDMA_MDMA_C7CR_HEX_Pos   = 0xd     // Position of HEX field.
	MDMA_MDMA_C7CR_HEX_Msk   = 0x2000  // Bit mask of HEX field.
	MDMA_MDMA_C7CR_HEX       = 0x2000  // Bit HEX.
	MDMA_MDMA_C7CR_WEX_Pos   = 0xe     // Position of WEX field.
	MDMA_MDMA_C7CR_WEX_Msk   = 0x4000  // Bit mask of WEX field.
	MDMA_MDMA_C7CR_WEX       = 0x4000  // Bit WEX.
	MDMA_MDMA_C7CR_SWRQ_Pos  = 0x10    // Position of SWRQ field.
	MDMA_MDMA_C7CR_SWRQ_Msk  = 0x10000 // Bit mask of SWRQ field.
	MDMA_MDMA_C7CR_SWRQ      = 0x10000 // Bit SWRQ.

	// MDMA_C7TCR: This register is used to configure the           concerned channel.
	MDMA_MDMA_C7TCR_SINC_Pos   = 0x0        // Position of SINC field.
	MDMA_MDMA_C7TCR_SINC_Msk   = 0x3        // Bit mask of SINC field.
	MDMA_MDMA_C7TCR_DINC_Pos   = 0x2        // Position of DINC field.
	MDMA_MDMA_C7TCR_DINC_Msk   = 0xc        // Bit mask of DINC field.
	MDMA_MDMA_C7TCR_SSIZE_Pos  = 0x4        // Position of SSIZE field.
	MDMA_MDMA_C7TCR_SSIZE_Msk  = 0x30       // Bit mask of SSIZE field.
	MDMA_MDMA_C7TCR_DSIZE_Pos  = 0x6        // Position of DSIZE field.
	MDMA_MDMA_C7TCR_DSIZE_Msk  = 0xc0       // Bit mask of DSIZE field.
	MDMA_MDMA_C7TCR_SINCOS_Pos = 0x8        // Position of SINCOS field.
	MDMA_MDMA_C7TCR_SINCOS_Msk = 0x300      // Bit mask of SINCOS field.
	MDMA_MDMA_C7TCR_DINCOS_Pos = 0xa        // Position of DINCOS field.
	MDMA_MDMA_C7TCR_DINCOS_Msk = 0xc00      // Bit mask of DINCOS field.
	MDMA_MDMA_C7TCR_SBURST_Pos = 0xc        // Position of SBURST field.
	MDMA_MDMA_C7TCR_SBURST_Msk = 0x7000     // Bit mask of SBURST field.
	MDMA_MDMA_C7TCR_DBURST_Pos = 0xf        // Position of DBURST field.
	MDMA_MDMA_C7TCR_DBURST_Msk = 0x38000    // Bit mask of DBURST field.
	MDMA_MDMA_C7TCR_TLEN_Pos   = 0x12       // Position of TLEN field.
	MDMA_MDMA_C7TCR_TLEN_Msk   = 0x1fc0000  // Bit mask of TLEN field.
	MDMA_MDMA_C7TCR_PKE_Pos    = 0x19       // Position of PKE field.
	MDMA_MDMA_C7TCR_PKE_Msk    = 0x2000000  // Bit mask of PKE field.
	MDMA_MDMA_C7TCR_PKE        = 0x2000000  // Bit PKE.
	MDMA_MDMA_C7TCR_PAM_Pos    = 0x1a       // Position of PAM field.
	MDMA_MDMA_C7TCR_PAM_Msk    = 0xc000000  // Bit mask of PAM field.
	MDMA_MDMA_C7TCR_TRGM_Pos   = 0x1c       // Position of TRGM field.
	MDMA_MDMA_C7TCR_TRGM_Msk   = 0x30000000 // Bit mask of TRGM field.
	MDMA_MDMA_C7TCR_SWRM_Pos   = 0x1e       // Position of SWRM field.
	MDMA_MDMA_C7TCR_SWRM_Msk   = 0x40000000 // Bit mask of SWRM field.
	MDMA_MDMA_C7TCR_SWRM       = 0x40000000 // Bit SWRM.
	MDMA_MDMA_C7TCR_BWM_Pos    = 0x1f       // Position of BWM field.
	MDMA_MDMA_C7TCR_BWM_Msk    = 0x80000000 // Bit mask of BWM field.
	MDMA_MDMA_C7TCR_BWM        = 0x80000000 // Bit BWM.

	// MDMA_C7BNDTR: MDMA Channel x block number of data           register
	MDMA_MDMA_C7BNDTR_BNDT_Pos  = 0x0        // Position of BNDT field.
	MDMA_MDMA_C7BNDTR_BNDT_Msk  = 0x1ffff    // Bit mask of BNDT field.
	MDMA_MDMA_C7BNDTR_BRSUM_Pos = 0x12       // Position of BRSUM field.
	MDMA_MDMA_C7BNDTR_BRSUM_Msk = 0x40000    // Bit mask of BRSUM field.
	MDMA_MDMA_C7BNDTR_BRSUM     = 0x40000    // Bit BRSUM.
	MDMA_MDMA_C7BNDTR_BRDUM_Pos = 0x13       // Position of BRDUM field.
	MDMA_MDMA_C7BNDTR_BRDUM_Msk = 0x80000    // Bit mask of BRDUM field.
	MDMA_MDMA_C7BNDTR_BRDUM     = 0x80000    // Bit BRDUM.
	MDMA_MDMA_C7BNDTR_BRC_Pos   = 0x14       // Position of BRC field.
	MDMA_MDMA_C7BNDTR_BRC_Msk   = 0xfff00000 // Bit mask of BRC field.

	// MDMA_C7SAR: MDMA channel x source address           register
	MDMA_MDMA_C7SAR_SAR_Pos = 0x0        // Position of SAR field.
	MDMA_MDMA_C7SAR_SAR_Msk = 0xffffffff // Bit mask of SAR field.

	// MDMA_C7DAR: MDMA channel x destination address           register
	MDMA_MDMA_C7DAR_DAR_Pos = 0x0        // Position of DAR field.
	MDMA_MDMA_C7DAR_DAR_Msk = 0xffffffff // Bit mask of DAR field.

	// MDMA_C7BRUR: MDMA channel x Block Repeat address Update           register
	MDMA_MDMA_C7BRUR_SUV_Pos = 0x0        // Position of SUV field.
	MDMA_MDMA_C7BRUR_SUV_Msk = 0xffff     // Bit mask of SUV field.
	MDMA_MDMA_C7BRUR_DUV_Pos = 0x10       // Position of DUV field.
	MDMA_MDMA_C7BRUR_DUV_Msk = 0xffff0000 // Bit mask of DUV field.

	// MDMA_C7LAR: MDMA channel x Link Address           register
	MDMA_MDMA_C7LAR_LAR_Pos = 0x0        // Position of LAR field.
	MDMA_MDMA_C7LAR_LAR_Msk = 0xffffffff // Bit mask of LAR field.

	// MDMA_C7TBR: MDMA channel x Trigger and Bus selection           Register
	MDMA_MDMA_C7TBR_TSEL_Pos = 0x0     // Position of TSEL field.
	MDMA_MDMA_C7TBR_TSEL_Msk = 0x3f    // Bit mask of TSEL field.
	MDMA_MDMA_C7TBR_SBUS_Pos = 0x10    // Position of SBUS field.
	MDMA_MDMA_C7TBR_SBUS_Msk = 0x10000 // Bit mask of SBUS field.
	MDMA_MDMA_C7TBR_SBUS     = 0x10000 // Bit SBUS.
	MDMA_MDMA_C7TBR_DBUS_Pos = 0x11    // Position of DBUS field.
	MDMA_MDMA_C7TBR_DBUS_Msk = 0x20000 // Bit mask of DBUS field.
	MDMA_MDMA_C7TBR_DBUS     = 0x20000 // Bit DBUS.

	// MDMA_C7MAR: MDMA channel x Mask address           register
	MDMA_MDMA_C7MAR_MAR_Pos = 0x0        // Position of MAR field.
	MDMA_MDMA_C7MAR_MAR_Msk = 0xffffffff // Bit mask of MAR field.

	// MDMA_C7MDR: MDMA channel x Mask Data           register
	MDMA_MDMA_C7MDR_MDR_Pos = 0x0        // Position of MDR field.
	MDMA_MDMA_C7MDR_MDR_Msk = 0xffffffff // Bit mask of MDR field.

	// MDMA_C8ISR: MDMA channel x interrupt/status           register
	MDMA_MDMA_C8ISR_TEIF8_Pos  = 0x0     // Position of TEIF8 field.
	MDMA_MDMA_C8ISR_TEIF8_Msk  = 0x1     // Bit mask of TEIF8 field.
	MDMA_MDMA_C8ISR_TEIF8      = 0x1     // Bit TEIF8.
	MDMA_MDMA_C8ISR_CTCIF8_Pos = 0x1     // Position of CTCIF8 field.
	MDMA_MDMA_C8ISR_CTCIF8_Msk = 0x2     // Bit mask of CTCIF8 field.
	MDMA_MDMA_C8ISR_CTCIF8     = 0x2     // Bit CTCIF8.
	MDMA_MDMA_C8ISR_BRTIF8_Pos = 0x2     // Position of BRTIF8 field.
	MDMA_MDMA_C8ISR_BRTIF8_Msk = 0x4     // Bit mask of BRTIF8 field.
	MDMA_MDMA_C8ISR_BRTIF8     = 0x4     // Bit BRTIF8.
	MDMA_MDMA_C8ISR_BTIF8_Pos  = 0x3     // Position of BTIF8 field.
	MDMA_MDMA_C8ISR_BTIF8_Msk  = 0x8     // Bit mask of BTIF8 field.
	MDMA_MDMA_C8ISR_BTIF8      = 0x8     // Bit BTIF8.
	MDMA_MDMA_C8ISR_TCIF8_Pos  = 0x4     // Position of TCIF8 field.
	MDMA_MDMA_C8ISR_TCIF8_Msk  = 0x10    // Bit mask of TCIF8 field.
	MDMA_MDMA_C8ISR_TCIF8      = 0x10    // Bit TCIF8.
	MDMA_MDMA_C8ISR_CRQA8_Pos  = 0x10    // Position of CRQA8 field.
	MDMA_MDMA_C8ISR_CRQA8_Msk  = 0x10000 // Bit mask of CRQA8 field.
	MDMA_MDMA_C8ISR_CRQA8      = 0x10000 // Bit CRQA8.

	// MDMA_C8IFCR: MDMA channel x interrupt flag clear           register
	MDMA_MDMA_C8IFCR_CTEIF8_Pos  = 0x0  // Position of CTEIF8 field.
	MDMA_MDMA_C8IFCR_CTEIF8_Msk  = 0x1  // Bit mask of CTEIF8 field.
	MDMA_MDMA_C8IFCR_CTEIF8      = 0x1  // Bit CTEIF8.
	MDMA_MDMA_C8IFCR_CCTCIF8_Pos = 0x1  // Position of CCTCIF8 field.
	MDMA_MDMA_C8IFCR_CCTCIF8_Msk = 0x2  // Bit mask of CCTCIF8 field.
	MDMA_MDMA_C8IFCR_CCTCIF8     = 0x2  // Bit CCTCIF8.
	MDMA_MDMA_C8IFCR_CBRTIF8_Pos = 0x2  // Position of CBRTIF8 field.
	MDMA_MDMA_C8IFCR_CBRTIF8_Msk = 0x4  // Bit mask of CBRTIF8 field.
	MDMA_MDMA_C8IFCR_CBRTIF8     = 0x4  // Bit CBRTIF8.
	MDMA_MDMA_C8IFCR_CBTIF8_Pos  = 0x3  // Position of CBTIF8 field.
	MDMA_MDMA_C8IFCR_CBTIF8_Msk  = 0x8  // Bit mask of CBTIF8 field.
	MDMA_MDMA_C8IFCR_CBTIF8      = 0x8  // Bit CBTIF8.
	MDMA_MDMA_C8IFCR_CLTCIF8_Pos = 0x4  // Position of CLTCIF8 field.
	MDMA_MDMA_C8IFCR_CLTCIF8_Msk = 0x10 // Bit mask of CLTCIF8 field.
	MDMA_MDMA_C8IFCR_CLTCIF8     = 0x10 // Bit CLTCIF8.

	// MDMA_C8ESR: MDMA Channel x error status           register
	MDMA_MDMA_C8ESR_TEA_Pos  = 0x0   // Position of TEA field.
	MDMA_MDMA_C8ESR_TEA_Msk  = 0x7f  // Bit mask of TEA field.
	MDMA_MDMA_C8ESR_TED_Pos  = 0x7   // Position of TED field.
	MDMA_MDMA_C8ESR_TED_Msk  = 0x80  // Bit mask of TED field.
	MDMA_MDMA_C8ESR_TED      = 0x80  // Bit TED.
	MDMA_MDMA_C8ESR_TELD_Pos = 0x8   // Position of TELD field.
	MDMA_MDMA_C8ESR_TELD_Msk = 0x100 // Bit mask of TELD field.
	MDMA_MDMA_C8ESR_TELD     = 0x100 // Bit TELD.
	MDMA_MDMA_C8ESR_TEMD_Pos = 0x9   // Position of TEMD field.
	MDMA_MDMA_C8ESR_TEMD_Msk = 0x200 // Bit mask of TEMD field.
	MDMA_MDMA_C8ESR_TEMD     = 0x200 // Bit TEMD.
	MDMA_MDMA_C8ESR_ASE_Pos  = 0xa   // Position of ASE field.
	MDMA_MDMA_C8ESR_ASE_Msk  = 0x400 // Bit mask of ASE field.
	MDMA_MDMA_C8ESR_ASE      = 0x400 // Bit ASE.
	MDMA_MDMA_C8ESR_BSE_Pos  = 0xb   // Position of BSE field.
	MDMA_MDMA_C8ESR_BSE_Msk  = 0x800 // Bit mask of BSE field.
	MDMA_MDMA_C8ESR_BSE      = 0x800 // Bit BSE.

	// MDMA_C8CR: This register is used to control the           concerned channel.
	MDMA_MDMA_C8CR_EN_Pos    = 0x0     // Position of EN field.
	MDMA_MDMA_C8CR_EN_Msk    = 0x1     // Bit mask of EN field.
	MDMA_MDMA_C8CR_EN        = 0x1     // Bit EN.
	MDMA_MDMA_C8CR_TEIE_Pos  = 0x1     // Position of TEIE field.
	MDMA_MDMA_C8CR_TEIE_Msk  = 0x2     // Bit mask of TEIE field.
	MDMA_MDMA_C8CR_TEIE      = 0x2     // Bit TEIE.
	MDMA_MDMA_C8CR_CTCIE_Pos = 0x2     // Position of CTCIE field.
	MDMA_MDMA_C8CR_CTCIE_Msk = 0x4     // Bit mask of CTCIE field.
	MDMA_MDMA_C8CR_CTCIE     = 0x4     // Bit CTCIE.
	MDMA_MDMA_C8CR_BRTIE_Pos = 0x3     // Position of BRTIE field.
	MDMA_MDMA_C8CR_BRTIE_Msk = 0x8     // Bit mask of BRTIE field.
	MDMA_MDMA_C8CR_BRTIE     = 0x8     // Bit BRTIE.
	MDMA_MDMA_C8CR_BTIE_Pos  = 0x4     // Position of BTIE field.
	MDMA_MDMA_C8CR_BTIE_Msk  = 0x10    // Bit mask of BTIE field.
	MDMA_MDMA_C8CR_BTIE      = 0x10    // Bit BTIE.
	MDMA_MDMA_C8CR_TCIE_Pos  = 0x5     // Position of TCIE field.
	MDMA_MDMA_C8CR_TCIE_Msk  = 0x20    // Bit mask of TCIE field.
	MDMA_MDMA_C8CR_TCIE      = 0x20    // Bit TCIE.
	MDMA_MDMA_C8CR_PL_Pos    = 0x6     // Position of PL field.
	MDMA_MDMA_C8CR_PL_Msk    = 0xc0    // Bit mask of PL field.
	MDMA_MDMA_C8CR_BEX_Pos   = 0xc     // Position of BEX field.
	MDMA_MDMA_C8CR_BEX_Msk   = 0x1000  // Bit mask of BEX field.
	MDMA_MDMA_C8CR_BEX       = 0x1000  // Bit BEX.
	MDMA_MDMA_C8CR_HEX_Pos   = 0xd     // Position of HEX field.
	MDMA_MDMA_C8CR_HEX_Msk   = 0x2000  // Bit mask of HEX field.
	MDMA_MDMA_C8CR_HEX       = 0x2000  // Bit HEX.
	MDMA_MDMA_C8CR_WEX_Pos   = 0xe     // Position of WEX field.
	MDMA_MDMA_C8CR_WEX_Msk   = 0x4000  // Bit mask of WEX field.
	MDMA_MDMA_C8CR_WEX       = 0x4000  // Bit WEX.
	MDMA_MDMA_C8CR_SWRQ_Pos  = 0x10    // Position of SWRQ field.
	MDMA_MDMA_C8CR_SWRQ_Msk  = 0x10000 // Bit mask of SWRQ field.
	MDMA_MDMA_C8CR_SWRQ      = 0x10000 // Bit SWRQ.

	// MDMA_C8TCR: This register is used to configure the           concerned channel.
	MDMA_MDMA_C8TCR_SINC_Pos   = 0x0        // Position of SINC field.
	MDMA_MDMA_C8TCR_SINC_Msk   = 0x3        // Bit mask of SINC field.
	MDMA_MDMA_C8TCR_DINC_Pos   = 0x2        // Position of DINC field.
	MDMA_MDMA_C8TCR_DINC_Msk   = 0xc        // Bit mask of DINC field.
	MDMA_MDMA_C8TCR_SSIZE_Pos  = 0x4        // Position of SSIZE field.
	MDMA_MDMA_C8TCR_SSIZE_Msk  = 0x30       // Bit mask of SSIZE field.
	MDMA_MDMA_C8TCR_DSIZE_Pos  = 0x6        // Position of DSIZE field.
	MDMA_MDMA_C8TCR_DSIZE_Msk  = 0xc0       // Bit mask of DSIZE field.
	MDMA_MDMA_C8TCR_SINCOS_Pos = 0x8        // Position of SINCOS field.
	MDMA_MDMA_C8TCR_SINCOS_Msk = 0x300      // Bit mask of SINCOS field.
	MDMA_MDMA_C8TCR_DINCOS_Pos = 0xa        // Position of DINCOS field.
	MDMA_MDMA_C8TCR_DINCOS_Msk = 0xc00      // Bit mask of DINCOS field.
	MDMA_MDMA_C8TCR_SBURST_Pos = 0xc        // Position of SBURST field.
	MDMA_MDMA_C8TCR_SBURST_Msk = 0x7000     // Bit mask of SBURST field.
	MDMA_MDMA_C8TCR_DBURST_Pos = 0xf        // Position of DBURST field.
	MDMA_MDMA_C8TCR_DBURST_Msk = 0x38000    // Bit mask of DBURST field.
	MDMA_MDMA_C8TCR_TLEN_Pos   = 0x12       // Position of TLEN field.
	MDMA_MDMA_C8TCR_TLEN_Msk   = 0x1fc0000  // Bit mask of TLEN field.
	MDMA_MDMA_C8TCR_PKE_Pos    = 0x19       // Position of PKE field.
	MDMA_MDMA_C8TCR_PKE_Msk    = 0x2000000  // Bit mask of PKE field.
	MDMA_MDMA_C8TCR_PKE        = 0x2000000  // Bit PKE.
	MDMA_MDMA_C8TCR_PAM_Pos    = 0x1a       // Position of PAM field.
	MDMA_MDMA_C8TCR_PAM_Msk    = 0xc000000  // Bit mask of PAM field.
	MDMA_MDMA_C8TCR_TRGM_Pos   = 0x1c       // Position of TRGM field.
	MDMA_MDMA_C8TCR_TRGM_Msk   = 0x30000000 // Bit mask of TRGM field.
	MDMA_MDMA_C8TCR_SWRM_Pos   = 0x1e       // Position of SWRM field.
	MDMA_MDMA_C8TCR_SWRM_Msk   = 0x40000000 // Bit mask of SWRM field.
	MDMA_MDMA_C8TCR_SWRM       = 0x40000000 // Bit SWRM.
	MDMA_MDMA_C8TCR_BWM_Pos    = 0x1f       // Position of BWM field.
	MDMA_MDMA_C8TCR_BWM_Msk    = 0x80000000 // Bit mask of BWM field.
	MDMA_MDMA_C8TCR_BWM        = 0x80000000 // Bit BWM.

	// MDMA_C8BNDTR: MDMA Channel x block number of data           register
	MDMA_MDMA_C8BNDTR_BNDT_Pos  = 0x0        // Position of BNDT field.
	MDMA_MDMA_C8BNDTR_BNDT_Msk  = 0x1ffff    // Bit mask of BNDT field.
	MDMA_MDMA_C8BNDTR_BRSUM_Pos = 0x12       // Position of BRSUM field.
	MDMA_MDMA_C8BNDTR_BRSUM_Msk = 0x40000    // Bit mask of BRSUM field.
	MDMA_MDMA_C8BNDTR_BRSUM     = 0x40000    // Bit BRSUM.
	MDMA_MDMA_C8BNDTR_BRDUM_Pos = 0x13       // Position of BRDUM field.
	MDMA_MDMA_C8BNDTR_BRDUM_Msk = 0x80000    // Bit mask of BRDUM field.
	MDMA_MDMA_C8BNDTR_BRDUM     = 0x80000    // Bit BRDUM.
	MDMA_MDMA_C8BNDTR_BRC_Pos   = 0x14       // Position of BRC field.
	MDMA_MDMA_C8BNDTR_BRC_Msk   = 0xfff00000 // Bit mask of BRC field.

	// MDMA_C8SAR: MDMA channel x source address           register
	MDMA_MDMA_C8SAR_SAR_Pos = 0x0        // Position of SAR field.
	MDMA_MDMA_C8SAR_SAR_Msk = 0xffffffff // Bit mask of SAR field.

	// MDMA_C8DAR: MDMA channel x destination address           register
	MDMA_MDMA_C8DAR_DAR_Pos = 0x0        // Position of DAR field.
	MDMA_MDMA_C8DAR_DAR_Msk = 0xffffffff // Bit mask of DAR field.

	// MDMA_C8BRUR: MDMA channel x Block Repeat address Update           register
	MDMA_MDMA_C8BRUR_SUV_Pos = 0x0        // Position of SUV field.
	MDMA_MDMA_C8BRUR_SUV_Msk = 0xffff     // Bit mask of SUV field.
	MDMA_MDMA_C8BRUR_DUV_Pos = 0x10       // Position of DUV field.
	MDMA_MDMA_C8BRUR_DUV_Msk = 0xffff0000 // Bit mask of DUV field.

	// MDMA_C8LAR: MDMA channel x Link Address           register
	MDMA_MDMA_C8LAR_LAR_Pos = 0x0        // Position of LAR field.
	MDMA_MDMA_C8LAR_LAR_Msk = 0xffffffff // Bit mask of LAR field.

	// MDMA_C8TBR: MDMA channel x Trigger and Bus selection           Register
	MDMA_MDMA_C8TBR_TSEL_Pos = 0x0     // Position of TSEL field.
	MDMA_MDMA_C8TBR_TSEL_Msk = 0x3f    // Bit mask of TSEL field.
	MDMA_MDMA_C8TBR_SBUS_Pos = 0x10    // Position of SBUS field.
	MDMA_MDMA_C8TBR_SBUS_Msk = 0x10000 // Bit mask of SBUS field.
	MDMA_MDMA_C8TBR_SBUS     = 0x10000 // Bit SBUS.
	MDMA_MDMA_C8TBR_DBUS_Pos = 0x11    // Position of DBUS field.
	MDMA_MDMA_C8TBR_DBUS_Msk = 0x20000 // Bit mask of DBUS field.
	MDMA_MDMA_C8TBR_DBUS     = 0x20000 // Bit DBUS.

	// MDMA_C8MAR: MDMA channel x Mask address           register
	MDMA_MDMA_C8MAR_MAR_Pos = 0x0        // Position of MAR field.
	MDMA_MDMA_C8MAR_MAR_Msk = 0xffffffff // Bit mask of MAR field.

	// MDMA_C8MDR: MDMA channel x Mask Data           register
	MDMA_MDMA_C8MDR_MDR_Pos = 0x0        // Position of MDR field.
	MDMA_MDMA_C8MDR_MDR_Msk = 0xffffffff // Bit mask of MDR field.

	// MDMA_C9ISR: MDMA channel x interrupt/status           register
	MDMA_MDMA_C9ISR_TEIF9_Pos  = 0x0     // Position of TEIF9 field.
	MDMA_MDMA_C9ISR_TEIF9_Msk  = 0x1     // Bit mask of TEIF9 field.
	MDMA_MDMA_C9ISR_TEIF9      = 0x1     // Bit TEIF9.
	MDMA_MDMA_C9ISR_CTCIF9_Pos = 0x1     // Position of CTCIF9 field.
	MDMA_MDMA_C9ISR_CTCIF9_Msk = 0x2     // Bit mask of CTCIF9 field.
	MDMA_MDMA_C9ISR_CTCIF9     = 0x2     // Bit CTCIF9.
	MDMA_MDMA_C9ISR_BRTIF9_Pos = 0x2     // Position of BRTIF9 field.
	MDMA_MDMA_C9ISR_BRTIF9_Msk = 0x4     // Bit mask of BRTIF9 field.
	MDMA_MDMA_C9ISR_BRTIF9     = 0x4     // Bit BRTIF9.
	MDMA_MDMA_C9ISR_BTIF9_Pos  = 0x3     // Position of BTIF9 field.
	MDMA_MDMA_C9ISR_BTIF9_Msk  = 0x8     // Bit mask of BTIF9 field.
	MDMA_MDMA_C9ISR_BTIF9      = 0x8     // Bit BTIF9.
	MDMA_MDMA_C9ISR_TCIF9_Pos  = 0x4     // Position of TCIF9 field.
	MDMA_MDMA_C9ISR_TCIF9_Msk  = 0x10    // Bit mask of TCIF9 field.
	MDMA_MDMA_C9ISR_TCIF9      = 0x10    // Bit TCIF9.
	MDMA_MDMA_C9ISR_CRQA9_Pos  = 0x10    // Position of CRQA9 field.
	MDMA_MDMA_C9ISR_CRQA9_Msk  = 0x10000 // Bit mask of CRQA9 field.
	MDMA_MDMA_C9ISR_CRQA9      = 0x10000 // Bit CRQA9.

	// MDMA_C9IFCR: MDMA channel x interrupt flag clear           register
	MDMA_MDMA_C9IFCR_CTEIF9_Pos  = 0x0  // Position of CTEIF9 field.
	MDMA_MDMA_C9IFCR_CTEIF9_Msk  = 0x1  // Bit mask of CTEIF9 field.
	MDMA_MDMA_C9IFCR_CTEIF9      = 0x1  // Bit CTEIF9.
	MDMA_MDMA_C9IFCR_CCTCIF9_Pos = 0x1  // Position of CCTCIF9 field.
	MDMA_MDMA_C9IFCR_CCTCIF9_Msk = 0x2  // Bit mask of CCTCIF9 field.
	MDMA_MDMA_C9IFCR_CCTCIF9     = 0x2  // Bit CCTCIF9.
	MDMA_MDMA_C9IFCR_CBRTIF9_Pos = 0x2  // Position of CBRTIF9 field.
	MDMA_MDMA_C9IFCR_CBRTIF9_Msk = 0x4  // Bit mask of CBRTIF9 field.
	MDMA_MDMA_C9IFCR_CBRTIF9     = 0x4  // Bit CBRTIF9.
	MDMA_MDMA_C9IFCR_CBTIF9_Pos  = 0x3  // Position of CBTIF9 field.
	MDMA_MDMA_C9IFCR_CBTIF9_Msk  = 0x8  // Bit mask of CBTIF9 field.
	MDMA_MDMA_C9IFCR_CBTIF9      = 0x8  // Bit CBTIF9.
	MDMA_MDMA_C9IFCR_CLTCIF9_Pos = 0x4  // Position of CLTCIF9 field.
	MDMA_MDMA_C9IFCR_CLTCIF9_Msk = 0x10 // Bit mask of CLTCIF9 field.
	MDMA_MDMA_C9IFCR_CLTCIF9     = 0x10 // Bit CLTCIF9.

	// MDMA_C9ESR: MDMA Channel x error status           register
	MDMA_MDMA_C9ESR_TEA_Pos  = 0x0   // Position of TEA field.
	MDMA_MDMA_C9ESR_TEA_Msk  = 0x7f  // Bit mask of TEA field.
	MDMA_MDMA_C9ESR_TED_Pos  = 0x7   // Position of TED field.
	MDMA_MDMA_C9ESR_TED_Msk  = 0x80  // Bit mask of TED field.
	MDMA_MDMA_C9ESR_TED      = 0x80  // Bit TED.
	MDMA_MDMA_C9ESR_TELD_Pos = 0x8   // Position of TELD field.
	MDMA_MDMA_C9ESR_TELD_Msk = 0x100 // Bit mask of TELD field.
	MDMA_MDMA_C9ESR_TELD     = 0x100 // Bit TELD.
	MDMA_MDMA_C9ESR_TEMD_Pos = 0x9   // Position of TEMD field.
	MDMA_MDMA_C9ESR_TEMD_Msk = 0x200 // Bit mask of TEMD field.
	MDMA_MDMA_C9ESR_TEMD     = 0x200 // Bit TEMD.
	MDMA_MDMA_C9ESR_ASE_Pos  = 0xa   // Position of ASE field.
	MDMA_MDMA_C9ESR_ASE_Msk  = 0x400 // Bit mask of ASE field.
	MDMA_MDMA_C9ESR_ASE      = 0x400 // Bit ASE.
	MDMA_MDMA_C9ESR_BSE_Pos  = 0xb   // Position of BSE field.
	MDMA_MDMA_C9ESR_BSE_Msk  = 0x800 // Bit mask of BSE field.
	MDMA_MDMA_C9ESR_BSE      = 0x800 // Bit BSE.

	// MDMA_C9CR: This register is used to control the           concerned channel.
	MDMA_MDMA_C9CR_EN_Pos    = 0x0     // Position of EN field.
	MDMA_MDMA_C9CR_EN_Msk    = 0x1     // Bit mask of EN field.
	MDMA_MDMA_C9CR_EN        = 0x1     // Bit EN.
	MDMA_MDMA_C9CR_TEIE_Pos  = 0x1     // Position of TEIE field.
	MDMA_MDMA_C9CR_TEIE_Msk  = 0x2     // Bit mask of TEIE field.
	MDMA_MDMA_C9CR_TEIE      = 0x2     // Bit TEIE.
	MDMA_MDMA_C9CR_CTCIE_Pos = 0x2     // Position of CTCIE field.
	MDMA_MDMA_C9CR_CTCIE_Msk = 0x4     // Bit mask of CTCIE field.
	MDMA_MDMA_C9CR_CTCIE     = 0x4     // Bit CTCIE.
	MDMA_MDMA_C9CR_BRTIE_Pos = 0x3     // Position of BRTIE field.
	MDMA_MDMA_C9CR_BRTIE_Msk = 0x8     // Bit mask of BRTIE field.
	MDMA_MDMA_C9CR_BRTIE     = 0x8     // Bit BRTIE.
	MDMA_MDMA_C9CR_BTIE_Pos  = 0x4     // Position of BTIE field.
	MDMA_MDMA_C9CR_BTIE_Msk  = 0x10    // Bit mask of BTIE field.
	MDMA_MDMA_C9CR_BTIE      = 0x10    // Bit BTIE.
	MDMA_MDMA_C9CR_TCIE_Pos  = 0x5     // Position of TCIE field.
	MDMA_MDMA_C9CR_TCIE_Msk  = 0x20    // Bit mask of TCIE field.
	MDMA_MDMA_C9CR_TCIE      = 0x20    // Bit TCIE.
	MDMA_MDMA_C9CR_PL_Pos    = 0x6     // Position of PL field.
	MDMA_MDMA_C9CR_PL_Msk    = 0xc0    // Bit mask of PL field.
	MDMA_MDMA_C9CR_BEX_Pos   = 0xc     // Position of BEX field.
	MDMA_MDMA_C9CR_BEX_Msk   = 0x1000  // Bit mask of BEX field.
	MDMA_MDMA_C9CR_BEX       = 0x1000  // Bit BEX.
	MDMA_MDMA_C9CR_HEX_Pos   = 0xd     // Position of HEX field.
	MDMA_MDMA_C9CR_HEX_Msk   = 0x2000  // Bit mask of HEX field.
	MDMA_MDMA_C9CR_HEX       = 0x2000  // Bit HEX.
	MDMA_MDMA_C9CR_WEX_Pos   = 0xe     // Position of WEX field.
	MDMA_MDMA_C9CR_WEX_Msk   = 0x4000  // Bit mask of WEX field.
	MDMA_MDMA_C9CR_WEX       = 0x4000  // Bit WEX.
	MDMA_MDMA_C9CR_SWRQ_Pos  = 0x10    // Position of SWRQ field.
	MDMA_MDMA_C9CR_SWRQ_Msk  = 0x10000 // Bit mask of SWRQ field.
	MDMA_MDMA_C9CR_SWRQ      = 0x10000 // Bit SWRQ.

	// MDMA_C9TCR: This register is used to configure the           concerned channel.
	MDMA_MDMA_C9TCR_SINC_Pos   = 0x0        // Position of SINC field.
	MDMA_MDMA_C9TCR_SINC_Msk   = 0x3        // Bit mask of SINC field.
	MDMA_MDMA_C9TCR_DINC_Pos   = 0x2        // Position of DINC field.
	MDMA_MDMA_C9TCR_DINC_Msk   = 0xc        // Bit mask of DINC field.
	MDMA_MDMA_C9TCR_SSIZE_Pos  = 0x4        // Position of SSIZE field.
	MDMA_MDMA_C9TCR_SSIZE_Msk  = 0x30       // Bit mask of SSIZE field.
	MDMA_MDMA_C9TCR_DSIZE_Pos  = 0x6        // Position of DSIZE field.
	MDMA_MDMA_C9TCR_DSIZE_Msk  = 0xc0       // Bit mask of DSIZE field.
	MDMA_MDMA_C9TCR_SINCOS_Pos = 0x8        // Position of SINCOS field.
	MDMA_MDMA_C9TCR_SINCOS_Msk = 0x300      // Bit mask of SINCOS field.
	MDMA_MDMA_C9TCR_DINCOS_Pos = 0xa        // Position of DINCOS field.
	MDMA_MDMA_C9TCR_DINCOS_Msk = 0xc00      // Bit mask of DINCOS field.
	MDMA_MDMA_C9TCR_SBURST_Pos = 0xc        // Position of SBURST field.
	MDMA_MDMA_C9TCR_SBURST_Msk = 0x7000     // Bit mask of SBURST field.
	MDMA_MDMA_C9TCR_DBURST_Pos = 0xf        // Position of DBURST field.
	MDMA_MDMA_C9TCR_DBURST_Msk = 0x38000    // Bit mask of DBURST field.
	MDMA_MDMA_C9TCR_TLEN_Pos   = 0x12       // Position of TLEN field.
	MDMA_MDMA_C9TCR_TLEN_Msk   = 0x1fc0000  // Bit mask of TLEN field.
	MDMA_MDMA_C9TCR_PKE_Pos    = 0x19       // Position of PKE field.
	MDMA_MDMA_C9TCR_PKE_Msk    = 0x2000000  // Bit mask of PKE field.
	MDMA_MDMA_C9TCR_PKE        = 0x2000000  // Bit PKE.
	MDMA_MDMA_C9TCR_PAM_Pos    = 0x1a       // Position of PAM field.
	MDMA_MDMA_C9TCR_PAM_Msk    = 0xc000000  // Bit mask of PAM field.
	MDMA_MDMA_C9TCR_TRGM_Pos   = 0x1c       // Position of TRGM field.
	MDMA_MDMA_C9TCR_TRGM_Msk   = 0x30000000 // Bit mask of TRGM field.
	MDMA_MDMA_C9TCR_SWRM_Pos   = 0x1e       // Position of SWRM field.
	MDMA_MDMA_C9TCR_SWRM_Msk   = 0x40000000 // Bit mask of SWRM field.
	MDMA_MDMA_C9TCR_SWRM       = 0x40000000 // Bit SWRM.
	MDMA_MDMA_C9TCR_BWM_Pos    = 0x1f       // Position of BWM field.
	MDMA_MDMA_C9TCR_BWM_Msk    = 0x80000000 // Bit mask of BWM field.
	MDMA_MDMA_C9TCR_BWM        = 0x80000000 // Bit BWM.

	// MDMA_C9BNDTR: MDMA Channel x block number of data           register
	MDMA_MDMA_C9BNDTR_BNDT_Pos  = 0x0        // Position of BNDT field.
	MDMA_MDMA_C9BNDTR_BNDT_Msk  = 0x1ffff    // Bit mask of BNDT field.
	MDMA_MDMA_C9BNDTR_BRSUM_Pos = 0x12       // Position of BRSUM field.
	MDMA_MDMA_C9BNDTR_BRSUM_Msk = 0x40000    // Bit mask of BRSUM field.
	MDMA_MDMA_C9BNDTR_BRSUM     = 0x40000    // Bit BRSUM.
	MDMA_MDMA_C9BNDTR_BRDUM_Pos = 0x13       // Position of BRDUM field.
	MDMA_MDMA_C9BNDTR_BRDUM_Msk = 0x80000    // Bit mask of BRDUM field.
	MDMA_MDMA_C9BNDTR_BRDUM     = 0x80000    // Bit BRDUM.
	MDMA_MDMA_C9BNDTR_BRC_Pos   = 0x14       // Position of BRC field.
	MDMA_MDMA_C9BNDTR_BRC_Msk   = 0xfff00000 // Bit mask of BRC field.

	// MDMA_C9SAR: MDMA channel x source address           register
	MDMA_MDMA_C9SAR_SAR_Pos = 0x0        // Position of SAR field.
	MDMA_MDMA_C9SAR_SAR_Msk = 0xffffffff // Bit mask of SAR field.

	// MDMA_C9DAR: MDMA channel x destination address           register
	MDMA_MDMA_C9DAR_DAR_Pos = 0x0        // Position of DAR field.
	MDMA_MDMA_C9DAR_DAR_Msk = 0xffffffff // Bit mask of DAR field.

	// MDMA_C9BRUR: MDMA channel x Block Repeat address Update           register
	MDMA_MDMA_C9BRUR_SUV_Pos = 0x0        // Position of SUV field.
	MDMA_MDMA_C9BRUR_SUV_Msk = 0xffff     // Bit mask of SUV field.
	MDMA_MDMA_C9BRUR_DUV_Pos = 0x10       // Position of DUV field.
	MDMA_MDMA_C9BRUR_DUV_Msk = 0xffff0000 // Bit mask of DUV field.

	// MDMA_C9LAR: MDMA channel x Link Address           register
	MDMA_MDMA_C9LAR_LAR_Pos = 0x0        // Position of LAR field.
	MDMA_MDMA_C9LAR_LAR_Msk = 0xffffffff // Bit mask of LAR field.

	// MDMA_C9TBR: MDMA channel x Trigger and Bus selection           Register
	MDMA_MDMA_C9TBR_TSEL_Pos = 0x0     // Position of TSEL field.
	MDMA_MDMA_C9TBR_TSEL_Msk = 0x3f    // Bit mask of TSEL field.
	MDMA_MDMA_C9TBR_SBUS_Pos = 0x10    // Position of SBUS field.
	MDMA_MDMA_C9TBR_SBUS_Msk = 0x10000 // Bit mask of SBUS field.
	MDMA_MDMA_C9TBR_SBUS     = 0x10000 // Bit SBUS.
	MDMA_MDMA_C9TBR_DBUS_Pos = 0x11    // Position of DBUS field.
	MDMA_MDMA_C9TBR_DBUS_Msk = 0x20000 // Bit mask of DBUS field.
	MDMA_MDMA_C9TBR_DBUS     = 0x20000 // Bit DBUS.

	// MDMA_C9MAR: MDMA channel x Mask address           register
	MDMA_MDMA_C9MAR_MAR_Pos = 0x0        // Position of MAR field.
	MDMA_MDMA_C9MAR_MAR_Msk = 0xffffffff // Bit mask of MAR field.

	// MDMA_C9MDR: MDMA channel x Mask Data           register
	MDMA_MDMA_C9MDR_MDR_Pos = 0x0        // Position of MDR field.
	MDMA_MDMA_C9MDR_MDR_Msk = 0xffffffff // Bit mask of MDR field.

	// MDMA_C10ISR: MDMA channel x interrupt/status           register
	MDMA_MDMA_C10ISR_TEIF10_Pos  = 0x0     // Position of TEIF10 field.
	MDMA_MDMA_C10ISR_TEIF10_Msk  = 0x1     // Bit mask of TEIF10 field.
	MDMA_MDMA_C10ISR_TEIF10      = 0x1     // Bit TEIF10.
	MDMA_MDMA_C10ISR_CTCIF10_Pos = 0x1     // Position of CTCIF10 field.
	MDMA_MDMA_C10ISR_CTCIF10_Msk = 0x2     // Bit mask of CTCIF10 field.
	MDMA_MDMA_C10ISR_CTCIF10     = 0x2     // Bit CTCIF10.
	MDMA_MDMA_C10ISR_BRTIF10_Pos = 0x2     // Position of BRTIF10 field.
	MDMA_MDMA_C10ISR_BRTIF10_Msk = 0x4     // Bit mask of BRTIF10 field.
	MDMA_MDMA_C10ISR_BRTIF10     = 0x4     // Bit BRTIF10.
	MDMA_MDMA_C10ISR_BTIF10_Pos  = 0x3     // Position of BTIF10 field.
	MDMA_MDMA_C10ISR_BTIF10_Msk  = 0x8     // Bit mask of BTIF10 field.
	MDMA_MDMA_C10ISR_BTIF10      = 0x8     // Bit BTIF10.
	MDMA_MDMA_C10ISR_TCIF10_Pos  = 0x4     // Position of TCIF10 field.
	MDMA_MDMA_C10ISR_TCIF10_Msk  = 0x10    // Bit mask of TCIF10 field.
	MDMA_MDMA_C10ISR_TCIF10      = 0x10    // Bit TCIF10.
	MDMA_MDMA_C10ISR_CRQA10_Pos  = 0x10    // Position of CRQA10 field.
	MDMA_MDMA_C10ISR_CRQA10_Msk  = 0x10000 // Bit mask of CRQA10 field.
	MDMA_MDMA_C10ISR_CRQA10      = 0x10000 // Bit CRQA10.

	// MDMA_C10IFCR: MDMA channel x interrupt flag clear           register
	MDMA_MDMA_C10IFCR_CTEIF10_Pos  = 0x0  // Position of CTEIF10 field.
	MDMA_MDMA_C10IFCR_CTEIF10_Msk  = 0x1  // Bit mask of CTEIF10 field.
	MDMA_MDMA_C10IFCR_CTEIF10      = 0x1  // Bit CTEIF10.
	MDMA_MDMA_C10IFCR_CCTCIF10_Pos = 0x1  // Position of CCTCIF10 field.
	MDMA_MDMA_C10IFCR_CCTCIF10_Msk = 0x2  // Bit mask of CCTCIF10 field.
	MDMA_MDMA_C10IFCR_CCTCIF10     = 0x2  // Bit CCTCIF10.
	MDMA_MDMA_C10IFCR_CBRTIF10_Pos = 0x2  // Position of CBRTIF10 field.
	MDMA_MDMA_C10IFCR_CBRTIF10_Msk = 0x4  // Bit mask of CBRTIF10 field.
	MDMA_MDMA_C10IFCR_CBRTIF10     = 0x4  // Bit CBRTIF10.
	MDMA_MDMA_C10IFCR_CBTIF10_Pos  = 0x3  // Position of CBTIF10 field.
	MDMA_MDMA_C10IFCR_CBTIF10_Msk  = 0x8  // Bit mask of CBTIF10 field.
	MDMA_MDMA_C10IFCR_CBTIF10      = 0x8  // Bit CBTIF10.
	MDMA_MDMA_C10IFCR_CLTCIF10_Pos = 0x4  // Position of CLTCIF10 field.
	MDMA_MDMA_C10IFCR_CLTCIF10_Msk = 0x10 // Bit mask of CLTCIF10 field.
	MDMA_MDMA_C10IFCR_CLTCIF10     = 0x10 // Bit CLTCIF10.

	// MDMA_C10ESR: MDMA Channel x error status           register
	MDMA_MDMA_C10ESR_TEA_Pos  = 0x0   // Position of TEA field.
	MDMA_MDMA_C10ESR_TEA_Msk  = 0x7f  // Bit mask of TEA field.
	MDMA_MDMA_C10ESR_TED_Pos  = 0x7   // Position of TED field.
	MDMA_MDMA_C10ESR_TED_Msk  = 0x80  // Bit mask of TED field.
	MDMA_MDMA_C10ESR_TED      = 0x80  // Bit TED.
	MDMA_MDMA_C10ESR_TELD_Pos = 0x8   // Position of TELD field.
	MDMA_MDMA_C10ESR_TELD_Msk = 0x100 // Bit mask of TELD field.
	MDMA_MDMA_C10ESR_TELD     = 0x100 // Bit TELD.
	MDMA_MDMA_C10ESR_TEMD_Pos = 0x9   // Position of TEMD field.
	MDMA_MDMA_C10ESR_TEMD_Msk = 0x200 // Bit mask of TEMD field.
	MDMA_MDMA_C10ESR_TEMD     = 0x200 // Bit TEMD.
	MDMA_MDMA_C10ESR_ASE_Pos  = 0xa   // Position of ASE field.
	MDMA_MDMA_C10ESR_ASE_Msk  = 0x400 // Bit mask of ASE field.
	MDMA_MDMA_C10ESR_ASE      = 0x400 // Bit ASE.
	MDMA_MDMA_C10ESR_BSE_Pos  = 0xb   // Position of BSE field.
	MDMA_MDMA_C10ESR_BSE_Msk  = 0x800 // Bit mask of BSE field.
	MDMA_MDMA_C10ESR_BSE      = 0x800 // Bit BSE.

	// MDMA_C10CR: This register is used to control the           concerned channel.
	MDMA_MDMA_C10CR_EN_Pos    = 0x0     // Position of EN field.
	MDMA_MDMA_C10CR_EN_Msk    = 0x1     // Bit mask of EN field.
	MDMA_MDMA_C10CR_EN        = 0x1     // Bit EN.
	MDMA_MDMA_C10CR_TEIE_Pos  = 0x1     // Position of TEIE field.
	MDMA_MDMA_C10CR_TEIE_Msk  = 0x2     // Bit mask of TEIE field.
	MDMA_MDMA_C10CR_TEIE      = 0x2     // Bit TEIE.
	MDMA_MDMA_C10CR_CTCIE_Pos = 0x2     // Position of CTCIE field.
	MDMA_MDMA_C10CR_CTCIE_Msk = 0x4     // Bit mask of CTCIE field.
	MDMA_MDMA_C10CR_CTCIE     = 0x4     // Bit CTCIE.
	MDMA_MDMA_C10CR_BRTIE_Pos = 0x3     // Position of BRTIE field.
	MDMA_MDMA_C10CR_BRTIE_Msk = 0x8     // Bit mask of BRTIE field.
	MDMA_MDMA_C10CR_BRTIE     = 0x8     // Bit BRTIE.
	MDMA_MDMA_C10CR_BTIE_Pos  = 0x4     // Position of BTIE field.
	MDMA_MDMA_C10CR_BTIE_Msk  = 0x10    // Bit mask of BTIE field.
	MDMA_MDMA_C10CR_BTIE      = 0x10    // Bit BTIE.
	MDMA_MDMA_C10CR_TCIE_Pos  = 0x5     // Position of TCIE field.
	MDMA_MDMA_C10CR_TCIE_Msk  = 0x20    // Bit mask of TCIE field.
	MDMA_MDMA_C10CR_TCIE      = 0x20    // Bit TCIE.
	MDMA_MDMA_C10CR_PL_Pos    = 0x6     // Position of PL field.
	MDMA_MDMA_C10CR_PL_Msk    = 0xc0    // Bit mask of PL field.
	MDMA_MDMA_C10CR_BEX_Pos   = 0xc     // Position of BEX field.
	MDMA_MDMA_C10CR_BEX_Msk   = 0x1000  // Bit mask of BEX field.
	MDMA_MDMA_C10CR_BEX       = 0x1000  // Bit BEX.
	MDMA_MDMA_C10CR_HEX_Pos   = 0xd     // Position of HEX field.
	MDMA_MDMA_C10CR_HEX_Msk   = 0x2000  // Bit mask of HEX field.
	MDMA_MDMA_C10CR_HEX       = 0x2000  // Bit HEX.
	MDMA_MDMA_C10CR_WEX_Pos   = 0xe     // Position of WEX field.
	MDMA_MDMA_C10CR_WEX_Msk   = 0x4000  // Bit mask of WEX field.
	MDMA_MDMA_C10CR_WEX       = 0x4000  // Bit WEX.
	MDMA_MDMA_C10CR_SWRQ_Pos  = 0x10    // Position of SWRQ field.
	MDMA_MDMA_C10CR_SWRQ_Msk  = 0x10000 // Bit mask of SWRQ field.
	MDMA_MDMA_C10CR_SWRQ      = 0x10000 // Bit SWRQ.

	// MDMA_C10TCR: This register is used to configure the           concerned channel.
	MDMA_MDMA_C10TCR_SINC_Pos   = 0x0        // Position of SINC field.
	MDMA_MDMA_C10TCR_SINC_Msk   = 0x3        // Bit mask of SINC field.
	MDMA_MDMA_C10TCR_DINC_Pos   = 0x2        // Position of DINC field.
	MDMA_MDMA_C10TCR_DINC_Msk   = 0xc        // Bit mask of DINC field.
	MDMA_MDMA_C10TCR_SSIZE_Pos  = 0x4        // Position of SSIZE field.
	MDMA_MDMA_C10TCR_SSIZE_Msk  = 0x30       // Bit mask of SSIZE field.
	MDMA_MDMA_C10TCR_DSIZE_Pos  = 0x6        // Position of DSIZE field.
	MDMA_MDMA_C10TCR_DSIZE_Msk  = 0xc0       // Bit mask of DSIZE field.
	MDMA_MDMA_C10TCR_SINCOS_Pos = 0x8        // Position of SINCOS field.
	MDMA_MDMA_C10TCR_SINCOS_Msk = 0x300      // Bit mask of SINCOS field.
	MDMA_MDMA_C10TCR_DINCOS_Pos = 0xa        // Position of DINCOS field.
	MDMA_MDMA_C10TCR_DINCOS_Msk = 0xc00      // Bit mask of DINCOS field.
	MDMA_MDMA_C10TCR_SBURST_Pos = 0xc        // Position of SBURST field.
	MDMA_MDMA_C10TCR_SBURST_Msk = 0x7000     // Bit mask of SBURST field.
	MDMA_MDMA_C10TCR_DBURST_Pos = 0xf        // Position of DBURST field.
	MDMA_MDMA_C10TCR_DBURST_Msk = 0x38000    // Bit mask of DBURST field.
	MDMA_MDMA_C10TCR_TLEN_Pos   = 0x12       // Position of TLEN field.
	MDMA_MDMA_C10TCR_TLEN_Msk   = 0x1fc0000  // Bit mask of TLEN field.
	MDMA_MDMA_C10TCR_PKE_Pos    = 0x19       // Position of PKE field.
	MDMA_MDMA_C10TCR_PKE_Msk    = 0x2000000  // Bit mask of PKE field.
	MDMA_MDMA_C10TCR_PKE        = 0x2000000  // Bit PKE.
	MDMA_MDMA_C10TCR_PAM_Pos    = 0x1a       // Position of PAM field.
	MDMA_MDMA_C10TCR_PAM_Msk    = 0xc000000  // Bit mask of PAM field.
	MDMA_MDMA_C10TCR_TRGM_Pos   = 0x1c       // Position of TRGM field.
	MDMA_MDMA_C10TCR_TRGM_Msk   = 0x30000000 // Bit mask of TRGM field.
	MDMA_MDMA_C10TCR_SWRM_Pos   = 0x1e       // Position of SWRM field.
	MDMA_MDMA_C10TCR_SWRM_Msk   = 0x40000000 // Bit mask of SWRM field.
	MDMA_MDMA_C10TCR_SWRM       = 0x40000000 // Bit SWRM.
	MDMA_MDMA_C10TCR_BWM_Pos    = 0x1f       // Position of BWM field.
	MDMA_MDMA_C10TCR_BWM_Msk    = 0x80000000 // Bit mask of BWM field.
	MDMA_MDMA_C10TCR_BWM        = 0x80000000 // Bit BWM.

	// MDMA_C10BNDTR: MDMA Channel x block number of data           register
	MDMA_MDMA_C10BNDTR_BNDT_Pos  = 0x0        // Position of BNDT field.
	MDMA_MDMA_C10BNDTR_BNDT_Msk  = 0x1ffff    // Bit mask of BNDT field.
	MDMA_MDMA_C10BNDTR_BRSUM_Pos = 0x12       // Position of BRSUM field.
	MDMA_MDMA_C10BNDTR_BRSUM_Msk = 0x40000    // Bit mask of BRSUM field.
	MDMA_MDMA_C10BNDTR_BRSUM     = 0x40000    // Bit BRSUM.
	MDMA_MDMA_C10BNDTR_BRDUM_Pos = 0x13       // Position of BRDUM field.
	MDMA_MDMA_C10BNDTR_BRDUM_Msk = 0x80000    // Bit mask of BRDUM field.
	MDMA_MDMA_C10BNDTR_BRDUM     = 0x80000    // Bit BRDUM.
	MDMA_MDMA_C10BNDTR_BRC_Pos   = 0x14       // Position of BRC field.
	MDMA_MDMA_C10BNDTR_BRC_Msk   = 0xfff00000 // Bit mask of BRC field.

	// MDMA_C10SAR: MDMA channel x source address           register
	MDMA_MDMA_C10SAR_SAR_Pos = 0x0        // Position of SAR field.
	MDMA_MDMA_C10SAR_SAR_Msk = 0xffffffff // Bit mask of SAR field.

	// MDMA_C10DAR: MDMA channel x destination address           register
	MDMA_MDMA_C10DAR_DAR_Pos = 0x0        // Position of DAR field.
	MDMA_MDMA_C10DAR_DAR_Msk = 0xffffffff // Bit mask of DAR field.

	// MDMA_C10BRUR: MDMA channel x Block Repeat address Update           register
	MDMA_MDMA_C10BRUR_SUV_Pos = 0x0        // Position of SUV field.
	MDMA_MDMA_C10BRUR_SUV_Msk = 0xffff     // Bit mask of SUV field.
	MDMA_MDMA_C10BRUR_DUV_Pos = 0x10       // Position of DUV field.
	MDMA_MDMA_C10BRUR_DUV_Msk = 0xffff0000 // Bit mask of DUV field.

	// MDMA_C10LAR: MDMA channel x Link Address           register
	MDMA_MDMA_C10LAR_LAR_Pos = 0x0        // Position of LAR field.
	MDMA_MDMA_C10LAR_LAR_Msk = 0xffffffff // Bit mask of LAR field.

	// MDMA_C10TBR: MDMA channel x Trigger and Bus selection           Register
	MDMA_MDMA_C10TBR_TSEL_Pos = 0x0     // Position of TSEL field.
	MDMA_MDMA_C10TBR_TSEL_Msk = 0x3f    // Bit mask of TSEL field.
	MDMA_MDMA_C10TBR_SBUS_Pos = 0x10    // Position of SBUS field.
	MDMA_MDMA_C10TBR_SBUS_Msk = 0x10000 // Bit mask of SBUS field.
	MDMA_MDMA_C10TBR_SBUS     = 0x10000 // Bit SBUS.
	MDMA_MDMA_C10TBR_DBUS_Pos = 0x11    // Position of DBUS field.
	MDMA_MDMA_C10TBR_DBUS_Msk = 0x20000 // Bit mask of DBUS field.
	MDMA_MDMA_C10TBR_DBUS     = 0x20000 // Bit DBUS.

	// MDMA_C10MAR: MDMA channel x Mask address           register
	MDMA_MDMA_C10MAR_MAR_Pos = 0x0        // Position of MAR field.
	MDMA_MDMA_C10MAR_MAR_Msk = 0xffffffff // Bit mask of MAR field.

	// MDMA_C10MDR: MDMA channel x Mask Data           register
	MDMA_MDMA_C10MDR_MDR_Pos = 0x0        // Position of MDR field.
	MDMA_MDMA_C10MDR_MDR_Msk = 0xffffffff // Bit mask of MDR field.

	// MDMA_C11ISR: MDMA channel x interrupt/status           register
	MDMA_MDMA_C11ISR_TEIF11_Pos  = 0x0     // Position of TEIF11 field.
	MDMA_MDMA_C11ISR_TEIF11_Msk  = 0x1     // Bit mask of TEIF11 field.
	MDMA_MDMA_C11ISR_TEIF11      = 0x1     // Bit TEIF11.
	MDMA_MDMA_C11ISR_CTCIF11_Pos = 0x1     // Position of CTCIF11 field.
	MDMA_MDMA_C11ISR_CTCIF11_Msk = 0x2     // Bit mask of CTCIF11 field.
	MDMA_MDMA_C11ISR_CTCIF11     = 0x2     // Bit CTCIF11.
	MDMA_MDMA_C11ISR_BRTIF11_Pos = 0x2     // Position of BRTIF11 field.
	MDMA_MDMA_C11ISR_BRTIF11_Msk = 0x4     // Bit mask of BRTIF11 field.
	MDMA_MDMA_C11ISR_BRTIF11     = 0x4     // Bit BRTIF11.
	MDMA_MDMA_C11ISR_BTIF11_Pos  = 0x3     // Position of BTIF11 field.
	MDMA_MDMA_C11ISR_BTIF11_Msk  = 0x8     // Bit mask of BTIF11 field.
	MDMA_MDMA_C11ISR_BTIF11      = 0x8     // Bit BTIF11.
	MDMA_MDMA_C11ISR_TCIF11_Pos  = 0x4     // Position of TCIF11 field.
	MDMA_MDMA_C11ISR_TCIF11_Msk  = 0x10    // Bit mask of TCIF11 field.
	MDMA_MDMA_C11ISR_TCIF11      = 0x10    // Bit TCIF11.
	MDMA_MDMA_C11ISR_CRQA11_Pos  = 0x10    // Position of CRQA11 field.
	MDMA_MDMA_C11ISR_CRQA11_Msk  = 0x10000 // Bit mask of CRQA11 field.
	MDMA_MDMA_C11ISR_CRQA11      = 0x10000 // Bit CRQA11.

	// MDMA_C11IFCR: MDMA channel x interrupt flag clear           register
	MDMA_MDMA_C11IFCR_CTEIF11_Pos  = 0x0  // Position of CTEIF11 field.
	MDMA_MDMA_C11IFCR_CTEIF11_Msk  = 0x1  // Bit mask of CTEIF11 field.
	MDMA_MDMA_C11IFCR_CTEIF11      = 0x1  // Bit CTEIF11.
	MDMA_MDMA_C11IFCR_CCTCIF11_Pos = 0x1  // Position of CCTCIF11 field.
	MDMA_MDMA_C11IFCR_CCTCIF11_Msk = 0x2  // Bit mask of CCTCIF11 field.
	MDMA_MDMA_C11IFCR_CCTCIF11     = 0x2  // Bit CCTCIF11.
	MDMA_MDMA_C11IFCR_CBRTIF11_Pos = 0x2  // Position of CBRTIF11 field.
	MDMA_MDMA_C11IFCR_CBRTIF11_Msk = 0x4  // Bit mask of CBRTIF11 field.
	MDMA_MDMA_C11IFCR_CBRTIF11     = 0x4  // Bit CBRTIF11.
	MDMA_MDMA_C11IFCR_CBTIF11_Pos  = 0x3  // Position of CBTIF11 field.
	MDMA_MDMA_C11IFCR_CBTIF11_Msk  = 0x8  // Bit mask of CBTIF11 field.
	MDMA_MDMA_C11IFCR_CBTIF11      = 0x8  // Bit CBTIF11.
	MDMA_MDMA_C11IFCR_CLTCIF11_Pos = 0x4  // Position of CLTCIF11 field.
	MDMA_MDMA_C11IFCR_CLTCIF11_Msk = 0x10 // Bit mask of CLTCIF11 field.
	MDMA_MDMA_C11IFCR_CLTCIF11     = 0x10 // Bit CLTCIF11.

	// MDMA_C11ESR: MDMA Channel x error status           register
	MDMA_MDMA_C11ESR_TEA_Pos  = 0x0   // Position of TEA field.
	MDMA_MDMA_C11ESR_TEA_Msk  = 0x7f  // Bit mask of TEA field.
	MDMA_MDMA_C11ESR_TED_Pos  = 0x7   // Position of TED field.
	MDMA_MDMA_C11ESR_TED_Msk  = 0x80  // Bit mask of TED field.
	MDMA_MDMA_C11ESR_TED      = 0x80  // Bit TED.
	MDMA_MDMA_C11ESR_TELD_Pos = 0x8   // Position of TELD field.
	MDMA_MDMA_C11ESR_TELD_Msk = 0x100 // Bit mask of TELD field.
	MDMA_MDMA_C11ESR_TELD     = 0x100 // Bit TELD.
	MDMA_MDMA_C11ESR_TEMD_Pos = 0x9   // Position of TEMD field.
	MDMA_MDMA_C11ESR_TEMD_Msk = 0x200 // Bit mask of TEMD field.
	MDMA_MDMA_C11ESR_TEMD     = 0x200 // Bit TEMD.
	MDMA_MDMA_C11ESR_ASE_Pos  = 0xa   // Position of ASE field.
	MDMA_MDMA_C11ESR_ASE_Msk  = 0x400 // Bit mask of ASE field.
	MDMA_MDMA_C11ESR_ASE      = 0x400 // Bit ASE.
	MDMA_MDMA_C11ESR_BSE_Pos  = 0xb   // Position of BSE field.
	MDMA_MDMA_C11ESR_BSE_Msk  = 0x800 // Bit mask of BSE field.
	MDMA_MDMA_C11ESR_BSE      = 0x800 // Bit BSE.

	// MDMA_C11CR: This register is used to control the           concerned channel.
	MDMA_MDMA_C11CR_EN_Pos    = 0x0     // Position of EN field.
	MDMA_MDMA_C11CR_EN_Msk    = 0x1     // Bit mask of EN field.
	MDMA_MDMA_C11CR_EN        = 0x1     // Bit EN.
	MDMA_MDMA_C11CR_TEIE_Pos  = 0x1     // Position of TEIE field.
	MDMA_MDMA_C11CR_TEIE_Msk  = 0x2     // Bit mask of TEIE field.
	MDMA_MDMA_C11CR_TEIE      = 0x2     // Bit TEIE.
	MDMA_MDMA_C11CR_CTCIE_Pos = 0x2     // Position of CTCIE field.
	MDMA_MDMA_C11CR_CTCIE_Msk = 0x4     // Bit mask of CTCIE field.
	MDMA_MDMA_C11CR_CTCIE     = 0x4     // Bit CTCIE.
	MDMA_MDMA_C11CR_BRTIE_Pos = 0x3     // Position of BRTIE field.
	MDMA_MDMA_C11CR_BRTIE_Msk = 0x8     // Bit mask of BRTIE field.
	MDMA_MDMA_C11CR_BRTIE     = 0x8     // Bit BRTIE.
	MDMA_MDMA_C11CR_BTIE_Pos  = 0x4     // Position of BTIE field.
	MDMA_MDMA_C11CR_BTIE_Msk  = 0x10    // Bit mask of BTIE field.
	MDMA_MDMA_C11CR_BTIE      = 0x10    // Bit BTIE.
	MDMA_MDMA_C11CR_TCIE_Pos  = 0x5     // Position of TCIE field.
	MDMA_MDMA_C11CR_TCIE_Msk  = 0x20    // Bit mask of TCIE field.
	MDMA_MDMA_C11CR_TCIE      = 0x20    // Bit TCIE.
	MDMA_MDMA_C11CR_PL_Pos    = 0x6     // Position of PL field.
	MDMA_MDMA_C11CR_PL_Msk    = 0xc0    // Bit mask of PL field.
	MDMA_MDMA_C11CR_BEX_Pos   = 0xc     // Position of BEX field.
	MDMA_MDMA_C11CR_BEX_Msk   = 0x1000  // Bit mask of BEX field.
	MDMA_MDMA_C11CR_BEX       = 0x1000  // Bit BEX.
	MDMA_MDMA_C11CR_HEX_Pos   = 0xd     // Position of HEX field.
	MDMA_MDMA_C11CR_HEX_Msk   = 0x2000  // Bit mask of HEX field.
	MDMA_MDMA_C11CR_HEX       = 0x2000  // Bit HEX.
	MDMA_MDMA_C11CR_WEX_Pos   = 0xe     // Position of WEX field.
	MDMA_MDMA_C11CR_WEX_Msk   = 0x4000  // Bit mask of WEX field.
	MDMA_MDMA_C11CR_WEX       = 0x4000  // Bit WEX.
	MDMA_MDMA_C11CR_SWRQ_Pos  = 0x10    // Position of SWRQ field.
	MDMA_MDMA_C11CR_SWRQ_Msk  = 0x10000 // Bit mask of SWRQ field.
	MDMA_MDMA_C11CR_SWRQ      = 0x10000 // Bit SWRQ.

	// MDMA_C11TCR: This register is used to configure the           concerned channel.
	MDMA_MDMA_C11TCR_SINC_Pos   = 0x0        // Position of SINC field.
	MDMA_MDMA_C11TCR_SINC_Msk   = 0x3        // Bit mask of SINC field.
	MDMA_MDMA_C11TCR_DINC_Pos   = 0x2        // Position of DINC field.
	MDMA_MDMA_C11TCR_DINC_Msk   = 0xc        // Bit mask of DINC field.
	MDMA_MDMA_C11TCR_SSIZE_Pos  = 0x4        // Position of SSIZE field.
	MDMA_MDMA_C11TCR_SSIZE_Msk  = 0x30       // Bit mask of SSIZE field.
	MDMA_MDMA_C11TCR_DSIZE_Pos  = 0x6        // Position of DSIZE field.
	MDMA_MDMA_C11TCR_DSIZE_Msk  = 0xc0       // Bit mask of DSIZE field.
	MDMA_MDMA_C11TCR_SINCOS_Pos = 0x8        // Position of SINCOS field.
	MDMA_MDMA_C11TCR_SINCOS_Msk = 0x300      // Bit mask of SINCOS field.
	MDMA_MDMA_C11TCR_DINCOS_Pos = 0xa        // Position of DINCOS field.
	MDMA_MDMA_C11TCR_DINCOS_Msk = 0xc00      // Bit mask of DINCOS field.
	MDMA_MDMA_C11TCR_SBURST_Pos = 0xc        // Position of SBURST field.
	MDMA_MDMA_C11TCR_SBURST_Msk = 0x7000     // Bit mask of SBURST field.
	MDMA_MDMA_C11TCR_DBURST_Pos = 0xf        // Position of DBURST field.
	MDMA_MDMA_C11TCR_DBURST_Msk = 0x38000    // Bit mask of DBURST field.
	MDMA_MDMA_C11TCR_TLEN_Pos   = 0x12       // Position of TLEN field.
	MDMA_MDMA_C11TCR_TLEN_Msk   = 0x1fc0000  // Bit mask of TLEN field.
	MDMA_MDMA_C11TCR_PKE_Pos    = 0x19       // Position of PKE field.
	MDMA_MDMA_C11TCR_PKE_Msk    = 0x2000000  // Bit mask of PKE field.
	MDMA_MDMA_C11TCR_PKE        = 0x2000000  // Bit PKE.
	MDMA_MDMA_C11TCR_PAM_Pos    = 0x1a       // Position of PAM field.
	MDMA_MDMA_C11TCR_PAM_Msk    = 0xc000000  // Bit mask of PAM field.
	MDMA_MDMA_C11TCR_TRGM_Pos   = 0x1c       // Position of TRGM field.
	MDMA_MDMA_C11TCR_TRGM_Msk   = 0x30000000 // Bit mask of TRGM field.
	MDMA_MDMA_C11TCR_SWRM_Pos   = 0x1e       // Position of SWRM field.
	MDMA_MDMA_C11TCR_SWRM_Msk   = 0x40000000 // Bit mask of SWRM field.
	MDMA_MDMA_C11TCR_SWRM       = 0x40000000 // Bit SWRM.
	MDMA_MDMA_C11TCR_BWM_Pos    = 0x1f       // Position of BWM field.
	MDMA_MDMA_C11TCR_BWM_Msk    = 0x80000000 // Bit mask of BWM field.
	MDMA_MDMA_C11TCR_BWM        = 0x80000000 // Bit BWM.

	// MDMA_C11BNDTR: MDMA Channel x block number of data           register
	MDMA_MDMA_C11BNDTR_BNDT_Pos  = 0x0        // Position of BNDT field.
	MDMA_MDMA_C11BNDTR_BNDT_Msk  = 0x1ffff    // Bit mask of BNDT field.
	MDMA_MDMA_C11BNDTR_BRSUM_Pos = 0x12       // Position of BRSUM field.
	MDMA_MDMA_C11BNDTR_BRSUM_Msk = 0x40000    // Bit mask of BRSUM field.
	MDMA_MDMA_C11BNDTR_BRSUM     = 0x40000    // Bit BRSUM.
	MDMA_MDMA_C11BNDTR_BRDUM_Pos = 0x13       // Position of BRDUM field.
	MDMA_MDMA_C11BNDTR_BRDUM_Msk = 0x80000    // Bit mask of BRDUM field.
	MDMA_MDMA_C11BNDTR_BRDUM     = 0x80000    // Bit BRDUM.
	MDMA_MDMA_C11BNDTR_BRC_Pos   = 0x14       // Position of BRC field.
	MDMA_MDMA_C11BNDTR_BRC_Msk   = 0xfff00000 // Bit mask of BRC field.

	// MDMA_C11SAR: MDMA channel x source address           register
	MDMA_MDMA_C11SAR_SAR_Pos = 0x0        // Position of SAR field.
	MDMA_MDMA_C11SAR_SAR_Msk = 0xffffffff // Bit mask of SAR field.

	// MDMA_C11DAR: MDMA channel x destination address           register
	MDMA_MDMA_C11DAR_DAR_Pos = 0x0        // Position of DAR field.
	MDMA_MDMA_C11DAR_DAR_Msk = 0xffffffff // Bit mask of DAR field.

	// MDMA_C11BRUR: MDMA channel x Block Repeat address Update           register
	MDMA_MDMA_C11BRUR_SUV_Pos = 0x0        // Position of SUV field.
	MDMA_MDMA_C11BRUR_SUV_Msk = 0xffff     // Bit mask of SUV field.
	MDMA_MDMA_C11BRUR_DUV_Pos = 0x10       // Position of DUV field.
	MDMA_MDMA_C11BRUR_DUV_Msk = 0xffff0000 // Bit mask of DUV field.

	// MDMA_C11LAR: MDMA channel x Link Address           register
	MDMA_MDMA_C11LAR_LAR_Pos = 0x0        // Position of LAR field.
	MDMA_MDMA_C11LAR_LAR_Msk = 0xffffffff // Bit mask of LAR field.

	// MDMA_C11TBR: MDMA channel x Trigger and Bus selection           Register
	MDMA_MDMA_C11TBR_TSEL_Pos = 0x0     // Position of TSEL field.
	MDMA_MDMA_C11TBR_TSEL_Msk = 0x3f    // Bit mask of TSEL field.
	MDMA_MDMA_C11TBR_SBUS_Pos = 0x10    // Position of SBUS field.
	MDMA_MDMA_C11TBR_SBUS_Msk = 0x10000 // Bit mask of SBUS field.
	MDMA_MDMA_C11TBR_SBUS     = 0x10000 // Bit SBUS.
	MDMA_MDMA_C11TBR_DBUS_Pos = 0x11    // Position of DBUS field.
	MDMA_MDMA_C11TBR_DBUS_Msk = 0x20000 // Bit mask of DBUS field.
	MDMA_MDMA_C11TBR_DBUS     = 0x20000 // Bit DBUS.

	// MDMA_C11MAR: MDMA channel x Mask address           register
	MDMA_MDMA_C11MAR_MAR_Pos = 0x0        // Position of MAR field.
	MDMA_MDMA_C11MAR_MAR_Msk = 0xffffffff // Bit mask of MAR field.

	// MDMA_C11MDR: MDMA channel x Mask Data           register
	MDMA_MDMA_C11MDR_MDR_Pos = 0x0        // Position of MDR field.
	MDMA_MDMA_C11MDR_MDR_Msk = 0xffffffff // Bit mask of MDR field.

	// MDMA_C12ISR: MDMA channel x interrupt/status           register
	MDMA_MDMA_C12ISR_TEIF12_Pos  = 0x0     // Position of TEIF12 field.
	MDMA_MDMA_C12ISR_TEIF12_Msk  = 0x1     // Bit mask of TEIF12 field.
	MDMA_MDMA_C12ISR_TEIF12      = 0x1     // Bit TEIF12.
	MDMA_MDMA_C12ISR_CTCIF12_Pos = 0x1     // Position of CTCIF12 field.
	MDMA_MDMA_C12ISR_CTCIF12_Msk = 0x2     // Bit mask of CTCIF12 field.
	MDMA_MDMA_C12ISR_CTCIF12     = 0x2     // Bit CTCIF12.
	MDMA_MDMA_C12ISR_BRTIF12_Pos = 0x2     // Position of BRTIF12 field.
	MDMA_MDMA_C12ISR_BRTIF12_Msk = 0x4     // Bit mask of BRTIF12 field.
	MDMA_MDMA_C12ISR_BRTIF12     = 0x4     // Bit BRTIF12.
	MDMA_MDMA_C12ISR_BTIF12_Pos  = 0x3     // Position of BTIF12 field.
	MDMA_MDMA_C12ISR_BTIF12_Msk  = 0x8     // Bit mask of BTIF12 field.
	MDMA_MDMA_C12ISR_BTIF12      = 0x8     // Bit BTIF12.
	MDMA_MDMA_C12ISR_TCIF12_Pos  = 0x4     // Position of TCIF12 field.
	MDMA_MDMA_C12ISR_TCIF12_Msk  = 0x10    // Bit mask of TCIF12 field.
	MDMA_MDMA_C12ISR_TCIF12      = 0x10    // Bit TCIF12.
	MDMA_MDMA_C12ISR_CRQA12_Pos  = 0x10    // Position of CRQA12 field.
	MDMA_MDMA_C12ISR_CRQA12_Msk  = 0x10000 // Bit mask of CRQA12 field.
	MDMA_MDMA_C12ISR_CRQA12      = 0x10000 // Bit CRQA12.

	// MDMA_C12IFCR: MDMA channel x interrupt flag clear           register
	MDMA_MDMA_C12IFCR_CTEIF12_Pos  = 0x0  // Position of CTEIF12 field.
	MDMA_MDMA_C12IFCR_CTEIF12_Msk  = 0x1  // Bit mask of CTEIF12 field.
	MDMA_MDMA_C12IFCR_CTEIF12      = 0x1  // Bit CTEIF12.
	MDMA_MDMA_C12IFCR_CCTCIF12_Pos = 0x1  // Position of CCTCIF12 field.
	MDMA_MDMA_C12IFCR_CCTCIF12_Msk = 0x2  // Bit mask of CCTCIF12 field.
	MDMA_MDMA_C12IFCR_CCTCIF12     = 0x2  // Bit CCTCIF12.
	MDMA_MDMA_C12IFCR_CBRTIF12_Pos = 0x2  // Position of CBRTIF12 field.
	MDMA_MDMA_C12IFCR_CBRTIF12_Msk = 0x4  // Bit mask of CBRTIF12 field.
	MDMA_MDMA_C12IFCR_CBRTIF12     = 0x4  // Bit CBRTIF12.
	MDMA_MDMA_C12IFCR_CBTIF12_Pos  = 0x3  // Position of CBTIF12 field.
	MDMA_MDMA_C12IFCR_CBTIF12_Msk  = 0x8  // Bit mask of CBTIF12 field.
	MDMA_MDMA_C12IFCR_CBTIF12      = 0x8  // Bit CBTIF12.
	MDMA_MDMA_C12IFCR_CLTCIF12_Pos = 0x4  // Position of CLTCIF12 field.
	MDMA_MDMA_C12IFCR_CLTCIF12_Msk = 0x10 // Bit mask of CLTCIF12 field.
	MDMA_MDMA_C12IFCR_CLTCIF12     = 0x10 // Bit CLTCIF12.

	// MDMA_C12ESR: MDMA Channel x error status           register
	MDMA_MDMA_C12ESR_TEA_Pos  = 0x0   // Position of TEA field.
	MDMA_MDMA_C12ESR_TEA_Msk  = 0x7f  // Bit mask of TEA field.
	MDMA_MDMA_C12ESR_TED_Pos  = 0x7   // Position of TED field.
	MDMA_MDMA_C12ESR_TED_Msk  = 0x80  // Bit mask of TED field.
	MDMA_MDMA_C12ESR_TED      = 0x80  // Bit TED.
	MDMA_MDMA_C12ESR_TELD_Pos = 0x8   // Position of TELD field.
	MDMA_MDMA_C12ESR_TELD_Msk = 0x100 // Bit mask of TELD field.
	MDMA_MDMA_C12ESR_TELD     = 0x100 // Bit TELD.
	MDMA_MDMA_C12ESR_TEMD_Pos = 0x9   // Position of TEMD field.
	MDMA_MDMA_C12ESR_TEMD_Msk = 0x200 // Bit mask of TEMD field.
	MDMA_MDMA_C12ESR_TEMD     = 0x200 // Bit TEMD.
	MDMA_MDMA_C12ESR_ASE_Pos  = 0xa   // Position of ASE field.
	MDMA_MDMA_C12ESR_ASE_Msk  = 0x400 // Bit mask of ASE field.
	MDMA_MDMA_C12ESR_ASE      = 0x400 // Bit ASE.
	MDMA_MDMA_C12ESR_BSE_Pos  = 0xb   // Position of BSE field.
	MDMA_MDMA_C12ESR_BSE_Msk  = 0x800 // Bit mask of BSE field.
	MDMA_MDMA_C12ESR_BSE      = 0x800 // Bit BSE.

	// MDMA_C12CR: This register is used to control the           concerned channel.
	MDMA_MDMA_C12CR_EN_Pos    = 0x0     // Position of EN field.
	MDMA_MDMA_C12CR_EN_Msk    = 0x1     // Bit mask of EN field.
	MDMA_MDMA_C12CR_EN        = 0x1     // Bit EN.
	MDMA_MDMA_C12CR_TEIE_Pos  = 0x1     // Position of TEIE field.
	MDMA_MDMA_C12CR_TEIE_Msk  = 0x2     // Bit mask of TEIE field.
	MDMA_MDMA_C12CR_TEIE      = 0x2     // Bit TEIE.
	MDMA_MDMA_C12CR_CTCIE_Pos = 0x2     // Position of CTCIE field.
	MDMA_MDMA_C12CR_CTCIE_Msk = 0x4     // Bit mask of CTCIE field.
	MDMA_MDMA_C12CR_CTCIE     = 0x4     // Bit CTCIE.
	MDMA_MDMA_C12CR_BRTIE_Pos = 0x3     // Position of BRTIE field.
	MDMA_MDMA_C12CR_BRTIE_Msk = 0x8     // Bit mask of BRTIE field.
	MDMA_MDMA_C12CR_BRTIE     = 0x8     // Bit BRTIE.
	MDMA_MDMA_C12CR_BTIE_Pos  = 0x4     // Position of BTIE field.
	MDMA_MDMA_C12CR_BTIE_Msk  = 0x10    // Bit mask of BTIE field.
	MDMA_MDMA_C12CR_BTIE      = 0x10    // Bit BTIE.
	MDMA_MDMA_C12CR_TCIE_Pos  = 0x5     // Position of TCIE field.
	MDMA_MDMA_C12CR_TCIE_Msk  = 0x20    // Bit mask of TCIE field.
	MDMA_MDMA_C12CR_TCIE      = 0x20    // Bit TCIE.
	MDMA_MDMA_C12CR_PL_Pos    = 0x6     // Position of PL field.
	MDMA_MDMA_C12CR_PL_Msk    = 0xc0    // Bit mask of PL field.
	MDMA_MDMA_C12CR_BEX_Pos   = 0xc     // Position of BEX field.
	MDMA_MDMA_C12CR_BEX_Msk   = 0x1000  // Bit mask of BEX field.
	MDMA_MDMA_C12CR_BEX       = 0x1000  // Bit BEX.
	MDMA_MDMA_C12CR_HEX_Pos   = 0xd     // Position of HEX field.
	MDMA_MDMA_C12CR_HEX_Msk   = 0x2000  // Bit mask of HEX field.
	MDMA_MDMA_C12CR_HEX       = 0x2000  // Bit HEX.
	MDMA_MDMA_C12CR_WEX_Pos   = 0xe     // Position of WEX field.
	MDMA_MDMA_C12CR_WEX_Msk   = 0x4000  // Bit mask of WEX field.
	MDMA_MDMA_C12CR_WEX       = 0x4000  // Bit WEX.
	MDMA_MDMA_C12CR_SWRQ_Pos  = 0x10    // Position of SWRQ field.
	MDMA_MDMA_C12CR_SWRQ_Msk  = 0x10000 // Bit mask of SWRQ field.
	MDMA_MDMA_C12CR_SWRQ      = 0x10000 // Bit SWRQ.

	// MDMA_C12TCR: This register is used to configure the           concerned channel.
	MDMA_MDMA_C12TCR_SINC_Pos   = 0x0        // Position of SINC field.
	MDMA_MDMA_C12TCR_SINC_Msk   = 0x3        // Bit mask of SINC field.
	MDMA_MDMA_C12TCR_DINC_Pos   = 0x2        // Position of DINC field.
	MDMA_MDMA_C12TCR_DINC_Msk   = 0xc        // Bit mask of DINC field.
	MDMA_MDMA_C12TCR_SSIZE_Pos  = 0x4        // Position of SSIZE field.
	MDMA_MDMA_C12TCR_SSIZE_Msk  = 0x30       // Bit mask of SSIZE field.
	MDMA_MDMA_C12TCR_DSIZE_Pos  = 0x6        // Position of DSIZE field.
	MDMA_MDMA_C12TCR_DSIZE_Msk  = 0xc0       // Bit mask of DSIZE field.
	MDMA_MDMA_C12TCR_SINCOS_Pos = 0x8        // Position of SINCOS field.
	MDMA_MDMA_C12TCR_SINCOS_Msk = 0x300      // Bit mask of SINCOS field.
	MDMA_MDMA_C12TCR_DINCOS_Pos = 0xa        // Position of DINCOS field.
	MDMA_MDMA_C12TCR_DINCOS_Msk = 0xc00      // Bit mask of DINCOS field.
	MDMA_MDMA_C12TCR_SBURST_Pos = 0xc        // Position of SBURST field.
	MDMA_MDMA_C12TCR_SBURST_Msk = 0x7000     // Bit mask of SBURST field.
	MDMA_MDMA_C12TCR_DBURST_Pos = 0xf        // Position of DBURST field.
	MDMA_MDMA_C12TCR_DBURST_Msk = 0x38000    // Bit mask of DBURST field.
	MDMA_MDMA_C12TCR_TLEN_Pos   = 0x12       // Position of TLEN field.
	MDMA_MDMA_C12TCR_TLEN_Msk   = 0x1fc0000  // Bit mask of TLEN field.
	MDMA_MDMA_C12TCR_PKE_Pos    = 0x19       // Position of PKE field.
	MDMA_MDMA_C12TCR_PKE_Msk    = 0x2000000  // Bit mask of PKE field.
	MDMA_MDMA_C12TCR_PKE        = 0x2000000  // Bit PKE.
	MDMA_MDMA_C12TCR_PAM_Pos    = 0x1a       // Position of PAM field.
	MDMA_MDMA_C12TCR_PAM_Msk    = 0xc000000  // Bit mask of PAM field.
	MDMA_MDMA_C12TCR_TRGM_Pos   = 0x1c       // Position of TRGM field.
	MDMA_MDMA_C12TCR_TRGM_Msk   = 0x30000000 // Bit mask of TRGM field.
	MDMA_MDMA_C12TCR_SWRM_Pos   = 0x1e       // Position of SWRM field.
	MDMA_MDMA_C12TCR_SWRM_Msk   = 0x40000000 // Bit mask of SWRM field.
	MDMA_MDMA_C12TCR_SWRM       = 0x40000000 // Bit SWRM.
	MDMA_MDMA_C12TCR_BWM_Pos    = 0x1f       // Position of BWM field.
	MDMA_MDMA_C12TCR_BWM_Msk    = 0x80000000 // Bit mask of BWM field.
	MDMA_MDMA_C12TCR_BWM        = 0x80000000 // Bit BWM.

	// MDMA_C12BNDTR: MDMA Channel x block number of data           register
	MDMA_MDMA_C12BNDTR_BNDT_Pos  = 0x0        // Position of BNDT field.
	MDMA_MDMA_C12BNDTR_BNDT_Msk  = 0x1ffff    // Bit mask of BNDT field.
	MDMA_MDMA_C12BNDTR_BRSUM_Pos = 0x12       // Position of BRSUM field.
	MDMA_MDMA_C12BNDTR_BRSUM_Msk = 0x40000    // Bit mask of BRSUM field.
	MDMA_MDMA_C12BNDTR_BRSUM     = 0x40000    // Bit BRSUM.
	MDMA_MDMA_C12BNDTR_BRDUM_Pos = 0x13       // Position of BRDUM field.
	MDMA_MDMA_C12BNDTR_BRDUM_Msk = 0x80000    // Bit mask of BRDUM field.
	MDMA_MDMA_C12BNDTR_BRDUM     = 0x80000    // Bit BRDUM.
	MDMA_MDMA_C12BNDTR_BRC_Pos   = 0x14       // Position of BRC field.
	MDMA_MDMA_C12BNDTR_BRC_Msk   = 0xfff00000 // Bit mask of BRC field.

	// MDMA_C12SAR: MDMA channel x source address           register
	MDMA_MDMA_C12SAR_SAR_Pos = 0x0        // Position of SAR field.
	MDMA_MDMA_C12SAR_SAR_Msk = 0xffffffff // Bit mask of SAR field.

	// MDMA_C12DAR: MDMA channel x destination address           register
	MDMA_MDMA_C12DAR_DAR_Pos = 0x0        // Position of DAR field.
	MDMA_MDMA_C12DAR_DAR_Msk = 0xffffffff // Bit mask of DAR field.

	// MDMA_C12BRUR: MDMA channel x Block Repeat address Update           register
	MDMA_MDMA_C12BRUR_SUV_Pos = 0x0        // Position of SUV field.
	MDMA_MDMA_C12BRUR_SUV_Msk = 0xffff     // Bit mask of SUV field.
	MDMA_MDMA_C12BRUR_DUV_Pos = 0x10       // Position of DUV field.
	MDMA_MDMA_C12BRUR_DUV_Msk = 0xffff0000 // Bit mask of DUV field.

	// MDMA_C12LAR: MDMA channel x Link Address           register
	MDMA_MDMA_C12LAR_LAR_Pos = 0x0        // Position of LAR field.
	MDMA_MDMA_C12LAR_LAR_Msk = 0xffffffff // Bit mask of LAR field.

	// MDMA_C12TBR: MDMA channel x Trigger and Bus selection           Register
	MDMA_MDMA_C12TBR_TSEL_Pos = 0x0     // Position of TSEL field.
	MDMA_MDMA_C12TBR_TSEL_Msk = 0x3f    // Bit mask of TSEL field.
	MDMA_MDMA_C12TBR_SBUS_Pos = 0x10    // Position of SBUS field.
	MDMA_MDMA_C12TBR_SBUS_Msk = 0x10000 // Bit mask of SBUS field.
	MDMA_MDMA_C12TBR_SBUS     = 0x10000 // Bit SBUS.
	MDMA_MDMA_C12TBR_DBUS_Pos = 0x11    // Position of DBUS field.
	MDMA_MDMA_C12TBR_DBUS_Msk = 0x20000 // Bit mask of DBUS field.
	MDMA_MDMA_C12TBR_DBUS     = 0x20000 // Bit DBUS.

	// MDMA_C12MAR: MDMA channel x Mask address           register
	MDMA_MDMA_C12MAR_MAR_Pos = 0x0        // Position of MAR field.
	MDMA_MDMA_C12MAR_MAR_Msk = 0xffffffff // Bit mask of MAR field.

	// MDMA_C12MDR: MDMA channel x Mask Data           register
	MDMA_MDMA_C12MDR_MDR_Pos = 0x0        // Position of MDR field.
	MDMA_MDMA_C12MDR_MDR_Msk = 0xffffffff // Bit mask of MDR field.

	// MDMA_C13ISR: MDMA channel x interrupt/status           register
	MDMA_MDMA_C13ISR_TEIF13_Pos  = 0x0     // Position of TEIF13 field.
	MDMA_MDMA_C13ISR_TEIF13_Msk  = 0x1     // Bit mask of TEIF13 field.
	MDMA_MDMA_C13ISR_TEIF13      = 0x1     // Bit TEIF13.
	MDMA_MDMA_C13ISR_CTCIF13_Pos = 0x1     // Position of CTCIF13 field.
	MDMA_MDMA_C13ISR_CTCIF13_Msk = 0x2     // Bit mask of CTCIF13 field.
	MDMA_MDMA_C13ISR_CTCIF13     = 0x2     // Bit CTCIF13.
	MDMA_MDMA_C13ISR_BRTIF13_Pos = 0x2     // Position of BRTIF13 field.
	MDMA_MDMA_C13ISR_BRTIF13_Msk = 0x4     // Bit mask of BRTIF13 field.
	MDMA_MDMA_C13ISR_BRTIF13     = 0x4     // Bit BRTIF13.
	MDMA_MDMA_C13ISR_BTIF13_Pos  = 0x3     // Position of BTIF13 field.
	MDMA_MDMA_C13ISR_BTIF13_Msk  = 0x8     // Bit mask of BTIF13 field.
	MDMA_MDMA_C13ISR_BTIF13      = 0x8     // Bit BTIF13.
	MDMA_MDMA_C13ISR_TCIF13_Pos  = 0x4     // Position of TCIF13 field.
	MDMA_MDMA_C13ISR_TCIF13_Msk  = 0x10    // Bit mask of TCIF13 field.
	MDMA_MDMA_C13ISR_TCIF13      = 0x10    // Bit TCIF13.
	MDMA_MDMA_C13ISR_CRQA13_Pos  = 0x10    // Position of CRQA13 field.
	MDMA_MDMA_C13ISR_CRQA13_Msk  = 0x10000 // Bit mask of CRQA13 field.
	MDMA_MDMA_C13ISR_CRQA13      = 0x10000 // Bit CRQA13.

	// MDMA_C13IFCR: MDMA channel x interrupt flag clear           register
	MDMA_MDMA_C13IFCR_CTEIF13_Pos  = 0x0  // Position of CTEIF13 field.
	MDMA_MDMA_C13IFCR_CTEIF13_Msk  = 0x1  // Bit mask of CTEIF13 field.
	MDMA_MDMA_C13IFCR_CTEIF13      = 0x1  // Bit CTEIF13.
	MDMA_MDMA_C13IFCR_CCTCIF13_Pos = 0x1  // Position of CCTCIF13 field.
	MDMA_MDMA_C13IFCR_CCTCIF13_Msk = 0x2  // Bit mask of CCTCIF13 field.
	MDMA_MDMA_C13IFCR_CCTCIF13     = 0x2  // Bit CCTCIF13.
	MDMA_MDMA_C13IFCR_CBRTIF13_Pos = 0x2  // Position of CBRTIF13 field.
	MDMA_MDMA_C13IFCR_CBRTIF13_Msk = 0x4  // Bit mask of CBRTIF13 field.
	MDMA_MDMA_C13IFCR_CBRTIF13     = 0x4  // Bit CBRTIF13.
	MDMA_MDMA_C13IFCR_CBTIF13_Pos  = 0x3  // Position of CBTIF13 field.
	MDMA_MDMA_C13IFCR_CBTIF13_Msk  = 0x8  // Bit mask of CBTIF13 field.
	MDMA_MDMA_C13IFCR_CBTIF13      = 0x8  // Bit CBTIF13.
	MDMA_MDMA_C13IFCR_CLTCIF13_Pos = 0x4  // Position of CLTCIF13 field.
	MDMA_MDMA_C13IFCR_CLTCIF13_Msk = 0x10 // Bit mask of CLTCIF13 field.
	MDMA_MDMA_C13IFCR_CLTCIF13     = 0x10 // Bit CLTCIF13.

	// MDMA_C13ESR: MDMA Channel x error status           register
	MDMA_MDMA_C13ESR_TEA_Pos  = 0x0   // Position of TEA field.
	MDMA_MDMA_C13ESR_TEA_Msk  = 0x7f  // Bit mask of TEA field.
	MDMA_MDMA_C13ESR_TED_Pos  = 0x7   // Position of TED field.
	MDMA_MDMA_C13ESR_TED_Msk  = 0x80  // Bit mask of TED field.
	MDMA_MDMA_C13ESR_TED      = 0x80  // Bit TED.
	MDMA_MDMA_C13ESR_TELD_Pos = 0x8   // Position of TELD field.
	MDMA_MDMA_C13ESR_TELD_Msk = 0x100 // Bit mask of TELD field.
	MDMA_MDMA_C13ESR_TELD     = 0x100 // Bit TELD.
	MDMA_MDMA_C13ESR_TEMD_Pos = 0x9   // Position of TEMD field.
	MDMA_MDMA_C13ESR_TEMD_Msk = 0x200 // Bit mask of TEMD field.
	MDMA_MDMA_C13ESR_TEMD     = 0x200 // Bit TEMD.
	MDMA_MDMA_C13ESR_ASE_Pos  = 0xa   // Position of ASE field.
	MDMA_MDMA_C13ESR_ASE_Msk  = 0x400 // Bit mask of ASE field.
	MDMA_MDMA_C13ESR_ASE      = 0x400 // Bit ASE.
	MDMA_MDMA_C13ESR_BSE_Pos  = 0xb   // Position of BSE field.
	MDMA_MDMA_C13ESR_BSE_Msk  = 0x800 // Bit mask of BSE field.
	MDMA_MDMA_C13ESR_BSE      = 0x800 // Bit BSE.

	// MDMA_C13CR: This register is used to control the           concerned channel.
	MDMA_MDMA_C13CR_EN_Pos    = 0x0     // Position of EN field.
	MDMA_MDMA_C13CR_EN_Msk    = 0x1     // Bit mask of EN field.
	MDMA_MDMA_C13CR_EN        = 0x1     // Bit EN.
	MDMA_MDMA_C13CR_TEIE_Pos  = 0x1     // Position of TEIE field.
	MDMA_MDMA_C13CR_TEIE_Msk  = 0x2     // Bit mask of TEIE field.
	MDMA_MDMA_C13CR_TEIE      = 0x2     // Bit TEIE.
	MDMA_MDMA_C13CR_CTCIE_Pos = 0x2     // Position of CTCIE field.
	MDMA_MDMA_C13CR_CTCIE_Msk = 0x4     // Bit mask of CTCIE field.
	MDMA_MDMA_C13CR_CTCIE     = 0x4     // Bit CTCIE.
	MDMA_MDMA_C13CR_BRTIE_Pos = 0x3     // Position of BRTIE field.
	MDMA_MDMA_C13CR_BRTIE_Msk = 0x8     // Bit mask of BRTIE field.
	MDMA_MDMA_C13CR_BRTIE     = 0x8     // Bit BRTIE.
	MDMA_MDMA_C13CR_BTIE_Pos  = 0x4     // Position of BTIE field.
	MDMA_MDMA_C13CR_BTIE_Msk  = 0x10    // Bit mask of BTIE field.
	MDMA_MDMA_C13CR_BTIE      = 0x10    // Bit BTIE.
	MDMA_MDMA_C13CR_TCIE_Pos  = 0x5     // Position of TCIE field.
	MDMA_MDMA_C13CR_TCIE_Msk  = 0x20    // Bit mask of TCIE field.
	MDMA_MDMA_C13CR_TCIE      = 0x20    // Bit TCIE.
	MDMA_MDMA_C13CR_PL_Pos    = 0x6     // Position of PL field.
	MDMA_MDMA_C13CR_PL_Msk    = 0xc0    // Bit mask of PL field.
	MDMA_MDMA_C13CR_BEX_Pos   = 0xc     // Position of BEX field.
	MDMA_MDMA_C13CR_BEX_Msk   = 0x1000  // Bit mask of BEX field.
	MDMA_MDMA_C13CR_BEX       = 0x1000  // Bit BEX.
	MDMA_MDMA_C13CR_HEX_Pos   = 0xd     // Position of HEX field.
	MDMA_MDMA_C13CR_HEX_Msk   = 0x2000  // Bit mask of HEX field.
	MDMA_MDMA_C13CR_HEX       = 0x2000  // Bit HEX.
	MDMA_MDMA_C13CR_WEX_Pos   = 0xe     // Position of WEX field.
	MDMA_MDMA_C13CR_WEX_Msk   = 0x4000  // Bit mask of WEX field.
	MDMA_MDMA_C13CR_WEX       = 0x4000  // Bit WEX.
	MDMA_MDMA_C13CR_SWRQ_Pos  = 0x10    // Position of SWRQ field.
	MDMA_MDMA_C13CR_SWRQ_Msk  = 0x10000 // Bit mask of SWRQ field.
	MDMA_MDMA_C13CR_SWRQ      = 0x10000 // Bit SWRQ.

	// MDMA_C13TCR: This register is used to configure the           concerned channel.
	MDMA_MDMA_C13TCR_SINC_Pos   = 0x0        // Position of SINC field.
	MDMA_MDMA_C13TCR_SINC_Msk   = 0x3        // Bit mask of SINC field.
	MDMA_MDMA_C13TCR_DINC_Pos   = 0x2        // Position of DINC field.
	MDMA_MDMA_C13TCR_DINC_Msk   = 0xc        // Bit mask of DINC field.
	MDMA_MDMA_C13TCR_SSIZE_Pos  = 0x4        // Position of SSIZE field.
	MDMA_MDMA_C13TCR_SSIZE_Msk  = 0x30       // Bit mask of SSIZE field.
	MDMA_MDMA_C13TCR_DSIZE_Pos  = 0x6        // Position of DSIZE field.
	MDMA_MDMA_C13TCR_DSIZE_Msk  = 0xc0       // Bit mask of DSIZE field.
	MDMA_MDMA_C13TCR_SINCOS_Pos = 0x8        // Position of SINCOS field.
	MDMA_MDMA_C13TCR_SINCOS_Msk = 0x300      // Bit mask of SINCOS field.
	MDMA_MDMA_C13TCR_DINCOS_Pos = 0xa        // Position of DINCOS field.
	MDMA_MDMA_C13TCR_DINCOS_Msk = 0xc00      // Bit mask of DINCOS field.
	MDMA_MDMA_C13TCR_SBURST_Pos = 0xc        // Position of SBURST field.
	MDMA_MDMA_C13TCR_SBURST_Msk = 0x7000     // Bit mask of SBURST field.
	MDMA_MDMA_C13TCR_DBURST_Pos = 0xf        // Position of DBURST field.
	MDMA_MDMA_C13TCR_DBURST_Msk = 0x38000    // Bit mask of DBURST field.
	MDMA_MDMA_C13TCR_TLEN_Pos   = 0x12       // Position of TLEN field.
	MDMA_MDMA_C13TCR_TLEN_Msk   = 0x1fc0000  // Bit mask of TLEN field.
	MDMA_MDMA_C13TCR_PKE_Pos    = 0x19       // Position of PKE field.
	MDMA_MDMA_C13TCR_PKE_Msk    = 0x2000000  // Bit mask of PKE field.
	MDMA_MDMA_C13TCR_PKE        = 0x2000000  // Bit PKE.
	MDMA_MDMA_C13TCR_PAM_Pos    = 0x1a       // Position of PAM field.
	MDMA_MDMA_C13TCR_PAM_Msk    = 0xc000000  // Bit mask of PAM field.
	MDMA_MDMA_C13TCR_TRGM_Pos   = 0x1c       // Position of TRGM field.
	MDMA_MDMA_C13TCR_TRGM_Msk   = 0x30000000 // Bit mask of TRGM field.
	MDMA_MDMA_C13TCR_SWRM_Pos   = 0x1e       // Position of SWRM field.
	MDMA_MDMA_C13TCR_SWRM_Msk   = 0x40000000 // Bit mask of SWRM field.
	MDMA_MDMA_C13TCR_SWRM       = 0x40000000 // Bit SWRM.
	MDMA_MDMA_C13TCR_BWM_Pos    = 0x1f       // Position of BWM field.
	MDMA_MDMA_C13TCR_BWM_Msk    = 0x80000000 // Bit mask of BWM field.
	MDMA_MDMA_C13TCR_BWM        = 0x80000000 // Bit BWM.

	// MDMA_C13BNDTR: MDMA Channel x block number of data           register
	MDMA_MDMA_C13BNDTR_BNDT_Pos  = 0x0        // Position of BNDT field.
	MDMA_MDMA_C13BNDTR_BNDT_Msk  = 0x1ffff    // Bit mask of BNDT field.
	MDMA_MDMA_C13BNDTR_BRSUM_Pos = 0x12       // Position of BRSUM field.
	MDMA_MDMA_C13BNDTR_BRSUM_Msk = 0x40000    // Bit mask of BRSUM field.
	MDMA_MDMA_C13BNDTR_BRSUM     = 0x40000    // Bit BRSUM.
	MDMA_MDMA_C13BNDTR_BRDUM_Pos = 0x13       // Position of BRDUM field.
	MDMA_MDMA_C13BNDTR_BRDUM_Msk = 0x80000    // Bit mask of BRDUM field.
	MDMA_MDMA_C13BNDTR_BRDUM     = 0x80000    // Bit BRDUM.
	MDMA_MDMA_C13BNDTR_BRC_Pos   = 0x14       // Position of BRC field.
	MDMA_MDMA_C13BNDTR_BRC_Msk   = 0xfff00000 // Bit mask of BRC field.

	// MDMA_C13SAR: MDMA channel x source address           register
	MDMA_MDMA_C13SAR_SAR_Pos = 0x0        // Position of SAR field.
	MDMA_MDMA_C13SAR_SAR_Msk = 0xffffffff // Bit mask of SAR field.

	// MDMA_C13DAR: MDMA channel x destination address           register
	MDMA_MDMA_C13DAR_DAR_Pos = 0x0        // Position of DAR field.
	MDMA_MDMA_C13DAR_DAR_Msk = 0xffffffff // Bit mask of DAR field.

	// MDMA_C13BRUR: MDMA channel x Block Repeat address Update           register
	MDMA_MDMA_C13BRUR_SUV_Pos = 0x0        // Position of SUV field.
	MDMA_MDMA_C13BRUR_SUV_Msk = 0xffff     // Bit mask of SUV field.
	MDMA_MDMA_C13BRUR_DUV_Pos = 0x10       // Position of DUV field.
	MDMA_MDMA_C13BRUR_DUV_Msk = 0xffff0000 // Bit mask of DUV field.

	// MDMA_C13LAR: MDMA channel x Link Address           register
	MDMA_MDMA_C13LAR_LAR_Pos = 0x0        // Position of LAR field.
	MDMA_MDMA_C13LAR_LAR_Msk = 0xffffffff // Bit mask of LAR field.

	// MDMA_C13TBR: MDMA channel x Trigger and Bus selection           Register
	MDMA_MDMA_C13TBR_TSEL_Pos = 0x0     // Position of TSEL field.
	MDMA_MDMA_C13TBR_TSEL_Msk = 0x3f    // Bit mask of TSEL field.
	MDMA_MDMA_C13TBR_SBUS_Pos = 0x10    // Position of SBUS field.
	MDMA_MDMA_C13TBR_SBUS_Msk = 0x10000 // Bit mask of SBUS field.
	MDMA_MDMA_C13TBR_SBUS     = 0x10000 // Bit SBUS.
	MDMA_MDMA_C13TBR_DBUS_Pos = 0x11    // Position of DBUS field.
	MDMA_MDMA_C13TBR_DBUS_Msk = 0x20000 // Bit mask of DBUS field.
	MDMA_MDMA_C13TBR_DBUS     = 0x20000 // Bit DBUS.

	// MDMA_C13MAR: MDMA channel x Mask address           register
	MDMA_MDMA_C13MAR_MAR_Pos = 0x0        // Position of MAR field.
	MDMA_MDMA_C13MAR_MAR_Msk = 0xffffffff // Bit mask of MAR field.

	// MDMA_C13MDR: MDMA channel x Mask Data           register
	MDMA_MDMA_C13MDR_MDR_Pos = 0x0        // Position of MDR field.
	MDMA_MDMA_C13MDR_MDR_Msk = 0xffffffff // Bit mask of MDR field.

	// MDMA_C14ISR: MDMA channel x interrupt/status           register
	MDMA_MDMA_C14ISR_TEIF14_Pos  = 0x0     // Position of TEIF14 field.
	MDMA_MDMA_C14ISR_TEIF14_Msk  = 0x1     // Bit mask of TEIF14 field.
	MDMA_MDMA_C14ISR_TEIF14      = 0x1     // Bit TEIF14.
	MDMA_MDMA_C14ISR_CTCIF14_Pos = 0x1     // Position of CTCIF14 field.
	MDMA_MDMA_C14ISR_CTCIF14_Msk = 0x2     // Bit mask of CTCIF14 field.
	MDMA_MDMA_C14ISR_CTCIF14     = 0x2     // Bit CTCIF14.
	MDMA_MDMA_C14ISR_BRTIF14_Pos = 0x2     // Position of BRTIF14 field.
	MDMA_MDMA_C14ISR_BRTIF14_Msk = 0x4     // Bit mask of BRTIF14 field.
	MDMA_MDMA_C14ISR_BRTIF14     = 0x4     // Bit BRTIF14.
	MDMA_MDMA_C14ISR_BTIF14_Pos  = 0x3     // Position of BTIF14 field.
	MDMA_MDMA_C14ISR_BTIF14_Msk  = 0x8     // Bit mask of BTIF14 field.
	MDMA_MDMA_C14ISR_BTIF14      = 0x8     // Bit BTIF14.
	MDMA_MDMA_C14ISR_TCIF14_Pos  = 0x4     // Position of TCIF14 field.
	MDMA_MDMA_C14ISR_TCIF14_Msk  = 0x10    // Bit mask of TCIF14 field.
	MDMA_MDMA_C14ISR_TCIF14      = 0x10    // Bit TCIF14.
	MDMA_MDMA_C14ISR_CRQA14_Pos  = 0x10    // Position of CRQA14 field.
	MDMA_MDMA_C14ISR_CRQA14_Msk  = 0x10000 // Bit mask of CRQA14 field.
	MDMA_MDMA_C14ISR_CRQA14      = 0x10000 // Bit CRQA14.

	// MDMA_C14IFCR: MDMA channel x interrupt flag clear           register
	MDMA_MDMA_C14IFCR_CTEIF14_Pos  = 0x0  // Position of CTEIF14 field.
	MDMA_MDMA_C14IFCR_CTEIF14_Msk  = 0x1  // Bit mask of CTEIF14 field.
	MDMA_MDMA_C14IFCR_CTEIF14      = 0x1  // Bit CTEIF14.
	MDMA_MDMA_C14IFCR_CCTCIF14_Pos = 0x1  // Position of CCTCIF14 field.
	MDMA_MDMA_C14IFCR_CCTCIF14_Msk = 0x2  // Bit mask of CCTCIF14 field.
	MDMA_MDMA_C14IFCR_CCTCIF14     = 0x2  // Bit CCTCIF14.
	MDMA_MDMA_C14IFCR_CBRTIF14_Pos = 0x2  // Position of CBRTIF14 field.
	MDMA_MDMA_C14IFCR_CBRTIF14_Msk = 0x4  // Bit mask of CBRTIF14 field.
	MDMA_MDMA_C14IFCR_CBRTIF14     = 0x4  // Bit CBRTIF14.
	MDMA_MDMA_C14IFCR_CBTIF14_Pos  = 0x3  // Position of CBTIF14 field.
	MDMA_MDMA_C14IFCR_CBTIF14_Msk  = 0x8  // Bit mask of CBTIF14 field.
	MDMA_MDMA_C14IFCR_CBTIF14      = 0x8  // Bit CBTIF14.
	MDMA_MDMA_C14IFCR_CLTCIF14_Pos = 0x4  // Position of CLTCIF14 field.
	MDMA_MDMA_C14IFCR_CLTCIF14_Msk = 0x10 // Bit mask of CLTCIF14 field.
	MDMA_MDMA_C14IFCR_CLTCIF14     = 0x10 // Bit CLTCIF14.

	// MDMA_C14ESR: MDMA Channel x error status           register
	MDMA_MDMA_C14ESR_TEA_Pos  = 0x0   // Position of TEA field.
	MDMA_MDMA_C14ESR_TEA_Msk  = 0x7f  // Bit mask of TEA field.
	MDMA_MDMA_C14ESR_TED_Pos  = 0x7   // Position of TED field.
	MDMA_MDMA_C14ESR_TED_Msk  = 0x80  // Bit mask of TED field.
	MDMA_MDMA_C14ESR_TED      = 0x80  // Bit TED.
	MDMA_MDMA_C14ESR_TELD_Pos = 0x8   // Position of TELD field.
	MDMA_MDMA_C14ESR_TELD_Msk = 0x100 // Bit mask of TELD field.
	MDMA_MDMA_C14ESR_TELD     = 0x100 // Bit TELD.
	MDMA_MDMA_C14ESR_TEMD_Pos = 0x9   // Position of TEMD field.
	MDMA_MDMA_C14ESR_TEMD_Msk = 0x200 // Bit mask of TEMD field.
	MDMA_MDMA_C14ESR_TEMD     = 0x200 // Bit TEMD.
	MDMA_MDMA_C14ESR_ASE_Pos  = 0xa   // Position of ASE field.
	MDMA_MDMA_C14ESR_ASE_Msk  = 0x400 // Bit mask of ASE field.
	MDMA_MDMA_C14ESR_ASE      = 0x400 // Bit ASE.
	MDMA_MDMA_C14ESR_BSE_Pos  = 0xb   // Position of BSE field.
	MDMA_MDMA_C14ESR_BSE_Msk  = 0x800 // Bit mask of BSE field.
	MDMA_MDMA_C14ESR_BSE      = 0x800 // Bit BSE.

	// MDMA_C14CR: This register is used to control the           concerned channel.
	MDMA_MDMA_C14CR_EN_Pos    = 0x0     // Position of EN field.
	MDMA_MDMA_C14CR_EN_Msk    = 0x1     // Bit mask of EN field.
	MDMA_MDMA_C14CR_EN        = 0x1     // Bit EN.
	MDMA_MDMA_C14CR_TEIE_Pos  = 0x1     // Position of TEIE field.
	MDMA_MDMA_C14CR_TEIE_Msk  = 0x2     // Bit mask of TEIE field.
	MDMA_MDMA_C14CR_TEIE      = 0x2     // Bit TEIE.
	MDMA_MDMA_C14CR_CTCIE_Pos = 0x2     // Position of CTCIE field.
	MDMA_MDMA_C14CR_CTCIE_Msk = 0x4     // Bit mask of CTCIE field.
	MDMA_MDMA_C14CR_CTCIE     = 0x4     // Bit CTCIE.
	MDMA_MDMA_C14CR_BRTIE_Pos = 0x3     // Position of BRTIE field.
	MDMA_MDMA_C14CR_BRTIE_Msk = 0x8     // Bit mask of BRTIE field.
	MDMA_MDMA_C14CR_BRTIE     = 0x8     // Bit BRTIE.
	MDMA_MDMA_C14CR_BTIE_Pos  = 0x4     // Position of BTIE field.
	MDMA_MDMA_C14CR_BTIE_Msk  = 0x10    // Bit mask of BTIE field.
	MDMA_MDMA_C14CR_BTIE      = 0x10    // Bit BTIE.
	MDMA_MDMA_C14CR_TCIE_Pos  = 0x5     // Position of TCIE field.
	MDMA_MDMA_C14CR_TCIE_Msk  = 0x20    // Bit mask of TCIE field.
	MDMA_MDMA_C14CR_TCIE      = 0x20    // Bit TCIE.
	MDMA_MDMA_C14CR_PL_Pos    = 0x6     // Position of PL field.
	MDMA_MDMA_C14CR_PL_Msk    = 0xc0    // Bit mask of PL field.
	MDMA_MDMA_C14CR_BEX_Pos   = 0xc     // Position of BEX field.
	MDMA_MDMA_C14CR_BEX_Msk   = 0x1000  // Bit mask of BEX field.
	MDMA_MDMA_C14CR_BEX       = 0x1000  // Bit BEX.
	MDMA_MDMA_C14CR_HEX_Pos   = 0xd     // Position of HEX field.
	MDMA_MDMA_C14CR_HEX_Msk   = 0x2000  // Bit mask of HEX field.
	MDMA_MDMA_C14CR_HEX       = 0x2000  // Bit HEX.
	MDMA_MDMA_C14CR_WEX_Pos   = 0xe     // Position of WEX field.
	MDMA_MDMA_C14CR_WEX_Msk   = 0x4000  // Bit mask of WEX field.
	MDMA_MDMA_C14CR_WEX       = 0x4000  // Bit WEX.
	MDMA_MDMA_C14CR_SWRQ_Pos  = 0x10    // Position of SWRQ field.
	MDMA_MDMA_C14CR_SWRQ_Msk  = 0x10000 // Bit mask of SWRQ field.
	MDMA_MDMA_C14CR_SWRQ      = 0x10000 // Bit SWRQ.

	// MDMA_C14TCR: This register is used to configure the           concerned channel.
	MDMA_MDMA_C14TCR_SINC_Pos   = 0x0        // Position of SINC field.
	MDMA_MDMA_C14TCR_SINC_Msk   = 0x3        // Bit mask of SINC field.
	MDMA_MDMA_C14TCR_DINC_Pos   = 0x2        // Position of DINC field.
	MDMA_MDMA_C14TCR_DINC_Msk   = 0xc        // Bit mask of DINC field.
	MDMA_MDMA_C14TCR_SSIZE_Pos  = 0x4        // Position of SSIZE field.
	MDMA_MDMA_C14TCR_SSIZE_Msk  = 0x30       // Bit mask of SSIZE field.
	MDMA_MDMA_C14TCR_DSIZE_Pos  = 0x6        // Position of DSIZE field.
	MDMA_MDMA_C14TCR_DSIZE_Msk  = 0xc0       // Bit mask of DSIZE field.
	MDMA_MDMA_C14TCR_SINCOS_Pos = 0x8        // Position of SINCOS field.
	MDMA_MDMA_C14TCR_SINCOS_Msk = 0x300      // Bit mask of SINCOS field.
	MDMA_MDMA_C14TCR_DINCOS_Pos = 0xa        // Position of DINCOS field.
	MDMA_MDMA_C14TCR_DINCOS_Msk = 0xc00      // Bit mask of DINCOS field.
	MDMA_MDMA_C14TCR_SBURST_Pos = 0xc        // Position of SBURST field.
	MDMA_MDMA_C14TCR_SBURST_Msk = 0x7000     // Bit mask of SBURST field.
	MDMA_MDMA_C14TCR_DBURST_Pos = 0xf        // Position of DBURST field.
	MDMA_MDMA_C14TCR_DBURST_Msk = 0x38000    // Bit mask of DBURST field.
	MDMA_MDMA_C14TCR_TLEN_Pos   = 0x12       // Position of TLEN field.
	MDMA_MDMA_C14TCR_TLEN_Msk   = 0x1fc0000  // Bit mask of TLEN field.
	MDMA_MDMA_C14TCR_PKE_Pos    = 0x19       // Position of PKE field.
	MDMA_MDMA_C14TCR_PKE_Msk    = 0x2000000  // Bit mask of PKE field.
	MDMA_MDMA_C14TCR_PKE        = 0x2000000  // Bit PKE.
	MDMA_MDMA_C14TCR_PAM_Pos    = 0x1a       // Position of PAM field.
	MDMA_MDMA_C14TCR_PAM_Msk    = 0xc000000  // Bit mask of PAM field.
	MDMA_MDMA_C14TCR_TRGM_Pos   = 0x1c       // Position of TRGM field.
	MDMA_MDMA_C14TCR_TRGM_Msk   = 0x30000000 // Bit mask of TRGM field.
	MDMA_MDMA_C14TCR_SWRM_Pos   = 0x1e       // Position of SWRM field.
	MDMA_MDMA_C14TCR_SWRM_Msk   = 0x40000000 // Bit mask of SWRM field.
	MDMA_MDMA_C14TCR_SWRM       = 0x40000000 // Bit SWRM.
	MDMA_MDMA_C14TCR_BWM_Pos    = 0x1f       // Position of BWM field.
	MDMA_MDMA_C14TCR_BWM_Msk    = 0x80000000 // Bit mask of BWM field.
	MDMA_MDMA_C14TCR_BWM        = 0x80000000 // Bit BWM.

	// MDMA_C14BNDTR: MDMA Channel x block number of data           register
	MDMA_MDMA_C14BNDTR_BNDT_Pos  = 0x0        // Position of BNDT field.
	MDMA_MDMA_C14BNDTR_BNDT_Msk  = 0x1ffff    // Bit mask of BNDT field.
	MDMA_MDMA_C14BNDTR_BRSUM_Pos = 0x12       // Position of BRSUM field.
	MDMA_MDMA_C14BNDTR_BRSUM_Msk = 0x40000    // Bit mask of BRSUM field.
	MDMA_MDMA_C14BNDTR_BRSUM     = 0x40000    // Bit BRSUM.
	MDMA_MDMA_C14BNDTR_BRDUM_Pos = 0x13       // Position of BRDUM field.
	MDMA_MDMA_C14BNDTR_BRDUM_Msk = 0x80000    // Bit mask of BRDUM field.
	MDMA_MDMA_C14BNDTR_BRDUM     = 0x80000    // Bit BRDUM.
	MDMA_MDMA_C14BNDTR_BRC_Pos   = 0x14       // Position of BRC field.
	MDMA_MDMA_C14BNDTR_BRC_Msk   = 0xfff00000 // Bit mask of BRC field.

	// MDMA_C14SAR: MDMA channel x source address           register
	MDMA_MDMA_C14SAR_SAR_Pos = 0x0        // Position of SAR field.
	MDMA_MDMA_C14SAR_SAR_Msk = 0xffffffff // Bit mask of SAR field.

	// MDMA_C14DAR: MDMA channel x destination address           register
	MDMA_MDMA_C14DAR_DAR_Pos = 0x0        // Position of DAR field.
	MDMA_MDMA_C14DAR_DAR_Msk = 0xffffffff // Bit mask of DAR field.

	// MDMA_C14BRUR: MDMA channel x Block Repeat address Update           register
	MDMA_MDMA_C14BRUR_SUV_Pos = 0x0        // Position of SUV field.
	MDMA_MDMA_C14BRUR_SUV_Msk = 0xffff     // Bit mask of SUV field.
	MDMA_MDMA_C14BRUR_DUV_Pos = 0x10       // Position of DUV field.
	MDMA_MDMA_C14BRUR_DUV_Msk = 0xffff0000 // Bit mask of DUV field.

	// MDMA_C14LAR: MDMA channel x Link Address           register
	MDMA_MDMA_C14LAR_LAR_Pos = 0x0        // Position of LAR field.
	MDMA_MDMA_C14LAR_LAR_Msk = 0xffffffff // Bit mask of LAR field.

	// MDMA_C14TBR: MDMA channel x Trigger and Bus selection           Register
	MDMA_MDMA_C14TBR_TSEL_Pos = 0x0     // Position of TSEL field.
	MDMA_MDMA_C14TBR_TSEL_Msk = 0x3f    // Bit mask of TSEL field.
	MDMA_MDMA_C14TBR_SBUS_Pos = 0x10    // Position of SBUS field.
	MDMA_MDMA_C14TBR_SBUS_Msk = 0x10000 // Bit mask of SBUS field.
	MDMA_MDMA_C14TBR_SBUS     = 0x10000 // Bit SBUS.
	MDMA_MDMA_C14TBR_DBUS_Pos = 0x11    // Position of DBUS field.
	MDMA_MDMA_C14TBR_DBUS_Msk = 0x20000 // Bit mask of DBUS field.
	MDMA_MDMA_C14TBR_DBUS     = 0x20000 // Bit DBUS.

	// MDMA_C14MAR: MDMA channel x Mask address           register
	MDMA_MDMA_C14MAR_MAR_Pos = 0x0        // Position of MAR field.
	MDMA_MDMA_C14MAR_MAR_Msk = 0xffffffff // Bit mask of MAR field.

	// MDMA_C14MDR: MDMA channel x Mask Data           register
	MDMA_MDMA_C14MDR_MDR_Pos = 0x0        // Position of MDR field.
	MDMA_MDMA_C14MDR_MDR_Msk = 0xffffffff // Bit mask of MDR field.

	// MDMA_C15ISR: MDMA channel x interrupt/status           register
	MDMA_MDMA_C15ISR_TEIF15_Pos  = 0x0     // Position of TEIF15 field.
	MDMA_MDMA_C15ISR_TEIF15_Msk  = 0x1     // Bit mask of TEIF15 field.
	MDMA_MDMA_C15ISR_TEIF15      = 0x1     // Bit TEIF15.
	MDMA_MDMA_C15ISR_CTCIF15_Pos = 0x1     // Position of CTCIF15 field.
	MDMA_MDMA_C15ISR_CTCIF15_Msk = 0x2     // Bit mask of CTCIF15 field.
	MDMA_MDMA_C15ISR_CTCIF15     = 0x2     // Bit CTCIF15.
	MDMA_MDMA_C15ISR_BRTIF15_Pos = 0x2     // Position of BRTIF15 field.
	MDMA_MDMA_C15ISR_BRTIF15_Msk = 0x4     // Bit mask of BRTIF15 field.
	MDMA_MDMA_C15ISR_BRTIF15     = 0x4     // Bit BRTIF15.
	MDMA_MDMA_C15ISR_BTIF15_Pos  = 0x3     // Position of BTIF15 field.
	MDMA_MDMA_C15ISR_BTIF15_Msk  = 0x8     // Bit mask of BTIF15 field.
	MDMA_MDMA_C15ISR_BTIF15      = 0x8     // Bit BTIF15.
	MDMA_MDMA_C15ISR_TCIF15_Pos  = 0x4     // Position of TCIF15 field.
	MDMA_MDMA_C15ISR_TCIF15_Msk  = 0x10    // Bit mask of TCIF15 field.
	MDMA_MDMA_C15ISR_TCIF15      = 0x10    // Bit TCIF15.
	MDMA_MDMA_C15ISR_CRQA15_Pos  = 0x10    // Position of CRQA15 field.
	MDMA_MDMA_C15ISR_CRQA15_Msk  = 0x10000 // Bit mask of CRQA15 field.
	MDMA_MDMA_C15ISR_CRQA15      = 0x10000 // Bit CRQA15.

	// MDMA_C15IFCR: MDMA channel x interrupt flag clear           register
	MDMA_MDMA_C15IFCR_CTEIF15_Pos  = 0x0  // Position of CTEIF15 field.
	MDMA_MDMA_C15IFCR_CTEIF15_Msk  = 0x1  // Bit mask of CTEIF15 field.
	MDMA_MDMA_C15IFCR_CTEIF15      = 0x1  // Bit CTEIF15.
	MDMA_MDMA_C15IFCR_CCTCIF15_Pos = 0x1  // Position of CCTCIF15 field.
	MDMA_MDMA_C15IFCR_CCTCIF15_Msk = 0x2  // Bit mask of CCTCIF15 field.
	MDMA_MDMA_C15IFCR_CCTCIF15     = 0x2  // Bit CCTCIF15.
	MDMA_MDMA_C15IFCR_CBRTIF15_Pos = 0x2  // Position of CBRTIF15 field.
	MDMA_MDMA_C15IFCR_CBRTIF15_Msk = 0x4  // Bit mask of CBRTIF15 field.
	MDMA_MDMA_C15IFCR_CBRTIF15     = 0x4  // Bit CBRTIF15.
	MDMA_MDMA_C15IFCR_CBTIF15_Pos  = 0x3  // Position of CBTIF15 field.
	MDMA_MDMA_C15IFCR_CBTIF15_Msk  = 0x8  // Bit mask of CBTIF15 field.
	MDMA_MDMA_C15IFCR_CBTIF15      = 0x8  // Bit CBTIF15.
	MDMA_MDMA_C15IFCR_CLTCIF15_Pos = 0x4  // Position of CLTCIF15 field.
	MDMA_MDMA_C15IFCR_CLTCIF15_Msk = 0x10 // Bit mask of CLTCIF15 field.
	MDMA_MDMA_C15IFCR_CLTCIF15     = 0x10 // Bit CLTCIF15.

	// MDMA_C15ESR: MDMA Channel x error status           register
	MDMA_MDMA_C15ESR_TEA_Pos  = 0x0   // Position of TEA field.
	MDMA_MDMA_C15ESR_TEA_Msk  = 0x7f  // Bit mask of TEA field.
	MDMA_MDMA_C15ESR_TED_Pos  = 0x7   // Position of TED field.
	MDMA_MDMA_C15ESR_TED_Msk  = 0x80  // Bit mask of TED field.
	MDMA_MDMA_C15ESR_TED      = 0x80  // Bit TED.
	MDMA_MDMA_C15ESR_TELD_Pos = 0x8   // Position of TELD field.
	MDMA_MDMA_C15ESR_TELD_Msk = 0x100 // Bit mask of TELD field.
	MDMA_MDMA_C15ESR_TELD     = 0x100 // Bit TELD.
	MDMA_MDMA_C15ESR_TEMD_Pos = 0x9   // Position of TEMD field.
	MDMA_MDMA_C15ESR_TEMD_Msk = 0x200 // Bit mask of TEMD field.
	MDMA_MDMA_C15ESR_TEMD     = 0x200 // Bit TEMD.
	MDMA_MDMA_C15ESR_ASE_Pos  = 0xa   // Position of ASE field.
	MDMA_MDMA_C15ESR_ASE_Msk  = 0x400 // Bit mask of ASE field.
	MDMA_MDMA_C15ESR_ASE      = 0x400 // Bit ASE.
	MDMA_MDMA_C15ESR_BSE_Pos  = 0xb   // Position of BSE field.
	MDMA_MDMA_C15ESR_BSE_Msk  = 0x800 // Bit mask of BSE field.
	MDMA_MDMA_C15ESR_BSE      = 0x800 // Bit BSE.

	// MDMA_C15CR: This register is used to control the           concerned channel.
	MDMA_MDMA_C15CR_EN_Pos    = 0x0     // Position of EN field.
	MDMA_MDMA_C15CR_EN_Msk    = 0x1     // Bit mask of EN field.
	MDMA_MDMA_C15CR_EN        = 0x1     // Bit EN.
	MDMA_MDMA_C15CR_TEIE_Pos  = 0x1     // Position of TEIE field.
	MDMA_MDMA_C15CR_TEIE_Msk  = 0x2     // Bit mask of TEIE field.
	MDMA_MDMA_C15CR_TEIE      = 0x2     // Bit TEIE.
	MDMA_MDMA_C15CR_CTCIE_Pos = 0x2     // Position of CTCIE field.
	MDMA_MDMA_C15CR_CTCIE_Msk = 0x4     // Bit mask of CTCIE field.
	MDMA_MDMA_C15CR_CTCIE     = 0x4     // Bit CTCIE.
	MDMA_MDMA_C15CR_BRTIE_Pos = 0x3     // Position of BRTIE field.
	MDMA_MDMA_C15CR_BRTIE_Msk = 0x8     // Bit mask of BRTIE field.
	MDMA_MDMA_C15CR_BRTIE     = 0x8     // Bit BRTIE.
	MDMA_MDMA_C15CR_BTIE_Pos  = 0x4     // Position of BTIE field.
	MDMA_MDMA_C15CR_BTIE_Msk  = 0x10    // Bit mask of BTIE field.
	MDMA_MDMA_C15CR_BTIE      = 0x10    // Bit BTIE.
	MDMA_MDMA_C15CR_TCIE_Pos  = 0x5     // Position of TCIE field.
	MDMA_MDMA_C15CR_TCIE_Msk  = 0x20    // Bit mask of TCIE field.
	MDMA_MDMA_C15CR_TCIE      = 0x20    // Bit TCIE.
	MDMA_MDMA_C15CR_PL_Pos    = 0x6     // Position of PL field.
	MDMA_MDMA_C15CR_PL_Msk    = 0xc0    // Bit mask of PL field.
	MDMA_MDMA_C15CR_BEX_Pos   = 0xc     // Position of BEX field.
	MDMA_MDMA_C15CR_BEX_Msk   = 0x1000  // Bit mask of BEX field.
	MDMA_MDMA_C15CR_BEX       = 0x1000  // Bit BEX.
	MDMA_MDMA_C15CR_HEX_Pos   = 0xd     // Position of HEX field.
	MDMA_MDMA_C15CR_HEX_Msk   = 0x2000  // Bit mask of HEX field.
	MDMA_MDMA_C15CR_HEX       = 0x2000  // Bit HEX.
	MDMA_MDMA_C15CR_WEX_Pos   = 0xe     // Position of WEX field.
	MDMA_MDMA_C15CR_WEX_Msk   = 0x4000  // Bit mask of WEX field.
	MDMA_MDMA_C15CR_WEX       = 0x4000  // Bit WEX.
	MDMA_MDMA_C15CR_SWRQ_Pos  = 0x10    // Position of SWRQ field.
	MDMA_MDMA_C15CR_SWRQ_Msk  = 0x10000 // Bit mask of SWRQ field.
	MDMA_MDMA_C15CR_SWRQ      = 0x10000 // Bit SWRQ.

	// MDMA_C15TCR: This register is used to configure the           concerned channel.
	MDMA_MDMA_C15TCR_SINC_Pos   = 0x0        // Position of SINC field.
	MDMA_MDMA_C15TCR_SINC_Msk   = 0x3        // Bit mask of SINC field.
	MDMA_MDMA_C15TCR_DINC_Pos   = 0x2        // Position of DINC field.
	MDMA_MDMA_C15TCR_DINC_Msk   = 0xc        // Bit mask of DINC field.
	MDMA_MDMA_C15TCR_SSIZE_Pos  = 0x4        // Position of SSIZE field.
	MDMA_MDMA_C15TCR_SSIZE_Msk  = 0x30       // Bit mask of SSIZE field.
	MDMA_MDMA_C15TCR_DSIZE_Pos  = 0x6        // Position of DSIZE field.
	MDMA_MDMA_C15TCR_DSIZE_Msk  = 0xc0       // Bit mask of DSIZE field.
	MDMA_MDMA_C15TCR_SINCOS_Pos = 0x8        // Position of SINCOS field.
	MDMA_MDMA_C15TCR_SINCOS_Msk = 0x300      // Bit mask of SINCOS field.
	MDMA_MDMA_C15TCR_DINCOS_Pos = 0xa        // Position of DINCOS field.
	MDMA_MDMA_C15TCR_DINCOS_Msk = 0xc00      // Bit mask of DINCOS field.
	MDMA_MDMA_C15TCR_SBURST_Pos = 0xc        // Position of SBURST field.
	MDMA_MDMA_C15TCR_SBURST_Msk = 0x7000     // Bit mask of SBURST field.
	MDMA_MDMA_C15TCR_DBURST_Pos = 0xf        // Position of DBURST field.
	MDMA_MDMA_C15TCR_DBURST_Msk = 0x38000    // Bit mask of DBURST field.
	MDMA_MDMA_C15TCR_TLEN_Pos   = 0x12       // Position of TLEN field.
	MDMA_MDMA_C15TCR_TLEN_Msk   = 0x1fc0000  // Bit mask of TLEN field.
	MDMA_MDMA_C15TCR_PKE_Pos    = 0x19       // Position of PKE field.
	MDMA_MDMA_C15TCR_PKE_Msk    = 0x2000000  // Bit mask of PKE field.
	MDMA_MDMA_C15TCR_PKE        = 0x2000000  // Bit PKE.
	MDMA_MDMA_C15TCR_PAM_Pos    = 0x1a       // Position of PAM field.
	MDMA_MDMA_C15TCR_PAM_Msk    = 0xc000000  // Bit mask of PAM field.
	MDMA_MDMA_C15TCR_TRGM_Pos   = 0x1c       // Position of TRGM field.
	MDMA_MDMA_C15TCR_TRGM_Msk   = 0x30000000 // Bit mask of TRGM field.
	MDMA_MDMA_C15TCR_SWRM_Pos   = 0x1e       // Position of SWRM field.
	MDMA_MDMA_C15TCR_SWRM_Msk   = 0x40000000 // Bit mask of SWRM field.
	MDMA_MDMA_C15TCR_SWRM       = 0x40000000 // Bit SWRM.
	MDMA_MDMA_C15TCR_BWM_Pos    = 0x1f       // Position of BWM field.
	MDMA_MDMA_C15TCR_BWM_Msk    = 0x80000000 // Bit mask of BWM field.
	MDMA_MDMA_C15TCR_BWM        = 0x80000000 // Bit BWM.

	// MDMA_C15BNDTR: MDMA Channel x block number of data           register
	MDMA_MDMA_C15BNDTR_BNDT_Pos  = 0x0        // Position of BNDT field.
	MDMA_MDMA_C15BNDTR_BNDT_Msk  = 0x1ffff    // Bit mask of BNDT field.
	MDMA_MDMA_C15BNDTR_BRSUM_Pos = 0x12       // Position of BRSUM field.
	MDMA_MDMA_C15BNDTR_BRSUM_Msk = 0x40000    // Bit mask of BRSUM field.
	MDMA_MDMA_C15BNDTR_BRSUM     = 0x40000    // Bit BRSUM.
	MDMA_MDMA_C15BNDTR_BRDUM_Pos = 0x13       // Position of BRDUM field.
	MDMA_MDMA_C15BNDTR_BRDUM_Msk = 0x80000    // Bit mask of BRDUM field.
	MDMA_MDMA_C15BNDTR_BRDUM     = 0x80000    // Bit BRDUM.
	MDMA_MDMA_C15BNDTR_BRC_Pos   = 0x14       // Position of BRC field.
	MDMA_MDMA_C15BNDTR_BRC_Msk   = 0xfff00000 // Bit mask of BRC field.

	// MDMA_C15SAR: MDMA channel x source address           register
	MDMA_MDMA_C15SAR_SAR_Pos = 0x0        // Position of SAR field.
	MDMA_MDMA_C15SAR_SAR_Msk = 0xffffffff // Bit mask of SAR field.

	// MDMA_C15DAR: MDMA channel x destination address           register
	MDMA_MDMA_C15DAR_DAR_Pos = 0x0        // Position of DAR field.
	MDMA_MDMA_C15DAR_DAR_Msk = 0xffffffff // Bit mask of DAR field.

	// MDMA_C15BRUR: MDMA channel x Block Repeat address Update           register
	MDMA_MDMA_C15BRUR_SUV_Pos = 0x0        // Position of SUV field.
	MDMA_MDMA_C15BRUR_SUV_Msk = 0xffff     // Bit mask of SUV field.
	MDMA_MDMA_C15BRUR_DUV_Pos = 0x10       // Position of DUV field.
	MDMA_MDMA_C15BRUR_DUV_Msk = 0xffff0000 // Bit mask of DUV field.

	// MDMA_C15LAR: MDMA channel x Link Address           register
	MDMA_MDMA_C15LAR_LAR_Pos = 0x0        // Position of LAR field.
	MDMA_MDMA_C15LAR_LAR_Msk = 0xffffffff // Bit mask of LAR field.

	// MDMA_C15TBR: MDMA channel x Trigger and Bus selection           Register
	MDMA_MDMA_C15TBR_TSEL_Pos = 0x0     // Position of TSEL field.
	MDMA_MDMA_C15TBR_TSEL_Msk = 0x3f    // Bit mask of TSEL field.
	MDMA_MDMA_C15TBR_SBUS_Pos = 0x10    // Position of SBUS field.
	MDMA_MDMA_C15TBR_SBUS_Msk = 0x10000 // Bit mask of SBUS field.
	MDMA_MDMA_C15TBR_SBUS     = 0x10000 // Bit SBUS.
	MDMA_MDMA_C15TBR_DBUS_Pos = 0x11    // Position of DBUS field.
	MDMA_MDMA_C15TBR_DBUS_Msk = 0x20000 // Bit mask of DBUS field.
	MDMA_MDMA_C15TBR_DBUS     = 0x20000 // Bit DBUS.

	// MDMA_C15MAR: MDMA channel x Mask address           register
	MDMA_MDMA_C15MAR_MAR_Pos = 0x0        // Position of MAR field.
	MDMA_MDMA_C15MAR_MAR_Msk = 0xffffffff // Bit mask of MAR field.

	// MDMA_C15MDR: MDMA channel x Mask Data           register
	MDMA_MDMA_C15MDR_MDR_Pos = 0x0        // Position of MDR field.
	MDMA_MDMA_C15MDR_MDR_Msk = 0xffffffff // Bit mask of MDR field.
)

// Bitfields for QUADSPI: QUADSPI
const (
	// CR: QUADSPI control register
	QUADSPI_CR_EN_Pos        = 0x0        // Position of EN field.
	QUADSPI_CR_EN_Msk        = 0x1        // Bit mask of EN field.
	QUADSPI_CR_EN            = 0x1        // Bit EN.
	QUADSPI_CR_ABORT_Pos     = 0x1        // Position of ABORT field.
	QUADSPI_CR_ABORT_Msk     = 0x2        // Bit mask of ABORT field.
	QUADSPI_CR_ABORT         = 0x2        // Bit ABORT.
	QUADSPI_CR_DMAEN_Pos     = 0x2        // Position of DMAEN field.
	QUADSPI_CR_DMAEN_Msk     = 0x4        // Bit mask of DMAEN field.
	QUADSPI_CR_DMAEN         = 0x4        // Bit DMAEN.
	QUADSPI_CR_TCEN_Pos      = 0x3        // Position of TCEN field.
	QUADSPI_CR_TCEN_Msk      = 0x8        // Bit mask of TCEN field.
	QUADSPI_CR_TCEN          = 0x8        // Bit TCEN.
	QUADSPI_CR_SSHIFT_Pos    = 0x4        // Position of SSHIFT field.
	QUADSPI_CR_SSHIFT_Msk    = 0x10       // Bit mask of SSHIFT field.
	QUADSPI_CR_SSHIFT        = 0x10       // Bit SSHIFT.
	QUADSPI_CR_DFM_Pos       = 0x6        // Position of DFM field.
	QUADSPI_CR_DFM_Msk       = 0x40       // Bit mask of DFM field.
	QUADSPI_CR_DFM           = 0x40       // Bit DFM.
	QUADSPI_CR_FSEL_Pos      = 0x7        // Position of FSEL field.
	QUADSPI_CR_FSEL_Msk      = 0x80       // Bit mask of FSEL field.
	QUADSPI_CR_FSEL          = 0x80       // Bit FSEL.
	QUADSPI_CR_FTHRES_Pos    = 0x8        // Position of FTHRES field.
	QUADSPI_CR_FTHRES_Msk    = 0x1f00     // Bit mask of FTHRES field.
	QUADSPI_CR_TEIE_Pos      = 0x10       // Position of TEIE field.
	QUADSPI_CR_TEIE_Msk      = 0x10000    // Bit mask of TEIE field.
	QUADSPI_CR_TEIE          = 0x10000    // Bit TEIE.
	QUADSPI_CR_TCIE_Pos      = 0x11       // Position of TCIE field.
	QUADSPI_CR_TCIE_Msk      = 0x20000    // Bit mask of TCIE field.
	QUADSPI_CR_TCIE          = 0x20000    // Bit TCIE.
	QUADSPI_CR_FTIE_Pos      = 0x12       // Position of FTIE field.
	QUADSPI_CR_FTIE_Msk      = 0x40000    // Bit mask of FTIE field.
	QUADSPI_CR_FTIE          = 0x40000    // Bit FTIE.
	QUADSPI_CR_SMIE_Pos      = 0x13       // Position of SMIE field.
	QUADSPI_CR_SMIE_Msk      = 0x80000    // Bit mask of SMIE field.
	QUADSPI_CR_SMIE          = 0x80000    // Bit SMIE.
	QUADSPI_CR_TOIE_Pos      = 0x14       // Position of TOIE field.
	QUADSPI_CR_TOIE_Msk      = 0x100000   // Bit mask of TOIE field.
	QUADSPI_CR_TOIE          = 0x100000   // Bit TOIE.
	QUADSPI_CR_APMS_Pos      = 0x16       // Position of APMS field.
	QUADSPI_CR_APMS_Msk      = 0x400000   // Bit mask of APMS field.
	QUADSPI_CR_APMS          = 0x400000   // Bit APMS.
	QUADSPI_CR_PMM_Pos       = 0x17       // Position of PMM field.
	QUADSPI_CR_PMM_Msk       = 0x800000   // Bit mask of PMM field.
	QUADSPI_CR_PMM           = 0x800000   // Bit PMM.
	QUADSPI_CR_PRESCALER_Pos = 0x18       // Position of PRESCALER field.
	QUADSPI_CR_PRESCALER_Msk = 0xff000000 // Bit mask of PRESCALER field.

	// DCR: QUADSPI device configuration           register
	QUADSPI_DCR_CKMODE_Pos = 0x0      // Position of CKMODE field.
	QUADSPI_DCR_CKMODE_Msk = 0x1      // Bit mask of CKMODE field.
	QUADSPI_DCR_CKMODE     = 0x1      // Bit CKMODE.
	QUADSPI_DCR_CSHT_Pos   = 0x8      // Position of CSHT field.
	QUADSPI_DCR_CSHT_Msk   = 0x700    // Bit mask of CSHT field.
	QUADSPI_DCR_FSIZE_Pos  = 0x10     // Position of FSIZE field.
	QUADSPI_DCR_FSIZE_Msk  = 0x1f0000 // Bit mask of FSIZE field.

	// SR: QUADSPI status register
	QUADSPI_SR_TEF_Pos    = 0x0    // Position of TEF field.
	QUADSPI_SR_TEF_Msk    = 0x1    // Bit mask of TEF field.
	QUADSPI_SR_TEF        = 0x1    // Bit TEF.
	QUADSPI_SR_TCF_Pos    = 0x1    // Position of TCF field.
	QUADSPI_SR_TCF_Msk    = 0x2    // Bit mask of TCF field.
	QUADSPI_SR_TCF        = 0x2    // Bit TCF.
	QUADSPI_SR_FTF_Pos    = 0x2    // Position of FTF field.
	QUADSPI_SR_FTF_Msk    = 0x4    // Bit mask of FTF field.
	QUADSPI_SR_FTF        = 0x4    // Bit FTF.
	QUADSPI_SR_SMF_Pos    = 0x3    // Position of SMF field.
	QUADSPI_SR_SMF_Msk    = 0x8    // Bit mask of SMF field.
	QUADSPI_SR_SMF        = 0x8    // Bit SMF.
	QUADSPI_SR_TOF_Pos    = 0x4    // Position of TOF field.
	QUADSPI_SR_TOF_Msk    = 0x10   // Bit mask of TOF field.
	QUADSPI_SR_TOF        = 0x10   // Bit TOF.
	QUADSPI_SR_BUSY_Pos   = 0x5    // Position of BUSY field.
	QUADSPI_SR_BUSY_Msk   = 0x20   // Bit mask of BUSY field.
	QUADSPI_SR_BUSY       = 0x20   // Bit BUSY.
	QUADSPI_SR_FLEVEL_Pos = 0x8    // Position of FLEVEL field.
	QUADSPI_SR_FLEVEL_Msk = 0x3f00 // Bit mask of FLEVEL field.

	// FCR: QUADSPI flag clear register
	QUADSPI_FCR_CTEF_Pos = 0x0  // Position of CTEF field.
	QUADSPI_FCR_CTEF_Msk = 0x1  // Bit mask of CTEF field.
	QUADSPI_FCR_CTEF     = 0x1  // Bit CTEF.
	QUADSPI_FCR_CTCF_Pos = 0x1  // Position of CTCF field.
	QUADSPI_FCR_CTCF_Msk = 0x2  // Bit mask of CTCF field.
	QUADSPI_FCR_CTCF     = 0x2  // Bit CTCF.
	QUADSPI_FCR_CSMF_Pos = 0x3  // Position of CSMF field.
	QUADSPI_FCR_CSMF_Msk = 0x8  // Bit mask of CSMF field.
	QUADSPI_FCR_CSMF     = 0x8  // Bit CSMF.
	QUADSPI_FCR_CTOF_Pos = 0x4  // Position of CTOF field.
	QUADSPI_FCR_CTOF_Msk = 0x10 // Bit mask of CTOF field.
	QUADSPI_FCR_CTOF     = 0x10 // Bit CTOF.

	// DLR: QUADSPI data length register
	QUADSPI_DLR_DL_Pos = 0x0        // Position of DL field.
	QUADSPI_DLR_DL_Msk = 0xffffffff // Bit mask of DL field.

	// CCR: QUADSPI communication configuration           register
	QUADSPI_CCR_INSTRUCTION_Pos = 0x0        // Position of INSTRUCTION field.
	QUADSPI_CCR_INSTRUCTION_Msk = 0xff       // Bit mask of INSTRUCTION field.
	QUADSPI_CCR_IMODE_Pos       = 0x8        // Position of IMODE field.
	QUADSPI_CCR_IMODE_Msk       = 0x300      // Bit mask of IMODE field.
	QUADSPI_CCR_ADMODE_Pos      = 0xa        // Position of ADMODE field.
	QUADSPI_CCR_ADMODE_Msk      = 0xc00      // Bit mask of ADMODE field.
	QUADSPI_CCR_ADSIZE_Pos      = 0xc        // Position of ADSIZE field.
	QUADSPI_CCR_ADSIZE_Msk      = 0x3000     // Bit mask of ADSIZE field.
	QUADSPI_CCR_ABMODE_Pos      = 0xe        // Position of ABMODE field.
	QUADSPI_CCR_ABMODE_Msk      = 0xc000     // Bit mask of ABMODE field.
	QUADSPI_CCR_ABSIZE_Pos      = 0x10       // Position of ABSIZE field.
	QUADSPI_CCR_ABSIZE_Msk      = 0x30000    // Bit mask of ABSIZE field.
	QUADSPI_CCR_DCYC_Pos        = 0x12       // Position of DCYC field.
	QUADSPI_CCR_DCYC_Msk        = 0x7c0000   // Bit mask of DCYC field.
	QUADSPI_CCR_DMODE_Pos       = 0x18       // Position of DMODE field.
	QUADSPI_CCR_DMODE_Msk       = 0x3000000  // Bit mask of DMODE field.
	QUADSPI_CCR_FMODE_Pos       = 0x1a       // Position of FMODE field.
	QUADSPI_CCR_FMODE_Msk       = 0xc000000  // Bit mask of FMODE field.
	QUADSPI_CCR_SIOO_Pos        = 0x1c       // Position of SIOO field.
	QUADSPI_CCR_SIOO_Msk        = 0x10000000 // Bit mask of SIOO field.
	QUADSPI_CCR_SIOO            = 0x10000000 // Bit SIOO.
	QUADSPI_CCR_DHHC_Pos        = 0x1e       // Position of DHHC field.
	QUADSPI_CCR_DHHC_Msk        = 0x40000000 // Bit mask of DHHC field.
	QUADSPI_CCR_DHHC            = 0x40000000 // Bit DHHC.
	QUADSPI_CCR_DDRM_Pos        = 0x1f       // Position of DDRM field.
	QUADSPI_CCR_DDRM_Msk        = 0x80000000 // Bit mask of DDRM field.
	QUADSPI_CCR_DDRM            = 0x80000000 // Bit DDRM.

	// AR: QUADSPI address register
	QUADSPI_AR_ADDRESS_Pos = 0x0        // Position of ADDRESS field.
	QUADSPI_AR_ADDRESS_Msk = 0xffffffff // Bit mask of ADDRESS field.

	// ABR: QUADSPI alternate bytes           registers
	QUADSPI_ABR_ALTERNATE_Pos = 0x0        // Position of ALTERNATE field.
	QUADSPI_ABR_ALTERNATE_Msk = 0xffffffff // Bit mask of ALTERNATE field.

	// DR: QUADSPI data register
	QUADSPI_DR_DATA_Pos = 0x0        // Position of DATA field.
	QUADSPI_DR_DATA_Msk = 0xffffffff // Bit mask of DATA field.

	// PSMKR: QUADSPI polling status mask           register
	QUADSPI_PSMKR_MASK_Pos = 0x0        // Position of MASK field.
	QUADSPI_PSMKR_MASK_Msk = 0xffffffff // Bit mask of MASK field.

	// PSMAR: QUADSPI polling status match           register
	QUADSPI_PSMAR_MATCH_Pos = 0x0        // Position of MATCH field.
	QUADSPI_PSMAR_MATCH_Msk = 0xffffffff // Bit mask of MATCH field.

	// PIR: QUADSPI polling interval           register
	QUADSPI_PIR_INTERVAL_Pos = 0x0    // Position of INTERVAL field.
	QUADSPI_PIR_INTERVAL_Msk = 0xffff // Bit mask of INTERVAL field.

	// LPTR: QUADSPI low-power timeout           register
	QUADSPI_LPTR_TIMEOUT_Pos = 0x0    // Position of TIMEOUT field.
	QUADSPI_LPTR_TIMEOUT_Msk = 0xffff // Bit mask of TIMEOUT field.
)

// Bitfields for RNG: RNG
const (
	// CR: RNG control register
	RNG_CR_RNGEN_Pos = 0x2  // Position of RNGEN field.
	RNG_CR_RNGEN_Msk = 0x4  // Bit mask of RNGEN field.
	RNG_CR_RNGEN     = 0x4  // Bit RNGEN.
	RNG_CR_IE_Pos    = 0x3  // Position of IE field.
	RNG_CR_IE_Msk    = 0x8  // Bit mask of IE field.
	RNG_CR_IE        = 0x8  // Bit IE.
	RNG_CR_CED_Pos   = 0x5  // Position of CED field.
	RNG_CR_CED_Msk   = 0x20 // Bit mask of CED field.
	RNG_CR_CED       = 0x20 // Bit CED.

	// SR: RNG status register
	RNG_SR_DRDY_Pos = 0x0  // Position of DRDY field.
	RNG_SR_DRDY_Msk = 0x1  // Bit mask of DRDY field.
	RNG_SR_DRDY     = 0x1  // Bit DRDY.
	RNG_SR_CECS_Pos = 0x1  // Position of CECS field.
	RNG_SR_CECS_Msk = 0x2  // Bit mask of CECS field.
	RNG_SR_CECS     = 0x2  // Bit CECS.
	RNG_SR_SECS_Pos = 0x2  // Position of SECS field.
	RNG_SR_SECS_Msk = 0x4  // Bit mask of SECS field.
	RNG_SR_SECS     = 0x4  // Bit SECS.
	RNG_SR_CEIS_Pos = 0x5  // Position of CEIS field.
	RNG_SR_CEIS_Msk = 0x20 // Bit mask of CEIS field.
	RNG_SR_CEIS     = 0x20 // Bit CEIS.
	RNG_SR_SEIS_Pos = 0x6  // Position of SEIS field.
	RNG_SR_SEIS_Msk = 0x40 // Bit mask of SEIS field.
	RNG_SR_SEIS     = 0x40 // Bit SEIS.

	// DR: The RNG_DR register is a read-only register           that delivers a 32-bit random value when read. The           content of this register is valid when DRDY= 1, even if           RNGEN=0.
	RNG_DR_RNDATA_Pos = 0x0        // Position of RNDATA field.
	RNG_DR_RNDATA_Msk = 0xffffffff // Bit mask of RNDATA field.
)

// Bitfields for RTC: RTC
const (
	// RTC_TR: The RTC_TR is the calendar time shadow           register. This register must be written in initialization           mode only. Refer to Calendar initialization and           configuration on page9 and Reading the calendar on           page10.This register is write protected. The write access           procedure is described in RTC register write protection           on page9.
	RTC_RTC_TR_SU_Pos  = 0x0      // Position of SU field.
	RTC_RTC_TR_SU_Msk  = 0xf      // Bit mask of SU field.
	RTC_RTC_TR_ST_Pos  = 0x4      // Position of ST field.
	RTC_RTC_TR_ST_Msk  = 0x70     // Bit mask of ST field.
	RTC_RTC_TR_MNU_Pos = 0x8      // Position of MNU field.
	RTC_RTC_TR_MNU_Msk = 0xf00    // Bit mask of MNU field.
	RTC_RTC_TR_MNT_Pos = 0xc      // Position of MNT field.
	RTC_RTC_TR_MNT_Msk = 0x7000   // Bit mask of MNT field.
	RTC_RTC_TR_HU_Pos  = 0x10     // Position of HU field.
	RTC_RTC_TR_HU_Msk  = 0xf0000  // Bit mask of HU field.
	RTC_RTC_TR_HT_Pos  = 0x14     // Position of HT field.
	RTC_RTC_TR_HT_Msk  = 0x300000 // Bit mask of HT field.
	RTC_RTC_TR_PM_Pos  = 0x16     // Position of PM field.
	RTC_RTC_TR_PM_Msk  = 0x400000 // Bit mask of PM field.
	RTC_RTC_TR_PM      = 0x400000 // Bit PM.

	// RTC_DR: The RTC_DR is the calendar date shadow           register. This register must be written in initialization           mode only. Refer to Calendar initialization and           configuration on page9 and Reading the calendar on           page10.This register is write protected. The write access           procedure is described in RTC register write protection           on page9.
	RTC_RTC_DR_DU_Pos  = 0x0      // Position of DU field.
	RTC_RTC_DR_DU_Msk  = 0xf      // Bit mask of DU field.
	RTC_RTC_DR_DT_Pos  = 0x4      // Position of DT field.
	RTC_RTC_DR_DT_Msk  = 0x30     // Bit mask of DT field.
	RTC_RTC_DR_MU_Pos  = 0x8      // Position of MU field.
	RTC_RTC_DR_MU_Msk  = 0xf00    // Bit mask of MU field.
	RTC_RTC_DR_MT_Pos  = 0xc      // Position of MT field.
	RTC_RTC_DR_MT_Msk  = 0x1000   // Bit mask of MT field.
	RTC_RTC_DR_MT      = 0x1000   // Bit MT.
	RTC_RTC_DR_WDU_Pos = 0xd      // Position of WDU field.
	RTC_RTC_DR_WDU_Msk = 0xe000   // Bit mask of WDU field.
	RTC_RTC_DR_YU_Pos  = 0x10     // Position of YU field.
	RTC_RTC_DR_YU_Msk  = 0xf0000  // Bit mask of YU field.
	RTC_RTC_DR_YT_Pos  = 0x14     // Position of YT field.
	RTC_RTC_DR_YT_Msk  = 0xf00000 // Bit mask of YT field.

	// RTC_CR: RTC control register
	RTC_RTC_CR_WUCKSEL_Pos = 0x0       // Position of WUCKSEL field.
	RTC_RTC_CR_WUCKSEL_Msk = 0x7       // Bit mask of WUCKSEL field.
	RTC_RTC_CR_TSEDGE_Pos  = 0x3       // Position of TSEDGE field.
	RTC_RTC_CR_TSEDGE_Msk  = 0x8       // Bit mask of TSEDGE field.
	RTC_RTC_CR_TSEDGE      = 0x8       // Bit TSEDGE.
	RTC_RTC_CR_REFCKON_Pos = 0x4       // Position of REFCKON field.
	RTC_RTC_CR_REFCKON_Msk = 0x10      // Bit mask of REFCKON field.
	RTC_RTC_CR_REFCKON     = 0x10      // Bit REFCKON.
	RTC_RTC_CR_BYPSHAD_Pos = 0x5       // Position of BYPSHAD field.
	RTC_RTC_CR_BYPSHAD_Msk = 0x20      // Bit mask of BYPSHAD field.
	RTC_RTC_CR_BYPSHAD     = 0x20      // Bit BYPSHAD.
	RTC_RTC_CR_FMT_Pos     = 0x6       // Position of FMT field.
	RTC_RTC_CR_FMT_Msk     = 0x40      // Bit mask of FMT field.
	RTC_RTC_CR_FMT         = 0x40      // Bit FMT.
	RTC_RTC_CR_ALRAE_Pos   = 0x8       // Position of ALRAE field.
	RTC_RTC_CR_ALRAE_Msk   = 0x100     // Bit mask of ALRAE field.
	RTC_RTC_CR_ALRAE       = 0x100     // Bit ALRAE.
	RTC_RTC_CR_ALRBE_Pos   = 0x9       // Position of ALRBE field.
	RTC_RTC_CR_ALRBE_Msk   = 0x200     // Bit mask of ALRBE field.
	RTC_RTC_CR_ALRBE       = 0x200     // Bit ALRBE.
	RTC_RTC_CR_WUTE_Pos    = 0xa       // Position of WUTE field.
	RTC_RTC_CR_WUTE_Msk    = 0x400     // Bit mask of WUTE field.
	RTC_RTC_CR_WUTE        = 0x400     // Bit WUTE.
	RTC_RTC_CR_TSE_Pos     = 0xb       // Position of TSE field.
	RTC_RTC_CR_TSE_Msk     = 0x800     // Bit mask of TSE field.
	RTC_RTC_CR_TSE         = 0x800     // Bit TSE.
	RTC_RTC_CR_ALRAIE_Pos  = 0xc       // Position of ALRAIE field.
	RTC_RTC_CR_ALRAIE_Msk  = 0x1000    // Bit mask of ALRAIE field.
	RTC_RTC_CR_ALRAIE      = 0x1000    // Bit ALRAIE.
	RTC_RTC_CR_ALRBIE_Pos  = 0xd       // Position of ALRBIE field.
	RTC_RTC_CR_ALRBIE_Msk  = 0x2000    // Bit mask of ALRBIE field.
	RTC_RTC_CR_ALRBIE      = 0x2000    // Bit ALRBIE.
	RTC_RTC_CR_WUTIE_Pos   = 0xe       // Position of WUTIE field.
	RTC_RTC_CR_WUTIE_Msk   = 0x4000    // Bit mask of WUTIE field.
	RTC_RTC_CR_WUTIE       = 0x4000    // Bit WUTIE.
	RTC_RTC_CR_TSIE_Pos    = 0xf       // Position of TSIE field.
	RTC_RTC_CR_TSIE_Msk    = 0x8000    // Bit mask of TSIE field.
	RTC_RTC_CR_TSIE        = 0x8000    // Bit TSIE.
	RTC_RTC_CR_ADD1H_Pos   = 0x10      // Position of ADD1H field.
	RTC_RTC_CR_ADD1H_Msk   = 0x10000   // Bit mask of ADD1H field.
	RTC_RTC_CR_ADD1H       = 0x10000   // Bit ADD1H.
	RTC_RTC_CR_SUB1H_Pos   = 0x11      // Position of SUB1H field.
	RTC_RTC_CR_SUB1H_Msk   = 0x20000   // Bit mask of SUB1H field.
	RTC_RTC_CR_SUB1H       = 0x20000   // Bit SUB1H.
	RTC_RTC_CR_BKP_Pos     = 0x12      // Position of BKP field.
	RTC_RTC_CR_BKP_Msk     = 0x40000   // Bit mask of BKP field.
	RTC_RTC_CR_BKP         = 0x40000   // Bit BKP.
	RTC_RTC_CR_COSEL_Pos   = 0x13      // Position of COSEL field.
	RTC_RTC_CR_COSEL_Msk   = 0x80000   // Bit mask of COSEL field.
	RTC_RTC_CR_COSEL       = 0x80000   // Bit COSEL.
	RTC_RTC_CR_POL_Pos     = 0x14      // Position of POL field.
	RTC_RTC_CR_POL_Msk     = 0x100000  // Bit mask of POL field.
	RTC_RTC_CR_POL         = 0x100000  // Bit POL.
	RTC_RTC_CR_OSEL_Pos    = 0x15      // Position of OSEL field.
	RTC_RTC_CR_OSEL_Msk    = 0x600000  // Bit mask of OSEL field.
	RTC_RTC_CR_COE_Pos     = 0x17      // Position of COE field.
	RTC_RTC_CR_COE_Msk     = 0x800000  // Bit mask of COE field.
	RTC_RTC_CR_COE         = 0x800000  // Bit COE.
	RTC_RTC_CR_ITSE_Pos    = 0x18      // Position of ITSE field.
	RTC_RTC_CR_ITSE_Msk    = 0x1000000 // Bit mask of ITSE field.
	RTC_RTC_CR_ITSE        = 0x1000000 // Bit ITSE.

	// RTC_ISR: This register is write protected (except for           RTC_ISR[13:8] bits). The write access procedure is           described in RTC register write protection on           page9.
	RTC_RTC_ISR_ALRAWF_Pos  = 0x0     // Position of ALRAWF field.
	RTC_RTC_ISR_ALRAWF_Msk  = 0x1     // Bit mask of ALRAWF field.
	RTC_RTC_ISR_ALRAWF      = 0x1     // Bit ALRAWF.
	RTC_RTC_ISR_ALRBWF_Pos  = 0x1     // Position of ALRBWF field.
	RTC_RTC_ISR_ALRBWF_Msk  = 0x2     // Bit mask of ALRBWF field.
	RTC_RTC_ISR_ALRBWF      = 0x2     // Bit ALRBWF.
	RTC_RTC_ISR_WUTWF_Pos   = 0x2     // Position of WUTWF field.
	RTC_RTC_ISR_WUTWF_Msk   = 0x4     // Bit mask of WUTWF field.
	RTC_RTC_ISR_WUTWF       = 0x4     // Bit WUTWF.
	RTC_RTC_ISR_SHPF_Pos    = 0x3     // Position of SHPF field.
	RTC_RTC_ISR_SHPF_Msk    = 0x8     // Bit mask of SHPF field.
	RTC_RTC_ISR_SHPF        = 0x8     // Bit SHPF.
	RTC_RTC_ISR_INITS_Pos   = 0x4     // Position of INITS field.
	RTC_RTC_ISR_INITS_Msk   = 0x10    // Bit mask of INITS field.
	RTC_RTC_ISR_INITS       = 0x10    // Bit INITS.
	RTC_RTC_ISR_RSF_Pos     = 0x5     // Position of RSF field.
	RTC_RTC_ISR_RSF_Msk     = 0x20    // Bit mask of RSF field.
	RTC_RTC_ISR_RSF         = 0x20    // Bit RSF.
	RTC_RTC_ISR_INITF_Pos   = 0x6     // Position of INITF field.
	RTC_RTC_ISR_INITF_Msk   = 0x40    // Bit mask of INITF field.
	RTC_RTC_ISR_INITF       = 0x40    // Bit INITF.
	RTC_RTC_ISR_INIT_Pos    = 0x7     // Position of INIT field.
	RTC_RTC_ISR_INIT_Msk    = 0x80    // Bit mask of INIT field.
	RTC_RTC_ISR_INIT        = 0x80    // Bit INIT.
	RTC_RTC_ISR_ALRAF_Pos   = 0x8     // Position of ALRAF field.
	RTC_RTC_ISR_ALRAF_Msk   = 0x100   // Bit mask of ALRAF field.
	RTC_RTC_ISR_ALRAF       = 0x100   // Bit ALRAF.
	RTC_RTC_ISR_ALRBF_Pos   = 0x9     // Position of ALRBF field.
	RTC_RTC_ISR_ALRBF_Msk   = 0x200   // Bit mask of ALRBF field.
	RTC_RTC_ISR_ALRBF       = 0x200   // Bit ALRBF.
	RTC_RTC_ISR_WUTF_Pos    = 0xa     // Position of WUTF field.
	RTC_RTC_ISR_WUTF_Msk    = 0x400   // Bit mask of WUTF field.
	RTC_RTC_ISR_WUTF        = 0x400   // Bit WUTF.
	RTC_RTC_ISR_TSF_Pos     = 0xb     // Position of TSF field.
	RTC_RTC_ISR_TSF_Msk     = 0x800   // Bit mask of TSF field.
	RTC_RTC_ISR_TSF         = 0x800   // Bit TSF.
	RTC_RTC_ISR_TSOVF_Pos   = 0xc     // Position of TSOVF field.
	RTC_RTC_ISR_TSOVF_Msk   = 0x1000  // Bit mask of TSOVF field.
	RTC_RTC_ISR_TSOVF       = 0x1000  // Bit TSOVF.
	RTC_RTC_ISR_TAMP1F_Pos  = 0xd     // Position of TAMP1F field.
	RTC_RTC_ISR_TAMP1F_Msk  = 0x2000  // Bit mask of TAMP1F field.
	RTC_RTC_ISR_TAMP1F      = 0x2000  // Bit TAMP1F.
	RTC_RTC_ISR_TAMP2F_Pos  = 0xe     // Position of TAMP2F field.
	RTC_RTC_ISR_TAMP2F_Msk  = 0x4000  // Bit mask of TAMP2F field.
	RTC_RTC_ISR_TAMP2F      = 0x4000  // Bit TAMP2F.
	RTC_RTC_ISR_TAMP3F_Pos  = 0xf     // Position of TAMP3F field.
	RTC_RTC_ISR_TAMP3F_Msk  = 0x8000  // Bit mask of TAMP3F field.
	RTC_RTC_ISR_TAMP3F      = 0x8000  // Bit TAMP3F.
	RTC_RTC_ISR_RECALPF_Pos = 0x10    // Position of RECALPF field.
	RTC_RTC_ISR_RECALPF_Msk = 0x10000 // Bit mask of RECALPF field.
	RTC_RTC_ISR_RECALPF     = 0x10000 // Bit RECALPF.
	RTC_RTC_ISR_ITSF_Pos    = 0x11    // Position of ITSF field.
	RTC_RTC_ISR_ITSF_Msk    = 0x20000 // Bit mask of ITSF field.
	RTC_RTC_ISR_ITSF        = 0x20000 // Bit ITSF.

	// RTC_PRER: This register must be written in           initialization mode only. The initialization must be           performed in two separate write accesses. Refer to           Calendar initialization and configuration on page9.This           register is write protected. The write access procedure           is described in RTC register write protection on           page9.
	RTC_RTC_PRER_PREDIV_S_Pos = 0x0      // Position of PREDIV_S field.
	RTC_RTC_PRER_PREDIV_S_Msk = 0x7fff   // Bit mask of PREDIV_S field.
	RTC_RTC_PRER_PREDIV_A_Pos = 0x10     // Position of PREDIV_A field.
	RTC_RTC_PRER_PREDIV_A_Msk = 0x7f0000 // Bit mask of PREDIV_A field.

	// RTC_WUTR: This register can be written only when WUTWF           is set to 1 in RTC_ISR.This register is write protected.           The write access procedure is described in RTC register           write protection on page9.
	RTC_RTC_WUTR_WUT_Pos = 0x0    // Position of WUT field.
	RTC_RTC_WUTR_WUT_Msk = 0xffff // Bit mask of WUT field.

	// RTC_ALRMAR: This register can be written only when           ALRAWF is set to 1 in RTC_ISR, or in initialization           mode.This register is write protected. The write access           procedure is described in RTC register write protection           on page9.
	RTC_RTC_ALRMAR_SU_Pos    = 0x0        // Position of SU field.
	RTC_RTC_ALRMAR_SU_Msk    = 0xf        // Bit mask of SU field.
	RTC_RTC_ALRMAR_ST_Pos    = 0x4        // Position of ST field.
	RTC_RTC_ALRMAR_ST_Msk    = 0x70       // Bit mask of ST field.
	RTC_RTC_ALRMAR_MSK1_Pos  = 0x7        // Position of MSK1 field.
	RTC_RTC_ALRMAR_MSK1_Msk  = 0x80       // Bit mask of MSK1 field.
	RTC_RTC_ALRMAR_MSK1      = 0x80       // Bit MSK1.
	RTC_RTC_ALRMAR_MNU_Pos   = 0x8        // Position of MNU field.
	RTC_RTC_ALRMAR_MNU_Msk   = 0xf00      // Bit mask of MNU field.
	RTC_RTC_ALRMAR_MNT_Pos   = 0xc        // Position of MNT field.
	RTC_RTC_ALRMAR_MNT_Msk   = 0x7000     // Bit mask of MNT field.
	RTC_RTC_ALRMAR_MSK2_Pos  = 0xf        // Position of MSK2 field.
	RTC_RTC_ALRMAR_MSK2_Msk  = 0x8000     // Bit mask of MSK2 field.
	RTC_RTC_ALRMAR_MSK2      = 0x8000     // Bit MSK2.
	RTC_RTC_ALRMAR_HU_Pos    = 0x10       // Position of HU field.
	RTC_RTC_ALRMAR_HU_Msk    = 0xf0000    // Bit mask of HU field.
	RTC_RTC_ALRMAR_HT_Pos    = 0x14       // Position of HT field.
	RTC_RTC_ALRMAR_HT_Msk    = 0x300000   // Bit mask of HT field.
	RTC_RTC_ALRMAR_PM_Pos    = 0x16       // Position of PM field.
	RTC_RTC_ALRMAR_PM_Msk    = 0x400000   // Bit mask of PM field.
	RTC_RTC_ALRMAR_PM        = 0x400000   // Bit PM.
	RTC_RTC_ALRMAR_MSK3_Pos  = 0x17       // Position of MSK3 field.
	RTC_RTC_ALRMAR_MSK3_Msk  = 0x800000   // Bit mask of MSK3 field.
	RTC_RTC_ALRMAR_MSK3      = 0x800000   // Bit MSK3.
	RTC_RTC_ALRMAR_DU_Pos    = 0x18       // Position of DU field.
	RTC_RTC_ALRMAR_DU_Msk    = 0xf000000  // Bit mask of DU field.
	RTC_RTC_ALRMAR_DT_Pos    = 0x1c       // Position of DT field.
	RTC_RTC_ALRMAR_DT_Msk    = 0x30000000 // Bit mask of DT field.
	RTC_RTC_ALRMAR_WDSEL_Pos = 0x1e       // Position of WDSEL field.
	RTC_RTC_ALRMAR_WDSEL_Msk = 0x40000000 // Bit mask of WDSEL field.
	RTC_RTC_ALRMAR_WDSEL     = 0x40000000 // Bit WDSEL.
	RTC_RTC_ALRMAR_MSK4_Pos  = 0x1f       // Position of MSK4 field.
	RTC_RTC_ALRMAR_MSK4_Msk  = 0x80000000 // Bit mask of MSK4 field.
	RTC_RTC_ALRMAR_MSK4      = 0x80000000 // Bit MSK4.

	// RTC_ALRMBR: This register can be written only when           ALRBWF is set to 1 in RTC_ISR, or in initialization           mode.This register is write protected. The write access           procedure is described in RTC register write protection           on page9.
	RTC_RTC_ALRMBR_SU_Pos    = 0x0        // Position of SU field.
	RTC_RTC_ALRMBR_SU_Msk    = 0xf        // Bit mask of SU field.
	RTC_RTC_ALRMBR_ST_Pos    = 0x4        // Position of ST field.
	RTC_RTC_ALRMBR_ST_Msk    = 0x70       // Bit mask of ST field.
	RTC_RTC_ALRMBR_MSK1_Pos  = 0x7        // Position of MSK1 field.
	RTC_RTC_ALRMBR_MSK1_Msk  = 0x80       // Bit mask of MSK1 field.
	RTC_RTC_ALRMBR_MSK1      = 0x80       // Bit MSK1.
	RTC_RTC_ALRMBR_MNU_Pos   = 0x8        // Position of MNU field.
	RTC_RTC_ALRMBR_MNU_Msk   = 0xf00      // Bit mask of MNU field.
	RTC_RTC_ALRMBR_MNT_Pos   = 0xc        // Position of MNT field.
	RTC_RTC_ALRMBR_MNT_Msk   = 0x7000     // Bit mask of MNT field.
	RTC_RTC_ALRMBR_MSK2_Pos  = 0xf        // Position of MSK2 field.
	RTC_RTC_ALRMBR_MSK2_Msk  = 0x8000     // Bit mask of MSK2 field.
	RTC_RTC_ALRMBR_MSK2      = 0x8000     // Bit MSK2.
	RTC_RTC_ALRMBR_HU_Pos    = 0x10       // Position of HU field.
	RTC_RTC_ALRMBR_HU_Msk    = 0xf0000    // Bit mask of HU field.
	RTC_RTC_ALRMBR_HT_Pos    = 0x14       // Position of HT field.
	RTC_RTC_ALRMBR_HT_Msk    = 0x300000   // Bit mask of HT field.
	RTC_RTC_ALRMBR_PM_Pos    = 0x16       // Position of PM field.
	RTC_RTC_ALRMBR_PM_Msk    = 0x400000   // Bit mask of PM field.
	RTC_RTC_ALRMBR_PM        = 0x400000   // Bit PM.
	RTC_RTC_ALRMBR_MSK3_Pos  = 0x17       // Position of MSK3 field.
	RTC_RTC_ALRMBR_MSK3_Msk  = 0x800000   // Bit mask of MSK3 field.
	RTC_RTC_ALRMBR_MSK3      = 0x800000   // Bit MSK3.
	RTC_RTC_ALRMBR_DU_Pos    = 0x18       // Position of DU field.
	RTC_RTC_ALRMBR_DU_Msk    = 0xf000000  // Bit mask of DU field.
	RTC_RTC_ALRMBR_DT_Pos    = 0x1c       // Position of DT field.
	RTC_RTC_ALRMBR_DT_Msk    = 0x30000000 // Bit mask of DT field.
	RTC_RTC_ALRMBR_WDSEL_Pos = 0x1e       // Position of WDSEL field.
	RTC_RTC_ALRMBR_WDSEL_Msk = 0x40000000 // Bit mask of WDSEL field.
	RTC_RTC_ALRMBR_WDSEL     = 0x40000000 // Bit WDSEL.
	RTC_RTC_ALRMBR_MSK4_Pos  = 0x1f       // Position of MSK4 field.
	RTC_RTC_ALRMBR_MSK4_Msk  = 0x80000000 // Bit mask of MSK4 field.
	RTC_RTC_ALRMBR_MSK4      = 0x80000000 // Bit MSK4.

	// RTC_WPR: RTC write protection register
	RTC_RTC_WPR_KEY_Pos = 0x0  // Position of KEY field.
	RTC_RTC_WPR_KEY_Msk = 0xff // Bit mask of KEY field.

	// RTC_SSR: RTC sub second register
	RTC_RTC_SSR_SS_Pos = 0x0    // Position of SS field.
	RTC_RTC_SSR_SS_Msk = 0xffff // Bit mask of SS field.

	// RTC_SHIFTR: This register is write protected. The write           access procedure is described in RTC register write           protection on page9.
	RTC_RTC_SHIFTR_SUBFS_Pos = 0x0        // Position of SUBFS field.
	RTC_RTC_SHIFTR_SUBFS_Msk = 0x7fff     // Bit mask of SUBFS field.
	RTC_RTC_SHIFTR_ADD1S_Pos = 0x1f       // Position of ADD1S field.
	RTC_RTC_SHIFTR_ADD1S_Msk = 0x80000000 // Bit mask of ADD1S field.
	RTC_RTC_SHIFTR_ADD1S     = 0x80000000 // Bit ADD1S.

	// RTC_TSTR: The content of this register is valid only           when TSF is set to 1 in RTC_ISR. It is cleared when TSF           bit is reset.
	RTC_RTC_TSTR_SU_Pos  = 0x0      // Position of SU field.
	RTC_RTC_TSTR_SU_Msk  = 0xf      // Bit mask of SU field.
	RTC_RTC_TSTR_ST_Pos  = 0x4      // Position of ST field.
	RTC_RTC_TSTR_ST_Msk  = 0x70     // Bit mask of ST field.
	RTC_RTC_TSTR_MNU_Pos = 0x8      // Position of MNU field.
	RTC_RTC_TSTR_MNU_Msk = 0xf00    // Bit mask of MNU field.
	RTC_RTC_TSTR_MNT_Pos = 0xc      // Position of MNT field.
	RTC_RTC_TSTR_MNT_Msk = 0x7000   // Bit mask of MNT field.
	RTC_RTC_TSTR_HU_Pos  = 0x10     // Position of HU field.
	RTC_RTC_TSTR_HU_Msk  = 0xf0000  // Bit mask of HU field.
	RTC_RTC_TSTR_HT_Pos  = 0x14     // Position of HT field.
	RTC_RTC_TSTR_HT_Msk  = 0x300000 // Bit mask of HT field.
	RTC_RTC_TSTR_PM_Pos  = 0x16     // Position of PM field.
	RTC_RTC_TSTR_PM_Msk  = 0x400000 // Bit mask of PM field.
	RTC_RTC_TSTR_PM      = 0x400000 // Bit PM.

	// RTC_TSDR: The content of this register is valid only           when TSF is set to 1 in RTC_ISR. It is cleared when TSF           bit is reset.
	RTC_RTC_TSDR_DU_Pos  = 0x0    // Position of DU field.
	RTC_RTC_TSDR_DU_Msk  = 0xf    // Bit mask of DU field.
	RTC_RTC_TSDR_DT_Pos  = 0x4    // Position of DT field.
	RTC_RTC_TSDR_DT_Msk  = 0x30   // Bit mask of DT field.
	RTC_RTC_TSDR_MU_Pos  = 0x8    // Position of MU field.
	RTC_RTC_TSDR_MU_Msk  = 0xf00  // Bit mask of MU field.
	RTC_RTC_TSDR_MT_Pos  = 0xc    // Position of MT field.
	RTC_RTC_TSDR_MT_Msk  = 0x1000 // Bit mask of MT field.
	RTC_RTC_TSDR_MT      = 0x1000 // Bit MT.
	RTC_RTC_TSDR_WDU_Pos = 0xd    // Position of WDU field.
	RTC_RTC_TSDR_WDU_Msk = 0xe000 // Bit mask of WDU field.

	// RTC_TSSSR: The content of this register is valid only           when RTC_ISR/TSF is set. It is cleared when the           RTC_ISR/TSF bit is reset.
	RTC_RTC_TSSSR_SS_Pos = 0x0    // Position of SS field.
	RTC_RTC_TSSSR_SS_Msk = 0xffff // Bit mask of SS field.

	// RTC_CALR: This register is write protected. The write           access procedure is described in RTC register write           protection on page9.
	RTC_RTC_CALR_CALM_Pos   = 0x0    // Position of CALM field.
	RTC_RTC_CALR_CALM_Msk   = 0x1ff  // Bit mask of CALM field.
	RTC_RTC_CALR_CALW16_Pos = 0xd    // Position of CALW16 field.
	RTC_RTC_CALR_CALW16_Msk = 0x2000 // Bit mask of CALW16 field.
	RTC_RTC_CALR_CALW16     = 0x2000 // Bit CALW16.
	RTC_RTC_CALR_CALW8_Pos  = 0xe    // Position of CALW8 field.
	RTC_RTC_CALR_CALW8_Msk  = 0x4000 // Bit mask of CALW8 field.
	RTC_RTC_CALR_CALW8      = 0x4000 // Bit CALW8.
	RTC_RTC_CALR_CALP_Pos   = 0xf    // Position of CALP field.
	RTC_RTC_CALR_CALP_Msk   = 0x8000 // Bit mask of CALP field.
	RTC_RTC_CALR_CALP       = 0x8000 // Bit CALP.

	// RTC_TAMPCR: RTC tamper and alternate function           configuration register
	RTC_RTC_TAMPCR_TAMP1E_Pos       = 0x0       // Position of TAMP1E field.
	RTC_RTC_TAMPCR_TAMP1E_Msk       = 0x1       // Bit mask of TAMP1E field.
	RTC_RTC_TAMPCR_TAMP1E           = 0x1       // Bit TAMP1E.
	RTC_RTC_TAMPCR_TAMP1TRG_Pos     = 0x1       // Position of TAMP1TRG field.
	RTC_RTC_TAMPCR_TAMP1TRG_Msk     = 0x2       // Bit mask of TAMP1TRG field.
	RTC_RTC_TAMPCR_TAMP1TRG         = 0x2       // Bit TAMP1TRG.
	RTC_RTC_TAMPCR_TAMPIE_Pos       = 0x2       // Position of TAMPIE field.
	RTC_RTC_TAMPCR_TAMPIE_Msk       = 0x4       // Bit mask of TAMPIE field.
	RTC_RTC_TAMPCR_TAMPIE           = 0x4       // Bit TAMPIE.
	RTC_RTC_TAMPCR_TAMP2E_Pos       = 0x3       // Position of TAMP2E field.
	RTC_RTC_TAMPCR_TAMP2E_Msk       = 0x8       // Bit mask of TAMP2E field.
	RTC_RTC_TAMPCR_TAMP2E           = 0x8       // Bit TAMP2E.
	RTC_RTC_TAMPCR_TAMP2TRG_Pos     = 0x4       // Position of TAMP2TRG field.
	RTC_RTC_TAMPCR_TAMP2TRG_Msk     = 0x10      // Bit mask of TAMP2TRG field.
	RTC_RTC_TAMPCR_TAMP2TRG         = 0x10      // Bit TAMP2TRG.
	RTC_RTC_TAMPCR_TAMP3E_Pos       = 0x5       // Position of TAMP3E field.
	RTC_RTC_TAMPCR_TAMP3E_Msk       = 0x20      // Bit mask of TAMP3E field.
	RTC_RTC_TAMPCR_TAMP3E           = 0x20      // Bit TAMP3E.
	RTC_RTC_TAMPCR_TAMP3TRG_Pos     = 0x6       // Position of TAMP3TRG field.
	RTC_RTC_TAMPCR_TAMP3TRG_Msk     = 0x40      // Bit mask of TAMP3TRG field.
	RTC_RTC_TAMPCR_TAMP3TRG         = 0x40      // Bit TAMP3TRG.
	RTC_RTC_TAMPCR_TAMPTS_Pos       = 0x7       // Position of TAMPTS field.
	RTC_RTC_TAMPCR_TAMPTS_Msk       = 0x80      // Bit mask of TAMPTS field.
	RTC_RTC_TAMPCR_TAMPTS           = 0x80      // Bit TAMPTS.
	RTC_RTC_TAMPCR_TAMPFREQ_Pos     = 0x8       // Position of TAMPFREQ field.
	RTC_RTC_TAMPCR_TAMPFREQ_Msk     = 0x700     // Bit mask of TAMPFREQ field.
	RTC_RTC_TAMPCR_TAMPFLT_Pos      = 0xb       // Position of TAMPFLT field.
	RTC_RTC_TAMPCR_TAMPFLT_Msk      = 0x1800    // Bit mask of TAMPFLT field.
	RTC_RTC_TAMPCR_TAMPPRCH_Pos     = 0xd       // Position of TAMPPRCH field.
	RTC_RTC_TAMPCR_TAMPPRCH_Msk     = 0x6000    // Bit mask of TAMPPRCH field.
	RTC_RTC_TAMPCR_TAMPPUDIS_Pos    = 0xf       // Position of TAMPPUDIS field.
	RTC_RTC_TAMPCR_TAMPPUDIS_Msk    = 0x8000    // Bit mask of TAMPPUDIS field.
	RTC_RTC_TAMPCR_TAMPPUDIS        = 0x8000    // Bit TAMPPUDIS.
	RTC_RTC_TAMPCR_TAMP1IE_Pos      = 0x10      // Position of TAMP1IE field.
	RTC_RTC_TAMPCR_TAMP1IE_Msk      = 0x10000   // Bit mask of TAMP1IE field.
	RTC_RTC_TAMPCR_TAMP1IE          = 0x10000   // Bit TAMP1IE.
	RTC_RTC_TAMPCR_TAMP1NOERASE_Pos = 0x11      // Position of TAMP1NOERASE field.
	RTC_RTC_TAMPCR_TAMP1NOERASE_Msk = 0x20000   // Bit mask of TAMP1NOERASE field.
	RTC_RTC_TAMPCR_TAMP1NOERASE     = 0x20000   // Bit TAMP1NOERASE.
	RTC_RTC_TAMPCR_TAMP1MF_Pos      = 0x12      // Position of TAMP1MF field.
	RTC_RTC_TAMPCR_TAMP1MF_Msk      = 0x40000   // Bit mask of TAMP1MF field.
	RTC_RTC_TAMPCR_TAMP1MF          = 0x40000   // Bit TAMP1MF.
	RTC_RTC_TAMPCR_TAMP2IE_Pos      = 0x13      // Position of TAMP2IE field.
	RTC_RTC_TAMPCR_TAMP2IE_Msk      = 0x80000   // Bit mask of TAMP2IE field.
	RTC_RTC_TAMPCR_TAMP2IE          = 0x80000   // Bit TAMP2IE.
	RTC_RTC_TAMPCR_TAMP2NOERASE_Pos = 0x14      // Position of TAMP2NOERASE field.
	RTC_RTC_TAMPCR_TAMP2NOERASE_Msk = 0x100000  // Bit mask of TAMP2NOERASE field.
	RTC_RTC_TAMPCR_TAMP2NOERASE     = 0x100000  // Bit TAMP2NOERASE.
	RTC_RTC_TAMPCR_TAMP2MF_Pos      = 0x15      // Position of TAMP2MF field.
	RTC_RTC_TAMPCR_TAMP2MF_Msk      = 0x200000  // Bit mask of TAMP2MF field.
	RTC_RTC_TAMPCR_TAMP2MF          = 0x200000  // Bit TAMP2MF.
	RTC_RTC_TAMPCR_TAMP3IE_Pos      = 0x16      // Position of TAMP3IE field.
	RTC_RTC_TAMPCR_TAMP3IE_Msk      = 0x400000  // Bit mask of TAMP3IE field.
	RTC_RTC_TAMPCR_TAMP3IE          = 0x400000  // Bit TAMP3IE.
	RTC_RTC_TAMPCR_TAMP3NOERASE_Pos = 0x17      // Position of TAMP3NOERASE field.
	RTC_RTC_TAMPCR_TAMP3NOERASE_Msk = 0x800000  // Bit mask of TAMP3NOERASE field.
	RTC_RTC_TAMPCR_TAMP3NOERASE     = 0x800000  // Bit TAMP3NOERASE.
	RTC_RTC_TAMPCR_TAMP3MF_Pos      = 0x18      // Position of TAMP3MF field.
	RTC_RTC_TAMPCR_TAMP3MF_Msk      = 0x1000000 // Bit mask of TAMP3MF field.
	RTC_RTC_TAMPCR_TAMP3MF          = 0x1000000 // Bit TAMP3MF.

	// RTC_ALRMASSR: This register can be written only when ALRAE           is reset in RTC_CR register, or in initialization           mode.This register is write protected. The write access           procedure is described in RTC register write protection           on page9
	RTC_RTC_ALRMASSR_SS_Pos     = 0x0       // Position of SS field.
	RTC_RTC_ALRMASSR_SS_Msk     = 0x7fff    // Bit mask of SS field.
	RTC_RTC_ALRMASSR_MASKSS_Pos = 0x18      // Position of MASKSS field.
	RTC_RTC_ALRMASSR_MASKSS_Msk = 0xf000000 // Bit mask of MASKSS field.

	// RTC_ALRMBSSR: This register can be written only when ALRBE           is reset in RTC_CR register, or in initialization           mode.This register is write protected.The write access           procedure is described in Section: RTC register write           protection.
	RTC_RTC_ALRMBSSR_SS_Pos     = 0x0       // Position of SS field.
	RTC_RTC_ALRMBSSR_SS_Msk     = 0x7fff    // Bit mask of SS field.
	RTC_RTC_ALRMBSSR_MASKSS_Pos = 0x18      // Position of MASKSS field.
	RTC_RTC_ALRMBSSR_MASKSS_Msk = 0xf000000 // Bit mask of MASKSS field.

	// RTC_OR: RTC option register
	RTC_RTC_OR_RTC_ALARM_TYPE_Pos = 0x0 // Position of RTC_ALARM_TYPE field.
	RTC_RTC_OR_RTC_ALARM_TYPE_Msk = 0x1 // Bit mask of RTC_ALARM_TYPE field.
	RTC_RTC_OR_RTC_ALARM_TYPE     = 0x1 // Bit RTC_ALARM_TYPE.
	RTC_RTC_OR_RTC_OUT_RMP_Pos    = 0x1 // Position of RTC_OUT_RMP field.
	RTC_RTC_OR_RTC_OUT_RMP_Msk    = 0x2 // Bit mask of RTC_OUT_RMP field.
	RTC_RTC_OR_RTC_OUT_RMP        = 0x2 // Bit RTC_OUT_RMP.

	// RTC_BKP0R: RTC backup registers
	RTC_RTC_BKP0R_BKP_Pos = 0x0        // Position of BKP field.
	RTC_RTC_BKP0R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// RTC_BKP1R: RTC backup registers
	RTC_RTC_BKP1R_BKP_Pos = 0x0        // Position of BKP field.
	RTC_RTC_BKP1R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// RTC_BKP2R: RTC backup registers
	RTC_RTC_BKP2R_BKP_Pos = 0x0        // Position of BKP field.
	RTC_RTC_BKP2R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// RTC_BKP3R: RTC backup registers
	RTC_RTC_BKP3R_BKP_Pos = 0x0        // Position of BKP field.
	RTC_RTC_BKP3R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// RTC_BKP4R: RTC backup registers
	RTC_RTC_BKP4R_BKP_Pos = 0x0        // Position of BKP field.
	RTC_RTC_BKP4R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// RTC_BKP5R: RTC backup registers
	RTC_RTC_BKP5R_BKP_Pos = 0x0        // Position of BKP field.
	RTC_RTC_BKP5R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// RTC_BKP6R: RTC backup registers
	RTC_RTC_BKP6R_BKP_Pos = 0x0        // Position of BKP field.
	RTC_RTC_BKP6R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// RTC_BKP7R: RTC backup registers
	RTC_RTC_BKP7R_BKP_Pos = 0x0        // Position of BKP field.
	RTC_RTC_BKP7R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// RTC_BKP8R: RTC backup registers
	RTC_RTC_BKP8R_BKP_Pos = 0x0        // Position of BKP field.
	RTC_RTC_BKP8R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// RTC_BKP9R: RTC backup registers
	RTC_RTC_BKP9R_BKP_Pos = 0x0        // Position of BKP field.
	RTC_RTC_BKP9R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// RTC_BKP10R: RTC backup registers
	RTC_RTC_BKP10R_BKP_Pos = 0x0        // Position of BKP field.
	RTC_RTC_BKP10R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// RTC_BKP11R: RTC backup registers
	RTC_RTC_BKP11R_BKP_Pos = 0x0        // Position of BKP field.
	RTC_RTC_BKP11R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// RTC_BKP12R: RTC backup registers
	RTC_RTC_BKP12R_BKP_Pos = 0x0        // Position of BKP field.
	RTC_RTC_BKP12R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// RTC_BKP13R: RTC backup registers
	RTC_RTC_BKP13R_BKP_Pos = 0x0        // Position of BKP field.
	RTC_RTC_BKP13R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// RTC_BKP14R: RTC backup registers
	RTC_RTC_BKP14R_BKP_Pos = 0x0        // Position of BKP field.
	RTC_RTC_BKP14R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// RTC_BKP15R: RTC backup registers
	RTC_RTC_BKP15R_BKP_Pos = 0x0        // Position of BKP field.
	RTC_RTC_BKP15R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// RTC_BKP16R: RTC backup registers
	RTC_RTC_BKP16R_BKP_Pos = 0x0        // Position of BKP field.
	RTC_RTC_BKP16R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// RTC_BKP17R: RTC backup registers
	RTC_RTC_BKP17R_BKP_Pos = 0x0        // Position of BKP field.
	RTC_RTC_BKP17R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// RTC_BKP18R: RTC backup registers
	RTC_RTC_BKP18R_BKP_Pos = 0x0        // Position of BKP field.
	RTC_RTC_BKP18R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// RTC_BKP19R: RTC backup registers
	RTC_RTC_BKP19R_BKP_Pos = 0x0        // Position of BKP field.
	RTC_RTC_BKP19R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// RTC_BKP20R: RTC backup registers
	RTC_RTC_BKP20R_BKP_Pos = 0x0        // Position of BKP field.
	RTC_RTC_BKP20R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// RTC_BKP21R: RTC backup registers
	RTC_RTC_BKP21R_BKP_Pos = 0x0        // Position of BKP field.
	RTC_RTC_BKP21R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// RTC_BKP22R: RTC backup registers
	RTC_RTC_BKP22R_BKP_Pos = 0x0        // Position of BKP field.
	RTC_RTC_BKP22R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// RTC_BKP23R: RTC backup registers
	RTC_RTC_BKP23R_BKP_Pos = 0x0        // Position of BKP field.
	RTC_RTC_BKP23R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// RTC_BKP24R: RTC backup registers
	RTC_RTC_BKP24R_BKP_Pos = 0x0        // Position of BKP field.
	RTC_RTC_BKP24R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// RTC_BKP25R: RTC backup registers
	RTC_RTC_BKP25R_BKP_Pos = 0x0        // Position of BKP field.
	RTC_RTC_BKP25R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// RTC_BKP26R: RTC backup registers
	RTC_RTC_BKP26R_BKP_Pos = 0x0        // Position of BKP field.
	RTC_RTC_BKP26R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// RTC_BKP27R: RTC backup registers
	RTC_RTC_BKP27R_BKP_Pos = 0x0        // Position of BKP field.
	RTC_RTC_BKP27R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// RTC_BKP28R: RTC backup registers
	RTC_RTC_BKP28R_BKP_Pos = 0x0        // Position of BKP field.
	RTC_RTC_BKP28R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// RTC_BKP29R: RTC backup registers
	RTC_RTC_BKP29R_BKP_Pos = 0x0        // Position of BKP field.
	RTC_RTC_BKP29R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// RTC_BKP30R: RTC backup registers
	RTC_RTC_BKP30R_BKP_Pos = 0x0        // Position of BKP field.
	RTC_RTC_BKP30R_BKP_Msk = 0xffffffff // Bit mask of BKP field.

	// RTC_BKP31R: RTC backup registers
	RTC_RTC_BKP31R_BKP_Pos = 0x0        // Position of BKP field.
	RTC_RTC_BKP31R_BKP_Msk = 0xffffffff // Bit mask of BKP field.
)

// Bitfields for SAI4: SAI
const (
	// SAI_GCR: Global configuration register
	SAI_SAI_GCR_SYNCOUT_Pos = 0x4  // Position of SYNCOUT field.
	SAI_SAI_GCR_SYNCOUT_Msk = 0x30 // Bit mask of SYNCOUT field.
	SAI_SAI_GCR_SYNCIN_Pos  = 0x0  // Position of SYNCIN field.
	SAI_SAI_GCR_SYNCIN_Msk  = 0x3  // Bit mask of SYNCIN field.

	// SAI_ACR1: Configuration register 1
	SAI_SAI_ACR1_MODE_Pos     = 0x0       // Position of MODE field.
	SAI_SAI_ACR1_MODE_Msk     = 0x3       // Bit mask of MODE field.
	SAI_SAI_ACR1_PRTCFG_Pos   = 0x2       // Position of PRTCFG field.
	SAI_SAI_ACR1_PRTCFG_Msk   = 0xc       // Bit mask of PRTCFG field.
	SAI_SAI_ACR1_DS_Pos       = 0x5       // Position of DS field.
	SAI_SAI_ACR1_DS_Msk       = 0xe0      // Bit mask of DS field.
	SAI_SAI_ACR1_LSBFIRST_Pos = 0x8       // Position of LSBFIRST field.
	SAI_SAI_ACR1_LSBFIRST_Msk = 0x100     // Bit mask of LSBFIRST field.
	SAI_SAI_ACR1_LSBFIRST     = 0x100     // Bit LSBFIRST.
	SAI_SAI_ACR1_CKSTR_Pos    = 0x9       // Position of CKSTR field.
	SAI_SAI_ACR1_CKSTR_Msk    = 0x200     // Bit mask of CKSTR field.
	SAI_SAI_ACR1_CKSTR        = 0x200     // Bit CKSTR.
	SAI_SAI_ACR1_SYNCEN_Pos   = 0xa       // Position of SYNCEN field.
	SAI_SAI_ACR1_SYNCEN_Msk   = 0xc00     // Bit mask of SYNCEN field.
	SAI_SAI_ACR1_MONO_Pos     = 0xc       // Position of MONO field.
	SAI_SAI_ACR1_MONO_Msk     = 0x1000    // Bit mask of MONO field.
	SAI_SAI_ACR1_MONO         = 0x1000    // Bit MONO.
	SAI_SAI_ACR1_OUTDRIV_Pos  = 0xd       // Position of OUTDRIV field.
	SAI_SAI_ACR1_OUTDRIV_Msk  = 0x2000    // Bit mask of OUTDRIV field.
	SAI_SAI_ACR1_OUTDRIV      = 0x2000    // Bit OUTDRIV.
	SAI_SAI_ACR1_SAIXEN_Pos   = 0x10      // Position of SAIXEN field.
	SAI_SAI_ACR1_SAIXEN_Msk   = 0x10000   // Bit mask of SAIXEN field.
	SAI_SAI_ACR1_SAIXEN       = 0x10000   // Bit SAIXEN.
	SAI_SAI_ACR1_DMAEN_Pos    = 0x11      // Position of DMAEN field.
	SAI_SAI_ACR1_DMAEN_Msk    = 0x20000   // Bit mask of DMAEN field.
	SAI_SAI_ACR1_DMAEN        = 0x20000   // Bit DMAEN.
	SAI_SAI_ACR1_NOMCK_Pos    = 0x13      // Position of NOMCK field.
	SAI_SAI_ACR1_NOMCK_Msk    = 0x80000   // Bit mask of NOMCK field.
	SAI_SAI_ACR1_NOMCK        = 0x80000   // Bit NOMCK.
	SAI_SAI_ACR1_MCKDIV_Pos   = 0x14      // Position of MCKDIV field.
	SAI_SAI_ACR1_MCKDIV_Msk   = 0xf00000  // Bit mask of MCKDIV field.
	SAI_SAI_ACR1_OSR_Pos      = 0x1a      // Position of OSR field.
	SAI_SAI_ACR1_OSR_Msk      = 0x4000000 // Bit mask of OSR field.
	SAI_SAI_ACR1_OSR          = 0x4000000 // Bit OSR.

	// SAI_ACR2: Configuration register 2
	SAI_SAI_ACR2_FTH_Pos     = 0x0    // Position of FTH field.
	SAI_SAI_ACR2_FTH_Msk     = 0x7    // Bit mask of FTH field.
	SAI_SAI_ACR2_FFLUSH_Pos  = 0x3    // Position of FFLUSH field.
	SAI_SAI_ACR2_FFLUSH_Msk  = 0x8    // Bit mask of FFLUSH field.
	SAI_SAI_ACR2_FFLUSH      = 0x8    // Bit FFLUSH.
	SAI_SAI_ACR2_TRIS_Pos    = 0x4    // Position of TRIS field.
	SAI_SAI_ACR2_TRIS_Msk    = 0x10   // Bit mask of TRIS field.
	SAI_SAI_ACR2_TRIS        = 0x10   // Bit TRIS.
	SAI_SAI_ACR2_MUTE_Pos    = 0x5    // Position of MUTE field.
	SAI_SAI_ACR2_MUTE_Msk    = 0x20   // Bit mask of MUTE field.
	SAI_SAI_ACR2_MUTE        = 0x20   // Bit MUTE.
	SAI_SAI_ACR2_MUTEVAL_Pos = 0x6    // Position of MUTEVAL field.
	SAI_SAI_ACR2_MUTEVAL_Msk = 0x40   // Bit mask of MUTEVAL field.
	SAI_SAI_ACR2_MUTEVAL     = 0x40   // Bit MUTEVAL.
	SAI_SAI_ACR2_MUTECNT_Pos = 0x7    // Position of MUTECNT field.
	SAI_SAI_ACR2_MUTECNT_Msk = 0x1f80 // Bit mask of MUTECNT field.
	SAI_SAI_ACR2_CPL_Pos     = 0xd    // Position of CPL field.
	SAI_SAI_ACR2_CPL_Msk     = 0x2000 // Bit mask of CPL field.
	SAI_SAI_ACR2_CPL         = 0x2000 // Bit CPL.
	SAI_SAI_ACR2_COMP_Pos    = 0xe    // Position of COMP field.
	SAI_SAI_ACR2_COMP_Msk    = 0xc000 // Bit mask of COMP field.

	// SAI_AFRCR: This register has no meaning in AC97 and           SPDIF audio protocol
	SAI_SAI_AFRCR_FRL_Pos   = 0x0     // Position of FRL field.
	SAI_SAI_AFRCR_FRL_Msk   = 0xff    // Bit mask of FRL field.
	SAI_SAI_AFRCR_FSALL_Pos = 0x8     // Position of FSALL field.
	SAI_SAI_AFRCR_FSALL_Msk = 0x7f00  // Bit mask of FSALL field.
	SAI_SAI_AFRCR_FSDEF_Pos = 0x10    // Position of FSDEF field.
	SAI_SAI_AFRCR_FSDEF_Msk = 0x10000 // Bit mask of FSDEF field.
	SAI_SAI_AFRCR_FSDEF     = 0x10000 // Bit FSDEF.
	SAI_SAI_AFRCR_FSPOL_Pos = 0x11    // Position of FSPOL field.
	SAI_SAI_AFRCR_FSPOL_Msk = 0x20000 // Bit mask of FSPOL field.
	SAI_SAI_AFRCR_FSPOL     = 0x20000 // Bit FSPOL.
	SAI_SAI_AFRCR_FSOFF_Pos = 0x12    // Position of FSOFF field.
	SAI_SAI_AFRCR_FSOFF_Msk = 0x40000 // Bit mask of FSOFF field.
	SAI_SAI_AFRCR_FSOFF     = 0x40000 // Bit FSOFF.

	// SAI_ASLOTR: This register has no meaning in AC97 and           SPDIF audio protocol
	SAI_SAI_ASLOTR_FBOFF_Pos  = 0x0        // Position of FBOFF field.
	SAI_SAI_ASLOTR_FBOFF_Msk  = 0x1f       // Bit mask of FBOFF field.
	SAI_SAI_ASLOTR_SLOTSZ_Pos = 0x6        // Position of SLOTSZ field.
	SAI_SAI_ASLOTR_SLOTSZ_Msk = 0xc0       // Bit mask of SLOTSZ field.
	SAI_SAI_ASLOTR_NBSLOT_Pos = 0x8        // Position of NBSLOT field.
	SAI_SAI_ASLOTR_NBSLOT_Msk = 0xf00      // Bit mask of NBSLOT field.
	SAI_SAI_ASLOTR_SLOTEN_Pos = 0x10       // Position of SLOTEN field.
	SAI_SAI_ASLOTR_SLOTEN_Msk = 0xffff0000 // Bit mask of SLOTEN field.

	// SAI_AIM: Interrupt mask register 2
	SAI_SAI_AIM_OVRUDRIE_Pos  = 0x0  // Position of OVRUDRIE field.
	SAI_SAI_AIM_OVRUDRIE_Msk  = 0x1  // Bit mask of OVRUDRIE field.
	SAI_SAI_AIM_OVRUDRIE      = 0x1  // Bit OVRUDRIE.
	SAI_SAI_AIM_MUTEDETIE_Pos = 0x1  // Position of MUTEDETIE field.
	SAI_SAI_AIM_MUTEDETIE_Msk = 0x2  // Bit mask of MUTEDETIE field.
	SAI_SAI_AIM_MUTEDETIE     = 0x2  // Bit MUTEDETIE.
	SAI_SAI_AIM_WCKCFGIE_Pos  = 0x2  // Position of WCKCFGIE field.
	SAI_SAI_AIM_WCKCFGIE_Msk  = 0x4  // Bit mask of WCKCFGIE field.
	SAI_SAI_AIM_WCKCFGIE      = 0x4  // Bit WCKCFGIE.
	SAI_SAI_AIM_FREQIE_Pos    = 0x3  // Position of FREQIE field.
	SAI_SAI_AIM_FREQIE_Msk    = 0x8  // Bit mask of FREQIE field.
	SAI_SAI_AIM_FREQIE        = 0x8  // Bit FREQIE.
	SAI_SAI_AIM_CNRDYIE_Pos   = 0x4  // Position of CNRDYIE field.
	SAI_SAI_AIM_CNRDYIE_Msk   = 0x10 // Bit mask of CNRDYIE field.
	SAI_SAI_AIM_CNRDYIE       = 0x10 // Bit CNRDYIE.
	SAI_SAI_AIM_AFSDETIE_Pos  = 0x5  // Position of AFSDETIE field.
	SAI_SAI_AIM_AFSDETIE_Msk  = 0x20 // Bit mask of AFSDETIE field.
	SAI_SAI_AIM_AFSDETIE      = 0x20 // Bit AFSDETIE.
	SAI_SAI_AIM_LFSDETIE_Pos  = 0x6  // Position of LFSDETIE field.
	SAI_SAI_AIM_LFSDETIE_Msk  = 0x40 // Bit mask of LFSDETIE field.
	SAI_SAI_AIM_LFSDETIE      = 0x40 // Bit LFSDETIE.

	// SAI_ASR: Status register
	SAI_SAI_ASR_OVRUDR_Pos  = 0x0     // Position of OVRUDR field.
	SAI_SAI_ASR_OVRUDR_Msk  = 0x1     // Bit mask of OVRUDR field.
	SAI_SAI_ASR_OVRUDR      = 0x1     // Bit OVRUDR.
	SAI_SAI_ASR_MUTEDET_Pos = 0x1     // Position of MUTEDET field.
	SAI_SAI_ASR_MUTEDET_Msk = 0x2     // Bit mask of MUTEDET field.
	SAI_SAI_ASR_MUTEDET     = 0x2     // Bit MUTEDET.
	SAI_SAI_ASR_WCKCFG_Pos  = 0x2     // Position of WCKCFG field.
	SAI_SAI_ASR_WCKCFG_Msk  = 0x4     // Bit mask of WCKCFG field.
	SAI_SAI_ASR_WCKCFG      = 0x4     // Bit WCKCFG.
	SAI_SAI_ASR_FREQ_Pos    = 0x3     // Position of FREQ field.
	SAI_SAI_ASR_FREQ_Msk    = 0x8     // Bit mask of FREQ field.
	SAI_SAI_ASR_FREQ        = 0x8     // Bit FREQ.
	SAI_SAI_ASR_CNRDY_Pos   = 0x4     // Position of CNRDY field.
	SAI_SAI_ASR_CNRDY_Msk   = 0x10    // Bit mask of CNRDY field.
	SAI_SAI_ASR_CNRDY       = 0x10    // Bit CNRDY.
	SAI_SAI_ASR_AFSDET_Pos  = 0x5     // Position of AFSDET field.
	SAI_SAI_ASR_AFSDET_Msk  = 0x20    // Bit mask of AFSDET field.
	SAI_SAI_ASR_AFSDET      = 0x20    // Bit AFSDET.
	SAI_SAI_ASR_LFSDET_Pos  = 0x6     // Position of LFSDET field.
	SAI_SAI_ASR_LFSDET_Msk  = 0x40    // Bit mask of LFSDET field.
	SAI_SAI_ASR_LFSDET      = 0x40    // Bit LFSDET.
	SAI_SAI_ASR_FLVL_Pos    = 0x10    // Position of FLVL field.
	SAI_SAI_ASR_FLVL_Msk    = 0x70000 // Bit mask of FLVL field.

	// SAI_ACLRFR: Clear flag register
	SAI_SAI_ACLRFR_COVRUDR_Pos  = 0x0  // Position of COVRUDR field.
	SAI_SAI_ACLRFR_COVRUDR_Msk  = 0x1  // Bit mask of COVRUDR field.
	SAI_SAI_ACLRFR_COVRUDR      = 0x1  // Bit COVRUDR.
	SAI_SAI_ACLRFR_CMUTEDET_Pos = 0x1  // Position of CMUTEDET field.
	SAI_SAI_ACLRFR_CMUTEDET_Msk = 0x2  // Bit mask of CMUTEDET field.
	SAI_SAI_ACLRFR_CMUTEDET     = 0x2  // Bit CMUTEDET.
	SAI_SAI_ACLRFR_CWCKCFG_Pos  = 0x2  // Position of CWCKCFG field.
	SAI_SAI_ACLRFR_CWCKCFG_Msk  = 0x4  // Bit mask of CWCKCFG field.
	SAI_SAI_ACLRFR_CWCKCFG      = 0x4  // Bit CWCKCFG.
	SAI_SAI_ACLRFR_CCNRDY_Pos   = 0x4  // Position of CCNRDY field.
	SAI_SAI_ACLRFR_CCNRDY_Msk   = 0x10 // Bit mask of CCNRDY field.
	SAI_SAI_ACLRFR_CCNRDY       = 0x10 // Bit CCNRDY.
	SAI_SAI_ACLRFR_CAFSDET_Pos  = 0x5  // Position of CAFSDET field.
	SAI_SAI_ACLRFR_CAFSDET_Msk  = 0x20 // Bit mask of CAFSDET field.
	SAI_SAI_ACLRFR_CAFSDET      = 0x20 // Bit CAFSDET.
	SAI_SAI_ACLRFR_CLFSDET_Pos  = 0x6  // Position of CLFSDET field.
	SAI_SAI_ACLRFR_CLFSDET_Msk  = 0x40 // Bit mask of CLFSDET field.
	SAI_SAI_ACLRFR_CLFSDET      = 0x40 // Bit CLFSDET.

	// SAI_ADR: Data register
	SAI_SAI_ADR_DATA_Pos = 0x0        // Position of DATA field.
	SAI_SAI_ADR_DATA_Msk = 0xffffffff // Bit mask of DATA field.

	// SAI_BCR1: Configuration register 1
	SAI_SAI_BCR1_MODE_Pos     = 0x0       // Position of MODE field.
	SAI_SAI_BCR1_MODE_Msk     = 0x3       // Bit mask of MODE field.
	SAI_SAI_BCR1_PRTCFG_Pos   = 0x2       // Position of PRTCFG field.
	SAI_SAI_BCR1_PRTCFG_Msk   = 0xc       // Bit mask of PRTCFG field.
	SAI_SAI_BCR1_DS_Pos       = 0x5       // Position of DS field.
	SAI_SAI_BCR1_DS_Msk       = 0xe0      // Bit mask of DS field.
	SAI_SAI_BCR1_LSBFIRST_Pos = 0x8       // Position of LSBFIRST field.
	SAI_SAI_BCR1_LSBFIRST_Msk = 0x100     // Bit mask of LSBFIRST field.
	SAI_SAI_BCR1_LSBFIRST     = 0x100     // Bit LSBFIRST.
	SAI_SAI_BCR1_CKSTR_Pos    = 0x9       // Position of CKSTR field.
	SAI_SAI_BCR1_CKSTR_Msk    = 0x200     // Bit mask of CKSTR field.
	SAI_SAI_BCR1_CKSTR        = 0x200     // Bit CKSTR.
	SAI_SAI_BCR1_SYNCEN_Pos   = 0xa       // Position of SYNCEN field.
	SAI_SAI_BCR1_SYNCEN_Msk   = 0xc00     // Bit mask of SYNCEN field.
	SAI_SAI_BCR1_MONO_Pos     = 0xc       // Position of MONO field.
	SAI_SAI_BCR1_MONO_Msk     = 0x1000    // Bit mask of MONO field.
	SAI_SAI_BCR1_MONO         = 0x1000    // Bit MONO.
	SAI_SAI_BCR1_OUTDRIV_Pos  = 0xd       // Position of OUTDRIV field.
	SAI_SAI_BCR1_OUTDRIV_Msk  = 0x2000    // Bit mask of OUTDRIV field.
	SAI_SAI_BCR1_OUTDRIV      = 0x2000    // Bit OUTDRIV.
	SAI_SAI_BCR1_SAIXEN_Pos   = 0x10      // Position of SAIXEN field.
	SAI_SAI_BCR1_SAIXEN_Msk   = 0x10000   // Bit mask of SAIXEN field.
	SAI_SAI_BCR1_SAIXEN       = 0x10000   // Bit SAIXEN.
	SAI_SAI_BCR1_DMAEN_Pos    = 0x11      // Position of DMAEN field.
	SAI_SAI_BCR1_DMAEN_Msk    = 0x20000   // Bit mask of DMAEN field.
	SAI_SAI_BCR1_DMAEN        = 0x20000   // Bit DMAEN.
	SAI_SAI_BCR1_NOMCK_Pos    = 0x13      // Position of NOMCK field.
	SAI_SAI_BCR1_NOMCK_Msk    = 0x80000   // Bit mask of NOMCK field.
	SAI_SAI_BCR1_NOMCK        = 0x80000   // Bit NOMCK.
	SAI_SAI_BCR1_MCKDIV_Pos   = 0x14      // Position of MCKDIV field.
	SAI_SAI_BCR1_MCKDIV_Msk   = 0xf00000  // Bit mask of MCKDIV field.
	SAI_SAI_BCR1_OSR_Pos      = 0x1a      // Position of OSR field.
	SAI_SAI_BCR1_OSR_Msk      = 0x4000000 // Bit mask of OSR field.
	SAI_SAI_BCR1_OSR          = 0x4000000 // Bit OSR.

	// SAI_BCR2: Configuration register 2
	SAI_SAI_BCR2_FTH_Pos     = 0x0    // Position of FTH field.
	SAI_SAI_BCR2_FTH_Msk     = 0x7    // Bit mask of FTH field.
	SAI_SAI_BCR2_FFLUSH_Pos  = 0x3    // Position of FFLUSH field.
	SAI_SAI_BCR2_FFLUSH_Msk  = 0x8    // Bit mask of FFLUSH field.
	SAI_SAI_BCR2_FFLUSH      = 0x8    // Bit FFLUSH.
	SAI_SAI_BCR2_TRIS_Pos    = 0x4    // Position of TRIS field.
	SAI_SAI_BCR2_TRIS_Msk    = 0x10   // Bit mask of TRIS field.
	SAI_SAI_BCR2_TRIS        = 0x10   // Bit TRIS.
	SAI_SAI_BCR2_MUTE_Pos    = 0x5    // Position of MUTE field.
	SAI_SAI_BCR2_MUTE_Msk    = 0x20   // Bit mask of MUTE field.
	SAI_SAI_BCR2_MUTE        = 0x20   // Bit MUTE.
	SAI_SAI_BCR2_MUTEVAL_Pos = 0x6    // Position of MUTEVAL field.
	SAI_SAI_BCR2_MUTEVAL_Msk = 0x40   // Bit mask of MUTEVAL field.
	SAI_SAI_BCR2_MUTEVAL     = 0x40   // Bit MUTEVAL.
	SAI_SAI_BCR2_MUTECNT_Pos = 0x7    // Position of MUTECNT field.
	SAI_SAI_BCR2_MUTECNT_Msk = 0x1f80 // Bit mask of MUTECNT field.
	SAI_SAI_BCR2_CPL_Pos     = 0xd    // Position of CPL field.
	SAI_SAI_BCR2_CPL_Msk     = 0x2000 // Bit mask of CPL field.
	SAI_SAI_BCR2_CPL         = 0x2000 // Bit CPL.
	SAI_SAI_BCR2_COMP_Pos    = 0xe    // Position of COMP field.
	SAI_SAI_BCR2_COMP_Msk    = 0xc000 // Bit mask of COMP field.

	// SAI_BFRCR: This register has no meaning in AC97 and           SPDIF audio protocol
	SAI_SAI_BFRCR_FRL_Pos   = 0x0     // Position of FRL field.
	SAI_SAI_BFRCR_FRL_Msk   = 0xff    // Bit mask of FRL field.
	SAI_SAI_BFRCR_FSALL_Pos = 0x8     // Position of FSALL field.
	SAI_SAI_BFRCR_FSALL_Msk = 0x7f00  // Bit mask of FSALL field.
	SAI_SAI_BFRCR_FSDEF_Pos = 0x10    // Position of FSDEF field.
	SAI_SAI_BFRCR_FSDEF_Msk = 0x10000 // Bit mask of FSDEF field.
	SAI_SAI_BFRCR_FSDEF     = 0x10000 // Bit FSDEF.
	SAI_SAI_BFRCR_FSPOL_Pos = 0x11    // Position of FSPOL field.
	SAI_SAI_BFRCR_FSPOL_Msk = 0x20000 // Bit mask of FSPOL field.
	SAI_SAI_BFRCR_FSPOL     = 0x20000 // Bit FSPOL.
	SAI_SAI_BFRCR_FSOFF_Pos = 0x12    // Position of FSOFF field.
	SAI_SAI_BFRCR_FSOFF_Msk = 0x40000 // Bit mask of FSOFF field.
	SAI_SAI_BFRCR_FSOFF     = 0x40000 // Bit FSOFF.

	// SAI_BSLOTR: This register has no meaning in AC97 and           SPDIF audio protocol
	SAI_SAI_BSLOTR_FBOFF_Pos  = 0x0        // Position of FBOFF field.
	SAI_SAI_BSLOTR_FBOFF_Msk  = 0x1f       // Bit mask of FBOFF field.
	SAI_SAI_BSLOTR_SLOTSZ_Pos = 0x6        // Position of SLOTSZ field.
	SAI_SAI_BSLOTR_SLOTSZ_Msk = 0xc0       // Bit mask of SLOTSZ field.
	SAI_SAI_BSLOTR_NBSLOT_Pos = 0x8        // Position of NBSLOT field.
	SAI_SAI_BSLOTR_NBSLOT_Msk = 0xf00      // Bit mask of NBSLOT field.
	SAI_SAI_BSLOTR_SLOTEN_Pos = 0x10       // Position of SLOTEN field.
	SAI_SAI_BSLOTR_SLOTEN_Msk = 0xffff0000 // Bit mask of SLOTEN field.

	// SAI_BIM: Interrupt mask register 2
	SAI_SAI_BIM_OVRUDRIE_Pos  = 0x0  // Position of OVRUDRIE field.
	SAI_SAI_BIM_OVRUDRIE_Msk  = 0x1  // Bit mask of OVRUDRIE field.
	SAI_SAI_BIM_OVRUDRIE      = 0x1  // Bit OVRUDRIE.
	SAI_SAI_BIM_MUTEDETIE_Pos = 0x1  // Position of MUTEDETIE field.
	SAI_SAI_BIM_MUTEDETIE_Msk = 0x2  // Bit mask of MUTEDETIE field.
	SAI_SAI_BIM_MUTEDETIE     = 0x2  // Bit MUTEDETIE.
	SAI_SAI_BIM_WCKCFGIE_Pos  = 0x2  // Position of WCKCFGIE field.
	SAI_SAI_BIM_WCKCFGIE_Msk  = 0x4  // Bit mask of WCKCFGIE field.
	SAI_SAI_BIM_WCKCFGIE      = 0x4  // Bit WCKCFGIE.
	SAI_SAI_BIM_FREQIE_Pos    = 0x3  // Position of FREQIE field.
	SAI_SAI_BIM_FREQIE_Msk    = 0x8  // Bit mask of FREQIE field.
	SAI_SAI_BIM_FREQIE        = 0x8  // Bit FREQIE.
	SAI_SAI_BIM_CNRDYIE_Pos   = 0x4  // Position of CNRDYIE field.
	SAI_SAI_BIM_CNRDYIE_Msk   = 0x10 // Bit mask of CNRDYIE field.
	SAI_SAI_BIM_CNRDYIE       = 0x10 // Bit CNRDYIE.
	SAI_SAI_BIM_AFSDETIE_Pos  = 0x5  // Position of AFSDETIE field.
	SAI_SAI_BIM_AFSDETIE_Msk  = 0x20 // Bit mask of AFSDETIE field.
	SAI_SAI_BIM_AFSDETIE      = 0x20 // Bit AFSDETIE.
	SAI_SAI_BIM_LFSDETIE_Pos  = 0x6  // Position of LFSDETIE field.
	SAI_SAI_BIM_LFSDETIE_Msk  = 0x40 // Bit mask of LFSDETIE field.
	SAI_SAI_BIM_LFSDETIE      = 0x40 // Bit LFSDETIE.

	// SAI_BSR: Status register
	SAI_SAI_BSR_OVRUDR_Pos  = 0x0     // Position of OVRUDR field.
	SAI_SAI_BSR_OVRUDR_Msk  = 0x1     // Bit mask of OVRUDR field.
	SAI_SAI_BSR_OVRUDR      = 0x1     // Bit OVRUDR.
	SAI_SAI_BSR_MUTEDET_Pos = 0x1     // Position of MUTEDET field.
	SAI_SAI_BSR_MUTEDET_Msk = 0x2     // Bit mask of MUTEDET field.
	SAI_SAI_BSR_MUTEDET     = 0x2     // Bit MUTEDET.
	SAI_SAI_BSR_WCKCFG_Pos  = 0x2     // Position of WCKCFG field.
	SAI_SAI_BSR_WCKCFG_Msk  = 0x4     // Bit mask of WCKCFG field.
	SAI_SAI_BSR_WCKCFG      = 0x4     // Bit WCKCFG.
	SAI_SAI_BSR_FREQ_Pos    = 0x3     // Position of FREQ field.
	SAI_SAI_BSR_FREQ_Msk    = 0x8     // Bit mask of FREQ field.
	SAI_SAI_BSR_FREQ        = 0x8     // Bit FREQ.
	SAI_SAI_BSR_CNRDY_Pos   = 0x4     // Position of CNRDY field.
	SAI_SAI_BSR_CNRDY_Msk   = 0x10    // Bit mask of CNRDY field.
	SAI_SAI_BSR_CNRDY       = 0x10    // Bit CNRDY.
	SAI_SAI_BSR_AFSDET_Pos  = 0x5     // Position of AFSDET field.
	SAI_SAI_BSR_AFSDET_Msk  = 0x20    // Bit mask of AFSDET field.
	SAI_SAI_BSR_AFSDET      = 0x20    // Bit AFSDET.
	SAI_SAI_BSR_LFSDET_Pos  = 0x6     // Position of LFSDET field.
	SAI_SAI_BSR_LFSDET_Msk  = 0x40    // Bit mask of LFSDET field.
	SAI_SAI_BSR_LFSDET      = 0x40    // Bit LFSDET.
	SAI_SAI_BSR_FLVL_Pos    = 0x10    // Position of FLVL field.
	SAI_SAI_BSR_FLVL_Msk    = 0x70000 // Bit mask of FLVL field.

	// SAI_BCLRFR: Clear flag register
	SAI_SAI_BCLRFR_COVRUDR_Pos  = 0x0  // Position of COVRUDR field.
	SAI_SAI_BCLRFR_COVRUDR_Msk  = 0x1  // Bit mask of COVRUDR field.
	SAI_SAI_BCLRFR_COVRUDR      = 0x1  // Bit COVRUDR.
	SAI_SAI_BCLRFR_CMUTEDET_Pos = 0x1  // Position of CMUTEDET field.
	SAI_SAI_BCLRFR_CMUTEDET_Msk = 0x2  // Bit mask of CMUTEDET field.
	SAI_SAI_BCLRFR_CMUTEDET     = 0x2  // Bit CMUTEDET.
	SAI_SAI_BCLRFR_CWCKCFG_Pos  = 0x2  // Position of CWCKCFG field.
	SAI_SAI_BCLRFR_CWCKCFG_Msk  = 0x4  // Bit mask of CWCKCFG field.
	SAI_SAI_BCLRFR_CWCKCFG      = 0x4  // Bit CWCKCFG.
	SAI_SAI_BCLRFR_CCNRDY_Pos   = 0x4  // Position of CCNRDY field.
	SAI_SAI_BCLRFR_CCNRDY_Msk   = 0x10 // Bit mask of CCNRDY field.
	SAI_SAI_BCLRFR_CCNRDY       = 0x10 // Bit CCNRDY.
	SAI_SAI_BCLRFR_CAFSDET_Pos  = 0x5  // Position of CAFSDET field.
	SAI_SAI_BCLRFR_CAFSDET_Msk  = 0x20 // Bit mask of CAFSDET field.
	SAI_SAI_BCLRFR_CAFSDET      = 0x20 // Bit CAFSDET.
	SAI_SAI_BCLRFR_CLFSDET_Pos  = 0x6  // Position of CLFSDET field.
	SAI_SAI_BCLRFR_CLFSDET_Msk  = 0x40 // Bit mask of CLFSDET field.
	SAI_SAI_BCLRFR_CLFSDET      = 0x40 // Bit CLFSDET.

	// SAI_BDR: Data register
	SAI_SAI_BDR_DATA_Pos = 0x0        // Position of DATA field.
	SAI_SAI_BDR_DATA_Msk = 0xffffffff // Bit mask of DATA field.

	// SAI_PDMCR: PDM control register
	SAI_SAI_PDMCR_PDMEN_Pos  = 0x0   // Position of PDMEN field.
	SAI_SAI_PDMCR_PDMEN_Msk  = 0x1   // Bit mask of PDMEN field.
	SAI_SAI_PDMCR_PDMEN      = 0x1   // Bit PDMEN.
	SAI_SAI_PDMCR_MICNBR_Pos = 0x4   // Position of MICNBR field.
	SAI_SAI_PDMCR_MICNBR_Msk = 0x30  // Bit mask of MICNBR field.
	SAI_SAI_PDMCR_CKEN1_Pos  = 0x8   // Position of CKEN1 field.
	SAI_SAI_PDMCR_CKEN1_Msk  = 0x100 // Bit mask of CKEN1 field.
	SAI_SAI_PDMCR_CKEN1      = 0x100 // Bit CKEN1.
	SAI_SAI_PDMCR_CKEN2_Pos  = 0x9   // Position of CKEN2 field.
	SAI_SAI_PDMCR_CKEN2_Msk  = 0x200 // Bit mask of CKEN2 field.
	SAI_SAI_PDMCR_CKEN2      = 0x200 // Bit CKEN2.
	SAI_SAI_PDMCR_CKEN3_Pos  = 0xa   // Position of CKEN3 field.
	SAI_SAI_PDMCR_CKEN3_Msk  = 0x400 // Bit mask of CKEN3 field.
	SAI_SAI_PDMCR_CKEN3      = 0x400 // Bit CKEN3.
	SAI_SAI_PDMCR_CKEN4_Pos  = 0xb   // Position of CKEN4 field.
	SAI_SAI_PDMCR_CKEN4_Msk  = 0x800 // Bit mask of CKEN4 field.
	SAI_SAI_PDMCR_CKEN4      = 0x800 // Bit CKEN4.

	// SAI_PDMDLY: PDM delay register
	SAI_SAI_PDMDLY_DLYM1L_Pos = 0x0        // Position of DLYM1L field.
	SAI_SAI_PDMDLY_DLYM1L_Msk = 0x7        // Bit mask of DLYM1L field.
	SAI_SAI_PDMDLY_DLYM1R_Pos = 0x4        // Position of DLYM1R field.
	SAI_SAI_PDMDLY_DLYM1R_Msk = 0x70       // Bit mask of DLYM1R field.
	SAI_SAI_PDMDLY_DLYM2L_Pos = 0x8        // Position of DLYM2L field.
	SAI_SAI_PDMDLY_DLYM2L_Msk = 0x700      // Bit mask of DLYM2L field.
	SAI_SAI_PDMDLY_DLYM2R_Pos = 0xc        // Position of DLYM2R field.
	SAI_SAI_PDMDLY_DLYM2R_Msk = 0x7000     // Bit mask of DLYM2R field.
	SAI_SAI_PDMDLY_DLYM3L_Pos = 0x10       // Position of DLYM3L field.
	SAI_SAI_PDMDLY_DLYM3L_Msk = 0x70000    // Bit mask of DLYM3L field.
	SAI_SAI_PDMDLY_DLYM3R_Pos = 0x14       // Position of DLYM3R field.
	SAI_SAI_PDMDLY_DLYM3R_Msk = 0x700000   // Bit mask of DLYM3R field.
	SAI_SAI_PDMDLY_DLYM4L_Pos = 0x18       // Position of DLYM4L field.
	SAI_SAI_PDMDLY_DLYM4L_Msk = 0x7000000  // Bit mask of DLYM4L field.
	SAI_SAI_PDMDLY_DLYM4R_Pos = 0x1c       // Position of DLYM4R field.
	SAI_SAI_PDMDLY_DLYM4R_Msk = 0x70000000 // Bit mask of DLYM4R field.
)

// Bitfields for SDMMC1: SDMMC1
const (
	// POWER: SDMMC power control register
	SDMMC_POWER_PWRCTRL_Pos   = 0x0  // Position of PWRCTRL field.
	SDMMC_POWER_PWRCTRL_Msk   = 0x3  // Bit mask of PWRCTRL field.
	SDMMC_POWER_VSWITCH_Pos   = 0x2  // Position of VSWITCH field.
	SDMMC_POWER_VSWITCH_Msk   = 0x4  // Bit mask of VSWITCH field.
	SDMMC_POWER_VSWITCH       = 0x4  // Bit VSWITCH.
	SDMMC_POWER_VSWITCHEN_Pos = 0x3  // Position of VSWITCHEN field.
	SDMMC_POWER_VSWITCHEN_Msk = 0x8  // Bit mask of VSWITCHEN field.
	SDMMC_POWER_VSWITCHEN     = 0x8  // Bit VSWITCHEN.
	SDMMC_POWER_DIRPOL_Pos    = 0x4  // Position of DIRPOL field.
	SDMMC_POWER_DIRPOL_Msk    = 0x10 // Bit mask of DIRPOL field.
	SDMMC_POWER_DIRPOL        = 0x10 // Bit DIRPOL.

	// CLKCR: The SDMMC_CLKCR register controls the           SDMMC_CK output clock, the SDMMC_RX_CLK receive clock,           and the bus width.
	SDMMC_CLKCR_CLKDIV_Pos   = 0x0      // Position of CLKDIV field.
	SDMMC_CLKCR_CLKDIV_Msk   = 0x3ff    // Bit mask of CLKDIV field.
	SDMMC_CLKCR_PWRSAV_Pos   = 0xc      // Position of PWRSAV field.
	SDMMC_CLKCR_PWRSAV_Msk   = 0x1000   // Bit mask of PWRSAV field.
	SDMMC_CLKCR_PWRSAV       = 0x1000   // Bit PWRSAV.
	SDMMC_CLKCR_WIDBUS_Pos   = 0xe      // Position of WIDBUS field.
	SDMMC_CLKCR_WIDBUS_Msk   = 0xc000   // Bit mask of WIDBUS field.
	SDMMC_CLKCR_NEGEDGE_Pos  = 0x10     // Position of NEGEDGE field.
	SDMMC_CLKCR_NEGEDGE_Msk  = 0x10000  // Bit mask of NEGEDGE field.
	SDMMC_CLKCR_NEGEDGE      = 0x10000  // Bit NEGEDGE.
	SDMMC_CLKCR_HWFC_EN_Pos  = 0x11     // Position of HWFC_EN field.
	SDMMC_CLKCR_HWFC_EN_Msk  = 0x20000  // Bit mask of HWFC_EN field.
	SDMMC_CLKCR_HWFC_EN      = 0x20000  // Bit HWFC_EN.
	SDMMC_CLKCR_DDR_Pos      = 0x12     // Position of DDR field.
	SDMMC_CLKCR_DDR_Msk      = 0x40000  // Bit mask of DDR field.
	SDMMC_CLKCR_DDR          = 0x40000  // Bit DDR.
	SDMMC_CLKCR_BUSSPEED_Pos = 0x13     // Position of BUSSPEED field.
	SDMMC_CLKCR_BUSSPEED_Msk = 0x80000  // Bit mask of BUSSPEED field.
	SDMMC_CLKCR_BUSSPEED     = 0x80000  // Bit BUSSPEED.
	SDMMC_CLKCR_SELCLKRX_Pos = 0x14     // Position of SELCLKRX field.
	SDMMC_CLKCR_SELCLKRX_Msk = 0x300000 // Bit mask of SELCLKRX field.

	// ARGR: The SDMMC_ARGR register contains a 32-bit           command argument, which is sent to a card as part of a           command message.
	SDMMC_ARGR_CMDARG_Pos = 0x0        // Position of CMDARG field.
	SDMMC_ARGR_CMDARG_Msk = 0xffffffff // Bit mask of CMDARG field.

	// CMDR: The SDMMC_CMDR register contains the command           index and command type bits. The command index is sent to           a card as part of a command message. The command type           bits control the command path state machine           (CPSM).
	SDMMC_CMDR_CMDINDEX_Pos   = 0x0     // Position of CMDINDEX field.
	SDMMC_CMDR_CMDINDEX_Msk   = 0x3f    // Bit mask of CMDINDEX field.
	SDMMC_CMDR_CMDTRANS_Pos   = 0x6     // Position of CMDTRANS field.
	SDMMC_CMDR_CMDTRANS_Msk   = 0x40    // Bit mask of CMDTRANS field.
	SDMMC_CMDR_CMDTRANS       = 0x40    // Bit CMDTRANS.
	SDMMC_CMDR_CMDSTOP_Pos    = 0x7     // Position of CMDSTOP field.
	SDMMC_CMDR_CMDSTOP_Msk    = 0x80    // Bit mask of CMDSTOP field.
	SDMMC_CMDR_CMDSTOP        = 0x80    // Bit CMDSTOP.
	SDMMC_CMDR_WAITRESP_Pos   = 0x8     // Position of WAITRESP field.
	SDMMC_CMDR_WAITRESP_Msk   = 0x300   // Bit mask of WAITRESP field.
	SDMMC_CMDR_WAITINT_Pos    = 0xa     // Position of WAITINT field.
	SDMMC_CMDR_WAITINT_Msk    = 0x400   // Bit mask of WAITINT field.
	SDMMC_CMDR_WAITINT        = 0x400   // Bit WAITINT.
	SDMMC_CMDR_WAITPEND_Pos   = 0xb     // Position of WAITPEND field.
	SDMMC_CMDR_WAITPEND_Msk   = 0x800   // Bit mask of WAITPEND field.
	SDMMC_CMDR_WAITPEND       = 0x800   // Bit WAITPEND.
	SDMMC_CMDR_CPSMEN_Pos     = 0xc     // Position of CPSMEN field.
	SDMMC_CMDR_CPSMEN_Msk     = 0x1000  // Bit mask of CPSMEN field.
	SDMMC_CMDR_CPSMEN         = 0x1000  // Bit CPSMEN.
	SDMMC_CMDR_DTHOLD_Pos     = 0xd     // Position of DTHOLD field.
	SDMMC_CMDR_DTHOLD_Msk     = 0x2000  // Bit mask of DTHOLD field.
	SDMMC_CMDR_DTHOLD         = 0x2000  // Bit DTHOLD.
	SDMMC_CMDR_BOOTMODE_Pos   = 0xe     // Position of BOOTMODE field.
	SDMMC_CMDR_BOOTMODE_Msk   = 0x4000  // Bit mask of BOOTMODE field.
	SDMMC_CMDR_BOOTMODE       = 0x4000  // Bit BOOTMODE.
	SDMMC_CMDR_BOOTEN_Pos     = 0xf     // Position of BOOTEN field.
	SDMMC_CMDR_BOOTEN_Msk     = 0x8000  // Bit mask of BOOTEN field.
	SDMMC_CMDR_BOOTEN         = 0x8000  // Bit BOOTEN.
	SDMMC_CMDR_CMDSUSPEND_Pos = 0x10    // Position of CMDSUSPEND field.
	SDMMC_CMDR_CMDSUSPEND_Msk = 0x10000 // Bit mask of CMDSUSPEND field.
	SDMMC_CMDR_CMDSUSPEND     = 0x10000 // Bit CMDSUSPEND.

	// RESPCMDR: SDMMC command response           register
	SDMMC_RESPCMDR_RESPCMD_Pos = 0x0  // Position of RESPCMD field.
	SDMMC_RESPCMDR_RESPCMD_Msk = 0x3f // Bit mask of RESPCMD field.

	// RESP1R: The SDMMC_RESP1/2/3/4R registers contain the           status of a card, which is part of the received           response.
	SDMMC_RESP1R_CARDSTATUS1_Pos = 0x0        // Position of CARDSTATUS1 field.
	SDMMC_RESP1R_CARDSTATUS1_Msk = 0xffffffff // Bit mask of CARDSTATUS1 field.

	// RESP2R: The SDMMC_RESP1/2/3/4R registers contain the           status of a card, which is part of the received           response.
	SDMMC_RESP2R_CARDSTATUS2_Pos = 0x0        // Position of CARDSTATUS2 field.
	SDMMC_RESP2R_CARDSTATUS2_Msk = 0xffffffff // Bit mask of CARDSTATUS2 field.

	// RESP3R: The SDMMC_RESP1/2/3/4R registers contain the           status of a card, which is part of the received           response.
	SDMMC_RESP3R_CARDSTATUS3_Pos = 0x0        // Position of CARDSTATUS3 field.
	SDMMC_RESP3R_CARDSTATUS3_Msk = 0xffffffff // Bit mask of CARDSTATUS3 field.

	// RESP4R: The SDMMC_RESP1/2/3/4R registers contain the           status of a card, which is part of the received           response.
	SDMMC_RESP4R_CARDSTATUS4_Pos = 0x0        // Position of CARDSTATUS4 field.
	SDMMC_RESP4R_CARDSTATUS4_Msk = 0xffffffff // Bit mask of CARDSTATUS4 field.

	// DTIMER: The SDMMC_DTIMER register contains the data           timeout period, in card bus clock periods. A counter           loads the value from the SDMMC_DTIMER register, and           starts decrementing when the data path state machine           (DPSM) enters the Wait_R or Busy state. If the timer           reaches 0 while the DPSM is in either of these states,           the timeout status flag is set.
	SDMMC_DTIMER_DATATIME_Pos = 0x0        // Position of DATATIME field.
	SDMMC_DTIMER_DATATIME_Msk = 0xffffffff // Bit mask of DATATIME field.

	// DLENR: The SDMMC_DLENR register contains the number           of data bytes to be transferred. The value is loaded into           the data counter when data transfer starts.
	SDMMC_DLENR_DATALENGTH_Pos = 0x0       // Position of DATALENGTH field.
	SDMMC_DLENR_DATALENGTH_Msk = 0x1ffffff // Bit mask of DATALENGTH field.

	// DCTRL: The SDMMC_DCTRL register control the data           path state machine (DPSM).
	SDMMC_DCTRL_DTEN_Pos       = 0x0    // Position of DTEN field.
	SDMMC_DCTRL_DTEN_Msk       = 0x1    // Bit mask of DTEN field.
	SDMMC_DCTRL_DTEN           = 0x1    // Bit DTEN.
	SDMMC_DCTRL_DTDIR_Pos      = 0x1    // Position of DTDIR field.
	SDMMC_DCTRL_DTDIR_Msk      = 0x2    // Bit mask of DTDIR field.
	SDMMC_DCTRL_DTDIR          = 0x2    // Bit DTDIR.
	SDMMC_DCTRL_DTMODE_Pos     = 0x2    // Position of DTMODE field.
	SDMMC_DCTRL_DTMODE_Msk     = 0xc    // Bit mask of DTMODE field.
	SDMMC_DCTRL_DBLOCKSIZE_Pos = 0x4    // Position of DBLOCKSIZE field.
	SDMMC_DCTRL_DBLOCKSIZE_Msk = 0xf0   // Bit mask of DBLOCKSIZE field.
	SDMMC_DCTRL_RWSTART_Pos    = 0x8    // Position of RWSTART field.
	SDMMC_DCTRL_RWSTART_Msk    = 0x100  // Bit mask of RWSTART field.
	SDMMC_DCTRL_RWSTART        = 0x100  // Bit RWSTART.
	SDMMC_DCTRL_RWSTOP_Pos     = 0x9    // Position of RWSTOP field.
	SDMMC_DCTRL_RWSTOP_Msk     = 0x200  // Bit mask of RWSTOP field.
	SDMMC_DCTRL_RWSTOP         = 0x200  // Bit RWSTOP.
	SDMMC_DCTRL_RWMOD_Pos      = 0xa    // Position of RWMOD field.
	SDMMC_DCTRL_RWMOD_Msk      = 0x400  // Bit mask of RWMOD field.
	SDMMC_DCTRL_RWMOD          = 0x400  // Bit RWMOD.
	SDMMC_DCTRL_SDIOEN_Pos     = 0xb    // Position of SDIOEN field.
	SDMMC_DCTRL_SDIOEN_Msk     = 0x800  // Bit mask of SDIOEN field.
	SDMMC_DCTRL_SDIOEN         = 0x800  // Bit SDIOEN.
	SDMMC_DCTRL_BOOTACKEN_Pos  = 0xc    // Position of BOOTACKEN field.
	SDMMC_DCTRL_BOOTACKEN_Msk  = 0x1000 // Bit mask of BOOTACKEN field.
	SDMMC_DCTRL_BOOTACKEN      = 0x1000 // Bit BOOTACKEN.
	SDMMC_DCTRL_FIFORST_Pos    = 0xd    // Position of FIFORST field.
	SDMMC_DCTRL_FIFORST_Msk    = 0x2000 // Bit mask of FIFORST field.
	SDMMC_DCTRL_FIFORST        = 0x2000 // Bit FIFORST.

	// DCNTR: The SDMMC_DCNTR register loads the value           from the data length register (see SDMMC_DLENR) when the           DPSM moves from the Idle state to the Wait_R or Wait_S           state. As data is transferred, the counter decrements the           value until it reaches 0. The DPSM then moves to the Idle           state and when there has been no error, the data status           end flag (DATAEND) is set.
	SDMMC_DCNTR_DATACOUNT_Pos = 0x0       // Position of DATACOUNT field.
	SDMMC_DCNTR_DATACOUNT_Msk = 0x1ffffff // Bit mask of DATACOUNT field.

	// STAR: The SDMMC_STAR register is a read-only           register. It contains two types of flag:Static flags           (bits [29,21,11:0]): these bits remain asserted until           they are cleared by writing to the SDMMC interrupt Clear           register (see SDMMC_ICR)Dynamic flags (bits [20:12]):           these bits change state depending on the state of the           underlying logic (for example, FIFO full and empty flags           are asserted and de-asserted as data while written to the           FIFO)
	SDMMC_STAR_CCRCFAIL_Pos   = 0x0        // Position of CCRCFAIL field.
	SDMMC_STAR_CCRCFAIL_Msk   = 0x1        // Bit mask of CCRCFAIL field.
	SDMMC_STAR_CCRCFAIL       = 0x1        // Bit CCRCFAIL.
	SDMMC_STAR_DCRCFAIL_Pos   = 0x1        // Position of DCRCFAIL field.
	SDMMC_STAR_DCRCFAIL_Msk   = 0x2        // Bit mask of DCRCFAIL field.
	SDMMC_STAR_DCRCFAIL       = 0x2        // Bit DCRCFAIL.
	SDMMC_STAR_CTIMEOUT_Pos   = 0x2        // Position of CTIMEOUT field.
	SDMMC_STAR_CTIMEOUT_Msk   = 0x4        // Bit mask of CTIMEOUT field.
	SDMMC_STAR_CTIMEOUT       = 0x4        // Bit CTIMEOUT.
	SDMMC_STAR_DTIMEOUT_Pos   = 0x3        // Position of DTIMEOUT field.
	SDMMC_STAR_DTIMEOUT_Msk   = 0x8        // Bit mask of DTIMEOUT field.
	SDMMC_STAR_DTIMEOUT       = 0x8        // Bit DTIMEOUT.
	SDMMC_STAR_TXUNDERR_Pos   = 0x4        // Position of TXUNDERR field.
	SDMMC_STAR_TXUNDERR_Msk   = 0x10       // Bit mask of TXUNDERR field.
	SDMMC_STAR_TXUNDERR       = 0x10       // Bit TXUNDERR.
	SDMMC_STAR_RXOVERR_Pos    = 0x5        // Position of RXOVERR field.
	SDMMC_STAR_RXOVERR_Msk    = 0x20       // Bit mask of RXOVERR field.
	SDMMC_STAR_RXOVERR        = 0x20       // Bit RXOVERR.
	SDMMC_STAR_CMDREND_Pos    = 0x6        // Position of CMDREND field.
	SDMMC_STAR_CMDREND_Msk    = 0x40       // Bit mask of CMDREND field.
	SDMMC_STAR_CMDREND        = 0x40       // Bit CMDREND.
	SDMMC_STAR_CMDSENT_Pos    = 0x7        // Position of CMDSENT field.
	SDMMC_STAR_CMDSENT_Msk    = 0x80       // Bit mask of CMDSENT field.
	SDMMC_STAR_CMDSENT        = 0x80       // Bit CMDSENT.
	SDMMC_STAR_DATAEND_Pos    = 0x8        // Position of DATAEND field.
	SDMMC_STAR_DATAEND_Msk    = 0x100      // Bit mask of DATAEND field.
	SDMMC_STAR_DATAEND        = 0x100      // Bit DATAEND.
	SDMMC_STAR_DHOLD_Pos      = 0x9        // Position of DHOLD field.
	SDMMC_STAR_DHOLD_Msk      = 0x200      // Bit mask of DHOLD field.
	SDMMC_STAR_DHOLD          = 0x200      // Bit DHOLD.
	SDMMC_STAR_DBCKEND_Pos    = 0xa        // Position of DBCKEND field.
	SDMMC_STAR_DBCKEND_Msk    = 0x400      // Bit mask of DBCKEND field.
	SDMMC_STAR_DBCKEND        = 0x400      // Bit DBCKEND.
	SDMMC_STAR_DABORT_Pos     = 0xb        // Position of DABORT field.
	SDMMC_STAR_DABORT_Msk     = 0x800      // Bit mask of DABORT field.
	SDMMC_STAR_DABORT         = 0x800      // Bit DABORT.
	SDMMC_STAR_DPSMACT_Pos    = 0xc        // Position of DPSMACT field.
	SDMMC_STAR_DPSMACT_Msk    = 0x1000     // Bit mask of DPSMACT field.
	SDMMC_STAR_DPSMACT        = 0x1000     // Bit DPSMACT.
	SDMMC_STAR_CPSMACT_Pos    = 0xd        // Position of CPSMACT field.
	SDMMC_STAR_CPSMACT_Msk    = 0x2000     // Bit mask of CPSMACT field.
	SDMMC_STAR_CPSMACT        = 0x2000     // Bit CPSMACT.
	SDMMC_STAR_TXFIFOHE_Pos   = 0xe        // Position of TXFIFOHE field.
	SDMMC_STAR_TXFIFOHE_Msk   = 0x4000     // Bit mask of TXFIFOHE field.
	SDMMC_STAR_TXFIFOHE       = 0x4000     // Bit TXFIFOHE.
	SDMMC_STAR_RXFIFOHF_Pos   = 0xf        // Position of RXFIFOHF field.
	SDMMC_STAR_RXFIFOHF_Msk   = 0x8000     // Bit mask of RXFIFOHF field.
	SDMMC_STAR_RXFIFOHF       = 0x8000     // Bit RXFIFOHF.
	SDMMC_STAR_TXFIFOF_Pos    = 0x10       // Position of TXFIFOF field.
	SDMMC_STAR_TXFIFOF_Msk    = 0x10000    // Bit mask of TXFIFOF field.
	SDMMC_STAR_TXFIFOF        = 0x10000    // Bit TXFIFOF.
	SDMMC_STAR_RXFIFOF_Pos    = 0x11       // Position of RXFIFOF field.
	SDMMC_STAR_RXFIFOF_Msk    = 0x20000    // Bit mask of RXFIFOF field.
	SDMMC_STAR_RXFIFOF        = 0x20000    // Bit RXFIFOF.
	SDMMC_STAR_TXFIFOE_Pos    = 0x12       // Position of TXFIFOE field.
	SDMMC_STAR_TXFIFOE_Msk    = 0x40000    // Bit mask of TXFIFOE field.
	SDMMC_STAR_TXFIFOE        = 0x40000    // Bit TXFIFOE.
	SDMMC_STAR_RXFIFOE_Pos    = 0x13       // Position of RXFIFOE field.
	SDMMC_STAR_RXFIFOE_Msk    = 0x80000    // Bit mask of RXFIFOE field.
	SDMMC_STAR_RXFIFOE        = 0x80000    // Bit RXFIFOE.
	SDMMC_STAR_BUSYD0_Pos     = 0x14       // Position of BUSYD0 field.
	SDMMC_STAR_BUSYD0_Msk     = 0x100000   // Bit mask of BUSYD0 field.
	SDMMC_STAR_BUSYD0         = 0x100000   // Bit BUSYD0.
	SDMMC_STAR_BUSYD0END_Pos  = 0x15       // Position of BUSYD0END field.
	SDMMC_STAR_BUSYD0END_Msk  = 0x200000   // Bit mask of BUSYD0END field.
	SDMMC_STAR_BUSYD0END      = 0x200000   // Bit BUSYD0END.
	SDMMC_STAR_SDIOIT_Pos     = 0x16       // Position of SDIOIT field.
	SDMMC_STAR_SDIOIT_Msk     = 0x400000   // Bit mask of SDIOIT field.
	SDMMC_STAR_SDIOIT         = 0x400000   // Bit SDIOIT.
	SDMMC_STAR_ACKFAIL_Pos    = 0x17       // Position of ACKFAIL field.
	SDMMC_STAR_ACKFAIL_Msk    = 0x800000   // Bit mask of ACKFAIL field.
	SDMMC_STAR_ACKFAIL        = 0x800000   // Bit ACKFAIL.
	SDMMC_STAR_ACKTIMEOUT_Pos = 0x18       // Position of ACKTIMEOUT field.
	SDMMC_STAR_ACKTIMEOUT_Msk = 0x1000000  // Bit mask of ACKTIMEOUT field.
	SDMMC_STAR_ACKTIMEOUT     = 0x1000000  // Bit ACKTIMEOUT.
	SDMMC_STAR_VSWEND_Pos     = 0x19       // Position of VSWEND field.
	SDMMC_STAR_VSWEND_Msk     = 0x2000000  // Bit mask of VSWEND field.
	SDMMC_STAR_VSWEND         = 0x2000000  // Bit VSWEND.
	SDMMC_STAR_CKSTOP_Pos     = 0x1a       // Position of CKSTOP field.
	SDMMC_STAR_CKSTOP_Msk     = 0x4000000  // Bit mask of CKSTOP field.
	SDMMC_STAR_CKSTOP         = 0x4000000  // Bit CKSTOP.
	SDMMC_STAR_IDMATE_Pos     = 0x1b       // Position of IDMATE field.
	SDMMC_STAR_IDMATE_Msk     = 0x8000000  // Bit mask of IDMATE field.
	SDMMC_STAR_IDMATE         = 0x8000000  // Bit IDMATE.
	SDMMC_STAR_IDMABTC_Pos    = 0x1c       // Position of IDMABTC field.
	SDMMC_STAR_IDMABTC_Msk    = 0x10000000 // Bit mask of IDMABTC field.
	SDMMC_STAR_IDMABTC        = 0x10000000 // Bit IDMABTC.

	// ICR: The SDMMC_ICR register is a write-only           register. Writing a bit with 1 clears the corresponding           bit in the SDMMC_STAR status register.
	SDMMC_ICR_CCRCFAILC_Pos   = 0x0        // Position of CCRCFAILC field.
	SDMMC_ICR_CCRCFAILC_Msk   = 0x1        // Bit mask of CCRCFAILC field.
	SDMMC_ICR_CCRCFAILC       = 0x1        // Bit CCRCFAILC.
	SDMMC_ICR_DCRCFAILC_Pos   = 0x1        // Position of DCRCFAILC field.
	SDMMC_ICR_DCRCFAILC_Msk   = 0x2        // Bit mask of DCRCFAILC field.
	SDMMC_ICR_DCRCFAILC       = 0x2        // Bit DCRCFAILC.
	SDMMC_ICR_CTIMEOUTC_Pos   = 0x2        // Position of CTIMEOUTC field.
	SDMMC_ICR_CTIMEOUTC_Msk   = 0x4        // Bit mask of CTIMEOUTC field.
	SDMMC_ICR_CTIMEOUTC       = 0x4        // Bit CTIMEOUTC.
	SDMMC_ICR_DTIMEOUTC_Pos   = 0x3        // Position of DTIMEOUTC field.
	SDMMC_ICR_DTIMEOUTC_Msk   = 0x8        // Bit mask of DTIMEOUTC field.
	SDMMC_ICR_DTIMEOUTC       = 0x8        // Bit DTIMEOUTC.
	SDMMC_ICR_TXUNDERRC_Pos   = 0x4        // Position of TXUNDERRC field.
	SDMMC_ICR_TXUNDERRC_Msk   = 0x10       // Bit mask of TXUNDERRC field.
	SDMMC_ICR_TXUNDERRC       = 0x10       // Bit TXUNDERRC.
	SDMMC_ICR_RXOVERRC_Pos    = 0x5        // Position of RXOVERRC field.
	SDMMC_ICR_RXOVERRC_Msk    = 0x20       // Bit mask of RXOVERRC field.
	SDMMC_ICR_RXOVERRC        = 0x20       // Bit RXOVERRC.
	SDMMC_ICR_CMDRENDC_Pos    = 0x6        // Position of CMDRENDC field.
	SDMMC_ICR_CMDRENDC_Msk    = 0x40       // Bit mask of CMDRENDC field.
	SDMMC_ICR_CMDRENDC        = 0x40       // Bit CMDRENDC.
	SDMMC_ICR_CMDSENTC_Pos    = 0x7        // Position of CMDSENTC field.
	SDMMC_ICR_CMDSENTC_Msk    = 0x80       // Bit mask of CMDSENTC field.
	SDMMC_ICR_CMDSENTC        = 0x80       // Bit CMDSENTC.
	SDMMC_ICR_DATAENDC_Pos    = 0x8        // Position of DATAENDC field.
	SDMMC_ICR_DATAENDC_Msk    = 0x100      // Bit mask of DATAENDC field.
	SDMMC_ICR_DATAENDC        = 0x100      // Bit DATAENDC.
	SDMMC_ICR_DHOLDC_Pos      = 0x9        // Position of DHOLDC field.
	SDMMC_ICR_DHOLDC_Msk      = 0x200      // Bit mask of DHOLDC field.
	SDMMC_ICR_DHOLDC          = 0x200      // Bit DHOLDC.
	SDMMC_ICR_DBCKENDC_Pos    = 0xa        // Position of DBCKENDC field.
	SDMMC_ICR_DBCKENDC_Msk    = 0x400      // Bit mask of DBCKENDC field.
	SDMMC_ICR_DBCKENDC        = 0x400      // Bit DBCKENDC.
	SDMMC_ICR_DABORTC_Pos     = 0xb        // Position of DABORTC field.
	SDMMC_ICR_DABORTC_Msk     = 0x800      // Bit mask of DABORTC field.
	SDMMC_ICR_DABORTC         = 0x800      // Bit DABORTC.
	SDMMC_ICR_BUSYD0ENDC_Pos  = 0x15       // Position of BUSYD0ENDC field.
	SDMMC_ICR_BUSYD0ENDC_Msk  = 0x200000   // Bit mask of BUSYD0ENDC field.
	SDMMC_ICR_BUSYD0ENDC      = 0x200000   // Bit BUSYD0ENDC.
	SDMMC_ICR_SDIOITC_Pos     = 0x16       // Position of SDIOITC field.
	SDMMC_ICR_SDIOITC_Msk     = 0x400000   // Bit mask of SDIOITC field.
	SDMMC_ICR_SDIOITC         = 0x400000   // Bit SDIOITC.
	SDMMC_ICR_ACKFAILC_Pos    = 0x17       // Position of ACKFAILC field.
	SDMMC_ICR_ACKFAILC_Msk    = 0x800000   // Bit mask of ACKFAILC field.
	SDMMC_ICR_ACKFAILC        = 0x800000   // Bit ACKFAILC.
	SDMMC_ICR_ACKTIMEOUTC_Pos = 0x18       // Position of ACKTIMEOUTC field.
	SDMMC_ICR_ACKTIMEOUTC_Msk = 0x1000000  // Bit mask of ACKTIMEOUTC field.
	SDMMC_ICR_ACKTIMEOUTC     = 0x1000000  // Bit ACKTIMEOUTC.
	SDMMC_ICR_VSWENDC_Pos     = 0x19       // Position of VSWENDC field.
	SDMMC_ICR_VSWENDC_Msk     = 0x2000000  // Bit mask of VSWENDC field.
	SDMMC_ICR_VSWENDC         = 0x2000000  // Bit VSWENDC.
	SDMMC_ICR_CKSTOPC_Pos     = 0x1a       // Position of CKSTOPC field.
	SDMMC_ICR_CKSTOPC_Msk     = 0x4000000  // Bit mask of CKSTOPC field.
	SDMMC_ICR_CKSTOPC         = 0x4000000  // Bit CKSTOPC.
	SDMMC_ICR_IDMATEC_Pos     = 0x1b       // Position of IDMATEC field.
	SDMMC_ICR_IDMATEC_Msk     = 0x8000000  // Bit mask of IDMATEC field.
	SDMMC_ICR_IDMATEC         = 0x8000000  // Bit IDMATEC.
	SDMMC_ICR_IDMABTCC_Pos    = 0x1c       // Position of IDMABTCC field.
	SDMMC_ICR_IDMABTCC_Msk    = 0x10000000 // Bit mask of IDMABTCC field.
	SDMMC_ICR_IDMABTCC        = 0x10000000 // Bit IDMABTCC.

	// MASKR: The interrupt mask register determines which           status flags generate an interrupt request by setting the           corresponding bit to 1.
	SDMMC_MASKR_CCRCFAILIE_Pos   = 0x0        // Position of CCRCFAILIE field.
	SDMMC_MASKR_CCRCFAILIE_Msk   = 0x1        // Bit mask of CCRCFAILIE field.
	SDMMC_MASKR_CCRCFAILIE       = 0x1        // Bit CCRCFAILIE.
	SDMMC_MASKR_DCRCFAILIE_Pos   = 0x1        // Position of DCRCFAILIE field.
	SDMMC_MASKR_DCRCFAILIE_Msk   = 0x2        // Bit mask of DCRCFAILIE field.
	SDMMC_MASKR_DCRCFAILIE       = 0x2        // Bit DCRCFAILIE.
	SDMMC_MASKR_CTIMEOUTIE_Pos   = 0x2        // Position of CTIMEOUTIE field.
	SDMMC_MASKR_CTIMEOUTIE_Msk   = 0x4        // Bit mask of CTIMEOUTIE field.
	SDMMC_MASKR_CTIMEOUTIE       = 0x4        // Bit CTIMEOUTIE.
	SDMMC_MASKR_DTIMEOUTIE_Pos   = 0x3        // Position of DTIMEOUTIE field.
	SDMMC_MASKR_DTIMEOUTIE_Msk   = 0x8        // Bit mask of DTIMEOUTIE field.
	SDMMC_MASKR_DTIMEOUTIE       = 0x8        // Bit DTIMEOUTIE.
	SDMMC_MASKR_TXUNDERRIE_Pos   = 0x4        // Position of TXUNDERRIE field.
	SDMMC_MASKR_TXUNDERRIE_Msk   = 0x10       // Bit mask of TXUNDERRIE field.
	SDMMC_MASKR_TXUNDERRIE       = 0x10       // Bit TXUNDERRIE.
	SDMMC_MASKR_RXOVERRIE_Pos    = 0x5        // Position of RXOVERRIE field.
	SDMMC_MASKR_RXOVERRIE_Msk    = 0x20       // Bit mask of RXOVERRIE field.
	SDMMC_MASKR_RXOVERRIE        = 0x20       // Bit RXOVERRIE.
	SDMMC_MASKR_CMDRENDIE_Pos    = 0x6        // Position of CMDRENDIE field.
	SDMMC_MASKR_CMDRENDIE_Msk    = 0x40       // Bit mask of CMDRENDIE field.
	SDMMC_MASKR_CMDRENDIE        = 0x40       // Bit CMDRENDIE.
	SDMMC_MASKR_CMDSENTIE_Pos    = 0x7        // Position of CMDSENTIE field.
	SDMMC_MASKR_CMDSENTIE_Msk    = 0x80       // Bit mask of CMDSENTIE field.
	SDMMC_MASKR_CMDSENTIE        = 0x80       // Bit CMDSENTIE.
	SDMMC_MASKR_DATAENDIE_Pos    = 0x8        // Position of DATAENDIE field.
	SDMMC_MASKR_DATAENDIE_Msk    = 0x100      // Bit mask of DATAENDIE field.
	SDMMC_MASKR_DATAENDIE        = 0x100      // Bit DATAENDIE.
	SDMMC_MASKR_DHOLDIE_Pos      = 0x9        // Position of DHOLDIE field.
	SDMMC_MASKR_DHOLDIE_Msk      = 0x200      // Bit mask of DHOLDIE field.
	SDMMC_MASKR_DHOLDIE          = 0x200      // Bit DHOLDIE.
	SDMMC_MASKR_DBCKENDIE_Pos    = 0xa        // Position of DBCKENDIE field.
	SDMMC_MASKR_DBCKENDIE_Msk    = 0x400      // Bit mask of DBCKENDIE field.
	SDMMC_MASKR_DBCKENDIE        = 0x400      // Bit DBCKENDIE.
	SDMMC_MASKR_DABORTIE_Pos     = 0xb        // Position of DABORTIE field.
	SDMMC_MASKR_DABORTIE_Msk     = 0x800      // Bit mask of DABORTIE field.
	SDMMC_MASKR_DABORTIE         = 0x800      // Bit DABORTIE.
	SDMMC_MASKR_TXFIFOHEIE_Pos   = 0xe        // Position of TXFIFOHEIE field.
	SDMMC_MASKR_TXFIFOHEIE_Msk   = 0x4000     // Bit mask of TXFIFOHEIE field.
	SDMMC_MASKR_TXFIFOHEIE       = 0x4000     // Bit TXFIFOHEIE.
	SDMMC_MASKR_RXFIFOHFIE_Pos   = 0xf        // Position of RXFIFOHFIE field.
	SDMMC_MASKR_RXFIFOHFIE_Msk   = 0x8000     // Bit mask of RXFIFOHFIE field.
	SDMMC_MASKR_RXFIFOHFIE       = 0x8000     // Bit RXFIFOHFIE.
	SDMMC_MASKR_RXFIFOFIE_Pos    = 0x11       // Position of RXFIFOFIE field.
	SDMMC_MASKR_RXFIFOFIE_Msk    = 0x20000    // Bit mask of RXFIFOFIE field.
	SDMMC_MASKR_RXFIFOFIE        = 0x20000    // Bit RXFIFOFIE.
	SDMMC_MASKR_TXFIFOEIE_Pos    = 0x12       // Position of TXFIFOEIE field.
	SDMMC_MASKR_TXFIFOEIE_Msk    = 0x40000    // Bit mask of TXFIFOEIE field.
	SDMMC_MASKR_TXFIFOEIE        = 0x40000    // Bit TXFIFOEIE.
	SDMMC_MASKR_BUSYD0ENDIE_Pos  = 0x15       // Position of BUSYD0ENDIE field.
	SDMMC_MASKR_BUSYD0ENDIE_Msk  = 0x200000   // Bit mask of BUSYD0ENDIE field.
	SDMMC_MASKR_BUSYD0ENDIE      = 0x200000   // Bit BUSYD0ENDIE.
	SDMMC_MASKR_SDIOITIE_Pos     = 0x16       // Position of SDIOITIE field.
	SDMMC_MASKR_SDIOITIE_Msk     = 0x400000   // Bit mask of SDIOITIE field.
	SDMMC_MASKR_SDIOITIE         = 0x400000   // Bit SDIOITIE.
	SDMMC_MASKR_ACKFAILIE_Pos    = 0x17       // Position of ACKFAILIE field.
	SDMMC_MASKR_ACKFAILIE_Msk    = 0x800000   // Bit mask of ACKFAILIE field.
	SDMMC_MASKR_ACKFAILIE        = 0x800000   // Bit ACKFAILIE.
	SDMMC_MASKR_ACKTIMEOUTIE_Pos = 0x18       // Position of ACKTIMEOUTIE field.
	SDMMC_MASKR_ACKTIMEOUTIE_Msk = 0x1000000  // Bit mask of ACKTIMEOUTIE field.
	SDMMC_MASKR_ACKTIMEOUTIE     = 0x1000000  // Bit ACKTIMEOUTIE.
	SDMMC_MASKR_VSWENDIE_Pos     = 0x19       // Position of VSWENDIE field.
	SDMMC_MASKR_VSWENDIE_Msk     = 0x2000000  // Bit mask of VSWENDIE field.
	SDMMC_MASKR_VSWENDIE         = 0x2000000  // Bit VSWENDIE.
	SDMMC_MASKR_CKSTOPIE_Pos     = 0x1a       // Position of CKSTOPIE field.
	SDMMC_MASKR_CKSTOPIE_Msk     = 0x4000000  // Bit mask of CKSTOPIE field.
	SDMMC_MASKR_CKSTOPIE         = 0x4000000  // Bit CKSTOPIE.
	SDMMC_MASKR_IDMABTCIE_Pos    = 0x1c       // Position of IDMABTCIE field.
	SDMMC_MASKR_IDMABTCIE_Msk    = 0x10000000 // Bit mask of IDMABTCIE field.
	SDMMC_MASKR_IDMABTCIE        = 0x10000000 // Bit IDMABTCIE.

	// ACKTIMER: The SDMMC_ACKTIMER register contains the           acknowledgment timeout period, in SDMMC_CK bus clock           periods. A counter loads the value from the           SDMMC_ACKTIMER register, and starts decrementing when the           data path state machine (DPSM) enters the Wait_Ack state.           If the timer reaches 0 while the DPSM is in this states,           the acknowledgment timeout status flag is           set.
	SDMMC_ACKTIMER_ACKTIME_Pos = 0x0       // Position of ACKTIME field.
	SDMMC_ACKTIMER_ACKTIME_Msk = 0x1ffffff // Bit mask of ACKTIME field.

	// IDMACTRLR: The receive and transmit FIFOs can be read           or written as 32-bit wide registers. The FIFOs contain 32           entries on 32 sequential addresses. This allows the CPU           to use its load and store multiple operands to read           from/write to the FIFO.
	SDMMC_IDMACTRLR_IDMAEN_Pos    = 0x0 // Position of IDMAEN field.
	SDMMC_IDMACTRLR_IDMAEN_Msk    = 0x1 // Bit mask of IDMAEN field.
	SDMMC_IDMACTRLR_IDMAEN        = 0x1 // Bit IDMAEN.
	SDMMC_IDMACTRLR_IDMABMODE_Pos = 0x1 // Position of IDMABMODE field.
	SDMMC_IDMACTRLR_IDMABMODE_Msk = 0x2 // Bit mask of IDMABMODE field.
	SDMMC_IDMACTRLR_IDMABMODE     = 0x2 // Bit IDMABMODE.
	SDMMC_IDMACTRLR_IDMABACT_Pos  = 0x2 // Position of IDMABACT field.
	SDMMC_IDMACTRLR_IDMABACT_Msk  = 0x4 // Bit mask of IDMABACT field.
	SDMMC_IDMACTRLR_IDMABACT      = 0x4 // Bit IDMABACT.

	// IDMABSIZER: The SDMMC_IDMABSIZER register contains the           buffers size when in double buffer           configuration.
	SDMMC_IDMABSIZER_IDMABNDT_Pos = 0x5    // Position of IDMABNDT field.
	SDMMC_IDMABSIZER_IDMABNDT_Msk = 0x1fe0 // Bit mask of IDMABNDT field.

	// IDMABASE0R: The SDMMC_IDMABASE0R register contains the           memory buffer base address in single buffer configuration           and the buffer 0 base address in double buffer           configuration.
	SDMMC_IDMABASE0R_IDMABASE0_Pos = 0x0        // Position of IDMABASE0 field.
	SDMMC_IDMABASE0R_IDMABASE0_Msk = 0xffffffff // Bit mask of IDMABASE0 field.

	// IDMABASE1R: The SDMMC_IDMABASE1R register contains the           double buffer configuration second buffer memory base           address.
	SDMMC_IDMABASE1R_IDMABASE1_Pos = 0x0        // Position of IDMABASE1 field.
	SDMMC_IDMABASE1R_IDMABASE1_Msk = 0xffffffff // Bit mask of IDMABASE1 field.

	// FIFOR: The receive and transmit FIFOs can be only           read or written as word (32-bit) wide registers. The           FIFOs contain 16 entries on sequential addresses. This           allows the CPU to use its load and store multiple           operands to read from/write to the FIFO.When accessing           SDMMC_FIFOR with half word or byte access an AHB bus           fault is generated.
	SDMMC_FIFOR_FIFODATA_Pos = 0x0        // Position of FIFODATA field.
	SDMMC_FIFOR_FIFODATA_Msk = 0xffffffff // Bit mask of FIFODATA field.

	// VER: SDMMC IP version register
	SDMMC_VER_MINREV_Pos = 0x0  // Position of MINREV field.
	SDMMC_VER_MINREV_Msk = 0xf  // Bit mask of MINREV field.
	SDMMC_VER_MAJREV_Pos = 0x4  // Position of MAJREV field.
	SDMMC_VER_MAJREV_Msk = 0xf0 // Bit mask of MAJREV field.

	// ID: SDMMC IP identification           register
	SDMMC_ID_IP_ID_Pos = 0x0        // Position of IP_ID field.
	SDMMC_ID_IP_ID_Msk = 0xffffffff // Bit mask of IP_ID field.
)

// Bitfields for VREFBUF: VREFBUF
const (
	// CSR: VREFBUF control and status           register
	VREFBUF_CSR_ENVR_Pos = 0x0  // Position of ENVR field.
	VREFBUF_CSR_ENVR_Msk = 0x1  // Bit mask of ENVR field.
	VREFBUF_CSR_ENVR     = 0x1  // Bit ENVR.
	VREFBUF_CSR_HIZ_Pos  = 0x1  // Position of HIZ field.
	VREFBUF_CSR_HIZ_Msk  = 0x2  // Bit mask of HIZ field.
	VREFBUF_CSR_HIZ      = 0x2  // Bit HIZ.
	VREFBUF_CSR_VRR_Pos  = 0x3  // Position of VRR field.
	VREFBUF_CSR_VRR_Msk  = 0x8  // Bit mask of VRR field.
	VREFBUF_CSR_VRR      = 0x8  // Bit VRR.
	VREFBUF_CSR_VRS_Pos  = 0x4  // Position of VRS field.
	VREFBUF_CSR_VRS_Msk  = 0x70 // Bit mask of VRS field.

	// CCR: VREFBUF calibration control           register
	VREFBUF_CCR_TRIM_Pos = 0x0  // Position of TRIM field.
	VREFBUF_CCR_TRIM_Msk = 0x3f // Bit mask of TRIM field.
)

// Bitfields for IWDG: IWDG
const (
	// KR: Key register
	IWDG_KR_KEY_Pos = 0x0    // Position of KEY field.
	IWDG_KR_KEY_Msk = 0xffff // Bit mask of KEY field.

	// PR: Prescaler register
	IWDG_PR_PR_Pos = 0x0 // Position of PR field.
	IWDG_PR_PR_Msk = 0x7 // Bit mask of PR field.

	// RLR: Reload register
	IWDG_RLR_RL_Pos = 0x0   // Position of RL field.
	IWDG_RLR_RL_Msk = 0xfff // Bit mask of RL field.

	// SR: Status register
	IWDG_SR_PVU_Pos = 0x0 // Position of PVU field.
	IWDG_SR_PVU_Msk = 0x1 // Bit mask of PVU field.
	IWDG_SR_PVU     = 0x1 // Bit PVU.
	IWDG_SR_RVU_Pos = 0x1 // Position of RVU field.
	IWDG_SR_RVU_Msk = 0x2 // Bit mask of RVU field.
	IWDG_SR_RVU     = 0x2 // Bit RVU.
	IWDG_SR_WVU_Pos = 0x2 // Position of WVU field.
	IWDG_SR_WVU_Msk = 0x4 // Bit mask of WVU field.
	IWDG_SR_WVU     = 0x4 // Bit WVU.

	// WINR: Window register
	IWDG_WINR_WIN_Pos = 0x0   // Position of WIN field.
	IWDG_WINR_WIN_Msk = 0xfff // Bit mask of WIN field.
)

// Bitfields for WWDG: WWDG
const (
	// CR: Control register
	WWDG_CR_T_Pos    = 0x0  // Position of T field.
	WWDG_CR_T_Msk    = 0x7f // Bit mask of T field.
	WWDG_CR_WDGA_Pos = 0x7  // Position of WDGA field.
	WWDG_CR_WDGA_Msk = 0x80 // Bit mask of WDGA field.
	WWDG_CR_WDGA     = 0x80 // Bit WDGA.

	// CFR: Configuration register
	WWDG_CFR_W_Pos     = 0x0    // Position of W field.
	WWDG_CFR_W_Msk     = 0x7f   // Bit mask of W field.
	WWDG_CFR_WDGTB_Pos = 0xb    // Position of WDGTB field.
	WWDG_CFR_WDGTB_Msk = 0x1800 // Bit mask of WDGTB field.
	WWDG_CFR_EWI_Pos   = 0x9    // Position of EWI field.
	WWDG_CFR_EWI_Msk   = 0x200  // Bit mask of EWI field.
	WWDG_CFR_EWI       = 0x200  // Bit EWI.

	// SR: Status register
	WWDG_SR_EWIF_Pos = 0x0 // Position of EWIF field.
	WWDG_SR_EWIF_Msk = 0x1 // Bit mask of EWIF field.
	WWDG_SR_EWIF     = 0x1 // Bit EWIF.
)

// Bitfields for PWR: PWR
const (
	// CR1: PWR control register 1
	PWR_CR1_LPDS_Pos  = 0x0     // Position of LPDS field.
	PWR_CR1_LPDS_Msk  = 0x1     // Bit mask of LPDS field.
	PWR_CR1_LPDS      = 0x1     // Bit LPDS.
	PWR_CR1_PVDE_Pos  = 0x4     // Position of PVDE field.
	PWR_CR1_PVDE_Msk  = 0x10    // Bit mask of PVDE field.
	PWR_CR1_PVDE      = 0x10    // Bit PVDE.
	PWR_CR1_PLS_Pos   = 0x5     // Position of PLS field.
	PWR_CR1_PLS_Msk   = 0xe0    // Bit mask of PLS field.
	PWR_CR1_DBP_Pos   = 0x8     // Position of DBP field.
	PWR_CR1_DBP_Msk   = 0x100   // Bit mask of DBP field.
	PWR_CR1_DBP       = 0x100   // Bit DBP.
	PWR_CR1_FLPS_Pos  = 0x9     // Position of FLPS field.
	PWR_CR1_FLPS_Msk  = 0x200   // Bit mask of FLPS field.
	PWR_CR1_FLPS      = 0x200   // Bit FLPS.
	PWR_CR1_SVOS_Pos  = 0xe     // Position of SVOS field.
	PWR_CR1_SVOS_Msk  = 0xc000  // Bit mask of SVOS field.
	PWR_CR1_AVDEN_Pos = 0x10    // Position of AVDEN field.
	PWR_CR1_AVDEN_Msk = 0x10000 // Bit mask of AVDEN field.
	PWR_CR1_AVDEN     = 0x10000 // Bit AVDEN.
	PWR_CR1_ALS_Pos   = 0x11    // Position of ALS field.
	PWR_CR1_ALS_Msk   = 0x60000 // Bit mask of ALS field.

	// CSR1: PWR control status register 1
	PWR_CSR1_PVDO_Pos      = 0x4     // Position of PVDO field.
	PWR_CSR1_PVDO_Msk      = 0x10    // Bit mask of PVDO field.
	PWR_CSR1_PVDO          = 0x10    // Bit PVDO.
	PWR_CSR1_ACTVOSRDY_Pos = 0xd     // Position of ACTVOSRDY field.
	PWR_CSR1_ACTVOSRDY_Msk = 0x2000  // Bit mask of ACTVOSRDY field.
	PWR_CSR1_ACTVOSRDY     = 0x2000  // Bit ACTVOSRDY.
	PWR_CSR1_ACTVOS_Pos    = 0xe     // Position of ACTVOS field.
	PWR_CSR1_ACTVOS_Msk    = 0xc000  // Bit mask of ACTVOS field.
	PWR_CSR1_AVDO_Pos      = 0x10    // Position of AVDO field.
	PWR_CSR1_AVDO_Msk      = 0x10000 // Bit mask of AVDO field.
	PWR_CSR1_AVDO          = 0x10000 // Bit AVDO.

	// CR2: This register is not reset by wakeup from           Standby mode, RESET signal and VDD POR. It is only reset           by VSW POR and VSWRST reset. This register shall not be           accessed when VSWRST bit in RCC_BDCR register resets the           VSW domain.After reset, PWR_CR2 register is           write-protected. Prior to modifying its content, the DBP           bit in PWR_CR1 register must be set to disable the write           protection.
	PWR_CR2_BREN_Pos  = 0x0      // Position of BREN field.
	PWR_CR2_BREN_Msk  = 0x1      // Bit mask of BREN field.
	PWR_CR2_BREN      = 0x1      // Bit BREN.
	PWR_CR2_MONEN_Pos = 0x4      // Position of MONEN field.
	PWR_CR2_MONEN_Msk = 0x10     // Bit mask of MONEN field.
	PWR_CR2_MONEN     = 0x10     // Bit MONEN.
	PWR_CR2_BRRDY_Pos = 0x10     // Position of BRRDY field.
	PWR_CR2_BRRDY_Msk = 0x10000  // Bit mask of BRRDY field.
	PWR_CR2_BRRDY     = 0x10000  // Bit BRRDY.
	PWR_CR2_VBATL_Pos = 0x14     // Position of VBATL field.
	PWR_CR2_VBATL_Msk = 0x100000 // Bit mask of VBATL field.
	PWR_CR2_VBATL     = 0x100000 // Bit VBATL.
	PWR_CR2_VBATH_Pos = 0x15     // Position of VBATH field.
	PWR_CR2_VBATH_Msk = 0x200000 // Bit mask of VBATH field.
	PWR_CR2_VBATH     = 0x200000 // Bit VBATH.
	PWR_CR2_TEMPL_Pos = 0x16     // Position of TEMPL field.
	PWR_CR2_TEMPL_Msk = 0x400000 // Bit mask of TEMPL field.
	PWR_CR2_TEMPL     = 0x400000 // Bit TEMPL.
	PWR_CR2_TEMPH_Pos = 0x17     // Position of TEMPH field.
	PWR_CR2_TEMPH_Msk = 0x800000 // Bit mask of TEMPH field.
	PWR_CR2_TEMPH     = 0x800000 // Bit TEMPH.

	// CR3: Reset only by POR only, not reset by wakeup           from Standby mode and RESET pad. The lower byte of this           register is written once after POR and shall be written           before changing VOS level or ck_sys clock frequency. No           limitation applies to the upper bytes.Programming data           corresponding to an invalid combination of SDLEVEL,           SDEXTHP, SDEN, LDOEN and BYPASS bits (see Table9) will be           ignored: data will not be written, the written-once           mechanism will lock the register and any further write           access will be ignored. The default supply configuration           will be kept and the ACTVOSRDY bit in PWR control status           register 1 (PWR_CSR1) will go on indicating invalid           voltage levels. The system shall be power cycled before           writing a new value.
	PWR_CR3_BYPASS_Pos   = 0x0       // Position of BYPASS field.
	PWR_CR3_BYPASS_Msk   = 0x1       // Bit mask of BYPASS field.
	PWR_CR3_BYPASS       = 0x1       // Bit BYPASS.
	PWR_CR3_LDOEN_Pos    = 0x1       // Position of LDOEN field.
	PWR_CR3_LDOEN_Msk    = 0x2       // Bit mask of LDOEN field.
	PWR_CR3_LDOEN        = 0x2       // Bit LDOEN.
	PWR_CR3_SCUEN_Pos    = 0x2       // Position of SCUEN field.
	PWR_CR3_SCUEN_Msk    = 0x4       // Bit mask of SCUEN field.
	PWR_CR3_SCUEN        = 0x4       // Bit SCUEN.
	PWR_CR3_VBE_Pos      = 0x8       // Position of VBE field.
	PWR_CR3_VBE_Msk      = 0x100     // Bit mask of VBE field.
	PWR_CR3_VBE          = 0x100     // Bit VBE.
	PWR_CR3_VBRS_Pos     = 0x9       // Position of VBRS field.
	PWR_CR3_VBRS_Msk     = 0x200     // Bit mask of VBRS field.
	PWR_CR3_VBRS         = 0x200     // Bit VBRS.
	PWR_CR3_USB33DEN_Pos = 0x18      // Position of USB33DEN field.
	PWR_CR3_USB33DEN_Msk = 0x1000000 // Bit mask of USB33DEN field.
	PWR_CR3_USB33DEN     = 0x1000000 // Bit USB33DEN.
	PWR_CR3_USBREGEN_Pos = 0x19      // Position of USBREGEN field.
	PWR_CR3_USBREGEN_Msk = 0x2000000 // Bit mask of USBREGEN field.
	PWR_CR3_USBREGEN     = 0x2000000 // Bit USBREGEN.
	PWR_CR3_USB33RDY_Pos = 0x1a      // Position of USB33RDY field.
	PWR_CR3_USB33RDY_Msk = 0x4000000 // Bit mask of USB33RDY field.
	PWR_CR3_USB33RDY     = 0x4000000 // Bit USB33RDY.

	// CPUCR: This register allows controlling CPU1           power.
	PWR_CPUCR_PDDS_D1_Pos = 0x0   // Position of PDDS_D1 field.
	PWR_CPUCR_PDDS_D1_Msk = 0x1   // Bit mask of PDDS_D1 field.
	PWR_CPUCR_PDDS_D1     = 0x1   // Bit PDDS_D1.
	PWR_CPUCR_PDDS_D2_Pos = 0x1   // Position of PDDS_D2 field.
	PWR_CPUCR_PDDS_D2_Msk = 0x2   // Bit mask of PDDS_D2 field.
	PWR_CPUCR_PDDS_D2     = 0x2   // Bit PDDS_D2.
	PWR_CPUCR_PDDS_D3_Pos = 0x2   // Position of PDDS_D3 field.
	PWR_CPUCR_PDDS_D3_Msk = 0x4   // Bit mask of PDDS_D3 field.
	PWR_CPUCR_PDDS_D3     = 0x4   // Bit PDDS_D3.
	PWR_CPUCR_STOPF_Pos   = 0x5   // Position of STOPF field.
	PWR_CPUCR_STOPF_Msk   = 0x20  // Bit mask of STOPF field.
	PWR_CPUCR_STOPF       = 0x20  // Bit STOPF.
	PWR_CPUCR_SBF_Pos     = 0x6   // Position of SBF field.
	PWR_CPUCR_SBF_Msk     = 0x40  // Bit mask of SBF field.
	PWR_CPUCR_SBF         = 0x40  // Bit SBF.
	PWR_CPUCR_SBF_D1_Pos  = 0x7   // Position of SBF_D1 field.
	PWR_CPUCR_SBF_D1_Msk  = 0x80  // Bit mask of SBF_D1 field.
	PWR_CPUCR_SBF_D1      = 0x80  // Bit SBF_D1.
	PWR_CPUCR_SBF_D2_Pos  = 0x8   // Position of SBF_D2 field.
	PWR_CPUCR_SBF_D2_Msk  = 0x100 // Bit mask of SBF_D2 field.
	PWR_CPUCR_SBF_D2      = 0x100 // Bit SBF_D2.
	PWR_CPUCR_CSSF_Pos    = 0x9   // Position of CSSF field.
	PWR_CPUCR_CSSF_Msk    = 0x200 // Bit mask of CSSF field.
	PWR_CPUCR_CSSF        = 0x200 // Bit CSSF.
	PWR_CPUCR_RUN_D3_Pos  = 0xb   // Position of RUN_D3 field.
	PWR_CPUCR_RUN_D3_Msk  = 0x800 // Bit mask of RUN_D3 field.
	PWR_CPUCR_RUN_D3      = 0x800 // Bit RUN_D3.

	// D3CR: This register allows controlling D3 domain           power.Following reset VOSRDY will be read 1 by           software
	PWR_D3CR_VOSRDY_Pos = 0xd    // Position of VOSRDY field.
	PWR_D3CR_VOSRDY_Msk = 0x2000 // Bit mask of VOSRDY field.
	PWR_D3CR_VOSRDY     = 0x2000 // Bit VOSRDY.
	PWR_D3CR_VOS_Pos    = 0xe    // Position of VOS field.
	PWR_D3CR_VOS_Msk    = 0xc000 // Bit mask of VOS field.

	// WKUPCR: reset only by system reset, not reset by           wakeup from Standby mode5 wait states are required when           writing this register (when clearing a WKUPF bit in           PWR_WKUPFR, the AHB write access will complete after the           WKUPF has been cleared).
	PWR_WKUPCR_WKUPC_Pos = 0x0  // Position of WKUPC field.
	PWR_WKUPCR_WKUPC_Msk = 0x3f // Bit mask of WKUPC field.

	// WKUPFR: reset only by system reset, not reset by           wakeup from Standby mode
	PWR_WKUPFR_WKUPF1_Pos = 0x0  // Position of WKUPF1 field.
	PWR_WKUPFR_WKUPF1_Msk = 0x1  // Bit mask of WKUPF1 field.
	PWR_WKUPFR_WKUPF1     = 0x1  // Bit WKUPF1.
	PWR_WKUPFR_WKUPF2_Pos = 0x1  // Position of WKUPF2 field.
	PWR_WKUPFR_WKUPF2_Msk = 0x2  // Bit mask of WKUPF2 field.
	PWR_WKUPFR_WKUPF2     = 0x2  // Bit WKUPF2.
	PWR_WKUPFR_WKUPF3_Pos = 0x2  // Position of WKUPF3 field.
	PWR_WKUPFR_WKUPF3_Msk = 0x4  // Bit mask of WKUPF3 field.
	PWR_WKUPFR_WKUPF3     = 0x4  // Bit WKUPF3.
	PWR_WKUPFR_WKUPF4_Pos = 0x3  // Position of WKUPF4 field.
	PWR_WKUPFR_WKUPF4_Msk = 0x8  // Bit mask of WKUPF4 field.
	PWR_WKUPFR_WKUPF4     = 0x8  // Bit WKUPF4.
	PWR_WKUPFR_WKUPF5_Pos = 0x4  // Position of WKUPF5 field.
	PWR_WKUPFR_WKUPF5_Msk = 0x10 // Bit mask of WKUPF5 field.
	PWR_WKUPFR_WKUPF5     = 0x10 // Bit WKUPF5.
	PWR_WKUPFR_WKUPF6_Pos = 0x5  // Position of WKUPF6 field.
	PWR_WKUPFR_WKUPF6_Msk = 0x20 // Bit mask of WKUPF6 field.
	PWR_WKUPFR_WKUPF6     = 0x20 // Bit WKUPF6.

	// WKUPEPR: Reset only by system reset, not reset by           wakeup from Standby mode
	PWR_WKUPEPR_WKUPEN1_Pos   = 0x0       // Position of WKUPEN1 field.
	PWR_WKUPEPR_WKUPEN1_Msk   = 0x1       // Bit mask of WKUPEN1 field.
	PWR_WKUPEPR_WKUPEN1       = 0x1       // Bit WKUPEN1.
	PWR_WKUPEPR_WKUPEN2_Pos   = 0x1       // Position of WKUPEN2 field.
	PWR_WKUPEPR_WKUPEN2_Msk   = 0x2       // Bit mask of WKUPEN2 field.
	PWR_WKUPEPR_WKUPEN2       = 0x2       // Bit WKUPEN2.
	PWR_WKUPEPR_WKUPEN3_Pos   = 0x2       // Position of WKUPEN3 field.
	PWR_WKUPEPR_WKUPEN3_Msk   = 0x4       // Bit mask of WKUPEN3 field.
	PWR_WKUPEPR_WKUPEN3       = 0x4       // Bit WKUPEN3.
	PWR_WKUPEPR_WKUPEN4_Pos   = 0x3       // Position of WKUPEN4 field.
	PWR_WKUPEPR_WKUPEN4_Msk   = 0x8       // Bit mask of WKUPEN4 field.
	PWR_WKUPEPR_WKUPEN4       = 0x8       // Bit WKUPEN4.
	PWR_WKUPEPR_WKUPEN5_Pos   = 0x4       // Position of WKUPEN5 field.
	PWR_WKUPEPR_WKUPEN5_Msk   = 0x10      // Bit mask of WKUPEN5 field.
	PWR_WKUPEPR_WKUPEN5       = 0x10      // Bit WKUPEN5.
	PWR_WKUPEPR_WKUPEN6_Pos   = 0x5       // Position of WKUPEN6 field.
	PWR_WKUPEPR_WKUPEN6_Msk   = 0x20      // Bit mask of WKUPEN6 field.
	PWR_WKUPEPR_WKUPEN6       = 0x20      // Bit WKUPEN6.
	PWR_WKUPEPR_WKUPP1_Pos    = 0x8       // Position of WKUPP1 field.
	PWR_WKUPEPR_WKUPP1_Msk    = 0x100     // Bit mask of WKUPP1 field.
	PWR_WKUPEPR_WKUPP1        = 0x100     // Bit WKUPP1.
	PWR_WKUPEPR_WKUPP2_Pos    = 0x9       // Position of WKUPP2 field.
	PWR_WKUPEPR_WKUPP2_Msk    = 0x200     // Bit mask of WKUPP2 field.
	PWR_WKUPEPR_WKUPP2        = 0x200     // Bit WKUPP2.
	PWR_WKUPEPR_WKUPP3_Pos    = 0xa       // Position of WKUPP3 field.
	PWR_WKUPEPR_WKUPP3_Msk    = 0x400     // Bit mask of WKUPP3 field.
	PWR_WKUPEPR_WKUPP3        = 0x400     // Bit WKUPP3.
	PWR_WKUPEPR_WKUPP4_Pos    = 0xb       // Position of WKUPP4 field.
	PWR_WKUPEPR_WKUPP4_Msk    = 0x800     // Bit mask of WKUPP4 field.
	PWR_WKUPEPR_WKUPP4        = 0x800     // Bit WKUPP4.
	PWR_WKUPEPR_WKUPP5_Pos    = 0xc       // Position of WKUPP5 field.
	PWR_WKUPEPR_WKUPP5_Msk    = 0x1000    // Bit mask of WKUPP5 field.
	PWR_WKUPEPR_WKUPP5        = 0x1000    // Bit WKUPP5.
	PWR_WKUPEPR_WKUPP6_Pos    = 0xd       // Position of WKUPP6 field.
	PWR_WKUPEPR_WKUPP6_Msk    = 0x2000    // Bit mask of WKUPP6 field.
	PWR_WKUPEPR_WKUPP6        = 0x2000    // Bit WKUPP6.
	PWR_WKUPEPR_WKUPPUPD1_Pos = 0x10      // Position of WKUPPUPD1 field.
	PWR_WKUPEPR_WKUPPUPD1_Msk = 0x30000   // Bit mask of WKUPPUPD1 field.
	PWR_WKUPEPR_WKUPPUPD2_Pos = 0x12      // Position of WKUPPUPD2 field.
	PWR_WKUPEPR_WKUPPUPD2_Msk = 0xc0000   // Bit mask of WKUPPUPD2 field.
	PWR_WKUPEPR_WKUPPUPD3_Pos = 0x14      // Position of WKUPPUPD3 field.
	PWR_WKUPEPR_WKUPPUPD3_Msk = 0x300000  // Bit mask of WKUPPUPD3 field.
	PWR_WKUPEPR_WKUPPUPD4_Pos = 0x16      // Position of WKUPPUPD4 field.
	PWR_WKUPEPR_WKUPPUPD4_Msk = 0xc00000  // Bit mask of WKUPPUPD4 field.
	PWR_WKUPEPR_WKUPPUPD5_Pos = 0x18      // Position of WKUPPUPD5 field.
	PWR_WKUPEPR_WKUPPUPD5_Msk = 0x3000000 // Bit mask of WKUPPUPD5 field.
	PWR_WKUPEPR_WKUPPUPD6_Pos = 0x1a      // Position of WKUPPUPD6 field.
	PWR_WKUPEPR_WKUPPUPD6_Msk = 0xc000000 // Bit mask of WKUPPUPD6 field.
)

// Bitfields for SPI1: Serial peripheral interface
const (
	// CR1: control register 1
	SPI_CR1_IOLOCK_Pos   = 0x10    // Position of IOLOCK field.
	SPI_CR1_IOLOCK_Msk   = 0x10000 // Bit mask of IOLOCK field.
	SPI_CR1_IOLOCK       = 0x10000 // Bit IOLOCK.
	SPI_CR1_TCRCI_Pos    = 0xf     // Position of TCRCI field.
	SPI_CR1_TCRCI_Msk    = 0x8000  // Bit mask of TCRCI field.
	SPI_CR1_TCRCI        = 0x8000  // Bit TCRCI.
	SPI_CR1_RCRCI_Pos    = 0xe     // Position of RCRCI field.
	SPI_CR1_RCRCI_Msk    = 0x4000  // Bit mask of RCRCI field.
	SPI_CR1_RCRCI        = 0x4000  // Bit RCRCI.
	SPI_CR1_CRC33_17_Pos = 0xd     // Position of CRC33_17 field.
	SPI_CR1_CRC33_17_Msk = 0x2000  // Bit mask of CRC33_17 field.
	SPI_CR1_CRC33_17     = 0x2000  // Bit CRC33_17.
	SPI_CR1_SSI_Pos      = 0xc     // Position of SSI field.
	SPI_CR1_SSI_Msk      = 0x1000  // Bit mask of SSI field.
	SPI_CR1_SSI          = 0x1000  // Bit SSI.
	SPI_CR1_HDDIR_Pos    = 0xb     // Position of HDDIR field.
	SPI_CR1_HDDIR_Msk    = 0x800   // Bit mask of HDDIR field.
	SPI_CR1_HDDIR        = 0x800   // Bit HDDIR.
	SPI_CR1_CSUSP_Pos    = 0xa     // Position of CSUSP field.
	SPI_CR1_CSUSP_Msk    = 0x400   // Bit mask of CSUSP field.
	SPI_CR1_CSUSP        = 0x400   // Bit CSUSP.
	SPI_CR1_CSTART_Pos   = 0x9     // Position of CSTART field.
	SPI_CR1_CSTART_Msk   = 0x200   // Bit mask of CSTART field.
	SPI_CR1_CSTART       = 0x200   // Bit CSTART.
	SPI_CR1_MASRX_Pos    = 0x8     // Position of MASRX field.
	SPI_CR1_MASRX_Msk    = 0x100   // Bit mask of MASRX field.
	SPI_CR1_MASRX        = 0x100   // Bit MASRX.
	SPI_CR1_SPE_Pos      = 0x0     // Position of SPE field.
	SPI_CR1_SPE_Msk      = 0x1     // Bit mask of SPE field.
	SPI_CR1_SPE          = 0x1     // Bit SPE.

	// CR2: control register 2
	SPI_CR2_TSER_Pos  = 0x10       // Position of TSER field.
	SPI_CR2_TSER_Msk  = 0xffff0000 // Bit mask of TSER field.
	SPI_CR2_TSIZE_Pos = 0x0        // Position of TSIZE field.
	SPI_CR2_TSIZE_Msk = 0xffff     // Bit mask of TSIZE field.

	// CFG1: configuration register 1
	SPI_CFG1_MBR_Pos     = 0x1c       // Position of MBR field.
	SPI_CFG1_MBR_Msk     = 0x70000000 // Bit mask of MBR field.
	SPI_CFG1_CRCEN_Pos   = 0x16       // Position of CRCEN field.
	SPI_CFG1_CRCEN_Msk   = 0x400000   // Bit mask of CRCEN field.
	SPI_CFG1_CRCEN       = 0x400000   // Bit CRCEN.
	SPI_CFG1_CRCSIZE_Pos = 0x10       // Position of CRCSIZE field.
	SPI_CFG1_CRCSIZE_Msk = 0x1f0000   // Bit mask of CRCSIZE field.
	SPI_CFG1_TXDMAEN_Pos = 0xf        // Position of TXDMAEN field.
	SPI_CFG1_TXDMAEN_Msk = 0x8000     // Bit mask of TXDMAEN field.
	SPI_CFG1_TXDMAEN     = 0x8000     // Bit TXDMAEN.
	SPI_CFG1_RXDMAEN_Pos = 0xe        // Position of RXDMAEN field.
	SPI_CFG1_RXDMAEN_Msk = 0x4000     // Bit mask of RXDMAEN field.
	SPI_CFG1_RXDMAEN     = 0x4000     // Bit RXDMAEN.
	SPI_CFG1_UDRDET_Pos  = 0xb        // Position of UDRDET field.
	SPI_CFG1_UDRDET_Msk  = 0x1800     // Bit mask of UDRDET field.
	SPI_CFG1_UDRCFG_Pos  = 0x9        // Position of UDRCFG field.
	SPI_CFG1_UDRCFG_Msk  = 0x600      // Bit mask of UDRCFG field.
	SPI_CFG1_FTHVL_Pos   = 0x5        // Position of FTHVL field.
	SPI_CFG1_FTHVL_Msk   = 0x1e0      // Bit mask of FTHVL field.
	SPI_CFG1_DSIZE_Pos   = 0x0        // Position of DSIZE field.
	SPI_CFG1_DSIZE_Msk   = 0x1f       // Bit mask of DSIZE field.

	// CFG2: configuration register 2
	SPI_CFG2_AFCNTR_Pos  = 0x1f       // Position of AFCNTR field.
	SPI_CFG2_AFCNTR_Msk  = 0x80000000 // Bit mask of AFCNTR field.
	SPI_CFG2_AFCNTR      = 0x80000000 // Bit AFCNTR.
	SPI_CFG2_SSOM_Pos    = 0x1e       // Position of SSOM field.
	SPI_CFG2_SSOM_Msk    = 0x40000000 // Bit mask of SSOM field.
	SPI_CFG2_SSOM        = 0x40000000 // Bit SSOM.
	SPI_CFG2_SSOE_Pos    = 0x1d       // Position of SSOE field.
	SPI_CFG2_SSOE_Msk    = 0x20000000 // Bit mask of SSOE field.
	SPI_CFG2_SSOE        = 0x20000000 // Bit SSOE.
	SPI_CFG2_SSIOP_Pos   = 0x1c       // Position of SSIOP field.
	SPI_CFG2_SSIOP_Msk   = 0x10000000 // Bit mask of SSIOP field.
	SPI_CFG2_SSIOP       = 0x10000000 // Bit SSIOP.
	SPI_CFG2_SSM_Pos     = 0x1a       // Position of SSM field.
	SPI_CFG2_SSM_Msk     = 0x4000000  // Bit mask of SSM field.
	SPI_CFG2_SSM         = 0x4000000  // Bit SSM.
	SPI_CFG2_CPOL_Pos    = 0x19       // Position of CPOL field.
	SPI_CFG2_CPOL_Msk    = 0x2000000  // Bit mask of CPOL field.
	SPI_CFG2_CPOL        = 0x2000000  // Bit CPOL.
	SPI_CFG2_CPHA_Pos    = 0x18       // Position of CPHA field.
	SPI_CFG2_CPHA_Msk    = 0x1000000  // Bit mask of CPHA field.
	SPI_CFG2_CPHA        = 0x1000000  // Bit CPHA.
	SPI_CFG2_LSBFRST_Pos = 0x17       // Position of LSBFRST field.
	SPI_CFG2_LSBFRST_Msk = 0x800000   // Bit mask of LSBFRST field.
	SPI_CFG2_LSBFRST     = 0x800000   // Bit LSBFRST.
	SPI_CFG2_MASTER_Pos  = 0x16       // Position of MASTER field.
	SPI_CFG2_MASTER_Msk  = 0x400000   // Bit mask of MASTER field.
	SPI_CFG2_MASTER      = 0x400000   // Bit MASTER.
	SPI_CFG2_SP_Pos      = 0x13       // Position of SP field.
	SPI_CFG2_SP_Msk      = 0x380000   // Bit mask of SP field.
	SPI_CFG2_COMM_Pos    = 0x11       // Position of COMM field.
	SPI_CFG2_COMM_Msk    = 0x60000    // Bit mask of COMM field.
	SPI_CFG2_IOSWP_Pos   = 0xf        // Position of IOSWP field.
	SPI_CFG2_IOSWP_Msk   = 0x8000     // Bit mask of IOSWP field.
	SPI_CFG2_IOSWP       = 0x8000     // Bit IOSWP.
	SPI_CFG2_MIDI_Pos    = 0x4        // Position of MIDI field.
	SPI_CFG2_MIDI_Msk    = 0xf0       // Bit mask of MIDI field.
	SPI_CFG2_MSSI_Pos    = 0x0        // Position of MSSI field.
	SPI_CFG2_MSSI_Msk    = 0xf        // Bit mask of MSSI field.

	// IER: Interrupt Enable Register
	SPI_IER_TSERFIE_Pos = 0xa   // Position of TSERFIE field.
	SPI_IER_TSERFIE_Msk = 0x400 // Bit mask of TSERFIE field.
	SPI_IER_TSERFIE     = 0x400 // Bit TSERFIE.
	SPI_IER_MODFIE_Pos  = 0x9   // Position of MODFIE field.
	SPI_IER_MODFIE_Msk  = 0x200 // Bit mask of MODFIE field.
	SPI_IER_MODFIE      = 0x200 // Bit MODFIE.
	SPI_IER_TIFREIE_Pos = 0x8   // Position of TIFREIE field.
	SPI_IER_TIFREIE_Msk = 0x100 // Bit mask of TIFREIE field.
	SPI_IER_TIFREIE     = 0x100 // Bit TIFREIE.
	SPI_IER_CRCEIE_Pos  = 0x7   // Position of CRCEIE field.
	SPI_IER_CRCEIE_Msk  = 0x80  // Bit mask of CRCEIE field.
	SPI_IER_CRCEIE      = 0x80  // Bit CRCEIE.
	SPI_IER_OVRIE_Pos   = 0x6   // Position of OVRIE field.
	SPI_IER_OVRIE_Msk   = 0x40  // Bit mask of OVRIE field.
	SPI_IER_OVRIE       = 0x40  // Bit OVRIE.
	SPI_IER_UDRIE_Pos   = 0x5   // Position of UDRIE field.
	SPI_IER_UDRIE_Msk   = 0x20  // Bit mask of UDRIE field.
	SPI_IER_UDRIE       = 0x20  // Bit UDRIE.
	SPI_IER_TXTFIE_Pos  = 0x4   // Position of TXTFIE field.
	SPI_IER_TXTFIE_Msk  = 0x10  // Bit mask of TXTFIE field.
	SPI_IER_TXTFIE      = 0x10  // Bit TXTFIE.
	SPI_IER_EOTIE_Pos   = 0x3   // Position of EOTIE field.
	SPI_IER_EOTIE_Msk   = 0x8   // Bit mask of EOTIE field.
	SPI_IER_EOTIE       = 0x8   // Bit EOTIE.
	SPI_IER_DPXPIE_Pos  = 0x2   // Position of DPXPIE field.
	SPI_IER_DPXPIE_Msk  = 0x4   // Bit mask of DPXPIE field.
	SPI_IER_DPXPIE      = 0x4   // Bit DPXPIE.
	SPI_IER_TXPIE_Pos   = 0x1   // Position of TXPIE field.
	SPI_IER_TXPIE_Msk   = 0x2   // Bit mask of TXPIE field.
	SPI_IER_TXPIE       = 0x2   // Bit TXPIE.
	SPI_IER_RXPIE_Pos   = 0x0   // Position of RXPIE field.
	SPI_IER_RXPIE_Msk   = 0x1   // Bit mask of RXPIE field.
	SPI_IER_RXPIE       = 0x1   // Bit RXPIE.

	// SR: Status Register
	SPI_SR_CTSIZE_Pos = 0x10       // Position of CTSIZE field.
	SPI_SR_CTSIZE_Msk = 0xffff0000 // Bit mask of CTSIZE field.
	SPI_SR_RXWNE_Pos  = 0xf        // Position of RXWNE field.
	SPI_SR_RXWNE_Msk  = 0x8000     // Bit mask of RXWNE field.
	SPI_SR_RXWNE      = 0x8000     // Bit RXWNE.
	SPI_SR_RXPLVL_Pos = 0xd        // Position of RXPLVL field.
	SPI_SR_RXPLVL_Msk = 0x6000     // Bit mask of RXPLVL field.
	SPI_SR_TXC_Pos    = 0xc        // Position of TXC field.
	SPI_SR_TXC_Msk    = 0x1000     // Bit mask of TXC field.
	SPI_SR_TXC        = 0x1000     // Bit TXC.
	SPI_SR_SUSP_Pos   = 0xb        // Position of SUSP field.
	SPI_SR_SUSP_Msk   = 0x800      // Bit mask of SUSP field.
	SPI_SR_SUSP       = 0x800      // Bit SUSP.
	SPI_SR_TSERF_Pos  = 0xa        // Position of TSERF field.
	SPI_SR_TSERF_Msk  = 0x400      // Bit mask of TSERF field.
	SPI_SR_TSERF      = 0x400      // Bit TSERF.
	SPI_SR_MODF_Pos   = 0x9        // Position of MODF field.
	SPI_SR_MODF_Msk   = 0x200      // Bit mask of MODF field.
	SPI_SR_MODF       = 0x200      // Bit MODF.
	SPI_SR_TIFRE_Pos  = 0x8        // Position of TIFRE field.
	SPI_SR_TIFRE_Msk  = 0x100      // Bit mask of TIFRE field.
	SPI_SR_TIFRE      = 0x100      // Bit TIFRE.
	SPI_SR_CRCE_Pos   = 0x7        // Position of CRCE field.
	SPI_SR_CRCE_Msk   = 0x80       // Bit mask of CRCE field.
	SPI_SR_CRCE       = 0x80       // Bit CRCE.
	SPI_SR_OVR_Pos    = 0x6        // Position of OVR field.
	SPI_SR_OVR_Msk    = 0x40       // Bit mask of OVR field.
	SPI_SR_OVR        = 0x40       // Bit OVR.
	SPI_SR_UDR_Pos    = 0x5        // Position of UDR field.
	SPI_SR_UDR_Msk    = 0x20       // Bit mask of UDR field.
	SPI_SR_UDR        = 0x20       // Bit UDR.
	SPI_SR_TXTF_Pos   = 0x4        // Position of TXTF field.
	SPI_SR_TXTF_Msk   = 0x10       // Bit mask of TXTF field.
	SPI_SR_TXTF       = 0x10       // Bit TXTF.
	SPI_SR_EOT_Pos    = 0x3        // Position of EOT field.
	SPI_SR_EOT_Msk    = 0x8        // Bit mask of EOT field.
	SPI_SR_EOT        = 0x8        // Bit EOT.
	SPI_SR_DXP_Pos    = 0x2        // Position of DXP field.
	SPI_SR_DXP_Msk    = 0x4        // Bit mask of DXP field.
	SPI_SR_DXP        = 0x4        // Bit DXP.
	SPI_SR_TXP_Pos    = 0x1        // Position of TXP field.
	SPI_SR_TXP_Msk    = 0x2        // Bit mask of TXP field.
	SPI_SR_TXP        = 0x2        // Bit TXP.
	SPI_SR_RXP_Pos    = 0x0        // Position of RXP field.
	SPI_SR_RXP_Msk    = 0x1        // Bit mask of RXP field.
	SPI_SR_RXP        = 0x1        // Bit RXP.

	// IFCR: Interrupt/Status Flags Clear           Register
	SPI_IFCR_SUSPC_Pos  = 0xb   // Position of SUSPC field.
	SPI_IFCR_SUSPC_Msk  = 0x800 // Bit mask of SUSPC field.
	SPI_IFCR_SUSPC      = 0x800 // Bit SUSPC.
	SPI_IFCR_TSERFC_Pos = 0xa   // Position of TSERFC field.
	SPI_IFCR_TSERFC_Msk = 0x400 // Bit mask of TSERFC field.
	SPI_IFCR_TSERFC     = 0x400 // Bit TSERFC.
	SPI_IFCR_MODFC_Pos  = 0x9   // Position of MODFC field.
	SPI_IFCR_MODFC_Msk  = 0x200 // Bit mask of MODFC field.
	SPI_IFCR_MODFC      = 0x200 // Bit MODFC.
	SPI_IFCR_TIFREC_Pos = 0x8   // Position of TIFREC field.
	SPI_IFCR_TIFREC_Msk = 0x100 // Bit mask of TIFREC field.
	SPI_IFCR_TIFREC     = 0x100 // Bit TIFREC.
	SPI_IFCR_CRCEC_Pos  = 0x7   // Position of CRCEC field.
	SPI_IFCR_CRCEC_Msk  = 0x80  // Bit mask of CRCEC field.
	SPI_IFCR_CRCEC      = 0x80  // Bit CRCEC.
	SPI_IFCR_OVRC_Pos   = 0x6   // Position of OVRC field.
	SPI_IFCR_OVRC_Msk   = 0x40  // Bit mask of OVRC field.
	SPI_IFCR_OVRC       = 0x40  // Bit OVRC.
	SPI_IFCR_UDRC_Pos   = 0x5   // Position of UDRC field.
	SPI_IFCR_UDRC_Msk   = 0x20  // Bit mask of UDRC field.
	SPI_IFCR_UDRC       = 0x20  // Bit UDRC.
	SPI_IFCR_TXTFC_Pos  = 0x4   // Position of TXTFC field.
	SPI_IFCR_TXTFC_Msk  = 0x10  // Bit mask of TXTFC field.
	SPI_IFCR_TXTFC      = 0x10  // Bit TXTFC.
	SPI_IFCR_EOTC_Pos   = 0x3   // Position of EOTC field.
	SPI_IFCR_EOTC_Msk   = 0x8   // Bit mask of EOTC field.
	SPI_IFCR_EOTC       = 0x8   // Bit EOTC.

	// TXDR: Transmit Data Register
	SPI_TXDR_TXDR_Pos = 0x0        // Position of TXDR field.
	SPI_TXDR_TXDR_Msk = 0xffffffff // Bit mask of TXDR field.

	// RXDR: Receive Data Register
	SPI_RXDR_RXDR_Pos = 0x0        // Position of RXDR field.
	SPI_RXDR_RXDR_Msk = 0xffffffff // Bit mask of RXDR field.

	// CRCPOLY: Polynomial Register
	SPI_CRCPOLY_CRCPOLY_Pos = 0x0        // Position of CRCPOLY field.
	SPI_CRCPOLY_CRCPOLY_Msk = 0xffffffff // Bit mask of CRCPOLY field.

	// TXCRC: Transmitter CRC Register
	SPI_TXCRC_TXCRC_Pos = 0x0        // Position of TXCRC field.
	SPI_TXCRC_TXCRC_Msk = 0xffffffff // Bit mask of TXCRC field.

	// RXCRC: Receiver CRC Register
	SPI_RXCRC_RXCRC_Pos = 0x0        // Position of RXCRC field.
	SPI_RXCRC_RXCRC_Msk = 0xffffffff // Bit mask of RXCRC field.

	// UDRDR: Underrun Data Register
	SPI_UDRDR_UDRDR_Pos = 0x0        // Position of UDRDR field.
	SPI_UDRDR_UDRDR_Msk = 0xffffffff // Bit mask of UDRDR field.

	// CGFR: configuration register
	SPI_CGFR_MCKOE_Pos   = 0x19      // Position of MCKOE field.
	SPI_CGFR_MCKOE_Msk   = 0x2000000 // Bit mask of MCKOE field.
	SPI_CGFR_MCKOE       = 0x2000000 // Bit MCKOE.
	SPI_CGFR_ODD_Pos     = 0x18      // Position of ODD field.
	SPI_CGFR_ODD_Msk     = 0x1000000 // Bit mask of ODD field.
	SPI_CGFR_ODD         = 0x1000000 // Bit ODD.
	SPI_CGFR_I2SDIV_Pos  = 0x10      // Position of I2SDIV field.
	SPI_CGFR_I2SDIV_Msk  = 0xff0000  // Bit mask of I2SDIV field.
	SPI_CGFR_DATFMT_Pos  = 0xe       // Position of DATFMT field.
	SPI_CGFR_DATFMT_Msk  = 0x4000    // Bit mask of DATFMT field.
	SPI_CGFR_DATFMT      = 0x4000    // Bit DATFMT.
	SPI_CGFR_WSINV_Pos   = 0xd       // Position of WSINV field.
	SPI_CGFR_WSINV_Msk   = 0x2000    // Bit mask of WSINV field.
	SPI_CGFR_WSINV       = 0x2000    // Bit WSINV.
	SPI_CGFR_FIXCH_Pos   = 0xc       // Position of FIXCH field.
	SPI_CGFR_FIXCH_Msk   = 0x1000    // Bit mask of FIXCH field.
	SPI_CGFR_FIXCH       = 0x1000    // Bit FIXCH.
	SPI_CGFR_CKPOL_Pos   = 0xb       // Position of CKPOL field.
	SPI_CGFR_CKPOL_Msk   = 0x800     // Bit mask of CKPOL field.
	SPI_CGFR_CKPOL       = 0x800     // Bit CKPOL.
	SPI_CGFR_CHLEN_Pos   = 0xa       // Position of CHLEN field.
	SPI_CGFR_CHLEN_Msk   = 0x400     // Bit mask of CHLEN field.
	SPI_CGFR_CHLEN       = 0x400     // Bit CHLEN.
	SPI_CGFR_DATLEN_Pos  = 0x8       // Position of DATLEN field.
	SPI_CGFR_DATLEN_Msk  = 0x300     // Bit mask of DATLEN field.
	SPI_CGFR_PCMSYNC_Pos = 0x7       // Position of PCMSYNC field.
	SPI_CGFR_PCMSYNC_Msk = 0x80      // Bit mask of PCMSYNC field.
	SPI_CGFR_PCMSYNC     = 0x80      // Bit PCMSYNC.
	SPI_CGFR_I2SSTD_Pos  = 0x4       // Position of I2SSTD field.
	SPI_CGFR_I2SSTD_Msk  = 0x30      // Bit mask of I2SSTD field.
	SPI_CGFR_I2SCFG_Pos  = 0x1       // Position of I2SCFG field.
	SPI_CGFR_I2SCFG_Msk  = 0xe       // Bit mask of I2SCFG field.
	SPI_CGFR_I2SMOD_Pos  = 0x0       // Position of I2SMOD field.
	SPI_CGFR_I2SMOD_Msk  = 0x1       // Bit mask of I2SMOD field.
	SPI_CGFR_I2SMOD      = 0x1       // Bit I2SMOD.
)

// Bitfields for LTDC: LCD-TFT Controller
const (
	// SSCR: Synchronization Size Configuration           Register
	LTDC_SSCR_HSW_Pos = 0x10      // Position of HSW field.
	LTDC_SSCR_HSW_Msk = 0x3ff0000 // Bit mask of HSW field.
	LTDC_SSCR_VSH_Pos = 0x0       // Position of VSH field.
	LTDC_SSCR_VSH_Msk = 0x7ff     // Bit mask of VSH field.

	// BPCR: Back Porch Configuration           Register
	LTDC_BPCR_AHBP_Pos = 0x10      // Position of AHBP field.
	LTDC_BPCR_AHBP_Msk = 0xfff0000 // Bit mask of AHBP field.
	LTDC_BPCR_AVBP_Pos = 0x0       // Position of AVBP field.
	LTDC_BPCR_AVBP_Msk = 0x7ff     // Bit mask of AVBP field.

	// AWCR: Active Width Configuration           Register
	LTDC_AWCR_AAV_Pos = 0x10      // Position of AAV field.
	LTDC_AWCR_AAV_Msk = 0xfff0000 // Bit mask of AAV field.
	LTDC_AWCR_AAH_Pos = 0x0       // Position of AAH field.
	LTDC_AWCR_AAH_Msk = 0x7ff     // Bit mask of AAH field.

	// TWCR: Total Width Configuration           Register
	LTDC_TWCR_TOTALW_Pos = 0x10      // Position of TOTALW field.
	LTDC_TWCR_TOTALW_Msk = 0xfff0000 // Bit mask of TOTALW field.
	LTDC_TWCR_TOTALH_Pos = 0x0       // Position of TOTALH field.
	LTDC_TWCR_TOTALH_Msk = 0x7ff     // Bit mask of TOTALH field.

	// GCR: Global Control Register
	LTDC_GCR_HSPOL_Pos  = 0x1f       // Position of HSPOL field.
	LTDC_GCR_HSPOL_Msk  = 0x80000000 // Bit mask of HSPOL field.
	LTDC_GCR_HSPOL      = 0x80000000 // Bit HSPOL.
	LTDC_GCR_VSPOL_Pos  = 0x1e       // Position of VSPOL field.
	LTDC_GCR_VSPOL_Msk  = 0x40000000 // Bit mask of VSPOL field.
	LTDC_GCR_VSPOL      = 0x40000000 // Bit VSPOL.
	LTDC_GCR_DEPOL_Pos  = 0x1d       // Position of DEPOL field.
	LTDC_GCR_DEPOL_Msk  = 0x20000000 // Bit mask of DEPOL field.
	LTDC_GCR_DEPOL      = 0x20000000 // Bit DEPOL.
	LTDC_GCR_PCPOL_Pos  = 0x1c       // Position of PCPOL field.
	LTDC_GCR_PCPOL_Msk  = 0x10000000 // Bit mask of PCPOL field.
	LTDC_GCR_PCPOL      = 0x10000000 // Bit PCPOL.
	LTDC_GCR_DEN_Pos    = 0x10       // Position of DEN field.
	LTDC_GCR_DEN_Msk    = 0x10000    // Bit mask of DEN field.
	LTDC_GCR_DEN        = 0x10000    // Bit DEN.
	LTDC_GCR_DRW_Pos    = 0xc        // Position of DRW field.
	LTDC_GCR_DRW_Msk    = 0x7000     // Bit mask of DRW field.
	LTDC_GCR_DGW_Pos    = 0x8        // Position of DGW field.
	LTDC_GCR_DGW_Msk    = 0x700      // Bit mask of DGW field.
	LTDC_GCR_DBW_Pos    = 0x4        // Position of DBW field.
	LTDC_GCR_DBW_Msk    = 0x70       // Bit mask of DBW field.
	LTDC_GCR_LTDCEN_Pos = 0x0        // Position of LTDCEN field.
	LTDC_GCR_LTDCEN_Msk = 0x1        // Bit mask of LTDCEN field.
	LTDC_GCR_LTDCEN     = 0x1        // Bit LTDCEN.

	// SRCR: Shadow Reload Configuration           Register
	LTDC_SRCR_VBR_Pos = 0x1 // Position of VBR field.
	LTDC_SRCR_VBR_Msk = 0x2 // Bit mask of VBR field.
	LTDC_SRCR_VBR     = 0x2 // Bit VBR.
	LTDC_SRCR_IMR_Pos = 0x0 // Position of IMR field.
	LTDC_SRCR_IMR_Msk = 0x1 // Bit mask of IMR field.
	LTDC_SRCR_IMR     = 0x1 // Bit IMR.

	// BCCR: Background Color Configuration           Register
	LTDC_BCCR_BCBLUE_Pos  = 0x0      // Position of BCBLUE field.
	LTDC_BCCR_BCBLUE_Msk  = 0xff     // Bit mask of BCBLUE field.
	LTDC_BCCR_BCGREEN_Pos = 0x8      // Position of BCGREEN field.
	LTDC_BCCR_BCGREEN_Msk = 0xff00   // Bit mask of BCGREEN field.
	LTDC_BCCR_BCRED_Pos   = 0x10     // Position of BCRED field.
	LTDC_BCCR_BCRED_Msk   = 0xff0000 // Bit mask of BCRED field.

	// IER: Interrupt Enable Register
	LTDC_IER_RRIE_Pos   = 0x3 // Position of RRIE field.
	LTDC_IER_RRIE_Msk   = 0x8 // Bit mask of RRIE field.
	LTDC_IER_RRIE       = 0x8 // Bit RRIE.
	LTDC_IER_TERRIE_Pos = 0x2 // Position of TERRIE field.
	LTDC_IER_TERRIE_Msk = 0x4 // Bit mask of TERRIE field.
	LTDC_IER_TERRIE     = 0x4 // Bit TERRIE.
	LTDC_IER_FUIE_Pos   = 0x1 // Position of FUIE field.
	LTDC_IER_FUIE_Msk   = 0x2 // Bit mask of FUIE field.
	LTDC_IER_FUIE       = 0x2 // Bit FUIE.
	LTDC_IER_LIE_Pos    = 0x0 // Position of LIE field.
	LTDC_IER_LIE_Msk    = 0x1 // Bit mask of LIE field.
	LTDC_IER_LIE        = 0x1 // Bit LIE.

	// ISR: Interrupt Status Register
	LTDC_ISR_RRIF_Pos   = 0x3 // Position of RRIF field.
	LTDC_ISR_RRIF_Msk   = 0x8 // Bit mask of RRIF field.
	LTDC_ISR_RRIF       = 0x8 // Bit RRIF.
	LTDC_ISR_TERRIF_Pos = 0x2 // Position of TERRIF field.
	LTDC_ISR_TERRIF_Msk = 0x4 // Bit mask of TERRIF field.
	LTDC_ISR_TERRIF     = 0x4 // Bit TERRIF.
	LTDC_ISR_FUIF_Pos   = 0x1 // Position of FUIF field.
	LTDC_ISR_FUIF_Msk   = 0x2 // Bit mask of FUIF field.
	LTDC_ISR_FUIF       = 0x2 // Bit FUIF.
	LTDC_ISR_LIF_Pos    = 0x0 // Position of LIF field.
	LTDC_ISR_LIF_Msk    = 0x1 // Bit mask of LIF field.
	LTDC_ISR_LIF        = 0x1 // Bit LIF.

	// ICR: Interrupt Clear Register
	LTDC_ICR_CRRIF_Pos   = 0x3 // Position of CRRIF field.
	LTDC_ICR_CRRIF_Msk   = 0x8 // Bit mask of CRRIF field.
	LTDC_ICR_CRRIF       = 0x8 // Bit CRRIF.
	LTDC_ICR_CTERRIF_Pos = 0x2 // Position of CTERRIF field.
	LTDC_ICR_CTERRIF_Msk = 0x4 // Bit mask of CTERRIF field.
	LTDC_ICR_CTERRIF     = 0x4 // Bit CTERRIF.
	LTDC_ICR_CFUIF_Pos   = 0x1 // Position of CFUIF field.
	LTDC_ICR_CFUIF_Msk   = 0x2 // Bit mask of CFUIF field.
	LTDC_ICR_CFUIF       = 0x2 // Bit CFUIF.
	LTDC_ICR_CLIF_Pos    = 0x0 // Position of CLIF field.
	LTDC_ICR_CLIF_Msk    = 0x1 // Bit mask of CLIF field.
	LTDC_ICR_CLIF        = 0x1 // Bit CLIF.

	// LIPCR: Line Interrupt Position Configuration           Register
	LTDC_LIPCR_LIPOS_Pos = 0x0   // Position of LIPOS field.
	LTDC_LIPCR_LIPOS_Msk = 0x7ff // Bit mask of LIPOS field.

	// CPSR: Current Position Status           Register
	LTDC_CPSR_CXPOS_Pos = 0x10       // Position of CXPOS field.
	LTDC_CPSR_CXPOS_Msk = 0xffff0000 // Bit mask of CXPOS field.
	LTDC_CPSR_CYPOS_Pos = 0x0        // Position of CYPOS field.
	LTDC_CPSR_CYPOS_Msk = 0xffff     // Bit mask of CYPOS field.

	// CDSR: Current Display Status           Register
	LTDC_CDSR_HSYNCS_Pos = 0x3 // Position of HSYNCS field.
	LTDC_CDSR_HSYNCS_Msk = 0x8 // Bit mask of HSYNCS field.
	LTDC_CDSR_HSYNCS     = 0x8 // Bit HSYNCS.
	LTDC_CDSR_VSYNCS_Pos = 0x2 // Position of VSYNCS field.
	LTDC_CDSR_VSYNCS_Msk = 0x4 // Bit mask of VSYNCS field.
	LTDC_CDSR_VSYNCS     = 0x4 // Bit VSYNCS.
	LTDC_CDSR_HDES_Pos   = 0x1 // Position of HDES field.
	LTDC_CDSR_HDES_Msk   = 0x2 // Bit mask of HDES field.
	LTDC_CDSR_HDES       = 0x2 // Bit HDES.
	LTDC_CDSR_VDES_Pos   = 0x0 // Position of VDES field.
	LTDC_CDSR_VDES_Msk   = 0x1 // Bit mask of VDES field.
	LTDC_CDSR_VDES       = 0x1 // Bit VDES.

	// L1CR: Layerx Control Register
	LTDC_L1CR_CLUTEN_Pos = 0x4  // Position of CLUTEN field.
	LTDC_L1CR_CLUTEN_Msk = 0x10 // Bit mask of CLUTEN field.
	LTDC_L1CR_CLUTEN     = 0x10 // Bit CLUTEN.
	LTDC_L1CR_COLKEN_Pos = 0x1  // Position of COLKEN field.
	LTDC_L1CR_COLKEN_Msk = 0x2  // Bit mask of COLKEN field.
	LTDC_L1CR_COLKEN     = 0x2  // Bit COLKEN.
	LTDC_L1CR_LEN_Pos    = 0x0  // Position of LEN field.
	LTDC_L1CR_LEN_Msk    = 0x1  // Bit mask of LEN field.
	LTDC_L1CR_LEN        = 0x1  // Bit LEN.

	// L1WHPCR: Layerx Window Horizontal Position           Configuration Register
	LTDC_L1WHPCR_WHSPPOS_Pos = 0x10      // Position of WHSPPOS field.
	LTDC_L1WHPCR_WHSPPOS_Msk = 0xfff0000 // Bit mask of WHSPPOS field.
	LTDC_L1WHPCR_WHSTPOS_Pos = 0x0       // Position of WHSTPOS field.
	LTDC_L1WHPCR_WHSTPOS_Msk = 0xfff     // Bit mask of WHSTPOS field.

	// L1WVPCR: Layerx Window Vertical Position           Configuration Register
	LTDC_L1WVPCR_WVSPPOS_Pos = 0x10      // Position of WVSPPOS field.
	LTDC_L1WVPCR_WVSPPOS_Msk = 0x7ff0000 // Bit mask of WVSPPOS field.
	LTDC_L1WVPCR_WVSTPOS_Pos = 0x0       // Position of WVSTPOS field.
	LTDC_L1WVPCR_WVSTPOS_Msk = 0x7ff     // Bit mask of WVSTPOS field.

	// L1CKCR: Layerx Color Keying Configuration           Register
	LTDC_L1CKCR_CKRED_Pos   = 0x10     // Position of CKRED field.
	LTDC_L1CKCR_CKRED_Msk   = 0xff0000 // Bit mask of CKRED field.
	LTDC_L1CKCR_CKGREEN_Pos = 0x8      // Position of CKGREEN field.
	LTDC_L1CKCR_CKGREEN_Msk = 0xff00   // Bit mask of CKGREEN field.
	LTDC_L1CKCR_CKBLUE_Pos  = 0x0      // Position of CKBLUE field.
	LTDC_L1CKCR_CKBLUE_Msk  = 0xff     // Bit mask of CKBLUE field.

	// L1PFCR: Layerx Pixel Format Configuration           Register
	LTDC_L1PFCR_PF_Pos = 0x0 // Position of PF field.
	LTDC_L1PFCR_PF_Msk = 0x7 // Bit mask of PF field.

	// L1CACR: Layerx Constant Alpha Configuration           Register
	LTDC_L1CACR_CONSTA_Pos = 0x0  // Position of CONSTA field.
	LTDC_L1CACR_CONSTA_Msk = 0xff // Bit mask of CONSTA field.

	// L1DCCR: Layerx Default Color Configuration           Register
	LTDC_L1DCCR_DCALPHA_Pos = 0x18       // Position of DCALPHA field.
	LTDC_L1DCCR_DCALPHA_Msk = 0xff000000 // Bit mask of DCALPHA field.
	LTDC_L1DCCR_DCRED_Pos   = 0x10       // Position of DCRED field.
	LTDC_L1DCCR_DCRED_Msk   = 0xff0000   // Bit mask of DCRED field.
	LTDC_L1DCCR_DCGREEN_Pos = 0x8        // Position of DCGREEN field.
	LTDC_L1DCCR_DCGREEN_Msk = 0xff00     // Bit mask of DCGREEN field.
	LTDC_L1DCCR_DCBLUE_Pos  = 0x0        // Position of DCBLUE field.
	LTDC_L1DCCR_DCBLUE_Msk  = 0xff       // Bit mask of DCBLUE field.

	// L1BFCR: Layerx Blending Factors Configuration           Register
	LTDC_L1BFCR_BF1_Pos = 0x8   // Position of BF1 field.
	LTDC_L1BFCR_BF1_Msk = 0x700 // Bit mask of BF1 field.
	LTDC_L1BFCR_BF2_Pos = 0x0   // Position of BF2 field.
	LTDC_L1BFCR_BF2_Msk = 0x7   // Bit mask of BF2 field.

	// L1CFBAR: Layerx Color Frame Buffer Address           Register
	LTDC_L1CFBAR_CFBADD_Pos = 0x0        // Position of CFBADD field.
	LTDC_L1CFBAR_CFBADD_Msk = 0xffffffff // Bit mask of CFBADD field.

	// L1CFBLR: Layerx Color Frame Buffer Length           Register
	LTDC_L1CFBLR_CFBP_Pos  = 0x10       // Position of CFBP field.
	LTDC_L1CFBLR_CFBP_Msk  = 0x1fff0000 // Bit mask of CFBP field.
	LTDC_L1CFBLR_CFBLL_Pos = 0x0        // Position of CFBLL field.
	LTDC_L1CFBLR_CFBLL_Msk = 0x1fff     // Bit mask of CFBLL field.

	// L1CFBLNR: Layerx ColorFrame Buffer Line Number           Register
	LTDC_L1CFBLNR_CFBLNBR_Pos = 0x0   // Position of CFBLNBR field.
	LTDC_L1CFBLNR_CFBLNBR_Msk = 0x7ff // Bit mask of CFBLNBR field.

	// L1CLUTWR: Layerx CLUT Write Register
	LTDC_L1CLUTWR_CLUTADD_Pos = 0x18       // Position of CLUTADD field.
	LTDC_L1CLUTWR_CLUTADD_Msk = 0xff000000 // Bit mask of CLUTADD field.
	LTDC_L1CLUTWR_RED_Pos     = 0x10       // Position of RED field.
	LTDC_L1CLUTWR_RED_Msk     = 0xff0000   // Bit mask of RED field.
	LTDC_L1CLUTWR_GREEN_Pos   = 0x8        // Position of GREEN field.
	LTDC_L1CLUTWR_GREEN_Msk   = 0xff00     // Bit mask of GREEN field.
	LTDC_L1CLUTWR_BLUE_Pos    = 0x0        // Position of BLUE field.
	LTDC_L1CLUTWR_BLUE_Msk    = 0xff       // Bit mask of BLUE field.

	// L2CR: Layerx Control Register
	LTDC_L2CR_CLUTEN_Pos = 0x4  // Position of CLUTEN field.
	LTDC_L2CR_CLUTEN_Msk = 0x10 // Bit mask of CLUTEN field.
	LTDC_L2CR_CLUTEN     = 0x10 // Bit CLUTEN.
	LTDC_L2CR_COLKEN_Pos = 0x1  // Position of COLKEN field.
	LTDC_L2CR_COLKEN_Msk = 0x2  // Bit mask of COLKEN field.
	LTDC_L2CR_COLKEN     = 0x2  // Bit COLKEN.
	LTDC_L2CR_LEN_Pos    = 0x0  // Position of LEN field.
	LTDC_L2CR_LEN_Msk    = 0x1  // Bit mask of LEN field.
	LTDC_L2CR_LEN        = 0x1  // Bit LEN.

	// L2WHPCR: Layerx Window Horizontal Position           Configuration Register
	LTDC_L2WHPCR_WHSPPOS_Pos = 0x10      // Position of WHSPPOS field.
	LTDC_L2WHPCR_WHSPPOS_Msk = 0xfff0000 // Bit mask of WHSPPOS field.
	LTDC_L2WHPCR_WHSTPOS_Pos = 0x0       // Position of WHSTPOS field.
	LTDC_L2WHPCR_WHSTPOS_Msk = 0xfff     // Bit mask of WHSTPOS field.

	// L2WVPCR: Layerx Window Vertical Position           Configuration Register
	LTDC_L2WVPCR_WVSPPOS_Pos = 0x10      // Position of WVSPPOS field.
	LTDC_L2WVPCR_WVSPPOS_Msk = 0x7ff0000 // Bit mask of WVSPPOS field.
	LTDC_L2WVPCR_WVSTPOS_Pos = 0x0       // Position of WVSTPOS field.
	LTDC_L2WVPCR_WVSTPOS_Msk = 0x7ff     // Bit mask of WVSTPOS field.

	// L2CKCR: Layerx Color Keying Configuration           Register
	LTDC_L2CKCR_CKRED_Pos   = 0x10     // Position of CKRED field.
	LTDC_L2CKCR_CKRED_Msk   = 0xff0000 // Bit mask of CKRED field.
	LTDC_L2CKCR_CKGREEN_Pos = 0x8      // Position of CKGREEN field.
	LTDC_L2CKCR_CKGREEN_Msk = 0xff00   // Bit mask of CKGREEN field.
	LTDC_L2CKCR_CKBLUE_Pos  = 0x0      // Position of CKBLUE field.
	LTDC_L2CKCR_CKBLUE_Msk  = 0xff     // Bit mask of CKBLUE field.

	// L2PFCR: Layerx Pixel Format Configuration           Register
	LTDC_L2PFCR_PF_Pos = 0x0 // Position of PF field.
	LTDC_L2PFCR_PF_Msk = 0x7 // Bit mask of PF field.

	// L2CACR: Layerx Constant Alpha Configuration           Register
	LTDC_L2CACR_CONSTA_Pos = 0x0  // Position of CONSTA field.
	LTDC_L2CACR_CONSTA_Msk = 0xff // Bit mask of CONSTA field.

	// L2DCCR: Layerx Default Color Configuration           Register
	LTDC_L2DCCR_DCALPHA_Pos = 0x18       // Position of DCALPHA field.
	LTDC_L2DCCR_DCALPHA_Msk = 0xff000000 // Bit mask of DCALPHA field.
	LTDC_L2DCCR_DCRED_Pos   = 0x10       // Position of DCRED field.
	LTDC_L2DCCR_DCRED_Msk   = 0xff0000   // Bit mask of DCRED field.
	LTDC_L2DCCR_DCGREEN_Pos = 0x8        // Position of DCGREEN field.
	LTDC_L2DCCR_DCGREEN_Msk = 0xff00     // Bit mask of DCGREEN field.
	LTDC_L2DCCR_DCBLUE_Pos  = 0x0        // Position of DCBLUE field.
	LTDC_L2DCCR_DCBLUE_Msk  = 0xff       // Bit mask of DCBLUE field.

	// L2BFCR: Layerx Blending Factors Configuration           Register
	LTDC_L2BFCR_BF1_Pos = 0x8   // Position of BF1 field.
	LTDC_L2BFCR_BF1_Msk = 0x700 // Bit mask of BF1 field.
	LTDC_L2BFCR_BF2_Pos = 0x0   // Position of BF2 field.
	LTDC_L2BFCR_BF2_Msk = 0x7   // Bit mask of BF2 field.

	// L2CFBAR: Layerx Color Frame Buffer Address           Register
	LTDC_L2CFBAR_CFBADD_Pos = 0x0        // Position of CFBADD field.
	LTDC_L2CFBAR_CFBADD_Msk = 0xffffffff // Bit mask of CFBADD field.

	// L2CFBLR: Layerx Color Frame Buffer Length           Register
	LTDC_L2CFBLR_CFBP_Pos  = 0x10       // Position of CFBP field.
	LTDC_L2CFBLR_CFBP_Msk  = 0x1fff0000 // Bit mask of CFBP field.
	LTDC_L2CFBLR_CFBLL_Pos = 0x0        // Position of CFBLL field.
	LTDC_L2CFBLR_CFBLL_Msk = 0x1fff     // Bit mask of CFBLL field.

	// L2CFBLNR: Layerx ColorFrame Buffer Line Number           Register
	LTDC_L2CFBLNR_CFBLNBR_Pos = 0x0   // Position of CFBLNBR field.
	LTDC_L2CFBLNR_CFBLNBR_Msk = 0x7ff // Bit mask of CFBLNBR field.

	// L2CLUTWR: Layerx CLUT Write Register
	LTDC_L2CLUTWR_CLUTADD_Pos = 0x18       // Position of CLUTADD field.
	LTDC_L2CLUTWR_CLUTADD_Msk = 0xff000000 // Bit mask of CLUTADD field.
	LTDC_L2CLUTWR_RED_Pos     = 0x10       // Position of RED field.
	LTDC_L2CLUTWR_RED_Msk     = 0xff0000   // Bit mask of RED field.
	LTDC_L2CLUTWR_GREEN_Pos   = 0x8        // Position of GREEN field.
	LTDC_L2CLUTWR_GREEN_Msk   = 0xff00     // Bit mask of GREEN field.
	LTDC_L2CLUTWR_BLUE_Pos    = 0x0        // Position of BLUE field.
	LTDC_L2CLUTWR_BLUE_Msk    = 0xff       // Bit mask of BLUE field.
)

// Bitfields for SPDIFRX: Receiver Interface
const (
	// CR: Control register
	SPDIFRX_CR_SPDIFRXEN_Pos = 0x0      // Position of SPDIFRXEN field.
	SPDIFRX_CR_SPDIFRXEN_Msk = 0x3      // Bit mask of SPDIFRXEN field.
	SPDIFRX_CR_RXDMAEN_Pos   = 0x2      // Position of RXDMAEN field.
	SPDIFRX_CR_RXDMAEN_Msk   = 0x4      // Bit mask of RXDMAEN field.
	SPDIFRX_CR_RXDMAEN       = 0x4      // Bit RXDMAEN.
	SPDIFRX_CR_RXSTEO_Pos    = 0x3      // Position of RXSTEO field.
	SPDIFRX_CR_RXSTEO_Msk    = 0x8      // Bit mask of RXSTEO field.
	SPDIFRX_CR_RXSTEO        = 0x8      // Bit RXSTEO.
	SPDIFRX_CR_DRFMT_Pos     = 0x4      // Position of DRFMT field.
	SPDIFRX_CR_DRFMT_Msk     = 0x30     // Bit mask of DRFMT field.
	SPDIFRX_CR_PMSK_Pos      = 0x6      // Position of PMSK field.
	SPDIFRX_CR_PMSK_Msk      = 0x40     // Bit mask of PMSK field.
	SPDIFRX_CR_PMSK          = 0x40     // Bit PMSK.
	SPDIFRX_CR_VMSK_Pos      = 0x7      // Position of VMSK field.
	SPDIFRX_CR_VMSK_Msk      = 0x80     // Bit mask of VMSK field.
	SPDIFRX_CR_VMSK          = 0x80     // Bit VMSK.
	SPDIFRX_CR_CUMSK_Pos     = 0x8      // Position of CUMSK field.
	SPDIFRX_CR_CUMSK_Msk     = 0x100    // Bit mask of CUMSK field.
	SPDIFRX_CR_CUMSK         = 0x100    // Bit CUMSK.
	SPDIFRX_CR_PTMSK_Pos     = 0x9      // Position of PTMSK field.
	SPDIFRX_CR_PTMSK_Msk     = 0x200    // Bit mask of PTMSK field.
	SPDIFRX_CR_PTMSK         = 0x200    // Bit PTMSK.
	SPDIFRX_CR_CBDMAEN_Pos   = 0xa      // Position of CBDMAEN field.
	SPDIFRX_CR_CBDMAEN_Msk   = 0x400    // Bit mask of CBDMAEN field.
	SPDIFRX_CR_CBDMAEN       = 0x400    // Bit CBDMAEN.
	SPDIFRX_CR_CHSEL_Pos     = 0xb      // Position of CHSEL field.
	SPDIFRX_CR_CHSEL_Msk     = 0x800    // Bit mask of CHSEL field.
	SPDIFRX_CR_CHSEL         = 0x800    // Bit CHSEL.
	SPDIFRX_CR_NBTR_Pos      = 0xc      // Position of NBTR field.
	SPDIFRX_CR_NBTR_Msk      = 0x3000   // Bit mask of NBTR field.
	SPDIFRX_CR_WFA_Pos       = 0xe      // Position of WFA field.
	SPDIFRX_CR_WFA_Msk       = 0x4000   // Bit mask of WFA field.
	SPDIFRX_CR_WFA           = 0x4000   // Bit WFA.
	SPDIFRX_CR_INSEL_Pos     = 0x10     // Position of INSEL field.
	SPDIFRX_CR_INSEL_Msk     = 0x70000  // Bit mask of INSEL field.
	SPDIFRX_CR_CKSEN_Pos     = 0x14     // Position of CKSEN field.
	SPDIFRX_CR_CKSEN_Msk     = 0x100000 // Bit mask of CKSEN field.
	SPDIFRX_CR_CKSEN         = 0x100000 // Bit CKSEN.
	SPDIFRX_CR_CKSBKPEN_Pos  = 0x15     // Position of CKSBKPEN field.
	SPDIFRX_CR_CKSBKPEN_Msk  = 0x200000 // Bit mask of CKSBKPEN field.
	SPDIFRX_CR_CKSBKPEN      = 0x200000 // Bit CKSBKPEN.

	// IMR: Interrupt mask register
	SPDIFRX_IMR_RXNEIE_Pos  = 0x0  // Position of RXNEIE field.
	SPDIFRX_IMR_RXNEIE_Msk  = 0x1  // Bit mask of RXNEIE field.
	SPDIFRX_IMR_RXNEIE      = 0x1  // Bit RXNEIE.
	SPDIFRX_IMR_CSRNEIE_Pos = 0x1  // Position of CSRNEIE field.
	SPDIFRX_IMR_CSRNEIE_Msk = 0x2  // Bit mask of CSRNEIE field.
	SPDIFRX_IMR_CSRNEIE     = 0x2  // Bit CSRNEIE.
	SPDIFRX_IMR_PERRIE_Pos  = 0x2  // Position of PERRIE field.
	SPDIFRX_IMR_PERRIE_Msk  = 0x4  // Bit mask of PERRIE field.
	SPDIFRX_IMR_PERRIE      = 0x4  // Bit PERRIE.
	SPDIFRX_IMR_OVRIE_Pos   = 0x3  // Position of OVRIE field.
	SPDIFRX_IMR_OVRIE_Msk   = 0x8  // Bit mask of OVRIE field.
	SPDIFRX_IMR_OVRIE       = 0x8  // Bit OVRIE.
	SPDIFRX_IMR_SBLKIE_Pos  = 0x4  // Position of SBLKIE field.
	SPDIFRX_IMR_SBLKIE_Msk  = 0x10 // Bit mask of SBLKIE field.
	SPDIFRX_IMR_SBLKIE      = 0x10 // Bit SBLKIE.
	SPDIFRX_IMR_SYNCDIE_Pos = 0x5  // Position of SYNCDIE field.
	SPDIFRX_IMR_SYNCDIE_Msk = 0x20 // Bit mask of SYNCDIE field.
	SPDIFRX_IMR_SYNCDIE     = 0x20 // Bit SYNCDIE.
	SPDIFRX_IMR_IFEIE_Pos   = 0x6  // Position of IFEIE field.
	SPDIFRX_IMR_IFEIE_Msk   = 0x40 // Bit mask of IFEIE field.
	SPDIFRX_IMR_IFEIE       = 0x40 // Bit IFEIE.

	// SR: Status register
	SPDIFRX_SR_RXNE_Pos   = 0x0        // Position of RXNE field.
	SPDIFRX_SR_RXNE_Msk   = 0x1        // Bit mask of RXNE field.
	SPDIFRX_SR_RXNE       = 0x1        // Bit RXNE.
	SPDIFRX_SR_CSRNE_Pos  = 0x1        // Position of CSRNE field.
	SPDIFRX_SR_CSRNE_Msk  = 0x2        // Bit mask of CSRNE field.
	SPDIFRX_SR_CSRNE      = 0x2        // Bit CSRNE.
	SPDIFRX_SR_PERR_Pos   = 0x2        // Position of PERR field.
	SPDIFRX_SR_PERR_Msk   = 0x4        // Bit mask of PERR field.
	SPDIFRX_SR_PERR       = 0x4        // Bit PERR.
	SPDIFRX_SR_OVR_Pos    = 0x3        // Position of OVR field.
	SPDIFRX_SR_OVR_Msk    = 0x8        // Bit mask of OVR field.
	SPDIFRX_SR_OVR        = 0x8        // Bit OVR.
	SPDIFRX_SR_SBD_Pos    = 0x4        // Position of SBD field.
	SPDIFRX_SR_SBD_Msk    = 0x10       // Bit mask of SBD field.
	SPDIFRX_SR_SBD        = 0x10       // Bit SBD.
	SPDIFRX_SR_SYNCD_Pos  = 0x5        // Position of SYNCD field.
	SPDIFRX_SR_SYNCD_Msk  = 0x20       // Bit mask of SYNCD field.
	SPDIFRX_SR_SYNCD      = 0x20       // Bit SYNCD.
	SPDIFRX_SR_FERR_Pos   = 0x6        // Position of FERR field.
	SPDIFRX_SR_FERR_Msk   = 0x40       // Bit mask of FERR field.
	SPDIFRX_SR_FERR       = 0x40       // Bit FERR.
	SPDIFRX_SR_SERR_Pos   = 0x7        // Position of SERR field.
	SPDIFRX_SR_SERR_Msk   = 0x80       // Bit mask of SERR field.
	SPDIFRX_SR_SERR       = 0x80       // Bit SERR.
	SPDIFRX_SR_TERR_Pos   = 0x8        // Position of TERR field.
	SPDIFRX_SR_TERR_Msk   = 0x100      // Bit mask of TERR field.
	SPDIFRX_SR_TERR       = 0x100      // Bit TERR.
	SPDIFRX_SR_WIDTH5_Pos = 0x10       // Position of WIDTH5 field.
	SPDIFRX_SR_WIDTH5_Msk = 0x7fff0000 // Bit mask of WIDTH5 field.

	// IFCR: Interrupt Flag Clear register
	SPDIFRX_IFCR_PERRCF_Pos  = 0x2  // Position of PERRCF field.
	SPDIFRX_IFCR_PERRCF_Msk  = 0x4  // Bit mask of PERRCF field.
	SPDIFRX_IFCR_PERRCF      = 0x4  // Bit PERRCF.
	SPDIFRX_IFCR_OVRCF_Pos   = 0x3  // Position of OVRCF field.
	SPDIFRX_IFCR_OVRCF_Msk   = 0x8  // Bit mask of OVRCF field.
	SPDIFRX_IFCR_OVRCF       = 0x8  // Bit OVRCF.
	SPDIFRX_IFCR_SBDCF_Pos   = 0x4  // Position of SBDCF field.
	SPDIFRX_IFCR_SBDCF_Msk   = 0x10 // Bit mask of SBDCF field.
	SPDIFRX_IFCR_SBDCF       = 0x10 // Bit SBDCF.
	SPDIFRX_IFCR_SYNCDCF_Pos = 0x5  // Position of SYNCDCF field.
	SPDIFRX_IFCR_SYNCDCF_Msk = 0x20 // Bit mask of SYNCDCF field.
	SPDIFRX_IFCR_SYNCDCF     = 0x20 // Bit SYNCDCF.

	// DR_00: Data input register
	SPDIFRX_DR_00_DR_Pos = 0x0        // Position of DR field.
	SPDIFRX_DR_00_DR_Msk = 0xffffff   // Bit mask of DR field.
	SPDIFRX_DR_00_PE_Pos = 0x18       // Position of PE field.
	SPDIFRX_DR_00_PE_Msk = 0x1000000  // Bit mask of PE field.
	SPDIFRX_DR_00_PE     = 0x1000000  // Bit PE.
	SPDIFRX_DR_00_V_Pos  = 0x19       // Position of V field.
	SPDIFRX_DR_00_V_Msk  = 0x2000000  // Bit mask of V field.
	SPDIFRX_DR_00_V      = 0x2000000  // Bit V.
	SPDIFRX_DR_00_U_Pos  = 0x1a       // Position of U field.
	SPDIFRX_DR_00_U_Msk  = 0x4000000  // Bit mask of U field.
	SPDIFRX_DR_00_U      = 0x4000000  // Bit U.
	SPDIFRX_DR_00_C_Pos  = 0x1b       // Position of C field.
	SPDIFRX_DR_00_C_Msk  = 0x8000000  // Bit mask of C field.
	SPDIFRX_DR_00_C      = 0x8000000  // Bit C.
	SPDIFRX_DR_00_PT_Pos = 0x1c       // Position of PT field.
	SPDIFRX_DR_00_PT_Msk = 0x30000000 // Bit mask of PT field.

	// DR_01: Data input register
	SPDIFRX_DR_01_PE_Pos = 0x0        // Position of PE field.
	SPDIFRX_DR_01_PE_Msk = 0x1        // Bit mask of PE field.
	SPDIFRX_DR_01_PE     = 0x1        // Bit PE.
	SPDIFRX_DR_01_V_Pos  = 0x1        // Position of V field.
	SPDIFRX_DR_01_V_Msk  = 0x2        // Bit mask of V field.
	SPDIFRX_DR_01_V      = 0x2        // Bit V.
	SPDIFRX_DR_01_U_Pos  = 0x2        // Position of U field.
	SPDIFRX_DR_01_U_Msk  = 0x4        // Bit mask of U field.
	SPDIFRX_DR_01_U      = 0x4        // Bit U.
	SPDIFRX_DR_01_C_Pos  = 0x3        // Position of C field.
	SPDIFRX_DR_01_C_Msk  = 0x8        // Bit mask of C field.
	SPDIFRX_DR_01_C      = 0x8        // Bit C.
	SPDIFRX_DR_01_PT_Pos = 0x4        // Position of PT field.
	SPDIFRX_DR_01_PT_Msk = 0x30       // Bit mask of PT field.
	SPDIFRX_DR_01_DR_Pos = 0x8        // Position of DR field.
	SPDIFRX_DR_01_DR_Msk = 0xffffff00 // Bit mask of DR field.

	// DR_10: Data input register
	SPDIFRX_DR_10_DRNL1_Pos = 0x0        // Position of DRNL1 field.
	SPDIFRX_DR_10_DRNL1_Msk = 0xffff     // Bit mask of DRNL1 field.
	SPDIFRX_DR_10_DRNL2_Pos = 0x10       // Position of DRNL2 field.
	SPDIFRX_DR_10_DRNL2_Msk = 0xffff0000 // Bit mask of DRNL2 field.

	// CSR: Channel Status register
	SPDIFRX_CSR_USR_Pos = 0x0       // Position of USR field.
	SPDIFRX_CSR_USR_Msk = 0xffff    // Bit mask of USR field.
	SPDIFRX_CSR_CS_Pos  = 0x10      // Position of CS field.
	SPDIFRX_CSR_CS_Msk  = 0xff0000  // Bit mask of CS field.
	SPDIFRX_CSR_SOB_Pos = 0x18      // Position of SOB field.
	SPDIFRX_CSR_SOB_Msk = 0x1000000 // Bit mask of SOB field.
	SPDIFRX_CSR_SOB     = 0x1000000 // Bit SOB.

	// DIR: Debug Information register
	SPDIFRX_DIR_THI_Pos = 0x0        // Position of THI field.
	SPDIFRX_DIR_THI_Msk = 0x1fff     // Bit mask of THI field.
	SPDIFRX_DIR_TLO_Pos = 0x10       // Position of TLO field.
	SPDIFRX_DIR_TLO_Msk = 0x1fff0000 // Bit mask of TLO field.

	// VERR: SPDIFRX version register
	SPDIFRX_VERR_MINREV_Pos = 0x0  // Position of MINREV field.
	SPDIFRX_VERR_MINREV_Msk = 0xf  // Bit mask of MINREV field.
	SPDIFRX_VERR_MAJREV_Pos = 0x4  // Position of MAJREV field.
	SPDIFRX_VERR_MAJREV_Msk = 0xf0 // Bit mask of MAJREV field.

	// IDR: SPDIFRX identification           register
	SPDIFRX_IDR_ID_Pos = 0x0        // Position of ID field.
	SPDIFRX_IDR_ID_Msk = 0xffffffff // Bit mask of ID field.

	// SIDR: SPDIFRX size identification           register
	SPDIFRX_SIDR_SID_Pos = 0x0        // Position of SID field.
	SPDIFRX_SIDR_SID_Msk = 0xffffffff // Bit mask of SID field.
)

// Bitfields for ADC3: Analog to Digital Converter
const (
	// ISR: ADC interrupt and status           register
	ADC_ISR_JQOVF_Pos = 0xa   // Position of JQOVF field.
	ADC_ISR_JQOVF_Msk = 0x400 // Bit mask of JQOVF field.
	ADC_ISR_JQOVF     = 0x400 // Bit JQOVF.
	ADC_ISR_AWD3_Pos  = 0x9   // Position of AWD3 field.
	ADC_ISR_AWD3_Msk  = 0x200 // Bit mask of AWD3 field.
	ADC_ISR_AWD3      = 0x200 // Bit AWD3.
	ADC_ISR_AWD2_Pos  = 0x8   // Position of AWD2 field.
	ADC_ISR_AWD2_Msk  = 0x100 // Bit mask of AWD2 field.
	ADC_ISR_AWD2      = 0x100 // Bit AWD2.
	ADC_ISR_AWD1_Pos  = 0x7   // Position of AWD1 field.
	ADC_ISR_AWD1_Msk  = 0x80  // Bit mask of AWD1 field.
	ADC_ISR_AWD1      = 0x80  // Bit AWD1.
	ADC_ISR_JEOS_Pos  = 0x6   // Position of JEOS field.
	ADC_ISR_JEOS_Msk  = 0x40  // Bit mask of JEOS field.
	ADC_ISR_JEOS      = 0x40  // Bit JEOS.
	ADC_ISR_JEOC_Pos  = 0x5   // Position of JEOC field.
	ADC_ISR_JEOC_Msk  = 0x20  // Bit mask of JEOC field.
	ADC_ISR_JEOC      = 0x20  // Bit JEOC.
	ADC_ISR_OVR_Pos   = 0x4   // Position of OVR field.
	ADC_ISR_OVR_Msk   = 0x10  // Bit mask of OVR field.
	ADC_ISR_OVR       = 0x10  // Bit OVR.
	ADC_ISR_EOS_Pos   = 0x3   // Position of EOS field.
	ADC_ISR_EOS_Msk   = 0x8   // Bit mask of EOS field.
	ADC_ISR_EOS       = 0x8   // Bit EOS.
	ADC_ISR_EOC_Pos   = 0x2   // Position of EOC field.
	ADC_ISR_EOC_Msk   = 0x4   // Bit mask of EOC field.
	ADC_ISR_EOC       = 0x4   // Bit EOC.
	ADC_ISR_EOSMP_Pos = 0x1   // Position of EOSMP field.
	ADC_ISR_EOSMP_Msk = 0x2   // Bit mask of EOSMP field.
	ADC_ISR_EOSMP     = 0x2   // Bit EOSMP.
	ADC_ISR_ADRDY_Pos = 0x0   // Position of ADRDY field.
	ADC_ISR_ADRDY_Msk = 0x1   // Bit mask of ADRDY field.
	ADC_ISR_ADRDY     = 0x1   // Bit ADRDY.

	// IER: ADC interrupt enable register
	ADC_IER_JQOVFIE_Pos = 0xa   // Position of JQOVFIE field.
	ADC_IER_JQOVFIE_Msk = 0x400 // Bit mask of JQOVFIE field.
	ADC_IER_JQOVFIE     = 0x400 // Bit JQOVFIE.
	ADC_IER_AWD3IE_Pos  = 0x9   // Position of AWD3IE field.
	ADC_IER_AWD3IE_Msk  = 0x200 // Bit mask of AWD3IE field.
	ADC_IER_AWD3IE      = 0x200 // Bit AWD3IE.
	ADC_IER_AWD2IE_Pos  = 0x8   // Position of AWD2IE field.
	ADC_IER_AWD2IE_Msk  = 0x100 // Bit mask of AWD2IE field.
	ADC_IER_AWD2IE      = 0x100 // Bit AWD2IE.
	ADC_IER_AWD1IE_Pos  = 0x7   // Position of AWD1IE field.
	ADC_IER_AWD1IE_Msk  = 0x80  // Bit mask of AWD1IE field.
	ADC_IER_AWD1IE      = 0x80  // Bit AWD1IE.
	ADC_IER_JEOSIE_Pos  = 0x6   // Position of JEOSIE field.
	ADC_IER_JEOSIE_Msk  = 0x40  // Bit mask of JEOSIE field.
	ADC_IER_JEOSIE      = 0x40  // Bit JEOSIE.
	ADC_IER_JEOCIE_Pos  = 0x5   // Position of JEOCIE field.
	ADC_IER_JEOCIE_Msk  = 0x20  // Bit mask of JEOCIE field.
	ADC_IER_JEOCIE      = 0x20  // Bit JEOCIE.
	ADC_IER_OVRIE_Pos   = 0x4   // Position of OVRIE field.
	ADC_IER_OVRIE_Msk   = 0x10  // Bit mask of OVRIE field.
	ADC_IER_OVRIE       = 0x10  // Bit OVRIE.
	ADC_IER_EOSIE_Pos   = 0x3   // Position of EOSIE field.
	ADC_IER_EOSIE_Msk   = 0x8   // Bit mask of EOSIE field.
	ADC_IER_EOSIE       = 0x8   // Bit EOSIE.
	ADC_IER_EOCIE_Pos   = 0x2   // Position of EOCIE field.
	ADC_IER_EOCIE_Msk   = 0x4   // Bit mask of EOCIE field.
	ADC_IER_EOCIE       = 0x4   // Bit EOCIE.
	ADC_IER_EOSMPIE_Pos = 0x1   // Position of EOSMPIE field.
	ADC_IER_EOSMPIE_Msk = 0x2   // Bit mask of EOSMPIE field.
	ADC_IER_EOSMPIE     = 0x2   // Bit EOSMPIE.
	ADC_IER_ADRDYIE_Pos = 0x0   // Position of ADRDYIE field.
	ADC_IER_ADRDYIE_Msk = 0x1   // Bit mask of ADRDYIE field.
	ADC_IER_ADRDYIE     = 0x1   // Bit ADRDYIE.

	// CR: ADC control register
	ADC_CR_ADCAL_Pos       = 0x1f       // Position of ADCAL field.
	ADC_CR_ADCAL_Msk       = 0x80000000 // Bit mask of ADCAL field.
	ADC_CR_ADCAL           = 0x80000000 // Bit ADCAL.
	ADC_CR_ADCALDIF_Pos    = 0x1e       // Position of ADCALDIF field.
	ADC_CR_ADCALDIF_Msk    = 0x40000000 // Bit mask of ADCALDIF field.
	ADC_CR_ADCALDIF        = 0x40000000 // Bit ADCALDIF.
	ADC_CR_DEEPPWD_Pos     = 0x1d       // Position of DEEPPWD field.
	ADC_CR_DEEPPWD_Msk     = 0x20000000 // Bit mask of DEEPPWD field.
	ADC_CR_DEEPPWD         = 0x20000000 // Bit DEEPPWD.
	ADC_CR_ADVREGEN_Pos    = 0x1c       // Position of ADVREGEN field.
	ADC_CR_ADVREGEN_Msk    = 0x10000000 // Bit mask of ADVREGEN field.
	ADC_CR_ADVREGEN        = 0x10000000 // Bit ADVREGEN.
	ADC_CR_LINCALRDYW6_Pos = 0x1b       // Position of LINCALRDYW6 field.
	ADC_CR_LINCALRDYW6_Msk = 0x8000000  // Bit mask of LINCALRDYW6 field.
	ADC_CR_LINCALRDYW6     = 0x8000000  // Bit LINCALRDYW6.
	ADC_CR_LINCALRDYW5_Pos = 0x1a       // Position of LINCALRDYW5 field.
	ADC_CR_LINCALRDYW5_Msk = 0x4000000  // Bit mask of LINCALRDYW5 field.
	ADC_CR_LINCALRDYW5     = 0x4000000  // Bit LINCALRDYW5.
	ADC_CR_LINCALRDYW4_Pos = 0x19       // Position of LINCALRDYW4 field.
	ADC_CR_LINCALRDYW4_Msk = 0x2000000  // Bit mask of LINCALRDYW4 field.
	ADC_CR_LINCALRDYW4     = 0x2000000  // Bit LINCALRDYW4.
	ADC_CR_LINCALRDYW3_Pos = 0x18       // Position of LINCALRDYW3 field.
	ADC_CR_LINCALRDYW3_Msk = 0x1000000  // Bit mask of LINCALRDYW3 field.
	ADC_CR_LINCALRDYW3     = 0x1000000  // Bit LINCALRDYW3.
	ADC_CR_LINCALRDYW2_Pos = 0x17       // Position of LINCALRDYW2 field.
	ADC_CR_LINCALRDYW2_Msk = 0x800000   // Bit mask of LINCALRDYW2 field.
	ADC_CR_LINCALRDYW2     = 0x800000   // Bit LINCALRDYW2.
	ADC_CR_LINCALRDYW1_Pos = 0x16       // Position of LINCALRDYW1 field.
	ADC_CR_LINCALRDYW1_Msk = 0x400000   // Bit mask of LINCALRDYW1 field.
	ADC_CR_LINCALRDYW1     = 0x400000   // Bit LINCALRDYW1.
	ADC_CR_ADCALLIN_Pos    = 0x10       // Position of ADCALLIN field.
	ADC_CR_ADCALLIN_Msk    = 0x10000    // Bit mask of ADCALLIN field.
	ADC_CR_ADCALLIN        = 0x10000    // Bit ADCALLIN.
	ADC_CR_BOOST_Pos       = 0x8        // Position of BOOST field.
	ADC_CR_BOOST_Msk       = 0x100      // Bit mask of BOOST field.
	ADC_CR_BOOST           = 0x100      // Bit BOOST.
	ADC_CR_JADSTP_Pos      = 0x5        // Position of JADSTP field.
	ADC_CR_JADSTP_Msk      = 0x20       // Bit mask of JADSTP field.
	ADC_CR_JADSTP          = 0x20       // Bit JADSTP.
	ADC_CR_ADSTP_Pos       = 0x4        // Position of ADSTP field.
	ADC_CR_ADSTP_Msk       = 0x10       // Bit mask of ADSTP field.
	ADC_CR_ADSTP           = 0x10       // Bit ADSTP.
	ADC_CR_JADSTART_Pos    = 0x3        // Position of JADSTART field.
	ADC_CR_JADSTART_Msk    = 0x8        // Bit mask of JADSTART field.
	ADC_CR_JADSTART        = 0x8        // Bit JADSTART.
	ADC_CR_ADSTART_Pos     = 0x2        // Position of ADSTART field.
	ADC_CR_ADSTART_Msk     = 0x4        // Bit mask of ADSTART field.
	ADC_CR_ADSTART         = 0x4        // Bit ADSTART.
	ADC_CR_ADDIS_Pos       = 0x1        // Position of ADDIS field.
	ADC_CR_ADDIS_Msk       = 0x2        // Bit mask of ADDIS field.
	ADC_CR_ADDIS           = 0x2        // Bit ADDIS.
	ADC_CR_ADEN_Pos        = 0x0        // Position of ADEN field.
	ADC_CR_ADEN_Msk        = 0x1        // Bit mask of ADEN field.
	ADC_CR_ADEN            = 0x1        // Bit ADEN.

	// CFGR: ADC configuration register 1
	ADC_CFGR_JQDIS_Pos    = 0x1f       // Position of JQDIS field.
	ADC_CFGR_JQDIS_Msk    = 0x80000000 // Bit mask of JQDIS field.
	ADC_CFGR_JQDIS        = 0x80000000 // Bit JQDIS.
	ADC_CFGR_AWDCH1CH_Pos = 0x1a       // Position of AWDCH1CH field.
	ADC_CFGR_AWDCH1CH_Msk = 0x7c000000 // Bit mask of AWDCH1CH field.
	ADC_CFGR_JAUTO_Pos    = 0x19       // Position of JAUTO field.
	ADC_CFGR_JAUTO_Msk    = 0x2000000  // Bit mask of JAUTO field.
	ADC_CFGR_JAUTO        = 0x2000000  // Bit JAUTO.
	ADC_CFGR_JAWD1EN_Pos  = 0x18       // Position of JAWD1EN field.
	ADC_CFGR_JAWD1EN_Msk  = 0x1000000  // Bit mask of JAWD1EN field.
	ADC_CFGR_JAWD1EN      = 0x1000000  // Bit JAWD1EN.
	ADC_CFGR_AWD1EN_Pos   = 0x17       // Position of AWD1EN field.
	ADC_CFGR_AWD1EN_Msk   = 0x800000   // Bit mask of AWD1EN field.
	ADC_CFGR_AWD1EN       = 0x800000   // Bit AWD1EN.
	ADC_CFGR_AWD1SGL_Pos  = 0x16       // Position of AWD1SGL field.
	ADC_CFGR_AWD1SGL_Msk  = 0x400000   // Bit mask of AWD1SGL field.
	ADC_CFGR_AWD1SGL      = 0x400000   // Bit AWD1SGL.
	ADC_CFGR_JQM_Pos      = 0x15       // Position of JQM field.
	ADC_CFGR_JQM_Msk      = 0x200000   // Bit mask of JQM field.
	ADC_CFGR_JQM          = 0x200000   // Bit JQM.
	ADC_CFGR_JDISCEN_Pos  = 0x14       // Position of JDISCEN field.
	ADC_CFGR_JDISCEN_Msk  = 0x100000   // Bit mask of JDISCEN field.
	ADC_CFGR_JDISCEN      = 0x100000   // Bit JDISCEN.
	ADC_CFGR_DISCNUM_Pos  = 0x11       // Position of DISCNUM field.
	ADC_CFGR_DISCNUM_Msk  = 0xe0000    // Bit mask of DISCNUM field.
	ADC_CFGR_DISCEN_Pos   = 0x10       // Position of DISCEN field.
	ADC_CFGR_DISCEN_Msk   = 0x10000    // Bit mask of DISCEN field.
	ADC_CFGR_DISCEN       = 0x10000    // Bit DISCEN.
	ADC_CFGR_AUTDLY_Pos   = 0xe        // Position of AUTDLY field.
	ADC_CFGR_AUTDLY_Msk   = 0x4000     // Bit mask of AUTDLY field.
	ADC_CFGR_AUTDLY       = 0x4000     // Bit AUTDLY.
	ADC_CFGR_CONT_Pos     = 0xd        // Position of CONT field.
	ADC_CFGR_CONT_Msk     = 0x2000     // Bit mask of CONT field.
	ADC_CFGR_CONT         = 0x2000     // Bit CONT.
	ADC_CFGR_OVRMOD_Pos   = 0xc        // Position of OVRMOD field.
	ADC_CFGR_OVRMOD_Msk   = 0x1000     // Bit mask of OVRMOD field.
	ADC_CFGR_OVRMOD       = 0x1000     // Bit OVRMOD.
	ADC_CFGR_EXTEN_Pos    = 0xa        // Position of EXTEN field.
	ADC_CFGR_EXTEN_Msk    = 0xc00      // Bit mask of EXTEN field.
	ADC_CFGR_EXTSEL_Pos   = 0x5        // Position of EXTSEL field.
	ADC_CFGR_EXTSEL_Msk   = 0x3e0      // Bit mask of EXTSEL field.
	ADC_CFGR_RES_Pos      = 0x2        // Position of RES field.
	ADC_CFGR_RES_Msk      = 0x1c       // Bit mask of RES field.
	ADC_CFGR_DMNGT_Pos    = 0x0        // Position of DMNGT field.
	ADC_CFGR_DMNGT_Msk    = 0x3        // Bit mask of DMNGT field.

	// CFGR2: ADC configuration register 2
	ADC_CFGR2_ROVSE_Pos   = 0x0        // Position of ROVSE field.
	ADC_CFGR2_ROVSE_Msk   = 0x1        // Bit mask of ROVSE field.
	ADC_CFGR2_ROVSE       = 0x1        // Bit ROVSE.
	ADC_CFGR2_JOVSE_Pos   = 0x1        // Position of JOVSE field.
	ADC_CFGR2_JOVSE_Msk   = 0x2        // Bit mask of JOVSE field.
	ADC_CFGR2_JOVSE       = 0x2        // Bit JOVSE.
	ADC_CFGR2_OVSS_Pos    = 0x5        // Position of OVSS field.
	ADC_CFGR2_OVSS_Msk    = 0x1e0      // Bit mask of OVSS field.
	ADC_CFGR2_TROVS_Pos   = 0x9        // Position of TROVS field.
	ADC_CFGR2_TROVS_Msk   = 0x200      // Bit mask of TROVS field.
	ADC_CFGR2_TROVS       = 0x200      // Bit TROVS.
	ADC_CFGR2_ROVSM_Pos   = 0xa        // Position of ROVSM field.
	ADC_CFGR2_ROVSM_Msk   = 0x400      // Bit mask of ROVSM field.
	ADC_CFGR2_ROVSM       = 0x400      // Bit ROVSM.
	ADC_CFGR2_RSHIFT1_Pos = 0xb        // Position of RSHIFT1 field.
	ADC_CFGR2_RSHIFT1_Msk = 0x800      // Bit mask of RSHIFT1 field.
	ADC_CFGR2_RSHIFT1     = 0x800      // Bit RSHIFT1.
	ADC_CFGR2_RSHIFT2_Pos = 0xc        // Position of RSHIFT2 field.
	ADC_CFGR2_RSHIFT2_Msk = 0x1000     // Bit mask of RSHIFT2 field.
	ADC_CFGR2_RSHIFT2     = 0x1000     // Bit RSHIFT2.
	ADC_CFGR2_RSHIFT3_Pos = 0xd        // Position of RSHIFT3 field.
	ADC_CFGR2_RSHIFT3_Msk = 0x2000     // Bit mask of RSHIFT3 field.
	ADC_CFGR2_RSHIFT3     = 0x2000     // Bit RSHIFT3.
	ADC_CFGR2_RSHIFT4_Pos = 0xe        // Position of RSHIFT4 field.
	ADC_CFGR2_RSHIFT4_Msk = 0x4000     // Bit mask of RSHIFT4 field.
	ADC_CFGR2_RSHIFT4     = 0x4000     // Bit RSHIFT4.
	ADC_CFGR2_OSR_Pos     = 0x10       // Position of OSR field.
	ADC_CFGR2_OSR_Msk     = 0x3ff0000  // Bit mask of OSR field.
	ADC_CFGR2_LSHIFT_Pos  = 0x1c       // Position of LSHIFT field.
	ADC_CFGR2_LSHIFT_Msk  = 0xf0000000 // Bit mask of LSHIFT field.

	// SMPR1: ADC sampling time register 1
	ADC_SMPR1_SMP9_Pos = 0x1b       // Position of SMP9 field.
	ADC_SMPR1_SMP9_Msk = 0x38000000 // Bit mask of SMP9 field.
	ADC_SMPR1_SMP8_Pos = 0x18       // Position of SMP8 field.
	ADC_SMPR1_SMP8_Msk = 0x7000000  // Bit mask of SMP8 field.
	ADC_SMPR1_SMP7_Pos = 0x15       // Position of SMP7 field.
	ADC_SMPR1_SMP7_Msk = 0xe00000   // Bit mask of SMP7 field.
	ADC_SMPR1_SMP6_Pos = 0x12       // Position of SMP6 field.
	ADC_SMPR1_SMP6_Msk = 0x1c0000   // Bit mask of SMP6 field.
	ADC_SMPR1_SMP5_Pos = 0xf        // Position of SMP5 field.
	ADC_SMPR1_SMP5_Msk = 0x38000    // Bit mask of SMP5 field.
	ADC_SMPR1_SMP4_Pos = 0xc        // Position of SMP4 field.
	ADC_SMPR1_SMP4_Msk = 0x7000     // Bit mask of SMP4 field.
	ADC_SMPR1_SMP3_Pos = 0x9        // Position of SMP3 field.
	ADC_SMPR1_SMP3_Msk = 0xe00      // Bit mask of SMP3 field.
	ADC_SMPR1_SMP2_Pos = 0x6        // Position of SMP2 field.
	ADC_SMPR1_SMP2_Msk = 0x1c0      // Bit mask of SMP2 field.
	ADC_SMPR1_SMP1_Pos = 0x3        // Position of SMP1 field.
	ADC_SMPR1_SMP1_Msk = 0x38       // Bit mask of SMP1 field.

	// SMPR2: ADC sampling time register 2
	ADC_SMPR2_SMP19_Pos = 0x1b       // Position of SMP19 field.
	ADC_SMPR2_SMP19_Msk = 0x38000000 // Bit mask of SMP19 field.
	ADC_SMPR2_SMP18_Pos = 0x18       // Position of SMP18 field.
	ADC_SMPR2_SMP18_Msk = 0x7000000  // Bit mask of SMP18 field.
	ADC_SMPR2_SMP17_Pos = 0x15       // Position of SMP17 field.
	ADC_SMPR2_SMP17_Msk = 0xe00000   // Bit mask of SMP17 field.
	ADC_SMPR2_SMP16_Pos = 0x12       // Position of SMP16 field.
	ADC_SMPR2_SMP16_Msk = 0x1c0000   // Bit mask of SMP16 field.
	ADC_SMPR2_SMP15_Pos = 0xf        // Position of SMP15 field.
	ADC_SMPR2_SMP15_Msk = 0x38000    // Bit mask of SMP15 field.
	ADC_SMPR2_SMP14_Pos = 0xc        // Position of SMP14 field.
	ADC_SMPR2_SMP14_Msk = 0x7000     // Bit mask of SMP14 field.
	ADC_SMPR2_SMP13_Pos = 0x9        // Position of SMP13 field.
	ADC_SMPR2_SMP13_Msk = 0xe00      // Bit mask of SMP13 field.
	ADC_SMPR2_SMP12_Pos = 0x6        // Position of SMP12 field.
	ADC_SMPR2_SMP12_Msk = 0x1c0      // Bit mask of SMP12 field.
	ADC_SMPR2_SMP11_Pos = 0x3        // Position of SMP11 field.
	ADC_SMPR2_SMP11_Msk = 0x38       // Bit mask of SMP11 field.
	ADC_SMPR2_SMP10_Pos = 0x0        // Position of SMP10 field.
	ADC_SMPR2_SMP10_Msk = 0x7        // Bit mask of SMP10 field.

	// PCSEL: ADC pre channel selection           register
	ADC_PCSEL_PCSEL_Pos = 0x0     // Position of PCSEL field.
	ADC_PCSEL_PCSEL_Msk = 0xfffff // Bit mask of PCSEL field.

	// LTR1: ADC analog watchdog 1 threshold           register
	ADC_LTR1_LTR1_Pos = 0x0       // Position of LTR1 field.
	ADC_LTR1_LTR1_Msk = 0x3ffffff // Bit mask of LTR1 field.

	// LHTR1: ADC analog watchdog 2 threshold           register
	ADC_LHTR1_LHTR1_Pos = 0x0       // Position of LHTR1 field.
	ADC_LHTR1_LHTR1_Msk = 0x3ffffff // Bit mask of LHTR1 field.

	// SQR1: ADC group regular sequencer ranks register           1
	ADC_SQR1_SQ4_Pos = 0x18       // Position of SQ4 field.
	ADC_SQR1_SQ4_Msk = 0x1f000000 // Bit mask of SQ4 field.
	ADC_SQR1_SQ3_Pos = 0x12       // Position of SQ3 field.
	ADC_SQR1_SQ3_Msk = 0x7c0000   // Bit mask of SQ3 field.
	ADC_SQR1_SQ2_Pos = 0xc        // Position of SQ2 field.
	ADC_SQR1_SQ2_Msk = 0x1f000    // Bit mask of SQ2 field.
	ADC_SQR1_SQ1_Pos = 0x6        // Position of SQ1 field.
	ADC_SQR1_SQ1_Msk = 0x7c0      // Bit mask of SQ1 field.
	ADC_SQR1_L3_Pos  = 0x0        // Position of L3 field.
	ADC_SQR1_L3_Msk  = 0xf        // Bit mask of L3 field.

	// SQR2: ADC group regular sequencer ranks register           2
	ADC_SQR2_SQ9_Pos = 0x18       // Position of SQ9 field.
	ADC_SQR2_SQ9_Msk = 0x1f000000 // Bit mask of SQ9 field.
	ADC_SQR2_SQ8_Pos = 0x12       // Position of SQ8 field.
	ADC_SQR2_SQ8_Msk = 0x7c0000   // Bit mask of SQ8 field.
	ADC_SQR2_SQ7_Pos = 0xc        // Position of SQ7 field.
	ADC_SQR2_SQ7_Msk = 0x1f000    // Bit mask of SQ7 field.
	ADC_SQR2_SQ6_Pos = 0x6        // Position of SQ6 field.
	ADC_SQR2_SQ6_Msk = 0x7c0      // Bit mask of SQ6 field.
	ADC_SQR2_SQ5_Pos = 0x0        // Position of SQ5 field.
	ADC_SQR2_SQ5_Msk = 0x1f       // Bit mask of SQ5 field.

	// SQR3: ADC group regular sequencer ranks register           3
	ADC_SQR3_SQ14_Pos = 0x18       // Position of SQ14 field.
	ADC_SQR3_SQ14_Msk = 0x1f000000 // Bit mask of SQ14 field.
	ADC_SQR3_SQ13_Pos = 0x12       // Position of SQ13 field.
	ADC_SQR3_SQ13_Msk = 0x7c0000   // Bit mask of SQ13 field.
	ADC_SQR3_SQ12_Pos = 0xc        // Position of SQ12 field.
	ADC_SQR3_SQ12_Msk = 0x1f000    // Bit mask of SQ12 field.
	ADC_SQR3_SQ11_Pos = 0x6        // Position of SQ11 field.
	ADC_SQR3_SQ11_Msk = 0x7c0      // Bit mask of SQ11 field.
	ADC_SQR3_SQ10_Pos = 0x0        // Position of SQ10 field.
	ADC_SQR3_SQ10_Msk = 0x1f       // Bit mask of SQ10 field.

	// SQR4: ADC group regular sequencer ranks register           4
	ADC_SQR4_SQ16_Pos = 0x6   // Position of SQ16 field.
	ADC_SQR4_SQ16_Msk = 0x7c0 // Bit mask of SQ16 field.
	ADC_SQR4_SQ15_Pos = 0x0   // Position of SQ15 field.
	ADC_SQR4_SQ15_Msk = 0x1f  // Bit mask of SQ15 field.

	// DR: ADC group regular conversion data           register
	ADC_DR_RDATA_Pos = 0x0    // Position of RDATA field.
	ADC_DR_RDATA_Msk = 0xffff // Bit mask of RDATA field.

	// JSQR: ADC group injected sequencer           register
	ADC_JSQR_JSQ4_Pos    = 0x1b       // Position of JSQ4 field.
	ADC_JSQR_JSQ4_Msk    = 0xf8000000 // Bit mask of JSQ4 field.
	ADC_JSQR_JSQ3_Pos    = 0x15       // Position of JSQ3 field.
	ADC_JSQR_JSQ3_Msk    = 0x3e00000  // Bit mask of JSQ3 field.
	ADC_JSQR_JSQ2_Pos    = 0xf        // Position of JSQ2 field.
	ADC_JSQR_JSQ2_Msk    = 0xf8000    // Bit mask of JSQ2 field.
	ADC_JSQR_JSQ1_Pos    = 0x9        // Position of JSQ1 field.
	ADC_JSQR_JSQ1_Msk    = 0x3e00     // Bit mask of JSQ1 field.
	ADC_JSQR_JEXTEN_Pos  = 0x7        // Position of JEXTEN field.
	ADC_JSQR_JEXTEN_Msk  = 0x180      // Bit mask of JEXTEN field.
	ADC_JSQR_JEXTSEL_Pos = 0x2        // Position of JEXTSEL field.
	ADC_JSQR_JEXTSEL_Msk = 0x7c       // Bit mask of JEXTSEL field.
	ADC_JSQR_JL_Pos      = 0x0        // Position of JL field.
	ADC_JSQR_JL_Msk      = 0x3        // Bit mask of JL field.

	// OFR1: ADC offset number 1 register
	ADC_OFR1_SSATE_Pos      = 0x1f       // Position of SSATE field.
	ADC_OFR1_SSATE_Msk      = 0x80000000 // Bit mask of SSATE field.
	ADC_OFR1_SSATE          = 0x80000000 // Bit SSATE.
	ADC_OFR1_OFFSET1_CH_Pos = 0x1a       // Position of OFFSET1_CH field.
	ADC_OFR1_OFFSET1_CH_Msk = 0x7c000000 // Bit mask of OFFSET1_CH field.
	ADC_OFR1_OFFSET1_Pos    = 0x0        // Position of OFFSET1 field.
	ADC_OFR1_OFFSET1_Msk    = 0x3ffffff  // Bit mask of OFFSET1 field.

	// OFR2: ADC offset number 2 register
	ADC_OFR2_SSATE_Pos      = 0x1f       // Position of SSATE field.
	ADC_OFR2_SSATE_Msk      = 0x80000000 // Bit mask of SSATE field.
	ADC_OFR2_SSATE          = 0x80000000 // Bit SSATE.
	ADC_OFR2_OFFSET1_CH_Pos = 0x1a       // Position of OFFSET1_CH field.
	ADC_OFR2_OFFSET1_CH_Msk = 0x7c000000 // Bit mask of OFFSET1_CH field.
	ADC_OFR2_OFFSET1_Pos    = 0x0        // Position of OFFSET1 field.
	ADC_OFR2_OFFSET1_Msk    = 0x3ffffff  // Bit mask of OFFSET1 field.

	// OFR3: ADC offset number 3 register
	ADC_OFR3_SSATE_Pos      = 0x1f       // Position of SSATE field.
	ADC_OFR3_SSATE_Msk      = 0x80000000 // Bit mask of SSATE field.
	ADC_OFR3_SSATE          = 0x80000000 // Bit SSATE.
	ADC_OFR3_OFFSET1_CH_Pos = 0x1a       // Position of OFFSET1_CH field.
	ADC_OFR3_OFFSET1_CH_Msk = 0x7c000000 // Bit mask of OFFSET1_CH field.
	ADC_OFR3_OFFSET1_Pos    = 0x0        // Position of OFFSET1 field.
	ADC_OFR3_OFFSET1_Msk    = 0x3ffffff  // Bit mask of OFFSET1 field.

	// OFR4: ADC offset number 4 register
	ADC_OFR4_SSATE_Pos      = 0x1f       // Position of SSATE field.
	ADC_OFR4_SSATE_Msk      = 0x80000000 // Bit mask of SSATE field.
	ADC_OFR4_SSATE          = 0x80000000 // Bit SSATE.
	ADC_OFR4_OFFSET1_CH_Pos = 0x1a       // Position of OFFSET1_CH field.
	ADC_OFR4_OFFSET1_CH_Msk = 0x7c000000 // Bit mask of OFFSET1_CH field.
	ADC_OFR4_OFFSET1_Pos    = 0x0        // Position of OFFSET1 field.
	ADC_OFR4_OFFSET1_Msk    = 0x3ffffff  // Bit mask of OFFSET1 field.

	// JDR1: ADC group injected sequencer rank 1           register
	ADC_JDR1_JDATA1_Pos = 0x0        // Position of JDATA1 field.
	ADC_JDR1_JDATA1_Msk = 0xffffffff // Bit mask of JDATA1 field.

	// JDR2: ADC group injected sequencer rank 2           register
	ADC_JDR2_JDATA2_Pos = 0x0        // Position of JDATA2 field.
	ADC_JDR2_JDATA2_Msk = 0xffffffff // Bit mask of JDATA2 field.

	// JDR3: ADC group injected sequencer rank 3           register
	ADC_JDR3_JDATA3_Pos = 0x0        // Position of JDATA3 field.
	ADC_JDR3_JDATA3_Msk = 0xffffffff // Bit mask of JDATA3 field.

	// JDR4: ADC group injected sequencer rank 4           register
	ADC_JDR4_JDATA4_Pos = 0x0        // Position of JDATA4 field.
	ADC_JDR4_JDATA4_Msk = 0xffffffff // Bit mask of JDATA4 field.

	// AWD2CR: ADC analog watchdog 2 configuration           register
	ADC_AWD2CR_AWD2CH_Pos = 0x0     // Position of AWD2CH field.
	ADC_AWD2CR_AWD2CH_Msk = 0xfffff // Bit mask of AWD2CH field.

	// AWD3CR: ADC analog watchdog 3 configuration           register
	ADC_AWD3CR_AWD3CH_Pos = 0x1      // Position of AWD3CH field.
	ADC_AWD3CR_AWD3CH_Msk = 0x1ffffe // Bit mask of AWD3CH field.

	// LTR2: ADC watchdog lower threshold register           2
	ADC_LTR2_LTR2_Pos = 0x0       // Position of LTR2 field.
	ADC_LTR2_LTR2_Msk = 0x3ffffff // Bit mask of LTR2 field.

	// HTR2: ADC watchdog higher threshold register           2
	ADC_HTR2_HTR2_Pos = 0x0       // Position of HTR2 field.
	ADC_HTR2_HTR2_Msk = 0x3ffffff // Bit mask of HTR2 field.

	// LTR3: ADC watchdog lower threshold register           3
	ADC_LTR3_LTR3_Pos = 0x0       // Position of LTR3 field.
	ADC_LTR3_LTR3_Msk = 0x3ffffff // Bit mask of LTR3 field.

	// HTR3: ADC watchdog higher threshold register           3
	ADC_HTR3_HTR3_Pos = 0x0       // Position of HTR3 field.
	ADC_HTR3_HTR3_Msk = 0x3ffffff // Bit mask of HTR3 field.

	// DIFSEL: ADC channel differential or single-ended           mode selection register
	ADC_DIFSEL_DIFSEL_Pos = 0x0     // Position of DIFSEL field.
	ADC_DIFSEL_DIFSEL_Msk = 0xfffff // Bit mask of DIFSEL field.

	// CALFACT: ADC calibration factors           register
	ADC_CALFACT_CALFACT_D_Pos = 0x10      // Position of CALFACT_D field.
	ADC_CALFACT_CALFACT_D_Msk = 0x7ff0000 // Bit mask of CALFACT_D field.
	ADC_CALFACT_CALFACT_S_Pos = 0x0       // Position of CALFACT_S field.
	ADC_CALFACT_CALFACT_S_Msk = 0x7ff     // Bit mask of CALFACT_S field.

	// CALFACT2: ADC Calibration Factor register           2
	ADC_CALFACT2_LINCALFACT_Pos = 0x0        // Position of LINCALFACT field.
	ADC_CALFACT2_LINCALFACT_Msk = 0x3fffffff // Bit mask of LINCALFACT field.
)

// Bitfields for CRC: Cryptographic processor
const (
	// DR: Data register
	CRC_DR_DR_Pos = 0x0        // Position of DR field.
	CRC_DR_DR_Msk = 0xffffffff // Bit mask of DR field.

	// IDR: Independent Data register
	CRC_IDR_IDR_Pos = 0x0        // Position of IDR field.
	CRC_IDR_IDR_Msk = 0xffffffff // Bit mask of IDR field.

	// CR: Control register
	CRC_CR_RESET_Pos    = 0x0  // Position of RESET field.
	CRC_CR_RESET_Msk    = 0x1  // Bit mask of RESET field.
	CRC_CR_RESET        = 0x1  // Bit RESET.
	CRC_CR_POLYSIZE_Pos = 0x3  // Position of POLYSIZE field.
	CRC_CR_POLYSIZE_Msk = 0x18 // Bit mask of POLYSIZE field.
	CRC_CR_REV_IN_Pos   = 0x5  // Position of REV_IN field.
	CRC_CR_REV_IN_Msk   = 0x60 // Bit mask of REV_IN field.
	CRC_CR_REV_OUT_Pos  = 0x7  // Position of REV_OUT field.
	CRC_CR_REV_OUT_Msk  = 0x80 // Bit mask of REV_OUT field.
	CRC_CR_REV_OUT      = 0x80 // Bit REV_OUT.

	// INIT: Initial CRC value
	CRC_INIT_CRC_INIT_Pos = 0x0        // Position of CRC_INIT field.
	CRC_INIT_CRC_INIT_Msk = 0xffffffff // Bit mask of CRC_INIT field.

	// POL: CRC polynomial
	CRC_POL_POL_Pos = 0x0        // Position of POL field.
	CRC_POL_POL_Msk = 0xffffffff // Bit mask of POL field.
)

// Bitfields for RCC: Reset and clock control
const (
	// CR: clock control register
	RCC_CR_HSION_Pos    = 0x0        // Position of HSION field.
	RCC_CR_HSION_Msk    = 0x1        // Bit mask of HSION field.
	RCC_CR_HSION        = 0x1        // Bit HSION.
	RCC_CR_HSIKERON_Pos = 0x1        // Position of HSIKERON field.
	RCC_CR_HSIKERON_Msk = 0x2        // Bit mask of HSIKERON field.
	RCC_CR_HSIKERON     = 0x2        // Bit HSIKERON.
	RCC_CR_HSIRDY_Pos   = 0x2        // Position of HSIRDY field.
	RCC_CR_HSIRDY_Msk   = 0x4        // Bit mask of HSIRDY field.
	RCC_CR_HSIRDY       = 0x4        // Bit HSIRDY.
	RCC_CR_HSIDIV_Pos   = 0x3        // Position of HSIDIV field.
	RCC_CR_HSIDIV_Msk   = 0x18       // Bit mask of HSIDIV field.
	RCC_CR_HSIDIVF_Pos  = 0x5        // Position of HSIDIVF field.
	RCC_CR_HSIDIVF_Msk  = 0x20       // Bit mask of HSIDIVF field.
	RCC_CR_HSIDIVF      = 0x20       // Bit HSIDIVF.
	RCC_CR_CSION_Pos    = 0x7        // Position of CSION field.
	RCC_CR_CSION_Msk    = 0x80       // Bit mask of CSION field.
	RCC_CR_CSION        = 0x80       // Bit CSION.
	RCC_CR_CSIRDY_Pos   = 0x8        // Position of CSIRDY field.
	RCC_CR_CSIRDY_Msk   = 0x100      // Bit mask of CSIRDY field.
	RCC_CR_CSIRDY       = 0x100      // Bit CSIRDY.
	RCC_CR_CSIKERON_Pos = 0x9        // Position of CSIKERON field.
	RCC_CR_CSIKERON_Msk = 0x200      // Bit mask of CSIKERON field.
	RCC_CR_CSIKERON     = 0x200      // Bit CSIKERON.
	RCC_CR_RC48ON_Pos   = 0xc        // Position of RC48ON field.
	RCC_CR_RC48ON_Msk   = 0x1000     // Bit mask of RC48ON field.
	RCC_CR_RC48ON       = 0x1000     // Bit RC48ON.
	RCC_CR_RC48RDY_Pos  = 0xd        // Position of RC48RDY field.
	RCC_CR_RC48RDY_Msk  = 0x2000     // Bit mask of RC48RDY field.
	RCC_CR_RC48RDY      = 0x2000     // Bit RC48RDY.
	RCC_CR_D1CKRDY_Pos  = 0xe        // Position of D1CKRDY field.
	RCC_CR_D1CKRDY_Msk  = 0x4000     // Bit mask of D1CKRDY field.
	RCC_CR_D1CKRDY      = 0x4000     // Bit D1CKRDY.
	RCC_CR_D2CKRDY_Pos  = 0xf        // Position of D2CKRDY field.
	RCC_CR_D2CKRDY_Msk  = 0x8000     // Bit mask of D2CKRDY field.
	RCC_CR_D2CKRDY      = 0x8000     // Bit D2CKRDY.
	RCC_CR_HSEON_Pos    = 0x10       // Position of HSEON field.
	RCC_CR_HSEON_Msk    = 0x10000    // Bit mask of HSEON field.
	RCC_CR_HSEON        = 0x10000    // Bit HSEON.
	RCC_CR_HSERDY_Pos   = 0x11       // Position of HSERDY field.
	RCC_CR_HSERDY_Msk   = 0x20000    // Bit mask of HSERDY field.
	RCC_CR_HSERDY       = 0x20000    // Bit HSERDY.
	RCC_CR_HSEBYP_Pos   = 0x12       // Position of HSEBYP field.
	RCC_CR_HSEBYP_Msk   = 0x40000    // Bit mask of HSEBYP field.
	RCC_CR_HSEBYP       = 0x40000    // Bit HSEBYP.
	RCC_CR_HSECSSON_Pos = 0x13       // Position of HSECSSON field.
	RCC_CR_HSECSSON_Msk = 0x80000    // Bit mask of HSECSSON field.
	RCC_CR_HSECSSON     = 0x80000    // Bit HSECSSON.
	RCC_CR_PLL1ON_Pos   = 0x18       // Position of PLL1ON field.
	RCC_CR_PLL1ON_Msk   = 0x1000000  // Bit mask of PLL1ON field.
	RCC_CR_PLL1ON       = 0x1000000  // Bit PLL1ON.
	RCC_CR_PLL1RDY_Pos  = 0x19       // Position of PLL1RDY field.
	RCC_CR_PLL1RDY_Msk  = 0x2000000  // Bit mask of PLL1RDY field.
	RCC_CR_PLL1RDY      = 0x2000000  // Bit PLL1RDY.
	RCC_CR_PLL2ON_Pos   = 0x1a       // Position of PLL2ON field.
	RCC_CR_PLL2ON_Msk   = 0x4000000  // Bit mask of PLL2ON field.
	RCC_CR_PLL2ON       = 0x4000000  // Bit PLL2ON.
	RCC_CR_PLL2RDY_Pos  = 0x1b       // Position of PLL2RDY field.
	RCC_CR_PLL2RDY_Msk  = 0x8000000  // Bit mask of PLL2RDY field.
	RCC_CR_PLL2RDY      = 0x8000000  // Bit PLL2RDY.
	RCC_CR_PLL3ON_Pos   = 0x1c       // Position of PLL3ON field.
	RCC_CR_PLL3ON_Msk   = 0x10000000 // Bit mask of PLL3ON field.
	RCC_CR_PLL3ON       = 0x10000000 // Bit PLL3ON.
	RCC_CR_PLL3RDY_Pos  = 0x1d       // Position of PLL3RDY field.
	RCC_CR_PLL3RDY_Msk  = 0x20000000 // Bit mask of PLL3RDY field.
	RCC_CR_PLL3RDY      = 0x20000000 // Bit PLL3RDY.

	// ICSCR: RCC Internal Clock Source Calibration           Register
	RCC_ICSCR_HSICAL_Pos  = 0x0        // Position of HSICAL field.
	RCC_ICSCR_HSICAL_Msk  = 0xfff      // Bit mask of HSICAL field.
	RCC_ICSCR_HSITRIM_Pos = 0xc        // Position of HSITRIM field.
	RCC_ICSCR_HSITRIM_Msk = 0x3f000    // Bit mask of HSITRIM field.
	RCC_ICSCR_CSICAL_Pos  = 0x12       // Position of CSICAL field.
	RCC_ICSCR_CSICAL_Msk  = 0x3fc0000  // Bit mask of CSICAL field.
	RCC_ICSCR_CSITRIM_Pos = 0x1a       // Position of CSITRIM field.
	RCC_ICSCR_CSITRIM_Msk = 0x7c000000 // Bit mask of CSITRIM field.

	// CRRCR: RCC Clock Recovery RC Register
	RCC_CRRCR_RC48CAL_Pos = 0x0   // Position of RC48CAL field.
	RCC_CRRCR_RC48CAL_Msk = 0x3ff // Bit mask of RC48CAL field.

	// CFGR: RCC Clock Configuration           Register
	RCC_CFGR_SW_Pos          = 0x0        // Position of SW field.
	RCC_CFGR_SW_Msk          = 0x7        // Bit mask of SW field.
	RCC_CFGR_SWS_Pos         = 0x3        // Position of SWS field.
	RCC_CFGR_SWS_Msk         = 0x38       // Bit mask of SWS field.
	RCC_CFGR_STOPWUCK_Pos    = 0x6        // Position of STOPWUCK field.
	RCC_CFGR_STOPWUCK_Msk    = 0x40       // Bit mask of STOPWUCK field.
	RCC_CFGR_STOPWUCK        = 0x40       // Bit STOPWUCK.
	RCC_CFGR_STOPKERWUCK_Pos = 0x7        // Position of STOPKERWUCK field.
	RCC_CFGR_STOPKERWUCK_Msk = 0x80       // Bit mask of STOPKERWUCK field.
	RCC_CFGR_STOPKERWUCK     = 0x80       // Bit STOPKERWUCK.
	RCC_CFGR_RTCPRE_Pos      = 0x8        // Position of RTCPRE field.
	RCC_CFGR_RTCPRE_Msk      = 0x3f00     // Bit mask of RTCPRE field.
	RCC_CFGR_HRTIMSEL_Pos    = 0xe        // Position of HRTIMSEL field.
	RCC_CFGR_HRTIMSEL_Msk    = 0x4000     // Bit mask of HRTIMSEL field.
	RCC_CFGR_HRTIMSEL        = 0x4000     // Bit HRTIMSEL.
	RCC_CFGR_TIMPRE_Pos      = 0xf        // Position of TIMPRE field.
	RCC_CFGR_TIMPRE_Msk      = 0x8000     // Bit mask of TIMPRE field.
	RCC_CFGR_TIMPRE          = 0x8000     // Bit TIMPRE.
	RCC_CFGR_MCO1PRE_Pos     = 0x12       // Position of MCO1PRE field.
	RCC_CFGR_MCO1PRE_Msk     = 0x3c0000   // Bit mask of MCO1PRE field.
	RCC_CFGR_MCO1SEL_Pos     = 0x16       // Position of MCO1SEL field.
	RCC_CFGR_MCO1SEL_Msk     = 0x1c00000  // Bit mask of MCO1SEL field.
	RCC_CFGR_MCO2PRE_Pos     = 0x19       // Position of MCO2PRE field.
	RCC_CFGR_MCO2PRE_Msk     = 0x1e000000 // Bit mask of MCO2PRE field.
	RCC_CFGR_MCO2SEL_Pos     = 0x1d       // Position of MCO2SEL field.
	RCC_CFGR_MCO2SEL_Msk     = 0xe0000000 // Bit mask of MCO2SEL field.

	// D1CFGR: RCC Domain 1 Clock Configuration           Register
	RCC_D1CFGR_HPRE_Pos   = 0x0   // Position of HPRE field.
	RCC_D1CFGR_HPRE_Msk   = 0xf   // Bit mask of HPRE field.
	RCC_D1CFGR_D1PPRE_Pos = 0x4   // Position of D1PPRE field.
	RCC_D1CFGR_D1PPRE_Msk = 0x70  // Bit mask of D1PPRE field.
	RCC_D1CFGR_D1CPRE_Pos = 0x8   // Position of D1CPRE field.
	RCC_D1CFGR_D1CPRE_Msk = 0xf00 // Bit mask of D1CPRE field.

	// D2CFGR: RCC Domain 2 Clock Configuration           Register
	RCC_D2CFGR_D2PPRE1_Pos = 0x4   // Position of D2PPRE1 field.
	RCC_D2CFGR_D2PPRE1_Msk = 0x70  // Bit mask of D2PPRE1 field.
	RCC_D2CFGR_D2PPRE2_Pos = 0x8   // Position of D2PPRE2 field.
	RCC_D2CFGR_D2PPRE2_Msk = 0x700 // Bit mask of D2PPRE2 field.

	// D3CFGR: RCC Domain 3 Clock Configuration           Register
	RCC_D3CFGR_D3PPRE_Pos = 0x4  // Position of D3PPRE field.
	RCC_D3CFGR_D3PPRE_Msk = 0x70 // Bit mask of D3PPRE field.

	// PLLCKSELR: RCC PLLs Clock Source Selection           Register
	RCC_PLLCKSELR_PLLSRC_Pos = 0x0       // Position of PLLSRC field.
	RCC_PLLCKSELR_PLLSRC_Msk = 0x3       // Bit mask of PLLSRC field.
	RCC_PLLCKSELR_DIVM1_Pos  = 0x4       // Position of DIVM1 field.
	RCC_PLLCKSELR_DIVM1_Msk  = 0x3f0     // Bit mask of DIVM1 field.
	RCC_PLLCKSELR_DIVM2_Pos  = 0xc       // Position of DIVM2 field.
	RCC_PLLCKSELR_DIVM2_Msk  = 0x3f000   // Bit mask of DIVM2 field.
	RCC_PLLCKSELR_DIVM3_Pos  = 0x14      // Position of DIVM3 field.
	RCC_PLLCKSELR_DIVM3_Msk  = 0x3f00000 // Bit mask of DIVM3 field.

	// PLLCFGR: RCC PLLs Configuration           Register
	RCC_PLLCFGR_PLL1FRACEN_Pos = 0x0       // Position of PLL1FRACEN field.
	RCC_PLLCFGR_PLL1FRACEN_Msk = 0x1       // Bit mask of PLL1FRACEN field.
	RCC_PLLCFGR_PLL1FRACEN     = 0x1       // Bit PLL1FRACEN.
	RCC_PLLCFGR_PLL1VCOSEL_Pos = 0x1       // Position of PLL1VCOSEL field.
	RCC_PLLCFGR_PLL1VCOSEL_Msk = 0x2       // Bit mask of PLL1VCOSEL field.
	RCC_PLLCFGR_PLL1VCOSEL     = 0x2       // Bit PLL1VCOSEL.
	RCC_PLLCFGR_PLL1RGE_Pos    = 0x2       // Position of PLL1RGE field.
	RCC_PLLCFGR_PLL1RGE_Msk    = 0xc       // Bit mask of PLL1RGE field.
	RCC_PLLCFGR_PLL2FRACEN_Pos = 0x4       // Position of PLL2FRACEN field.
	RCC_PLLCFGR_PLL2FRACEN_Msk = 0x10      // Bit mask of PLL2FRACEN field.
	RCC_PLLCFGR_PLL2FRACEN     = 0x10      // Bit PLL2FRACEN.
	RCC_PLLCFGR_PLL2VCOSEL_Pos = 0x5       // Position of PLL2VCOSEL field.
	RCC_PLLCFGR_PLL2VCOSEL_Msk = 0x20      // Bit mask of PLL2VCOSEL field.
	RCC_PLLCFGR_PLL2VCOSEL     = 0x20      // Bit PLL2VCOSEL.
	RCC_PLLCFGR_PLL2RGE_Pos    = 0x6       // Position of PLL2RGE field.
	RCC_PLLCFGR_PLL2RGE_Msk    = 0xc0      // Bit mask of PLL2RGE field.
	RCC_PLLCFGR_PLL3FRACEN_Pos = 0x8       // Position of PLL3FRACEN field.
	RCC_PLLCFGR_PLL3FRACEN_Msk = 0x100     // Bit mask of PLL3FRACEN field.
	RCC_PLLCFGR_PLL3FRACEN     = 0x100     // Bit PLL3FRACEN.
	RCC_PLLCFGR_PLL3VCOSEL_Pos = 0x9       // Position of PLL3VCOSEL field.
	RCC_PLLCFGR_PLL3VCOSEL_Msk = 0x200     // Bit mask of PLL3VCOSEL field.
	RCC_PLLCFGR_PLL3VCOSEL     = 0x200     // Bit PLL3VCOSEL.
	RCC_PLLCFGR_PLL3RGE_Pos    = 0xa       // Position of PLL3RGE field.
	RCC_PLLCFGR_PLL3RGE_Msk    = 0xc00     // Bit mask of PLL3RGE field.
	RCC_PLLCFGR_DIVP1EN_Pos    = 0x10      // Position of DIVP1EN field.
	RCC_PLLCFGR_DIVP1EN_Msk    = 0x10000   // Bit mask of DIVP1EN field.
	RCC_PLLCFGR_DIVP1EN        = 0x10000   // Bit DIVP1EN.
	RCC_PLLCFGR_DIVQ1EN_Pos    = 0x11      // Position of DIVQ1EN field.
	RCC_PLLCFGR_DIVQ1EN_Msk    = 0x20000   // Bit mask of DIVQ1EN field.
	RCC_PLLCFGR_DIVQ1EN        = 0x20000   // Bit DIVQ1EN.
	RCC_PLLCFGR_DIVR1EN_Pos    = 0x12      // Position of DIVR1EN field.
	RCC_PLLCFGR_DIVR1EN_Msk    = 0x40000   // Bit mask of DIVR1EN field.
	RCC_PLLCFGR_DIVR1EN        = 0x40000   // Bit DIVR1EN.
	RCC_PLLCFGR_DIVP2EN_Pos    = 0x13      // Position of DIVP2EN field.
	RCC_PLLCFGR_DIVP2EN_Msk    = 0x80000   // Bit mask of DIVP2EN field.
	RCC_PLLCFGR_DIVP2EN        = 0x80000   // Bit DIVP2EN.
	RCC_PLLCFGR_DIVQ2EN_Pos    = 0x14      // Position of DIVQ2EN field.
	RCC_PLLCFGR_DIVQ2EN_Msk    = 0x100000  // Bit mask of DIVQ2EN field.
	RCC_PLLCFGR_DIVQ2EN        = 0x100000  // Bit DIVQ2EN.
	RCC_PLLCFGR_DIVR2EN_Pos    = 0x15      // Position of DIVR2EN field.
	RCC_PLLCFGR_DIVR2EN_Msk    = 0x200000  // Bit mask of DIVR2EN field.
	RCC_PLLCFGR_DIVR2EN        = 0x200000  // Bit DIVR2EN.
	RCC_PLLCFGR_DIVP3EN_Pos    = 0x16      // Position of DIVP3EN field.
	RCC_PLLCFGR_DIVP3EN_Msk    = 0x400000  // Bit mask of DIVP3EN field.
	RCC_PLLCFGR_DIVP3EN        = 0x400000  // Bit DIVP3EN.
	RCC_PLLCFGR_DIVQ3EN_Pos    = 0x17      // Position of DIVQ3EN field.
	RCC_PLLCFGR_DIVQ3EN_Msk    = 0x800000  // Bit mask of DIVQ3EN field.
	RCC_PLLCFGR_DIVQ3EN        = 0x800000  // Bit DIVQ3EN.
	RCC_PLLCFGR_DIVR3EN_Pos    = 0x18      // Position of DIVR3EN field.
	RCC_PLLCFGR_DIVR3EN_Msk    = 0x1000000 // Bit mask of DIVR3EN field.
	RCC_PLLCFGR_DIVR3EN        = 0x1000000 // Bit DIVR3EN.

	// PLL1DIVR: RCC PLL1 Dividers Configuration           Register
	RCC_PLL1DIVR_DIVN1_Pos = 0x0        // Position of DIVN1 field.
	RCC_PLL1DIVR_DIVN1_Msk = 0x1ff      // Bit mask of DIVN1 field.
	RCC_PLL1DIVR_DIVP1_Pos = 0x9        // Position of DIVP1 field.
	RCC_PLL1DIVR_DIVP1_Msk = 0xfe00     // Bit mask of DIVP1 field.
	RCC_PLL1DIVR_DIVQ1_Pos = 0x10       // Position of DIVQ1 field.
	RCC_PLL1DIVR_DIVQ1_Msk = 0x7f0000   // Bit mask of DIVQ1 field.
	RCC_PLL1DIVR_DIVR1_Pos = 0x18       // Position of DIVR1 field.
	RCC_PLL1DIVR_DIVR1_Msk = 0x7f000000 // Bit mask of DIVR1 field.

	// PLL1FRACR: RCC PLL1 Fractional Divider           Register
	RCC_PLL1FRACR_FRACN1_Pos = 0x3    // Position of FRACN1 field.
	RCC_PLL1FRACR_FRACN1_Msk = 0xfff8 // Bit mask of FRACN1 field.

	// PLL2DIVR: RCC PLL2 Dividers Configuration           Register
	RCC_PLL2DIVR_DIVN1_Pos = 0x0        // Position of DIVN1 field.
	RCC_PLL2DIVR_DIVN1_Msk = 0x1ff      // Bit mask of DIVN1 field.
	RCC_PLL2DIVR_DIVP1_Pos = 0x9        // Position of DIVP1 field.
	RCC_PLL2DIVR_DIVP1_Msk = 0xfe00     // Bit mask of DIVP1 field.
	RCC_PLL2DIVR_DIVQ1_Pos = 0x10       // Position of DIVQ1 field.
	RCC_PLL2DIVR_DIVQ1_Msk = 0x7f0000   // Bit mask of DIVQ1 field.
	RCC_PLL2DIVR_DIVR1_Pos = 0x18       // Position of DIVR1 field.
	RCC_PLL2DIVR_DIVR1_Msk = 0x7f000000 // Bit mask of DIVR1 field.

	// PLL2FRACR: RCC PLL2 Fractional Divider           Register
	RCC_PLL2FRACR_FRACN2_Pos = 0x3    // Position of FRACN2 field.
	RCC_PLL2FRACR_FRACN2_Msk = 0xfff8 // Bit mask of FRACN2 field.

	// PLL3DIVR: RCC PLL3 Dividers Configuration           Register
	RCC_PLL3DIVR_DIVN3_Pos = 0x0        // Position of DIVN3 field.
	RCC_PLL3DIVR_DIVN3_Msk = 0x1ff      // Bit mask of DIVN3 field.
	RCC_PLL3DIVR_DIVP3_Pos = 0x9        // Position of DIVP3 field.
	RCC_PLL3DIVR_DIVP3_Msk = 0xfe00     // Bit mask of DIVP3 field.
	RCC_PLL3DIVR_DIVQ3_Pos = 0x10       // Position of DIVQ3 field.
	RCC_PLL3DIVR_DIVQ3_Msk = 0x7f0000   // Bit mask of DIVQ3 field.
	RCC_PLL3DIVR_DIVR3_Pos = 0x18       // Position of DIVR3 field.
	RCC_PLL3DIVR_DIVR3_Msk = 0x7f000000 // Bit mask of DIVR3 field.

	// PLL3FRACR: RCC PLL3 Fractional Divider           Register
	RCC_PLL3FRACR_FRACN3_Pos = 0x3    // Position of FRACN3 field.
	RCC_PLL3FRACR_FRACN3_Msk = 0xfff8 // Bit mask of FRACN3 field.

	// D1CCIPR: RCC Domain 1 Kernel Clock Configuration           Register
	RCC_D1CCIPR_FMCSRC_Pos   = 0x0        // Position of FMCSRC field.
	RCC_D1CCIPR_FMCSRC_Msk   = 0x3        // Bit mask of FMCSRC field.
	RCC_D1CCIPR_QSPISRC_Pos  = 0x4        // Position of QSPISRC field.
	RCC_D1CCIPR_QSPISRC_Msk  = 0x30       // Bit mask of QSPISRC field.
	RCC_D1CCIPR_SDMMCSRC_Pos = 0x10       // Position of SDMMCSRC field.
	RCC_D1CCIPR_SDMMCSRC_Msk = 0x10000    // Bit mask of SDMMCSRC field.
	RCC_D1CCIPR_SDMMCSRC     = 0x10000    // Bit SDMMCSRC.
	RCC_D1CCIPR_CKPERSRC_Pos = 0x1c       // Position of CKPERSRC field.
	RCC_D1CCIPR_CKPERSRC_Msk = 0x30000000 // Bit mask of CKPERSRC field.

	// D2CCIP1R: RCC Domain 2 Kernel Clock Configuration           Register
	RCC_D2CCIP1R_SAI1SRC_Pos   = 0x0        // Position of SAI1SRC field.
	RCC_D2CCIP1R_SAI1SRC_Msk   = 0x7        // Bit mask of SAI1SRC field.
	RCC_D2CCIP1R_SAI23SRC_Pos  = 0x6        // Position of SAI23SRC field.
	RCC_D2CCIP1R_SAI23SRC_Msk  = 0x1c0      // Bit mask of SAI23SRC field.
	RCC_D2CCIP1R_SPI123SRC_Pos = 0xc        // Position of SPI123SRC field.
	RCC_D2CCIP1R_SPI123SRC_Msk = 0x7000     // Bit mask of SPI123SRC field.
	RCC_D2CCIP1R_SPI45SRC_Pos  = 0x10       // Position of SPI45SRC field.
	RCC_D2CCIP1R_SPI45SRC_Msk  = 0x70000    // Bit mask of SPI45SRC field.
	RCC_D2CCIP1R_SPDIFSRC_Pos  = 0x14       // Position of SPDIFSRC field.
	RCC_D2CCIP1R_SPDIFSRC_Msk  = 0x300000   // Bit mask of SPDIFSRC field.
	RCC_D2CCIP1R_DFSDM1SRC_Pos = 0x18       // Position of DFSDM1SRC field.
	RCC_D2CCIP1R_DFSDM1SRC_Msk = 0x1000000  // Bit mask of DFSDM1SRC field.
	RCC_D2CCIP1R_DFSDM1SRC     = 0x1000000  // Bit DFSDM1SRC.
	RCC_D2CCIP1R_FDCANSRC_Pos  = 0x1c       // Position of FDCANSRC field.
	RCC_D2CCIP1R_FDCANSRC_Msk  = 0x30000000 // Bit mask of FDCANSRC field.
	RCC_D2CCIP1R_SWPSRC_Pos    = 0x1f       // Position of SWPSRC field.
	RCC_D2CCIP1R_SWPSRC_Msk    = 0x80000000 // Bit mask of SWPSRC field.
	RCC_D2CCIP1R_SWPSRC        = 0x80000000 // Bit SWPSRC.

	// D2CCIP2R: RCC Domain 2 Kernel Clock Configuration           Register
	RCC_D2CCIP2R_USART234578SRC_Pos = 0x0        // Position of USART234578SRC field.
	RCC_D2CCIP2R_USART234578SRC_Msk = 0x7        // Bit mask of USART234578SRC field.
	RCC_D2CCIP2R_USART16SRC_Pos     = 0x3        // Position of USART16SRC field.
	RCC_D2CCIP2R_USART16SRC_Msk     = 0x38       // Bit mask of USART16SRC field.
	RCC_D2CCIP2R_RNGSRC_Pos         = 0x8        // Position of RNGSRC field.
	RCC_D2CCIP2R_RNGSRC_Msk         = 0x300      // Bit mask of RNGSRC field.
	RCC_D2CCIP2R_I2C123SRC_Pos      = 0xc        // Position of I2C123SRC field.
	RCC_D2CCIP2R_I2C123SRC_Msk      = 0x3000     // Bit mask of I2C123SRC field.
	RCC_D2CCIP2R_USBSRC_Pos         = 0x14       // Position of USBSRC field.
	RCC_D2CCIP2R_USBSRC_Msk         = 0x300000   // Bit mask of USBSRC field.
	RCC_D2CCIP2R_CECSRC_Pos         = 0x16       // Position of CECSRC field.
	RCC_D2CCIP2R_CECSRC_Msk         = 0xc00000   // Bit mask of CECSRC field.
	RCC_D2CCIP2R_LPTIM1SRC_Pos      = 0x1c       // Position of LPTIM1SRC field.
	RCC_D2CCIP2R_LPTIM1SRC_Msk      = 0x70000000 // Bit mask of LPTIM1SRC field.

	// D3CCIPR: RCC Domain 3 Kernel Clock Configuration           Register
	RCC_D3CCIPR_LPUART1SRC_Pos  = 0x0        // Position of LPUART1SRC field.
	RCC_D3CCIPR_LPUART1SRC_Msk  = 0x7        // Bit mask of LPUART1SRC field.
	RCC_D3CCIPR_I2C4SRC_Pos     = 0x8        // Position of I2C4SRC field.
	RCC_D3CCIPR_I2C4SRC_Msk     = 0x300      // Bit mask of I2C4SRC field.
	RCC_D3CCIPR_LPTIM2SRC_Pos   = 0xa        // Position of LPTIM2SRC field.
	RCC_D3CCIPR_LPTIM2SRC_Msk   = 0x1c00     // Bit mask of LPTIM2SRC field.
	RCC_D3CCIPR_LPTIM345SRC_Pos = 0xd        // Position of LPTIM345SRC field.
	RCC_D3CCIPR_LPTIM345SRC_Msk = 0xe000     // Bit mask of LPTIM345SRC field.
	RCC_D3CCIPR_ADCSRC_Pos      = 0x10       // Position of ADCSRC field.
	RCC_D3CCIPR_ADCSRC_Msk      = 0x30000    // Bit mask of ADCSRC field.
	RCC_D3CCIPR_SAI4ASRC_Pos    = 0x15       // Position of SAI4ASRC field.
	RCC_D3CCIPR_SAI4ASRC_Msk    = 0xe00000   // Bit mask of SAI4ASRC field.
	RCC_D3CCIPR_SAI4BSRC_Pos    = 0x18       // Position of SAI4BSRC field.
	RCC_D3CCIPR_SAI4BSRC_Msk    = 0x7000000  // Bit mask of SAI4BSRC field.
	RCC_D3CCIPR_SPI6SRC_Pos     = 0x1c       // Position of SPI6SRC field.
	RCC_D3CCIPR_SPI6SRC_Msk     = 0x70000000 // Bit mask of SPI6SRC field.

	// CIER: RCC Clock Source Interrupt Enable           Register
	RCC_CIER_LSIRDYIE_Pos  = 0x0   // Position of LSIRDYIE field.
	RCC_CIER_LSIRDYIE_Msk  = 0x1   // Bit mask of LSIRDYIE field.
	RCC_CIER_LSIRDYIE      = 0x1   // Bit LSIRDYIE.
	RCC_CIER_LSERDYIE_Pos  = 0x1   // Position of LSERDYIE field.
	RCC_CIER_LSERDYIE_Msk  = 0x2   // Bit mask of LSERDYIE field.
	RCC_CIER_LSERDYIE      = 0x2   // Bit LSERDYIE.
	RCC_CIER_HSIRDYIE_Pos  = 0x2   // Position of HSIRDYIE field.
	RCC_CIER_HSIRDYIE_Msk  = 0x4   // Bit mask of HSIRDYIE field.
	RCC_CIER_HSIRDYIE      = 0x4   // Bit HSIRDYIE.
	RCC_CIER_HSERDYIE_Pos  = 0x3   // Position of HSERDYIE field.
	RCC_CIER_HSERDYIE_Msk  = 0x8   // Bit mask of HSERDYIE field.
	RCC_CIER_HSERDYIE      = 0x8   // Bit HSERDYIE.
	RCC_CIER_CSIRDYIE_Pos  = 0x4   // Position of CSIRDYIE field.
	RCC_CIER_CSIRDYIE_Msk  = 0x10  // Bit mask of CSIRDYIE field.
	RCC_CIER_CSIRDYIE      = 0x10  // Bit CSIRDYIE.
	RCC_CIER_RC48RDYIE_Pos = 0x5   // Position of RC48RDYIE field.
	RCC_CIER_RC48RDYIE_Msk = 0x20  // Bit mask of RC48RDYIE field.
	RCC_CIER_RC48RDYIE     = 0x20  // Bit RC48RDYIE.
	RCC_CIER_PLL1RDYIE_Pos = 0x6   // Position of PLL1RDYIE field.
	RCC_CIER_PLL1RDYIE_Msk = 0x40  // Bit mask of PLL1RDYIE field.
	RCC_CIER_PLL1RDYIE     = 0x40  // Bit PLL1RDYIE.
	RCC_CIER_PLL2RDYIE_Pos = 0x7   // Position of PLL2RDYIE field.
	RCC_CIER_PLL2RDYIE_Msk = 0x80  // Bit mask of PLL2RDYIE field.
	RCC_CIER_PLL2RDYIE     = 0x80  // Bit PLL2RDYIE.
	RCC_CIER_PLL3RDYIE_Pos = 0x8   // Position of PLL3RDYIE field.
	RCC_CIER_PLL3RDYIE_Msk = 0x100 // Bit mask of PLL3RDYIE field.
	RCC_CIER_PLL3RDYIE     = 0x100 // Bit PLL3RDYIE.
	RCC_CIER_LSECSSIE_Pos  = 0x9   // Position of LSECSSIE field.
	RCC_CIER_LSECSSIE_Msk  = 0x200 // Bit mask of LSECSSIE field.
	RCC_CIER_LSECSSIE      = 0x200 // Bit LSECSSIE.

	// CIFR: RCC Clock Source Interrupt Flag           Register
	RCC_CIFR_LSIRDYF_Pos  = 0x0   // Position of LSIRDYF field.
	RCC_CIFR_LSIRDYF_Msk  = 0x1   // Bit mask of LSIRDYF field.
	RCC_CIFR_LSIRDYF      = 0x1   // Bit LSIRDYF.
	RCC_CIFR_LSERDYF_Pos  = 0x1   // Position of LSERDYF field.
	RCC_CIFR_LSERDYF_Msk  = 0x2   // Bit mask of LSERDYF field.
	RCC_CIFR_LSERDYF      = 0x2   // Bit LSERDYF.
	RCC_CIFR_HSIRDYF_Pos  = 0x2   // Position of HSIRDYF field.
	RCC_CIFR_HSIRDYF_Msk  = 0x4   // Bit mask of HSIRDYF field.
	RCC_CIFR_HSIRDYF      = 0x4   // Bit HSIRDYF.
	RCC_CIFR_HSERDYF_Pos  = 0x3   // Position of HSERDYF field.
	RCC_CIFR_HSERDYF_Msk  = 0x8   // Bit mask of HSERDYF field.
	RCC_CIFR_HSERDYF      = 0x8   // Bit HSERDYF.
	RCC_CIFR_CSIRDY_Pos   = 0x4   // Position of CSIRDY field.
	RCC_CIFR_CSIRDY_Msk   = 0x10  // Bit mask of CSIRDY field.
	RCC_CIFR_CSIRDY       = 0x10  // Bit CSIRDY.
	RCC_CIFR_RC48RDYF_Pos = 0x5   // Position of RC48RDYF field.
	RCC_CIFR_RC48RDYF_Msk = 0x20  // Bit mask of RC48RDYF field.
	RCC_CIFR_RC48RDYF     = 0x20  // Bit RC48RDYF.
	RCC_CIFR_PLL1RDYF_Pos = 0x6   // Position of PLL1RDYF field.
	RCC_CIFR_PLL1RDYF_Msk = 0x40  // Bit mask of PLL1RDYF field.
	RCC_CIFR_PLL1RDYF     = 0x40  // Bit PLL1RDYF.
	RCC_CIFR_PLL2RDYF_Pos = 0x7   // Position of PLL2RDYF field.
	RCC_CIFR_PLL2RDYF_Msk = 0x80  // Bit mask of PLL2RDYF field.
	RCC_CIFR_PLL2RDYF     = 0x80  // Bit PLL2RDYF.
	RCC_CIFR_PLL3RDYF_Pos = 0x8   // Position of PLL3RDYF field.
	RCC_CIFR_PLL3RDYF_Msk = 0x100 // Bit mask of PLL3RDYF field.
	RCC_CIFR_PLL3RDYF     = 0x100 // Bit PLL3RDYF.
	RCC_CIFR_LSECSSF_Pos  = 0x9   // Position of LSECSSF field.
	RCC_CIFR_LSECSSF_Msk  = 0x200 // Bit mask of LSECSSF field.
	RCC_CIFR_LSECSSF      = 0x200 // Bit LSECSSF.
	RCC_CIFR_HSECSSF_Pos  = 0xa   // Position of HSECSSF field.
	RCC_CIFR_HSECSSF_Msk  = 0x400 // Bit mask of HSECSSF field.
	RCC_CIFR_HSECSSF      = 0x400 // Bit HSECSSF.

	// CICR: RCC Clock Source Interrupt Clear           Register
	RCC_CICR_LSIRDYC_Pos                   = 0x0   // Position of LSIRDYC field.
	RCC_CICR_LSIRDYC_Msk                   = 0x1   // Bit mask of LSIRDYC field.
	RCC_CICR_LSIRDYC                       = 0x1   // Bit LSIRDYC.
	RCC_CICR_LSERDYC_Pos                   = 0x1   // Position of LSERDYC field.
	RCC_CICR_LSERDYC_Msk                   = 0x2   // Bit mask of LSERDYC field.
	RCC_CICR_LSERDYC                       = 0x2   // Bit LSERDYC.
	RCC_CICR_HSIRDYC_Pos                   = 0x2   // Position of HSIRDYC field.
	RCC_CICR_HSIRDYC_Msk                   = 0x4   // Bit mask of HSIRDYC field.
	RCC_CICR_HSIRDYC                       = 0x4   // Bit HSIRDYC.
	RCC_CICR_HSERDYC_Pos                   = 0x3   // Position of HSERDYC field.
	RCC_CICR_HSERDYC_Msk                   = 0x8   // Bit mask of HSERDYC field.
	RCC_CICR_HSERDYC                       = 0x8   // Bit HSERDYC.
	RCC_CICR_HSE_ready_Interrupt_Clear_Pos = 0x4   // Position of HSE_ready_Interrupt_Clear field.
	RCC_CICR_HSE_ready_Interrupt_Clear_Msk = 0x10  // Bit mask of HSE_ready_Interrupt_Clear field.
	RCC_CICR_HSE_ready_Interrupt_Clear     = 0x10  // Bit HSE_ready_Interrupt_Clear.
	RCC_CICR_RC48RDYC_Pos                  = 0x5   // Position of RC48RDYC field.
	RCC_CICR_RC48RDYC_Msk                  = 0x20  // Bit mask of RC48RDYC field.
	RCC_CICR_RC48RDYC                      = 0x20  // Bit RC48RDYC.
	RCC_CICR_PLL1RDYC_Pos                  = 0x6   // Position of PLL1RDYC field.
	RCC_CICR_PLL1RDYC_Msk                  = 0x40  // Bit mask of PLL1RDYC field.
	RCC_CICR_PLL1RDYC                      = 0x40  // Bit PLL1RDYC.
	RCC_CICR_PLL2RDYC_Pos                  = 0x7   // Position of PLL2RDYC field.
	RCC_CICR_PLL2RDYC_Msk                  = 0x80  // Bit mask of PLL2RDYC field.
	RCC_CICR_PLL2RDYC                      = 0x80  // Bit PLL2RDYC.
	RCC_CICR_PLL3RDYC_Pos                  = 0x8   // Position of PLL3RDYC field.
	RCC_CICR_PLL3RDYC_Msk                  = 0x100 // Bit mask of PLL3RDYC field.
	RCC_CICR_PLL3RDYC                      = 0x100 // Bit PLL3RDYC.
	RCC_CICR_LSECSSC_Pos                   = 0x9   // Position of LSECSSC field.
	RCC_CICR_LSECSSC_Msk                   = 0x200 // Bit mask of LSECSSC field.
	RCC_CICR_LSECSSC                       = 0x200 // Bit LSECSSC.
	RCC_CICR_HSECSSC_Pos                   = 0xa   // Position of HSECSSC field.
	RCC_CICR_HSECSSC_Msk                   = 0x400 // Bit mask of HSECSSC field.
	RCC_CICR_HSECSSC                       = 0x400 // Bit HSECSSC.

	// BDCR: RCC Backup Domain Control           Register
	RCC_BDCR_LSEON_Pos    = 0x0     // Position of LSEON field.
	RCC_BDCR_LSEON_Msk    = 0x1     // Bit mask of LSEON field.
	RCC_BDCR_LSEON        = 0x1     // Bit LSEON.
	RCC_BDCR_LSERDY_Pos   = 0x1     // Position of LSERDY field.
	RCC_BDCR_LSERDY_Msk   = 0x2     // Bit mask of LSERDY field.
	RCC_BDCR_LSERDY       = 0x2     // Bit LSERDY.
	RCC_BDCR_LSEBYP_Pos   = 0x2     // Position of LSEBYP field.
	RCC_BDCR_LSEBYP_Msk   = 0x4     // Bit mask of LSEBYP field.
	RCC_BDCR_LSEBYP       = 0x4     // Bit LSEBYP.
	RCC_BDCR_LSEDRV_Pos   = 0x3     // Position of LSEDRV field.
	RCC_BDCR_LSEDRV_Msk   = 0x18    // Bit mask of LSEDRV field.
	RCC_BDCR_LSECSSON_Pos = 0x5     // Position of LSECSSON field.
	RCC_BDCR_LSECSSON_Msk = 0x20    // Bit mask of LSECSSON field.
	RCC_BDCR_LSECSSON     = 0x20    // Bit LSECSSON.
	RCC_BDCR_LSECSSD_Pos  = 0x6     // Position of LSECSSD field.
	RCC_BDCR_LSECSSD_Msk  = 0x40    // Bit mask of LSECSSD field.
	RCC_BDCR_LSECSSD      = 0x40    // Bit LSECSSD.
	RCC_BDCR_RTCSRC_Pos   = 0x8     // Position of RTCSRC field.
	RCC_BDCR_RTCSRC_Msk   = 0x300   // Bit mask of RTCSRC field.
	RCC_BDCR_RTCEN_Pos    = 0xf     // Position of RTCEN field.
	RCC_BDCR_RTCEN_Msk    = 0x8000  // Bit mask of RTCEN field.
	RCC_BDCR_RTCEN        = 0x8000  // Bit RTCEN.
	RCC_BDCR_VSWRST_Pos   = 0x10    // Position of VSWRST field.
	RCC_BDCR_VSWRST_Msk   = 0x10000 // Bit mask of VSWRST field.
	RCC_BDCR_VSWRST       = 0x10000 // Bit VSWRST.

	// CSR: RCC Clock Control and Status           Register
	RCC_CSR_LSION_Pos  = 0x0 // Position of LSION field.
	RCC_CSR_LSION_Msk  = 0x1 // Bit mask of LSION field.
	RCC_CSR_LSION      = 0x1 // Bit LSION.
	RCC_CSR_LSIRDY_Pos = 0x1 // Position of LSIRDY field.
	RCC_CSR_LSIRDY_Msk = 0x2 // Bit mask of LSIRDY field.
	RCC_CSR_LSIRDY     = 0x2 // Bit LSIRDY.

	// AHB3RSTR: RCC AHB3 Reset Register
	RCC_AHB3RSTR_MDMARST_Pos   = 0x0        // Position of MDMARST field.
	RCC_AHB3RSTR_MDMARST_Msk   = 0x1        // Bit mask of MDMARST field.
	RCC_AHB3RSTR_MDMARST       = 0x1        // Bit MDMARST.
	RCC_AHB3RSTR_DMA2DRST_Pos  = 0x4        // Position of DMA2DRST field.
	RCC_AHB3RSTR_DMA2DRST_Msk  = 0x10       // Bit mask of DMA2DRST field.
	RCC_AHB3RSTR_DMA2DRST      = 0x10       // Bit DMA2DRST.
	RCC_AHB3RSTR_JPGDECRST_Pos = 0x5        // Position of JPGDECRST field.
	RCC_AHB3RSTR_JPGDECRST_Msk = 0x20       // Bit mask of JPGDECRST field.
	RCC_AHB3RSTR_JPGDECRST     = 0x20       // Bit JPGDECRST.
	RCC_AHB3RSTR_FMCRST_Pos    = 0xc        // Position of FMCRST field.
	RCC_AHB3RSTR_FMCRST_Msk    = 0x1000     // Bit mask of FMCRST field.
	RCC_AHB3RSTR_FMCRST        = 0x1000     // Bit FMCRST.
	RCC_AHB3RSTR_QSPIRST_Pos   = 0xe        // Position of QSPIRST field.
	RCC_AHB3RSTR_QSPIRST_Msk   = 0x4000     // Bit mask of QSPIRST field.
	RCC_AHB3RSTR_QSPIRST       = 0x4000     // Bit QSPIRST.
	RCC_AHB3RSTR_SDMMC1RST_Pos = 0x10       // Position of SDMMC1RST field.
	RCC_AHB3RSTR_SDMMC1RST_Msk = 0x10000    // Bit mask of SDMMC1RST field.
	RCC_AHB3RSTR_SDMMC1RST     = 0x10000    // Bit SDMMC1RST.
	RCC_AHB3RSTR_CPURST_Pos    = 0x1f       // Position of CPURST field.
	RCC_AHB3RSTR_CPURST_Msk    = 0x80000000 // Bit mask of CPURST field.
	RCC_AHB3RSTR_CPURST        = 0x80000000 // Bit CPURST.

	// AHB1RSTR: RCC AHB1 Peripheral Reset           Register
	RCC_AHB1RSTR_DMA1RST_Pos    = 0x0       // Position of DMA1RST field.
	RCC_AHB1RSTR_DMA1RST_Msk    = 0x1       // Bit mask of DMA1RST field.
	RCC_AHB1RSTR_DMA1RST        = 0x1       // Bit DMA1RST.
	RCC_AHB1RSTR_DMA2RST_Pos    = 0x1       // Position of DMA2RST field.
	RCC_AHB1RSTR_DMA2RST_Msk    = 0x2       // Bit mask of DMA2RST field.
	RCC_AHB1RSTR_DMA2RST        = 0x2       // Bit DMA2RST.
	RCC_AHB1RSTR_ADC12RST_Pos   = 0x5       // Position of ADC12RST field.
	RCC_AHB1RSTR_ADC12RST_Msk   = 0x20      // Bit mask of ADC12RST field.
	RCC_AHB1RSTR_ADC12RST       = 0x20      // Bit ADC12RST.
	RCC_AHB1RSTR_ETH1MACRST_Pos = 0xf       // Position of ETH1MACRST field.
	RCC_AHB1RSTR_ETH1MACRST_Msk = 0x8000    // Bit mask of ETH1MACRST field.
	RCC_AHB1RSTR_ETH1MACRST     = 0x8000    // Bit ETH1MACRST.
	RCC_AHB1RSTR_USB1OTGRST_Pos = 0x19      // Position of USB1OTGRST field.
	RCC_AHB1RSTR_USB1OTGRST_Msk = 0x2000000 // Bit mask of USB1OTGRST field.
	RCC_AHB1RSTR_USB1OTGRST     = 0x2000000 // Bit USB1OTGRST.
	RCC_AHB1RSTR_USB2OTGRST_Pos = 0x1b      // Position of USB2OTGRST field.
	RCC_AHB1RSTR_USB2OTGRST_Msk = 0x8000000 // Bit mask of USB2OTGRST field.
	RCC_AHB1RSTR_USB2OTGRST     = 0x8000000 // Bit USB2OTGRST.

	// AHB2RSTR: RCC AHB2 Peripheral Reset           Register
	RCC_AHB2RSTR_CAMITFRST_Pos = 0x0   // Position of CAMITFRST field.
	RCC_AHB2RSTR_CAMITFRST_Msk = 0x1   // Bit mask of CAMITFRST field.
	RCC_AHB2RSTR_CAMITFRST     = 0x1   // Bit CAMITFRST.
	RCC_AHB2RSTR_CRYPTRST_Pos  = 0x4   // Position of CRYPTRST field.
	RCC_AHB2RSTR_CRYPTRST_Msk  = 0x10  // Bit mask of CRYPTRST field.
	RCC_AHB2RSTR_CRYPTRST      = 0x10  // Bit CRYPTRST.
	RCC_AHB2RSTR_HASHRST_Pos   = 0x5   // Position of HASHRST field.
	RCC_AHB2RSTR_HASHRST_Msk   = 0x20  // Bit mask of HASHRST field.
	RCC_AHB2RSTR_HASHRST       = 0x20  // Bit HASHRST.
	RCC_AHB2RSTR_RNGRST_Pos    = 0x6   // Position of RNGRST field.
	RCC_AHB2RSTR_RNGRST_Msk    = 0x40  // Bit mask of RNGRST field.
	RCC_AHB2RSTR_RNGRST        = 0x40  // Bit RNGRST.
	RCC_AHB2RSTR_SDMMC2RST_Pos = 0x9   // Position of SDMMC2RST field.
	RCC_AHB2RSTR_SDMMC2RST_Msk = 0x200 // Bit mask of SDMMC2RST field.
	RCC_AHB2RSTR_SDMMC2RST     = 0x200 // Bit SDMMC2RST.

	// AHB4RSTR: RCC AHB4 Peripheral Reset           Register
	RCC_AHB4RSTR_GPIOARST_Pos = 0x0       // Position of GPIOARST field.
	RCC_AHB4RSTR_GPIOARST_Msk = 0x1       // Bit mask of GPIOARST field.
	RCC_AHB4RSTR_GPIOARST     = 0x1       // Bit GPIOARST.
	RCC_AHB4RSTR_GPIOBRST_Pos = 0x1       // Position of GPIOBRST field.
	RCC_AHB4RSTR_GPIOBRST_Msk = 0x2       // Bit mask of GPIOBRST field.
	RCC_AHB4RSTR_GPIOBRST     = 0x2       // Bit GPIOBRST.
	RCC_AHB4RSTR_GPIOCRST_Pos = 0x2       // Position of GPIOCRST field.
	RCC_AHB4RSTR_GPIOCRST_Msk = 0x4       // Bit mask of GPIOCRST field.
	RCC_AHB4RSTR_GPIOCRST     = 0x4       // Bit GPIOCRST.
	RCC_AHB4RSTR_GPIODRST_Pos = 0x3       // Position of GPIODRST field.
	RCC_AHB4RSTR_GPIODRST_Msk = 0x8       // Bit mask of GPIODRST field.
	RCC_AHB4RSTR_GPIODRST     = 0x8       // Bit GPIODRST.
	RCC_AHB4RSTR_GPIOERST_Pos = 0x4       // Position of GPIOERST field.
	RCC_AHB4RSTR_GPIOERST_Msk = 0x10      // Bit mask of GPIOERST field.
	RCC_AHB4RSTR_GPIOERST     = 0x10      // Bit GPIOERST.
	RCC_AHB4RSTR_GPIOFRST_Pos = 0x5       // Position of GPIOFRST field.
	RCC_AHB4RSTR_GPIOFRST_Msk = 0x20      // Bit mask of GPIOFRST field.
	RCC_AHB4RSTR_GPIOFRST     = 0x20      // Bit GPIOFRST.
	RCC_AHB4RSTR_GPIOGRST_Pos = 0x6       // Position of GPIOGRST field.
	RCC_AHB4RSTR_GPIOGRST_Msk = 0x40      // Bit mask of GPIOGRST field.
	RCC_AHB4RSTR_GPIOGRST     = 0x40      // Bit GPIOGRST.
	RCC_AHB4RSTR_GPIOHRST_Pos = 0x7       // Position of GPIOHRST field.
	RCC_AHB4RSTR_GPIOHRST_Msk = 0x80      // Bit mask of GPIOHRST field.
	RCC_AHB4RSTR_GPIOHRST     = 0x80      // Bit GPIOHRST.
	RCC_AHB4RSTR_GPIOIRST_Pos = 0x8       // Position of GPIOIRST field.
	RCC_AHB4RSTR_GPIOIRST_Msk = 0x100     // Bit mask of GPIOIRST field.
	RCC_AHB4RSTR_GPIOIRST     = 0x100     // Bit GPIOIRST.
	RCC_AHB4RSTR_GPIOJRST_Pos = 0x9       // Position of GPIOJRST field.
	RCC_AHB4RSTR_GPIOJRST_Msk = 0x200     // Bit mask of GPIOJRST field.
	RCC_AHB4RSTR_GPIOJRST     = 0x200     // Bit GPIOJRST.
	RCC_AHB4RSTR_GPIOKRST_Pos = 0xa       // Position of GPIOKRST field.
	RCC_AHB4RSTR_GPIOKRST_Msk = 0x400     // Bit mask of GPIOKRST field.
	RCC_AHB4RSTR_GPIOKRST     = 0x400     // Bit GPIOKRST.
	RCC_AHB4RSTR_CRCRST_Pos   = 0x13      // Position of CRCRST field.
	RCC_AHB4RSTR_CRCRST_Msk   = 0x80000   // Bit mask of CRCRST field.
	RCC_AHB4RSTR_CRCRST       = 0x80000   // Bit CRCRST.
	RCC_AHB4RSTR_BDMARST_Pos  = 0x15      // Position of BDMARST field.
	RCC_AHB4RSTR_BDMARST_Msk  = 0x200000  // Bit mask of BDMARST field.
	RCC_AHB4RSTR_BDMARST      = 0x200000  // Bit BDMARST.
	RCC_AHB4RSTR_ADC3RST_Pos  = 0x18      // Position of ADC3RST field.
	RCC_AHB4RSTR_ADC3RST_Msk  = 0x1000000 // Bit mask of ADC3RST field.
	RCC_AHB4RSTR_ADC3RST      = 0x1000000 // Bit ADC3RST.
	RCC_AHB4RSTR_HSEMRST_Pos  = 0x19      // Position of HSEMRST field.
	RCC_AHB4RSTR_HSEMRST_Msk  = 0x2000000 // Bit mask of HSEMRST field.
	RCC_AHB4RSTR_HSEMRST      = 0x2000000 // Bit HSEMRST.

	// APB3RSTR: RCC APB3 Peripheral Reset           Register
	RCC_APB3RSTR_LTDCRST_Pos = 0x3 // Position of LTDCRST field.
	RCC_APB3RSTR_LTDCRST_Msk = 0x8 // Bit mask of LTDCRST field.
	RCC_APB3RSTR_LTDCRST     = 0x8 // Bit LTDCRST.

	// APB1LRSTR: RCC APB1 Peripheral Reset           Register
	RCC_APB1LRSTR_TIM2RST_Pos    = 0x0        // Position of TIM2RST field.
	RCC_APB1LRSTR_TIM2RST_Msk    = 0x1        // Bit mask of TIM2RST field.
	RCC_APB1LRSTR_TIM2RST        = 0x1        // Bit TIM2RST.
	RCC_APB1LRSTR_TIM3RST_Pos    = 0x1        // Position of TIM3RST field.
	RCC_APB1LRSTR_TIM3RST_Msk    = 0x2        // Bit mask of TIM3RST field.
	RCC_APB1LRSTR_TIM3RST        = 0x2        // Bit TIM3RST.
	RCC_APB1LRSTR_TIM4RST_Pos    = 0x2        // Position of TIM4RST field.
	RCC_APB1LRSTR_TIM4RST_Msk    = 0x4        // Bit mask of TIM4RST field.
	RCC_APB1LRSTR_TIM4RST        = 0x4        // Bit TIM4RST.
	RCC_APB1LRSTR_TIM5RST_Pos    = 0x3        // Position of TIM5RST field.
	RCC_APB1LRSTR_TIM5RST_Msk    = 0x8        // Bit mask of TIM5RST field.
	RCC_APB1LRSTR_TIM5RST        = 0x8        // Bit TIM5RST.
	RCC_APB1LRSTR_TIM6RST_Pos    = 0x4        // Position of TIM6RST field.
	RCC_APB1LRSTR_TIM6RST_Msk    = 0x10       // Bit mask of TIM6RST field.
	RCC_APB1LRSTR_TIM6RST        = 0x10       // Bit TIM6RST.
	RCC_APB1LRSTR_TIM7RST_Pos    = 0x5        // Position of TIM7RST field.
	RCC_APB1LRSTR_TIM7RST_Msk    = 0x20       // Bit mask of TIM7RST field.
	RCC_APB1LRSTR_TIM7RST        = 0x20       // Bit TIM7RST.
	RCC_APB1LRSTR_TIM12RST_Pos   = 0x6        // Position of TIM12RST field.
	RCC_APB1LRSTR_TIM12RST_Msk   = 0x40       // Bit mask of TIM12RST field.
	RCC_APB1LRSTR_TIM12RST       = 0x40       // Bit TIM12RST.
	RCC_APB1LRSTR_TIM13RST_Pos   = 0x7        // Position of TIM13RST field.
	RCC_APB1LRSTR_TIM13RST_Msk   = 0x80       // Bit mask of TIM13RST field.
	RCC_APB1LRSTR_TIM13RST       = 0x80       // Bit TIM13RST.
	RCC_APB1LRSTR_TIM14RST_Pos   = 0x8        // Position of TIM14RST field.
	RCC_APB1LRSTR_TIM14RST_Msk   = 0x100      // Bit mask of TIM14RST field.
	RCC_APB1LRSTR_TIM14RST       = 0x100      // Bit TIM14RST.
	RCC_APB1LRSTR_LPTIM1RST_Pos  = 0x9        // Position of LPTIM1RST field.
	RCC_APB1LRSTR_LPTIM1RST_Msk  = 0x200      // Bit mask of LPTIM1RST field.
	RCC_APB1LRSTR_LPTIM1RST      = 0x200      // Bit LPTIM1RST.
	RCC_APB1LRSTR_SPI2RST_Pos    = 0xe        // Position of SPI2RST field.
	RCC_APB1LRSTR_SPI2RST_Msk    = 0x4000     // Bit mask of SPI2RST field.
	RCC_APB1LRSTR_SPI2RST        = 0x4000     // Bit SPI2RST.
	RCC_APB1LRSTR_SPI3RST_Pos    = 0xf        // Position of SPI3RST field.
	RCC_APB1LRSTR_SPI3RST_Msk    = 0x8000     // Bit mask of SPI3RST field.
	RCC_APB1LRSTR_SPI3RST        = 0x8000     // Bit SPI3RST.
	RCC_APB1LRSTR_SPDIFRXRST_Pos = 0x10       // Position of SPDIFRXRST field.
	RCC_APB1LRSTR_SPDIFRXRST_Msk = 0x10000    // Bit mask of SPDIFRXRST field.
	RCC_APB1LRSTR_SPDIFRXRST     = 0x10000    // Bit SPDIFRXRST.
	RCC_APB1LRSTR_USART2RST_Pos  = 0x11       // Position of USART2RST field.
	RCC_APB1LRSTR_USART2RST_Msk  = 0x20000    // Bit mask of USART2RST field.
	RCC_APB1LRSTR_USART2RST      = 0x20000    // Bit USART2RST.
	RCC_APB1LRSTR_USART3RST_Pos  = 0x12       // Position of USART3RST field.
	RCC_APB1LRSTR_USART3RST_Msk  = 0x40000    // Bit mask of USART3RST field.
	RCC_APB1LRSTR_USART3RST      = 0x40000    // Bit USART3RST.
	RCC_APB1LRSTR_UART4RST_Pos   = 0x13       // Position of UART4RST field.
	RCC_APB1LRSTR_UART4RST_Msk   = 0x80000    // Bit mask of UART4RST field.
	RCC_APB1LRSTR_UART4RST       = 0x80000    // Bit UART4RST.
	RCC_APB1LRSTR_UART5RST_Pos   = 0x14       // Position of UART5RST field.
	RCC_APB1LRSTR_UART5RST_Msk   = 0x100000   // Bit mask of UART5RST field.
	RCC_APB1LRSTR_UART5RST       = 0x100000   // Bit UART5RST.
	RCC_APB1LRSTR_I2C1RST_Pos    = 0x15       // Position of I2C1RST field.
	RCC_APB1LRSTR_I2C1RST_Msk    = 0x200000   // Bit mask of I2C1RST field.
	RCC_APB1LRSTR_I2C1RST        = 0x200000   // Bit I2C1RST.
	RCC_APB1LRSTR_I2C2RST_Pos    = 0x16       // Position of I2C2RST field.
	RCC_APB1LRSTR_I2C2RST_Msk    = 0x400000   // Bit mask of I2C2RST field.
	RCC_APB1LRSTR_I2C2RST        = 0x400000   // Bit I2C2RST.
	RCC_APB1LRSTR_I2C3RST_Pos    = 0x17       // Position of I2C3RST field.
	RCC_APB1LRSTR_I2C3RST_Msk    = 0x800000   // Bit mask of I2C3RST field.
	RCC_APB1LRSTR_I2C3RST        = 0x800000   // Bit I2C3RST.
	RCC_APB1LRSTR_CECRST_Pos     = 0x1b       // Position of CECRST field.
	RCC_APB1LRSTR_CECRST_Msk     = 0x8000000  // Bit mask of CECRST field.
	RCC_APB1LRSTR_CECRST         = 0x8000000  // Bit CECRST.
	RCC_APB1LRSTR_DAC12RST_Pos   = 0x1d       // Position of DAC12RST field.
	RCC_APB1LRSTR_DAC12RST_Msk   = 0x20000000 // Bit mask of DAC12RST field.
	RCC_APB1LRSTR_DAC12RST       = 0x20000000 // Bit DAC12RST.
	RCC_APB1LRSTR_USART7RST_Pos  = 0x1e       // Position of USART7RST field.
	RCC_APB1LRSTR_USART7RST_Msk  = 0x40000000 // Bit mask of USART7RST field.
	RCC_APB1LRSTR_USART7RST      = 0x40000000 // Bit USART7RST.
	RCC_APB1LRSTR_USART8RST_Pos  = 0x1f       // Position of USART8RST field.
	RCC_APB1LRSTR_USART8RST_Msk  = 0x80000000 // Bit mask of USART8RST field.
	RCC_APB1LRSTR_USART8RST      = 0x80000000 // Bit USART8RST.

	// APB1HRSTR: RCC APB1 Peripheral Reset           Register
	RCC_APB1HRSTR_CRSRST_Pos   = 0x1   // Position of CRSRST field.
	RCC_APB1HRSTR_CRSRST_Msk   = 0x2   // Bit mask of CRSRST field.
	RCC_APB1HRSTR_CRSRST       = 0x2   // Bit CRSRST.
	RCC_APB1HRSTR_SWPRST_Pos   = 0x2   // Position of SWPRST field.
	RCC_APB1HRSTR_SWPRST_Msk   = 0x4   // Bit mask of SWPRST field.
	RCC_APB1HRSTR_SWPRST       = 0x4   // Bit SWPRST.
	RCC_APB1HRSTR_OPAMPRST_Pos = 0x4   // Position of OPAMPRST field.
	RCC_APB1HRSTR_OPAMPRST_Msk = 0x10  // Bit mask of OPAMPRST field.
	RCC_APB1HRSTR_OPAMPRST     = 0x10  // Bit OPAMPRST.
	RCC_APB1HRSTR_MDIOSRST_Pos = 0x5   // Position of MDIOSRST field.
	RCC_APB1HRSTR_MDIOSRST_Msk = 0x20  // Bit mask of MDIOSRST field.
	RCC_APB1HRSTR_MDIOSRST     = 0x20  // Bit MDIOSRST.
	RCC_APB1HRSTR_FDCANRST_Pos = 0x8   // Position of FDCANRST field.
	RCC_APB1HRSTR_FDCANRST_Msk = 0x100 // Bit mask of FDCANRST field.
	RCC_APB1HRSTR_FDCANRST     = 0x100 // Bit FDCANRST.

	// APB2RSTR: RCC APB2 Peripheral Reset           Register
	RCC_APB2RSTR_TIM1RST_Pos   = 0x0        // Position of TIM1RST field.
	RCC_APB2RSTR_TIM1RST_Msk   = 0x1        // Bit mask of TIM1RST field.
	RCC_APB2RSTR_TIM1RST       = 0x1        // Bit TIM1RST.
	RCC_APB2RSTR_TIM8RST_Pos   = 0x1        // Position of TIM8RST field.
	RCC_APB2RSTR_TIM8RST_Msk   = 0x2        // Bit mask of TIM8RST field.
	RCC_APB2RSTR_TIM8RST       = 0x2        // Bit TIM8RST.
	RCC_APB2RSTR_USART1RST_Pos = 0x4        // Position of USART1RST field.
	RCC_APB2RSTR_USART1RST_Msk = 0x10       // Bit mask of USART1RST field.
	RCC_APB2RSTR_USART1RST     = 0x10       // Bit USART1RST.
	RCC_APB2RSTR_USART6RST_Pos = 0x5        // Position of USART6RST field.
	RCC_APB2RSTR_USART6RST_Msk = 0x20       // Bit mask of USART6RST field.
	RCC_APB2RSTR_USART6RST     = 0x20       // Bit USART6RST.
	RCC_APB2RSTR_SPI1RST_Pos   = 0xc        // Position of SPI1RST field.
	RCC_APB2RSTR_SPI1RST_Msk   = 0x1000     // Bit mask of SPI1RST field.
	RCC_APB2RSTR_SPI1RST       = 0x1000     // Bit SPI1RST.
	RCC_APB2RSTR_SPI4RST_Pos   = 0xd        // Position of SPI4RST field.
	RCC_APB2RSTR_SPI4RST_Msk   = 0x2000     // Bit mask of SPI4RST field.
	RCC_APB2RSTR_SPI4RST       = 0x2000     // Bit SPI4RST.
	RCC_APB2RSTR_TIM15RST_Pos  = 0x10       // Position of TIM15RST field.
	RCC_APB2RSTR_TIM15RST_Msk  = 0x10000    // Bit mask of TIM15RST field.
	RCC_APB2RSTR_TIM15RST      = 0x10000    // Bit TIM15RST.
	RCC_APB2RSTR_TIM16RST_Pos  = 0x11       // Position of TIM16RST field.
	RCC_APB2RSTR_TIM16RST_Msk  = 0x20000    // Bit mask of TIM16RST field.
	RCC_APB2RSTR_TIM16RST      = 0x20000    // Bit TIM16RST.
	RCC_APB2RSTR_TIM17RST_Pos  = 0x12       // Position of TIM17RST field.
	RCC_APB2RSTR_TIM17RST_Msk  = 0x40000    // Bit mask of TIM17RST field.
	RCC_APB2RSTR_TIM17RST      = 0x40000    // Bit TIM17RST.
	RCC_APB2RSTR_SPI5RST_Pos   = 0x14       // Position of SPI5RST field.
	RCC_APB2RSTR_SPI5RST_Msk   = 0x100000   // Bit mask of SPI5RST field.
	RCC_APB2RSTR_SPI5RST       = 0x100000   // Bit SPI5RST.
	RCC_APB2RSTR_SAI1RST_Pos   = 0x16       // Position of SAI1RST field.
	RCC_APB2RSTR_SAI1RST_Msk   = 0x400000   // Bit mask of SAI1RST field.
	RCC_APB2RSTR_SAI1RST       = 0x400000   // Bit SAI1RST.
	RCC_APB2RSTR_SAI2RST_Pos   = 0x17       // Position of SAI2RST field.
	RCC_APB2RSTR_SAI2RST_Msk   = 0x800000   // Bit mask of SAI2RST field.
	RCC_APB2RSTR_SAI2RST       = 0x800000   // Bit SAI2RST.
	RCC_APB2RSTR_SAI3RST_Pos   = 0x18       // Position of SAI3RST field.
	RCC_APB2RSTR_SAI3RST_Msk   = 0x1000000  // Bit mask of SAI3RST field.
	RCC_APB2RSTR_SAI3RST       = 0x1000000  // Bit SAI3RST.
	RCC_APB2RSTR_DFSDM1RST_Pos = 0x1c       // Position of DFSDM1RST field.
	RCC_APB2RSTR_DFSDM1RST_Msk = 0x10000000 // Bit mask of DFSDM1RST field.
	RCC_APB2RSTR_DFSDM1RST     = 0x10000000 // Bit DFSDM1RST.
	RCC_APB2RSTR_HRTIMRST_Pos  = 0x1d       // Position of HRTIMRST field.
	RCC_APB2RSTR_HRTIMRST_Msk  = 0x20000000 // Bit mask of HRTIMRST field.
	RCC_APB2RSTR_HRTIMRST      = 0x20000000 // Bit HRTIMRST.

	// APB4RSTR: RCC APB4 Peripheral Reset           Register
	RCC_APB4RSTR_SYSCFGRST_Pos  = 0x1      // Position of SYSCFGRST field.
	RCC_APB4RSTR_SYSCFGRST_Msk  = 0x2      // Bit mask of SYSCFGRST field.
	RCC_APB4RSTR_SYSCFGRST      = 0x2      // Bit SYSCFGRST.
	RCC_APB4RSTR_LPUART1RST_Pos = 0x3      // Position of LPUART1RST field.
	RCC_APB4RSTR_LPUART1RST_Msk = 0x8      // Bit mask of LPUART1RST field.
	RCC_APB4RSTR_LPUART1RST     = 0x8      // Bit LPUART1RST.
	RCC_APB4RSTR_SPI6RST_Pos    = 0x5      // Position of SPI6RST field.
	RCC_APB4RSTR_SPI6RST_Msk    = 0x20     // Bit mask of SPI6RST field.
	RCC_APB4RSTR_SPI6RST        = 0x20     // Bit SPI6RST.
	RCC_APB4RSTR_I2C4RST_Pos    = 0x7      // Position of I2C4RST field.
	RCC_APB4RSTR_I2C4RST_Msk    = 0x80     // Bit mask of I2C4RST field.
	RCC_APB4RSTR_I2C4RST        = 0x80     // Bit I2C4RST.
	RCC_APB4RSTR_LPTIM2RST_Pos  = 0x9      // Position of LPTIM2RST field.
	RCC_APB4RSTR_LPTIM2RST_Msk  = 0x200    // Bit mask of LPTIM2RST field.
	RCC_APB4RSTR_LPTIM2RST      = 0x200    // Bit LPTIM2RST.
	RCC_APB4RSTR_LPTIM3RST_Pos  = 0xa      // Position of LPTIM3RST field.
	RCC_APB4RSTR_LPTIM3RST_Msk  = 0x400    // Bit mask of LPTIM3RST field.
	RCC_APB4RSTR_LPTIM3RST      = 0x400    // Bit LPTIM3RST.
	RCC_APB4RSTR_LPTIM4RST_Pos  = 0xb      // Position of LPTIM4RST field.
	RCC_APB4RSTR_LPTIM4RST_Msk  = 0x800    // Bit mask of LPTIM4RST field.
	RCC_APB4RSTR_LPTIM4RST      = 0x800    // Bit LPTIM4RST.
	RCC_APB4RSTR_LPTIM5RST_Pos  = 0xc      // Position of LPTIM5RST field.
	RCC_APB4RSTR_LPTIM5RST_Msk  = 0x1000   // Bit mask of LPTIM5RST field.
	RCC_APB4RSTR_LPTIM5RST      = 0x1000   // Bit LPTIM5RST.
	RCC_APB4RSTR_COMP12RST_Pos  = 0xe      // Position of COMP12RST field.
	RCC_APB4RSTR_COMP12RST_Msk  = 0x4000   // Bit mask of COMP12RST field.
	RCC_APB4RSTR_COMP12RST      = 0x4000   // Bit COMP12RST.
	RCC_APB4RSTR_VREFRST_Pos    = 0xf      // Position of VREFRST field.
	RCC_APB4RSTR_VREFRST_Msk    = 0x8000   // Bit mask of VREFRST field.
	RCC_APB4RSTR_VREFRST        = 0x8000   // Bit VREFRST.
	RCC_APB4RSTR_SAI4RST_Pos    = 0x15     // Position of SAI4RST field.
	RCC_APB4RSTR_SAI4RST_Msk    = 0x200000 // Bit mask of SAI4RST field.
	RCC_APB4RSTR_SAI4RST        = 0x200000 // Bit SAI4RST.

	// GCR: RCC Global Control Register
	RCC_GCR_WW1RSC_Pos = 0x0 // Position of WW1RSC field.
	RCC_GCR_WW1RSC_Msk = 0x1 // Bit mask of WW1RSC field.
	RCC_GCR_WW1RSC     = 0x1 // Bit WW1RSC.

	// D3AMR: RCC D3 Autonomous mode           Register
	RCC_D3AMR_BDMAAMEN_Pos    = 0x0        // Position of BDMAAMEN field.
	RCC_D3AMR_BDMAAMEN_Msk    = 0x1        // Bit mask of BDMAAMEN field.
	RCC_D3AMR_BDMAAMEN        = 0x1        // Bit BDMAAMEN.
	RCC_D3AMR_LPUART1AMEN_Pos = 0x3        // Position of LPUART1AMEN field.
	RCC_D3AMR_LPUART1AMEN_Msk = 0x8        // Bit mask of LPUART1AMEN field.
	RCC_D3AMR_LPUART1AMEN     = 0x8        // Bit LPUART1AMEN.
	RCC_D3AMR_SPI6AMEN_Pos    = 0x5        // Position of SPI6AMEN field.
	RCC_D3AMR_SPI6AMEN_Msk    = 0x20       // Bit mask of SPI6AMEN field.
	RCC_D3AMR_SPI6AMEN        = 0x20       // Bit SPI6AMEN.
	RCC_D3AMR_I2C4AMEN_Pos    = 0x7        // Position of I2C4AMEN field.
	RCC_D3AMR_I2C4AMEN_Msk    = 0x80       // Bit mask of I2C4AMEN field.
	RCC_D3AMR_I2C4AMEN        = 0x80       // Bit I2C4AMEN.
	RCC_D3AMR_LPTIM2AMEN_Pos  = 0x9        // Position of LPTIM2AMEN field.
	RCC_D3AMR_LPTIM2AMEN_Msk  = 0x200      // Bit mask of LPTIM2AMEN field.
	RCC_D3AMR_LPTIM2AMEN      = 0x200      // Bit LPTIM2AMEN.
	RCC_D3AMR_LPTIM3AMEN_Pos  = 0xa        // Position of LPTIM3AMEN field.
	RCC_D3AMR_LPTIM3AMEN_Msk  = 0x400      // Bit mask of LPTIM3AMEN field.
	RCC_D3AMR_LPTIM3AMEN      = 0x400      // Bit LPTIM3AMEN.
	RCC_D3AMR_LPTIM4AMEN_Pos  = 0xb        // Position of LPTIM4AMEN field.
	RCC_D3AMR_LPTIM4AMEN_Msk  = 0x800      // Bit mask of LPTIM4AMEN field.
	RCC_D3AMR_LPTIM4AMEN      = 0x800      // Bit LPTIM4AMEN.
	RCC_D3AMR_LPTIM5AMEN_Pos  = 0xc        // Position of LPTIM5AMEN field.
	RCC_D3AMR_LPTIM5AMEN_Msk  = 0x1000     // Bit mask of LPTIM5AMEN field.
	RCC_D3AMR_LPTIM5AMEN      = 0x1000     // Bit LPTIM5AMEN.
	RCC_D3AMR_COMP12AMEN_Pos  = 0xe        // Position of COMP12AMEN field.
	RCC_D3AMR_COMP12AMEN_Msk  = 0x4000     // Bit mask of COMP12AMEN field.
	RCC_D3AMR_COMP12AMEN      = 0x4000     // Bit COMP12AMEN.
	RCC_D3AMR_VREFAMEN_Pos    = 0xf        // Position of VREFAMEN field.
	RCC_D3AMR_VREFAMEN_Msk    = 0x8000     // Bit mask of VREFAMEN field.
	RCC_D3AMR_VREFAMEN        = 0x8000     // Bit VREFAMEN.
	RCC_D3AMR_RTCAMEN_Pos     = 0x10       // Position of RTCAMEN field.
	RCC_D3AMR_RTCAMEN_Msk     = 0x10000    // Bit mask of RTCAMEN field.
	RCC_D3AMR_RTCAMEN         = 0x10000    // Bit RTCAMEN.
	RCC_D3AMR_CRCAMEN_Pos     = 0x13       // Position of CRCAMEN field.
	RCC_D3AMR_CRCAMEN_Msk     = 0x80000    // Bit mask of CRCAMEN field.
	RCC_D3AMR_CRCAMEN         = 0x80000    // Bit CRCAMEN.
	RCC_D3AMR_SAI4AMEN_Pos    = 0x15       // Position of SAI4AMEN field.
	RCC_D3AMR_SAI4AMEN_Msk    = 0x200000   // Bit mask of SAI4AMEN field.
	RCC_D3AMR_SAI4AMEN        = 0x200000   // Bit SAI4AMEN.
	RCC_D3AMR_ADC3AMEN_Pos    = 0x18       // Position of ADC3AMEN field.
	RCC_D3AMR_ADC3AMEN_Msk    = 0x1000000  // Bit mask of ADC3AMEN field.
	RCC_D3AMR_ADC3AMEN        = 0x1000000  // Bit ADC3AMEN.
	RCC_D3AMR_BKPRAMAMEN_Pos  = 0x1c       // Position of BKPRAMAMEN field.
	RCC_D3AMR_BKPRAMAMEN_Msk  = 0x10000000 // Bit mask of BKPRAMAMEN field.
	RCC_D3AMR_BKPRAMAMEN      = 0x10000000 // Bit BKPRAMAMEN.
	RCC_D3AMR_SRAM4AMEN_Pos   = 0x1d       // Position of SRAM4AMEN field.
	RCC_D3AMR_SRAM4AMEN_Msk   = 0x20000000 // Bit mask of SRAM4AMEN field.
	RCC_D3AMR_SRAM4AMEN       = 0x20000000 // Bit SRAM4AMEN.

	// RSR: RCC Reset Status Register
	RCC_RSR_RMVF_Pos      = 0x10       // Position of RMVF field.
	RCC_RSR_RMVF_Msk      = 0x10000    // Bit mask of RMVF field.
	RCC_RSR_RMVF          = 0x10000    // Bit RMVF.
	RCC_RSR_CPURSTF_Pos   = 0x11       // Position of CPURSTF field.
	RCC_RSR_CPURSTF_Msk   = 0x20000    // Bit mask of CPURSTF field.
	RCC_RSR_CPURSTF       = 0x20000    // Bit CPURSTF.
	RCC_RSR_D1RSTF_Pos    = 0x13       // Position of D1RSTF field.
	RCC_RSR_D1RSTF_Msk    = 0x80000    // Bit mask of D1RSTF field.
	RCC_RSR_D1RSTF        = 0x80000    // Bit D1RSTF.
	RCC_RSR_D2RSTF_Pos    = 0x14       // Position of D2RSTF field.
	RCC_RSR_D2RSTF_Msk    = 0x100000   // Bit mask of D2RSTF field.
	RCC_RSR_D2RSTF        = 0x100000   // Bit D2RSTF.
	RCC_RSR_BORRSTF_Pos   = 0x15       // Position of BORRSTF field.
	RCC_RSR_BORRSTF_Msk   = 0x200000   // Bit mask of BORRSTF field.
	RCC_RSR_BORRSTF       = 0x200000   // Bit BORRSTF.
	RCC_RSR_PINRSTF_Pos   = 0x16       // Position of PINRSTF field.
	RCC_RSR_PINRSTF_Msk   = 0x400000   // Bit mask of PINRSTF field.
	RCC_RSR_PINRSTF       = 0x400000   // Bit PINRSTF.
	RCC_RSR_PORRSTF_Pos   = 0x17       // Position of PORRSTF field.
	RCC_RSR_PORRSTF_Msk   = 0x800000   // Bit mask of PORRSTF field.
	RCC_RSR_PORRSTF       = 0x800000   // Bit PORRSTF.
	RCC_RSR_SFTRSTF_Pos   = 0x18       // Position of SFTRSTF field.
	RCC_RSR_SFTRSTF_Msk   = 0x1000000  // Bit mask of SFTRSTF field.
	RCC_RSR_SFTRSTF       = 0x1000000  // Bit SFTRSTF.
	RCC_RSR_IWDG1RSTF_Pos = 0x1a       // Position of IWDG1RSTF field.
	RCC_RSR_IWDG1RSTF_Msk = 0x4000000  // Bit mask of IWDG1RSTF field.
	RCC_RSR_IWDG1RSTF     = 0x4000000  // Bit IWDG1RSTF.
	RCC_RSR_WWDG1RSTF_Pos = 0x1c       // Position of WWDG1RSTF field.
	RCC_RSR_WWDG1RSTF_Msk = 0x10000000 // Bit mask of WWDG1RSTF field.
	RCC_RSR_WWDG1RSTF     = 0x10000000 // Bit WWDG1RSTF.
	RCC_RSR_LPWRRSTF_Pos  = 0x1e       // Position of LPWRRSTF field.
	RCC_RSR_LPWRRSTF_Msk  = 0x40000000 // Bit mask of LPWRRSTF field.
	RCC_RSR_LPWRRSTF      = 0x40000000 // Bit LPWRRSTF.

	// AHB3ENR: RCC AHB3 Clock Register
	RCC_AHB3ENR_MDMAEN_Pos   = 0x0     // Position of MDMAEN field.
	RCC_AHB3ENR_MDMAEN_Msk   = 0x1     // Bit mask of MDMAEN field.
	RCC_AHB3ENR_MDMAEN       = 0x1     // Bit MDMAEN.
	RCC_AHB3ENR_DMA2DEN_Pos  = 0x4     // Position of DMA2DEN field.
	RCC_AHB3ENR_DMA2DEN_Msk  = 0x10    // Bit mask of DMA2DEN field.
	RCC_AHB3ENR_DMA2DEN      = 0x10    // Bit DMA2DEN.
	RCC_AHB3ENR_JPGDECEN_Pos = 0x5     // Position of JPGDECEN field.
	RCC_AHB3ENR_JPGDECEN_Msk = 0x20    // Bit mask of JPGDECEN field.
	RCC_AHB3ENR_JPGDECEN     = 0x20    // Bit JPGDECEN.
	RCC_AHB3ENR_FMCEN_Pos    = 0xc     // Position of FMCEN field.
	RCC_AHB3ENR_FMCEN_Msk    = 0x1000  // Bit mask of FMCEN field.
	RCC_AHB3ENR_FMCEN        = 0x1000  // Bit FMCEN.
	RCC_AHB3ENR_QSPIEN_Pos   = 0xe     // Position of QSPIEN field.
	RCC_AHB3ENR_QSPIEN_Msk   = 0x4000  // Bit mask of QSPIEN field.
	RCC_AHB3ENR_QSPIEN       = 0x4000  // Bit QSPIEN.
	RCC_AHB3ENR_SDMMC1EN_Pos = 0x10    // Position of SDMMC1EN field.
	RCC_AHB3ENR_SDMMC1EN_Msk = 0x10000 // Bit mask of SDMMC1EN field.
	RCC_AHB3ENR_SDMMC1EN     = 0x10000 // Bit SDMMC1EN.

	// AHB1ENR: RCC AHB1 Clock Register
	RCC_AHB1ENR_DMA1EN_Pos          = 0x0        // Position of DMA1EN field.
	RCC_AHB1ENR_DMA1EN_Msk          = 0x1        // Bit mask of DMA1EN field.
	RCC_AHB1ENR_DMA1EN              = 0x1        // Bit DMA1EN.
	RCC_AHB1ENR_DMA2EN_Pos          = 0x1        // Position of DMA2EN field.
	RCC_AHB1ENR_DMA2EN_Msk          = 0x2        // Bit mask of DMA2EN field.
	RCC_AHB1ENR_DMA2EN              = 0x2        // Bit DMA2EN.
	RCC_AHB1ENR_ADC12EN_Pos         = 0x5        // Position of ADC12EN field.
	RCC_AHB1ENR_ADC12EN_Msk         = 0x20       // Bit mask of ADC12EN field.
	RCC_AHB1ENR_ADC12EN             = 0x20       // Bit ADC12EN.
	RCC_AHB1ENR_ETH1MACEN_Pos       = 0xf        // Position of ETH1MACEN field.
	RCC_AHB1ENR_ETH1MACEN_Msk       = 0x8000     // Bit mask of ETH1MACEN field.
	RCC_AHB1ENR_ETH1MACEN           = 0x8000     // Bit ETH1MACEN.
	RCC_AHB1ENR_ETH1TXEN_Pos        = 0x10       // Position of ETH1TXEN field.
	RCC_AHB1ENR_ETH1TXEN_Msk        = 0x10000    // Bit mask of ETH1TXEN field.
	RCC_AHB1ENR_ETH1TXEN            = 0x10000    // Bit ETH1TXEN.
	RCC_AHB1ENR_ETH1RXEN_Pos        = 0x11       // Position of ETH1RXEN field.
	RCC_AHB1ENR_ETH1RXEN_Msk        = 0x20000    // Bit mask of ETH1RXEN field.
	RCC_AHB1ENR_ETH1RXEN            = 0x20000    // Bit ETH1RXEN.
	RCC_AHB1ENR_USB2OTGHSULPIEN_Pos = 0x12       // Position of USB2OTGHSULPIEN field.
	RCC_AHB1ENR_USB2OTGHSULPIEN_Msk = 0x40000    // Bit mask of USB2OTGHSULPIEN field.
	RCC_AHB1ENR_USB2OTGHSULPIEN     = 0x40000    // Bit USB2OTGHSULPIEN.
	RCC_AHB1ENR_USB1OTGEN_Pos       = 0x19       // Position of USB1OTGEN field.
	RCC_AHB1ENR_USB1OTGEN_Msk       = 0x2000000  // Bit mask of USB1OTGEN field.
	RCC_AHB1ENR_USB1OTGEN           = 0x2000000  // Bit USB1OTGEN.
	RCC_AHB1ENR_USB1ULPIEN_Pos      = 0x1a       // Position of USB1ULPIEN field.
	RCC_AHB1ENR_USB1ULPIEN_Msk      = 0x4000000  // Bit mask of USB1ULPIEN field.
	RCC_AHB1ENR_USB1ULPIEN          = 0x4000000  // Bit USB1ULPIEN.
	RCC_AHB1ENR_USB2OTGEN_Pos       = 0x1b       // Position of USB2OTGEN field.
	RCC_AHB1ENR_USB2OTGEN_Msk       = 0x8000000  // Bit mask of USB2OTGEN field.
	RCC_AHB1ENR_USB2OTGEN           = 0x8000000  // Bit USB2OTGEN.
	RCC_AHB1ENR_USB2ULPIEN_Pos      = 0x1c       // Position of USB2ULPIEN field.
	RCC_AHB1ENR_USB2ULPIEN_Msk      = 0x10000000 // Bit mask of USB2ULPIEN field.
	RCC_AHB1ENR_USB2ULPIEN          = 0x10000000 // Bit USB2ULPIEN.

	// AHB2ENR: RCC AHB2 Clock Register
	RCC_AHB2ENR_CAMITFEN_Pos = 0x0        // Position of CAMITFEN field.
	RCC_AHB2ENR_CAMITFEN_Msk = 0x1        // Bit mask of CAMITFEN field.
	RCC_AHB2ENR_CAMITFEN     = 0x1        // Bit CAMITFEN.
	RCC_AHB2ENR_CRYPTEN_Pos  = 0x4        // Position of CRYPTEN field.
	RCC_AHB2ENR_CRYPTEN_Msk  = 0x10       // Bit mask of CRYPTEN field.
	RCC_AHB2ENR_CRYPTEN      = 0x10       // Bit CRYPTEN.
	RCC_AHB2ENR_HASHEN_Pos   = 0x5        // Position of HASHEN field.
	RCC_AHB2ENR_HASHEN_Msk   = 0x20       // Bit mask of HASHEN field.
	RCC_AHB2ENR_HASHEN       = 0x20       // Bit HASHEN.
	RCC_AHB2ENR_RNGEN_Pos    = 0x6        // Position of RNGEN field.
	RCC_AHB2ENR_RNGEN_Msk    = 0x40       // Bit mask of RNGEN field.
	RCC_AHB2ENR_RNGEN        = 0x40       // Bit RNGEN.
	RCC_AHB2ENR_SDMMC2EN_Pos = 0x9        // Position of SDMMC2EN field.
	RCC_AHB2ENR_SDMMC2EN_Msk = 0x200      // Bit mask of SDMMC2EN field.
	RCC_AHB2ENR_SDMMC2EN     = 0x200      // Bit SDMMC2EN.
	RCC_AHB2ENR_SRAM1EN_Pos  = 0x1d       // Position of SRAM1EN field.
	RCC_AHB2ENR_SRAM1EN_Msk  = 0x20000000 // Bit mask of SRAM1EN field.
	RCC_AHB2ENR_SRAM1EN      = 0x20000000 // Bit SRAM1EN.
	RCC_AHB2ENR_SRAM2EN_Pos  = 0x1e       // Position of SRAM2EN field.
	RCC_AHB2ENR_SRAM2EN_Msk  = 0x40000000 // Bit mask of SRAM2EN field.
	RCC_AHB2ENR_SRAM2EN      = 0x40000000 // Bit SRAM2EN.
	RCC_AHB2ENR_SRAM3EN_Pos  = 0x1f       // Position of SRAM3EN field.
	RCC_AHB2ENR_SRAM3EN_Msk  = 0x80000000 // Bit mask of SRAM3EN field.
	RCC_AHB2ENR_SRAM3EN      = 0x80000000 // Bit SRAM3EN.

	// AHB4ENR: RCC AHB4 Clock Register
	RCC_AHB4ENR_GPIOAEN_Pos  = 0x0        // Position of GPIOAEN field.
	RCC_AHB4ENR_GPIOAEN_Msk  = 0x1        // Bit mask of GPIOAEN field.
	RCC_AHB4ENR_GPIOAEN      = 0x1        // Bit GPIOAEN.
	RCC_AHB4ENR_GPIOBEN_Pos  = 0x1        // Position of GPIOBEN field.
	RCC_AHB4ENR_GPIOBEN_Msk  = 0x2        // Bit mask of GPIOBEN field.
	RCC_AHB4ENR_GPIOBEN      = 0x2        // Bit GPIOBEN.
	RCC_AHB4ENR_GPIOCEN_Pos  = 0x2        // Position of GPIOCEN field.
	RCC_AHB4ENR_GPIOCEN_Msk  = 0x4        // Bit mask of GPIOCEN field.
	RCC_AHB4ENR_GPIOCEN      = 0x4        // Bit GPIOCEN.
	RCC_AHB4ENR_GPIODEN_Pos  = 0x3        // Position of GPIODEN field.
	RCC_AHB4ENR_GPIODEN_Msk  = 0x8        // Bit mask of GPIODEN field.
	RCC_AHB4ENR_GPIODEN      = 0x8        // Bit GPIODEN.
	RCC_AHB4ENR_GPIOEEN_Pos  = 0x4        // Position of GPIOEEN field.
	RCC_AHB4ENR_GPIOEEN_Msk  = 0x10       // Bit mask of GPIOEEN field.
	RCC_AHB4ENR_GPIOEEN      = 0x10       // Bit GPIOEEN.
	RCC_AHB4ENR_GPIOFEN_Pos  = 0x5        // Position of GPIOFEN field.
	RCC_AHB4ENR_GPIOFEN_Msk  = 0x20       // Bit mask of GPIOFEN field.
	RCC_AHB4ENR_GPIOFEN      = 0x20       // Bit GPIOFEN.
	RCC_AHB4ENR_GPIOGEN_Pos  = 0x6        // Position of GPIOGEN field.
	RCC_AHB4ENR_GPIOGEN_Msk  = 0x40       // Bit mask of GPIOGEN field.
	RCC_AHB4ENR_GPIOGEN      = 0x40       // Bit GPIOGEN.
	RCC_AHB4ENR_GPIOHEN_Pos  = 0x7        // Position of GPIOHEN field.
	RCC_AHB4ENR_GPIOHEN_Msk  = 0x80       // Bit mask of GPIOHEN field.
	RCC_AHB4ENR_GPIOHEN      = 0x80       // Bit GPIOHEN.
	RCC_AHB4ENR_GPIOIEN_Pos  = 0x8        // Position of GPIOIEN field.
	RCC_AHB4ENR_GPIOIEN_Msk  = 0x100      // Bit mask of GPIOIEN field.
	RCC_AHB4ENR_GPIOIEN      = 0x100      // Bit GPIOIEN.
	RCC_AHB4ENR_GPIOJEN_Pos  = 0x9        // Position of GPIOJEN field.
	RCC_AHB4ENR_GPIOJEN_Msk  = 0x200      // Bit mask of GPIOJEN field.
	RCC_AHB4ENR_GPIOJEN      = 0x200      // Bit GPIOJEN.
	RCC_AHB4ENR_GPIOKEN_Pos  = 0xa        // Position of GPIOKEN field.
	RCC_AHB4ENR_GPIOKEN_Msk  = 0x400      // Bit mask of GPIOKEN field.
	RCC_AHB4ENR_GPIOKEN      = 0x400      // Bit GPIOKEN.
	RCC_AHB4ENR_CRCEN_Pos    = 0x13       // Position of CRCEN field.
	RCC_AHB4ENR_CRCEN_Msk    = 0x80000    // Bit mask of CRCEN field.
	RCC_AHB4ENR_CRCEN        = 0x80000    // Bit CRCEN.
	RCC_AHB4ENR_BDMAEN_Pos   = 0x15       // Position of BDMAEN field.
	RCC_AHB4ENR_BDMAEN_Msk   = 0x200000   // Bit mask of BDMAEN field.
	RCC_AHB4ENR_BDMAEN       = 0x200000   // Bit BDMAEN.
	RCC_AHB4ENR_ADC3EN_Pos   = 0x18       // Position of ADC3EN field.
	RCC_AHB4ENR_ADC3EN_Msk   = 0x1000000  // Bit mask of ADC3EN field.
	RCC_AHB4ENR_ADC3EN       = 0x1000000  // Bit ADC3EN.
	RCC_AHB4ENR_HSEMEN_Pos   = 0x19       // Position of HSEMEN field.
	RCC_AHB4ENR_HSEMEN_Msk   = 0x2000000  // Bit mask of HSEMEN field.
	RCC_AHB4ENR_HSEMEN       = 0x2000000  // Bit HSEMEN.
	RCC_AHB4ENR_BKPRAMEN_Pos = 0x1c       // Position of BKPRAMEN field.
	RCC_AHB4ENR_BKPRAMEN_Msk = 0x10000000 // Bit mask of BKPRAMEN field.
	RCC_AHB4ENR_BKPRAMEN     = 0x10000000 // Bit BKPRAMEN.

	// APB3ENR: RCC APB3 Clock Register
	RCC_APB3ENR_LTDCEN_Pos  = 0x3  // Position of LTDCEN field.
	RCC_APB3ENR_LTDCEN_Msk  = 0x8  // Bit mask of LTDCEN field.
	RCC_APB3ENR_LTDCEN      = 0x8  // Bit LTDCEN.
	RCC_APB3ENR_WWDG1EN_Pos = 0x6  // Position of WWDG1EN field.
	RCC_APB3ENR_WWDG1EN_Msk = 0x40 // Bit mask of WWDG1EN field.
	RCC_APB3ENR_WWDG1EN     = 0x40 // Bit WWDG1EN.

	// APB1LENR: RCC APB1 Clock Register
	RCC_APB1LENR_TIM2EN_Pos    = 0x0        // Position of TIM2EN field.
	RCC_APB1LENR_TIM2EN_Msk    = 0x1        // Bit mask of TIM2EN field.
	RCC_APB1LENR_TIM2EN        = 0x1        // Bit TIM2EN.
	RCC_APB1LENR_TIM3EN_Pos    = 0x1        // Position of TIM3EN field.
	RCC_APB1LENR_TIM3EN_Msk    = 0x2        // Bit mask of TIM3EN field.
	RCC_APB1LENR_TIM3EN        = 0x2        // Bit TIM3EN.
	RCC_APB1LENR_TIM4EN_Pos    = 0x2        // Position of TIM4EN field.
	RCC_APB1LENR_TIM4EN_Msk    = 0x4        // Bit mask of TIM4EN field.
	RCC_APB1LENR_TIM4EN        = 0x4        // Bit TIM4EN.
	RCC_APB1LENR_TIM5EN_Pos    = 0x3        // Position of TIM5EN field.
	RCC_APB1LENR_TIM5EN_Msk    = 0x8        // Bit mask of TIM5EN field.
	RCC_APB1LENR_TIM5EN        = 0x8        // Bit TIM5EN.
	RCC_APB1LENR_TIM6EN_Pos    = 0x4        // Position of TIM6EN field.
	RCC_APB1LENR_TIM6EN_Msk    = 0x10       // Bit mask of TIM6EN field.
	RCC_APB1LENR_TIM6EN        = 0x10       // Bit TIM6EN.
	RCC_APB1LENR_TIM7EN_Pos    = 0x5        // Position of TIM7EN field.
	RCC_APB1LENR_TIM7EN_Msk    = 0x20       // Bit mask of TIM7EN field.
	RCC_APB1LENR_TIM7EN        = 0x20       // Bit TIM7EN.
	RCC_APB1LENR_TIM12EN_Pos   = 0x6        // Position of TIM12EN field.
	RCC_APB1LENR_TIM12EN_Msk   = 0x40       // Bit mask of TIM12EN field.
	RCC_APB1LENR_TIM12EN       = 0x40       // Bit TIM12EN.
	RCC_APB1LENR_TIM13EN_Pos   = 0x7        // Position of TIM13EN field.
	RCC_APB1LENR_TIM13EN_Msk   = 0x80       // Bit mask of TIM13EN field.
	RCC_APB1LENR_TIM13EN       = 0x80       // Bit TIM13EN.
	RCC_APB1LENR_TIM14EN_Pos   = 0x8        // Position of TIM14EN field.
	RCC_APB1LENR_TIM14EN_Msk   = 0x100      // Bit mask of TIM14EN field.
	RCC_APB1LENR_TIM14EN       = 0x100      // Bit TIM14EN.
	RCC_APB1LENR_LPTIM1EN_Pos  = 0x9        // Position of LPTIM1EN field.
	RCC_APB1LENR_LPTIM1EN_Msk  = 0x200      // Bit mask of LPTIM1EN field.
	RCC_APB1LENR_LPTIM1EN      = 0x200      // Bit LPTIM1EN.
	RCC_APB1LENR_SPI2EN_Pos    = 0xe        // Position of SPI2EN field.
	RCC_APB1LENR_SPI2EN_Msk    = 0x4000     // Bit mask of SPI2EN field.
	RCC_APB1LENR_SPI2EN        = 0x4000     // Bit SPI2EN.
	RCC_APB1LENR_SPI3EN_Pos    = 0xf        // Position of SPI3EN field.
	RCC_APB1LENR_SPI3EN_Msk    = 0x8000     // Bit mask of SPI3EN field.
	RCC_APB1LENR_SPI3EN        = 0x8000     // Bit SPI3EN.
	RCC_APB1LENR_SPDIFRXEN_Pos = 0x10       // Position of SPDIFRXEN field.
	RCC_APB1LENR_SPDIFRXEN_Msk = 0x10000    // Bit mask of SPDIFRXEN field.
	RCC_APB1LENR_SPDIFRXEN     = 0x10000    // Bit SPDIFRXEN.
	RCC_APB1LENR_USART2EN_Pos  = 0x11       // Position of USART2EN field.
	RCC_APB1LENR_USART2EN_Msk  = 0x20000    // Bit mask of USART2EN field.
	RCC_APB1LENR_USART2EN      = 0x20000    // Bit USART2EN.
	RCC_APB1LENR_USART3EN_Pos  = 0x12       // Position of USART3EN field.
	RCC_APB1LENR_USART3EN_Msk  = 0x40000    // Bit mask of USART3EN field.
	RCC_APB1LENR_USART3EN      = 0x40000    // Bit USART3EN.
	RCC_APB1LENR_UART4EN_Pos   = 0x13       // Position of UART4EN field.
	RCC_APB1LENR_UART4EN_Msk   = 0x80000    // Bit mask of UART4EN field.
	RCC_APB1LENR_UART4EN       = 0x80000    // Bit UART4EN.
	RCC_APB1LENR_UART5EN_Pos   = 0x14       // Position of UART5EN field.
	RCC_APB1LENR_UART5EN_Msk   = 0x100000   // Bit mask of UART5EN field.
	RCC_APB1LENR_UART5EN       = 0x100000   // Bit UART5EN.
	RCC_APB1LENR_I2C1EN_Pos    = 0x15       // Position of I2C1EN field.
	RCC_APB1LENR_I2C1EN_Msk    = 0x200000   // Bit mask of I2C1EN field.
	RCC_APB1LENR_I2C1EN        = 0x200000   // Bit I2C1EN.
	RCC_APB1LENR_I2C2EN_Pos    = 0x16       // Position of I2C2EN field.
	RCC_APB1LENR_I2C2EN_Msk    = 0x400000   // Bit mask of I2C2EN field.
	RCC_APB1LENR_I2C2EN        = 0x400000   // Bit I2C2EN.
	RCC_APB1LENR_I2C3EN_Pos    = 0x17       // Position of I2C3EN field.
	RCC_APB1LENR_I2C3EN_Msk    = 0x800000   // Bit mask of I2C3EN field.
	RCC_APB1LENR_I2C3EN        = 0x800000   // Bit I2C3EN.
	RCC_APB1LENR_CECEN_Pos     = 0x1b       // Position of CECEN field.
	RCC_APB1LENR_CECEN_Msk     = 0x8000000  // Bit mask of CECEN field.
	RCC_APB1LENR_CECEN         = 0x8000000  // Bit CECEN.
	RCC_APB1LENR_DAC12EN_Pos   = 0x1d       // Position of DAC12EN field.
	RCC_APB1LENR_DAC12EN_Msk   = 0x20000000 // Bit mask of DAC12EN field.
	RCC_APB1LENR_DAC12EN       = 0x20000000 // Bit DAC12EN.
	RCC_APB1LENR_USART7EN_Pos  = 0x1e       // Position of USART7EN field.
	RCC_APB1LENR_USART7EN_Msk  = 0x40000000 // Bit mask of USART7EN field.
	RCC_APB1LENR_USART7EN      = 0x40000000 // Bit USART7EN.
	RCC_APB1LENR_USART8EN_Pos  = 0x1f       // Position of USART8EN field.
	RCC_APB1LENR_USART8EN_Msk  = 0x80000000 // Bit mask of USART8EN field.
	RCC_APB1LENR_USART8EN      = 0x80000000 // Bit USART8EN.

	// APB1HENR: RCC APB1 Clock Register
	RCC_APB1HENR_CRSEN_Pos   = 0x1   // Position of CRSEN field.
	RCC_APB1HENR_CRSEN_Msk   = 0x2   // Bit mask of CRSEN field.
	RCC_APB1HENR_CRSEN       = 0x2   // Bit CRSEN.
	RCC_APB1HENR_SWPEN_Pos   = 0x2   // Position of SWPEN field.
	RCC_APB1HENR_SWPEN_Msk   = 0x4   // Bit mask of SWPEN field.
	RCC_APB1HENR_SWPEN       = 0x4   // Bit SWPEN.
	RCC_APB1HENR_OPAMPEN_Pos = 0x4   // Position of OPAMPEN field.
	RCC_APB1HENR_OPAMPEN_Msk = 0x10  // Bit mask of OPAMPEN field.
	RCC_APB1HENR_OPAMPEN     = 0x10  // Bit OPAMPEN.
	RCC_APB1HENR_MDIOSEN_Pos = 0x5   // Position of MDIOSEN field.
	RCC_APB1HENR_MDIOSEN_Msk = 0x20  // Bit mask of MDIOSEN field.
	RCC_APB1HENR_MDIOSEN     = 0x20  // Bit MDIOSEN.
	RCC_APB1HENR_FDCANEN_Pos = 0x8   // Position of FDCANEN field.
	RCC_APB1HENR_FDCANEN_Msk = 0x100 // Bit mask of FDCANEN field.
	RCC_APB1HENR_FDCANEN     = 0x100 // Bit FDCANEN.

	// APB2ENR: RCC APB2 Clock Register
	RCC_APB2ENR_TIM1EN_Pos   = 0x0        // Position of TIM1EN field.
	RCC_APB2ENR_TIM1EN_Msk   = 0x1        // Bit mask of TIM1EN field.
	RCC_APB2ENR_TIM1EN       = 0x1        // Bit TIM1EN.
	RCC_APB2ENR_TIM8EN_Pos   = 0x1        // Position of TIM8EN field.
	RCC_APB2ENR_TIM8EN_Msk   = 0x2        // Bit mask of TIM8EN field.
	RCC_APB2ENR_TIM8EN       = 0x2        // Bit TIM8EN.
	RCC_APB2ENR_USART1EN_Pos = 0x4        // Position of USART1EN field.
	RCC_APB2ENR_USART1EN_Msk = 0x10       // Bit mask of USART1EN field.
	RCC_APB2ENR_USART1EN     = 0x10       // Bit USART1EN.
	RCC_APB2ENR_USART6EN_Pos = 0x5        // Position of USART6EN field.
	RCC_APB2ENR_USART6EN_Msk = 0x20       // Bit mask of USART6EN field.
	RCC_APB2ENR_USART6EN     = 0x20       // Bit USART6EN.
	RCC_APB2ENR_SPI1EN_Pos   = 0xc        // Position of SPI1EN field.
	RCC_APB2ENR_SPI1EN_Msk   = 0x1000     // Bit mask of SPI1EN field.
	RCC_APB2ENR_SPI1EN       = 0x1000     // Bit SPI1EN.
	RCC_APB2ENR_SPI4EN_Pos   = 0xd        // Position of SPI4EN field.
	RCC_APB2ENR_SPI4EN_Msk   = 0x2000     // Bit mask of SPI4EN field.
	RCC_APB2ENR_SPI4EN       = 0x2000     // Bit SPI4EN.
	RCC_APB2ENR_TIM16EN_Pos  = 0x11       // Position of TIM16EN field.
	RCC_APB2ENR_TIM16EN_Msk  = 0x20000    // Bit mask of TIM16EN field.
	RCC_APB2ENR_TIM16EN      = 0x20000    // Bit TIM16EN.
	RCC_APB2ENR_TIM15EN_Pos  = 0x10       // Position of TIM15EN field.
	RCC_APB2ENR_TIM15EN_Msk  = 0x10000    // Bit mask of TIM15EN field.
	RCC_APB2ENR_TIM15EN      = 0x10000    // Bit TIM15EN.
	RCC_APB2ENR_TIM17EN_Pos  = 0x12       // Position of TIM17EN field.
	RCC_APB2ENR_TIM17EN_Msk  = 0x40000    // Bit mask of TIM17EN field.
	RCC_APB2ENR_TIM17EN      = 0x40000    // Bit TIM17EN.
	RCC_APB2ENR_SPI5EN_Pos   = 0x14       // Position of SPI5EN field.
	RCC_APB2ENR_SPI5EN_Msk   = 0x100000   // Bit mask of SPI5EN field.
	RCC_APB2ENR_SPI5EN       = 0x100000   // Bit SPI5EN.
	RCC_APB2ENR_SAI1EN_Pos   = 0x16       // Position of SAI1EN field.
	RCC_APB2ENR_SAI1EN_Msk   = 0x400000   // Bit mask of SAI1EN field.
	RCC_APB2ENR_SAI1EN       = 0x400000   // Bit SAI1EN.
	RCC_APB2ENR_SAI2EN_Pos   = 0x17       // Position of SAI2EN field.
	RCC_APB2ENR_SAI2EN_Msk   = 0x800000   // Bit mask of SAI2EN field.
	RCC_APB2ENR_SAI2EN       = 0x800000   // Bit SAI2EN.
	RCC_APB2ENR_SAI3EN_Pos   = 0x18       // Position of SAI3EN field.
	RCC_APB2ENR_SAI3EN_Msk   = 0x1000000  // Bit mask of SAI3EN field.
	RCC_APB2ENR_SAI3EN       = 0x1000000  // Bit SAI3EN.
	RCC_APB2ENR_DFSDM1EN_Pos = 0x1c       // Position of DFSDM1EN field.
	RCC_APB2ENR_DFSDM1EN_Msk = 0x10000000 // Bit mask of DFSDM1EN field.
	RCC_APB2ENR_DFSDM1EN     = 0x10000000 // Bit DFSDM1EN.
	RCC_APB2ENR_HRTIMEN_Pos  = 0x1d       // Position of HRTIMEN field.
	RCC_APB2ENR_HRTIMEN_Msk  = 0x20000000 // Bit mask of HRTIMEN field.
	RCC_APB2ENR_HRTIMEN      = 0x20000000 // Bit HRTIMEN.

	// APB4ENR: RCC APB4 Clock Register
	RCC_APB4ENR_SYSCFGEN_Pos  = 0x1      // Position of SYSCFGEN field.
	RCC_APB4ENR_SYSCFGEN_Msk  = 0x2      // Bit mask of SYSCFGEN field.
	RCC_APB4ENR_SYSCFGEN      = 0x2      // Bit SYSCFGEN.
	RCC_APB4ENR_LPUART1EN_Pos = 0x3      // Position of LPUART1EN field.
	RCC_APB4ENR_LPUART1EN_Msk = 0x8      // Bit mask of LPUART1EN field.
	RCC_APB4ENR_LPUART1EN     = 0x8      // Bit LPUART1EN.
	RCC_APB4ENR_SPI6EN_Pos    = 0x5      // Position of SPI6EN field.
	RCC_APB4ENR_SPI6EN_Msk    = 0x20     // Bit mask of SPI6EN field.
	RCC_APB4ENR_SPI6EN        = 0x20     // Bit SPI6EN.
	RCC_APB4ENR_I2C4EN_Pos    = 0x7      // Position of I2C4EN field.
	RCC_APB4ENR_I2C4EN_Msk    = 0x80     // Bit mask of I2C4EN field.
	RCC_APB4ENR_I2C4EN        = 0x80     // Bit I2C4EN.
	RCC_APB4ENR_LPTIM2EN_Pos  = 0x9      // Position of LPTIM2EN field.
	RCC_APB4ENR_LPTIM2EN_Msk  = 0x200    // Bit mask of LPTIM2EN field.
	RCC_APB4ENR_LPTIM2EN      = 0x200    // Bit LPTIM2EN.
	RCC_APB4ENR_LPTIM3EN_Pos  = 0xa      // Position of LPTIM3EN field.
	RCC_APB4ENR_LPTIM3EN_Msk  = 0x400    // Bit mask of LPTIM3EN field.
	RCC_APB4ENR_LPTIM3EN      = 0x400    // Bit LPTIM3EN.
	RCC_APB4ENR_LPTIM4EN_Pos  = 0xb      // Position of LPTIM4EN field.
	RCC_APB4ENR_LPTIM4EN_Msk  = 0x800    // Bit mask of LPTIM4EN field.
	RCC_APB4ENR_LPTIM4EN      = 0x800    // Bit LPTIM4EN.
	RCC_APB4ENR_LPTIM5EN_Pos  = 0xc      // Position of LPTIM5EN field.
	RCC_APB4ENR_LPTIM5EN_Msk  = 0x1000   // Bit mask of LPTIM5EN field.
	RCC_APB4ENR_LPTIM5EN      = 0x1000   // Bit LPTIM5EN.
	RCC_APB4ENR_COMP12EN_Pos  = 0xe      // Position of COMP12EN field.
	RCC_APB4ENR_COMP12EN_Msk  = 0x4000   // Bit mask of COMP12EN field.
	RCC_APB4ENR_COMP12EN      = 0x4000   // Bit COMP12EN.
	RCC_APB4ENR_VREFEN_Pos    = 0xf      // Position of VREFEN field.
	RCC_APB4ENR_VREFEN_Msk    = 0x8000   // Bit mask of VREFEN field.
	RCC_APB4ENR_VREFEN        = 0x8000   // Bit VREFEN.
	RCC_APB4ENR_RTCAPBEN_Pos  = 0x10     // Position of RTCAPBEN field.
	RCC_APB4ENR_RTCAPBEN_Msk  = 0x10000  // Bit mask of RTCAPBEN field.
	RCC_APB4ENR_RTCAPBEN      = 0x10000  // Bit RTCAPBEN.
	RCC_APB4ENR_SAI4EN_Pos    = 0x15     // Position of SAI4EN field.
	RCC_APB4ENR_SAI4EN_Msk    = 0x200000 // Bit mask of SAI4EN field.
	RCC_APB4ENR_SAI4EN        = 0x200000 // Bit SAI4EN.

	// AHB3LPENR: RCC AHB3 Sleep Clock Register
	RCC_AHB3LPENR_MDMALPEN_Pos    = 0x0        // Position of MDMALPEN field.
	RCC_AHB3LPENR_MDMALPEN_Msk    = 0x1        // Bit mask of MDMALPEN field.
	RCC_AHB3LPENR_MDMALPEN        = 0x1        // Bit MDMALPEN.
	RCC_AHB3LPENR_DMA2DLPEN_Pos   = 0x4        // Position of DMA2DLPEN field.
	RCC_AHB3LPENR_DMA2DLPEN_Msk   = 0x10       // Bit mask of DMA2DLPEN field.
	RCC_AHB3LPENR_DMA2DLPEN       = 0x10       // Bit DMA2DLPEN.
	RCC_AHB3LPENR_JPGDECLPEN_Pos  = 0x5        // Position of JPGDECLPEN field.
	RCC_AHB3LPENR_JPGDECLPEN_Msk  = 0x20       // Bit mask of JPGDECLPEN field.
	RCC_AHB3LPENR_JPGDECLPEN      = 0x20       // Bit JPGDECLPEN.
	RCC_AHB3LPENR_FLASHLPEN_Pos   = 0x8        // Position of FLASHLPEN field.
	RCC_AHB3LPENR_FLASHLPEN_Msk   = 0x100      // Bit mask of FLASHLPEN field.
	RCC_AHB3LPENR_FLASHLPEN       = 0x100      // Bit FLASHLPEN.
	RCC_AHB3LPENR_FMCLPEN_Pos     = 0xc        // Position of FMCLPEN field.
	RCC_AHB3LPENR_FMCLPEN_Msk     = 0x1000     // Bit mask of FMCLPEN field.
	RCC_AHB3LPENR_FMCLPEN         = 0x1000     // Bit FMCLPEN.
	RCC_AHB3LPENR_QSPILPEN_Pos    = 0xe        // Position of QSPILPEN field.
	RCC_AHB3LPENR_QSPILPEN_Msk    = 0x4000     // Bit mask of QSPILPEN field.
	RCC_AHB3LPENR_QSPILPEN        = 0x4000     // Bit QSPILPEN.
	RCC_AHB3LPENR_SDMMC1LPEN_Pos  = 0x10       // Position of SDMMC1LPEN field.
	RCC_AHB3LPENR_SDMMC1LPEN_Msk  = 0x10000    // Bit mask of SDMMC1LPEN field.
	RCC_AHB3LPENR_SDMMC1LPEN      = 0x10000    // Bit SDMMC1LPEN.
	RCC_AHB3LPENR_D1DTCM1LPEN_Pos = 0x1c       // Position of D1DTCM1LPEN field.
	RCC_AHB3LPENR_D1DTCM1LPEN_Msk = 0x10000000 // Bit mask of D1DTCM1LPEN field.
	RCC_AHB3LPENR_D1DTCM1LPEN     = 0x10000000 // Bit D1DTCM1LPEN.
	RCC_AHB3LPENR_DTCM2LPEN_Pos   = 0x1d       // Position of DTCM2LPEN field.
	RCC_AHB3LPENR_DTCM2LPEN_Msk   = 0x20000000 // Bit mask of DTCM2LPEN field.
	RCC_AHB3LPENR_DTCM2LPEN       = 0x20000000 // Bit DTCM2LPEN.
	RCC_AHB3LPENR_ITCMLPEN_Pos    = 0x1e       // Position of ITCMLPEN field.
	RCC_AHB3LPENR_ITCMLPEN_Msk    = 0x40000000 // Bit mask of ITCMLPEN field.
	RCC_AHB3LPENR_ITCMLPEN        = 0x40000000 // Bit ITCMLPEN.
	RCC_AHB3LPENR_AXISRAMLPEN_Pos = 0x1f       // Position of AXISRAMLPEN field.
	RCC_AHB3LPENR_AXISRAMLPEN_Msk = 0x80000000 // Bit mask of AXISRAMLPEN field.
	RCC_AHB3LPENR_AXISRAMLPEN     = 0x80000000 // Bit AXISRAMLPEN.

	// AHB1LPENR: RCC AHB1 Sleep Clock Register
	RCC_AHB1LPENR_DMA1LPEN_Pos          = 0x0        // Position of DMA1LPEN field.
	RCC_AHB1LPENR_DMA1LPEN_Msk          = 0x1        // Bit mask of DMA1LPEN field.
	RCC_AHB1LPENR_DMA1LPEN              = 0x1        // Bit DMA1LPEN.
	RCC_AHB1LPENR_DMA2LPEN_Pos          = 0x1        // Position of DMA2LPEN field.
	RCC_AHB1LPENR_DMA2LPEN_Msk          = 0x2        // Bit mask of DMA2LPEN field.
	RCC_AHB1LPENR_DMA2LPEN              = 0x2        // Bit DMA2LPEN.
	RCC_AHB1LPENR_ADC12LPEN_Pos         = 0x5        // Position of ADC12LPEN field.
	RCC_AHB1LPENR_ADC12LPEN_Msk         = 0x20       // Bit mask of ADC12LPEN field.
	RCC_AHB1LPENR_ADC12LPEN             = 0x20       // Bit ADC12LPEN.
	RCC_AHB1LPENR_ETH1MACLPEN_Pos       = 0xf        // Position of ETH1MACLPEN field.
	RCC_AHB1LPENR_ETH1MACLPEN_Msk       = 0x8000     // Bit mask of ETH1MACLPEN field.
	RCC_AHB1LPENR_ETH1MACLPEN           = 0x8000     // Bit ETH1MACLPEN.
	RCC_AHB1LPENR_ETH1TXLPEN_Pos        = 0x10       // Position of ETH1TXLPEN field.
	RCC_AHB1LPENR_ETH1TXLPEN_Msk        = 0x10000    // Bit mask of ETH1TXLPEN field.
	RCC_AHB1LPENR_ETH1TXLPEN            = 0x10000    // Bit ETH1TXLPEN.
	RCC_AHB1LPENR_ETH1RXLPEN_Pos        = 0x11       // Position of ETH1RXLPEN field.
	RCC_AHB1LPENR_ETH1RXLPEN_Msk        = 0x20000    // Bit mask of ETH1RXLPEN field.
	RCC_AHB1LPENR_ETH1RXLPEN            = 0x20000    // Bit ETH1RXLPEN.
	RCC_AHB1LPENR_USB1OTGHSLPEN_Pos     = 0x19       // Position of USB1OTGHSLPEN field.
	RCC_AHB1LPENR_USB1OTGHSLPEN_Msk     = 0x2000000  // Bit mask of USB1OTGHSLPEN field.
	RCC_AHB1LPENR_USB1OTGHSLPEN         = 0x2000000  // Bit USB1OTGHSLPEN.
	RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos = 0x1a       // Position of USB1OTGHSULPILPEN field.
	RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk = 0x4000000  // Bit mask of USB1OTGHSULPILPEN field.
	RCC_AHB1LPENR_USB1OTGHSULPILPEN     = 0x4000000  // Bit USB1OTGHSULPILPEN.
	RCC_AHB1LPENR_USB2OTGHSLPEN_Pos     = 0x1b       // Position of USB2OTGHSLPEN field.
	RCC_AHB1LPENR_USB2OTGHSLPEN_Msk     = 0x8000000  // Bit mask of USB2OTGHSLPEN field.
	RCC_AHB1LPENR_USB2OTGHSLPEN         = 0x8000000  // Bit USB2OTGHSLPEN.
	RCC_AHB1LPENR_USB2OTGHSULPILPEN_Pos = 0x1c       // Position of USB2OTGHSULPILPEN field.
	RCC_AHB1LPENR_USB2OTGHSULPILPEN_Msk = 0x10000000 // Bit mask of USB2OTGHSULPILPEN field.
	RCC_AHB1LPENR_USB2OTGHSULPILPEN     = 0x10000000 // Bit USB2OTGHSULPILPEN.

	// AHB2LPENR: RCC AHB2 Sleep Clock Register
	RCC_AHB2LPENR_CAMITFLPEN_Pos = 0x0        // Position of CAMITFLPEN field.
	RCC_AHB2LPENR_CAMITFLPEN_Msk = 0x1        // Bit mask of CAMITFLPEN field.
	RCC_AHB2LPENR_CAMITFLPEN     = 0x1        // Bit CAMITFLPEN.
	RCC_AHB2LPENR_CRYPTLPEN_Pos  = 0x4        // Position of CRYPTLPEN field.
	RCC_AHB2LPENR_CRYPTLPEN_Msk  = 0x10       // Bit mask of CRYPTLPEN field.
	RCC_AHB2LPENR_CRYPTLPEN      = 0x10       // Bit CRYPTLPEN.
	RCC_AHB2LPENR_HASHLPEN_Pos   = 0x5        // Position of HASHLPEN field.
	RCC_AHB2LPENR_HASHLPEN_Msk   = 0x20       // Bit mask of HASHLPEN field.
	RCC_AHB2LPENR_HASHLPEN       = 0x20       // Bit HASHLPEN.
	RCC_AHB2LPENR_SDMMC2LPEN_Pos = 0x9        // Position of SDMMC2LPEN field.
	RCC_AHB2LPENR_SDMMC2LPEN_Msk = 0x200      // Bit mask of SDMMC2LPEN field.
	RCC_AHB2LPENR_SDMMC2LPEN     = 0x200      // Bit SDMMC2LPEN.
	RCC_AHB2LPENR_RNGLPEN_Pos    = 0x6        // Position of RNGLPEN field.
	RCC_AHB2LPENR_RNGLPEN_Msk    = 0x40       // Bit mask of RNGLPEN field.
	RCC_AHB2LPENR_RNGLPEN        = 0x40       // Bit RNGLPEN.
	RCC_AHB2LPENR_SRAM1LPEN_Pos  = 0x1d       // Position of SRAM1LPEN field.
	RCC_AHB2LPENR_SRAM1LPEN_Msk  = 0x20000000 // Bit mask of SRAM1LPEN field.
	RCC_AHB2LPENR_SRAM1LPEN      = 0x20000000 // Bit SRAM1LPEN.
	RCC_AHB2LPENR_SRAM2LPEN_Pos  = 0x1e       // Position of SRAM2LPEN field.
	RCC_AHB2LPENR_SRAM2LPEN_Msk  = 0x40000000 // Bit mask of SRAM2LPEN field.
	RCC_AHB2LPENR_SRAM2LPEN      = 0x40000000 // Bit SRAM2LPEN.
	RCC_AHB2LPENR_SRAM3LPEN_Pos  = 0x1f       // Position of SRAM3LPEN field.
	RCC_AHB2LPENR_SRAM3LPEN_Msk  = 0x80000000 // Bit mask of SRAM3LPEN field.
	RCC_AHB2LPENR_SRAM3LPEN      = 0x80000000 // Bit SRAM3LPEN.

	// AHB4LPENR: RCC AHB4 Sleep Clock Register
	RCC_AHB4LPENR_GPIOALPEN_Pos  = 0x0        // Position of GPIOALPEN field.
	RCC_AHB4LPENR_GPIOALPEN_Msk  = 0x1        // Bit mask of GPIOALPEN field.
	RCC_AHB4LPENR_GPIOALPEN      = 0x1        // Bit GPIOALPEN.
	RCC_AHB4LPENR_GPIOBLPEN_Pos  = 0x1        // Position of GPIOBLPEN field.
	RCC_AHB4LPENR_GPIOBLPEN_Msk  = 0x2        // Bit mask of GPIOBLPEN field.
	RCC_AHB4LPENR_GPIOBLPEN      = 0x2        // Bit GPIOBLPEN.
	RCC_AHB4LPENR_GPIOCLPEN_Pos  = 0x2        // Position of GPIOCLPEN field.
	RCC_AHB4LPENR_GPIOCLPEN_Msk  = 0x4        // Bit mask of GPIOCLPEN field.
	RCC_AHB4LPENR_GPIOCLPEN      = 0x4        // Bit GPIOCLPEN.
	RCC_AHB4LPENR_GPIODLPEN_Pos  = 0x3        // Position of GPIODLPEN field.
	RCC_AHB4LPENR_GPIODLPEN_Msk  = 0x8        // Bit mask of GPIODLPEN field.
	RCC_AHB4LPENR_GPIODLPEN      = 0x8        // Bit GPIODLPEN.
	RCC_AHB4LPENR_GPIOELPEN_Pos  = 0x4        // Position of GPIOELPEN field.
	RCC_AHB4LPENR_GPIOELPEN_Msk  = 0x10       // Bit mask of GPIOELPEN field.
	RCC_AHB4LPENR_GPIOELPEN      = 0x10       // Bit GPIOELPEN.
	RCC_AHB4LPENR_GPIOFLPEN_Pos  = 0x5        // Position of GPIOFLPEN field.
	RCC_AHB4LPENR_GPIOFLPEN_Msk  = 0x20       // Bit mask of GPIOFLPEN field.
	RCC_AHB4LPENR_GPIOFLPEN      = 0x20       // Bit GPIOFLPEN.
	RCC_AHB4LPENR_GPIOGLPEN_Pos  = 0x6        // Position of GPIOGLPEN field.
	RCC_AHB4LPENR_GPIOGLPEN_Msk  = 0x40       // Bit mask of GPIOGLPEN field.
	RCC_AHB4LPENR_GPIOGLPEN      = 0x40       // Bit GPIOGLPEN.
	RCC_AHB4LPENR_GPIOHLPEN_Pos  = 0x7        // Position of GPIOHLPEN field.
	RCC_AHB4LPENR_GPIOHLPEN_Msk  = 0x80       // Bit mask of GPIOHLPEN field.
	RCC_AHB4LPENR_GPIOHLPEN      = 0x80       // Bit GPIOHLPEN.
	RCC_AHB4LPENR_GPIOILPEN_Pos  = 0x8        // Position of GPIOILPEN field.
	RCC_AHB4LPENR_GPIOILPEN_Msk  = 0x100      // Bit mask of GPIOILPEN field.
	RCC_AHB4LPENR_GPIOILPEN      = 0x100      // Bit GPIOILPEN.
	RCC_AHB4LPENR_GPIOJLPEN_Pos  = 0x9        // Position of GPIOJLPEN field.
	RCC_AHB4LPENR_GPIOJLPEN_Msk  = 0x200      // Bit mask of GPIOJLPEN field.
	RCC_AHB4LPENR_GPIOJLPEN      = 0x200      // Bit GPIOJLPEN.
	RCC_AHB4LPENR_GPIOKLPEN_Pos  = 0xa        // Position of GPIOKLPEN field.
	RCC_AHB4LPENR_GPIOKLPEN_Msk  = 0x400      // Bit mask of GPIOKLPEN field.
	RCC_AHB4LPENR_GPIOKLPEN      = 0x400      // Bit GPIOKLPEN.
	RCC_AHB4LPENR_CRCLPEN_Pos    = 0x13       // Position of CRCLPEN field.
	RCC_AHB4LPENR_CRCLPEN_Msk    = 0x80000    // Bit mask of CRCLPEN field.
	RCC_AHB4LPENR_CRCLPEN        = 0x80000    // Bit CRCLPEN.
	RCC_AHB4LPENR_BDMALPEN_Pos   = 0x15       // Position of BDMALPEN field.
	RCC_AHB4LPENR_BDMALPEN_Msk   = 0x200000   // Bit mask of BDMALPEN field.
	RCC_AHB4LPENR_BDMALPEN       = 0x200000   // Bit BDMALPEN.
	RCC_AHB4LPENR_ADC3LPEN_Pos   = 0x18       // Position of ADC3LPEN field.
	RCC_AHB4LPENR_ADC3LPEN_Msk   = 0x1000000  // Bit mask of ADC3LPEN field.
	RCC_AHB4LPENR_ADC3LPEN       = 0x1000000  // Bit ADC3LPEN.
	RCC_AHB4LPENR_BKPRAMLPEN_Pos = 0x1c       // Position of BKPRAMLPEN field.
	RCC_AHB4LPENR_BKPRAMLPEN_Msk = 0x10000000 // Bit mask of BKPRAMLPEN field.
	RCC_AHB4LPENR_BKPRAMLPEN     = 0x10000000 // Bit BKPRAMLPEN.
	RCC_AHB4LPENR_SRAM4LPEN_Pos  = 0x1d       // Position of SRAM4LPEN field.
	RCC_AHB4LPENR_SRAM4LPEN_Msk  = 0x20000000 // Bit mask of SRAM4LPEN field.
	RCC_AHB4LPENR_SRAM4LPEN      = 0x20000000 // Bit SRAM4LPEN.

	// APB3LPENR: RCC APB3 Sleep Clock Register
	RCC_APB3LPENR_LTDCLPEN_Pos  = 0x3  // Position of LTDCLPEN field.
	RCC_APB3LPENR_LTDCLPEN_Msk  = 0x8  // Bit mask of LTDCLPEN field.
	RCC_APB3LPENR_LTDCLPEN      = 0x8  // Bit LTDCLPEN.
	RCC_APB3LPENR_WWDG1LPEN_Pos = 0x6  // Position of WWDG1LPEN field.
	RCC_APB3LPENR_WWDG1LPEN_Msk = 0x40 // Bit mask of WWDG1LPEN field.
	RCC_APB3LPENR_WWDG1LPEN     = 0x40 // Bit WWDG1LPEN.

	// APB1LLPENR: RCC APB1 Low Sleep Clock           Register
	RCC_APB1LLPENR_TIM2LPEN_Pos    = 0x0        // Position of TIM2LPEN field.
	RCC_APB1LLPENR_TIM2LPEN_Msk    = 0x1        // Bit mask of TIM2LPEN field.
	RCC_APB1LLPENR_TIM2LPEN        = 0x1        // Bit TIM2LPEN.
	RCC_APB1LLPENR_TIM3LPEN_Pos    = 0x1        // Position of TIM3LPEN field.
	RCC_APB1LLPENR_TIM3LPEN_Msk    = 0x2        // Bit mask of TIM3LPEN field.
	RCC_APB1LLPENR_TIM3LPEN        = 0x2        // Bit TIM3LPEN.
	RCC_APB1LLPENR_TIM4LPEN_Pos    = 0x2        // Position of TIM4LPEN field.
	RCC_APB1LLPENR_TIM4LPEN_Msk    = 0x4        // Bit mask of TIM4LPEN field.
	RCC_APB1LLPENR_TIM4LPEN        = 0x4        // Bit TIM4LPEN.
	RCC_APB1LLPENR_TIM5LPEN_Pos    = 0x3        // Position of TIM5LPEN field.
	RCC_APB1LLPENR_TIM5LPEN_Msk    = 0x8        // Bit mask of TIM5LPEN field.
	RCC_APB1LLPENR_TIM5LPEN        = 0x8        // Bit TIM5LPEN.
	RCC_APB1LLPENR_TIM6LPEN_Pos    = 0x4        // Position of TIM6LPEN field.
	RCC_APB1LLPENR_TIM6LPEN_Msk    = 0x10       // Bit mask of TIM6LPEN field.
	RCC_APB1LLPENR_TIM6LPEN        = 0x10       // Bit TIM6LPEN.
	RCC_APB1LLPENR_TIM7LPEN_Pos    = 0x5        // Position of TIM7LPEN field.
	RCC_APB1LLPENR_TIM7LPEN_Msk    = 0x20       // Bit mask of TIM7LPEN field.
	RCC_APB1LLPENR_TIM7LPEN        = 0x20       // Bit TIM7LPEN.
	RCC_APB1LLPENR_TIM12LPEN_Pos   = 0x6        // Position of TIM12LPEN field.
	RCC_APB1LLPENR_TIM12LPEN_Msk   = 0x40       // Bit mask of TIM12LPEN field.
	RCC_APB1LLPENR_TIM12LPEN       = 0x40       // Bit TIM12LPEN.
	RCC_APB1LLPENR_TIM13LPEN_Pos   = 0x7        // Position of TIM13LPEN field.
	RCC_APB1LLPENR_TIM13LPEN_Msk   = 0x80       // Bit mask of TIM13LPEN field.
	RCC_APB1LLPENR_TIM13LPEN       = 0x80       // Bit TIM13LPEN.
	RCC_APB1LLPENR_TIM14LPEN_Pos   = 0x8        // Position of TIM14LPEN field.
	RCC_APB1LLPENR_TIM14LPEN_Msk   = 0x100      // Bit mask of TIM14LPEN field.
	RCC_APB1LLPENR_TIM14LPEN       = 0x100      // Bit TIM14LPEN.
	RCC_APB1LLPENR_LPTIM1LPEN_Pos  = 0x9        // Position of LPTIM1LPEN field.
	RCC_APB1LLPENR_LPTIM1LPEN_Msk  = 0x200      // Bit mask of LPTIM1LPEN field.
	RCC_APB1LLPENR_LPTIM1LPEN      = 0x200      // Bit LPTIM1LPEN.
	RCC_APB1LLPENR_SPI2LPEN_Pos    = 0xe        // Position of SPI2LPEN field.
	RCC_APB1LLPENR_SPI2LPEN_Msk    = 0x4000     // Bit mask of SPI2LPEN field.
	RCC_APB1LLPENR_SPI2LPEN        = 0x4000     // Bit SPI2LPEN.
	RCC_APB1LLPENR_SPI3LPEN_Pos    = 0xf        // Position of SPI3LPEN field.
	RCC_APB1LLPENR_SPI3LPEN_Msk    = 0x8000     // Bit mask of SPI3LPEN field.
	RCC_APB1LLPENR_SPI3LPEN        = 0x8000     // Bit SPI3LPEN.
	RCC_APB1LLPENR_SPDIFRXLPEN_Pos = 0x10       // Position of SPDIFRXLPEN field.
	RCC_APB1LLPENR_SPDIFRXLPEN_Msk = 0x10000    // Bit mask of SPDIFRXLPEN field.
	RCC_APB1LLPENR_SPDIFRXLPEN     = 0x10000    // Bit SPDIFRXLPEN.
	RCC_APB1LLPENR_USART2LPEN_Pos  = 0x11       // Position of USART2LPEN field.
	RCC_APB1LLPENR_USART2LPEN_Msk  = 0x20000    // Bit mask of USART2LPEN field.
	RCC_APB1LLPENR_USART2LPEN      = 0x20000    // Bit USART2LPEN.
	RCC_APB1LLPENR_USART3LPEN_Pos  = 0x12       // Position of USART3LPEN field.
	RCC_APB1LLPENR_USART3LPEN_Msk  = 0x40000    // Bit mask of USART3LPEN field.
	RCC_APB1LLPENR_USART3LPEN      = 0x40000    // Bit USART3LPEN.
	RCC_APB1LLPENR_UART4LPEN_Pos   = 0x13       // Position of UART4LPEN field.
	RCC_APB1LLPENR_UART4LPEN_Msk   = 0x80000    // Bit mask of UART4LPEN field.
	RCC_APB1LLPENR_UART4LPEN       = 0x80000    // Bit UART4LPEN.
	RCC_APB1LLPENR_UART5LPEN_Pos   = 0x14       // Position of UART5LPEN field.
	RCC_APB1LLPENR_UART5LPEN_Msk   = 0x100000   // Bit mask of UART5LPEN field.
	RCC_APB1LLPENR_UART5LPEN       = 0x100000   // Bit UART5LPEN.
	RCC_APB1LLPENR_I2C1LPEN_Pos    = 0x15       // Position of I2C1LPEN field.
	RCC_APB1LLPENR_I2C1LPEN_Msk    = 0x200000   // Bit mask of I2C1LPEN field.
	RCC_APB1LLPENR_I2C1LPEN        = 0x200000   // Bit I2C1LPEN.
	RCC_APB1LLPENR_I2C2LPEN_Pos    = 0x16       // Position of I2C2LPEN field.
	RCC_APB1LLPENR_I2C2LPEN_Msk    = 0x400000   // Bit mask of I2C2LPEN field.
	RCC_APB1LLPENR_I2C2LPEN        = 0x400000   // Bit I2C2LPEN.
	RCC_APB1LLPENR_I2C3LPEN_Pos    = 0x17       // Position of I2C3LPEN field.
	RCC_APB1LLPENR_I2C3LPEN_Msk    = 0x800000   // Bit mask of I2C3LPEN field.
	RCC_APB1LLPENR_I2C3LPEN        = 0x800000   // Bit I2C3LPEN.
	RCC_APB1LLPENR_HDMICECLPEN_Pos = 0x1b       // Position of HDMICECLPEN field.
	RCC_APB1LLPENR_HDMICECLPEN_Msk = 0x8000000  // Bit mask of HDMICECLPEN field.
	RCC_APB1LLPENR_HDMICECLPEN     = 0x8000000  // Bit HDMICECLPEN.
	RCC_APB1LLPENR_DAC12LPEN_Pos   = 0x1d       // Position of DAC12LPEN field.
	RCC_APB1LLPENR_DAC12LPEN_Msk   = 0x20000000 // Bit mask of DAC12LPEN field.
	RCC_APB1LLPENR_DAC12LPEN       = 0x20000000 // Bit DAC12LPEN.
	RCC_APB1LLPENR_USART7LPEN_Pos  = 0x1e       // Position of USART7LPEN field.
	RCC_APB1LLPENR_USART7LPEN_Msk  = 0x40000000 // Bit mask of USART7LPEN field.
	RCC_APB1LLPENR_USART7LPEN      = 0x40000000 // Bit USART7LPEN.
	RCC_APB1LLPENR_USART8LPEN_Pos  = 0x1f       // Position of USART8LPEN field.
	RCC_APB1LLPENR_USART8LPEN_Msk  = 0x80000000 // Bit mask of USART8LPEN field.
	RCC_APB1LLPENR_USART8LPEN      = 0x80000000 // Bit USART8LPEN.

	// APB1HLPENR: RCC APB1 High Sleep Clock           Register
	RCC_APB1HLPENR_CRSLPEN_Pos   = 0x1   // Position of CRSLPEN field.
	RCC_APB1HLPENR_CRSLPEN_Msk   = 0x2   // Bit mask of CRSLPEN field.
	RCC_APB1HLPENR_CRSLPEN       = 0x2   // Bit CRSLPEN.
	RCC_APB1HLPENR_SWPLPEN_Pos   = 0x2   // Position of SWPLPEN field.
	RCC_APB1HLPENR_SWPLPEN_Msk   = 0x4   // Bit mask of SWPLPEN field.
	RCC_APB1HLPENR_SWPLPEN       = 0x4   // Bit SWPLPEN.
	RCC_APB1HLPENR_OPAMPLPEN_Pos = 0x4   // Position of OPAMPLPEN field.
	RCC_APB1HLPENR_OPAMPLPEN_Msk = 0x10  // Bit mask of OPAMPLPEN field.
	RCC_APB1HLPENR_OPAMPLPEN     = 0x10  // Bit OPAMPLPEN.
	RCC_APB1HLPENR_MDIOSLPEN_Pos = 0x5   // Position of MDIOSLPEN field.
	RCC_APB1HLPENR_MDIOSLPEN_Msk = 0x20  // Bit mask of MDIOSLPEN field.
	RCC_APB1HLPENR_MDIOSLPEN     = 0x20  // Bit MDIOSLPEN.
	RCC_APB1HLPENR_FDCANLPEN_Pos = 0x8   // Position of FDCANLPEN field.
	RCC_APB1HLPENR_FDCANLPEN_Msk = 0x100 // Bit mask of FDCANLPEN field.
	RCC_APB1HLPENR_FDCANLPEN     = 0x100 // Bit FDCANLPEN.

	// APB2LPENR: RCC APB2 Sleep Clock Register
	RCC_APB2LPENR_TIM1LPEN_Pos   = 0x0        // Position of TIM1LPEN field.
	RCC_APB2LPENR_TIM1LPEN_Msk   = 0x1        // Bit mask of TIM1LPEN field.
	RCC_APB2LPENR_TIM1LPEN       = 0x1        // Bit TIM1LPEN.
	RCC_APB2LPENR_TIM8LPEN_Pos   = 0x1        // Position of TIM8LPEN field.
	RCC_APB2LPENR_TIM8LPEN_Msk   = 0x2        // Bit mask of TIM8LPEN field.
	RCC_APB2LPENR_TIM8LPEN       = 0x2        // Bit TIM8LPEN.
	RCC_APB2LPENR_USART1LPEN_Pos = 0x4        // Position of USART1LPEN field.
	RCC_APB2LPENR_USART1LPEN_Msk = 0x10       // Bit mask of USART1LPEN field.
	RCC_APB2LPENR_USART1LPEN     = 0x10       // Bit USART1LPEN.
	RCC_APB2LPENR_USART6LPEN_Pos = 0x5        // Position of USART6LPEN field.
	RCC_APB2LPENR_USART6LPEN_Msk = 0x20       // Bit mask of USART6LPEN field.
	RCC_APB2LPENR_USART6LPEN     = 0x20       // Bit USART6LPEN.
	RCC_APB2LPENR_SPI1LPEN_Pos   = 0xc        // Position of SPI1LPEN field.
	RCC_APB2LPENR_SPI1LPEN_Msk   = 0x1000     // Bit mask of SPI1LPEN field.
	RCC_APB2LPENR_SPI1LPEN       = 0x1000     // Bit SPI1LPEN.
	RCC_APB2LPENR_SPI4LPEN_Pos   = 0xd        // Position of SPI4LPEN field.
	RCC_APB2LPENR_SPI4LPEN_Msk   = 0x2000     // Bit mask of SPI4LPEN field.
	RCC_APB2LPENR_SPI4LPEN       = 0x2000     // Bit SPI4LPEN.
	RCC_APB2LPENR_TIM15LPEN_Pos  = 0x10       // Position of TIM15LPEN field.
	RCC_APB2LPENR_TIM15LPEN_Msk  = 0x10000    // Bit mask of TIM15LPEN field.
	RCC_APB2LPENR_TIM15LPEN      = 0x10000    // Bit TIM15LPEN.
	RCC_APB2LPENR_TIM16LPEN_Pos  = 0x11       // Position of TIM16LPEN field.
	RCC_APB2LPENR_TIM16LPEN_Msk  = 0x20000    // Bit mask of TIM16LPEN field.
	RCC_APB2LPENR_TIM16LPEN      = 0x20000    // Bit TIM16LPEN.
	RCC_APB2LPENR_TIM17LPEN_Pos  = 0x12       // Position of TIM17LPEN field.
	RCC_APB2LPENR_TIM17LPEN_Msk  = 0x40000    // Bit mask of TIM17LPEN field.
	RCC_APB2LPENR_TIM17LPEN      = 0x40000    // Bit TIM17LPEN.
	RCC_APB2LPENR_SPI5LPEN_Pos   = 0x14       // Position of SPI5LPEN field.
	RCC_APB2LPENR_SPI5LPEN_Msk   = 0x100000   // Bit mask of SPI5LPEN field.
	RCC_APB2LPENR_SPI5LPEN       = 0x100000   // Bit SPI5LPEN.
	RCC_APB2LPENR_SAI1LPEN_Pos   = 0x16       // Position of SAI1LPEN field.
	RCC_APB2LPENR_SAI1LPEN_Msk   = 0x400000   // Bit mask of SAI1LPEN field.
	RCC_APB2LPENR_SAI1LPEN       = 0x400000   // Bit SAI1LPEN.
	RCC_APB2LPENR_SAI2LPEN_Pos   = 0x17       // Position of SAI2LPEN field.
	RCC_APB2LPENR_SAI2LPEN_Msk   = 0x800000   // Bit mask of SAI2LPEN field.
	RCC_APB2LPENR_SAI2LPEN       = 0x800000   // Bit SAI2LPEN.
	RCC_APB2LPENR_SAI3LPEN_Pos   = 0x18       // Position of SAI3LPEN field.
	RCC_APB2LPENR_SAI3LPEN_Msk   = 0x1000000  // Bit mask of SAI3LPEN field.
	RCC_APB2LPENR_SAI3LPEN       = 0x1000000  // Bit SAI3LPEN.
	RCC_APB2LPENR_DFSDM1LPEN_Pos = 0x1c       // Position of DFSDM1LPEN field.
	RCC_APB2LPENR_DFSDM1LPEN_Msk = 0x10000000 // Bit mask of DFSDM1LPEN field.
	RCC_APB2LPENR_DFSDM1LPEN     = 0x10000000 // Bit DFSDM1LPEN.
	RCC_APB2LPENR_HRTIMLPEN_Pos  = 0x1d       // Position of HRTIMLPEN field.
	RCC_APB2LPENR_HRTIMLPEN_Msk  = 0x20000000 // Bit mask of HRTIMLPEN field.
	RCC_APB2LPENR_HRTIMLPEN      = 0x20000000 // Bit HRTIMLPEN.

	// APB4LPENR: RCC APB4 Sleep Clock Register
	RCC_APB4LPENR_SYSCFGLPEN_Pos  = 0x1      // Position of SYSCFGLPEN field.
	RCC_APB4LPENR_SYSCFGLPEN_Msk  = 0x2      // Bit mask of SYSCFGLPEN field.
	RCC_APB4LPENR_SYSCFGLPEN      = 0x2      // Bit SYSCFGLPEN.
	RCC_APB4LPENR_LPUART1LPEN_Pos = 0x3      // Position of LPUART1LPEN field.
	RCC_APB4LPENR_LPUART1LPEN_Msk = 0x8      // Bit mask of LPUART1LPEN field.
	RCC_APB4LPENR_LPUART1LPEN     = 0x8      // Bit LPUART1LPEN.
	RCC_APB4LPENR_SPI6LPEN_Pos    = 0x5      // Position of SPI6LPEN field.
	RCC_APB4LPENR_SPI6LPEN_Msk    = 0x20     // Bit mask of SPI6LPEN field.
	RCC_APB4LPENR_SPI6LPEN        = 0x20     // Bit SPI6LPEN.
	RCC_APB4LPENR_I2C4LPEN_Pos    = 0x7      // Position of I2C4LPEN field.
	RCC_APB4LPENR_I2C4LPEN_Msk    = 0x80     // Bit mask of I2C4LPEN field.
	RCC_APB4LPENR_I2C4LPEN        = 0x80     // Bit I2C4LPEN.
	RCC_APB4LPENR_LPTIM2LPEN_Pos  = 0x9      // Position of LPTIM2LPEN field.
	RCC_APB4LPENR_LPTIM2LPEN_Msk  = 0x200    // Bit mask of LPTIM2LPEN field.
	RCC_APB4LPENR_LPTIM2LPEN      = 0x200    // Bit LPTIM2LPEN.
	RCC_APB4LPENR_LPTIM3LPEN_Pos  = 0xa      // Position of LPTIM3LPEN field.
	RCC_APB4LPENR_LPTIM3LPEN_Msk  = 0x400    // Bit mask of LPTIM3LPEN field.
	RCC_APB4LPENR_LPTIM3LPEN      = 0x400    // Bit LPTIM3LPEN.
	RCC_APB4LPENR_LPTIM4LPEN_Pos  = 0xb      // Position of LPTIM4LPEN field.
	RCC_APB4LPENR_LPTIM4LPEN_Msk  = 0x800    // Bit mask of LPTIM4LPEN field.
	RCC_APB4LPENR_LPTIM4LPEN      = 0x800    // Bit LPTIM4LPEN.
	RCC_APB4LPENR_LPTIM5LPEN_Pos  = 0xc      // Position of LPTIM5LPEN field.
	RCC_APB4LPENR_LPTIM5LPEN_Msk  = 0x1000   // Bit mask of LPTIM5LPEN field.
	RCC_APB4LPENR_LPTIM5LPEN      = 0x1000   // Bit LPTIM5LPEN.
	RCC_APB4LPENR_COMP12LPEN_Pos  = 0xe      // Position of COMP12LPEN field.
	RCC_APB4LPENR_COMP12LPEN_Msk  = 0x4000   // Bit mask of COMP12LPEN field.
	RCC_APB4LPENR_COMP12LPEN      = 0x4000   // Bit COMP12LPEN.
	RCC_APB4LPENR_VREFLPEN_Pos    = 0xf      // Position of VREFLPEN field.
	RCC_APB4LPENR_VREFLPEN_Msk    = 0x8000   // Bit mask of VREFLPEN field.
	RCC_APB4LPENR_VREFLPEN        = 0x8000   // Bit VREFLPEN.
	RCC_APB4LPENR_RTCAPBLPEN_Pos  = 0x10     // Position of RTCAPBLPEN field.
	RCC_APB4LPENR_RTCAPBLPEN_Msk  = 0x10000  // Bit mask of RTCAPBLPEN field.
	RCC_APB4LPENR_RTCAPBLPEN      = 0x10000  // Bit RTCAPBLPEN.
	RCC_APB4LPENR_SAI4LPEN_Pos    = 0x15     // Position of SAI4LPEN field.
	RCC_APB4LPENR_SAI4LPEN_Msk    = 0x200000 // Bit mask of SAI4LPEN field.
	RCC_APB4LPENR_SAI4LPEN        = 0x200000 // Bit SAI4LPEN.

	// C1_RSR: RCC Reset Status Register
	RCC_C1_RSR_RMVF_Pos      = 0x10       // Position of RMVF field.
	RCC_C1_RSR_RMVF_Msk      = 0x10000    // Bit mask of RMVF field.
	RCC_C1_RSR_RMVF          = 0x10000    // Bit RMVF.
	RCC_C1_RSR_CPURSTF_Pos   = 0x11       // Position of CPURSTF field.
	RCC_C1_RSR_CPURSTF_Msk   = 0x20000    // Bit mask of CPURSTF field.
	RCC_C1_RSR_CPURSTF       = 0x20000    // Bit CPURSTF.
	RCC_C1_RSR_D1RSTF_Pos    = 0x13       // Position of D1RSTF field.
	RCC_C1_RSR_D1RSTF_Msk    = 0x80000    // Bit mask of D1RSTF field.
	RCC_C1_RSR_D1RSTF        = 0x80000    // Bit D1RSTF.
	RCC_C1_RSR_D2RSTF_Pos    = 0x14       // Position of D2RSTF field.
	RCC_C1_RSR_D2RSTF_Msk    = 0x100000   // Bit mask of D2RSTF field.
	RCC_C1_RSR_D2RSTF        = 0x100000   // Bit D2RSTF.
	RCC_C1_RSR_BORRSTF_Pos   = 0x15       // Position of BORRSTF field.
	RCC_C1_RSR_BORRSTF_Msk   = 0x200000   // Bit mask of BORRSTF field.
	RCC_C1_RSR_BORRSTF       = 0x200000   // Bit BORRSTF.
	RCC_C1_RSR_PINRSTF_Pos   = 0x16       // Position of PINRSTF field.
	RCC_C1_RSR_PINRSTF_Msk   = 0x400000   // Bit mask of PINRSTF field.
	RCC_C1_RSR_PINRSTF       = 0x400000   // Bit PINRSTF.
	RCC_C1_RSR_PORRSTF_Pos   = 0x17       // Position of PORRSTF field.
	RCC_C1_RSR_PORRSTF_Msk   = 0x800000   // Bit mask of PORRSTF field.
	RCC_C1_RSR_PORRSTF       = 0x800000   // Bit PORRSTF.
	RCC_C1_RSR_SFTRSTF_Pos   = 0x18       // Position of SFTRSTF field.
	RCC_C1_RSR_SFTRSTF_Msk   = 0x1000000  // Bit mask of SFTRSTF field.
	RCC_C1_RSR_SFTRSTF       = 0x1000000  // Bit SFTRSTF.
	RCC_C1_RSR_IWDG1RSTF_Pos = 0x1a       // Position of IWDG1RSTF field.
	RCC_C1_RSR_IWDG1RSTF_Msk = 0x4000000  // Bit mask of IWDG1RSTF field.
	RCC_C1_RSR_IWDG1RSTF     = 0x4000000  // Bit IWDG1RSTF.
	RCC_C1_RSR_WWDG1RSTF_Pos = 0x1c       // Position of WWDG1RSTF field.
	RCC_C1_RSR_WWDG1RSTF_Msk = 0x10000000 // Bit mask of WWDG1RSTF field.
	RCC_C1_RSR_WWDG1RSTF     = 0x10000000 // Bit WWDG1RSTF.
	RCC_C1_RSR_LPWRRSTF_Pos  = 0x1e       // Position of LPWRRSTF field.
	RCC_C1_RSR_LPWRRSTF_Msk  = 0x40000000 // Bit mask of LPWRRSTF field.
	RCC_C1_RSR_LPWRRSTF      = 0x40000000 // Bit LPWRRSTF.

	// C1_AHB3ENR: RCC AHB3 Clock Register
	RCC_C1_AHB3ENR_MDMAEN_Pos   = 0x0     // Position of MDMAEN field.
	RCC_C1_AHB3ENR_MDMAEN_Msk   = 0x1     // Bit mask of MDMAEN field.
	RCC_C1_AHB3ENR_MDMAEN       = 0x1     // Bit MDMAEN.
	RCC_C1_AHB3ENR_DMA2DEN_Pos  = 0x4     // Position of DMA2DEN field.
	RCC_C1_AHB3ENR_DMA2DEN_Msk  = 0x10    // Bit mask of DMA2DEN field.
	RCC_C1_AHB3ENR_DMA2DEN      = 0x10    // Bit DMA2DEN.
	RCC_C1_AHB3ENR_JPGDECEN_Pos = 0x5     // Position of JPGDECEN field.
	RCC_C1_AHB3ENR_JPGDECEN_Msk = 0x20    // Bit mask of JPGDECEN field.
	RCC_C1_AHB3ENR_JPGDECEN     = 0x20    // Bit JPGDECEN.
	RCC_C1_AHB3ENR_FMCEN_Pos    = 0xc     // Position of FMCEN field.
	RCC_C1_AHB3ENR_FMCEN_Msk    = 0x1000  // Bit mask of FMCEN field.
	RCC_C1_AHB3ENR_FMCEN        = 0x1000  // Bit FMCEN.
	RCC_C1_AHB3ENR_QSPIEN_Pos   = 0xe     // Position of QSPIEN field.
	RCC_C1_AHB3ENR_QSPIEN_Msk   = 0x4000  // Bit mask of QSPIEN field.
	RCC_C1_AHB3ENR_QSPIEN       = 0x4000  // Bit QSPIEN.
	RCC_C1_AHB3ENR_SDMMC1EN_Pos = 0x10    // Position of SDMMC1EN field.
	RCC_C1_AHB3ENR_SDMMC1EN_Msk = 0x10000 // Bit mask of SDMMC1EN field.
	RCC_C1_AHB3ENR_SDMMC1EN     = 0x10000 // Bit SDMMC1EN.

	// C1_AHB1ENR: RCC AHB1 Clock Register
	RCC_C1_AHB1ENR_DMA1EN_Pos     = 0x0        // Position of DMA1EN field.
	RCC_C1_AHB1ENR_DMA1EN_Msk     = 0x1        // Bit mask of DMA1EN field.
	RCC_C1_AHB1ENR_DMA1EN         = 0x1        // Bit DMA1EN.
	RCC_C1_AHB1ENR_DMA2EN_Pos     = 0x1        // Position of DMA2EN field.
	RCC_C1_AHB1ENR_DMA2EN_Msk     = 0x2        // Bit mask of DMA2EN field.
	RCC_C1_AHB1ENR_DMA2EN         = 0x2        // Bit DMA2EN.
	RCC_C1_AHB1ENR_ADC12EN_Pos    = 0x5        // Position of ADC12EN field.
	RCC_C1_AHB1ENR_ADC12EN_Msk    = 0x20       // Bit mask of ADC12EN field.
	RCC_C1_AHB1ENR_ADC12EN        = 0x20       // Bit ADC12EN.
	RCC_C1_AHB1ENR_ETH1MACEN_Pos  = 0xf        // Position of ETH1MACEN field.
	RCC_C1_AHB1ENR_ETH1MACEN_Msk  = 0x8000     // Bit mask of ETH1MACEN field.
	RCC_C1_AHB1ENR_ETH1MACEN      = 0x8000     // Bit ETH1MACEN.
	RCC_C1_AHB1ENR_ETH1TXEN_Pos   = 0x10       // Position of ETH1TXEN field.
	RCC_C1_AHB1ENR_ETH1TXEN_Msk   = 0x10000    // Bit mask of ETH1TXEN field.
	RCC_C1_AHB1ENR_ETH1TXEN       = 0x10000    // Bit ETH1TXEN.
	RCC_C1_AHB1ENR_ETH1RXEN_Pos   = 0x11       // Position of ETH1RXEN field.
	RCC_C1_AHB1ENR_ETH1RXEN_Msk   = 0x20000    // Bit mask of ETH1RXEN field.
	RCC_C1_AHB1ENR_ETH1RXEN       = 0x20000    // Bit ETH1RXEN.
	RCC_C1_AHB1ENR_USB1OTGEN_Pos  = 0x19       // Position of USB1OTGEN field.
	RCC_C1_AHB1ENR_USB1OTGEN_Msk  = 0x2000000  // Bit mask of USB1OTGEN field.
	RCC_C1_AHB1ENR_USB1OTGEN      = 0x2000000  // Bit USB1OTGEN.
	RCC_C1_AHB1ENR_USB1ULPIEN_Pos = 0x1a       // Position of USB1ULPIEN field.
	RCC_C1_AHB1ENR_USB1ULPIEN_Msk = 0x4000000  // Bit mask of USB1ULPIEN field.
	RCC_C1_AHB1ENR_USB1ULPIEN     = 0x4000000  // Bit USB1ULPIEN.
	RCC_C1_AHB1ENR_USB2OTGEN_Pos  = 0x1b       // Position of USB2OTGEN field.
	RCC_C1_AHB1ENR_USB2OTGEN_Msk  = 0x8000000  // Bit mask of USB2OTGEN field.
	RCC_C1_AHB1ENR_USB2OTGEN      = 0x8000000  // Bit USB2OTGEN.
	RCC_C1_AHB1ENR_USB2ULPIEN_Pos = 0x1c       // Position of USB2ULPIEN field.
	RCC_C1_AHB1ENR_USB2ULPIEN_Msk = 0x10000000 // Bit mask of USB2ULPIEN field.
	RCC_C1_AHB1ENR_USB2ULPIEN     = 0x10000000 // Bit USB2ULPIEN.

	// C1_AHB2ENR: RCC AHB2 Clock Register
	RCC_C1_AHB2ENR_CAMITFEN_Pos = 0x0        // Position of CAMITFEN field.
	RCC_C1_AHB2ENR_CAMITFEN_Msk = 0x1        // Bit mask of CAMITFEN field.
	RCC_C1_AHB2ENR_CAMITFEN     = 0x1        // Bit CAMITFEN.
	RCC_C1_AHB2ENR_CRYPTEN_Pos  = 0x4        // Position of CRYPTEN field.
	RCC_C1_AHB2ENR_CRYPTEN_Msk  = 0x10       // Bit mask of CRYPTEN field.
	RCC_C1_AHB2ENR_CRYPTEN      = 0x10       // Bit CRYPTEN.
	RCC_C1_AHB2ENR_HASHEN_Pos   = 0x5        // Position of HASHEN field.
	RCC_C1_AHB2ENR_HASHEN_Msk   = 0x20       // Bit mask of HASHEN field.
	RCC_C1_AHB2ENR_HASHEN       = 0x20       // Bit HASHEN.
	RCC_C1_AHB2ENR_RNGEN_Pos    = 0x6        // Position of RNGEN field.
	RCC_C1_AHB2ENR_RNGEN_Msk    = 0x40       // Bit mask of RNGEN field.
	RCC_C1_AHB2ENR_RNGEN        = 0x40       // Bit RNGEN.
	RCC_C1_AHB2ENR_SDMMC2EN_Pos = 0x9        // Position of SDMMC2EN field.
	RCC_C1_AHB2ENR_SDMMC2EN_Msk = 0x200      // Bit mask of SDMMC2EN field.
	RCC_C1_AHB2ENR_SDMMC2EN     = 0x200      // Bit SDMMC2EN.
	RCC_C1_AHB2ENR_SRAM1EN_Pos  = 0x1d       // Position of SRAM1EN field.
	RCC_C1_AHB2ENR_SRAM1EN_Msk  = 0x20000000 // Bit mask of SRAM1EN field.
	RCC_C1_AHB2ENR_SRAM1EN      = 0x20000000 // Bit SRAM1EN.
	RCC_C1_AHB2ENR_SRAM2EN_Pos  = 0x1e       // Position of SRAM2EN field.
	RCC_C1_AHB2ENR_SRAM2EN_Msk  = 0x40000000 // Bit mask of SRAM2EN field.
	RCC_C1_AHB2ENR_SRAM2EN      = 0x40000000 // Bit SRAM2EN.
	RCC_C1_AHB2ENR_SRAM3EN_Pos  = 0x1f       // Position of SRAM3EN field.
	RCC_C1_AHB2ENR_SRAM3EN_Msk  = 0x80000000 // Bit mask of SRAM3EN field.
	RCC_C1_AHB2ENR_SRAM3EN      = 0x80000000 // Bit SRAM3EN.

	// C1_AHB4ENR: RCC AHB4 Clock Register
	RCC_C1_AHB4ENR_GPIOAEN_Pos  = 0x0        // Position of GPIOAEN field.
	RCC_C1_AHB4ENR_GPIOAEN_Msk  = 0x1        // Bit mask of GPIOAEN field.
	RCC_C1_AHB4ENR_GPIOAEN      = 0x1        // Bit GPIOAEN.
	RCC_C1_AHB4ENR_GPIOBEN_Pos  = 0x1        // Position of GPIOBEN field.
	RCC_C1_AHB4ENR_GPIOBEN_Msk  = 0x2        // Bit mask of GPIOBEN field.
	RCC_C1_AHB4ENR_GPIOBEN      = 0x2        // Bit GPIOBEN.
	RCC_C1_AHB4ENR_GPIOCEN_Pos  = 0x2        // Position of GPIOCEN field.
	RCC_C1_AHB4ENR_GPIOCEN_Msk  = 0x4        // Bit mask of GPIOCEN field.
	RCC_C1_AHB4ENR_GPIOCEN      = 0x4        // Bit GPIOCEN.
	RCC_C1_AHB4ENR_GPIODEN_Pos  = 0x3        // Position of GPIODEN field.
	RCC_C1_AHB4ENR_GPIODEN_Msk  = 0x8        // Bit mask of GPIODEN field.
	RCC_C1_AHB4ENR_GPIODEN      = 0x8        // Bit GPIODEN.
	RCC_C1_AHB4ENR_GPIOEEN_Pos  = 0x4        // Position of GPIOEEN field.
	RCC_C1_AHB4ENR_GPIOEEN_Msk  = 0x10       // Bit mask of GPIOEEN field.
	RCC_C1_AHB4ENR_GPIOEEN      = 0x10       // Bit GPIOEEN.
	RCC_C1_AHB4ENR_GPIOFEN_Pos  = 0x5        // Position of GPIOFEN field.
	RCC_C1_AHB4ENR_GPIOFEN_Msk  = 0x20       // Bit mask of GPIOFEN field.
	RCC_C1_AHB4ENR_GPIOFEN      = 0x20       // Bit GPIOFEN.
	RCC_C1_AHB4ENR_GPIOGEN_Pos  = 0x6        // Position of GPIOGEN field.
	RCC_C1_AHB4ENR_GPIOGEN_Msk  = 0x40       // Bit mask of GPIOGEN field.
	RCC_C1_AHB4ENR_GPIOGEN      = 0x40       // Bit GPIOGEN.
	RCC_C1_AHB4ENR_GPIOHEN_Pos  = 0x7        // Position of GPIOHEN field.
	RCC_C1_AHB4ENR_GPIOHEN_Msk  = 0x80       // Bit mask of GPIOHEN field.
	RCC_C1_AHB4ENR_GPIOHEN      = 0x80       // Bit GPIOHEN.
	RCC_C1_AHB4ENR_GPIOIEN_Pos  = 0x8        // Position of GPIOIEN field.
	RCC_C1_AHB4ENR_GPIOIEN_Msk  = 0x100      // Bit mask of GPIOIEN field.
	RCC_C1_AHB4ENR_GPIOIEN      = 0x100      // Bit GPIOIEN.
	RCC_C1_AHB4ENR_GPIOJEN_Pos  = 0x9        // Position of GPIOJEN field.
	RCC_C1_AHB4ENR_GPIOJEN_Msk  = 0x200      // Bit mask of GPIOJEN field.
	RCC_C1_AHB4ENR_GPIOJEN      = 0x200      // Bit GPIOJEN.
	RCC_C1_AHB4ENR_GPIOKEN_Pos  = 0xa        // Position of GPIOKEN field.
	RCC_C1_AHB4ENR_GPIOKEN_Msk  = 0x400      // Bit mask of GPIOKEN field.
	RCC_C1_AHB4ENR_GPIOKEN      = 0x400      // Bit GPIOKEN.
	RCC_C1_AHB4ENR_CRCEN_Pos    = 0x13       // Position of CRCEN field.
	RCC_C1_AHB4ENR_CRCEN_Msk    = 0x80000    // Bit mask of CRCEN field.
	RCC_C1_AHB4ENR_CRCEN        = 0x80000    // Bit CRCEN.
	RCC_C1_AHB4ENR_BDMAEN_Pos   = 0x15       // Position of BDMAEN field.
	RCC_C1_AHB4ENR_BDMAEN_Msk   = 0x200000   // Bit mask of BDMAEN field.
	RCC_C1_AHB4ENR_BDMAEN       = 0x200000   // Bit BDMAEN.
	RCC_C1_AHB4ENR_ADC3EN_Pos   = 0x18       // Position of ADC3EN field.
	RCC_C1_AHB4ENR_ADC3EN_Msk   = 0x1000000  // Bit mask of ADC3EN field.
	RCC_C1_AHB4ENR_ADC3EN       = 0x1000000  // Bit ADC3EN.
	RCC_C1_AHB4ENR_HSEMEN_Pos   = 0x19       // Position of HSEMEN field.
	RCC_C1_AHB4ENR_HSEMEN_Msk   = 0x2000000  // Bit mask of HSEMEN field.
	RCC_C1_AHB4ENR_HSEMEN       = 0x2000000  // Bit HSEMEN.
	RCC_C1_AHB4ENR_BKPRAMEN_Pos = 0x1c       // Position of BKPRAMEN field.
	RCC_C1_AHB4ENR_BKPRAMEN_Msk = 0x10000000 // Bit mask of BKPRAMEN field.
	RCC_C1_AHB4ENR_BKPRAMEN     = 0x10000000 // Bit BKPRAMEN.

	// C1_APB3ENR: RCC APB3 Clock Register
	RCC_C1_APB3ENR_LTDCEN_Pos  = 0x3  // Position of LTDCEN field.
	RCC_C1_APB3ENR_LTDCEN_Msk  = 0x8  // Bit mask of LTDCEN field.
	RCC_C1_APB3ENR_LTDCEN      = 0x8  // Bit LTDCEN.
	RCC_C1_APB3ENR_WWDG1EN_Pos = 0x6  // Position of WWDG1EN field.
	RCC_C1_APB3ENR_WWDG1EN_Msk = 0x40 // Bit mask of WWDG1EN field.
	RCC_C1_APB3ENR_WWDG1EN     = 0x40 // Bit WWDG1EN.

	// C1_APB1LENR: RCC APB1 Clock Register
	RCC_C1_APB1LENR_TIM2EN_Pos    = 0x0        // Position of TIM2EN field.
	RCC_C1_APB1LENR_TIM2EN_Msk    = 0x1        // Bit mask of TIM2EN field.
	RCC_C1_APB1LENR_TIM2EN        = 0x1        // Bit TIM2EN.
	RCC_C1_APB1LENR_TIM3EN_Pos    = 0x1        // Position of TIM3EN field.
	RCC_C1_APB1LENR_TIM3EN_Msk    = 0x2        // Bit mask of TIM3EN field.
	RCC_C1_APB1LENR_TIM3EN        = 0x2        // Bit TIM3EN.
	RCC_C1_APB1LENR_TIM4EN_Pos    = 0x2        // Position of TIM4EN field.
	RCC_C1_APB1LENR_TIM4EN_Msk    = 0x4        // Bit mask of TIM4EN field.
	RCC_C1_APB1LENR_TIM4EN        = 0x4        // Bit TIM4EN.
	RCC_C1_APB1LENR_TIM5EN_Pos    = 0x3        // Position of TIM5EN field.
	RCC_C1_APB1LENR_TIM5EN_Msk    = 0x8        // Bit mask of TIM5EN field.
	RCC_C1_APB1LENR_TIM5EN        = 0x8        // Bit TIM5EN.
	RCC_C1_APB1LENR_TIM6EN_Pos    = 0x4        // Position of TIM6EN field.
	RCC_C1_APB1LENR_TIM6EN_Msk    = 0x10       // Bit mask of TIM6EN field.
	RCC_C1_APB1LENR_TIM6EN        = 0x10       // Bit TIM6EN.
	RCC_C1_APB1LENR_TIM7EN_Pos    = 0x5        // Position of TIM7EN field.
	RCC_C1_APB1LENR_TIM7EN_Msk    = 0x20       // Bit mask of TIM7EN field.
	RCC_C1_APB1LENR_TIM7EN        = 0x20       // Bit TIM7EN.
	RCC_C1_APB1LENR_TIM12EN_Pos   = 0x6        // Position of TIM12EN field.
	RCC_C1_APB1LENR_TIM12EN_Msk   = 0x40       // Bit mask of TIM12EN field.
	RCC_C1_APB1LENR_TIM12EN       = 0x40       // Bit TIM12EN.
	RCC_C1_APB1LENR_TIM13EN_Pos   = 0x7        // Position of TIM13EN field.
	RCC_C1_APB1LENR_TIM13EN_Msk   = 0x80       // Bit mask of TIM13EN field.
	RCC_C1_APB1LENR_TIM13EN       = 0x80       // Bit TIM13EN.
	RCC_C1_APB1LENR_TIM14EN_Pos   = 0x8        // Position of TIM14EN field.
	RCC_C1_APB1LENR_TIM14EN_Msk   = 0x100      // Bit mask of TIM14EN field.
	RCC_C1_APB1LENR_TIM14EN       = 0x100      // Bit TIM14EN.
	RCC_C1_APB1LENR_LPTIM1EN_Pos  = 0x9        // Position of LPTIM1EN field.
	RCC_C1_APB1LENR_LPTIM1EN_Msk  = 0x200      // Bit mask of LPTIM1EN field.
	RCC_C1_APB1LENR_LPTIM1EN      = 0x200      // Bit LPTIM1EN.
	RCC_C1_APB1LENR_SPI2EN_Pos    = 0xe        // Position of SPI2EN field.
	RCC_C1_APB1LENR_SPI2EN_Msk    = 0x4000     // Bit mask of SPI2EN field.
	RCC_C1_APB1LENR_SPI2EN        = 0x4000     // Bit SPI2EN.
	RCC_C1_APB1LENR_SPI3EN_Pos    = 0xf        // Position of SPI3EN field.
	RCC_C1_APB1LENR_SPI3EN_Msk    = 0x8000     // Bit mask of SPI3EN field.
	RCC_C1_APB1LENR_SPI3EN        = 0x8000     // Bit SPI3EN.
	RCC_C1_APB1LENR_SPDIFRXEN_Pos = 0x10       // Position of SPDIFRXEN field.
	RCC_C1_APB1LENR_SPDIFRXEN_Msk = 0x10000    // Bit mask of SPDIFRXEN field.
	RCC_C1_APB1LENR_SPDIFRXEN     = 0x10000    // Bit SPDIFRXEN.
	RCC_C1_APB1LENR_USART2EN_Pos  = 0x11       // Position of USART2EN field.
	RCC_C1_APB1LENR_USART2EN_Msk  = 0x20000    // Bit mask of USART2EN field.
	RCC_C1_APB1LENR_USART2EN      = 0x20000    // Bit USART2EN.
	RCC_C1_APB1LENR_USART3EN_Pos  = 0x12       // Position of USART3EN field.
	RCC_C1_APB1LENR_USART3EN_Msk  = 0x40000    // Bit mask of USART3EN field.
	RCC_C1_APB1LENR_USART3EN      = 0x40000    // Bit USART3EN.
	RCC_C1_APB1LENR_UART4EN_Pos   = 0x13       // Position of UART4EN field.
	RCC_C1_APB1LENR_UART4EN_Msk   = 0x80000    // Bit mask of UART4EN field.
	RCC_C1_APB1LENR_UART4EN       = 0x80000    // Bit UART4EN.
	RCC_C1_APB1LENR_UART5EN_Pos   = 0x14       // Position of UART5EN field.
	RCC_C1_APB1LENR_UART5EN_Msk   = 0x100000   // Bit mask of UART5EN field.
	RCC_C1_APB1LENR_UART5EN       = 0x100000   // Bit UART5EN.
	RCC_C1_APB1LENR_I2C1EN_Pos    = 0x15       // Position of I2C1EN field.
	RCC_C1_APB1LENR_I2C1EN_Msk    = 0x200000   // Bit mask of I2C1EN field.
	RCC_C1_APB1LENR_I2C1EN        = 0x200000   // Bit I2C1EN.
	RCC_C1_APB1LENR_I2C2EN_Pos    = 0x16       // Position of I2C2EN field.
	RCC_C1_APB1LENR_I2C2EN_Msk    = 0x400000   // Bit mask of I2C2EN field.
	RCC_C1_APB1LENR_I2C2EN        = 0x400000   // Bit I2C2EN.
	RCC_C1_APB1LENR_I2C3EN_Pos    = 0x17       // Position of I2C3EN field.
	RCC_C1_APB1LENR_I2C3EN_Msk    = 0x800000   // Bit mask of I2C3EN field.
	RCC_C1_APB1LENR_I2C3EN        = 0x800000   // Bit I2C3EN.
	RCC_C1_APB1LENR_HDMICECEN_Pos = 0x1b       // Position of HDMICECEN field.
	RCC_C1_APB1LENR_HDMICECEN_Msk = 0x8000000  // Bit mask of HDMICECEN field.
	RCC_C1_APB1LENR_HDMICECEN     = 0x8000000  // Bit HDMICECEN.
	RCC_C1_APB1LENR_DAC12EN_Pos   = 0x1d       // Position of DAC12EN field.
	RCC_C1_APB1LENR_DAC12EN_Msk   = 0x20000000 // Bit mask of DAC12EN field.
	RCC_C1_APB1LENR_DAC12EN       = 0x20000000 // Bit DAC12EN.
	RCC_C1_APB1LENR_USART7EN_Pos  = 0x1e       // Position of USART7EN field.
	RCC_C1_APB1LENR_USART7EN_Msk  = 0x40000000 // Bit mask of USART7EN field.
	RCC_C1_APB1LENR_USART7EN      = 0x40000000 // Bit USART7EN.
	RCC_C1_APB1LENR_USART8EN_Pos  = 0x1f       // Position of USART8EN field.
	RCC_C1_APB1LENR_USART8EN_Msk  = 0x80000000 // Bit mask of USART8EN field.
	RCC_C1_APB1LENR_USART8EN      = 0x80000000 // Bit USART8EN.

	// C1_APB1HENR: RCC APB1 Clock Register
	RCC_C1_APB1HENR_CRSEN_Pos   = 0x1   // Position of CRSEN field.
	RCC_C1_APB1HENR_CRSEN_Msk   = 0x2   // Bit mask of CRSEN field.
	RCC_C1_APB1HENR_CRSEN       = 0x2   // Bit CRSEN.
	RCC_C1_APB1HENR_SWPEN_Pos   = 0x2   // Position of SWPEN field.
	RCC_C1_APB1HENR_SWPEN_Msk   = 0x4   // Bit mask of SWPEN field.
	RCC_C1_APB1HENR_SWPEN       = 0x4   // Bit SWPEN.
	RCC_C1_APB1HENR_OPAMPEN_Pos = 0x4   // Position of OPAMPEN field.
	RCC_C1_APB1HENR_OPAMPEN_Msk = 0x10  // Bit mask of OPAMPEN field.
	RCC_C1_APB1HENR_OPAMPEN     = 0x10  // Bit OPAMPEN.
	RCC_C1_APB1HENR_MDIOSEN_Pos = 0x5   // Position of MDIOSEN field.
	RCC_C1_APB1HENR_MDIOSEN_Msk = 0x20  // Bit mask of MDIOSEN field.
	RCC_C1_APB1HENR_MDIOSEN     = 0x20  // Bit MDIOSEN.
	RCC_C1_APB1HENR_FDCANEN_Pos = 0x8   // Position of FDCANEN field.
	RCC_C1_APB1HENR_FDCANEN_Msk = 0x100 // Bit mask of FDCANEN field.
	RCC_C1_APB1HENR_FDCANEN     = 0x100 // Bit FDCANEN.

	// C1_APB2ENR: RCC APB2 Clock Register
	RCC_C1_APB2ENR_TIM1EN_Pos   = 0x0        // Position of TIM1EN field.
	RCC_C1_APB2ENR_TIM1EN_Msk   = 0x1        // Bit mask of TIM1EN field.
	RCC_C1_APB2ENR_TIM1EN       = 0x1        // Bit TIM1EN.
	RCC_C1_APB2ENR_TIM8EN_Pos   = 0x1        // Position of TIM8EN field.
	RCC_C1_APB2ENR_TIM8EN_Msk   = 0x2        // Bit mask of TIM8EN field.
	RCC_C1_APB2ENR_TIM8EN       = 0x2        // Bit TIM8EN.
	RCC_C1_APB2ENR_USART1EN_Pos = 0x4        // Position of USART1EN field.
	RCC_C1_APB2ENR_USART1EN_Msk = 0x10       // Bit mask of USART1EN field.
	RCC_C1_APB2ENR_USART1EN     = 0x10       // Bit USART1EN.
	RCC_C1_APB2ENR_USART6EN_Pos = 0x5        // Position of USART6EN field.
	RCC_C1_APB2ENR_USART6EN_Msk = 0x20       // Bit mask of USART6EN field.
	RCC_C1_APB2ENR_USART6EN     = 0x20       // Bit USART6EN.
	RCC_C1_APB2ENR_SPI1EN_Pos   = 0xc        // Position of SPI1EN field.
	RCC_C1_APB2ENR_SPI1EN_Msk   = 0x1000     // Bit mask of SPI1EN field.
	RCC_C1_APB2ENR_SPI1EN       = 0x1000     // Bit SPI1EN.
	RCC_C1_APB2ENR_SPI4EN_Pos   = 0xd        // Position of SPI4EN field.
	RCC_C1_APB2ENR_SPI4EN_Msk   = 0x2000     // Bit mask of SPI4EN field.
	RCC_C1_APB2ENR_SPI4EN       = 0x2000     // Bit SPI4EN.
	RCC_C1_APB2ENR_TIM16EN_Pos  = 0x11       // Position of TIM16EN field.
	RCC_C1_APB2ENR_TIM16EN_Msk  = 0x20000    // Bit mask of TIM16EN field.
	RCC_C1_APB2ENR_TIM16EN      = 0x20000    // Bit TIM16EN.
	RCC_C1_APB2ENR_TIM15EN_Pos  = 0x10       // Position of TIM15EN field.
	RCC_C1_APB2ENR_TIM15EN_Msk  = 0x10000    // Bit mask of TIM15EN field.
	RCC_C1_APB2ENR_TIM15EN      = 0x10000    // Bit TIM15EN.
	RCC_C1_APB2ENR_TIM17EN_Pos  = 0x12       // Position of TIM17EN field.
	RCC_C1_APB2ENR_TIM17EN_Msk  = 0x40000    // Bit mask of TIM17EN field.
	RCC_C1_APB2ENR_TIM17EN      = 0x40000    // Bit TIM17EN.
	RCC_C1_APB2ENR_SPI5EN_Pos   = 0x14       // Position of SPI5EN field.
	RCC_C1_APB2ENR_SPI5EN_Msk   = 0x100000   // Bit mask of SPI5EN field.
	RCC_C1_APB2ENR_SPI5EN       = 0x100000   // Bit SPI5EN.
	RCC_C1_APB2ENR_SAI1EN_Pos   = 0x16       // Position of SAI1EN field.
	RCC_C1_APB2ENR_SAI1EN_Msk   = 0x400000   // Bit mask of SAI1EN field.
	RCC_C1_APB2ENR_SAI1EN       = 0x400000   // Bit SAI1EN.
	RCC_C1_APB2ENR_SAI2EN_Pos   = 0x17       // Position of SAI2EN field.
	RCC_C1_APB2ENR_SAI2EN_Msk   = 0x800000   // Bit mask of SAI2EN field.
	RCC_C1_APB2ENR_SAI2EN       = 0x800000   // Bit SAI2EN.
	RCC_C1_APB2ENR_SAI3EN_Pos   = 0x18       // Position of SAI3EN field.
	RCC_C1_APB2ENR_SAI3EN_Msk   = 0x1000000  // Bit mask of SAI3EN field.
	RCC_C1_APB2ENR_SAI3EN       = 0x1000000  // Bit SAI3EN.
	RCC_C1_APB2ENR_DFSDM1EN_Pos = 0x1c       // Position of DFSDM1EN field.
	RCC_C1_APB2ENR_DFSDM1EN_Msk = 0x10000000 // Bit mask of DFSDM1EN field.
	RCC_C1_APB2ENR_DFSDM1EN     = 0x10000000 // Bit DFSDM1EN.
	RCC_C1_APB2ENR_HRTIMEN_Pos  = 0x1d       // Position of HRTIMEN field.
	RCC_C1_APB2ENR_HRTIMEN_Msk  = 0x20000000 // Bit mask of HRTIMEN field.
	RCC_C1_APB2ENR_HRTIMEN      = 0x20000000 // Bit HRTIMEN.

	// C1_APB4ENR: RCC APB4 Clock Register
	RCC_C1_APB4ENR_SYSCFGEN_Pos  = 0x1      // Position of SYSCFGEN field.
	RCC_C1_APB4ENR_SYSCFGEN_Msk  = 0x2      // Bit mask of SYSCFGEN field.
	RCC_C1_APB4ENR_SYSCFGEN      = 0x2      // Bit SYSCFGEN.
	RCC_C1_APB4ENR_LPUART1EN_Pos = 0x3      // Position of LPUART1EN field.
	RCC_C1_APB4ENR_LPUART1EN_Msk = 0x8      // Bit mask of LPUART1EN field.
	RCC_C1_APB4ENR_LPUART1EN     = 0x8      // Bit LPUART1EN.
	RCC_C1_APB4ENR_SPI6EN_Pos    = 0x5      // Position of SPI6EN field.
	RCC_C1_APB4ENR_SPI6EN_Msk    = 0x20     // Bit mask of SPI6EN field.
	RCC_C1_APB4ENR_SPI6EN        = 0x20     // Bit SPI6EN.
	RCC_C1_APB4ENR_I2C4EN_Pos    = 0x7      // Position of I2C4EN field.
	RCC_C1_APB4ENR_I2C4EN_Msk    = 0x80     // Bit mask of I2C4EN field.
	RCC_C1_APB4ENR_I2C4EN        = 0x80     // Bit I2C4EN.
	RCC_C1_APB4ENR_LPTIM2EN_Pos  = 0x9      // Position of LPTIM2EN field.
	RCC_C1_APB4ENR_LPTIM2EN_Msk  = 0x200    // Bit mask of LPTIM2EN field.
	RCC_C1_APB4ENR_LPTIM2EN      = 0x200    // Bit LPTIM2EN.
	RCC_C1_APB4ENR_LPTIM3EN_Pos  = 0xa      // Position of LPTIM3EN field.
	RCC_C1_APB4ENR_LPTIM3EN_Msk  = 0x400    // Bit mask of LPTIM3EN field.
	RCC_C1_APB4ENR_LPTIM3EN      = 0x400    // Bit LPTIM3EN.
	RCC_C1_APB4ENR_LPTIM4EN_Pos  = 0xb      // Position of LPTIM4EN field.
	RCC_C1_APB4ENR_LPTIM4EN_Msk  = 0x800    // Bit mask of LPTIM4EN field.
	RCC_C1_APB4ENR_LPTIM4EN      = 0x800    // Bit LPTIM4EN.
	RCC_C1_APB4ENR_LPTIM5EN_Pos  = 0xc      // Position of LPTIM5EN field.
	RCC_C1_APB4ENR_LPTIM5EN_Msk  = 0x1000   // Bit mask of LPTIM5EN field.
	RCC_C1_APB4ENR_LPTIM5EN      = 0x1000   // Bit LPTIM5EN.
	RCC_C1_APB4ENR_COMP12EN_Pos  = 0xe      // Position of COMP12EN field.
	RCC_C1_APB4ENR_COMP12EN_Msk  = 0x4000   // Bit mask of COMP12EN field.
	RCC_C1_APB4ENR_COMP12EN      = 0x4000   // Bit COMP12EN.
	RCC_C1_APB4ENR_VREFEN_Pos    = 0xf      // Position of VREFEN field.
	RCC_C1_APB4ENR_VREFEN_Msk    = 0x8000   // Bit mask of VREFEN field.
	RCC_C1_APB4ENR_VREFEN        = 0x8000   // Bit VREFEN.
	RCC_C1_APB4ENR_RTCAPBEN_Pos  = 0x10     // Position of RTCAPBEN field.
	RCC_C1_APB4ENR_RTCAPBEN_Msk  = 0x10000  // Bit mask of RTCAPBEN field.
	RCC_C1_APB4ENR_RTCAPBEN      = 0x10000  // Bit RTCAPBEN.
	RCC_C1_APB4ENR_SAI4EN_Pos    = 0x15     // Position of SAI4EN field.
	RCC_C1_APB4ENR_SAI4EN_Msk    = 0x200000 // Bit mask of SAI4EN field.
	RCC_C1_APB4ENR_SAI4EN        = 0x200000 // Bit SAI4EN.

	// C1_AHB3LPENR: RCC AHB3 Sleep Clock Register
	RCC_C1_AHB3LPENR_MDMALPEN_Pos    = 0x0        // Position of MDMALPEN field.
	RCC_C1_AHB3LPENR_MDMALPEN_Msk    = 0x1        // Bit mask of MDMALPEN field.
	RCC_C1_AHB3LPENR_MDMALPEN        = 0x1        // Bit MDMALPEN.
	RCC_C1_AHB3LPENR_DMA2DLPEN_Pos   = 0x4        // Position of DMA2DLPEN field.
	RCC_C1_AHB3LPENR_DMA2DLPEN_Msk   = 0x10       // Bit mask of DMA2DLPEN field.
	RCC_C1_AHB3LPENR_DMA2DLPEN       = 0x10       // Bit DMA2DLPEN.
	RCC_C1_AHB3LPENR_JPGDECLPEN_Pos  = 0x5        // Position of JPGDECLPEN field.
	RCC_C1_AHB3LPENR_JPGDECLPEN_Msk  = 0x20       // Bit mask of JPGDECLPEN field.
	RCC_C1_AHB3LPENR_JPGDECLPEN      = 0x20       // Bit JPGDECLPEN.
	RCC_C1_AHB3LPENR_FLITFLPEN_Pos   = 0x8        // Position of FLITFLPEN field.
	RCC_C1_AHB3LPENR_FLITFLPEN_Msk   = 0x100      // Bit mask of FLITFLPEN field.
	RCC_C1_AHB3LPENR_FLITFLPEN       = 0x100      // Bit FLITFLPEN.
	RCC_C1_AHB3LPENR_FMCLPEN_Pos     = 0xc        // Position of FMCLPEN field.
	RCC_C1_AHB3LPENR_FMCLPEN_Msk     = 0x1000     // Bit mask of FMCLPEN field.
	RCC_C1_AHB3LPENR_FMCLPEN         = 0x1000     // Bit FMCLPEN.
	RCC_C1_AHB3LPENR_QSPILPEN_Pos    = 0xe        // Position of QSPILPEN field.
	RCC_C1_AHB3LPENR_QSPILPEN_Msk    = 0x4000     // Bit mask of QSPILPEN field.
	RCC_C1_AHB3LPENR_QSPILPEN        = 0x4000     // Bit QSPILPEN.
	RCC_C1_AHB3LPENR_SDMMC1LPEN_Pos  = 0x10       // Position of SDMMC1LPEN field.
	RCC_C1_AHB3LPENR_SDMMC1LPEN_Msk  = 0x10000    // Bit mask of SDMMC1LPEN field.
	RCC_C1_AHB3LPENR_SDMMC1LPEN      = 0x10000    // Bit SDMMC1LPEN.
	RCC_C1_AHB3LPENR_D1DTCM1LPEN_Pos = 0x1c       // Position of D1DTCM1LPEN field.
	RCC_C1_AHB3LPENR_D1DTCM1LPEN_Msk = 0x10000000 // Bit mask of D1DTCM1LPEN field.
	RCC_C1_AHB3LPENR_D1DTCM1LPEN     = 0x10000000 // Bit D1DTCM1LPEN.
	RCC_C1_AHB3LPENR_DTCM2LPEN_Pos   = 0x1d       // Position of DTCM2LPEN field.
	RCC_C1_AHB3LPENR_DTCM2LPEN_Msk   = 0x20000000 // Bit mask of DTCM2LPEN field.
	RCC_C1_AHB3LPENR_DTCM2LPEN       = 0x20000000 // Bit DTCM2LPEN.
	RCC_C1_AHB3LPENR_ITCMLPEN_Pos    = 0x1e       // Position of ITCMLPEN field.
	RCC_C1_AHB3LPENR_ITCMLPEN_Msk    = 0x40000000 // Bit mask of ITCMLPEN field.
	RCC_C1_AHB3LPENR_ITCMLPEN        = 0x40000000 // Bit ITCMLPEN.
	RCC_C1_AHB3LPENR_AXISRAMLPEN_Pos = 0x1f       // Position of AXISRAMLPEN field.
	RCC_C1_AHB3LPENR_AXISRAMLPEN_Msk = 0x80000000 // Bit mask of AXISRAMLPEN field.
	RCC_C1_AHB3LPENR_AXISRAMLPEN     = 0x80000000 // Bit AXISRAMLPEN.

	// C1_AHB1LPENR: RCC AHB1 Sleep Clock Register
	RCC_C1_AHB1LPENR_DMA1LPEN_Pos     = 0x0        // Position of DMA1LPEN field.
	RCC_C1_AHB1LPENR_DMA1LPEN_Msk     = 0x1        // Bit mask of DMA1LPEN field.
	RCC_C1_AHB1LPENR_DMA1LPEN         = 0x1        // Bit DMA1LPEN.
	RCC_C1_AHB1LPENR_DMA2LPEN_Pos     = 0x1        // Position of DMA2LPEN field.
	RCC_C1_AHB1LPENR_DMA2LPEN_Msk     = 0x2        // Bit mask of DMA2LPEN field.
	RCC_C1_AHB1LPENR_DMA2LPEN         = 0x2        // Bit DMA2LPEN.
	RCC_C1_AHB1LPENR_ADC12LPEN_Pos    = 0x5        // Position of ADC12LPEN field.
	RCC_C1_AHB1LPENR_ADC12LPEN_Msk    = 0x20       // Bit mask of ADC12LPEN field.
	RCC_C1_AHB1LPENR_ADC12LPEN        = 0x20       // Bit ADC12LPEN.
	RCC_C1_AHB1LPENR_ETH1MACLPEN_Pos  = 0xf        // Position of ETH1MACLPEN field.
	RCC_C1_AHB1LPENR_ETH1MACLPEN_Msk  = 0x8000     // Bit mask of ETH1MACLPEN field.
	RCC_C1_AHB1LPENR_ETH1MACLPEN      = 0x8000     // Bit ETH1MACLPEN.
	RCC_C1_AHB1LPENR_ETH1TXLPEN_Pos   = 0x10       // Position of ETH1TXLPEN field.
	RCC_C1_AHB1LPENR_ETH1TXLPEN_Msk   = 0x10000    // Bit mask of ETH1TXLPEN field.
	RCC_C1_AHB1LPENR_ETH1TXLPEN       = 0x10000    // Bit ETH1TXLPEN.
	RCC_C1_AHB1LPENR_ETH1RXLPEN_Pos   = 0x11       // Position of ETH1RXLPEN field.
	RCC_C1_AHB1LPENR_ETH1RXLPEN_Msk   = 0x20000    // Bit mask of ETH1RXLPEN field.
	RCC_C1_AHB1LPENR_ETH1RXLPEN       = 0x20000    // Bit ETH1RXLPEN.
	RCC_C1_AHB1LPENR_USB1OTGLPEN_Pos  = 0x19       // Position of USB1OTGLPEN field.
	RCC_C1_AHB1LPENR_USB1OTGLPEN_Msk  = 0x2000000  // Bit mask of USB1OTGLPEN field.
	RCC_C1_AHB1LPENR_USB1OTGLPEN      = 0x2000000  // Bit USB1OTGLPEN.
	RCC_C1_AHB1LPENR_USB1ULPILPEN_Pos = 0x1a       // Position of USB1ULPILPEN field.
	RCC_C1_AHB1LPENR_USB1ULPILPEN_Msk = 0x4000000  // Bit mask of USB1ULPILPEN field.
	RCC_C1_AHB1LPENR_USB1ULPILPEN     = 0x4000000  // Bit USB1ULPILPEN.
	RCC_C1_AHB1LPENR_USB2OTGLPEN_Pos  = 0x1b       // Position of USB2OTGLPEN field.
	RCC_C1_AHB1LPENR_USB2OTGLPEN_Msk  = 0x8000000  // Bit mask of USB2OTGLPEN field.
	RCC_C1_AHB1LPENR_USB2OTGLPEN      = 0x8000000  // Bit USB2OTGLPEN.
	RCC_C1_AHB1LPENR_USB2ULPILPEN_Pos = 0x1c       // Position of USB2ULPILPEN field.
	RCC_C1_AHB1LPENR_USB2ULPILPEN_Msk = 0x10000000 // Bit mask of USB2ULPILPEN field.
	RCC_C1_AHB1LPENR_USB2ULPILPEN     = 0x10000000 // Bit USB2ULPILPEN.

	// C1_AHB2LPENR: RCC AHB2 Sleep Clock Register
	RCC_C1_AHB2LPENR_CAMITFLPEN_Pos = 0x0        // Position of CAMITFLPEN field.
	RCC_C1_AHB2LPENR_CAMITFLPEN_Msk = 0x1        // Bit mask of CAMITFLPEN field.
	RCC_C1_AHB2LPENR_CAMITFLPEN     = 0x1        // Bit CAMITFLPEN.
	RCC_C1_AHB2LPENR_CRYPTLPEN_Pos  = 0x4        // Position of CRYPTLPEN field.
	RCC_C1_AHB2LPENR_CRYPTLPEN_Msk  = 0x10       // Bit mask of CRYPTLPEN field.
	RCC_C1_AHB2LPENR_CRYPTLPEN      = 0x10       // Bit CRYPTLPEN.
	RCC_C1_AHB2LPENR_HASHLPEN_Pos   = 0x5        // Position of HASHLPEN field.
	RCC_C1_AHB2LPENR_HASHLPEN_Msk   = 0x20       // Bit mask of HASHLPEN field.
	RCC_C1_AHB2LPENR_HASHLPEN       = 0x20       // Bit HASHLPEN.
	RCC_C1_AHB2LPENR_SDMMC2LPEN_Pos = 0x9        // Position of SDMMC2LPEN field.
	RCC_C1_AHB2LPENR_SDMMC2LPEN_Msk = 0x200      // Bit mask of SDMMC2LPEN field.
	RCC_C1_AHB2LPENR_SDMMC2LPEN     = 0x200      // Bit SDMMC2LPEN.
	RCC_C1_AHB2LPENR_RNGLPEN_Pos    = 0x6        // Position of RNGLPEN field.
	RCC_C1_AHB2LPENR_RNGLPEN_Msk    = 0x40       // Bit mask of RNGLPEN field.
	RCC_C1_AHB2LPENR_RNGLPEN        = 0x40       // Bit RNGLPEN.
	RCC_C1_AHB2LPENR_SRAM1LPEN_Pos  = 0x1d       // Position of SRAM1LPEN field.
	RCC_C1_AHB2LPENR_SRAM1LPEN_Msk  = 0x20000000 // Bit mask of SRAM1LPEN field.
	RCC_C1_AHB2LPENR_SRAM1LPEN      = 0x20000000 // Bit SRAM1LPEN.
	RCC_C1_AHB2LPENR_SRAM2LPEN_Pos  = 0x1e       // Position of SRAM2LPEN field.
	RCC_C1_AHB2LPENR_SRAM2LPEN_Msk  = 0x40000000 // Bit mask of SRAM2LPEN field.
	RCC_C1_AHB2LPENR_SRAM2LPEN      = 0x40000000 // Bit SRAM2LPEN.
	RCC_C1_AHB2LPENR_SRAM3LPEN_Pos  = 0x1f       // Position of SRAM3LPEN field.
	RCC_C1_AHB2LPENR_SRAM3LPEN_Msk  = 0x80000000 // Bit mask of SRAM3LPEN field.
	RCC_C1_AHB2LPENR_SRAM3LPEN      = 0x80000000 // Bit SRAM3LPEN.

	// C1_AHB4LPENR: RCC AHB4 Sleep Clock Register
	RCC_C1_AHB4LPENR_GPIOALPEN_Pos  = 0x0        // Position of GPIOALPEN field.
	RCC_C1_AHB4LPENR_GPIOALPEN_Msk  = 0x1        // Bit mask of GPIOALPEN field.
	RCC_C1_AHB4LPENR_GPIOALPEN      = 0x1        // Bit GPIOALPEN.
	RCC_C1_AHB4LPENR_GPIOBLPEN_Pos  = 0x1        // Position of GPIOBLPEN field.
	RCC_C1_AHB4LPENR_GPIOBLPEN_Msk  = 0x2        // Bit mask of GPIOBLPEN field.
	RCC_C1_AHB4LPENR_GPIOBLPEN      = 0x2        // Bit GPIOBLPEN.
	RCC_C1_AHB4LPENR_GPIOCLPEN_Pos  = 0x2        // Position of GPIOCLPEN field.
	RCC_C1_AHB4LPENR_GPIOCLPEN_Msk  = 0x4        // Bit mask of GPIOCLPEN field.
	RCC_C1_AHB4LPENR_GPIOCLPEN      = 0x4        // Bit GPIOCLPEN.
	RCC_C1_AHB4LPENR_GPIODLPEN_Pos  = 0x3        // Position of GPIODLPEN field.
	RCC_C1_AHB4LPENR_GPIODLPEN_Msk  = 0x8        // Bit mask of GPIODLPEN field.
	RCC_C1_AHB4LPENR_GPIODLPEN      = 0x8        // Bit GPIODLPEN.
	RCC_C1_AHB4LPENR_GPIOELPEN_Pos  = 0x4        // Position of GPIOELPEN field.
	RCC_C1_AHB4LPENR_GPIOELPEN_Msk  = 0x10       // Bit mask of GPIOELPEN field.
	RCC_C1_AHB4LPENR_GPIOELPEN      = 0x10       // Bit GPIOELPEN.
	RCC_C1_AHB4LPENR_GPIOFLPEN_Pos  = 0x5        // Position of GPIOFLPEN field.
	RCC_C1_AHB4LPENR_GPIOFLPEN_Msk  = 0x20       // Bit mask of GPIOFLPEN field.
	RCC_C1_AHB4LPENR_GPIOFLPEN      = 0x20       // Bit GPIOFLPEN.
	RCC_C1_AHB4LPENR_GPIOGLPEN_Pos  = 0x6        // Position of GPIOGLPEN field.
	RCC_C1_AHB4LPENR_GPIOGLPEN_Msk  = 0x40       // Bit mask of GPIOGLPEN field.
	RCC_C1_AHB4LPENR_GPIOGLPEN      = 0x40       // Bit GPIOGLPEN.
	RCC_C1_AHB4LPENR_GPIOHLPEN_Pos  = 0x7        // Position of GPIOHLPEN field.
	RCC_C1_AHB4LPENR_GPIOHLPEN_Msk  = 0x80       // Bit mask of GPIOHLPEN field.
	RCC_C1_AHB4LPENR_GPIOHLPEN      = 0x80       // Bit GPIOHLPEN.
	RCC_C1_AHB4LPENR_GPIOILPEN_Pos  = 0x8        // Position of GPIOILPEN field.
	RCC_C1_AHB4LPENR_GPIOILPEN_Msk  = 0x100      // Bit mask of GPIOILPEN field.
	RCC_C1_AHB4LPENR_GPIOILPEN      = 0x100      // Bit GPIOILPEN.
	RCC_C1_AHB4LPENR_GPIOJLPEN_Pos  = 0x9        // Position of GPIOJLPEN field.
	RCC_C1_AHB4LPENR_GPIOJLPEN_Msk  = 0x200      // Bit mask of GPIOJLPEN field.
	RCC_C1_AHB4LPENR_GPIOJLPEN      = 0x200      // Bit GPIOJLPEN.
	RCC_C1_AHB4LPENR_GPIOKLPEN_Pos  = 0xa        // Position of GPIOKLPEN field.
	RCC_C1_AHB4LPENR_GPIOKLPEN_Msk  = 0x400      // Bit mask of GPIOKLPEN field.
	RCC_C1_AHB4LPENR_GPIOKLPEN      = 0x400      // Bit GPIOKLPEN.
	RCC_C1_AHB4LPENR_CRCLPEN_Pos    = 0x13       // Position of CRCLPEN field.
	RCC_C1_AHB4LPENR_CRCLPEN_Msk    = 0x80000    // Bit mask of CRCLPEN field.
	RCC_C1_AHB4LPENR_CRCLPEN        = 0x80000    // Bit CRCLPEN.
	RCC_C1_AHB4LPENR_BDMALPEN_Pos   = 0x15       // Position of BDMALPEN field.
	RCC_C1_AHB4LPENR_BDMALPEN_Msk   = 0x200000   // Bit mask of BDMALPEN field.
	RCC_C1_AHB4LPENR_BDMALPEN       = 0x200000   // Bit BDMALPEN.
	RCC_C1_AHB4LPENR_ADC3LPEN_Pos   = 0x18       // Position of ADC3LPEN field.
	RCC_C1_AHB4LPENR_ADC3LPEN_Msk   = 0x1000000  // Bit mask of ADC3LPEN field.
	RCC_C1_AHB4LPENR_ADC3LPEN       = 0x1000000  // Bit ADC3LPEN.
	RCC_C1_AHB4LPENR_BKPRAMLPEN_Pos = 0x1c       // Position of BKPRAMLPEN field.
	RCC_C1_AHB4LPENR_BKPRAMLPEN_Msk = 0x10000000 // Bit mask of BKPRAMLPEN field.
	RCC_C1_AHB4LPENR_BKPRAMLPEN     = 0x10000000 // Bit BKPRAMLPEN.
	RCC_C1_AHB4LPENR_SRAM4LPEN_Pos  = 0x1d       // Position of SRAM4LPEN field.
	RCC_C1_AHB4LPENR_SRAM4LPEN_Msk  = 0x20000000 // Bit mask of SRAM4LPEN field.
	RCC_C1_AHB4LPENR_SRAM4LPEN      = 0x20000000 // Bit SRAM4LPEN.

	// C1_APB3LPENR: RCC APB3 Sleep Clock Register
	RCC_C1_APB3LPENR_LTDCLPEN_Pos  = 0x3  // Position of LTDCLPEN field.
	RCC_C1_APB3LPENR_LTDCLPEN_Msk  = 0x8  // Bit mask of LTDCLPEN field.
	RCC_C1_APB3LPENR_LTDCLPEN      = 0x8  // Bit LTDCLPEN.
	RCC_C1_APB3LPENR_WWDG1LPEN_Pos = 0x6  // Position of WWDG1LPEN field.
	RCC_C1_APB3LPENR_WWDG1LPEN_Msk = 0x40 // Bit mask of WWDG1LPEN field.
	RCC_C1_APB3LPENR_WWDG1LPEN     = 0x40 // Bit WWDG1LPEN.

	// C1_APB1LLPENR: RCC APB1 Low Sleep Clock           Register
	RCC_C1_APB1LLPENR_TIM2LPEN_Pos    = 0x0        // Position of TIM2LPEN field.
	RCC_C1_APB1LLPENR_TIM2LPEN_Msk    = 0x1        // Bit mask of TIM2LPEN field.
	RCC_C1_APB1LLPENR_TIM2LPEN        = 0x1        // Bit TIM2LPEN.
	RCC_C1_APB1LLPENR_TIM3LPEN_Pos    = 0x1        // Position of TIM3LPEN field.
	RCC_C1_APB1LLPENR_TIM3LPEN_Msk    = 0x2        // Bit mask of TIM3LPEN field.
	RCC_C1_APB1LLPENR_TIM3LPEN        = 0x2        // Bit TIM3LPEN.
	RCC_C1_APB1LLPENR_TIM4LPEN_Pos    = 0x2        // Position of TIM4LPEN field.
	RCC_C1_APB1LLPENR_TIM4LPEN_Msk    = 0x4        // Bit mask of TIM4LPEN field.
	RCC_C1_APB1LLPENR_TIM4LPEN        = 0x4        // Bit TIM4LPEN.
	RCC_C1_APB1LLPENR_TIM5LPEN_Pos    = 0x3        // Position of TIM5LPEN field.
	RCC_C1_APB1LLPENR_TIM5LPEN_Msk    = 0x8        // Bit mask of TIM5LPEN field.
	RCC_C1_APB1LLPENR_TIM5LPEN        = 0x8        // Bit TIM5LPEN.
	RCC_C1_APB1LLPENR_TIM6LPEN_Pos    = 0x4        // Position of TIM6LPEN field.
	RCC_C1_APB1LLPENR_TIM6LPEN_Msk    = 0x10       // Bit mask of TIM6LPEN field.
	RCC_C1_APB1LLPENR_TIM6LPEN        = 0x10       // Bit TIM6LPEN.
	RCC_C1_APB1LLPENR_TIM7LPEN_Pos    = 0x5        // Position of TIM7LPEN field.
	RCC_C1_APB1LLPENR_TIM7LPEN_Msk    = 0x20       // Bit mask of TIM7LPEN field.
	RCC_C1_APB1LLPENR_TIM7LPEN        = 0x20       // Bit TIM7LPEN.
	RCC_C1_APB1LLPENR_TIM12LPEN_Pos   = 0x6        // Position of TIM12LPEN field.
	RCC_C1_APB1LLPENR_TIM12LPEN_Msk   = 0x40       // Bit mask of TIM12LPEN field.
	RCC_C1_APB1LLPENR_TIM12LPEN       = 0x40       // Bit TIM12LPEN.
	RCC_C1_APB1LLPENR_TIM13LPEN_Pos   = 0x7        // Position of TIM13LPEN field.
	RCC_C1_APB1LLPENR_TIM13LPEN_Msk   = 0x80       // Bit mask of TIM13LPEN field.
	RCC_C1_APB1LLPENR_TIM13LPEN       = 0x80       // Bit TIM13LPEN.
	RCC_C1_APB1LLPENR_TIM14LPEN_Pos   = 0x8        // Position of TIM14LPEN field.
	RCC_C1_APB1LLPENR_TIM14LPEN_Msk   = 0x100      // Bit mask of TIM14LPEN field.
	RCC_C1_APB1LLPENR_TIM14LPEN       = 0x100      // Bit TIM14LPEN.
	RCC_C1_APB1LLPENR_LPTIM1LPEN_Pos  = 0x9        // Position of LPTIM1LPEN field.
	RCC_C1_APB1LLPENR_LPTIM1LPEN_Msk  = 0x200      // Bit mask of LPTIM1LPEN field.
	RCC_C1_APB1LLPENR_LPTIM1LPEN      = 0x200      // Bit LPTIM1LPEN.
	RCC_C1_APB1LLPENR_SPI2LPEN_Pos    = 0xe        // Position of SPI2LPEN field.
	RCC_C1_APB1LLPENR_SPI2LPEN_Msk    = 0x4000     // Bit mask of SPI2LPEN field.
	RCC_C1_APB1LLPENR_SPI2LPEN        = 0x4000     // Bit SPI2LPEN.
	RCC_C1_APB1LLPENR_SPI3LPEN_Pos    = 0xf        // Position of SPI3LPEN field.
	RCC_C1_APB1LLPENR_SPI3LPEN_Msk    = 0x8000     // Bit mask of SPI3LPEN field.
	RCC_C1_APB1LLPENR_SPI3LPEN        = 0x8000     // Bit SPI3LPEN.
	RCC_C1_APB1LLPENR_SPDIFRXLPEN_Pos = 0x10       // Position of SPDIFRXLPEN field.
	RCC_C1_APB1LLPENR_SPDIFRXLPEN_Msk = 0x10000    // Bit mask of SPDIFRXLPEN field.
	RCC_C1_APB1LLPENR_SPDIFRXLPEN     = 0x10000    // Bit SPDIFRXLPEN.
	RCC_C1_APB1LLPENR_USART2LPEN_Pos  = 0x11       // Position of USART2LPEN field.
	RCC_C1_APB1LLPENR_USART2LPEN_Msk  = 0x20000    // Bit mask of USART2LPEN field.
	RCC_C1_APB1LLPENR_USART2LPEN      = 0x20000    // Bit USART2LPEN.
	RCC_C1_APB1LLPENR_USART3LPEN_Pos  = 0x12       // Position of USART3LPEN field.
	RCC_C1_APB1LLPENR_USART3LPEN_Msk  = 0x40000    // Bit mask of USART3LPEN field.
	RCC_C1_APB1LLPENR_USART3LPEN      = 0x40000    // Bit USART3LPEN.
	RCC_C1_APB1LLPENR_UART4LPEN_Pos   = 0x13       // Position of UART4LPEN field.
	RCC_C1_APB1LLPENR_UART4LPEN_Msk   = 0x80000    // Bit mask of UART4LPEN field.
	RCC_C1_APB1LLPENR_UART4LPEN       = 0x80000    // Bit UART4LPEN.
	RCC_C1_APB1LLPENR_UART5LPEN_Pos   = 0x14       // Position of UART5LPEN field.
	RCC_C1_APB1LLPENR_UART5LPEN_Msk   = 0x100000   // Bit mask of UART5LPEN field.
	RCC_C1_APB1LLPENR_UART5LPEN       = 0x100000   // Bit UART5LPEN.
	RCC_C1_APB1LLPENR_I2C1LPEN_Pos    = 0x15       // Position of I2C1LPEN field.
	RCC_C1_APB1LLPENR_I2C1LPEN_Msk    = 0x200000   // Bit mask of I2C1LPEN field.
	RCC_C1_APB1LLPENR_I2C1LPEN        = 0x200000   // Bit I2C1LPEN.
	RCC_C1_APB1LLPENR_I2C2LPEN_Pos    = 0x16       // Position of I2C2LPEN field.
	RCC_C1_APB1LLPENR_I2C2LPEN_Msk    = 0x400000   // Bit mask of I2C2LPEN field.
	RCC_C1_APB1LLPENR_I2C2LPEN        = 0x400000   // Bit I2C2LPEN.
	RCC_C1_APB1LLPENR_I2C3LPEN_Pos    = 0x17       // Position of I2C3LPEN field.
	RCC_C1_APB1LLPENR_I2C3LPEN_Msk    = 0x800000   // Bit mask of I2C3LPEN field.
	RCC_C1_APB1LLPENR_I2C3LPEN        = 0x800000   // Bit I2C3LPEN.
	RCC_C1_APB1LLPENR_HDMICECLPEN_Pos = 0x1b       // Position of HDMICECLPEN field.
	RCC_C1_APB1LLPENR_HDMICECLPEN_Msk = 0x8000000  // Bit mask of HDMICECLPEN field.
	RCC_C1_APB1LLPENR_HDMICECLPEN     = 0x8000000  // Bit HDMICECLPEN.
	RCC_C1_APB1LLPENR_DAC12LPEN_Pos   = 0x1d       // Position of DAC12LPEN field.
	RCC_C1_APB1LLPENR_DAC12LPEN_Msk   = 0x20000000 // Bit mask of DAC12LPEN field.
	RCC_C1_APB1LLPENR_DAC12LPEN       = 0x20000000 // Bit DAC12LPEN.
	RCC_C1_APB1LLPENR_USART7LPEN_Pos  = 0x1e       // Position of USART7LPEN field.
	RCC_C1_APB1LLPENR_USART7LPEN_Msk  = 0x40000000 // Bit mask of USART7LPEN field.
	RCC_C1_APB1LLPENR_USART7LPEN      = 0x40000000 // Bit USART7LPEN.
	RCC_C1_APB1LLPENR_USART8LPEN_Pos  = 0x1f       // Position of USART8LPEN field.
	RCC_C1_APB1LLPENR_USART8LPEN_Msk  = 0x80000000 // Bit mask of USART8LPEN field.
	RCC_C1_APB1LLPENR_USART8LPEN      = 0x80000000 // Bit USART8LPEN.

	// C1_APB1HLPENR: RCC APB1 High Sleep Clock           Register
	RCC_C1_APB1HLPENR_CRSLPEN_Pos   = 0x1   // Position of CRSLPEN field.
	RCC_C1_APB1HLPENR_CRSLPEN_Msk   = 0x2   // Bit mask of CRSLPEN field.
	RCC_C1_APB1HLPENR_CRSLPEN       = 0x2   // Bit CRSLPEN.
	RCC_C1_APB1HLPENR_SWPLPEN_Pos   = 0x2   // Position of SWPLPEN field.
	RCC_C1_APB1HLPENR_SWPLPEN_Msk   = 0x4   // Bit mask of SWPLPEN field.
	RCC_C1_APB1HLPENR_SWPLPEN       = 0x4   // Bit SWPLPEN.
	RCC_C1_APB1HLPENR_OPAMPLPEN_Pos = 0x4   // Position of OPAMPLPEN field.
	RCC_C1_APB1HLPENR_OPAMPLPEN_Msk = 0x10  // Bit mask of OPAMPLPEN field.
	RCC_C1_APB1HLPENR_OPAMPLPEN     = 0x10  // Bit OPAMPLPEN.
	RCC_C1_APB1HLPENR_MDIOSLPEN_Pos = 0x5   // Position of MDIOSLPEN field.
	RCC_C1_APB1HLPENR_MDIOSLPEN_Msk = 0x20  // Bit mask of MDIOSLPEN field.
	RCC_C1_APB1HLPENR_MDIOSLPEN     = 0x20  // Bit MDIOSLPEN.
	RCC_C1_APB1HLPENR_FDCANLPEN_Pos = 0x8   // Position of FDCANLPEN field.
	RCC_C1_APB1HLPENR_FDCANLPEN_Msk = 0x100 // Bit mask of FDCANLPEN field.
	RCC_C1_APB1HLPENR_FDCANLPEN     = 0x100 // Bit FDCANLPEN.

	// C1_APB2LPENR: RCC APB2 Sleep Clock Register
	RCC_C1_APB2LPENR_TIM1LPEN_Pos   = 0x0        // Position of TIM1LPEN field.
	RCC_C1_APB2LPENR_TIM1LPEN_Msk   = 0x1        // Bit mask of TIM1LPEN field.
	RCC_C1_APB2LPENR_TIM1LPEN       = 0x1        // Bit TIM1LPEN.
	RCC_C1_APB2LPENR_TIM8LPEN_Pos   = 0x1        // Position of TIM8LPEN field.
	RCC_C1_APB2LPENR_TIM8LPEN_Msk   = 0x2        // Bit mask of TIM8LPEN field.
	RCC_C1_APB2LPENR_TIM8LPEN       = 0x2        // Bit TIM8LPEN.
	RCC_C1_APB2LPENR_USART1LPEN_Pos = 0x4        // Position of USART1LPEN field.
	RCC_C1_APB2LPENR_USART1LPEN_Msk = 0x10       // Bit mask of USART1LPEN field.
	RCC_C1_APB2LPENR_USART1LPEN     = 0x10       // Bit USART1LPEN.
	RCC_C1_APB2LPENR_USART6LPEN_Pos = 0x5        // Position of USART6LPEN field.
	RCC_C1_APB2LPENR_USART6LPEN_Msk = 0x20       // Bit mask of USART6LPEN field.
	RCC_C1_APB2LPENR_USART6LPEN     = 0x20       // Bit USART6LPEN.
	RCC_C1_APB2LPENR_SPI1LPEN_Pos   = 0xc        // Position of SPI1LPEN field.
	RCC_C1_APB2LPENR_SPI1LPEN_Msk   = 0x1000     // Bit mask of SPI1LPEN field.
	RCC_C1_APB2LPENR_SPI1LPEN       = 0x1000     // Bit SPI1LPEN.
	RCC_C1_APB2LPENR_SPI4LPEN_Pos   = 0xd        // Position of SPI4LPEN field.
	RCC_C1_APB2LPENR_SPI4LPEN_Msk   = 0x2000     // Bit mask of SPI4LPEN field.
	RCC_C1_APB2LPENR_SPI4LPEN       = 0x2000     // Bit SPI4LPEN.
	RCC_C1_APB2LPENR_TIM15LPEN_Pos  = 0x10       // Position of TIM15LPEN field.
	RCC_C1_APB2LPENR_TIM15LPEN_Msk  = 0x10000    // Bit mask of TIM15LPEN field.
	RCC_C1_APB2LPENR_TIM15LPEN      = 0x10000    // Bit TIM15LPEN.
	RCC_C1_APB2LPENR_TIM16LPEN_Pos  = 0x11       // Position of TIM16LPEN field.
	RCC_C1_APB2LPENR_TIM16LPEN_Msk  = 0x20000    // Bit mask of TIM16LPEN field.
	RCC_C1_APB2LPENR_TIM16LPEN      = 0x20000    // Bit TIM16LPEN.
	RCC_C1_APB2LPENR_TIM17LPEN_Pos  = 0x12       // Position of TIM17LPEN field.
	RCC_C1_APB2LPENR_TIM17LPEN_Msk  = 0x40000    // Bit mask of TIM17LPEN field.
	RCC_C1_APB2LPENR_TIM17LPEN      = 0x40000    // Bit TIM17LPEN.
	RCC_C1_APB2LPENR_SPI5LPEN_Pos   = 0x14       // Position of SPI5LPEN field.
	RCC_C1_APB2LPENR_SPI5LPEN_Msk   = 0x100000   // Bit mask of SPI5LPEN field.
	RCC_C1_APB2LPENR_SPI5LPEN       = 0x100000   // Bit SPI5LPEN.
	RCC_C1_APB2LPENR_SAI1LPEN_Pos   = 0x16       // Position of SAI1LPEN field.
	RCC_C1_APB2LPENR_SAI1LPEN_Msk   = 0x400000   // Bit mask of SAI1LPEN field.
	RCC_C1_APB2LPENR_SAI1LPEN       = 0x400000   // Bit SAI1LPEN.
	RCC_C1_APB2LPENR_SAI2LPEN_Pos   = 0x17       // Position of SAI2LPEN field.
	RCC_C1_APB2LPENR_SAI2LPEN_Msk   = 0x800000   // Bit mask of SAI2LPEN field.
	RCC_C1_APB2LPENR_SAI2LPEN       = 0x800000   // Bit SAI2LPEN.
	RCC_C1_APB2LPENR_SAI3LPEN_Pos   = 0x18       // Position of SAI3LPEN field.
	RCC_C1_APB2LPENR_SAI3LPEN_Msk   = 0x1000000  // Bit mask of SAI3LPEN field.
	RCC_C1_APB2LPENR_SAI3LPEN       = 0x1000000  // Bit SAI3LPEN.
	RCC_C1_APB2LPENR_DFSDM1LPEN_Pos = 0x1c       // Position of DFSDM1LPEN field.
	RCC_C1_APB2LPENR_DFSDM1LPEN_Msk = 0x10000000 // Bit mask of DFSDM1LPEN field.
	RCC_C1_APB2LPENR_DFSDM1LPEN     = 0x10000000 // Bit DFSDM1LPEN.
	RCC_C1_APB2LPENR_HRTIMLPEN_Pos  = 0x1d       // Position of HRTIMLPEN field.
	RCC_C1_APB2LPENR_HRTIMLPEN_Msk  = 0x20000000 // Bit mask of HRTIMLPEN field.
	RCC_C1_APB2LPENR_HRTIMLPEN      = 0x20000000 // Bit HRTIMLPEN.

	// C1_APB4LPENR: RCC APB4 Sleep Clock Register
	RCC_C1_APB4LPENR_SYSCFGLPEN_Pos  = 0x1      // Position of SYSCFGLPEN field.
	RCC_C1_APB4LPENR_SYSCFGLPEN_Msk  = 0x2      // Bit mask of SYSCFGLPEN field.
	RCC_C1_APB4LPENR_SYSCFGLPEN      = 0x2      // Bit SYSCFGLPEN.
	RCC_C1_APB4LPENR_LPUART1LPEN_Pos = 0x3      // Position of LPUART1LPEN field.
	RCC_C1_APB4LPENR_LPUART1LPEN_Msk = 0x8      // Bit mask of LPUART1LPEN field.
	RCC_C1_APB4LPENR_LPUART1LPEN     = 0x8      // Bit LPUART1LPEN.
	RCC_C1_APB4LPENR_SPI6LPEN_Pos    = 0x5      // Position of SPI6LPEN field.
	RCC_C1_APB4LPENR_SPI6LPEN_Msk    = 0x20     // Bit mask of SPI6LPEN field.
	RCC_C1_APB4LPENR_SPI6LPEN        = 0x20     // Bit SPI6LPEN.
	RCC_C1_APB4LPENR_I2C4LPEN_Pos    = 0x7      // Position of I2C4LPEN field.
	RCC_C1_APB4LPENR_I2C4LPEN_Msk    = 0x80     // Bit mask of I2C4LPEN field.
	RCC_C1_APB4LPENR_I2C4LPEN        = 0x80     // Bit I2C4LPEN.
	RCC_C1_APB4LPENR_LPTIM2LPEN_Pos  = 0x9      // Position of LPTIM2LPEN field.
	RCC_C1_APB4LPENR_LPTIM2LPEN_Msk  = 0x200    // Bit mask of LPTIM2LPEN field.
	RCC_C1_APB4LPENR_LPTIM2LPEN      = 0x200    // Bit LPTIM2LPEN.
	RCC_C1_APB4LPENR_LPTIM3LPEN_Pos  = 0xa      // Position of LPTIM3LPEN field.
	RCC_C1_APB4LPENR_LPTIM3LPEN_Msk  = 0x400    // Bit mask of LPTIM3LPEN field.
	RCC_C1_APB4LPENR_LPTIM3LPEN      = 0x400    // Bit LPTIM3LPEN.
	RCC_C1_APB4LPENR_LPTIM4LPEN_Pos  = 0xb      // Position of LPTIM4LPEN field.
	RCC_C1_APB4LPENR_LPTIM4LPEN_Msk  = 0x800    // Bit mask of LPTIM4LPEN field.
	RCC_C1_APB4LPENR_LPTIM4LPEN      = 0x800    // Bit LPTIM4LPEN.
	RCC_C1_APB4LPENR_LPTIM5LPEN_Pos  = 0xc      // Position of LPTIM5LPEN field.
	RCC_C1_APB4LPENR_LPTIM5LPEN_Msk  = 0x1000   // Bit mask of LPTIM5LPEN field.
	RCC_C1_APB4LPENR_LPTIM5LPEN      = 0x1000   // Bit LPTIM5LPEN.
	RCC_C1_APB4LPENR_COMP12LPEN_Pos  = 0xe      // Position of COMP12LPEN field.
	RCC_C1_APB4LPENR_COMP12LPEN_Msk  = 0x4000   // Bit mask of COMP12LPEN field.
	RCC_C1_APB4LPENR_COMP12LPEN      = 0x4000   // Bit COMP12LPEN.
	RCC_C1_APB4LPENR_VREFLPEN_Pos    = 0xf      // Position of VREFLPEN field.
	RCC_C1_APB4LPENR_VREFLPEN_Msk    = 0x8000   // Bit mask of VREFLPEN field.
	RCC_C1_APB4LPENR_VREFLPEN        = 0x8000   // Bit VREFLPEN.
	RCC_C1_APB4LPENR_RTCAPBLPEN_Pos  = 0x10     // Position of RTCAPBLPEN field.
	RCC_C1_APB4LPENR_RTCAPBLPEN_Msk  = 0x10000  // Bit mask of RTCAPBLPEN field.
	RCC_C1_APB4LPENR_RTCAPBLPEN      = 0x10000  // Bit RTCAPBLPEN.
	RCC_C1_APB4LPENR_SAI4LPEN_Pos    = 0x15     // Position of SAI4LPEN field.
	RCC_C1_APB4LPENR_SAI4LPEN_Msk    = 0x200000 // Bit mask of SAI4LPEN field.
	RCC_C1_APB4LPENR_SAI4LPEN        = 0x200000 // Bit SAI4LPEN.
)

// Bitfields for LPTIM1: Low power timer
const (
	// ISR: Interrupt and Status Register
	LPTIM_ISR_DOWN_Pos    = 0x6  // Position of DOWN field.
	LPTIM_ISR_DOWN_Msk    = 0x40 // Bit mask of DOWN field.
	LPTIM_ISR_DOWN        = 0x40 // Bit DOWN.
	LPTIM_ISR_UP_Pos      = 0x5  // Position of UP field.
	LPTIM_ISR_UP_Msk      = 0x20 // Bit mask of UP field.
	LPTIM_ISR_UP          = 0x20 // Bit UP.
	LPTIM_ISR_ARROK_Pos   = 0x4  // Position of ARROK field.
	LPTIM_ISR_ARROK_Msk   = 0x10 // Bit mask of ARROK field.
	LPTIM_ISR_ARROK       = 0x10 // Bit ARROK.
	LPTIM_ISR_CMPOK_Pos   = 0x3  // Position of CMPOK field.
	LPTIM_ISR_CMPOK_Msk   = 0x8  // Bit mask of CMPOK field.
	LPTIM_ISR_CMPOK       = 0x8  // Bit CMPOK.
	LPTIM_ISR_EXTTRIG_Pos = 0x2  // Position of EXTTRIG field.
	LPTIM_ISR_EXTTRIG_Msk = 0x4  // Bit mask of EXTTRIG field.
	LPTIM_ISR_EXTTRIG     = 0x4  // Bit EXTTRIG.
	LPTIM_ISR_ARRM_Pos    = 0x1  // Position of ARRM field.
	LPTIM_ISR_ARRM_Msk    = 0x2  // Bit mask of ARRM field.
	LPTIM_ISR_ARRM        = 0x2  // Bit ARRM.
	LPTIM_ISR_CMPM_Pos    = 0x0  // Position of CMPM field.
	LPTIM_ISR_CMPM_Msk    = 0x1  // Bit mask of CMPM field.
	LPTIM_ISR_CMPM        = 0x1  // Bit CMPM.

	// ICR: Interrupt Clear Register
	LPTIM_ICR_DOWNCF_Pos    = 0x6  // Position of DOWNCF field.
	LPTIM_ICR_DOWNCF_Msk    = 0x40 // Bit mask of DOWNCF field.
	LPTIM_ICR_DOWNCF        = 0x40 // Bit DOWNCF.
	LPTIM_ICR_UPCF_Pos      = 0x5  // Position of UPCF field.
	LPTIM_ICR_UPCF_Msk      = 0x20 // Bit mask of UPCF field.
	LPTIM_ICR_UPCF          = 0x20 // Bit UPCF.
	LPTIM_ICR_ARROKCF_Pos   = 0x4  // Position of ARROKCF field.
	LPTIM_ICR_ARROKCF_Msk   = 0x10 // Bit mask of ARROKCF field.
	LPTIM_ICR_ARROKCF       = 0x10 // Bit ARROKCF.
	LPTIM_ICR_CMPOKCF_Pos   = 0x3  // Position of CMPOKCF field.
	LPTIM_ICR_CMPOKCF_Msk   = 0x8  // Bit mask of CMPOKCF field.
	LPTIM_ICR_CMPOKCF       = 0x8  // Bit CMPOKCF.
	LPTIM_ICR_EXTTRIGCF_Pos = 0x2  // Position of EXTTRIGCF field.
	LPTIM_ICR_EXTTRIGCF_Msk = 0x4  // Bit mask of EXTTRIGCF field.
	LPTIM_ICR_EXTTRIGCF     = 0x4  // Bit EXTTRIGCF.
	LPTIM_ICR_ARRMCF_Pos    = 0x1  // Position of ARRMCF field.
	LPTIM_ICR_ARRMCF_Msk    = 0x2  // Bit mask of ARRMCF field.
	LPTIM_ICR_ARRMCF        = 0x2  // Bit ARRMCF.
	LPTIM_ICR_CMPMCF_Pos    = 0x0  // Position of CMPMCF field.
	LPTIM_ICR_CMPMCF_Msk    = 0x1  // Bit mask of CMPMCF field.
	LPTIM_ICR_CMPMCF        = 0x1  // Bit CMPMCF.

	// IER: Interrupt Enable Register
	LPTIM_IER_DOWNIE_Pos    = 0x6  // Position of DOWNIE field.
	LPTIM_IER_DOWNIE_Msk    = 0x40 // Bit mask of DOWNIE field.
	LPTIM_IER_DOWNIE        = 0x40 // Bit DOWNIE.
	LPTIM_IER_UPIE_Pos      = 0x5  // Position of UPIE field.
	LPTIM_IER_UPIE_Msk      = 0x20 // Bit mask of UPIE field.
	LPTIM_IER_UPIE          = 0x20 // Bit UPIE.
	LPTIM_IER_ARROKIE_Pos   = 0x4  // Position of ARROKIE field.
	LPTIM_IER_ARROKIE_Msk   = 0x10 // Bit mask of ARROKIE field.
	LPTIM_IER_ARROKIE       = 0x10 // Bit ARROKIE.
	LPTIM_IER_CMPOKIE_Pos   = 0x3  // Position of CMPOKIE field.
	LPTIM_IER_CMPOKIE_Msk   = 0x8  // Bit mask of CMPOKIE field.
	LPTIM_IER_CMPOKIE       = 0x8  // Bit CMPOKIE.
	LPTIM_IER_EXTTRIGIE_Pos = 0x2  // Position of EXTTRIGIE field.
	LPTIM_IER_EXTTRIGIE_Msk = 0x4  // Bit mask of EXTTRIGIE field.
	LPTIM_IER_EXTTRIGIE     = 0x4  // Bit EXTTRIGIE.
	LPTIM_IER_ARRMIE_Pos    = 0x1  // Position of ARRMIE field.
	LPTIM_IER_ARRMIE_Msk    = 0x2  // Bit mask of ARRMIE field.
	LPTIM_IER_ARRMIE        = 0x2  // Bit ARRMIE.
	LPTIM_IER_CMPMIE_Pos    = 0x0  // Position of CMPMIE field.
	LPTIM_IER_CMPMIE_Msk    = 0x1  // Bit mask of CMPMIE field.
	LPTIM_IER_CMPMIE        = 0x1  // Bit CMPMIE.

	// CFGR: Configuration Register
	LPTIM_CFGR_ENC_Pos       = 0x18      // Position of ENC field.
	LPTIM_CFGR_ENC_Msk       = 0x1000000 // Bit mask of ENC field.
	LPTIM_CFGR_ENC           = 0x1000000 // Bit ENC.
	LPTIM_CFGR_COUNTMODE_Pos = 0x17      // Position of COUNTMODE field.
	LPTIM_CFGR_COUNTMODE_Msk = 0x800000  // Bit mask of COUNTMODE field.
	LPTIM_CFGR_COUNTMODE     = 0x800000  // Bit COUNTMODE.
	LPTIM_CFGR_PRELOAD_Pos   = 0x16      // Position of PRELOAD field.
	LPTIM_CFGR_PRELOAD_Msk   = 0x400000  // Bit mask of PRELOAD field.
	LPTIM_CFGR_PRELOAD       = 0x400000  // Bit PRELOAD.
	LPTIM_CFGR_WAVPOL_Pos    = 0x15      // Position of WAVPOL field.
	LPTIM_CFGR_WAVPOL_Msk    = 0x200000  // Bit mask of WAVPOL field.
	LPTIM_CFGR_WAVPOL        = 0x200000  // Bit WAVPOL.
	LPTIM_CFGR_WAVE_Pos      = 0x14      // Position of WAVE field.
	LPTIM_CFGR_WAVE_Msk      = 0x100000  // Bit mask of WAVE field.
	LPTIM_CFGR_WAVE          = 0x100000  // Bit WAVE.
	LPTIM_CFGR_TIMOUT_Pos    = 0x13      // Position of TIMOUT field.
	LPTIM_CFGR_TIMOUT_Msk    = 0x80000   // Bit mask of TIMOUT field.
	LPTIM_CFGR_TIMOUT        = 0x80000   // Bit TIMOUT.
	LPTIM_CFGR_TRIGEN_Pos    = 0x11      // Position of TRIGEN field.
	LPTIM_CFGR_TRIGEN_Msk    = 0x60000   // Bit mask of TRIGEN field.
	LPTIM_CFGR_TRIGSEL_Pos   = 0xd       // Position of TRIGSEL field.
	LPTIM_CFGR_TRIGSEL_Msk   = 0xe000    // Bit mask of TRIGSEL field.
	LPTIM_CFGR_PRESC_Pos     = 0x9       // Position of PRESC field.
	LPTIM_CFGR_PRESC_Msk     = 0xe00     // Bit mask of PRESC field.
	LPTIM_CFGR_TRGFLT_Pos    = 0x6       // Position of TRGFLT field.
	LPTIM_CFGR_TRGFLT_Msk    = 0xc0      // Bit mask of TRGFLT field.
	LPTIM_CFGR_CKFLT_Pos     = 0x3       // Position of CKFLT field.
	LPTIM_CFGR_CKFLT_Msk     = 0x18      // Bit mask of CKFLT field.
	LPTIM_CFGR_CKPOL_Pos     = 0x1       // Position of CKPOL field.
	LPTIM_CFGR_CKPOL_Msk     = 0x6       // Bit mask of CKPOL field.
	LPTIM_CFGR_CKSEL_Pos     = 0x0       // Position of CKSEL field.
	LPTIM_CFGR_CKSEL_Msk     = 0x1       // Bit mask of CKSEL field.
	LPTIM_CFGR_CKSEL         = 0x1       // Bit CKSEL.

	// CR: Control Register
	LPTIM_CR_ENABLE_Pos   = 0x0  // Position of ENABLE field.
	LPTIM_CR_ENABLE_Msk   = 0x1  // Bit mask of ENABLE field.
	LPTIM_CR_ENABLE       = 0x1  // Bit ENABLE.
	LPTIM_CR_SNGSTRT_Pos  = 0x1  // Position of SNGSTRT field.
	LPTIM_CR_SNGSTRT_Msk  = 0x2  // Bit mask of SNGSTRT field.
	LPTIM_CR_SNGSTRT      = 0x2  // Bit SNGSTRT.
	LPTIM_CR_CNTSTRT_Pos  = 0x2  // Position of CNTSTRT field.
	LPTIM_CR_CNTSTRT_Msk  = 0x4  // Bit mask of CNTSTRT field.
	LPTIM_CR_CNTSTRT      = 0x4  // Bit CNTSTRT.
	LPTIM_CR_COUNTRST_Pos = 0x3  // Position of COUNTRST field.
	LPTIM_CR_COUNTRST_Msk = 0x8  // Bit mask of COUNTRST field.
	LPTIM_CR_COUNTRST     = 0x8  // Bit COUNTRST.
	LPTIM_CR_RSTARE_Pos   = 0x4  // Position of RSTARE field.
	LPTIM_CR_RSTARE_Msk   = 0x10 // Bit mask of RSTARE field.
	LPTIM_CR_RSTARE       = 0x10 // Bit RSTARE.

	// CMP: Compare Register
	LPTIM_CMP_CMP_Pos = 0x0    // Position of CMP field.
	LPTIM_CMP_CMP_Msk = 0xffff // Bit mask of CMP field.

	// ARR: Autoreload Register
	LPTIM_ARR_ARR_Pos = 0x0    // Position of ARR field.
	LPTIM_ARR_ARR_Msk = 0xffff // Bit mask of ARR field.

	// CNT: Counter Register
	LPTIM_CNT_CNT_Pos = 0x0    // Position of CNT field.
	LPTIM_CNT_CNT_Msk = 0xffff // Bit mask of CNT field.

	// CFGR2: LPTIM configuration register 2
	LPTIM_CFGR2_IN1SEL_Pos = 0x0  // Position of IN1SEL field.
	LPTIM_CFGR2_IN1SEL_Msk = 0x3  // Bit mask of IN1SEL field.
	LPTIM_CFGR2_IN2SEL_Pos = 0x4  // Position of IN2SEL field.
	LPTIM_CFGR2_IN2SEL_Msk = 0x30 // Bit mask of IN2SEL field.
)

// Bitfields for LPUART1: LPUART1
const (
	// CR1: Control register 1
	LPUART_CR1_RXFFIE_Pos = 0x1f       // Position of RXFFIE field.
	LPUART_CR1_RXFFIE_Msk = 0x80000000 // Bit mask of RXFFIE field.
	LPUART_CR1_RXFFIE     = 0x80000000 // Bit RXFFIE.
	LPUART_CR1_TXFEIE_Pos = 0x1e       // Position of TXFEIE field.
	LPUART_CR1_TXFEIE_Msk = 0x40000000 // Bit mask of TXFEIE field.
	LPUART_CR1_TXFEIE     = 0x40000000 // Bit TXFEIE.
	LPUART_CR1_FIFOEN_Pos = 0x1d       // Position of FIFOEN field.
	LPUART_CR1_FIFOEN_Msk = 0x20000000 // Bit mask of FIFOEN field.
	LPUART_CR1_FIFOEN     = 0x20000000 // Bit FIFOEN.
	LPUART_CR1_M1_Pos     = 0x1c       // Position of M1 field.
	LPUART_CR1_M1_Msk     = 0x10000000 // Bit mask of M1 field.
	LPUART_CR1_M1         = 0x10000000 // Bit M1.
	LPUART_CR1_DEAT_Pos   = 0x15       // Position of DEAT field.
	LPUART_CR1_DEAT_Msk   = 0x3e00000  // Bit mask of DEAT field.
	LPUART_CR1_DEDT_Pos   = 0x10       // Position of DEDT field.
	LPUART_CR1_DEDT_Msk   = 0x1f0000   // Bit mask of DEDT field.
	LPUART_CR1_CMIE_Pos   = 0xe        // Position of CMIE field.
	LPUART_CR1_CMIE_Msk   = 0x4000     // Bit mask of CMIE field.
	LPUART_CR1_CMIE       = 0x4000     // Bit CMIE.
	LPUART_CR1_MME_Pos    = 0xd        // Position of MME field.
	LPUART_CR1_MME_Msk    = 0x2000     // Bit mask of MME field.
	LPUART_CR1_MME        = 0x2000     // Bit MME.
	LPUART_CR1_M0_Pos     = 0xc        // Position of M0 field.
	LPUART_CR1_M0_Msk     = 0x1000     // Bit mask of M0 field.
	LPUART_CR1_M0         = 0x1000     // Bit M0.
	LPUART_CR1_WAKE_Pos   = 0xb        // Position of WAKE field.
	LPUART_CR1_WAKE_Msk   = 0x800      // Bit mask of WAKE field.
	LPUART_CR1_WAKE       = 0x800      // Bit WAKE.
	LPUART_CR1_PCE_Pos    = 0xa        // Position of PCE field.
	LPUART_CR1_PCE_Msk    = 0x400      // Bit mask of PCE field.
	LPUART_CR1_PCE        = 0x400      // Bit PCE.
	LPUART_CR1_PS_Pos     = 0x9        // Position of PS field.
	LPUART_CR1_PS_Msk     = 0x200      // Bit mask of PS field.
	LPUART_CR1_PS         = 0x200      // Bit PS.
	LPUART_CR1_PEIE_Pos   = 0x8        // Position of PEIE field.
	LPUART_CR1_PEIE_Msk   = 0x100      // Bit mask of PEIE field.
	LPUART_CR1_PEIE       = 0x100      // Bit PEIE.
	LPUART_CR1_TXEIE_Pos  = 0x7        // Position of TXEIE field.
	LPUART_CR1_TXEIE_Msk  = 0x80       // Bit mask of TXEIE field.
	LPUART_CR1_TXEIE      = 0x80       // Bit TXEIE.
	LPUART_CR1_TCIE_Pos   = 0x6        // Position of TCIE field.
	LPUART_CR1_TCIE_Msk   = 0x40       // Bit mask of TCIE field.
	LPUART_CR1_TCIE       = 0x40       // Bit TCIE.
	LPUART_CR1_RXNEIE_Pos = 0x5        // Position of RXNEIE field.
	LPUART_CR1_RXNEIE_Msk = 0x20       // Bit mask of RXNEIE field.
	LPUART_CR1_RXNEIE     = 0x20       // Bit RXNEIE.
	LPUART_CR1_IDLEIE_Pos = 0x4        // Position of IDLEIE field.
	LPUART_CR1_IDLEIE_Msk = 0x10       // Bit mask of IDLEIE field.
	LPUART_CR1_IDLEIE     = 0x10       // Bit IDLEIE.
	LPUART_CR1_TE_Pos     = 0x3        // Position of TE field.
	LPUART_CR1_TE_Msk     = 0x8        // Bit mask of TE field.
	LPUART_CR1_TE         = 0x8        // Bit TE.
	LPUART_CR1_RE_Pos     = 0x2        // Position of RE field.
	LPUART_CR1_RE_Msk     = 0x4        // Bit mask of RE field.
	LPUART_CR1_RE         = 0x4        // Bit RE.
	LPUART_CR1_UESM_Pos   = 0x1        // Position of UESM field.
	LPUART_CR1_UESM_Msk   = 0x2        // Bit mask of UESM field.
	LPUART_CR1_UESM       = 0x2        // Bit UESM.
	LPUART_CR1_UE_Pos     = 0x0        // Position of UE field.
	LPUART_CR1_UE_Msk     = 0x1        // Bit mask of UE field.
	LPUART_CR1_UE         = 0x1        // Bit UE.

	// CR2: Control register 2
	LPUART_CR2_ADD_Pos      = 0x18       // Position of ADD field.
	LPUART_CR2_ADD_Msk      = 0xff000000 // Bit mask of ADD field.
	LPUART_CR2_MSBFIRST_Pos = 0x13       // Position of MSBFIRST field.
	LPUART_CR2_MSBFIRST_Msk = 0x80000    // Bit mask of MSBFIRST field.
	LPUART_CR2_MSBFIRST     = 0x80000    // Bit MSBFIRST.
	LPUART_CR2_DATAINV_Pos  = 0x12       // Position of DATAINV field.
	LPUART_CR2_DATAINV_Msk  = 0x40000    // Bit mask of DATAINV field.
	LPUART_CR2_DATAINV      = 0x40000    // Bit DATAINV.
	LPUART_CR2_TXINV_Pos    = 0x11       // Position of TXINV field.
	LPUART_CR2_TXINV_Msk    = 0x20000    // Bit mask of TXINV field.
	LPUART_CR2_TXINV        = 0x20000    // Bit TXINV.
	LPUART_CR2_RXINV_Pos    = 0x10       // Position of RXINV field.
	LPUART_CR2_RXINV_Msk    = 0x10000    // Bit mask of RXINV field.
	LPUART_CR2_RXINV        = 0x10000    // Bit RXINV.
	LPUART_CR2_SWAP_Pos     = 0xf        // Position of SWAP field.
	LPUART_CR2_SWAP_Msk     = 0x8000     // Bit mask of SWAP field.
	LPUART_CR2_SWAP         = 0x8000     // Bit SWAP.
	LPUART_CR2_STOP_Pos     = 0xc        // Position of STOP field.
	LPUART_CR2_STOP_Msk     = 0x3000     // Bit mask of STOP field.
	LPUART_CR2_ADDM7_Pos    = 0x4        // Position of ADDM7 field.
	LPUART_CR2_ADDM7_Msk    = 0x10       // Bit mask of ADDM7 field.
	LPUART_CR2_ADDM7        = 0x10       // Bit ADDM7.

	// CR3: Control register 3
	LPUART_CR3_TXFTCFG_Pos = 0x1d       // Position of TXFTCFG field.
	LPUART_CR3_TXFTCFG_Msk = 0xe0000000 // Bit mask of TXFTCFG field.
	LPUART_CR3_RXFTIE_Pos  = 0x1c       // Position of RXFTIE field.
	LPUART_CR3_RXFTIE_Msk  = 0x10000000 // Bit mask of RXFTIE field.
	LPUART_CR3_RXFTIE      = 0x10000000 // Bit RXFTIE.
	LPUART_CR3_RXFTCFG_Pos = 0x19       // Position of RXFTCFG field.
	LPUART_CR3_RXFTCFG_Msk = 0xe000000  // Bit mask of RXFTCFG field.
	LPUART_CR3_TXFTIE_Pos  = 0x17       // Position of TXFTIE field.
	LPUART_CR3_TXFTIE_Msk  = 0x800000   // Bit mask of TXFTIE field.
	LPUART_CR3_TXFTIE      = 0x800000   // Bit TXFTIE.
	LPUART_CR3_WUFIE_Pos   = 0x16       // Position of WUFIE field.
	LPUART_CR3_WUFIE_Msk   = 0x400000   // Bit mask of WUFIE field.
	LPUART_CR3_WUFIE       = 0x400000   // Bit WUFIE.
	LPUART_CR3_WUS_Pos     = 0x14       // Position of WUS field.
	LPUART_CR3_WUS_Msk     = 0x300000   // Bit mask of WUS field.
	LPUART_CR3_DEP_Pos     = 0xf        // Position of DEP field.
	LPUART_CR3_DEP_Msk     = 0x8000     // Bit mask of DEP field.
	LPUART_CR3_DEP         = 0x8000     // Bit DEP.
	LPUART_CR3_DEM_Pos     = 0xe        // Position of DEM field.
	LPUART_CR3_DEM_Msk     = 0x4000     // Bit mask of DEM field.
	LPUART_CR3_DEM         = 0x4000     // Bit DEM.
	LPUART_CR3_DDRE_Pos    = 0xd        // Position of DDRE field.
	LPUART_CR3_DDRE_Msk    = 0x2000     // Bit mask of DDRE field.
	LPUART_CR3_DDRE        = 0x2000     // Bit DDRE.
	LPUART_CR3_OVRDIS_Pos  = 0xc        // Position of OVRDIS field.
	LPUART_CR3_OVRDIS_Msk  = 0x1000     // Bit mask of OVRDIS field.
	LPUART_CR3_OVRDIS      = 0x1000     // Bit OVRDIS.
	LPUART_CR3_CTSIE_Pos   = 0xa        // Position of CTSIE field.
	LPUART_CR3_CTSIE_Msk   = 0x400      // Bit mask of CTSIE field.
	LPUART_CR3_CTSIE       = 0x400      // Bit CTSIE.
	LPUART_CR3_CTSE_Pos    = 0x9        // Position of CTSE field.
	LPUART_CR3_CTSE_Msk    = 0x200      // Bit mask of CTSE field.
	LPUART_CR3_CTSE        = 0x200      // Bit CTSE.
	LPUART_CR3_RTSE_Pos    = 0x8        // Position of RTSE field.
	LPUART_CR3_RTSE_Msk    = 0x100      // Bit mask of RTSE field.
	LPUART_CR3_RTSE        = 0x100      // Bit RTSE.
	LPUART_CR3_DMAT_Pos    = 0x7        // Position of DMAT field.
	LPUART_CR3_DMAT_Msk    = 0x80       // Bit mask of DMAT field.
	LPUART_CR3_DMAT        = 0x80       // Bit DMAT.
	LPUART_CR3_DMAR_Pos    = 0x6        // Position of DMAR field.
	LPUART_CR3_DMAR_Msk    = 0x40       // Bit mask of DMAR field.
	LPUART_CR3_DMAR        = 0x40       // Bit DMAR.
	LPUART_CR3_HDSEL_Pos   = 0x3        // Position of HDSEL field.
	LPUART_CR3_HDSEL_Msk   = 0x8        // Bit mask of HDSEL field.
	LPUART_CR3_HDSEL       = 0x8        // Bit HDSEL.
	LPUART_CR3_EIE_Pos     = 0x0        // Position of EIE field.
	LPUART_CR3_EIE_Msk     = 0x1        // Bit mask of EIE field.
	LPUART_CR3_EIE         = 0x1        // Bit EIE.

	// BRR: Baud rate register
	LPUART_BRR_BRR_Pos = 0x0     // Position of BRR field.
	LPUART_BRR_BRR_Msk = 0xfffff // Bit mask of BRR field.

	// GTPR: Guard time and prescaler           register
	LPUART_GTPR_GT_Pos  = 0x8    // Position of GT field.
	LPUART_GTPR_GT_Msk  = 0xff00 // Bit mask of GT field.
	LPUART_GTPR_PSC_Pos = 0x0    // Position of PSC field.
	LPUART_GTPR_PSC_Msk = 0xff   // Bit mask of PSC field.

	// RTOR: Receiver timeout register
	LPUART_RTOR_BLEN_Pos = 0x18       // Position of BLEN field.
	LPUART_RTOR_BLEN_Msk = 0xff000000 // Bit mask of BLEN field.
	LPUART_RTOR_RTO_Pos  = 0x0        // Position of RTO field.
	LPUART_RTOR_RTO_Msk  = 0xffffff   // Bit mask of RTO field.

	// RQR: Request register
	LPUART_RQR_TXFRQ_Pos = 0x4  // Position of TXFRQ field.
	LPUART_RQR_TXFRQ_Msk = 0x10 // Bit mask of TXFRQ field.
	LPUART_RQR_TXFRQ     = 0x10 // Bit TXFRQ.
	LPUART_RQR_RXFRQ_Pos = 0x3  // Position of RXFRQ field.
	LPUART_RQR_RXFRQ_Msk = 0x8  // Bit mask of RXFRQ field.
	LPUART_RQR_RXFRQ     = 0x8  // Bit RXFRQ.
	LPUART_RQR_MMRQ_Pos  = 0x2  // Position of MMRQ field.
	LPUART_RQR_MMRQ_Msk  = 0x4  // Bit mask of MMRQ field.
	LPUART_RQR_MMRQ      = 0x4  // Bit MMRQ.
	LPUART_RQR_SBKRQ_Pos = 0x1  // Position of SBKRQ field.
	LPUART_RQR_SBKRQ_Msk = 0x2  // Bit mask of SBKRQ field.
	LPUART_RQR_SBKRQ     = 0x2  // Bit SBKRQ.
	LPUART_RQR_ABRRQ_Pos = 0x0  // Position of ABRRQ field.
	LPUART_RQR_ABRRQ_Msk = 0x1  // Bit mask of ABRRQ field.
	LPUART_RQR_ABRRQ     = 0x1  // Bit ABRRQ.

	// ISR: Interrupt & status           register
	LPUART_ISR_TXFT_Pos  = 0x1b      // Position of TXFT field.
	LPUART_ISR_TXFT_Msk  = 0x8000000 // Bit mask of TXFT field.
	LPUART_ISR_TXFT      = 0x8000000 // Bit TXFT.
	LPUART_ISR_RXFT_Pos  = 0x1a      // Position of RXFT field.
	LPUART_ISR_RXFT_Msk  = 0x4000000 // Bit mask of RXFT field.
	LPUART_ISR_RXFT      = 0x4000000 // Bit RXFT.
	LPUART_ISR_RXFF_Pos  = 0x18      // Position of RXFF field.
	LPUART_ISR_RXFF_Msk  = 0x1000000 // Bit mask of RXFF field.
	LPUART_ISR_RXFF      = 0x1000000 // Bit RXFF.
	LPUART_ISR_TXFE_Pos  = 0x17      // Position of TXFE field.
	LPUART_ISR_TXFE_Msk  = 0x800000  // Bit mask of TXFE field.
	LPUART_ISR_TXFE      = 0x800000  // Bit TXFE.
	LPUART_ISR_REACK_Pos = 0x16      // Position of REACK field.
	LPUART_ISR_REACK_Msk = 0x400000  // Bit mask of REACK field.
	LPUART_ISR_REACK     = 0x400000  // Bit REACK.
	LPUART_ISR_TEACK_Pos = 0x15      // Position of TEACK field.
	LPUART_ISR_TEACK_Msk = 0x200000  // Bit mask of TEACK field.
	LPUART_ISR_TEACK     = 0x200000  // Bit TEACK.
	LPUART_ISR_WUF_Pos   = 0x14      // Position of WUF field.
	LPUART_ISR_WUF_Msk   = 0x100000  // Bit mask of WUF field.
	LPUART_ISR_WUF       = 0x100000  // Bit WUF.
	LPUART_ISR_RWU_Pos   = 0x13      // Position of RWU field.
	LPUART_ISR_RWU_Msk   = 0x80000   // Bit mask of RWU field.
	LPUART_ISR_RWU       = 0x80000   // Bit RWU.
	LPUART_ISR_SBKF_Pos  = 0x12      // Position of SBKF field.
	LPUART_ISR_SBKF_Msk  = 0x40000   // Bit mask of SBKF field.
	LPUART_ISR_SBKF      = 0x40000   // Bit SBKF.
	LPUART_ISR_CMF_Pos   = 0x11      // Position of CMF field.
	LPUART_ISR_CMF_Msk   = 0x20000   // Bit mask of CMF field.
	LPUART_ISR_CMF       = 0x20000   // Bit CMF.
	LPUART_ISR_BUSY_Pos  = 0x10      // Position of BUSY field.
	LPUART_ISR_BUSY_Msk  = 0x10000   // Bit mask of BUSY field.
	LPUART_ISR_BUSY      = 0x10000   // Bit BUSY.
	LPUART_ISR_CTS_Pos   = 0xa       // Position of CTS field.
	LPUART_ISR_CTS_Msk   = 0x400     // Bit mask of CTS field.
	LPUART_ISR_CTS       = 0x400     // Bit CTS.
	LPUART_ISR_CTSIF_Pos = 0x9       // Position of CTSIF field.
	LPUART_ISR_CTSIF_Msk = 0x200     // Bit mask of CTSIF field.
	LPUART_ISR_CTSIF     = 0x200     // Bit CTSIF.
	LPUART_ISR_TXE_Pos   = 0x7       // Position of TXE field.
	LPUART_ISR_TXE_Msk   = 0x80      // Bit mask of TXE field.
	LPUART_ISR_TXE       = 0x80      // Bit TXE.
	LPUART_ISR_TC_Pos    = 0x6       // Position of TC field.
	LPUART_ISR_TC_Msk    = 0x40      // Bit mask of TC field.
	LPUART_ISR_TC        = 0x40      // Bit TC.
	LPUART_ISR_RXNE_Pos  = 0x5       // Position of RXNE field.
	LPUART_ISR_RXNE_Msk  = 0x20      // Bit mask of RXNE field.
	LPUART_ISR_RXNE      = 0x20      // Bit RXNE.
	LPUART_ISR_IDLE_Pos  = 0x4       // Position of IDLE field.
	LPUART_ISR_IDLE_Msk  = 0x10      // Bit mask of IDLE field.
	LPUART_ISR_IDLE      = 0x10      // Bit IDLE.
	LPUART_ISR_ORE_Pos   = 0x3       // Position of ORE field.
	LPUART_ISR_ORE_Msk   = 0x8       // Bit mask of ORE field.
	LPUART_ISR_ORE       = 0x8       // Bit ORE.
	LPUART_ISR_NE_Pos    = 0x2       // Position of NE field.
	LPUART_ISR_NE_Msk    = 0x4       // Bit mask of NE field.
	LPUART_ISR_NE        = 0x4       // Bit NE.
	LPUART_ISR_FE_Pos    = 0x1       // Position of FE field.
	LPUART_ISR_FE_Msk    = 0x2       // Bit mask of FE field.
	LPUART_ISR_FE        = 0x2       // Bit FE.
	LPUART_ISR_PE_Pos    = 0x0       // Position of PE field.
	LPUART_ISR_PE_Msk    = 0x1       // Bit mask of PE field.
	LPUART_ISR_PE        = 0x1       // Bit PE.

	// ICR: Interrupt flag clear register
	LPUART_ICR_WUCF_Pos   = 0x14     // Position of WUCF field.
	LPUART_ICR_WUCF_Msk   = 0x100000 // Bit mask of WUCF field.
	LPUART_ICR_WUCF       = 0x100000 // Bit WUCF.
	LPUART_ICR_CMCF_Pos   = 0x11     // Position of CMCF field.
	LPUART_ICR_CMCF_Msk   = 0x20000  // Bit mask of CMCF field.
	LPUART_ICR_CMCF       = 0x20000  // Bit CMCF.
	LPUART_ICR_CTSCF_Pos  = 0x9      // Position of CTSCF field.
	LPUART_ICR_CTSCF_Msk  = 0x200    // Bit mask of CTSCF field.
	LPUART_ICR_CTSCF      = 0x200    // Bit CTSCF.
	LPUART_ICR_TCCF_Pos   = 0x6      // Position of TCCF field.
	LPUART_ICR_TCCF_Msk   = 0x40     // Bit mask of TCCF field.
	LPUART_ICR_TCCF       = 0x40     // Bit TCCF.
	LPUART_ICR_IDLECF_Pos = 0x4      // Position of IDLECF field.
	LPUART_ICR_IDLECF_Msk = 0x10     // Bit mask of IDLECF field.
	LPUART_ICR_IDLECF     = 0x10     // Bit IDLECF.
	LPUART_ICR_ORECF_Pos  = 0x3      // Position of ORECF field.
	LPUART_ICR_ORECF_Msk  = 0x8      // Bit mask of ORECF field.
	LPUART_ICR_ORECF      = 0x8      // Bit ORECF.
	LPUART_ICR_NCF_Pos    = 0x2      // Position of NCF field.
	LPUART_ICR_NCF_Msk    = 0x4      // Bit mask of NCF field.
	LPUART_ICR_NCF        = 0x4      // Bit NCF.
	LPUART_ICR_FECF_Pos   = 0x1      // Position of FECF field.
	LPUART_ICR_FECF_Msk   = 0x2      // Bit mask of FECF field.
	LPUART_ICR_FECF       = 0x2      // Bit FECF.
	LPUART_ICR_PECF_Pos   = 0x0      // Position of PECF field.
	LPUART_ICR_PECF_Msk   = 0x1      // Bit mask of PECF field.
	LPUART_ICR_PECF       = 0x1      // Bit PECF.

	// RDR: Receive data register
	LPUART_RDR_RDR_Pos = 0x0   // Position of RDR field.
	LPUART_RDR_RDR_Msk = 0x1ff // Bit mask of RDR field.

	// TDR: Transmit data register
	LPUART_TDR_TDR_Pos = 0x0   // Position of TDR field.
	LPUART_TDR_TDR_Msk = 0x1ff // Bit mask of TDR field.

	// PRESC: Prescaler register
	LPUART_PRESC_PRESCALER_Pos = 0x0 // Position of PRESCALER field.
	LPUART_PRESC_PRESCALER_Msk = 0xf // Bit mask of PRESCALER field.
)

// Bitfields for SYSCFG: System configuration controller
const (
	// PMCR: peripheral mode configuration           register
	SYSCFG_PMCR_I2C1FMP_Pos     = 0x0       // Position of I2C1FMP field.
	SYSCFG_PMCR_I2C1FMP_Msk     = 0x1       // Bit mask of I2C1FMP field.
	SYSCFG_PMCR_I2C1FMP         = 0x1       // Bit I2C1FMP.
	SYSCFG_PMCR_I2C2FMP_Pos     = 0x1       // Position of I2C2FMP field.
	SYSCFG_PMCR_I2C2FMP_Msk     = 0x2       // Bit mask of I2C2FMP field.
	SYSCFG_PMCR_I2C2FMP         = 0x2       // Bit I2C2FMP.
	SYSCFG_PMCR_I2C3FMP_Pos     = 0x2       // Position of I2C3FMP field.
	SYSCFG_PMCR_I2C3FMP_Msk     = 0x4       // Bit mask of I2C3FMP field.
	SYSCFG_PMCR_I2C3FMP         = 0x4       // Bit I2C3FMP.
	SYSCFG_PMCR_I2C4FMP_Pos     = 0x3       // Position of I2C4FMP field.
	SYSCFG_PMCR_I2C4FMP_Msk     = 0x8       // Bit mask of I2C4FMP field.
	SYSCFG_PMCR_I2C4FMP         = 0x8       // Bit I2C4FMP.
	SYSCFG_PMCR_PB6FMP_Pos      = 0x4       // Position of PB6FMP field.
	SYSCFG_PMCR_PB6FMP_Msk      = 0x10      // Bit mask of PB6FMP field.
	SYSCFG_PMCR_PB6FMP          = 0x10      // Bit PB6FMP.
	SYSCFG_PMCR_PB7FMP_Pos      = 0x5       // Position of PB7FMP field.
	SYSCFG_PMCR_PB7FMP_Msk      = 0x20      // Bit mask of PB7FMP field.
	SYSCFG_PMCR_PB7FMP          = 0x20      // Bit PB7FMP.
	SYSCFG_PMCR_PB8FMP_Pos      = 0x6       // Position of PB8FMP field.
	SYSCFG_PMCR_PB8FMP_Msk      = 0x40      // Bit mask of PB8FMP field.
	SYSCFG_PMCR_PB8FMP          = 0x40      // Bit PB8FMP.
	SYSCFG_PMCR_PB9FMP_Pos      = 0x7       // Position of PB9FMP field.
	SYSCFG_PMCR_PB9FMP_Msk      = 0x80      // Bit mask of PB9FMP field.
	SYSCFG_PMCR_PB9FMP          = 0x80      // Bit PB9FMP.
	SYSCFG_PMCR_BOOSTE_Pos      = 0x8       // Position of BOOSTE field.
	SYSCFG_PMCR_BOOSTE_Msk      = 0x100     // Bit mask of BOOSTE field.
	SYSCFG_PMCR_BOOSTE          = 0x100     // Bit BOOSTE.
	SYSCFG_PMCR_BOOSTVDDSEL_Pos = 0x9       // Position of BOOSTVDDSEL field.
	SYSCFG_PMCR_BOOSTVDDSEL_Msk = 0x200     // Bit mask of BOOSTVDDSEL field.
	SYSCFG_PMCR_BOOSTVDDSEL     = 0x200     // Bit BOOSTVDDSEL.
	SYSCFG_PMCR_EPIS_Pos        = 0x15      // Position of EPIS field.
	SYSCFG_PMCR_EPIS_Msk        = 0xe00000  // Bit mask of EPIS field.
	SYSCFG_PMCR_PA0SO_Pos       = 0x18      // Position of PA0SO field.
	SYSCFG_PMCR_PA0SO_Msk       = 0x1000000 // Bit mask of PA0SO field.
	SYSCFG_PMCR_PA0SO           = 0x1000000 // Bit PA0SO.
	SYSCFG_PMCR_PA1SO_Pos       = 0x19      // Position of PA1SO field.
	SYSCFG_PMCR_PA1SO_Msk       = 0x2000000 // Bit mask of PA1SO field.
	SYSCFG_PMCR_PA1SO           = 0x2000000 // Bit PA1SO.
	SYSCFG_PMCR_PC2SO_Pos       = 0x1a      // Position of PC2SO field.
	SYSCFG_PMCR_PC2SO_Msk       = 0x4000000 // Bit mask of PC2SO field.
	SYSCFG_PMCR_PC2SO           = 0x4000000 // Bit PC2SO.
	SYSCFG_PMCR_PC3SO_Pos       = 0x1b      // Position of PC3SO field.
	SYSCFG_PMCR_PC3SO_Msk       = 0x8000000 // Bit mask of PC3SO field.
	SYSCFG_PMCR_PC3SO           = 0x8000000 // Bit PC3SO.

	// EXTICR1: external interrupt configuration register           1
	SYSCFG_EXTICR1_EXTI3_Pos = 0xc    // Position of EXTI3 field.
	SYSCFG_EXTICR1_EXTI3_Msk = 0xf000 // Bit mask of EXTI3 field.
	SYSCFG_EXTICR1_EXTI2_Pos = 0x8    // Position of EXTI2 field.
	SYSCFG_EXTICR1_EXTI2_Msk = 0xf00  // Bit mask of EXTI2 field.
	SYSCFG_EXTICR1_EXTI1_Pos = 0x4    // Position of EXTI1 field.
	SYSCFG_EXTICR1_EXTI1_Msk = 0xf0   // Bit mask of EXTI1 field.
	SYSCFG_EXTICR1_EXTI0_Pos = 0x0    // Position of EXTI0 field.
	SYSCFG_EXTICR1_EXTI0_Msk = 0xf    // Bit mask of EXTI0 field.

	// EXTICR2: external interrupt configuration register           2
	SYSCFG_EXTICR2_EXTI7_Pos = 0xc    // Position of EXTI7 field.
	SYSCFG_EXTICR2_EXTI7_Msk = 0xf000 // Bit mask of EXTI7 field.
	SYSCFG_EXTICR2_EXTI6_Pos = 0x8    // Position of EXTI6 field.
	SYSCFG_EXTICR2_EXTI6_Msk = 0xf00  // Bit mask of EXTI6 field.
	SYSCFG_EXTICR2_EXTI5_Pos = 0x4    // Position of EXTI5 field.
	SYSCFG_EXTICR2_EXTI5_Msk = 0xf0   // Bit mask of EXTI5 field.
	SYSCFG_EXTICR2_EXTI4_Pos = 0x0    // Position of EXTI4 field.
	SYSCFG_EXTICR2_EXTI4_Msk = 0xf    // Bit mask of EXTI4 field.

	// EXTICR3: external interrupt configuration register           3
	SYSCFG_EXTICR3_EXTI11_Pos = 0xc    // Position of EXTI11 field.
	SYSCFG_EXTICR3_EXTI11_Msk = 0xf000 // Bit mask of EXTI11 field.
	SYSCFG_EXTICR3_EXTI10_Pos = 0x8    // Position of EXTI10 field.
	SYSCFG_EXTICR3_EXTI10_Msk = 0xf00  // Bit mask of EXTI10 field.
	SYSCFG_EXTICR3_EXTI9_Pos  = 0x4    // Position of EXTI9 field.
	SYSCFG_EXTICR3_EXTI9_Msk  = 0xf0   // Bit mask of EXTI9 field.
	SYSCFG_EXTICR3_EXTI8_Pos  = 0x0    // Position of EXTI8 field.
	SYSCFG_EXTICR3_EXTI8_Msk  = 0xf    // Bit mask of EXTI8 field.

	// EXTICR4: external interrupt configuration register           4
	SYSCFG_EXTICR4_EXTI15_Pos = 0xc    // Position of EXTI15 field.
	SYSCFG_EXTICR4_EXTI15_Msk = 0xf000 // Bit mask of EXTI15 field.
	SYSCFG_EXTICR4_EXTI14_Pos = 0x8    // Position of EXTI14 field.
	SYSCFG_EXTICR4_EXTI14_Msk = 0xf00  // Bit mask of EXTI14 field.
	SYSCFG_EXTICR4_EXTI13_Pos = 0x4    // Position of EXTI13 field.
	SYSCFG_EXTICR4_EXTI13_Msk = 0xf0   // Bit mask of EXTI13 field.
	SYSCFG_EXTICR4_EXTI12_Pos = 0x0    // Position of EXTI12 field.
	SYSCFG_EXTICR4_EXTI12_Msk = 0xf    // Bit mask of EXTI12 field.

	// CCCSR: compensation cell control/status           register
	SYSCFG_CCCSR_EN_Pos    = 0x0     // Position of EN field.
	SYSCFG_CCCSR_EN_Msk    = 0x1     // Bit mask of EN field.
	SYSCFG_CCCSR_EN        = 0x1     // Bit EN.
	SYSCFG_CCCSR_CS_Pos    = 0x1     // Position of CS field.
	SYSCFG_CCCSR_CS_Msk    = 0x2     // Bit mask of CS field.
	SYSCFG_CCCSR_CS        = 0x2     // Bit CS.
	SYSCFG_CCCSR_READY_Pos = 0x8     // Position of READY field.
	SYSCFG_CCCSR_READY_Msk = 0x100   // Bit mask of READY field.
	SYSCFG_CCCSR_READY     = 0x100   // Bit READY.
	SYSCFG_CCCSR_HSLV_Pos  = 0x10    // Position of HSLV field.
	SYSCFG_CCCSR_HSLV_Msk  = 0x10000 // Bit mask of HSLV field.
	SYSCFG_CCCSR_HSLV      = 0x10000 // Bit HSLV.

	// CCVR: SYSCFG compensation cell value           register
	SYSCFG_CCVR_NCV_Pos = 0x0  // Position of NCV field.
	SYSCFG_CCVR_NCV_Msk = 0xf  // Bit mask of NCV field.
	SYSCFG_CCVR_PCV_Pos = 0x4  // Position of PCV field.
	SYSCFG_CCVR_PCV_Msk = 0xf0 // Bit mask of PCV field.

	// CCCR: SYSCFG compensation cell code           register
	SYSCFG_CCCR_NCC_Pos = 0x0  // Position of NCC field.
	SYSCFG_CCCR_NCC_Msk = 0xf  // Bit mask of NCC field.
	SYSCFG_CCCR_PCC_Pos = 0x4  // Position of PCC field.
	SYSCFG_CCCR_PCC_Msk = 0xf0 // Bit mask of PCC field.

	// PWRCR: SYSCFG power control register
	SYSCFG_PWRCR_ODEN_Pos = 0x0 // Position of ODEN field.
	SYSCFG_PWRCR_ODEN_Msk = 0xf // Bit mask of ODEN field.

	// PKGR: SYSCFG package register
	SYSCFG_PKGR_PKG_Pos = 0x0 // Position of PKG field.
	SYSCFG_PKGR_PKG_Msk = 0xf // Bit mask of PKG field.

	// UR0: SYSCFG user register 0
	SYSCFG_UR0_BKS_Pos = 0x0      // Position of BKS field.
	SYSCFG_UR0_BKS_Msk = 0x1      // Bit mask of BKS field.
	SYSCFG_UR0_BKS     = 0x1      // Bit BKS.
	SYSCFG_UR0_RDP_Pos = 0x10     // Position of RDP field.
	SYSCFG_UR0_RDP_Msk = 0xff0000 // Bit mask of RDP field.

	// UR2: SYSCFG user register 2
	SYSCFG_UR2_BORH_Pos      = 0x0        // Position of BORH field.
	SYSCFG_UR2_BORH_Msk      = 0x3        // Bit mask of BORH field.
	SYSCFG_UR2_BOOT_ADD0_Pos = 0x10       // Position of BOOT_ADD0 field.
	SYSCFG_UR2_BOOT_ADD0_Msk = 0xffff0000 // Bit mask of BOOT_ADD0 field.

	// UR3: SYSCFG user register 3
	SYSCFG_UR3_BOOT_ADD1_Pos = 0x10       // Position of BOOT_ADD1 field.
	SYSCFG_UR3_BOOT_ADD1_Msk = 0xffff0000 // Bit mask of BOOT_ADD1 field.

	// UR4: SYSCFG user register 4
	SYSCFG_UR4_MEPAD_1_Pos = 0x10    // Position of MEPAD_1 field.
	SYSCFG_UR4_MEPAD_1_Msk = 0x10000 // Bit mask of MEPAD_1 field.
	SYSCFG_UR4_MEPAD_1     = 0x10000 // Bit MEPAD_1.

	// UR5: SYSCFG user register 5
	SYSCFG_UR5_MESAD_1_Pos = 0x0      // Position of MESAD_1 field.
	SYSCFG_UR5_MESAD_1_Msk = 0x1      // Bit mask of MESAD_1 field.
	SYSCFG_UR5_MESAD_1     = 0x1      // Bit MESAD_1.
	SYSCFG_UR5_WRPN_1_Pos  = 0x10     // Position of WRPN_1 field.
	SYSCFG_UR5_WRPN_1_Msk  = 0xff0000 // Bit mask of WRPN_1 field.

	// UR6: SYSCFG user register 6
	SYSCFG_UR6_PA_BEG_1_Pos = 0x0       // Position of PA_BEG_1 field.
	SYSCFG_UR6_PA_BEG_1_Msk = 0xfff     // Bit mask of PA_BEG_1 field.
	SYSCFG_UR6_PA_END_1_Pos = 0x10      // Position of PA_END_1 field.
	SYSCFG_UR6_PA_END_1_Msk = 0xfff0000 // Bit mask of PA_END_1 field.

	// UR7: SYSCFG user register 7
	SYSCFG_UR7_SA_BEG_1_Pos = 0x0       // Position of SA_BEG_1 field.
	SYSCFG_UR7_SA_BEG_1_Msk = 0xfff     // Bit mask of SA_BEG_1 field.
	SYSCFG_UR7_SA_END_1_Pos = 0x10      // Position of SA_END_1 field.
	SYSCFG_UR7_SA_END_1_Msk = 0xfff0000 // Bit mask of SA_END_1 field.

	// UR8: SYSCFG user register 8
	SYSCFG_UR8_MEPAD_2_Pos = 0x0     // Position of MEPAD_2 field.
	SYSCFG_UR8_MEPAD_2_Msk = 0x1     // Bit mask of MEPAD_2 field.
	SYSCFG_UR8_MEPAD_2     = 0x1     // Bit MEPAD_2.
	SYSCFG_UR8_MESAD_2_Pos = 0x10    // Position of MESAD_2 field.
	SYSCFG_UR8_MESAD_2_Msk = 0x10000 // Bit mask of MESAD_2 field.
	SYSCFG_UR8_MESAD_2     = 0x10000 // Bit MESAD_2.

	// UR9: SYSCFG user register 9
	SYSCFG_UR9_WRPN_2_Pos   = 0x0       // Position of WRPN_2 field.
	SYSCFG_UR9_WRPN_2_Msk   = 0xff      // Bit mask of WRPN_2 field.
	SYSCFG_UR9_PA_BEG_2_Pos = 0x10      // Position of PA_BEG_2 field.
	SYSCFG_UR9_PA_BEG_2_Msk = 0xfff0000 // Bit mask of PA_BEG_2 field.

	// UR10: SYSCFG user register 10
	SYSCFG_UR10_PA_END_2_Pos = 0x0       // Position of PA_END_2 field.
	SYSCFG_UR10_PA_END_2_Msk = 0xfff     // Bit mask of PA_END_2 field.
	SYSCFG_UR10_SA_BEG_2_Pos = 0x10      // Position of SA_BEG_2 field.
	SYSCFG_UR10_SA_BEG_2_Msk = 0xfff0000 // Bit mask of SA_BEG_2 field.

	// UR11: SYSCFG user register 11
	SYSCFG_UR11_SA_END_2_Pos = 0x0     // Position of SA_END_2 field.
	SYSCFG_UR11_SA_END_2_Msk = 0xfff   // Bit mask of SA_END_2 field.
	SYSCFG_UR11_IWDG1M_Pos   = 0x10    // Position of IWDG1M field.
	SYSCFG_UR11_IWDG1M_Msk   = 0x10000 // Bit mask of IWDG1M field.
	SYSCFG_UR11_IWDG1M       = 0x10000 // Bit IWDG1M.

	// UR12: SYSCFG user register 12
	SYSCFG_UR12_SECURE_Pos = 0x10    // Position of SECURE field.
	SYSCFG_UR12_SECURE_Msk = 0x10000 // Bit mask of SECURE field.
	SYSCFG_UR12_SECURE     = 0x10000 // Bit SECURE.

	// UR13: SYSCFG user register 13
	SYSCFG_UR13_SDRS_Pos    = 0x0     // Position of SDRS field.
	SYSCFG_UR13_SDRS_Msk    = 0x3     // Bit mask of SDRS field.
	SYSCFG_UR13_D1SBRST_Pos = 0x10    // Position of D1SBRST field.
	SYSCFG_UR13_D1SBRST_Msk = 0x10000 // Bit mask of D1SBRST field.
	SYSCFG_UR13_D1SBRST     = 0x10000 // Bit D1SBRST.

	// UR14: SYSCFG user register 14
	SYSCFG_UR14_D1STPRST_Pos = 0x0 // Position of D1STPRST field.
	SYSCFG_UR14_D1STPRST_Msk = 0x1 // Bit mask of D1STPRST field.
	SYSCFG_UR14_D1STPRST     = 0x1 // Bit D1STPRST.

	// UR15: SYSCFG user register 15
	SYSCFG_UR15_FZIWDGSTB_Pos = 0x10    // Position of FZIWDGSTB field.
	SYSCFG_UR15_FZIWDGSTB_Msk = 0x10000 // Bit mask of FZIWDGSTB field.
	SYSCFG_UR15_FZIWDGSTB     = 0x10000 // Bit FZIWDGSTB.

	// UR16: SYSCFG user register 16
	SYSCFG_UR16_FZIWDGSTP_Pos = 0x0     // Position of FZIWDGSTP field.
	SYSCFG_UR16_FZIWDGSTP_Msk = 0x1     // Bit mask of FZIWDGSTP field.
	SYSCFG_UR16_FZIWDGSTP     = 0x1     // Bit FZIWDGSTP.
	SYSCFG_UR16_PKP_Pos       = 0x10    // Position of PKP field.
	SYSCFG_UR16_PKP_Msk       = 0x10000 // Bit mask of PKP field.
	SYSCFG_UR16_PKP           = 0x10000 // Bit PKP.

	// UR17: SYSCFG user register 17
	SYSCFG_UR17_IO_HSLV_Pos = 0x0 // Position of IO_HSLV field.
	SYSCFG_UR17_IO_HSLV_Msk = 0x1 // Bit mask of IO_HSLV field.
	SYSCFG_UR17_IO_HSLV     = 0x1 // Bit IO_HSLV.
)

// Bitfields for EXTI: External interrupt/event controller
const (
	// RTSR1: EXTI rising trigger selection           register
	EXTI_RTSR1_TR0_Pos  = 0x0      // Position of TR0 field.
	EXTI_RTSR1_TR0_Msk  = 0x1      // Bit mask of TR0 field.
	EXTI_RTSR1_TR0      = 0x1      // Bit TR0.
	EXTI_RTSR1_TR1_Pos  = 0x1      // Position of TR1 field.
	EXTI_RTSR1_TR1_Msk  = 0x2      // Bit mask of TR1 field.
	EXTI_RTSR1_TR1      = 0x2      // Bit TR1.
	EXTI_RTSR1_TR2_Pos  = 0x2      // Position of TR2 field.
	EXTI_RTSR1_TR2_Msk  = 0x4      // Bit mask of TR2 field.
	EXTI_RTSR1_TR2      = 0x4      // Bit TR2.
	EXTI_RTSR1_TR3_Pos  = 0x3      // Position of TR3 field.
	EXTI_RTSR1_TR3_Msk  = 0x8      // Bit mask of TR3 field.
	EXTI_RTSR1_TR3      = 0x8      // Bit TR3.
	EXTI_RTSR1_TR4_Pos  = 0x4      // Position of TR4 field.
	EXTI_RTSR1_TR4_Msk  = 0x10     // Bit mask of TR4 field.
	EXTI_RTSR1_TR4      = 0x10     // Bit TR4.
	EXTI_RTSR1_TR5_Pos  = 0x5      // Position of TR5 field.
	EXTI_RTSR1_TR5_Msk  = 0x20     // Bit mask of TR5 field.
	EXTI_RTSR1_TR5      = 0x20     // Bit TR5.
	EXTI_RTSR1_TR6_Pos  = 0x6      // Position of TR6 field.
	EXTI_RTSR1_TR6_Msk  = 0x40     // Bit mask of TR6 field.
	EXTI_RTSR1_TR6      = 0x40     // Bit TR6.
	EXTI_RTSR1_TR7_Pos  = 0x7      // Position of TR7 field.
	EXTI_RTSR1_TR7_Msk  = 0x80     // Bit mask of TR7 field.
	EXTI_RTSR1_TR7      = 0x80     // Bit TR7.
	EXTI_RTSR1_TR8_Pos  = 0x8      // Position of TR8 field.
	EXTI_RTSR1_TR8_Msk  = 0x100    // Bit mask of TR8 field.
	EXTI_RTSR1_TR8      = 0x100    // Bit TR8.
	EXTI_RTSR1_TR9_Pos  = 0x9      // Position of TR9 field.
	EXTI_RTSR1_TR9_Msk  = 0x200    // Bit mask of TR9 field.
	EXTI_RTSR1_TR9      = 0x200    // Bit TR9.
	EXTI_RTSR1_TR10_Pos = 0xa      // Position of TR10 field.
	EXTI_RTSR1_TR10_Msk = 0x400    // Bit mask of TR10 field.
	EXTI_RTSR1_TR10     = 0x400    // Bit TR10.
	EXTI_RTSR1_TR11_Pos = 0xb      // Position of TR11 field.
	EXTI_RTSR1_TR11_Msk = 0x800    // Bit mask of TR11 field.
	EXTI_RTSR1_TR11     = 0x800    // Bit TR11.
	EXTI_RTSR1_TR12_Pos = 0xc      // Position of TR12 field.
	EXTI_RTSR1_TR12_Msk = 0x1000   // Bit mask of TR12 field.
	EXTI_RTSR1_TR12     = 0x1000   // Bit TR12.
	EXTI_RTSR1_TR13_Pos = 0xd      // Position of TR13 field.
	EXTI_RTSR1_TR13_Msk = 0x2000   // Bit mask of TR13 field.
	EXTI_RTSR1_TR13     = 0x2000   // Bit TR13.
	EXTI_RTSR1_TR14_Pos = 0xe      // Position of TR14 field.
	EXTI_RTSR1_TR14_Msk = 0x4000   // Bit mask of TR14 field.
	EXTI_RTSR1_TR14     = 0x4000   // Bit TR14.
	EXTI_RTSR1_TR15_Pos = 0xf      // Position of TR15 field.
	EXTI_RTSR1_TR15_Msk = 0x8000   // Bit mask of TR15 field.
	EXTI_RTSR1_TR15     = 0x8000   // Bit TR15.
	EXTI_RTSR1_TR16_Pos = 0x10     // Position of TR16 field.
	EXTI_RTSR1_TR16_Msk = 0x10000  // Bit mask of TR16 field.
	EXTI_RTSR1_TR16     = 0x10000  // Bit TR16.
	EXTI_RTSR1_TR17_Pos = 0x11     // Position of TR17 field.
	EXTI_RTSR1_TR17_Msk = 0x20000  // Bit mask of TR17 field.
	EXTI_RTSR1_TR17     = 0x20000  // Bit TR17.
	EXTI_RTSR1_TR18_Pos = 0x12     // Position of TR18 field.
	EXTI_RTSR1_TR18_Msk = 0x40000  // Bit mask of TR18 field.
	EXTI_RTSR1_TR18     = 0x40000  // Bit TR18.
	EXTI_RTSR1_TR19_Pos = 0x13     // Position of TR19 field.
	EXTI_RTSR1_TR19_Msk = 0x80000  // Bit mask of TR19 field.
	EXTI_RTSR1_TR19     = 0x80000  // Bit TR19.
	EXTI_RTSR1_TR20_Pos = 0x14     // Position of TR20 field.
	EXTI_RTSR1_TR20_Msk = 0x100000 // Bit mask of TR20 field.
	EXTI_RTSR1_TR20     = 0x100000 // Bit TR20.
	EXTI_RTSR1_TR21_Pos = 0x15     // Position of TR21 field.
	EXTI_RTSR1_TR21_Msk = 0x200000 // Bit mask of TR21 field.
	EXTI_RTSR1_TR21     = 0x200000 // Bit TR21.

	// FTSR1: EXTI falling trigger selection           register
	EXTI_FTSR1_TR0_Pos  = 0x0      // Position of TR0 field.
	EXTI_FTSR1_TR0_Msk  = 0x1      // Bit mask of TR0 field.
	EXTI_FTSR1_TR0      = 0x1      // Bit TR0.
	EXTI_FTSR1_TR1_Pos  = 0x1      // Position of TR1 field.
	EXTI_FTSR1_TR1_Msk  = 0x2      // Bit mask of TR1 field.
	EXTI_FTSR1_TR1      = 0x2      // Bit TR1.
	EXTI_FTSR1_TR2_Pos  = 0x2      // Position of TR2 field.
	EXTI_FTSR1_TR2_Msk  = 0x4      // Bit mask of TR2 field.
	EXTI_FTSR1_TR2      = 0x4      // Bit TR2.
	EXTI_FTSR1_TR3_Pos  = 0x3      // Position of TR3 field.
	EXTI_FTSR1_TR3_Msk  = 0x8      // Bit mask of TR3 field.
	EXTI_FTSR1_TR3      = 0x8      // Bit TR3.
	EXTI_FTSR1_TR4_Pos  = 0x4      // Position of TR4 field.
	EXTI_FTSR1_TR4_Msk  = 0x10     // Bit mask of TR4 field.
	EXTI_FTSR1_TR4      = 0x10     // Bit TR4.
	EXTI_FTSR1_TR5_Pos  = 0x5      // Position of TR5 field.
	EXTI_FTSR1_TR5_Msk  = 0x20     // Bit mask of TR5 field.
	EXTI_FTSR1_TR5      = 0x20     // Bit TR5.
	EXTI_FTSR1_TR6_Pos  = 0x6      // Position of TR6 field.
	EXTI_FTSR1_TR6_Msk  = 0x40     // Bit mask of TR6 field.
	EXTI_FTSR1_TR6      = 0x40     // Bit TR6.
	EXTI_FTSR1_TR7_Pos  = 0x7      // Position of TR7 field.
	EXTI_FTSR1_TR7_Msk  = 0x80     // Bit mask of TR7 field.
	EXTI_FTSR1_TR7      = 0x80     // Bit TR7.
	EXTI_FTSR1_TR8_Pos  = 0x8      // Position of TR8 field.
	EXTI_FTSR1_TR8_Msk  = 0x100    // Bit mask of TR8 field.
	EXTI_FTSR1_TR8      = 0x100    // Bit TR8.
	EXTI_FTSR1_TR9_Pos  = 0x9      // Position of TR9 field.
	EXTI_FTSR1_TR9_Msk  = 0x200    // Bit mask of TR9 field.
	EXTI_FTSR1_TR9      = 0x200    // Bit TR9.
	EXTI_FTSR1_TR10_Pos = 0xa      // Position of TR10 field.
	EXTI_FTSR1_TR10_Msk = 0x400    // Bit mask of TR10 field.
	EXTI_FTSR1_TR10     = 0x400    // Bit TR10.
	EXTI_FTSR1_TR11_Pos = 0xb      // Position of TR11 field.
	EXTI_FTSR1_TR11_Msk = 0x800    // Bit mask of TR11 field.
	EXTI_FTSR1_TR11     = 0x800    // Bit TR11.
	EXTI_FTSR1_TR12_Pos = 0xc      // Position of TR12 field.
	EXTI_FTSR1_TR12_Msk = 0x1000   // Bit mask of TR12 field.
	EXTI_FTSR1_TR12     = 0x1000   // Bit TR12.
	EXTI_FTSR1_TR13_Pos = 0xd      // Position of TR13 field.
	EXTI_FTSR1_TR13_Msk = 0x2000   // Bit mask of TR13 field.
	EXTI_FTSR1_TR13     = 0x2000   // Bit TR13.
	EXTI_FTSR1_TR14_Pos = 0xe      // Position of TR14 field.
	EXTI_FTSR1_TR14_Msk = 0x4000   // Bit mask of TR14 field.
	EXTI_FTSR1_TR14     = 0x4000   // Bit TR14.
	EXTI_FTSR1_TR15_Pos = 0xf      // Position of TR15 field.
	EXTI_FTSR1_TR15_Msk = 0x8000   // Bit mask of TR15 field.
	EXTI_FTSR1_TR15     = 0x8000   // Bit TR15.
	EXTI_FTSR1_TR16_Pos = 0x10     // Position of TR16 field.
	EXTI_FTSR1_TR16_Msk = 0x10000  // Bit mask of TR16 field.
	EXTI_FTSR1_TR16     = 0x10000  // Bit TR16.
	EXTI_FTSR1_TR17_Pos = 0x11     // Position of TR17 field.
	EXTI_FTSR1_TR17_Msk = 0x20000  // Bit mask of TR17 field.
	EXTI_FTSR1_TR17     = 0x20000  // Bit TR17.
	EXTI_FTSR1_TR18_Pos = 0x12     // Position of TR18 field.
	EXTI_FTSR1_TR18_Msk = 0x40000  // Bit mask of TR18 field.
	EXTI_FTSR1_TR18     = 0x40000  // Bit TR18.
	EXTI_FTSR1_TR19_Pos = 0x13     // Position of TR19 field.
	EXTI_FTSR1_TR19_Msk = 0x80000  // Bit mask of TR19 field.
	EXTI_FTSR1_TR19     = 0x80000  // Bit TR19.
	EXTI_FTSR1_TR20_Pos = 0x14     // Position of TR20 field.
	EXTI_FTSR1_TR20_Msk = 0x100000 // Bit mask of TR20 field.
	EXTI_FTSR1_TR20     = 0x100000 // Bit TR20.
	EXTI_FTSR1_TR21_Pos = 0x15     // Position of TR21 field.
	EXTI_FTSR1_TR21_Msk = 0x200000 // Bit mask of TR21 field.
	EXTI_FTSR1_TR21     = 0x200000 // Bit TR21.

	// SWIER1: EXTI software interrupt event           register
	EXTI_SWIER1_SWIER0_Pos  = 0x0      // Position of SWIER0 field.
	EXTI_SWIER1_SWIER0_Msk  = 0x1      // Bit mask of SWIER0 field.
	EXTI_SWIER1_SWIER0      = 0x1      // Bit SWIER0.
	EXTI_SWIER1_SWIER1_Pos  = 0x1      // Position of SWIER1 field.
	EXTI_SWIER1_SWIER1_Msk  = 0x2      // Bit mask of SWIER1 field.
	EXTI_SWIER1_SWIER1      = 0x2      // Bit SWIER1.
	EXTI_SWIER1_SWIER2_Pos  = 0x2      // Position of SWIER2 field.
	EXTI_SWIER1_SWIER2_Msk  = 0x4      // Bit mask of SWIER2 field.
	EXTI_SWIER1_SWIER2      = 0x4      // Bit SWIER2.
	EXTI_SWIER1_SWIER3_Pos  = 0x3      // Position of SWIER3 field.
	EXTI_SWIER1_SWIER3_Msk  = 0x8      // Bit mask of SWIER3 field.
	EXTI_SWIER1_SWIER3      = 0x8      // Bit SWIER3.
	EXTI_SWIER1_SWIER4_Pos  = 0x4      // Position of SWIER4 field.
	EXTI_SWIER1_SWIER4_Msk  = 0x10     // Bit mask of SWIER4 field.
	EXTI_SWIER1_SWIER4      = 0x10     // Bit SWIER4.
	EXTI_SWIER1_SWIER5_Pos  = 0x5      // Position of SWIER5 field.
	EXTI_SWIER1_SWIER5_Msk  = 0x20     // Bit mask of SWIER5 field.
	EXTI_SWIER1_SWIER5      = 0x20     // Bit SWIER5.
	EXTI_SWIER1_SWIER6_Pos  = 0x6      // Position of SWIER6 field.
	EXTI_SWIER1_SWIER6_Msk  = 0x40     // Bit mask of SWIER6 field.
	EXTI_SWIER1_SWIER6      = 0x40     // Bit SWIER6.
	EXTI_SWIER1_SWIER7_Pos  = 0x7      // Position of SWIER7 field.
	EXTI_SWIER1_SWIER7_Msk  = 0x80     // Bit mask of SWIER7 field.
	EXTI_SWIER1_SWIER7      = 0x80     // Bit SWIER7.
	EXTI_SWIER1_SWIER8_Pos  = 0x8      // Position of SWIER8 field.
	EXTI_SWIER1_SWIER8_Msk  = 0x100    // Bit mask of SWIER8 field.
	EXTI_SWIER1_SWIER8      = 0x100    // Bit SWIER8.
	EXTI_SWIER1_SWIER9_Pos  = 0x9      // Position of SWIER9 field.
	EXTI_SWIER1_SWIER9_Msk  = 0x200    // Bit mask of SWIER9 field.
	EXTI_SWIER1_SWIER9      = 0x200    // Bit SWIER9.
	EXTI_SWIER1_SWIER10_Pos = 0xa      // Position of SWIER10 field.
	EXTI_SWIER1_SWIER10_Msk = 0x400    // Bit mask of SWIER10 field.
	EXTI_SWIER1_SWIER10     = 0x400    // Bit SWIER10.
	EXTI_SWIER1_SWIER11_Pos = 0xb      // Position of SWIER11 field.
	EXTI_SWIER1_SWIER11_Msk = 0x800    // Bit mask of SWIER11 field.
	EXTI_SWIER1_SWIER11     = 0x800    // Bit SWIER11.
	EXTI_SWIER1_SWIER12_Pos = 0xc      // Position of SWIER12 field.
	EXTI_SWIER1_SWIER12_Msk = 0x1000   // Bit mask of SWIER12 field.
	EXTI_SWIER1_SWIER12     = 0x1000   // Bit SWIER12.
	EXTI_SWIER1_SWIER13_Pos = 0xd      // Position of SWIER13 field.
	EXTI_SWIER1_SWIER13_Msk = 0x2000   // Bit mask of SWIER13 field.
	EXTI_SWIER1_SWIER13     = 0x2000   // Bit SWIER13.
	EXTI_SWIER1_SWIER14_Pos = 0xe      // Position of SWIER14 field.
	EXTI_SWIER1_SWIER14_Msk = 0x4000   // Bit mask of SWIER14 field.
	EXTI_SWIER1_SWIER14     = 0x4000   // Bit SWIER14.
	EXTI_SWIER1_SWIER15_Pos = 0xf      // Position of SWIER15 field.
	EXTI_SWIER1_SWIER15_Msk = 0x8000   // Bit mask of SWIER15 field.
	EXTI_SWIER1_SWIER15     = 0x8000   // Bit SWIER15.
	EXTI_SWIER1_SWIER16_Pos = 0x10     // Position of SWIER16 field.
	EXTI_SWIER1_SWIER16_Msk = 0x10000  // Bit mask of SWIER16 field.
	EXTI_SWIER1_SWIER16     = 0x10000  // Bit SWIER16.
	EXTI_SWIER1_SWIER17_Pos = 0x11     // Position of SWIER17 field.
	EXTI_SWIER1_SWIER17_Msk = 0x20000  // Bit mask of SWIER17 field.
	EXTI_SWIER1_SWIER17     = 0x20000  // Bit SWIER17.
	EXTI_SWIER1_SWIER18_Pos = 0x12     // Position of SWIER18 field.
	EXTI_SWIER1_SWIER18_Msk = 0x40000  // Bit mask of SWIER18 field.
	EXTI_SWIER1_SWIER18     = 0x40000  // Bit SWIER18.
	EXTI_SWIER1_SWIER19_Pos = 0x13     // Position of SWIER19 field.
	EXTI_SWIER1_SWIER19_Msk = 0x80000  // Bit mask of SWIER19 field.
	EXTI_SWIER1_SWIER19     = 0x80000  // Bit SWIER19.
	EXTI_SWIER1_SWIER20_Pos = 0x14     // Position of SWIER20 field.
	EXTI_SWIER1_SWIER20_Msk = 0x100000 // Bit mask of SWIER20 field.
	EXTI_SWIER1_SWIER20     = 0x100000 // Bit SWIER20.
	EXTI_SWIER1_SWIER21_Pos = 0x15     // Position of SWIER21 field.
	EXTI_SWIER1_SWIER21_Msk = 0x200000 // Bit mask of SWIER21 field.
	EXTI_SWIER1_SWIER21     = 0x200000 // Bit SWIER21.

	// D3PMR1: EXTI D3 pending mask register
	EXTI_D3PMR1_MR0_Pos  = 0x0       // Position of MR0 field.
	EXTI_D3PMR1_MR0_Msk  = 0x1       // Bit mask of MR0 field.
	EXTI_D3PMR1_MR0      = 0x1       // Bit MR0.
	EXTI_D3PMR1_MR1_Pos  = 0x1       // Position of MR1 field.
	EXTI_D3PMR1_MR1_Msk  = 0x2       // Bit mask of MR1 field.
	EXTI_D3PMR1_MR1      = 0x2       // Bit MR1.
	EXTI_D3PMR1_MR2_Pos  = 0x2       // Position of MR2 field.
	EXTI_D3PMR1_MR2_Msk  = 0x4       // Bit mask of MR2 field.
	EXTI_D3PMR1_MR2      = 0x4       // Bit MR2.
	EXTI_D3PMR1_MR3_Pos  = 0x3       // Position of MR3 field.
	EXTI_D3PMR1_MR3_Msk  = 0x8       // Bit mask of MR3 field.
	EXTI_D3PMR1_MR3      = 0x8       // Bit MR3.
	EXTI_D3PMR1_MR4_Pos  = 0x4       // Position of MR4 field.
	EXTI_D3PMR1_MR4_Msk  = 0x10      // Bit mask of MR4 field.
	EXTI_D3PMR1_MR4      = 0x10      // Bit MR4.
	EXTI_D3PMR1_MR5_Pos  = 0x5       // Position of MR5 field.
	EXTI_D3PMR1_MR5_Msk  = 0x20      // Bit mask of MR5 field.
	EXTI_D3PMR1_MR5      = 0x20      // Bit MR5.
	EXTI_D3PMR1_MR6_Pos  = 0x6       // Position of MR6 field.
	EXTI_D3PMR1_MR6_Msk  = 0x40      // Bit mask of MR6 field.
	EXTI_D3PMR1_MR6      = 0x40      // Bit MR6.
	EXTI_D3PMR1_MR7_Pos  = 0x7       // Position of MR7 field.
	EXTI_D3PMR1_MR7_Msk  = 0x80      // Bit mask of MR7 field.
	EXTI_D3PMR1_MR7      = 0x80      // Bit MR7.
	EXTI_D3PMR1_MR8_Pos  = 0x8       // Position of MR8 field.
	EXTI_D3PMR1_MR8_Msk  = 0x100     // Bit mask of MR8 field.
	EXTI_D3PMR1_MR8      = 0x100     // Bit MR8.
	EXTI_D3PMR1_MR9_Pos  = 0x9       // Position of MR9 field.
	EXTI_D3PMR1_MR9_Msk  = 0x200     // Bit mask of MR9 field.
	EXTI_D3PMR1_MR9      = 0x200     // Bit MR9.
	EXTI_D3PMR1_MR10_Pos = 0xa       // Position of MR10 field.
	EXTI_D3PMR1_MR10_Msk = 0x400     // Bit mask of MR10 field.
	EXTI_D3PMR1_MR10     = 0x400     // Bit MR10.
	EXTI_D3PMR1_MR11_Pos = 0xb       // Position of MR11 field.
	EXTI_D3PMR1_MR11_Msk = 0x800     // Bit mask of MR11 field.
	EXTI_D3PMR1_MR11     = 0x800     // Bit MR11.
	EXTI_D3PMR1_MR12_Pos = 0xc       // Position of MR12 field.
	EXTI_D3PMR1_MR12_Msk = 0x1000    // Bit mask of MR12 field.
	EXTI_D3PMR1_MR12     = 0x1000    // Bit MR12.
	EXTI_D3PMR1_MR13_Pos = 0xd       // Position of MR13 field.
	EXTI_D3PMR1_MR13_Msk = 0x2000    // Bit mask of MR13 field.
	EXTI_D3PMR1_MR13     = 0x2000    // Bit MR13.
	EXTI_D3PMR1_MR14_Pos = 0xe       // Position of MR14 field.
	EXTI_D3PMR1_MR14_Msk = 0x4000    // Bit mask of MR14 field.
	EXTI_D3PMR1_MR14     = 0x4000    // Bit MR14.
	EXTI_D3PMR1_MR15_Pos = 0xf       // Position of MR15 field.
	EXTI_D3PMR1_MR15_Msk = 0x8000    // Bit mask of MR15 field.
	EXTI_D3PMR1_MR15     = 0x8000    // Bit MR15.
	EXTI_D3PMR1_MR19_Pos = 0x13      // Position of MR19 field.
	EXTI_D3PMR1_MR19_Msk = 0x80000   // Bit mask of MR19 field.
	EXTI_D3PMR1_MR19     = 0x80000   // Bit MR19.
	EXTI_D3PMR1_MR20_Pos = 0x14      // Position of MR20 field.
	EXTI_D3PMR1_MR20_Msk = 0x100000  // Bit mask of MR20 field.
	EXTI_D3PMR1_MR20     = 0x100000  // Bit MR20.
	EXTI_D3PMR1_MR21_Pos = 0x15      // Position of MR21 field.
	EXTI_D3PMR1_MR21_Msk = 0x200000  // Bit mask of MR21 field.
	EXTI_D3PMR1_MR21     = 0x200000  // Bit MR21.
	EXTI_D3PMR1_MR25_Pos = 0x19      // Position of MR25 field.
	EXTI_D3PMR1_MR25_Msk = 0x2000000 // Bit mask of MR25 field.
	EXTI_D3PMR1_MR25     = 0x2000000 // Bit MR25.

	// D3PCR1L: EXTI D3 pending clear selection register           low
	EXTI_D3PCR1L_PCS0_Pos  = 0x0        // Position of PCS0 field.
	EXTI_D3PCR1L_PCS0_Msk  = 0x3        // Bit mask of PCS0 field.
	EXTI_D3PCR1L_PCS1_Pos  = 0x2        // Position of PCS1 field.
	EXTI_D3PCR1L_PCS1_Msk  = 0xc        // Bit mask of PCS1 field.
	EXTI_D3PCR1L_PCS2_Pos  = 0x4        // Position of PCS2 field.
	EXTI_D3PCR1L_PCS2_Msk  = 0x30       // Bit mask of PCS2 field.
	EXTI_D3PCR1L_PCS3_Pos  = 0x6        // Position of PCS3 field.
	EXTI_D3PCR1L_PCS3_Msk  = 0xc0       // Bit mask of PCS3 field.
	EXTI_D3PCR1L_PCS4_Pos  = 0x8        // Position of PCS4 field.
	EXTI_D3PCR1L_PCS4_Msk  = 0x300      // Bit mask of PCS4 field.
	EXTI_D3PCR1L_PCS5_Pos  = 0xa        // Position of PCS5 field.
	EXTI_D3PCR1L_PCS5_Msk  = 0xc00      // Bit mask of PCS5 field.
	EXTI_D3PCR1L_PCS6_Pos  = 0xc        // Position of PCS6 field.
	EXTI_D3PCR1L_PCS6_Msk  = 0x3000     // Bit mask of PCS6 field.
	EXTI_D3PCR1L_PCS7_Pos  = 0xe        // Position of PCS7 field.
	EXTI_D3PCR1L_PCS7_Msk  = 0xc000     // Bit mask of PCS7 field.
	EXTI_D3PCR1L_PCS8_Pos  = 0x10       // Position of PCS8 field.
	EXTI_D3PCR1L_PCS8_Msk  = 0x30000    // Bit mask of PCS8 field.
	EXTI_D3PCR1L_PCS9_Pos  = 0x12       // Position of PCS9 field.
	EXTI_D3PCR1L_PCS9_Msk  = 0xc0000    // Bit mask of PCS9 field.
	EXTI_D3PCR1L_PCS10_Pos = 0x14       // Position of PCS10 field.
	EXTI_D3PCR1L_PCS10_Msk = 0x300000   // Bit mask of PCS10 field.
	EXTI_D3PCR1L_PCS11_Pos = 0x16       // Position of PCS11 field.
	EXTI_D3PCR1L_PCS11_Msk = 0xc00000   // Bit mask of PCS11 field.
	EXTI_D3PCR1L_PCS12_Pos = 0x18       // Position of PCS12 field.
	EXTI_D3PCR1L_PCS12_Msk = 0x3000000  // Bit mask of PCS12 field.
	EXTI_D3PCR1L_PCS13_Pos = 0x1a       // Position of PCS13 field.
	EXTI_D3PCR1L_PCS13_Msk = 0xc000000  // Bit mask of PCS13 field.
	EXTI_D3PCR1L_PCS14_Pos = 0x1c       // Position of PCS14 field.
	EXTI_D3PCR1L_PCS14_Msk = 0x30000000 // Bit mask of PCS14 field.
	EXTI_D3PCR1L_PCS15_Pos = 0x1e       // Position of PCS15 field.
	EXTI_D3PCR1L_PCS15_Msk = 0xc0000000 // Bit mask of PCS15 field.

	// D3PCR1H: EXTI D3 pending clear selection register           high
	EXTI_D3PCR1H_PCS19_Pos = 0x6     // Position of PCS19 field.
	EXTI_D3PCR1H_PCS19_Msk = 0xc0    // Bit mask of PCS19 field.
	EXTI_D3PCR1H_PCS20_Pos = 0x8     // Position of PCS20 field.
	EXTI_D3PCR1H_PCS20_Msk = 0x300   // Bit mask of PCS20 field.
	EXTI_D3PCR1H_PCS21_Pos = 0xa     // Position of PCS21 field.
	EXTI_D3PCR1H_PCS21_Msk = 0xc00   // Bit mask of PCS21 field.
	EXTI_D3PCR1H_PCS25_Pos = 0x12    // Position of PCS25 field.
	EXTI_D3PCR1H_PCS25_Msk = 0xc0000 // Bit mask of PCS25 field.

	// RTSR2: EXTI rising trigger selection           register
	EXTI_RTSR2_TR49_Pos = 0x11    // Position of TR49 field.
	EXTI_RTSR2_TR49_Msk = 0x20000 // Bit mask of TR49 field.
	EXTI_RTSR2_TR49     = 0x20000 // Bit TR49.
	EXTI_RTSR2_TR51_Pos = 0x13    // Position of TR51 field.
	EXTI_RTSR2_TR51_Msk = 0x80000 // Bit mask of TR51 field.
	EXTI_RTSR2_TR51     = 0x80000 // Bit TR51.

	// FTSR2: EXTI falling trigger selection           register
	EXTI_FTSR2_TR49_Pos = 0x11    // Position of TR49 field.
	EXTI_FTSR2_TR49_Msk = 0x20000 // Bit mask of TR49 field.
	EXTI_FTSR2_TR49     = 0x20000 // Bit TR49.
	EXTI_FTSR2_TR51_Pos = 0x13    // Position of TR51 field.
	EXTI_FTSR2_TR51_Msk = 0x80000 // Bit mask of TR51 field.
	EXTI_FTSR2_TR51     = 0x80000 // Bit TR51.

	// SWIER2: EXTI software interrupt event           register
	EXTI_SWIER2_SWIER49_Pos = 0x11    // Position of SWIER49 field.
	EXTI_SWIER2_SWIER49_Msk = 0x20000 // Bit mask of SWIER49 field.
	EXTI_SWIER2_SWIER49     = 0x20000 // Bit SWIER49.
	EXTI_SWIER2_SWIER51_Pos = 0x13    // Position of SWIER51 field.
	EXTI_SWIER2_SWIER51_Msk = 0x80000 // Bit mask of SWIER51 field.
	EXTI_SWIER2_SWIER51     = 0x80000 // Bit SWIER51.

	// D3PMR2: EXTI D3 pending mask register
	EXTI_D3PMR2_MR34_Pos = 0x2      // Position of MR34 field.
	EXTI_D3PMR2_MR34_Msk = 0x4      // Bit mask of MR34 field.
	EXTI_D3PMR2_MR34     = 0x4      // Bit MR34.
	EXTI_D3PMR2_MR35_Pos = 0x3      // Position of MR35 field.
	EXTI_D3PMR2_MR35_Msk = 0x8      // Bit mask of MR35 field.
	EXTI_D3PMR2_MR35     = 0x8      // Bit MR35.
	EXTI_D3PMR2_MR41_Pos = 0x9      // Position of MR41 field.
	EXTI_D3PMR2_MR41_Msk = 0x200    // Bit mask of MR41 field.
	EXTI_D3PMR2_MR41     = 0x200    // Bit MR41.
	EXTI_D3PMR2_MR48_Pos = 0x10     // Position of MR48 field.
	EXTI_D3PMR2_MR48_Msk = 0x10000  // Bit mask of MR48 field.
	EXTI_D3PMR2_MR48     = 0x10000  // Bit MR48.
	EXTI_D3PMR2_MR49_Pos = 0x11     // Position of MR49 field.
	EXTI_D3PMR2_MR49_Msk = 0x20000  // Bit mask of MR49 field.
	EXTI_D3PMR2_MR49     = 0x20000  // Bit MR49.
	EXTI_D3PMR2_MR50_Pos = 0x12     // Position of MR50 field.
	EXTI_D3PMR2_MR50_Msk = 0x40000  // Bit mask of MR50 field.
	EXTI_D3PMR2_MR50     = 0x40000  // Bit MR50.
	EXTI_D3PMR2_MR51_Pos = 0x13     // Position of MR51 field.
	EXTI_D3PMR2_MR51_Msk = 0x80000  // Bit mask of MR51 field.
	EXTI_D3PMR2_MR51     = 0x80000  // Bit MR51.
	EXTI_D3PMR2_MR52_Pos = 0x14     // Position of MR52 field.
	EXTI_D3PMR2_MR52_Msk = 0x100000 // Bit mask of MR52 field.
	EXTI_D3PMR2_MR52     = 0x100000 // Bit MR52.
	EXTI_D3PMR2_MR53_Pos = 0x15     // Position of MR53 field.
	EXTI_D3PMR2_MR53_Msk = 0x200000 // Bit mask of MR53 field.
	EXTI_D3PMR2_MR53     = 0x200000 // Bit MR53.

	// D3PCR2L: EXTI D3 pending clear selection register           low
	EXTI_D3PCR2L_PCS35_Pos = 0x6     // Position of PCS35 field.
	EXTI_D3PCR2L_PCS35_Msk = 0xc0    // Bit mask of PCS35 field.
	EXTI_D3PCR2L_PCS34_Pos = 0x4     // Position of PCS34 field.
	EXTI_D3PCR2L_PCS34_Msk = 0x30    // Bit mask of PCS34 field.
	EXTI_D3PCR2L_PCS41_Pos = 0x12    // Position of PCS41 field.
	EXTI_D3PCR2L_PCS41_Msk = 0xc0000 // Bit mask of PCS41 field.

	// D3PCR2H: EXTI D3 pending clear selection register           high
	EXTI_D3PCR2H_PCS48_Pos = 0x0   // Position of PCS48 field.
	EXTI_D3PCR2H_PCS48_Msk = 0x3   // Bit mask of PCS48 field.
	EXTI_D3PCR2H_PCS49_Pos = 0x2   // Position of PCS49 field.
	EXTI_D3PCR2H_PCS49_Msk = 0xc   // Bit mask of PCS49 field.
	EXTI_D3PCR2H_PCS50_Pos = 0x4   // Position of PCS50 field.
	EXTI_D3PCR2H_PCS50_Msk = 0x30  // Bit mask of PCS50 field.
	EXTI_D3PCR2H_PCS51_Pos = 0x6   // Position of PCS51 field.
	EXTI_D3PCR2H_PCS51_Msk = 0xc0  // Bit mask of PCS51 field.
	EXTI_D3PCR2H_PCS52_Pos = 0x8   // Position of PCS52 field.
	EXTI_D3PCR2H_PCS52_Msk = 0x300 // Bit mask of PCS52 field.
	EXTI_D3PCR2H_PCS53_Pos = 0xa   // Position of PCS53 field.
	EXTI_D3PCR2H_PCS53_Msk = 0xc00 // Bit mask of PCS53 field.

	// RTSR3: EXTI rising trigger selection           register
	EXTI_RTSR3_TR82_Pos = 0x12     // Position of TR82 field.
	EXTI_RTSR3_TR82_Msk = 0x40000  // Bit mask of TR82 field.
	EXTI_RTSR3_TR82     = 0x40000  // Bit TR82.
	EXTI_RTSR3_TR84_Pos = 0x14     // Position of TR84 field.
	EXTI_RTSR3_TR84_Msk = 0x100000 // Bit mask of TR84 field.
	EXTI_RTSR3_TR84     = 0x100000 // Bit TR84.
	EXTI_RTSR3_TR85_Pos = 0x15     // Position of TR85 field.
	EXTI_RTSR3_TR85_Msk = 0x200000 // Bit mask of TR85 field.
	EXTI_RTSR3_TR85     = 0x200000 // Bit TR85.
	EXTI_RTSR3_TR86_Pos = 0x16     // Position of TR86 field.
	EXTI_RTSR3_TR86_Msk = 0x400000 // Bit mask of TR86 field.
	EXTI_RTSR3_TR86     = 0x400000 // Bit TR86.

	// FTSR3: EXTI falling trigger selection           register
	EXTI_FTSR3_TR82_Pos = 0x12     // Position of TR82 field.
	EXTI_FTSR3_TR82_Msk = 0x40000  // Bit mask of TR82 field.
	EXTI_FTSR3_TR82     = 0x40000  // Bit TR82.
	EXTI_FTSR3_TR84_Pos = 0x14     // Position of TR84 field.
	EXTI_FTSR3_TR84_Msk = 0x100000 // Bit mask of TR84 field.
	EXTI_FTSR3_TR84     = 0x100000 // Bit TR84.
	EXTI_FTSR3_TR85_Pos = 0x15     // Position of TR85 field.
	EXTI_FTSR3_TR85_Msk = 0x200000 // Bit mask of TR85 field.
	EXTI_FTSR3_TR85     = 0x200000 // Bit TR85.
	EXTI_FTSR3_TR86_Pos = 0x16     // Position of TR86 field.
	EXTI_FTSR3_TR86_Msk = 0x400000 // Bit mask of TR86 field.
	EXTI_FTSR3_TR86     = 0x400000 // Bit TR86.

	// SWIER3: EXTI software interrupt event           register
	EXTI_SWIER3_SWIER82_Pos = 0x12     // Position of SWIER82 field.
	EXTI_SWIER3_SWIER82_Msk = 0x40000  // Bit mask of SWIER82 field.
	EXTI_SWIER3_SWIER82     = 0x40000  // Bit SWIER82.
	EXTI_SWIER3_SWIER84_Pos = 0x14     // Position of SWIER84 field.
	EXTI_SWIER3_SWIER84_Msk = 0x100000 // Bit mask of SWIER84 field.
	EXTI_SWIER3_SWIER84     = 0x100000 // Bit SWIER84.
	EXTI_SWIER3_SWIER85_Pos = 0x15     // Position of SWIER85 field.
	EXTI_SWIER3_SWIER85_Msk = 0x200000 // Bit mask of SWIER85 field.
	EXTI_SWIER3_SWIER85     = 0x200000 // Bit SWIER85.
	EXTI_SWIER3_SWIER86_Pos = 0x16     // Position of SWIER86 field.
	EXTI_SWIER3_SWIER86_Msk = 0x400000 // Bit mask of SWIER86 field.
	EXTI_SWIER3_SWIER86     = 0x400000 // Bit SWIER86.

	// D3PMR3: EXTI D3 pending mask register
	EXTI_D3PMR3_MR88_Pos = 0x18      // Position of MR88 field.
	EXTI_D3PMR3_MR88_Msk = 0x1000000 // Bit mask of MR88 field.
	EXTI_D3PMR3_MR88     = 0x1000000 // Bit MR88.

	// D3PCR3H: EXTI D3 pending clear selection register           high
	EXTI_D3PCR3H_PCS88_Pos = 0x12    // Position of PCS88 field.
	EXTI_D3PCR3H_PCS88_Msk = 0xc0000 // Bit mask of PCS88 field.

	// CPUIMR1: EXTI interrupt mask register
	EXTI_CPUIMR1_MR0_Pos  = 0x0        // Position of MR0 field.
	EXTI_CPUIMR1_MR0_Msk  = 0x1        // Bit mask of MR0 field.
	EXTI_CPUIMR1_MR0      = 0x1        // Bit MR0.
	EXTI_CPUIMR1_MR1_Pos  = 0x1        // Position of MR1 field.
	EXTI_CPUIMR1_MR1_Msk  = 0x2        // Bit mask of MR1 field.
	EXTI_CPUIMR1_MR1      = 0x2        // Bit MR1.
	EXTI_CPUIMR1_MR2_Pos  = 0x2        // Position of MR2 field.
	EXTI_CPUIMR1_MR2_Msk  = 0x4        // Bit mask of MR2 field.
	EXTI_CPUIMR1_MR2      = 0x4        // Bit MR2.
	EXTI_CPUIMR1_MR3_Pos  = 0x3        // Position of MR3 field.
	EXTI_CPUIMR1_MR3_Msk  = 0x8        // Bit mask of MR3 field.
	EXTI_CPUIMR1_MR3      = 0x8        // Bit MR3.
	EXTI_CPUIMR1_MR4_Pos  = 0x4        // Position of MR4 field.
	EXTI_CPUIMR1_MR4_Msk  = 0x10       // Bit mask of MR4 field.
	EXTI_CPUIMR1_MR4      = 0x10       // Bit MR4.
	EXTI_CPUIMR1_MR5_Pos  = 0x5        // Position of MR5 field.
	EXTI_CPUIMR1_MR5_Msk  = 0x20       // Bit mask of MR5 field.
	EXTI_CPUIMR1_MR5      = 0x20       // Bit MR5.
	EXTI_CPUIMR1_MR6_Pos  = 0x6        // Position of MR6 field.
	EXTI_CPUIMR1_MR6_Msk  = 0x40       // Bit mask of MR6 field.
	EXTI_CPUIMR1_MR6      = 0x40       // Bit MR6.
	EXTI_CPUIMR1_MR7_Pos  = 0x7        // Position of MR7 field.
	EXTI_CPUIMR1_MR7_Msk  = 0x80       // Bit mask of MR7 field.
	EXTI_CPUIMR1_MR7      = 0x80       // Bit MR7.
	EXTI_CPUIMR1_MR8_Pos  = 0x8        // Position of MR8 field.
	EXTI_CPUIMR1_MR8_Msk  = 0x100      // Bit mask of MR8 field.
	EXTI_CPUIMR1_MR8      = 0x100      // Bit MR8.
	EXTI_CPUIMR1_MR9_Pos  = 0x9        // Position of MR9 field.
	EXTI_CPUIMR1_MR9_Msk  = 0x200      // Bit mask of MR9 field.
	EXTI_CPUIMR1_MR9      = 0x200      // Bit MR9.
	EXTI_CPUIMR1_MR10_Pos = 0xa        // Position of MR10 field.
	EXTI_CPUIMR1_MR10_Msk = 0x400      // Bit mask of MR10 field.
	EXTI_CPUIMR1_MR10     = 0x400      // Bit MR10.
	EXTI_CPUIMR1_MR11_Pos = 0xb        // Position of MR11 field.
	EXTI_CPUIMR1_MR11_Msk = 0x800      // Bit mask of MR11 field.
	EXTI_CPUIMR1_MR11     = 0x800      // Bit MR11.
	EXTI_CPUIMR1_MR12_Pos = 0xc        // Position of MR12 field.
	EXTI_CPUIMR1_MR12_Msk = 0x1000     // Bit mask of MR12 field.
	EXTI_CPUIMR1_MR12     = 0x1000     // Bit MR12.
	EXTI_CPUIMR1_MR13_Pos = 0xd        // Position of MR13 field.
	EXTI_CPUIMR1_MR13_Msk = 0x2000     // Bit mask of MR13 field.
	EXTI_CPUIMR1_MR13     = 0x2000     // Bit MR13.
	EXTI_CPUIMR1_MR14_Pos = 0xe        // Position of MR14 field.
	EXTI_CPUIMR1_MR14_Msk = 0x4000     // Bit mask of MR14 field.
	EXTI_CPUIMR1_MR14     = 0x4000     // Bit MR14.
	EXTI_CPUIMR1_MR15_Pos = 0xf        // Position of MR15 field.
	EXTI_CPUIMR1_MR15_Msk = 0x8000     // Bit mask of MR15 field.
	EXTI_CPUIMR1_MR15     = 0x8000     // Bit MR15.
	EXTI_CPUIMR1_MR16_Pos = 0x10       // Position of MR16 field.
	EXTI_CPUIMR1_MR16_Msk = 0x10000    // Bit mask of MR16 field.
	EXTI_CPUIMR1_MR16     = 0x10000    // Bit MR16.
	EXTI_CPUIMR1_MR17_Pos = 0x11       // Position of MR17 field.
	EXTI_CPUIMR1_MR17_Msk = 0x20000    // Bit mask of MR17 field.
	EXTI_CPUIMR1_MR17     = 0x20000    // Bit MR17.
	EXTI_CPUIMR1_MR18_Pos = 0x12       // Position of MR18 field.
	EXTI_CPUIMR1_MR18_Msk = 0x40000    // Bit mask of MR18 field.
	EXTI_CPUIMR1_MR18     = 0x40000    // Bit MR18.
	EXTI_CPUIMR1_MR19_Pos = 0x13       // Position of MR19 field.
	EXTI_CPUIMR1_MR19_Msk = 0x80000    // Bit mask of MR19 field.
	EXTI_CPUIMR1_MR19     = 0x80000    // Bit MR19.
	EXTI_CPUIMR1_MR20_Pos = 0x14       // Position of MR20 field.
	EXTI_CPUIMR1_MR20_Msk = 0x100000   // Bit mask of MR20 field.
	EXTI_CPUIMR1_MR20     = 0x100000   // Bit MR20.
	EXTI_CPUIMR1_MR21_Pos = 0x15       // Position of MR21 field.
	EXTI_CPUIMR1_MR21_Msk = 0x200000   // Bit mask of MR21 field.
	EXTI_CPUIMR1_MR21     = 0x200000   // Bit MR21.
	EXTI_CPUIMR1_MR22_Pos = 0x16       // Position of MR22 field.
	EXTI_CPUIMR1_MR22_Msk = 0x400000   // Bit mask of MR22 field.
	EXTI_CPUIMR1_MR22     = 0x400000   // Bit MR22.
	EXTI_CPUIMR1_MR23_Pos = 0x17       // Position of MR23 field.
	EXTI_CPUIMR1_MR23_Msk = 0x800000   // Bit mask of MR23 field.
	EXTI_CPUIMR1_MR23     = 0x800000   // Bit MR23.
	EXTI_CPUIMR1_MR24_Pos = 0x18       // Position of MR24 field.
	EXTI_CPUIMR1_MR24_Msk = 0x1000000  // Bit mask of MR24 field.
	EXTI_CPUIMR1_MR24     = 0x1000000  // Bit MR24.
	EXTI_CPUIMR1_MR25_Pos = 0x19       // Position of MR25 field.
	EXTI_CPUIMR1_MR25_Msk = 0x2000000  // Bit mask of MR25 field.
	EXTI_CPUIMR1_MR25     = 0x2000000  // Bit MR25.
	EXTI_CPUIMR1_MR26_Pos = 0x1a       // Position of MR26 field.
	EXTI_CPUIMR1_MR26_Msk = 0x4000000  // Bit mask of MR26 field.
	EXTI_CPUIMR1_MR26     = 0x4000000  // Bit MR26.
	EXTI_CPUIMR1_MR27_Pos = 0x1b       // Position of MR27 field.
	EXTI_CPUIMR1_MR27_Msk = 0x8000000  // Bit mask of MR27 field.
	EXTI_CPUIMR1_MR27     = 0x8000000  // Bit MR27.
	EXTI_CPUIMR1_MR28_Pos = 0x1c       // Position of MR28 field.
	EXTI_CPUIMR1_MR28_Msk = 0x10000000 // Bit mask of MR28 field.
	EXTI_CPUIMR1_MR28     = 0x10000000 // Bit MR28.
	EXTI_CPUIMR1_MR29_Pos = 0x1d       // Position of MR29 field.
	EXTI_CPUIMR1_MR29_Msk = 0x20000000 // Bit mask of MR29 field.
	EXTI_CPUIMR1_MR29     = 0x20000000 // Bit MR29.
	EXTI_CPUIMR1_MR30_Pos = 0x1e       // Position of MR30 field.
	EXTI_CPUIMR1_MR30_Msk = 0x40000000 // Bit mask of MR30 field.
	EXTI_CPUIMR1_MR30     = 0x40000000 // Bit MR30.
	EXTI_CPUIMR1_MR31_Pos = 0x1f       // Position of MR31 field.
	EXTI_CPUIMR1_MR31_Msk = 0x80000000 // Bit mask of MR31 field.
	EXTI_CPUIMR1_MR31     = 0x80000000 // Bit MR31.

	// CPUEMR1: EXTI event mask register
	EXTI_CPUEMR1_MR0_Pos  = 0x0        // Position of MR0 field.
	EXTI_CPUEMR1_MR0_Msk  = 0x1        // Bit mask of MR0 field.
	EXTI_CPUEMR1_MR0      = 0x1        // Bit MR0.
	EXTI_CPUEMR1_MR1_Pos  = 0x1        // Position of MR1 field.
	EXTI_CPUEMR1_MR1_Msk  = 0x2        // Bit mask of MR1 field.
	EXTI_CPUEMR1_MR1      = 0x2        // Bit MR1.
	EXTI_CPUEMR1_MR2_Pos  = 0x2        // Position of MR2 field.
	EXTI_CPUEMR1_MR2_Msk  = 0x4        // Bit mask of MR2 field.
	EXTI_CPUEMR1_MR2      = 0x4        // Bit MR2.
	EXTI_CPUEMR1_MR3_Pos  = 0x3        // Position of MR3 field.
	EXTI_CPUEMR1_MR3_Msk  = 0x8        // Bit mask of MR3 field.
	EXTI_CPUEMR1_MR3      = 0x8        // Bit MR3.
	EXTI_CPUEMR1_MR4_Pos  = 0x4        // Position of MR4 field.
	EXTI_CPUEMR1_MR4_Msk  = 0x10       // Bit mask of MR4 field.
	EXTI_CPUEMR1_MR4      = 0x10       // Bit MR4.
	EXTI_CPUEMR1_MR5_Pos  = 0x5        // Position of MR5 field.
	EXTI_CPUEMR1_MR5_Msk  = 0x20       // Bit mask of MR5 field.
	EXTI_CPUEMR1_MR5      = 0x20       // Bit MR5.
	EXTI_CPUEMR1_MR6_Pos  = 0x6        // Position of MR6 field.
	EXTI_CPUEMR1_MR6_Msk  = 0x40       // Bit mask of MR6 field.
	EXTI_CPUEMR1_MR6      = 0x40       // Bit MR6.
	EXTI_CPUEMR1_MR7_Pos  = 0x7        // Position of MR7 field.
	EXTI_CPUEMR1_MR7_Msk  = 0x80       // Bit mask of MR7 field.
	EXTI_CPUEMR1_MR7      = 0x80       // Bit MR7.
	EXTI_CPUEMR1_MR8_Pos  = 0x8        // Position of MR8 field.
	EXTI_CPUEMR1_MR8_Msk  = 0x100      // Bit mask of MR8 field.
	EXTI_CPUEMR1_MR8      = 0x100      // Bit MR8.
	EXTI_CPUEMR1_MR9_Pos  = 0x9        // Position of MR9 field.
	EXTI_CPUEMR1_MR9_Msk  = 0x200      // Bit mask of MR9 field.
	EXTI_CPUEMR1_MR9      = 0x200      // Bit MR9.
	EXTI_CPUEMR1_MR10_Pos = 0xa        // Position of MR10 field.
	EXTI_CPUEMR1_MR10_Msk = 0x400      // Bit mask of MR10 field.
	EXTI_CPUEMR1_MR10     = 0x400      // Bit MR10.
	EXTI_CPUEMR1_MR11_Pos = 0xb        // Position of MR11 field.
	EXTI_CPUEMR1_MR11_Msk = 0x800      // Bit mask of MR11 field.
	EXTI_CPUEMR1_MR11     = 0x800      // Bit MR11.
	EXTI_CPUEMR1_MR12_Pos = 0xc        // Position of MR12 field.
	EXTI_CPUEMR1_MR12_Msk = 0x1000     // Bit mask of MR12 field.
	EXTI_CPUEMR1_MR12     = 0x1000     // Bit MR12.
	EXTI_CPUEMR1_MR13_Pos = 0xd        // Position of MR13 field.
	EXTI_CPUEMR1_MR13_Msk = 0x2000     // Bit mask of MR13 field.
	EXTI_CPUEMR1_MR13     = 0x2000     // Bit MR13.
	EXTI_CPUEMR1_MR14_Pos = 0xe        // Position of MR14 field.
	EXTI_CPUEMR1_MR14_Msk = 0x4000     // Bit mask of MR14 field.
	EXTI_CPUEMR1_MR14     = 0x4000     // Bit MR14.
	EXTI_CPUEMR1_MR15_Pos = 0xf        // Position of MR15 field.
	EXTI_CPUEMR1_MR15_Msk = 0x8000     // Bit mask of MR15 field.
	EXTI_CPUEMR1_MR15     = 0x8000     // Bit MR15.
	EXTI_CPUEMR1_MR16_Pos = 0x10       // Position of MR16 field.
	EXTI_CPUEMR1_MR16_Msk = 0x10000    // Bit mask of MR16 field.
	EXTI_CPUEMR1_MR16     = 0x10000    // Bit MR16.
	EXTI_CPUEMR1_MR17_Pos = 0x11       // Position of MR17 field.
	EXTI_CPUEMR1_MR17_Msk = 0x20000    // Bit mask of MR17 field.
	EXTI_CPUEMR1_MR17     = 0x20000    // Bit MR17.
	EXTI_CPUEMR1_MR18_Pos = 0x12       // Position of MR18 field.
	EXTI_CPUEMR1_MR18_Msk = 0x40000    // Bit mask of MR18 field.
	EXTI_CPUEMR1_MR18     = 0x40000    // Bit MR18.
	EXTI_CPUEMR1_MR19_Pos = 0x13       // Position of MR19 field.
	EXTI_CPUEMR1_MR19_Msk = 0x80000    // Bit mask of MR19 field.
	EXTI_CPUEMR1_MR19     = 0x80000    // Bit MR19.
	EXTI_CPUEMR1_MR20_Pos = 0x14       // Position of MR20 field.
	EXTI_CPUEMR1_MR20_Msk = 0x100000   // Bit mask of MR20 field.
	EXTI_CPUEMR1_MR20     = 0x100000   // Bit MR20.
	EXTI_CPUEMR1_MR21_Pos = 0x15       // Position of MR21 field.
	EXTI_CPUEMR1_MR21_Msk = 0x200000   // Bit mask of MR21 field.
	EXTI_CPUEMR1_MR21     = 0x200000   // Bit MR21.
	EXTI_CPUEMR1_MR22_Pos = 0x16       // Position of MR22 field.
	EXTI_CPUEMR1_MR22_Msk = 0x400000   // Bit mask of MR22 field.
	EXTI_CPUEMR1_MR22     = 0x400000   // Bit MR22.
	EXTI_CPUEMR1_MR23_Pos = 0x17       // Position of MR23 field.
	EXTI_CPUEMR1_MR23_Msk = 0x800000   // Bit mask of MR23 field.
	EXTI_CPUEMR1_MR23     = 0x800000   // Bit MR23.
	EXTI_CPUEMR1_MR24_Pos = 0x18       // Position of MR24 field.
	EXTI_CPUEMR1_MR24_Msk = 0x1000000  // Bit mask of MR24 field.
	EXTI_CPUEMR1_MR24     = 0x1000000  // Bit MR24.
	EXTI_CPUEMR1_MR25_Pos = 0x19       // Position of MR25 field.
	EXTI_CPUEMR1_MR25_Msk = 0x2000000  // Bit mask of MR25 field.
	EXTI_CPUEMR1_MR25     = 0x2000000  // Bit MR25.
	EXTI_CPUEMR1_MR26_Pos = 0x1a       // Position of MR26 field.
	EXTI_CPUEMR1_MR26_Msk = 0x4000000  // Bit mask of MR26 field.
	EXTI_CPUEMR1_MR26     = 0x4000000  // Bit MR26.
	EXTI_CPUEMR1_MR27_Pos = 0x1b       // Position of MR27 field.
	EXTI_CPUEMR1_MR27_Msk = 0x8000000  // Bit mask of MR27 field.
	EXTI_CPUEMR1_MR27     = 0x8000000  // Bit MR27.
	EXTI_CPUEMR1_MR28_Pos = 0x1c       // Position of MR28 field.
	EXTI_CPUEMR1_MR28_Msk = 0x10000000 // Bit mask of MR28 field.
	EXTI_CPUEMR1_MR28     = 0x10000000 // Bit MR28.
	EXTI_CPUEMR1_MR29_Pos = 0x1d       // Position of MR29 field.
	EXTI_CPUEMR1_MR29_Msk = 0x20000000 // Bit mask of MR29 field.
	EXTI_CPUEMR1_MR29     = 0x20000000 // Bit MR29.
	EXTI_CPUEMR1_MR30_Pos = 0x1e       // Position of MR30 field.
	EXTI_CPUEMR1_MR30_Msk = 0x40000000 // Bit mask of MR30 field.
	EXTI_CPUEMR1_MR30     = 0x40000000 // Bit MR30.
	EXTI_CPUEMR1_MR31_Pos = 0x1f       // Position of MR31 field.
	EXTI_CPUEMR1_MR31_Msk = 0x80000000 // Bit mask of MR31 field.
	EXTI_CPUEMR1_MR31     = 0x80000000 // Bit MR31.

	// CPUPR1: EXTI pending register
	EXTI_CPUPR1_PR0_Pos  = 0x0      // Position of PR0 field.
	EXTI_CPUPR1_PR0_Msk  = 0x1      // Bit mask of PR0 field.
	EXTI_CPUPR1_PR0      = 0x1      // Bit PR0.
	EXTI_CPUPR1_PR1_Pos  = 0x1      // Position of PR1 field.
	EXTI_CPUPR1_PR1_Msk  = 0x2      // Bit mask of PR1 field.
	EXTI_CPUPR1_PR1      = 0x2      // Bit PR1.
	EXTI_CPUPR1_PR2_Pos  = 0x2      // Position of PR2 field.
	EXTI_CPUPR1_PR2_Msk  = 0x4      // Bit mask of PR2 field.
	EXTI_CPUPR1_PR2      = 0x4      // Bit PR2.
	EXTI_CPUPR1_PR3_Pos  = 0x3      // Position of PR3 field.
	EXTI_CPUPR1_PR3_Msk  = 0x8      // Bit mask of PR3 field.
	EXTI_CPUPR1_PR3      = 0x8      // Bit PR3.
	EXTI_CPUPR1_PR4_Pos  = 0x4      // Position of PR4 field.
	EXTI_CPUPR1_PR4_Msk  = 0x10     // Bit mask of PR4 field.
	EXTI_CPUPR1_PR4      = 0x10     // Bit PR4.
	EXTI_CPUPR1_PR5_Pos  = 0x5      // Position of PR5 field.
	EXTI_CPUPR1_PR5_Msk  = 0x20     // Bit mask of PR5 field.
	EXTI_CPUPR1_PR5      = 0x20     // Bit PR5.
	EXTI_CPUPR1_PR6_Pos  = 0x6      // Position of PR6 field.
	EXTI_CPUPR1_PR6_Msk  = 0x40     // Bit mask of PR6 field.
	EXTI_CPUPR1_PR6      = 0x40     // Bit PR6.
	EXTI_CPUPR1_PR7_Pos  = 0x7      // Position of PR7 field.
	EXTI_CPUPR1_PR7_Msk  = 0x80     // Bit mask of PR7 field.
	EXTI_CPUPR1_PR7      = 0x80     // Bit PR7.
	EXTI_CPUPR1_PR8_Pos  = 0x8      // Position of PR8 field.
	EXTI_CPUPR1_PR8_Msk  = 0x100    // Bit mask of PR8 field.
	EXTI_CPUPR1_PR8      = 0x100    // Bit PR8.
	EXTI_CPUPR1_PR9_Pos  = 0x9      // Position of PR9 field.
	EXTI_CPUPR1_PR9_Msk  = 0x200    // Bit mask of PR9 field.
	EXTI_CPUPR1_PR9      = 0x200    // Bit PR9.
	EXTI_CPUPR1_PR10_Pos = 0xa      // Position of PR10 field.
	EXTI_CPUPR1_PR10_Msk = 0x400    // Bit mask of PR10 field.
	EXTI_CPUPR1_PR10     = 0x400    // Bit PR10.
	EXTI_CPUPR1_PR11_Pos = 0xb      // Position of PR11 field.
	EXTI_CPUPR1_PR11_Msk = 0x800    // Bit mask of PR11 field.
	EXTI_CPUPR1_PR11     = 0x800    // Bit PR11.
	EXTI_CPUPR1_PR12_Pos = 0xc      // Position of PR12 field.
	EXTI_CPUPR1_PR12_Msk = 0x1000   // Bit mask of PR12 field.
	EXTI_CPUPR1_PR12     = 0x1000   // Bit PR12.
	EXTI_CPUPR1_PR13_Pos = 0xd      // Position of PR13 field.
	EXTI_CPUPR1_PR13_Msk = 0x2000   // Bit mask of PR13 field.
	EXTI_CPUPR1_PR13     = 0x2000   // Bit PR13.
	EXTI_CPUPR1_PR14_Pos = 0xe      // Position of PR14 field.
	EXTI_CPUPR1_PR14_Msk = 0x4000   // Bit mask of PR14 field.
	EXTI_CPUPR1_PR14     = 0x4000   // Bit PR14.
	EXTI_CPUPR1_PR15_Pos = 0xf      // Position of PR15 field.
	EXTI_CPUPR1_PR15_Msk = 0x8000   // Bit mask of PR15 field.
	EXTI_CPUPR1_PR15     = 0x8000   // Bit PR15.
	EXTI_CPUPR1_PR16_Pos = 0x10     // Position of PR16 field.
	EXTI_CPUPR1_PR16_Msk = 0x10000  // Bit mask of PR16 field.
	EXTI_CPUPR1_PR16     = 0x10000  // Bit PR16.
	EXTI_CPUPR1_PR17_Pos = 0x11     // Position of PR17 field.
	EXTI_CPUPR1_PR17_Msk = 0x20000  // Bit mask of PR17 field.
	EXTI_CPUPR1_PR17     = 0x20000  // Bit PR17.
	EXTI_CPUPR1_PR18_Pos = 0x12     // Position of PR18 field.
	EXTI_CPUPR1_PR18_Msk = 0x40000  // Bit mask of PR18 field.
	EXTI_CPUPR1_PR18     = 0x40000  // Bit PR18.
	EXTI_CPUPR1_PR19_Pos = 0x13     // Position of PR19 field.
	EXTI_CPUPR1_PR19_Msk = 0x80000  // Bit mask of PR19 field.
	EXTI_CPUPR1_PR19     = 0x80000  // Bit PR19.
	EXTI_CPUPR1_PR20_Pos = 0x14     // Position of PR20 field.
	EXTI_CPUPR1_PR20_Msk = 0x100000 // Bit mask of PR20 field.
	EXTI_CPUPR1_PR20     = 0x100000 // Bit PR20.
	EXTI_CPUPR1_PR21_Pos = 0x15     // Position of PR21 field.
	EXTI_CPUPR1_PR21_Msk = 0x200000 // Bit mask of PR21 field.
	EXTI_CPUPR1_PR21     = 0x200000 // Bit PR21.

	// CPUIMR2: EXTI interrupt mask register
	EXTI_CPUIMR2_MR0_Pos  = 0x0        // Position of MR0 field.
	EXTI_CPUIMR2_MR0_Msk  = 0x1        // Bit mask of MR0 field.
	EXTI_CPUIMR2_MR0      = 0x1        // Bit MR0.
	EXTI_CPUIMR2_MR1_Pos  = 0x1        // Position of MR1 field.
	EXTI_CPUIMR2_MR1_Msk  = 0x2        // Bit mask of MR1 field.
	EXTI_CPUIMR2_MR1      = 0x2        // Bit MR1.
	EXTI_CPUIMR2_MR2_Pos  = 0x2        // Position of MR2 field.
	EXTI_CPUIMR2_MR2_Msk  = 0x4        // Bit mask of MR2 field.
	EXTI_CPUIMR2_MR2      = 0x4        // Bit MR2.
	EXTI_CPUIMR2_MR3_Pos  = 0x3        // Position of MR3 field.
	EXTI_CPUIMR2_MR3_Msk  = 0x8        // Bit mask of MR3 field.
	EXTI_CPUIMR2_MR3      = 0x8        // Bit MR3.
	EXTI_CPUIMR2_MR4_Pos  = 0x4        // Position of MR4 field.
	EXTI_CPUIMR2_MR4_Msk  = 0x10       // Bit mask of MR4 field.
	EXTI_CPUIMR2_MR4      = 0x10       // Bit MR4.
	EXTI_CPUIMR2_MR5_Pos  = 0x5        // Position of MR5 field.
	EXTI_CPUIMR2_MR5_Msk  = 0x20       // Bit mask of MR5 field.
	EXTI_CPUIMR2_MR5      = 0x20       // Bit MR5.
	EXTI_CPUIMR2_MR6_Pos  = 0x6        // Position of MR6 field.
	EXTI_CPUIMR2_MR6_Msk  = 0x40       // Bit mask of MR6 field.
	EXTI_CPUIMR2_MR6      = 0x40       // Bit MR6.
	EXTI_CPUIMR2_MR7_Pos  = 0x7        // Position of MR7 field.
	EXTI_CPUIMR2_MR7_Msk  = 0x80       // Bit mask of MR7 field.
	EXTI_CPUIMR2_MR7      = 0x80       // Bit MR7.
	EXTI_CPUIMR2_MR8_Pos  = 0x8        // Position of MR8 field.
	EXTI_CPUIMR2_MR8_Msk  = 0x100      // Bit mask of MR8 field.
	EXTI_CPUIMR2_MR8      = 0x100      // Bit MR8.
	EXTI_CPUIMR2_MR9_Pos  = 0x9        // Position of MR9 field.
	EXTI_CPUIMR2_MR9_Msk  = 0x200      // Bit mask of MR9 field.
	EXTI_CPUIMR2_MR9      = 0x200      // Bit MR9.
	EXTI_CPUIMR2_MR10_Pos = 0xa        // Position of MR10 field.
	EXTI_CPUIMR2_MR10_Msk = 0x400      // Bit mask of MR10 field.
	EXTI_CPUIMR2_MR10     = 0x400      // Bit MR10.
	EXTI_CPUIMR2_MR11_Pos = 0xb        // Position of MR11 field.
	EXTI_CPUIMR2_MR11_Msk = 0x800      // Bit mask of MR11 field.
	EXTI_CPUIMR2_MR11     = 0x800      // Bit MR11.
	EXTI_CPUIMR2_MR12_Pos = 0xc        // Position of MR12 field.
	EXTI_CPUIMR2_MR12_Msk = 0x1000     // Bit mask of MR12 field.
	EXTI_CPUIMR2_MR12     = 0x1000     // Bit MR12.
	EXTI_CPUIMR2_MR14_Pos = 0xe        // Position of MR14 field.
	EXTI_CPUIMR2_MR14_Msk = 0x4000     // Bit mask of MR14 field.
	EXTI_CPUIMR2_MR14     = 0x4000     // Bit MR14.
	EXTI_CPUIMR2_MR15_Pos = 0xf        // Position of MR15 field.
	EXTI_CPUIMR2_MR15_Msk = 0x8000     // Bit mask of MR15 field.
	EXTI_CPUIMR2_MR15     = 0x8000     // Bit MR15.
	EXTI_CPUIMR2_MR16_Pos = 0x10       // Position of MR16 field.
	EXTI_CPUIMR2_MR16_Msk = 0x10000    // Bit mask of MR16 field.
	EXTI_CPUIMR2_MR16     = 0x10000    // Bit MR16.
	EXTI_CPUIMR2_MR17_Pos = 0x11       // Position of MR17 field.
	EXTI_CPUIMR2_MR17_Msk = 0x20000    // Bit mask of MR17 field.
	EXTI_CPUIMR2_MR17     = 0x20000    // Bit MR17.
	EXTI_CPUIMR2_MR18_Pos = 0x12       // Position of MR18 field.
	EXTI_CPUIMR2_MR18_Msk = 0x40000    // Bit mask of MR18 field.
	EXTI_CPUIMR2_MR18     = 0x40000    // Bit MR18.
	EXTI_CPUIMR2_MR19_Pos = 0x13       // Position of MR19 field.
	EXTI_CPUIMR2_MR19_Msk = 0x80000    // Bit mask of MR19 field.
	EXTI_CPUIMR2_MR19     = 0x80000    // Bit MR19.
	EXTI_CPUIMR2_MR20_Pos = 0x14       // Position of MR20 field.
	EXTI_CPUIMR2_MR20_Msk = 0x100000   // Bit mask of MR20 field.
	EXTI_CPUIMR2_MR20     = 0x100000   // Bit MR20.
	EXTI_CPUIMR2_MR21_Pos = 0x15       // Position of MR21 field.
	EXTI_CPUIMR2_MR21_Msk = 0x200000   // Bit mask of MR21 field.
	EXTI_CPUIMR2_MR21     = 0x200000   // Bit MR21.
	EXTI_CPUIMR2_MR22_Pos = 0x16       // Position of MR22 field.
	EXTI_CPUIMR2_MR22_Msk = 0x400000   // Bit mask of MR22 field.
	EXTI_CPUIMR2_MR22     = 0x400000   // Bit MR22.
	EXTI_CPUIMR2_MR23_Pos = 0x17       // Position of MR23 field.
	EXTI_CPUIMR2_MR23_Msk = 0x800000   // Bit mask of MR23 field.
	EXTI_CPUIMR2_MR23     = 0x800000   // Bit MR23.
	EXTI_CPUIMR2_MR24_Pos = 0x18       // Position of MR24 field.
	EXTI_CPUIMR2_MR24_Msk = 0x1000000  // Bit mask of MR24 field.
	EXTI_CPUIMR2_MR24     = 0x1000000  // Bit MR24.
	EXTI_CPUIMR2_MR25_Pos = 0x19       // Position of MR25 field.
	EXTI_CPUIMR2_MR25_Msk = 0x2000000  // Bit mask of MR25 field.
	EXTI_CPUIMR2_MR25     = 0x2000000  // Bit MR25.
	EXTI_CPUIMR2_MR26_Pos = 0x1a       // Position of MR26 field.
	EXTI_CPUIMR2_MR26_Msk = 0x4000000  // Bit mask of MR26 field.
	EXTI_CPUIMR2_MR26     = 0x4000000  // Bit MR26.
	EXTI_CPUIMR2_MR27_Pos = 0x1b       // Position of MR27 field.
	EXTI_CPUIMR2_MR27_Msk = 0x8000000  // Bit mask of MR27 field.
	EXTI_CPUIMR2_MR27     = 0x8000000  // Bit MR27.
	EXTI_CPUIMR2_MR28_Pos = 0x1c       // Position of MR28 field.
	EXTI_CPUIMR2_MR28_Msk = 0x10000000 // Bit mask of MR28 field.
	EXTI_CPUIMR2_MR28     = 0x10000000 // Bit MR28.
	EXTI_CPUIMR2_MR29_Pos = 0x1d       // Position of MR29 field.
	EXTI_CPUIMR2_MR29_Msk = 0x20000000 // Bit mask of MR29 field.
	EXTI_CPUIMR2_MR29     = 0x20000000 // Bit MR29.
	EXTI_CPUIMR2_MR30_Pos = 0x1e       // Position of MR30 field.
	EXTI_CPUIMR2_MR30_Msk = 0x40000000 // Bit mask of MR30 field.
	EXTI_CPUIMR2_MR30     = 0x40000000 // Bit MR30.
	EXTI_CPUIMR2_MR31_Pos = 0x1f       // Position of MR31 field.
	EXTI_CPUIMR2_MR31_Msk = 0x80000000 // Bit mask of MR31 field.
	EXTI_CPUIMR2_MR31     = 0x80000000 // Bit MR31.

	// CPUEMR2: EXTI event mask register
	EXTI_CPUEMR2_MR32_Pos = 0x0        // Position of MR32 field.
	EXTI_CPUEMR2_MR32_Msk = 0x1        // Bit mask of MR32 field.
	EXTI_CPUEMR2_MR32     = 0x1        // Bit MR32.
	EXTI_CPUEMR2_MR33_Pos = 0x1        // Position of MR33 field.
	EXTI_CPUEMR2_MR33_Msk = 0x2        // Bit mask of MR33 field.
	EXTI_CPUEMR2_MR33     = 0x2        // Bit MR33.
	EXTI_CPUEMR2_MR34_Pos = 0x2        // Position of MR34 field.
	EXTI_CPUEMR2_MR34_Msk = 0x4        // Bit mask of MR34 field.
	EXTI_CPUEMR2_MR34     = 0x4        // Bit MR34.
	EXTI_CPUEMR2_MR35_Pos = 0x3        // Position of MR35 field.
	EXTI_CPUEMR2_MR35_Msk = 0x8        // Bit mask of MR35 field.
	EXTI_CPUEMR2_MR35     = 0x8        // Bit MR35.
	EXTI_CPUEMR2_MR36_Pos = 0x4        // Position of MR36 field.
	EXTI_CPUEMR2_MR36_Msk = 0x10       // Bit mask of MR36 field.
	EXTI_CPUEMR2_MR36     = 0x10       // Bit MR36.
	EXTI_CPUEMR2_MR37_Pos = 0x5        // Position of MR37 field.
	EXTI_CPUEMR2_MR37_Msk = 0x20       // Bit mask of MR37 field.
	EXTI_CPUEMR2_MR37     = 0x20       // Bit MR37.
	EXTI_CPUEMR2_MR38_Pos = 0x6        // Position of MR38 field.
	EXTI_CPUEMR2_MR38_Msk = 0x40       // Bit mask of MR38 field.
	EXTI_CPUEMR2_MR38     = 0x40       // Bit MR38.
	EXTI_CPUEMR2_MR39_Pos = 0x7        // Position of MR39 field.
	EXTI_CPUEMR2_MR39_Msk = 0x80       // Bit mask of MR39 field.
	EXTI_CPUEMR2_MR39     = 0x80       // Bit MR39.
	EXTI_CPUEMR2_MR40_Pos = 0x8        // Position of MR40 field.
	EXTI_CPUEMR2_MR40_Msk = 0x100      // Bit mask of MR40 field.
	EXTI_CPUEMR2_MR40     = 0x100      // Bit MR40.
	EXTI_CPUEMR2_MR41_Pos = 0x9        // Position of MR41 field.
	EXTI_CPUEMR2_MR41_Msk = 0x200      // Bit mask of MR41 field.
	EXTI_CPUEMR2_MR41     = 0x200      // Bit MR41.
	EXTI_CPUEMR2_MR42_Pos = 0xa        // Position of MR42 field.
	EXTI_CPUEMR2_MR42_Msk = 0x400      // Bit mask of MR42 field.
	EXTI_CPUEMR2_MR42     = 0x400      // Bit MR42.
	EXTI_CPUEMR2_MR43_Pos = 0xb        // Position of MR43 field.
	EXTI_CPUEMR2_MR43_Msk = 0x800      // Bit mask of MR43 field.
	EXTI_CPUEMR2_MR43     = 0x800      // Bit MR43.
	EXTI_CPUEMR2_MR44_Pos = 0xc        // Position of MR44 field.
	EXTI_CPUEMR2_MR44_Msk = 0x1000     // Bit mask of MR44 field.
	EXTI_CPUEMR2_MR44     = 0x1000     // Bit MR44.
	EXTI_CPUEMR2_MR46_Pos = 0xe        // Position of MR46 field.
	EXTI_CPUEMR2_MR46_Msk = 0x4000     // Bit mask of MR46 field.
	EXTI_CPUEMR2_MR46     = 0x4000     // Bit MR46.
	EXTI_CPUEMR2_MR47_Pos = 0xf        // Position of MR47 field.
	EXTI_CPUEMR2_MR47_Msk = 0x8000     // Bit mask of MR47 field.
	EXTI_CPUEMR2_MR47     = 0x8000     // Bit MR47.
	EXTI_CPUEMR2_MR48_Pos = 0x10       // Position of MR48 field.
	EXTI_CPUEMR2_MR48_Msk = 0x10000    // Bit mask of MR48 field.
	EXTI_CPUEMR2_MR48     = 0x10000    // Bit MR48.
	EXTI_CPUEMR2_MR49_Pos = 0x11       // Position of MR49 field.
	EXTI_CPUEMR2_MR49_Msk = 0x20000    // Bit mask of MR49 field.
	EXTI_CPUEMR2_MR49     = 0x20000    // Bit MR49.
	EXTI_CPUEMR2_MR50_Pos = 0x12       // Position of MR50 field.
	EXTI_CPUEMR2_MR50_Msk = 0x40000    // Bit mask of MR50 field.
	EXTI_CPUEMR2_MR50     = 0x40000    // Bit MR50.
	EXTI_CPUEMR2_MR51_Pos = 0x13       // Position of MR51 field.
	EXTI_CPUEMR2_MR51_Msk = 0x80000    // Bit mask of MR51 field.
	EXTI_CPUEMR2_MR51     = 0x80000    // Bit MR51.
	EXTI_CPUEMR2_MR52_Pos = 0x14       // Position of MR52 field.
	EXTI_CPUEMR2_MR52_Msk = 0x100000   // Bit mask of MR52 field.
	EXTI_CPUEMR2_MR52     = 0x100000   // Bit MR52.
	EXTI_CPUEMR2_MR53_Pos = 0x15       // Position of MR53 field.
	EXTI_CPUEMR2_MR53_Msk = 0x200000   // Bit mask of MR53 field.
	EXTI_CPUEMR2_MR53     = 0x200000   // Bit MR53.
	EXTI_CPUEMR2_MR54_Pos = 0x16       // Position of MR54 field.
	EXTI_CPUEMR2_MR54_Msk = 0x400000   // Bit mask of MR54 field.
	EXTI_CPUEMR2_MR54     = 0x400000   // Bit MR54.
	EXTI_CPUEMR2_MR55_Pos = 0x17       // Position of MR55 field.
	EXTI_CPUEMR2_MR55_Msk = 0x800000   // Bit mask of MR55 field.
	EXTI_CPUEMR2_MR55     = 0x800000   // Bit MR55.
	EXTI_CPUEMR2_MR56_Pos = 0x18       // Position of MR56 field.
	EXTI_CPUEMR2_MR56_Msk = 0x1000000  // Bit mask of MR56 field.
	EXTI_CPUEMR2_MR56     = 0x1000000  // Bit MR56.
	EXTI_CPUEMR2_MR57_Pos = 0x19       // Position of MR57 field.
	EXTI_CPUEMR2_MR57_Msk = 0x2000000  // Bit mask of MR57 field.
	EXTI_CPUEMR2_MR57     = 0x2000000  // Bit MR57.
	EXTI_CPUEMR2_MR58_Pos = 0x1a       // Position of MR58 field.
	EXTI_CPUEMR2_MR58_Msk = 0x4000000  // Bit mask of MR58 field.
	EXTI_CPUEMR2_MR58     = 0x4000000  // Bit MR58.
	EXTI_CPUEMR2_MR59_Pos = 0x1b       // Position of MR59 field.
	EXTI_CPUEMR2_MR59_Msk = 0x8000000  // Bit mask of MR59 field.
	EXTI_CPUEMR2_MR59     = 0x8000000  // Bit MR59.
	EXTI_CPUEMR2_MR60_Pos = 0x1c       // Position of MR60 field.
	EXTI_CPUEMR2_MR60_Msk = 0x10000000 // Bit mask of MR60 field.
	EXTI_CPUEMR2_MR60     = 0x10000000 // Bit MR60.
	EXTI_CPUEMR2_MR61_Pos = 0x1d       // Position of MR61 field.
	EXTI_CPUEMR2_MR61_Msk = 0x20000000 // Bit mask of MR61 field.
	EXTI_CPUEMR2_MR61     = 0x20000000 // Bit MR61.
	EXTI_CPUEMR2_MR62_Pos = 0x1e       // Position of MR62 field.
	EXTI_CPUEMR2_MR62_Msk = 0x40000000 // Bit mask of MR62 field.
	EXTI_CPUEMR2_MR62     = 0x40000000 // Bit MR62.
	EXTI_CPUEMR2_MR63_Pos = 0x1f       // Position of MR63 field.
	EXTI_CPUEMR2_MR63_Msk = 0x80000000 // Bit mask of MR63 field.
	EXTI_CPUEMR2_MR63     = 0x80000000 // Bit MR63.

	// CPUPR2: EXTI pending register
	EXTI_CPUPR2_PR49_Pos = 0x11    // Position of PR49 field.
	EXTI_CPUPR2_PR49_Msk = 0x20000 // Bit mask of PR49 field.
	EXTI_CPUPR2_PR49     = 0x20000 // Bit PR49.
	EXTI_CPUPR2_PR51_Pos = 0x13    // Position of PR51 field.
	EXTI_CPUPR2_PR51_Msk = 0x80000 // Bit mask of PR51 field.
	EXTI_CPUPR2_PR51     = 0x80000 // Bit PR51.

	// CPUIMR3: EXTI interrupt mask register
	EXTI_CPUIMR3_MR64_Pos = 0x0       // Position of MR64 field.
	EXTI_CPUIMR3_MR64_Msk = 0x1       // Bit mask of MR64 field.
	EXTI_CPUIMR3_MR64     = 0x1       // Bit MR64.
	EXTI_CPUIMR3_MR65_Pos = 0x1       // Position of MR65 field.
	EXTI_CPUIMR3_MR65_Msk = 0x2       // Bit mask of MR65 field.
	EXTI_CPUIMR3_MR65     = 0x2       // Bit MR65.
	EXTI_CPUIMR3_MR66_Pos = 0x2       // Position of MR66 field.
	EXTI_CPUIMR3_MR66_Msk = 0x4       // Bit mask of MR66 field.
	EXTI_CPUIMR3_MR66     = 0x4       // Bit MR66.
	EXTI_CPUIMR3_MR67_Pos = 0x3       // Position of MR67 field.
	EXTI_CPUIMR3_MR67_Msk = 0x8       // Bit mask of MR67 field.
	EXTI_CPUIMR3_MR67     = 0x8       // Bit MR67.
	EXTI_CPUIMR3_MR68_Pos = 0x4       // Position of MR68 field.
	EXTI_CPUIMR3_MR68_Msk = 0x10      // Bit mask of MR68 field.
	EXTI_CPUIMR3_MR68     = 0x10      // Bit MR68.
	EXTI_CPUIMR3_MR69_Pos = 0x5       // Position of MR69 field.
	EXTI_CPUIMR3_MR69_Msk = 0x20      // Bit mask of MR69 field.
	EXTI_CPUIMR3_MR69     = 0x20      // Bit MR69.
	EXTI_CPUIMR3_MR70_Pos = 0x6       // Position of MR70 field.
	EXTI_CPUIMR3_MR70_Msk = 0x40      // Bit mask of MR70 field.
	EXTI_CPUIMR3_MR70     = 0x40      // Bit MR70.
	EXTI_CPUIMR3_MR71_Pos = 0x7       // Position of MR71 field.
	EXTI_CPUIMR3_MR71_Msk = 0x80      // Bit mask of MR71 field.
	EXTI_CPUIMR3_MR71     = 0x80      // Bit MR71.
	EXTI_CPUIMR3_MR72_Pos = 0x8       // Position of MR72 field.
	EXTI_CPUIMR3_MR72_Msk = 0x100     // Bit mask of MR72 field.
	EXTI_CPUIMR3_MR72     = 0x100     // Bit MR72.
	EXTI_CPUIMR3_MR73_Pos = 0x9       // Position of MR73 field.
	EXTI_CPUIMR3_MR73_Msk = 0x200     // Bit mask of MR73 field.
	EXTI_CPUIMR3_MR73     = 0x200     // Bit MR73.
	EXTI_CPUIMR3_MR74_Pos = 0xa       // Position of MR74 field.
	EXTI_CPUIMR3_MR74_Msk = 0x400     // Bit mask of MR74 field.
	EXTI_CPUIMR3_MR74     = 0x400     // Bit MR74.
	EXTI_CPUIMR3_MR75_Pos = 0xb       // Position of MR75 field.
	EXTI_CPUIMR3_MR75_Msk = 0x800     // Bit mask of MR75 field.
	EXTI_CPUIMR3_MR75     = 0x800     // Bit MR75.
	EXTI_CPUIMR3_MR76_Pos = 0xc       // Position of MR76 field.
	EXTI_CPUIMR3_MR76_Msk = 0x1000    // Bit mask of MR76 field.
	EXTI_CPUIMR3_MR76     = 0x1000    // Bit MR76.
	EXTI_CPUIMR3_MR77_Pos = 0xd       // Position of MR77 field.
	EXTI_CPUIMR3_MR77_Msk = 0x2000    // Bit mask of MR77 field.
	EXTI_CPUIMR3_MR77     = 0x2000    // Bit MR77.
	EXTI_CPUIMR3_MR78_Pos = 0xe       // Position of MR78 field.
	EXTI_CPUIMR3_MR78_Msk = 0x4000    // Bit mask of MR78 field.
	EXTI_CPUIMR3_MR78     = 0x4000    // Bit MR78.
	EXTI_CPUIMR3_MR79_Pos = 0xf       // Position of MR79 field.
	EXTI_CPUIMR3_MR79_Msk = 0x8000    // Bit mask of MR79 field.
	EXTI_CPUIMR3_MR79     = 0x8000    // Bit MR79.
	EXTI_CPUIMR3_MR80_Pos = 0x10      // Position of MR80 field.
	EXTI_CPUIMR3_MR80_Msk = 0x10000   // Bit mask of MR80 field.
	EXTI_CPUIMR3_MR80     = 0x10000   // Bit MR80.
	EXTI_CPUIMR3_MR82_Pos = 0x12      // Position of MR82 field.
	EXTI_CPUIMR3_MR82_Msk = 0x40000   // Bit mask of MR82 field.
	EXTI_CPUIMR3_MR82     = 0x40000   // Bit MR82.
	EXTI_CPUIMR3_MR84_Pos = 0x14      // Position of MR84 field.
	EXTI_CPUIMR3_MR84_Msk = 0x100000  // Bit mask of MR84 field.
	EXTI_CPUIMR3_MR84     = 0x100000  // Bit MR84.
	EXTI_CPUIMR3_MR85_Pos = 0x15      // Position of MR85 field.
	EXTI_CPUIMR3_MR85_Msk = 0x200000  // Bit mask of MR85 field.
	EXTI_CPUIMR3_MR85     = 0x200000  // Bit MR85.
	EXTI_CPUIMR3_MR86_Pos = 0x16      // Position of MR86 field.
	EXTI_CPUIMR3_MR86_Msk = 0x400000  // Bit mask of MR86 field.
	EXTI_CPUIMR3_MR86     = 0x400000  // Bit MR86.
	EXTI_CPUIMR3_MR87_Pos = 0x17      // Position of MR87 field.
	EXTI_CPUIMR3_MR87_Msk = 0x800000  // Bit mask of MR87 field.
	EXTI_CPUIMR3_MR87     = 0x800000  // Bit MR87.
	EXTI_CPUIMR3_MR88_Pos = 0x18      // Position of MR88 field.
	EXTI_CPUIMR3_MR88_Msk = 0x1000000 // Bit mask of MR88 field.
	EXTI_CPUIMR3_MR88     = 0x1000000 // Bit MR88.

	// CPUEMR3: EXTI event mask register
	EXTI_CPUEMR3_MR64_Pos = 0x0       // Position of MR64 field.
	EXTI_CPUEMR3_MR64_Msk = 0x1       // Bit mask of MR64 field.
	EXTI_CPUEMR3_MR64     = 0x1       // Bit MR64.
	EXTI_CPUEMR3_MR65_Pos = 0x1       // Position of MR65 field.
	EXTI_CPUEMR3_MR65_Msk = 0x2       // Bit mask of MR65 field.
	EXTI_CPUEMR3_MR65     = 0x2       // Bit MR65.
	EXTI_CPUEMR3_MR66_Pos = 0x2       // Position of MR66 field.
	EXTI_CPUEMR3_MR66_Msk = 0x4       // Bit mask of MR66 field.
	EXTI_CPUEMR3_MR66     = 0x4       // Bit MR66.
	EXTI_CPUEMR3_MR67_Pos = 0x3       // Position of MR67 field.
	EXTI_CPUEMR3_MR67_Msk = 0x8       // Bit mask of MR67 field.
	EXTI_CPUEMR3_MR67     = 0x8       // Bit MR67.
	EXTI_CPUEMR3_MR68_Pos = 0x4       // Position of MR68 field.
	EXTI_CPUEMR3_MR68_Msk = 0x10      // Bit mask of MR68 field.
	EXTI_CPUEMR3_MR68     = 0x10      // Bit MR68.
	EXTI_CPUEMR3_MR69_Pos = 0x5       // Position of MR69 field.
	EXTI_CPUEMR3_MR69_Msk = 0x20      // Bit mask of MR69 field.
	EXTI_CPUEMR3_MR69     = 0x20      // Bit MR69.
	EXTI_CPUEMR3_MR70_Pos = 0x6       // Position of MR70 field.
	EXTI_CPUEMR3_MR70_Msk = 0x40      // Bit mask of MR70 field.
	EXTI_CPUEMR3_MR70     = 0x40      // Bit MR70.
	EXTI_CPUEMR3_MR71_Pos = 0x7       // Position of MR71 field.
	EXTI_CPUEMR3_MR71_Msk = 0x80      // Bit mask of MR71 field.
	EXTI_CPUEMR3_MR71     = 0x80      // Bit MR71.
	EXTI_CPUEMR3_MR72_Pos = 0x8       // Position of MR72 field.
	EXTI_CPUEMR3_MR72_Msk = 0x100     // Bit mask of MR72 field.
	EXTI_CPUEMR3_MR72     = 0x100     // Bit MR72.
	EXTI_CPUEMR3_MR73_Pos = 0x9       // Position of MR73 field.
	EXTI_CPUEMR3_MR73_Msk = 0x200     // Bit mask of MR73 field.
	EXTI_CPUEMR3_MR73     = 0x200     // Bit MR73.
	EXTI_CPUEMR3_MR74_Pos = 0xa       // Position of MR74 field.
	EXTI_CPUEMR3_MR74_Msk = 0x400     // Bit mask of MR74 field.
	EXTI_CPUEMR3_MR74     = 0x400     // Bit MR74.
	EXTI_CPUEMR3_MR75_Pos = 0xb       // Position of MR75 field.
	EXTI_CPUEMR3_MR75_Msk = 0x800     // Bit mask of MR75 field.
	EXTI_CPUEMR3_MR75     = 0x800     // Bit MR75.
	EXTI_CPUEMR3_MR76_Pos = 0xc       // Position of MR76 field.
	EXTI_CPUEMR3_MR76_Msk = 0x1000    // Bit mask of MR76 field.
	EXTI_CPUEMR3_MR76     = 0x1000    // Bit MR76.
	EXTI_CPUEMR3_MR77_Pos = 0xd       // Position of MR77 field.
	EXTI_CPUEMR3_MR77_Msk = 0x2000    // Bit mask of MR77 field.
	EXTI_CPUEMR3_MR77     = 0x2000    // Bit MR77.
	EXTI_CPUEMR3_MR78_Pos = 0xe       // Position of MR78 field.
	EXTI_CPUEMR3_MR78_Msk = 0x4000    // Bit mask of MR78 field.
	EXTI_CPUEMR3_MR78     = 0x4000    // Bit MR78.
	EXTI_CPUEMR3_MR79_Pos = 0xf       // Position of MR79 field.
	EXTI_CPUEMR3_MR79_Msk = 0x8000    // Bit mask of MR79 field.
	EXTI_CPUEMR3_MR79     = 0x8000    // Bit MR79.
	EXTI_CPUEMR3_MR80_Pos = 0x10      // Position of MR80 field.
	EXTI_CPUEMR3_MR80_Msk = 0x10000   // Bit mask of MR80 field.
	EXTI_CPUEMR3_MR80     = 0x10000   // Bit MR80.
	EXTI_CPUEMR3_MR82_Pos = 0x12      // Position of MR82 field.
	EXTI_CPUEMR3_MR82_Msk = 0x40000   // Bit mask of MR82 field.
	EXTI_CPUEMR3_MR82     = 0x40000   // Bit MR82.
	EXTI_CPUEMR3_MR84_Pos = 0x14      // Position of MR84 field.
	EXTI_CPUEMR3_MR84_Msk = 0x100000  // Bit mask of MR84 field.
	EXTI_CPUEMR3_MR84     = 0x100000  // Bit MR84.
	EXTI_CPUEMR3_MR85_Pos = 0x15      // Position of MR85 field.
	EXTI_CPUEMR3_MR85_Msk = 0x200000  // Bit mask of MR85 field.
	EXTI_CPUEMR3_MR85     = 0x200000  // Bit MR85.
	EXTI_CPUEMR3_MR86_Pos = 0x16      // Position of MR86 field.
	EXTI_CPUEMR3_MR86_Msk = 0x400000  // Bit mask of MR86 field.
	EXTI_CPUEMR3_MR86     = 0x400000  // Bit MR86.
	EXTI_CPUEMR3_MR87_Pos = 0x17      // Position of MR87 field.
	EXTI_CPUEMR3_MR87_Msk = 0x800000  // Bit mask of MR87 field.
	EXTI_CPUEMR3_MR87     = 0x800000  // Bit MR87.
	EXTI_CPUEMR3_MR88_Pos = 0x18      // Position of MR88 field.
	EXTI_CPUEMR3_MR88_Msk = 0x1000000 // Bit mask of MR88 field.
	EXTI_CPUEMR3_MR88     = 0x1000000 // Bit MR88.

	// CPUPR3: EXTI pending register
	EXTI_CPUPR3_PR82_Pos = 0x12     // Position of PR82 field.
	EXTI_CPUPR3_PR82_Msk = 0x40000  // Bit mask of PR82 field.
	EXTI_CPUPR3_PR82     = 0x40000  // Bit PR82.
	EXTI_CPUPR3_PR84_Pos = 0x14     // Position of PR84 field.
	EXTI_CPUPR3_PR84_Msk = 0x100000 // Bit mask of PR84 field.
	EXTI_CPUPR3_PR84     = 0x100000 // Bit PR84.
	EXTI_CPUPR3_PR85_Pos = 0x15     // Position of PR85 field.
	EXTI_CPUPR3_PR85_Msk = 0x200000 // Bit mask of PR85 field.
	EXTI_CPUPR3_PR85     = 0x200000 // Bit PR85.
	EXTI_CPUPR3_PR86_Pos = 0x16     // Position of PR86 field.
	EXTI_CPUPR3_PR86_Msk = 0x400000 // Bit mask of PR86 field.
	EXTI_CPUPR3_PR86     = 0x400000 // Bit PR86.
)

// Bitfields for DELAY_Block_SDMMC1: DELAY_Block_SDMMC1
const (
	// CR: DLYB control register
	DLYB_CR_DEN_Pos = 0x0 // Position of DEN field.
	DLYB_CR_DEN_Msk = 0x1 // Bit mask of DEN field.
	DLYB_CR_DEN     = 0x1 // Bit DEN.
	DLYB_CR_SEN_Pos = 0x1 // Position of SEN field.
	DLYB_CR_SEN_Msk = 0x2 // Bit mask of SEN field.
	DLYB_CR_SEN     = 0x2 // Bit SEN.

	// CFGR: DLYB configuration register
	DLYB_CFGR_SEL_Pos  = 0x0        // Position of SEL field.
	DLYB_CFGR_SEL_Msk  = 0xf        // Bit mask of SEL field.
	DLYB_CFGR_UNIT_Pos = 0x8        // Position of UNIT field.
	DLYB_CFGR_UNIT_Msk = 0x7f00     // Bit mask of UNIT field.
	DLYB_CFGR_LNG_Pos  = 0x10       // Position of LNG field.
	DLYB_CFGR_LNG_Msk  = 0xfff0000  // Bit mask of LNG field.
	DLYB_CFGR_LNGF_Pos = 0x1f       // Position of LNGF field.
	DLYB_CFGR_LNGF_Msk = 0x80000000 // Bit mask of LNGF field.
	DLYB_CFGR_LNGF     = 0x80000000 // Bit LNGF.
)

// Bitfields for Flash: Flash
const (
	// ACR: Access control register
	Flash_ACR_LATENCY_Pos    = 0x0  // Position of LATENCY field.
	Flash_ACR_LATENCY_Msk    = 0x7  // Bit mask of LATENCY field.
	Flash_ACR_WRHIGHFREQ_Pos = 0x4  // Position of WRHIGHFREQ field.
	Flash_ACR_WRHIGHFREQ_Msk = 0x30 // Bit mask of WRHIGHFREQ field.

	// KEYR1: FLASH key register for bank 1
	Flash_KEYR1_KEYR1_Pos = 0x0        // Position of KEYR1 field.
	Flash_KEYR1_KEYR1_Msk = 0xffffffff // Bit mask of KEYR1 field.

	// OPTKEYR: FLASH option key register
	Flash_OPTKEYR_OPTKEYR_Pos = 0x0        // Position of OPTKEYR field.
	Flash_OPTKEYR_OPTKEYR_Msk = 0xffffffff // Bit mask of OPTKEYR field.

	// CR1: FLASH control register for bank           1
	Flash_CR1_LOCK1_Pos       = 0x0       // Position of LOCK1 field.
	Flash_CR1_LOCK1_Msk       = 0x1       // Bit mask of LOCK1 field.
	Flash_CR1_LOCK1           = 0x1       // Bit LOCK1.
	Flash_CR1_PG1_Pos         = 0x1       // Position of PG1 field.
	Flash_CR1_PG1_Msk         = 0x2       // Bit mask of PG1 field.
	Flash_CR1_PG1             = 0x2       // Bit PG1.
	Flash_CR1_SER1_Pos        = 0x2       // Position of SER1 field.
	Flash_CR1_SER1_Msk        = 0x4       // Bit mask of SER1 field.
	Flash_CR1_SER1            = 0x4       // Bit SER1.
	Flash_CR1_BER1_Pos        = 0x3       // Position of BER1 field.
	Flash_CR1_BER1_Msk        = 0x8       // Bit mask of BER1 field.
	Flash_CR1_BER1            = 0x8       // Bit BER1.
	Flash_CR1_PSIZE1_Pos      = 0x4       // Position of PSIZE1 field.
	Flash_CR1_PSIZE1_Msk      = 0x30      // Bit mask of PSIZE1 field.
	Flash_CR1_FW1_Pos         = 0x6       // Position of FW1 field.
	Flash_CR1_FW1_Msk         = 0x40      // Bit mask of FW1 field.
	Flash_CR1_FW1             = 0x40      // Bit FW1.
	Flash_CR1_START1_Pos      = 0x7       // Position of START1 field.
	Flash_CR1_START1_Msk      = 0x80      // Bit mask of START1 field.
	Flash_CR1_START1          = 0x80      // Bit START1.
	Flash_CR1_SNB1_Pos        = 0x8       // Position of SNB1 field.
	Flash_CR1_SNB1_Msk        = 0x700     // Bit mask of SNB1 field.
	Flash_CR1_CRC_EN_Pos      = 0xf       // Position of CRC_EN field.
	Flash_CR1_CRC_EN_Msk      = 0x8000    // Bit mask of CRC_EN field.
	Flash_CR1_CRC_EN          = 0x8000    // Bit CRC_EN.
	Flash_CR1_EOPIE1_Pos      = 0x10      // Position of EOPIE1 field.
	Flash_CR1_EOPIE1_Msk      = 0x10000   // Bit mask of EOPIE1 field.
	Flash_CR1_EOPIE1          = 0x10000   // Bit EOPIE1.
	Flash_CR1_WRPERRIE1_Pos   = 0x11      // Position of WRPERRIE1 field.
	Flash_CR1_WRPERRIE1_Msk   = 0x20000   // Bit mask of WRPERRIE1 field.
	Flash_CR1_WRPERRIE1       = 0x20000   // Bit WRPERRIE1.
	Flash_CR1_PGSERRIE1_Pos   = 0x12      // Position of PGSERRIE1 field.
	Flash_CR1_PGSERRIE1_Msk   = 0x40000   // Bit mask of PGSERRIE1 field.
	Flash_CR1_PGSERRIE1       = 0x40000   // Bit PGSERRIE1.
	Flash_CR1_STRBERRIE1_Pos  = 0x13      // Position of STRBERRIE1 field.
	Flash_CR1_STRBERRIE1_Msk  = 0x80000   // Bit mask of STRBERRIE1 field.
	Flash_CR1_STRBERRIE1      = 0x80000   // Bit STRBERRIE1.
	Flash_CR1_INCERRIE1_Pos   = 0x15      // Position of INCERRIE1 field.
	Flash_CR1_INCERRIE1_Msk   = 0x200000  // Bit mask of INCERRIE1 field.
	Flash_CR1_INCERRIE1       = 0x200000  // Bit INCERRIE1.
	Flash_CR1_OPERRIE1_Pos    = 0x16      // Position of OPERRIE1 field.
	Flash_CR1_OPERRIE1_Msk    = 0x400000  // Bit mask of OPERRIE1 field.
	Flash_CR1_OPERRIE1        = 0x400000  // Bit OPERRIE1.
	Flash_CR1_RDPERRIE1_Pos   = 0x17      // Position of RDPERRIE1 field.
	Flash_CR1_RDPERRIE1_Msk   = 0x800000  // Bit mask of RDPERRIE1 field.
	Flash_CR1_RDPERRIE1       = 0x800000  // Bit RDPERRIE1.
	Flash_CR1_RDSERRIE1_Pos   = 0x18      // Position of RDSERRIE1 field.
	Flash_CR1_RDSERRIE1_Msk   = 0x1000000 // Bit mask of RDSERRIE1 field.
	Flash_CR1_RDSERRIE1       = 0x1000000 // Bit RDSERRIE1.
	Flash_CR1_SNECCERRIE1_Pos = 0x19      // Position of SNECCERRIE1 field.
	Flash_CR1_SNECCERRIE1_Msk = 0x2000000 // Bit mask of SNECCERRIE1 field.
	Flash_CR1_SNECCERRIE1     = 0x2000000 // Bit SNECCERRIE1.
	Flash_CR1_DBECCERRIE1_Pos = 0x1a      // Position of DBECCERRIE1 field.
	Flash_CR1_DBECCERRIE1_Msk = 0x4000000 // Bit mask of DBECCERRIE1 field.
	Flash_CR1_DBECCERRIE1     = 0x4000000 // Bit DBECCERRIE1.
	Flash_CR1_CRCENDIE1_Pos   = 0x1b      // Position of CRCENDIE1 field.
	Flash_CR1_CRCENDIE1_Msk   = 0x8000000 // Bit mask of CRCENDIE1 field.
	Flash_CR1_CRCENDIE1       = 0x8000000 // Bit CRCENDIE1.

	// SR1: FLASH status register for bank           1
	Flash_SR1_BSY1_Pos       = 0x0       // Position of BSY1 field.
	Flash_SR1_BSY1_Msk       = 0x1       // Bit mask of BSY1 field.
	Flash_SR1_BSY1           = 0x1       // Bit BSY1.
	Flash_SR1_WBNE1_Pos      = 0x1       // Position of WBNE1 field.
	Flash_SR1_WBNE1_Msk      = 0x2       // Bit mask of WBNE1 field.
	Flash_SR1_WBNE1          = 0x2       // Bit WBNE1.
	Flash_SR1_QW1_Pos        = 0x2       // Position of QW1 field.
	Flash_SR1_QW1_Msk        = 0x4       // Bit mask of QW1 field.
	Flash_SR1_QW1            = 0x4       // Bit QW1.
	Flash_SR1_CRC_BUSY1_Pos  = 0x3       // Position of CRC_BUSY1 field.
	Flash_SR1_CRC_BUSY1_Msk  = 0x8       // Bit mask of CRC_BUSY1 field.
	Flash_SR1_CRC_BUSY1      = 0x8       // Bit CRC_BUSY1.
	Flash_SR1_EOP1_Pos       = 0x10      // Position of EOP1 field.
	Flash_SR1_EOP1_Msk       = 0x10000   // Bit mask of EOP1 field.
	Flash_SR1_EOP1           = 0x10000   // Bit EOP1.
	Flash_SR1_WRPERR1_Pos    = 0x11      // Position of WRPERR1 field.
	Flash_SR1_WRPERR1_Msk    = 0x20000   // Bit mask of WRPERR1 field.
	Flash_SR1_WRPERR1        = 0x20000   // Bit WRPERR1.
	Flash_SR1_PGSERR1_Pos    = 0x12      // Position of PGSERR1 field.
	Flash_SR1_PGSERR1_Msk    = 0x40000   // Bit mask of PGSERR1 field.
	Flash_SR1_PGSERR1        = 0x40000   // Bit PGSERR1.
	Flash_SR1_STRBERR1_Pos   = 0x13      // Position of STRBERR1 field.
	Flash_SR1_STRBERR1_Msk   = 0x80000   // Bit mask of STRBERR1 field.
	Flash_SR1_STRBERR1       = 0x80000   // Bit STRBERR1.
	Flash_SR1_INCERR1_Pos    = 0x15      // Position of INCERR1 field.
	Flash_SR1_INCERR1_Msk    = 0x200000  // Bit mask of INCERR1 field.
	Flash_SR1_INCERR1        = 0x200000  // Bit INCERR1.
	Flash_SR1_OPERR1_Pos     = 0x16      // Position of OPERR1 field.
	Flash_SR1_OPERR1_Msk     = 0x400000  // Bit mask of OPERR1 field.
	Flash_SR1_OPERR1         = 0x400000  // Bit OPERR1.
	Flash_SR1_RDPERR1_Pos    = 0x17      // Position of RDPERR1 field.
	Flash_SR1_RDPERR1_Msk    = 0x800000  // Bit mask of RDPERR1 field.
	Flash_SR1_RDPERR1        = 0x800000  // Bit RDPERR1.
	Flash_SR1_RDSERR1_Pos    = 0x18      // Position of RDSERR1 field.
	Flash_SR1_RDSERR1_Msk    = 0x1000000 // Bit mask of RDSERR1 field.
	Flash_SR1_RDSERR1        = 0x1000000 // Bit RDSERR1.
	Flash_SR1_SNECCERR11_Pos = 0x19      // Position of SNECCERR11 field.
	Flash_SR1_SNECCERR11_Msk = 0x2000000 // Bit mask of SNECCERR11 field.
	Flash_SR1_SNECCERR11     = 0x2000000 // Bit SNECCERR11.
	Flash_SR1_DBECCERR1_Pos  = 0x1a      // Position of DBECCERR1 field.
	Flash_SR1_DBECCERR1_Msk  = 0x4000000 // Bit mask of DBECCERR1 field.
	Flash_SR1_DBECCERR1      = 0x4000000 // Bit DBECCERR1.
	Flash_SR1_CRCEND1_Pos    = 0x1b      // Position of CRCEND1 field.
	Flash_SR1_CRCEND1_Msk    = 0x8000000 // Bit mask of CRCEND1 field.
	Flash_SR1_CRCEND1        = 0x8000000 // Bit CRCEND1.

	// CCR1: FLASH clear control register for bank           1
	Flash_CCR1_CLR_EOP1_Pos      = 0x10      // Position of CLR_EOP1 field.
	Flash_CCR1_CLR_EOP1_Msk      = 0x10000   // Bit mask of CLR_EOP1 field.
	Flash_CCR1_CLR_EOP1          = 0x10000   // Bit CLR_EOP1.
	Flash_CCR1_CLR_WRPERR1_Pos   = 0x11      // Position of CLR_WRPERR1 field.
	Flash_CCR1_CLR_WRPERR1_Msk   = 0x20000   // Bit mask of CLR_WRPERR1 field.
	Flash_CCR1_CLR_WRPERR1       = 0x20000   // Bit CLR_WRPERR1.
	Flash_CCR1_CLR_PGSERR1_Pos   = 0x12      // Position of CLR_PGSERR1 field.
	Flash_CCR1_CLR_PGSERR1_Msk   = 0x40000   // Bit mask of CLR_PGSERR1 field.
	Flash_CCR1_CLR_PGSERR1       = 0x40000   // Bit CLR_PGSERR1.
	Flash_CCR1_CLR_STRBERR1_Pos  = 0x13      // Position of CLR_STRBERR1 field.
	Flash_CCR1_CLR_STRBERR1_Msk  = 0x80000   // Bit mask of CLR_STRBERR1 field.
	Flash_CCR1_CLR_STRBERR1      = 0x80000   // Bit CLR_STRBERR1.
	Flash_CCR1_CLR_INCERR1_Pos   = 0x15      // Position of CLR_INCERR1 field.
	Flash_CCR1_CLR_INCERR1_Msk   = 0x200000  // Bit mask of CLR_INCERR1 field.
	Flash_CCR1_CLR_INCERR1       = 0x200000  // Bit CLR_INCERR1.
	Flash_CCR1_CLR_OPERR1_Pos    = 0x16      // Position of CLR_OPERR1 field.
	Flash_CCR1_CLR_OPERR1_Msk    = 0x400000  // Bit mask of CLR_OPERR1 field.
	Flash_CCR1_CLR_OPERR1        = 0x400000  // Bit CLR_OPERR1.
	Flash_CCR1_CLR_RDPERR1_Pos   = 0x17      // Position of CLR_RDPERR1 field.
	Flash_CCR1_CLR_RDPERR1_Msk   = 0x800000  // Bit mask of CLR_RDPERR1 field.
	Flash_CCR1_CLR_RDPERR1       = 0x800000  // Bit CLR_RDPERR1.
	Flash_CCR1_CLR_RDSERR1_Pos   = 0x18      // Position of CLR_RDSERR1 field.
	Flash_CCR1_CLR_RDSERR1_Msk   = 0x1000000 // Bit mask of CLR_RDSERR1 field.
	Flash_CCR1_CLR_RDSERR1       = 0x1000000 // Bit CLR_RDSERR1.
	Flash_CCR1_CLR_SNECCERR1_Pos = 0x19      // Position of CLR_SNECCERR1 field.
	Flash_CCR1_CLR_SNECCERR1_Msk = 0x2000000 // Bit mask of CLR_SNECCERR1 field.
	Flash_CCR1_CLR_SNECCERR1     = 0x2000000 // Bit CLR_SNECCERR1.
	Flash_CCR1_CLR_DBECCERR1_Pos = 0x1a      // Position of CLR_DBECCERR1 field.
	Flash_CCR1_CLR_DBECCERR1_Msk = 0x4000000 // Bit mask of CLR_DBECCERR1 field.
	Flash_CCR1_CLR_DBECCERR1     = 0x4000000 // Bit CLR_DBECCERR1.
	Flash_CCR1_CLR_CRCEND1_Pos   = 0x1b      // Position of CLR_CRCEND1 field.
	Flash_CCR1_CLR_CRCEND1_Msk   = 0x8000000 // Bit mask of CLR_CRCEND1 field.
	Flash_CCR1_CLR_CRCEND1       = 0x8000000 // Bit CLR_CRCEND1.

	// OPTCR: FLASH option control register
	Flash_OPTCR_OPTLOCK_Pos        = 0x0        // Position of OPTLOCK field.
	Flash_OPTCR_OPTLOCK_Msk        = 0x1        // Bit mask of OPTLOCK field.
	Flash_OPTCR_OPTLOCK            = 0x1        // Bit OPTLOCK.
	Flash_OPTCR_OPTSTART_Pos       = 0x1        // Position of OPTSTART field.
	Flash_OPTCR_OPTSTART_Msk       = 0x2        // Bit mask of OPTSTART field.
	Flash_OPTCR_OPTSTART           = 0x2        // Bit OPTSTART.
	Flash_OPTCR_MER_Pos            = 0x4        // Position of MER field.
	Flash_OPTCR_MER_Msk            = 0x10       // Bit mask of MER field.
	Flash_OPTCR_MER                = 0x10       // Bit MER.
	Flash_OPTCR_OPTCHANGEERRIE_Pos = 0x1e       // Position of OPTCHANGEERRIE field.
	Flash_OPTCR_OPTCHANGEERRIE_Msk = 0x40000000 // Bit mask of OPTCHANGEERRIE field.
	Flash_OPTCR_OPTCHANGEERRIE     = 0x40000000 // Bit OPTCHANGEERRIE.
	Flash_OPTCR_SWAP_BANK_Pos      = 0x1f       // Position of SWAP_BANK field.
	Flash_OPTCR_SWAP_BANK_Msk      = 0x80000000 // Bit mask of SWAP_BANK field.
	Flash_OPTCR_SWAP_BANK          = 0x80000000 // Bit SWAP_BANK.

	// OPTSR_CUR: FLASH option status register
	Flash_OPTSR_CUR_OPT_BUSY_Pos      = 0x0        // Position of OPT_BUSY field.
	Flash_OPTSR_CUR_OPT_BUSY_Msk      = 0x1        // Bit mask of OPT_BUSY field.
	Flash_OPTSR_CUR_OPT_BUSY          = 0x1        // Bit OPT_BUSY.
	Flash_OPTSR_CUR_BOR_LEV_Pos       = 0x2        // Position of BOR_LEV field.
	Flash_OPTSR_CUR_BOR_LEV_Msk       = 0xc        // Bit mask of BOR_LEV field.
	Flash_OPTSR_CUR_IWDG1_HW_Pos      = 0x4        // Position of IWDG1_HW field.
	Flash_OPTSR_CUR_IWDG1_HW_Msk      = 0x10       // Bit mask of IWDG1_HW field.
	Flash_OPTSR_CUR_IWDG1_HW          = 0x10       // Bit IWDG1_HW.
	Flash_OPTSR_CUR_NRST_STOP_D1_Pos  = 0x6        // Position of NRST_STOP_D1 field.
	Flash_OPTSR_CUR_NRST_STOP_D1_Msk  = 0x40       // Bit mask of NRST_STOP_D1 field.
	Flash_OPTSR_CUR_NRST_STOP_D1      = 0x40       // Bit NRST_STOP_D1.
	Flash_OPTSR_CUR_NRST_STBY_D1_Pos  = 0x7        // Position of NRST_STBY_D1 field.
	Flash_OPTSR_CUR_NRST_STBY_D1_Msk  = 0x80       // Bit mask of NRST_STBY_D1 field.
	Flash_OPTSR_CUR_NRST_STBY_D1      = 0x80       // Bit NRST_STBY_D1.
	Flash_OPTSR_CUR_RDP_Pos           = 0x8        // Position of RDP field.
	Flash_OPTSR_CUR_RDP_Msk           = 0xff00     // Bit mask of RDP field.
	Flash_OPTSR_CUR_FZ_IWDG_STOP_Pos  = 0x11       // Position of FZ_IWDG_STOP field.
	Flash_OPTSR_CUR_FZ_IWDG_STOP_Msk  = 0x20000    // Bit mask of FZ_IWDG_STOP field.
	Flash_OPTSR_CUR_FZ_IWDG_STOP      = 0x20000    // Bit FZ_IWDG_STOP.
	Flash_OPTSR_CUR_FZ_IWDG_SDBY_Pos  = 0x12       // Position of FZ_IWDG_SDBY field.
	Flash_OPTSR_CUR_FZ_IWDG_SDBY_Msk  = 0x40000    // Bit mask of FZ_IWDG_SDBY field.
	Flash_OPTSR_CUR_FZ_IWDG_SDBY      = 0x40000    // Bit FZ_IWDG_SDBY.
	Flash_OPTSR_CUR_ST_RAM_SIZE_Pos   = 0x13       // Position of ST_RAM_SIZE field.
	Flash_OPTSR_CUR_ST_RAM_SIZE_Msk   = 0x180000   // Bit mask of ST_RAM_SIZE field.
	Flash_OPTSR_CUR_SECURITY_Pos      = 0x15       // Position of SECURITY field.
	Flash_OPTSR_CUR_SECURITY_Msk      = 0x200000   // Bit mask of SECURITY field.
	Flash_OPTSR_CUR_SECURITY          = 0x200000   // Bit SECURITY.
	Flash_OPTSR_CUR_RSS1_Pos          = 0x1a       // Position of RSS1 field.
	Flash_OPTSR_CUR_RSS1_Msk          = 0x4000000  // Bit mask of RSS1 field.
	Flash_OPTSR_CUR_RSS1              = 0x4000000  // Bit RSS1.
	Flash_OPTSR_CUR_PERSO_OK_Pos      = 0x1c       // Position of PERSO_OK field.
	Flash_OPTSR_CUR_PERSO_OK_Msk      = 0x10000000 // Bit mask of PERSO_OK field.
	Flash_OPTSR_CUR_PERSO_OK          = 0x10000000 // Bit PERSO_OK.
	Flash_OPTSR_CUR_IO_HSLV_Pos       = 0x1d       // Position of IO_HSLV field.
	Flash_OPTSR_CUR_IO_HSLV_Msk       = 0x20000000 // Bit mask of IO_HSLV field.
	Flash_OPTSR_CUR_IO_HSLV           = 0x20000000 // Bit IO_HSLV.
	Flash_OPTSR_CUR_OPTCHANGEERR_Pos  = 0x1e       // Position of OPTCHANGEERR field.
	Flash_OPTSR_CUR_OPTCHANGEERR_Msk  = 0x40000000 // Bit mask of OPTCHANGEERR field.
	Flash_OPTSR_CUR_OPTCHANGEERR      = 0x40000000 // Bit OPTCHANGEERR.
	Flash_OPTSR_CUR_SWAP_BANK_OPT_Pos = 0x1f       // Position of SWAP_BANK_OPT field.
	Flash_OPTSR_CUR_SWAP_BANK_OPT_Msk = 0x80000000 // Bit mask of SWAP_BANK_OPT field.
	Flash_OPTSR_CUR_SWAP_BANK_OPT     = 0x80000000 // Bit SWAP_BANK_OPT.

	// OPTSR_PRG: FLASH option status register
	Flash_OPTSR_PRG_BOR_LEV_Pos       = 0x2        // Position of BOR_LEV field.
	Flash_OPTSR_PRG_BOR_LEV_Msk       = 0xc        // Bit mask of BOR_LEV field.
	Flash_OPTSR_PRG_IWDG1_HW_Pos      = 0x4        // Position of IWDG1_HW field.
	Flash_OPTSR_PRG_IWDG1_HW_Msk      = 0x10       // Bit mask of IWDG1_HW field.
	Flash_OPTSR_PRG_IWDG1_HW          = 0x10       // Bit IWDG1_HW.
	Flash_OPTSR_PRG_NRST_STOP_D1_Pos  = 0x6        // Position of NRST_STOP_D1 field.
	Flash_OPTSR_PRG_NRST_STOP_D1_Msk  = 0x40       // Bit mask of NRST_STOP_D1 field.
	Flash_OPTSR_PRG_NRST_STOP_D1      = 0x40       // Bit NRST_STOP_D1.
	Flash_OPTSR_PRG_NRST_STBY_D1_Pos  = 0x7        // Position of NRST_STBY_D1 field.
	Flash_OPTSR_PRG_NRST_STBY_D1_Msk  = 0x80       // Bit mask of NRST_STBY_D1 field.
	Flash_OPTSR_PRG_NRST_STBY_D1      = 0x80       // Bit NRST_STBY_D1.
	Flash_OPTSR_PRG_RDP_Pos           = 0x8        // Position of RDP field.
	Flash_OPTSR_PRG_RDP_Msk           = 0xff00     // Bit mask of RDP field.
	Flash_OPTSR_PRG_FZ_IWDG_STOP_Pos  = 0x11       // Position of FZ_IWDG_STOP field.
	Flash_OPTSR_PRG_FZ_IWDG_STOP_Msk  = 0x20000    // Bit mask of FZ_IWDG_STOP field.
	Flash_OPTSR_PRG_FZ_IWDG_STOP      = 0x20000    // Bit FZ_IWDG_STOP.
	Flash_OPTSR_PRG_FZ_IWDG_SDBY_Pos  = 0x12       // Position of FZ_IWDG_SDBY field.
	Flash_OPTSR_PRG_FZ_IWDG_SDBY_Msk  = 0x40000    // Bit mask of FZ_IWDG_SDBY field.
	Flash_OPTSR_PRG_FZ_IWDG_SDBY      = 0x40000    // Bit FZ_IWDG_SDBY.
	Flash_OPTSR_PRG_ST_RAM_SIZE_Pos   = 0x13       // Position of ST_RAM_SIZE field.
	Flash_OPTSR_PRG_ST_RAM_SIZE_Msk   = 0x180000   // Bit mask of ST_RAM_SIZE field.
	Flash_OPTSR_PRG_SECURITY_Pos      = 0x15       // Position of SECURITY field.
	Flash_OPTSR_PRG_SECURITY_Msk      = 0x200000   // Bit mask of SECURITY field.
	Flash_OPTSR_PRG_SECURITY          = 0x200000   // Bit SECURITY.
	Flash_OPTSR_PRG_RSS1_Pos          = 0x1a       // Position of RSS1 field.
	Flash_OPTSR_PRG_RSS1_Msk          = 0x4000000  // Bit mask of RSS1 field.
	Flash_OPTSR_PRG_RSS1              = 0x4000000  // Bit RSS1.
	Flash_OPTSR_PRG_RSS2_Pos          = 0x1b       // Position of RSS2 field.
	Flash_OPTSR_PRG_RSS2_Msk          = 0x8000000  // Bit mask of RSS2 field.
	Flash_OPTSR_PRG_RSS2              = 0x8000000  // Bit RSS2.
	Flash_OPTSR_PRG_IO_HSLV_Pos       = 0x1d       // Position of IO_HSLV field.
	Flash_OPTSR_PRG_IO_HSLV_Msk       = 0x20000000 // Bit mask of IO_HSLV field.
	Flash_OPTSR_PRG_IO_HSLV           = 0x20000000 // Bit IO_HSLV.
	Flash_OPTSR_PRG_SWAP_BANK_OPT_Pos = 0x1f       // Position of SWAP_BANK_OPT field.
	Flash_OPTSR_PRG_SWAP_BANK_OPT_Msk = 0x80000000 // Bit mask of SWAP_BANK_OPT field.
	Flash_OPTSR_PRG_SWAP_BANK_OPT     = 0x80000000 // Bit SWAP_BANK_OPT.

	// OPTCCR: FLASH option clear control           register
	Flash_OPTCCR_CLR_OPTCHANGEERR_Pos = 0x1e       // Position of CLR_OPTCHANGEERR field.
	Flash_OPTCCR_CLR_OPTCHANGEERR_Msk = 0x40000000 // Bit mask of CLR_OPTCHANGEERR field.
	Flash_OPTCCR_CLR_OPTCHANGEERR     = 0x40000000 // Bit CLR_OPTCHANGEERR.

	// PRAR_CUR1: FLASH protection address for bank           1
	Flash_PRAR_CUR1_PROT_AREA_START1_Pos = 0x0        // Position of PROT_AREA_START1 field.
	Flash_PRAR_CUR1_PROT_AREA_START1_Msk = 0xfff      // Bit mask of PROT_AREA_START1 field.
	Flash_PRAR_CUR1_PROT_AREA_END1_Pos   = 0x10       // Position of PROT_AREA_END1 field.
	Flash_PRAR_CUR1_PROT_AREA_END1_Msk   = 0xfff0000  // Bit mask of PROT_AREA_END1 field.
	Flash_PRAR_CUR1_DMEP1_Pos            = 0x1f       // Position of DMEP1 field.
	Flash_PRAR_CUR1_DMEP1_Msk            = 0x80000000 // Bit mask of DMEP1 field.
	Flash_PRAR_CUR1_DMEP1                = 0x80000000 // Bit DMEP1.

	// PRAR_PRG1: FLASH protection address for bank           1
	Flash_PRAR_PRG1_PROT_AREA_START1_Pos = 0x0        // Position of PROT_AREA_START1 field.
	Flash_PRAR_PRG1_PROT_AREA_START1_Msk = 0xfff      // Bit mask of PROT_AREA_START1 field.
	Flash_PRAR_PRG1_PROT_AREA_END1_Pos   = 0x10       // Position of PROT_AREA_END1 field.
	Flash_PRAR_PRG1_PROT_AREA_END1_Msk   = 0xfff0000  // Bit mask of PROT_AREA_END1 field.
	Flash_PRAR_PRG1_DMEP1_Pos            = 0x1f       // Position of DMEP1 field.
	Flash_PRAR_PRG1_DMEP1_Msk            = 0x80000000 // Bit mask of DMEP1 field.
	Flash_PRAR_PRG1_DMEP1                = 0x80000000 // Bit DMEP1.

	// PRAR_PRG2: FLASH protection address for bank           2
	Flash_PRAR_PRG2_PROT_AREA_START2_Pos = 0x0        // Position of PROT_AREA_START2 field.
	Flash_PRAR_PRG2_PROT_AREA_START2_Msk = 0xfff      // Bit mask of PROT_AREA_START2 field.
	Flash_PRAR_PRG2_PROT_AREA_END2_Pos   = 0x10       // Position of PROT_AREA_END2 field.
	Flash_PRAR_PRG2_PROT_AREA_END2_Msk   = 0xfff0000  // Bit mask of PROT_AREA_END2 field.
	Flash_PRAR_PRG2_DMEP2_Pos            = 0x1f       // Position of DMEP2 field.
	Flash_PRAR_PRG2_DMEP2_Msk            = 0x80000000 // Bit mask of DMEP2 field.
	Flash_PRAR_PRG2_DMEP2                = 0x80000000 // Bit DMEP2.

	// SCAR_CUR1: FLASH secure address for bank           1
	Flash_SCAR_CUR1_SEC_AREA_START1_Pos = 0x0        // Position of SEC_AREA_START1 field.
	Flash_SCAR_CUR1_SEC_AREA_START1_Msk = 0xfff      // Bit mask of SEC_AREA_START1 field.
	Flash_SCAR_CUR1_SEC_AREA_END1_Pos   = 0x10       // Position of SEC_AREA_END1 field.
	Flash_SCAR_CUR1_SEC_AREA_END1_Msk   = 0xfff0000  // Bit mask of SEC_AREA_END1 field.
	Flash_SCAR_CUR1_DMES1_Pos           = 0x1f       // Position of DMES1 field.
	Flash_SCAR_CUR1_DMES1_Msk           = 0x80000000 // Bit mask of DMES1 field.
	Flash_SCAR_CUR1_DMES1               = 0x80000000 // Bit DMES1.

	// SCAR_PRG1: FLASH secure address for bank           1
	Flash_SCAR_PRG1_SEC_AREA_START1_Pos = 0x0        // Position of SEC_AREA_START1 field.
	Flash_SCAR_PRG1_SEC_AREA_START1_Msk = 0xfff      // Bit mask of SEC_AREA_START1 field.
	Flash_SCAR_PRG1_SEC_AREA_END1_Pos   = 0x10       // Position of SEC_AREA_END1 field.
	Flash_SCAR_PRG1_SEC_AREA_END1_Msk   = 0xfff0000  // Bit mask of SEC_AREA_END1 field.
	Flash_SCAR_PRG1_DMES1_Pos           = 0x1f       // Position of DMES1 field.
	Flash_SCAR_PRG1_DMES1_Msk           = 0x80000000 // Bit mask of DMES1 field.
	Flash_SCAR_PRG1_DMES1               = 0x80000000 // Bit DMES1.

	// WPSN_CUR1R: FLASH write sector protection for bank           1
	Flash_WPSN_CUR1R_WRPSn1_Pos = 0x0  // Position of WRPSn1 field.
	Flash_WPSN_CUR1R_WRPSn1_Msk = 0xff // Bit mask of WRPSn1 field.

	// WPSN_PRG1R: FLASH write sector protection for bank           1
	Flash_WPSN_PRG1R_WRPSn1_Pos = 0x0  // Position of WRPSn1 field.
	Flash_WPSN_PRG1R_WRPSn1_Msk = 0xff // Bit mask of WRPSn1 field.

	// BOOT_CURR: FLASH register with boot           address
	Flash_BOOT_CURR_BOOT_ADD0_Pos = 0x0        // Position of BOOT_ADD0 field.
	Flash_BOOT_CURR_BOOT_ADD0_Msk = 0xffff     // Bit mask of BOOT_ADD0 field.
	Flash_BOOT_CURR_BOOT_ADD1_Pos = 0x10       // Position of BOOT_ADD1 field.
	Flash_BOOT_CURR_BOOT_ADD1_Msk = 0xffff0000 // Bit mask of BOOT_ADD1 field.

	// BOOT_PRGR: FLASH register with boot           address
	Flash_BOOT_PRGR_BOOT_ADD0_Pos = 0x0        // Position of BOOT_ADD0 field.
	Flash_BOOT_PRGR_BOOT_ADD0_Msk = 0xffff     // Bit mask of BOOT_ADD0 field.
	Flash_BOOT_PRGR_BOOT_ADD1_Pos = 0x10       // Position of BOOT_ADD1 field.
	Flash_BOOT_PRGR_BOOT_ADD1_Msk = 0xffff0000 // Bit mask of BOOT_ADD1 field.

	// CRCCR1: FLASH CRC control register for bank           1
	Flash_CRCCR1_CRC_SECT_Pos    = 0x0      // Position of CRC_SECT field.
	Flash_CRCCR1_CRC_SECT_Msk    = 0x7      // Bit mask of CRC_SECT field.
	Flash_CRCCR1_ALL_BANK_Pos    = 0x7      // Position of ALL_BANK field.
	Flash_CRCCR1_ALL_BANK_Msk    = 0x80     // Bit mask of ALL_BANK field.
	Flash_CRCCR1_ALL_BANK        = 0x80     // Bit ALL_BANK.
	Flash_CRCCR1_CRC_BY_SECT_Pos = 0x8      // Position of CRC_BY_SECT field.
	Flash_CRCCR1_CRC_BY_SECT_Msk = 0x100    // Bit mask of CRC_BY_SECT field.
	Flash_CRCCR1_CRC_BY_SECT     = 0x100    // Bit CRC_BY_SECT.
	Flash_CRCCR1_ADD_SECT_Pos    = 0x9      // Position of ADD_SECT field.
	Flash_CRCCR1_ADD_SECT_Msk    = 0x200    // Bit mask of ADD_SECT field.
	Flash_CRCCR1_ADD_SECT        = 0x200    // Bit ADD_SECT.
	Flash_CRCCR1_CLEAN_SECT_Pos  = 0xa      // Position of CLEAN_SECT field.
	Flash_CRCCR1_CLEAN_SECT_Msk  = 0x400    // Bit mask of CLEAN_SECT field.
	Flash_CRCCR1_CLEAN_SECT      = 0x400    // Bit CLEAN_SECT.
	Flash_CRCCR1_START_CRC_Pos   = 0x10     // Position of START_CRC field.
	Flash_CRCCR1_START_CRC_Msk   = 0x10000  // Bit mask of START_CRC field.
	Flash_CRCCR1_START_CRC       = 0x10000  // Bit START_CRC.
	Flash_CRCCR1_CLEAN_CRC_Pos   = 0x11     // Position of CLEAN_CRC field.
	Flash_CRCCR1_CLEAN_CRC_Msk   = 0x20000  // Bit mask of CLEAN_CRC field.
	Flash_CRCCR1_CLEAN_CRC       = 0x20000  // Bit CLEAN_CRC.
	Flash_CRCCR1_CRC_BURST_Pos   = 0x14     // Position of CRC_BURST field.
	Flash_CRCCR1_CRC_BURST_Msk   = 0x300000 // Bit mask of CRC_BURST field.

	// CRCSADD1R: FLASH CRC start address register for bank           1
	Flash_CRCSADD1R_CRC_START_ADDR_Pos = 0x0        // Position of CRC_START_ADDR field.
	Flash_CRCSADD1R_CRC_START_ADDR_Msk = 0xffffffff // Bit mask of CRC_START_ADDR field.

	// CRCEADD1R: FLASH CRC end address register for bank           1
	Flash_CRCEADD1R_CRC_END_ADDR_Pos = 0x0        // Position of CRC_END_ADDR field.
	Flash_CRCEADD1R_CRC_END_ADDR_Msk = 0xffffffff // Bit mask of CRC_END_ADDR field.

	// CRCDATAR: FLASH CRC data register
	Flash_CRCDATAR_CRC_DATA_Pos = 0x0        // Position of CRC_DATA field.
	Flash_CRCDATAR_CRC_DATA_Msk = 0xffffffff // Bit mask of CRC_DATA field.

	// ECC_FA1R: FLASH ECC fail address for bank           1
	Flash_ECC_FA1R_FAIL_ECC_ADDR1_Pos = 0x0    // Position of FAIL_ECC_ADDR1 field.
	Flash_ECC_FA1R_FAIL_ECC_ADDR1_Msk = 0x7fff // Bit mask of FAIL_ECC_ADDR1 field.

	// ACR_: Access control register
	Flash_ACR__LATENCY_Pos    = 0x0  // Position of LATENCY field.
	Flash_ACR__LATENCY_Msk    = 0x7  // Bit mask of LATENCY field.
	Flash_ACR__WRHIGHFREQ_Pos = 0x4  // Position of WRHIGHFREQ field.
	Flash_ACR__WRHIGHFREQ_Msk = 0x30 // Bit mask of WRHIGHFREQ field.

	// KEYR2: FLASH key register for bank 2
	Flash_KEYR2_KEYR2_Pos = 0x0        // Position of KEYR2 field.
	Flash_KEYR2_KEYR2_Msk = 0xffffffff // Bit mask of KEYR2 field.

	// OPTKEYR_: FLASH option key register
	Flash_OPTKEYR__OPTKEYR_Pos = 0x0        // Position of OPTKEYR field.
	Flash_OPTKEYR__OPTKEYR_Msk = 0xffffffff // Bit mask of OPTKEYR field.

	// CR2: FLASH control register for bank           2
	Flash_CR2_LOCK2_Pos       = 0x0       // Position of LOCK2 field.
	Flash_CR2_LOCK2_Msk       = 0x1       // Bit mask of LOCK2 field.
	Flash_CR2_LOCK2           = 0x1       // Bit LOCK2.
	Flash_CR2_PG2_Pos         = 0x1       // Position of PG2 field.
	Flash_CR2_PG2_Msk         = 0x2       // Bit mask of PG2 field.
	Flash_CR2_PG2             = 0x2       // Bit PG2.
	Flash_CR2_SER2_Pos        = 0x2       // Position of SER2 field.
	Flash_CR2_SER2_Msk        = 0x4       // Bit mask of SER2 field.
	Flash_CR2_SER2            = 0x4       // Bit SER2.
	Flash_CR2_BER2_Pos        = 0x3       // Position of BER2 field.
	Flash_CR2_BER2_Msk        = 0x8       // Bit mask of BER2 field.
	Flash_CR2_BER2            = 0x8       // Bit BER2.
	Flash_CR2_PSIZE2_Pos      = 0x4       // Position of PSIZE2 field.
	Flash_CR2_PSIZE2_Msk      = 0x30      // Bit mask of PSIZE2 field.
	Flash_CR2_FW2_Pos         = 0x6       // Position of FW2 field.
	Flash_CR2_FW2_Msk         = 0x40      // Bit mask of FW2 field.
	Flash_CR2_FW2             = 0x40      // Bit FW2.
	Flash_CR2_START2_Pos      = 0x7       // Position of START2 field.
	Flash_CR2_START2_Msk      = 0x80      // Bit mask of START2 field.
	Flash_CR2_START2          = 0x80      // Bit START2.
	Flash_CR2_SNB2_Pos        = 0x8       // Position of SNB2 field.
	Flash_CR2_SNB2_Msk        = 0x700     // Bit mask of SNB2 field.
	Flash_CR2_CRC_EN_Pos      = 0xf       // Position of CRC_EN field.
	Flash_CR2_CRC_EN_Msk      = 0x8000    // Bit mask of CRC_EN field.
	Flash_CR2_CRC_EN          = 0x8000    // Bit CRC_EN.
	Flash_CR2_EOPIE2_Pos      = 0x10      // Position of EOPIE2 field.
	Flash_CR2_EOPIE2_Msk      = 0x10000   // Bit mask of EOPIE2 field.
	Flash_CR2_EOPIE2          = 0x10000   // Bit EOPIE2.
	Flash_CR2_WRPERRIE2_Pos   = 0x11      // Position of WRPERRIE2 field.
	Flash_CR2_WRPERRIE2_Msk   = 0x20000   // Bit mask of WRPERRIE2 field.
	Flash_CR2_WRPERRIE2       = 0x20000   // Bit WRPERRIE2.
	Flash_CR2_PGSERRIE2_Pos   = 0x12      // Position of PGSERRIE2 field.
	Flash_CR2_PGSERRIE2_Msk   = 0x40000   // Bit mask of PGSERRIE2 field.
	Flash_CR2_PGSERRIE2       = 0x40000   // Bit PGSERRIE2.
	Flash_CR2_STRBERRIE2_Pos  = 0x13      // Position of STRBERRIE2 field.
	Flash_CR2_STRBERRIE2_Msk  = 0x80000   // Bit mask of STRBERRIE2 field.
	Flash_CR2_STRBERRIE2      = 0x80000   // Bit STRBERRIE2.
	Flash_CR2_INCERRIE2_Pos   = 0x15      // Position of INCERRIE2 field.
	Flash_CR2_INCERRIE2_Msk   = 0x200000  // Bit mask of INCERRIE2 field.
	Flash_CR2_INCERRIE2       = 0x200000  // Bit INCERRIE2.
	Flash_CR2_OPERRIE2_Pos    = 0x16      // Position of OPERRIE2 field.
	Flash_CR2_OPERRIE2_Msk    = 0x400000  // Bit mask of OPERRIE2 field.
	Flash_CR2_OPERRIE2        = 0x400000  // Bit OPERRIE2.
	Flash_CR2_RDPERRIE2_Pos   = 0x17      // Position of RDPERRIE2 field.
	Flash_CR2_RDPERRIE2_Msk   = 0x800000  // Bit mask of RDPERRIE2 field.
	Flash_CR2_RDPERRIE2       = 0x800000  // Bit RDPERRIE2.
	Flash_CR2_RDSERRIE2_Pos   = 0x18      // Position of RDSERRIE2 field.
	Flash_CR2_RDSERRIE2_Msk   = 0x1000000 // Bit mask of RDSERRIE2 field.
	Flash_CR2_RDSERRIE2       = 0x1000000 // Bit RDSERRIE2.
	Flash_CR2_SNECCERRIE2_Pos = 0x19      // Position of SNECCERRIE2 field.
	Flash_CR2_SNECCERRIE2_Msk = 0x2000000 // Bit mask of SNECCERRIE2 field.
	Flash_CR2_SNECCERRIE2     = 0x2000000 // Bit SNECCERRIE2.
	Flash_CR2_DBECCERRIE2_Pos = 0x1a      // Position of DBECCERRIE2 field.
	Flash_CR2_DBECCERRIE2_Msk = 0x4000000 // Bit mask of DBECCERRIE2 field.
	Flash_CR2_DBECCERRIE2     = 0x4000000 // Bit DBECCERRIE2.
	Flash_CR2_CRCENDIE2_Pos   = 0x1b      // Position of CRCENDIE2 field.
	Flash_CR2_CRCENDIE2_Msk   = 0x8000000 // Bit mask of CRCENDIE2 field.
	Flash_CR2_CRCENDIE2       = 0x8000000 // Bit CRCENDIE2.

	// SR2: FLASH status register for bank           2
	Flash_SR2_BSY2_Pos      = 0x0       // Position of BSY2 field.
	Flash_SR2_BSY2_Msk      = 0x1       // Bit mask of BSY2 field.
	Flash_SR2_BSY2          = 0x1       // Bit BSY2.
	Flash_SR2_WBNE2_Pos     = 0x1       // Position of WBNE2 field.
	Flash_SR2_WBNE2_Msk     = 0x2       // Bit mask of WBNE2 field.
	Flash_SR2_WBNE2         = 0x2       // Bit WBNE2.
	Flash_SR2_QW2_Pos       = 0x2       // Position of QW2 field.
	Flash_SR2_QW2_Msk       = 0x4       // Bit mask of QW2 field.
	Flash_SR2_QW2           = 0x4       // Bit QW2.
	Flash_SR2_CRC_BUSY2_Pos = 0x3       // Position of CRC_BUSY2 field.
	Flash_SR2_CRC_BUSY2_Msk = 0x8       // Bit mask of CRC_BUSY2 field.
	Flash_SR2_CRC_BUSY2     = 0x8       // Bit CRC_BUSY2.
	Flash_SR2_EOP2_Pos      = 0x10      // Position of EOP2 field.
	Flash_SR2_EOP2_Msk      = 0x10000   // Bit mask of EOP2 field.
	Flash_SR2_EOP2          = 0x10000   // Bit EOP2.
	Flash_SR2_WRPERR2_Pos   = 0x11      // Position of WRPERR2 field.
	Flash_SR2_WRPERR2_Msk   = 0x20000   // Bit mask of WRPERR2 field.
	Flash_SR2_WRPERR2       = 0x20000   // Bit WRPERR2.
	Flash_SR2_PGSERR2_Pos   = 0x12      // Position of PGSERR2 field.
	Flash_SR2_PGSERR2_Msk   = 0x40000   // Bit mask of PGSERR2 field.
	Flash_SR2_PGSERR2       = 0x40000   // Bit PGSERR2.
	Flash_SR2_STRBERR2_Pos  = 0x13      // Position of STRBERR2 field.
	Flash_SR2_STRBERR2_Msk  = 0x80000   // Bit mask of STRBERR2 field.
	Flash_SR2_STRBERR2      = 0x80000   // Bit STRBERR2.
	Flash_SR2_INCERR2_Pos   = 0x15      // Position of INCERR2 field.
	Flash_SR2_INCERR2_Msk   = 0x200000  // Bit mask of INCERR2 field.
	Flash_SR2_INCERR2       = 0x200000  // Bit INCERR2.
	Flash_SR2_OPERR2_Pos    = 0x16      // Position of OPERR2 field.
	Flash_SR2_OPERR2_Msk    = 0x400000  // Bit mask of OPERR2 field.
	Flash_SR2_OPERR2        = 0x400000  // Bit OPERR2.
	Flash_SR2_RDPERR2_Pos   = 0x17      // Position of RDPERR2 field.
	Flash_SR2_RDPERR2_Msk   = 0x800000  // Bit mask of RDPERR2 field.
	Flash_SR2_RDPERR2       = 0x800000  // Bit RDPERR2.
	Flash_SR2_RDSERR2_Pos   = 0x18      // Position of RDSERR2 field.
	Flash_SR2_RDSERR2_Msk   = 0x1000000 // Bit mask of RDSERR2 field.
	Flash_SR2_RDSERR2       = 0x1000000 // Bit RDSERR2.
	Flash_SR2_SNECCERR2_Pos = 0x19      // Position of SNECCERR2 field.
	Flash_SR2_SNECCERR2_Msk = 0x2000000 // Bit mask of SNECCERR2 field.
	Flash_SR2_SNECCERR2     = 0x2000000 // Bit SNECCERR2.
	Flash_SR2_DBECCERR2_Pos = 0x1a      // Position of DBECCERR2 field.
	Flash_SR2_DBECCERR2_Msk = 0x4000000 // Bit mask of DBECCERR2 field.
	Flash_SR2_DBECCERR2     = 0x4000000 // Bit DBECCERR2.
	Flash_SR2_CRCEND2_Pos   = 0x1b      // Position of CRCEND2 field.
	Flash_SR2_CRCEND2_Msk   = 0x8000000 // Bit mask of CRCEND2 field.
	Flash_SR2_CRCEND2       = 0x8000000 // Bit CRCEND2.

	// CCR2: FLASH clear control register for bank           2
	Flash_CCR2_CLR_EOP2_Pos      = 0x10      // Position of CLR_EOP2 field.
	Flash_CCR2_CLR_EOP2_Msk      = 0x10000   // Bit mask of CLR_EOP2 field.
	Flash_CCR2_CLR_EOP2          = 0x10000   // Bit CLR_EOP2.
	Flash_CCR2_CLR_WRPERR2_Pos   = 0x11      // Position of CLR_WRPERR2 field.
	Flash_CCR2_CLR_WRPERR2_Msk   = 0x20000   // Bit mask of CLR_WRPERR2 field.
	Flash_CCR2_CLR_WRPERR2       = 0x20000   // Bit CLR_WRPERR2.
	Flash_CCR2_CLR_PGSERR2_Pos   = 0x12      // Position of CLR_PGSERR2 field.
	Flash_CCR2_CLR_PGSERR2_Msk   = 0x40000   // Bit mask of CLR_PGSERR2 field.
	Flash_CCR2_CLR_PGSERR2       = 0x40000   // Bit CLR_PGSERR2.
	Flash_CCR2_CLR_STRBERR2_Pos  = 0x13      // Position of CLR_STRBERR2 field.
	Flash_CCR2_CLR_STRBERR2_Msk  = 0x80000   // Bit mask of CLR_STRBERR2 field.
	Flash_CCR2_CLR_STRBERR2      = 0x80000   // Bit CLR_STRBERR2.
	Flash_CCR2_CLR_INCERR2_Pos   = 0x15      // Position of CLR_INCERR2 field.
	Flash_CCR2_CLR_INCERR2_Msk   = 0x200000  // Bit mask of CLR_INCERR2 field.
	Flash_CCR2_CLR_INCERR2       = 0x200000  // Bit CLR_INCERR2.
	Flash_CCR2_CLR_OPERR2_Pos    = 0x16      // Position of CLR_OPERR2 field.
	Flash_CCR2_CLR_OPERR2_Msk    = 0x400000  // Bit mask of CLR_OPERR2 field.
	Flash_CCR2_CLR_OPERR2        = 0x400000  // Bit CLR_OPERR2.
	Flash_CCR2_CLR_RDPERR2_Pos   = 0x17      // Position of CLR_RDPERR2 field.
	Flash_CCR2_CLR_RDPERR2_Msk   = 0x800000  // Bit mask of CLR_RDPERR2 field.
	Flash_CCR2_CLR_RDPERR2       = 0x800000  // Bit CLR_RDPERR2.
	Flash_CCR2_CLR_RDSERR1_Pos   = 0x18      // Position of CLR_RDSERR1 field.
	Flash_CCR2_CLR_RDSERR1_Msk   = 0x1000000 // Bit mask of CLR_RDSERR1 field.
	Flash_CCR2_CLR_RDSERR1       = 0x1000000 // Bit CLR_RDSERR1.
	Flash_CCR2_CLR_SNECCERR2_Pos = 0x19      // Position of CLR_SNECCERR2 field.
	Flash_CCR2_CLR_SNECCERR2_Msk = 0x2000000 // Bit mask of CLR_SNECCERR2 field.
	Flash_CCR2_CLR_SNECCERR2     = 0x2000000 // Bit CLR_SNECCERR2.
	Flash_CCR2_CLR_DBECCERR1_Pos = 0x1a      // Position of CLR_DBECCERR1 field.
	Flash_CCR2_CLR_DBECCERR1_Msk = 0x4000000 // Bit mask of CLR_DBECCERR1 field.
	Flash_CCR2_CLR_DBECCERR1     = 0x4000000 // Bit CLR_DBECCERR1.
	Flash_CCR2_CLR_CRCEND2_Pos   = 0x1b      // Position of CLR_CRCEND2 field.
	Flash_CCR2_CLR_CRCEND2_Msk   = 0x8000000 // Bit mask of CLR_CRCEND2 field.
	Flash_CCR2_CLR_CRCEND2       = 0x8000000 // Bit CLR_CRCEND2.

	// OPTCR_: FLASH option control register
	Flash_OPTCR__OPTLOCK_Pos        = 0x0        // Position of OPTLOCK field.
	Flash_OPTCR__OPTLOCK_Msk        = 0x1        // Bit mask of OPTLOCK field.
	Flash_OPTCR__OPTLOCK            = 0x1        // Bit OPTLOCK.
	Flash_OPTCR__OPTSTART_Pos       = 0x1        // Position of OPTSTART field.
	Flash_OPTCR__OPTSTART_Msk       = 0x2        // Bit mask of OPTSTART field.
	Flash_OPTCR__OPTSTART           = 0x2        // Bit OPTSTART.
	Flash_OPTCR__MER_Pos            = 0x4        // Position of MER field.
	Flash_OPTCR__MER_Msk            = 0x10       // Bit mask of MER field.
	Flash_OPTCR__MER                = 0x10       // Bit MER.
	Flash_OPTCR__OPTCHANGEERRIE_Pos = 0x1e       // Position of OPTCHANGEERRIE field.
	Flash_OPTCR__OPTCHANGEERRIE_Msk = 0x40000000 // Bit mask of OPTCHANGEERRIE field.
	Flash_OPTCR__OPTCHANGEERRIE     = 0x40000000 // Bit OPTCHANGEERRIE.
	Flash_OPTCR__SWAP_BANK_Pos      = 0x1f       // Position of SWAP_BANK field.
	Flash_OPTCR__SWAP_BANK_Msk      = 0x80000000 // Bit mask of SWAP_BANK field.
	Flash_OPTCR__SWAP_BANK          = 0x80000000 // Bit SWAP_BANK.

	// OPTSR_CUR_: FLASH option status register
	Flash_OPTSR_CUR__OPT_BUSY_Pos      = 0x0        // Position of OPT_BUSY field.
	Flash_OPTSR_CUR__OPT_BUSY_Msk      = 0x1        // Bit mask of OPT_BUSY field.
	Flash_OPTSR_CUR__OPT_BUSY          = 0x1        // Bit OPT_BUSY.
	Flash_OPTSR_CUR__BOR_LEV_Pos       = 0x2        // Position of BOR_LEV field.
	Flash_OPTSR_CUR__BOR_LEV_Msk       = 0xc        // Bit mask of BOR_LEV field.
	Flash_OPTSR_CUR__IWDG1_HW_Pos      = 0x4        // Position of IWDG1_HW field.
	Flash_OPTSR_CUR__IWDG1_HW_Msk      = 0x10       // Bit mask of IWDG1_HW field.
	Flash_OPTSR_CUR__IWDG1_HW          = 0x10       // Bit IWDG1_HW.
	Flash_OPTSR_CUR__NRST_STOP_D1_Pos  = 0x6        // Position of NRST_STOP_D1 field.
	Flash_OPTSR_CUR__NRST_STOP_D1_Msk  = 0x40       // Bit mask of NRST_STOP_D1 field.
	Flash_OPTSR_CUR__NRST_STOP_D1      = 0x40       // Bit NRST_STOP_D1.
	Flash_OPTSR_CUR__NRST_STBY_D1_Pos  = 0x7        // Position of NRST_STBY_D1 field.
	Flash_OPTSR_CUR__NRST_STBY_D1_Msk  = 0x80       // Bit mask of NRST_STBY_D1 field.
	Flash_OPTSR_CUR__NRST_STBY_D1      = 0x80       // Bit NRST_STBY_D1.
	Flash_OPTSR_CUR__RDP_Pos           = 0x8        // Position of RDP field.
	Flash_OPTSR_CUR__RDP_Msk           = 0xff00     // Bit mask of RDP field.
	Flash_OPTSR_CUR__FZ_IWDG_STOP_Pos  = 0x11       // Position of FZ_IWDG_STOP field.
	Flash_OPTSR_CUR__FZ_IWDG_STOP_Msk  = 0x20000    // Bit mask of FZ_IWDG_STOP field.
	Flash_OPTSR_CUR__FZ_IWDG_STOP      = 0x20000    // Bit FZ_IWDG_STOP.
	Flash_OPTSR_CUR__FZ_IWDG_SDBY_Pos  = 0x12       // Position of FZ_IWDG_SDBY field.
	Flash_OPTSR_CUR__FZ_IWDG_SDBY_Msk  = 0x40000    // Bit mask of FZ_IWDG_SDBY field.
	Flash_OPTSR_CUR__FZ_IWDG_SDBY      = 0x40000    // Bit FZ_IWDG_SDBY.
	Flash_OPTSR_CUR__ST_RAM_SIZE_Pos   = 0x13       // Position of ST_RAM_SIZE field.
	Flash_OPTSR_CUR__ST_RAM_SIZE_Msk   = 0x180000   // Bit mask of ST_RAM_SIZE field.
	Flash_OPTSR_CUR__SECURITY_Pos      = 0x15       // Position of SECURITY field.
	Flash_OPTSR_CUR__SECURITY_Msk      = 0x200000   // Bit mask of SECURITY field.
	Flash_OPTSR_CUR__SECURITY          = 0x200000   // Bit SECURITY.
	Flash_OPTSR_CUR__RSS1_Pos          = 0x1a       // Position of RSS1 field.
	Flash_OPTSR_CUR__RSS1_Msk          = 0x4000000  // Bit mask of RSS1 field.
	Flash_OPTSR_CUR__RSS1              = 0x4000000  // Bit RSS1.
	Flash_OPTSR_CUR__PERSO_OK_Pos      = 0x1c       // Position of PERSO_OK field.
	Flash_OPTSR_CUR__PERSO_OK_Msk      = 0x10000000 // Bit mask of PERSO_OK field.
	Flash_OPTSR_CUR__PERSO_OK          = 0x10000000 // Bit PERSO_OK.
	Flash_OPTSR_CUR__IO_HSLV_Pos       = 0x1d       // Position of IO_HSLV field.
	Flash_OPTSR_CUR__IO_HSLV_Msk       = 0x20000000 // Bit mask of IO_HSLV field.
	Flash_OPTSR_CUR__IO_HSLV           = 0x20000000 // Bit IO_HSLV.
	Flash_OPTSR_CUR__OPTCHANGEERR_Pos  = 0x1e       // Position of OPTCHANGEERR field.
	Flash_OPTSR_CUR__OPTCHANGEERR_Msk  = 0x40000000 // Bit mask of OPTCHANGEERR field.
	Flash_OPTSR_CUR__OPTCHANGEERR      = 0x40000000 // Bit OPTCHANGEERR.
	Flash_OPTSR_CUR__SWAP_BANK_OPT_Pos = 0x1f       // Position of SWAP_BANK_OPT field.
	Flash_OPTSR_CUR__SWAP_BANK_OPT_Msk = 0x80000000 // Bit mask of SWAP_BANK_OPT field.
	Flash_OPTSR_CUR__SWAP_BANK_OPT     = 0x80000000 // Bit SWAP_BANK_OPT.

	// OPTSR_PRG_: FLASH option status register
	Flash_OPTSR_PRG__BOR_LEV_Pos       = 0x2        // Position of BOR_LEV field.
	Flash_OPTSR_PRG__BOR_LEV_Msk       = 0xc        // Bit mask of BOR_LEV field.
	Flash_OPTSR_PRG__IWDG1_HW_Pos      = 0x4        // Position of IWDG1_HW field.
	Flash_OPTSR_PRG__IWDG1_HW_Msk      = 0x10       // Bit mask of IWDG1_HW field.
	Flash_OPTSR_PRG__IWDG1_HW          = 0x10       // Bit IWDG1_HW.
	Flash_OPTSR_PRG__NRST_STOP_D1_Pos  = 0x6        // Position of NRST_STOP_D1 field.
	Flash_OPTSR_PRG__NRST_STOP_D1_Msk  = 0x40       // Bit mask of NRST_STOP_D1 field.
	Flash_OPTSR_PRG__NRST_STOP_D1      = 0x40       // Bit NRST_STOP_D1.
	Flash_OPTSR_PRG__NRST_STBY_D1_Pos  = 0x7        // Position of NRST_STBY_D1 field.
	Flash_OPTSR_PRG__NRST_STBY_D1_Msk  = 0x80       // Bit mask of NRST_STBY_D1 field.
	Flash_OPTSR_PRG__NRST_STBY_D1      = 0x80       // Bit NRST_STBY_D1.
	Flash_OPTSR_PRG__RDP_Pos           = 0x8        // Position of RDP field.
	Flash_OPTSR_PRG__RDP_Msk           = 0xff00     // Bit mask of RDP field.
	Flash_OPTSR_PRG__FZ_IWDG_STOP_Pos  = 0x11       // Position of FZ_IWDG_STOP field.
	Flash_OPTSR_PRG__FZ_IWDG_STOP_Msk  = 0x20000    // Bit mask of FZ_IWDG_STOP field.
	Flash_OPTSR_PRG__FZ_IWDG_STOP      = 0x20000    // Bit FZ_IWDG_STOP.
	Flash_OPTSR_PRG__FZ_IWDG_SDBY_Pos  = 0x12       // Position of FZ_IWDG_SDBY field.
	Flash_OPTSR_PRG__FZ_IWDG_SDBY_Msk  = 0x40000    // Bit mask of FZ_IWDG_SDBY field.
	Flash_OPTSR_PRG__FZ_IWDG_SDBY      = 0x40000    // Bit FZ_IWDG_SDBY.
	Flash_OPTSR_PRG__ST_RAM_SIZE_Pos   = 0x13       // Position of ST_RAM_SIZE field.
	Flash_OPTSR_PRG__ST_RAM_SIZE_Msk   = 0x180000   // Bit mask of ST_RAM_SIZE field.
	Flash_OPTSR_PRG__SECURITY_Pos      = 0x15       // Position of SECURITY field.
	Flash_OPTSR_PRG__SECURITY_Msk      = 0x200000   // Bit mask of SECURITY field.
	Flash_OPTSR_PRG__SECURITY          = 0x200000   // Bit SECURITY.
	Flash_OPTSR_PRG__RSS1_Pos          = 0x1a       // Position of RSS1 field.
	Flash_OPTSR_PRG__RSS1_Msk          = 0x4000000  // Bit mask of RSS1 field.
	Flash_OPTSR_PRG__RSS1              = 0x4000000  // Bit RSS1.
	Flash_OPTSR_PRG__RSS2_Pos          = 0x1b       // Position of RSS2 field.
	Flash_OPTSR_PRG__RSS2_Msk          = 0x8000000  // Bit mask of RSS2 field.
	Flash_OPTSR_PRG__RSS2              = 0x8000000  // Bit RSS2.
	Flash_OPTSR_PRG__IO_HSLV_Pos       = 0x1d       // Position of IO_HSLV field.
	Flash_OPTSR_PRG__IO_HSLV_Msk       = 0x20000000 // Bit mask of IO_HSLV field.
	Flash_OPTSR_PRG__IO_HSLV           = 0x20000000 // Bit IO_HSLV.
	Flash_OPTSR_PRG__SWAP_BANK_OPT_Pos = 0x1f       // Position of SWAP_BANK_OPT field.
	Flash_OPTSR_PRG__SWAP_BANK_OPT_Msk = 0x80000000 // Bit mask of SWAP_BANK_OPT field.
	Flash_OPTSR_PRG__SWAP_BANK_OPT     = 0x80000000 // Bit SWAP_BANK_OPT.

	// OPTCCR_: FLASH option clear control           register
	Flash_OPTCCR__CLR_OPTCHANGEERR_Pos = 0x1e       // Position of CLR_OPTCHANGEERR field.
	Flash_OPTCCR__CLR_OPTCHANGEERR_Msk = 0x40000000 // Bit mask of CLR_OPTCHANGEERR field.
	Flash_OPTCCR__CLR_OPTCHANGEERR     = 0x40000000 // Bit CLR_OPTCHANGEERR.

	// PRAR_CUR2: FLASH protection address for bank           1
	Flash_PRAR_CUR2_PROT_AREA_START2_Pos = 0x0        // Position of PROT_AREA_START2 field.
	Flash_PRAR_CUR2_PROT_AREA_START2_Msk = 0xfff      // Bit mask of PROT_AREA_START2 field.
	Flash_PRAR_CUR2_PROT_AREA_END2_Pos   = 0x10       // Position of PROT_AREA_END2 field.
	Flash_PRAR_CUR2_PROT_AREA_END2_Msk   = 0xfff0000  // Bit mask of PROT_AREA_END2 field.
	Flash_PRAR_CUR2_DMEP2_Pos            = 0x1f       // Position of DMEP2 field.
	Flash_PRAR_CUR2_DMEP2_Msk            = 0x80000000 // Bit mask of DMEP2 field.
	Flash_PRAR_CUR2_DMEP2                = 0x80000000 // Bit DMEP2.

	// SCAR_CUR2: FLASH secure address for bank           2
	Flash_SCAR_CUR2_SEC_AREA_START2_Pos = 0x0        // Position of SEC_AREA_START2 field.
	Flash_SCAR_CUR2_SEC_AREA_START2_Msk = 0xfff      // Bit mask of SEC_AREA_START2 field.
	Flash_SCAR_CUR2_SEC_AREA_END2_Pos   = 0x10       // Position of SEC_AREA_END2 field.
	Flash_SCAR_CUR2_SEC_AREA_END2_Msk   = 0xfff0000  // Bit mask of SEC_AREA_END2 field.
	Flash_SCAR_CUR2_DMES2_Pos           = 0x1f       // Position of DMES2 field.
	Flash_SCAR_CUR2_DMES2_Msk           = 0x80000000 // Bit mask of DMES2 field.
	Flash_SCAR_CUR2_DMES2               = 0x80000000 // Bit DMES2.

	// SCAR_PRG2: FLASH secure address for bank           2
	Flash_SCAR_PRG2_SEC_AREA_START2_Pos = 0x0        // Position of SEC_AREA_START2 field.
	Flash_SCAR_PRG2_SEC_AREA_START2_Msk = 0xfff      // Bit mask of SEC_AREA_START2 field.
	Flash_SCAR_PRG2_SEC_AREA_END2_Pos   = 0x10       // Position of SEC_AREA_END2 field.
	Flash_SCAR_PRG2_SEC_AREA_END2_Msk   = 0xfff0000  // Bit mask of SEC_AREA_END2 field.
	Flash_SCAR_PRG2_DMES2_Pos           = 0x1f       // Position of DMES2 field.
	Flash_SCAR_PRG2_DMES2_Msk           = 0x80000000 // Bit mask of DMES2 field.
	Flash_SCAR_PRG2_DMES2               = 0x80000000 // Bit DMES2.

	// WPSN_CUR2R: FLASH write sector protection for bank           2
	Flash_WPSN_CUR2R_WRPSn2_Pos = 0x0  // Position of WRPSn2 field.
	Flash_WPSN_CUR2R_WRPSn2_Msk = 0xff // Bit mask of WRPSn2 field.

	// WPSN_PRG2R: FLASH write sector protection for bank           2
	Flash_WPSN_PRG2R_WRPSn2_Pos = 0x0  // Position of WRPSn2 field.
	Flash_WPSN_PRG2R_WRPSn2_Msk = 0xff // Bit mask of WRPSn2 field.

	// CRCCR2: FLASH CRC control register for bank           1
	Flash_CRCCR2_CRC_SECT_Pos    = 0x0      // Position of CRC_SECT field.
	Flash_CRCCR2_CRC_SECT_Msk    = 0x7      // Bit mask of CRC_SECT field.
	Flash_CRCCR2_ALL_BANK_Pos    = 0x7      // Position of ALL_BANK field.
	Flash_CRCCR2_ALL_BANK_Msk    = 0x80     // Bit mask of ALL_BANK field.
	Flash_CRCCR2_ALL_BANK        = 0x80     // Bit ALL_BANK.
	Flash_CRCCR2_CRC_BY_SECT_Pos = 0x8      // Position of CRC_BY_SECT field.
	Flash_CRCCR2_CRC_BY_SECT_Msk = 0x100    // Bit mask of CRC_BY_SECT field.
	Flash_CRCCR2_CRC_BY_SECT     = 0x100    // Bit CRC_BY_SECT.
	Flash_CRCCR2_ADD_SECT_Pos    = 0x9      // Position of ADD_SECT field.
	Flash_CRCCR2_ADD_SECT_Msk    = 0x200    // Bit mask of ADD_SECT field.
	Flash_CRCCR2_ADD_SECT        = 0x200    // Bit ADD_SECT.
	Flash_CRCCR2_CLEAN_SECT_Pos  = 0xa      // Position of CLEAN_SECT field.
	Flash_CRCCR2_CLEAN_SECT_Msk  = 0x400    // Bit mask of CLEAN_SECT field.
	Flash_CRCCR2_CLEAN_SECT      = 0x400    // Bit CLEAN_SECT.
	Flash_CRCCR2_START_CRC_Pos   = 0x10     // Position of START_CRC field.
	Flash_CRCCR2_START_CRC_Msk   = 0x10000  // Bit mask of START_CRC field.
	Flash_CRCCR2_START_CRC       = 0x10000  // Bit START_CRC.
	Flash_CRCCR2_CLEAN_CRC_Pos   = 0x11     // Position of CLEAN_CRC field.
	Flash_CRCCR2_CLEAN_CRC_Msk   = 0x20000  // Bit mask of CLEAN_CRC field.
	Flash_CRCCR2_CLEAN_CRC       = 0x20000  // Bit CLEAN_CRC.
	Flash_CRCCR2_CRC_BURST_Pos   = 0x14     // Position of CRC_BURST field.
	Flash_CRCCR2_CRC_BURST_Msk   = 0x300000 // Bit mask of CRC_BURST field.

	// CRCSADD2R: FLASH CRC start address register for bank           2
	Flash_CRCSADD2R_CRC_START_ADDR_Pos = 0x0        // Position of CRC_START_ADDR field.
	Flash_CRCSADD2R_CRC_START_ADDR_Msk = 0xffffffff // Bit mask of CRC_START_ADDR field.

	// CRCEADD2R: FLASH CRC end address register for bank           2
	Flash_CRCEADD2R_CRC_END_ADDR_Pos = 0x0        // Position of CRC_END_ADDR field.
	Flash_CRCEADD2R_CRC_END_ADDR_Msk = 0xffffffff // Bit mask of CRC_END_ADDR field.

	// ECC_FA2R: FLASH ECC fail address for bank           2
	Flash_ECC_FA2R_FAIL_ECC_ADDR2_Pos = 0x0    // Position of FAIL_ECC_ADDR2 field.
	Flash_ECC_FA2R_FAIL_ECC_ADDR2_Msk = 0x7fff // Bit mask of FAIL_ECC_ADDR2 field.
)

// Bitfields for AXI: AXI interconnect registers
const (
	// AXI_PERIPH_ID_4: AXI interconnect - peripheral ID4           register
	AXI_AXI_PERIPH_ID_4_JEP106CON_Pos = 0x0  // Position of JEP106CON field.
	AXI_AXI_PERIPH_ID_4_JEP106CON_Msk = 0xf  // Bit mask of JEP106CON field.
	AXI_AXI_PERIPH_ID_4_KCOUNT4_Pos   = 0x4  // Position of KCOUNT4 field.
	AXI_AXI_PERIPH_ID_4_KCOUNT4_Msk   = 0xf0 // Bit mask of KCOUNT4 field.

	// AXI_PERIPH_ID_0: AXI interconnect - peripheral ID0           register
	AXI_AXI_PERIPH_ID_0_PARTNUM_Pos = 0x0  // Position of PARTNUM field.
	AXI_AXI_PERIPH_ID_0_PARTNUM_Msk = 0xff // Bit mask of PARTNUM field.

	// AXI_PERIPH_ID_1: AXI interconnect - peripheral ID1           register
	AXI_AXI_PERIPH_ID_1_PARTNUM_Pos = 0x0  // Position of PARTNUM field.
	AXI_AXI_PERIPH_ID_1_PARTNUM_Msk = 0xf  // Bit mask of PARTNUM field.
	AXI_AXI_PERIPH_ID_1_JEP106I_Pos = 0x4  // Position of JEP106I field.
	AXI_AXI_PERIPH_ID_1_JEP106I_Msk = 0xf0 // Bit mask of JEP106I field.

	// AXI_PERIPH_ID_2: AXI interconnect - peripheral ID2           register
	AXI_AXI_PERIPH_ID_2_JEP106ID_Pos = 0x0  // Position of JEP106ID field.
	AXI_AXI_PERIPH_ID_2_JEP106ID_Msk = 0x7  // Bit mask of JEP106ID field.
	AXI_AXI_PERIPH_ID_2_JEDEC_Pos    = 0x3  // Position of JEDEC field.
	AXI_AXI_PERIPH_ID_2_JEDEC_Msk    = 0x8  // Bit mask of JEDEC field.
	AXI_AXI_PERIPH_ID_2_JEDEC        = 0x8  // Bit JEDEC.
	AXI_AXI_PERIPH_ID_2_REVISION_Pos = 0x4  // Position of REVISION field.
	AXI_AXI_PERIPH_ID_2_REVISION_Msk = 0xf0 // Bit mask of REVISION field.

	// AXI_PERIPH_ID_3: AXI interconnect - peripheral ID3           register
	AXI_AXI_PERIPH_ID_3_CUST_MOD_NUM_Pos = 0x0  // Position of CUST_MOD_NUM field.
	AXI_AXI_PERIPH_ID_3_CUST_MOD_NUM_Msk = 0xf  // Bit mask of CUST_MOD_NUM field.
	AXI_AXI_PERIPH_ID_3_REV_AND_Pos      = 0x4  // Position of REV_AND field.
	AXI_AXI_PERIPH_ID_3_REV_AND_Msk      = 0xf0 // Bit mask of REV_AND field.

	// AXI_COMP_ID_0: AXI interconnect - component ID0           register
	AXI_AXI_COMP_ID_0_PREAMBLE_Pos = 0x0  // Position of PREAMBLE field.
	AXI_AXI_COMP_ID_0_PREAMBLE_Msk = 0xff // Bit mask of PREAMBLE field.

	// AXI_COMP_ID_1: AXI interconnect - component ID1           register
	AXI_AXI_COMP_ID_1_PREAMBLE_Pos = 0x0  // Position of PREAMBLE field.
	AXI_AXI_COMP_ID_1_PREAMBLE_Msk = 0xf  // Bit mask of PREAMBLE field.
	AXI_AXI_COMP_ID_1_CLASS_Pos    = 0x4  // Position of CLASS field.
	AXI_AXI_COMP_ID_1_CLASS_Msk    = 0xf0 // Bit mask of CLASS field.

	// AXI_COMP_ID_2: AXI interconnect - component ID2           register
	AXI_AXI_COMP_ID_2_PREAMBLE_Pos = 0x0  // Position of PREAMBLE field.
	AXI_AXI_COMP_ID_2_PREAMBLE_Msk = 0xff // Bit mask of PREAMBLE field.

	// AXI_COMP_ID_3: AXI interconnect - component ID3           register
	AXI_AXI_COMP_ID_3_PREAMBLE_Pos = 0x0  // Position of PREAMBLE field.
	AXI_AXI_COMP_ID_3_PREAMBLE_Msk = 0xff // Bit mask of PREAMBLE field.

	// AXI_TARG1_FN_MOD_ISS_BM: AXI interconnect - TARG x bus matrix issuing           functionality register
	AXI_AXI_TARG1_FN_MOD_ISS_BM_READ_ISS_OVERRIDE_Pos  = 0x0 // Position of READ_ISS_OVERRIDE field.
	AXI_AXI_TARG1_FN_MOD_ISS_BM_READ_ISS_OVERRIDE_Msk  = 0x1 // Bit mask of READ_ISS_OVERRIDE field.
	AXI_AXI_TARG1_FN_MOD_ISS_BM_READ_ISS_OVERRIDE      = 0x1 // Bit READ_ISS_OVERRIDE.
	AXI_AXI_TARG1_FN_MOD_ISS_BM_WRITE_ISS_OVERRIDE_Pos = 0x1 // Position of WRITE_ISS_OVERRIDE field.
	AXI_AXI_TARG1_FN_MOD_ISS_BM_WRITE_ISS_OVERRIDE_Msk = 0x2 // Bit mask of WRITE_ISS_OVERRIDE field.
	AXI_AXI_TARG1_FN_MOD_ISS_BM_WRITE_ISS_OVERRIDE     = 0x2 // Bit WRITE_ISS_OVERRIDE.

	// AXI_TARG1_FN_MOD2: AXI interconnect - TARG x bus matrix           functionality 2 register
	AXI_AXI_TARG1_FN_MOD2_BYPASS_MERGE_Pos = 0x0 // Position of BYPASS_MERGE field.
	AXI_AXI_TARG1_FN_MOD2_BYPASS_MERGE_Msk = 0x1 // Bit mask of BYPASS_MERGE field.
	AXI_AXI_TARG1_FN_MOD2_BYPASS_MERGE     = 0x1 // Bit BYPASS_MERGE.

	// AXI_TARG1_FN_MOD_LB: AXI interconnect - TARG x long burst           functionality modification
	AXI_AXI_TARG1_FN_MOD_LB_FN_MOD_LB_Pos = 0x0 // Position of FN_MOD_LB field.
	AXI_AXI_TARG1_FN_MOD_LB_FN_MOD_LB_Msk = 0x1 // Bit mask of FN_MOD_LB field.
	AXI_AXI_TARG1_FN_MOD_LB_FN_MOD_LB     = 0x1 // Bit FN_MOD_LB.

	// AXI_TARG1_FN_MOD: AXI interconnect - TARG x long burst           functionality modification
	AXI_AXI_TARG1_FN_MOD_READ_ISS_OVERRIDE_Pos  = 0x0 // Position of READ_ISS_OVERRIDE field.
	AXI_AXI_TARG1_FN_MOD_READ_ISS_OVERRIDE_Msk  = 0x1 // Bit mask of READ_ISS_OVERRIDE field.
	AXI_AXI_TARG1_FN_MOD_READ_ISS_OVERRIDE      = 0x1 // Bit READ_ISS_OVERRIDE.
	AXI_AXI_TARG1_FN_MOD_WRITE_ISS_OVERRIDE_Pos = 0x1 // Position of WRITE_ISS_OVERRIDE field.
	AXI_AXI_TARG1_FN_MOD_WRITE_ISS_OVERRIDE_Msk = 0x2 // Bit mask of WRITE_ISS_OVERRIDE field.
	AXI_AXI_TARG1_FN_MOD_WRITE_ISS_OVERRIDE     = 0x2 // Bit WRITE_ISS_OVERRIDE.

	// AXI_TARG2_FN_MOD_ISS_BM: AXI interconnect - TARG x bus matrix issuing           functionality register
	AXI_AXI_TARG2_FN_MOD_ISS_BM_READ_ISS_OVERRIDE_Pos  = 0x0 // Position of READ_ISS_OVERRIDE field.
	AXI_AXI_TARG2_FN_MOD_ISS_BM_READ_ISS_OVERRIDE_Msk  = 0x1 // Bit mask of READ_ISS_OVERRIDE field.
	AXI_AXI_TARG2_FN_MOD_ISS_BM_READ_ISS_OVERRIDE      = 0x1 // Bit READ_ISS_OVERRIDE.
	AXI_AXI_TARG2_FN_MOD_ISS_BM_WRITE_ISS_OVERRIDE_Pos = 0x1 // Position of WRITE_ISS_OVERRIDE field.
	AXI_AXI_TARG2_FN_MOD_ISS_BM_WRITE_ISS_OVERRIDE_Msk = 0x2 // Bit mask of WRITE_ISS_OVERRIDE field.
	AXI_AXI_TARG2_FN_MOD_ISS_BM_WRITE_ISS_OVERRIDE     = 0x2 // Bit WRITE_ISS_OVERRIDE.

	// AXI_TARG2_FN_MOD2: AXI interconnect - TARG x bus matrix           functionality 2 register
	AXI_AXI_TARG2_FN_MOD2_BYPASS_MERGE_Pos = 0x0 // Position of BYPASS_MERGE field.
	AXI_AXI_TARG2_FN_MOD2_BYPASS_MERGE_Msk = 0x1 // Bit mask of BYPASS_MERGE field.
	AXI_AXI_TARG2_FN_MOD2_BYPASS_MERGE     = 0x1 // Bit BYPASS_MERGE.

	// AXI_TARG2_FN_MOD_LB: AXI interconnect - TARG x long burst           functionality modification
	AXI_AXI_TARG2_FN_MOD_LB_FN_MOD_LB_Pos = 0x0 // Position of FN_MOD_LB field.
	AXI_AXI_TARG2_FN_MOD_LB_FN_MOD_LB_Msk = 0x1 // Bit mask of FN_MOD_LB field.
	AXI_AXI_TARG2_FN_MOD_LB_FN_MOD_LB     = 0x1 // Bit FN_MOD_LB.

	// AXI_TARG2_FN_MOD: AXI interconnect - TARG x long burst           functionality modification
	AXI_AXI_TARG2_FN_MOD_READ_ISS_OVERRIDE_Pos  = 0x0 // Position of READ_ISS_OVERRIDE field.
	AXI_AXI_TARG2_FN_MOD_READ_ISS_OVERRIDE_Msk  = 0x1 // Bit mask of READ_ISS_OVERRIDE field.
	AXI_AXI_TARG2_FN_MOD_READ_ISS_OVERRIDE      = 0x1 // Bit READ_ISS_OVERRIDE.
	AXI_AXI_TARG2_FN_MOD_WRITE_ISS_OVERRIDE_Pos = 0x1 // Position of WRITE_ISS_OVERRIDE field.
	AXI_AXI_TARG2_FN_MOD_WRITE_ISS_OVERRIDE_Msk = 0x2 // Bit mask of WRITE_ISS_OVERRIDE field.
	AXI_AXI_TARG2_FN_MOD_WRITE_ISS_OVERRIDE     = 0x2 // Bit WRITE_ISS_OVERRIDE.

	// AXI_TARG3_FN_MOD_ISS_BM: AXI interconnect - TARG x bus matrix issuing           functionality register
	AXI_AXI_TARG3_FN_MOD_ISS_BM_READ_ISS_OVERRIDE_Pos  = 0x0 // Position of READ_ISS_OVERRIDE field.
	AXI_AXI_TARG3_FN_MOD_ISS_BM_READ_ISS_OVERRIDE_Msk  = 0x1 // Bit mask of READ_ISS_OVERRIDE field.
	AXI_AXI_TARG3_FN_MOD_ISS_BM_READ_ISS_OVERRIDE      = 0x1 // Bit READ_ISS_OVERRIDE.
	AXI_AXI_TARG3_FN_MOD_ISS_BM_WRITE_ISS_OVERRIDE_Pos = 0x1 // Position of WRITE_ISS_OVERRIDE field.
	AXI_AXI_TARG3_FN_MOD_ISS_BM_WRITE_ISS_OVERRIDE_Msk = 0x2 // Bit mask of WRITE_ISS_OVERRIDE field.
	AXI_AXI_TARG3_FN_MOD_ISS_BM_WRITE_ISS_OVERRIDE     = 0x2 // Bit WRITE_ISS_OVERRIDE.

	// AXI_TARG4_FN_MOD_ISS_BM: AXI interconnect - TARG x bus matrix issuing           functionality register
	AXI_AXI_TARG4_FN_MOD_ISS_BM_READ_ISS_OVERRIDE_Pos  = 0x0 // Position of READ_ISS_OVERRIDE field.
	AXI_AXI_TARG4_FN_MOD_ISS_BM_READ_ISS_OVERRIDE_Msk  = 0x1 // Bit mask of READ_ISS_OVERRIDE field.
	AXI_AXI_TARG4_FN_MOD_ISS_BM_READ_ISS_OVERRIDE      = 0x1 // Bit READ_ISS_OVERRIDE.
	AXI_AXI_TARG4_FN_MOD_ISS_BM_WRITE_ISS_OVERRIDE_Pos = 0x1 // Position of WRITE_ISS_OVERRIDE field.
	AXI_AXI_TARG4_FN_MOD_ISS_BM_WRITE_ISS_OVERRIDE_Msk = 0x2 // Bit mask of WRITE_ISS_OVERRIDE field.
	AXI_AXI_TARG4_FN_MOD_ISS_BM_WRITE_ISS_OVERRIDE     = 0x2 // Bit WRITE_ISS_OVERRIDE.

	// AXI_TARG5_FN_MOD_ISS_BM: AXI interconnect - TARG x bus matrix issuing           functionality register
	AXI_AXI_TARG5_FN_MOD_ISS_BM_READ_ISS_OVERRIDE_Pos  = 0x0 // Position of READ_ISS_OVERRIDE field.
	AXI_AXI_TARG5_FN_MOD_ISS_BM_READ_ISS_OVERRIDE_Msk  = 0x1 // Bit mask of READ_ISS_OVERRIDE field.
	AXI_AXI_TARG5_FN_MOD_ISS_BM_READ_ISS_OVERRIDE      = 0x1 // Bit READ_ISS_OVERRIDE.
	AXI_AXI_TARG5_FN_MOD_ISS_BM_WRITE_ISS_OVERRIDE_Pos = 0x1 // Position of WRITE_ISS_OVERRIDE field.
	AXI_AXI_TARG5_FN_MOD_ISS_BM_WRITE_ISS_OVERRIDE_Msk = 0x2 // Bit mask of WRITE_ISS_OVERRIDE field.
	AXI_AXI_TARG5_FN_MOD_ISS_BM_WRITE_ISS_OVERRIDE     = 0x2 // Bit WRITE_ISS_OVERRIDE.

	// AXI_TARG6_FN_MOD_ISS_BM: AXI interconnect - TARG x bus matrix issuing           functionality register
	AXI_AXI_TARG6_FN_MOD_ISS_BM_READ_ISS_OVERRIDE_Pos  = 0x0 // Position of READ_ISS_OVERRIDE field.
	AXI_AXI_TARG6_FN_MOD_ISS_BM_READ_ISS_OVERRIDE_Msk  = 0x1 // Bit mask of READ_ISS_OVERRIDE field.
	AXI_AXI_TARG6_FN_MOD_ISS_BM_READ_ISS_OVERRIDE      = 0x1 // Bit READ_ISS_OVERRIDE.
	AXI_AXI_TARG6_FN_MOD_ISS_BM_WRITE_ISS_OVERRIDE_Pos = 0x1 // Position of WRITE_ISS_OVERRIDE field.
	AXI_AXI_TARG6_FN_MOD_ISS_BM_WRITE_ISS_OVERRIDE_Msk = 0x2 // Bit mask of WRITE_ISS_OVERRIDE field.
	AXI_AXI_TARG6_FN_MOD_ISS_BM_WRITE_ISS_OVERRIDE     = 0x2 // Bit WRITE_ISS_OVERRIDE.

	// AXI_TARG7_FN_MOD_ISS_BM: AXI interconnect - TARG x bus matrix issuing           functionality register
	AXI_AXI_TARG7_FN_MOD_ISS_BM_READ_ISS_OVERRIDE_Pos  = 0x0 // Position of READ_ISS_OVERRIDE field.
	AXI_AXI_TARG7_FN_MOD_ISS_BM_READ_ISS_OVERRIDE_Msk  = 0x1 // Bit mask of READ_ISS_OVERRIDE field.
	AXI_AXI_TARG7_FN_MOD_ISS_BM_READ_ISS_OVERRIDE      = 0x1 // Bit READ_ISS_OVERRIDE.
	AXI_AXI_TARG7_FN_MOD_ISS_BM_WRITE_ISS_OVERRIDE_Pos = 0x1 // Position of WRITE_ISS_OVERRIDE field.
	AXI_AXI_TARG7_FN_MOD_ISS_BM_WRITE_ISS_OVERRIDE_Msk = 0x2 // Bit mask of WRITE_ISS_OVERRIDE field.
	AXI_AXI_TARG7_FN_MOD_ISS_BM_WRITE_ISS_OVERRIDE     = 0x2 // Bit WRITE_ISS_OVERRIDE.

	// AXI_TARG7_FN_MOD2: AXI interconnect - TARG x bus matrix           functionality 2 register
	AXI_AXI_TARG7_FN_MOD2_BYPASS_MERGE_Pos = 0x0 // Position of BYPASS_MERGE field.
	AXI_AXI_TARG7_FN_MOD2_BYPASS_MERGE_Msk = 0x1 // Bit mask of BYPASS_MERGE field.
	AXI_AXI_TARG7_FN_MOD2_BYPASS_MERGE     = 0x1 // Bit BYPASS_MERGE.

	// AXI_TARG7_FN_MOD: AXI interconnect - TARG x long burst           functionality modification
	AXI_AXI_TARG7_FN_MOD_READ_ISS_OVERRIDE_Pos  = 0x0 // Position of READ_ISS_OVERRIDE field.
	AXI_AXI_TARG7_FN_MOD_READ_ISS_OVERRIDE_Msk  = 0x1 // Bit mask of READ_ISS_OVERRIDE field.
	AXI_AXI_TARG7_FN_MOD_READ_ISS_OVERRIDE      = 0x1 // Bit READ_ISS_OVERRIDE.
	AXI_AXI_TARG7_FN_MOD_WRITE_ISS_OVERRIDE_Pos = 0x1 // Position of WRITE_ISS_OVERRIDE field.
	AXI_AXI_TARG7_FN_MOD_WRITE_ISS_OVERRIDE_Msk = 0x2 // Bit mask of WRITE_ISS_OVERRIDE field.
	AXI_AXI_TARG7_FN_MOD_WRITE_ISS_OVERRIDE     = 0x2 // Bit WRITE_ISS_OVERRIDE.

	// AXI_INI1_FN_MOD2: AXI interconnect - INI x functionality           modification 2 register
	AXI_AXI_INI1_FN_MOD2_BYPASS_MERGE_Pos = 0x0 // Position of BYPASS_MERGE field.
	AXI_AXI_INI1_FN_MOD2_BYPASS_MERGE_Msk = 0x1 // Bit mask of BYPASS_MERGE field.
	AXI_AXI_INI1_FN_MOD2_BYPASS_MERGE     = 0x1 // Bit BYPASS_MERGE.

	// AXI_INI1_FN_MOD_AHB: AXI interconnect - INI x AHB functionality           modification register
	AXI_AXI_INI1_FN_MOD_AHB_RD_INC_OVERRIDE_Pos = 0x0 // Position of RD_INC_OVERRIDE field.
	AXI_AXI_INI1_FN_MOD_AHB_RD_INC_OVERRIDE_Msk = 0x1 // Bit mask of RD_INC_OVERRIDE field.
	AXI_AXI_INI1_FN_MOD_AHB_RD_INC_OVERRIDE     = 0x1 // Bit RD_INC_OVERRIDE.
	AXI_AXI_INI1_FN_MOD_AHB_WR_INC_OVERRIDE_Pos = 0x1 // Position of WR_INC_OVERRIDE field.
	AXI_AXI_INI1_FN_MOD_AHB_WR_INC_OVERRIDE_Msk = 0x2 // Bit mask of WR_INC_OVERRIDE field.
	AXI_AXI_INI1_FN_MOD_AHB_WR_INC_OVERRIDE     = 0x2 // Bit WR_INC_OVERRIDE.

	// AXI_INI1_READ_QOS: AXI interconnect - INI x read QoS           register
	AXI_AXI_INI1_READ_QOS_AR_QOS_Pos = 0x0 // Position of AR_QOS field.
	AXI_AXI_INI1_READ_QOS_AR_QOS_Msk = 0xf // Bit mask of AR_QOS field.

	// AXI_INI1_WRITE_QOS: AXI interconnect - INI x write QoS           register
	AXI_AXI_INI1_WRITE_QOS_AW_QOS_Pos = 0x0 // Position of AW_QOS field.
	AXI_AXI_INI1_WRITE_QOS_AW_QOS_Msk = 0xf // Bit mask of AW_QOS field.

	// AXI_INI1_FN_MOD: AXI interconnect - INI x issuing           functionality modification register
	AXI_AXI_INI1_FN_MOD_READ_ISS_OVERRIDE_Pos  = 0x0 // Position of READ_ISS_OVERRIDE field.
	AXI_AXI_INI1_FN_MOD_READ_ISS_OVERRIDE_Msk  = 0x1 // Bit mask of READ_ISS_OVERRIDE field.
	AXI_AXI_INI1_FN_MOD_READ_ISS_OVERRIDE      = 0x1 // Bit READ_ISS_OVERRIDE.
	AXI_AXI_INI1_FN_MOD_WRITE_ISS_OVERRIDE_Pos = 0x1 // Position of WRITE_ISS_OVERRIDE field.
	AXI_AXI_INI1_FN_MOD_WRITE_ISS_OVERRIDE_Msk = 0x2 // Bit mask of WRITE_ISS_OVERRIDE field.
	AXI_AXI_INI1_FN_MOD_WRITE_ISS_OVERRIDE     = 0x2 // Bit WRITE_ISS_OVERRIDE.

	// AXI_INI2_READ_QOS: AXI interconnect - INI x read QoS           register
	AXI_AXI_INI2_READ_QOS_AR_QOS_Pos = 0x0 // Position of AR_QOS field.
	AXI_AXI_INI2_READ_QOS_AR_QOS_Msk = 0xf // Bit mask of AR_QOS field.

	// AXI_INI2_WRITE_QOS: AXI interconnect - INI x write QoS           register
	AXI_AXI_INI2_WRITE_QOS_AW_QOS_Pos = 0x0 // Position of AW_QOS field.
	AXI_AXI_INI2_WRITE_QOS_AW_QOS_Msk = 0xf // Bit mask of AW_QOS field.

	// AXI_INI2_FN_MOD: AXI interconnect - INI x issuing           functionality modification register
	AXI_AXI_INI2_FN_MOD_READ_ISS_OVERRIDE_Pos  = 0x0 // Position of READ_ISS_OVERRIDE field.
	AXI_AXI_INI2_FN_MOD_READ_ISS_OVERRIDE_Msk  = 0x1 // Bit mask of READ_ISS_OVERRIDE field.
	AXI_AXI_INI2_FN_MOD_READ_ISS_OVERRIDE      = 0x1 // Bit READ_ISS_OVERRIDE.
	AXI_AXI_INI2_FN_MOD_WRITE_ISS_OVERRIDE_Pos = 0x1 // Position of WRITE_ISS_OVERRIDE field.
	AXI_AXI_INI2_FN_MOD_WRITE_ISS_OVERRIDE_Msk = 0x2 // Bit mask of WRITE_ISS_OVERRIDE field.
	AXI_AXI_INI2_FN_MOD_WRITE_ISS_OVERRIDE     = 0x2 // Bit WRITE_ISS_OVERRIDE.

	// AXI_INI3_FN_MOD2: AXI interconnect - INI x functionality           modification 2 register
	AXI_AXI_INI3_FN_MOD2_BYPASS_MERGE_Pos = 0x0 // Position of BYPASS_MERGE field.
	AXI_AXI_INI3_FN_MOD2_BYPASS_MERGE_Msk = 0x1 // Bit mask of BYPASS_MERGE field.
	AXI_AXI_INI3_FN_MOD2_BYPASS_MERGE     = 0x1 // Bit BYPASS_MERGE.

	// AXI_INI3_FN_MOD_AHB: AXI interconnect - INI x AHB functionality           modification register
	AXI_AXI_INI3_FN_MOD_AHB_RD_INC_OVERRIDE_Pos = 0x0 // Position of RD_INC_OVERRIDE field.
	AXI_AXI_INI3_FN_MOD_AHB_RD_INC_OVERRIDE_Msk = 0x1 // Bit mask of RD_INC_OVERRIDE field.
	AXI_AXI_INI3_FN_MOD_AHB_RD_INC_OVERRIDE     = 0x1 // Bit RD_INC_OVERRIDE.
	AXI_AXI_INI3_FN_MOD_AHB_WR_INC_OVERRIDE_Pos = 0x1 // Position of WR_INC_OVERRIDE field.
	AXI_AXI_INI3_FN_MOD_AHB_WR_INC_OVERRIDE_Msk = 0x2 // Bit mask of WR_INC_OVERRIDE field.
	AXI_AXI_INI3_FN_MOD_AHB_WR_INC_OVERRIDE     = 0x2 // Bit WR_INC_OVERRIDE.

	// AXI_INI3_READ_QOS: AXI interconnect - INI x read QoS           register
	AXI_AXI_INI3_READ_QOS_AR_QOS_Pos = 0x0 // Position of AR_QOS field.
	AXI_AXI_INI3_READ_QOS_AR_QOS_Msk = 0xf // Bit mask of AR_QOS field.

	// AXI_INI3_WRITE_QOS: AXI interconnect - INI x write QoS           register
	AXI_AXI_INI3_WRITE_QOS_AW_QOS_Pos = 0x0 // Position of AW_QOS field.
	AXI_AXI_INI3_WRITE_QOS_AW_QOS_Msk = 0xf // Bit mask of AW_QOS field.

	// AXI_INI3_FN_MOD: AXI interconnect - INI x issuing           functionality modification register
	AXI_AXI_INI3_FN_MOD_READ_ISS_OVERRIDE_Pos  = 0x0 // Position of READ_ISS_OVERRIDE field.
	AXI_AXI_INI3_FN_MOD_READ_ISS_OVERRIDE_Msk  = 0x1 // Bit mask of READ_ISS_OVERRIDE field.
	AXI_AXI_INI3_FN_MOD_READ_ISS_OVERRIDE      = 0x1 // Bit READ_ISS_OVERRIDE.
	AXI_AXI_INI3_FN_MOD_WRITE_ISS_OVERRIDE_Pos = 0x1 // Position of WRITE_ISS_OVERRIDE field.
	AXI_AXI_INI3_FN_MOD_WRITE_ISS_OVERRIDE_Msk = 0x2 // Bit mask of WRITE_ISS_OVERRIDE field.
	AXI_AXI_INI3_FN_MOD_WRITE_ISS_OVERRIDE     = 0x2 // Bit WRITE_ISS_OVERRIDE.

	// AXI_INI4_READ_QOS: AXI interconnect - INI x read QoS           register
	AXI_AXI_INI4_READ_QOS_AR_QOS_Pos = 0x0 // Position of AR_QOS field.
	AXI_AXI_INI4_READ_QOS_AR_QOS_Msk = 0xf // Bit mask of AR_QOS field.

	// AXI_INI4_WRITE_QOS: AXI interconnect - INI x write QoS           register
	AXI_AXI_INI4_WRITE_QOS_AW_QOS_Pos = 0x0 // Position of AW_QOS field.
	AXI_AXI_INI4_WRITE_QOS_AW_QOS_Msk = 0xf // Bit mask of AW_QOS field.

	// AXI_INI4_FN_MOD: AXI interconnect - INI x issuing           functionality modification register
	AXI_AXI_INI4_FN_MOD_READ_ISS_OVERRIDE_Pos  = 0x0 // Position of READ_ISS_OVERRIDE field.
	AXI_AXI_INI4_FN_MOD_READ_ISS_OVERRIDE_Msk  = 0x1 // Bit mask of READ_ISS_OVERRIDE field.
	AXI_AXI_INI4_FN_MOD_READ_ISS_OVERRIDE      = 0x1 // Bit READ_ISS_OVERRIDE.
	AXI_AXI_INI4_FN_MOD_WRITE_ISS_OVERRIDE_Pos = 0x1 // Position of WRITE_ISS_OVERRIDE field.
	AXI_AXI_INI4_FN_MOD_WRITE_ISS_OVERRIDE_Msk = 0x2 // Bit mask of WRITE_ISS_OVERRIDE field.
	AXI_AXI_INI4_FN_MOD_WRITE_ISS_OVERRIDE     = 0x2 // Bit WRITE_ISS_OVERRIDE.

	// AXI_INI5_READ_QOS: AXI interconnect - INI x read QoS           register
	AXI_AXI_INI5_READ_QOS_AR_QOS_Pos = 0x0 // Position of AR_QOS field.
	AXI_AXI_INI5_READ_QOS_AR_QOS_Msk = 0xf // Bit mask of AR_QOS field.

	// AXI_INI5_WRITE_QOS: AXI interconnect - INI x write QoS           register
	AXI_AXI_INI5_WRITE_QOS_AW_QOS_Pos = 0x0 // Position of AW_QOS field.
	AXI_AXI_INI5_WRITE_QOS_AW_QOS_Msk = 0xf // Bit mask of AW_QOS field.

	// AXI_INI5_FN_MOD: AXI interconnect - INI x issuing           functionality modification register
	AXI_AXI_INI5_FN_MOD_READ_ISS_OVERRIDE_Pos  = 0x0 // Position of READ_ISS_OVERRIDE field.
	AXI_AXI_INI5_FN_MOD_READ_ISS_OVERRIDE_Msk  = 0x1 // Bit mask of READ_ISS_OVERRIDE field.
	AXI_AXI_INI5_FN_MOD_READ_ISS_OVERRIDE      = 0x1 // Bit READ_ISS_OVERRIDE.
	AXI_AXI_INI5_FN_MOD_WRITE_ISS_OVERRIDE_Pos = 0x1 // Position of WRITE_ISS_OVERRIDE field.
	AXI_AXI_INI5_FN_MOD_WRITE_ISS_OVERRIDE_Msk = 0x2 // Bit mask of WRITE_ISS_OVERRIDE field.
	AXI_AXI_INI5_FN_MOD_WRITE_ISS_OVERRIDE     = 0x2 // Bit WRITE_ISS_OVERRIDE.

	// AXI_INI6_READ_QOS: AXI interconnect - INI x read QoS           register
	AXI_AXI_INI6_READ_QOS_AR_QOS_Pos = 0x0 // Position of AR_QOS field.
	AXI_AXI_INI6_READ_QOS_AR_QOS_Msk = 0xf // Bit mask of AR_QOS field.

	// AXI_INI6_WRITE_QOS: AXI interconnect - INI x write QoS           register
	AXI_AXI_INI6_WRITE_QOS_AW_QOS_Pos = 0x0 // Position of AW_QOS field.
	AXI_AXI_INI6_WRITE_QOS_AW_QOS_Msk = 0xf // Bit mask of AW_QOS field.

	// AXI_INI6_FN_MOD: AXI interconnect - INI x issuing           functionality modification register
	AXI_AXI_INI6_FN_MOD_READ_ISS_OVERRIDE_Pos  = 0x0 // Position of READ_ISS_OVERRIDE field.
	AXI_AXI_INI6_FN_MOD_READ_ISS_OVERRIDE_Msk  = 0x1 // Bit mask of READ_ISS_OVERRIDE field.
	AXI_AXI_INI6_FN_MOD_READ_ISS_OVERRIDE      = 0x1 // Bit READ_ISS_OVERRIDE.
	AXI_AXI_INI6_FN_MOD_WRITE_ISS_OVERRIDE_Pos = 0x1 // Position of WRITE_ISS_OVERRIDE field.
	AXI_AXI_INI6_FN_MOD_WRITE_ISS_OVERRIDE_Msk = 0x2 // Bit mask of WRITE_ISS_OVERRIDE field.
	AXI_AXI_INI6_FN_MOD_WRITE_ISS_OVERRIDE     = 0x2 // Bit WRITE_ISS_OVERRIDE.
)

// Bitfields for HASH: Hash processor
const (
	// CR: control register
	HASH_CR_INIT_Pos     = 0x2     // Position of INIT field.
	HASH_CR_INIT_Msk     = 0x4     // Bit mask of INIT field.
	HASH_CR_INIT         = 0x4     // Bit INIT.
	HASH_CR_DMAE_Pos     = 0x3     // Position of DMAE field.
	HASH_CR_DMAE_Msk     = 0x8     // Bit mask of DMAE field.
	HASH_CR_DMAE         = 0x8     // Bit DMAE.
	HASH_CR_DATATYPE_Pos = 0x4     // Position of DATATYPE field.
	HASH_CR_DATATYPE_Msk = 0x30    // Bit mask of DATATYPE field.
	HASH_CR_MODE_Pos     = 0x6     // Position of MODE field.
	HASH_CR_MODE_Msk     = 0x40    // Bit mask of MODE field.
	HASH_CR_MODE         = 0x40    // Bit MODE.
	HASH_CR_ALGO0_Pos    = 0x7     // Position of ALGO0 field.
	HASH_CR_ALGO0_Msk    = 0x80    // Bit mask of ALGO0 field.
	HASH_CR_ALGO0        = 0x80    // Bit ALGO0.
	HASH_CR_NBW_Pos      = 0x8     // Position of NBW field.
	HASH_CR_NBW_Msk      = 0xf00   // Bit mask of NBW field.
	HASH_CR_DINNE_Pos    = 0xc     // Position of DINNE field.
	HASH_CR_DINNE_Msk    = 0x1000  // Bit mask of DINNE field.
	HASH_CR_DINNE        = 0x1000  // Bit DINNE.
	HASH_CR_MDMAT_Pos    = 0xd     // Position of MDMAT field.
	HASH_CR_MDMAT_Msk    = 0x2000  // Bit mask of MDMAT field.
	HASH_CR_MDMAT        = 0x2000  // Bit MDMAT.
	HASH_CR_LKEY_Pos     = 0x10    // Position of LKEY field.
	HASH_CR_LKEY_Msk     = 0x10000 // Bit mask of LKEY field.
	HASH_CR_LKEY         = 0x10000 // Bit LKEY.
	HASH_CR_ALGO1_Pos    = 0x12    // Position of ALGO1 field.
	HASH_CR_ALGO1_Msk    = 0x40000 // Bit mask of ALGO1 field.
	HASH_CR_ALGO1        = 0x40000 // Bit ALGO1.

	// DIN: data input register
	HASH_DIN_DATAIN_Pos = 0x0        // Position of DATAIN field.
	HASH_DIN_DATAIN_Msk = 0xffffffff // Bit mask of DATAIN field.

	// STR: start register
	HASH_STR_DCAL_Pos = 0x8   // Position of DCAL field.
	HASH_STR_DCAL_Msk = 0x100 // Bit mask of DCAL field.
	HASH_STR_DCAL     = 0x100 // Bit DCAL.
	HASH_STR_NBLW_Pos = 0x0   // Position of NBLW field.
	HASH_STR_NBLW_Msk = 0x1f  // Bit mask of NBLW field.

	// HR0: digest registers
	HASH_HR0_H0_Pos = 0x0        // Position of H0 field.
	HASH_HR0_H0_Msk = 0xffffffff // Bit mask of H0 field.

	// HR1: digest registers
	HASH_HR1_H1_Pos = 0x0        // Position of H1 field.
	HASH_HR1_H1_Msk = 0xffffffff // Bit mask of H1 field.

	// HR2: digest registers
	HASH_HR2_H2_Pos = 0x0        // Position of H2 field.
	HASH_HR2_H2_Msk = 0xffffffff // Bit mask of H2 field.

	// HR3: digest registers
	HASH_HR3_H3_Pos = 0x0        // Position of H3 field.
	HASH_HR3_H3_Msk = 0xffffffff // Bit mask of H3 field.

	// HR4: digest registers
	HASH_HR4_H4_Pos = 0x0        // Position of H4 field.
	HASH_HR4_H4_Msk = 0xffffffff // Bit mask of H4 field.

	// IMR: interrupt enable register
	HASH_IMR_DCIE_Pos  = 0x1 // Position of DCIE field.
	HASH_IMR_DCIE_Msk  = 0x2 // Bit mask of DCIE field.
	HASH_IMR_DCIE      = 0x2 // Bit DCIE.
	HASH_IMR_DINIE_Pos = 0x0 // Position of DINIE field.
	HASH_IMR_DINIE_Msk = 0x1 // Bit mask of DINIE field.
	HASH_IMR_DINIE     = 0x1 // Bit DINIE.

	// SR: status register
	HASH_SR_BUSY_Pos  = 0x3 // Position of BUSY field.
	HASH_SR_BUSY_Msk  = 0x8 // Bit mask of BUSY field.
	HASH_SR_BUSY      = 0x8 // Bit BUSY.
	HASH_SR_DMAS_Pos  = 0x2 // Position of DMAS field.
	HASH_SR_DMAS_Msk  = 0x4 // Bit mask of DMAS field.
	HASH_SR_DMAS      = 0x4 // Bit DMAS.
	HASH_SR_DCIS_Pos  = 0x1 // Position of DCIS field.
	HASH_SR_DCIS_Msk  = 0x2 // Bit mask of DCIS field.
	HASH_SR_DCIS      = 0x2 // Bit DCIS.
	HASH_SR_DINIS_Pos = 0x0 // Position of DINIS field.
	HASH_SR_DINIS_Msk = 0x1 // Bit mask of DINIS field.
	HASH_SR_DINIS     = 0x1 // Bit DINIS.

	// CSR0: context swap registers
	HASH_CSR0_CSR0_Pos = 0x0        // Position of CSR0 field.
	HASH_CSR0_CSR0_Msk = 0xffffffff // Bit mask of CSR0 field.

	// CSR1: context swap registers
	HASH_CSR1_CSR1_Pos = 0x0        // Position of CSR1 field.
	HASH_CSR1_CSR1_Msk = 0xffffffff // Bit mask of CSR1 field.

	// CSR2: context swap registers
	HASH_CSR2_CSR2_Pos = 0x0        // Position of CSR2 field.
	HASH_CSR2_CSR2_Msk = 0xffffffff // Bit mask of CSR2 field.

	// CSR3: context swap registers
	HASH_CSR3_CSR3_Pos = 0x0        // Position of CSR3 field.
	HASH_CSR3_CSR3_Msk = 0xffffffff // Bit mask of CSR3 field.

	// CSR4: context swap registers
	HASH_CSR4_CSR4_Pos = 0x0        // Position of CSR4 field.
	HASH_CSR4_CSR4_Msk = 0xffffffff // Bit mask of CSR4 field.

	// CSR5: context swap registers
	HASH_CSR5_CSR5_Pos = 0x0        // Position of CSR5 field.
	HASH_CSR5_CSR5_Msk = 0xffffffff // Bit mask of CSR5 field.

	// CSR6: context swap registers
	HASH_CSR6_CSR6_Pos = 0x0        // Position of CSR6 field.
	HASH_CSR6_CSR6_Msk = 0xffffffff // Bit mask of CSR6 field.

	// CSR7: context swap registers
	HASH_CSR7_CSR7_Pos = 0x0        // Position of CSR7 field.
	HASH_CSR7_CSR7_Msk = 0xffffffff // Bit mask of CSR7 field.

	// CSR8: context swap registers
	HASH_CSR8_CSR8_Pos = 0x0        // Position of CSR8 field.
	HASH_CSR8_CSR8_Msk = 0xffffffff // Bit mask of CSR8 field.

	// CSR9: context swap registers
	HASH_CSR9_CSR9_Pos = 0x0        // Position of CSR9 field.
	HASH_CSR9_CSR9_Msk = 0xffffffff // Bit mask of CSR9 field.

	// CSR10: context swap registers
	HASH_CSR10_CSR10_Pos = 0x0        // Position of CSR10 field.
	HASH_CSR10_CSR10_Msk = 0xffffffff // Bit mask of CSR10 field.

	// CSR11: context swap registers
	HASH_CSR11_CSR11_Pos = 0x0        // Position of CSR11 field.
	HASH_CSR11_CSR11_Msk = 0xffffffff // Bit mask of CSR11 field.

	// CSR12: context swap registers
	HASH_CSR12_CSR12_Pos = 0x0        // Position of CSR12 field.
	HASH_CSR12_CSR12_Msk = 0xffffffff // Bit mask of CSR12 field.

	// CSR13: context swap registers
	HASH_CSR13_CSR13_Pos = 0x0        // Position of CSR13 field.
	HASH_CSR13_CSR13_Msk = 0xffffffff // Bit mask of CSR13 field.

	// CSR14: context swap registers
	HASH_CSR14_CSR14_Pos = 0x0        // Position of CSR14 field.
	HASH_CSR14_CSR14_Msk = 0xffffffff // Bit mask of CSR14 field.

	// CSR15: context swap registers
	HASH_CSR15_CSR15_Pos = 0x0        // Position of CSR15 field.
	HASH_CSR15_CSR15_Msk = 0xffffffff // Bit mask of CSR15 field.

	// CSR16: context swap registers
	HASH_CSR16_CSR16_Pos = 0x0        // Position of CSR16 field.
	HASH_CSR16_CSR16_Msk = 0xffffffff // Bit mask of CSR16 field.

	// CSR17: context swap registers
	HASH_CSR17_CSR17_Pos = 0x0        // Position of CSR17 field.
	HASH_CSR17_CSR17_Msk = 0xffffffff // Bit mask of CSR17 field.

	// CSR18: context swap registers
	HASH_CSR18_CSR18_Pos = 0x0        // Position of CSR18 field.
	HASH_CSR18_CSR18_Msk = 0xffffffff // Bit mask of CSR18 field.

	// CSR19: context swap registers
	HASH_CSR19_CSR19_Pos = 0x0        // Position of CSR19 field.
	HASH_CSR19_CSR19_Msk = 0xffffffff // Bit mask of CSR19 field.

	// CSR20: context swap registers
	HASH_CSR20_CSR20_Pos = 0x0        // Position of CSR20 field.
	HASH_CSR20_CSR20_Msk = 0xffffffff // Bit mask of CSR20 field.

	// CSR21: context swap registers
	HASH_CSR21_CSR21_Pos = 0x0        // Position of CSR21 field.
	HASH_CSR21_CSR21_Msk = 0xffffffff // Bit mask of CSR21 field.

	// CSR22: context swap registers
	HASH_CSR22_CSR22_Pos = 0x0        // Position of CSR22 field.
	HASH_CSR22_CSR22_Msk = 0xffffffff // Bit mask of CSR22 field.

	// CSR23: context swap registers
	HASH_CSR23_CSR23_Pos = 0x0        // Position of CSR23 field.
	HASH_CSR23_CSR23_Msk = 0xffffffff // Bit mask of CSR23 field.

	// CSR24: context swap registers
	HASH_CSR24_CSR24_Pos = 0x0        // Position of CSR24 field.
	HASH_CSR24_CSR24_Msk = 0xffffffff // Bit mask of CSR24 field.

	// CSR25: context swap registers
	HASH_CSR25_CSR25_Pos = 0x0        // Position of CSR25 field.
	HASH_CSR25_CSR25_Msk = 0xffffffff // Bit mask of CSR25 field.

	// CSR26: context swap registers
	HASH_CSR26_CSR26_Pos = 0x0        // Position of CSR26 field.
	HASH_CSR26_CSR26_Msk = 0xffffffff // Bit mask of CSR26 field.

	// CSR27: context swap registers
	HASH_CSR27_CSR27_Pos = 0x0        // Position of CSR27 field.
	HASH_CSR27_CSR27_Msk = 0xffffffff // Bit mask of CSR27 field.

	// CSR28: context swap registers
	HASH_CSR28_CSR28_Pos = 0x0        // Position of CSR28 field.
	HASH_CSR28_CSR28_Msk = 0xffffffff // Bit mask of CSR28 field.

	// CSR29: context swap registers
	HASH_CSR29_CSR29_Pos = 0x0        // Position of CSR29 field.
	HASH_CSR29_CSR29_Msk = 0xffffffff // Bit mask of CSR29 field.

	// CSR30: context swap registers
	HASH_CSR30_CSR30_Pos = 0x0        // Position of CSR30 field.
	HASH_CSR30_CSR30_Msk = 0xffffffff // Bit mask of CSR30 field.

	// CSR31: context swap registers
	HASH_CSR31_CSR31_Pos = 0x0        // Position of CSR31 field.
	HASH_CSR31_CSR31_Msk = 0xffffffff // Bit mask of CSR31 field.

	// CSR32: context swap registers
	HASH_CSR32_CSR32_Pos = 0x0        // Position of CSR32 field.
	HASH_CSR32_CSR32_Msk = 0xffffffff // Bit mask of CSR32 field.

	// CSR33: context swap registers
	HASH_CSR33_CSR33_Pos = 0x0        // Position of CSR33 field.
	HASH_CSR33_CSR33_Msk = 0xffffffff // Bit mask of CSR33 field.

	// CSR34: context swap registers
	HASH_CSR34_CSR34_Pos = 0x0        // Position of CSR34 field.
	HASH_CSR34_CSR34_Msk = 0xffffffff // Bit mask of CSR34 field.

	// CSR35: context swap registers
	HASH_CSR35_CSR35_Pos = 0x0        // Position of CSR35 field.
	HASH_CSR35_CSR35_Msk = 0xffffffff // Bit mask of CSR35 field.

	// CSR36: context swap registers
	HASH_CSR36_CSR36_Pos = 0x0        // Position of CSR36 field.
	HASH_CSR36_CSR36_Msk = 0xffffffff // Bit mask of CSR36 field.

	// CSR37: context swap registers
	HASH_CSR37_CSR37_Pos = 0x0        // Position of CSR37 field.
	HASH_CSR37_CSR37_Msk = 0xffffffff // Bit mask of CSR37 field.

	// CSR38: context swap registers
	HASH_CSR38_CSR38_Pos = 0x0        // Position of CSR38 field.
	HASH_CSR38_CSR38_Msk = 0xffffffff // Bit mask of CSR38 field.

	// CSR39: context swap registers
	HASH_CSR39_CSR39_Pos = 0x0        // Position of CSR39 field.
	HASH_CSR39_CSR39_Msk = 0xffffffff // Bit mask of CSR39 field.

	// CSR40: context swap registers
	HASH_CSR40_CSR40_Pos = 0x0        // Position of CSR40 field.
	HASH_CSR40_CSR40_Msk = 0xffffffff // Bit mask of CSR40 field.

	// CSR41: context swap registers
	HASH_CSR41_CSR41_Pos = 0x0        // Position of CSR41 field.
	HASH_CSR41_CSR41_Msk = 0xffffffff // Bit mask of CSR41 field.

	// CSR42: context swap registers
	HASH_CSR42_CSR42_Pos = 0x0        // Position of CSR42 field.
	HASH_CSR42_CSR42_Msk = 0xffffffff // Bit mask of CSR42 field.

	// CSR43: context swap registers
	HASH_CSR43_CSR43_Pos = 0x0        // Position of CSR43 field.
	HASH_CSR43_CSR43_Msk = 0xffffffff // Bit mask of CSR43 field.

	// CSR44: context swap registers
	HASH_CSR44_CSR44_Pos = 0x0        // Position of CSR44 field.
	HASH_CSR44_CSR44_Msk = 0xffffffff // Bit mask of CSR44 field.

	// CSR45: context swap registers
	HASH_CSR45_CSR45_Pos = 0x0        // Position of CSR45 field.
	HASH_CSR45_CSR45_Msk = 0xffffffff // Bit mask of CSR45 field.

	// CSR46: context swap registers
	HASH_CSR46_CSR46_Pos = 0x0        // Position of CSR46 field.
	HASH_CSR46_CSR46_Msk = 0xffffffff // Bit mask of CSR46 field.

	// CSR47: context swap registers
	HASH_CSR47_CSR47_Pos = 0x0        // Position of CSR47 field.
	HASH_CSR47_CSR47_Msk = 0xffffffff // Bit mask of CSR47 field.

	// CSR48: context swap registers
	HASH_CSR48_CSR48_Pos = 0x0        // Position of CSR48 field.
	HASH_CSR48_CSR48_Msk = 0xffffffff // Bit mask of CSR48 field.

	// CSR49: context swap registers
	HASH_CSR49_CSR49_Pos = 0x0        // Position of CSR49 field.
	HASH_CSR49_CSR49_Msk = 0xffffffff // Bit mask of CSR49 field.

	// CSR50: context swap registers
	HASH_CSR50_CSR50_Pos = 0x0        // Position of CSR50 field.
	HASH_CSR50_CSR50_Msk = 0xffffffff // Bit mask of CSR50 field.

	// CSR51: context swap registers
	HASH_CSR51_CSR51_Pos = 0x0        // Position of CSR51 field.
	HASH_CSR51_CSR51_Msk = 0xffffffff // Bit mask of CSR51 field.

	// CSR52: context swap registers
	HASH_CSR52_CSR52_Pos = 0x0        // Position of CSR52 field.
	HASH_CSR52_CSR52_Msk = 0xffffffff // Bit mask of CSR52 field.

	// CSR53: context swap registers
	HASH_CSR53_CSR53_Pos = 0x0        // Position of CSR53 field.
	HASH_CSR53_CSR53_Msk = 0xffffffff // Bit mask of CSR53 field.

	// HASH_HR0: HASH digest register
	HASH_HASH_HR0_H0_Pos = 0x0        // Position of H0 field.
	HASH_HASH_HR0_H0_Msk = 0xffffffff // Bit mask of H0 field.

	// HASH_HR1: read-only
	HASH_HASH_HR1_H1_Pos = 0x0        // Position of H1 field.
	HASH_HASH_HR1_H1_Msk = 0xffffffff // Bit mask of H1 field.

	// HASH_HR2: read-only
	HASH_HASH_HR2_H2_Pos = 0x0        // Position of H2 field.
	HASH_HASH_HR2_H2_Msk = 0xffffffff // Bit mask of H2 field.

	// HASH_HR3: read-only
	HASH_HASH_HR3_H3_Pos = 0x0        // Position of H3 field.
	HASH_HASH_HR3_H3_Msk = 0xffffffff // Bit mask of H3 field.

	// HASH_HR4: read-only
	HASH_HASH_HR4_H4_Pos = 0x0        // Position of H4 field.
	HASH_HASH_HR4_H4_Msk = 0xffffffff // Bit mask of H4 field.

	// HASH_HR5: read-only
	HASH_HASH_HR5_H5_Pos = 0x0        // Position of H5 field.
	HASH_HASH_HR5_H5_Msk = 0xffffffff // Bit mask of H5 field.

	// HASH_HR6: read-only
	HASH_HASH_HR6_H6_Pos = 0x0        // Position of H6 field.
	HASH_HASH_HR6_H6_Msk = 0xffffffff // Bit mask of H6 field.

	// HASH_HR7: read-only
	HASH_HASH_HR7_H7_Pos = 0x0        // Position of H7 field.
	HASH_HASH_HR7_H7_Msk = 0xffffffff // Bit mask of H7 field.
)

// Bitfields for CRYP: Cryptographic processor
const (
	// CR: control register
	CRYP_CR_ALGODIR_Pos   = 0x2     // Position of ALGODIR field.
	CRYP_CR_ALGODIR_Msk   = 0x4     // Bit mask of ALGODIR field.
	CRYP_CR_ALGODIR       = 0x4     // Bit ALGODIR.
	CRYP_CR_ALGOMODE0_Pos = 0x3     // Position of ALGOMODE0 field.
	CRYP_CR_ALGOMODE0_Msk = 0x38    // Bit mask of ALGOMODE0 field.
	CRYP_CR_DATATYPE_Pos  = 0x6     // Position of DATATYPE field.
	CRYP_CR_DATATYPE_Msk  = 0xc0    // Bit mask of DATATYPE field.
	CRYP_CR_KEYSIZE_Pos   = 0x8     // Position of KEYSIZE field.
	CRYP_CR_KEYSIZE_Msk   = 0x300   // Bit mask of KEYSIZE field.
	CRYP_CR_FFLUSH_Pos    = 0xe     // Position of FFLUSH field.
	CRYP_CR_FFLUSH_Msk    = 0x4000  // Bit mask of FFLUSH field.
	CRYP_CR_FFLUSH        = 0x4000  // Bit FFLUSH.
	CRYP_CR_CRYPEN_Pos    = 0xf     // Position of CRYPEN field.
	CRYP_CR_CRYPEN_Msk    = 0x8000  // Bit mask of CRYPEN field.
	CRYP_CR_CRYPEN        = 0x8000  // Bit CRYPEN.
	CRYP_CR_GCM_CCMPH_Pos = 0x10    // Position of GCM_CCMPH field.
	CRYP_CR_GCM_CCMPH_Msk = 0x30000 // Bit mask of GCM_CCMPH field.
	CRYP_CR_ALGOMODE3_Pos = 0x13    // Position of ALGOMODE3 field.
	CRYP_CR_ALGOMODE3_Msk = 0x80000 // Bit mask of ALGOMODE3 field.
	CRYP_CR_ALGOMODE3     = 0x80000 // Bit ALGOMODE3.

	// SR: status register
	CRYP_SR_BUSY_Pos = 0x4  // Position of BUSY field.
	CRYP_SR_BUSY_Msk = 0x10 // Bit mask of BUSY field.
	CRYP_SR_BUSY     = 0x10 // Bit BUSY.
	CRYP_SR_OFFU_Pos = 0x3  // Position of OFFU field.
	CRYP_SR_OFFU_Msk = 0x8  // Bit mask of OFFU field.
	CRYP_SR_OFFU     = 0x8  // Bit OFFU.
	CRYP_SR_OFNE_Pos = 0x2  // Position of OFNE field.
	CRYP_SR_OFNE_Msk = 0x4  // Bit mask of OFNE field.
	CRYP_SR_OFNE     = 0x4  // Bit OFNE.
	CRYP_SR_IFNF_Pos = 0x1  // Position of IFNF field.
	CRYP_SR_IFNF_Msk = 0x2  // Bit mask of IFNF field.
	CRYP_SR_IFNF     = 0x2  // Bit IFNF.
	CRYP_SR_IFEM_Pos = 0x0  // Position of IFEM field.
	CRYP_SR_IFEM_Msk = 0x1  // Bit mask of IFEM field.
	CRYP_SR_IFEM     = 0x1  // Bit IFEM.

	// DIN: data input register
	CRYP_DIN_DATAIN_Pos = 0x0        // Position of DATAIN field.
	CRYP_DIN_DATAIN_Msk = 0xffffffff // Bit mask of DATAIN field.

	// DOUT: data output register
	CRYP_DOUT_DATAOUT_Pos = 0x0        // Position of DATAOUT field.
	CRYP_DOUT_DATAOUT_Msk = 0xffffffff // Bit mask of DATAOUT field.

	// DMACR: DMA control register
	CRYP_DMACR_DOEN_Pos = 0x1 // Position of DOEN field.
	CRYP_DMACR_DOEN_Msk = 0x2 // Bit mask of DOEN field.
	CRYP_DMACR_DOEN     = 0x2 // Bit DOEN.
	CRYP_DMACR_DIEN_Pos = 0x0 // Position of DIEN field.
	CRYP_DMACR_DIEN_Msk = 0x1 // Bit mask of DIEN field.
	CRYP_DMACR_DIEN     = 0x1 // Bit DIEN.

	// IMSCR: interrupt mask set/clear           register
	CRYP_IMSCR_OUTIM_Pos = 0x1 // Position of OUTIM field.
	CRYP_IMSCR_OUTIM_Msk = 0x2 // Bit mask of OUTIM field.
	CRYP_IMSCR_OUTIM     = 0x2 // Bit OUTIM.
	CRYP_IMSCR_INIM_Pos  = 0x0 // Position of INIM field.
	CRYP_IMSCR_INIM_Msk  = 0x1 // Bit mask of INIM field.
	CRYP_IMSCR_INIM      = 0x1 // Bit INIM.

	// RISR: raw interrupt status register
	CRYP_RISR_OUTRIS_Pos = 0x1 // Position of OUTRIS field.
	CRYP_RISR_OUTRIS_Msk = 0x2 // Bit mask of OUTRIS field.
	CRYP_RISR_OUTRIS     = 0x2 // Bit OUTRIS.
	CRYP_RISR_INRIS_Pos  = 0x0 // Position of INRIS field.
	CRYP_RISR_INRIS_Msk  = 0x1 // Bit mask of INRIS field.
	CRYP_RISR_INRIS      = 0x1 // Bit INRIS.

	// MISR: masked interrupt status           register
	CRYP_MISR_OUTMIS_Pos = 0x1 // Position of OUTMIS field.
	CRYP_MISR_OUTMIS_Msk = 0x2 // Bit mask of OUTMIS field.
	CRYP_MISR_OUTMIS     = 0x2 // Bit OUTMIS.
	CRYP_MISR_INMIS_Pos  = 0x0 // Position of INMIS field.
	CRYP_MISR_INMIS_Msk  = 0x1 // Bit mask of INMIS field.
	CRYP_MISR_INMIS      = 0x1 // Bit INMIS.

	// K0LR: key registers
	CRYP_K0LR_K224_Pos = 0x0        // Position of K224 field.
	CRYP_K0LR_K224_Msk = 0x1        // Bit mask of K224 field.
	CRYP_K0LR_K224     = 0x1        // Bit K224.
	CRYP_K0LR_K225_Pos = 0x1        // Position of K225 field.
	CRYP_K0LR_K225_Msk = 0x2        // Bit mask of K225 field.
	CRYP_K0LR_K225     = 0x2        // Bit K225.
	CRYP_K0LR_K226_Pos = 0x2        // Position of K226 field.
	CRYP_K0LR_K226_Msk = 0x4        // Bit mask of K226 field.
	CRYP_K0LR_K226     = 0x4        // Bit K226.
	CRYP_K0LR_K227_Pos = 0x3        // Position of K227 field.
	CRYP_K0LR_K227_Msk = 0x8        // Bit mask of K227 field.
	CRYP_K0LR_K227     = 0x8        // Bit K227.
	CRYP_K0LR_K228_Pos = 0x4        // Position of K228 field.
	CRYP_K0LR_K228_Msk = 0x10       // Bit mask of K228 field.
	CRYP_K0LR_K228     = 0x10       // Bit K228.
	CRYP_K0LR_K229_Pos = 0x5        // Position of K229 field.
	CRYP_K0LR_K229_Msk = 0x20       // Bit mask of K229 field.
	CRYP_K0LR_K229     = 0x20       // Bit K229.
	CRYP_K0LR_K230_Pos = 0x6        // Position of K230 field.
	CRYP_K0LR_K230_Msk = 0x40       // Bit mask of K230 field.
	CRYP_K0LR_K230     = 0x40       // Bit K230.
	CRYP_K0LR_K231_Pos = 0x7        // Position of K231 field.
	CRYP_K0LR_K231_Msk = 0x80       // Bit mask of K231 field.
	CRYP_K0LR_K231     = 0x80       // Bit K231.
	CRYP_K0LR_K232_Pos = 0x8        // Position of K232 field.
	CRYP_K0LR_K232_Msk = 0x100      // Bit mask of K232 field.
	CRYP_K0LR_K232     = 0x100      // Bit K232.
	CRYP_K0LR_K233_Pos = 0x9        // Position of K233 field.
	CRYP_K0LR_K233_Msk = 0x200      // Bit mask of K233 field.
	CRYP_K0LR_K233     = 0x200      // Bit K233.
	CRYP_K0LR_K234_Pos = 0xa        // Position of K234 field.
	CRYP_K0LR_K234_Msk = 0x400      // Bit mask of K234 field.
	CRYP_K0LR_K234     = 0x400      // Bit K234.
	CRYP_K0LR_K235_Pos = 0xb        // Position of K235 field.
	CRYP_K0LR_K235_Msk = 0x800      // Bit mask of K235 field.
	CRYP_K0LR_K235     = 0x800      // Bit K235.
	CRYP_K0LR_K236_Pos = 0xc        // Position of K236 field.
	CRYP_K0LR_K236_Msk = 0x1000     // Bit mask of K236 field.
	CRYP_K0LR_K236     = 0x1000     // Bit K236.
	CRYP_K0LR_K237_Pos = 0xd        // Position of K237 field.
	CRYP_K0LR_K237_Msk = 0x2000     // Bit mask of K237 field.
	CRYP_K0LR_K237     = 0x2000     // Bit K237.
	CRYP_K0LR_K238_Pos = 0xe        // Position of K238 field.
	CRYP_K0LR_K238_Msk = 0x4000     // Bit mask of K238 field.
	CRYP_K0LR_K238     = 0x4000     // Bit K238.
	CRYP_K0LR_K239_Pos = 0xf        // Position of K239 field.
	CRYP_K0LR_K239_Msk = 0x8000     // Bit mask of K239 field.
	CRYP_K0LR_K239     = 0x8000     // Bit K239.
	CRYP_K0LR_K240_Pos = 0x10       // Position of K240 field.
	CRYP_K0LR_K240_Msk = 0x10000    // Bit mask of K240 field.
	CRYP_K0LR_K240     = 0x10000    // Bit K240.
	CRYP_K0LR_K241_Pos = 0x11       // Position of K241 field.
	CRYP_K0LR_K241_Msk = 0x20000    // Bit mask of K241 field.
	CRYP_K0LR_K241     = 0x20000    // Bit K241.
	CRYP_K0LR_K242_Pos = 0x12       // Position of K242 field.
	CRYP_K0LR_K242_Msk = 0x40000    // Bit mask of K242 field.
	CRYP_K0LR_K242     = 0x40000    // Bit K242.
	CRYP_K0LR_K243_Pos = 0x13       // Position of K243 field.
	CRYP_K0LR_K243_Msk = 0x80000    // Bit mask of K243 field.
	CRYP_K0LR_K243     = 0x80000    // Bit K243.
	CRYP_K0LR_K244_Pos = 0x14       // Position of K244 field.
	CRYP_K0LR_K244_Msk = 0x100000   // Bit mask of K244 field.
	CRYP_K0LR_K244     = 0x100000   // Bit K244.
	CRYP_K0LR_K245_Pos = 0x15       // Position of K245 field.
	CRYP_K0LR_K245_Msk = 0x200000   // Bit mask of K245 field.
	CRYP_K0LR_K245     = 0x200000   // Bit K245.
	CRYP_K0LR_K246_Pos = 0x16       // Position of K246 field.
	CRYP_K0LR_K246_Msk = 0x400000   // Bit mask of K246 field.
	CRYP_K0LR_K246     = 0x400000   // Bit K246.
	CRYP_K0LR_K247_Pos = 0x17       // Position of K247 field.
	CRYP_K0LR_K247_Msk = 0x800000   // Bit mask of K247 field.
	CRYP_K0LR_K247     = 0x800000   // Bit K247.
	CRYP_K0LR_K248_Pos = 0x18       // Position of K248 field.
	CRYP_K0LR_K248_Msk = 0x1000000  // Bit mask of K248 field.
	CRYP_K0LR_K248     = 0x1000000  // Bit K248.
	CRYP_K0LR_K249_Pos = 0x19       // Position of K249 field.
	CRYP_K0LR_K249_Msk = 0x2000000  // Bit mask of K249 field.
	CRYP_K0LR_K249     = 0x2000000  // Bit K249.
	CRYP_K0LR_K250_Pos = 0x1a       // Position of K250 field.
	CRYP_K0LR_K250_Msk = 0x4000000  // Bit mask of K250 field.
	CRYP_K0LR_K250     = 0x4000000  // Bit K250.
	CRYP_K0LR_K251_Pos = 0x1b       // Position of K251 field.
	CRYP_K0LR_K251_Msk = 0x8000000  // Bit mask of K251 field.
	CRYP_K0LR_K251     = 0x8000000  // Bit K251.
	CRYP_K0LR_K252_Pos = 0x1c       // Position of K252 field.
	CRYP_K0LR_K252_Msk = 0x10000000 // Bit mask of K252 field.
	CRYP_K0LR_K252     = 0x10000000 // Bit K252.
	CRYP_K0LR_K253_Pos = 0x1d       // Position of K253 field.
	CRYP_K0LR_K253_Msk = 0x20000000 // Bit mask of K253 field.
	CRYP_K0LR_K253     = 0x20000000 // Bit K253.
	CRYP_K0LR_K254_Pos = 0x1e       // Position of K254 field.
	CRYP_K0LR_K254_Msk = 0x40000000 // Bit mask of K254 field.
	CRYP_K0LR_K254     = 0x40000000 // Bit K254.
	CRYP_K0LR_K255_Pos = 0x1f       // Position of K255 field.
	CRYP_K0LR_K255_Msk = 0x80000000 // Bit mask of K255 field.
	CRYP_K0LR_K255     = 0x80000000 // Bit K255.

	// K0RR: key registers
	CRYP_K0RR_K192_Pos = 0x0        // Position of K192 field.
	CRYP_K0RR_K192_Msk = 0x1        // Bit mask of K192 field.
	CRYP_K0RR_K192     = 0x1        // Bit K192.
	CRYP_K0RR_K193_Pos = 0x1        // Position of K193 field.
	CRYP_K0RR_K193_Msk = 0x2        // Bit mask of K193 field.
	CRYP_K0RR_K193     = 0x2        // Bit K193.
	CRYP_K0RR_K194_Pos = 0x2        // Position of K194 field.
	CRYP_K0RR_K194_Msk = 0x4        // Bit mask of K194 field.
	CRYP_K0RR_K194     = 0x4        // Bit K194.
	CRYP_K0RR_K195_Pos = 0x3        // Position of K195 field.
	CRYP_K0RR_K195_Msk = 0x8        // Bit mask of K195 field.
	CRYP_K0RR_K195     = 0x8        // Bit K195.
	CRYP_K0RR_K196_Pos = 0x4        // Position of K196 field.
	CRYP_K0RR_K196_Msk = 0x10       // Bit mask of K196 field.
	CRYP_K0RR_K196     = 0x10       // Bit K196.
	CRYP_K0RR_K197_Pos = 0x5        // Position of K197 field.
	CRYP_K0RR_K197_Msk = 0x20       // Bit mask of K197 field.
	CRYP_K0RR_K197     = 0x20       // Bit K197.
	CRYP_K0RR_K198_Pos = 0x6        // Position of K198 field.
	CRYP_K0RR_K198_Msk = 0x40       // Bit mask of K198 field.
	CRYP_K0RR_K198     = 0x40       // Bit K198.
	CRYP_K0RR_K199_Pos = 0x7        // Position of K199 field.
	CRYP_K0RR_K199_Msk = 0x80       // Bit mask of K199 field.
	CRYP_K0RR_K199     = 0x80       // Bit K199.
	CRYP_K0RR_K200_Pos = 0x8        // Position of K200 field.
	CRYP_K0RR_K200_Msk = 0x100      // Bit mask of K200 field.
	CRYP_K0RR_K200     = 0x100      // Bit K200.
	CRYP_K0RR_K201_Pos = 0x9        // Position of K201 field.
	CRYP_K0RR_K201_Msk = 0x200      // Bit mask of K201 field.
	CRYP_K0RR_K201     = 0x200      // Bit K201.
	CRYP_K0RR_K202_Pos = 0xa        // Position of K202 field.
	CRYP_K0RR_K202_Msk = 0x400      // Bit mask of K202 field.
	CRYP_K0RR_K202     = 0x400      // Bit K202.
	CRYP_K0RR_K203_Pos = 0xb        // Position of K203 field.
	CRYP_K0RR_K203_Msk = 0x800      // Bit mask of K203 field.
	CRYP_K0RR_K203     = 0x800      // Bit K203.
	CRYP_K0RR_K204_Pos = 0xc        // Position of K204 field.
	CRYP_K0RR_K204_Msk = 0x1000     // Bit mask of K204 field.
	CRYP_K0RR_K204     = 0x1000     // Bit K204.
	CRYP_K0RR_K205_Pos = 0xd        // Position of K205 field.
	CRYP_K0RR_K205_Msk = 0x2000     // Bit mask of K205 field.
	CRYP_K0RR_K205     = 0x2000     // Bit K205.
	CRYP_K0RR_K206_Pos = 0xe        // Position of K206 field.
	CRYP_K0RR_K206_Msk = 0x4000     // Bit mask of K206 field.
	CRYP_K0RR_K206     = 0x4000     // Bit K206.
	CRYP_K0RR_K207_Pos = 0xf        // Position of K207 field.
	CRYP_K0RR_K207_Msk = 0x8000     // Bit mask of K207 field.
	CRYP_K0RR_K207     = 0x8000     // Bit K207.
	CRYP_K0RR_K208_Pos = 0x10       // Position of K208 field.
	CRYP_K0RR_K208_Msk = 0x10000    // Bit mask of K208 field.
	CRYP_K0RR_K208     = 0x10000    // Bit K208.
	CRYP_K0RR_K209_Pos = 0x11       // Position of K209 field.
	CRYP_K0RR_K209_Msk = 0x20000    // Bit mask of K209 field.
	CRYP_K0RR_K209     = 0x20000    // Bit K209.
	CRYP_K0RR_K210_Pos = 0x12       // Position of K210 field.
	CRYP_K0RR_K210_Msk = 0x40000    // Bit mask of K210 field.
	CRYP_K0RR_K210     = 0x40000    // Bit K210.
	CRYP_K0RR_K211_Pos = 0x13       // Position of K211 field.
	CRYP_K0RR_K211_Msk = 0x80000    // Bit mask of K211 field.
	CRYP_K0RR_K211     = 0x80000    // Bit K211.
	CRYP_K0RR_K212_Pos = 0x14       // Position of K212 field.
	CRYP_K0RR_K212_Msk = 0x100000   // Bit mask of K212 field.
	CRYP_K0RR_K212     = 0x100000   // Bit K212.
	CRYP_K0RR_K213_Pos = 0x15       // Position of K213 field.
	CRYP_K0RR_K213_Msk = 0x200000   // Bit mask of K213 field.
	CRYP_K0RR_K213     = 0x200000   // Bit K213.
	CRYP_K0RR_K214_Pos = 0x16       // Position of K214 field.
	CRYP_K0RR_K214_Msk = 0x400000   // Bit mask of K214 field.
	CRYP_K0RR_K214     = 0x400000   // Bit K214.
	CRYP_K0RR_K215_Pos = 0x17       // Position of K215 field.
	CRYP_K0RR_K215_Msk = 0x800000   // Bit mask of K215 field.
	CRYP_K0RR_K215     = 0x800000   // Bit K215.
	CRYP_K0RR_K216_Pos = 0x18       // Position of K216 field.
	CRYP_K0RR_K216_Msk = 0x1000000  // Bit mask of K216 field.
	CRYP_K0RR_K216     = 0x1000000  // Bit K216.
	CRYP_K0RR_K217_Pos = 0x19       // Position of K217 field.
	CRYP_K0RR_K217_Msk = 0x2000000  // Bit mask of K217 field.
	CRYP_K0RR_K217     = 0x2000000  // Bit K217.
	CRYP_K0RR_K218_Pos = 0x1a       // Position of K218 field.
	CRYP_K0RR_K218_Msk = 0x4000000  // Bit mask of K218 field.
	CRYP_K0RR_K218     = 0x4000000  // Bit K218.
	CRYP_K0RR_K219_Pos = 0x1b       // Position of K219 field.
	CRYP_K0RR_K219_Msk = 0x8000000  // Bit mask of K219 field.
	CRYP_K0RR_K219     = 0x8000000  // Bit K219.
	CRYP_K0RR_K220_Pos = 0x1c       // Position of K220 field.
	CRYP_K0RR_K220_Msk = 0x10000000 // Bit mask of K220 field.
	CRYP_K0RR_K220     = 0x10000000 // Bit K220.
	CRYP_K0RR_K221_Pos = 0x1d       // Position of K221 field.
	CRYP_K0RR_K221_Msk = 0x20000000 // Bit mask of K221 field.
	CRYP_K0RR_K221     = 0x20000000 // Bit K221.
	CRYP_K0RR_K222_Pos = 0x1e       // Position of K222 field.
	CRYP_K0RR_K222_Msk = 0x40000000 // Bit mask of K222 field.
	CRYP_K0RR_K222     = 0x40000000 // Bit K222.
	CRYP_K0RR_K223_Pos = 0x1f       // Position of K223 field.
	CRYP_K0RR_K223_Msk = 0x80000000 // Bit mask of K223 field.
	CRYP_K0RR_K223     = 0x80000000 // Bit K223.

	// K1LR: key registers
	CRYP_K1LR_K160_Pos = 0x0        // Position of K160 field.
	CRYP_K1LR_K160_Msk = 0x1        // Bit mask of K160 field.
	CRYP_K1LR_K160     = 0x1        // Bit K160.
	CRYP_K1LR_K161_Pos = 0x1        // Position of K161 field.
	CRYP_K1LR_K161_Msk = 0x2        // Bit mask of K161 field.
	CRYP_K1LR_K161     = 0x2        // Bit K161.
	CRYP_K1LR_K162_Pos = 0x2        // Position of K162 field.
	CRYP_K1LR_K162_Msk = 0x4        // Bit mask of K162 field.
	CRYP_K1LR_K162     = 0x4        // Bit K162.
	CRYP_K1LR_K163_Pos = 0x3        // Position of K163 field.
	CRYP_K1LR_K163_Msk = 0x8        // Bit mask of K163 field.
	CRYP_K1LR_K163     = 0x8        // Bit K163.
	CRYP_K1LR_K164_Pos = 0x4        // Position of K164 field.
	CRYP_K1LR_K164_Msk = 0x10       // Bit mask of K164 field.
	CRYP_K1LR_K164     = 0x10       // Bit K164.
	CRYP_K1LR_K165_Pos = 0x5        // Position of K165 field.
	CRYP_K1LR_K165_Msk = 0x20       // Bit mask of K165 field.
	CRYP_K1LR_K165     = 0x20       // Bit K165.
	CRYP_K1LR_K166_Pos = 0x6        // Position of K166 field.
	CRYP_K1LR_K166_Msk = 0x40       // Bit mask of K166 field.
	CRYP_K1LR_K166     = 0x40       // Bit K166.
	CRYP_K1LR_K167_Pos = 0x7        // Position of K167 field.
	CRYP_K1LR_K167_Msk = 0x80       // Bit mask of K167 field.
	CRYP_K1LR_K167     = 0x80       // Bit K167.
	CRYP_K1LR_K168_Pos = 0x8        // Position of K168 field.
	CRYP_K1LR_K168_Msk = 0x100      // Bit mask of K168 field.
	CRYP_K1LR_K168     = 0x100      // Bit K168.
	CRYP_K1LR_K169_Pos = 0x9        // Position of K169 field.
	CRYP_K1LR_K169_Msk = 0x200      // Bit mask of K169 field.
	CRYP_K1LR_K169     = 0x200      // Bit K169.
	CRYP_K1LR_K170_Pos = 0xa        // Position of K170 field.
	CRYP_K1LR_K170_Msk = 0x400      // Bit mask of K170 field.
	CRYP_K1LR_K170     = 0x400      // Bit K170.
	CRYP_K1LR_K171_Pos = 0xb        // Position of K171 field.
	CRYP_K1LR_K171_Msk = 0x800      // Bit mask of K171 field.
	CRYP_K1LR_K171     = 0x800      // Bit K171.
	CRYP_K1LR_K172_Pos = 0xc        // Position of K172 field.
	CRYP_K1LR_K172_Msk = 0x1000     // Bit mask of K172 field.
	CRYP_K1LR_K172     = 0x1000     // Bit K172.
	CRYP_K1LR_K173_Pos = 0xd        // Position of K173 field.
	CRYP_K1LR_K173_Msk = 0x2000     // Bit mask of K173 field.
	CRYP_K1LR_K173     = 0x2000     // Bit K173.
	CRYP_K1LR_K174_Pos = 0xe        // Position of K174 field.
	CRYP_K1LR_K174_Msk = 0x4000     // Bit mask of K174 field.
	CRYP_K1LR_K174     = 0x4000     // Bit K174.
	CRYP_K1LR_K175_Pos = 0xf        // Position of K175 field.
	CRYP_K1LR_K175_Msk = 0x8000     // Bit mask of K175 field.
	CRYP_K1LR_K175     = 0x8000     // Bit K175.
	CRYP_K1LR_K176_Pos = 0x10       // Position of K176 field.
	CRYP_K1LR_K176_Msk = 0x10000    // Bit mask of K176 field.
	CRYP_K1LR_K176     = 0x10000    // Bit K176.
	CRYP_K1LR_K177_Pos = 0x11       // Position of K177 field.
	CRYP_K1LR_K177_Msk = 0x20000    // Bit mask of K177 field.
	CRYP_K1LR_K177     = 0x20000    // Bit K177.
	CRYP_K1LR_K178_Pos = 0x12       // Position of K178 field.
	CRYP_K1LR_K178_Msk = 0x40000    // Bit mask of K178 field.
	CRYP_K1LR_K178     = 0x40000    // Bit K178.
	CRYP_K1LR_K179_Pos = 0x13       // Position of K179 field.
	CRYP_K1LR_K179_Msk = 0x80000    // Bit mask of K179 field.
	CRYP_K1LR_K179     = 0x80000    // Bit K179.
	CRYP_K1LR_K180_Pos = 0x14       // Position of K180 field.
	CRYP_K1LR_K180_Msk = 0x100000   // Bit mask of K180 field.
	CRYP_K1LR_K180     = 0x100000   // Bit K180.
	CRYP_K1LR_K181_Pos = 0x15       // Position of K181 field.
	CRYP_K1LR_K181_Msk = 0x200000   // Bit mask of K181 field.
	CRYP_K1LR_K181     = 0x200000   // Bit K181.
	CRYP_K1LR_K182_Pos = 0x16       // Position of K182 field.
	CRYP_K1LR_K182_Msk = 0x400000   // Bit mask of K182 field.
	CRYP_K1LR_K182     = 0x400000   // Bit K182.
	CRYP_K1LR_K183_Pos = 0x17       // Position of K183 field.
	CRYP_K1LR_K183_Msk = 0x800000   // Bit mask of K183 field.
	CRYP_K1LR_K183     = 0x800000   // Bit K183.
	CRYP_K1LR_K184_Pos = 0x18       // Position of K184 field.
	CRYP_K1LR_K184_Msk = 0x1000000  // Bit mask of K184 field.
	CRYP_K1LR_K184     = 0x1000000  // Bit K184.
	CRYP_K1LR_K185_Pos = 0x19       // Position of K185 field.
	CRYP_K1LR_K185_Msk = 0x2000000  // Bit mask of K185 field.
	CRYP_K1LR_K185     = 0x2000000  // Bit K185.
	CRYP_K1LR_K186_Pos = 0x1a       // Position of K186 field.
	CRYP_K1LR_K186_Msk = 0x4000000  // Bit mask of K186 field.
	CRYP_K1LR_K186     = 0x4000000  // Bit K186.
	CRYP_K1LR_K187_Pos = 0x1b       // Position of K187 field.
	CRYP_K1LR_K187_Msk = 0x8000000  // Bit mask of K187 field.
	CRYP_K1LR_K187     = 0x8000000  // Bit K187.
	CRYP_K1LR_K188_Pos = 0x1c       // Position of K188 field.
	CRYP_K1LR_K188_Msk = 0x10000000 // Bit mask of K188 field.
	CRYP_K1LR_K188     = 0x10000000 // Bit K188.
	CRYP_K1LR_K189_Pos = 0x1d       // Position of K189 field.
	CRYP_K1LR_K189_Msk = 0x20000000 // Bit mask of K189 field.
	CRYP_K1LR_K189     = 0x20000000 // Bit K189.
	CRYP_K1LR_K190_Pos = 0x1e       // Position of K190 field.
	CRYP_K1LR_K190_Msk = 0x40000000 // Bit mask of K190 field.
	CRYP_K1LR_K190     = 0x40000000 // Bit K190.
	CRYP_K1LR_K191_Pos = 0x1f       // Position of K191 field.
	CRYP_K1LR_K191_Msk = 0x80000000 // Bit mask of K191 field.
	CRYP_K1LR_K191     = 0x80000000 // Bit K191.

	// K1RR: key registers
	CRYP_K1RR_K128_Pos = 0x0        // Position of K128 field.
	CRYP_K1RR_K128_Msk = 0x1        // Bit mask of K128 field.
	CRYP_K1RR_K128     = 0x1        // Bit K128.
	CRYP_K1RR_K129_Pos = 0x1        // Position of K129 field.
	CRYP_K1RR_K129_Msk = 0x2        // Bit mask of K129 field.
	CRYP_K1RR_K129     = 0x2        // Bit K129.
	CRYP_K1RR_K130_Pos = 0x2        // Position of K130 field.
	CRYP_K1RR_K130_Msk = 0x4        // Bit mask of K130 field.
	CRYP_K1RR_K130     = 0x4        // Bit K130.
	CRYP_K1RR_K131_Pos = 0x3        // Position of K131 field.
	CRYP_K1RR_K131_Msk = 0x8        // Bit mask of K131 field.
	CRYP_K1RR_K131     = 0x8        // Bit K131.
	CRYP_K1RR_K132_Pos = 0x4        // Position of K132 field.
	CRYP_K1RR_K132_Msk = 0x10       // Bit mask of K132 field.
	CRYP_K1RR_K132     = 0x10       // Bit K132.
	CRYP_K1RR_K133_Pos = 0x5        // Position of K133 field.
	CRYP_K1RR_K133_Msk = 0x20       // Bit mask of K133 field.
	CRYP_K1RR_K133     = 0x20       // Bit K133.
	CRYP_K1RR_K134_Pos = 0x6        // Position of K134 field.
	CRYP_K1RR_K134_Msk = 0x40       // Bit mask of K134 field.
	CRYP_K1RR_K134     = 0x40       // Bit K134.
	CRYP_K1RR_K135_Pos = 0x7        // Position of K135 field.
	CRYP_K1RR_K135_Msk = 0x80       // Bit mask of K135 field.
	CRYP_K1RR_K135     = 0x80       // Bit K135.
	CRYP_K1RR_K136_Pos = 0x8        // Position of K136 field.
	CRYP_K1RR_K136_Msk = 0x100      // Bit mask of K136 field.
	CRYP_K1RR_K136     = 0x100      // Bit K136.
	CRYP_K1RR_K137_Pos = 0x9        // Position of K137 field.
	CRYP_K1RR_K137_Msk = 0x200      // Bit mask of K137 field.
	CRYP_K1RR_K137     = 0x200      // Bit K137.
	CRYP_K1RR_K138_Pos = 0xa        // Position of K138 field.
	CRYP_K1RR_K138_Msk = 0x400      // Bit mask of K138 field.
	CRYP_K1RR_K138     = 0x400      // Bit K138.
	CRYP_K1RR_K139_Pos = 0xb        // Position of K139 field.
	CRYP_K1RR_K139_Msk = 0x800      // Bit mask of K139 field.
	CRYP_K1RR_K139     = 0x800      // Bit K139.
	CRYP_K1RR_K140_Pos = 0xc        // Position of K140 field.
	CRYP_K1RR_K140_Msk = 0x1000     // Bit mask of K140 field.
	CRYP_K1RR_K140     = 0x1000     // Bit K140.
	CRYP_K1RR_K141_Pos = 0xd        // Position of K141 field.
	CRYP_K1RR_K141_Msk = 0x2000     // Bit mask of K141 field.
	CRYP_K1RR_K141     = 0x2000     // Bit K141.
	CRYP_K1RR_K142_Pos = 0xe        // Position of K142 field.
	CRYP_K1RR_K142_Msk = 0x4000     // Bit mask of K142 field.
	CRYP_K1RR_K142     = 0x4000     // Bit K142.
	CRYP_K1RR_K143_Pos = 0xf        // Position of K143 field.
	CRYP_K1RR_K143_Msk = 0x8000     // Bit mask of K143 field.
	CRYP_K1RR_K143     = 0x8000     // Bit K143.
	CRYP_K1RR_K144_Pos = 0x10       // Position of K144 field.
	CRYP_K1RR_K144_Msk = 0x10000    // Bit mask of K144 field.
	CRYP_K1RR_K144     = 0x10000    // Bit K144.
	CRYP_K1RR_K145_Pos = 0x11       // Position of K145 field.
	CRYP_K1RR_K145_Msk = 0x20000    // Bit mask of K145 field.
	CRYP_K1RR_K145     = 0x20000    // Bit K145.
	CRYP_K1RR_K146_Pos = 0x12       // Position of K146 field.
	CRYP_K1RR_K146_Msk = 0x40000    // Bit mask of K146 field.
	CRYP_K1RR_K146     = 0x40000    // Bit K146.
	CRYP_K1RR_K147_Pos = 0x13       // Position of K147 field.
	CRYP_K1RR_K147_Msk = 0x80000    // Bit mask of K147 field.
	CRYP_K1RR_K147     = 0x80000    // Bit K147.
	CRYP_K1RR_K148_Pos = 0x14       // Position of K148 field.
	CRYP_K1RR_K148_Msk = 0x100000   // Bit mask of K148 field.
	CRYP_K1RR_K148     = 0x100000   // Bit K148.
	CRYP_K1RR_K149_Pos = 0x15       // Position of K149 field.
	CRYP_K1RR_K149_Msk = 0x200000   // Bit mask of K149 field.
	CRYP_K1RR_K149     = 0x200000   // Bit K149.
	CRYP_K1RR_K150_Pos = 0x16       // Position of K150 field.
	CRYP_K1RR_K150_Msk = 0x400000   // Bit mask of K150 field.
	CRYP_K1RR_K150     = 0x400000   // Bit K150.
	CRYP_K1RR_K151_Pos = 0x17       // Position of K151 field.
	CRYP_K1RR_K151_Msk = 0x800000   // Bit mask of K151 field.
	CRYP_K1RR_K151     = 0x800000   // Bit K151.
	CRYP_K1RR_K152_Pos = 0x18       // Position of K152 field.
	CRYP_K1RR_K152_Msk = 0x1000000  // Bit mask of K152 field.
	CRYP_K1RR_K152     = 0x1000000  // Bit K152.
	CRYP_K1RR_K153_Pos = 0x19       // Position of K153 field.
	CRYP_K1RR_K153_Msk = 0x2000000  // Bit mask of K153 field.
	CRYP_K1RR_K153     = 0x2000000  // Bit K153.
	CRYP_K1RR_K154_Pos = 0x1a       // Position of K154 field.
	CRYP_K1RR_K154_Msk = 0x4000000  // Bit mask of K154 field.
	CRYP_K1RR_K154     = 0x4000000  // Bit K154.
	CRYP_K1RR_K155_Pos = 0x1b       // Position of K155 field.
	CRYP_K1RR_K155_Msk = 0x8000000  // Bit mask of K155 field.
	CRYP_K1RR_K155     = 0x8000000  // Bit K155.
	CRYP_K1RR_K156_Pos = 0x1c       // Position of K156 field.
	CRYP_K1RR_K156_Msk = 0x10000000 // Bit mask of K156 field.
	CRYP_K1RR_K156     = 0x10000000 // Bit K156.
	CRYP_K1RR_K157_Pos = 0x1d       // Position of K157 field.
	CRYP_K1RR_K157_Msk = 0x20000000 // Bit mask of K157 field.
	CRYP_K1RR_K157     = 0x20000000 // Bit K157.
	CRYP_K1RR_K158_Pos = 0x1e       // Position of K158 field.
	CRYP_K1RR_K158_Msk = 0x40000000 // Bit mask of K158 field.
	CRYP_K1RR_K158     = 0x40000000 // Bit K158.
	CRYP_K1RR_K159_Pos = 0x1f       // Position of K159 field.
	CRYP_K1RR_K159_Msk = 0x80000000 // Bit mask of K159 field.
	CRYP_K1RR_K159     = 0x80000000 // Bit K159.

	// K2LR: key registers
	CRYP_K2LR_K96_Pos  = 0x0        // Position of K96 field.
	CRYP_K2LR_K96_Msk  = 0x1        // Bit mask of K96 field.
	CRYP_K2LR_K96      = 0x1        // Bit K96.
	CRYP_K2LR_K97_Pos  = 0x1        // Position of K97 field.
	CRYP_K2LR_K97_Msk  = 0x2        // Bit mask of K97 field.
	CRYP_K2LR_K97      = 0x2        // Bit K97.
	CRYP_K2LR_K98_Pos  = 0x2        // Position of K98 field.
	CRYP_K2LR_K98_Msk  = 0x4        // Bit mask of K98 field.
	CRYP_K2LR_K98      = 0x4        // Bit K98.
	CRYP_K2LR_K99_Pos  = 0x3        // Position of K99 field.
	CRYP_K2LR_K99_Msk  = 0x8        // Bit mask of K99 field.
	CRYP_K2LR_K99      = 0x8        // Bit K99.
	CRYP_K2LR_K100_Pos = 0x4        // Position of K100 field.
	CRYP_K2LR_K100_Msk = 0x10       // Bit mask of K100 field.
	CRYP_K2LR_K100     = 0x10       // Bit K100.
	CRYP_K2LR_K101_Pos = 0x5        // Position of K101 field.
	CRYP_K2LR_K101_Msk = 0x20       // Bit mask of K101 field.
	CRYP_K2LR_K101     = 0x20       // Bit K101.
	CRYP_K2LR_K102_Pos = 0x6        // Position of K102 field.
	CRYP_K2LR_K102_Msk = 0x40       // Bit mask of K102 field.
	CRYP_K2LR_K102     = 0x40       // Bit K102.
	CRYP_K2LR_K103_Pos = 0x7        // Position of K103 field.
	CRYP_K2LR_K103_Msk = 0x80       // Bit mask of K103 field.
	CRYP_K2LR_K103     = 0x80       // Bit K103.
	CRYP_K2LR_K104_Pos = 0x8        // Position of K104 field.
	CRYP_K2LR_K104_Msk = 0x100      // Bit mask of K104 field.
	CRYP_K2LR_K104     = 0x100      // Bit K104.
	CRYP_K2LR_K105_Pos = 0x9        // Position of K105 field.
	CRYP_K2LR_K105_Msk = 0x200      // Bit mask of K105 field.
	CRYP_K2LR_K105     = 0x200      // Bit K105.
	CRYP_K2LR_K106_Pos = 0xa        // Position of K106 field.
	CRYP_K2LR_K106_Msk = 0x400      // Bit mask of K106 field.
	CRYP_K2LR_K106     = 0x400      // Bit K106.
	CRYP_K2LR_K107_Pos = 0xb        // Position of K107 field.
	CRYP_K2LR_K107_Msk = 0x800      // Bit mask of K107 field.
	CRYP_K2LR_K107     = 0x800      // Bit K107.
	CRYP_K2LR_K108_Pos = 0xc        // Position of K108 field.
	CRYP_K2LR_K108_Msk = 0x1000     // Bit mask of K108 field.
	CRYP_K2LR_K108     = 0x1000     // Bit K108.
	CRYP_K2LR_K109_Pos = 0xd        // Position of K109 field.
	CRYP_K2LR_K109_Msk = 0x2000     // Bit mask of K109 field.
	CRYP_K2LR_K109     = 0x2000     // Bit K109.
	CRYP_K2LR_K110_Pos = 0xe        // Position of K110 field.
	CRYP_K2LR_K110_Msk = 0x4000     // Bit mask of K110 field.
	CRYP_K2LR_K110     = 0x4000     // Bit K110.
	CRYP_K2LR_K111_Pos = 0xf        // Position of K111 field.
	CRYP_K2LR_K111_Msk = 0x8000     // Bit mask of K111 field.
	CRYP_K2LR_K111     = 0x8000     // Bit K111.
	CRYP_K2LR_K112_Pos = 0x10       // Position of K112 field.
	CRYP_K2LR_K112_Msk = 0x10000    // Bit mask of K112 field.
	CRYP_K2LR_K112     = 0x10000    // Bit K112.
	CRYP_K2LR_K113_Pos = 0x11       // Position of K113 field.
	CRYP_K2LR_K113_Msk = 0x20000    // Bit mask of K113 field.
	CRYP_K2LR_K113     = 0x20000    // Bit K113.
	CRYP_K2LR_K114_Pos = 0x12       // Position of K114 field.
	CRYP_K2LR_K114_Msk = 0x40000    // Bit mask of K114 field.
	CRYP_K2LR_K114     = 0x40000    // Bit K114.
	CRYP_K2LR_K115_Pos = 0x13       // Position of K115 field.
	CRYP_K2LR_K115_Msk = 0x80000    // Bit mask of K115 field.
	CRYP_K2LR_K115     = 0x80000    // Bit K115.
	CRYP_K2LR_K116_Pos = 0x14       // Position of K116 field.
	CRYP_K2LR_K116_Msk = 0x100000   // Bit mask of K116 field.
	CRYP_K2LR_K116     = 0x100000   // Bit K116.
	CRYP_K2LR_K117_Pos = 0x15       // Position of K117 field.
	CRYP_K2LR_K117_Msk = 0x200000   // Bit mask of K117 field.
	CRYP_K2LR_K117     = 0x200000   // Bit K117.
	CRYP_K2LR_K118_Pos = 0x16       // Position of K118 field.
	CRYP_K2LR_K118_Msk = 0x400000   // Bit mask of K118 field.
	CRYP_K2LR_K118     = 0x400000   // Bit K118.
	CRYP_K2LR_K119_Pos = 0x17       // Position of K119 field.
	CRYP_K2LR_K119_Msk = 0x800000   // Bit mask of K119 field.
	CRYP_K2LR_K119     = 0x800000   // Bit K119.
	CRYP_K2LR_K120_Pos = 0x18       // Position of K120 field.
	CRYP_K2LR_K120_Msk = 0x1000000  // Bit mask of K120 field.
	CRYP_K2LR_K120     = 0x1000000  // Bit K120.
	CRYP_K2LR_K121_Pos = 0x19       // Position of K121 field.
	CRYP_K2LR_K121_Msk = 0x2000000  // Bit mask of K121 field.
	CRYP_K2LR_K121     = 0x2000000  // Bit K121.
	CRYP_K2LR_K122_Pos = 0x1a       // Position of K122 field.
	CRYP_K2LR_K122_Msk = 0x4000000  // Bit mask of K122 field.
	CRYP_K2LR_K122     = 0x4000000  // Bit K122.
	CRYP_K2LR_K123_Pos = 0x1b       // Position of K123 field.
	CRYP_K2LR_K123_Msk = 0x8000000  // Bit mask of K123 field.
	CRYP_K2LR_K123     = 0x8000000  // Bit K123.
	CRYP_K2LR_K124_Pos = 0x1c       // Position of K124 field.
	CRYP_K2LR_K124_Msk = 0x10000000 // Bit mask of K124 field.
	CRYP_K2LR_K124     = 0x10000000 // Bit K124.
	CRYP_K2LR_K125_Pos = 0x1d       // Position of K125 field.
	CRYP_K2LR_K125_Msk = 0x20000000 // Bit mask of K125 field.
	CRYP_K2LR_K125     = 0x20000000 // Bit K125.
	CRYP_K2LR_K126_Pos = 0x1e       // Position of K126 field.
	CRYP_K2LR_K126_Msk = 0x40000000 // Bit mask of K126 field.
	CRYP_K2LR_K126     = 0x40000000 // Bit K126.
	CRYP_K2LR_K127_Pos = 0x1f       // Position of K127 field.
	CRYP_K2LR_K127_Msk = 0x80000000 // Bit mask of K127 field.
	CRYP_K2LR_K127     = 0x80000000 // Bit K127.

	// K2RR: key registers
	CRYP_K2RR_K64_Pos = 0x0        // Position of K64 field.
	CRYP_K2RR_K64_Msk = 0x1        // Bit mask of K64 field.
	CRYP_K2RR_K64     = 0x1        // Bit K64.
	CRYP_K2RR_K65_Pos = 0x1        // Position of K65 field.
	CRYP_K2RR_K65_Msk = 0x2        // Bit mask of K65 field.
	CRYP_K2RR_K65     = 0x2        // Bit K65.
	CRYP_K2RR_K66_Pos = 0x2        // Position of K66 field.
	CRYP_K2RR_K66_Msk = 0x4        // Bit mask of K66 field.
	CRYP_K2RR_K66     = 0x4        // Bit K66.
	CRYP_K2RR_K67_Pos = 0x3        // Position of K67 field.
	CRYP_K2RR_K67_Msk = 0x8        // Bit mask of K67 field.
	CRYP_K2RR_K67     = 0x8        // Bit K67.
	CRYP_K2RR_K68_Pos = 0x4        // Position of K68 field.
	CRYP_K2RR_K68_Msk = 0x10       // Bit mask of K68 field.
	CRYP_K2RR_K68     = 0x10       // Bit K68.
	CRYP_K2RR_K69_Pos = 0x5        // Position of K69 field.
	CRYP_K2RR_K69_Msk = 0x20       // Bit mask of K69 field.
	CRYP_K2RR_K69     = 0x20       // Bit K69.
	CRYP_K2RR_K70_Pos = 0x6        // Position of K70 field.
	CRYP_K2RR_K70_Msk = 0x40       // Bit mask of K70 field.
	CRYP_K2RR_K70     = 0x40       // Bit K70.
	CRYP_K2RR_K71_Pos = 0x7        // Position of K71 field.
	CRYP_K2RR_K71_Msk = 0x80       // Bit mask of K71 field.
	CRYP_K2RR_K71     = 0x80       // Bit K71.
	CRYP_K2RR_K72_Pos = 0x8        // Position of K72 field.
	CRYP_K2RR_K72_Msk = 0x100      // Bit mask of K72 field.
	CRYP_K2RR_K72     = 0x100      // Bit K72.
	CRYP_K2RR_K73_Pos = 0x9        // Position of K73 field.
	CRYP_K2RR_K73_Msk = 0x200      // Bit mask of K73 field.
	CRYP_K2RR_K73     = 0x200      // Bit K73.
	CRYP_K2RR_K74_Pos = 0xa        // Position of K74 field.
	CRYP_K2RR_K74_Msk = 0x400      // Bit mask of K74 field.
	CRYP_K2RR_K74     = 0x400      // Bit K74.
	CRYP_K2RR_K75_Pos = 0xb        // Position of K75 field.
	CRYP_K2RR_K75_Msk = 0x800      // Bit mask of K75 field.
	CRYP_K2RR_K75     = 0x800      // Bit K75.
	CRYP_K2RR_K76_Pos = 0xc        // Position of K76 field.
	CRYP_K2RR_K76_Msk = 0x1000     // Bit mask of K76 field.
	CRYP_K2RR_K76     = 0x1000     // Bit K76.
	CRYP_K2RR_K77_Pos = 0xd        // Position of K77 field.
	CRYP_K2RR_K77_Msk = 0x2000     // Bit mask of K77 field.
	CRYP_K2RR_K77     = 0x2000     // Bit K77.
	CRYP_K2RR_K78_Pos = 0xe        // Position of K78 field.
	CRYP_K2RR_K78_Msk = 0x4000     // Bit mask of K78 field.
	CRYP_K2RR_K78     = 0x4000     // Bit K78.
	CRYP_K2RR_K79_Pos = 0xf        // Position of K79 field.
	CRYP_K2RR_K79_Msk = 0x8000     // Bit mask of K79 field.
	CRYP_K2RR_K79     = 0x8000     // Bit K79.
	CRYP_K2RR_K80_Pos = 0x10       // Position of K80 field.
	CRYP_K2RR_K80_Msk = 0x10000    // Bit mask of K80 field.
	CRYP_K2RR_K80     = 0x10000    // Bit K80.
	CRYP_K2RR_K81_Pos = 0x11       // Position of K81 field.
	CRYP_K2RR_K81_Msk = 0x20000    // Bit mask of K81 field.
	CRYP_K2RR_K81     = 0x20000    // Bit K81.
	CRYP_K2RR_K82_Pos = 0x12       // Position of K82 field.
	CRYP_K2RR_K82_Msk = 0x40000    // Bit mask of K82 field.
	CRYP_K2RR_K82     = 0x40000    // Bit K82.
	CRYP_K2RR_K83_Pos = 0x13       // Position of K83 field.
	CRYP_K2RR_K83_Msk = 0x80000    // Bit mask of K83 field.
	CRYP_K2RR_K83     = 0x80000    // Bit K83.
	CRYP_K2RR_K84_Pos = 0x14       // Position of K84 field.
	CRYP_K2RR_K84_Msk = 0x100000   // Bit mask of K84 field.
	CRYP_K2RR_K84     = 0x100000   // Bit K84.
	CRYP_K2RR_K85_Pos = 0x15       // Position of K85 field.
	CRYP_K2RR_K85_Msk = 0x200000   // Bit mask of K85 field.
	CRYP_K2RR_K85     = 0x200000   // Bit K85.
	CRYP_K2RR_K86_Pos = 0x16       // Position of K86 field.
	CRYP_K2RR_K86_Msk = 0x400000   // Bit mask of K86 field.
	CRYP_K2RR_K86     = 0x400000   // Bit K86.
	CRYP_K2RR_K87_Pos = 0x17       // Position of K87 field.
	CRYP_K2RR_K87_Msk = 0x800000   // Bit mask of K87 field.
	CRYP_K2RR_K87     = 0x800000   // Bit K87.
	CRYP_K2RR_K88_Pos = 0x18       // Position of K88 field.
	CRYP_K2RR_K88_Msk = 0x1000000  // Bit mask of K88 field.
	CRYP_K2RR_K88     = 0x1000000  // Bit K88.
	CRYP_K2RR_K89_Pos = 0x19       // Position of K89 field.
	CRYP_K2RR_K89_Msk = 0x2000000  // Bit mask of K89 field.
	CRYP_K2RR_K89     = 0x2000000  // Bit K89.
	CRYP_K2RR_K90_Pos = 0x1a       // Position of K90 field.
	CRYP_K2RR_K90_Msk = 0x4000000  // Bit mask of K90 field.
	CRYP_K2RR_K90     = 0x4000000  // Bit K90.
	CRYP_K2RR_K91_Pos = 0x1b       // Position of K91 field.
	CRYP_K2RR_K91_Msk = 0x8000000  // Bit mask of K91 field.
	CRYP_K2RR_K91     = 0x8000000  // Bit K91.
	CRYP_K2RR_K92_Pos = 0x1c       // Position of K92 field.
	CRYP_K2RR_K92_Msk = 0x10000000 // Bit mask of K92 field.
	CRYP_K2RR_K92     = 0x10000000 // Bit K92.
	CRYP_K2RR_K93_Pos = 0x1d       // Position of K93 field.
	CRYP_K2RR_K93_Msk = 0x20000000 // Bit mask of K93 field.
	CRYP_K2RR_K93     = 0x20000000 // Bit K93.
	CRYP_K2RR_K94_Pos = 0x1e       // Position of K94 field.
	CRYP_K2RR_K94_Msk = 0x40000000 // Bit mask of K94 field.
	CRYP_K2RR_K94     = 0x40000000 // Bit K94.
	CRYP_K2RR_K95_Pos = 0x1f       // Position of K95 field.
	CRYP_K2RR_K95_Msk = 0x80000000 // Bit mask of K95 field.
	CRYP_K2RR_K95     = 0x80000000 // Bit K95.

	// K3LR: key registers
	CRYP_K3LR_K32_Pos = 0x0        // Position of K32 field.
	CRYP_K3LR_K32_Msk = 0x1        // Bit mask of K32 field.
	CRYP_K3LR_K32     = 0x1        // Bit K32.
	CRYP_K3LR_K33_Pos = 0x1        // Position of K33 field.
	CRYP_K3LR_K33_Msk = 0x2        // Bit mask of K33 field.
	CRYP_K3LR_K33     = 0x2        // Bit K33.
	CRYP_K3LR_K34_Pos = 0x2        // Position of K34 field.
	CRYP_K3LR_K34_Msk = 0x4        // Bit mask of K34 field.
	CRYP_K3LR_K34     = 0x4        // Bit K34.
	CRYP_K3LR_K35_Pos = 0x3        // Position of K35 field.
	CRYP_K3LR_K35_Msk = 0x8        // Bit mask of K35 field.
	CRYP_K3LR_K35     = 0x8        // Bit K35.
	CRYP_K3LR_K36_Pos = 0x4        // Position of K36 field.
	CRYP_K3LR_K36_Msk = 0x10       // Bit mask of K36 field.
	CRYP_K3LR_K36     = 0x10       // Bit K36.
	CRYP_K3LR_K37_Pos = 0x5        // Position of K37 field.
	CRYP_K3LR_K37_Msk = 0x20       // Bit mask of K37 field.
	CRYP_K3LR_K37     = 0x20       // Bit K37.
	CRYP_K3LR_K38_Pos = 0x6        // Position of K38 field.
	CRYP_K3LR_K38_Msk = 0x40       // Bit mask of K38 field.
	CRYP_K3LR_K38     = 0x40       // Bit K38.
	CRYP_K3LR_K39_Pos = 0x7        // Position of K39 field.
	CRYP_K3LR_K39_Msk = 0x80       // Bit mask of K39 field.
	CRYP_K3LR_K39     = 0x80       // Bit K39.
	CRYP_K3LR_K40_Pos = 0x8        // Position of K40 field.
	CRYP_K3LR_K40_Msk = 0x100      // Bit mask of K40 field.
	CRYP_K3LR_K40     = 0x100      // Bit K40.
	CRYP_K3LR_K41_Pos = 0x9        // Position of K41 field.
	CRYP_K3LR_K41_Msk = 0x200      // Bit mask of K41 field.
	CRYP_K3LR_K41     = 0x200      // Bit K41.
	CRYP_K3LR_K42_Pos = 0xa        // Position of K42 field.
	CRYP_K3LR_K42_Msk = 0x400      // Bit mask of K42 field.
	CRYP_K3LR_K42     = 0x400      // Bit K42.
	CRYP_K3LR_K43_Pos = 0xb        // Position of K43 field.
	CRYP_K3LR_K43_Msk = 0x800      // Bit mask of K43 field.
	CRYP_K3LR_K43     = 0x800      // Bit K43.
	CRYP_K3LR_K44_Pos = 0xc        // Position of K44 field.
	CRYP_K3LR_K44_Msk = 0x1000     // Bit mask of K44 field.
	CRYP_K3LR_K44     = 0x1000     // Bit K44.
	CRYP_K3LR_K45_Pos = 0xd        // Position of K45 field.
	CRYP_K3LR_K45_Msk = 0x2000     // Bit mask of K45 field.
	CRYP_K3LR_K45     = 0x2000     // Bit K45.
	CRYP_K3LR_K46_Pos = 0xe        // Position of K46 field.
	CRYP_K3LR_K46_Msk = 0x4000     // Bit mask of K46 field.
	CRYP_K3LR_K46     = 0x4000     // Bit K46.
	CRYP_K3LR_K47_Pos = 0xf        // Position of K47 field.
	CRYP_K3LR_K47_Msk = 0x8000     // Bit mask of K47 field.
	CRYP_K3LR_K47     = 0x8000     // Bit K47.
	CRYP_K3LR_K48_Pos = 0x10       // Position of K48 field.
	CRYP_K3LR_K48_Msk = 0x10000    // Bit mask of K48 field.
	CRYP_K3LR_K48     = 0x10000    // Bit K48.
	CRYP_K3LR_K49_Pos = 0x11       // Position of K49 field.
	CRYP_K3LR_K49_Msk = 0x20000    // Bit mask of K49 field.
	CRYP_K3LR_K49     = 0x20000    // Bit K49.
	CRYP_K3LR_K50_Pos = 0x12       // Position of K50 field.
	CRYP_K3LR_K50_Msk = 0x40000    // Bit mask of K50 field.
	CRYP_K3LR_K50     = 0x40000    // Bit K50.
	CRYP_K3LR_K51_Pos = 0x13       // Position of K51 field.
	CRYP_K3LR_K51_Msk = 0x80000    // Bit mask of K51 field.
	CRYP_K3LR_K51     = 0x80000    // Bit K51.
	CRYP_K3LR_K52_Pos = 0x14       // Position of K52 field.
	CRYP_K3LR_K52_Msk = 0x100000   // Bit mask of K52 field.
	CRYP_K3LR_K52     = 0x100000   // Bit K52.
	CRYP_K3LR_K53_Pos = 0x15       // Position of K53 field.
	CRYP_K3LR_K53_Msk = 0x200000   // Bit mask of K53 field.
	CRYP_K3LR_K53     = 0x200000   // Bit K53.
	CRYP_K3LR_K54_Pos = 0x16       // Position of K54 field.
	CRYP_K3LR_K54_Msk = 0x400000   // Bit mask of K54 field.
	CRYP_K3LR_K54     = 0x400000   // Bit K54.
	CRYP_K3LR_K55_Pos = 0x17       // Position of K55 field.
	CRYP_K3LR_K55_Msk = 0x800000   // Bit mask of K55 field.
	CRYP_K3LR_K55     = 0x800000   // Bit K55.
	CRYP_K3LR_K56_Pos = 0x18       // Position of K56 field.
	CRYP_K3LR_K56_Msk = 0x1000000  // Bit mask of K56 field.
	CRYP_K3LR_K56     = 0x1000000  // Bit K56.
	CRYP_K3LR_K57_Pos = 0x19       // Position of K57 field.
	CRYP_K3LR_K57_Msk = 0x2000000  // Bit mask of K57 field.
	CRYP_K3LR_K57     = 0x2000000  // Bit K57.
	CRYP_K3LR_K58_Pos = 0x1a       // Position of K58 field.
	CRYP_K3LR_K58_Msk = 0x4000000  // Bit mask of K58 field.
	CRYP_K3LR_K58     = 0x4000000  // Bit K58.
	CRYP_K3LR_K59_Pos = 0x1b       // Position of K59 field.
	CRYP_K3LR_K59_Msk = 0x8000000  // Bit mask of K59 field.
	CRYP_K3LR_K59     = 0x8000000  // Bit K59.
	CRYP_K3LR_K60_Pos = 0x1c       // Position of K60 field.
	CRYP_K3LR_K60_Msk = 0x10000000 // Bit mask of K60 field.
	CRYP_K3LR_K60     = 0x10000000 // Bit K60.
	CRYP_K3LR_K61_Pos = 0x1d       // Position of K61 field.
	CRYP_K3LR_K61_Msk = 0x20000000 // Bit mask of K61 field.
	CRYP_K3LR_K61     = 0x20000000 // Bit K61.
	CRYP_K3LR_K62_Pos = 0x1e       // Position of K62 field.
	CRYP_K3LR_K62_Msk = 0x40000000 // Bit mask of K62 field.
	CRYP_K3LR_K62     = 0x40000000 // Bit K62.
	CRYP_K3LR_K63_Pos = 0x1f       // Position of K63 field.
	CRYP_K3LR_K63_Msk = 0x80000000 // Bit mask of K63 field.
	CRYP_K3LR_K63     = 0x80000000 // Bit K63.

	// K3RR: key registers
	CRYP_K3RR_K0_Pos  = 0x0        // Position of K0 field.
	CRYP_K3RR_K0_Msk  = 0x1        // Bit mask of K0 field.
	CRYP_K3RR_K0      = 0x1        // Bit K0.
	CRYP_K3RR_K1_Pos  = 0x1        // Position of K1 field.
	CRYP_K3RR_K1_Msk  = 0x2        // Bit mask of K1 field.
	CRYP_K3RR_K1      = 0x2        // Bit K1.
	CRYP_K3RR_K2_Pos  = 0x2        // Position of K2 field.
	CRYP_K3RR_K2_Msk  = 0x4        // Bit mask of K2 field.
	CRYP_K3RR_K2      = 0x4        // Bit K2.
	CRYP_K3RR_K3_Pos  = 0x3        // Position of K3 field.
	CRYP_K3RR_K3_Msk  = 0x8        // Bit mask of K3 field.
	CRYP_K3RR_K3      = 0x8        // Bit K3.
	CRYP_K3RR_K4_Pos  = 0x4        // Position of K4 field.
	CRYP_K3RR_K4_Msk  = 0x10       // Bit mask of K4 field.
	CRYP_K3RR_K4      = 0x10       // Bit K4.
	CRYP_K3RR_K5_Pos  = 0x5        // Position of K5 field.
	CRYP_K3RR_K5_Msk  = 0x20       // Bit mask of K5 field.
	CRYP_K3RR_K5      = 0x20       // Bit K5.
	CRYP_K3RR_K6_Pos  = 0x6        // Position of K6 field.
	CRYP_K3RR_K6_Msk  = 0x40       // Bit mask of K6 field.
	CRYP_K3RR_K6      = 0x40       // Bit K6.
	CRYP_K3RR_K7_Pos  = 0x7        // Position of K7 field.
	CRYP_K3RR_K7_Msk  = 0x80       // Bit mask of K7 field.
	CRYP_K3RR_K7      = 0x80       // Bit K7.
	CRYP_K3RR_K8_Pos  = 0x8        // Position of K8 field.
	CRYP_K3RR_K8_Msk  = 0x100      // Bit mask of K8 field.
	CRYP_K3RR_K8      = 0x100      // Bit K8.
	CRYP_K3RR_K9_Pos  = 0x9        // Position of K9 field.
	CRYP_K3RR_K9_Msk  = 0x200      // Bit mask of K9 field.
	CRYP_K3RR_K9      = 0x200      // Bit K9.
	CRYP_K3RR_K10_Pos = 0xa        // Position of K10 field.
	CRYP_K3RR_K10_Msk = 0x400      // Bit mask of K10 field.
	CRYP_K3RR_K10     = 0x400      // Bit K10.
	CRYP_K3RR_K11_Pos = 0xb        // Position of K11 field.
	CRYP_K3RR_K11_Msk = 0x800      // Bit mask of K11 field.
	CRYP_K3RR_K11     = 0x800      // Bit K11.
	CRYP_K3RR_K12_Pos = 0xc        // Position of K12 field.
	CRYP_K3RR_K12_Msk = 0x1000     // Bit mask of K12 field.
	CRYP_K3RR_K12     = 0x1000     // Bit K12.
	CRYP_K3RR_K13_Pos = 0xd        // Position of K13 field.
	CRYP_K3RR_K13_Msk = 0x2000     // Bit mask of K13 field.
	CRYP_K3RR_K13     = 0x2000     // Bit K13.
	CRYP_K3RR_K14_Pos = 0xe        // Position of K14 field.
	CRYP_K3RR_K14_Msk = 0x4000     // Bit mask of K14 field.
	CRYP_K3RR_K14     = 0x4000     // Bit K14.
	CRYP_K3RR_K15_Pos = 0xf        // Position of K15 field.
	CRYP_K3RR_K15_Msk = 0x8000     // Bit mask of K15 field.
	CRYP_K3RR_K15     = 0x8000     // Bit K15.
	CRYP_K3RR_K16_Pos = 0x10       // Position of K16 field.
	CRYP_K3RR_K16_Msk = 0x10000    // Bit mask of K16 field.
	CRYP_K3RR_K16     = 0x10000    // Bit K16.
	CRYP_K3RR_K17_Pos = 0x11       // Position of K17 field.
	CRYP_K3RR_K17_Msk = 0x20000    // Bit mask of K17 field.
	CRYP_K3RR_K17     = 0x20000    // Bit K17.
	CRYP_K3RR_K18_Pos = 0x12       // Position of K18 field.
	CRYP_K3RR_K18_Msk = 0x40000    // Bit mask of K18 field.
	CRYP_K3RR_K18     = 0x40000    // Bit K18.
	CRYP_K3RR_K19_Pos = 0x13       // Position of K19 field.
	CRYP_K3RR_K19_Msk = 0x80000    // Bit mask of K19 field.
	CRYP_K3RR_K19     = 0x80000    // Bit K19.
	CRYP_K3RR_K20_Pos = 0x14       // Position of K20 field.
	CRYP_K3RR_K20_Msk = 0x100000   // Bit mask of K20 field.
	CRYP_K3RR_K20     = 0x100000   // Bit K20.
	CRYP_K3RR_K21_Pos = 0x15       // Position of K21 field.
	CRYP_K3RR_K21_Msk = 0x200000   // Bit mask of K21 field.
	CRYP_K3RR_K21     = 0x200000   // Bit K21.
	CRYP_K3RR_K22_Pos = 0x16       // Position of K22 field.
	CRYP_K3RR_K22_Msk = 0x400000   // Bit mask of K22 field.
	CRYP_K3RR_K22     = 0x400000   // Bit K22.
	CRYP_K3RR_K23_Pos = 0x17       // Position of K23 field.
	CRYP_K3RR_K23_Msk = 0x800000   // Bit mask of K23 field.
	CRYP_K3RR_K23     = 0x800000   // Bit K23.
	CRYP_K3RR_K24_Pos = 0x18       // Position of K24 field.
	CRYP_K3RR_K24_Msk = 0x1000000  // Bit mask of K24 field.
	CRYP_K3RR_K24     = 0x1000000  // Bit K24.
	CRYP_K3RR_K25_Pos = 0x19       // Position of K25 field.
	CRYP_K3RR_K25_Msk = 0x2000000  // Bit mask of K25 field.
	CRYP_K3RR_K25     = 0x2000000  // Bit K25.
	CRYP_K3RR_K26_Pos = 0x1a       // Position of K26 field.
	CRYP_K3RR_K26_Msk = 0x4000000  // Bit mask of K26 field.
	CRYP_K3RR_K26     = 0x4000000  // Bit K26.
	CRYP_K3RR_K27_Pos = 0x1b       // Position of K27 field.
	CRYP_K3RR_K27_Msk = 0x8000000  // Bit mask of K27 field.
	CRYP_K3RR_K27     = 0x8000000  // Bit K27.
	CRYP_K3RR_K28_Pos = 0x1c       // Position of K28 field.
	CRYP_K3RR_K28_Msk = 0x10000000 // Bit mask of K28 field.
	CRYP_K3RR_K28     = 0x10000000 // Bit K28.
	CRYP_K3RR_K29_Pos = 0x1d       // Position of K29 field.
	CRYP_K3RR_K29_Msk = 0x20000000 // Bit mask of K29 field.
	CRYP_K3RR_K29     = 0x20000000 // Bit K29.
	CRYP_K3RR_K30_Pos = 0x1e       // Position of K30 field.
	CRYP_K3RR_K30_Msk = 0x40000000 // Bit mask of K30 field.
	CRYP_K3RR_K30     = 0x40000000 // Bit K30.
	CRYP_K3RR_K31_Pos = 0x1f       // Position of K31 field.
	CRYP_K3RR_K31_Msk = 0x80000000 // Bit mask of K31 field.
	CRYP_K3RR_K31     = 0x80000000 // Bit K31.

	// IV0LR: initialization vector           registers
	CRYP_IV0LR_IV31_Pos = 0x0        // Position of IV31 field.
	CRYP_IV0LR_IV31_Msk = 0x1        // Bit mask of IV31 field.
	CRYP_IV0LR_IV31     = 0x1        // Bit IV31.
	CRYP_IV0LR_IV30_Pos = 0x1        // Position of IV30 field.
	CRYP_IV0LR_IV30_Msk = 0x2        // Bit mask of IV30 field.
	CRYP_IV0LR_IV30     = 0x2        // Bit IV30.
	CRYP_IV0LR_IV29_Pos = 0x2        // Position of IV29 field.
	CRYP_IV0LR_IV29_Msk = 0x4        // Bit mask of IV29 field.
	CRYP_IV0LR_IV29     = 0x4        // Bit IV29.
	CRYP_IV0LR_IV28_Pos = 0x3        // Position of IV28 field.
	CRYP_IV0LR_IV28_Msk = 0x8        // Bit mask of IV28 field.
	CRYP_IV0LR_IV28     = 0x8        // Bit IV28.
	CRYP_IV0LR_IV27_Pos = 0x4        // Position of IV27 field.
	CRYP_IV0LR_IV27_Msk = 0x10       // Bit mask of IV27 field.
	CRYP_IV0LR_IV27     = 0x10       // Bit IV27.
	CRYP_IV0LR_IV26_Pos = 0x5        // Position of IV26 field.
	CRYP_IV0LR_IV26_Msk = 0x20       // Bit mask of IV26 field.
	CRYP_IV0LR_IV26     = 0x20       // Bit IV26.
	CRYP_IV0LR_IV25_Pos = 0x6        // Position of IV25 field.
	CRYP_IV0LR_IV25_Msk = 0x40       // Bit mask of IV25 field.
	CRYP_IV0LR_IV25     = 0x40       // Bit IV25.
	CRYP_IV0LR_IV24_Pos = 0x7        // Position of IV24 field.
	CRYP_IV0LR_IV24_Msk = 0x80       // Bit mask of IV24 field.
	CRYP_IV0LR_IV24     = 0x80       // Bit IV24.
	CRYP_IV0LR_IV23_Pos = 0x8        // Position of IV23 field.
	CRYP_IV0LR_IV23_Msk = 0x100      // Bit mask of IV23 field.
	CRYP_IV0LR_IV23     = 0x100      // Bit IV23.
	CRYP_IV0LR_IV22_Pos = 0x9        // Position of IV22 field.
	CRYP_IV0LR_IV22_Msk = 0x200      // Bit mask of IV22 field.
	CRYP_IV0LR_IV22     = 0x200      // Bit IV22.
	CRYP_IV0LR_IV21_Pos = 0xa        // Position of IV21 field.
	CRYP_IV0LR_IV21_Msk = 0x400      // Bit mask of IV21 field.
	CRYP_IV0LR_IV21     = 0x400      // Bit IV21.
	CRYP_IV0LR_IV20_Pos = 0xb        // Position of IV20 field.
	CRYP_IV0LR_IV20_Msk = 0x800      // Bit mask of IV20 field.
	CRYP_IV0LR_IV20     = 0x800      // Bit IV20.
	CRYP_IV0LR_IV19_Pos = 0xc        // Position of IV19 field.
	CRYP_IV0LR_IV19_Msk = 0x1000     // Bit mask of IV19 field.
	CRYP_IV0LR_IV19     = 0x1000     // Bit IV19.
	CRYP_IV0LR_IV18_Pos = 0xd        // Position of IV18 field.
	CRYP_IV0LR_IV18_Msk = 0x2000     // Bit mask of IV18 field.
	CRYP_IV0LR_IV18     = 0x2000     // Bit IV18.
	CRYP_IV0LR_IV17_Pos = 0xe        // Position of IV17 field.
	CRYP_IV0LR_IV17_Msk = 0x4000     // Bit mask of IV17 field.
	CRYP_IV0LR_IV17     = 0x4000     // Bit IV17.
	CRYP_IV0LR_IV16_Pos = 0xf        // Position of IV16 field.
	CRYP_IV0LR_IV16_Msk = 0x8000     // Bit mask of IV16 field.
	CRYP_IV0LR_IV16     = 0x8000     // Bit IV16.
	CRYP_IV0LR_IV15_Pos = 0x10       // Position of IV15 field.
	CRYP_IV0LR_IV15_Msk = 0x10000    // Bit mask of IV15 field.
	CRYP_IV0LR_IV15     = 0x10000    // Bit IV15.
	CRYP_IV0LR_IV14_Pos = 0x11       // Position of IV14 field.
	CRYP_IV0LR_IV14_Msk = 0x20000    // Bit mask of IV14 field.
	CRYP_IV0LR_IV14     = 0x20000    // Bit IV14.
	CRYP_IV0LR_IV13_Pos = 0x12       // Position of IV13 field.
	CRYP_IV0LR_IV13_Msk = 0x40000    // Bit mask of IV13 field.
	CRYP_IV0LR_IV13     = 0x40000    // Bit IV13.
	CRYP_IV0LR_IV12_Pos = 0x13       // Position of IV12 field.
	CRYP_IV0LR_IV12_Msk = 0x80000    // Bit mask of IV12 field.
	CRYP_IV0LR_IV12     = 0x80000    // Bit IV12.
	CRYP_IV0LR_IV11_Pos = 0x14       // Position of IV11 field.
	CRYP_IV0LR_IV11_Msk = 0x100000   // Bit mask of IV11 field.
	CRYP_IV0LR_IV11     = 0x100000   // Bit IV11.
	CRYP_IV0LR_IV10_Pos = 0x15       // Position of IV10 field.
	CRYP_IV0LR_IV10_Msk = 0x200000   // Bit mask of IV10 field.
	CRYP_IV0LR_IV10     = 0x200000   // Bit IV10.
	CRYP_IV0LR_IV9_Pos  = 0x16       // Position of IV9 field.
	CRYP_IV0LR_IV9_Msk  = 0x400000   // Bit mask of IV9 field.
	CRYP_IV0LR_IV9      = 0x400000   // Bit IV9.
	CRYP_IV0LR_IV8_Pos  = 0x17       // Position of IV8 field.
	CRYP_IV0LR_IV8_Msk  = 0x800000   // Bit mask of IV8 field.
	CRYP_IV0LR_IV8      = 0x800000   // Bit IV8.
	CRYP_IV0LR_IV7_Pos  = 0x18       // Position of IV7 field.
	CRYP_IV0LR_IV7_Msk  = 0x1000000  // Bit mask of IV7 field.
	CRYP_IV0LR_IV7      = 0x1000000  // Bit IV7.
	CRYP_IV0LR_IV6_Pos  = 0x19       // Position of IV6 field.
	CRYP_IV0LR_IV6_Msk  = 0x2000000  // Bit mask of IV6 field.
	CRYP_IV0LR_IV6      = 0x2000000  // Bit IV6.
	CRYP_IV0LR_IV5_Pos  = 0x1a       // Position of IV5 field.
	CRYP_IV0LR_IV5_Msk  = 0x4000000  // Bit mask of IV5 field.
	CRYP_IV0LR_IV5      = 0x4000000  // Bit IV5.
	CRYP_IV0LR_IV4_Pos  = 0x1b       // Position of IV4 field.
	CRYP_IV0LR_IV4_Msk  = 0x8000000  // Bit mask of IV4 field.
	CRYP_IV0LR_IV4      = 0x8000000  // Bit IV4.
	CRYP_IV0LR_IV3_Pos  = 0x1c       // Position of IV3 field.
	CRYP_IV0LR_IV3_Msk  = 0x10000000 // Bit mask of IV3 field.
	CRYP_IV0LR_IV3      = 0x10000000 // Bit IV3.
	CRYP_IV0LR_IV2_Pos  = 0x1d       // Position of IV2 field.
	CRYP_IV0LR_IV2_Msk  = 0x20000000 // Bit mask of IV2 field.
	CRYP_IV0LR_IV2      = 0x20000000 // Bit IV2.
	CRYP_IV0LR_IV1_Pos  = 0x1e       // Position of IV1 field.
	CRYP_IV0LR_IV1_Msk  = 0x40000000 // Bit mask of IV1 field.
	CRYP_IV0LR_IV1      = 0x40000000 // Bit IV1.
	CRYP_IV0LR_IV0_Pos  = 0x1f       // Position of IV0 field.
	CRYP_IV0LR_IV0_Msk  = 0x80000000 // Bit mask of IV0 field.
	CRYP_IV0LR_IV0      = 0x80000000 // Bit IV0.

	// IV0RR: initialization vector           registers
	CRYP_IV0RR_IV63_Pos = 0x0        // Position of IV63 field.
	CRYP_IV0RR_IV63_Msk = 0x1        // Bit mask of IV63 field.
	CRYP_IV0RR_IV63     = 0x1        // Bit IV63.
	CRYP_IV0RR_IV62_Pos = 0x1        // Position of IV62 field.
	CRYP_IV0RR_IV62_Msk = 0x2        // Bit mask of IV62 field.
	CRYP_IV0RR_IV62     = 0x2        // Bit IV62.
	CRYP_IV0RR_IV61_Pos = 0x2        // Position of IV61 field.
	CRYP_IV0RR_IV61_Msk = 0x4        // Bit mask of IV61 field.
	CRYP_IV0RR_IV61     = 0x4        // Bit IV61.
	CRYP_IV0RR_IV60_Pos = 0x3        // Position of IV60 field.
	CRYP_IV0RR_IV60_Msk = 0x8        // Bit mask of IV60 field.
	CRYP_IV0RR_IV60     = 0x8        // Bit IV60.
	CRYP_IV0RR_IV59_Pos = 0x4        // Position of IV59 field.
	CRYP_IV0RR_IV59_Msk = 0x10       // Bit mask of IV59 field.
	CRYP_IV0RR_IV59     = 0x10       // Bit IV59.
	CRYP_IV0RR_IV58_Pos = 0x5        // Position of IV58 field.
	CRYP_IV0RR_IV58_Msk = 0x20       // Bit mask of IV58 field.
	CRYP_IV0RR_IV58     = 0x20       // Bit IV58.
	CRYP_IV0RR_IV57_Pos = 0x6        // Position of IV57 field.
	CRYP_IV0RR_IV57_Msk = 0x40       // Bit mask of IV57 field.
	CRYP_IV0RR_IV57     = 0x40       // Bit IV57.
	CRYP_IV0RR_IV56_Pos = 0x7        // Position of IV56 field.
	CRYP_IV0RR_IV56_Msk = 0x80       // Bit mask of IV56 field.
	CRYP_IV0RR_IV56     = 0x80       // Bit IV56.
	CRYP_IV0RR_IV55_Pos = 0x8        // Position of IV55 field.
	CRYP_IV0RR_IV55_Msk = 0x100      // Bit mask of IV55 field.
	CRYP_IV0RR_IV55     = 0x100      // Bit IV55.
	CRYP_IV0RR_IV54_Pos = 0x9        // Position of IV54 field.
	CRYP_IV0RR_IV54_Msk = 0x200      // Bit mask of IV54 field.
	CRYP_IV0RR_IV54     = 0x200      // Bit IV54.
	CRYP_IV0RR_IV53_Pos = 0xa        // Position of IV53 field.
	CRYP_IV0RR_IV53_Msk = 0x400      // Bit mask of IV53 field.
	CRYP_IV0RR_IV53     = 0x400      // Bit IV53.
	CRYP_IV0RR_IV52_Pos = 0xb        // Position of IV52 field.
	CRYP_IV0RR_IV52_Msk = 0x800      // Bit mask of IV52 field.
	CRYP_IV0RR_IV52     = 0x800      // Bit IV52.
	CRYP_IV0RR_IV51_Pos = 0xc        // Position of IV51 field.
	CRYP_IV0RR_IV51_Msk = 0x1000     // Bit mask of IV51 field.
	CRYP_IV0RR_IV51     = 0x1000     // Bit IV51.
	CRYP_IV0RR_IV50_Pos = 0xd        // Position of IV50 field.
	CRYP_IV0RR_IV50_Msk = 0x2000     // Bit mask of IV50 field.
	CRYP_IV0RR_IV50     = 0x2000     // Bit IV50.
	CRYP_IV0RR_IV49_Pos = 0xe        // Position of IV49 field.
	CRYP_IV0RR_IV49_Msk = 0x4000     // Bit mask of IV49 field.
	CRYP_IV0RR_IV49     = 0x4000     // Bit IV49.
	CRYP_IV0RR_IV48_Pos = 0xf        // Position of IV48 field.
	CRYP_IV0RR_IV48_Msk = 0x8000     // Bit mask of IV48 field.
	CRYP_IV0RR_IV48     = 0x8000     // Bit IV48.
	CRYP_IV0RR_IV47_Pos = 0x10       // Position of IV47 field.
	CRYP_IV0RR_IV47_Msk = 0x10000    // Bit mask of IV47 field.
	CRYP_IV0RR_IV47     = 0x10000    // Bit IV47.
	CRYP_IV0RR_IV46_Pos = 0x11       // Position of IV46 field.
	CRYP_IV0RR_IV46_Msk = 0x20000    // Bit mask of IV46 field.
	CRYP_IV0RR_IV46     = 0x20000    // Bit IV46.
	CRYP_IV0RR_IV45_Pos = 0x12       // Position of IV45 field.
	CRYP_IV0RR_IV45_Msk = 0x40000    // Bit mask of IV45 field.
	CRYP_IV0RR_IV45     = 0x40000    // Bit IV45.
	CRYP_IV0RR_IV44_Pos = 0x13       // Position of IV44 field.
	CRYP_IV0RR_IV44_Msk = 0x80000    // Bit mask of IV44 field.
	CRYP_IV0RR_IV44     = 0x80000    // Bit IV44.
	CRYP_IV0RR_IV43_Pos = 0x14       // Position of IV43 field.
	CRYP_IV0RR_IV43_Msk = 0x100000   // Bit mask of IV43 field.
	CRYP_IV0RR_IV43     = 0x100000   // Bit IV43.
	CRYP_IV0RR_IV42_Pos = 0x15       // Position of IV42 field.
	CRYP_IV0RR_IV42_Msk = 0x200000   // Bit mask of IV42 field.
	CRYP_IV0RR_IV42     = 0x200000   // Bit IV42.
	CRYP_IV0RR_IV41_Pos = 0x16       // Position of IV41 field.
	CRYP_IV0RR_IV41_Msk = 0x400000   // Bit mask of IV41 field.
	CRYP_IV0RR_IV41     = 0x400000   // Bit IV41.
	CRYP_IV0RR_IV40_Pos = 0x17       // Position of IV40 field.
	CRYP_IV0RR_IV40_Msk = 0x800000   // Bit mask of IV40 field.
	CRYP_IV0RR_IV40     = 0x800000   // Bit IV40.
	CRYP_IV0RR_IV39_Pos = 0x18       // Position of IV39 field.
	CRYP_IV0RR_IV39_Msk = 0x1000000  // Bit mask of IV39 field.
	CRYP_IV0RR_IV39     = 0x1000000  // Bit IV39.
	CRYP_IV0RR_IV38_Pos = 0x19       // Position of IV38 field.
	CRYP_IV0RR_IV38_Msk = 0x2000000  // Bit mask of IV38 field.
	CRYP_IV0RR_IV38     = 0x2000000  // Bit IV38.
	CRYP_IV0RR_IV37_Pos = 0x1a       // Position of IV37 field.
	CRYP_IV0RR_IV37_Msk = 0x4000000  // Bit mask of IV37 field.
	CRYP_IV0RR_IV37     = 0x4000000  // Bit IV37.
	CRYP_IV0RR_IV36_Pos = 0x1b       // Position of IV36 field.
	CRYP_IV0RR_IV36_Msk = 0x8000000  // Bit mask of IV36 field.
	CRYP_IV0RR_IV36     = 0x8000000  // Bit IV36.
	CRYP_IV0RR_IV35_Pos = 0x1c       // Position of IV35 field.
	CRYP_IV0RR_IV35_Msk = 0x10000000 // Bit mask of IV35 field.
	CRYP_IV0RR_IV35     = 0x10000000 // Bit IV35.
	CRYP_IV0RR_IV34_Pos = 0x1d       // Position of IV34 field.
	CRYP_IV0RR_IV34_Msk = 0x20000000 // Bit mask of IV34 field.
	CRYP_IV0RR_IV34     = 0x20000000 // Bit IV34.
	CRYP_IV0RR_IV33_Pos = 0x1e       // Position of IV33 field.
	CRYP_IV0RR_IV33_Msk = 0x40000000 // Bit mask of IV33 field.
	CRYP_IV0RR_IV33     = 0x40000000 // Bit IV33.
	CRYP_IV0RR_IV32_Pos = 0x1f       // Position of IV32 field.
	CRYP_IV0RR_IV32_Msk = 0x80000000 // Bit mask of IV32 field.
	CRYP_IV0RR_IV32     = 0x80000000 // Bit IV32.

	// IV1LR: initialization vector           registers
	CRYP_IV1LR_IV95_Pos = 0x0        // Position of IV95 field.
	CRYP_IV1LR_IV95_Msk = 0x1        // Bit mask of IV95 field.
	CRYP_IV1LR_IV95     = 0x1        // Bit IV95.
	CRYP_IV1LR_IV94_Pos = 0x1        // Position of IV94 field.
	CRYP_IV1LR_IV94_Msk = 0x2        // Bit mask of IV94 field.
	CRYP_IV1LR_IV94     = 0x2        // Bit IV94.
	CRYP_IV1LR_IV93_Pos = 0x2        // Position of IV93 field.
	CRYP_IV1LR_IV93_Msk = 0x4        // Bit mask of IV93 field.
	CRYP_IV1LR_IV93     = 0x4        // Bit IV93.
	CRYP_IV1LR_IV92_Pos = 0x3        // Position of IV92 field.
	CRYP_IV1LR_IV92_Msk = 0x8        // Bit mask of IV92 field.
	CRYP_IV1LR_IV92     = 0x8        // Bit IV92.
	CRYP_IV1LR_IV91_Pos = 0x4        // Position of IV91 field.
	CRYP_IV1LR_IV91_Msk = 0x10       // Bit mask of IV91 field.
	CRYP_IV1LR_IV91     = 0x10       // Bit IV91.
	CRYP_IV1LR_IV90_Pos = 0x5        // Position of IV90 field.
	CRYP_IV1LR_IV90_Msk = 0x20       // Bit mask of IV90 field.
	CRYP_IV1LR_IV90     = 0x20       // Bit IV90.
	CRYP_IV1LR_IV89_Pos = 0x6        // Position of IV89 field.
	CRYP_IV1LR_IV89_Msk = 0x40       // Bit mask of IV89 field.
	CRYP_IV1LR_IV89     = 0x40       // Bit IV89.
	CRYP_IV1LR_IV88_Pos = 0x7        // Position of IV88 field.
	CRYP_IV1LR_IV88_Msk = 0x80       // Bit mask of IV88 field.
	CRYP_IV1LR_IV88     = 0x80       // Bit IV88.
	CRYP_IV1LR_IV87_Pos = 0x8        // Position of IV87 field.
	CRYP_IV1LR_IV87_Msk = 0x100      // Bit mask of IV87 field.
	CRYP_IV1LR_IV87     = 0x100      // Bit IV87.
	CRYP_IV1LR_IV86_Pos = 0x9        // Position of IV86 field.
	CRYP_IV1LR_IV86_Msk = 0x200      // Bit mask of IV86 field.
	CRYP_IV1LR_IV86     = 0x200      // Bit IV86.
	CRYP_IV1LR_IV85_Pos = 0xa        // Position of IV85 field.
	CRYP_IV1LR_IV85_Msk = 0x400      // Bit mask of IV85 field.
	CRYP_IV1LR_IV85     = 0x400      // Bit IV85.
	CRYP_IV1LR_IV84_Pos = 0xb        // Position of IV84 field.
	CRYP_IV1LR_IV84_Msk = 0x800      // Bit mask of IV84 field.
	CRYP_IV1LR_IV84     = 0x800      // Bit IV84.
	CRYP_IV1LR_IV83_Pos = 0xc        // Position of IV83 field.
	CRYP_IV1LR_IV83_Msk = 0x1000     // Bit mask of IV83 field.
	CRYP_IV1LR_IV83     = 0x1000     // Bit IV83.
	CRYP_IV1LR_IV82_Pos = 0xd        // Position of IV82 field.
	CRYP_IV1LR_IV82_Msk = 0x2000     // Bit mask of IV82 field.
	CRYP_IV1LR_IV82     = 0x2000     // Bit IV82.
	CRYP_IV1LR_IV81_Pos = 0xe        // Position of IV81 field.
	CRYP_IV1LR_IV81_Msk = 0x4000     // Bit mask of IV81 field.
	CRYP_IV1LR_IV81     = 0x4000     // Bit IV81.
	CRYP_IV1LR_IV80_Pos = 0xf        // Position of IV80 field.
	CRYP_IV1LR_IV80_Msk = 0x8000     // Bit mask of IV80 field.
	CRYP_IV1LR_IV80     = 0x8000     // Bit IV80.
	CRYP_IV1LR_IV79_Pos = 0x10       // Position of IV79 field.
	CRYP_IV1LR_IV79_Msk = 0x10000    // Bit mask of IV79 field.
	CRYP_IV1LR_IV79     = 0x10000    // Bit IV79.
	CRYP_IV1LR_IV78_Pos = 0x11       // Position of IV78 field.
	CRYP_IV1LR_IV78_Msk = 0x20000    // Bit mask of IV78 field.
	CRYP_IV1LR_IV78     = 0x20000    // Bit IV78.
	CRYP_IV1LR_IV77_Pos = 0x12       // Position of IV77 field.
	CRYP_IV1LR_IV77_Msk = 0x40000    // Bit mask of IV77 field.
	CRYP_IV1LR_IV77     = 0x40000    // Bit IV77.
	CRYP_IV1LR_IV76_Pos = 0x13       // Position of IV76 field.
	CRYP_IV1LR_IV76_Msk = 0x80000    // Bit mask of IV76 field.
	CRYP_IV1LR_IV76     = 0x80000    // Bit IV76.
	CRYP_IV1LR_IV75_Pos = 0x14       // Position of IV75 field.
	CRYP_IV1LR_IV75_Msk = 0x100000   // Bit mask of IV75 field.
	CRYP_IV1LR_IV75     = 0x100000   // Bit IV75.
	CRYP_IV1LR_IV74_Pos = 0x15       // Position of IV74 field.
	CRYP_IV1LR_IV74_Msk = 0x200000   // Bit mask of IV74 field.
	CRYP_IV1LR_IV74     = 0x200000   // Bit IV74.
	CRYP_IV1LR_IV73_Pos = 0x16       // Position of IV73 field.
	CRYP_IV1LR_IV73_Msk = 0x400000   // Bit mask of IV73 field.
	CRYP_IV1LR_IV73     = 0x400000   // Bit IV73.
	CRYP_IV1LR_IV72_Pos = 0x17       // Position of IV72 field.
	CRYP_IV1LR_IV72_Msk = 0x800000   // Bit mask of IV72 field.
	CRYP_IV1LR_IV72     = 0x800000   // Bit IV72.
	CRYP_IV1LR_IV71_Pos = 0x18       // Position of IV71 field.
	CRYP_IV1LR_IV71_Msk = 0x1000000  // Bit mask of IV71 field.
	CRYP_IV1LR_IV71     = 0x1000000  // Bit IV71.
	CRYP_IV1LR_IV70_Pos = 0x19       // Position of IV70 field.
	CRYP_IV1LR_IV70_Msk = 0x2000000  // Bit mask of IV70 field.
	CRYP_IV1LR_IV70     = 0x2000000  // Bit IV70.
	CRYP_IV1LR_IV69_Pos = 0x1a       // Position of IV69 field.
	CRYP_IV1LR_IV69_Msk = 0x4000000  // Bit mask of IV69 field.
	CRYP_IV1LR_IV69     = 0x4000000  // Bit IV69.
	CRYP_IV1LR_IV68_Pos = 0x1b       // Position of IV68 field.
	CRYP_IV1LR_IV68_Msk = 0x8000000  // Bit mask of IV68 field.
	CRYP_IV1LR_IV68     = 0x8000000  // Bit IV68.
	CRYP_IV1LR_IV67_Pos = 0x1c       // Position of IV67 field.
	CRYP_IV1LR_IV67_Msk = 0x10000000 // Bit mask of IV67 field.
	CRYP_IV1LR_IV67     = 0x10000000 // Bit IV67.
	CRYP_IV1LR_IV66_Pos = 0x1d       // Position of IV66 field.
	CRYP_IV1LR_IV66_Msk = 0x20000000 // Bit mask of IV66 field.
	CRYP_IV1LR_IV66     = 0x20000000 // Bit IV66.
	CRYP_IV1LR_IV65_Pos = 0x1e       // Position of IV65 field.
	CRYP_IV1LR_IV65_Msk = 0x40000000 // Bit mask of IV65 field.
	CRYP_IV1LR_IV65     = 0x40000000 // Bit IV65.
	CRYP_IV1LR_IV64_Pos = 0x1f       // Position of IV64 field.
	CRYP_IV1LR_IV64_Msk = 0x80000000 // Bit mask of IV64 field.
	CRYP_IV1LR_IV64     = 0x80000000 // Bit IV64.

	// IV1RR: initialization vector           registers
	CRYP_IV1RR_IV127_Pos = 0x0        // Position of IV127 field.
	CRYP_IV1RR_IV127_Msk = 0x1        // Bit mask of IV127 field.
	CRYP_IV1RR_IV127     = 0x1        // Bit IV127.
	CRYP_IV1RR_IV126_Pos = 0x1        // Position of IV126 field.
	CRYP_IV1RR_IV126_Msk = 0x2        // Bit mask of IV126 field.
	CRYP_IV1RR_IV126     = 0x2        // Bit IV126.
	CRYP_IV1RR_IV125_Pos = 0x2        // Position of IV125 field.
	CRYP_IV1RR_IV125_Msk = 0x4        // Bit mask of IV125 field.
	CRYP_IV1RR_IV125     = 0x4        // Bit IV125.
	CRYP_IV1RR_IV124_Pos = 0x3        // Position of IV124 field.
	CRYP_IV1RR_IV124_Msk = 0x8        // Bit mask of IV124 field.
	CRYP_IV1RR_IV124     = 0x8        // Bit IV124.
	CRYP_IV1RR_IV123_Pos = 0x4        // Position of IV123 field.
	CRYP_IV1RR_IV123_Msk = 0x10       // Bit mask of IV123 field.
	CRYP_IV1RR_IV123     = 0x10       // Bit IV123.
	CRYP_IV1RR_IV122_Pos = 0x5        // Position of IV122 field.
	CRYP_IV1RR_IV122_Msk = 0x20       // Bit mask of IV122 field.
	CRYP_IV1RR_IV122     = 0x20       // Bit IV122.
	CRYP_IV1RR_IV121_Pos = 0x6        // Position of IV121 field.
	CRYP_IV1RR_IV121_Msk = 0x40       // Bit mask of IV121 field.
	CRYP_IV1RR_IV121     = 0x40       // Bit IV121.
	CRYP_IV1RR_IV120_Pos = 0x7        // Position of IV120 field.
	CRYP_IV1RR_IV120_Msk = 0x80       // Bit mask of IV120 field.
	CRYP_IV1RR_IV120     = 0x80       // Bit IV120.
	CRYP_IV1RR_IV119_Pos = 0x8        // Position of IV119 field.
	CRYP_IV1RR_IV119_Msk = 0x100      // Bit mask of IV119 field.
	CRYP_IV1RR_IV119     = 0x100      // Bit IV119.
	CRYP_IV1RR_IV118_Pos = 0x9        // Position of IV118 field.
	CRYP_IV1RR_IV118_Msk = 0x200      // Bit mask of IV118 field.
	CRYP_IV1RR_IV118     = 0x200      // Bit IV118.
	CRYP_IV1RR_IV117_Pos = 0xa        // Position of IV117 field.
	CRYP_IV1RR_IV117_Msk = 0x400      // Bit mask of IV117 field.
	CRYP_IV1RR_IV117     = 0x400      // Bit IV117.
	CRYP_IV1RR_IV116_Pos = 0xb        // Position of IV116 field.
	CRYP_IV1RR_IV116_Msk = 0x800      // Bit mask of IV116 field.
	CRYP_IV1RR_IV116     = 0x800      // Bit IV116.
	CRYP_IV1RR_IV115_Pos = 0xc        // Position of IV115 field.
	CRYP_IV1RR_IV115_Msk = 0x1000     // Bit mask of IV115 field.
	CRYP_IV1RR_IV115     = 0x1000     // Bit IV115.
	CRYP_IV1RR_IV114_Pos = 0xd        // Position of IV114 field.
	CRYP_IV1RR_IV114_Msk = 0x2000     // Bit mask of IV114 field.
	CRYP_IV1RR_IV114     = 0x2000     // Bit IV114.
	CRYP_IV1RR_IV113_Pos = 0xe        // Position of IV113 field.
	CRYP_IV1RR_IV113_Msk = 0x4000     // Bit mask of IV113 field.
	CRYP_IV1RR_IV113     = 0x4000     // Bit IV113.
	CRYP_IV1RR_IV112_Pos = 0xf        // Position of IV112 field.
	CRYP_IV1RR_IV112_Msk = 0x8000     // Bit mask of IV112 field.
	CRYP_IV1RR_IV112     = 0x8000     // Bit IV112.
	CRYP_IV1RR_IV111_Pos = 0x10       // Position of IV111 field.
	CRYP_IV1RR_IV111_Msk = 0x10000    // Bit mask of IV111 field.
	CRYP_IV1RR_IV111     = 0x10000    // Bit IV111.
	CRYP_IV1RR_IV110_Pos = 0x11       // Position of IV110 field.
	CRYP_IV1RR_IV110_Msk = 0x20000    // Bit mask of IV110 field.
	CRYP_IV1RR_IV110     = 0x20000    // Bit IV110.
	CRYP_IV1RR_IV109_Pos = 0x12       // Position of IV109 field.
	CRYP_IV1RR_IV109_Msk = 0x40000    // Bit mask of IV109 field.
	CRYP_IV1RR_IV109     = 0x40000    // Bit IV109.
	CRYP_IV1RR_IV108_Pos = 0x13       // Position of IV108 field.
	CRYP_IV1RR_IV108_Msk = 0x80000    // Bit mask of IV108 field.
	CRYP_IV1RR_IV108     = 0x80000    // Bit IV108.
	CRYP_IV1RR_IV107_Pos = 0x14       // Position of IV107 field.
	CRYP_IV1RR_IV107_Msk = 0x100000   // Bit mask of IV107 field.
	CRYP_IV1RR_IV107     = 0x100000   // Bit IV107.
	CRYP_IV1RR_IV106_Pos = 0x15       // Position of IV106 field.
	CRYP_IV1RR_IV106_Msk = 0x200000   // Bit mask of IV106 field.
	CRYP_IV1RR_IV106     = 0x200000   // Bit IV106.
	CRYP_IV1RR_IV105_Pos = 0x16       // Position of IV105 field.
	CRYP_IV1RR_IV105_Msk = 0x400000   // Bit mask of IV105 field.
	CRYP_IV1RR_IV105     = 0x400000   // Bit IV105.
	CRYP_IV1RR_IV104_Pos = 0x17       // Position of IV104 field.
	CRYP_IV1RR_IV104_Msk = 0x800000   // Bit mask of IV104 field.
	CRYP_IV1RR_IV104     = 0x800000   // Bit IV104.
	CRYP_IV1RR_IV103_Pos = 0x18       // Position of IV103 field.
	CRYP_IV1RR_IV103_Msk = 0x1000000  // Bit mask of IV103 field.
	CRYP_IV1RR_IV103     = 0x1000000  // Bit IV103.
	CRYP_IV1RR_IV102_Pos = 0x19       // Position of IV102 field.
	CRYP_IV1RR_IV102_Msk = 0x2000000  // Bit mask of IV102 field.
	CRYP_IV1RR_IV102     = 0x2000000  // Bit IV102.
	CRYP_IV1RR_IV101_Pos = 0x1a       // Position of IV101 field.
	CRYP_IV1RR_IV101_Msk = 0x4000000  // Bit mask of IV101 field.
	CRYP_IV1RR_IV101     = 0x4000000  // Bit IV101.
	CRYP_IV1RR_IV100_Pos = 0x1b       // Position of IV100 field.
	CRYP_IV1RR_IV100_Msk = 0x8000000  // Bit mask of IV100 field.
	CRYP_IV1RR_IV100     = 0x8000000  // Bit IV100.
	CRYP_IV1RR_IV99_Pos  = 0x1c       // Position of IV99 field.
	CRYP_IV1RR_IV99_Msk  = 0x10000000 // Bit mask of IV99 field.
	CRYP_IV1RR_IV99      = 0x10000000 // Bit IV99.
	CRYP_IV1RR_IV98_Pos  = 0x1d       // Position of IV98 field.
	CRYP_IV1RR_IV98_Msk  = 0x20000000 // Bit mask of IV98 field.
	CRYP_IV1RR_IV98      = 0x20000000 // Bit IV98.
	CRYP_IV1RR_IV97_Pos  = 0x1e       // Position of IV97 field.
	CRYP_IV1RR_IV97_Msk  = 0x40000000 // Bit mask of IV97 field.
	CRYP_IV1RR_IV97      = 0x40000000 // Bit IV97.
	CRYP_IV1RR_IV96_Pos  = 0x1f       // Position of IV96 field.
	CRYP_IV1RR_IV96_Msk  = 0x80000000 // Bit mask of IV96 field.
	CRYP_IV1RR_IV96      = 0x80000000 // Bit IV96.

	// CSGCMCCM0R: context swap register
	CRYP_CSGCMCCM0R_CSGCMCCM0_Pos = 0x0        // Position of CSGCMCCM0 field.
	CRYP_CSGCMCCM0R_CSGCMCCM0_Msk = 0xffffffff // Bit mask of CSGCMCCM0 field.

	// CSGCMCCM1R: context swap register
	CRYP_CSGCMCCM1R_CSGCMCCM1_Pos = 0x0        // Position of CSGCMCCM1 field.
	CRYP_CSGCMCCM1R_CSGCMCCM1_Msk = 0xffffffff // Bit mask of CSGCMCCM1 field.

	// CSGCMCCM2R: context swap register
	CRYP_CSGCMCCM2R_CSGCMCCM2_Pos = 0x0        // Position of CSGCMCCM2 field.
	CRYP_CSGCMCCM2R_CSGCMCCM2_Msk = 0xffffffff // Bit mask of CSGCMCCM2 field.

	// CSGCMCCM3R: context swap register
	CRYP_CSGCMCCM3R_CSGCMCCM3_Pos = 0x0        // Position of CSGCMCCM3 field.
	CRYP_CSGCMCCM3R_CSGCMCCM3_Msk = 0xffffffff // Bit mask of CSGCMCCM3 field.

	// CSGCMCCM4R: context swap register
	CRYP_CSGCMCCM4R_CSGCMCCM4_Pos = 0x0        // Position of CSGCMCCM4 field.
	CRYP_CSGCMCCM4R_CSGCMCCM4_Msk = 0xffffffff // Bit mask of CSGCMCCM4 field.

	// CSGCMCCM5R: context swap register
	CRYP_CSGCMCCM5R_CSGCMCCM5_Pos = 0x0        // Position of CSGCMCCM5 field.
	CRYP_CSGCMCCM5R_CSGCMCCM5_Msk = 0xffffffff // Bit mask of CSGCMCCM5 field.

	// CSGCMCCM6R: context swap register
	CRYP_CSGCMCCM6R_CSGCMCCM6_Pos = 0x0        // Position of CSGCMCCM6 field.
	CRYP_CSGCMCCM6R_CSGCMCCM6_Msk = 0xffffffff // Bit mask of CSGCMCCM6 field.

	// CSGCMCCM7R: context swap register
	CRYP_CSGCMCCM7R_CSGCMCCM7_Pos = 0x0        // Position of CSGCMCCM7 field.
	CRYP_CSGCMCCM7R_CSGCMCCM7_Msk = 0xffffffff // Bit mask of CSGCMCCM7 field.

	// CSGCM0R: context swap register
	CRYP_CSGCM0R_CSGCM0_Pos = 0x0        // Position of CSGCM0 field.
	CRYP_CSGCM0R_CSGCM0_Msk = 0xffffffff // Bit mask of CSGCM0 field.

	// CSGCM1R: context swap register
	CRYP_CSGCM1R_CSGCM1_Pos = 0x0        // Position of CSGCM1 field.
	CRYP_CSGCM1R_CSGCM1_Msk = 0xffffffff // Bit mask of CSGCM1 field.

	// CSGCM2R: context swap register
	CRYP_CSGCM2R_CSGCM2_Pos = 0x0        // Position of CSGCM2 field.
	CRYP_CSGCM2R_CSGCM2_Msk = 0xffffffff // Bit mask of CSGCM2 field.

	// CSGCM3R: context swap register
	CRYP_CSGCM3R_CSGCM3_Pos = 0x0        // Position of CSGCM3 field.
	CRYP_CSGCM3R_CSGCM3_Msk = 0xffffffff // Bit mask of CSGCM3 field.

	// CSGCM4R: context swap register
	CRYP_CSGCM4R_CSGCM4_Pos = 0x0        // Position of CSGCM4 field.
	CRYP_CSGCM4R_CSGCM4_Msk = 0xffffffff // Bit mask of CSGCM4 field.

	// CSGCM5R: context swap register
	CRYP_CSGCM5R_CSGCM5_Pos = 0x0        // Position of CSGCM5 field.
	CRYP_CSGCM5R_CSGCM5_Msk = 0xffffffff // Bit mask of CSGCM5 field.

	// CSGCM6R: context swap register
	CRYP_CSGCM6R_CSGCM6_Pos = 0x0        // Position of CSGCM6 field.
	CRYP_CSGCM6R_CSGCM6_Msk = 0xffffffff // Bit mask of CSGCM6 field.

	// CSGCM7R: context swap register
	CRYP_CSGCM7R_CSGCM7_Pos = 0x0        // Position of CSGCM7 field.
	CRYP_CSGCM7R_CSGCM7_Msk = 0xffffffff // Bit mask of CSGCM7 field.
)

// Bitfields for DCMI: Digital camera interface
const (
	// CR: control register 1
	DCMI_CR_OELS_Pos    = 0x14     // Position of OELS field.
	DCMI_CR_OELS_Msk    = 0x100000 // Bit mask of OELS field.
	DCMI_CR_OELS        = 0x100000 // Bit OELS.
	DCMI_CR_LSM_Pos     = 0x13     // Position of LSM field.
	DCMI_CR_LSM_Msk     = 0x80000  // Bit mask of LSM field.
	DCMI_CR_LSM         = 0x80000  // Bit LSM.
	DCMI_CR_OEBS_Pos    = 0x12     // Position of OEBS field.
	DCMI_CR_OEBS_Msk    = 0x40000  // Bit mask of OEBS field.
	DCMI_CR_OEBS        = 0x40000  // Bit OEBS.
	DCMI_CR_BSM_Pos     = 0x10     // Position of BSM field.
	DCMI_CR_BSM_Msk     = 0x30000  // Bit mask of BSM field.
	DCMI_CR_ENABLE_Pos  = 0xe      // Position of ENABLE field.
	DCMI_CR_ENABLE_Msk  = 0x4000   // Bit mask of ENABLE field.
	DCMI_CR_ENABLE      = 0x4000   // Bit ENABLE.
	DCMI_CR_EDM_Pos     = 0xa      // Position of EDM field.
	DCMI_CR_EDM_Msk     = 0xc00    // Bit mask of EDM field.
	DCMI_CR_FCRC_Pos    = 0x8      // Position of FCRC field.
	DCMI_CR_FCRC_Msk    = 0x300    // Bit mask of FCRC field.
	DCMI_CR_VSPOL_Pos   = 0x7      // Position of VSPOL field.
	DCMI_CR_VSPOL_Msk   = 0x80     // Bit mask of VSPOL field.
	DCMI_CR_VSPOL       = 0x80     // Bit VSPOL.
	DCMI_CR_HSPOL_Pos   = 0x6      // Position of HSPOL field.
	DCMI_CR_HSPOL_Msk   = 0x40     // Bit mask of HSPOL field.
	DCMI_CR_HSPOL       = 0x40     // Bit HSPOL.
	DCMI_CR_PCKPOL_Pos  = 0x5      // Position of PCKPOL field.
	DCMI_CR_PCKPOL_Msk  = 0x20     // Bit mask of PCKPOL field.
	DCMI_CR_PCKPOL      = 0x20     // Bit PCKPOL.
	DCMI_CR_ESS_Pos     = 0x4      // Position of ESS field.
	DCMI_CR_ESS_Msk     = 0x10     // Bit mask of ESS field.
	DCMI_CR_ESS         = 0x10     // Bit ESS.
	DCMI_CR_JPEG_Pos    = 0x3      // Position of JPEG field.
	DCMI_CR_JPEG_Msk    = 0x8      // Bit mask of JPEG field.
	DCMI_CR_JPEG        = 0x8      // Bit JPEG.
	DCMI_CR_CROP_Pos    = 0x2      // Position of CROP field.
	DCMI_CR_CROP_Msk    = 0x4      // Bit mask of CROP field.
	DCMI_CR_CROP        = 0x4      // Bit CROP.
	DCMI_CR_CM_Pos      = 0x1      // Position of CM field.
	DCMI_CR_CM_Msk      = 0x2      // Bit mask of CM field.
	DCMI_CR_CM          = 0x2      // Bit CM.
	DCMI_CR_CAPTURE_Pos = 0x0      // Position of CAPTURE field.
	DCMI_CR_CAPTURE_Msk = 0x1      // Bit mask of CAPTURE field.
	DCMI_CR_CAPTURE     = 0x1      // Bit CAPTURE.

	// SR: status register
	DCMI_SR_FNE_Pos   = 0x2 // Position of FNE field.
	DCMI_SR_FNE_Msk   = 0x4 // Bit mask of FNE field.
	DCMI_SR_FNE       = 0x4 // Bit FNE.
	DCMI_SR_VSYNC_Pos = 0x1 // Position of VSYNC field.
	DCMI_SR_VSYNC_Msk = 0x2 // Bit mask of VSYNC field.
	DCMI_SR_VSYNC     = 0x2 // Bit VSYNC.
	DCMI_SR_HSYNC_Pos = 0x0 // Position of HSYNC field.
	DCMI_SR_HSYNC_Msk = 0x1 // Bit mask of HSYNC field.
	DCMI_SR_HSYNC     = 0x1 // Bit HSYNC.

	// RIS: raw interrupt status register
	DCMI_RIS_LINE_RIS_Pos  = 0x4  // Position of LINE_RIS field.
	DCMI_RIS_LINE_RIS_Msk  = 0x10 // Bit mask of LINE_RIS field.
	DCMI_RIS_LINE_RIS      = 0x10 // Bit LINE_RIS.
	DCMI_RIS_VSYNC_RIS_Pos = 0x3  // Position of VSYNC_RIS field.
	DCMI_RIS_VSYNC_RIS_Msk = 0x8  // Bit mask of VSYNC_RIS field.
	DCMI_RIS_VSYNC_RIS     = 0x8  // Bit VSYNC_RIS.
	DCMI_RIS_ERR_RIS_Pos   = 0x2  // Position of ERR_RIS field.
	DCMI_RIS_ERR_RIS_Msk   = 0x4  // Bit mask of ERR_RIS field.
	DCMI_RIS_ERR_RIS       = 0x4  // Bit ERR_RIS.
	DCMI_RIS_OVR_RIS_Pos   = 0x1  // Position of OVR_RIS field.
	DCMI_RIS_OVR_RIS_Msk   = 0x2  // Bit mask of OVR_RIS field.
	DCMI_RIS_OVR_RIS       = 0x2  // Bit OVR_RIS.
	DCMI_RIS_FRAME_RIS_Pos = 0x0  // Position of FRAME_RIS field.
	DCMI_RIS_FRAME_RIS_Msk = 0x1  // Bit mask of FRAME_RIS field.
	DCMI_RIS_FRAME_RIS     = 0x1  // Bit FRAME_RIS.

	// IER: interrupt enable register
	DCMI_IER_LINE_IE_Pos  = 0x4  // Position of LINE_IE field.
	DCMI_IER_LINE_IE_Msk  = 0x10 // Bit mask of LINE_IE field.
	DCMI_IER_LINE_IE      = 0x10 // Bit LINE_IE.
	DCMI_IER_VSYNC_IE_Pos = 0x3  // Position of VSYNC_IE field.
	DCMI_IER_VSYNC_IE_Msk = 0x8  // Bit mask of VSYNC_IE field.
	DCMI_IER_VSYNC_IE     = 0x8  // Bit VSYNC_IE.
	DCMI_IER_ERR_IE_Pos   = 0x2  // Position of ERR_IE field.
	DCMI_IER_ERR_IE_Msk   = 0x4  // Bit mask of ERR_IE field.
	DCMI_IER_ERR_IE       = 0x4  // Bit ERR_IE.
	DCMI_IER_OVR_IE_Pos   = 0x1  // Position of OVR_IE field.
	DCMI_IER_OVR_IE_Msk   = 0x2  // Bit mask of OVR_IE field.
	DCMI_IER_OVR_IE       = 0x2  // Bit OVR_IE.
	DCMI_IER_FRAME_IE_Pos = 0x0  // Position of FRAME_IE field.
	DCMI_IER_FRAME_IE_Msk = 0x1  // Bit mask of FRAME_IE field.
	DCMI_IER_FRAME_IE     = 0x1  // Bit FRAME_IE.

	// MIS: masked interrupt status           register
	DCMI_MIS_LINE_MIS_Pos  = 0x4  // Position of LINE_MIS field.
	DCMI_MIS_LINE_MIS_Msk  = 0x10 // Bit mask of LINE_MIS field.
	DCMI_MIS_LINE_MIS      = 0x10 // Bit LINE_MIS.
	DCMI_MIS_VSYNC_MIS_Pos = 0x3  // Position of VSYNC_MIS field.
	DCMI_MIS_VSYNC_MIS_Msk = 0x8  // Bit mask of VSYNC_MIS field.
	DCMI_MIS_VSYNC_MIS     = 0x8  // Bit VSYNC_MIS.
	DCMI_MIS_ERR_MIS_Pos   = 0x2  // Position of ERR_MIS field.
	DCMI_MIS_ERR_MIS_Msk   = 0x4  // Bit mask of ERR_MIS field.
	DCMI_MIS_ERR_MIS       = 0x4  // Bit ERR_MIS.
	DCMI_MIS_OVR_MIS_Pos   = 0x1  // Position of OVR_MIS field.
	DCMI_MIS_OVR_MIS_Msk   = 0x2  // Bit mask of OVR_MIS field.
	DCMI_MIS_OVR_MIS       = 0x2  // Bit OVR_MIS.
	DCMI_MIS_FRAME_MIS_Pos = 0x0  // Position of FRAME_MIS field.
	DCMI_MIS_FRAME_MIS_Msk = 0x1  // Bit mask of FRAME_MIS field.
	DCMI_MIS_FRAME_MIS     = 0x1  // Bit FRAME_MIS.

	// ICR: interrupt clear register
	DCMI_ICR_LINE_ISC_Pos  = 0x4  // Position of LINE_ISC field.
	DCMI_ICR_LINE_ISC_Msk  = 0x10 // Bit mask of LINE_ISC field.
	DCMI_ICR_LINE_ISC      = 0x10 // Bit LINE_ISC.
	DCMI_ICR_VSYNC_ISC_Pos = 0x3  // Position of VSYNC_ISC field.
	DCMI_ICR_VSYNC_ISC_Msk = 0x8  // Bit mask of VSYNC_ISC field.
	DCMI_ICR_VSYNC_ISC     = 0x8  // Bit VSYNC_ISC.
	DCMI_ICR_ERR_ISC_Pos   = 0x2  // Position of ERR_ISC field.
	DCMI_ICR_ERR_ISC_Msk   = 0x4  // Bit mask of ERR_ISC field.
	DCMI_ICR_ERR_ISC       = 0x4  // Bit ERR_ISC.
	DCMI_ICR_OVR_ISC_Pos   = 0x1  // Position of OVR_ISC field.
	DCMI_ICR_OVR_ISC_Msk   = 0x2  // Bit mask of OVR_ISC field.
	DCMI_ICR_OVR_ISC       = 0x2  // Bit OVR_ISC.
	DCMI_ICR_FRAME_ISC_Pos = 0x0  // Position of FRAME_ISC field.
	DCMI_ICR_FRAME_ISC_Msk = 0x1  // Bit mask of FRAME_ISC field.
	DCMI_ICR_FRAME_ISC     = 0x1  // Bit FRAME_ISC.

	// ESCR: embedded synchronization code           register
	DCMI_ESCR_FEC_Pos = 0x18       // Position of FEC field.
	DCMI_ESCR_FEC_Msk = 0xff000000 // Bit mask of FEC field.
	DCMI_ESCR_LEC_Pos = 0x10       // Position of LEC field.
	DCMI_ESCR_LEC_Msk = 0xff0000   // Bit mask of LEC field.
	DCMI_ESCR_LSC_Pos = 0x8        // Position of LSC field.
	DCMI_ESCR_LSC_Msk = 0xff00     // Bit mask of LSC field.
	DCMI_ESCR_FSC_Pos = 0x0        // Position of FSC field.
	DCMI_ESCR_FSC_Msk = 0xff       // Bit mask of FSC field.

	// ESUR: embedded synchronization unmask           register
	DCMI_ESUR_FEU_Pos = 0x18       // Position of FEU field.
	DCMI_ESUR_FEU_Msk = 0xff000000 // Bit mask of FEU field.
	DCMI_ESUR_LEU_Pos = 0x10       // Position of LEU field.
	DCMI_ESUR_LEU_Msk = 0xff0000   // Bit mask of LEU field.
	DCMI_ESUR_LSU_Pos = 0x8        // Position of LSU field.
	DCMI_ESUR_LSU_Msk = 0xff00     // Bit mask of LSU field.
	DCMI_ESUR_FSU_Pos = 0x0        // Position of FSU field.
	DCMI_ESUR_FSU_Msk = 0xff       // Bit mask of FSU field.

	// CWSTRT: crop window start
	DCMI_CWSTRT_VST_Pos     = 0x10       // Position of VST field.
	DCMI_CWSTRT_VST_Msk     = 0x1fff0000 // Bit mask of VST field.
	DCMI_CWSTRT_HOFFCNT_Pos = 0x0        // Position of HOFFCNT field.
	DCMI_CWSTRT_HOFFCNT_Msk = 0x3fff     // Bit mask of HOFFCNT field.

	// CWSIZE: crop window size
	DCMI_CWSIZE_VLINE_Pos  = 0x10       // Position of VLINE field.
	DCMI_CWSIZE_VLINE_Msk  = 0x3fff0000 // Bit mask of VLINE field.
	DCMI_CWSIZE_CAPCNT_Pos = 0x0        // Position of CAPCNT field.
	DCMI_CWSIZE_CAPCNT_Msk = 0x3fff     // Bit mask of CAPCNT field.

	// DR: data register
	DCMI_DR_Byte3_Pos = 0x18       // Position of Byte3 field.
	DCMI_DR_Byte3_Msk = 0xff000000 // Bit mask of Byte3 field.
	DCMI_DR_Byte2_Pos = 0x10       // Position of Byte2 field.
	DCMI_DR_Byte2_Msk = 0xff0000   // Bit mask of Byte2 field.
	DCMI_DR_Byte1_Pos = 0x8        // Position of Byte1 field.
	DCMI_DR_Byte1_Msk = 0xff00     // Bit mask of Byte1 field.
	DCMI_DR_Byte0_Pos = 0x0        // Position of Byte0 field.
	DCMI_DR_Byte0_Msk = 0xff       // Bit mask of Byte0 field.
)

// Bitfields for OTG1_HS_GLOBAL: USB 1 on the go high speed
const (
	// OTG_HS_GOTGCTL: OTG_HS control and status           register
	USB_OTG_HS_OTG_HS_GOTGCTL_SRQSCS_Pos  = 0x0     // Position of SRQSCS field.
	USB_OTG_HS_OTG_HS_GOTGCTL_SRQSCS_Msk  = 0x1     // Bit mask of SRQSCS field.
	USB_OTG_HS_OTG_HS_GOTGCTL_SRQSCS      = 0x1     // Bit SRQSCS.
	USB_OTG_HS_OTG_HS_GOTGCTL_SRQ_Pos     = 0x1     // Position of SRQ field.
	USB_OTG_HS_OTG_HS_GOTGCTL_SRQ_Msk     = 0x2     // Bit mask of SRQ field.
	USB_OTG_HS_OTG_HS_GOTGCTL_SRQ         = 0x2     // Bit SRQ.
	USB_OTG_HS_OTG_HS_GOTGCTL_HNGSCS_Pos  = 0x8     // Position of HNGSCS field.
	USB_OTG_HS_OTG_HS_GOTGCTL_HNGSCS_Msk  = 0x100   // Bit mask of HNGSCS field.
	USB_OTG_HS_OTG_HS_GOTGCTL_HNGSCS      = 0x100   // Bit HNGSCS.
	USB_OTG_HS_OTG_HS_GOTGCTL_HNPRQ_Pos   = 0x9     // Position of HNPRQ field.
	USB_OTG_HS_OTG_HS_GOTGCTL_HNPRQ_Msk   = 0x200   // Bit mask of HNPRQ field.
	USB_OTG_HS_OTG_HS_GOTGCTL_HNPRQ       = 0x200   // Bit HNPRQ.
	USB_OTG_HS_OTG_HS_GOTGCTL_HSHNPEN_Pos = 0xa     // Position of HSHNPEN field.
	USB_OTG_HS_OTG_HS_GOTGCTL_HSHNPEN_Msk = 0x400   // Bit mask of HSHNPEN field.
	USB_OTG_HS_OTG_HS_GOTGCTL_HSHNPEN     = 0x400   // Bit HSHNPEN.
	USB_OTG_HS_OTG_HS_GOTGCTL_DHNPEN_Pos  = 0xb     // Position of DHNPEN field.
	USB_OTG_HS_OTG_HS_GOTGCTL_DHNPEN_Msk  = 0x800   // Bit mask of DHNPEN field.
	USB_OTG_HS_OTG_HS_GOTGCTL_DHNPEN      = 0x800   // Bit DHNPEN.
	USB_OTG_HS_OTG_HS_GOTGCTL_CIDSTS_Pos  = 0x10    // Position of CIDSTS field.
	USB_OTG_HS_OTG_HS_GOTGCTL_CIDSTS_Msk  = 0x10000 // Bit mask of CIDSTS field.
	USB_OTG_HS_OTG_HS_GOTGCTL_CIDSTS      = 0x10000 // Bit CIDSTS.
	USB_OTG_HS_OTG_HS_GOTGCTL_DBCT_Pos    = 0x11    // Position of DBCT field.
	USB_OTG_HS_OTG_HS_GOTGCTL_DBCT_Msk    = 0x20000 // Bit mask of DBCT field.
	USB_OTG_HS_OTG_HS_GOTGCTL_DBCT        = 0x20000 // Bit DBCT.
	USB_OTG_HS_OTG_HS_GOTGCTL_ASVLD_Pos   = 0x12    // Position of ASVLD field.
	USB_OTG_HS_OTG_HS_GOTGCTL_ASVLD_Msk   = 0x40000 // Bit mask of ASVLD field.
	USB_OTG_HS_OTG_HS_GOTGCTL_ASVLD       = 0x40000 // Bit ASVLD.
	USB_OTG_HS_OTG_HS_GOTGCTL_BSVLD_Pos   = 0x13    // Position of BSVLD field.
	USB_OTG_HS_OTG_HS_GOTGCTL_BSVLD_Msk   = 0x80000 // Bit mask of BSVLD field.
	USB_OTG_HS_OTG_HS_GOTGCTL_BSVLD       = 0x80000 // Bit BSVLD.
	USB_OTG_HS_OTG_HS_GOTGCTL_EHEN_Pos    = 0xc     // Position of EHEN field.
	USB_OTG_HS_OTG_HS_GOTGCTL_EHEN_Msk    = 0x1000  // Bit mask of EHEN field.
	USB_OTG_HS_OTG_HS_GOTGCTL_EHEN        = 0x1000  // Bit EHEN.

	// OTG_HS_GOTGINT: OTG_HS interrupt register
	USB_OTG_HS_OTG_HS_GOTGINT_SEDET_Pos   = 0x2      // Position of SEDET field.
	USB_OTG_HS_OTG_HS_GOTGINT_SEDET_Msk   = 0x4      // Bit mask of SEDET field.
	USB_OTG_HS_OTG_HS_GOTGINT_SEDET       = 0x4      // Bit SEDET.
	USB_OTG_HS_OTG_HS_GOTGINT_SRSSCHG_Pos = 0x8      // Position of SRSSCHG field.
	USB_OTG_HS_OTG_HS_GOTGINT_SRSSCHG_Msk = 0x100    // Bit mask of SRSSCHG field.
	USB_OTG_HS_OTG_HS_GOTGINT_SRSSCHG     = 0x100    // Bit SRSSCHG.
	USB_OTG_HS_OTG_HS_GOTGINT_HNSSCHG_Pos = 0x9      // Position of HNSSCHG field.
	USB_OTG_HS_OTG_HS_GOTGINT_HNSSCHG_Msk = 0x200    // Bit mask of HNSSCHG field.
	USB_OTG_HS_OTG_HS_GOTGINT_HNSSCHG     = 0x200    // Bit HNSSCHG.
	USB_OTG_HS_OTG_HS_GOTGINT_HNGDET_Pos  = 0x11     // Position of HNGDET field.
	USB_OTG_HS_OTG_HS_GOTGINT_HNGDET_Msk  = 0x20000  // Bit mask of HNGDET field.
	USB_OTG_HS_OTG_HS_GOTGINT_HNGDET      = 0x20000  // Bit HNGDET.
	USB_OTG_HS_OTG_HS_GOTGINT_ADTOCHG_Pos = 0x12     // Position of ADTOCHG field.
	USB_OTG_HS_OTG_HS_GOTGINT_ADTOCHG_Msk = 0x40000  // Bit mask of ADTOCHG field.
	USB_OTG_HS_OTG_HS_GOTGINT_ADTOCHG     = 0x40000  // Bit ADTOCHG.
	USB_OTG_HS_OTG_HS_GOTGINT_DBCDNE_Pos  = 0x13     // Position of DBCDNE field.
	USB_OTG_HS_OTG_HS_GOTGINT_DBCDNE_Msk  = 0x80000  // Bit mask of DBCDNE field.
	USB_OTG_HS_OTG_HS_GOTGINT_DBCDNE      = 0x80000  // Bit DBCDNE.
	USB_OTG_HS_OTG_HS_GOTGINT_IDCHNG_Pos  = 0x14     // Position of IDCHNG field.
	USB_OTG_HS_OTG_HS_GOTGINT_IDCHNG_Msk  = 0x100000 // Bit mask of IDCHNG field.
	USB_OTG_HS_OTG_HS_GOTGINT_IDCHNG      = 0x100000 // Bit IDCHNG.

	// OTG_HS_GAHBCFG: OTG_HS AHB configuration           register
	USB_OTG_HS_OTG_HS_GAHBCFG_GINT_Pos     = 0x0   // Position of GINT field.
	USB_OTG_HS_OTG_HS_GAHBCFG_GINT_Msk     = 0x1   // Bit mask of GINT field.
	USB_OTG_HS_OTG_HS_GAHBCFG_GINT         = 0x1   // Bit GINT.
	USB_OTG_HS_OTG_HS_GAHBCFG_HBSTLEN_Pos  = 0x1   // Position of HBSTLEN field.
	USB_OTG_HS_OTG_HS_GAHBCFG_HBSTLEN_Msk  = 0x1e  // Bit mask of HBSTLEN field.
	USB_OTG_HS_OTG_HS_GAHBCFG_DMAEN_Pos    = 0x5   // Position of DMAEN field.
	USB_OTG_HS_OTG_HS_GAHBCFG_DMAEN_Msk    = 0x20  // Bit mask of DMAEN field.
	USB_OTG_HS_OTG_HS_GAHBCFG_DMAEN        = 0x20  // Bit DMAEN.
	USB_OTG_HS_OTG_HS_GAHBCFG_TXFELVL_Pos  = 0x7   // Position of TXFELVL field.
	USB_OTG_HS_OTG_HS_GAHBCFG_TXFELVL_Msk  = 0x80  // Bit mask of TXFELVL field.
	USB_OTG_HS_OTG_HS_GAHBCFG_TXFELVL      = 0x80  // Bit TXFELVL.
	USB_OTG_HS_OTG_HS_GAHBCFG_PTXFELVL_Pos = 0x8   // Position of PTXFELVL field.
	USB_OTG_HS_OTG_HS_GAHBCFG_PTXFELVL_Msk = 0x100 // Bit mask of PTXFELVL field.
	USB_OTG_HS_OTG_HS_GAHBCFG_PTXFELVL     = 0x100 // Bit PTXFELVL.

	// OTG_HS_GUSBCFG: OTG_HS USB configuration           register
	USB_OTG_HS_OTG_HS_GUSBCFG_TOCAL_Pos      = 0x0        // Position of TOCAL field.
	USB_OTG_HS_OTG_HS_GUSBCFG_TOCAL_Msk      = 0x7        // Bit mask of TOCAL field.
	USB_OTG_HS_OTG_HS_GUSBCFG_PHYSEL_Pos     = 0x6        // Position of PHYSEL field.
	USB_OTG_HS_OTG_HS_GUSBCFG_PHYSEL_Msk     = 0x40       // Bit mask of PHYSEL field.
	USB_OTG_HS_OTG_HS_GUSBCFG_PHYSEL         = 0x40       // Bit PHYSEL.
	USB_OTG_HS_OTG_HS_GUSBCFG_SRPCAP_Pos     = 0x8        // Position of SRPCAP field.
	USB_OTG_HS_OTG_HS_GUSBCFG_SRPCAP_Msk     = 0x100      // Bit mask of SRPCAP field.
	USB_OTG_HS_OTG_HS_GUSBCFG_SRPCAP         = 0x100      // Bit SRPCAP.
	USB_OTG_HS_OTG_HS_GUSBCFG_HNPCAP_Pos     = 0x9        // Position of HNPCAP field.
	USB_OTG_HS_OTG_HS_GUSBCFG_HNPCAP_Msk     = 0x200      // Bit mask of HNPCAP field.
	USB_OTG_HS_OTG_HS_GUSBCFG_HNPCAP         = 0x200      // Bit HNPCAP.
	USB_OTG_HS_OTG_HS_GUSBCFG_TRDT_Pos       = 0xa        // Position of TRDT field.
	USB_OTG_HS_OTG_HS_GUSBCFG_TRDT_Msk       = 0x3c00     // Bit mask of TRDT field.
	USB_OTG_HS_OTG_HS_GUSBCFG_PHYLPCS_Pos    = 0xf        // Position of PHYLPCS field.
	USB_OTG_HS_OTG_HS_GUSBCFG_PHYLPCS_Msk    = 0x8000     // Bit mask of PHYLPCS field.
	USB_OTG_HS_OTG_HS_GUSBCFG_PHYLPCS        = 0x8000     // Bit PHYLPCS.
	USB_OTG_HS_OTG_HS_GUSBCFG_ULPIFSLS_Pos   = 0x11       // Position of ULPIFSLS field.
	USB_OTG_HS_OTG_HS_GUSBCFG_ULPIFSLS_Msk   = 0x20000    // Bit mask of ULPIFSLS field.
	USB_OTG_HS_OTG_HS_GUSBCFG_ULPIFSLS       = 0x20000    // Bit ULPIFSLS.
	USB_OTG_HS_OTG_HS_GUSBCFG_ULPIAR_Pos     = 0x12       // Position of ULPIAR field.
	USB_OTG_HS_OTG_HS_GUSBCFG_ULPIAR_Msk     = 0x40000    // Bit mask of ULPIAR field.
	USB_OTG_HS_OTG_HS_GUSBCFG_ULPIAR         = 0x40000    // Bit ULPIAR.
	USB_OTG_HS_OTG_HS_GUSBCFG_ULPICSM_Pos    = 0x13       // Position of ULPICSM field.
	USB_OTG_HS_OTG_HS_GUSBCFG_ULPICSM_Msk    = 0x80000    // Bit mask of ULPICSM field.
	USB_OTG_HS_OTG_HS_GUSBCFG_ULPICSM        = 0x80000    // Bit ULPICSM.
	USB_OTG_HS_OTG_HS_GUSBCFG_ULPIEVBUSD_Pos = 0x14       // Position of ULPIEVBUSD field.
	USB_OTG_HS_OTG_HS_GUSBCFG_ULPIEVBUSD_Msk = 0x100000   // Bit mask of ULPIEVBUSD field.
	USB_OTG_HS_OTG_HS_GUSBCFG_ULPIEVBUSD     = 0x100000   // Bit ULPIEVBUSD.
	USB_OTG_HS_OTG_HS_GUSBCFG_ULPIEVBUSI_Pos = 0x15       // Position of ULPIEVBUSI field.
	USB_OTG_HS_OTG_HS_GUSBCFG_ULPIEVBUSI_Msk = 0x200000   // Bit mask of ULPIEVBUSI field.
	USB_OTG_HS_OTG_HS_GUSBCFG_ULPIEVBUSI     = 0x200000   // Bit ULPIEVBUSI.
	USB_OTG_HS_OTG_HS_GUSBCFG_TSDPS_Pos      = 0x16       // Position of TSDPS field.
	USB_OTG_HS_OTG_HS_GUSBCFG_TSDPS_Msk      = 0x400000   // Bit mask of TSDPS field.
	USB_OTG_HS_OTG_HS_GUSBCFG_TSDPS          = 0x400000   // Bit TSDPS.
	USB_OTG_HS_OTG_HS_GUSBCFG_PCCI_Pos       = 0x17       // Position of PCCI field.
	USB_OTG_HS_OTG_HS_GUSBCFG_PCCI_Msk       = 0x800000   // Bit mask of PCCI field.
	USB_OTG_HS_OTG_HS_GUSBCFG_PCCI           = 0x800000   // Bit PCCI.
	USB_OTG_HS_OTG_HS_GUSBCFG_PTCI_Pos       = 0x18       // Position of PTCI field.
	USB_OTG_HS_OTG_HS_GUSBCFG_PTCI_Msk       = 0x1000000  // Bit mask of PTCI field.
	USB_OTG_HS_OTG_HS_GUSBCFG_PTCI           = 0x1000000  // Bit PTCI.
	USB_OTG_HS_OTG_HS_GUSBCFG_ULPIIPD_Pos    = 0x19       // Position of ULPIIPD field.
	USB_OTG_HS_OTG_HS_GUSBCFG_ULPIIPD_Msk    = 0x2000000  // Bit mask of ULPIIPD field.
	USB_OTG_HS_OTG_HS_GUSBCFG_ULPIIPD        = 0x2000000  // Bit ULPIIPD.
	USB_OTG_HS_OTG_HS_GUSBCFG_FHMOD_Pos      = 0x1d       // Position of FHMOD field.
	USB_OTG_HS_OTG_HS_GUSBCFG_FHMOD_Msk      = 0x20000000 // Bit mask of FHMOD field.
	USB_OTG_HS_OTG_HS_GUSBCFG_FHMOD          = 0x20000000 // Bit FHMOD.
	USB_OTG_HS_OTG_HS_GUSBCFG_FDMOD_Pos      = 0x1e       // Position of FDMOD field.
	USB_OTG_HS_OTG_HS_GUSBCFG_FDMOD_Msk      = 0x40000000 // Bit mask of FDMOD field.
	USB_OTG_HS_OTG_HS_GUSBCFG_FDMOD          = 0x40000000 // Bit FDMOD.

	// OTG_HS_GRSTCTL: OTG_HS reset register
	USB_OTG_HS_OTG_HS_GRSTCTL_CSRST_Pos   = 0x0        // Position of CSRST field.
	USB_OTG_HS_OTG_HS_GRSTCTL_CSRST_Msk   = 0x1        // Bit mask of CSRST field.
	USB_OTG_HS_OTG_HS_GRSTCTL_CSRST       = 0x1        // Bit CSRST.
	USB_OTG_HS_OTG_HS_GRSTCTL_HSRST_Pos   = 0x1        // Position of HSRST field.
	USB_OTG_HS_OTG_HS_GRSTCTL_HSRST_Msk   = 0x2        // Bit mask of HSRST field.
	USB_OTG_HS_OTG_HS_GRSTCTL_HSRST       = 0x2        // Bit HSRST.
	USB_OTG_HS_OTG_HS_GRSTCTL_FCRST_Pos   = 0x2        // Position of FCRST field.
	USB_OTG_HS_OTG_HS_GRSTCTL_FCRST_Msk   = 0x4        // Bit mask of FCRST field.
	USB_OTG_HS_OTG_HS_GRSTCTL_FCRST       = 0x4        // Bit FCRST.
	USB_OTG_HS_OTG_HS_GRSTCTL_RXFFLSH_Pos = 0x4        // Position of RXFFLSH field.
	USB_OTG_HS_OTG_HS_GRSTCTL_RXFFLSH_Msk = 0x10       // Bit mask of RXFFLSH field.
	USB_OTG_HS_OTG_HS_GRSTCTL_RXFFLSH     = 0x10       // Bit RXFFLSH.
	USB_OTG_HS_OTG_HS_GRSTCTL_TXFFLSH_Pos = 0x5        // Position of TXFFLSH field.
	USB_OTG_HS_OTG_HS_GRSTCTL_TXFFLSH_Msk = 0x20       // Bit mask of TXFFLSH field.
	USB_OTG_HS_OTG_HS_GRSTCTL_TXFFLSH     = 0x20       // Bit TXFFLSH.
	USB_OTG_HS_OTG_HS_GRSTCTL_TXFNUM_Pos  = 0x6        // Position of TXFNUM field.
	USB_OTG_HS_OTG_HS_GRSTCTL_TXFNUM_Msk  = 0x7c0      // Bit mask of TXFNUM field.
	USB_OTG_HS_OTG_HS_GRSTCTL_AHBIDL_Pos  = 0x1f       // Position of AHBIDL field.
	USB_OTG_HS_OTG_HS_GRSTCTL_AHBIDL_Msk  = 0x80000000 // Bit mask of AHBIDL field.
	USB_OTG_HS_OTG_HS_GRSTCTL_AHBIDL      = 0x80000000 // Bit AHBIDL.
	USB_OTG_HS_OTG_HS_GRSTCTL_DMAREQ_Pos  = 0x1e       // Position of DMAREQ field.
	USB_OTG_HS_OTG_HS_GRSTCTL_DMAREQ_Msk  = 0x40000000 // Bit mask of DMAREQ field.
	USB_OTG_HS_OTG_HS_GRSTCTL_DMAREQ      = 0x40000000 // Bit DMAREQ.

	// OTG_HS_GINTSTS: OTG_HS core interrupt register
	USB_OTG_HS_OTG_HS_GINTSTS_CMOD_Pos              = 0x0        // Position of CMOD field.
	USB_OTG_HS_OTG_HS_GINTSTS_CMOD_Msk              = 0x1        // Bit mask of CMOD field.
	USB_OTG_HS_OTG_HS_GINTSTS_CMOD                  = 0x1        // Bit CMOD.
	USB_OTG_HS_OTG_HS_GINTSTS_MMIS_Pos              = 0x1        // Position of MMIS field.
	USB_OTG_HS_OTG_HS_GINTSTS_MMIS_Msk              = 0x2        // Bit mask of MMIS field.
	USB_OTG_HS_OTG_HS_GINTSTS_MMIS                  = 0x2        // Bit MMIS.
	USB_OTG_HS_OTG_HS_GINTSTS_OTGINT_Pos            = 0x2        // Position of OTGINT field.
	USB_OTG_HS_OTG_HS_GINTSTS_OTGINT_Msk            = 0x4        // Bit mask of OTGINT field.
	USB_OTG_HS_OTG_HS_GINTSTS_OTGINT                = 0x4        // Bit OTGINT.
	USB_OTG_HS_OTG_HS_GINTSTS_SOF_Pos               = 0x3        // Position of SOF field.
	USB_OTG_HS_OTG_HS_GINTSTS_SOF_Msk               = 0x8        // Bit mask of SOF field.
	USB_OTG_HS_OTG_HS_GINTSTS_SOF                   = 0x8        // Bit SOF.
	USB_OTG_HS_OTG_HS_GINTSTS_RXFLVL_Pos            = 0x4        // Position of RXFLVL field.
	USB_OTG_HS_OTG_HS_GINTSTS_RXFLVL_Msk            = 0x10       // Bit mask of RXFLVL field.
	USB_OTG_HS_OTG_HS_GINTSTS_RXFLVL                = 0x10       // Bit RXFLVL.
	USB_OTG_HS_OTG_HS_GINTSTS_NPTXFE_Pos            = 0x5        // Position of NPTXFE field.
	USB_OTG_HS_OTG_HS_GINTSTS_NPTXFE_Msk            = 0x20       // Bit mask of NPTXFE field.
	USB_OTG_HS_OTG_HS_GINTSTS_NPTXFE                = 0x20       // Bit NPTXFE.
	USB_OTG_HS_OTG_HS_GINTSTS_GINAKEFF_Pos          = 0x6        // Position of GINAKEFF field.
	USB_OTG_HS_OTG_HS_GINTSTS_GINAKEFF_Msk          = 0x40       // Bit mask of GINAKEFF field.
	USB_OTG_HS_OTG_HS_GINTSTS_GINAKEFF              = 0x40       // Bit GINAKEFF.
	USB_OTG_HS_OTG_HS_GINTSTS_BOUTNAKEFF_Pos        = 0x7        // Position of BOUTNAKEFF field.
	USB_OTG_HS_OTG_HS_GINTSTS_BOUTNAKEFF_Msk        = 0x80       // Bit mask of BOUTNAKEFF field.
	USB_OTG_HS_OTG_HS_GINTSTS_BOUTNAKEFF            = 0x80       // Bit BOUTNAKEFF.
	USB_OTG_HS_OTG_HS_GINTSTS_ESUSP_Pos             = 0xa        // Position of ESUSP field.
	USB_OTG_HS_OTG_HS_GINTSTS_ESUSP_Msk             = 0x400      // Bit mask of ESUSP field.
	USB_OTG_HS_OTG_HS_GINTSTS_ESUSP                 = 0x400      // Bit ESUSP.
	USB_OTG_HS_OTG_HS_GINTSTS_USBSUSP_Pos           = 0xb        // Position of USBSUSP field.
	USB_OTG_HS_OTG_HS_GINTSTS_USBSUSP_Msk           = 0x800      // Bit mask of USBSUSP field.
	USB_OTG_HS_OTG_HS_GINTSTS_USBSUSP               = 0x800      // Bit USBSUSP.
	USB_OTG_HS_OTG_HS_GINTSTS_USBRST_Pos            = 0xc        // Position of USBRST field.
	USB_OTG_HS_OTG_HS_GINTSTS_USBRST_Msk            = 0x1000     // Bit mask of USBRST field.
	USB_OTG_HS_OTG_HS_GINTSTS_USBRST                = 0x1000     // Bit USBRST.
	USB_OTG_HS_OTG_HS_GINTSTS_ENUMDNE_Pos           = 0xd        // Position of ENUMDNE field.
	USB_OTG_HS_OTG_HS_GINTSTS_ENUMDNE_Msk           = 0x2000     // Bit mask of ENUMDNE field.
	USB_OTG_HS_OTG_HS_GINTSTS_ENUMDNE               = 0x2000     // Bit ENUMDNE.
	USB_OTG_HS_OTG_HS_GINTSTS_ISOODRP_Pos           = 0xe        // Position of ISOODRP field.
	USB_OTG_HS_OTG_HS_GINTSTS_ISOODRP_Msk           = 0x4000     // Bit mask of ISOODRP field.
	USB_OTG_HS_OTG_HS_GINTSTS_ISOODRP               = 0x4000     // Bit ISOODRP.
	USB_OTG_HS_OTG_HS_GINTSTS_EOPF_Pos              = 0xf        // Position of EOPF field.
	USB_OTG_HS_OTG_HS_GINTSTS_EOPF_Msk              = 0x8000     // Bit mask of EOPF field.
	USB_OTG_HS_OTG_HS_GINTSTS_EOPF                  = 0x8000     // Bit EOPF.
	USB_OTG_HS_OTG_HS_GINTSTS_IEPINT_Pos            = 0x12       // Position of IEPINT field.
	USB_OTG_HS_OTG_HS_GINTSTS_IEPINT_Msk            = 0x40000    // Bit mask of IEPINT field.
	USB_OTG_HS_OTG_HS_GINTSTS_IEPINT                = 0x40000    // Bit IEPINT.
	USB_OTG_HS_OTG_HS_GINTSTS_OEPINT_Pos            = 0x13       // Position of OEPINT field.
	USB_OTG_HS_OTG_HS_GINTSTS_OEPINT_Msk            = 0x80000    // Bit mask of OEPINT field.
	USB_OTG_HS_OTG_HS_GINTSTS_OEPINT                = 0x80000    // Bit OEPINT.
	USB_OTG_HS_OTG_HS_GINTSTS_IISOIXFR_Pos          = 0x14       // Position of IISOIXFR field.
	USB_OTG_HS_OTG_HS_GINTSTS_IISOIXFR_Msk          = 0x100000   // Bit mask of IISOIXFR field.
	USB_OTG_HS_OTG_HS_GINTSTS_IISOIXFR              = 0x100000   // Bit IISOIXFR.
	USB_OTG_HS_OTG_HS_GINTSTS_PXFR_INCOMPISOOUT_Pos = 0x15       // Position of PXFR_INCOMPISOOUT field.
	USB_OTG_HS_OTG_HS_GINTSTS_PXFR_INCOMPISOOUT_Msk = 0x200000   // Bit mask of PXFR_INCOMPISOOUT field.
	USB_OTG_HS_OTG_HS_GINTSTS_PXFR_INCOMPISOOUT     = 0x200000   // Bit PXFR_INCOMPISOOUT.
	USB_OTG_HS_OTG_HS_GINTSTS_DATAFSUSP_Pos         = 0x16       // Position of DATAFSUSP field.
	USB_OTG_HS_OTG_HS_GINTSTS_DATAFSUSP_Msk         = 0x400000   // Bit mask of DATAFSUSP field.
	USB_OTG_HS_OTG_HS_GINTSTS_DATAFSUSP             = 0x400000   // Bit DATAFSUSP.
	USB_OTG_HS_OTG_HS_GINTSTS_HPRTINT_Pos           = 0x18       // Position of HPRTINT field.
	USB_OTG_HS_OTG_HS_GINTSTS_HPRTINT_Msk           = 0x1000000  // Bit mask of HPRTINT field.
	USB_OTG_HS_OTG_HS_GINTSTS_HPRTINT               = 0x1000000  // Bit HPRTINT.
	USB_OTG_HS_OTG_HS_GINTSTS_HCINT_Pos             = 0x19       // Position of HCINT field.
	USB_OTG_HS_OTG_HS_GINTSTS_HCINT_Msk             = 0x2000000  // Bit mask of HCINT field.
	USB_OTG_HS_OTG_HS_GINTSTS_HCINT                 = 0x2000000  // Bit HCINT.
	USB_OTG_HS_OTG_HS_GINTSTS_PTXFE_Pos             = 0x1a       // Position of PTXFE field.
	USB_OTG_HS_OTG_HS_GINTSTS_PTXFE_Msk             = 0x4000000  // Bit mask of PTXFE field.
	USB_OTG_HS_OTG_HS_GINTSTS_PTXFE                 = 0x4000000  // Bit PTXFE.
	USB_OTG_HS_OTG_HS_GINTSTS_CIDSCHG_Pos           = 0x1c       // Position of CIDSCHG field.
	USB_OTG_HS_OTG_HS_GINTSTS_CIDSCHG_Msk           = 0x10000000 // Bit mask of CIDSCHG field.
	USB_OTG_HS_OTG_HS_GINTSTS_CIDSCHG               = 0x10000000 // Bit CIDSCHG.
	USB_OTG_HS_OTG_HS_GINTSTS_DISCINT_Pos           = 0x1d       // Position of DISCINT field.
	USB_OTG_HS_OTG_HS_GINTSTS_DISCINT_Msk           = 0x20000000 // Bit mask of DISCINT field.
	USB_OTG_HS_OTG_HS_GINTSTS_DISCINT               = 0x20000000 // Bit DISCINT.
	USB_OTG_HS_OTG_HS_GINTSTS_SRQINT_Pos            = 0x1e       // Position of SRQINT field.
	USB_OTG_HS_OTG_HS_GINTSTS_SRQINT_Msk            = 0x40000000 // Bit mask of SRQINT field.
	USB_OTG_HS_OTG_HS_GINTSTS_SRQINT                = 0x40000000 // Bit SRQINT.
	USB_OTG_HS_OTG_HS_GINTSTS_WKUINT_Pos            = 0x1f       // Position of WKUINT field.
	USB_OTG_HS_OTG_HS_GINTSTS_WKUINT_Msk            = 0x80000000 // Bit mask of WKUINT field.
	USB_OTG_HS_OTG_HS_GINTSTS_WKUINT                = 0x80000000 // Bit WKUINT.

	// OTG_HS_GINTMSK: OTG_HS interrupt mask register
	USB_OTG_HS_OTG_HS_GINTMSK_MMISM_Pos           = 0x1        // Position of MMISM field.
	USB_OTG_HS_OTG_HS_GINTMSK_MMISM_Msk           = 0x2        // Bit mask of MMISM field.
	USB_OTG_HS_OTG_HS_GINTMSK_MMISM               = 0x2        // Bit MMISM.
	USB_OTG_HS_OTG_HS_GINTMSK_OTGINT_Pos          = 0x2        // Position of OTGINT field.
	USB_OTG_HS_OTG_HS_GINTMSK_OTGINT_Msk          = 0x4        // Bit mask of OTGINT field.
	USB_OTG_HS_OTG_HS_GINTMSK_OTGINT              = 0x4        // Bit OTGINT.
	USB_OTG_HS_OTG_HS_GINTMSK_SOFM_Pos            = 0x3        // Position of SOFM field.
	USB_OTG_HS_OTG_HS_GINTMSK_SOFM_Msk            = 0x8        // Bit mask of SOFM field.
	USB_OTG_HS_OTG_HS_GINTMSK_SOFM                = 0x8        // Bit SOFM.
	USB_OTG_HS_OTG_HS_GINTMSK_RXFLVLM_Pos         = 0x4        // Position of RXFLVLM field.
	USB_OTG_HS_OTG_HS_GINTMSK_RXFLVLM_Msk         = 0x10       // Bit mask of RXFLVLM field.
	USB_OTG_HS_OTG_HS_GINTMSK_RXFLVLM             = 0x10       // Bit RXFLVLM.
	USB_OTG_HS_OTG_HS_GINTMSK_NPTXFEM_Pos         = 0x5        // Position of NPTXFEM field.
	USB_OTG_HS_OTG_HS_GINTMSK_NPTXFEM_Msk         = 0x20       // Bit mask of NPTXFEM field.
	USB_OTG_HS_OTG_HS_GINTMSK_NPTXFEM             = 0x20       // Bit NPTXFEM.
	USB_OTG_HS_OTG_HS_GINTMSK_GINAKEFFM_Pos       = 0x6        // Position of GINAKEFFM field.
	USB_OTG_HS_OTG_HS_GINTMSK_GINAKEFFM_Msk       = 0x40       // Bit mask of GINAKEFFM field.
	USB_OTG_HS_OTG_HS_GINTMSK_GINAKEFFM           = 0x40       // Bit GINAKEFFM.
	USB_OTG_HS_OTG_HS_GINTMSK_GONAKEFFM_Pos       = 0x7        // Position of GONAKEFFM field.
	USB_OTG_HS_OTG_HS_GINTMSK_GONAKEFFM_Msk       = 0x80       // Bit mask of GONAKEFFM field.
	USB_OTG_HS_OTG_HS_GINTMSK_GONAKEFFM           = 0x80       // Bit GONAKEFFM.
	USB_OTG_HS_OTG_HS_GINTMSK_ESUSPM_Pos          = 0xa        // Position of ESUSPM field.
	USB_OTG_HS_OTG_HS_GINTMSK_ESUSPM_Msk          = 0x400      // Bit mask of ESUSPM field.
	USB_OTG_HS_OTG_HS_GINTMSK_ESUSPM              = 0x400      // Bit ESUSPM.
	USB_OTG_HS_OTG_HS_GINTMSK_USBSUSPM_Pos        = 0xb        // Position of USBSUSPM field.
	USB_OTG_HS_OTG_HS_GINTMSK_USBSUSPM_Msk        = 0x800      // Bit mask of USBSUSPM field.
	USB_OTG_HS_OTG_HS_GINTMSK_USBSUSPM            = 0x800      // Bit USBSUSPM.
	USB_OTG_HS_OTG_HS_GINTMSK_USBRST_Pos          = 0xc        // Position of USBRST field.
	USB_OTG_HS_OTG_HS_GINTMSK_USBRST_Msk          = 0x1000     // Bit mask of USBRST field.
	USB_OTG_HS_OTG_HS_GINTMSK_USBRST              = 0x1000     // Bit USBRST.
	USB_OTG_HS_OTG_HS_GINTMSK_ENUMDNEM_Pos        = 0xd        // Position of ENUMDNEM field.
	USB_OTG_HS_OTG_HS_GINTMSK_ENUMDNEM_Msk        = 0x2000     // Bit mask of ENUMDNEM field.
	USB_OTG_HS_OTG_HS_GINTMSK_ENUMDNEM            = 0x2000     // Bit ENUMDNEM.
	USB_OTG_HS_OTG_HS_GINTMSK_ISOODRPM_Pos        = 0xe        // Position of ISOODRPM field.
	USB_OTG_HS_OTG_HS_GINTMSK_ISOODRPM_Msk        = 0x4000     // Bit mask of ISOODRPM field.
	USB_OTG_HS_OTG_HS_GINTMSK_ISOODRPM            = 0x4000     // Bit ISOODRPM.
	USB_OTG_HS_OTG_HS_GINTMSK_EOPFM_Pos           = 0xf        // Position of EOPFM field.
	USB_OTG_HS_OTG_HS_GINTMSK_EOPFM_Msk           = 0x8000     // Bit mask of EOPFM field.
	USB_OTG_HS_OTG_HS_GINTMSK_EOPFM               = 0x8000     // Bit EOPFM.
	USB_OTG_HS_OTG_HS_GINTMSK_IEPINT_Pos          = 0x12       // Position of IEPINT field.
	USB_OTG_HS_OTG_HS_GINTMSK_IEPINT_Msk          = 0x40000    // Bit mask of IEPINT field.
	USB_OTG_HS_OTG_HS_GINTMSK_IEPINT              = 0x40000    // Bit IEPINT.
	USB_OTG_HS_OTG_HS_GINTMSK_OEPINT_Pos          = 0x13       // Position of OEPINT field.
	USB_OTG_HS_OTG_HS_GINTMSK_OEPINT_Msk          = 0x80000    // Bit mask of OEPINT field.
	USB_OTG_HS_OTG_HS_GINTMSK_OEPINT              = 0x80000    // Bit OEPINT.
	USB_OTG_HS_OTG_HS_GINTMSK_IISOIXFRM_Pos       = 0x14       // Position of IISOIXFRM field.
	USB_OTG_HS_OTG_HS_GINTMSK_IISOIXFRM_Msk       = 0x100000   // Bit mask of IISOIXFRM field.
	USB_OTG_HS_OTG_HS_GINTMSK_IISOIXFRM           = 0x100000   // Bit IISOIXFRM.
	USB_OTG_HS_OTG_HS_GINTMSK_PXFRM_IISOOXFRM_Pos = 0x15       // Position of PXFRM_IISOOXFRM field.
	USB_OTG_HS_OTG_HS_GINTMSK_PXFRM_IISOOXFRM_Msk = 0x200000   // Bit mask of PXFRM_IISOOXFRM field.
	USB_OTG_HS_OTG_HS_GINTMSK_PXFRM_IISOOXFRM     = 0x200000   // Bit PXFRM_IISOOXFRM.
	USB_OTG_HS_OTG_HS_GINTMSK_FSUSPM_Pos          = 0x16       // Position of FSUSPM field.
	USB_OTG_HS_OTG_HS_GINTMSK_FSUSPM_Msk          = 0x400000   // Bit mask of FSUSPM field.
	USB_OTG_HS_OTG_HS_GINTMSK_FSUSPM              = 0x400000   // Bit FSUSPM.
	USB_OTG_HS_OTG_HS_GINTMSK_PRTIM_Pos           = 0x18       // Position of PRTIM field.
	USB_OTG_HS_OTG_HS_GINTMSK_PRTIM_Msk           = 0x1000000  // Bit mask of PRTIM field.
	USB_OTG_HS_OTG_HS_GINTMSK_PRTIM               = 0x1000000  // Bit PRTIM.
	USB_OTG_HS_OTG_HS_GINTMSK_HCIM_Pos            = 0x19       // Position of HCIM field.
	USB_OTG_HS_OTG_HS_GINTMSK_HCIM_Msk            = 0x2000000  // Bit mask of HCIM field.
	USB_OTG_HS_OTG_HS_GINTMSK_HCIM                = 0x2000000  // Bit HCIM.
	USB_OTG_HS_OTG_HS_GINTMSK_PTXFEM_Pos          = 0x1a       // Position of PTXFEM field.
	USB_OTG_HS_OTG_HS_GINTMSK_PTXFEM_Msk          = 0x4000000  // Bit mask of PTXFEM field.
	USB_OTG_HS_OTG_HS_GINTMSK_PTXFEM              = 0x4000000  // Bit PTXFEM.
	USB_OTG_HS_OTG_HS_GINTMSK_CIDSCHGM_Pos        = 0x1c       // Position of CIDSCHGM field.
	USB_OTG_HS_OTG_HS_GINTMSK_CIDSCHGM_Msk        = 0x10000000 // Bit mask of CIDSCHGM field.
	USB_OTG_HS_OTG_HS_GINTMSK_CIDSCHGM            = 0x10000000 // Bit CIDSCHGM.
	USB_OTG_HS_OTG_HS_GINTMSK_DISCINT_Pos         = 0x1d       // Position of DISCINT field.
	USB_OTG_HS_OTG_HS_GINTMSK_DISCINT_Msk         = 0x20000000 // Bit mask of DISCINT field.
	USB_OTG_HS_OTG_HS_GINTMSK_DISCINT             = 0x20000000 // Bit DISCINT.
	USB_OTG_HS_OTG_HS_GINTMSK_SRQIM_Pos           = 0x1e       // Position of SRQIM field.
	USB_OTG_HS_OTG_HS_GINTMSK_SRQIM_Msk           = 0x40000000 // Bit mask of SRQIM field.
	USB_OTG_HS_OTG_HS_GINTMSK_SRQIM               = 0x40000000 // Bit SRQIM.
	USB_OTG_HS_OTG_HS_GINTMSK_WUIM_Pos            = 0x1f       // Position of WUIM field.
	USB_OTG_HS_OTG_HS_GINTMSK_WUIM_Msk            = 0x80000000 // Bit mask of WUIM field.
	USB_OTG_HS_OTG_HS_GINTMSK_WUIM                = 0x80000000 // Bit WUIM.
	USB_OTG_HS_OTG_HS_GINTMSK_RSTDE_Pos           = 0x17       // Position of RSTDE field.
	USB_OTG_HS_OTG_HS_GINTMSK_RSTDE_Msk           = 0x800000   // Bit mask of RSTDE field.
	USB_OTG_HS_OTG_HS_GINTMSK_RSTDE               = 0x800000   // Bit RSTDE.
	USB_OTG_HS_OTG_HS_GINTMSK_LPMINTM_Pos         = 0x1b       // Position of LPMINTM field.
	USB_OTG_HS_OTG_HS_GINTMSK_LPMINTM_Msk         = 0x8000000  // Bit mask of LPMINTM field.
	USB_OTG_HS_OTG_HS_GINTMSK_LPMINTM             = 0x8000000  // Bit LPMINTM.

	// OTG_HS_GRXSTSR_Host: OTG_HS Receive status debug read register           (host mode)
	USB_OTG_HS_OTG_HS_GRXSTSR_Host_CHNUM_Pos  = 0x0      // Position of CHNUM field.
	USB_OTG_HS_OTG_HS_GRXSTSR_Host_CHNUM_Msk  = 0xf      // Bit mask of CHNUM field.
	USB_OTG_HS_OTG_HS_GRXSTSR_Host_BCNT_Pos   = 0x4      // Position of BCNT field.
	USB_OTG_HS_OTG_HS_GRXSTSR_Host_BCNT_Msk   = 0x7ff0   // Bit mask of BCNT field.
	USB_OTG_HS_OTG_HS_GRXSTSR_Host_DPID_Pos   = 0xf      // Position of DPID field.
	USB_OTG_HS_OTG_HS_GRXSTSR_Host_DPID_Msk   = 0x18000  // Bit mask of DPID field.
	USB_OTG_HS_OTG_HS_GRXSTSR_Host_PKTSTS_Pos = 0x11     // Position of PKTSTS field.
	USB_OTG_HS_OTG_HS_GRXSTSR_Host_PKTSTS_Msk = 0x1e0000 // Bit mask of PKTSTS field.

	// OTG_HS_GRXSTSR_Device: OTG_HS Receive status debug read register           (peripheral mode mode)
	USB_OTG_HS_OTG_HS_GRXSTSR_Device_EPNUM_Pos  = 0x0       // Position of EPNUM field.
	USB_OTG_HS_OTG_HS_GRXSTSR_Device_EPNUM_Msk  = 0xf       // Bit mask of EPNUM field.
	USB_OTG_HS_OTG_HS_GRXSTSR_Device_BCNT_Pos   = 0x4       // Position of BCNT field.
	USB_OTG_HS_OTG_HS_GRXSTSR_Device_BCNT_Msk   = 0x7ff0    // Bit mask of BCNT field.
	USB_OTG_HS_OTG_HS_GRXSTSR_Device_DPID_Pos   = 0xf       // Position of DPID field.
	USB_OTG_HS_OTG_HS_GRXSTSR_Device_DPID_Msk   = 0x18000   // Bit mask of DPID field.
	USB_OTG_HS_OTG_HS_GRXSTSR_Device_PKTSTS_Pos = 0x11      // Position of PKTSTS field.
	USB_OTG_HS_OTG_HS_GRXSTSR_Device_PKTSTS_Msk = 0x1e0000  // Bit mask of PKTSTS field.
	USB_OTG_HS_OTG_HS_GRXSTSR_Device_FRMNUM_Pos = 0x15      // Position of FRMNUM field.
	USB_OTG_HS_OTG_HS_GRXSTSR_Device_FRMNUM_Msk = 0x1e00000 // Bit mask of FRMNUM field.

	// OTG_HS_GRXSTSP_Host: OTG_HS status read and pop register (host           mode)
	USB_OTG_HS_OTG_HS_GRXSTSP_Host_CHNUM_Pos  = 0x0      // Position of CHNUM field.
	USB_OTG_HS_OTG_HS_GRXSTSP_Host_CHNUM_Msk  = 0xf      // Bit mask of CHNUM field.
	USB_OTG_HS_OTG_HS_GRXSTSP_Host_BCNT_Pos   = 0x4      // Position of BCNT field.
	USB_OTG_HS_OTG_HS_GRXSTSP_Host_BCNT_Msk   = 0x7ff0   // Bit mask of BCNT field.
	USB_OTG_HS_OTG_HS_GRXSTSP_Host_DPID_Pos   = 0xf      // Position of DPID field.
	USB_OTG_HS_OTG_HS_GRXSTSP_Host_DPID_Msk   = 0x18000  // Bit mask of DPID field.
	USB_OTG_HS_OTG_HS_GRXSTSP_Host_PKTSTS_Pos = 0x11     // Position of PKTSTS field.
	USB_OTG_HS_OTG_HS_GRXSTSP_Host_PKTSTS_Msk = 0x1e0000 // Bit mask of PKTSTS field.

	// OTG_HS_GRXSTSP_Device: OTG_HS status read and pop register           (peripheral mode)
	USB_OTG_HS_OTG_HS_GRXSTSP_Device_EPNUM_Pos  = 0x0       // Position of EPNUM field.
	USB_OTG_HS_OTG_HS_GRXSTSP_Device_EPNUM_Msk  = 0xf       // Bit mask of EPNUM field.
	USB_OTG_HS_OTG_HS_GRXSTSP_Device_BCNT_Pos   = 0x4       // Position of BCNT field.
	USB_OTG_HS_OTG_HS_GRXSTSP_Device_BCNT_Msk   = 0x7ff0    // Bit mask of BCNT field.
	USB_OTG_HS_OTG_HS_GRXSTSP_Device_DPID_Pos   = 0xf       // Position of DPID field.
	USB_OTG_HS_OTG_HS_GRXSTSP_Device_DPID_Msk   = 0x18000   // Bit mask of DPID field.
	USB_OTG_HS_OTG_HS_GRXSTSP_Device_PKTSTS_Pos = 0x11      // Position of PKTSTS field.
	USB_OTG_HS_OTG_HS_GRXSTSP_Device_PKTSTS_Msk = 0x1e0000  // Bit mask of PKTSTS field.
	USB_OTG_HS_OTG_HS_GRXSTSP_Device_FRMNUM_Pos = 0x15      // Position of FRMNUM field.
	USB_OTG_HS_OTG_HS_GRXSTSP_Device_FRMNUM_Msk = 0x1e00000 // Bit mask of FRMNUM field.

	// OTG_HS_GRXFSIZ: OTG_HS Receive FIFO size           register
	USB_OTG_HS_OTG_HS_GRXFSIZ_RXFD_Pos = 0x0    // Position of RXFD field.
	USB_OTG_HS_OTG_HS_GRXFSIZ_RXFD_Msk = 0xffff // Bit mask of RXFD field.

	// OTG_HS_HNPTXFSIZ_Host: OTG_HS nonperiodic transmit FIFO size           register (host mode)
	USB_OTG_HS_OTG_HS_HNPTXFSIZ_Host_NPTXFSA_Pos = 0x0        // Position of NPTXFSA field.
	USB_OTG_HS_OTG_HS_HNPTXFSIZ_Host_NPTXFSA_Msk = 0xffff     // Bit mask of NPTXFSA field.
	USB_OTG_HS_OTG_HS_HNPTXFSIZ_Host_NPTXFD_Pos  = 0x10       // Position of NPTXFD field.
	USB_OTG_HS_OTG_HS_HNPTXFSIZ_Host_NPTXFD_Msk  = 0xffff0000 // Bit mask of NPTXFD field.

	// OTG_HS_DIEPTXF0_Device: Endpoint 0 transmit FIFO size (peripheral           mode)
	USB_OTG_HS_OTG_HS_DIEPTXF0_Device_TX0FSA_Pos = 0x0        // Position of TX0FSA field.
	USB_OTG_HS_OTG_HS_DIEPTXF0_Device_TX0FSA_Msk = 0xffff     // Bit mask of TX0FSA field.
	USB_OTG_HS_OTG_HS_DIEPTXF0_Device_TX0FD_Pos  = 0x10       // Position of TX0FD field.
	USB_OTG_HS_OTG_HS_DIEPTXF0_Device_TX0FD_Msk  = 0xffff0000 // Bit mask of TX0FD field.

	// OTG_HS_GNPTXSTS: OTG_HS nonperiodic transmit FIFO/queue           status register
	USB_OTG_HS_OTG_HS_GNPTXSTS_NPTXFSAV_Pos = 0x0        // Position of NPTXFSAV field.
	USB_OTG_HS_OTG_HS_GNPTXSTS_NPTXFSAV_Msk = 0xffff     // Bit mask of NPTXFSAV field.
	USB_OTG_HS_OTG_HS_GNPTXSTS_NPTQXSAV_Pos = 0x10       // Position of NPTQXSAV field.
	USB_OTG_HS_OTG_HS_GNPTXSTS_NPTQXSAV_Msk = 0xff0000   // Bit mask of NPTQXSAV field.
	USB_OTG_HS_OTG_HS_GNPTXSTS_NPTXQTOP_Pos = 0x18       // Position of NPTXQTOP field.
	USB_OTG_HS_OTG_HS_GNPTXSTS_NPTXQTOP_Msk = 0x7f000000 // Bit mask of NPTXQTOP field.

	// OTG_HS_GCCFG: OTG_HS general core configuration           register
	USB_OTG_HS_OTG_HS_GCCFG_PWRDWN_Pos = 0x10     // Position of PWRDWN field.
	USB_OTG_HS_OTG_HS_GCCFG_PWRDWN_Msk = 0x10000  // Bit mask of PWRDWN field.
	USB_OTG_HS_OTG_HS_GCCFG_PWRDWN     = 0x10000  // Bit PWRDWN.
	USB_OTG_HS_OTG_HS_GCCFG_BCDEN_Pos  = 0x11     // Position of BCDEN field.
	USB_OTG_HS_OTG_HS_GCCFG_BCDEN_Msk  = 0x20000  // Bit mask of BCDEN field.
	USB_OTG_HS_OTG_HS_GCCFG_BCDEN      = 0x20000  // Bit BCDEN.
	USB_OTG_HS_OTG_HS_GCCFG_DCDEN_Pos  = 0x12     // Position of DCDEN field.
	USB_OTG_HS_OTG_HS_GCCFG_DCDEN_Msk  = 0x40000  // Bit mask of DCDEN field.
	USB_OTG_HS_OTG_HS_GCCFG_DCDEN      = 0x40000  // Bit DCDEN.
	USB_OTG_HS_OTG_HS_GCCFG_PDEN_Pos   = 0x13     // Position of PDEN field.
	USB_OTG_HS_OTG_HS_GCCFG_PDEN_Msk   = 0x80000  // Bit mask of PDEN field.
	USB_OTG_HS_OTG_HS_GCCFG_PDEN       = 0x80000  // Bit PDEN.
	USB_OTG_HS_OTG_HS_GCCFG_SDEN_Pos   = 0x14     // Position of SDEN field.
	USB_OTG_HS_OTG_HS_GCCFG_SDEN_Msk   = 0x100000 // Bit mask of SDEN field.
	USB_OTG_HS_OTG_HS_GCCFG_SDEN       = 0x100000 // Bit SDEN.
	USB_OTG_HS_OTG_HS_GCCFG_VBDEN_Pos  = 0x15     // Position of VBDEN field.
	USB_OTG_HS_OTG_HS_GCCFG_VBDEN_Msk  = 0x200000 // Bit mask of VBDEN field.
	USB_OTG_HS_OTG_HS_GCCFG_VBDEN      = 0x200000 // Bit VBDEN.
	USB_OTG_HS_OTG_HS_GCCFG_DCDET_Pos  = 0x0      // Position of DCDET field.
	USB_OTG_HS_OTG_HS_GCCFG_DCDET_Msk  = 0x1      // Bit mask of DCDET field.
	USB_OTG_HS_OTG_HS_GCCFG_DCDET      = 0x1      // Bit DCDET.
	USB_OTG_HS_OTG_HS_GCCFG_PDET_Pos   = 0x1      // Position of PDET field.
	USB_OTG_HS_OTG_HS_GCCFG_PDET_Msk   = 0x2      // Bit mask of PDET field.
	USB_OTG_HS_OTG_HS_GCCFG_PDET       = 0x2      // Bit PDET.
	USB_OTG_HS_OTG_HS_GCCFG_SDET_Pos   = 0x2      // Position of SDET field.
	USB_OTG_HS_OTG_HS_GCCFG_SDET_Msk   = 0x4      // Bit mask of SDET field.
	USB_OTG_HS_OTG_HS_GCCFG_SDET       = 0x4      // Bit SDET.
	USB_OTG_HS_OTG_HS_GCCFG_PS2DET_Pos = 0x3      // Position of PS2DET field.
	USB_OTG_HS_OTG_HS_GCCFG_PS2DET_Msk = 0x8      // Bit mask of PS2DET field.
	USB_OTG_HS_OTG_HS_GCCFG_PS2DET     = 0x8      // Bit PS2DET.

	// OTG_HS_CID: OTG_HS core ID register
	USB_OTG_HS_OTG_HS_CID_PRODUCT_ID_Pos = 0x0        // Position of PRODUCT_ID field.
	USB_OTG_HS_OTG_HS_CID_PRODUCT_ID_Msk = 0xffffffff // Bit mask of PRODUCT_ID field.

	// OTG_HS_GLPMCFG: OTG core LPM configuration           register
	USB_OTG_HS_OTG_HS_GLPMCFG_LPMEN_Pos      = 0x0        // Position of LPMEN field.
	USB_OTG_HS_OTG_HS_GLPMCFG_LPMEN_Msk      = 0x1        // Bit mask of LPMEN field.
	USB_OTG_HS_OTG_HS_GLPMCFG_LPMEN          = 0x1        // Bit LPMEN.
	USB_OTG_HS_OTG_HS_GLPMCFG_LPMACK_Pos     = 0x1        // Position of LPMACK field.
	USB_OTG_HS_OTG_HS_GLPMCFG_LPMACK_Msk     = 0x2        // Bit mask of LPMACK field.
	USB_OTG_HS_OTG_HS_GLPMCFG_LPMACK         = 0x2        // Bit LPMACK.
	USB_OTG_HS_OTG_HS_GLPMCFG_BESL_Pos       = 0x2        // Position of BESL field.
	USB_OTG_HS_OTG_HS_GLPMCFG_BESL_Msk       = 0x3c       // Bit mask of BESL field.
	USB_OTG_HS_OTG_HS_GLPMCFG_REMWAKE_Pos    = 0x6        // Position of REMWAKE field.
	USB_OTG_HS_OTG_HS_GLPMCFG_REMWAKE_Msk    = 0x40       // Bit mask of REMWAKE field.
	USB_OTG_HS_OTG_HS_GLPMCFG_REMWAKE        = 0x40       // Bit REMWAKE.
	USB_OTG_HS_OTG_HS_GLPMCFG_L1SSEN_Pos     = 0x7        // Position of L1SSEN field.
	USB_OTG_HS_OTG_HS_GLPMCFG_L1SSEN_Msk     = 0x80       // Bit mask of L1SSEN field.
	USB_OTG_HS_OTG_HS_GLPMCFG_L1SSEN         = 0x80       // Bit L1SSEN.
	USB_OTG_HS_OTG_HS_GLPMCFG_BESLTHRS_Pos   = 0x8        // Position of BESLTHRS field.
	USB_OTG_HS_OTG_HS_GLPMCFG_BESLTHRS_Msk   = 0xf00      // Bit mask of BESLTHRS field.
	USB_OTG_HS_OTG_HS_GLPMCFG_L1DSEN_Pos     = 0xc        // Position of L1DSEN field.
	USB_OTG_HS_OTG_HS_GLPMCFG_L1DSEN_Msk     = 0x1000     // Bit mask of L1DSEN field.
	USB_OTG_HS_OTG_HS_GLPMCFG_L1DSEN         = 0x1000     // Bit L1DSEN.
	USB_OTG_HS_OTG_HS_GLPMCFG_LPMRST_Pos     = 0xd        // Position of LPMRST field.
	USB_OTG_HS_OTG_HS_GLPMCFG_LPMRST_Msk     = 0x6000     // Bit mask of LPMRST field.
	USB_OTG_HS_OTG_HS_GLPMCFG_SLPSTS_Pos     = 0xf        // Position of SLPSTS field.
	USB_OTG_HS_OTG_HS_GLPMCFG_SLPSTS_Msk     = 0x8000     // Bit mask of SLPSTS field.
	USB_OTG_HS_OTG_HS_GLPMCFG_SLPSTS         = 0x8000     // Bit SLPSTS.
	USB_OTG_HS_OTG_HS_GLPMCFG_L1RSMOK_Pos    = 0x10       // Position of L1RSMOK field.
	USB_OTG_HS_OTG_HS_GLPMCFG_L1RSMOK_Msk    = 0x10000    // Bit mask of L1RSMOK field.
	USB_OTG_HS_OTG_HS_GLPMCFG_L1RSMOK        = 0x10000    // Bit L1RSMOK.
	USB_OTG_HS_OTG_HS_GLPMCFG_LPMCHIDX_Pos   = 0x11       // Position of LPMCHIDX field.
	USB_OTG_HS_OTG_HS_GLPMCFG_LPMCHIDX_Msk   = 0x1e0000   // Bit mask of LPMCHIDX field.
	USB_OTG_HS_OTG_HS_GLPMCFG_LPMRCNT_Pos    = 0x15       // Position of LPMRCNT field.
	USB_OTG_HS_OTG_HS_GLPMCFG_LPMRCNT_Msk    = 0xe00000   // Bit mask of LPMRCNT field.
	USB_OTG_HS_OTG_HS_GLPMCFG_SNDLPM_Pos     = 0x18       // Position of SNDLPM field.
	USB_OTG_HS_OTG_HS_GLPMCFG_SNDLPM_Msk     = 0x1000000  // Bit mask of SNDLPM field.
	USB_OTG_HS_OTG_HS_GLPMCFG_SNDLPM         = 0x1000000  // Bit SNDLPM.
	USB_OTG_HS_OTG_HS_GLPMCFG_LPMRCNTSTS_Pos = 0x19       // Position of LPMRCNTSTS field.
	USB_OTG_HS_OTG_HS_GLPMCFG_LPMRCNTSTS_Msk = 0xe000000  // Bit mask of LPMRCNTSTS field.
	USB_OTG_HS_OTG_HS_GLPMCFG_ENBESL_Pos     = 0x1c       // Position of ENBESL field.
	USB_OTG_HS_OTG_HS_GLPMCFG_ENBESL_Msk     = 0x10000000 // Bit mask of ENBESL field.
	USB_OTG_HS_OTG_HS_GLPMCFG_ENBESL         = 0x10000000 // Bit ENBESL.

	// OTG_HS_HPTXFSIZ: OTG_HS Host periodic transmit FIFO size           register
	USB_OTG_HS_OTG_HS_HPTXFSIZ_PTXSA_Pos = 0x0        // Position of PTXSA field.
	USB_OTG_HS_OTG_HS_HPTXFSIZ_PTXSA_Msk = 0xffff     // Bit mask of PTXSA field.
	USB_OTG_HS_OTG_HS_HPTXFSIZ_PTXFD_Pos = 0x10       // Position of PTXFD field.
	USB_OTG_HS_OTG_HS_HPTXFSIZ_PTXFD_Msk = 0xffff0000 // Bit mask of PTXFD field.

	// OTG_HS_DIEPTXF1: OTG_HS device IN endpoint transmit FIFO size           register
	USB_OTG_HS_OTG_HS_DIEPTXF1_INEPTXSA_Pos = 0x0        // Position of INEPTXSA field.
	USB_OTG_HS_OTG_HS_DIEPTXF1_INEPTXSA_Msk = 0xffff     // Bit mask of INEPTXSA field.
	USB_OTG_HS_OTG_HS_DIEPTXF1_INEPTXFD_Pos = 0x10       // Position of INEPTXFD field.
	USB_OTG_HS_OTG_HS_DIEPTXF1_INEPTXFD_Msk = 0xffff0000 // Bit mask of INEPTXFD field.

	// OTG_HS_DIEPTXF2: OTG_HS device IN endpoint transmit FIFO size           register
	USB_OTG_HS_OTG_HS_DIEPTXF2_INEPTXSA_Pos = 0x0        // Position of INEPTXSA field.
	USB_OTG_HS_OTG_HS_DIEPTXF2_INEPTXSA_Msk = 0xffff     // Bit mask of INEPTXSA field.
	USB_OTG_HS_OTG_HS_DIEPTXF2_INEPTXFD_Pos = 0x10       // Position of INEPTXFD field.
	USB_OTG_HS_OTG_HS_DIEPTXF2_INEPTXFD_Msk = 0xffff0000 // Bit mask of INEPTXFD field.

	// OTG_HS_DIEPTXF3: OTG_HS device IN endpoint transmit FIFO size           register
	USB_OTG_HS_OTG_HS_DIEPTXF3_INEPTXSA_Pos = 0x0        // Position of INEPTXSA field.
	USB_OTG_HS_OTG_HS_DIEPTXF3_INEPTXSA_Msk = 0xffff     // Bit mask of INEPTXSA field.
	USB_OTG_HS_OTG_HS_DIEPTXF3_INEPTXFD_Pos = 0x10       // Position of INEPTXFD field.
	USB_OTG_HS_OTG_HS_DIEPTXF3_INEPTXFD_Msk = 0xffff0000 // Bit mask of INEPTXFD field.

	// OTG_HS_DIEPTXF4: OTG_HS device IN endpoint transmit FIFO size           register
	USB_OTG_HS_OTG_HS_DIEPTXF4_INEPTXSA_Pos = 0x0        // Position of INEPTXSA field.
	USB_OTG_HS_OTG_HS_DIEPTXF4_INEPTXSA_Msk = 0xffff     // Bit mask of INEPTXSA field.
	USB_OTG_HS_OTG_HS_DIEPTXF4_INEPTXFD_Pos = 0x10       // Position of INEPTXFD field.
	USB_OTG_HS_OTG_HS_DIEPTXF4_INEPTXFD_Msk = 0xffff0000 // Bit mask of INEPTXFD field.

	// OTG_HS_DIEPTXF5: OTG_HS device IN endpoint transmit FIFO size           register
	USB_OTG_HS_OTG_HS_DIEPTXF5_INEPTXSA_Pos = 0x0        // Position of INEPTXSA field.
	USB_OTG_HS_OTG_HS_DIEPTXF5_INEPTXSA_Msk = 0xffff     // Bit mask of INEPTXSA field.
	USB_OTG_HS_OTG_HS_DIEPTXF5_INEPTXFD_Pos = 0x10       // Position of INEPTXFD field.
	USB_OTG_HS_OTG_HS_DIEPTXF5_INEPTXFD_Msk = 0xffff0000 // Bit mask of INEPTXFD field.

	// OTG_HS_DIEPTXF6: OTG_HS device IN endpoint transmit FIFO size           register
	USB_OTG_HS_OTG_HS_DIEPTXF6_INEPTXSA_Pos = 0x0        // Position of INEPTXSA field.
	USB_OTG_HS_OTG_HS_DIEPTXF6_INEPTXSA_Msk = 0xffff     // Bit mask of INEPTXSA field.
	USB_OTG_HS_OTG_HS_DIEPTXF6_INEPTXFD_Pos = 0x10       // Position of INEPTXFD field.
	USB_OTG_HS_OTG_HS_DIEPTXF6_INEPTXFD_Msk = 0xffff0000 // Bit mask of INEPTXFD field.

	// OTG_HS_DIEPTXF7: OTG_HS device IN endpoint transmit FIFO size           register
	USB_OTG_HS_OTG_HS_DIEPTXF7_INEPTXSA_Pos = 0x0        // Position of INEPTXSA field.
	USB_OTG_HS_OTG_HS_DIEPTXF7_INEPTXSA_Msk = 0xffff     // Bit mask of INEPTXSA field.
	USB_OTG_HS_OTG_HS_DIEPTXF7_INEPTXFD_Pos = 0x10       // Position of INEPTXFD field.
	USB_OTG_HS_OTG_HS_DIEPTXF7_INEPTXFD_Msk = 0xffff0000 // Bit mask of INEPTXFD field.
)

// Bitfields for Ethernet_DMA: Ethernet: DMA mode register (DMA)
const (
	// DMAMR: DMA mode register
	Ethernet_DMAMR_SWR_Pos  = 0x0     // Position of SWR field.
	Ethernet_DMAMR_SWR_Msk  = 0x1     // Bit mask of SWR field.
	Ethernet_DMAMR_SWR      = 0x1     // Bit SWR.
	Ethernet_DMAMR_DA_Pos   = 0x1     // Position of DA field.
	Ethernet_DMAMR_DA_Msk   = 0x2     // Bit mask of DA field.
	Ethernet_DMAMR_DA       = 0x2     // Bit DA.
	Ethernet_DMAMR_TXPR_Pos = 0xb     // Position of TXPR field.
	Ethernet_DMAMR_TXPR_Msk = 0x800   // Bit mask of TXPR field.
	Ethernet_DMAMR_TXPR     = 0x800   // Bit TXPR.
	Ethernet_DMAMR_PR_Pos   = 0xc     // Position of PR field.
	Ethernet_DMAMR_PR_Msk   = 0x7000  // Bit mask of PR field.
	Ethernet_DMAMR_INTM_Pos = 0x10    // Position of INTM field.
	Ethernet_DMAMR_INTM_Msk = 0x10000 // Bit mask of INTM field.
	Ethernet_DMAMR_INTM     = 0x10000 // Bit INTM.

	// DMASBMR: System bus mode register
	Ethernet_DMASBMR_FB_Pos  = 0x0    // Position of FB field.
	Ethernet_DMASBMR_FB_Msk  = 0x1    // Bit mask of FB field.
	Ethernet_DMASBMR_FB      = 0x1    // Bit FB.
	Ethernet_DMASBMR_AAL_Pos = 0xc    // Position of AAL field.
	Ethernet_DMASBMR_AAL_Msk = 0x1000 // Bit mask of AAL field.
	Ethernet_DMASBMR_AAL     = 0x1000 // Bit AAL.
	Ethernet_DMASBMR_MB_Pos  = 0xe    // Position of MB field.
	Ethernet_DMASBMR_MB_Msk  = 0x4000 // Bit mask of MB field.
	Ethernet_DMASBMR_MB      = 0x4000 // Bit MB.
	Ethernet_DMASBMR_RB_Pos  = 0xf    // Position of RB field.
	Ethernet_DMASBMR_RB_Msk  = 0x8000 // Bit mask of RB field.
	Ethernet_DMASBMR_RB      = 0x8000 // Bit RB.

	// DMAISR: Interrupt status register
	Ethernet_DMAISR_DC0IS_Pos = 0x0     // Position of DC0IS field.
	Ethernet_DMAISR_DC0IS_Msk = 0x1     // Bit mask of DC0IS field.
	Ethernet_DMAISR_DC0IS     = 0x1     // Bit DC0IS.
	Ethernet_DMAISR_MTLIS_Pos = 0x10    // Position of MTLIS field.
	Ethernet_DMAISR_MTLIS_Msk = 0x10000 // Bit mask of MTLIS field.
	Ethernet_DMAISR_MTLIS     = 0x10000 // Bit MTLIS.
	Ethernet_DMAISR_MACIS_Pos = 0x11    // Position of MACIS field.
	Ethernet_DMAISR_MACIS_Msk = 0x20000 // Bit mask of MACIS field.
	Ethernet_DMAISR_MACIS     = 0x20000 // Bit MACIS.

	// DMADSR: Debug status register
	Ethernet_DMADSR_AXWHSTS_Pos = 0x0    // Position of AXWHSTS field.
	Ethernet_DMADSR_AXWHSTS_Msk = 0x1    // Bit mask of AXWHSTS field.
	Ethernet_DMADSR_AXWHSTS     = 0x1    // Bit AXWHSTS.
	Ethernet_DMADSR_RPS0_Pos    = 0x8    // Position of RPS0 field.
	Ethernet_DMADSR_RPS0_Msk    = 0xf00  // Bit mask of RPS0 field.
	Ethernet_DMADSR_TPS0_Pos    = 0xc    // Position of TPS0 field.
	Ethernet_DMADSR_TPS0_Msk    = 0xf000 // Bit mask of TPS0 field.

	// DMACCR: Channel control register
	Ethernet_DMACCR_MSS_Pos   = 0x0      // Position of MSS field.
	Ethernet_DMACCR_MSS_Msk   = 0x3fff   // Bit mask of MSS field.
	Ethernet_DMACCR_PBLX8_Pos = 0x10     // Position of PBLX8 field.
	Ethernet_DMACCR_PBLX8_Msk = 0x10000  // Bit mask of PBLX8 field.
	Ethernet_DMACCR_PBLX8     = 0x10000  // Bit PBLX8.
	Ethernet_DMACCR_DSL_Pos   = 0x12     // Position of DSL field.
	Ethernet_DMACCR_DSL_Msk   = 0x1c0000 // Bit mask of DSL field.

	// DMACTxCR: Channel transmit control           register
	Ethernet_DMACTxCR_ST_Pos    = 0x0      // Position of ST field.
	Ethernet_DMACTxCR_ST_Msk    = 0x1      // Bit mask of ST field.
	Ethernet_DMACTxCR_ST        = 0x1      // Bit ST.
	Ethernet_DMACTxCR_OSF_Pos   = 0x4      // Position of OSF field.
	Ethernet_DMACTxCR_OSF_Msk   = 0x10     // Bit mask of OSF field.
	Ethernet_DMACTxCR_OSF       = 0x10     // Bit OSF.
	Ethernet_DMACTxCR_TSE_Pos   = 0xc      // Position of TSE field.
	Ethernet_DMACTxCR_TSE_Msk   = 0x1000   // Bit mask of TSE field.
	Ethernet_DMACTxCR_TSE       = 0x1000   // Bit TSE.
	Ethernet_DMACTxCR_TXPBL_Pos = 0x10     // Position of TXPBL field.
	Ethernet_DMACTxCR_TXPBL_Msk = 0x3f0000 // Bit mask of TXPBL field.

	// DMACRxCR: Channel receive control           register
	Ethernet_DMACRxCR_SR_Pos    = 0x0        // Position of SR field.
	Ethernet_DMACRxCR_SR_Msk    = 0x1        // Bit mask of SR field.
	Ethernet_DMACRxCR_SR        = 0x1        // Bit SR.
	Ethernet_DMACRxCR_RBSZ_Pos  = 0x1        // Position of RBSZ field.
	Ethernet_DMACRxCR_RBSZ_Msk  = 0x7ffe     // Bit mask of RBSZ field.
	Ethernet_DMACRxCR_RXPBL_Pos = 0x10       // Position of RXPBL field.
	Ethernet_DMACRxCR_RXPBL_Msk = 0x3f0000   // Bit mask of RXPBL field.
	Ethernet_DMACRxCR_RPF_Pos   = 0x1f       // Position of RPF field.
	Ethernet_DMACRxCR_RPF_Msk   = 0x80000000 // Bit mask of RPF field.
	Ethernet_DMACRxCR_RPF       = 0x80000000 // Bit RPF.

	// DMACTxDLAR: Channel Tx descriptor list address           register
	Ethernet_DMACTxDLAR_TDESLA_Pos = 0x2        // Position of TDESLA field.
	Ethernet_DMACTxDLAR_TDESLA_Msk = 0xfffffffc // Bit mask of TDESLA field.

	// DMACRxDLAR: Channel Rx descriptor list address           register
	Ethernet_DMACRxDLAR_RDESLA_Pos = 0x2        // Position of RDESLA field.
	Ethernet_DMACRxDLAR_RDESLA_Msk = 0xfffffffc // Bit mask of RDESLA field.

	// DMACTxDTPR: Channel Tx descriptor tail pointer           register
	Ethernet_DMACTxDTPR_TDT_Pos = 0x2        // Position of TDT field.
	Ethernet_DMACTxDTPR_TDT_Msk = 0xfffffffc // Bit mask of TDT field.

	// DMACRxDTPR: Channel Rx descriptor tail pointer           register
	Ethernet_DMACRxDTPR_RDT_Pos = 0x2        // Position of RDT field.
	Ethernet_DMACRxDTPR_RDT_Msk = 0xfffffffc // Bit mask of RDT field.

	// DMACTxRLR: Channel Tx descriptor ring length           register
	Ethernet_DMACTxRLR_TDRL_Pos = 0x0   // Position of TDRL field.
	Ethernet_DMACTxRLR_TDRL_Msk = 0x3ff // Bit mask of TDRL field.

	// DMACRxRLR: Channel Rx descriptor ring length           register
	Ethernet_DMACRxRLR_RDRL_Pos = 0x0   // Position of RDRL field.
	Ethernet_DMACRxRLR_RDRL_Msk = 0x3ff // Bit mask of RDRL field.

	// DMACIER: Channel interrupt enable           register
	Ethernet_DMACIER_TIE_Pos  = 0x0    // Position of TIE field.
	Ethernet_DMACIER_TIE_Msk  = 0x1    // Bit mask of TIE field.
	Ethernet_DMACIER_TIE      = 0x1    // Bit TIE.
	Ethernet_DMACIER_TXSE_Pos = 0x1    // Position of TXSE field.
	Ethernet_DMACIER_TXSE_Msk = 0x2    // Bit mask of TXSE field.
	Ethernet_DMACIER_TXSE     = 0x2    // Bit TXSE.
	Ethernet_DMACIER_TBUE_Pos = 0x2    // Position of TBUE field.
	Ethernet_DMACIER_TBUE_Msk = 0x4    // Bit mask of TBUE field.
	Ethernet_DMACIER_TBUE     = 0x4    // Bit TBUE.
	Ethernet_DMACIER_RIE_Pos  = 0x6    // Position of RIE field.
	Ethernet_DMACIER_RIE_Msk  = 0x40   // Bit mask of RIE field.
	Ethernet_DMACIER_RIE      = 0x40   // Bit RIE.
	Ethernet_DMACIER_RBUE_Pos = 0x7    // Position of RBUE field.
	Ethernet_DMACIER_RBUE_Msk = 0x80   // Bit mask of RBUE field.
	Ethernet_DMACIER_RBUE     = 0x80   // Bit RBUE.
	Ethernet_DMACIER_RSE_Pos  = 0x8    // Position of RSE field.
	Ethernet_DMACIER_RSE_Msk  = 0x100  // Bit mask of RSE field.
	Ethernet_DMACIER_RSE      = 0x100  // Bit RSE.
	Ethernet_DMACIER_RWTE_Pos = 0x9    // Position of RWTE field.
	Ethernet_DMACIER_RWTE_Msk = 0x200  // Bit mask of RWTE field.
	Ethernet_DMACIER_RWTE     = 0x200  // Bit RWTE.
	Ethernet_DMACIER_ETIE_Pos = 0xa    // Position of ETIE field.
	Ethernet_DMACIER_ETIE_Msk = 0x400  // Bit mask of ETIE field.
	Ethernet_DMACIER_ETIE     = 0x400  // Bit ETIE.
	Ethernet_DMACIER_ERIE_Pos = 0xb    // Position of ERIE field.
	Ethernet_DMACIER_ERIE_Msk = 0x800  // Bit mask of ERIE field.
	Ethernet_DMACIER_ERIE     = 0x800  // Bit ERIE.
	Ethernet_DMACIER_FBEE_Pos = 0xc    // Position of FBEE field.
	Ethernet_DMACIER_FBEE_Msk = 0x1000 // Bit mask of FBEE field.
	Ethernet_DMACIER_FBEE     = 0x1000 // Bit FBEE.
	Ethernet_DMACIER_CDEE_Pos = 0xd    // Position of CDEE field.
	Ethernet_DMACIER_CDEE_Msk = 0x2000 // Bit mask of CDEE field.
	Ethernet_DMACIER_CDEE     = 0x2000 // Bit CDEE.
	Ethernet_DMACIER_AIE_Pos  = 0xe    // Position of AIE field.
	Ethernet_DMACIER_AIE_Msk  = 0x4000 // Bit mask of AIE field.
	Ethernet_DMACIER_AIE      = 0x4000 // Bit AIE.
	Ethernet_DMACIER_NIE_Pos  = 0xf    // Position of NIE field.
	Ethernet_DMACIER_NIE_Msk  = 0x8000 // Bit mask of NIE field.
	Ethernet_DMACIER_NIE      = 0x8000 // Bit NIE.

	// DMACRxIWTR: Channel Rx interrupt watchdog timer           register
	Ethernet_DMACRxIWTR_RWT_Pos = 0x0  // Position of RWT field.
	Ethernet_DMACRxIWTR_RWT_Msk = 0xff // Bit mask of RWT field.

	// DMACCATxDR: Channel current application transmit           descriptor register
	Ethernet_DMACCATxDR_CURTDESAPTR_Pos = 0x0        // Position of CURTDESAPTR field.
	Ethernet_DMACCATxDR_CURTDESAPTR_Msk = 0xffffffff // Bit mask of CURTDESAPTR field.

	// DMACCARxDR: Channel current application receive           descriptor register
	Ethernet_DMACCARxDR_CURRDESAPTR_Pos = 0x0        // Position of CURRDESAPTR field.
	Ethernet_DMACCARxDR_CURRDESAPTR_Msk = 0xffffffff // Bit mask of CURRDESAPTR field.

	// DMACCATxBR: Channel current application transmit buffer           register
	Ethernet_DMACCATxBR_CURTBUFAPTR_Pos = 0x0        // Position of CURTBUFAPTR field.
	Ethernet_DMACCATxBR_CURTBUFAPTR_Msk = 0xffffffff // Bit mask of CURTBUFAPTR field.

	// DMACCARxBR: Channel current application receive buffer           register
	Ethernet_DMACCARxBR_CURRBUFAPTR_Pos = 0x0        // Position of CURRBUFAPTR field.
	Ethernet_DMACCARxBR_CURRBUFAPTR_Msk = 0xffffffff // Bit mask of CURRBUFAPTR field.

	// DMACSR: Channel status register
	Ethernet_DMACSR_TI_Pos  = 0x0      // Position of TI field.
	Ethernet_DMACSR_TI_Msk  = 0x1      // Bit mask of TI field.
	Ethernet_DMACSR_TI      = 0x1      // Bit TI.
	Ethernet_DMACSR_TPS_Pos = 0x1      // Position of TPS field.
	Ethernet_DMACSR_TPS_Msk = 0x2      // Bit mask of TPS field.
	Ethernet_DMACSR_TPS     = 0x2      // Bit TPS.
	Ethernet_DMACSR_TBU_Pos = 0x2      // Position of TBU field.
	Ethernet_DMACSR_TBU_Msk = 0x4      // Bit mask of TBU field.
	Ethernet_DMACSR_TBU     = 0x4      // Bit TBU.
	Ethernet_DMACSR_RI_Pos  = 0x6      // Position of RI field.
	Ethernet_DMACSR_RI_Msk  = 0x40     // Bit mask of RI field.
	Ethernet_DMACSR_RI      = 0x40     // Bit RI.
	Ethernet_DMACSR_RBU_Pos = 0x7      // Position of RBU field.
	Ethernet_DMACSR_RBU_Msk = 0x80     // Bit mask of RBU field.
	Ethernet_DMACSR_RBU     = 0x80     // Bit RBU.
	Ethernet_DMACSR_RPS_Pos = 0x8      // Position of RPS field.
	Ethernet_DMACSR_RPS_Msk = 0x100    // Bit mask of RPS field.
	Ethernet_DMACSR_RPS     = 0x100    // Bit RPS.
	Ethernet_DMACSR_RWT_Pos = 0x9      // Position of RWT field.
	Ethernet_DMACSR_RWT_Msk = 0x200    // Bit mask of RWT field.
	Ethernet_DMACSR_RWT     = 0x200    // Bit RWT.
	Ethernet_DMACSR_ET_Pos  = 0xa      // Position of ET field.
	Ethernet_DMACSR_ET_Msk  = 0x400    // Bit mask of ET field.
	Ethernet_DMACSR_ET      = 0x400    // Bit ET.
	Ethernet_DMACSR_ER_Pos  = 0xb      // Position of ER field.
	Ethernet_DMACSR_ER_Msk  = 0x800    // Bit mask of ER field.
	Ethernet_DMACSR_ER      = 0x800    // Bit ER.
	Ethernet_DMACSR_FBE_Pos = 0xc      // Position of FBE field.
	Ethernet_DMACSR_FBE_Msk = 0x1000   // Bit mask of FBE field.
	Ethernet_DMACSR_FBE     = 0x1000   // Bit FBE.
	Ethernet_DMACSR_CDE_Pos = 0xd      // Position of CDE field.
	Ethernet_DMACSR_CDE_Msk = 0x2000   // Bit mask of CDE field.
	Ethernet_DMACSR_CDE     = 0x2000   // Bit CDE.
	Ethernet_DMACSR_AIS_Pos = 0xe      // Position of AIS field.
	Ethernet_DMACSR_AIS_Msk = 0x4000   // Bit mask of AIS field.
	Ethernet_DMACSR_AIS     = 0x4000   // Bit AIS.
	Ethernet_DMACSR_NIS_Pos = 0xf      // Position of NIS field.
	Ethernet_DMACSR_NIS_Msk = 0x8000   // Bit mask of NIS field.
	Ethernet_DMACSR_NIS     = 0x8000   // Bit NIS.
	Ethernet_DMACSR_TEB_Pos = 0x10     // Position of TEB field.
	Ethernet_DMACSR_TEB_Msk = 0x70000  // Bit mask of TEB field.
	Ethernet_DMACSR_REB_Pos = 0x13     // Position of REB field.
	Ethernet_DMACSR_REB_Msk = 0x380000 // Bit mask of REB field.

	// DMACMFCR: Channel missed frame count           register
	Ethernet_DMACMFCR_MFC_Pos  = 0x0    // Position of MFC field.
	Ethernet_DMACMFCR_MFC_Msk  = 0x7ff  // Bit mask of MFC field.
	Ethernet_DMACMFCR_MFCO_Pos = 0xf    // Position of MFCO field.
	Ethernet_DMACMFCR_MFCO_Msk = 0x8000 // Bit mask of MFCO field.
	Ethernet_DMACMFCR_MFCO     = 0x8000 // Bit MFCO.
)

// Bitfields for DMA1: DMA controller
const (
	// LISR: low interrupt status register
	DMA_LISR_TCIF3_Pos  = 0x1b      // Position of TCIF3 field.
	DMA_LISR_TCIF3_Msk  = 0x8000000 // Bit mask of TCIF3 field.
	DMA_LISR_TCIF3      = 0x8000000 // Bit TCIF3.
	DMA_LISR_HTIF3_Pos  = 0x1a      // Position of HTIF3 field.
	DMA_LISR_HTIF3_Msk  = 0x4000000 // Bit mask of HTIF3 field.
	DMA_LISR_HTIF3      = 0x4000000 // Bit HTIF3.
	DMA_LISR_TEIF3_Pos  = 0x19      // Position of TEIF3 field.
	DMA_LISR_TEIF3_Msk  = 0x2000000 // Bit mask of TEIF3 field.
	DMA_LISR_TEIF3      = 0x2000000 // Bit TEIF3.
	DMA_LISR_DMEIF3_Pos = 0x18      // Position of DMEIF3 field.
	DMA_LISR_DMEIF3_Msk = 0x1000000 // Bit mask of DMEIF3 field.
	DMA_LISR_DMEIF3     = 0x1000000 // Bit DMEIF3.
	DMA_LISR_FEIF3_Pos  = 0x16      // Position of FEIF3 field.
	DMA_LISR_FEIF3_Msk  = 0x400000  // Bit mask of FEIF3 field.
	DMA_LISR_FEIF3      = 0x400000  // Bit FEIF3.
	DMA_LISR_TCIF2_Pos  = 0x15      // Position of TCIF2 field.
	DMA_LISR_TCIF2_Msk  = 0x200000  // Bit mask of TCIF2 field.
	DMA_LISR_TCIF2      = 0x200000  // Bit TCIF2.
	DMA_LISR_HTIF2_Pos  = 0x14      // Position of HTIF2 field.
	DMA_LISR_HTIF2_Msk  = 0x100000  // Bit mask of HTIF2 field.
	DMA_LISR_HTIF2      = 0x100000  // Bit HTIF2.
	DMA_LISR_TEIF2_Pos  = 0x13      // Position of TEIF2 field.
	DMA_LISR_TEIF2_Msk  = 0x80000   // Bit mask of TEIF2 field.
	DMA_LISR_TEIF2      = 0x80000   // Bit TEIF2.
	DMA_LISR_DMEIF2_Pos = 0x12      // Position of DMEIF2 field.
	DMA_LISR_DMEIF2_Msk = 0x40000   // Bit mask of DMEIF2 field.
	DMA_LISR_DMEIF2     = 0x40000   // Bit DMEIF2.
	DMA_LISR_FEIF2_Pos  = 0x10      // Position of FEIF2 field.
	DMA_LISR_FEIF2_Msk  = 0x10000   // Bit mask of FEIF2 field.
	DMA_LISR_FEIF2      = 0x10000   // Bit FEIF2.
	DMA_LISR_TCIF1_Pos  = 0xb       // Position of TCIF1 field.
	DMA_LISR_TCIF1_Msk  = 0x800     // Bit mask of TCIF1 field.
	DMA_LISR_TCIF1      = 0x800     // Bit TCIF1.
	DMA_LISR_HTIF1_Pos  = 0xa       // Position of HTIF1 field.
	DMA_LISR_HTIF1_Msk  = 0x400     // Bit mask of HTIF1 field.
	DMA_LISR_HTIF1      = 0x400     // Bit HTIF1.
	DMA_LISR_TEIF1_Pos  = 0x9       // Position of TEIF1 field.
	DMA_LISR_TEIF1_Msk  = 0x200     // Bit mask of TEIF1 field.
	DMA_LISR_TEIF1      = 0x200     // Bit TEIF1.
	DMA_LISR_DMEIF1_Pos = 0x8       // Position of DMEIF1 field.
	DMA_LISR_DMEIF1_Msk = 0x100     // Bit mask of DMEIF1 field.
	DMA_LISR_DMEIF1     = 0x100     // Bit DMEIF1.
	DMA_LISR_FEIF1_Pos  = 0x6       // Position of FEIF1 field.
	DMA_LISR_FEIF1_Msk  = 0x40      // Bit mask of FEIF1 field.
	DMA_LISR_FEIF1      = 0x40      // Bit FEIF1.
	DMA_LISR_TCIF0_Pos  = 0x5       // Position of TCIF0 field.
	DMA_LISR_TCIF0_Msk  = 0x20      // Bit mask of TCIF0 field.
	DMA_LISR_TCIF0      = 0x20      // Bit TCIF0.
	DMA_LISR_HTIF0_Pos  = 0x4       // Position of HTIF0 field.
	DMA_LISR_HTIF0_Msk  = 0x10      // Bit mask of HTIF0 field.
	DMA_LISR_HTIF0      = 0x10      // Bit HTIF0.
	DMA_LISR_TEIF0_Pos  = 0x3       // Position of TEIF0 field.
	DMA_LISR_TEIF0_Msk  = 0x8       // Bit mask of TEIF0 field.
	DMA_LISR_TEIF0      = 0x8       // Bit TEIF0.
	DMA_LISR_DMEIF0_Pos = 0x2       // Position of DMEIF0 field.
	DMA_LISR_DMEIF0_Msk = 0x4       // Bit mask of DMEIF0 field.
	DMA_LISR_DMEIF0     = 0x4       // Bit DMEIF0.
	DMA_LISR_FEIF0_Pos  = 0x0       // Position of FEIF0 field.
	DMA_LISR_FEIF0_Msk  = 0x1       // Bit mask of FEIF0 field.
	DMA_LISR_FEIF0      = 0x1       // Bit FEIF0.

	// HISR: high interrupt status register
	DMA_HISR_TCIF7_Pos  = 0x1b      // Position of TCIF7 field.
	DMA_HISR_TCIF7_Msk  = 0x8000000 // Bit mask of TCIF7 field.
	DMA_HISR_TCIF7      = 0x8000000 // Bit TCIF7.
	DMA_HISR_HTIF7_Pos  = 0x1a      // Position of HTIF7 field.
	DMA_HISR_HTIF7_Msk  = 0x4000000 // Bit mask of HTIF7 field.
	DMA_HISR_HTIF7      = 0x4000000 // Bit HTIF7.
	DMA_HISR_TEIF7_Pos  = 0x19      // Position of TEIF7 field.
	DMA_HISR_TEIF7_Msk  = 0x2000000 // Bit mask of TEIF7 field.
	DMA_HISR_TEIF7      = 0x2000000 // Bit TEIF7.
	DMA_HISR_DMEIF7_Pos = 0x18      // Position of DMEIF7 field.
	DMA_HISR_DMEIF7_Msk = 0x1000000 // Bit mask of DMEIF7 field.
	DMA_HISR_DMEIF7     = 0x1000000 // Bit DMEIF7.
	DMA_HISR_FEIF7_Pos  = 0x16      // Position of FEIF7 field.
	DMA_HISR_FEIF7_Msk  = 0x400000  // Bit mask of FEIF7 field.
	DMA_HISR_FEIF7      = 0x400000  // Bit FEIF7.
	DMA_HISR_TCIF6_Pos  = 0x15      // Position of TCIF6 field.
	DMA_HISR_TCIF6_Msk  = 0x200000  // Bit mask of TCIF6 field.
	DMA_HISR_TCIF6      = 0x200000  // Bit TCIF6.
	DMA_HISR_HTIF6_Pos  = 0x14      // Position of HTIF6 field.
	DMA_HISR_HTIF6_Msk  = 0x100000  // Bit mask of HTIF6 field.
	DMA_HISR_HTIF6      = 0x100000  // Bit HTIF6.
	DMA_HISR_TEIF6_Pos  = 0x13      // Position of TEIF6 field.
	DMA_HISR_TEIF6_Msk  = 0x80000   // Bit mask of TEIF6 field.
	DMA_HISR_TEIF6      = 0x80000   // Bit TEIF6.
	DMA_HISR_DMEIF6_Pos = 0x12      // Position of DMEIF6 field.
	DMA_HISR_DMEIF6_Msk = 0x40000   // Bit mask of DMEIF6 field.
	DMA_HISR_DMEIF6     = 0x40000   // Bit DMEIF6.
	DMA_HISR_FEIF6_Pos  = 0x10      // Position of FEIF6 field.
	DMA_HISR_FEIF6_Msk  = 0x10000   // Bit mask of FEIF6 field.
	DMA_HISR_FEIF6      = 0x10000   // Bit FEIF6.
	DMA_HISR_TCIF5_Pos  = 0xb       // Position of TCIF5 field.
	DMA_HISR_TCIF5_Msk  = 0x800     // Bit mask of TCIF5 field.
	DMA_HISR_TCIF5      = 0x800     // Bit TCIF5.
	DMA_HISR_HTIF5_Pos  = 0xa       // Position of HTIF5 field.
	DMA_HISR_HTIF5_Msk  = 0x400     // Bit mask of HTIF5 field.
	DMA_HISR_HTIF5      = 0x400     // Bit HTIF5.
	DMA_HISR_TEIF5_Pos  = 0x9       // Position of TEIF5 field.
	DMA_HISR_TEIF5_Msk  = 0x200     // Bit mask of TEIF5 field.
	DMA_HISR_TEIF5      = 0x200     // Bit TEIF5.
	DMA_HISR_DMEIF5_Pos = 0x8       // Position of DMEIF5 field.
	DMA_HISR_DMEIF5_Msk = 0x100     // Bit mask of DMEIF5 field.
	DMA_HISR_DMEIF5     = 0x100     // Bit DMEIF5.
	DMA_HISR_FEIF5_Pos  = 0x6       // Position of FEIF5 field.
	DMA_HISR_FEIF5_Msk  = 0x40      // Bit mask of FEIF5 field.
	DMA_HISR_FEIF5      = 0x40      // Bit FEIF5.
	DMA_HISR_TCIF4_Pos  = 0x5       // Position of TCIF4 field.
	DMA_HISR_TCIF4_Msk  = 0x20      // Bit mask of TCIF4 field.
	DMA_HISR_TCIF4      = 0x20      // Bit TCIF4.
	DMA_HISR_HTIF4_Pos  = 0x4       // Position of HTIF4 field.
	DMA_HISR_HTIF4_Msk  = 0x10      // Bit mask of HTIF4 field.
	DMA_HISR_HTIF4      = 0x10      // Bit HTIF4.
	DMA_HISR_TEIF4_Pos  = 0x3       // Position of TEIF4 field.
	DMA_HISR_TEIF4_Msk  = 0x8       // Bit mask of TEIF4 field.
	DMA_HISR_TEIF4      = 0x8       // Bit TEIF4.
	DMA_HISR_DMEIF4_Pos = 0x2       // Position of DMEIF4 field.
	DMA_HISR_DMEIF4_Msk = 0x4       // Bit mask of DMEIF4 field.
	DMA_HISR_DMEIF4     = 0x4       // Bit DMEIF4.
	DMA_HISR_FEIF4_Pos  = 0x0       // Position of FEIF4 field.
	DMA_HISR_FEIF4_Msk  = 0x1       // Bit mask of FEIF4 field.
	DMA_HISR_FEIF4      = 0x1       // Bit FEIF4.

	// LIFCR: low interrupt flag clear           register
	DMA_LIFCR_CTCIF3_Pos  = 0x1b      // Position of CTCIF3 field.
	DMA_LIFCR_CTCIF3_Msk  = 0x8000000 // Bit mask of CTCIF3 field.
	DMA_LIFCR_CTCIF3      = 0x8000000 // Bit CTCIF3.
	DMA_LIFCR_CHTIF3_Pos  = 0x1a      // Position of CHTIF3 field.
	DMA_LIFCR_CHTIF3_Msk  = 0x4000000 // Bit mask of CHTIF3 field.
	DMA_LIFCR_CHTIF3      = 0x4000000 // Bit CHTIF3.
	DMA_LIFCR_CTEIF3_Pos  = 0x19      // Position of CTEIF3 field.
	DMA_LIFCR_CTEIF3_Msk  = 0x2000000 // Bit mask of CTEIF3 field.
	DMA_LIFCR_CTEIF3      = 0x2000000 // Bit CTEIF3.
	DMA_LIFCR_CDMEIF3_Pos = 0x18      // Position of CDMEIF3 field.
	DMA_LIFCR_CDMEIF3_Msk = 0x1000000 // Bit mask of CDMEIF3 field.
	DMA_LIFCR_CDMEIF3     = 0x1000000 // Bit CDMEIF3.
	DMA_LIFCR_CFEIF3_Pos  = 0x16      // Position of CFEIF3 field.
	DMA_LIFCR_CFEIF3_Msk  = 0x400000  // Bit mask of CFEIF3 field.
	DMA_LIFCR_CFEIF3      = 0x400000  // Bit CFEIF3.
	DMA_LIFCR_CTCIF2_Pos  = 0x15      // Position of CTCIF2 field.
	DMA_LIFCR_CTCIF2_Msk  = 0x200000  // Bit mask of CTCIF2 field.
	DMA_LIFCR_CTCIF2      = 0x200000  // Bit CTCIF2.
	DMA_LIFCR_CHTIF2_Pos  = 0x14      // Position of CHTIF2 field.
	DMA_LIFCR_CHTIF2_Msk  = 0x100000  // Bit mask of CHTIF2 field.
	DMA_LIFCR_CHTIF2      = 0x100000  // Bit CHTIF2.
	DMA_LIFCR_CTEIF2_Pos  = 0x13      // Position of CTEIF2 field.
	DMA_LIFCR_CTEIF2_Msk  = 0x80000   // Bit mask of CTEIF2 field.
	DMA_LIFCR_CTEIF2      = 0x80000   // Bit CTEIF2.
	DMA_LIFCR_CDMEIF2_Pos = 0x12      // Position of CDMEIF2 field.
	DMA_LIFCR_CDMEIF2_Msk = 0x40000   // Bit mask of CDMEIF2 field.
	DMA_LIFCR_CDMEIF2     = 0x40000   // Bit CDMEIF2.
	DMA_LIFCR_CFEIF2_Pos  = 0x10      // Position of CFEIF2 field.
	DMA_LIFCR_CFEIF2_Msk  = 0x10000   // Bit mask of CFEIF2 field.
	DMA_LIFCR_CFEIF2      = 0x10000   // Bit CFEIF2.
	DMA_LIFCR_CTCIF1_Pos  = 0xb       // Position of CTCIF1 field.
	DMA_LIFCR_CTCIF1_Msk  = 0x800     // Bit mask of CTCIF1 field.
	DMA_LIFCR_CTCIF1      = 0x800     // Bit CTCIF1.
	DMA_LIFCR_CHTIF1_Pos  = 0xa       // Position of CHTIF1 field.
	DMA_LIFCR_CHTIF1_Msk  = 0x400     // Bit mask of CHTIF1 field.
	DMA_LIFCR_CHTIF1      = 0x400     // Bit CHTIF1.
	DMA_LIFCR_CTEIF1_Pos  = 0x9       // Position of CTEIF1 field.
	DMA_LIFCR_CTEIF1_Msk  = 0x200     // Bit mask of CTEIF1 field.
	DMA_LIFCR_CTEIF1      = 0x200     // Bit CTEIF1.
	DMA_LIFCR_CDMEIF1_Pos = 0x8       // Position of CDMEIF1 field.
	DMA_LIFCR_CDMEIF1_Msk = 0x100     // Bit mask of CDMEIF1 field.
	DMA_LIFCR_CDMEIF1     = 0x100     // Bit CDMEIF1.
	DMA_LIFCR_CFEIF1_Pos  = 0x6       // Position of CFEIF1 field.
	DMA_LIFCR_CFEIF1_Msk  = 0x40      // Bit mask of CFEIF1 field.
	DMA_LIFCR_CFEIF1      = 0x40      // Bit CFEIF1.
	DMA_LIFCR_CTCIF0_Pos  = 0x5       // Position of CTCIF0 field.
	DMA_LIFCR_CTCIF0_Msk  = 0x20      // Bit mask of CTCIF0 field.
	DMA_LIFCR_CTCIF0      = 0x20      // Bit CTCIF0.
	DMA_LIFCR_CHTIF0_Pos  = 0x4       // Position of CHTIF0 field.
	DMA_LIFCR_CHTIF0_Msk  = 0x10      // Bit mask of CHTIF0 field.
	DMA_LIFCR_CHTIF0      = 0x10      // Bit CHTIF0.
	DMA_LIFCR_CTEIF0_Pos  = 0x3       // Position of CTEIF0 field.
	DMA_LIFCR_CTEIF0_Msk  = 0x8       // Bit mask of CTEIF0 field.
	DMA_LIFCR_CTEIF0      = 0x8       // Bit CTEIF0.
	DMA_LIFCR_CDMEIF0_Pos = 0x2       // Position of CDMEIF0 field.
	DMA_LIFCR_CDMEIF0_Msk = 0x4       // Bit mask of CDMEIF0 field.
	DMA_LIFCR_CDMEIF0     = 0x4       // Bit CDMEIF0.
	DMA_LIFCR_CFEIF0_Pos  = 0x0       // Position of CFEIF0 field.
	DMA_LIFCR_CFEIF0_Msk  = 0x1       // Bit mask of CFEIF0 field.
	DMA_LIFCR_CFEIF0      = 0x1       // Bit CFEIF0.

	// HIFCR: high interrupt flag clear           register
	DMA_HIFCR_CTCIF7_Pos  = 0x1b      // Position of CTCIF7 field.
	DMA_HIFCR_CTCIF7_Msk  = 0x8000000 // Bit mask of CTCIF7 field.
	DMA_HIFCR_CTCIF7      = 0x8000000 // Bit CTCIF7.
	DMA_HIFCR_CHTIF7_Pos  = 0x1a      // Position of CHTIF7 field.
	DMA_HIFCR_CHTIF7_Msk  = 0x4000000 // Bit mask of CHTIF7 field.
	DMA_HIFCR_CHTIF7      = 0x4000000 // Bit CHTIF7.
	DMA_HIFCR_CTEIF7_Pos  = 0x19      // Position of CTEIF7 field.
	DMA_HIFCR_CTEIF7_Msk  = 0x2000000 // Bit mask of CTEIF7 field.
	DMA_HIFCR_CTEIF7      = 0x2000000 // Bit CTEIF7.
	DMA_HIFCR_CDMEIF7_Pos = 0x18      // Position of CDMEIF7 field.
	DMA_HIFCR_CDMEIF7_Msk = 0x1000000 // Bit mask of CDMEIF7 field.
	DMA_HIFCR_CDMEIF7     = 0x1000000 // Bit CDMEIF7.
	DMA_HIFCR_CFEIF7_Pos  = 0x16      // Position of CFEIF7 field.
	DMA_HIFCR_CFEIF7_Msk  = 0x400000  // Bit mask of CFEIF7 field.
	DMA_HIFCR_CFEIF7      = 0x400000  // Bit CFEIF7.
	DMA_HIFCR_CTCIF6_Pos  = 0x15      // Position of CTCIF6 field.
	DMA_HIFCR_CTCIF6_Msk  = 0x200000  // Bit mask of CTCIF6 field.
	DMA_HIFCR_CTCIF6      = 0x200000  // Bit CTCIF6.
	DMA_HIFCR_CHTIF6_Pos  = 0x14      // Position of CHTIF6 field.
	DMA_HIFCR_CHTIF6_Msk  = 0x100000  // Bit mask of CHTIF6 field.
	DMA_HIFCR_CHTIF6      = 0x100000  // Bit CHTIF6.
	DMA_HIFCR_CTEIF6_Pos  = 0x13      // Position of CTEIF6 field.
	DMA_HIFCR_CTEIF6_Msk  = 0x80000   // Bit mask of CTEIF6 field.
	DMA_HIFCR_CTEIF6      = 0x80000   // Bit CTEIF6.
	DMA_HIFCR_CDMEIF6_Pos = 0x12      // Position of CDMEIF6 field.
	DMA_HIFCR_CDMEIF6_Msk = 0x40000   // Bit mask of CDMEIF6 field.
	DMA_HIFCR_CDMEIF6     = 0x40000   // Bit CDMEIF6.
	DMA_HIFCR_CFEIF6_Pos  = 0x10      // Position of CFEIF6 field.
	DMA_HIFCR_CFEIF6_Msk  = 0x10000   // Bit mask of CFEIF6 field.
	DMA_HIFCR_CFEIF6      = 0x10000   // Bit CFEIF6.
	DMA_HIFCR_CTCIF5_Pos  = 0xb       // Position of CTCIF5 field.
	DMA_HIFCR_CTCIF5_Msk  = 0x800     // Bit mask of CTCIF5 field.
	DMA_HIFCR_CTCIF5      = 0x800     // Bit CTCIF5.
	DMA_HIFCR_CHTIF5_Pos  = 0xa       // Position of CHTIF5 field.
	DMA_HIFCR_CHTIF5_Msk  = 0x400     // Bit mask of CHTIF5 field.
	DMA_HIFCR_CHTIF5      = 0x400     // Bit CHTIF5.
	DMA_HIFCR_CTEIF5_Pos  = 0x9       // Position of CTEIF5 field.
	DMA_HIFCR_CTEIF5_Msk  = 0x200     // Bit mask of CTEIF5 field.
	DMA_HIFCR_CTEIF5      = 0x200     // Bit CTEIF5.
	DMA_HIFCR_CDMEIF5_Pos = 0x8       // Position of CDMEIF5 field.
	DMA_HIFCR_CDMEIF5_Msk = 0x100     // Bit mask of CDMEIF5 field.
	DMA_HIFCR_CDMEIF5     = 0x100     // Bit CDMEIF5.
	DMA_HIFCR_CFEIF5_Pos  = 0x6       // Position of CFEIF5 field.
	DMA_HIFCR_CFEIF5_Msk  = 0x40      // Bit mask of CFEIF5 field.
	DMA_HIFCR_CFEIF5      = 0x40      // Bit CFEIF5.
	DMA_HIFCR_CTCIF4_Pos  = 0x5       // Position of CTCIF4 field.
	DMA_HIFCR_CTCIF4_Msk  = 0x20      // Bit mask of CTCIF4 field.
	DMA_HIFCR_CTCIF4      = 0x20      // Bit CTCIF4.
	DMA_HIFCR_CHTIF4_Pos  = 0x4       // Position of CHTIF4 field.
	DMA_HIFCR_CHTIF4_Msk  = 0x10      // Bit mask of CHTIF4 field.
	DMA_HIFCR_CHTIF4      = 0x10      // Bit CHTIF4.
	DMA_HIFCR_CTEIF4_Pos  = 0x3       // Position of CTEIF4 field.
	DMA_HIFCR_CTEIF4_Msk  = 0x8       // Bit mask of CTEIF4 field.
	DMA_HIFCR_CTEIF4      = 0x8       // Bit CTEIF4.
	DMA_HIFCR_CDMEIF4_Pos = 0x2       // Position of CDMEIF4 field.
	DMA_HIFCR_CDMEIF4_Msk = 0x4       // Bit mask of CDMEIF4 field.
	DMA_HIFCR_CDMEIF4     = 0x4       // Bit CDMEIF4.
	DMA_HIFCR_CFEIF4_Pos  = 0x0       // Position of CFEIF4 field.
	DMA_HIFCR_CFEIF4_Msk  = 0x1       // Bit mask of CFEIF4 field.
	DMA_HIFCR_CFEIF4      = 0x1       // Bit CFEIF4.

	// S0CR: stream x configuration           register
	DMA_S0CR_MBURST_Pos = 0x17      // Position of MBURST field.
	DMA_S0CR_MBURST_Msk = 0x1800000 // Bit mask of MBURST field.
	DMA_S0CR_PBURST_Pos = 0x15      // Position of PBURST field.
	DMA_S0CR_PBURST_Msk = 0x600000  // Bit mask of PBURST field.
	DMA_S0CR_CT_Pos     = 0x13      // Position of CT field.
	DMA_S0CR_CT_Msk     = 0x80000   // Bit mask of CT field.
	DMA_S0CR_CT         = 0x80000   // Bit CT.
	DMA_S0CR_DBM_Pos    = 0x12      // Position of DBM field.
	DMA_S0CR_DBM_Msk    = 0x40000   // Bit mask of DBM field.
	DMA_S0CR_DBM        = 0x40000   // Bit DBM.
	DMA_S0CR_PL_Pos     = 0x10      // Position of PL field.
	DMA_S0CR_PL_Msk     = 0x30000   // Bit mask of PL field.
	DMA_S0CR_PINCOS_Pos = 0xf       // Position of PINCOS field.
	DMA_S0CR_PINCOS_Msk = 0x8000    // Bit mask of PINCOS field.
	DMA_S0CR_PINCOS     = 0x8000    // Bit PINCOS.
	DMA_S0CR_MSIZE_Pos  = 0xd       // Position of MSIZE field.
	DMA_S0CR_MSIZE_Msk  = 0x6000    // Bit mask of MSIZE field.
	DMA_S0CR_PSIZE_Pos  = 0xb       // Position of PSIZE field.
	DMA_S0CR_PSIZE_Msk  = 0x1800    // Bit mask of PSIZE field.
	DMA_S0CR_MINC_Pos   = 0xa       // Position of MINC field.
	DMA_S0CR_MINC_Msk   = 0x400     // Bit mask of MINC field.
	DMA_S0CR_MINC       = 0x400     // Bit MINC.
	DMA_S0CR_PINC_Pos   = 0x9       // Position of PINC field.
	DMA_S0CR_PINC_Msk   = 0x200     // Bit mask of PINC field.
	DMA_S0CR_PINC       = 0x200     // Bit PINC.
	DMA_S0CR_CIRC_Pos   = 0x8       // Position of CIRC field.
	DMA_S0CR_CIRC_Msk   = 0x100     // Bit mask of CIRC field.
	DMA_S0CR_CIRC       = 0x100     // Bit CIRC.
	DMA_S0CR_DIR_Pos    = 0x6       // Position of DIR field.
	DMA_S0CR_DIR_Msk    = 0xc0      // Bit mask of DIR field.
	DMA_S0CR_PFCTRL_Pos = 0x5       // Position of PFCTRL field.
	DMA_S0CR_PFCTRL_Msk = 0x20      // Bit mask of PFCTRL field.
	DMA_S0CR_PFCTRL     = 0x20      // Bit PFCTRL.
	DMA_S0CR_TCIE_Pos   = 0x4       // Position of TCIE field.
	DMA_S0CR_TCIE_Msk   = 0x10      // Bit mask of TCIE field.
	DMA_S0CR_TCIE       = 0x10      // Bit TCIE.
	DMA_S0CR_HTIE_Pos   = 0x3       // Position of HTIE field.
	DMA_S0CR_HTIE_Msk   = 0x8       // Bit mask of HTIE field.
	DMA_S0CR_HTIE       = 0x8       // Bit HTIE.
	DMA_S0CR_TEIE_Pos   = 0x2       // Position of TEIE field.
	DMA_S0CR_TEIE_Msk   = 0x4       // Bit mask of TEIE field.
	DMA_S0CR_TEIE       = 0x4       // Bit TEIE.
	DMA_S0CR_DMEIE_Pos  = 0x1       // Position of DMEIE field.
	DMA_S0CR_DMEIE_Msk  = 0x2       // Bit mask of DMEIE field.
	DMA_S0CR_DMEIE      = 0x2       // Bit DMEIE.
	DMA_S0CR_EN_Pos     = 0x0       // Position of EN field.
	DMA_S0CR_EN_Msk     = 0x1       // Bit mask of EN field.
	DMA_S0CR_EN         = 0x1       // Bit EN.

	// S0NDTR: stream x number of data           register
	DMA_S0NDTR_NDT_Pos = 0x0    // Position of NDT field.
	DMA_S0NDTR_NDT_Msk = 0xffff // Bit mask of NDT field.

	// S0PAR: stream x peripheral address           register
	DMA_S0PAR_PA_Pos = 0x0        // Position of PA field.
	DMA_S0PAR_PA_Msk = 0xffffffff // Bit mask of PA field.

	// S0M0AR: stream x memory 0 address           register
	DMA_S0M0AR_M0A_Pos = 0x0        // Position of M0A field.
	DMA_S0M0AR_M0A_Msk = 0xffffffff // Bit mask of M0A field.

	// S0M1AR: stream x memory 1 address           register
	DMA_S0M1AR_M1A_Pos = 0x0        // Position of M1A field.
	DMA_S0M1AR_M1A_Msk = 0xffffffff // Bit mask of M1A field.

	// S0FCR: stream x FIFO control register
	DMA_S0FCR_FEIE_Pos  = 0x7  // Position of FEIE field.
	DMA_S0FCR_FEIE_Msk  = 0x80 // Bit mask of FEIE field.
	DMA_S0FCR_FEIE      = 0x80 // Bit FEIE.
	DMA_S0FCR_FS_Pos    = 0x3  // Position of FS field.
	DMA_S0FCR_FS_Msk    = 0x38 // Bit mask of FS field.
	DMA_S0FCR_DMDIS_Pos = 0x2  // Position of DMDIS field.
	DMA_S0FCR_DMDIS_Msk = 0x4  // Bit mask of DMDIS field.
	DMA_S0FCR_DMDIS     = 0x4  // Bit DMDIS.
	DMA_S0FCR_FTH_Pos   = 0x0  // Position of FTH field.
	DMA_S0FCR_FTH_Msk   = 0x3  // Bit mask of FTH field.

	// S1CR: stream x configuration           register
	DMA_S1CR_MBURST_Pos = 0x17      // Position of MBURST field.
	DMA_S1CR_MBURST_Msk = 0x1800000 // Bit mask of MBURST field.
	DMA_S1CR_PBURST_Pos = 0x15      // Position of PBURST field.
	DMA_S1CR_PBURST_Msk = 0x600000  // Bit mask of PBURST field.
	DMA_S1CR_ACK_Pos    = 0x14      // Position of ACK field.
	DMA_S1CR_ACK_Msk    = 0x100000  // Bit mask of ACK field.
	DMA_S1CR_ACK        = 0x100000  // Bit ACK.
	DMA_S1CR_CT_Pos     = 0x13      // Position of CT field.
	DMA_S1CR_CT_Msk     = 0x80000   // Bit mask of CT field.
	DMA_S1CR_CT         = 0x80000   // Bit CT.
	DMA_S1CR_DBM_Pos    = 0x12      // Position of DBM field.
	DMA_S1CR_DBM_Msk    = 0x40000   // Bit mask of DBM field.
	DMA_S1CR_DBM        = 0x40000   // Bit DBM.
	DMA_S1CR_PL_Pos     = 0x10      // Position of PL field.
	DMA_S1CR_PL_Msk     = 0x30000   // Bit mask of PL field.
	DMA_S1CR_PINCOS_Pos = 0xf       // Position of PINCOS field.
	DMA_S1CR_PINCOS_Msk = 0x8000    // Bit mask of PINCOS field.
	DMA_S1CR_PINCOS     = 0x8000    // Bit PINCOS.
	DMA_S1CR_MSIZE_Pos  = 0xd       // Position of MSIZE field.
	DMA_S1CR_MSIZE_Msk  = 0x6000    // Bit mask of MSIZE field.
	DMA_S1CR_PSIZE_Pos  = 0xb       // Position of PSIZE field.
	DMA_S1CR_PSIZE_Msk  = 0x1800    // Bit mask of PSIZE field.
	DMA_S1CR_MINC_Pos   = 0xa       // Position of MINC field.
	DMA_S1CR_MINC_Msk   = 0x400     // Bit mask of MINC field.
	DMA_S1CR_MINC       = 0x400     // Bit MINC.
	DMA_S1CR_PINC_Pos   = 0x9       // Position of PINC field.
	DMA_S1CR_PINC_Msk   = 0x200     // Bit mask of PINC field.
	DMA_S1CR_PINC       = 0x200     // Bit PINC.
	DMA_S1CR_CIRC_Pos   = 0x8       // Position of CIRC field.
	DMA_S1CR_CIRC_Msk   = 0x100     // Bit mask of CIRC field.
	DMA_S1CR_CIRC       = 0x100     // Bit CIRC.
	DMA_S1CR_DIR_Pos    = 0x6       // Position of DIR field.
	DMA_S1CR_DIR_Msk    = 0xc0      // Bit mask of DIR field.
	DMA_S1CR_PFCTRL_Pos = 0x5       // Position of PFCTRL field.
	DMA_S1CR_PFCTRL_Msk = 0x20      // Bit mask of PFCTRL field.
	DMA_S1CR_PFCTRL     = 0x20      // Bit PFCTRL.
	DMA_S1CR_TCIE_Pos   = 0x4       // Position of TCIE field.
	DMA_S1CR_TCIE_Msk   = 0x10      // Bit mask of TCIE field.
	DMA_S1CR_TCIE       = 0x10      // Bit TCIE.
	DMA_S1CR_HTIE_Pos   = 0x3       // Position of HTIE field.
	DMA_S1CR_HTIE_Msk   = 0x8       // Bit mask of HTIE field.
	DMA_S1CR_HTIE       = 0x8       // Bit HTIE.
	DMA_S1CR_TEIE_Pos   = 0x2       // Position of TEIE field.
	DMA_S1CR_TEIE_Msk   = 0x4       // Bit mask of TEIE field.
	DMA_S1CR_TEIE       = 0x4       // Bit TEIE.
	DMA_S1CR_DMEIE_Pos  = 0x1       // Position of DMEIE field.
	DMA_S1CR_DMEIE_Msk  = 0x2       // Bit mask of DMEIE field.
	DMA_S1CR_DMEIE      = 0x2       // Bit DMEIE.
	DMA_S1CR_EN_Pos     = 0x0       // Position of EN field.
	DMA_S1CR_EN_Msk     = 0x1       // Bit mask of EN field.
	DMA_S1CR_EN         = 0x1       // Bit EN.

	// S1NDTR: stream x number of data           register
	DMA_S1NDTR_NDT_Pos = 0x0    // Position of NDT field.
	DMA_S1NDTR_NDT_Msk = 0xffff // Bit mask of NDT field.

	// S1PAR: stream x peripheral address           register
	DMA_S1PAR_PA_Pos = 0x0        // Position of PA field.
	DMA_S1PAR_PA_Msk = 0xffffffff // Bit mask of PA field.

	// S1M0AR: stream x memory 0 address           register
	DMA_S1M0AR_M0A_Pos = 0x0        // Position of M0A field.
	DMA_S1M0AR_M0A_Msk = 0xffffffff // Bit mask of M0A field.

	// S1M1AR: stream x memory 1 address           register
	DMA_S1M1AR_M1A_Pos = 0x0        // Position of M1A field.
	DMA_S1M1AR_M1A_Msk = 0xffffffff // Bit mask of M1A field.

	// S1FCR: stream x FIFO control register
	DMA_S1FCR_FEIE_Pos  = 0x7  // Position of FEIE field.
	DMA_S1FCR_FEIE_Msk  = 0x80 // Bit mask of FEIE field.
	DMA_S1FCR_FEIE      = 0x80 // Bit FEIE.
	DMA_S1FCR_FS_Pos    = 0x3  // Position of FS field.
	DMA_S1FCR_FS_Msk    = 0x38 // Bit mask of FS field.
	DMA_S1FCR_DMDIS_Pos = 0x2  // Position of DMDIS field.
	DMA_S1FCR_DMDIS_Msk = 0x4  // Bit mask of DMDIS field.
	DMA_S1FCR_DMDIS     = 0x4  // Bit DMDIS.
	DMA_S1FCR_FTH_Pos   = 0x0  // Position of FTH field.
	DMA_S1FCR_FTH_Msk   = 0x3  // Bit mask of FTH field.

	// S2CR: stream x configuration           register
	DMA_S2CR_MBURST_Pos = 0x17      // Position of MBURST field.
	DMA_S2CR_MBURST_Msk = 0x1800000 // Bit mask of MBURST field.
	DMA_S2CR_PBURST_Pos = 0x15      // Position of PBURST field.
	DMA_S2CR_PBURST_Msk = 0x600000  // Bit mask of PBURST field.
	DMA_S2CR_ACK_Pos    = 0x14      // Position of ACK field.
	DMA_S2CR_ACK_Msk    = 0x100000  // Bit mask of ACK field.
	DMA_S2CR_ACK        = 0x100000  // Bit ACK.
	DMA_S2CR_CT_Pos     = 0x13      // Position of CT field.
	DMA_S2CR_CT_Msk     = 0x80000   // Bit mask of CT field.
	DMA_S2CR_CT         = 0x80000   // Bit CT.
	DMA_S2CR_DBM_Pos    = 0x12      // Position of DBM field.
	DMA_S2CR_DBM_Msk    = 0x40000   // Bit mask of DBM field.
	DMA_S2CR_DBM        = 0x40000   // Bit DBM.
	DMA_S2CR_PL_Pos     = 0x10      // Position of PL field.
	DMA_S2CR_PL_Msk     = 0x30000   // Bit mask of PL field.
	DMA_S2CR_PINCOS_Pos = 0xf       // Position of PINCOS field.
	DMA_S2CR_PINCOS_Msk = 0x8000    // Bit mask of PINCOS field.
	DMA_S2CR_PINCOS     = 0x8000    // Bit PINCOS.
	DMA_S2CR_MSIZE_Pos  = 0xd       // Position of MSIZE field.
	DMA_S2CR_MSIZE_Msk  = 0x6000    // Bit mask of MSIZE field.
	DMA_S2CR_PSIZE_Pos  = 0xb       // Position of PSIZE field.
	DMA_S2CR_PSIZE_Msk  = 0x1800    // Bit mask of PSIZE field.
	DMA_S2CR_MINC_Pos   = 0xa       // Position of MINC field.
	DMA_S2CR_MINC_Msk   = 0x400     // Bit mask of MINC field.
	DMA_S2CR_MINC       = 0x400     // Bit MINC.
	DMA_S2CR_PINC_Pos   = 0x9       // Position of PINC field.
	DMA_S2CR_PINC_Msk   = 0x200     // Bit mask of PINC field.
	DMA_S2CR_PINC       = 0x200     // Bit PINC.
	DMA_S2CR_CIRC_Pos   = 0x8       // Position of CIRC field.
	DMA_S2CR_CIRC_Msk   = 0x100     // Bit mask of CIRC field.
	DMA_S2CR_CIRC       = 0x100     // Bit CIRC.
	DMA_S2CR_DIR_Pos    = 0x6       // Position of DIR field.
	DMA_S2CR_DIR_Msk    = 0xc0      // Bit mask of DIR field.
	DMA_S2CR_PFCTRL_Pos = 0x5       // Position of PFCTRL field.
	DMA_S2CR_PFCTRL_Msk = 0x20      // Bit mask of PFCTRL field.
	DMA_S2CR_PFCTRL     = 0x20      // Bit PFCTRL.
	DMA_S2CR_TCIE_Pos   = 0x4       // Position of TCIE field.
	DMA_S2CR_TCIE_Msk   = 0x10      // Bit mask of TCIE field.
	DMA_S2CR_TCIE       = 0x10      // Bit TCIE.
	DMA_S2CR_HTIE_Pos   = 0x3       // Position of HTIE field.
	DMA_S2CR_HTIE_Msk   = 0x8       // Bit mask of HTIE field.
	DMA_S2CR_HTIE       = 0x8       // Bit HTIE.
	DMA_S2CR_TEIE_Pos   = 0x2       // Position of TEIE field.
	DMA_S2CR_TEIE_Msk   = 0x4       // Bit mask of TEIE field.
	DMA_S2CR_TEIE       = 0x4       // Bit TEIE.
	DMA_S2CR_DMEIE_Pos  = 0x1       // Position of DMEIE field.
	DMA_S2CR_DMEIE_Msk  = 0x2       // Bit mask of DMEIE field.
	DMA_S2CR_DMEIE      = 0x2       // Bit DMEIE.
	DMA_S2CR_EN_Pos     = 0x0       // Position of EN field.
	DMA_S2CR_EN_Msk     = 0x1       // Bit mask of EN field.
	DMA_S2CR_EN         = 0x1       // Bit EN.

	// S2NDTR: stream x number of data           register
	DMA_S2NDTR_NDT_Pos = 0x0    // Position of NDT field.
	DMA_S2NDTR_NDT_Msk = 0xffff // Bit mask of NDT field.

	// S2PAR: stream x peripheral address           register
	DMA_S2PAR_PA_Pos = 0x0        // Position of PA field.
	DMA_S2PAR_PA_Msk = 0xffffffff // Bit mask of PA field.

	// S2M0AR: stream x memory 0 address           register
	DMA_S2M0AR_M0A_Pos = 0x0        // Position of M0A field.
	DMA_S2M0AR_M0A_Msk = 0xffffffff // Bit mask of M0A field.

	// S2M1AR: stream x memory 1 address           register
	DMA_S2M1AR_M1A_Pos = 0x0        // Position of M1A field.
	DMA_S2M1AR_M1A_Msk = 0xffffffff // Bit mask of M1A field.

	// S2FCR: stream x FIFO control register
	DMA_S2FCR_FEIE_Pos  = 0x7  // Position of FEIE field.
	DMA_S2FCR_FEIE_Msk  = 0x80 // Bit mask of FEIE field.
	DMA_S2FCR_FEIE      = 0x80 // Bit FEIE.
	DMA_S2FCR_FS_Pos    = 0x3  // Position of FS field.
	DMA_S2FCR_FS_Msk    = 0x38 // Bit mask of FS field.
	DMA_S2FCR_DMDIS_Pos = 0x2  // Position of DMDIS field.
	DMA_S2FCR_DMDIS_Msk = 0x4  // Bit mask of DMDIS field.
	DMA_S2FCR_DMDIS     = 0x4  // Bit DMDIS.
	DMA_S2FCR_FTH_Pos   = 0x0  // Position of FTH field.
	DMA_S2FCR_FTH_Msk   = 0x3  // Bit mask of FTH field.

	// S3CR: stream x configuration           register
	DMA_S3CR_MBURST_Pos = 0x17      // Position of MBURST field.
	DMA_S3CR_MBURST_Msk = 0x1800000 // Bit mask of MBURST field.
	DMA_S3CR_PBURST_Pos = 0x15      // Position of PBURST field.
	DMA_S3CR_PBURST_Msk = 0x600000  // Bit mask of PBURST field.
	DMA_S3CR_ACK_Pos    = 0x14      // Position of ACK field.
	DMA_S3CR_ACK_Msk    = 0x100000  // Bit mask of ACK field.
	DMA_S3CR_ACK        = 0x100000  // Bit ACK.
	DMA_S3CR_CT_Pos     = 0x13      // Position of CT field.
	DMA_S3CR_CT_Msk     = 0x80000   // Bit mask of CT field.
	DMA_S3CR_CT         = 0x80000   // Bit CT.
	DMA_S3CR_DBM_Pos    = 0x12      // Position of DBM field.
	DMA_S3CR_DBM_Msk    = 0x40000   // Bit mask of DBM field.
	DMA_S3CR_DBM        = 0x40000   // Bit DBM.
	DMA_S3CR_PL_Pos     = 0x10      // Position of PL field.
	DMA_S3CR_PL_Msk     = 0x30000   // Bit mask of PL field.
	DMA_S3CR_PINCOS_Pos = 0xf       // Position of PINCOS field.
	DMA_S3CR_PINCOS_Msk = 0x8000    // Bit mask of PINCOS field.
	DMA_S3CR_PINCOS     = 0x8000    // Bit PINCOS.
	DMA_S3CR_MSIZE_Pos  = 0xd       // Position of MSIZE field.
	DMA_S3CR_MSIZE_Msk  = 0x6000    // Bit mask of MSIZE field.
	DMA_S3CR_PSIZE_Pos  = 0xb       // Position of PSIZE field.
	DMA_S3CR_PSIZE_Msk  = 0x1800    // Bit mask of PSIZE field.
	DMA_S3CR_MINC_Pos   = 0xa       // Position of MINC field.
	DMA_S3CR_MINC_Msk   = 0x400     // Bit mask of MINC field.
	DMA_S3CR_MINC       = 0x400     // Bit MINC.
	DMA_S3CR_PINC_Pos   = 0x9       // Position of PINC field.
	DMA_S3CR_PINC_Msk   = 0x200     // Bit mask of PINC field.
	DMA_S3CR_PINC       = 0x200     // Bit PINC.
	DMA_S3CR_CIRC_Pos   = 0x8       // Position of CIRC field.
	DMA_S3CR_CIRC_Msk   = 0x100     // Bit mask of CIRC field.
	DMA_S3CR_CIRC       = 0x100     // Bit CIRC.
	DMA_S3CR_DIR_Pos    = 0x6       // Position of DIR field.
	DMA_S3CR_DIR_Msk    = 0xc0      // Bit mask of DIR field.
	DMA_S3CR_PFCTRL_Pos = 0x5       // Position of PFCTRL field.
	DMA_S3CR_PFCTRL_Msk = 0x20      // Bit mask of PFCTRL field.
	DMA_S3CR_PFCTRL     = 0x20      // Bit PFCTRL.
	DMA_S3CR_TCIE_Pos   = 0x4       // Position of TCIE field.
	DMA_S3CR_TCIE_Msk   = 0x10      // Bit mask of TCIE field.
	DMA_S3CR_TCIE       = 0x10      // Bit TCIE.
	DMA_S3CR_HTIE_Pos   = 0x3       // Position of HTIE field.
	DMA_S3CR_HTIE_Msk   = 0x8       // Bit mask of HTIE field.
	DMA_S3CR_HTIE       = 0x8       // Bit HTIE.
	DMA_S3CR_TEIE_Pos   = 0x2       // Position of TEIE field.
	DMA_S3CR_TEIE_Msk   = 0x4       // Bit mask of TEIE field.
	DMA_S3CR_TEIE       = 0x4       // Bit TEIE.
	DMA_S3CR_DMEIE_Pos  = 0x1       // Position of DMEIE field.
	DMA_S3CR_DMEIE_Msk  = 0x2       // Bit mask of DMEIE field.
	DMA_S3CR_DMEIE      = 0x2       // Bit DMEIE.
	DMA_S3CR_EN_Pos     = 0x0       // Position of EN field.
	DMA_S3CR_EN_Msk     = 0x1       // Bit mask of EN field.
	DMA_S3CR_EN         = 0x1       // Bit EN.

	// S3NDTR: stream x number of data           register
	DMA_S3NDTR_NDT_Pos = 0x0    // Position of NDT field.
	DMA_S3NDTR_NDT_Msk = 0xffff // Bit mask of NDT field.

	// S3PAR: stream x peripheral address           register
	DMA_S3PAR_PA_Pos = 0x0        // Position of PA field.
	DMA_S3PAR_PA_Msk = 0xffffffff // Bit mask of PA field.

	// S3M0AR: stream x memory 0 address           register
	DMA_S3M0AR_M0A_Pos = 0x0        // Position of M0A field.
	DMA_S3M0AR_M0A_Msk = 0xffffffff // Bit mask of M0A field.

	// S3M1AR: stream x memory 1 address           register
	DMA_S3M1AR_M1A_Pos = 0x0        // Position of M1A field.
	DMA_S3M1AR_M1A_Msk = 0xffffffff // Bit mask of M1A field.

	// S3FCR: stream x FIFO control register
	DMA_S3FCR_FEIE_Pos  = 0x7  // Position of FEIE field.
	DMA_S3FCR_FEIE_Msk  = 0x80 // Bit mask of FEIE field.
	DMA_S3FCR_FEIE      = 0x80 // Bit FEIE.
	DMA_S3FCR_FS_Pos    = 0x3  // Position of FS field.
	DMA_S3FCR_FS_Msk    = 0x38 // Bit mask of FS field.
	DMA_S3FCR_DMDIS_Pos = 0x2  // Position of DMDIS field.
	DMA_S3FCR_DMDIS_Msk = 0x4  // Bit mask of DMDIS field.
	DMA_S3FCR_DMDIS     = 0x4  // Bit DMDIS.
	DMA_S3FCR_FTH_Pos   = 0x0  // Position of FTH field.
	DMA_S3FCR_FTH_Msk   = 0x3  // Bit mask of FTH field.

	// S4CR: stream x configuration           register
	DMA_S4CR_MBURST_Pos = 0x17      // Position of MBURST field.
	DMA_S4CR_MBURST_Msk = 0x1800000 // Bit mask of MBURST field.
	DMA_S4CR_PBURST_Pos = 0x15      // Position of PBURST field.
	DMA_S4CR_PBURST_Msk = 0x600000  // Bit mask of PBURST field.
	DMA_S4CR_ACK_Pos    = 0x14      // Position of ACK field.
	DMA_S4CR_ACK_Msk    = 0x100000  // Bit mask of ACK field.
	DMA_S4CR_ACK        = 0x100000  // Bit ACK.
	DMA_S4CR_CT_Pos     = 0x13      // Position of CT field.
	DMA_S4CR_CT_Msk     = 0x80000   // Bit mask of CT field.
	DMA_S4CR_CT         = 0x80000   // Bit CT.
	DMA_S4CR_DBM_Pos    = 0x12      // Position of DBM field.
	DMA_S4CR_DBM_Msk    = 0x40000   // Bit mask of DBM field.
	DMA_S4CR_DBM        = 0x40000   // Bit DBM.
	DMA_S4CR_PL_Pos     = 0x10      // Position of PL field.
	DMA_S4CR_PL_Msk     = 0x30000   // Bit mask of PL field.
	DMA_S4CR_PINCOS_Pos = 0xf       // Position of PINCOS field.
	DMA_S4CR_PINCOS_Msk = 0x8000    // Bit mask of PINCOS field.
	DMA_S4CR_PINCOS     = 0x8000    // Bit PINCOS.
	DMA_S4CR_MSIZE_Pos  = 0xd       // Position of MSIZE field.
	DMA_S4CR_MSIZE_Msk  = 0x6000    // Bit mask of MSIZE field.
	DMA_S4CR_PSIZE_Pos  = 0xb       // Position of PSIZE field.
	DMA_S4CR_PSIZE_Msk  = 0x1800    // Bit mask of PSIZE field.
	DMA_S4CR_MINC_Pos   = 0xa       // Position of MINC field.
	DMA_S4CR_MINC_Msk   = 0x400     // Bit mask of MINC field.
	DMA_S4CR_MINC       = 0x400     // Bit MINC.
	DMA_S4CR_PINC_Pos   = 0x9       // Position of PINC field.
	DMA_S4CR_PINC_Msk   = 0x200     // Bit mask of PINC field.
	DMA_S4CR_PINC       = 0x200     // Bit PINC.
	DMA_S4CR_CIRC_Pos   = 0x8       // Position of CIRC field.
	DMA_S4CR_CIRC_Msk   = 0x100     // Bit mask of CIRC field.
	DMA_S4CR_CIRC       = 0x100     // Bit CIRC.
	DMA_S4CR_DIR_Pos    = 0x6       // Position of DIR field.
	DMA_S4CR_DIR_Msk    = 0xc0      // Bit mask of DIR field.
	DMA_S4CR_PFCTRL_Pos = 0x5       // Position of PFCTRL field.
	DMA_S4CR_PFCTRL_Msk = 0x20      // Bit mask of PFCTRL field.
	DMA_S4CR_PFCTRL     = 0x20      // Bit PFCTRL.
	DMA_S4CR_TCIE_Pos   = 0x4       // Position of TCIE field.
	DMA_S4CR_TCIE_Msk   = 0x10      // Bit mask of TCIE field.
	DMA_S4CR_TCIE       = 0x10      // Bit TCIE.
	DMA_S4CR_HTIE_Pos   = 0x3       // Position of HTIE field.
	DMA_S4CR_HTIE_Msk   = 0x8       // Bit mask of HTIE field.
	DMA_S4CR_HTIE       = 0x8       // Bit HTIE.
	DMA_S4CR_TEIE_Pos   = 0x2       // Position of TEIE field.
	DMA_S4CR_TEIE_Msk   = 0x4       // Bit mask of TEIE field.
	DMA_S4CR_TEIE       = 0x4       // Bit TEIE.
	DMA_S4CR_DMEIE_Pos  = 0x1       // Position of DMEIE field.
	DMA_S4CR_DMEIE_Msk  = 0x2       // Bit mask of DMEIE field.
	DMA_S4CR_DMEIE      = 0x2       // Bit DMEIE.
	DMA_S4CR_EN_Pos     = 0x0       // Position of EN field.
	DMA_S4CR_EN_Msk     = 0x1       // Bit mask of EN field.
	DMA_S4CR_EN         = 0x1       // Bit EN.

	// S4NDTR: stream x number of data           register
	DMA_S4NDTR_NDT_Pos = 0x0    // Position of NDT field.
	DMA_S4NDTR_NDT_Msk = 0xffff // Bit mask of NDT field.

	// S4PAR: stream x peripheral address           register
	DMA_S4PAR_PA_Pos = 0x0        // Position of PA field.
	DMA_S4PAR_PA_Msk = 0xffffffff // Bit mask of PA field.

	// S4M0AR: stream x memory 0 address           register
	DMA_S4M0AR_M0A_Pos = 0x0        // Position of M0A field.
	DMA_S4M0AR_M0A_Msk = 0xffffffff // Bit mask of M0A field.

	// S4M1AR: stream x memory 1 address           register
	DMA_S4M1AR_M1A_Pos = 0x0        // Position of M1A field.
	DMA_S4M1AR_M1A_Msk = 0xffffffff // Bit mask of M1A field.

	// S4FCR: stream x FIFO control register
	DMA_S4FCR_FEIE_Pos  = 0x7  // Position of FEIE field.
	DMA_S4FCR_FEIE_Msk  = 0x80 // Bit mask of FEIE field.
	DMA_S4FCR_FEIE      = 0x80 // Bit FEIE.
	DMA_S4FCR_FS_Pos    = 0x3  // Position of FS field.
	DMA_S4FCR_FS_Msk    = 0x38 // Bit mask of FS field.
	DMA_S4FCR_DMDIS_Pos = 0x2  // Position of DMDIS field.
	DMA_S4FCR_DMDIS_Msk = 0x4  // Bit mask of DMDIS field.
	DMA_S4FCR_DMDIS     = 0x4  // Bit DMDIS.
	DMA_S4FCR_FTH_Pos   = 0x0  // Position of FTH field.
	DMA_S4FCR_FTH_Msk   = 0x3  // Bit mask of FTH field.

	// S5CR: stream x configuration           register
	DMA_S5CR_MBURST_Pos = 0x17      // Position of MBURST field.
	DMA_S5CR_MBURST_Msk = 0x1800000 // Bit mask of MBURST field.
	DMA_S5CR_PBURST_Pos = 0x15      // Position of PBURST field.
	DMA_S5CR_PBURST_Msk = 0x600000  // Bit mask of PBURST field.
	DMA_S5CR_ACK_Pos    = 0x14      // Position of ACK field.
	DMA_S5CR_ACK_Msk    = 0x100000  // Bit mask of ACK field.
	DMA_S5CR_ACK        = 0x100000  // Bit ACK.
	DMA_S5CR_CT_Pos     = 0x13      // Position of CT field.
	DMA_S5CR_CT_Msk     = 0x80000   // Bit mask of CT field.
	DMA_S5CR_CT         = 0x80000   // Bit CT.
	DMA_S5CR_DBM_Pos    = 0x12      // Position of DBM field.
	DMA_S5CR_DBM_Msk    = 0x40000   // Bit mask of DBM field.
	DMA_S5CR_DBM        = 0x40000   // Bit DBM.
	DMA_S5CR_PL_Pos     = 0x10      // Position of PL field.
	DMA_S5CR_PL_Msk     = 0x30000   // Bit mask of PL field.
	DMA_S5CR_PINCOS_Pos = 0xf       // Position of PINCOS field.
	DMA_S5CR_PINCOS_Msk = 0x8000    // Bit mask of PINCOS field.
	DMA_S5CR_PINCOS     = 0x8000    // Bit PINCOS.
	DMA_S5CR_MSIZE_Pos  = 0xd       // Position of MSIZE field.
	DMA_S5CR_MSIZE_Msk  = 0x6000    // Bit mask of MSIZE field.
	DMA_S5CR_PSIZE_Pos  = 0xb       // Position of PSIZE field.
	DMA_S5CR_PSIZE_Msk  = 0x1800    // Bit mask of PSIZE field.
	DMA_S5CR_MINC_Pos   = 0xa       // Position of MINC field.
	DMA_S5CR_MINC_Msk   = 0x400     // Bit mask of MINC field.
	DMA_S5CR_MINC       = 0x400     // Bit MINC.
	DMA_S5CR_PINC_Pos   = 0x9       // Position of PINC field.
	DMA_S5CR_PINC_Msk   = 0x200     // Bit mask of PINC field.
	DMA_S5CR_PINC       = 0x200     // Bit PINC.
	DMA_S5CR_CIRC_Pos   = 0x8       // Position of CIRC field.
	DMA_S5CR_CIRC_Msk   = 0x100     // Bit mask of CIRC field.
	DMA_S5CR_CIRC       = 0x100     // Bit CIRC.
	DMA_S5CR_DIR_Pos    = 0x6       // Position of DIR field.
	DMA_S5CR_DIR_Msk    = 0xc0      // Bit mask of DIR field.
	DMA_S5CR_PFCTRL_Pos = 0x5       // Position of PFCTRL field.
	DMA_S5CR_PFCTRL_Msk = 0x20      // Bit mask of PFCTRL field.
	DMA_S5CR_PFCTRL     = 0x20      // Bit PFCTRL.
	DMA_S5CR_TCIE_Pos   = 0x4       // Position of TCIE field.
	DMA_S5CR_TCIE_Msk   = 0x10      // Bit mask of TCIE field.
	DMA_S5CR_TCIE       = 0x10      // Bit TCIE.
	DMA_S5CR_HTIE_Pos   = 0x3       // Position of HTIE field.
	DMA_S5CR_HTIE_Msk   = 0x8       // Bit mask of HTIE field.
	DMA_S5CR_HTIE       = 0x8       // Bit HTIE.
	DMA_S5CR_TEIE_Pos   = 0x2       // Position of TEIE field.
	DMA_S5CR_TEIE_Msk   = 0x4       // Bit mask of TEIE field.
	DMA_S5CR_TEIE       = 0x4       // Bit TEIE.
	DMA_S5CR_DMEIE_Pos  = 0x1       // Position of DMEIE field.
	DMA_S5CR_DMEIE_Msk  = 0x2       // Bit mask of DMEIE field.
	DMA_S5CR_DMEIE      = 0x2       // Bit DMEIE.
	DMA_S5CR_EN_Pos     = 0x0       // Position of EN field.
	DMA_S5CR_EN_Msk     = 0x1       // Bit mask of EN field.
	DMA_S5CR_EN         = 0x1       // Bit EN.

	// S5NDTR: stream x number of data           register
	DMA_S5NDTR_NDT_Pos = 0x0    // Position of NDT field.
	DMA_S5NDTR_NDT_Msk = 0xffff // Bit mask of NDT field.

	// S5PAR: stream x peripheral address           register
	DMA_S5PAR_PA_Pos = 0x0        // Position of PA field.
	DMA_S5PAR_PA_Msk = 0xffffffff // Bit mask of PA field.

	// S5M0AR: stream x memory 0 address           register
	DMA_S5M0AR_M0A_Pos = 0x0        // Position of M0A field.
	DMA_S5M0AR_M0A_Msk = 0xffffffff // Bit mask of M0A field.

	// S5M1AR: stream x memory 1 address           register
	DMA_S5M1AR_M1A_Pos = 0x0        // Position of M1A field.
	DMA_S5M1AR_M1A_Msk = 0xffffffff // Bit mask of M1A field.

	// S5FCR: stream x FIFO control register
	DMA_S5FCR_FEIE_Pos  = 0x7  // Position of FEIE field.
	DMA_S5FCR_FEIE_Msk  = 0x80 // Bit mask of FEIE field.
	DMA_S5FCR_FEIE      = 0x80 // Bit FEIE.
	DMA_S5FCR_FS_Pos    = 0x3  // Position of FS field.
	DMA_S5FCR_FS_Msk    = 0x38 // Bit mask of FS field.
	DMA_S5FCR_DMDIS_Pos = 0x2  // Position of DMDIS field.
	DMA_S5FCR_DMDIS_Msk = 0x4  // Bit mask of DMDIS field.
	DMA_S5FCR_DMDIS     = 0x4  // Bit DMDIS.
	DMA_S5FCR_FTH_Pos   = 0x0  // Position of FTH field.
	DMA_S5FCR_FTH_Msk   = 0x3  // Bit mask of FTH field.

	// S6CR: stream x configuration           register
	DMA_S6CR_MBURST_Pos = 0x17      // Position of MBURST field.
	DMA_S6CR_MBURST_Msk = 0x1800000 // Bit mask of MBURST field.
	DMA_S6CR_PBURST_Pos = 0x15      // Position of PBURST field.
	DMA_S6CR_PBURST_Msk = 0x600000  // Bit mask of PBURST field.
	DMA_S6CR_ACK_Pos    = 0x14      // Position of ACK field.
	DMA_S6CR_ACK_Msk    = 0x100000  // Bit mask of ACK field.
	DMA_S6CR_ACK        = 0x100000  // Bit ACK.
	DMA_S6CR_CT_Pos     = 0x13      // Position of CT field.
	DMA_S6CR_CT_Msk     = 0x80000   // Bit mask of CT field.
	DMA_S6CR_CT         = 0x80000   // Bit CT.
	DMA_S6CR_DBM_Pos    = 0x12      // Position of DBM field.
	DMA_S6CR_DBM_Msk    = 0x40000   // Bit mask of DBM field.
	DMA_S6CR_DBM        = 0x40000   // Bit DBM.
	DMA_S6CR_PL_Pos     = 0x10      // Position of PL field.
	DMA_S6CR_PL_Msk     = 0x30000   // Bit mask of PL field.
	DMA_S6CR_PINCOS_Pos = 0xf       // Position of PINCOS field.
	DMA_S6CR_PINCOS_Msk = 0x8000    // Bit mask of PINCOS field.
	DMA_S6CR_PINCOS     = 0x8000    // Bit PINCOS.
	DMA_S6CR_MSIZE_Pos  = 0xd       // Position of MSIZE field.
	DMA_S6CR_MSIZE_Msk  = 0x6000    // Bit mask of MSIZE field.
	DMA_S6CR_PSIZE_Pos  = 0xb       // Position of PSIZE field.
	DMA_S6CR_PSIZE_Msk  = 0x1800    // Bit mask of PSIZE field.
	DMA_S6CR_MINC_Pos   = 0xa       // Position of MINC field.
	DMA_S6CR_MINC_Msk   = 0x400     // Bit mask of MINC field.
	DMA_S6CR_MINC       = 0x400     // Bit MINC.
	DMA_S6CR_PINC_Pos   = 0x9       // Position of PINC field.
	DMA_S6CR_PINC_Msk   = 0x200     // Bit mask of PINC field.
	DMA_S6CR_PINC       = 0x200     // Bit PINC.
	DMA_S6CR_CIRC_Pos   = 0x8       // Position of CIRC field.
	DMA_S6CR_CIRC_Msk   = 0x100     // Bit mask of CIRC field.
	DMA_S6CR_CIRC       = 0x100     // Bit CIRC.
	DMA_S6CR_DIR_Pos    = 0x6       // Position of DIR field.
	DMA_S6CR_DIR_Msk    = 0xc0      // Bit mask of DIR field.
	DMA_S6CR_PFCTRL_Pos = 0x5       // Position of PFCTRL field.
	DMA_S6CR_PFCTRL_Msk = 0x20      // Bit mask of PFCTRL field.
	DMA_S6CR_PFCTRL     = 0x20      // Bit PFCTRL.
	DMA_S6CR_TCIE_Pos   = 0x4       // Position of TCIE field.
	DMA_S6CR_TCIE_Msk   = 0x10      // Bit mask of TCIE field.
	DMA_S6CR_TCIE       = 0x10      // Bit TCIE.
	DMA_S6CR_HTIE_Pos   = 0x3       // Position of HTIE field.
	DMA_S6CR_HTIE_Msk   = 0x8       // Bit mask of HTIE field.
	DMA_S6CR_HTIE       = 0x8       // Bit HTIE.
	DMA_S6CR_TEIE_Pos   = 0x2       // Position of TEIE field.
	DMA_S6CR_TEIE_Msk   = 0x4       // Bit mask of TEIE field.
	DMA_S6CR_TEIE       = 0x4       // Bit TEIE.
	DMA_S6CR_DMEIE_Pos  = 0x1       // Position of DMEIE field.
	DMA_S6CR_DMEIE_Msk  = 0x2       // Bit mask of DMEIE field.
	DMA_S6CR_DMEIE      = 0x2       // Bit DMEIE.
	DMA_S6CR_EN_Pos     = 0x0       // Position of EN field.
	DMA_S6CR_EN_Msk     = 0x1       // Bit mask of EN field.
	DMA_S6CR_EN         = 0x1       // Bit EN.

	// S6NDTR: stream x number of data           register
	DMA_S6NDTR_NDT_Pos = 0x0    // Position of NDT field.
	DMA_S6NDTR_NDT_Msk = 0xffff // Bit mask of NDT field.

	// S6PAR: stream x peripheral address           register
	DMA_S6PAR_PA_Pos = 0x0        // Position of PA field.
	DMA_S6PAR_PA_Msk = 0xffffffff // Bit mask of PA field.

	// S6M0AR: stream x memory 0 address           register
	DMA_S6M0AR_M0A_Pos = 0x0        // Position of M0A field.
	DMA_S6M0AR_M0A_Msk = 0xffffffff // Bit mask of M0A field.

	// S6M1AR: stream x memory 1 address           register
	DMA_S6M1AR_M1A_Pos = 0x0        // Position of M1A field.
	DMA_S6M1AR_M1A_Msk = 0xffffffff // Bit mask of M1A field.

	// S6FCR: stream x FIFO control register
	DMA_S6FCR_FEIE_Pos  = 0x7  // Position of FEIE field.
	DMA_S6FCR_FEIE_Msk  = 0x80 // Bit mask of FEIE field.
	DMA_S6FCR_FEIE      = 0x80 // Bit FEIE.
	DMA_S6FCR_FS_Pos    = 0x3  // Position of FS field.
	DMA_S6FCR_FS_Msk    = 0x38 // Bit mask of FS field.
	DMA_S6FCR_DMDIS_Pos = 0x2  // Position of DMDIS field.
	DMA_S6FCR_DMDIS_Msk = 0x4  // Bit mask of DMDIS field.
	DMA_S6FCR_DMDIS     = 0x4  // Bit DMDIS.
	DMA_S6FCR_FTH_Pos   = 0x0  // Position of FTH field.
	DMA_S6FCR_FTH_Msk   = 0x3  // Bit mask of FTH field.

	// S7CR: stream x configuration           register
	DMA_S7CR_MBURST_Pos = 0x17      // Position of MBURST field.
	DMA_S7CR_MBURST_Msk = 0x1800000 // Bit mask of MBURST field.
	DMA_S7CR_PBURST_Pos = 0x15      // Position of PBURST field.
	DMA_S7CR_PBURST_Msk = 0x600000  // Bit mask of PBURST field.
	DMA_S7CR_ACK_Pos    = 0x14      // Position of ACK field.
	DMA_S7CR_ACK_Msk    = 0x100000  // Bit mask of ACK field.
	DMA_S7CR_ACK        = 0x100000  // Bit ACK.
	DMA_S7CR_CT_Pos     = 0x13      // Position of CT field.
	DMA_S7CR_CT_Msk     = 0x80000   // Bit mask of CT field.
	DMA_S7CR_CT         = 0x80000   // Bit CT.
	DMA_S7CR_DBM_Pos    = 0x12      // Position of DBM field.
	DMA_S7CR_DBM_Msk    = 0x40000   // Bit mask of DBM field.
	DMA_S7CR_DBM        = 0x40000   // Bit DBM.
	DMA_S7CR_PL_Pos     = 0x10      // Position of PL field.
	DMA_S7CR_PL_Msk     = 0x30000   // Bit mask of PL field.
	DMA_S7CR_PINCOS_Pos = 0xf       // Position of PINCOS field.
	DMA_S7CR_PINCOS_Msk = 0x8000    // Bit mask of PINCOS field.
	DMA_S7CR_PINCOS     = 0x8000    // Bit PINCOS.
	DMA_S7CR_MSIZE_Pos  = 0xd       // Position of MSIZE field.
	DMA_S7CR_MSIZE_Msk  = 0x6000    // Bit mask of MSIZE field.
	DMA_S7CR_PSIZE_Pos  = 0xb       // Position of PSIZE field.
	DMA_S7CR_PSIZE_Msk  = 0x1800    // Bit mask of PSIZE field.
	DMA_S7CR_MINC_Pos   = 0xa       // Position of MINC field.
	DMA_S7CR_MINC_Msk   = 0x400     // Bit mask of MINC field.
	DMA_S7CR_MINC       = 0x400     // Bit MINC.
	DMA_S7CR_PINC_Pos   = 0x9       // Position of PINC field.
	DMA_S7CR_PINC_Msk   = 0x200     // Bit mask of PINC field.
	DMA_S7CR_PINC       = 0x200     // Bit PINC.
	DMA_S7CR_CIRC_Pos   = 0x8       // Position of CIRC field.
	DMA_S7CR_CIRC_Msk   = 0x100     // Bit mask of CIRC field.
	DMA_S7CR_CIRC       = 0x100     // Bit CIRC.
	DMA_S7CR_DIR_Pos    = 0x6       // Position of DIR field.
	DMA_S7CR_DIR_Msk    = 0xc0      // Bit mask of DIR field.
	DMA_S7CR_PFCTRL_Pos = 0x5       // Position of PFCTRL field.
	DMA_S7CR_PFCTRL_Msk = 0x20      // Bit mask of PFCTRL field.
	DMA_S7CR_PFCTRL     = 0x20      // Bit PFCTRL.
	DMA_S7CR_TCIE_Pos   = 0x4       // Position of TCIE field.
	DMA_S7CR_TCIE_Msk   = 0x10      // Bit mask of TCIE field.
	DMA_S7CR_TCIE       = 0x10      // Bit TCIE.
	DMA_S7CR_HTIE_Pos   = 0x3       // Position of HTIE field.
	DMA_S7CR_HTIE_Msk   = 0x8       // Bit mask of HTIE field.
	DMA_S7CR_HTIE       = 0x8       // Bit HTIE.
	DMA_S7CR_TEIE_Pos   = 0x2       // Position of TEIE field.
	DMA_S7CR_TEIE_Msk   = 0x4       // Bit mask of TEIE field.
	DMA_S7CR_TEIE       = 0x4       // Bit TEIE.
	DMA_S7CR_DMEIE_Pos  = 0x1       // Position of DMEIE field.
	DMA_S7CR_DMEIE_Msk  = 0x2       // Bit mask of DMEIE field.
	DMA_S7CR_DMEIE      = 0x2       // Bit DMEIE.
	DMA_S7CR_EN_Pos     = 0x0       // Position of EN field.
	DMA_S7CR_EN_Msk     = 0x1       // Bit mask of EN field.
	DMA_S7CR_EN         = 0x1       // Bit EN.

	// S7NDTR: stream x number of data           register
	DMA_S7NDTR_NDT_Pos = 0x0    // Position of NDT field.
	DMA_S7NDTR_NDT_Msk = 0xffff // Bit mask of NDT field.

	// S7PAR: stream x peripheral address           register
	DMA_S7PAR_PA_Pos = 0x0        // Position of PA field.
	DMA_S7PAR_PA_Msk = 0xffffffff // Bit mask of PA field.

	// S7M0AR: stream x memory 0 address           register
	DMA_S7M0AR_M0A_Pos = 0x0        // Position of M0A field.
	DMA_S7M0AR_M0A_Msk = 0xffffffff // Bit mask of M0A field.

	// S7M1AR: stream x memory 1 address           register
	DMA_S7M1AR_M1A_Pos = 0x0        // Position of M1A field.
	DMA_S7M1AR_M1A_Msk = 0xffffffff // Bit mask of M1A field.

	// S7FCR: stream x FIFO control register
	DMA_S7FCR_FEIE_Pos  = 0x7  // Position of FEIE field.
	DMA_S7FCR_FEIE_Msk  = 0x80 // Bit mask of FEIE field.
	DMA_S7FCR_FEIE      = 0x80 // Bit FEIE.
	DMA_S7FCR_FS_Pos    = 0x3  // Position of FS field.
	DMA_S7FCR_FS_Msk    = 0x38 // Bit mask of FS field.
	DMA_S7FCR_DMDIS_Pos = 0x2  // Position of DMDIS field.
	DMA_S7FCR_DMDIS_Msk = 0x4  // Bit mask of DMDIS field.
	DMA_S7FCR_DMDIS     = 0x4  // Bit DMDIS.
	DMA_S7FCR_FTH_Pos   = 0x0  // Position of FTH field.
	DMA_S7FCR_FTH_Msk   = 0x3  // Bit mask of FTH field.
)

// Bitfields for HRTIM_Master: High Resolution Timer: Master Timers
const (
	// MCR: Master Timer Control Register
	HRTIM_MCR_BRSTDMA_Pos   = 0x1e       // Position of BRSTDMA field.
	HRTIM_MCR_BRSTDMA_Msk   = 0xc0000000 // Bit mask of BRSTDMA field.
	HRTIM_MCR_MREPU_Pos     = 0x1d       // Position of MREPU field.
	HRTIM_MCR_MREPU_Msk     = 0x20000000 // Bit mask of MREPU field.
	HRTIM_MCR_MREPU         = 0x20000000 // Bit MREPU.
	HRTIM_MCR_PREEN_Pos     = 0x1b       // Position of PREEN field.
	HRTIM_MCR_PREEN_Msk     = 0x8000000  // Bit mask of PREEN field.
	HRTIM_MCR_PREEN         = 0x8000000  // Bit PREEN.
	HRTIM_MCR_DACSYNC_Pos   = 0x19       // Position of DACSYNC field.
	HRTIM_MCR_DACSYNC_Msk   = 0x6000000  // Bit mask of DACSYNC field.
	HRTIM_MCR_TECEN_Pos     = 0x15       // Position of TECEN field.
	HRTIM_MCR_TECEN_Msk     = 0x200000   // Bit mask of TECEN field.
	HRTIM_MCR_TECEN         = 0x200000   // Bit TECEN.
	HRTIM_MCR_TDCEN_Pos     = 0x14       // Position of TDCEN field.
	HRTIM_MCR_TDCEN_Msk     = 0x100000   // Bit mask of TDCEN field.
	HRTIM_MCR_TDCEN         = 0x100000   // Bit TDCEN.
	HRTIM_MCR_TCCEN_Pos     = 0x13       // Position of TCCEN field.
	HRTIM_MCR_TCCEN_Msk     = 0x80000    // Bit mask of TCCEN field.
	HRTIM_MCR_TCCEN         = 0x80000    // Bit TCCEN.
	HRTIM_MCR_TBCEN_Pos     = 0x12       // Position of TBCEN field.
	HRTIM_MCR_TBCEN_Msk     = 0x40000    // Bit mask of TBCEN field.
	HRTIM_MCR_TBCEN         = 0x40000    // Bit TBCEN.
	HRTIM_MCR_TACEN_Pos     = 0x11       // Position of TACEN field.
	HRTIM_MCR_TACEN_Msk     = 0x20000    // Bit mask of TACEN field.
	HRTIM_MCR_TACEN         = 0x20000    // Bit TACEN.
	HRTIM_MCR_MCEN_Pos      = 0x10       // Position of MCEN field.
	HRTIM_MCR_MCEN_Msk      = 0x10000    // Bit mask of MCEN field.
	HRTIM_MCR_MCEN          = 0x10000    // Bit MCEN.
	HRTIM_MCR_SYNC_SRC_Pos  = 0xe        // Position of SYNC_SRC field.
	HRTIM_MCR_SYNC_SRC_Msk  = 0xc000     // Bit mask of SYNC_SRC field.
	HRTIM_MCR_SYNC_OUT_Pos  = 0xc        // Position of SYNC_OUT field.
	HRTIM_MCR_SYNC_OUT_Msk  = 0x3000     // Bit mask of SYNC_OUT field.
	HRTIM_MCR_SYNCSTRTM_Pos = 0xb        // Position of SYNCSTRTM field.
	HRTIM_MCR_SYNCSTRTM_Msk = 0x800      // Bit mask of SYNCSTRTM field.
	HRTIM_MCR_SYNCSTRTM     = 0x800      // Bit SYNCSTRTM.
	HRTIM_MCR_SYNCRSTM_Pos  = 0xa        // Position of SYNCRSTM field.
	HRTIM_MCR_SYNCRSTM_Msk  = 0x400      // Bit mask of SYNCRSTM field.
	HRTIM_MCR_SYNCRSTM      = 0x400      // Bit SYNCRSTM.
	HRTIM_MCR_SYNC_IN_Pos   = 0x8        // Position of SYNC_IN field.
	HRTIM_MCR_SYNC_IN_Msk   = 0x300      // Bit mask of SYNC_IN field.
	HRTIM_MCR_HALF_Pos      = 0x5        // Position of HALF field.
	HRTIM_MCR_HALF_Msk      = 0x20       // Bit mask of HALF field.
	HRTIM_MCR_HALF          = 0x20       // Bit HALF.
	HRTIM_MCR_RETRIG_Pos    = 0x4        // Position of RETRIG field.
	HRTIM_MCR_RETRIG_Msk    = 0x10       // Bit mask of RETRIG field.
	HRTIM_MCR_RETRIG        = 0x10       // Bit RETRIG.
	HRTIM_MCR_CONT_Pos      = 0x3        // Position of CONT field.
	HRTIM_MCR_CONT_Msk      = 0x8        // Bit mask of CONT field.
	HRTIM_MCR_CONT          = 0x8        // Bit CONT.
	HRTIM_MCR_CK_PSC_Pos    = 0x0        // Position of CK_PSC field.
	HRTIM_MCR_CK_PSC_Msk    = 0x7        // Bit mask of CK_PSC field.

	// MISR: Master Timer Interrupt Status           Register
	HRTIM_MISR_MUPD_Pos  = 0x6  // Position of MUPD field.
	HRTIM_MISR_MUPD_Msk  = 0x40 // Bit mask of MUPD field.
	HRTIM_MISR_MUPD      = 0x40 // Bit MUPD.
	HRTIM_MISR_SYNC_Pos  = 0x5  // Position of SYNC field.
	HRTIM_MISR_SYNC_Msk  = 0x20 // Bit mask of SYNC field.
	HRTIM_MISR_SYNC      = 0x20 // Bit SYNC.
	HRTIM_MISR_MREP_Pos  = 0x4  // Position of MREP field.
	HRTIM_MISR_MREP_Msk  = 0x10 // Bit mask of MREP field.
	HRTIM_MISR_MREP      = 0x10 // Bit MREP.
	HRTIM_MISR_MCMP4_Pos = 0x3  // Position of MCMP4 field.
	HRTIM_MISR_MCMP4_Msk = 0x8  // Bit mask of MCMP4 field.
	HRTIM_MISR_MCMP4     = 0x8  // Bit MCMP4.
	HRTIM_MISR_MCMP3_Pos = 0x2  // Position of MCMP3 field.
	HRTIM_MISR_MCMP3_Msk = 0x4  // Bit mask of MCMP3 field.
	HRTIM_MISR_MCMP3     = 0x4  // Bit MCMP3.
	HRTIM_MISR_MCMP2_Pos = 0x1  // Position of MCMP2 field.
	HRTIM_MISR_MCMP2_Msk = 0x2  // Bit mask of MCMP2 field.
	HRTIM_MISR_MCMP2     = 0x2  // Bit MCMP2.
	HRTIM_MISR_MCMP1_Pos = 0x0  // Position of MCMP1 field.
	HRTIM_MISR_MCMP1_Msk = 0x1  // Bit mask of MCMP1 field.
	HRTIM_MISR_MCMP1     = 0x1  // Bit MCMP1.

	// MICR: Master Timer Interrupt Clear           Register
	HRTIM_MICR_MUPDC_Pos  = 0x6  // Position of MUPDC field.
	HRTIM_MICR_MUPDC_Msk  = 0x40 // Bit mask of MUPDC field.
	HRTIM_MICR_MUPDC      = 0x40 // Bit MUPDC.
	HRTIM_MICR_SYNCC_Pos  = 0x5  // Position of SYNCC field.
	HRTIM_MICR_SYNCC_Msk  = 0x20 // Bit mask of SYNCC field.
	HRTIM_MICR_SYNCC      = 0x20 // Bit SYNCC.
	HRTIM_MICR_MREPC_Pos  = 0x4  // Position of MREPC field.
	HRTIM_MICR_MREPC_Msk  = 0x10 // Bit mask of MREPC field.
	HRTIM_MICR_MREPC      = 0x10 // Bit MREPC.
	HRTIM_MICR_MCMP4C_Pos = 0x3  // Position of MCMP4C field.
	HRTIM_MICR_MCMP4C_Msk = 0x8  // Bit mask of MCMP4C field.
	HRTIM_MICR_MCMP4C     = 0x8  // Bit MCMP4C.
	HRTIM_MICR_MCMP3C_Pos = 0x2  // Position of MCMP3C field.
	HRTIM_MICR_MCMP3C_Msk = 0x4  // Bit mask of MCMP3C field.
	HRTIM_MICR_MCMP3C     = 0x4  // Bit MCMP3C.
	HRTIM_MICR_MCMP2C_Pos = 0x1  // Position of MCMP2C field.
	HRTIM_MICR_MCMP2C_Msk = 0x2  // Bit mask of MCMP2C field.
	HRTIM_MICR_MCMP2C     = 0x2  // Bit MCMP2C.
	HRTIM_MICR_MCMP1C_Pos = 0x0  // Position of MCMP1C field.
	HRTIM_MICR_MCMP1C_Msk = 0x1  // Bit mask of MCMP1C field.
	HRTIM_MICR_MCMP1C     = 0x1  // Bit MCMP1C.

	// MDIER4: MDIER4
	HRTIM_MDIER4_MUPDDE_Pos  = 0x16     // Position of MUPDDE field.
	HRTIM_MDIER4_MUPDDE_Msk  = 0x400000 // Bit mask of MUPDDE field.
	HRTIM_MDIER4_MUPDDE      = 0x400000 // Bit MUPDDE.
	HRTIM_MDIER4_SYNCDE_Pos  = 0x15     // Position of SYNCDE field.
	HRTIM_MDIER4_SYNCDE_Msk  = 0x200000 // Bit mask of SYNCDE field.
	HRTIM_MDIER4_SYNCDE      = 0x200000 // Bit SYNCDE.
	HRTIM_MDIER4_MREPDE_Pos  = 0x14     // Position of MREPDE field.
	HRTIM_MDIER4_MREPDE_Msk  = 0x100000 // Bit mask of MREPDE field.
	HRTIM_MDIER4_MREPDE      = 0x100000 // Bit MREPDE.
	HRTIM_MDIER4_MCMP4DE_Pos = 0x13     // Position of MCMP4DE field.
	HRTIM_MDIER4_MCMP4DE_Msk = 0x80000  // Bit mask of MCMP4DE field.
	HRTIM_MDIER4_MCMP4DE     = 0x80000  // Bit MCMP4DE.
	HRTIM_MDIER4_MCMP3DE_Pos = 0x12     // Position of MCMP3DE field.
	HRTIM_MDIER4_MCMP3DE_Msk = 0x40000  // Bit mask of MCMP3DE field.
	HRTIM_MDIER4_MCMP3DE     = 0x40000  // Bit MCMP3DE.
	HRTIM_MDIER4_MCMP2DE_Pos = 0x11     // Position of MCMP2DE field.
	HRTIM_MDIER4_MCMP2DE_Msk = 0x20000  // Bit mask of MCMP2DE field.
	HRTIM_MDIER4_MCMP2DE     = 0x20000  // Bit MCMP2DE.
	HRTIM_MDIER4_MCMP1DE_Pos = 0x10     // Position of MCMP1DE field.
	HRTIM_MDIER4_MCMP1DE_Msk = 0x10000  // Bit mask of MCMP1DE field.
	HRTIM_MDIER4_MCMP1DE     = 0x10000  // Bit MCMP1DE.
	HRTIM_MDIER4_MUPDIE_Pos  = 0x6      // Position of MUPDIE field.
	HRTIM_MDIER4_MUPDIE_Msk  = 0x40     // Bit mask of MUPDIE field.
	HRTIM_MDIER4_MUPDIE      = 0x40     // Bit MUPDIE.
	HRTIM_MDIER4_SYNCIE_Pos  = 0x5      // Position of SYNCIE field.
	HRTIM_MDIER4_SYNCIE_Msk  = 0x20     // Bit mask of SYNCIE field.
	HRTIM_MDIER4_SYNCIE      = 0x20     // Bit SYNCIE.
	HRTIM_MDIER4_MREPIE_Pos  = 0x4      // Position of MREPIE field.
	HRTIM_MDIER4_MREPIE_Msk  = 0x10     // Bit mask of MREPIE field.
	HRTIM_MDIER4_MREPIE      = 0x10     // Bit MREPIE.
	HRTIM_MDIER4_MCMP4IE_Pos = 0x3      // Position of MCMP4IE field.
	HRTIM_MDIER4_MCMP4IE_Msk = 0x8      // Bit mask of MCMP4IE field.
	HRTIM_MDIER4_MCMP4IE     = 0x8      // Bit MCMP4IE.
	HRTIM_MDIER4_MCMP3IE_Pos = 0x2      // Position of MCMP3IE field.
	HRTIM_MDIER4_MCMP3IE_Msk = 0x4      // Bit mask of MCMP3IE field.
	HRTIM_MDIER4_MCMP3IE     = 0x4      // Bit MCMP3IE.
	HRTIM_MDIER4_MCMP2IE_Pos = 0x1      // Position of MCMP2IE field.
	HRTIM_MDIER4_MCMP2IE_Msk = 0x2      // Bit mask of MCMP2IE field.
	HRTIM_MDIER4_MCMP2IE     = 0x2      // Bit MCMP2IE.
	HRTIM_MDIER4_MCMP1IE_Pos = 0x0      // Position of MCMP1IE field.
	HRTIM_MDIER4_MCMP1IE_Msk = 0x1      // Bit mask of MCMP1IE field.
	HRTIM_MDIER4_MCMP1IE     = 0x1      // Bit MCMP1IE.

	// MCNTR: Master Timer Counter Register
	HRTIM_MCNTR_MCNT_Pos = 0x0    // Position of MCNT field.
	HRTIM_MCNTR_MCNT_Msk = 0xffff // Bit mask of MCNT field.

	// MPER: Master Timer Period Register
	HRTIM_MPER_MPER_Pos = 0x0    // Position of MPER field.
	HRTIM_MPER_MPER_Msk = 0xffff // Bit mask of MPER field.

	// MREP: Master Timer Repetition           Register
	HRTIM_MREP_MREP_Pos = 0x0  // Position of MREP field.
	HRTIM_MREP_MREP_Msk = 0xff // Bit mask of MREP field.

	// MCMP1R: Master Timer Compare 1           Register
	HRTIM_MCMP1R_MCMP1_Pos = 0x0    // Position of MCMP1 field.
	HRTIM_MCMP1R_MCMP1_Msk = 0xffff // Bit mask of MCMP1 field.

	// MCMP2R: Master Timer Compare 2           Register
	HRTIM_MCMP2R_MCMP2_Pos = 0x0    // Position of MCMP2 field.
	HRTIM_MCMP2R_MCMP2_Msk = 0xffff // Bit mask of MCMP2 field.

	// MCMP3R: Master Timer Compare 3           Register
	HRTIM_MCMP3R_MCMP3_Pos = 0x0    // Position of MCMP3 field.
	HRTIM_MCMP3R_MCMP3_Msk = 0xffff // Bit mask of MCMP3 field.

	// MCMP4R: Master Timer Compare 4           Register
	HRTIM_MCMP4R_MCMP4_Pos = 0x0    // Position of MCMP4 field.
	HRTIM_MCMP4R_MCMP4_Msk = 0xffff // Bit mask of MCMP4 field.
)

// Bitfields for DFSDM: Digital filter for sigma delta modulators
const (
	// DFSDM_CHCFG0R1: DFSDM channel configuration 0 register           1
	DFSDM_DFSDM_CHCFG0R1_SITP_Pos     = 0x0        // Position of SITP field.
	DFSDM_DFSDM_CHCFG0R1_SITP_Msk     = 0x3        // Bit mask of SITP field.
	DFSDM_DFSDM_CHCFG0R1_SPICKSEL_Pos = 0x2        // Position of SPICKSEL field.
	DFSDM_DFSDM_CHCFG0R1_SPICKSEL_Msk = 0xc        // Bit mask of SPICKSEL field.
	DFSDM_DFSDM_CHCFG0R1_SCDEN_Pos    = 0x5        // Position of SCDEN field.
	DFSDM_DFSDM_CHCFG0R1_SCDEN_Msk    = 0x20       // Bit mask of SCDEN field.
	DFSDM_DFSDM_CHCFG0R1_SCDEN        = 0x20       // Bit SCDEN.
	DFSDM_DFSDM_CHCFG0R1_CKABEN_Pos   = 0x6        // Position of CKABEN field.
	DFSDM_DFSDM_CHCFG0R1_CKABEN_Msk   = 0x40       // Bit mask of CKABEN field.
	DFSDM_DFSDM_CHCFG0R1_CKABEN       = 0x40       // Bit CKABEN.
	DFSDM_DFSDM_CHCFG0R1_CHEN_Pos     = 0x7        // Position of CHEN field.
	DFSDM_DFSDM_CHCFG0R1_CHEN_Msk     = 0x80       // Bit mask of CHEN field.
	DFSDM_DFSDM_CHCFG0R1_CHEN         = 0x80       // Bit CHEN.
	DFSDM_DFSDM_CHCFG0R1_CHINSEL_Pos  = 0x8        // Position of CHINSEL field.
	DFSDM_DFSDM_CHCFG0R1_CHINSEL_Msk  = 0x100      // Bit mask of CHINSEL field.
	DFSDM_DFSDM_CHCFG0R1_CHINSEL      = 0x100      // Bit CHINSEL.
	DFSDM_DFSDM_CHCFG0R1_DATMPX_Pos   = 0xc        // Position of DATMPX field.
	DFSDM_DFSDM_CHCFG0R1_DATMPX_Msk   = 0x3000     // Bit mask of DATMPX field.
	DFSDM_DFSDM_CHCFG0R1_DATPACK_Pos  = 0xe        // Position of DATPACK field.
	DFSDM_DFSDM_CHCFG0R1_DATPACK_Msk  = 0xc000     // Bit mask of DATPACK field.
	DFSDM_DFSDM_CHCFG0R1_CKOUTDIV_Pos = 0x10       // Position of CKOUTDIV field.
	DFSDM_DFSDM_CHCFG0R1_CKOUTDIV_Msk = 0xff0000   // Bit mask of CKOUTDIV field.
	DFSDM_DFSDM_CHCFG0R1_CKOUTSRC_Pos = 0x1e       // Position of CKOUTSRC field.
	DFSDM_DFSDM_CHCFG0R1_CKOUTSRC_Msk = 0x40000000 // Bit mask of CKOUTSRC field.
	DFSDM_DFSDM_CHCFG0R1_CKOUTSRC     = 0x40000000 // Bit CKOUTSRC.
	DFSDM_DFSDM_CHCFG0R1_DFSDMEN_Pos  = 0x1f       // Position of DFSDMEN field.
	DFSDM_DFSDM_CHCFG0R1_DFSDMEN_Msk  = 0x80000000 // Bit mask of DFSDMEN field.
	DFSDM_DFSDM_CHCFG0R1_DFSDMEN      = 0x80000000 // Bit DFSDMEN.

	// DFSDM_CHCFG1R1: DFSDM channel configuration 1 register           1
	DFSDM_DFSDM_CHCFG1R1_SITP_Pos     = 0x0        // Position of SITP field.
	DFSDM_DFSDM_CHCFG1R1_SITP_Msk     = 0x3        // Bit mask of SITP field.
	DFSDM_DFSDM_CHCFG1R1_SPICKSEL_Pos = 0x2        // Position of SPICKSEL field.
	DFSDM_DFSDM_CHCFG1R1_SPICKSEL_Msk = 0xc        // Bit mask of SPICKSEL field.
	DFSDM_DFSDM_CHCFG1R1_SCDEN_Pos    = 0x5        // Position of SCDEN field.
	DFSDM_DFSDM_CHCFG1R1_SCDEN_Msk    = 0x20       // Bit mask of SCDEN field.
	DFSDM_DFSDM_CHCFG1R1_SCDEN        = 0x20       // Bit SCDEN.
	DFSDM_DFSDM_CHCFG1R1_CKABEN_Pos   = 0x6        // Position of CKABEN field.
	DFSDM_DFSDM_CHCFG1R1_CKABEN_Msk   = 0x40       // Bit mask of CKABEN field.
	DFSDM_DFSDM_CHCFG1R1_CKABEN       = 0x40       // Bit CKABEN.
	DFSDM_DFSDM_CHCFG1R1_CHEN_Pos     = 0x7        // Position of CHEN field.
	DFSDM_DFSDM_CHCFG1R1_CHEN_Msk     = 0x80       // Bit mask of CHEN field.
	DFSDM_DFSDM_CHCFG1R1_CHEN         = 0x80       // Bit CHEN.
	DFSDM_DFSDM_CHCFG1R1_CHINSEL_Pos  = 0x8        // Position of CHINSEL field.
	DFSDM_DFSDM_CHCFG1R1_CHINSEL_Msk  = 0x100      // Bit mask of CHINSEL field.
	DFSDM_DFSDM_CHCFG1R1_CHINSEL      = 0x100      // Bit CHINSEL.
	DFSDM_DFSDM_CHCFG1R1_DATMPX_Pos   = 0xc        // Position of DATMPX field.
	DFSDM_DFSDM_CHCFG1R1_DATMPX_Msk   = 0x3000     // Bit mask of DATMPX field.
	DFSDM_DFSDM_CHCFG1R1_DATPACK_Pos  = 0xe        // Position of DATPACK field.
	DFSDM_DFSDM_CHCFG1R1_DATPACK_Msk  = 0xc000     // Bit mask of DATPACK field.
	DFSDM_DFSDM_CHCFG1R1_CKOUTDIV_Pos = 0x10       // Position of CKOUTDIV field.
	DFSDM_DFSDM_CHCFG1R1_CKOUTDIV_Msk = 0xff0000   // Bit mask of CKOUTDIV field.
	DFSDM_DFSDM_CHCFG1R1_CKOUTSRC_Pos = 0x1e       // Position of CKOUTSRC field.
	DFSDM_DFSDM_CHCFG1R1_CKOUTSRC_Msk = 0x40000000 // Bit mask of CKOUTSRC field.
	DFSDM_DFSDM_CHCFG1R1_CKOUTSRC     = 0x40000000 // Bit CKOUTSRC.
	DFSDM_DFSDM_CHCFG1R1_DFSDMEN_Pos  = 0x1f       // Position of DFSDMEN field.
	DFSDM_DFSDM_CHCFG1R1_DFSDMEN_Msk  = 0x80000000 // Bit mask of DFSDMEN field.
	DFSDM_DFSDM_CHCFG1R1_DFSDMEN      = 0x80000000 // Bit DFSDMEN.

	// DFSDM_CHCFG2R1: DFSDM channel configuration 2 register           1
	DFSDM_DFSDM_CHCFG2R1_SITP_Pos     = 0x0        // Position of SITP field.
	DFSDM_DFSDM_CHCFG2R1_SITP_Msk     = 0x3        // Bit mask of SITP field.
	DFSDM_DFSDM_CHCFG2R1_SPICKSEL_Pos = 0x2        // Position of SPICKSEL field.
	DFSDM_DFSDM_CHCFG2R1_SPICKSEL_Msk = 0xc        // Bit mask of SPICKSEL field.
	DFSDM_DFSDM_CHCFG2R1_SCDEN_Pos    = 0x5        // Position of SCDEN field.
	DFSDM_DFSDM_CHCFG2R1_SCDEN_Msk    = 0x20       // Bit mask of SCDEN field.
	DFSDM_DFSDM_CHCFG2R1_SCDEN        = 0x20       // Bit SCDEN.
	DFSDM_DFSDM_CHCFG2R1_CKABEN_Pos   = 0x6        // Position of CKABEN field.
	DFSDM_DFSDM_CHCFG2R1_CKABEN_Msk   = 0x40       // Bit mask of CKABEN field.
	DFSDM_DFSDM_CHCFG2R1_CKABEN       = 0x40       // Bit CKABEN.
	DFSDM_DFSDM_CHCFG2R1_CHEN_Pos     = 0x7        // Position of CHEN field.
	DFSDM_DFSDM_CHCFG2R1_CHEN_Msk     = 0x80       // Bit mask of CHEN field.
	DFSDM_DFSDM_CHCFG2R1_CHEN         = 0x80       // Bit CHEN.
	DFSDM_DFSDM_CHCFG2R1_CHINSEL_Pos  = 0x8        // Position of CHINSEL field.
	DFSDM_DFSDM_CHCFG2R1_CHINSEL_Msk  = 0x100      // Bit mask of CHINSEL field.
	DFSDM_DFSDM_CHCFG2R1_CHINSEL      = 0x100      // Bit CHINSEL.
	DFSDM_DFSDM_CHCFG2R1_DATMPX_Pos   = 0xc        // Position of DATMPX field.
	DFSDM_DFSDM_CHCFG2R1_DATMPX_Msk   = 0x3000     // Bit mask of DATMPX field.
	DFSDM_DFSDM_CHCFG2R1_DATPACK_Pos  = 0xe        // Position of DATPACK field.
	DFSDM_DFSDM_CHCFG2R1_DATPACK_Msk  = 0xc000     // Bit mask of DATPACK field.
	DFSDM_DFSDM_CHCFG2R1_CKOUTDIV_Pos = 0x10       // Position of CKOUTDIV field.
	DFSDM_DFSDM_CHCFG2R1_CKOUTDIV_Msk = 0xff0000   // Bit mask of CKOUTDIV field.
	DFSDM_DFSDM_CHCFG2R1_CKOUTSRC_Pos = 0x1e       // Position of CKOUTSRC field.
	DFSDM_DFSDM_CHCFG2R1_CKOUTSRC_Msk = 0x40000000 // Bit mask of CKOUTSRC field.
	DFSDM_DFSDM_CHCFG2R1_CKOUTSRC     = 0x40000000 // Bit CKOUTSRC.
	DFSDM_DFSDM_CHCFG2R1_DFSDMEN_Pos  = 0x1f       // Position of DFSDMEN field.
	DFSDM_DFSDM_CHCFG2R1_DFSDMEN_Msk  = 0x80000000 // Bit mask of DFSDMEN field.
	DFSDM_DFSDM_CHCFG2R1_DFSDMEN      = 0x80000000 // Bit DFSDMEN.

	// DFSDM_CHCFG3R1: DFSDM channel configuration 3 register           1
	DFSDM_DFSDM_CHCFG3R1_SITP_Pos     = 0x0        // Position of SITP field.
	DFSDM_DFSDM_CHCFG3R1_SITP_Msk     = 0x3        // Bit mask of SITP field.
	DFSDM_DFSDM_CHCFG3R1_SPICKSEL_Pos = 0x2        // Position of SPICKSEL field.
	DFSDM_DFSDM_CHCFG3R1_SPICKSEL_Msk = 0xc        // Bit mask of SPICKSEL field.
	DFSDM_DFSDM_CHCFG3R1_SCDEN_Pos    = 0x5        // Position of SCDEN field.
	DFSDM_DFSDM_CHCFG3R1_SCDEN_Msk    = 0x20       // Bit mask of SCDEN field.
	DFSDM_DFSDM_CHCFG3R1_SCDEN        = 0x20       // Bit SCDEN.
	DFSDM_DFSDM_CHCFG3R1_CKABEN_Pos   = 0x6        // Position of CKABEN field.
	DFSDM_DFSDM_CHCFG3R1_CKABEN_Msk   = 0x40       // Bit mask of CKABEN field.
	DFSDM_DFSDM_CHCFG3R1_CKABEN       = 0x40       // Bit CKABEN.
	DFSDM_DFSDM_CHCFG3R1_CHEN_Pos     = 0x7        // Position of CHEN field.
	DFSDM_DFSDM_CHCFG3R1_CHEN_Msk     = 0x80       // Bit mask of CHEN field.
	DFSDM_DFSDM_CHCFG3R1_CHEN         = 0x80       // Bit CHEN.
	DFSDM_DFSDM_CHCFG3R1_CHINSEL_Pos  = 0x8        // Position of CHINSEL field.
	DFSDM_DFSDM_CHCFG3R1_CHINSEL_Msk  = 0x100      // Bit mask of CHINSEL field.
	DFSDM_DFSDM_CHCFG3R1_CHINSEL      = 0x100      // Bit CHINSEL.
	DFSDM_DFSDM_CHCFG3R1_DATMPX_Pos   = 0xc        // Position of DATMPX field.
	DFSDM_DFSDM_CHCFG3R1_DATMPX_Msk   = 0x3000     // Bit mask of DATMPX field.
	DFSDM_DFSDM_CHCFG3R1_DATPACK_Pos  = 0xe        // Position of DATPACK field.
	DFSDM_DFSDM_CHCFG3R1_DATPACK_Msk  = 0xc000     // Bit mask of DATPACK field.
	DFSDM_DFSDM_CHCFG3R1_CKOUTDIV_Pos = 0x10       // Position of CKOUTDIV field.
	DFSDM_DFSDM_CHCFG3R1_CKOUTDIV_Msk = 0xff0000   // Bit mask of CKOUTDIV field.
	DFSDM_DFSDM_CHCFG3R1_CKOUTSRC_Pos = 0x1e       // Position of CKOUTSRC field.
	DFSDM_DFSDM_CHCFG3R1_CKOUTSRC_Msk = 0x40000000 // Bit mask of CKOUTSRC field.
	DFSDM_DFSDM_CHCFG3R1_CKOUTSRC     = 0x40000000 // Bit CKOUTSRC.
	DFSDM_DFSDM_CHCFG3R1_DFSDMEN_Pos  = 0x1f       // Position of DFSDMEN field.
	DFSDM_DFSDM_CHCFG3R1_DFSDMEN_Msk  = 0x80000000 // Bit mask of DFSDMEN field.
	DFSDM_DFSDM_CHCFG3R1_DFSDMEN      = 0x80000000 // Bit DFSDMEN.

	// DFSDM_CHCFG4R1: DFSDM channel configuration 4 register           1
	DFSDM_DFSDM_CHCFG4R1_SITP_Pos     = 0x0        // Position of SITP field.
	DFSDM_DFSDM_CHCFG4R1_SITP_Msk     = 0x3        // Bit mask of SITP field.
	DFSDM_DFSDM_CHCFG4R1_SPICKSEL_Pos = 0x2        // Position of SPICKSEL field.
	DFSDM_DFSDM_CHCFG4R1_SPICKSEL_Msk = 0xc        // Bit mask of SPICKSEL field.
	DFSDM_DFSDM_CHCFG4R1_SCDEN_Pos    = 0x5        // Position of SCDEN field.
	DFSDM_DFSDM_CHCFG4R1_SCDEN_Msk    = 0x20       // Bit mask of SCDEN field.
	DFSDM_DFSDM_CHCFG4R1_SCDEN        = 0x20       // Bit SCDEN.
	DFSDM_DFSDM_CHCFG4R1_CKABEN_Pos   = 0x6        // Position of CKABEN field.
	DFSDM_DFSDM_CHCFG4R1_CKABEN_Msk   = 0x40       // Bit mask of CKABEN field.
	DFSDM_DFSDM_CHCFG4R1_CKABEN       = 0x40       // Bit CKABEN.
	DFSDM_DFSDM_CHCFG4R1_CHEN_Pos     = 0x7        // Position of CHEN field.
	DFSDM_DFSDM_CHCFG4R1_CHEN_Msk     = 0x80       // Bit mask of CHEN field.
	DFSDM_DFSDM_CHCFG4R1_CHEN         = 0x80       // Bit CHEN.
	DFSDM_DFSDM_CHCFG4R1_CHINSEL_Pos  = 0x8        // Position of CHINSEL field.
	DFSDM_DFSDM_CHCFG4R1_CHINSEL_Msk  = 0x100      // Bit mask of CHINSEL field.
	DFSDM_DFSDM_CHCFG4R1_CHINSEL      = 0x100      // Bit CHINSEL.
	DFSDM_DFSDM_CHCFG4R1_DATMPX_Pos   = 0xc        // Position of DATMPX field.
	DFSDM_DFSDM_CHCFG4R1_DATMPX_Msk   = 0x3000     // Bit mask of DATMPX field.
	DFSDM_DFSDM_CHCFG4R1_DATPACK_Pos  = 0xe        // Position of DATPACK field.
	DFSDM_DFSDM_CHCFG4R1_DATPACK_Msk  = 0xc000     // Bit mask of DATPACK field.
	DFSDM_DFSDM_CHCFG4R1_CKOUTDIV_Pos = 0x10       // Position of CKOUTDIV field.
	DFSDM_DFSDM_CHCFG4R1_CKOUTDIV_Msk = 0xff0000   // Bit mask of CKOUTDIV field.
	DFSDM_DFSDM_CHCFG4R1_CKOUTSRC_Pos = 0x1e       // Position of CKOUTSRC field.
	DFSDM_DFSDM_CHCFG4R1_CKOUTSRC_Msk = 0x40000000 // Bit mask of CKOUTSRC field.
	DFSDM_DFSDM_CHCFG4R1_CKOUTSRC     = 0x40000000 // Bit CKOUTSRC.
	DFSDM_DFSDM_CHCFG4R1_DFSDMEN_Pos  = 0x1f       // Position of DFSDMEN field.
	DFSDM_DFSDM_CHCFG4R1_DFSDMEN_Msk  = 0x80000000 // Bit mask of DFSDMEN field.
	DFSDM_DFSDM_CHCFG4R1_DFSDMEN      = 0x80000000 // Bit DFSDMEN.

	// DFSDM_CHCFG5R1: DFSDM channel configuration 5 register           1
	DFSDM_DFSDM_CHCFG5R1_SITP_Pos     = 0x0        // Position of SITP field.
	DFSDM_DFSDM_CHCFG5R1_SITP_Msk     = 0x3        // Bit mask of SITP field.
	DFSDM_DFSDM_CHCFG5R1_SPICKSEL_Pos = 0x2        // Position of SPICKSEL field.
	DFSDM_DFSDM_CHCFG5R1_SPICKSEL_Msk = 0xc        // Bit mask of SPICKSEL field.
	DFSDM_DFSDM_CHCFG5R1_SCDEN_Pos    = 0x5        // Position of SCDEN field.
	DFSDM_DFSDM_CHCFG5R1_SCDEN_Msk    = 0x20       // Bit mask of SCDEN field.
	DFSDM_DFSDM_CHCFG5R1_SCDEN        = 0x20       // Bit SCDEN.
	DFSDM_DFSDM_CHCFG5R1_CKABEN_Pos   = 0x6        // Position of CKABEN field.
	DFSDM_DFSDM_CHCFG5R1_CKABEN_Msk   = 0x40       // Bit mask of CKABEN field.
	DFSDM_DFSDM_CHCFG5R1_CKABEN       = 0x40       // Bit CKABEN.
	DFSDM_DFSDM_CHCFG5R1_CHEN_Pos     = 0x7        // Position of CHEN field.
	DFSDM_DFSDM_CHCFG5R1_CHEN_Msk     = 0x80       // Bit mask of CHEN field.
	DFSDM_DFSDM_CHCFG5R1_CHEN         = 0x80       // Bit CHEN.
	DFSDM_DFSDM_CHCFG5R1_CHINSEL_Pos  = 0x8        // Position of CHINSEL field.
	DFSDM_DFSDM_CHCFG5R1_CHINSEL_Msk  = 0x100      // Bit mask of CHINSEL field.
	DFSDM_DFSDM_CHCFG5R1_CHINSEL      = 0x100      // Bit CHINSEL.
	DFSDM_DFSDM_CHCFG5R1_DATMPX_Pos   = 0xc        // Position of DATMPX field.
	DFSDM_DFSDM_CHCFG5R1_DATMPX_Msk   = 0x3000     // Bit mask of DATMPX field.
	DFSDM_DFSDM_CHCFG5R1_DATPACK_Pos  = 0xe        // Position of DATPACK field.
	DFSDM_DFSDM_CHCFG5R1_DATPACK_Msk  = 0xc000     // Bit mask of DATPACK field.
	DFSDM_DFSDM_CHCFG5R1_CKOUTDIV_Pos = 0x10       // Position of CKOUTDIV field.
	DFSDM_DFSDM_CHCFG5R1_CKOUTDIV_Msk = 0xff0000   // Bit mask of CKOUTDIV field.
	DFSDM_DFSDM_CHCFG5R1_CKOUTSRC_Pos = 0x1e       // Position of CKOUTSRC field.
	DFSDM_DFSDM_CHCFG5R1_CKOUTSRC_Msk = 0x40000000 // Bit mask of CKOUTSRC field.
	DFSDM_DFSDM_CHCFG5R1_CKOUTSRC     = 0x40000000 // Bit CKOUTSRC.
	DFSDM_DFSDM_CHCFG5R1_DFSDMEN_Pos  = 0x1f       // Position of DFSDMEN field.
	DFSDM_DFSDM_CHCFG5R1_DFSDMEN_Msk  = 0x80000000 // Bit mask of DFSDMEN field.
	DFSDM_DFSDM_CHCFG5R1_DFSDMEN      = 0x80000000 // Bit DFSDMEN.

	// DFSDM_CHCFG6R1: DFSDM channel configuration 6 register           1
	DFSDM_DFSDM_CHCFG6R1_SITP_Pos     = 0x0        // Position of SITP field.
	DFSDM_DFSDM_CHCFG6R1_SITP_Msk     = 0x3        // Bit mask of SITP field.
	DFSDM_DFSDM_CHCFG6R1_SPICKSEL_Pos = 0x2        // Position of SPICKSEL field.
	DFSDM_DFSDM_CHCFG6R1_SPICKSEL_Msk = 0xc        // Bit mask of SPICKSEL field.
	DFSDM_DFSDM_CHCFG6R1_SCDEN_Pos    = 0x5        // Position of SCDEN field.
	DFSDM_DFSDM_CHCFG6R1_SCDEN_Msk    = 0x20       // Bit mask of SCDEN field.
	DFSDM_DFSDM_CHCFG6R1_SCDEN        = 0x20       // Bit SCDEN.
	DFSDM_DFSDM_CHCFG6R1_CKABEN_Pos   = 0x6        // Position of CKABEN field.
	DFSDM_DFSDM_CHCFG6R1_CKABEN_Msk   = 0x40       // Bit mask of CKABEN field.
	DFSDM_DFSDM_CHCFG6R1_CKABEN       = 0x40       // Bit CKABEN.
	DFSDM_DFSDM_CHCFG6R1_CHEN_Pos     = 0x7        // Position of CHEN field.
	DFSDM_DFSDM_CHCFG6R1_CHEN_Msk     = 0x80       // Bit mask of CHEN field.
	DFSDM_DFSDM_CHCFG6R1_CHEN         = 0x80       // Bit CHEN.
	DFSDM_DFSDM_CHCFG6R1_CHINSEL_Pos  = 0x8        // Position of CHINSEL field.
	DFSDM_DFSDM_CHCFG6R1_CHINSEL_Msk  = 0x100      // Bit mask of CHINSEL field.
	DFSDM_DFSDM_CHCFG6R1_CHINSEL      = 0x100      // Bit CHINSEL.
	DFSDM_DFSDM_CHCFG6R1_DATMPX_Pos   = 0xc        // Position of DATMPX field.
	DFSDM_DFSDM_CHCFG6R1_DATMPX_Msk   = 0x3000     // Bit mask of DATMPX field.
	DFSDM_DFSDM_CHCFG6R1_DATPACK_Pos  = 0xe        // Position of DATPACK field.
	DFSDM_DFSDM_CHCFG6R1_DATPACK_Msk  = 0xc000     // Bit mask of DATPACK field.
	DFSDM_DFSDM_CHCFG6R1_CKOUTDIV_Pos = 0x10       // Position of CKOUTDIV field.
	DFSDM_DFSDM_CHCFG6R1_CKOUTDIV_Msk = 0xff0000   // Bit mask of CKOUTDIV field.
	DFSDM_DFSDM_CHCFG6R1_CKOUTSRC_Pos = 0x1e       // Position of CKOUTSRC field.
	DFSDM_DFSDM_CHCFG6R1_CKOUTSRC_Msk = 0x40000000 // Bit mask of CKOUTSRC field.
	DFSDM_DFSDM_CHCFG6R1_CKOUTSRC     = 0x40000000 // Bit CKOUTSRC.
	DFSDM_DFSDM_CHCFG6R1_DFSDMEN_Pos  = 0x1f       // Position of DFSDMEN field.
	DFSDM_DFSDM_CHCFG6R1_DFSDMEN_Msk  = 0x80000000 // Bit mask of DFSDMEN field.
	DFSDM_DFSDM_CHCFG6R1_DFSDMEN      = 0x80000000 // Bit DFSDMEN.

	// DFSDM_CHCFG7R1: DFSDM channel configuration 7 register           1
	DFSDM_DFSDM_CHCFG7R1_SITP_Pos     = 0x0        // Position of SITP field.
	DFSDM_DFSDM_CHCFG7R1_SITP_Msk     = 0x3        // Bit mask of SITP field.
	DFSDM_DFSDM_CHCFG7R1_SPICKSEL_Pos = 0x2        // Position of SPICKSEL field.
	DFSDM_DFSDM_CHCFG7R1_SPICKSEL_Msk = 0xc        // Bit mask of SPICKSEL field.
	DFSDM_DFSDM_CHCFG7R1_SCDEN_Pos    = 0x5        // Position of SCDEN field.
	DFSDM_DFSDM_CHCFG7R1_SCDEN_Msk    = 0x20       // Bit mask of SCDEN field.
	DFSDM_DFSDM_CHCFG7R1_SCDEN        = 0x20       // Bit SCDEN.
	DFSDM_DFSDM_CHCFG7R1_CKABEN_Pos   = 0x6        // Position of CKABEN field.
	DFSDM_DFSDM_CHCFG7R1_CKABEN_Msk   = 0x40       // Bit mask of CKABEN field.
	DFSDM_DFSDM_CHCFG7R1_CKABEN       = 0x40       // Bit CKABEN.
	DFSDM_DFSDM_CHCFG7R1_CHEN_Pos     = 0x7        // Position of CHEN field.
	DFSDM_DFSDM_CHCFG7R1_CHEN_Msk     = 0x80       // Bit mask of CHEN field.
	DFSDM_DFSDM_CHCFG7R1_CHEN         = 0x80       // Bit CHEN.
	DFSDM_DFSDM_CHCFG7R1_CHINSEL_Pos  = 0x8        // Position of CHINSEL field.
	DFSDM_DFSDM_CHCFG7R1_CHINSEL_Msk  = 0x100      // Bit mask of CHINSEL field.
	DFSDM_DFSDM_CHCFG7R1_CHINSEL      = 0x100      // Bit CHINSEL.
	DFSDM_DFSDM_CHCFG7R1_DATMPX_Pos   = 0xc        // Position of DATMPX field.
	DFSDM_DFSDM_CHCFG7R1_DATMPX_Msk   = 0x3000     // Bit mask of DATMPX field.
	DFSDM_DFSDM_CHCFG7R1_DATPACK_Pos  = 0xe        // Position of DATPACK field.
	DFSDM_DFSDM_CHCFG7R1_DATPACK_Msk  = 0xc000     // Bit mask of DATPACK field.
	DFSDM_DFSDM_CHCFG7R1_CKOUTDIV_Pos = 0x10       // Position of CKOUTDIV field.
	DFSDM_DFSDM_CHCFG7R1_CKOUTDIV_Msk = 0xff0000   // Bit mask of CKOUTDIV field.
	DFSDM_DFSDM_CHCFG7R1_CKOUTSRC_Pos = 0x1e       // Position of CKOUTSRC field.
	DFSDM_DFSDM_CHCFG7R1_CKOUTSRC_Msk = 0x40000000 // Bit mask of CKOUTSRC field.
	DFSDM_DFSDM_CHCFG7R1_CKOUTSRC     = 0x40000000 // Bit CKOUTSRC.
	DFSDM_DFSDM_CHCFG7R1_DFSDMEN_Pos  = 0x1f       // Position of DFSDMEN field.
	DFSDM_DFSDM_CHCFG7R1_DFSDMEN_Msk  = 0x80000000 // Bit mask of DFSDMEN field.
	DFSDM_DFSDM_CHCFG7R1_DFSDMEN      = 0x80000000 // Bit DFSDMEN.

	// DFSDM_CHCFG0R2: DFSDM channel configuration 0 register           2
	DFSDM_DFSDM_CHCFG0R2_DTRBS_Pos  = 0x3        // Position of DTRBS field.
	DFSDM_DFSDM_CHCFG0R2_DTRBS_Msk  = 0xf8       // Bit mask of DTRBS field.
	DFSDM_DFSDM_CHCFG0R2_OFFSET_Pos = 0x8        // Position of OFFSET field.
	DFSDM_DFSDM_CHCFG0R2_OFFSET_Msk = 0xffffff00 // Bit mask of OFFSET field.

	// DFSDM_CHCFG1R2: DFSDM channel configuration 1 register           2
	DFSDM_DFSDM_CHCFG1R2_DTRBS_Pos  = 0x3        // Position of DTRBS field.
	DFSDM_DFSDM_CHCFG1R2_DTRBS_Msk  = 0xf8       // Bit mask of DTRBS field.
	DFSDM_DFSDM_CHCFG1R2_OFFSET_Pos = 0x8        // Position of OFFSET field.
	DFSDM_DFSDM_CHCFG1R2_OFFSET_Msk = 0xffffff00 // Bit mask of OFFSET field.

	// DFSDM_CHCFG2R2: DFSDM channel configuration 2 register           2
	DFSDM_DFSDM_CHCFG2R2_DTRBS_Pos  = 0x3        // Position of DTRBS field.
	DFSDM_DFSDM_CHCFG2R2_DTRBS_Msk  = 0xf8       // Bit mask of DTRBS field.
	DFSDM_DFSDM_CHCFG2R2_OFFSET_Pos = 0x8        // Position of OFFSET field.
	DFSDM_DFSDM_CHCFG2R2_OFFSET_Msk = 0xffffff00 // Bit mask of OFFSET field.

	// DFSDM_CHCFG3R2: DFSDM channel configuration 3 register           2
	DFSDM_DFSDM_CHCFG3R2_DTRBS_Pos  = 0x3        // Position of DTRBS field.
	DFSDM_DFSDM_CHCFG3R2_DTRBS_Msk  = 0xf8       // Bit mask of DTRBS field.
	DFSDM_DFSDM_CHCFG3R2_OFFSET_Pos = 0x8        // Position of OFFSET field.
	DFSDM_DFSDM_CHCFG3R2_OFFSET_Msk = 0xffffff00 // Bit mask of OFFSET field.

	// DFSDM_CHCFG4R2: DFSDM channel configuration 4 register           2
	DFSDM_DFSDM_CHCFG4R2_DTRBS_Pos  = 0x3        // Position of DTRBS field.
	DFSDM_DFSDM_CHCFG4R2_DTRBS_Msk  = 0xf8       // Bit mask of DTRBS field.
	DFSDM_DFSDM_CHCFG4R2_OFFSET_Pos = 0x8        // Position of OFFSET field.
	DFSDM_DFSDM_CHCFG4R2_OFFSET_Msk = 0xffffff00 // Bit mask of OFFSET field.

	// DFSDM_CHCFG5R2: DFSDM channel configuration 5 register           2
	DFSDM_DFSDM_CHCFG5R2_DTRBS_Pos  = 0x3        // Position of DTRBS field.
	DFSDM_DFSDM_CHCFG5R2_DTRBS_Msk  = 0xf8       // Bit mask of DTRBS field.
	DFSDM_DFSDM_CHCFG5R2_OFFSET_Pos = 0x8        // Position of OFFSET field.
	DFSDM_DFSDM_CHCFG5R2_OFFSET_Msk = 0xffffff00 // Bit mask of OFFSET field.

	// DFSDM_CHCFG6R2: DFSDM channel configuration 6 register           2
	DFSDM_DFSDM_CHCFG6R2_DTRBS_Pos  = 0x3        // Position of DTRBS field.
	DFSDM_DFSDM_CHCFG6R2_DTRBS_Msk  = 0xf8       // Bit mask of DTRBS field.
	DFSDM_DFSDM_CHCFG6R2_OFFSET_Pos = 0x8        // Position of OFFSET field.
	DFSDM_DFSDM_CHCFG6R2_OFFSET_Msk = 0xffffff00 // Bit mask of OFFSET field.

	// DFSDM_CHCFG7R2: DFSDM channel configuration 7 register           2
	DFSDM_DFSDM_CHCFG7R2_DTRBS_Pos  = 0x3        // Position of DTRBS field.
	DFSDM_DFSDM_CHCFG7R2_DTRBS_Msk  = 0xf8       // Bit mask of DTRBS field.
	DFSDM_DFSDM_CHCFG7R2_OFFSET_Pos = 0x8        // Position of OFFSET field.
	DFSDM_DFSDM_CHCFG7R2_OFFSET_Msk = 0xffffff00 // Bit mask of OFFSET field.

	// DFSDM_AWSCD0R: DFSDM analog watchdog and short-circuit           detector register
	DFSDM_DFSDM_AWSCD0R_SCDT_Pos   = 0x0      // Position of SCDT field.
	DFSDM_DFSDM_AWSCD0R_SCDT_Msk   = 0xff     // Bit mask of SCDT field.
	DFSDM_DFSDM_AWSCD0R_BKSCD_Pos  = 0xc      // Position of BKSCD field.
	DFSDM_DFSDM_AWSCD0R_BKSCD_Msk  = 0xf000   // Bit mask of BKSCD field.
	DFSDM_DFSDM_AWSCD0R_AWFOSR_Pos = 0x10     // Position of AWFOSR field.
	DFSDM_DFSDM_AWSCD0R_AWFOSR_Msk = 0x1f0000 // Bit mask of AWFOSR field.
	DFSDM_DFSDM_AWSCD0R_AWFORD_Pos = 0x16     // Position of AWFORD field.
	DFSDM_DFSDM_AWSCD0R_AWFORD_Msk = 0xc00000 // Bit mask of AWFORD field.

	// DFSDM_AWSCD1R: DFSDM analog watchdog and short-circuit           detector register
	DFSDM_DFSDM_AWSCD1R_SCDT_Pos   = 0x0      // Position of SCDT field.
	DFSDM_DFSDM_AWSCD1R_SCDT_Msk   = 0xff     // Bit mask of SCDT field.
	DFSDM_DFSDM_AWSCD1R_BKSCD_Pos  = 0xc      // Position of BKSCD field.
	DFSDM_DFSDM_AWSCD1R_BKSCD_Msk  = 0xf000   // Bit mask of BKSCD field.
	DFSDM_DFSDM_AWSCD1R_AWFOSR_Pos = 0x10     // Position of AWFOSR field.
	DFSDM_DFSDM_AWSCD1R_AWFOSR_Msk = 0x1f0000 // Bit mask of AWFOSR field.
	DFSDM_DFSDM_AWSCD1R_AWFORD_Pos = 0x16     // Position of AWFORD field.
	DFSDM_DFSDM_AWSCD1R_AWFORD_Msk = 0xc00000 // Bit mask of AWFORD field.

	// DFSDM_AWSCD2R: DFSDM analog watchdog and short-circuit           detector register
	DFSDM_DFSDM_AWSCD2R_SCDT_Pos   = 0x0      // Position of SCDT field.
	DFSDM_DFSDM_AWSCD2R_SCDT_Msk   = 0xff     // Bit mask of SCDT field.
	DFSDM_DFSDM_AWSCD2R_BKSCD_Pos  = 0xc      // Position of BKSCD field.
	DFSDM_DFSDM_AWSCD2R_BKSCD_Msk  = 0xf000   // Bit mask of BKSCD field.
	DFSDM_DFSDM_AWSCD2R_AWFOSR_Pos = 0x10     // Position of AWFOSR field.
	DFSDM_DFSDM_AWSCD2R_AWFOSR_Msk = 0x1f0000 // Bit mask of AWFOSR field.
	DFSDM_DFSDM_AWSCD2R_AWFORD_Pos = 0x16     // Position of AWFORD field.
	DFSDM_DFSDM_AWSCD2R_AWFORD_Msk = 0xc00000 // Bit mask of AWFORD field.

	// DFSDM_AWSCD3R: DFSDM analog watchdog and short-circuit           detector register
	DFSDM_DFSDM_AWSCD3R_SCDT_Pos   = 0x0      // Position of SCDT field.
	DFSDM_DFSDM_AWSCD3R_SCDT_Msk   = 0xff     // Bit mask of SCDT field.
	DFSDM_DFSDM_AWSCD3R_BKSCD_Pos  = 0xc      // Position of BKSCD field.
	DFSDM_DFSDM_AWSCD3R_BKSCD_Msk  = 0xf000   // Bit mask of BKSCD field.
	DFSDM_DFSDM_AWSCD3R_AWFOSR_Pos = 0x10     // Position of AWFOSR field.
	DFSDM_DFSDM_AWSCD3R_AWFOSR_Msk = 0x1f0000 // Bit mask of AWFOSR field.
	DFSDM_DFSDM_AWSCD3R_AWFORD_Pos = 0x16     // Position of AWFORD field.
	DFSDM_DFSDM_AWSCD3R_AWFORD_Msk = 0xc00000 // Bit mask of AWFORD field.

	// DFSDM_AWSCD4R: DFSDM analog watchdog and short-circuit           detector register
	DFSDM_DFSDM_AWSCD4R_SCDT_Pos   = 0x0      // Position of SCDT field.
	DFSDM_DFSDM_AWSCD4R_SCDT_Msk   = 0xff     // Bit mask of SCDT field.
	DFSDM_DFSDM_AWSCD4R_BKSCD_Pos  = 0xc      // Position of BKSCD field.
	DFSDM_DFSDM_AWSCD4R_BKSCD_Msk  = 0xf000   // Bit mask of BKSCD field.
	DFSDM_DFSDM_AWSCD4R_AWFOSR_Pos = 0x10     // Position of AWFOSR field.
	DFSDM_DFSDM_AWSCD4R_AWFOSR_Msk = 0x1f0000 // Bit mask of AWFOSR field.
	DFSDM_DFSDM_AWSCD4R_AWFORD_Pos = 0x16     // Position of AWFORD field.
	DFSDM_DFSDM_AWSCD4R_AWFORD_Msk = 0xc00000 // Bit mask of AWFORD field.

	// DFSDM_AWSCD5R: DFSDM analog watchdog and short-circuit           detector register
	DFSDM_DFSDM_AWSCD5R_SCDT_Pos   = 0x0      // Position of SCDT field.
	DFSDM_DFSDM_AWSCD5R_SCDT_Msk   = 0xff     // Bit mask of SCDT field.
	DFSDM_DFSDM_AWSCD5R_BKSCD_Pos  = 0xc      // Position of BKSCD field.
	DFSDM_DFSDM_AWSCD5R_BKSCD_Msk  = 0xf000   // Bit mask of BKSCD field.
	DFSDM_DFSDM_AWSCD5R_AWFOSR_Pos = 0x10     // Position of AWFOSR field.
	DFSDM_DFSDM_AWSCD5R_AWFOSR_Msk = 0x1f0000 // Bit mask of AWFOSR field.
	DFSDM_DFSDM_AWSCD5R_AWFORD_Pos = 0x16     // Position of AWFORD field.
	DFSDM_DFSDM_AWSCD5R_AWFORD_Msk = 0xc00000 // Bit mask of AWFORD field.

	// DFSDM_AWSCD6R: DFSDM analog watchdog and short-circuit           detector register
	DFSDM_DFSDM_AWSCD6R_SCDT_Pos   = 0x0      // Position of SCDT field.
	DFSDM_DFSDM_AWSCD6R_SCDT_Msk   = 0xff     // Bit mask of SCDT field.
	DFSDM_DFSDM_AWSCD6R_BKSCD_Pos  = 0xc      // Position of BKSCD field.
	DFSDM_DFSDM_AWSCD6R_BKSCD_Msk  = 0xf000   // Bit mask of BKSCD field.
	DFSDM_DFSDM_AWSCD6R_AWFOSR_Pos = 0x10     // Position of AWFOSR field.
	DFSDM_DFSDM_AWSCD6R_AWFOSR_Msk = 0x1f0000 // Bit mask of AWFOSR field.
	DFSDM_DFSDM_AWSCD6R_AWFORD_Pos = 0x16     // Position of AWFORD field.
	DFSDM_DFSDM_AWSCD6R_AWFORD_Msk = 0xc00000 // Bit mask of AWFORD field.

	// DFSDM_AWSCD7R: DFSDM analog watchdog and short-circuit           detector register
	DFSDM_DFSDM_AWSCD7R_SCDT_Pos   = 0x0      // Position of SCDT field.
	DFSDM_DFSDM_AWSCD7R_SCDT_Msk   = 0xff     // Bit mask of SCDT field.
	DFSDM_DFSDM_AWSCD7R_BKSCD_Pos  = 0xc      // Position of BKSCD field.
	DFSDM_DFSDM_AWSCD7R_BKSCD_Msk  = 0xf000   // Bit mask of BKSCD field.
	DFSDM_DFSDM_AWSCD7R_AWFOSR_Pos = 0x10     // Position of AWFOSR field.
	DFSDM_DFSDM_AWSCD7R_AWFOSR_Msk = 0x1f0000 // Bit mask of AWFOSR field.
	DFSDM_DFSDM_AWSCD7R_AWFORD_Pos = 0x16     // Position of AWFORD field.
	DFSDM_DFSDM_AWSCD7R_AWFORD_Msk = 0xc00000 // Bit mask of AWFORD field.

	// DFSDM_CHWDAT0R: DFSDM channel watchdog filter data           register
	DFSDM_DFSDM_CHWDAT0R_WDATA_Pos = 0x0    // Position of WDATA field.
	DFSDM_DFSDM_CHWDAT0R_WDATA_Msk = 0xffff // Bit mask of WDATA field.

	// DFSDM_CHWDAT1R: DFSDM channel watchdog filter data           register
	DFSDM_DFSDM_CHWDAT1R_WDATA_Pos = 0x0    // Position of WDATA field.
	DFSDM_DFSDM_CHWDAT1R_WDATA_Msk = 0xffff // Bit mask of WDATA field.

	// DFSDM_CHWDAT2R: DFSDM channel watchdog filter data           register
	DFSDM_DFSDM_CHWDAT2R_WDATA_Pos = 0x0    // Position of WDATA field.
	DFSDM_DFSDM_CHWDAT2R_WDATA_Msk = 0xffff // Bit mask of WDATA field.

	// DFSDM_CHWDAT3R: DFSDM channel watchdog filter data           register
	DFSDM_DFSDM_CHWDAT3R_WDATA_Pos = 0x0    // Position of WDATA field.
	DFSDM_DFSDM_CHWDAT3R_WDATA_Msk = 0xffff // Bit mask of WDATA field.

	// DFSDM_CHWDAT4R: DFSDM channel watchdog filter data           register
	DFSDM_DFSDM_CHWDAT4R_WDATA_Pos = 0x0    // Position of WDATA field.
	DFSDM_DFSDM_CHWDAT4R_WDATA_Msk = 0xffff // Bit mask of WDATA field.

	// DFSDM_CHWDAT5R: DFSDM channel watchdog filter data           register
	DFSDM_DFSDM_CHWDAT5R_WDATA_Pos = 0x0    // Position of WDATA field.
	DFSDM_DFSDM_CHWDAT5R_WDATA_Msk = 0xffff // Bit mask of WDATA field.

	// DFSDM_CHWDAT6R: DFSDM channel watchdog filter data           register
	DFSDM_DFSDM_CHWDAT6R_WDATA_Pos = 0x0    // Position of WDATA field.
	DFSDM_DFSDM_CHWDAT6R_WDATA_Msk = 0xffff // Bit mask of WDATA field.

	// DFSDM_CHWDAT7R: DFSDM channel watchdog filter data           register
	DFSDM_DFSDM_CHWDAT7R_WDATA_Pos = 0x0    // Position of WDATA field.
	DFSDM_DFSDM_CHWDAT7R_WDATA_Msk = 0xffff // Bit mask of WDATA field.

	// DFSDM_CHDATIN0R: DFSDM channel data input           register
	DFSDM_DFSDM_CHDATIN0R_INDAT0_Pos = 0x0        // Position of INDAT0 field.
	DFSDM_DFSDM_CHDATIN0R_INDAT0_Msk = 0xffff     // Bit mask of INDAT0 field.
	DFSDM_DFSDM_CHDATIN0R_INDAT1_Pos = 0x10       // Position of INDAT1 field.
	DFSDM_DFSDM_CHDATIN0R_INDAT1_Msk = 0xffff0000 // Bit mask of INDAT1 field.

	// DFSDM_CHDATIN1R: DFSDM channel data input           register
	DFSDM_DFSDM_CHDATIN1R_INDAT0_Pos = 0x0        // Position of INDAT0 field.
	DFSDM_DFSDM_CHDATIN1R_INDAT0_Msk = 0xffff     // Bit mask of INDAT0 field.
	DFSDM_DFSDM_CHDATIN1R_INDAT1_Pos = 0x10       // Position of INDAT1 field.
	DFSDM_DFSDM_CHDATIN1R_INDAT1_Msk = 0xffff0000 // Bit mask of INDAT1 field.

	// DFSDM_CHDATIN2R: DFSDM channel data input           register
	DFSDM_DFSDM_CHDATIN2R_INDAT0_Pos = 0x0        // Position of INDAT0 field.
	DFSDM_DFSDM_CHDATIN2R_INDAT0_Msk = 0xffff     // Bit mask of INDAT0 field.
	DFSDM_DFSDM_CHDATIN2R_INDAT1_Pos = 0x10       // Position of INDAT1 field.
	DFSDM_DFSDM_CHDATIN2R_INDAT1_Msk = 0xffff0000 // Bit mask of INDAT1 field.

	// DFSDM_CHDATIN3R: DFSDM channel data input           register
	DFSDM_DFSDM_CHDATIN3R_INDAT0_Pos = 0x0        // Position of INDAT0 field.
	DFSDM_DFSDM_CHDATIN3R_INDAT0_Msk = 0xffff     // Bit mask of INDAT0 field.
	DFSDM_DFSDM_CHDATIN3R_INDAT1_Pos = 0x10       // Position of INDAT1 field.
	DFSDM_DFSDM_CHDATIN3R_INDAT1_Msk = 0xffff0000 // Bit mask of INDAT1 field.

	// DFSDM_CHDATIN4R: DFSDM channel data input           register
	DFSDM_DFSDM_CHDATIN4R_INDAT0_Pos = 0x0        // Position of INDAT0 field.
	DFSDM_DFSDM_CHDATIN4R_INDAT0_Msk = 0xffff     // Bit mask of INDAT0 field.
	DFSDM_DFSDM_CHDATIN4R_INDAT1_Pos = 0x10       // Position of INDAT1 field.
	DFSDM_DFSDM_CHDATIN4R_INDAT1_Msk = 0xffff0000 // Bit mask of INDAT1 field.

	// DFSDM_CHDATIN5R: DFSDM channel data input           register
	DFSDM_DFSDM_CHDATIN5R_INDAT0_Pos = 0x0        // Position of INDAT0 field.
	DFSDM_DFSDM_CHDATIN5R_INDAT0_Msk = 0xffff     // Bit mask of INDAT0 field.
	DFSDM_DFSDM_CHDATIN5R_INDAT1_Pos = 0x10       // Position of INDAT1 field.
	DFSDM_DFSDM_CHDATIN5R_INDAT1_Msk = 0xffff0000 // Bit mask of INDAT1 field.

	// DFSDM_CHDATIN6R: DFSDM channel data input           register
	DFSDM_DFSDM_CHDATIN6R_INDAT0_Pos = 0x0        // Position of INDAT0 field.
	DFSDM_DFSDM_CHDATIN6R_INDAT0_Msk = 0xffff     // Bit mask of INDAT0 field.
	DFSDM_DFSDM_CHDATIN6R_INDAT1_Pos = 0x10       // Position of INDAT1 field.
	DFSDM_DFSDM_CHDATIN6R_INDAT1_Msk = 0xffff0000 // Bit mask of INDAT1 field.

	// DFSDM_CHDATIN7R: DFSDM channel data input           register
	DFSDM_DFSDM_CHDATIN7R_INDAT0_Pos = 0x0        // Position of INDAT0 field.
	DFSDM_DFSDM_CHDATIN7R_INDAT0_Msk = 0xffff     // Bit mask of INDAT0 field.
	DFSDM_DFSDM_CHDATIN7R_INDAT1_Pos = 0x10       // Position of INDAT1 field.
	DFSDM_DFSDM_CHDATIN7R_INDAT1_Msk = 0xffff0000 // Bit mask of INDAT1 field.

	// DFSDM0_CR1: DFSDM control register 1
	DFSDM_DFSDM0_CR1_DFEN_Pos     = 0x0        // Position of DFEN field.
	DFSDM_DFSDM0_CR1_DFEN_Msk     = 0x1        // Bit mask of DFEN field.
	DFSDM_DFSDM0_CR1_DFEN         = 0x1        // Bit DFEN.
	DFSDM_DFSDM0_CR1_JSWSTART_Pos = 0x1        // Position of JSWSTART field.
	DFSDM_DFSDM0_CR1_JSWSTART_Msk = 0x2        // Bit mask of JSWSTART field.
	DFSDM_DFSDM0_CR1_JSWSTART     = 0x2        // Bit JSWSTART.
	DFSDM_DFSDM0_CR1_JSYNC_Pos    = 0x3        // Position of JSYNC field.
	DFSDM_DFSDM0_CR1_JSYNC_Msk    = 0x8        // Bit mask of JSYNC field.
	DFSDM_DFSDM0_CR1_JSYNC        = 0x8        // Bit JSYNC.
	DFSDM_DFSDM0_CR1_JSCAN_Pos    = 0x4        // Position of JSCAN field.
	DFSDM_DFSDM0_CR1_JSCAN_Msk    = 0x10       // Bit mask of JSCAN field.
	DFSDM_DFSDM0_CR1_JSCAN        = 0x10       // Bit JSCAN.
	DFSDM_DFSDM0_CR1_JDMAEN_Pos   = 0x5        // Position of JDMAEN field.
	DFSDM_DFSDM0_CR1_JDMAEN_Msk   = 0x20       // Bit mask of JDMAEN field.
	DFSDM_DFSDM0_CR1_JDMAEN       = 0x20       // Bit JDMAEN.
	DFSDM_DFSDM0_CR1_JEXTSEL_Pos  = 0x8        // Position of JEXTSEL field.
	DFSDM_DFSDM0_CR1_JEXTSEL_Msk  = 0x1f00     // Bit mask of JEXTSEL field.
	DFSDM_DFSDM0_CR1_JEXTEN_Pos   = 0xd        // Position of JEXTEN field.
	DFSDM_DFSDM0_CR1_JEXTEN_Msk   = 0x6000     // Bit mask of JEXTEN field.
	DFSDM_DFSDM0_CR1_RSWSTART_Pos = 0x11       // Position of RSWSTART field.
	DFSDM_DFSDM0_CR1_RSWSTART_Msk = 0x20000    // Bit mask of RSWSTART field.
	DFSDM_DFSDM0_CR1_RSWSTART     = 0x20000    // Bit RSWSTART.
	DFSDM_DFSDM0_CR1_RCONT_Pos    = 0x12       // Position of RCONT field.
	DFSDM_DFSDM0_CR1_RCONT_Msk    = 0x40000    // Bit mask of RCONT field.
	DFSDM_DFSDM0_CR1_RCONT        = 0x40000    // Bit RCONT.
	DFSDM_DFSDM0_CR1_RSYNC_Pos    = 0x13       // Position of RSYNC field.
	DFSDM_DFSDM0_CR1_RSYNC_Msk    = 0x80000    // Bit mask of RSYNC field.
	DFSDM_DFSDM0_CR1_RSYNC        = 0x80000    // Bit RSYNC.
	DFSDM_DFSDM0_CR1_RDMAEN_Pos   = 0x15       // Position of RDMAEN field.
	DFSDM_DFSDM0_CR1_RDMAEN_Msk   = 0x200000   // Bit mask of RDMAEN field.
	DFSDM_DFSDM0_CR1_RDMAEN       = 0x200000   // Bit RDMAEN.
	DFSDM_DFSDM0_CR1_RCH_Pos      = 0x18       // Position of RCH field.
	DFSDM_DFSDM0_CR1_RCH_Msk      = 0x7000000  // Bit mask of RCH field.
	DFSDM_DFSDM0_CR1_FAST_Pos     = 0x1d       // Position of FAST field.
	DFSDM_DFSDM0_CR1_FAST_Msk     = 0x20000000 // Bit mask of FAST field.
	DFSDM_DFSDM0_CR1_FAST         = 0x20000000 // Bit FAST.
	DFSDM_DFSDM0_CR1_AWFSEL_Pos   = 0x1e       // Position of AWFSEL field.
	DFSDM_DFSDM0_CR1_AWFSEL_Msk   = 0x40000000 // Bit mask of AWFSEL field.
	DFSDM_DFSDM0_CR1_AWFSEL       = 0x40000000 // Bit AWFSEL.

	// DFSDM1_CR1: DFSDM control register 1
	DFSDM_DFSDM1_CR1_DFEN_Pos     = 0x0        // Position of DFEN field.
	DFSDM_DFSDM1_CR1_DFEN_Msk     = 0x1        // Bit mask of DFEN field.
	DFSDM_DFSDM1_CR1_DFEN         = 0x1        // Bit DFEN.
	DFSDM_DFSDM1_CR1_JSWSTART_Pos = 0x1        // Position of JSWSTART field.
	DFSDM_DFSDM1_CR1_JSWSTART_Msk = 0x2        // Bit mask of JSWSTART field.
	DFSDM_DFSDM1_CR1_JSWSTART     = 0x2        // Bit JSWSTART.
	DFSDM_DFSDM1_CR1_JSYNC_Pos    = 0x3        // Position of JSYNC field.
	DFSDM_DFSDM1_CR1_JSYNC_Msk    = 0x8        // Bit mask of JSYNC field.
	DFSDM_DFSDM1_CR1_JSYNC        = 0x8        // Bit JSYNC.
	DFSDM_DFSDM1_CR1_JSCAN_Pos    = 0x4        // Position of JSCAN field.
	DFSDM_DFSDM1_CR1_JSCAN_Msk    = 0x10       // Bit mask of JSCAN field.
	DFSDM_DFSDM1_CR1_JSCAN        = 0x10       // Bit JSCAN.
	DFSDM_DFSDM1_CR1_JDMAEN_Pos   = 0x5        // Position of JDMAEN field.
	DFSDM_DFSDM1_CR1_JDMAEN_Msk   = 0x20       // Bit mask of JDMAEN field.
	DFSDM_DFSDM1_CR1_JDMAEN       = 0x20       // Bit JDMAEN.
	DFSDM_DFSDM1_CR1_JEXTSEL_Pos  = 0x8        // Position of JEXTSEL field.
	DFSDM_DFSDM1_CR1_JEXTSEL_Msk  = 0x1f00     // Bit mask of JEXTSEL field.
	DFSDM_DFSDM1_CR1_JEXTEN_Pos   = 0xd        // Position of JEXTEN field.
	DFSDM_DFSDM1_CR1_JEXTEN_Msk   = 0x6000     // Bit mask of JEXTEN field.
	DFSDM_DFSDM1_CR1_RSWSTART_Pos = 0x11       // Position of RSWSTART field.
	DFSDM_DFSDM1_CR1_RSWSTART_Msk = 0x20000    // Bit mask of RSWSTART field.
	DFSDM_DFSDM1_CR1_RSWSTART     = 0x20000    // Bit RSWSTART.
	DFSDM_DFSDM1_CR1_RCONT_Pos    = 0x12       // Position of RCONT field.
	DFSDM_DFSDM1_CR1_RCONT_Msk    = 0x40000    // Bit mask of RCONT field.
	DFSDM_DFSDM1_CR1_RCONT        = 0x40000    // Bit RCONT.
	DFSDM_DFSDM1_CR1_RSYNC_Pos    = 0x13       // Position of RSYNC field.
	DFSDM_DFSDM1_CR1_RSYNC_Msk    = 0x80000    // Bit mask of RSYNC field.
	DFSDM_DFSDM1_CR1_RSYNC        = 0x80000    // Bit RSYNC.
	DFSDM_DFSDM1_CR1_RDMAEN_Pos   = 0x15       // Position of RDMAEN field.
	DFSDM_DFSDM1_CR1_RDMAEN_Msk   = 0x200000   // Bit mask of RDMAEN field.
	DFSDM_DFSDM1_CR1_RDMAEN       = 0x200000   // Bit RDMAEN.
	DFSDM_DFSDM1_CR1_RCH_Pos      = 0x18       // Position of RCH field.
	DFSDM_DFSDM1_CR1_RCH_Msk      = 0x7000000  // Bit mask of RCH field.
	DFSDM_DFSDM1_CR1_FAST_Pos     = 0x1d       // Position of FAST field.
	DFSDM_DFSDM1_CR1_FAST_Msk     = 0x20000000 // Bit mask of FAST field.
	DFSDM_DFSDM1_CR1_FAST         = 0x20000000 // Bit FAST.
	DFSDM_DFSDM1_CR1_AWFSEL_Pos   = 0x1e       // Position of AWFSEL field.
	DFSDM_DFSDM1_CR1_AWFSEL_Msk   = 0x40000000 // Bit mask of AWFSEL field.
	DFSDM_DFSDM1_CR1_AWFSEL       = 0x40000000 // Bit AWFSEL.

	// DFSDM2_CR1: DFSDM control register 1
	DFSDM_DFSDM2_CR1_DFEN_Pos     = 0x0        // Position of DFEN field.
	DFSDM_DFSDM2_CR1_DFEN_Msk     = 0x1        // Bit mask of DFEN field.
	DFSDM_DFSDM2_CR1_DFEN         = 0x1        // Bit DFEN.
	DFSDM_DFSDM2_CR1_JSWSTART_Pos = 0x1        // Position of JSWSTART field.
	DFSDM_DFSDM2_CR1_JSWSTART_Msk = 0x2        // Bit mask of JSWSTART field.
	DFSDM_DFSDM2_CR1_JSWSTART     = 0x2        // Bit JSWSTART.
	DFSDM_DFSDM2_CR1_JSYNC_Pos    = 0x3        // Position of JSYNC field.
	DFSDM_DFSDM2_CR1_JSYNC_Msk    = 0x8        // Bit mask of JSYNC field.
	DFSDM_DFSDM2_CR1_JSYNC        = 0x8        // Bit JSYNC.
	DFSDM_DFSDM2_CR1_JSCAN_Pos    = 0x4        // Position of JSCAN field.
	DFSDM_DFSDM2_CR1_JSCAN_Msk    = 0x10       // Bit mask of JSCAN field.
	DFSDM_DFSDM2_CR1_JSCAN        = 0x10       // Bit JSCAN.
	DFSDM_DFSDM2_CR1_JDMAEN_Pos   = 0x5        // Position of JDMAEN field.
	DFSDM_DFSDM2_CR1_JDMAEN_Msk   = 0x20       // Bit mask of JDMAEN field.
	DFSDM_DFSDM2_CR1_JDMAEN       = 0x20       // Bit JDMAEN.
	DFSDM_DFSDM2_CR1_JEXTSEL_Pos  = 0x8        // Position of JEXTSEL field.
	DFSDM_DFSDM2_CR1_JEXTSEL_Msk  = 0x1f00     // Bit mask of JEXTSEL field.
	DFSDM_DFSDM2_CR1_JEXTEN_Pos   = 0xd        // Position of JEXTEN field.
	DFSDM_DFSDM2_CR1_JEXTEN_Msk   = 0x6000     // Bit mask of JEXTEN field.
	DFSDM_DFSDM2_CR1_RSWSTART_Pos = 0x11       // Position of RSWSTART field.
	DFSDM_DFSDM2_CR1_RSWSTART_Msk = 0x20000    // Bit mask of RSWSTART field.
	DFSDM_DFSDM2_CR1_RSWSTART     = 0x20000    // Bit RSWSTART.
	DFSDM_DFSDM2_CR1_RCONT_Pos    = 0x12       // Position of RCONT field.
	DFSDM_DFSDM2_CR1_RCONT_Msk    = 0x40000    // Bit mask of RCONT field.
	DFSDM_DFSDM2_CR1_RCONT        = 0x40000    // Bit RCONT.
	DFSDM_DFSDM2_CR1_RSYNC_Pos    = 0x13       // Position of RSYNC field.
	DFSDM_DFSDM2_CR1_RSYNC_Msk    = 0x80000    // Bit mask of RSYNC field.
	DFSDM_DFSDM2_CR1_RSYNC        = 0x80000    // Bit RSYNC.
	DFSDM_DFSDM2_CR1_RDMAEN_Pos   = 0x15       // Position of RDMAEN field.
	DFSDM_DFSDM2_CR1_RDMAEN_Msk   = 0x200000   // Bit mask of RDMAEN field.
	DFSDM_DFSDM2_CR1_RDMAEN       = 0x200000   // Bit RDMAEN.
	DFSDM_DFSDM2_CR1_RCH_Pos      = 0x18       // Position of RCH field.
	DFSDM_DFSDM2_CR1_RCH_Msk      = 0x7000000  // Bit mask of RCH field.
	DFSDM_DFSDM2_CR1_FAST_Pos     = 0x1d       // Position of FAST field.
	DFSDM_DFSDM2_CR1_FAST_Msk     = 0x20000000 // Bit mask of FAST field.
	DFSDM_DFSDM2_CR1_FAST         = 0x20000000 // Bit FAST.
	DFSDM_DFSDM2_CR1_AWFSEL_Pos   = 0x1e       // Position of AWFSEL field.
	DFSDM_DFSDM2_CR1_AWFSEL_Msk   = 0x40000000 // Bit mask of AWFSEL field.
	DFSDM_DFSDM2_CR1_AWFSEL       = 0x40000000 // Bit AWFSEL.

	// DFSDM3_CR1: DFSDM control register 1
	DFSDM_DFSDM3_CR1_DFEN_Pos     = 0x0        // Position of DFEN field.
	DFSDM_DFSDM3_CR1_DFEN_Msk     = 0x1        // Bit mask of DFEN field.
	DFSDM_DFSDM3_CR1_DFEN         = 0x1        // Bit DFEN.
	DFSDM_DFSDM3_CR1_JSWSTART_Pos = 0x1        // Position of JSWSTART field.
	DFSDM_DFSDM3_CR1_JSWSTART_Msk = 0x2        // Bit mask of JSWSTART field.
	DFSDM_DFSDM3_CR1_JSWSTART     = 0x2        // Bit JSWSTART.
	DFSDM_DFSDM3_CR1_JSYNC_Pos    = 0x3        // Position of JSYNC field.
	DFSDM_DFSDM3_CR1_JSYNC_Msk    = 0x8        // Bit mask of JSYNC field.
	DFSDM_DFSDM3_CR1_JSYNC        = 0x8        // Bit JSYNC.
	DFSDM_DFSDM3_CR1_JSCAN_Pos    = 0x4        // Position of JSCAN field.
	DFSDM_DFSDM3_CR1_JSCAN_Msk    = 0x10       // Bit mask of JSCAN field.
	DFSDM_DFSDM3_CR1_JSCAN        = 0x10       // Bit JSCAN.
	DFSDM_DFSDM3_CR1_JDMAEN_Pos   = 0x5        // Position of JDMAEN field.
	DFSDM_DFSDM3_CR1_JDMAEN_Msk   = 0x20       // Bit mask of JDMAEN field.
	DFSDM_DFSDM3_CR1_JDMAEN       = 0x20       // Bit JDMAEN.
	DFSDM_DFSDM3_CR1_JEXTSEL_Pos  = 0x8        // Position of JEXTSEL field.
	DFSDM_DFSDM3_CR1_JEXTSEL_Msk  = 0x1f00     // Bit mask of JEXTSEL field.
	DFSDM_DFSDM3_CR1_JEXTEN_Pos   = 0xd        // Position of JEXTEN field.
	DFSDM_DFSDM3_CR1_JEXTEN_Msk   = 0x6000     // Bit mask of JEXTEN field.
	DFSDM_DFSDM3_CR1_RSWSTART_Pos = 0x11       // Position of RSWSTART field.
	DFSDM_DFSDM3_CR1_RSWSTART_Msk = 0x20000    // Bit mask of RSWSTART field.
	DFSDM_DFSDM3_CR1_RSWSTART     = 0x20000    // Bit RSWSTART.
	DFSDM_DFSDM3_CR1_RCONT_Pos    = 0x12       // Position of RCONT field.
	DFSDM_DFSDM3_CR1_RCONT_Msk    = 0x40000    // Bit mask of RCONT field.
	DFSDM_DFSDM3_CR1_RCONT        = 0x40000    // Bit RCONT.
	DFSDM_DFSDM3_CR1_RSYNC_Pos    = 0x13       // Position of RSYNC field.
	DFSDM_DFSDM3_CR1_RSYNC_Msk    = 0x80000    // Bit mask of RSYNC field.
	DFSDM_DFSDM3_CR1_RSYNC        = 0x80000    // Bit RSYNC.
	DFSDM_DFSDM3_CR1_RDMAEN_Pos   = 0x15       // Position of RDMAEN field.
	DFSDM_DFSDM3_CR1_RDMAEN_Msk   = 0x200000   // Bit mask of RDMAEN field.
	DFSDM_DFSDM3_CR1_RDMAEN       = 0x200000   // Bit RDMAEN.
	DFSDM_DFSDM3_CR1_RCH_Pos      = 0x18       // Position of RCH field.
	DFSDM_DFSDM3_CR1_RCH_Msk      = 0x7000000  // Bit mask of RCH field.
	DFSDM_DFSDM3_CR1_FAST_Pos     = 0x1d       // Position of FAST field.
	DFSDM_DFSDM3_CR1_FAST_Msk     = 0x20000000 // Bit mask of FAST field.
	DFSDM_DFSDM3_CR1_FAST         = 0x20000000 // Bit FAST.
	DFSDM_DFSDM3_CR1_AWFSEL_Pos   = 0x1e       // Position of AWFSEL field.
	DFSDM_DFSDM3_CR1_AWFSEL_Msk   = 0x40000000 // Bit mask of AWFSEL field.
	DFSDM_DFSDM3_CR1_AWFSEL       = 0x40000000 // Bit AWFSEL.

	// DFSDM0_CR2: DFSDM control register 2
	DFSDM_DFSDM0_CR2_JEOCIE_Pos = 0x0      // Position of JEOCIE field.
	DFSDM_DFSDM0_CR2_JEOCIE_Msk = 0x1      // Bit mask of JEOCIE field.
	DFSDM_DFSDM0_CR2_JEOCIE     = 0x1      // Bit JEOCIE.
	DFSDM_DFSDM0_CR2_REOCIE_Pos = 0x1      // Position of REOCIE field.
	DFSDM_DFSDM0_CR2_REOCIE_Msk = 0x2      // Bit mask of REOCIE field.
	DFSDM_DFSDM0_CR2_REOCIE     = 0x2      // Bit REOCIE.
	DFSDM_DFSDM0_CR2_JOVRIE_Pos = 0x2      // Position of JOVRIE field.
	DFSDM_DFSDM0_CR2_JOVRIE_Msk = 0x4      // Bit mask of JOVRIE field.
	DFSDM_DFSDM0_CR2_JOVRIE     = 0x4      // Bit JOVRIE.
	DFSDM_DFSDM0_CR2_ROVRIE_Pos = 0x3      // Position of ROVRIE field.
	DFSDM_DFSDM0_CR2_ROVRIE_Msk = 0x8      // Bit mask of ROVRIE field.
	DFSDM_DFSDM0_CR2_ROVRIE     = 0x8      // Bit ROVRIE.
	DFSDM_DFSDM0_CR2_AWDIE_Pos  = 0x4      // Position of AWDIE field.
	DFSDM_DFSDM0_CR2_AWDIE_Msk  = 0x10     // Bit mask of AWDIE field.
	DFSDM_DFSDM0_CR2_AWDIE      = 0x10     // Bit AWDIE.
	DFSDM_DFSDM0_CR2_SCDIE_Pos  = 0x5      // Position of SCDIE field.
	DFSDM_DFSDM0_CR2_SCDIE_Msk  = 0x20     // Bit mask of SCDIE field.
	DFSDM_DFSDM0_CR2_SCDIE      = 0x20     // Bit SCDIE.
	DFSDM_DFSDM0_CR2_CKABIE_Pos = 0x6      // Position of CKABIE field.
	DFSDM_DFSDM0_CR2_CKABIE_Msk = 0x40     // Bit mask of CKABIE field.
	DFSDM_DFSDM0_CR2_CKABIE     = 0x40     // Bit CKABIE.
	DFSDM_DFSDM0_CR2_EXCH_Pos   = 0x8      // Position of EXCH field.
	DFSDM_DFSDM0_CR2_EXCH_Msk   = 0xff00   // Bit mask of EXCH field.
	DFSDM_DFSDM0_CR2_AWDCH_Pos  = 0x10     // Position of AWDCH field.
	DFSDM_DFSDM0_CR2_AWDCH_Msk  = 0xff0000 // Bit mask of AWDCH field.

	// DFSDM1_CR2: DFSDM control register 2
	DFSDM_DFSDM1_CR2_JEOCIE_Pos = 0x0      // Position of JEOCIE field.
	DFSDM_DFSDM1_CR2_JEOCIE_Msk = 0x1      // Bit mask of JEOCIE field.
	DFSDM_DFSDM1_CR2_JEOCIE     = 0x1      // Bit JEOCIE.
	DFSDM_DFSDM1_CR2_REOCIE_Pos = 0x1      // Position of REOCIE field.
	DFSDM_DFSDM1_CR2_REOCIE_Msk = 0x2      // Bit mask of REOCIE field.
	DFSDM_DFSDM1_CR2_REOCIE     = 0x2      // Bit REOCIE.
	DFSDM_DFSDM1_CR2_JOVRIE_Pos = 0x2      // Position of JOVRIE field.
	DFSDM_DFSDM1_CR2_JOVRIE_Msk = 0x4      // Bit mask of JOVRIE field.
	DFSDM_DFSDM1_CR2_JOVRIE     = 0x4      // Bit JOVRIE.
	DFSDM_DFSDM1_CR2_ROVRIE_Pos = 0x3      // Position of ROVRIE field.
	DFSDM_DFSDM1_CR2_ROVRIE_Msk = 0x8      // Bit mask of ROVRIE field.
	DFSDM_DFSDM1_CR2_ROVRIE     = 0x8      // Bit ROVRIE.
	DFSDM_DFSDM1_CR2_AWDIE_Pos  = 0x4      // Position of AWDIE field.
	DFSDM_DFSDM1_CR2_AWDIE_Msk  = 0x10     // Bit mask of AWDIE field.
	DFSDM_DFSDM1_CR2_AWDIE      = 0x10     // Bit AWDIE.
	DFSDM_DFSDM1_CR2_SCDIE_Pos  = 0x5      // Position of SCDIE field.
	DFSDM_DFSDM1_CR2_SCDIE_Msk  = 0x20     // Bit mask of SCDIE field.
	DFSDM_DFSDM1_CR2_SCDIE      = 0x20     // Bit SCDIE.
	DFSDM_DFSDM1_CR2_CKABIE_Pos = 0x6      // Position of CKABIE field.
	DFSDM_DFSDM1_CR2_CKABIE_Msk = 0x40     // Bit mask of CKABIE field.
	DFSDM_DFSDM1_CR2_CKABIE     = 0x40     // Bit CKABIE.
	DFSDM_DFSDM1_CR2_EXCH_Pos   = 0x8      // Position of EXCH field.
	DFSDM_DFSDM1_CR2_EXCH_Msk   = 0xff00   // Bit mask of EXCH field.
	DFSDM_DFSDM1_CR2_AWDCH_Pos  = 0x10     // Position of AWDCH field.
	DFSDM_DFSDM1_CR2_AWDCH_Msk  = 0xff0000 // Bit mask of AWDCH field.

	// DFSDM2_CR2: DFSDM control register 2
	DFSDM_DFSDM2_CR2_JEOCIE_Pos = 0x0      // Position of JEOCIE field.
	DFSDM_DFSDM2_CR2_JEOCIE_Msk = 0x1      // Bit mask of JEOCIE field.
	DFSDM_DFSDM2_CR2_JEOCIE     = 0x1      // Bit JEOCIE.
	DFSDM_DFSDM2_CR2_REOCIE_Pos = 0x1      // Position of REOCIE field.
	DFSDM_DFSDM2_CR2_REOCIE_Msk = 0x2      // Bit mask of REOCIE field.
	DFSDM_DFSDM2_CR2_REOCIE     = 0x2      // Bit REOCIE.
	DFSDM_DFSDM2_CR2_JOVRIE_Pos = 0x2      // Position of JOVRIE field.
	DFSDM_DFSDM2_CR2_JOVRIE_Msk = 0x4      // Bit mask of JOVRIE field.
	DFSDM_DFSDM2_CR2_JOVRIE     = 0x4      // Bit JOVRIE.
	DFSDM_DFSDM2_CR2_ROVRIE_Pos = 0x3      // Position of ROVRIE field.
	DFSDM_DFSDM2_CR2_ROVRIE_Msk = 0x8      // Bit mask of ROVRIE field.
	DFSDM_DFSDM2_CR2_ROVRIE     = 0x8      // Bit ROVRIE.
	DFSDM_DFSDM2_CR2_AWDIE_Pos  = 0x4      // Position of AWDIE field.
	DFSDM_DFSDM2_CR2_AWDIE_Msk  = 0x10     // Bit mask of AWDIE field.
	DFSDM_DFSDM2_CR2_AWDIE      = 0x10     // Bit AWDIE.
	DFSDM_DFSDM2_CR2_SCDIE_Pos  = 0x5      // Position of SCDIE field.
	DFSDM_DFSDM2_CR2_SCDIE_Msk  = 0x20     // Bit mask of SCDIE field.
	DFSDM_DFSDM2_CR2_SCDIE      = 0x20     // Bit SCDIE.
	DFSDM_DFSDM2_CR2_CKABIE_Pos = 0x6      // Position of CKABIE field.
	DFSDM_DFSDM2_CR2_CKABIE_Msk = 0x40     // Bit mask of CKABIE field.
	DFSDM_DFSDM2_CR2_CKABIE     = 0x40     // Bit CKABIE.
	DFSDM_DFSDM2_CR2_EXCH_Pos   = 0x8      // Position of EXCH field.
	DFSDM_DFSDM2_CR2_EXCH_Msk   = 0xff00   // Bit mask of EXCH field.
	DFSDM_DFSDM2_CR2_AWDCH_Pos  = 0x10     // Position of AWDCH field.
	DFSDM_DFSDM2_CR2_AWDCH_Msk  = 0xff0000 // Bit mask of AWDCH field.

	// DFSDM3_CR2: DFSDM control register 2
	DFSDM_DFSDM3_CR2_JEOCIE_Pos = 0x0      // Position of JEOCIE field.
	DFSDM_DFSDM3_CR2_JEOCIE_Msk = 0x1      // Bit mask of JEOCIE field.
	DFSDM_DFSDM3_CR2_JEOCIE     = 0x1      // Bit JEOCIE.
	DFSDM_DFSDM3_CR2_REOCIE_Pos = 0x1      // Position of REOCIE field.
	DFSDM_DFSDM3_CR2_REOCIE_Msk = 0x2      // Bit mask of REOCIE field.
	DFSDM_DFSDM3_CR2_REOCIE     = 0x2      // Bit REOCIE.
	DFSDM_DFSDM3_CR2_JOVRIE_Pos = 0x2      // Position of JOVRIE field.
	DFSDM_DFSDM3_CR2_JOVRIE_Msk = 0x4      // Bit mask of JOVRIE field.
	DFSDM_DFSDM3_CR2_JOVRIE     = 0x4      // Bit JOVRIE.
	DFSDM_DFSDM3_CR2_ROVRIE_Pos = 0x3      // Position of ROVRIE field.
	DFSDM_DFSDM3_CR2_ROVRIE_Msk = 0x8      // Bit mask of ROVRIE field.
	DFSDM_DFSDM3_CR2_ROVRIE     = 0x8      // Bit ROVRIE.
	DFSDM_DFSDM3_CR2_AWDIE_Pos  = 0x4      // Position of AWDIE field.
	DFSDM_DFSDM3_CR2_AWDIE_Msk  = 0x10     // Bit mask of AWDIE field.
	DFSDM_DFSDM3_CR2_AWDIE      = 0x10     // Bit AWDIE.
	DFSDM_DFSDM3_CR2_SCDIE_Pos  = 0x5      // Position of SCDIE field.
	DFSDM_DFSDM3_CR2_SCDIE_Msk  = 0x20     // Bit mask of SCDIE field.
	DFSDM_DFSDM3_CR2_SCDIE      = 0x20     // Bit SCDIE.
	DFSDM_DFSDM3_CR2_CKABIE_Pos = 0x6      // Position of CKABIE field.
	DFSDM_DFSDM3_CR2_CKABIE_Msk = 0x40     // Bit mask of CKABIE field.
	DFSDM_DFSDM3_CR2_CKABIE     = 0x40     // Bit CKABIE.
	DFSDM_DFSDM3_CR2_EXCH_Pos   = 0x8      // Position of EXCH field.
	DFSDM_DFSDM3_CR2_EXCH_Msk   = 0xff00   // Bit mask of EXCH field.
	DFSDM_DFSDM3_CR2_AWDCH_Pos  = 0x10     // Position of AWDCH field.
	DFSDM_DFSDM3_CR2_AWDCH_Msk  = 0xff0000 // Bit mask of AWDCH field.

	// DFSDM0_ISR: DFSDM interrupt and status           register
	DFSDM_DFSDM0_ISR_JEOCF_Pos = 0x0        // Position of JEOCF field.
	DFSDM_DFSDM0_ISR_JEOCF_Msk = 0x1        // Bit mask of JEOCF field.
	DFSDM_DFSDM0_ISR_JEOCF     = 0x1        // Bit JEOCF.
	DFSDM_DFSDM0_ISR_REOCF_Pos = 0x1        // Position of REOCF field.
	DFSDM_DFSDM0_ISR_REOCF_Msk = 0x2        // Bit mask of REOCF field.
	DFSDM_DFSDM0_ISR_REOCF     = 0x2        // Bit REOCF.
	DFSDM_DFSDM0_ISR_JOVRF_Pos = 0x2        // Position of JOVRF field.
	DFSDM_DFSDM0_ISR_JOVRF_Msk = 0x4        // Bit mask of JOVRF field.
	DFSDM_DFSDM0_ISR_JOVRF     = 0x4        // Bit JOVRF.
	DFSDM_DFSDM0_ISR_ROVRF_Pos = 0x3        // Position of ROVRF field.
	DFSDM_DFSDM0_ISR_ROVRF_Msk = 0x8        // Bit mask of ROVRF field.
	DFSDM_DFSDM0_ISR_ROVRF     = 0x8        // Bit ROVRF.
	DFSDM_DFSDM0_ISR_AWDF_Pos  = 0x4        // Position of AWDF field.
	DFSDM_DFSDM0_ISR_AWDF_Msk  = 0x10       // Bit mask of AWDF field.
	DFSDM_DFSDM0_ISR_AWDF      = 0x10       // Bit AWDF.
	DFSDM_DFSDM0_ISR_JCIP_Pos  = 0xd        // Position of JCIP field.
	DFSDM_DFSDM0_ISR_JCIP_Msk  = 0x2000     // Bit mask of JCIP field.
	DFSDM_DFSDM0_ISR_JCIP      = 0x2000     // Bit JCIP.
	DFSDM_DFSDM0_ISR_RCIP_Pos  = 0xe        // Position of RCIP field.
	DFSDM_DFSDM0_ISR_RCIP_Msk  = 0x4000     // Bit mask of RCIP field.
	DFSDM_DFSDM0_ISR_RCIP      = 0x4000     // Bit RCIP.
	DFSDM_DFSDM0_ISR_CKABF_Pos = 0x10       // Position of CKABF field.
	DFSDM_DFSDM0_ISR_CKABF_Msk = 0xff0000   // Bit mask of CKABF field.
	DFSDM_DFSDM0_ISR_SCDF_Pos  = 0x18       // Position of SCDF field.
	DFSDM_DFSDM0_ISR_SCDF_Msk  = 0xff000000 // Bit mask of SCDF field.

	// DFSDM1_ISR: DFSDM interrupt and status           register
	DFSDM_DFSDM1_ISR_JEOCF_Pos = 0x0        // Position of JEOCF field.
	DFSDM_DFSDM1_ISR_JEOCF_Msk = 0x1        // Bit mask of JEOCF field.
	DFSDM_DFSDM1_ISR_JEOCF     = 0x1        // Bit JEOCF.
	DFSDM_DFSDM1_ISR_REOCF_Pos = 0x1        // Position of REOCF field.
	DFSDM_DFSDM1_ISR_REOCF_Msk = 0x2        // Bit mask of REOCF field.
	DFSDM_DFSDM1_ISR_REOCF     = 0x2        // Bit REOCF.
	DFSDM_DFSDM1_ISR_JOVRF_Pos = 0x2        // Position of JOVRF field.
	DFSDM_DFSDM1_ISR_JOVRF_Msk = 0x4        // Bit mask of JOVRF field.
	DFSDM_DFSDM1_ISR_JOVRF     = 0x4        // Bit JOVRF.
	DFSDM_DFSDM1_ISR_ROVRF_Pos = 0x3        // Position of ROVRF field.
	DFSDM_DFSDM1_ISR_ROVRF_Msk = 0x8        // Bit mask of ROVRF field.
	DFSDM_DFSDM1_ISR_ROVRF     = 0x8        // Bit ROVRF.
	DFSDM_DFSDM1_ISR_AWDF_Pos  = 0x4        // Position of AWDF field.
	DFSDM_DFSDM1_ISR_AWDF_Msk  = 0x10       // Bit mask of AWDF field.
	DFSDM_DFSDM1_ISR_AWDF      = 0x10       // Bit AWDF.
	DFSDM_DFSDM1_ISR_JCIP_Pos  = 0xd        // Position of JCIP field.
	DFSDM_DFSDM1_ISR_JCIP_Msk  = 0x2000     // Bit mask of JCIP field.
	DFSDM_DFSDM1_ISR_JCIP      = 0x2000     // Bit JCIP.
	DFSDM_DFSDM1_ISR_RCIP_Pos  = 0xe        // Position of RCIP field.
	DFSDM_DFSDM1_ISR_RCIP_Msk  = 0x4000     // Bit mask of RCIP field.
	DFSDM_DFSDM1_ISR_RCIP      = 0x4000     // Bit RCIP.
	DFSDM_DFSDM1_ISR_CKABF_Pos = 0x10       // Position of CKABF field.
	DFSDM_DFSDM1_ISR_CKABF_Msk = 0xff0000   // Bit mask of CKABF field.
	DFSDM_DFSDM1_ISR_SCDF_Pos  = 0x18       // Position of SCDF field.
	DFSDM_DFSDM1_ISR_SCDF_Msk  = 0xff000000 // Bit mask of SCDF field.

	// DFSDM2_ISR: DFSDM interrupt and status           register
	DFSDM_DFSDM2_ISR_JEOCF_Pos = 0x0        // Position of JEOCF field.
	DFSDM_DFSDM2_ISR_JEOCF_Msk = 0x1        // Bit mask of JEOCF field.
	DFSDM_DFSDM2_ISR_JEOCF     = 0x1        // Bit JEOCF.
	DFSDM_DFSDM2_ISR_REOCF_Pos = 0x1        // Position of REOCF field.
	DFSDM_DFSDM2_ISR_REOCF_Msk = 0x2        // Bit mask of REOCF field.
	DFSDM_DFSDM2_ISR_REOCF     = 0x2        // Bit REOCF.
	DFSDM_DFSDM2_ISR_JOVRF_Pos = 0x2        // Position of JOVRF field.
	DFSDM_DFSDM2_ISR_JOVRF_Msk = 0x4        // Bit mask of JOVRF field.
	DFSDM_DFSDM2_ISR_JOVRF     = 0x4        // Bit JOVRF.
	DFSDM_DFSDM2_ISR_ROVRF_Pos = 0x3        // Position of ROVRF field.
	DFSDM_DFSDM2_ISR_ROVRF_Msk = 0x8        // Bit mask of ROVRF field.
	DFSDM_DFSDM2_ISR_ROVRF     = 0x8        // Bit ROVRF.
	DFSDM_DFSDM2_ISR_AWDF_Pos  = 0x4        // Position of AWDF field.
	DFSDM_DFSDM2_ISR_AWDF_Msk  = 0x10       // Bit mask of AWDF field.
	DFSDM_DFSDM2_ISR_AWDF      = 0x10       // Bit AWDF.
	DFSDM_DFSDM2_ISR_JCIP_Pos  = 0xd        // Position of JCIP field.
	DFSDM_DFSDM2_ISR_JCIP_Msk  = 0x2000     // Bit mask of JCIP field.
	DFSDM_DFSDM2_ISR_JCIP      = 0x2000     // Bit JCIP.
	DFSDM_DFSDM2_ISR_RCIP_Pos  = 0xe        // Position of RCIP field.
	DFSDM_DFSDM2_ISR_RCIP_Msk  = 0x4000     // Bit mask of RCIP field.
	DFSDM_DFSDM2_ISR_RCIP      = 0x4000     // Bit RCIP.
	DFSDM_DFSDM2_ISR_CKABF_Pos = 0x10       // Position of CKABF field.
	DFSDM_DFSDM2_ISR_CKABF_Msk = 0xff0000   // Bit mask of CKABF field.
	DFSDM_DFSDM2_ISR_SCDF_Pos  = 0x18       // Position of SCDF field.
	DFSDM_DFSDM2_ISR_SCDF_Msk  = 0xff000000 // Bit mask of SCDF field.

	// DFSDM3_ISR: DFSDM interrupt and status           register
	DFSDM_DFSDM3_ISR_JEOCF_Pos = 0x0        // Position of JEOCF field.
	DFSDM_DFSDM3_ISR_JEOCF_Msk = 0x1        // Bit mask of JEOCF field.
	DFSDM_DFSDM3_ISR_JEOCF     = 0x1        // Bit JEOCF.
	DFSDM_DFSDM3_ISR_REOCF_Pos = 0x1        // Position of REOCF field.
	DFSDM_DFSDM3_ISR_REOCF_Msk = 0x2        // Bit mask of REOCF field.
	DFSDM_DFSDM3_ISR_REOCF     = 0x2        // Bit REOCF.
	DFSDM_DFSDM3_ISR_JOVRF_Pos = 0x2        // Position of JOVRF field.
	DFSDM_DFSDM3_ISR_JOVRF_Msk = 0x4        // Bit mask of JOVRF field.
	DFSDM_DFSDM3_ISR_JOVRF     = 0x4        // Bit JOVRF.
	DFSDM_DFSDM3_ISR_ROVRF_Pos = 0x3        // Position of ROVRF field.
	DFSDM_DFSDM3_ISR_ROVRF_Msk = 0x8        // Bit mask of ROVRF field.
	DFSDM_DFSDM3_ISR_ROVRF     = 0x8        // Bit ROVRF.
	DFSDM_DFSDM3_ISR_AWDF_Pos  = 0x4        // Position of AWDF field.
	DFSDM_DFSDM3_ISR_AWDF_Msk  = 0x10       // Bit mask of AWDF field.
	DFSDM_DFSDM3_ISR_AWDF      = 0x10       // Bit AWDF.
	DFSDM_DFSDM3_ISR_JCIP_Pos  = 0xd        // Position of JCIP field.
	DFSDM_DFSDM3_ISR_JCIP_Msk  = 0x2000     // Bit mask of JCIP field.
	DFSDM_DFSDM3_ISR_JCIP      = 0x2000     // Bit JCIP.
	DFSDM_DFSDM3_ISR_RCIP_Pos  = 0xe        // Position of RCIP field.
	DFSDM_DFSDM3_ISR_RCIP_Msk  = 0x4000     // Bit mask of RCIP field.
	DFSDM_DFSDM3_ISR_RCIP      = 0x4000     // Bit RCIP.
	DFSDM_DFSDM3_ISR_CKABF_Pos = 0x10       // Position of CKABF field.
	DFSDM_DFSDM3_ISR_CKABF_Msk = 0xff0000   // Bit mask of CKABF field.
	DFSDM_DFSDM3_ISR_SCDF_Pos  = 0x18       // Position of SCDF field.
	DFSDM_DFSDM3_ISR_SCDF_Msk  = 0xff000000 // Bit mask of SCDF field.

	// DFSDM0_ICR: DFSDM interrupt flag clear           register
	DFSDM_DFSDM0_ICR_CLRJOVRF_Pos = 0x2        // Position of CLRJOVRF field.
	DFSDM_DFSDM0_ICR_CLRJOVRF_Msk = 0x4        // Bit mask of CLRJOVRF field.
	DFSDM_DFSDM0_ICR_CLRJOVRF     = 0x4        // Bit CLRJOVRF.
	DFSDM_DFSDM0_ICR_CLRROVRF_Pos = 0x3        // Position of CLRROVRF field.
	DFSDM_DFSDM0_ICR_CLRROVRF_Msk = 0x8        // Bit mask of CLRROVRF field.
	DFSDM_DFSDM0_ICR_CLRROVRF     = 0x8        // Bit CLRROVRF.
	DFSDM_DFSDM0_ICR_CLRCKABF_Pos = 0x10       // Position of CLRCKABF field.
	DFSDM_DFSDM0_ICR_CLRCKABF_Msk = 0xff0000   // Bit mask of CLRCKABF field.
	DFSDM_DFSDM0_ICR_CLRSCDF_Pos  = 0x18       // Position of CLRSCDF field.
	DFSDM_DFSDM0_ICR_CLRSCDF_Msk  = 0xff000000 // Bit mask of CLRSCDF field.

	// DFSDM1_ICR: DFSDM interrupt flag clear           register
	DFSDM_DFSDM1_ICR_CLRJOVRF_Pos = 0x2        // Position of CLRJOVRF field.
	DFSDM_DFSDM1_ICR_CLRJOVRF_Msk = 0x4        // Bit mask of CLRJOVRF field.
	DFSDM_DFSDM1_ICR_CLRJOVRF     = 0x4        // Bit CLRJOVRF.
	DFSDM_DFSDM1_ICR_CLRROVRF_Pos = 0x3        // Position of CLRROVRF field.
	DFSDM_DFSDM1_ICR_CLRROVRF_Msk = 0x8        // Bit mask of CLRROVRF field.
	DFSDM_DFSDM1_ICR_CLRROVRF     = 0x8        // Bit CLRROVRF.
	DFSDM_DFSDM1_ICR_CLRCKABF_Pos = 0x10       // Position of CLRCKABF field.
	DFSDM_DFSDM1_ICR_CLRCKABF_Msk = 0xff0000   // Bit mask of CLRCKABF field.
	DFSDM_DFSDM1_ICR_CLRSCDF_Pos  = 0x18       // Position of CLRSCDF field.
	DFSDM_DFSDM1_ICR_CLRSCDF_Msk  = 0xff000000 // Bit mask of CLRSCDF field.

	// DFSDM2_ICR: DFSDM interrupt flag clear           register
	DFSDM_DFSDM2_ICR_CLRJOVRF_Pos = 0x2        // Position of CLRJOVRF field.
	DFSDM_DFSDM2_ICR_CLRJOVRF_Msk = 0x4        // Bit mask of CLRJOVRF field.
	DFSDM_DFSDM2_ICR_CLRJOVRF     = 0x4        // Bit CLRJOVRF.
	DFSDM_DFSDM2_ICR_CLRROVRF_Pos = 0x3        // Position of CLRROVRF field.
	DFSDM_DFSDM2_ICR_CLRROVRF_Msk = 0x8        // Bit mask of CLRROVRF field.
	DFSDM_DFSDM2_ICR_CLRROVRF     = 0x8        // Bit CLRROVRF.
	DFSDM_DFSDM2_ICR_CLRCKABF_Pos = 0x10       // Position of CLRCKABF field.
	DFSDM_DFSDM2_ICR_CLRCKABF_Msk = 0xff0000   // Bit mask of CLRCKABF field.
	DFSDM_DFSDM2_ICR_CLRSCDF_Pos  = 0x18       // Position of CLRSCDF field.
	DFSDM_DFSDM2_ICR_CLRSCDF_Msk  = 0xff000000 // Bit mask of CLRSCDF field.

	// DFSDM3_ICR: DFSDM interrupt flag clear           register
	DFSDM_DFSDM3_ICR_CLRJOVRF_Pos = 0x2        // Position of CLRJOVRF field.
	DFSDM_DFSDM3_ICR_CLRJOVRF_Msk = 0x4        // Bit mask of CLRJOVRF field.
	DFSDM_DFSDM3_ICR_CLRJOVRF     = 0x4        // Bit CLRJOVRF.
	DFSDM_DFSDM3_ICR_CLRROVRF_Pos = 0x3        // Position of CLRROVRF field.
	DFSDM_DFSDM3_ICR_CLRROVRF_Msk = 0x8        // Bit mask of CLRROVRF field.
	DFSDM_DFSDM3_ICR_CLRROVRF     = 0x8        // Bit CLRROVRF.
	DFSDM_DFSDM3_ICR_CLRCKABF_Pos = 0x10       // Position of CLRCKABF field.
	DFSDM_DFSDM3_ICR_CLRCKABF_Msk = 0xff0000   // Bit mask of CLRCKABF field.
	DFSDM_DFSDM3_ICR_CLRSCDF_Pos  = 0x18       // Position of CLRSCDF field.
	DFSDM_DFSDM3_ICR_CLRSCDF_Msk  = 0xff000000 // Bit mask of CLRSCDF field.

	// DFSDM0_JCHGR: DFSDM injected channel group selection           register
	DFSDM_DFSDM0_JCHGR_JCHG_Pos = 0x0  // Position of JCHG field.
	DFSDM_DFSDM0_JCHGR_JCHG_Msk = 0xff // Bit mask of JCHG field.

	// DFSDM1_JCHGR: DFSDM injected channel group selection           register
	DFSDM_DFSDM1_JCHGR_JCHG_Pos = 0x0  // Position of JCHG field.
	DFSDM_DFSDM1_JCHGR_JCHG_Msk = 0xff // Bit mask of JCHG field.

	// DFSDM2_JCHGR: DFSDM injected channel group selection           register
	DFSDM_DFSDM2_JCHGR_JCHG_Pos = 0x0  // Position of JCHG field.
	DFSDM_DFSDM2_JCHGR_JCHG_Msk = 0xff // Bit mask of JCHG field.

	// DFSDM3_JCHGR: DFSDM injected channel group selection           register
	DFSDM_DFSDM3_JCHGR_JCHG_Pos = 0x0  // Position of JCHG field.
	DFSDM_DFSDM3_JCHGR_JCHG_Msk = 0xff // Bit mask of JCHG field.

	// DFSDM0_FCR: DFSDM filter control register
	DFSDM_DFSDM0_FCR_IOSR_Pos = 0x0        // Position of IOSR field.
	DFSDM_DFSDM0_FCR_IOSR_Msk = 0xff       // Bit mask of IOSR field.
	DFSDM_DFSDM0_FCR_FOSR_Pos = 0x10       // Position of FOSR field.
	DFSDM_DFSDM0_FCR_FOSR_Msk = 0x3ff0000  // Bit mask of FOSR field.
	DFSDM_DFSDM0_FCR_FORD_Pos = 0x1d       // Position of FORD field.
	DFSDM_DFSDM0_FCR_FORD_Msk = 0xe0000000 // Bit mask of FORD field.

	// DFSDM1_FCR: DFSDM filter control register
	DFSDM_DFSDM1_FCR_IOSR_Pos = 0x0        // Position of IOSR field.
	DFSDM_DFSDM1_FCR_IOSR_Msk = 0xff       // Bit mask of IOSR field.
	DFSDM_DFSDM1_FCR_FOSR_Pos = 0x10       // Position of FOSR field.
	DFSDM_DFSDM1_FCR_FOSR_Msk = 0x3ff0000  // Bit mask of FOSR field.
	DFSDM_DFSDM1_FCR_FORD_Pos = 0x1d       // Position of FORD field.
	DFSDM_DFSDM1_FCR_FORD_Msk = 0xe0000000 // Bit mask of FORD field.

	// DFSDM2_FCR: DFSDM filter control register
	DFSDM_DFSDM2_FCR_IOSR_Pos = 0x0        // Position of IOSR field.
	DFSDM_DFSDM2_FCR_IOSR_Msk = 0xff       // Bit mask of IOSR field.
	DFSDM_DFSDM2_FCR_FOSR_Pos = 0x10       // Position of FOSR field.
	DFSDM_DFSDM2_FCR_FOSR_Msk = 0x3ff0000  // Bit mask of FOSR field.
	DFSDM_DFSDM2_FCR_FORD_Pos = 0x1d       // Position of FORD field.
	DFSDM_DFSDM2_FCR_FORD_Msk = 0xe0000000 // Bit mask of FORD field.

	// DFSDM3_FCR: DFSDM filter control register
	DFSDM_DFSDM3_FCR_IOSR_Pos = 0x0        // Position of IOSR field.
	DFSDM_DFSDM3_FCR_IOSR_Msk = 0xff       // Bit mask of IOSR field.
	DFSDM_DFSDM3_FCR_FOSR_Pos = 0x10       // Position of FOSR field.
	DFSDM_DFSDM3_FCR_FOSR_Msk = 0x3ff0000  // Bit mask of FOSR field.
	DFSDM_DFSDM3_FCR_FORD_Pos = 0x1d       // Position of FORD field.
	DFSDM_DFSDM3_FCR_FORD_Msk = 0xe0000000 // Bit mask of FORD field.

	// DFSDM0_JDATAR: DFSDM data register for injected           group
	DFSDM_DFSDM0_JDATAR_JDATACH_Pos = 0x0        // Position of JDATACH field.
	DFSDM_DFSDM0_JDATAR_JDATACH_Msk = 0x7        // Bit mask of JDATACH field.
	DFSDM_DFSDM0_JDATAR_JDATA_Pos   = 0x8        // Position of JDATA field.
	DFSDM_DFSDM0_JDATAR_JDATA_Msk   = 0xffffff00 // Bit mask of JDATA field.

	// DFSDM1_JDATAR: DFSDM data register for injected           group
	DFSDM_DFSDM1_JDATAR_JDATACH_Pos = 0x0        // Position of JDATACH field.
	DFSDM_DFSDM1_JDATAR_JDATACH_Msk = 0x7        // Bit mask of JDATACH field.
	DFSDM_DFSDM1_JDATAR_JDATA_Pos   = 0x8        // Position of JDATA field.
	DFSDM_DFSDM1_JDATAR_JDATA_Msk   = 0xffffff00 // Bit mask of JDATA field.

	// DFSDM2_JDATAR: DFSDM data register for injected           group
	DFSDM_DFSDM2_JDATAR_JDATACH_Pos = 0x0        // Position of JDATACH field.
	DFSDM_DFSDM2_JDATAR_JDATACH_Msk = 0x7        // Bit mask of JDATACH field.
	DFSDM_DFSDM2_JDATAR_JDATA_Pos   = 0x8        // Position of JDATA field.
	DFSDM_DFSDM2_JDATAR_JDATA_Msk   = 0xffffff00 // Bit mask of JDATA field.

	// DFSDM3_JDATAR: DFSDM data register for injected           group
	DFSDM_DFSDM3_JDATAR_JDATACH_Pos = 0x0        // Position of JDATACH field.
	DFSDM_DFSDM3_JDATAR_JDATACH_Msk = 0x7        // Bit mask of JDATACH field.
	DFSDM_DFSDM3_JDATAR_JDATA_Pos   = 0x8        // Position of JDATA field.
	DFSDM_DFSDM3_JDATAR_JDATA_Msk   = 0xffffff00 // Bit mask of JDATA field.

	// DFSDM0_RDATAR: DFSDM data register for the regular           channel
	DFSDM_DFSDM0_RDATAR_RDATACH_Pos = 0x0        // Position of RDATACH field.
	DFSDM_DFSDM0_RDATAR_RDATACH_Msk = 0x7        // Bit mask of RDATACH field.
	DFSDM_DFSDM0_RDATAR_RPEND_Pos   = 0x4        // Position of RPEND field.
	DFSDM_DFSDM0_RDATAR_RPEND_Msk   = 0x10       // Bit mask of RPEND field.
	DFSDM_DFSDM0_RDATAR_RPEND       = 0x10       // Bit RPEND.
	DFSDM_DFSDM0_RDATAR_RDATA_Pos   = 0x8        // Position of RDATA field.
	DFSDM_DFSDM0_RDATAR_RDATA_Msk   = 0xffffff00 // Bit mask of RDATA field.

	// DFSDM1_RDATAR: DFSDM data register for the regular           channel
	DFSDM_DFSDM1_RDATAR_RDATACH_Pos = 0x0        // Position of RDATACH field.
	DFSDM_DFSDM1_RDATAR_RDATACH_Msk = 0x7        // Bit mask of RDATACH field.
	DFSDM_DFSDM1_RDATAR_RPEND_Pos   = 0x4        // Position of RPEND field.
	DFSDM_DFSDM1_RDATAR_RPEND_Msk   = 0x10       // Bit mask of RPEND field.
	DFSDM_DFSDM1_RDATAR_RPEND       = 0x10       // Bit RPEND.
	DFSDM_DFSDM1_RDATAR_RDATA_Pos   = 0x8        // Position of RDATA field.
	DFSDM_DFSDM1_RDATAR_RDATA_Msk   = 0xffffff00 // Bit mask of RDATA field.

	// DFSDM2_RDATAR: DFSDM data register for the regular           channel
	DFSDM_DFSDM2_RDATAR_RDATACH_Pos = 0x0        // Position of RDATACH field.
	DFSDM_DFSDM2_RDATAR_RDATACH_Msk = 0x7        // Bit mask of RDATACH field.
	DFSDM_DFSDM2_RDATAR_RPEND_Pos   = 0x4        // Position of RPEND field.
	DFSDM_DFSDM2_RDATAR_RPEND_Msk   = 0x10       // Bit mask of RPEND field.
	DFSDM_DFSDM2_RDATAR_RPEND       = 0x10       // Bit RPEND.
	DFSDM_DFSDM2_RDATAR_RDATA_Pos   = 0x8        // Position of RDATA field.
	DFSDM_DFSDM2_RDATAR_RDATA_Msk   = 0xffffff00 // Bit mask of RDATA field.

	// DFSDM3_RDATAR: DFSDM data register for the regular           channel
	DFSDM_DFSDM3_RDATAR_RDATACH_Pos = 0x0        // Position of RDATACH field.
	DFSDM_DFSDM3_RDATAR_RDATACH_Msk = 0x7        // Bit mask of RDATACH field.
	DFSDM_DFSDM3_RDATAR_RPEND_Pos   = 0x4        // Position of RPEND field.
	DFSDM_DFSDM3_RDATAR_RPEND_Msk   = 0x10       // Bit mask of RPEND field.
	DFSDM_DFSDM3_RDATAR_RPEND       = 0x10       // Bit RPEND.
	DFSDM_DFSDM3_RDATAR_RDATA_Pos   = 0x8        // Position of RDATA field.
	DFSDM_DFSDM3_RDATAR_RDATA_Msk   = 0xffffff00 // Bit mask of RDATA field.

	// DFSDM0_AWHTR: DFSDM analog watchdog high threshold           register
	DFSDM_DFSDM0_AWHTR_BKAWH_Pos = 0x0        // Position of BKAWH field.
	DFSDM_DFSDM0_AWHTR_BKAWH_Msk = 0xf        // Bit mask of BKAWH field.
	DFSDM_DFSDM0_AWHTR_AWHT_Pos  = 0x8        // Position of AWHT field.
	DFSDM_DFSDM0_AWHTR_AWHT_Msk  = 0xffffff00 // Bit mask of AWHT field.

	// DFSDM1_AWHTR: DFSDM analog watchdog high threshold           register
	DFSDM_DFSDM1_AWHTR_BKAWH_Pos = 0x0        // Position of BKAWH field.
	DFSDM_DFSDM1_AWHTR_BKAWH_Msk = 0xf        // Bit mask of BKAWH field.
	DFSDM_DFSDM1_AWHTR_AWHT_Pos  = 0x8        // Position of AWHT field.
	DFSDM_DFSDM1_AWHTR_AWHT_Msk  = 0xffffff00 // Bit mask of AWHT field.

	// DFSDM2_AWHTR: DFSDM analog watchdog high threshold           register
	DFSDM_DFSDM2_AWHTR_BKAWH_Pos = 0x0        // Position of BKAWH field.
	DFSDM_DFSDM2_AWHTR_BKAWH_Msk = 0xf        // Bit mask of BKAWH field.
	DFSDM_DFSDM2_AWHTR_AWHT_Pos  = 0x8        // Position of AWHT field.
	DFSDM_DFSDM2_AWHTR_AWHT_Msk  = 0xffffff00 // Bit mask of AWHT field.

	// DFSDM3_AWHTR: DFSDM analog watchdog high threshold           register
	DFSDM_DFSDM3_AWHTR_BKAWH_Pos = 0x0        // Position of BKAWH field.
	DFSDM_DFSDM3_AWHTR_BKAWH_Msk = 0xf        // Bit mask of BKAWH field.
	DFSDM_DFSDM3_AWHTR_AWHT_Pos  = 0x8        // Position of AWHT field.
	DFSDM_DFSDM3_AWHTR_AWHT_Msk  = 0xffffff00 // Bit mask of AWHT field.

	// DFSDM0_AWLTR: DFSDM analog watchdog low threshold           register
	DFSDM_DFSDM0_AWLTR_BKAWL_Pos = 0x0        // Position of BKAWL field.
	DFSDM_DFSDM0_AWLTR_BKAWL_Msk = 0xf        // Bit mask of BKAWL field.
	DFSDM_DFSDM0_AWLTR_AWLT_Pos  = 0x8        // Position of AWLT field.
	DFSDM_DFSDM0_AWLTR_AWLT_Msk  = 0xffffff00 // Bit mask of AWLT field.

	// DFSDM1_AWLTR: DFSDM analog watchdog low threshold           register
	DFSDM_DFSDM1_AWLTR_BKAWL_Pos = 0x0        // Position of BKAWL field.
	DFSDM_DFSDM1_AWLTR_BKAWL_Msk = 0xf        // Bit mask of BKAWL field.
	DFSDM_DFSDM1_AWLTR_AWLT_Pos  = 0x8        // Position of AWLT field.
	DFSDM_DFSDM1_AWLTR_AWLT_Msk  = 0xffffff00 // Bit mask of AWLT field.

	// DFSDM2_AWLTR: DFSDM analog watchdog low threshold           register
	DFSDM_DFSDM2_AWLTR_BKAWL_Pos = 0x0        // Position of BKAWL field.
	DFSDM_DFSDM2_AWLTR_BKAWL_Msk = 0xf        // Bit mask of BKAWL field.
	DFSDM_DFSDM2_AWLTR_AWLT_Pos  = 0x8        // Position of AWLT field.
	DFSDM_DFSDM2_AWLTR_AWLT_Msk  = 0xffffff00 // Bit mask of AWLT field.

	// DFSDM3_AWLTR: DFSDM analog watchdog low threshold           register
	DFSDM_DFSDM3_AWLTR_BKAWL_Pos = 0x0        // Position of BKAWL field.
	DFSDM_DFSDM3_AWLTR_BKAWL_Msk = 0xf        // Bit mask of BKAWL field.
	DFSDM_DFSDM3_AWLTR_AWLT_Pos  = 0x8        // Position of AWLT field.
	DFSDM_DFSDM3_AWLTR_AWLT_Msk  = 0xffffff00 // Bit mask of AWLT field.

	// DFSDM0_AWSR: DFSDM analog watchdog status           register
	DFSDM_DFSDM0_AWSR_AWLTF_Pos = 0x0    // Position of AWLTF field.
	DFSDM_DFSDM0_AWSR_AWLTF_Msk = 0xff   // Bit mask of AWLTF field.
	DFSDM_DFSDM0_AWSR_AWHTF_Pos = 0x8    // Position of AWHTF field.
	DFSDM_DFSDM0_AWSR_AWHTF_Msk = 0xff00 // Bit mask of AWHTF field.

	// DFSDM1_AWSR: DFSDM analog watchdog status           register
	DFSDM_DFSDM1_AWSR_AWLTF_Pos = 0x0    // Position of AWLTF field.
	DFSDM_DFSDM1_AWSR_AWLTF_Msk = 0xff   // Bit mask of AWLTF field.
	DFSDM_DFSDM1_AWSR_AWHTF_Pos = 0x8    // Position of AWHTF field.
	DFSDM_DFSDM1_AWSR_AWHTF_Msk = 0xff00 // Bit mask of AWHTF field.

	// DFSDM2_AWSR: DFSDM analog watchdog status           register
	DFSDM_DFSDM2_AWSR_AWLTF_Pos = 0x0    // Position of AWLTF field.
	DFSDM_DFSDM2_AWSR_AWLTF_Msk = 0xff   // Bit mask of AWLTF field.
	DFSDM_DFSDM2_AWSR_AWHTF_Pos = 0x8    // Position of AWHTF field.
	DFSDM_DFSDM2_AWSR_AWHTF_Msk = 0xff00 // Bit mask of AWHTF field.

	// DFSDM3_AWSR: DFSDM analog watchdog status           register
	DFSDM_DFSDM3_AWSR_AWLTF_Pos = 0x0    // Position of AWLTF field.
	DFSDM_DFSDM3_AWSR_AWLTF_Msk = 0xff   // Bit mask of AWLTF field.
	DFSDM_DFSDM3_AWSR_AWHTF_Pos = 0x8    // Position of AWHTF field.
	DFSDM_DFSDM3_AWSR_AWHTF_Msk = 0xff00 // Bit mask of AWHTF field.

	// DFSDM0_AWCFR: DFSDM analog watchdog clear flag           register
	DFSDM_DFSDM0_AWCFR_CLRAWLTF_Pos = 0x0    // Position of CLRAWLTF field.
	DFSDM_DFSDM0_AWCFR_CLRAWLTF_Msk = 0xff   // Bit mask of CLRAWLTF field.
	DFSDM_DFSDM0_AWCFR_CLRAWHTF_Pos = 0x8    // Position of CLRAWHTF field.
	DFSDM_DFSDM0_AWCFR_CLRAWHTF_Msk = 0xff00 // Bit mask of CLRAWHTF field.

	// DFSDM1_AWCFR: DFSDM analog watchdog clear flag           register
	DFSDM_DFSDM1_AWCFR_CLRAWLTF_Pos = 0x0    // Position of CLRAWLTF field.
	DFSDM_DFSDM1_AWCFR_CLRAWLTF_Msk = 0xff   // Bit mask of CLRAWLTF field.
	DFSDM_DFSDM1_AWCFR_CLRAWHTF_Pos = 0x8    // Position of CLRAWHTF field.
	DFSDM_DFSDM1_AWCFR_CLRAWHTF_Msk = 0xff00 // Bit mask of CLRAWHTF field.

	// DFSDM2_AWCFR: DFSDM analog watchdog clear flag           register
	DFSDM_DFSDM2_AWCFR_CLRAWLTF_Pos = 0x0    // Position of CLRAWLTF field.
	DFSDM_DFSDM2_AWCFR_CLRAWLTF_Msk = 0xff   // Bit mask of CLRAWLTF field.
	DFSDM_DFSDM2_AWCFR_CLRAWHTF_Pos = 0x8    // Position of CLRAWHTF field.
	DFSDM_DFSDM2_AWCFR_CLRAWHTF_Msk = 0xff00 // Bit mask of CLRAWHTF field.

	// DFSDM3_AWCFR: DFSDM analog watchdog clear flag           register
	DFSDM_DFSDM3_AWCFR_CLRAWLTF_Pos = 0x0    // Position of CLRAWLTF field.
	DFSDM_DFSDM3_AWCFR_CLRAWLTF_Msk = 0xff   // Bit mask of CLRAWLTF field.
	DFSDM_DFSDM3_AWCFR_CLRAWHTF_Pos = 0x8    // Position of CLRAWHTF field.
	DFSDM_DFSDM3_AWCFR_CLRAWHTF_Msk = 0xff00 // Bit mask of CLRAWHTF field.

	// DFSDM0_EXMAX: DFSDM Extremes detector maximum           register
	DFSDM_DFSDM0_EXMAX_EXMAXCH_Pos = 0x0        // Position of EXMAXCH field.
	DFSDM_DFSDM0_EXMAX_EXMAXCH_Msk = 0x7        // Bit mask of EXMAXCH field.
	DFSDM_DFSDM0_EXMAX_EXMAX_Pos   = 0x8        // Position of EXMAX field.
	DFSDM_DFSDM0_EXMAX_EXMAX_Msk   = 0xffffff00 // Bit mask of EXMAX field.

	// DFSDM1_EXMAX: DFSDM Extremes detector maximum           register
	DFSDM_DFSDM1_EXMAX_EXMAXCH_Pos = 0x0        // Position of EXMAXCH field.
	DFSDM_DFSDM1_EXMAX_EXMAXCH_Msk = 0x7        // Bit mask of EXMAXCH field.
	DFSDM_DFSDM1_EXMAX_EXMAX_Pos   = 0x8        // Position of EXMAX field.
	DFSDM_DFSDM1_EXMAX_EXMAX_Msk   = 0xffffff00 // Bit mask of EXMAX field.

	// DFSDM2_EXMAX: DFSDM Extremes detector maximum           register
	DFSDM_DFSDM2_EXMAX_EXMAXCH_Pos = 0x0        // Position of EXMAXCH field.
	DFSDM_DFSDM2_EXMAX_EXMAXCH_Msk = 0x7        // Bit mask of EXMAXCH field.
	DFSDM_DFSDM2_EXMAX_EXMAX_Pos   = 0x8        // Position of EXMAX field.
	DFSDM_DFSDM2_EXMAX_EXMAX_Msk   = 0xffffff00 // Bit mask of EXMAX field.

	// DFSDM3_EXMAX: DFSDM Extremes detector maximum           register
	DFSDM_DFSDM3_EXMAX_EXMAXCH_Pos = 0x0        // Position of EXMAXCH field.
	DFSDM_DFSDM3_EXMAX_EXMAXCH_Msk = 0x7        // Bit mask of EXMAXCH field.
	DFSDM_DFSDM3_EXMAX_EXMAX_Pos   = 0x8        // Position of EXMAX field.
	DFSDM_DFSDM3_EXMAX_EXMAX_Msk   = 0xffffff00 // Bit mask of EXMAX field.

	// DFSDM0_EXMIN: DFSDM Extremes detector minimum           register
	DFSDM_DFSDM0_EXMIN_EXMINCH_Pos = 0x0        // Position of EXMINCH field.
	DFSDM_DFSDM0_EXMIN_EXMINCH_Msk = 0x7        // Bit mask of EXMINCH field.
	DFSDM_DFSDM0_EXMIN_EXMIN_Pos   = 0x8        // Position of EXMIN field.
	DFSDM_DFSDM0_EXMIN_EXMIN_Msk   = 0xffffff00 // Bit mask of EXMIN field.

	// DFSDM1_EXMIN: DFSDM Extremes detector minimum           register
	DFSDM_DFSDM1_EXMIN_EXMINCH_Pos = 0x0        // Position of EXMINCH field.
	DFSDM_DFSDM1_EXMIN_EXMINCH_Msk = 0x7        // Bit mask of EXMINCH field.
	DFSDM_DFSDM1_EXMIN_EXMIN_Pos   = 0x8        // Position of EXMIN field.
	DFSDM_DFSDM1_EXMIN_EXMIN_Msk   = 0xffffff00 // Bit mask of EXMIN field.

	// DFSDM2_EXMIN: DFSDM Extremes detector minimum           register
	DFSDM_DFSDM2_EXMIN_EXMINCH_Pos = 0x0        // Position of EXMINCH field.
	DFSDM_DFSDM2_EXMIN_EXMINCH_Msk = 0x7        // Bit mask of EXMINCH field.
	DFSDM_DFSDM2_EXMIN_EXMIN_Pos   = 0x8        // Position of EXMIN field.
	DFSDM_DFSDM2_EXMIN_EXMIN_Msk   = 0xffffff00 // Bit mask of EXMIN field.

	// DFSDM3_EXMIN: DFSDM Extremes detector minimum           register
	DFSDM_DFSDM3_EXMIN_EXMINCH_Pos = 0x0        // Position of EXMINCH field.
	DFSDM_DFSDM3_EXMIN_EXMINCH_Msk = 0x7        // Bit mask of EXMINCH field.
	DFSDM_DFSDM3_EXMIN_EXMIN_Pos   = 0x8        // Position of EXMIN field.
	DFSDM_DFSDM3_EXMIN_EXMIN_Msk   = 0xffffff00 // Bit mask of EXMIN field.

	// DFSDM0_CNVTIMR: DFSDM conversion timer           register
	DFSDM_DFSDM0_CNVTIMR_CNVCNT_Pos = 0x4        // Position of CNVCNT field.
	DFSDM_DFSDM0_CNVTIMR_CNVCNT_Msk = 0xfffffff0 // Bit mask of CNVCNT field.

	// DFSDM1_CNVTIMR: DFSDM conversion timer           register
	DFSDM_DFSDM1_CNVTIMR_CNVCNT_Pos = 0x4        // Position of CNVCNT field.
	DFSDM_DFSDM1_CNVTIMR_CNVCNT_Msk = 0xfffffff0 // Bit mask of CNVCNT field.

	// DFSDM2_CNVTIMR: DFSDM conversion timer           register
	DFSDM_DFSDM2_CNVTIMR_CNVCNT_Pos = 0x4        // Position of CNVCNT field.
	DFSDM_DFSDM2_CNVTIMR_CNVCNT_Msk = 0xfffffff0 // Bit mask of CNVCNT field.

	// DFSDM3_CNVTIMR: DFSDM conversion timer           register
	DFSDM_DFSDM3_CNVTIMR_CNVCNT_Pos = 0x4        // Position of CNVCNT field.
	DFSDM_DFSDM3_CNVTIMR_CNVCNT_Msk = 0xfffffff0 // Bit mask of CNVCNT field.
)

// Bitfields for TIM16: General-purpose-timers
const (
	// CR1: control register 1
	TIMs_CR1_CEN_Pos      = 0x0   // Position of CEN field.
	TIMs_CR1_CEN_Msk      = 0x1   // Bit mask of CEN field.
	TIMs_CR1_CEN          = 0x1   // Bit CEN.
	TIMs_CR1_UDIS_Pos     = 0x1   // Position of UDIS field.
	TIMs_CR1_UDIS_Msk     = 0x2   // Bit mask of UDIS field.
	TIMs_CR1_UDIS         = 0x2   // Bit UDIS.
	TIMs_CR1_URS_Pos      = 0x2   // Position of URS field.
	TIMs_CR1_URS_Msk      = 0x4   // Bit mask of URS field.
	TIMs_CR1_URS          = 0x4   // Bit URS.
	TIMs_CR1_OPM_Pos      = 0x3   // Position of OPM field.
	TIMs_CR1_OPM_Msk      = 0x8   // Bit mask of OPM field.
	TIMs_CR1_OPM          = 0x8   // Bit OPM.
	TIMs_CR1_ARPE_Pos     = 0x7   // Position of ARPE field.
	TIMs_CR1_ARPE_Msk     = 0x80  // Bit mask of ARPE field.
	TIMs_CR1_ARPE         = 0x80  // Bit ARPE.
	TIMs_CR1_CKD_Pos      = 0x8   // Position of CKD field.
	TIMs_CR1_CKD_Msk      = 0x300 // Bit mask of CKD field.
	TIMs_CR1_UIFREMAP_Pos = 0xb   // Position of UIFREMAP field.
	TIMs_CR1_UIFREMAP_Msk = 0x800 // Bit mask of UIFREMAP field.
	TIMs_CR1_UIFREMAP     = 0x800 // Bit UIFREMAP.

	// CR2: control register 2
	TIMs_CR2_OIS1N_Pos = 0x9   // Position of OIS1N field.
	TIMs_CR2_OIS1N_Msk = 0x200 // Bit mask of OIS1N field.
	TIMs_CR2_OIS1N     = 0x200 // Bit OIS1N.
	TIMs_CR2_OIS1_Pos  = 0x8   // Position of OIS1 field.
	TIMs_CR2_OIS1_Msk  = 0x100 // Bit mask of OIS1 field.
	TIMs_CR2_OIS1      = 0x100 // Bit OIS1.
	TIMs_CR2_CCDS_Pos  = 0x3   // Position of CCDS field.
	TIMs_CR2_CCDS_Msk  = 0x8   // Bit mask of CCDS field.
	TIMs_CR2_CCDS      = 0x8   // Bit CCDS.
	TIMs_CR2_CCUS_Pos  = 0x2   // Position of CCUS field.
	TIMs_CR2_CCUS_Msk  = 0x4   // Bit mask of CCUS field.
	TIMs_CR2_CCUS      = 0x4   // Bit CCUS.
	TIMs_CR2_CCPC_Pos  = 0x0   // Position of CCPC field.
	TIMs_CR2_CCPC_Msk  = 0x1   // Bit mask of CCPC field.
	TIMs_CR2_CCPC      = 0x1   // Bit CCPC.

	// DIER: DMA/Interrupt enable register
	TIMs_DIER_UIE_Pos   = 0x0    // Position of UIE field.
	TIMs_DIER_UIE_Msk   = 0x1    // Bit mask of UIE field.
	TIMs_DIER_UIE       = 0x1    // Bit UIE.
	TIMs_DIER_CC1IE_Pos = 0x1    // Position of CC1IE field.
	TIMs_DIER_CC1IE_Msk = 0x2    // Bit mask of CC1IE field.
	TIMs_DIER_CC1IE     = 0x2    // Bit CC1IE.
	TIMs_DIER_COMIE_Pos = 0x5    // Position of COMIE field.
	TIMs_DIER_COMIE_Msk = 0x20   // Bit mask of COMIE field.
	TIMs_DIER_COMIE     = 0x20   // Bit COMIE.
	TIMs_DIER_BIE_Pos   = 0x7    // Position of BIE field.
	TIMs_DIER_BIE_Msk   = 0x80   // Bit mask of BIE field.
	TIMs_DIER_BIE       = 0x80   // Bit BIE.
	TIMs_DIER_UDE_Pos   = 0x8    // Position of UDE field.
	TIMs_DIER_UDE_Msk   = 0x100  // Bit mask of UDE field.
	TIMs_DIER_UDE       = 0x100  // Bit UDE.
	TIMs_DIER_CC1DE_Pos = 0x9    // Position of CC1DE field.
	TIMs_DIER_CC1DE_Msk = 0x200  // Bit mask of CC1DE field.
	TIMs_DIER_CC1DE     = 0x200  // Bit CC1DE.
	TIMs_DIER_COMDE_Pos = 0xd    // Position of COMDE field.
	TIMs_DIER_COMDE_Msk = 0x2000 // Bit mask of COMDE field.
	TIMs_DIER_COMDE     = 0x2000 // Bit COMDE.

	// SR: status register
	TIMs_SR_CC1OF_Pos = 0x9   // Position of CC1OF field.
	TIMs_SR_CC1OF_Msk = 0x200 // Bit mask of CC1OF field.
	TIMs_SR_CC1OF     = 0x200 // Bit CC1OF.
	TIMs_SR_BIF_Pos   = 0x7   // Position of BIF field.
	TIMs_SR_BIF_Msk   = 0x80  // Bit mask of BIF field.
	TIMs_SR_BIF       = 0x80  // Bit BIF.
	TIMs_SR_COMIF_Pos = 0x5   // Position of COMIF field.
	TIMs_SR_COMIF_Msk = 0x20  // Bit mask of COMIF field.
	TIMs_SR_COMIF     = 0x20  // Bit COMIF.
	TIMs_SR_CC1IF_Pos = 0x1   // Position of CC1IF field.
	TIMs_SR_CC1IF_Msk = 0x2   // Bit mask of CC1IF field.
	TIMs_SR_CC1IF     = 0x2   // Bit CC1IF.
	TIMs_SR_UIF_Pos   = 0x0   // Position of UIF field.
	TIMs_SR_UIF_Msk   = 0x1   // Bit mask of UIF field.
	TIMs_SR_UIF       = 0x1   // Bit UIF.

	// EGR: event generation register
	TIMs_EGR_BG_Pos   = 0x7  // Position of BG field.
	TIMs_EGR_BG_Msk   = 0x80 // Bit mask of BG field.
	TIMs_EGR_BG       = 0x80 // Bit BG.
	TIMs_EGR_COMG_Pos = 0x5  // Position of COMG field.
	TIMs_EGR_COMG_Msk = 0x20 // Bit mask of COMG field.
	TIMs_EGR_COMG     = 0x20 // Bit COMG.
	TIMs_EGR_CC1G_Pos = 0x1  // Position of CC1G field.
	TIMs_EGR_CC1G_Msk = 0x2  // Bit mask of CC1G field.
	TIMs_EGR_CC1G     = 0x2  // Bit CC1G.
	TIMs_EGR_UG_Pos   = 0x0  // Position of UG field.
	TIMs_EGR_UG_Msk   = 0x1  // Bit mask of UG field.
	TIMs_EGR_UG       = 0x1  // Bit UG.

	// CCMR1_Output: capture/compare mode register (output           mode)
	TIMs_CCMR1_Output_CC1S_Pos   = 0x0     // Position of CC1S field.
	TIMs_CCMR1_Output_CC1S_Msk   = 0x3     // Bit mask of CC1S field.
	TIMs_CCMR1_Output_OC1FE_Pos  = 0x2     // Position of OC1FE field.
	TIMs_CCMR1_Output_OC1FE_Msk  = 0x4     // Bit mask of OC1FE field.
	TIMs_CCMR1_Output_OC1FE      = 0x4     // Bit OC1FE.
	TIMs_CCMR1_Output_OC1PE_Pos  = 0x3     // Position of OC1PE field.
	TIMs_CCMR1_Output_OC1PE_Msk  = 0x8     // Bit mask of OC1PE field.
	TIMs_CCMR1_Output_OC1PE      = 0x8     // Bit OC1PE.
	TIMs_CCMR1_Output_OC1M_Pos   = 0x4     // Position of OC1M field.
	TIMs_CCMR1_Output_OC1M_Msk   = 0x70    // Bit mask of OC1M field.
	TIMs_CCMR1_Output_OC1M_3_Pos = 0x10    // Position of OC1M_3 field.
	TIMs_CCMR1_Output_OC1M_3_Msk = 0x10000 // Bit mask of OC1M_3 field.
	TIMs_CCMR1_Output_OC1M_3     = 0x10000 // Bit OC1M_3.

	// CCMR1_Input: capture/compare mode register 1 (input           mode)
	TIMs_CCMR1_Input_IC1F_Pos   = 0x4  // Position of IC1F field.
	TIMs_CCMR1_Input_IC1F_Msk   = 0xf0 // Bit mask of IC1F field.
	TIMs_CCMR1_Input_IC1PSC_Pos = 0x2  // Position of IC1PSC field.
	TIMs_CCMR1_Input_IC1PSC_Msk = 0xc  // Bit mask of IC1PSC field.
	TIMs_CCMR1_Input_CC1S_Pos   = 0x0  // Position of CC1S field.
	TIMs_CCMR1_Input_CC1S_Msk   = 0x3  // Bit mask of CC1S field.

	// CCER: capture/compare enable           register
	TIMs_CCER_CC1NP_Pos = 0x3 // Position of CC1NP field.
	TIMs_CCER_CC1NP_Msk = 0x8 // Bit mask of CC1NP field.
	TIMs_CCER_CC1NP     = 0x8 // Bit CC1NP.
	TIMs_CCER_CC1NE_Pos = 0x2 // Position of CC1NE field.
	TIMs_CCER_CC1NE_Msk = 0x4 // Bit mask of CC1NE field.
	TIMs_CCER_CC1NE     = 0x4 // Bit CC1NE.
	TIMs_CCER_CC1P_Pos  = 0x1 // Position of CC1P field.
	TIMs_CCER_CC1P_Msk  = 0x2 // Bit mask of CC1P field.
	TIMs_CCER_CC1P      = 0x2 // Bit CC1P.
	TIMs_CCER_CC1E_Pos  = 0x0 // Position of CC1E field.
	TIMs_CCER_CC1E_Msk  = 0x1 // Bit mask of CC1E field.
	TIMs_CCER_CC1E      = 0x1 // Bit CC1E.

	// CNT: counter
	TIMs_CNT_CNT_Pos    = 0x0        // Position of CNT field.
	TIMs_CNT_CNT_Msk    = 0xffff     // Bit mask of CNT field.
	TIMs_CNT_UIFCPY_Pos = 0x1f       // Position of UIFCPY field.
	TIMs_CNT_UIFCPY_Msk = 0x80000000 // Bit mask of UIFCPY field.
	TIMs_CNT_UIFCPY     = 0x80000000 // Bit UIFCPY.

	// PSC: prescaler
	TIMs_PSC_PSC_Pos = 0x0    // Position of PSC field.
	TIMs_PSC_PSC_Msk = 0xffff // Bit mask of PSC field.

	// ARR: auto-reload register
	TIMs_ARR_ARR_Pos = 0x0    // Position of ARR field.
	TIMs_ARR_ARR_Msk = 0xffff // Bit mask of ARR field.

	// RCR: repetition counter register
	TIMs_RCR_REP_Pos = 0x0  // Position of REP field.
	TIMs_RCR_REP_Msk = 0xff // Bit mask of REP field.

	// CCR1: capture/compare register 1
	TIMs_CCR1_CCR1_Pos = 0x0    // Position of CCR1 field.
	TIMs_CCR1_CCR1_Msk = 0xffff // Bit mask of CCR1 field.

	// BDTR: break and dead-time register
	TIMs_BDTR_DTG_Pos  = 0x0     // Position of DTG field.
	TIMs_BDTR_DTG_Msk  = 0xff    // Bit mask of DTG field.
	TIMs_BDTR_LOCK_Pos = 0x8     // Position of LOCK field.
	TIMs_BDTR_LOCK_Msk = 0x300   // Bit mask of LOCK field.
	TIMs_BDTR_OSSI_Pos = 0xa     // Position of OSSI field.
	TIMs_BDTR_OSSI_Msk = 0x400   // Bit mask of OSSI field.
	TIMs_BDTR_OSSI     = 0x400   // Bit OSSI.
	TIMs_BDTR_OSSR_Pos = 0xb     // Position of OSSR field.
	TIMs_BDTR_OSSR_Msk = 0x800   // Bit mask of OSSR field.
	TIMs_BDTR_OSSR     = 0x800   // Bit OSSR.
	TIMs_BDTR_BKE_Pos  = 0xc     // Position of BKE field.
	TIMs_BDTR_BKE_Msk  = 0x1000  // Bit mask of BKE field.
	TIMs_BDTR_BKE      = 0x1000  // Bit BKE.
	TIMs_BDTR_BKP_Pos  = 0xd     // Position of BKP field.
	TIMs_BDTR_BKP_Msk  = 0x2000  // Bit mask of BKP field.
	TIMs_BDTR_BKP      = 0x2000  // Bit BKP.
	TIMs_BDTR_AOE_Pos  = 0xe     // Position of AOE field.
	TIMs_BDTR_AOE_Msk  = 0x4000  // Bit mask of AOE field.
	TIMs_BDTR_AOE      = 0x4000  // Bit AOE.
	TIMs_BDTR_MOE_Pos  = 0xf     // Position of MOE field.
	TIMs_BDTR_MOE_Msk  = 0x8000  // Bit mask of MOE field.
	TIMs_BDTR_MOE      = 0x8000  // Bit MOE.
	TIMs_BDTR_BKF_Pos  = 0x10    // Position of BKF field.
	TIMs_BDTR_BKF_Msk  = 0xf0000 // Bit mask of BKF field.

	// DCR: DMA control register
	TIMs_DCR_DBL_Pos = 0x8    // Position of DBL field.
	TIMs_DCR_DBL_Msk = 0x1f00 // Bit mask of DBL field.
	TIMs_DCR_DBA_Pos = 0x0    // Position of DBA field.
	TIMs_DCR_DBA_Msk = 0x1f   // Bit mask of DBA field.

	// DMAR: DMA address for full transfer
	TIMs_DMAR_DMAB_Pos = 0x0    // Position of DMAB field.
	TIMs_DMAR_DMAB_Msk = 0xffff // Bit mask of DMAB field.

	// TIM16_AF1: TIM16 alternate function register           1
	TIMs_TIM16_AF1_BKINE_Pos    = 0x0   // Position of BKINE field.
	TIMs_TIM16_AF1_BKINE_Msk    = 0x1   // Bit mask of BKINE field.
	TIMs_TIM16_AF1_BKINE        = 0x1   // Bit BKINE.
	TIMs_TIM16_AF1_BKCMP1E_Pos  = 0x1   // Position of BKCMP1E field.
	TIMs_TIM16_AF1_BKCMP1E_Msk  = 0x2   // Bit mask of BKCMP1E field.
	TIMs_TIM16_AF1_BKCMP1E      = 0x2   // Bit BKCMP1E.
	TIMs_TIM16_AF1_BKCMP2E_Pos  = 0x2   // Position of BKCMP2E field.
	TIMs_TIM16_AF1_BKCMP2E_Msk  = 0x4   // Bit mask of BKCMP2E field.
	TIMs_TIM16_AF1_BKCMP2E      = 0x4   // Bit BKCMP2E.
	TIMs_TIM16_AF1_BKDFBK1E_Pos = 0x8   // Position of BKDFBK1E field.
	TIMs_TIM16_AF1_BKDFBK1E_Msk = 0x100 // Bit mask of BKDFBK1E field.
	TIMs_TIM16_AF1_BKDFBK1E     = 0x100 // Bit BKDFBK1E.
	TIMs_TIM16_AF1_BKINP_Pos    = 0x9   // Position of BKINP field.
	TIMs_TIM16_AF1_BKINP_Msk    = 0x200 // Bit mask of BKINP field.
	TIMs_TIM16_AF1_BKINP        = 0x200 // Bit BKINP.
	TIMs_TIM16_AF1_BKCMP1P_Pos  = 0xa   // Position of BKCMP1P field.
	TIMs_TIM16_AF1_BKCMP1P_Msk  = 0x400 // Bit mask of BKCMP1P field.
	TIMs_TIM16_AF1_BKCMP1P      = 0x400 // Bit BKCMP1P.
	TIMs_TIM16_AF1_BKCMP2P_Pos  = 0xb   // Position of BKCMP2P field.
	TIMs_TIM16_AF1_BKCMP2P_Msk  = 0x800 // Bit mask of BKCMP2P field.
	TIMs_TIM16_AF1_BKCMP2P      = 0x800 // Bit BKCMP2P.

	// TIM16_TISEL: TIM16 input selection register
	TIMs_TIM16_TISEL_TI1SEL_Pos = 0x0 // Position of TI1SEL field.
	TIMs_TIM16_TISEL_TI1SEL_Msk = 0xf // Bit mask of TI1SEL field.
)

// Bitfields for USART1: Universal synchronous asynchronous receiver transmitter
const (
	// CR1: Control register 1
	USART_CR1_RXFFIE_Pos = 0x1f       // Position of RXFFIE field.
	USART_CR1_RXFFIE_Msk = 0x80000000 // Bit mask of RXFFIE field.
	USART_CR1_RXFFIE     = 0x80000000 // Bit RXFFIE.
	USART_CR1_TXFEIE_Pos = 0x1e       // Position of TXFEIE field.
	USART_CR1_TXFEIE_Msk = 0x40000000 // Bit mask of TXFEIE field.
	USART_CR1_TXFEIE     = 0x40000000 // Bit TXFEIE.
	USART_CR1_FIFOEN_Pos = 0x1d       // Position of FIFOEN field.
	USART_CR1_FIFOEN_Msk = 0x20000000 // Bit mask of FIFOEN field.
	USART_CR1_FIFOEN     = 0x20000000 // Bit FIFOEN.
	USART_CR1_M1_Pos     = 0x1c       // Position of M1 field.
	USART_CR1_M1_Msk     = 0x10000000 // Bit mask of M1 field.
	USART_CR1_M1         = 0x10000000 // Bit M1.
	USART_CR1_EOBIE_Pos  = 0x1b       // Position of EOBIE field.
	USART_CR1_EOBIE_Msk  = 0x8000000  // Bit mask of EOBIE field.
	USART_CR1_EOBIE      = 0x8000000  // Bit EOBIE.
	USART_CR1_RTOIE_Pos  = 0x1a       // Position of RTOIE field.
	USART_CR1_RTOIE_Msk  = 0x4000000  // Bit mask of RTOIE field.
	USART_CR1_RTOIE      = 0x4000000  // Bit RTOIE.
	USART_CR1_DEAT4_Pos  = 0x19       // Position of DEAT4 field.
	USART_CR1_DEAT4_Msk  = 0x2000000  // Bit mask of DEAT4 field.
	USART_CR1_DEAT4      = 0x2000000  // Bit DEAT4.
	USART_CR1_DEAT3_Pos  = 0x18       // Position of DEAT3 field.
	USART_CR1_DEAT3_Msk  = 0x1000000  // Bit mask of DEAT3 field.
	USART_CR1_DEAT3      = 0x1000000  // Bit DEAT3.
	USART_CR1_DEAT2_Pos  = 0x17       // Position of DEAT2 field.
	USART_CR1_DEAT2_Msk  = 0x800000   // Bit mask of DEAT2 field.
	USART_CR1_DEAT2      = 0x800000   // Bit DEAT2.
	USART_CR1_DEAT1_Pos  = 0x16       // Position of DEAT1 field.
	USART_CR1_DEAT1_Msk  = 0x400000   // Bit mask of DEAT1 field.
	USART_CR1_DEAT1      = 0x400000   // Bit DEAT1.
	USART_CR1_DEAT0_Pos  = 0x15       // Position of DEAT0 field.
	USART_CR1_DEAT0_Msk  = 0x200000   // Bit mask of DEAT0 field.
	USART_CR1_DEAT0      = 0x200000   // Bit DEAT0.
	USART_CR1_DEDT4_Pos  = 0x14       // Position of DEDT4 field.
	USART_CR1_DEDT4_Msk  = 0x100000   // Bit mask of DEDT4 field.
	USART_CR1_DEDT4      = 0x100000   // Bit DEDT4.
	USART_CR1_DEDT3_Pos  = 0x13       // Position of DEDT3 field.
	USART_CR1_DEDT3_Msk  = 0x80000    // Bit mask of DEDT3 field.
	USART_CR1_DEDT3      = 0x80000    // Bit DEDT3.
	USART_CR1_DEDT2_Pos  = 0x12       // Position of DEDT2 field.
	USART_CR1_DEDT2_Msk  = 0x40000    // Bit mask of DEDT2 field.
	USART_CR1_DEDT2      = 0x40000    // Bit DEDT2.
	USART_CR1_DEDT1_Pos  = 0x11       // Position of DEDT1 field.
	USART_CR1_DEDT1_Msk  = 0x20000    // Bit mask of DEDT1 field.
	USART_CR1_DEDT1      = 0x20000    // Bit DEDT1.
	USART_CR1_DEDT0_Pos  = 0x10       // Position of DEDT0 field.
	USART_CR1_DEDT0_Msk  = 0x10000    // Bit mask of DEDT0 field.
	USART_CR1_DEDT0      = 0x10000    // Bit DEDT0.
	USART_CR1_OVER8_Pos  = 0xf        // Position of OVER8 field.
	USART_CR1_OVER8_Msk  = 0x8000     // Bit mask of OVER8 field.
	USART_CR1_OVER8      = 0x8000     // Bit OVER8.
	USART_CR1_CMIE_Pos   = 0xe        // Position of CMIE field.
	USART_CR1_CMIE_Msk   = 0x4000     // Bit mask of CMIE field.
	USART_CR1_CMIE       = 0x4000     // Bit CMIE.
	USART_CR1_MME_Pos    = 0xd        // Position of MME field.
	USART_CR1_MME_Msk    = 0x2000     // Bit mask of MME field.
	USART_CR1_MME        = 0x2000     // Bit MME.
	USART_CR1_M0_Pos     = 0xc        // Position of M0 field.
	USART_CR1_M0_Msk     = 0x1000     // Bit mask of M0 field.
	USART_CR1_M0         = 0x1000     // Bit M0.
	USART_CR1_WAKE_Pos   = 0xb        // Position of WAKE field.
	USART_CR1_WAKE_Msk   = 0x800      // Bit mask of WAKE field.
	USART_CR1_WAKE       = 0x800      // Bit WAKE.
	USART_CR1_PCE_Pos    = 0xa        // Position of PCE field.
	USART_CR1_PCE_Msk    = 0x400      // Bit mask of PCE field.
	USART_CR1_PCE        = 0x400      // Bit PCE.
	USART_CR1_PS_Pos     = 0x9        // Position of PS field.
	USART_CR1_PS_Msk     = 0x200      // Bit mask of PS field.
	USART_CR1_PS         = 0x200      // Bit PS.
	USART_CR1_PEIE_Pos   = 0x8        // Position of PEIE field.
	USART_CR1_PEIE_Msk   = 0x100      // Bit mask of PEIE field.
	USART_CR1_PEIE       = 0x100      // Bit PEIE.
	USART_CR1_TXEIE_Pos  = 0x7        // Position of TXEIE field.
	USART_CR1_TXEIE_Msk  = 0x80       // Bit mask of TXEIE field.
	USART_CR1_TXEIE      = 0x80       // Bit TXEIE.
	USART_CR1_TCIE_Pos   = 0x6        // Position of TCIE field.
	USART_CR1_TCIE_Msk   = 0x40       // Bit mask of TCIE field.
	USART_CR1_TCIE       = 0x40       // Bit TCIE.
	USART_CR1_RXNEIE_Pos = 0x5        // Position of RXNEIE field.
	USART_CR1_RXNEIE_Msk = 0x20       // Bit mask of RXNEIE field.
	USART_CR1_RXNEIE     = 0x20       // Bit RXNEIE.
	USART_CR1_IDLEIE_Pos = 0x4        // Position of IDLEIE field.
	USART_CR1_IDLEIE_Msk = 0x10       // Bit mask of IDLEIE field.
	USART_CR1_IDLEIE     = 0x10       // Bit IDLEIE.
	USART_CR1_TE_Pos     = 0x3        // Position of TE field.
	USART_CR1_TE_Msk     = 0x8        // Bit mask of TE field.
	USART_CR1_TE         = 0x8        // Bit TE.
	USART_CR1_RE_Pos     = 0x2        // Position of RE field.
	USART_CR1_RE_Msk     = 0x4        // Bit mask of RE field.
	USART_CR1_RE         = 0x4        // Bit RE.
	USART_CR1_UESM_Pos   = 0x1        // Position of UESM field.
	USART_CR1_UESM_Msk   = 0x2        // Bit mask of UESM field.
	USART_CR1_UESM       = 0x2        // Bit UESM.
	USART_CR1_UE_Pos     = 0x0        // Position of UE field.
	USART_CR1_UE_Msk     = 0x1        // Bit mask of UE field.
	USART_CR1_UE         = 0x1        // Bit UE.

	// CR2: Control register 2
	USART_CR2_ADD4_7_Pos   = 0x1c       // Position of ADD4_7 field.
	USART_CR2_ADD4_7_Msk   = 0xf0000000 // Bit mask of ADD4_7 field.
	USART_CR2_ADD0_3_Pos   = 0x18       // Position of ADD0_3 field.
	USART_CR2_ADD0_3_Msk   = 0xf000000  // Bit mask of ADD0_3 field.
	USART_CR2_RTOEN_Pos    = 0x17       // Position of RTOEN field.
	USART_CR2_RTOEN_Msk    = 0x800000   // Bit mask of RTOEN field.
	USART_CR2_RTOEN        = 0x800000   // Bit RTOEN.
	USART_CR2_ABRMOD1_Pos  = 0x16       // Position of ABRMOD1 field.
	USART_CR2_ABRMOD1_Msk  = 0x400000   // Bit mask of ABRMOD1 field.
	USART_CR2_ABRMOD1      = 0x400000   // Bit ABRMOD1.
	USART_CR2_ABRMOD0_Pos  = 0x15       // Position of ABRMOD0 field.
	USART_CR2_ABRMOD0_Msk  = 0x200000   // Bit mask of ABRMOD0 field.
	USART_CR2_ABRMOD0      = 0x200000   // Bit ABRMOD0.
	USART_CR2_ABREN_Pos    = 0x14       // Position of ABREN field.
	USART_CR2_ABREN_Msk    = 0x100000   // Bit mask of ABREN field.
	USART_CR2_ABREN        = 0x100000   // Bit ABREN.
	USART_CR2_MSBFIRST_Pos = 0x13       // Position of MSBFIRST field.
	USART_CR2_MSBFIRST_Msk = 0x80000    // Bit mask of MSBFIRST field.
	USART_CR2_MSBFIRST     = 0x80000    // Bit MSBFIRST.
	USART_CR2_TAINV_Pos    = 0x12       // Position of TAINV field.
	USART_CR2_TAINV_Msk    = 0x40000    // Bit mask of TAINV field.
	USART_CR2_TAINV        = 0x40000    // Bit TAINV.
	USART_CR2_TXINV_Pos    = 0x11       // Position of TXINV field.
	USART_CR2_TXINV_Msk    = 0x20000    // Bit mask of TXINV field.
	USART_CR2_TXINV        = 0x20000    // Bit TXINV.
	USART_CR2_RXINV_Pos    = 0x10       // Position of RXINV field.
	USART_CR2_RXINV_Msk    = 0x10000    // Bit mask of RXINV field.
	USART_CR2_RXINV        = 0x10000    // Bit RXINV.
	USART_CR2_SWAP_Pos     = 0xf        // Position of SWAP field.
	USART_CR2_SWAP_Msk     = 0x8000     // Bit mask of SWAP field.
	USART_CR2_SWAP         = 0x8000     // Bit SWAP.
	USART_CR2_LINEN_Pos    = 0xe        // Position of LINEN field.
	USART_CR2_LINEN_Msk    = 0x4000     // Bit mask of LINEN field.
	USART_CR2_LINEN        = 0x4000     // Bit LINEN.
	USART_CR2_STOP_Pos     = 0xc        // Position of STOP field.
	USART_CR2_STOP_Msk     = 0x3000     // Bit mask of STOP field.
	USART_CR2_CLKEN_Pos    = 0xb        // Position of CLKEN field.
	USART_CR2_CLKEN_Msk    = 0x800      // Bit mask of CLKEN field.
	USART_CR2_CLKEN        = 0x800      // Bit CLKEN.
	USART_CR2_CPOL_Pos     = 0xa        // Position of CPOL field.
	USART_CR2_CPOL_Msk     = 0x400      // Bit mask of CPOL field.
	USART_CR2_CPOL         = 0x400      // Bit CPOL.
	USART_CR2_CPHA_Pos     = 0x9        // Position of CPHA field.
	USART_CR2_CPHA_Msk     = 0x200      // Bit mask of CPHA field.
	USART_CR2_CPHA         = 0x200      // Bit CPHA.
	USART_CR2_LBCL_Pos     = 0x8        // Position of LBCL field.
	USART_CR2_LBCL_Msk     = 0x100      // Bit mask of LBCL field.
	USART_CR2_LBCL         = 0x100      // Bit LBCL.
	USART_CR2_LBDIE_Pos    = 0x6        // Position of LBDIE field.
	USART_CR2_LBDIE_Msk    = 0x40       // Bit mask of LBDIE field.
	USART_CR2_LBDIE        = 0x40       // Bit LBDIE.
	USART_CR2_LBDL_Pos     = 0x5        // Position of LBDL field.
	USART_CR2_LBDL_Msk     = 0x20       // Bit mask of LBDL field.
	USART_CR2_LBDL         = 0x20       // Bit LBDL.
	USART_CR2_ADDM7_Pos    = 0x4        // Position of ADDM7 field.
	USART_CR2_ADDM7_Msk    = 0x10       // Bit mask of ADDM7 field.
	USART_CR2_ADDM7        = 0x10       // Bit ADDM7.
	USART_CR2_DIS_NSS_Pos  = 0x3        // Position of DIS_NSS field.
	USART_CR2_DIS_NSS_Msk  = 0x8        // Bit mask of DIS_NSS field.
	USART_CR2_DIS_NSS      = 0x8        // Bit DIS_NSS.
	USART_CR2_SLVEN_Pos    = 0x0        // Position of SLVEN field.
	USART_CR2_SLVEN_Msk    = 0x1        // Bit mask of SLVEN field.
	USART_CR2_SLVEN        = 0x1        // Bit SLVEN.

	// CR3: Control register 3
	USART_CR3_TXFTCFG_Pos = 0x1d       // Position of TXFTCFG field.
	USART_CR3_TXFTCFG_Msk = 0xe0000000 // Bit mask of TXFTCFG field.
	USART_CR3_RXFTIE_Pos  = 0x1c       // Position of RXFTIE field.
	USART_CR3_RXFTIE_Msk  = 0x10000000 // Bit mask of RXFTIE field.
	USART_CR3_RXFTIE      = 0x10000000 // Bit RXFTIE.
	USART_CR3_RXFTCFG_Pos = 0x19       // Position of RXFTCFG field.
	USART_CR3_RXFTCFG_Msk = 0xe000000  // Bit mask of RXFTCFG field.
	USART_CR3_TCBGTIE_Pos = 0x18       // Position of TCBGTIE field.
	USART_CR3_TCBGTIE_Msk = 0x1000000  // Bit mask of TCBGTIE field.
	USART_CR3_TCBGTIE     = 0x1000000  // Bit TCBGTIE.
	USART_CR3_TXFTIE_Pos  = 0x17       // Position of TXFTIE field.
	USART_CR3_TXFTIE_Msk  = 0x800000   // Bit mask of TXFTIE field.
	USART_CR3_TXFTIE      = 0x800000   // Bit TXFTIE.
	USART_CR3_WUFIE_Pos   = 0x16       // Position of WUFIE field.
	USART_CR3_WUFIE_Msk   = 0x400000   // Bit mask of WUFIE field.
	USART_CR3_WUFIE       = 0x400000   // Bit WUFIE.
	USART_CR3_WUS_Pos     = 0x14       // Position of WUS field.
	USART_CR3_WUS_Msk     = 0x300000   // Bit mask of WUS field.
	USART_CR3_SCARCNT_Pos = 0x11       // Position of SCARCNT field.
	USART_CR3_SCARCNT_Msk = 0xe0000    // Bit mask of SCARCNT field.
	USART_CR3_DEP_Pos     = 0xf        // Position of DEP field.
	USART_CR3_DEP_Msk     = 0x8000     // Bit mask of DEP field.
	USART_CR3_DEP         = 0x8000     // Bit DEP.
	USART_CR3_DEM_Pos     = 0xe        // Position of DEM field.
	USART_CR3_DEM_Msk     = 0x4000     // Bit mask of DEM field.
	USART_CR3_DEM         = 0x4000     // Bit DEM.
	USART_CR3_DDRE_Pos    = 0xd        // Position of DDRE field.
	USART_CR3_DDRE_Msk    = 0x2000     // Bit mask of DDRE field.
	USART_CR3_DDRE        = 0x2000     // Bit DDRE.
	USART_CR3_OVRDIS_Pos  = 0xc        // Position of OVRDIS field.
	USART_CR3_OVRDIS_Msk  = 0x1000     // Bit mask of OVRDIS field.
	USART_CR3_OVRDIS      = 0x1000     // Bit OVRDIS.
	USART_CR3_ONEBIT_Pos  = 0xb        // Position of ONEBIT field.
	USART_CR3_ONEBIT_Msk  = 0x800      // Bit mask of ONEBIT field.
	USART_CR3_ONEBIT      = 0x800      // Bit ONEBIT.
	USART_CR3_CTSIE_Pos   = 0xa        // Position of CTSIE field.
	USART_CR3_CTSIE_Msk   = 0x400      // Bit mask of CTSIE field.
	USART_CR3_CTSIE       = 0x400      // Bit CTSIE.
	USART_CR3_CTSE_Pos    = 0x9        // Position of CTSE field.
	USART_CR3_CTSE_Msk    = 0x200      // Bit mask of CTSE field.
	USART_CR3_CTSE        = 0x200      // Bit CTSE.
	USART_CR3_RTSE_Pos    = 0x8        // Position of RTSE field.
	USART_CR3_RTSE_Msk    = 0x100      // Bit mask of RTSE field.
	USART_CR3_RTSE        = 0x100      // Bit RTSE.
	USART_CR3_DMAT_Pos    = 0x7        // Position of DMAT field.
	USART_CR3_DMAT_Msk    = 0x80       // Bit mask of DMAT field.
	USART_CR3_DMAT        = 0x80       // Bit DMAT.
	USART_CR3_DMAR_Pos    = 0x6        // Position of DMAR field.
	USART_CR3_DMAR_Msk    = 0x40       // Bit mask of DMAR field.
	USART_CR3_DMAR        = 0x40       // Bit DMAR.
	USART_CR3_SCEN_Pos    = 0x5        // Position of SCEN field.
	USART_CR3_SCEN_Msk    = 0x20       // Bit mask of SCEN field.
	USART_CR3_SCEN        = 0x20       // Bit SCEN.
	USART_CR3_NACK_Pos    = 0x4        // Position of NACK field.
	USART_CR3_NACK_Msk    = 0x10       // Bit mask of NACK field.
	USART_CR3_NACK        = 0x10       // Bit NACK.
	USART_CR3_HDSEL_Pos   = 0x3        // Position of HDSEL field.
	USART_CR3_HDSEL_Msk   = 0x8        // Bit mask of HDSEL field.
	USART_CR3_HDSEL       = 0x8        // Bit HDSEL.
	USART_CR3_IRLP_Pos    = 0x2        // Position of IRLP field.
	USART_CR3_IRLP_Msk    = 0x4        // Bit mask of IRLP field.
	USART_CR3_IRLP        = 0x4        // Bit IRLP.
	USART_CR3_IREN_Pos    = 0x1        // Position of IREN field.
	USART_CR3_IREN_Msk    = 0x2        // Bit mask of IREN field.
	USART_CR3_IREN        = 0x2        // Bit IREN.
	USART_CR3_EIE_Pos     = 0x0        // Position of EIE field.
	USART_CR3_EIE_Msk     = 0x1        // Bit mask of EIE field.
	USART_CR3_EIE         = 0x1        // Bit EIE.

	// BRR: Baud rate register
	USART_BRR_BRR_4_15_Pos = 0x4    // Position of BRR_4_15 field.
	USART_BRR_BRR_4_15_Msk = 0xfff0 // Bit mask of BRR_4_15 field.
	USART_BRR_BRR_0_3_Pos  = 0x0    // Position of BRR_0_3 field.
	USART_BRR_BRR_0_3_Msk  = 0xf    // Bit mask of BRR_0_3 field.

	// GTPR: Guard time and prescaler           register
	USART_GTPR_GT_Pos  = 0x8    // Position of GT field.
	USART_GTPR_GT_Msk  = 0xff00 // Bit mask of GT field.
	USART_GTPR_PSC_Pos = 0x0    // Position of PSC field.
	USART_GTPR_PSC_Msk = 0xff   // Bit mask of PSC field.

	// RTOR: Receiver timeout register
	USART_RTOR_BLEN_Pos = 0x18       // Position of BLEN field.
	USART_RTOR_BLEN_Msk = 0xff000000 // Bit mask of BLEN field.
	USART_RTOR_RTO_Pos  = 0x0        // Position of RTO field.
	USART_RTOR_RTO_Msk  = 0xffffff   // Bit mask of RTO field.

	// RQR: Request register
	USART_RQR_TXFRQ_Pos = 0x4  // Position of TXFRQ field.
	USART_RQR_TXFRQ_Msk = 0x10 // Bit mask of TXFRQ field.
	USART_RQR_TXFRQ     = 0x10 // Bit TXFRQ.
	USART_RQR_RXFRQ_Pos = 0x3  // Position of RXFRQ field.
	USART_RQR_RXFRQ_Msk = 0x8  // Bit mask of RXFRQ field.
	USART_RQR_RXFRQ     = 0x8  // Bit RXFRQ.
	USART_RQR_MMRQ_Pos  = 0x2  // Position of MMRQ field.
	USART_RQR_MMRQ_Msk  = 0x4  // Bit mask of MMRQ field.
	USART_RQR_MMRQ      = 0x4  // Bit MMRQ.
	USART_RQR_SBKRQ_Pos = 0x1  // Position of SBKRQ field.
	USART_RQR_SBKRQ_Msk = 0x2  // Bit mask of SBKRQ field.
	USART_RQR_SBKRQ     = 0x2  // Bit SBKRQ.
	USART_RQR_ABRRQ_Pos = 0x0  // Position of ABRRQ field.
	USART_RQR_ABRRQ_Msk = 0x1  // Bit mask of ABRRQ field.
	USART_RQR_ABRRQ     = 0x1  // Bit ABRRQ.

	// ISR: Interrupt & status           register
	USART_ISR_TXFT_Pos  = 0x1b      // Position of TXFT field.
	USART_ISR_TXFT_Msk  = 0x8000000 // Bit mask of TXFT field.
	USART_ISR_TXFT      = 0x8000000 // Bit TXFT.
	USART_ISR_RXFT_Pos  = 0x1a      // Position of RXFT field.
	USART_ISR_RXFT_Msk  = 0x4000000 // Bit mask of RXFT field.
	USART_ISR_RXFT      = 0x4000000 // Bit RXFT.
	USART_ISR_TCBGT_Pos = 0x19      // Position of TCBGT field.
	USART_ISR_TCBGT_Msk = 0x2000000 // Bit mask of TCBGT field.
	USART_ISR_TCBGT     = 0x2000000 // Bit TCBGT.
	USART_ISR_RXFF_Pos  = 0x18      // Position of RXFF field.
	USART_ISR_RXFF_Msk  = 0x1000000 // Bit mask of RXFF field.
	USART_ISR_RXFF      = 0x1000000 // Bit RXFF.
	USART_ISR_TXFE_Pos  = 0x17      // Position of TXFE field.
	USART_ISR_TXFE_Msk  = 0x800000  // Bit mask of TXFE field.
	USART_ISR_TXFE      = 0x800000  // Bit TXFE.
	USART_ISR_REACK_Pos = 0x16      // Position of REACK field.
	USART_ISR_REACK_Msk = 0x400000  // Bit mask of REACK field.
	USART_ISR_REACK     = 0x400000  // Bit REACK.
	USART_ISR_TEACK_Pos = 0x15      // Position of TEACK field.
	USART_ISR_TEACK_Msk = 0x200000  // Bit mask of TEACK field.
	USART_ISR_TEACK     = 0x200000  // Bit TEACK.
	USART_ISR_WUF_Pos   = 0x14      // Position of WUF field.
	USART_ISR_WUF_Msk   = 0x100000  // Bit mask of WUF field.
	USART_ISR_WUF       = 0x100000  // Bit WUF.
	USART_ISR_RWU_Pos   = 0x13      // Position of RWU field.
	USART_ISR_RWU_Msk   = 0x80000   // Bit mask of RWU field.
	USART_ISR_RWU       = 0x80000   // Bit RWU.
	USART_ISR_SBKF_Pos  = 0x12      // Position of SBKF field.
	USART_ISR_SBKF_Msk  = 0x40000   // Bit mask of SBKF field.
	USART_ISR_SBKF      = 0x40000   // Bit SBKF.
	USART_ISR_CMF_Pos   = 0x11      // Position of CMF field.
	USART_ISR_CMF_Msk   = 0x20000   // Bit mask of CMF field.
	USART_ISR_CMF       = 0x20000   // Bit CMF.
	USART_ISR_BUSY_Pos  = 0x10      // Position of BUSY field.
	USART_ISR_BUSY_Msk  = 0x10000   // Bit mask of BUSY field.
	USART_ISR_BUSY      = 0x10000   // Bit BUSY.
	USART_ISR_ABRF_Pos  = 0xf       // Position of ABRF field.
	USART_ISR_ABRF_Msk  = 0x8000    // Bit mask of ABRF field.
	USART_ISR_ABRF      = 0x8000    // Bit ABRF.
	USART_ISR_ABRE_Pos  = 0xe       // Position of ABRE field.
	USART_ISR_ABRE_Msk  = 0x4000    // Bit mask of ABRE field.
	USART_ISR_ABRE      = 0x4000    // Bit ABRE.
	USART_ISR_UDR_Pos   = 0xd       // Position of UDR field.
	USART_ISR_UDR_Msk   = 0x2000    // Bit mask of UDR field.
	USART_ISR_UDR       = 0x2000    // Bit UDR.
	USART_ISR_EOBF_Pos  = 0xc       // Position of EOBF field.
	USART_ISR_EOBF_Msk  = 0x1000    // Bit mask of EOBF field.
	USART_ISR_EOBF      = 0x1000    // Bit EOBF.
	USART_ISR_RTOF_Pos  = 0xb       // Position of RTOF field.
	USART_ISR_RTOF_Msk  = 0x800     // Bit mask of RTOF field.
	USART_ISR_RTOF      = 0x800     // Bit RTOF.
	USART_ISR_CTS_Pos   = 0xa       // Position of CTS field.
	USART_ISR_CTS_Msk   = 0x400     // Bit mask of CTS field.
	USART_ISR_CTS       = 0x400     // Bit CTS.
	USART_ISR_CTSIF_Pos = 0x9       // Position of CTSIF field.
	USART_ISR_CTSIF_Msk = 0x200     // Bit mask of CTSIF field.
	USART_ISR_CTSIF     = 0x200     // Bit CTSIF.
	USART_ISR_LBDF_Pos  = 0x8       // Position of LBDF field.
	USART_ISR_LBDF_Msk  = 0x100     // Bit mask of LBDF field.
	USART_ISR_LBDF      = 0x100     // Bit LBDF.
	USART_ISR_TXE_Pos   = 0x7       // Position of TXE field.
	USART_ISR_TXE_Msk   = 0x80      // Bit mask of TXE field.
	USART_ISR_TXE       = 0x80      // Bit TXE.
	USART_ISR_TC_Pos    = 0x6       // Position of TC field.
	USART_ISR_TC_Msk    = 0x40      // Bit mask of TC field.
	USART_ISR_TC        = 0x40      // Bit TC.
	USART_ISR_RXNE_Pos  = 0x5       // Position of RXNE field.
	USART_ISR_RXNE_Msk  = 0x20      // Bit mask of RXNE field.
	USART_ISR_RXNE      = 0x20      // Bit RXNE.
	USART_ISR_IDLE_Pos  = 0x4       // Position of IDLE field.
	USART_ISR_IDLE_Msk  = 0x10      // Bit mask of IDLE field.
	USART_ISR_IDLE      = 0x10      // Bit IDLE.
	USART_ISR_ORE_Pos   = 0x3       // Position of ORE field.
	USART_ISR_ORE_Msk   = 0x8       // Bit mask of ORE field.
	USART_ISR_ORE       = 0x8       // Bit ORE.
	USART_ISR_NF_Pos    = 0x2       // Position of NF field.
	USART_ISR_NF_Msk    = 0x4       // Bit mask of NF field.
	USART_ISR_NF        = 0x4       // Bit NF.
	USART_ISR_FE_Pos    = 0x1       // Position of FE field.
	USART_ISR_FE_Msk    = 0x2       // Bit mask of FE field.
	USART_ISR_FE        = 0x2       // Bit FE.
	USART_ISR_PE_Pos    = 0x0       // Position of PE field.
	USART_ISR_PE_Msk    = 0x1       // Bit mask of PE field.
	USART_ISR_PE        = 0x1       // Bit PE.

	// ICR: Interrupt flag clear register
	USART_ICR_WUCF_Pos   = 0x14     // Position of WUCF field.
	USART_ICR_WUCF_Msk   = 0x100000 // Bit mask of WUCF field.
	USART_ICR_WUCF       = 0x100000 // Bit WUCF.
	USART_ICR_CMCF_Pos   = 0x11     // Position of CMCF field.
	USART_ICR_CMCF_Msk   = 0x20000  // Bit mask of CMCF field.
	USART_ICR_CMCF       = 0x20000  // Bit CMCF.
	USART_ICR_UDRCF_Pos  = 0xd      // Position of UDRCF field.
	USART_ICR_UDRCF_Msk  = 0x2000   // Bit mask of UDRCF field.
	USART_ICR_UDRCF      = 0x2000   // Bit UDRCF.
	USART_ICR_EOBCF_Pos  = 0xc      // Position of EOBCF field.
	USART_ICR_EOBCF_Msk  = 0x1000   // Bit mask of EOBCF field.
	USART_ICR_EOBCF      = 0x1000   // Bit EOBCF.
	USART_ICR_RTOCF_Pos  = 0xb      // Position of RTOCF field.
	USART_ICR_RTOCF_Msk  = 0x800    // Bit mask of RTOCF field.
	USART_ICR_RTOCF      = 0x800    // Bit RTOCF.
	USART_ICR_CTSCF_Pos  = 0x9      // Position of CTSCF field.
	USART_ICR_CTSCF_Msk  = 0x200    // Bit mask of CTSCF field.
	USART_ICR_CTSCF      = 0x200    // Bit CTSCF.
	USART_ICR_LBDCF_Pos  = 0x8      // Position of LBDCF field.
	USART_ICR_LBDCF_Msk  = 0x100    // Bit mask of LBDCF field.
	USART_ICR_LBDCF      = 0x100    // Bit LBDCF.
	USART_ICR_TCBGTC_Pos = 0x7      // Position of TCBGTC field.
	USART_ICR_TCBGTC_Msk = 0x80     // Bit mask of TCBGTC field.
	USART_ICR_TCBGTC     = 0x80     // Bit TCBGTC.
	USART_ICR_TCCF_Pos   = 0x6      // Position of TCCF field.
	USART_ICR_TCCF_Msk   = 0x40     // Bit mask of TCCF field.
	USART_ICR_TCCF       = 0x40     // Bit TCCF.
	USART_ICR_TXFECF_Pos = 0x5      // Position of TXFECF field.
	USART_ICR_TXFECF_Msk = 0x20     // Bit mask of TXFECF field.
	USART_ICR_TXFECF     = 0x20     // Bit TXFECF.
	USART_ICR_IDLECF_Pos = 0x4      // Position of IDLECF field.
	USART_ICR_IDLECF_Msk = 0x10     // Bit mask of IDLECF field.
	USART_ICR_IDLECF     = 0x10     // Bit IDLECF.
	USART_ICR_ORECF_Pos  = 0x3      // Position of ORECF field.
	USART_ICR_ORECF_Msk  = 0x8      // Bit mask of ORECF field.
	USART_ICR_ORECF      = 0x8      // Bit ORECF.
	USART_ICR_NCF_Pos    = 0x2      // Position of NCF field.
	USART_ICR_NCF_Msk    = 0x4      // Bit mask of NCF field.
	USART_ICR_NCF        = 0x4      // Bit NCF.
	USART_ICR_FECF_Pos   = 0x1      // Position of FECF field.
	USART_ICR_FECF_Msk   = 0x2      // Bit mask of FECF field.
	USART_ICR_FECF       = 0x2      // Bit FECF.
	USART_ICR_PECF_Pos   = 0x0      // Position of PECF field.
	USART_ICR_PECF_Msk   = 0x1      // Bit mask of PECF field.
	USART_ICR_PECF       = 0x1      // Bit PECF.

	// RDR: Receive data register
	USART_RDR_RDR_Pos = 0x0   // Position of RDR field.
	USART_RDR_RDR_Msk = 0x1ff // Bit mask of RDR field.

	// TDR: Transmit data register
	USART_TDR_TDR_Pos = 0x0   // Position of TDR field.
	USART_TDR_TDR_Msk = 0x1ff // Bit mask of TDR field.

	// PRESC: USART prescaler register
	USART_PRESC_PRESCALER_Pos = 0x0 // Position of PRESCALER field.
	USART_PRESC_PRESCALER_Msk = 0xf // Bit mask of PRESCALER field.
)

// Bitfields for TIM1: Advanced-timers
const (
	// CR1: control register 1
	TIM_CR1_CEN_Pos      = 0x0   // Position of CEN field.
	TIM_CR1_CEN_Msk      = 0x1   // Bit mask of CEN field.
	TIM_CR1_CEN          = 0x1   // Bit CEN.
	TIM_CR1_UDIS_Pos     = 0x1   // Position of UDIS field.
	TIM_CR1_UDIS_Msk     = 0x2   // Bit mask of UDIS field.
	TIM_CR1_UDIS         = 0x2   // Bit UDIS.
	TIM_CR1_URS_Pos      = 0x2   // Position of URS field.
	TIM_CR1_URS_Msk      = 0x4   // Bit mask of URS field.
	TIM_CR1_URS          = 0x4   // Bit URS.
	TIM_CR1_OPM_Pos      = 0x3   // Position of OPM field.
	TIM_CR1_OPM_Msk      = 0x8   // Bit mask of OPM field.
	TIM_CR1_OPM          = 0x8   // Bit OPM.
	TIM_CR1_DIR_Pos      = 0x4   // Position of DIR field.
	TIM_CR1_DIR_Msk      = 0x10  // Bit mask of DIR field.
	TIM_CR1_DIR          = 0x10  // Bit DIR.
	TIM_CR1_CMS_Pos      = 0x5   // Position of CMS field.
	TIM_CR1_CMS_Msk      = 0x60  // Bit mask of CMS field.
	TIM_CR1_ARPE_Pos     = 0x7   // Position of ARPE field.
	TIM_CR1_ARPE_Msk     = 0x80  // Bit mask of ARPE field.
	TIM_CR1_ARPE         = 0x80  // Bit ARPE.
	TIM_CR1_CKD_Pos      = 0x8   // Position of CKD field.
	TIM_CR1_CKD_Msk      = 0x300 // Bit mask of CKD field.
	TIM_CR1_UIFREMAP_Pos = 0xb   // Position of UIFREMAP field.
	TIM_CR1_UIFREMAP_Msk = 0x800 // Bit mask of UIFREMAP field.
	TIM_CR1_UIFREMAP     = 0x800 // Bit UIFREMAP.

	// CR2: control register 2
	TIM_CR2_MMS2_Pos  = 0x14     // Position of MMS2 field.
	TIM_CR2_MMS2_Msk  = 0xf00000 // Bit mask of MMS2 field.
	TIM_CR2_OIS6_Pos  = 0x12     // Position of OIS6 field.
	TIM_CR2_OIS6_Msk  = 0x40000  // Bit mask of OIS6 field.
	TIM_CR2_OIS6      = 0x40000  // Bit OIS6.
	TIM_CR2_OIS5_Pos  = 0x10     // Position of OIS5 field.
	TIM_CR2_OIS5_Msk  = 0x10000  // Bit mask of OIS5 field.
	TIM_CR2_OIS5      = 0x10000  // Bit OIS5.
	TIM_CR2_OIS4_Pos  = 0xe      // Position of OIS4 field.
	TIM_CR2_OIS4_Msk  = 0x4000   // Bit mask of OIS4 field.
	TIM_CR2_OIS4      = 0x4000   // Bit OIS4.
	TIM_CR2_OIS3N_Pos = 0xd      // Position of OIS3N field.
	TIM_CR2_OIS3N_Msk = 0x2000   // Bit mask of OIS3N field.
	TIM_CR2_OIS3N     = 0x2000   // Bit OIS3N.
	TIM_CR2_OIS3_Pos  = 0xc      // Position of OIS3 field.
	TIM_CR2_OIS3_Msk  = 0x1000   // Bit mask of OIS3 field.
	TIM_CR2_OIS3      = 0x1000   // Bit OIS3.
	TIM_CR2_OIS2N_Pos = 0xb      // Position of OIS2N field.
	TIM_CR2_OIS2N_Msk = 0x800    // Bit mask of OIS2N field.
	TIM_CR2_OIS2N     = 0x800    // Bit OIS2N.
	TIM_CR2_OIS2_Pos  = 0xa      // Position of OIS2 field.
	TIM_CR2_OIS2_Msk  = 0x400    // Bit mask of OIS2 field.
	TIM_CR2_OIS2      = 0x400    // Bit OIS2.
	TIM_CR2_OIS1N_Pos = 0x9      // Position of OIS1N field.
	TIM_CR2_OIS1N_Msk = 0x200    // Bit mask of OIS1N field.
	TIM_CR2_OIS1N     = 0x200    // Bit OIS1N.
	TIM_CR2_OIS1_Pos  = 0x8      // Position of OIS1 field.
	TIM_CR2_OIS1_Msk  = 0x100    // Bit mask of OIS1 field.
	TIM_CR2_OIS1      = 0x100    // Bit OIS1.
	TIM_CR2_TI1S_Pos  = 0x7      // Position of TI1S field.
	TIM_CR2_TI1S_Msk  = 0x80     // Bit mask of TI1S field.
	TIM_CR2_TI1S      = 0x80     // Bit TI1S.
	TIM_CR2_MMS_Pos   = 0x4      // Position of MMS field.
	TIM_CR2_MMS_Msk   = 0x70     // Bit mask of MMS field.
	TIM_CR2_CCDS_Pos  = 0x3      // Position of CCDS field.
	TIM_CR2_CCDS_Msk  = 0x8      // Bit mask of CCDS field.
	TIM_CR2_CCDS      = 0x8      // Bit CCDS.
	TIM_CR2_CCUS_Pos  = 0x2      // Position of CCUS field.
	TIM_CR2_CCUS_Msk  = 0x4      // Bit mask of CCUS field.
	TIM_CR2_CCUS      = 0x4      // Bit CCUS.
	TIM_CR2_CCPC_Pos  = 0x0      // Position of CCPC field.
	TIM_CR2_CCPC_Msk  = 0x1      // Bit mask of CCPC field.
	TIM_CR2_CCPC      = 0x1      // Bit CCPC.

	// SMCR: slave mode control register
	TIM_SMCR_SMS_Pos    = 0x0      // Position of SMS field.
	TIM_SMCR_SMS_Msk    = 0x7      // Bit mask of SMS field.
	TIM_SMCR_TS_Pos     = 0x4      // Position of TS field.
	TIM_SMCR_TS_Msk     = 0x70     // Bit mask of TS field.
	TIM_SMCR_MSM_Pos    = 0x7      // Position of MSM field.
	TIM_SMCR_MSM_Msk    = 0x80     // Bit mask of MSM field.
	TIM_SMCR_MSM        = 0x80     // Bit MSM.
	TIM_SMCR_ETF_Pos    = 0x8      // Position of ETF field.
	TIM_SMCR_ETF_Msk    = 0xf00    // Bit mask of ETF field.
	TIM_SMCR_ETPS_Pos   = 0xc      // Position of ETPS field.
	TIM_SMCR_ETPS_Msk   = 0x3000   // Bit mask of ETPS field.
	TIM_SMCR_ECE_Pos    = 0xe      // Position of ECE field.
	TIM_SMCR_ECE_Msk    = 0x4000   // Bit mask of ECE field.
	TIM_SMCR_ECE        = 0x4000   // Bit ECE.
	TIM_SMCR_ETP_Pos    = 0xf      // Position of ETP field.
	TIM_SMCR_ETP_Msk    = 0x8000   // Bit mask of ETP field.
	TIM_SMCR_ETP        = 0x8000   // Bit ETP.
	TIM_SMCR_SMS_3_Pos  = 0x10     // Position of SMS_3 field.
	TIM_SMCR_SMS_3_Msk  = 0x10000  // Bit mask of SMS_3 field.
	TIM_SMCR_SMS_3      = 0x10000  // Bit SMS_3.
	TIM_SMCR_TS_4_3_Pos = 0x14     // Position of TS_4_3 field.
	TIM_SMCR_TS_4_3_Msk = 0x300000 // Bit mask of TS_4_3 field.

	// DIER: DMA/Interrupt enable register
	TIM_DIER_TDE_Pos   = 0xe    // Position of TDE field.
	TIM_DIER_TDE_Msk   = 0x4000 // Bit mask of TDE field.
	TIM_DIER_TDE       = 0x4000 // Bit TDE.
	TIM_DIER_COMDE_Pos = 0xd    // Position of COMDE field.
	TIM_DIER_COMDE_Msk = 0x2000 // Bit mask of COMDE field.
	TIM_DIER_COMDE     = 0x2000 // Bit COMDE.
	TIM_DIER_CC4DE_Pos = 0xc    // Position of CC4DE field.
	TIM_DIER_CC4DE_Msk = 0x1000 // Bit mask of CC4DE field.
	TIM_DIER_CC4DE     = 0x1000 // Bit CC4DE.
	TIM_DIER_CC3DE_Pos = 0xb    // Position of CC3DE field.
	TIM_DIER_CC3DE_Msk = 0x800  // Bit mask of CC3DE field.
	TIM_DIER_CC3DE     = 0x800  // Bit CC3DE.
	TIM_DIER_CC2DE_Pos = 0xa    // Position of CC2DE field.
	TIM_DIER_CC2DE_Msk = 0x400  // Bit mask of CC2DE field.
	TIM_DIER_CC2DE     = 0x400  // Bit CC2DE.
	TIM_DIER_CC1DE_Pos = 0x9    // Position of CC1DE field.
	TIM_DIER_CC1DE_Msk = 0x200  // Bit mask of CC1DE field.
	TIM_DIER_CC1DE     = 0x200  // Bit CC1DE.
	TIM_DIER_UDE_Pos   = 0x8    // Position of UDE field.
	TIM_DIER_UDE_Msk   = 0x100  // Bit mask of UDE field.
	TIM_DIER_UDE       = 0x100  // Bit UDE.
	TIM_DIER_TIE_Pos   = 0x6    // Position of TIE field.
	TIM_DIER_TIE_Msk   = 0x40   // Bit mask of TIE field.
	TIM_DIER_TIE       = 0x40   // Bit TIE.
	TIM_DIER_CC4IE_Pos = 0x4    // Position of CC4IE field.
	TIM_DIER_CC4IE_Msk = 0x10   // Bit mask of CC4IE field.
	TIM_DIER_CC4IE     = 0x10   // Bit CC4IE.
	TIM_DIER_CC3IE_Pos = 0x3    // Position of CC3IE field.
	TIM_DIER_CC3IE_Msk = 0x8    // Bit mask of CC3IE field.
	TIM_DIER_CC3IE     = 0x8    // Bit CC3IE.
	TIM_DIER_CC2IE_Pos = 0x2    // Position of CC2IE field.
	TIM_DIER_CC2IE_Msk = 0x4    // Bit mask of CC2IE field.
	TIM_DIER_CC2IE     = 0x4    // Bit CC2IE.
	TIM_DIER_CC1IE_Pos = 0x1    // Position of CC1IE field.
	TIM_DIER_CC1IE_Msk = 0x2    // Bit mask of CC1IE field.
	TIM_DIER_CC1IE     = 0x2    // Bit CC1IE.
	TIM_DIER_UIE_Pos   = 0x0    // Position of UIE field.
	TIM_DIER_UIE_Msk   = 0x1    // Bit mask of UIE field.
	TIM_DIER_UIE       = 0x1    // Bit UIE.
	TIM_DIER_BIE_Pos   = 0x7    // Position of BIE field.
	TIM_DIER_BIE_Msk   = 0x80   // Bit mask of BIE field.
	TIM_DIER_BIE       = 0x80   // Bit BIE.
	TIM_DIER_COMIE_Pos = 0x5    // Position of COMIE field.
	TIM_DIER_COMIE_Msk = 0x20   // Bit mask of COMIE field.
	TIM_DIER_COMIE     = 0x20   // Bit COMIE.

	// SR: status register
	TIM_SR_CC6IF_Pos = 0x11    // Position of CC6IF field.
	TIM_SR_CC6IF_Msk = 0x20000 // Bit mask of CC6IF field.
	TIM_SR_CC6IF     = 0x20000 // Bit CC6IF.
	TIM_SR_CC5IF_Pos = 0x10    // Position of CC5IF field.
	TIM_SR_CC5IF_Msk = 0x10000 // Bit mask of CC5IF field.
	TIM_SR_CC5IF     = 0x10000 // Bit CC5IF.
	TIM_SR_SBIF_Pos  = 0xd     // Position of SBIF field.
	TIM_SR_SBIF_Msk  = 0x2000  // Bit mask of SBIF field.
	TIM_SR_SBIF      = 0x2000  // Bit SBIF.
	TIM_SR_CC4OF_Pos = 0xc     // Position of CC4OF field.
	TIM_SR_CC4OF_Msk = 0x1000  // Bit mask of CC4OF field.
	TIM_SR_CC4OF     = 0x1000  // Bit CC4OF.
	TIM_SR_CC3OF_Pos = 0xb     // Position of CC3OF field.
	TIM_SR_CC3OF_Msk = 0x800   // Bit mask of CC3OF field.
	TIM_SR_CC3OF     = 0x800   // Bit CC3OF.
	TIM_SR_CC2OF_Pos = 0xa     // Position of CC2OF field.
	TIM_SR_CC2OF_Msk = 0x400   // Bit mask of CC2OF field.
	TIM_SR_CC2OF     = 0x400   // Bit CC2OF.
	TIM_SR_CC1OF_Pos = 0x9     // Position of CC1OF field.
	TIM_SR_CC1OF_Msk = 0x200   // Bit mask of CC1OF field.
	TIM_SR_CC1OF     = 0x200   // Bit CC1OF.
	TIM_SR_B2IF_Pos  = 0x8     // Position of B2IF field.
	TIM_SR_B2IF_Msk  = 0x100   // Bit mask of B2IF field.
	TIM_SR_B2IF      = 0x100   // Bit B2IF.
	TIM_SR_BIF_Pos   = 0x7     // Position of BIF field.
	TIM_SR_BIF_Msk   = 0x80    // Bit mask of BIF field.
	TIM_SR_BIF       = 0x80    // Bit BIF.
	TIM_SR_TIF_Pos   = 0x6     // Position of TIF field.
	TIM_SR_TIF_Msk   = 0x40    // Bit mask of TIF field.
	TIM_SR_TIF       = 0x40    // Bit TIF.
	TIM_SR_COMIF_Pos = 0x5     // Position of COMIF field.
	TIM_SR_COMIF_Msk = 0x20    // Bit mask of COMIF field.
	TIM_SR_COMIF     = 0x20    // Bit COMIF.
	TIM_SR_CC4IF_Pos = 0x4     // Position of CC4IF field.
	TIM_SR_CC4IF_Msk = 0x10    // Bit mask of CC4IF field.
	TIM_SR_CC4IF     = 0x10    // Bit CC4IF.
	TIM_SR_CC3IF_Pos = 0x3     // Position of CC3IF field.
	TIM_SR_CC3IF_Msk = 0x8     // Bit mask of CC3IF field.
	TIM_SR_CC3IF     = 0x8     // Bit CC3IF.
	TIM_SR_CC2IF_Pos = 0x2     // Position of CC2IF field.
	TIM_SR_CC2IF_Msk = 0x4     // Bit mask of CC2IF field.
	TIM_SR_CC2IF     = 0x4     // Bit CC2IF.
	TIM_SR_CC1IF_Pos = 0x1     // Position of CC1IF field.
	TIM_SR_CC1IF_Msk = 0x2     // Bit mask of CC1IF field.
	TIM_SR_CC1IF     = 0x2     // Bit CC1IF.
	TIM_SR_UIF_Pos   = 0x0     // Position of UIF field.
	TIM_SR_UIF_Msk   = 0x1     // Bit mask of UIF field.
	TIM_SR_UIF       = 0x1     // Bit UIF.

	// EGR: event generation register
	TIM_EGR_UG_Pos   = 0x0   // Position of UG field.
	TIM_EGR_UG_Msk   = 0x1   // Bit mask of UG field.
	TIM_EGR_UG       = 0x1   // Bit UG.
	TIM_EGR_CC1G_Pos = 0x1   // Position of CC1G field.
	TIM_EGR_CC1G_Msk = 0x2   // Bit mask of CC1G field.
	TIM_EGR_CC1G     = 0x2   // Bit CC1G.
	TIM_EGR_CC2G_Pos = 0x2   // Position of CC2G field.
	TIM_EGR_CC2G_Msk = 0x4   // Bit mask of CC2G field.
	TIM_EGR_CC2G     = 0x4   // Bit CC2G.
	TIM_EGR_CC3G_Pos = 0x3   // Position of CC3G field.
	TIM_EGR_CC3G_Msk = 0x8   // Bit mask of CC3G field.
	TIM_EGR_CC3G     = 0x8   // Bit CC3G.
	TIM_EGR_CC4G_Pos = 0x4   // Position of CC4G field.
	TIM_EGR_CC4G_Msk = 0x10  // Bit mask of CC4G field.
	TIM_EGR_CC4G     = 0x10  // Bit CC4G.
	TIM_EGR_COMG_Pos = 0x5   // Position of COMG field.
	TIM_EGR_COMG_Msk = 0x20  // Bit mask of COMG field.
	TIM_EGR_COMG     = 0x20  // Bit COMG.
	TIM_EGR_TG_Pos   = 0x6   // Position of TG field.
	TIM_EGR_TG_Msk   = 0x40  // Bit mask of TG field.
	TIM_EGR_TG       = 0x40  // Bit TG.
	TIM_EGR_BG_Pos   = 0x7   // Position of BG field.
	TIM_EGR_BG_Msk   = 0x80  // Bit mask of BG field.
	TIM_EGR_BG       = 0x80  // Bit BG.
	TIM_EGR_B2G_Pos  = 0x8   // Position of B2G field.
	TIM_EGR_B2G_Msk  = 0x100 // Bit mask of B2G field.
	TIM_EGR_B2G      = 0x100 // Bit B2G.

	// CCMR1_Output: capture/compare mode register 1 (output           mode)
	TIM_CCMR1_Output_CC1S_Pos   = 0x0       // Position of CC1S field.
	TIM_CCMR1_Output_CC1S_Msk   = 0x3       // Bit mask of CC1S field.
	TIM_CCMR1_Output_OC1FE_Pos  = 0x2       // Position of OC1FE field.
	TIM_CCMR1_Output_OC1FE_Msk  = 0x4       // Bit mask of OC1FE field.
	TIM_CCMR1_Output_OC1FE      = 0x4       // Bit OC1FE.
	TIM_CCMR1_Output_OC1PE_Pos  = 0x3       // Position of OC1PE field.
	TIM_CCMR1_Output_OC1PE_Msk  = 0x8       // Bit mask of OC1PE field.
	TIM_CCMR1_Output_OC1PE      = 0x8       // Bit OC1PE.
	TIM_CCMR1_Output_OC1M_Pos   = 0x4       // Position of OC1M field.
	TIM_CCMR1_Output_OC1M_Msk   = 0x70      // Bit mask of OC1M field.
	TIM_CCMR1_Output_OC1CE_Pos  = 0x7       // Position of OC1CE field.
	TIM_CCMR1_Output_OC1CE_Msk  = 0x80      // Bit mask of OC1CE field.
	TIM_CCMR1_Output_OC1CE      = 0x80      // Bit OC1CE.
	TIM_CCMR1_Output_CC2S_Pos   = 0x8       // Position of CC2S field.
	TIM_CCMR1_Output_CC2S_Msk   = 0x300     // Bit mask of CC2S field.
	TIM_CCMR1_Output_OC2FE_Pos  = 0xa       // Position of OC2FE field.
	TIM_CCMR1_Output_OC2FE_Msk  = 0x400     // Bit mask of OC2FE field.
	TIM_CCMR1_Output_OC2FE      = 0x400     // Bit OC2FE.
	TIM_CCMR1_Output_OC2PE_Pos  = 0xb       // Position of OC2PE field.
	TIM_CCMR1_Output_OC2PE_Msk  = 0x800     // Bit mask of OC2PE field.
	TIM_CCMR1_Output_OC2PE      = 0x800     // Bit OC2PE.
	TIM_CCMR1_Output_OC2M_Pos   = 0xc       // Position of OC2M field.
	TIM_CCMR1_Output_OC2M_Msk   = 0x7000    // Bit mask of OC2M field.
	TIM_CCMR1_Output_OC2CE_Pos  = 0xf       // Position of OC2CE field.
	TIM_CCMR1_Output_OC2CE_Msk  = 0x8000    // Bit mask of OC2CE field.
	TIM_CCMR1_Output_OC2CE      = 0x8000    // Bit OC2CE.
	TIM_CCMR1_Output_OC1M_3_Pos = 0x10      // Position of OC1M_3 field.
	TIM_CCMR1_Output_OC1M_3_Msk = 0x10000   // Bit mask of OC1M_3 field.
	TIM_CCMR1_Output_OC1M_3     = 0x10000   // Bit OC1M_3.
	TIM_CCMR1_Output_OC2M_3_Pos = 0x18      // Position of OC2M_3 field.
	TIM_CCMR1_Output_OC2M_3_Msk = 0x1000000 // Bit mask of OC2M_3 field.
	TIM_CCMR1_Output_OC2M_3     = 0x1000000 // Bit OC2M_3.

	// CCMR1_Input: capture/compare mode register 1 (input           mode)
	TIM_CCMR1_Input_IC2F_Pos   = 0xc    // Position of IC2F field.
	TIM_CCMR1_Input_IC2F_Msk   = 0xf000 // Bit mask of IC2F field.
	TIM_CCMR1_Input_IC2PCS_Pos = 0xa    // Position of IC2PCS field.
	TIM_CCMR1_Input_IC2PCS_Msk = 0xc00  // Bit mask of IC2PCS field.
	TIM_CCMR1_Input_CC2S_Pos   = 0x8    // Position of CC2S field.
	TIM_CCMR1_Input_CC2S_Msk   = 0x300  // Bit mask of CC2S field.
	TIM_CCMR1_Input_IC1F_Pos   = 0x4    // Position of IC1F field.
	TIM_CCMR1_Input_IC1F_Msk   = 0xf0   // Bit mask of IC1F field.
	TIM_CCMR1_Input_ICPCS_Pos  = 0x2    // Position of ICPCS field.
	TIM_CCMR1_Input_ICPCS_Msk  = 0xc    // Bit mask of ICPCS field.
	TIM_CCMR1_Input_CC1S_Pos   = 0x0    // Position of CC1S field.
	TIM_CCMR1_Input_CC1S_Msk   = 0x3    // Bit mask of CC1S field.

	// CCMR2_Output: capture/compare mode register 2 (output           mode)
	TIM_CCMR2_Output_CC3S_Pos   = 0x0       // Position of CC3S field.
	TIM_CCMR2_Output_CC3S_Msk   = 0x3       // Bit mask of CC3S field.
	TIM_CCMR2_Output_OC3FE_Pos  = 0x2       // Position of OC3FE field.
	TIM_CCMR2_Output_OC3FE_Msk  = 0x4       // Bit mask of OC3FE field.
	TIM_CCMR2_Output_OC3FE      = 0x4       // Bit OC3FE.
	TIM_CCMR2_Output_OC3PE_Pos  = 0x3       // Position of OC3PE field.
	TIM_CCMR2_Output_OC3PE_Msk  = 0x8       // Bit mask of OC3PE field.
	TIM_CCMR2_Output_OC3PE      = 0x8       // Bit OC3PE.
	TIM_CCMR2_Output_OC3M_Pos   = 0x4       // Position of OC3M field.
	TIM_CCMR2_Output_OC3M_Msk   = 0x70      // Bit mask of OC3M field.
	TIM_CCMR2_Output_OC3CE_Pos  = 0x7       // Position of OC3CE field.
	TIM_CCMR2_Output_OC3CE_Msk  = 0x80      // Bit mask of OC3CE field.
	TIM_CCMR2_Output_OC3CE      = 0x80      // Bit OC3CE.
	TIM_CCMR2_Output_CC4S_Pos   = 0x8       // Position of CC4S field.
	TIM_CCMR2_Output_CC4S_Msk   = 0x300     // Bit mask of CC4S field.
	TIM_CCMR2_Output_OC4FE_Pos  = 0xa       // Position of OC4FE field.
	TIM_CCMR2_Output_OC4FE_Msk  = 0x400     // Bit mask of OC4FE field.
	TIM_CCMR2_Output_OC4FE      = 0x400     // Bit OC4FE.
	TIM_CCMR2_Output_OC4PE_Pos  = 0xb       // Position of OC4PE field.
	TIM_CCMR2_Output_OC4PE_Msk  = 0x800     // Bit mask of OC4PE field.
	TIM_CCMR2_Output_OC4PE      = 0x800     // Bit OC4PE.
	TIM_CCMR2_Output_OC4M_Pos   = 0xc       // Position of OC4M field.
	TIM_CCMR2_Output_OC4M_Msk   = 0x7000    // Bit mask of OC4M field.
	TIM_CCMR2_Output_OC4CE_Pos  = 0xf       // Position of OC4CE field.
	TIM_CCMR2_Output_OC4CE_Msk  = 0x8000    // Bit mask of OC4CE field.
	TIM_CCMR2_Output_OC4CE      = 0x8000    // Bit OC4CE.
	TIM_CCMR2_Output_OC3M_3_Pos = 0x10      // Position of OC3M_3 field.
	TIM_CCMR2_Output_OC3M_3_Msk = 0x10000   // Bit mask of OC3M_3 field.
	TIM_CCMR2_Output_OC3M_3     = 0x10000   // Bit OC3M_3.
	TIM_CCMR2_Output_OC4M_4_Pos = 0x18      // Position of OC4M_4 field.
	TIM_CCMR2_Output_OC4M_4_Msk = 0x1000000 // Bit mask of OC4M_4 field.
	TIM_CCMR2_Output_OC4M_4     = 0x1000000 // Bit OC4M_4.

	// CCMR2_Input: capture/compare mode register 2 (input           mode)
	TIM_CCMR2_Input_IC4F_Pos   = 0xc    // Position of IC4F field.
	TIM_CCMR2_Input_IC4F_Msk   = 0xf000 // Bit mask of IC4F field.
	TIM_CCMR2_Input_IC4PSC_Pos = 0xa    // Position of IC4PSC field.
	TIM_CCMR2_Input_IC4PSC_Msk = 0xc00  // Bit mask of IC4PSC field.
	TIM_CCMR2_Input_CC4S_Pos   = 0x8    // Position of CC4S field.
	TIM_CCMR2_Input_CC4S_Msk   = 0x300  // Bit mask of CC4S field.
	TIM_CCMR2_Input_IC3F_Pos   = 0x4    // Position of IC3F field.
	TIM_CCMR2_Input_IC3F_Msk   = 0xf0   // Bit mask of IC3F field.
	TIM_CCMR2_Input_IC3PSC_Pos = 0x2    // Position of IC3PSC field.
	TIM_CCMR2_Input_IC3PSC_Msk = 0xc    // Bit mask of IC3PSC field.
	TIM_CCMR2_Input_CC3S_Pos   = 0x0    // Position of CC3S field.
	TIM_CCMR2_Input_CC3S_Msk   = 0x3    // Bit mask of CC3S field.

	// CCER: capture/compare enable           register
	TIM_CCER_CC1E_Pos  = 0x0      // Position of CC1E field.
	TIM_CCER_CC1E_Msk  = 0x1      // Bit mask of CC1E field.
	TIM_CCER_CC1E      = 0x1      // Bit CC1E.
	TIM_CCER_CC1P_Pos  = 0x1      // Position of CC1P field.
	TIM_CCER_CC1P_Msk  = 0x2      // Bit mask of CC1P field.
	TIM_CCER_CC1P      = 0x2      // Bit CC1P.
	TIM_CCER_CC1NE_Pos = 0x2      // Position of CC1NE field.
	TIM_CCER_CC1NE_Msk = 0x4      // Bit mask of CC1NE field.
	TIM_CCER_CC1NE     = 0x4      // Bit CC1NE.
	TIM_CCER_CC1NP_Pos = 0x3      // Position of CC1NP field.
	TIM_CCER_CC1NP_Msk = 0x8      // Bit mask of CC1NP field.
	TIM_CCER_CC1NP     = 0x8      // Bit CC1NP.
	TIM_CCER_CC2E_Pos  = 0x4      // Position of CC2E field.
	TIM_CCER_CC2E_Msk  = 0x10     // Bit mask of CC2E field.
	TIM_CCER_CC2E      = 0x10     // Bit CC2E.
	TIM_CCER_CC2P_Pos  = 0x5      // Position of CC2P field.
	TIM_CCER_CC2P_Msk  = 0x20     // Bit mask of CC2P field.
	TIM_CCER_CC2P      = 0x20     // Bit CC2P.
	TIM_CCER_CC2NE_Pos = 0x6      // Position of CC2NE field.
	TIM_CCER_CC2NE_Msk = 0x40     // Bit mask of CC2NE field.
	TIM_CCER_CC2NE     = 0x40     // Bit CC2NE.
	TIM_CCER_CC2NP_Pos = 0x7      // Position of CC2NP field.
	TIM_CCER_CC2NP_Msk = 0x80     // Bit mask of CC2NP field.
	TIM_CCER_CC2NP     = 0x80     // Bit CC2NP.
	TIM_CCER_CC3E_Pos  = 0x8      // Position of CC3E field.
	TIM_CCER_CC3E_Msk  = 0x100    // Bit mask of CC3E field.
	TIM_CCER_CC3E      = 0x100    // Bit CC3E.
	TIM_CCER_CC3P_Pos  = 0x9      // Position of CC3P field.
	TIM_CCER_CC3P_Msk  = 0x200    // Bit mask of CC3P field.
	TIM_CCER_CC3P      = 0x200    // Bit CC3P.
	TIM_CCER_CC3NE_Pos = 0xa      // Position of CC3NE field.
	TIM_CCER_CC3NE_Msk = 0x400    // Bit mask of CC3NE field.
	TIM_CCER_CC3NE     = 0x400    // Bit CC3NE.
	TIM_CCER_CC3NP_Pos = 0xb      // Position of CC3NP field.
	TIM_CCER_CC3NP_Msk = 0x800    // Bit mask of CC3NP field.
	TIM_CCER_CC3NP     = 0x800    // Bit CC3NP.
	TIM_CCER_CC4E_Pos  = 0xc      // Position of CC4E field.
	TIM_CCER_CC4E_Msk  = 0x1000   // Bit mask of CC4E field.
	TIM_CCER_CC4E      = 0x1000   // Bit CC4E.
	TIM_CCER_CC4P_Pos  = 0xd      // Position of CC4P field.
	TIM_CCER_CC4P_Msk  = 0x2000   // Bit mask of CC4P field.
	TIM_CCER_CC4P      = 0x2000   // Bit CC4P.
	TIM_CCER_CC4NP_Pos = 0xf      // Position of CC4NP field.
	TIM_CCER_CC4NP_Msk = 0x8000   // Bit mask of CC4NP field.
	TIM_CCER_CC4NP     = 0x8000   // Bit CC4NP.
	TIM_CCER_CC5E_Pos  = 0x10     // Position of CC5E field.
	TIM_CCER_CC5E_Msk  = 0x10000  // Bit mask of CC5E field.
	TIM_CCER_CC5E      = 0x10000  // Bit CC5E.
	TIM_CCER_CC5P_Pos  = 0x11     // Position of CC5P field.
	TIM_CCER_CC5P_Msk  = 0x20000  // Bit mask of CC5P field.
	TIM_CCER_CC5P      = 0x20000  // Bit CC5P.
	TIM_CCER_CC6E_Pos  = 0x14     // Position of CC6E field.
	TIM_CCER_CC6E_Msk  = 0x100000 // Bit mask of CC6E field.
	TIM_CCER_CC6E      = 0x100000 // Bit CC6E.
	TIM_CCER_CC6P_Pos  = 0x15     // Position of CC6P field.
	TIM_CCER_CC6P_Msk  = 0x200000 // Bit mask of CC6P field.
	TIM_CCER_CC6P      = 0x200000 // Bit CC6P.

	// CNT: counter
	TIM_CNT_CNT_Pos    = 0x0        // Position of CNT field.
	TIM_CNT_CNT_Msk    = 0xffff     // Bit mask of CNT field.
	TIM_CNT_UIFCPY_Pos = 0x1f       // Position of UIFCPY field.
	TIM_CNT_UIFCPY_Msk = 0x80000000 // Bit mask of UIFCPY field.
	TIM_CNT_UIFCPY     = 0x80000000 // Bit UIFCPY.

	// PSC: prescaler
	TIM_PSC_PSC_Pos = 0x0    // Position of PSC field.
	TIM_PSC_PSC_Msk = 0xffff // Bit mask of PSC field.

	// ARR: auto-reload register
	TIM_ARR_ARR_Pos = 0x0    // Position of ARR field.
	TIM_ARR_ARR_Msk = 0xffff // Bit mask of ARR field.

	// RCR: repetition counter register
	TIM_RCR_REP_Pos = 0x0  // Position of REP field.
	TIM_RCR_REP_Msk = 0xff // Bit mask of REP field.

	// CCR1: capture/compare register 1
	TIM_CCR1_CCR1_Pos = 0x0    // Position of CCR1 field.
	TIM_CCR1_CCR1_Msk = 0xffff // Bit mask of CCR1 field.

	// CCR2: capture/compare register 2
	TIM_CCR2_CCR2_Pos = 0x0    // Position of CCR2 field.
	TIM_CCR2_CCR2_Msk = 0xffff // Bit mask of CCR2 field.

	// CCR3: capture/compare register 3
	TIM_CCR3_CCR3_Pos = 0x0    // Position of CCR3 field.
	TIM_CCR3_CCR3_Msk = 0xffff // Bit mask of CCR3 field.

	// CCR4: capture/compare register 4
	TIM_CCR4_CCR4_Pos = 0x0    // Position of CCR4 field.
	TIM_CCR4_CCR4_Msk = 0xffff // Bit mask of CCR4 field.

	// BDTR: break and dead-time register
	TIM_BDTR_DTG_Pos  = 0x0       // Position of DTG field.
	TIM_BDTR_DTG_Msk  = 0xff      // Bit mask of DTG field.
	TIM_BDTR_LOCK_Pos = 0x8       // Position of LOCK field.
	TIM_BDTR_LOCK_Msk = 0x300     // Bit mask of LOCK field.
	TIM_BDTR_OSSI_Pos = 0xa       // Position of OSSI field.
	TIM_BDTR_OSSI_Msk = 0x400     // Bit mask of OSSI field.
	TIM_BDTR_OSSI     = 0x400     // Bit OSSI.
	TIM_BDTR_OSSR_Pos = 0xb       // Position of OSSR field.
	TIM_BDTR_OSSR_Msk = 0x800     // Bit mask of OSSR field.
	TIM_BDTR_OSSR     = 0x800     // Bit OSSR.
	TIM_BDTR_BKE_Pos  = 0xc       // Position of BKE field.
	TIM_BDTR_BKE_Msk  = 0x1000    // Bit mask of BKE field.
	TIM_BDTR_BKE      = 0x1000    // Bit BKE.
	TIM_BDTR_BKP_Pos  = 0xd       // Position of BKP field.
	TIM_BDTR_BKP_Msk  = 0x2000    // Bit mask of BKP field.
	TIM_BDTR_BKP      = 0x2000    // Bit BKP.
	TIM_BDTR_AOE_Pos  = 0xe       // Position of AOE field.
	TIM_BDTR_AOE_Msk  = 0x4000    // Bit mask of AOE field.
	TIM_BDTR_AOE      = 0x4000    // Bit AOE.
	TIM_BDTR_MOE_Pos  = 0xf       // Position of MOE field.
	TIM_BDTR_MOE_Msk  = 0x8000    // Bit mask of MOE field.
	TIM_BDTR_MOE      = 0x8000    // Bit MOE.
	TIM_BDTR_BKF_Pos  = 0x10      // Position of BKF field.
	TIM_BDTR_BKF_Msk  = 0xf0000   // Bit mask of BKF field.
	TIM_BDTR_BK2F_Pos = 0x14      // Position of BK2F field.
	TIM_BDTR_BK2F_Msk = 0xf00000  // Bit mask of BK2F field.
	TIM_BDTR_BK2E_Pos = 0x18      // Position of BK2E field.
	TIM_BDTR_BK2E_Msk = 0x1000000 // Bit mask of BK2E field.
	TIM_BDTR_BK2E     = 0x1000000 // Bit BK2E.
	TIM_BDTR_BK2P_Pos = 0x19      // Position of BK2P field.
	TIM_BDTR_BK2P_Msk = 0x2000000 // Bit mask of BK2P field.
	TIM_BDTR_BK2P     = 0x2000000 // Bit BK2P.

	// DCR: DMA control register
	TIM_DCR_DBL_Pos = 0x8    // Position of DBL field.
	TIM_DCR_DBL_Msk = 0x1f00 // Bit mask of DBL field.
	TIM_DCR_DBA_Pos = 0x0    // Position of DBA field.
	TIM_DCR_DBA_Msk = 0x1f   // Bit mask of DBA field.

	// DMAR: DMA address for full transfer
	TIM_DMAR_DMAB_Pos = 0x0    // Position of DMAB field.
	TIM_DMAR_DMAB_Msk = 0xffff // Bit mask of DMAB field.

	// CCMR3_Output: capture/compare mode register 3 (output           mode)
	TIM_CCMR3_Output_OC5FE_Pos = 0x2       // Position of OC5FE field.
	TIM_CCMR3_Output_OC5FE_Msk = 0x4       // Bit mask of OC5FE field.
	TIM_CCMR3_Output_OC5FE     = 0x4       // Bit OC5FE.
	TIM_CCMR3_Output_OC5PE_Pos = 0x3       // Position of OC5PE field.
	TIM_CCMR3_Output_OC5PE_Msk = 0x8       // Bit mask of OC5PE field.
	TIM_CCMR3_Output_OC5PE     = 0x8       // Bit OC5PE.
	TIM_CCMR3_Output_OC5M_Pos  = 0x4       // Position of OC5M field.
	TIM_CCMR3_Output_OC5M_Msk  = 0x70      // Bit mask of OC5M field.
	TIM_CCMR3_Output_OC5CE_Pos = 0x7       // Position of OC5CE field.
	TIM_CCMR3_Output_OC5CE_Msk = 0x80      // Bit mask of OC5CE field.
	TIM_CCMR3_Output_OC5CE     = 0x80      // Bit OC5CE.
	TIM_CCMR3_Output_OC6FE_Pos = 0xa       // Position of OC6FE field.
	TIM_CCMR3_Output_OC6FE_Msk = 0x400     // Bit mask of OC6FE field.
	TIM_CCMR3_Output_OC6FE     = 0x400     // Bit OC6FE.
	TIM_CCMR3_Output_OC6PE_Pos = 0xb       // Position of OC6PE field.
	TIM_CCMR3_Output_OC6PE_Msk = 0x800     // Bit mask of OC6PE field.
	TIM_CCMR3_Output_OC6PE     = 0x800     // Bit OC6PE.
	TIM_CCMR3_Output_OC6M_Pos  = 0xc       // Position of OC6M field.
	TIM_CCMR3_Output_OC6M_Msk  = 0x7000    // Bit mask of OC6M field.
	TIM_CCMR3_Output_OC6CE_Pos = 0xf       // Position of OC6CE field.
	TIM_CCMR3_Output_OC6CE_Msk = 0x8000    // Bit mask of OC6CE field.
	TIM_CCMR3_Output_OC6CE     = 0x8000    // Bit OC6CE.
	TIM_CCMR3_Output_OC5M3_Pos = 0x10      // Position of OC5M3 field.
	TIM_CCMR3_Output_OC5M3_Msk = 0x10000   // Bit mask of OC5M3 field.
	TIM_CCMR3_Output_OC5M3     = 0x10000   // Bit OC5M3.
	TIM_CCMR3_Output_OC6M3_Pos = 0x18      // Position of OC6M3 field.
	TIM_CCMR3_Output_OC6M3_Msk = 0x1000000 // Bit mask of OC6M3 field.
	TIM_CCMR3_Output_OC6M3     = 0x1000000 // Bit OC6M3.

	// CCR5: capture/compare register 5
	TIM_CCR5_CCR5_Pos  = 0x0        // Position of CCR5 field.
	TIM_CCR5_CCR5_Msk  = 0xffff     // Bit mask of CCR5 field.
	TIM_CCR5_GC5C1_Pos = 0x1d       // Position of GC5C1 field.
	TIM_CCR5_GC5C1_Msk = 0x20000000 // Bit mask of GC5C1 field.
	TIM_CCR5_GC5C1     = 0x20000000 // Bit GC5C1.
	TIM_CCR5_GC5C2_Pos = 0x1e       // Position of GC5C2 field.
	TIM_CCR5_GC5C2_Msk = 0x40000000 // Bit mask of GC5C2 field.
	TIM_CCR5_GC5C2     = 0x40000000 // Bit GC5C2.
	TIM_CCR5_GC5C3_Pos = 0x1f       // Position of GC5C3 field.
	TIM_CCR5_GC5C3_Msk = 0x80000000 // Bit mask of GC5C3 field.
	TIM_CCR5_GC5C3     = 0x80000000 // Bit GC5C3.

	// CRR6: capture/compare register 6
	TIM_CRR6_CCR6_Pos = 0x0    // Position of CCR6 field.
	TIM_CRR6_CCR6_Msk = 0xffff // Bit mask of CCR6 field.

	// AF1: TIM1 alternate function option register           1
	TIM_AF1_BKINE_Pos     = 0x0     // Position of BKINE field.
	TIM_AF1_BKINE_Msk     = 0x1     // Bit mask of BKINE field.
	TIM_AF1_BKINE         = 0x1     // Bit BKINE.
	TIM_AF1_BKCMP1E_Pos   = 0x1     // Position of BKCMP1E field.
	TIM_AF1_BKCMP1E_Msk   = 0x2     // Bit mask of BKCMP1E field.
	TIM_AF1_BKCMP1E       = 0x2     // Bit BKCMP1E.
	TIM_AF1_BKCMP2E_Pos   = 0x2     // Position of BKCMP2E field.
	TIM_AF1_BKCMP2E_Msk   = 0x4     // Bit mask of BKCMP2E field.
	TIM_AF1_BKCMP2E       = 0x4     // Bit BKCMP2E.
	TIM_AF1_BKDF1BK0E_Pos = 0x8     // Position of BKDF1BK0E field.
	TIM_AF1_BKDF1BK0E_Msk = 0x100   // Bit mask of BKDF1BK0E field.
	TIM_AF1_BKDF1BK0E     = 0x100   // Bit BKDF1BK0E.
	TIM_AF1_BKINP_Pos     = 0x9     // Position of BKINP field.
	TIM_AF1_BKINP_Msk     = 0x200   // Bit mask of BKINP field.
	TIM_AF1_BKINP         = 0x200   // Bit BKINP.
	TIM_AF1_BKCMP1P_Pos   = 0xa     // Position of BKCMP1P field.
	TIM_AF1_BKCMP1P_Msk   = 0x400   // Bit mask of BKCMP1P field.
	TIM_AF1_BKCMP1P       = 0x400   // Bit BKCMP1P.
	TIM_AF1_BKCMP2P_Pos   = 0xb     // Position of BKCMP2P field.
	TIM_AF1_BKCMP2P_Msk   = 0x800   // Bit mask of BKCMP2P field.
	TIM_AF1_BKCMP2P       = 0x800   // Bit BKCMP2P.
	TIM_AF1_ETRSEL_Pos    = 0xe     // Position of ETRSEL field.
	TIM_AF1_ETRSEL_Msk    = 0x3c000 // Bit mask of ETRSEL field.

	// AF2: TIM1 Alternate function odfsdm1_breakster           2
	TIM_AF2_BK2INE_Pos     = 0x0   // Position of BK2INE field.
	TIM_AF2_BK2INE_Msk     = 0x1   // Bit mask of BK2INE field.
	TIM_AF2_BK2INE         = 0x1   // Bit BK2INE.
	TIM_AF2_BK2CMP1E_Pos   = 0x1   // Position of BK2CMP1E field.
	TIM_AF2_BK2CMP1E_Msk   = 0x2   // Bit mask of BK2CMP1E field.
	TIM_AF2_BK2CMP1E       = 0x2   // Bit BK2CMP1E.
	TIM_AF2_BK2CMP2E_Pos   = 0x2   // Position of BK2CMP2E field.
	TIM_AF2_BK2CMP2E_Msk   = 0x4   // Bit mask of BK2CMP2E field.
	TIM_AF2_BK2CMP2E       = 0x4   // Bit BK2CMP2E.
	TIM_AF2_BK2DF1BK1E_Pos = 0x8   // Position of BK2DF1BK1E field.
	TIM_AF2_BK2DF1BK1E_Msk = 0x100 // Bit mask of BK2DF1BK1E field.
	TIM_AF2_BK2DF1BK1E     = 0x100 // Bit BK2DF1BK1E.
	TIM_AF2_BK2INP_Pos     = 0x9   // Position of BK2INP field.
	TIM_AF2_BK2INP_Msk     = 0x200 // Bit mask of BK2INP field.
	TIM_AF2_BK2INP         = 0x200 // Bit BK2INP.
	TIM_AF2_BK2CMP1P_Pos   = 0xa   // Position of BK2CMP1P field.
	TIM_AF2_BK2CMP1P_Msk   = 0x400 // Bit mask of BK2CMP1P field.
	TIM_AF2_BK2CMP1P       = 0x400 // Bit BK2CMP1P.
	TIM_AF2_BK2CMP2P_Pos   = 0xb   // Position of BK2CMP2P field.
	TIM_AF2_BK2CMP2P_Msk   = 0x800 // Bit mask of BK2CMP2P field.
	TIM_AF2_BK2CMP2P       = 0x800 // Bit BK2CMP2P.

	// TISEL: TIM1 timer input selection           register
	TIM_TISEL_TI1SEL_Pos = 0x0       // Position of TI1SEL field.
	TIM_TISEL_TI1SEL_Msk = 0xf       // Bit mask of TI1SEL field.
	TIM_TISEL_TI2SEL_Pos = 0x8       // Position of TI2SEL field.
	TIM_TISEL_TI2SEL_Msk = 0xf00     // Bit mask of TI2SEL field.
	TIM_TISEL_TI3SEL_Pos = 0x10      // Position of TI3SEL field.
	TIM_TISEL_TI3SEL_Msk = 0xf0000   // Bit mask of TI3SEL field.
	TIM_TISEL_TI4SEL_Pos = 0x18      // Position of TI4SEL field.
	TIM_TISEL_TI4SEL_Msk = 0xf000000 // Bit mask of TI4SEL field.
)

// Bitfields for FDCAN1: FDCAN1
const (
	// FDCAN_CREL: FDCAN Core Release Register
	FDCAN_FDCAN_CREL_REL_Pos     = 0x1c       // Position of REL field.
	FDCAN_FDCAN_CREL_REL_Msk     = 0xf0000000 // Bit mask of REL field.
	FDCAN_FDCAN_CREL_STEP_Pos    = 0x18       // Position of STEP field.
	FDCAN_FDCAN_CREL_STEP_Msk    = 0xf000000  // Bit mask of STEP field.
	FDCAN_FDCAN_CREL_SUBSTEP_Pos = 0x14       // Position of SUBSTEP field.
	FDCAN_FDCAN_CREL_SUBSTEP_Msk = 0xf00000   // Bit mask of SUBSTEP field.
	FDCAN_FDCAN_CREL_YEAR_Pos    = 0x10       // Position of YEAR field.
	FDCAN_FDCAN_CREL_YEAR_Msk    = 0xf0000    // Bit mask of YEAR field.
	FDCAN_FDCAN_CREL_MON_Pos     = 0x8        // Position of MON field.
	FDCAN_FDCAN_CREL_MON_Msk     = 0xff00     // Bit mask of MON field.
	FDCAN_FDCAN_CREL_DAY_Pos     = 0x0        // Position of DAY field.
	FDCAN_FDCAN_CREL_DAY_Msk     = 0xff       // Bit mask of DAY field.

	// FDCAN_ENDN: FDCAN Core Release Register
	FDCAN_FDCAN_ENDN_ETV_Pos = 0x0        // Position of ETV field.
	FDCAN_FDCAN_ENDN_ETV_Msk = 0xffffffff // Bit mask of ETV field.

	// FDCAN_DBTP: FDCAN Data Bit Timing and Prescaler           Register
	FDCAN_FDCAN_DBTP_DSJW_Pos   = 0x0      // Position of DSJW field.
	FDCAN_FDCAN_DBTP_DSJW_Msk   = 0xf      // Bit mask of DSJW field.
	FDCAN_FDCAN_DBTP_DTSEG2_Pos = 0x4      // Position of DTSEG2 field.
	FDCAN_FDCAN_DBTP_DTSEG2_Msk = 0xf0     // Bit mask of DTSEG2 field.
	FDCAN_FDCAN_DBTP_DTSEG1_Pos = 0x8      // Position of DTSEG1 field.
	FDCAN_FDCAN_DBTP_DTSEG1_Msk = 0x1f00   // Bit mask of DTSEG1 field.
	FDCAN_FDCAN_DBTP_DBRP_Pos   = 0x10     // Position of DBRP field.
	FDCAN_FDCAN_DBTP_DBRP_Msk   = 0x1f0000 // Bit mask of DBRP field.
	FDCAN_FDCAN_DBTP_TDC_Pos    = 0x17     // Position of TDC field.
	FDCAN_FDCAN_DBTP_TDC_Msk    = 0x800000 // Bit mask of TDC field.
	FDCAN_FDCAN_DBTP_TDC        = 0x800000 // Bit TDC.

	// FDCAN_TEST: FDCAN Test Register
	FDCAN_FDCAN_TEST_LBCK_Pos = 0x4  // Position of LBCK field.
	FDCAN_FDCAN_TEST_LBCK_Msk = 0x10 // Bit mask of LBCK field.
	FDCAN_FDCAN_TEST_LBCK     = 0x10 // Bit LBCK.
	FDCAN_FDCAN_TEST_TX_Pos   = 0x5  // Position of TX field.
	FDCAN_FDCAN_TEST_TX_Msk   = 0x60 // Bit mask of TX field.
	FDCAN_FDCAN_TEST_RX_Pos   = 0x7  // Position of RX field.
	FDCAN_FDCAN_TEST_RX_Msk   = 0x80 // Bit mask of RX field.
	FDCAN_FDCAN_TEST_RX       = 0x80 // Bit RX.

	// FDCAN_RWD: FDCAN RAM Watchdog Register
	FDCAN_FDCAN_RWD_WDV_Pos = 0x8    // Position of WDV field.
	FDCAN_FDCAN_RWD_WDV_Msk = 0xff00 // Bit mask of WDV field.
	FDCAN_FDCAN_RWD_WDC_Pos = 0x0    // Position of WDC field.
	FDCAN_FDCAN_RWD_WDC_Msk = 0xff   // Bit mask of WDC field.

	// FDCAN_CCCR: FDCAN CC Control Register
	FDCAN_FDCAN_CCCR_INIT_Pos = 0x0    // Position of INIT field.
	FDCAN_FDCAN_CCCR_INIT_Msk = 0x1    // Bit mask of INIT field.
	FDCAN_FDCAN_CCCR_INIT     = 0x1    // Bit INIT.
	FDCAN_FDCAN_CCCR_CCE_Pos  = 0x1    // Position of CCE field.
	FDCAN_FDCAN_CCCR_CCE_Msk  = 0x2    // Bit mask of CCE field.
	FDCAN_FDCAN_CCCR_CCE      = 0x2    // Bit CCE.
	FDCAN_FDCAN_CCCR_ASM_Pos  = 0x2    // Position of ASM field.
	FDCAN_FDCAN_CCCR_ASM_Msk  = 0x4    // Bit mask of ASM field.
	FDCAN_FDCAN_CCCR_ASM      = 0x4    // Bit ASM.
	FDCAN_FDCAN_CCCR_CSA_Pos  = 0x3    // Position of CSA field.
	FDCAN_FDCAN_CCCR_CSA_Msk  = 0x8    // Bit mask of CSA field.
	FDCAN_FDCAN_CCCR_CSA      = 0x8    // Bit CSA.
	FDCAN_FDCAN_CCCR_CSR_Pos  = 0x4    // Position of CSR field.
	FDCAN_FDCAN_CCCR_CSR_Msk  = 0x10   // Bit mask of CSR field.
	FDCAN_FDCAN_CCCR_CSR      = 0x10   // Bit CSR.
	FDCAN_FDCAN_CCCR_MON_Pos  = 0x5    // Position of MON field.
	FDCAN_FDCAN_CCCR_MON_Msk  = 0x20   // Bit mask of MON field.
	FDCAN_FDCAN_CCCR_MON      = 0x20   // Bit MON.
	FDCAN_FDCAN_CCCR_DAR_Pos  = 0x6    // Position of DAR field.
	FDCAN_FDCAN_CCCR_DAR_Msk  = 0x40   // Bit mask of DAR field.
	FDCAN_FDCAN_CCCR_DAR      = 0x40   // Bit DAR.
	FDCAN_FDCAN_CCCR_TEST_Pos = 0x7    // Position of TEST field.
	FDCAN_FDCAN_CCCR_TEST_Msk = 0x80   // Bit mask of TEST field.
	FDCAN_FDCAN_CCCR_TEST     = 0x80   // Bit TEST.
	FDCAN_FDCAN_CCCR_FDOE_Pos = 0x8    // Position of FDOE field.
	FDCAN_FDCAN_CCCR_FDOE_Msk = 0x100  // Bit mask of FDOE field.
	FDCAN_FDCAN_CCCR_FDOE     = 0x100  // Bit FDOE.
	FDCAN_FDCAN_CCCR_BSE_Pos  = 0x9    // Position of BSE field.
	FDCAN_FDCAN_CCCR_BSE_Msk  = 0x200  // Bit mask of BSE field.
	FDCAN_FDCAN_CCCR_BSE      = 0x200  // Bit BSE.
	FDCAN_FDCAN_CCCR_PXHD_Pos = 0xc    // Position of PXHD field.
	FDCAN_FDCAN_CCCR_PXHD_Msk = 0x1000 // Bit mask of PXHD field.
	FDCAN_FDCAN_CCCR_PXHD     = 0x1000 // Bit PXHD.
	FDCAN_FDCAN_CCCR_EFBI_Pos = 0xd    // Position of EFBI field.
	FDCAN_FDCAN_CCCR_EFBI_Msk = 0x2000 // Bit mask of EFBI field.
	FDCAN_FDCAN_CCCR_EFBI     = 0x2000 // Bit EFBI.
	FDCAN_FDCAN_CCCR_TXP_Pos  = 0xe    // Position of TXP field.
	FDCAN_FDCAN_CCCR_TXP_Msk  = 0x4000 // Bit mask of TXP field.
	FDCAN_FDCAN_CCCR_TXP      = 0x4000 // Bit TXP.
	FDCAN_FDCAN_CCCR_NISO_Pos = 0xf    // Position of NISO field.
	FDCAN_FDCAN_CCCR_NISO_Msk = 0x8000 // Bit mask of NISO field.
	FDCAN_FDCAN_CCCR_NISO     = 0x8000 // Bit NISO.

	// FDCAN_NBTP: FDCAN Nominal Bit Timing and Prescaler           Register
	FDCAN_FDCAN_NBTP_NSJW_Pos   = 0x19       // Position of NSJW field.
	FDCAN_FDCAN_NBTP_NSJW_Msk   = 0xfe000000 // Bit mask of NSJW field.
	FDCAN_FDCAN_NBTP_NBRP_Pos   = 0x10       // Position of NBRP field.
	FDCAN_FDCAN_NBTP_NBRP_Msk   = 0x1ff0000  // Bit mask of NBRP field.
	FDCAN_FDCAN_NBTP_NTSEG1_Pos = 0x8        // Position of NTSEG1 field.
	FDCAN_FDCAN_NBTP_NTSEG1_Msk = 0xff00     // Bit mask of NTSEG1 field.
	FDCAN_FDCAN_NBTP_TSEG2_Pos  = 0x0        // Position of TSEG2 field.
	FDCAN_FDCAN_NBTP_TSEG2_Msk  = 0x7f       // Bit mask of TSEG2 field.

	// FDCAN_TSCC: FDCAN Timestamp Counter Configuration           Register
	FDCAN_FDCAN_TSCC_TCP_Pos = 0x10    // Position of TCP field.
	FDCAN_FDCAN_TSCC_TCP_Msk = 0xf0000 // Bit mask of TCP field.
	FDCAN_FDCAN_TSCC_TSS_Pos = 0x0     // Position of TSS field.
	FDCAN_FDCAN_TSCC_TSS_Msk = 0x3     // Bit mask of TSS field.

	// FDCAN_TSCV: FDCAN Timestamp Counter Value           Register
	FDCAN_FDCAN_TSCV_TSC_Pos = 0x0    // Position of TSC field.
	FDCAN_FDCAN_TSCV_TSC_Msk = 0xffff // Bit mask of TSC field.

	// FDCAN_TOCC: FDCAN Timeout Counter Configuration           Register
	FDCAN_FDCAN_TOCC_ETOC_Pos = 0x0        // Position of ETOC field.
	FDCAN_FDCAN_TOCC_ETOC_Msk = 0x1        // Bit mask of ETOC field.
	FDCAN_FDCAN_TOCC_ETOC     = 0x1        // Bit ETOC.
	FDCAN_FDCAN_TOCC_TOS_Pos  = 0x1        // Position of TOS field.
	FDCAN_FDCAN_TOCC_TOS_Msk  = 0x6        // Bit mask of TOS field.
	FDCAN_FDCAN_TOCC_TOP_Pos  = 0x10       // Position of TOP field.
	FDCAN_FDCAN_TOCC_TOP_Msk  = 0xffff0000 // Bit mask of TOP field.

	// FDCAN_TOCV: FDCAN Timeout Counter Value           Register
	FDCAN_FDCAN_TOCV_TOC_Pos = 0x0    // Position of TOC field.
	FDCAN_FDCAN_TOCV_TOC_Msk = 0xffff // Bit mask of TOC field.

	// FDCAN_ECR: FDCAN Error Counter Register
	FDCAN_FDCAN_ECR_CEL_Pos  = 0x10     // Position of CEL field.
	FDCAN_FDCAN_ECR_CEL_Msk  = 0xff0000 // Bit mask of CEL field.
	FDCAN_FDCAN_ECR_RP_Pos   = 0xf      // Position of RP field.
	FDCAN_FDCAN_ECR_RP_Msk   = 0x8000   // Bit mask of RP field.
	FDCAN_FDCAN_ECR_RP       = 0x8000   // Bit RP.
	FDCAN_FDCAN_ECR_TREC_Pos = 0x8      // Position of TREC field.
	FDCAN_FDCAN_ECR_TREC_Msk = 0x7f00   // Bit mask of TREC field.
	FDCAN_FDCAN_ECR_TEC_Pos  = 0x0      // Position of TEC field.
	FDCAN_FDCAN_ECR_TEC_Msk  = 0xff     // Bit mask of TEC field.

	// FDCAN_PSR: FDCAN Protocol Status Register
	FDCAN_FDCAN_PSR_LEC_Pos  = 0x0      // Position of LEC field.
	FDCAN_FDCAN_PSR_LEC_Msk  = 0x7      // Bit mask of LEC field.
	FDCAN_FDCAN_PSR_ACT_Pos  = 0x3      // Position of ACT field.
	FDCAN_FDCAN_PSR_ACT_Msk  = 0x18     // Bit mask of ACT field.
	FDCAN_FDCAN_PSR_EP_Pos   = 0x5      // Position of EP field.
	FDCAN_FDCAN_PSR_EP_Msk   = 0x20     // Bit mask of EP field.
	FDCAN_FDCAN_PSR_EP       = 0x20     // Bit EP.
	FDCAN_FDCAN_PSR_EW_Pos   = 0x6      // Position of EW field.
	FDCAN_FDCAN_PSR_EW_Msk   = 0x40     // Bit mask of EW field.
	FDCAN_FDCAN_PSR_EW       = 0x40     // Bit EW.
	FDCAN_FDCAN_PSR_BO_Pos   = 0x7      // Position of BO field.
	FDCAN_FDCAN_PSR_BO_Msk   = 0x80     // Bit mask of BO field.
	FDCAN_FDCAN_PSR_BO       = 0x80     // Bit BO.
	FDCAN_FDCAN_PSR_DLEC_Pos = 0x8      // Position of DLEC field.
	FDCAN_FDCAN_PSR_DLEC_Msk = 0x700    // Bit mask of DLEC field.
	FDCAN_FDCAN_PSR_RESI_Pos = 0xb      // Position of RESI field.
	FDCAN_FDCAN_PSR_RESI_Msk = 0x800    // Bit mask of RESI field.
	FDCAN_FDCAN_PSR_RESI     = 0x800    // Bit RESI.
	FDCAN_FDCAN_PSR_RBRS_Pos = 0xc      // Position of RBRS field.
	FDCAN_FDCAN_PSR_RBRS_Msk = 0x1000   // Bit mask of RBRS field.
	FDCAN_FDCAN_PSR_RBRS     = 0x1000   // Bit RBRS.
	FDCAN_FDCAN_PSR_REDL_Pos = 0xd      // Position of REDL field.
	FDCAN_FDCAN_PSR_REDL_Msk = 0x2000   // Bit mask of REDL field.
	FDCAN_FDCAN_PSR_REDL     = 0x2000   // Bit REDL.
	FDCAN_FDCAN_PSR_PXE_Pos  = 0xe      // Position of PXE field.
	FDCAN_FDCAN_PSR_PXE_Msk  = 0x4000   // Bit mask of PXE field.
	FDCAN_FDCAN_PSR_PXE      = 0x4000   // Bit PXE.
	FDCAN_FDCAN_PSR_TDCV_Pos = 0x10     // Position of TDCV field.
	FDCAN_FDCAN_PSR_TDCV_Msk = 0x7f0000 // Bit mask of TDCV field.

	// FDCAN_TDCR: FDCAN Transmitter Delay Compensation           Register
	FDCAN_FDCAN_TDCR_TDCF_Pos = 0x0    // Position of TDCF field.
	FDCAN_FDCAN_TDCR_TDCF_Msk = 0x7f   // Bit mask of TDCF field.
	FDCAN_FDCAN_TDCR_TDCO_Pos = 0x8    // Position of TDCO field.
	FDCAN_FDCAN_TDCR_TDCO_Msk = 0x7f00 // Bit mask of TDCO field.

	// FDCAN_IR: FDCAN Interrupt Register
	FDCAN_FDCAN_IR_RF0N_Pos = 0x0        // Position of RF0N field.
	FDCAN_FDCAN_IR_RF0N_Msk = 0x1        // Bit mask of RF0N field.
	FDCAN_FDCAN_IR_RF0N     = 0x1        // Bit RF0N.
	FDCAN_FDCAN_IR_RF0W_Pos = 0x1        // Position of RF0W field.
	FDCAN_FDCAN_IR_RF0W_Msk = 0x2        // Bit mask of RF0W field.
	FDCAN_FDCAN_IR_RF0W     = 0x2        // Bit RF0W.
	FDCAN_FDCAN_IR_RF0F_Pos = 0x2        // Position of RF0F field.
	FDCAN_FDCAN_IR_RF0F_Msk = 0x4        // Bit mask of RF0F field.
	FDCAN_FDCAN_IR_RF0F     = 0x4        // Bit RF0F.
	FDCAN_FDCAN_IR_RF0L_Pos = 0x3        // Position of RF0L field.
	FDCAN_FDCAN_IR_RF0L_Msk = 0x8        // Bit mask of RF0L field.
	FDCAN_FDCAN_IR_RF0L     = 0x8        // Bit RF0L.
	FDCAN_FDCAN_IR_RF1N_Pos = 0x4        // Position of RF1N field.
	FDCAN_FDCAN_IR_RF1N_Msk = 0x10       // Bit mask of RF1N field.
	FDCAN_FDCAN_IR_RF1N     = 0x10       // Bit RF1N.
	FDCAN_FDCAN_IR_RF1W_Pos = 0x5        // Position of RF1W field.
	FDCAN_FDCAN_IR_RF1W_Msk = 0x20       // Bit mask of RF1W field.
	FDCAN_FDCAN_IR_RF1W     = 0x20       // Bit RF1W.
	FDCAN_FDCAN_IR_RF1F_Pos = 0x6        // Position of RF1F field.
	FDCAN_FDCAN_IR_RF1F_Msk = 0x40       // Bit mask of RF1F field.
	FDCAN_FDCAN_IR_RF1F     = 0x40       // Bit RF1F.
	FDCAN_FDCAN_IR_RF1L_Pos = 0x7        // Position of RF1L field.
	FDCAN_FDCAN_IR_RF1L_Msk = 0x80       // Bit mask of RF1L field.
	FDCAN_FDCAN_IR_RF1L     = 0x80       // Bit RF1L.
	FDCAN_FDCAN_IR_HPM_Pos  = 0x8        // Position of HPM field.
	FDCAN_FDCAN_IR_HPM_Msk  = 0x100      // Bit mask of HPM field.
	FDCAN_FDCAN_IR_HPM      = 0x100      // Bit HPM.
	FDCAN_FDCAN_IR_TC_Pos   = 0x9        // Position of TC field.
	FDCAN_FDCAN_IR_TC_Msk   = 0x200      // Bit mask of TC field.
	FDCAN_FDCAN_IR_TC       = 0x200      // Bit TC.
	FDCAN_FDCAN_IR_TCF_Pos  = 0xa        // Position of TCF field.
	FDCAN_FDCAN_IR_TCF_Msk  = 0x400      // Bit mask of TCF field.
	FDCAN_FDCAN_IR_TCF      = 0x400      // Bit TCF.
	FDCAN_FDCAN_IR_TEF_Pos  = 0xb        // Position of TEF field.
	FDCAN_FDCAN_IR_TEF_Msk  = 0x800      // Bit mask of TEF field.
	FDCAN_FDCAN_IR_TEF      = 0x800      // Bit TEF.
	FDCAN_FDCAN_IR_TEFN_Pos = 0xc        // Position of TEFN field.
	FDCAN_FDCAN_IR_TEFN_Msk = 0x1000     // Bit mask of TEFN field.
	FDCAN_FDCAN_IR_TEFN     = 0x1000     // Bit TEFN.
	FDCAN_FDCAN_IR_TEFW_Pos = 0xd        // Position of TEFW field.
	FDCAN_FDCAN_IR_TEFW_Msk = 0x2000     // Bit mask of TEFW field.
	FDCAN_FDCAN_IR_TEFW     = 0x2000     // Bit TEFW.
	FDCAN_FDCAN_IR_TEFF_Pos = 0xe        // Position of TEFF field.
	FDCAN_FDCAN_IR_TEFF_Msk = 0x4000     // Bit mask of TEFF field.
	FDCAN_FDCAN_IR_TEFF     = 0x4000     // Bit TEFF.
	FDCAN_FDCAN_IR_TEFL_Pos = 0xf        // Position of TEFL field.
	FDCAN_FDCAN_IR_TEFL_Msk = 0x8000     // Bit mask of TEFL field.
	FDCAN_FDCAN_IR_TEFL     = 0x8000     // Bit TEFL.
	FDCAN_FDCAN_IR_TSW_Pos  = 0x10       // Position of TSW field.
	FDCAN_FDCAN_IR_TSW_Msk  = 0x10000    // Bit mask of TSW field.
	FDCAN_FDCAN_IR_TSW      = 0x10000    // Bit TSW.
	FDCAN_FDCAN_IR_MRAF_Pos = 0x11       // Position of MRAF field.
	FDCAN_FDCAN_IR_MRAF_Msk = 0x20000    // Bit mask of MRAF field.
	FDCAN_FDCAN_IR_MRAF     = 0x20000    // Bit MRAF.
	FDCAN_FDCAN_IR_TOO_Pos  = 0x12       // Position of TOO field.
	FDCAN_FDCAN_IR_TOO_Msk  = 0x40000    // Bit mask of TOO field.
	FDCAN_FDCAN_IR_TOO      = 0x40000    // Bit TOO.
	FDCAN_FDCAN_IR_DRX_Pos  = 0x13       // Position of DRX field.
	FDCAN_FDCAN_IR_DRX_Msk  = 0x80000    // Bit mask of DRX field.
	FDCAN_FDCAN_IR_DRX      = 0x80000    // Bit DRX.
	FDCAN_FDCAN_IR_ELO_Pos  = 0x16       // Position of ELO field.
	FDCAN_FDCAN_IR_ELO_Msk  = 0x400000   // Bit mask of ELO field.
	FDCAN_FDCAN_IR_ELO      = 0x400000   // Bit ELO.
	FDCAN_FDCAN_IR_EP_Pos   = 0x17       // Position of EP field.
	FDCAN_FDCAN_IR_EP_Msk   = 0x800000   // Bit mask of EP field.
	FDCAN_FDCAN_IR_EP       = 0x800000   // Bit EP.
	FDCAN_FDCAN_IR_EW_Pos   = 0x18       // Position of EW field.
	FDCAN_FDCAN_IR_EW_Msk   = 0x1000000  // Bit mask of EW field.
	FDCAN_FDCAN_IR_EW       = 0x1000000  // Bit EW.
	FDCAN_FDCAN_IR_BO_Pos   = 0x19       // Position of BO field.
	FDCAN_FDCAN_IR_BO_Msk   = 0x2000000  // Bit mask of BO field.
	FDCAN_FDCAN_IR_BO       = 0x2000000  // Bit BO.
	FDCAN_FDCAN_IR_WDI_Pos  = 0x1a       // Position of WDI field.
	FDCAN_FDCAN_IR_WDI_Msk  = 0x4000000  // Bit mask of WDI field.
	FDCAN_FDCAN_IR_WDI      = 0x4000000  // Bit WDI.
	FDCAN_FDCAN_IR_PEA_Pos  = 0x1b       // Position of PEA field.
	FDCAN_FDCAN_IR_PEA_Msk  = 0x8000000  // Bit mask of PEA field.
	FDCAN_FDCAN_IR_PEA      = 0x8000000  // Bit PEA.
	FDCAN_FDCAN_IR_PED_Pos  = 0x1c       // Position of PED field.
	FDCAN_FDCAN_IR_PED_Msk  = 0x10000000 // Bit mask of PED field.
	FDCAN_FDCAN_IR_PED      = 0x10000000 // Bit PED.
	FDCAN_FDCAN_IR_ARA_Pos  = 0x1d       // Position of ARA field.
	FDCAN_FDCAN_IR_ARA_Msk  = 0x20000000 // Bit mask of ARA field.
	FDCAN_FDCAN_IR_ARA      = 0x20000000 // Bit ARA.

	// FDCAN_IE: FDCAN Interrupt Enable           Register
	FDCAN_FDCAN_IE_RF0NE_Pos = 0x0        // Position of RF0NE field.
	FDCAN_FDCAN_IE_RF0NE_Msk = 0x1        // Bit mask of RF0NE field.
	FDCAN_FDCAN_IE_RF0NE     = 0x1        // Bit RF0NE.
	FDCAN_FDCAN_IE_RF0WE_Pos = 0x1        // Position of RF0WE field.
	FDCAN_FDCAN_IE_RF0WE_Msk = 0x2        // Bit mask of RF0WE field.
	FDCAN_FDCAN_IE_RF0WE     = 0x2        // Bit RF0WE.
	FDCAN_FDCAN_IE_RF0FE_Pos = 0x2        // Position of RF0FE field.
	FDCAN_FDCAN_IE_RF0FE_Msk = 0x4        // Bit mask of RF0FE field.
	FDCAN_FDCAN_IE_RF0FE     = 0x4        // Bit RF0FE.
	FDCAN_FDCAN_IE_RF0LE_Pos = 0x3        // Position of RF0LE field.
	FDCAN_FDCAN_IE_RF0LE_Msk = 0x8        // Bit mask of RF0LE field.
	FDCAN_FDCAN_IE_RF0LE     = 0x8        // Bit RF0LE.
	FDCAN_FDCAN_IE_RF1NE_Pos = 0x4        // Position of RF1NE field.
	FDCAN_FDCAN_IE_RF1NE_Msk = 0x10       // Bit mask of RF1NE field.
	FDCAN_FDCAN_IE_RF1NE     = 0x10       // Bit RF1NE.
	FDCAN_FDCAN_IE_RF1WE_Pos = 0x5        // Position of RF1WE field.
	FDCAN_FDCAN_IE_RF1WE_Msk = 0x20       // Bit mask of RF1WE field.
	FDCAN_FDCAN_IE_RF1WE     = 0x20       // Bit RF1WE.
	FDCAN_FDCAN_IE_RF1FE_Pos = 0x6        // Position of RF1FE field.
	FDCAN_FDCAN_IE_RF1FE_Msk = 0x40       // Bit mask of RF1FE field.
	FDCAN_FDCAN_IE_RF1FE     = 0x40       // Bit RF1FE.
	FDCAN_FDCAN_IE_RF1LE_Pos = 0x7        // Position of RF1LE field.
	FDCAN_FDCAN_IE_RF1LE_Msk = 0x80       // Bit mask of RF1LE field.
	FDCAN_FDCAN_IE_RF1LE     = 0x80       // Bit RF1LE.
	FDCAN_FDCAN_IE_HPME_Pos  = 0x8        // Position of HPME field.
	FDCAN_FDCAN_IE_HPME_Msk  = 0x100      // Bit mask of HPME field.
	FDCAN_FDCAN_IE_HPME      = 0x100      // Bit HPME.
	FDCAN_FDCAN_IE_TCE_Pos   = 0x9        // Position of TCE field.
	FDCAN_FDCAN_IE_TCE_Msk   = 0x200      // Bit mask of TCE field.
	FDCAN_FDCAN_IE_TCE       = 0x200      // Bit TCE.
	FDCAN_FDCAN_IE_TCFE_Pos  = 0xa        // Position of TCFE field.
	FDCAN_FDCAN_IE_TCFE_Msk  = 0x400      // Bit mask of TCFE field.
	FDCAN_FDCAN_IE_TCFE      = 0x400      // Bit TCFE.
	FDCAN_FDCAN_IE_TEFE_Pos  = 0xb        // Position of TEFE field.
	FDCAN_FDCAN_IE_TEFE_Msk  = 0x800      // Bit mask of TEFE field.
	FDCAN_FDCAN_IE_TEFE      = 0x800      // Bit TEFE.
	FDCAN_FDCAN_IE_TEFNE_Pos = 0xc        // Position of TEFNE field.
	FDCAN_FDCAN_IE_TEFNE_Msk = 0x1000     // Bit mask of TEFNE field.
	FDCAN_FDCAN_IE_TEFNE     = 0x1000     // Bit TEFNE.
	FDCAN_FDCAN_IE_TEFWE_Pos = 0xd        // Position of TEFWE field.
	FDCAN_FDCAN_IE_TEFWE_Msk = 0x2000     // Bit mask of TEFWE field.
	FDCAN_FDCAN_IE_TEFWE     = 0x2000     // Bit TEFWE.
	FDCAN_FDCAN_IE_TEFFE_Pos = 0xe        // Position of TEFFE field.
	FDCAN_FDCAN_IE_TEFFE_Msk = 0x4000     // Bit mask of TEFFE field.
	FDCAN_FDCAN_IE_TEFFE     = 0x4000     // Bit TEFFE.
	FDCAN_FDCAN_IE_TEFLE_Pos = 0xf        // Position of TEFLE field.
	FDCAN_FDCAN_IE_TEFLE_Msk = 0x8000     // Bit mask of TEFLE field.
	FDCAN_FDCAN_IE_TEFLE     = 0x8000     // Bit TEFLE.
	FDCAN_FDCAN_IE_TSWE_Pos  = 0x10       // Position of TSWE field.
	FDCAN_FDCAN_IE_TSWE_Msk  = 0x10000    // Bit mask of TSWE field.
	FDCAN_FDCAN_IE_TSWE      = 0x10000    // Bit TSWE.
	FDCAN_FDCAN_IE_MRAFE_Pos = 0x11       // Position of MRAFE field.
	FDCAN_FDCAN_IE_MRAFE_Msk = 0x20000    // Bit mask of MRAFE field.
	FDCAN_FDCAN_IE_MRAFE     = 0x20000    // Bit MRAFE.
	FDCAN_FDCAN_IE_TOOE_Pos  = 0x12       // Position of TOOE field.
	FDCAN_FDCAN_IE_TOOE_Msk  = 0x40000    // Bit mask of TOOE field.
	FDCAN_FDCAN_IE_TOOE      = 0x40000    // Bit TOOE.
	FDCAN_FDCAN_IE_DRXE_Pos  = 0x13       // Position of DRXE field.
	FDCAN_FDCAN_IE_DRXE_Msk  = 0x80000    // Bit mask of DRXE field.
	FDCAN_FDCAN_IE_DRXE      = 0x80000    // Bit DRXE.
	FDCAN_FDCAN_IE_BECE_Pos  = 0x14       // Position of BECE field.
	FDCAN_FDCAN_IE_BECE_Msk  = 0x100000   // Bit mask of BECE field.
	FDCAN_FDCAN_IE_BECE      = 0x100000   // Bit BECE.
	FDCAN_FDCAN_IE_BEUE_Pos  = 0x15       // Position of BEUE field.
	FDCAN_FDCAN_IE_BEUE_Msk  = 0x200000   // Bit mask of BEUE field.
	FDCAN_FDCAN_IE_BEUE      = 0x200000   // Bit BEUE.
	FDCAN_FDCAN_IE_ELOE_Pos  = 0x16       // Position of ELOE field.
	FDCAN_FDCAN_IE_ELOE_Msk  = 0x400000   // Bit mask of ELOE field.
	FDCAN_FDCAN_IE_ELOE      = 0x400000   // Bit ELOE.
	FDCAN_FDCAN_IE_EPE_Pos   = 0x17       // Position of EPE field.
	FDCAN_FDCAN_IE_EPE_Msk   = 0x800000   // Bit mask of EPE field.
	FDCAN_FDCAN_IE_EPE       = 0x800000   // Bit EPE.
	FDCAN_FDCAN_IE_EWE_Pos   = 0x18       // Position of EWE field.
	FDCAN_FDCAN_IE_EWE_Msk   = 0x1000000  // Bit mask of EWE field.
	FDCAN_FDCAN_IE_EWE       = 0x1000000  // Bit EWE.
	FDCAN_FDCAN_IE_BOE_Pos   = 0x19       // Position of BOE field.
	FDCAN_FDCAN_IE_BOE_Msk   = 0x2000000  // Bit mask of BOE field.
	FDCAN_FDCAN_IE_BOE       = 0x2000000  // Bit BOE.
	FDCAN_FDCAN_IE_WDIE_Pos  = 0x1a       // Position of WDIE field.
	FDCAN_FDCAN_IE_WDIE_Msk  = 0x4000000  // Bit mask of WDIE field.
	FDCAN_FDCAN_IE_WDIE      = 0x4000000  // Bit WDIE.
	FDCAN_FDCAN_IE_PEAE_Pos  = 0x1b       // Position of PEAE field.
	FDCAN_FDCAN_IE_PEAE_Msk  = 0x8000000  // Bit mask of PEAE field.
	FDCAN_FDCAN_IE_PEAE      = 0x8000000  // Bit PEAE.
	FDCAN_FDCAN_IE_PEDE_Pos  = 0x1c       // Position of PEDE field.
	FDCAN_FDCAN_IE_PEDE_Msk  = 0x10000000 // Bit mask of PEDE field.
	FDCAN_FDCAN_IE_PEDE      = 0x10000000 // Bit PEDE.
	FDCAN_FDCAN_IE_ARAE_Pos  = 0x1d       // Position of ARAE field.
	FDCAN_FDCAN_IE_ARAE_Msk  = 0x20000000 // Bit mask of ARAE field.
	FDCAN_FDCAN_IE_ARAE      = 0x20000000 // Bit ARAE.

	// FDCAN_ILS: FDCAN Interrupt Line Select           Register
	FDCAN_FDCAN_ILS_RF0NL_Pos = 0x0        // Position of RF0NL field.
	FDCAN_FDCAN_ILS_RF0NL_Msk = 0x1        // Bit mask of RF0NL field.
	FDCAN_FDCAN_ILS_RF0NL     = 0x1        // Bit RF0NL.
	FDCAN_FDCAN_ILS_RF0WL_Pos = 0x1        // Position of RF0WL field.
	FDCAN_FDCAN_ILS_RF0WL_Msk = 0x2        // Bit mask of RF0WL field.
	FDCAN_FDCAN_ILS_RF0WL     = 0x2        // Bit RF0WL.
	FDCAN_FDCAN_ILS_RF0FL_Pos = 0x2        // Position of RF0FL field.
	FDCAN_FDCAN_ILS_RF0FL_Msk = 0x4        // Bit mask of RF0FL field.
	FDCAN_FDCAN_ILS_RF0FL     = 0x4        // Bit RF0FL.
	FDCAN_FDCAN_ILS_RF0LL_Pos = 0x3        // Position of RF0LL field.
	FDCAN_FDCAN_ILS_RF0LL_Msk = 0x8        // Bit mask of RF0LL field.
	FDCAN_FDCAN_ILS_RF0LL     = 0x8        // Bit RF0LL.
	FDCAN_FDCAN_ILS_RF1NL_Pos = 0x4        // Position of RF1NL field.
	FDCAN_FDCAN_ILS_RF1NL_Msk = 0x10       // Bit mask of RF1NL field.
	FDCAN_FDCAN_ILS_RF1NL     = 0x10       // Bit RF1NL.
	FDCAN_FDCAN_ILS_RF1WL_Pos = 0x5        // Position of RF1WL field.
	FDCAN_FDCAN_ILS_RF1WL_Msk = 0x20       // Bit mask of RF1WL field.
	FDCAN_FDCAN_ILS_RF1WL     = 0x20       // Bit RF1WL.
	FDCAN_FDCAN_ILS_RF1FL_Pos = 0x6        // Position of RF1FL field.
	FDCAN_FDCAN_ILS_RF1FL_Msk = 0x40       // Bit mask of RF1FL field.
	FDCAN_FDCAN_ILS_RF1FL     = 0x40       // Bit RF1FL.
	FDCAN_FDCAN_ILS_RF1LL_Pos = 0x7        // Position of RF1LL field.
	FDCAN_FDCAN_ILS_RF1LL_Msk = 0x80       // Bit mask of RF1LL field.
	FDCAN_FDCAN_ILS_RF1LL     = 0x80       // Bit RF1LL.
	FDCAN_FDCAN_ILS_HPML_Pos  = 0x8        // Position of HPML field.
	FDCAN_FDCAN_ILS_HPML_Msk  = 0x100      // Bit mask of HPML field.
	FDCAN_FDCAN_ILS_HPML      = 0x100      // Bit HPML.
	FDCAN_FDCAN_ILS_TCL_Pos   = 0x9        // Position of TCL field.
	FDCAN_FDCAN_ILS_TCL_Msk   = 0x200      // Bit mask of TCL field.
	FDCAN_FDCAN_ILS_TCL       = 0x200      // Bit TCL.
	FDCAN_FDCAN_ILS_TCFL_Pos  = 0xa        // Position of TCFL field.
	FDCAN_FDCAN_ILS_TCFL_Msk  = 0x400      // Bit mask of TCFL field.
	FDCAN_FDCAN_ILS_TCFL      = 0x400      // Bit TCFL.
	FDCAN_FDCAN_ILS_TEFL_Pos  = 0xb        // Position of TEFL field.
	FDCAN_FDCAN_ILS_TEFL_Msk  = 0x800      // Bit mask of TEFL field.
	FDCAN_FDCAN_ILS_TEFL      = 0x800      // Bit TEFL.
	FDCAN_FDCAN_ILS_TEFNL_Pos = 0xc        // Position of TEFNL field.
	FDCAN_FDCAN_ILS_TEFNL_Msk = 0x1000     // Bit mask of TEFNL field.
	FDCAN_FDCAN_ILS_TEFNL     = 0x1000     // Bit TEFNL.
	FDCAN_FDCAN_ILS_TEFWL_Pos = 0xd        // Position of TEFWL field.
	FDCAN_FDCAN_ILS_TEFWL_Msk = 0x2000     // Bit mask of TEFWL field.
	FDCAN_FDCAN_ILS_TEFWL     = 0x2000     // Bit TEFWL.
	FDCAN_FDCAN_ILS_TEFFL_Pos = 0xe        // Position of TEFFL field.
	FDCAN_FDCAN_ILS_TEFFL_Msk = 0x4000     // Bit mask of TEFFL field.
	FDCAN_FDCAN_ILS_TEFFL     = 0x4000     // Bit TEFFL.
	FDCAN_FDCAN_ILS_TEFLL_Pos = 0xf        // Position of TEFLL field.
	FDCAN_FDCAN_ILS_TEFLL_Msk = 0x8000     // Bit mask of TEFLL field.
	FDCAN_FDCAN_ILS_TEFLL     = 0x8000     // Bit TEFLL.
	FDCAN_FDCAN_ILS_TSWL_Pos  = 0x10       // Position of TSWL field.
	FDCAN_FDCAN_ILS_TSWL_Msk  = 0x10000    // Bit mask of TSWL field.
	FDCAN_FDCAN_ILS_TSWL      = 0x10000    // Bit TSWL.
	FDCAN_FDCAN_ILS_MRAFL_Pos = 0x11       // Position of MRAFL field.
	FDCAN_FDCAN_ILS_MRAFL_Msk = 0x20000    // Bit mask of MRAFL field.
	FDCAN_FDCAN_ILS_MRAFL     = 0x20000    // Bit MRAFL.
	FDCAN_FDCAN_ILS_TOOL_Pos  = 0x12       // Position of TOOL field.
	FDCAN_FDCAN_ILS_TOOL_Msk  = 0x40000    // Bit mask of TOOL field.
	FDCAN_FDCAN_ILS_TOOL      = 0x40000    // Bit TOOL.
	FDCAN_FDCAN_ILS_DRXL_Pos  = 0x13       // Position of DRXL field.
	FDCAN_FDCAN_ILS_DRXL_Msk  = 0x80000    // Bit mask of DRXL field.
	FDCAN_FDCAN_ILS_DRXL      = 0x80000    // Bit DRXL.
	FDCAN_FDCAN_ILS_BECL_Pos  = 0x14       // Position of BECL field.
	FDCAN_FDCAN_ILS_BECL_Msk  = 0x100000   // Bit mask of BECL field.
	FDCAN_FDCAN_ILS_BECL      = 0x100000   // Bit BECL.
	FDCAN_FDCAN_ILS_BEUL_Pos  = 0x15       // Position of BEUL field.
	FDCAN_FDCAN_ILS_BEUL_Msk  = 0x200000   // Bit mask of BEUL field.
	FDCAN_FDCAN_ILS_BEUL      = 0x200000   // Bit BEUL.
	FDCAN_FDCAN_ILS_ELOL_Pos  = 0x16       // Position of ELOL field.
	FDCAN_FDCAN_ILS_ELOL_Msk  = 0x400000   // Bit mask of ELOL field.
	FDCAN_FDCAN_ILS_ELOL      = 0x400000   // Bit ELOL.
	FDCAN_FDCAN_ILS_EPL_Pos   = 0x17       // Position of EPL field.
	FDCAN_FDCAN_ILS_EPL_Msk   = 0x800000   // Bit mask of EPL field.
	FDCAN_FDCAN_ILS_EPL       = 0x800000   // Bit EPL.
	FDCAN_FDCAN_ILS_EWL_Pos   = 0x18       // Position of EWL field.
	FDCAN_FDCAN_ILS_EWL_Msk   = 0x1000000  // Bit mask of EWL field.
	FDCAN_FDCAN_ILS_EWL       = 0x1000000  // Bit EWL.
	FDCAN_FDCAN_ILS_BOL_Pos   = 0x19       // Position of BOL field.
	FDCAN_FDCAN_ILS_BOL_Msk   = 0x2000000  // Bit mask of BOL field.
	FDCAN_FDCAN_ILS_BOL       = 0x2000000  // Bit BOL.
	FDCAN_FDCAN_ILS_WDIL_Pos  = 0x1a       // Position of WDIL field.
	FDCAN_FDCAN_ILS_WDIL_Msk  = 0x4000000  // Bit mask of WDIL field.
	FDCAN_FDCAN_ILS_WDIL      = 0x4000000  // Bit WDIL.
	FDCAN_FDCAN_ILS_PEAL_Pos  = 0x1b       // Position of PEAL field.
	FDCAN_FDCAN_ILS_PEAL_Msk  = 0x8000000  // Bit mask of PEAL field.
	FDCAN_FDCAN_ILS_PEAL      = 0x8000000  // Bit PEAL.
	FDCAN_FDCAN_ILS_PEDL_Pos  = 0x1c       // Position of PEDL field.
	FDCAN_FDCAN_ILS_PEDL_Msk  = 0x10000000 // Bit mask of PEDL field.
	FDCAN_FDCAN_ILS_PEDL      = 0x10000000 // Bit PEDL.
	FDCAN_FDCAN_ILS_ARAL_Pos  = 0x1d       // Position of ARAL field.
	FDCAN_FDCAN_ILS_ARAL_Msk  = 0x20000000 // Bit mask of ARAL field.
	FDCAN_FDCAN_ILS_ARAL      = 0x20000000 // Bit ARAL.

	// FDCAN_ILE: FDCAN Interrupt Line Enable           Register
	FDCAN_FDCAN_ILE_EINT0_Pos = 0x0 // Position of EINT0 field.
	FDCAN_FDCAN_ILE_EINT0_Msk = 0x1 // Bit mask of EINT0 field.
	FDCAN_FDCAN_ILE_EINT0     = 0x1 // Bit EINT0.
	FDCAN_FDCAN_ILE_EINT1_Pos = 0x1 // Position of EINT1 field.
	FDCAN_FDCAN_ILE_EINT1_Msk = 0x2 // Bit mask of EINT1 field.
	FDCAN_FDCAN_ILE_EINT1     = 0x2 // Bit EINT1.

	// FDCAN_GFC: FDCAN Global Filter Configuration           Register
	FDCAN_FDCAN_GFC_RRFE_Pos = 0x0  // Position of RRFE field.
	FDCAN_FDCAN_GFC_RRFE_Msk = 0x1  // Bit mask of RRFE field.
	FDCAN_FDCAN_GFC_RRFE     = 0x1  // Bit RRFE.
	FDCAN_FDCAN_GFC_RRFS_Pos = 0x1  // Position of RRFS field.
	FDCAN_FDCAN_GFC_RRFS_Msk = 0x2  // Bit mask of RRFS field.
	FDCAN_FDCAN_GFC_RRFS     = 0x2  // Bit RRFS.
	FDCAN_FDCAN_GFC_ANFE_Pos = 0x2  // Position of ANFE field.
	FDCAN_FDCAN_GFC_ANFE_Msk = 0xc  // Bit mask of ANFE field.
	FDCAN_FDCAN_GFC_ANFS_Pos = 0x4  // Position of ANFS field.
	FDCAN_FDCAN_GFC_ANFS_Msk = 0x30 // Bit mask of ANFS field.

	// FDCAN_SIDFC: FDCAN Standard ID Filter Configuration           Register
	FDCAN_FDCAN_SIDFC_FLSSA_Pos = 0x2      // Position of FLSSA field.
	FDCAN_FDCAN_SIDFC_FLSSA_Msk = 0xfffc   // Bit mask of FLSSA field.
	FDCAN_FDCAN_SIDFC_LSS_Pos   = 0x10     // Position of LSS field.
	FDCAN_FDCAN_SIDFC_LSS_Msk   = 0xff0000 // Bit mask of LSS field.

	// FDCAN_XIDFC: FDCAN Extended ID Filter Configuration           Register
	FDCAN_FDCAN_XIDFC_FLESA_Pos = 0x2      // Position of FLESA field.
	FDCAN_FDCAN_XIDFC_FLESA_Msk = 0xfffc   // Bit mask of FLESA field.
	FDCAN_FDCAN_XIDFC_LSE_Pos   = 0x10     // Position of LSE field.
	FDCAN_FDCAN_XIDFC_LSE_Msk   = 0xff0000 // Bit mask of LSE field.

	// FDCAN_XIDAM: FDCAN Extended ID and Mask           Register
	FDCAN_FDCAN_XIDAM_EIDM_Pos = 0x0        // Position of EIDM field.
	FDCAN_FDCAN_XIDAM_EIDM_Msk = 0x1fffffff // Bit mask of EIDM field.

	// FDCAN_HPMS: FDCAN High Priority Message Status           Register
	FDCAN_FDCAN_HPMS_BIDX_Pos = 0x0    // Position of BIDX field.
	FDCAN_FDCAN_HPMS_BIDX_Msk = 0x3f   // Bit mask of BIDX field.
	FDCAN_FDCAN_HPMS_MSI_Pos  = 0x6    // Position of MSI field.
	FDCAN_FDCAN_HPMS_MSI_Msk  = 0xc0   // Bit mask of MSI field.
	FDCAN_FDCAN_HPMS_FIDX_Pos = 0x8    // Position of FIDX field.
	FDCAN_FDCAN_HPMS_FIDX_Msk = 0x7f00 // Bit mask of FIDX field.
	FDCAN_FDCAN_HPMS_FLST_Pos = 0xf    // Position of FLST field.
	FDCAN_FDCAN_HPMS_FLST_Msk = 0x8000 // Bit mask of FLST field.
	FDCAN_FDCAN_HPMS_FLST     = 0x8000 // Bit FLST.

	// FDCAN_NDAT1: FDCAN New Data 1 Register
	FDCAN_FDCAN_NDAT1_ND0_Pos  = 0x0        // Position of ND0 field.
	FDCAN_FDCAN_NDAT1_ND0_Msk  = 0x1        // Bit mask of ND0 field.
	FDCAN_FDCAN_NDAT1_ND0      = 0x1        // Bit ND0.
	FDCAN_FDCAN_NDAT1_ND1_Pos  = 0x1        // Position of ND1 field.
	FDCAN_FDCAN_NDAT1_ND1_Msk  = 0x2        // Bit mask of ND1 field.
	FDCAN_FDCAN_NDAT1_ND1      = 0x2        // Bit ND1.
	FDCAN_FDCAN_NDAT1_ND2_Pos  = 0x2        // Position of ND2 field.
	FDCAN_FDCAN_NDAT1_ND2_Msk  = 0x4        // Bit mask of ND2 field.
	FDCAN_FDCAN_NDAT1_ND2      = 0x4        // Bit ND2.
	FDCAN_FDCAN_NDAT1_ND3_Pos  = 0x3        // Position of ND3 field.
	FDCAN_FDCAN_NDAT1_ND3_Msk  = 0x8        // Bit mask of ND3 field.
	FDCAN_FDCAN_NDAT1_ND3      = 0x8        // Bit ND3.
	FDCAN_FDCAN_NDAT1_ND4_Pos  = 0x4        // Position of ND4 field.
	FDCAN_FDCAN_NDAT1_ND4_Msk  = 0x10       // Bit mask of ND4 field.
	FDCAN_FDCAN_NDAT1_ND4      = 0x10       // Bit ND4.
	FDCAN_FDCAN_NDAT1_ND5_Pos  = 0x5        // Position of ND5 field.
	FDCAN_FDCAN_NDAT1_ND5_Msk  = 0x20       // Bit mask of ND5 field.
	FDCAN_FDCAN_NDAT1_ND5      = 0x20       // Bit ND5.
	FDCAN_FDCAN_NDAT1_ND6_Pos  = 0x6        // Position of ND6 field.
	FDCAN_FDCAN_NDAT1_ND6_Msk  = 0x40       // Bit mask of ND6 field.
	FDCAN_FDCAN_NDAT1_ND6      = 0x40       // Bit ND6.
	FDCAN_FDCAN_NDAT1_ND7_Pos  = 0x7        // Position of ND7 field.
	FDCAN_FDCAN_NDAT1_ND7_Msk  = 0x80       // Bit mask of ND7 field.
	FDCAN_FDCAN_NDAT1_ND7      = 0x80       // Bit ND7.
	FDCAN_FDCAN_NDAT1_ND8_Pos  = 0x8        // Position of ND8 field.
	FDCAN_FDCAN_NDAT1_ND8_Msk  = 0x100      // Bit mask of ND8 field.
	FDCAN_FDCAN_NDAT1_ND8      = 0x100      // Bit ND8.
	FDCAN_FDCAN_NDAT1_ND9_Pos  = 0x9        // Position of ND9 field.
	FDCAN_FDCAN_NDAT1_ND9_Msk  = 0x200      // Bit mask of ND9 field.
	FDCAN_FDCAN_NDAT1_ND9      = 0x200      // Bit ND9.
	FDCAN_FDCAN_NDAT1_ND10_Pos = 0xa        // Position of ND10 field.
	FDCAN_FDCAN_NDAT1_ND10_Msk = 0x400      // Bit mask of ND10 field.
	FDCAN_FDCAN_NDAT1_ND10     = 0x400      // Bit ND10.
	FDCAN_FDCAN_NDAT1_ND11_Pos = 0xb        // Position of ND11 field.
	FDCAN_FDCAN_NDAT1_ND11_Msk = 0x800      // Bit mask of ND11 field.
	FDCAN_FDCAN_NDAT1_ND11     = 0x800      // Bit ND11.
	FDCAN_FDCAN_NDAT1_ND12_Pos = 0xc        // Position of ND12 field.
	FDCAN_FDCAN_NDAT1_ND12_Msk = 0x1000     // Bit mask of ND12 field.
	FDCAN_FDCAN_NDAT1_ND12     = 0x1000     // Bit ND12.
	FDCAN_FDCAN_NDAT1_ND13_Pos = 0xd        // Position of ND13 field.
	FDCAN_FDCAN_NDAT1_ND13_Msk = 0x2000     // Bit mask of ND13 field.
	FDCAN_FDCAN_NDAT1_ND13     = 0x2000     // Bit ND13.
	FDCAN_FDCAN_NDAT1_ND14_Pos = 0xe        // Position of ND14 field.
	FDCAN_FDCAN_NDAT1_ND14_Msk = 0x4000     // Bit mask of ND14 field.
	FDCAN_FDCAN_NDAT1_ND14     = 0x4000     // Bit ND14.
	FDCAN_FDCAN_NDAT1_ND15_Pos = 0xf        // Position of ND15 field.
	FDCAN_FDCAN_NDAT1_ND15_Msk = 0x8000     // Bit mask of ND15 field.
	FDCAN_FDCAN_NDAT1_ND15     = 0x8000     // Bit ND15.
	FDCAN_FDCAN_NDAT1_ND16_Pos = 0x10       // Position of ND16 field.
	FDCAN_FDCAN_NDAT1_ND16_Msk = 0x10000    // Bit mask of ND16 field.
	FDCAN_FDCAN_NDAT1_ND16     = 0x10000    // Bit ND16.
	FDCAN_FDCAN_NDAT1_ND17_Pos = 0x11       // Position of ND17 field.
	FDCAN_FDCAN_NDAT1_ND17_Msk = 0x20000    // Bit mask of ND17 field.
	FDCAN_FDCAN_NDAT1_ND17     = 0x20000    // Bit ND17.
	FDCAN_FDCAN_NDAT1_ND18_Pos = 0x12       // Position of ND18 field.
	FDCAN_FDCAN_NDAT1_ND18_Msk = 0x40000    // Bit mask of ND18 field.
	FDCAN_FDCAN_NDAT1_ND18     = 0x40000    // Bit ND18.
	FDCAN_FDCAN_NDAT1_ND19_Pos = 0x13       // Position of ND19 field.
	FDCAN_FDCAN_NDAT1_ND19_Msk = 0x80000    // Bit mask of ND19 field.
	FDCAN_FDCAN_NDAT1_ND19     = 0x80000    // Bit ND19.
	FDCAN_FDCAN_NDAT1_ND20_Pos = 0x14       // Position of ND20 field.
	FDCAN_FDCAN_NDAT1_ND20_Msk = 0x100000   // Bit mask of ND20 field.
	FDCAN_FDCAN_NDAT1_ND20     = 0x100000   // Bit ND20.
	FDCAN_FDCAN_NDAT1_ND21_Pos = 0x15       // Position of ND21 field.
	FDCAN_FDCAN_NDAT1_ND21_Msk = 0x200000   // Bit mask of ND21 field.
	FDCAN_FDCAN_NDAT1_ND21     = 0x200000   // Bit ND21.
	FDCAN_FDCAN_NDAT1_ND22_Pos = 0x16       // Position of ND22 field.
	FDCAN_FDCAN_NDAT1_ND22_Msk = 0x400000   // Bit mask of ND22 field.
	FDCAN_FDCAN_NDAT1_ND22     = 0x400000   // Bit ND22.
	FDCAN_FDCAN_NDAT1_ND23_Pos = 0x17       // Position of ND23 field.
	FDCAN_FDCAN_NDAT1_ND23_Msk = 0x800000   // Bit mask of ND23 field.
	FDCAN_FDCAN_NDAT1_ND23     = 0x800000   // Bit ND23.
	FDCAN_FDCAN_NDAT1_ND24_Pos = 0x18       // Position of ND24 field.
	FDCAN_FDCAN_NDAT1_ND24_Msk = 0x1000000  // Bit mask of ND24 field.
	FDCAN_FDCAN_NDAT1_ND24     = 0x1000000  // Bit ND24.
	FDCAN_FDCAN_NDAT1_ND25_Pos = 0x19       // Position of ND25 field.
	FDCAN_FDCAN_NDAT1_ND25_Msk = 0x2000000  // Bit mask of ND25 field.
	FDCAN_FDCAN_NDAT1_ND25     = 0x2000000  // Bit ND25.
	FDCAN_FDCAN_NDAT1_ND26_Pos = 0x1a       // Position of ND26 field.
	FDCAN_FDCAN_NDAT1_ND26_Msk = 0x4000000  // Bit mask of ND26 field.
	FDCAN_FDCAN_NDAT1_ND26     = 0x4000000  // Bit ND26.
	FDCAN_FDCAN_NDAT1_ND27_Pos = 0x1b       // Position of ND27 field.
	FDCAN_FDCAN_NDAT1_ND27_Msk = 0x8000000  // Bit mask of ND27 field.
	FDCAN_FDCAN_NDAT1_ND27     = 0x8000000  // Bit ND27.
	FDCAN_FDCAN_NDAT1_ND28_Pos = 0x1c       // Position of ND28 field.
	FDCAN_FDCAN_NDAT1_ND28_Msk = 0x10000000 // Bit mask of ND28 field.
	FDCAN_FDCAN_NDAT1_ND28     = 0x10000000 // Bit ND28.
	FDCAN_FDCAN_NDAT1_ND29_Pos = 0x1d       // Position of ND29 field.
	FDCAN_FDCAN_NDAT1_ND29_Msk = 0x20000000 // Bit mask of ND29 field.
	FDCAN_FDCAN_NDAT1_ND29     = 0x20000000 // Bit ND29.
	FDCAN_FDCAN_NDAT1_ND30_Pos = 0x1e       // Position of ND30 field.
	FDCAN_FDCAN_NDAT1_ND30_Msk = 0x40000000 // Bit mask of ND30 field.
	FDCAN_FDCAN_NDAT1_ND30     = 0x40000000 // Bit ND30.
	FDCAN_FDCAN_NDAT1_ND31_Pos = 0x1f       // Position of ND31 field.
	FDCAN_FDCAN_NDAT1_ND31_Msk = 0x80000000 // Bit mask of ND31 field.
	FDCAN_FDCAN_NDAT1_ND31     = 0x80000000 // Bit ND31.

	// FDCAN_NDAT2: FDCAN New Data 2 Register
	FDCAN_FDCAN_NDAT2_ND32_Pos = 0x0        // Position of ND32 field.
	FDCAN_FDCAN_NDAT2_ND32_Msk = 0x1        // Bit mask of ND32 field.
	FDCAN_FDCAN_NDAT2_ND32     = 0x1        // Bit ND32.
	FDCAN_FDCAN_NDAT2_ND33_Pos = 0x1        // Position of ND33 field.
	FDCAN_FDCAN_NDAT2_ND33_Msk = 0x2        // Bit mask of ND33 field.
	FDCAN_FDCAN_NDAT2_ND33     = 0x2        // Bit ND33.
	FDCAN_FDCAN_NDAT2_ND34_Pos = 0x2        // Position of ND34 field.
	FDCAN_FDCAN_NDAT2_ND34_Msk = 0x4        // Bit mask of ND34 field.
	FDCAN_FDCAN_NDAT2_ND34     = 0x4        // Bit ND34.
	FDCAN_FDCAN_NDAT2_ND35_Pos = 0x3        // Position of ND35 field.
	FDCAN_FDCAN_NDAT2_ND35_Msk = 0x8        // Bit mask of ND35 field.
	FDCAN_FDCAN_NDAT2_ND35     = 0x8        // Bit ND35.
	FDCAN_FDCAN_NDAT2_ND36_Pos = 0x4        // Position of ND36 field.
	FDCAN_FDCAN_NDAT2_ND36_Msk = 0x10       // Bit mask of ND36 field.
	FDCAN_FDCAN_NDAT2_ND36     = 0x10       // Bit ND36.
	FDCAN_FDCAN_NDAT2_ND37_Pos = 0x5        // Position of ND37 field.
	FDCAN_FDCAN_NDAT2_ND37_Msk = 0x20       // Bit mask of ND37 field.
	FDCAN_FDCAN_NDAT2_ND37     = 0x20       // Bit ND37.
	FDCAN_FDCAN_NDAT2_ND38_Pos = 0x6        // Position of ND38 field.
	FDCAN_FDCAN_NDAT2_ND38_Msk = 0x40       // Bit mask of ND38 field.
	FDCAN_FDCAN_NDAT2_ND38     = 0x40       // Bit ND38.
	FDCAN_FDCAN_NDAT2_ND39_Pos = 0x7        // Position of ND39 field.
	FDCAN_FDCAN_NDAT2_ND39_Msk = 0x80       // Bit mask of ND39 field.
	FDCAN_FDCAN_NDAT2_ND39     = 0x80       // Bit ND39.
	FDCAN_FDCAN_NDAT2_ND40_Pos = 0x8        // Position of ND40 field.
	FDCAN_FDCAN_NDAT2_ND40_Msk = 0x100      // Bit mask of ND40 field.
	FDCAN_FDCAN_NDAT2_ND40     = 0x100      // Bit ND40.
	FDCAN_FDCAN_NDAT2_ND41_Pos = 0x9        // Position of ND41 field.
	FDCAN_FDCAN_NDAT2_ND41_Msk = 0x200      // Bit mask of ND41 field.
	FDCAN_FDCAN_NDAT2_ND41     = 0x200      // Bit ND41.
	FDCAN_FDCAN_NDAT2_ND42_Pos = 0xa        // Position of ND42 field.
	FDCAN_FDCAN_NDAT2_ND42_Msk = 0x400      // Bit mask of ND42 field.
	FDCAN_FDCAN_NDAT2_ND42     = 0x400      // Bit ND42.
	FDCAN_FDCAN_NDAT2_ND43_Pos = 0xb        // Position of ND43 field.
	FDCAN_FDCAN_NDAT2_ND43_Msk = 0x800      // Bit mask of ND43 field.
	FDCAN_FDCAN_NDAT2_ND43     = 0x800      // Bit ND43.
	FDCAN_FDCAN_NDAT2_ND44_Pos = 0xc        // Position of ND44 field.
	FDCAN_FDCAN_NDAT2_ND44_Msk = 0x1000     // Bit mask of ND44 field.
	FDCAN_FDCAN_NDAT2_ND44     = 0x1000     // Bit ND44.
	FDCAN_FDCAN_NDAT2_ND45_Pos = 0xd        // Position of ND45 field.
	FDCAN_FDCAN_NDAT2_ND45_Msk = 0x2000     // Bit mask of ND45 field.
	FDCAN_FDCAN_NDAT2_ND45     = 0x2000     // Bit ND45.
	FDCAN_FDCAN_NDAT2_ND46_Pos = 0xe        // Position of ND46 field.
	FDCAN_FDCAN_NDAT2_ND46_Msk = 0x4000     // Bit mask of ND46 field.
	FDCAN_FDCAN_NDAT2_ND46     = 0x4000     // Bit ND46.
	FDCAN_FDCAN_NDAT2_ND47_Pos = 0xf        // Position of ND47 field.
	FDCAN_FDCAN_NDAT2_ND47_Msk = 0x8000     // Bit mask of ND47 field.
	FDCAN_FDCAN_NDAT2_ND47     = 0x8000     // Bit ND47.
	FDCAN_FDCAN_NDAT2_ND48_Pos = 0x10       // Position of ND48 field.
	FDCAN_FDCAN_NDAT2_ND48_Msk = 0x10000    // Bit mask of ND48 field.
	FDCAN_FDCAN_NDAT2_ND48     = 0x10000    // Bit ND48.
	FDCAN_FDCAN_NDAT2_ND49_Pos = 0x11       // Position of ND49 field.
	FDCAN_FDCAN_NDAT2_ND49_Msk = 0x20000    // Bit mask of ND49 field.
	FDCAN_FDCAN_NDAT2_ND49     = 0x20000    // Bit ND49.
	FDCAN_FDCAN_NDAT2_ND50_Pos = 0x12       // Position of ND50 field.
	FDCAN_FDCAN_NDAT2_ND50_Msk = 0x40000    // Bit mask of ND50 field.
	FDCAN_FDCAN_NDAT2_ND50     = 0x40000    // Bit ND50.
	FDCAN_FDCAN_NDAT2_ND51_Pos = 0x13       // Position of ND51 field.
	FDCAN_FDCAN_NDAT2_ND51_Msk = 0x80000    // Bit mask of ND51 field.
	FDCAN_FDCAN_NDAT2_ND51     = 0x80000    // Bit ND51.
	FDCAN_FDCAN_NDAT2_ND52_Pos = 0x14       // Position of ND52 field.
	FDCAN_FDCAN_NDAT2_ND52_Msk = 0x100000   // Bit mask of ND52 field.
	FDCAN_FDCAN_NDAT2_ND52     = 0x100000   // Bit ND52.
	FDCAN_FDCAN_NDAT2_ND53_Pos = 0x15       // Position of ND53 field.
	FDCAN_FDCAN_NDAT2_ND53_Msk = 0x200000   // Bit mask of ND53 field.
	FDCAN_FDCAN_NDAT2_ND53     = 0x200000   // Bit ND53.
	FDCAN_FDCAN_NDAT2_ND54_Pos = 0x16       // Position of ND54 field.
	FDCAN_FDCAN_NDAT2_ND54_Msk = 0x400000   // Bit mask of ND54 field.
	FDCAN_FDCAN_NDAT2_ND54     = 0x400000   // Bit ND54.
	FDCAN_FDCAN_NDAT2_ND55_Pos = 0x17       // Position of ND55 field.
	FDCAN_FDCAN_NDAT2_ND55_Msk = 0x800000   // Bit mask of ND55 field.
	FDCAN_FDCAN_NDAT2_ND55     = 0x800000   // Bit ND55.
	FDCAN_FDCAN_NDAT2_ND56_Pos = 0x18       // Position of ND56 field.
	FDCAN_FDCAN_NDAT2_ND56_Msk = 0x1000000  // Bit mask of ND56 field.
	FDCAN_FDCAN_NDAT2_ND56     = 0x1000000  // Bit ND56.
	FDCAN_FDCAN_NDAT2_ND57_Pos = 0x19       // Position of ND57 field.
	FDCAN_FDCAN_NDAT2_ND57_Msk = 0x2000000  // Bit mask of ND57 field.
	FDCAN_FDCAN_NDAT2_ND57     = 0x2000000  // Bit ND57.
	FDCAN_FDCAN_NDAT2_ND58_Pos = 0x1a       // Position of ND58 field.
	FDCAN_FDCAN_NDAT2_ND58_Msk = 0x4000000  // Bit mask of ND58 field.
	FDCAN_FDCAN_NDAT2_ND58     = 0x4000000  // Bit ND58.
	FDCAN_FDCAN_NDAT2_ND59_Pos = 0x1b       // Position of ND59 field.
	FDCAN_FDCAN_NDAT2_ND59_Msk = 0x8000000  // Bit mask of ND59 field.
	FDCAN_FDCAN_NDAT2_ND59     = 0x8000000  // Bit ND59.
	FDCAN_FDCAN_NDAT2_ND60_Pos = 0x1c       // Position of ND60 field.
	FDCAN_FDCAN_NDAT2_ND60_Msk = 0x10000000 // Bit mask of ND60 field.
	FDCAN_FDCAN_NDAT2_ND60     = 0x10000000 // Bit ND60.
	FDCAN_FDCAN_NDAT2_ND61_Pos = 0x1d       // Position of ND61 field.
	FDCAN_FDCAN_NDAT2_ND61_Msk = 0x20000000 // Bit mask of ND61 field.
	FDCAN_FDCAN_NDAT2_ND61     = 0x20000000 // Bit ND61.
	FDCAN_FDCAN_NDAT2_ND62_Pos = 0x1e       // Position of ND62 field.
	FDCAN_FDCAN_NDAT2_ND62_Msk = 0x40000000 // Bit mask of ND62 field.
	FDCAN_FDCAN_NDAT2_ND62     = 0x40000000 // Bit ND62.
	FDCAN_FDCAN_NDAT2_ND63_Pos = 0x1f       // Position of ND63 field.
	FDCAN_FDCAN_NDAT2_ND63_Msk = 0x80000000 // Bit mask of ND63 field.
	FDCAN_FDCAN_NDAT2_ND63     = 0x80000000 // Bit ND63.

	// FDCAN_RXF0C: FDCAN Rx FIFO 0 Configuration           Register
	FDCAN_FDCAN_RXF0C_F0SA_Pos = 0x2        // Position of F0SA field.
	FDCAN_FDCAN_RXF0C_F0SA_Msk = 0xfffc     // Bit mask of F0SA field.
	FDCAN_FDCAN_RXF0C_F0S_Pos  = 0x10       // Position of F0S field.
	FDCAN_FDCAN_RXF0C_F0S_Msk  = 0xff0000   // Bit mask of F0S field.
	FDCAN_FDCAN_RXF0C_F0WM_Pos = 0x18       // Position of F0WM field.
	FDCAN_FDCAN_RXF0C_F0WM_Msk = 0xff000000 // Bit mask of F0WM field.

	// FDCAN_RXF0S: FDCAN Rx FIFO 0 Status           Register
	FDCAN_FDCAN_RXF0S_F0FL_Pos = 0x0       // Position of F0FL field.
	FDCAN_FDCAN_RXF0S_F0FL_Msk = 0x7f      // Bit mask of F0FL field.
	FDCAN_FDCAN_RXF0S_F0G_Pos  = 0x8       // Position of F0G field.
	FDCAN_FDCAN_RXF0S_F0G_Msk  = 0x3f00    // Bit mask of F0G field.
	FDCAN_FDCAN_RXF0S_F0P_Pos  = 0x10      // Position of F0P field.
	FDCAN_FDCAN_RXF0S_F0P_Msk  = 0x3f0000  // Bit mask of F0P field.
	FDCAN_FDCAN_RXF0S_F0F_Pos  = 0x18      // Position of F0F field.
	FDCAN_FDCAN_RXF0S_F0F_Msk  = 0x1000000 // Bit mask of F0F field.
	FDCAN_FDCAN_RXF0S_F0F      = 0x1000000 // Bit F0F.
	FDCAN_FDCAN_RXF0S_RF0L_Pos = 0x19      // Position of RF0L field.
	FDCAN_FDCAN_RXF0S_RF0L_Msk = 0x2000000 // Bit mask of RF0L field.
	FDCAN_FDCAN_RXF0S_RF0L     = 0x2000000 // Bit RF0L.

	// FDCAN_RXF0A: CAN Rx FIFO 0 Acknowledge           Register
	FDCAN_FDCAN_RXF0A_FA01_Pos = 0x0  // Position of FA01 field.
	FDCAN_FDCAN_RXF0A_FA01_Msk = 0x3f // Bit mask of FA01 field.

	// FDCAN_RXBC: FDCAN Rx Buffer Configuration           Register
	FDCAN_FDCAN_RXBC_RBSA_Pos = 0x2    // Position of RBSA field.
	FDCAN_FDCAN_RXBC_RBSA_Msk = 0xfffc // Bit mask of RBSA field.

	// FDCAN_RXF1C: FDCAN Rx FIFO 1 Configuration           Register
	FDCAN_FDCAN_RXF1C_F1SA_Pos = 0x2        // Position of F1SA field.
	FDCAN_FDCAN_RXF1C_F1SA_Msk = 0xfffc     // Bit mask of F1SA field.
	FDCAN_FDCAN_RXF1C_F1S_Pos  = 0x10       // Position of F1S field.
	FDCAN_FDCAN_RXF1C_F1S_Msk  = 0x7f0000   // Bit mask of F1S field.
	FDCAN_FDCAN_RXF1C_F1WM_Pos = 0x18       // Position of F1WM field.
	FDCAN_FDCAN_RXF1C_F1WM_Msk = 0x7f000000 // Bit mask of F1WM field.

	// FDCAN_RXF1S: FDCAN Rx FIFO 1 Status           Register
	FDCAN_FDCAN_RXF1S_F1FL_Pos = 0x0        // Position of F1FL field.
	FDCAN_FDCAN_RXF1S_F1FL_Msk = 0x7f       // Bit mask of F1FL field.
	FDCAN_FDCAN_RXF1S_F1GI_Pos = 0x8        // Position of F1GI field.
	FDCAN_FDCAN_RXF1S_F1GI_Msk = 0x7f00     // Bit mask of F1GI field.
	FDCAN_FDCAN_RXF1S_F1PI_Pos = 0x10       // Position of F1PI field.
	FDCAN_FDCAN_RXF1S_F1PI_Msk = 0x7f0000   // Bit mask of F1PI field.
	FDCAN_FDCAN_RXF1S_F1F_Pos  = 0x18       // Position of F1F field.
	FDCAN_FDCAN_RXF1S_F1F_Msk  = 0x1000000  // Bit mask of F1F field.
	FDCAN_FDCAN_RXF1S_F1F      = 0x1000000  // Bit F1F.
	FDCAN_FDCAN_RXF1S_RF1L_Pos = 0x19       // Position of RF1L field.
	FDCAN_FDCAN_RXF1S_RF1L_Msk = 0x2000000  // Bit mask of RF1L field.
	FDCAN_FDCAN_RXF1S_RF1L     = 0x2000000  // Bit RF1L.
	FDCAN_FDCAN_RXF1S_DMS_Pos  = 0x1e       // Position of DMS field.
	FDCAN_FDCAN_RXF1S_DMS_Msk  = 0xc0000000 // Bit mask of DMS field.

	// FDCAN_RXF1A: FDCAN Rx FIFO 1 Acknowledge           Register
	FDCAN_FDCAN_RXF1A_F1AI_Pos = 0x0  // Position of F1AI field.
	FDCAN_FDCAN_RXF1A_F1AI_Msk = 0x3f // Bit mask of F1AI field.

	// FDCAN_RXESC: FDCAN Rx Buffer Element Size Configuration           Register
	FDCAN_FDCAN_RXESC_F0DS_Pos = 0x0   // Position of F0DS field.
	FDCAN_FDCAN_RXESC_F0DS_Msk = 0x7   // Bit mask of F0DS field.
	FDCAN_FDCAN_RXESC_F1DS_Pos = 0x4   // Position of F1DS field.
	FDCAN_FDCAN_RXESC_F1DS_Msk = 0x70  // Bit mask of F1DS field.
	FDCAN_FDCAN_RXESC_RBDS_Pos = 0x8   // Position of RBDS field.
	FDCAN_FDCAN_RXESC_RBDS_Msk = 0x700 // Bit mask of RBDS field.

	// FDCAN_TXBC: FDCAN Tx Buffer Configuration           Register
	FDCAN_FDCAN_TXBC_TBSA_Pos = 0x2        // Position of TBSA field.
	FDCAN_FDCAN_TXBC_TBSA_Msk = 0xfffc     // Bit mask of TBSA field.
	FDCAN_FDCAN_TXBC_NDTB_Pos = 0x10       // Position of NDTB field.
	FDCAN_FDCAN_TXBC_NDTB_Msk = 0x3f0000   // Bit mask of NDTB field.
	FDCAN_FDCAN_TXBC_TFQS_Pos = 0x18       // Position of TFQS field.
	FDCAN_FDCAN_TXBC_TFQS_Msk = 0x3f000000 // Bit mask of TFQS field.
	FDCAN_FDCAN_TXBC_TFQM_Pos = 0x1e       // Position of TFQM field.
	FDCAN_FDCAN_TXBC_TFQM_Msk = 0x40000000 // Bit mask of TFQM field.
	FDCAN_FDCAN_TXBC_TFQM     = 0x40000000 // Bit TFQM.

	// FDCAN_TXFQS: FDCAN Tx FIFO/Queue Status           Register
	FDCAN_FDCAN_TXFQS_TFFL_Pos  = 0x0      // Position of TFFL field.
	FDCAN_FDCAN_TXFQS_TFFL_Msk  = 0x3f     // Bit mask of TFFL field.
	FDCAN_FDCAN_TXFQS_TFGI_Pos  = 0x8      // Position of TFGI field.
	FDCAN_FDCAN_TXFQS_TFGI_Msk  = 0x1f00   // Bit mask of TFGI field.
	FDCAN_FDCAN_TXFQS_TFQPI_Pos = 0x10     // Position of TFQPI field.
	FDCAN_FDCAN_TXFQS_TFQPI_Msk = 0x1f0000 // Bit mask of TFQPI field.
	FDCAN_FDCAN_TXFQS_TFQF_Pos  = 0x15     // Position of TFQF field.
	FDCAN_FDCAN_TXFQS_TFQF_Msk  = 0x200000 // Bit mask of TFQF field.
	FDCAN_FDCAN_TXFQS_TFQF      = 0x200000 // Bit TFQF.

	// FDCAN_TXESC: FDCAN Tx Buffer Element Size Configuration           Register
	FDCAN_FDCAN_TXESC_TBDS_Pos = 0x0 // Position of TBDS field.
	FDCAN_FDCAN_TXESC_TBDS_Msk = 0x7 // Bit mask of TBDS field.

	// FDCAN_TXBRP: FDCAN Tx Buffer Request Pending           Register
	FDCAN_FDCAN_TXBRP_TRP_Pos = 0x0        // Position of TRP field.
	FDCAN_FDCAN_TXBRP_TRP_Msk = 0xffffffff // Bit mask of TRP field.

	// FDCAN_TXBAR: FDCAN Tx Buffer Add Request           Register
	FDCAN_FDCAN_TXBAR_AR_Pos = 0x0        // Position of AR field.
	FDCAN_FDCAN_TXBAR_AR_Msk = 0xffffffff // Bit mask of AR field.

	// FDCAN_TXBCR: FDCAN Tx Buffer Cancellation Request           Register
	FDCAN_FDCAN_TXBCR_CR_Pos = 0x0        // Position of CR field.
	FDCAN_FDCAN_TXBCR_CR_Msk = 0xffffffff // Bit mask of CR field.

	// FDCAN_TXBTO: FDCAN Tx Buffer Transmission Occurred           Register
	FDCAN_FDCAN_TXBTO_TO_Pos = 0x0        // Position of TO field.
	FDCAN_FDCAN_TXBTO_TO_Msk = 0xffffffff // Bit mask of TO field.

	// FDCAN_TXBCF: FDCAN Tx Buffer Cancellation Finished           Register
	FDCAN_FDCAN_TXBCF_CF_Pos = 0x0        // Position of CF field.
	FDCAN_FDCAN_TXBCF_CF_Msk = 0xffffffff // Bit mask of CF field.

	// FDCAN_TXBTIE: FDCAN Tx Buffer Transmission Interrupt           Enable Register
	FDCAN_FDCAN_TXBTIE_TIE_Pos = 0x0        // Position of TIE field.
	FDCAN_FDCAN_TXBTIE_TIE_Msk = 0xffffffff // Bit mask of TIE field.

	// FDCAN_TXBCIE: FDCAN Tx Buffer Cancellation Finished           Interrupt Enable Register
	FDCAN_FDCAN_TXBCIE_CF_Pos = 0x0        // Position of CF field.
	FDCAN_FDCAN_TXBCIE_CF_Msk = 0xffffffff // Bit mask of CF field.

	// FDCAN_TXEFC: FDCAN Tx Event FIFO Configuration           Register
	FDCAN_FDCAN_TXEFC_EFSA_Pos = 0x2        // Position of EFSA field.
	FDCAN_FDCAN_TXEFC_EFSA_Msk = 0xfffc     // Bit mask of EFSA field.
	FDCAN_FDCAN_TXEFC_EFS_Pos  = 0x10       // Position of EFS field.
	FDCAN_FDCAN_TXEFC_EFS_Msk  = 0x3f0000   // Bit mask of EFS field.
	FDCAN_FDCAN_TXEFC_EFWM_Pos = 0x18       // Position of EFWM field.
	FDCAN_FDCAN_TXEFC_EFWM_Msk = 0x3f000000 // Bit mask of EFWM field.

	// FDCAN_TXEFS: FDCAN Tx Event FIFO Status           Register
	FDCAN_FDCAN_TXEFS_EFFL_Pos = 0x0       // Position of EFFL field.
	FDCAN_FDCAN_TXEFS_EFFL_Msk = 0x3f      // Bit mask of EFFL field.
	FDCAN_FDCAN_TXEFS_EFGI_Pos = 0x8       // Position of EFGI field.
	FDCAN_FDCAN_TXEFS_EFGI_Msk = 0x1f00    // Bit mask of EFGI field.
	FDCAN_FDCAN_TXEFS_EFF_Pos  = 0x18      // Position of EFF field.
	FDCAN_FDCAN_TXEFS_EFF_Msk  = 0x1000000 // Bit mask of EFF field.
	FDCAN_FDCAN_TXEFS_EFF      = 0x1000000 // Bit EFF.
	FDCAN_FDCAN_TXEFS_TEFL_Pos = 0x19      // Position of TEFL field.
	FDCAN_FDCAN_TXEFS_TEFL_Msk = 0x2000000 // Bit mask of TEFL field.
	FDCAN_FDCAN_TXEFS_TEFL     = 0x2000000 // Bit TEFL.

	// FDCAN_TXEFA: FDCAN Tx Event FIFO Acknowledge           Register
	FDCAN_FDCAN_TXEFA_EFAI_Pos = 0x0  // Position of EFAI field.
	FDCAN_FDCAN_TXEFA_EFAI_Msk = 0x1f // Bit mask of EFAI field.

	// FDCAN_TTTMC: FDCAN TT Trigger Memory Configuration           Register
	FDCAN_FDCAN_TTTMC_TMSA_Pos = 0x2      // Position of TMSA field.
	FDCAN_FDCAN_TTTMC_TMSA_Msk = 0xfffc   // Bit mask of TMSA field.
	FDCAN_FDCAN_TTTMC_TME_Pos  = 0x10     // Position of TME field.
	FDCAN_FDCAN_TTTMC_TME_Msk  = 0x7f0000 // Bit mask of TME field.

	// FDCAN_TTRMC: FDCAN TT Reference Message Configuration           Register
	FDCAN_FDCAN_TTRMC_RID_Pos  = 0x0        // Position of RID field.
	FDCAN_FDCAN_TTRMC_RID_Msk  = 0x1fffffff // Bit mask of RID field.
	FDCAN_FDCAN_TTRMC_XTD_Pos  = 0x1e       // Position of XTD field.
	FDCAN_FDCAN_TTRMC_XTD_Msk  = 0x40000000 // Bit mask of XTD field.
	FDCAN_FDCAN_TTRMC_XTD      = 0x40000000 // Bit XTD.
	FDCAN_FDCAN_TTRMC_RMPS_Pos = 0x1f       // Position of RMPS field.
	FDCAN_FDCAN_TTRMC_RMPS_Msk = 0x80000000 // Bit mask of RMPS field.
	FDCAN_FDCAN_TTRMC_RMPS     = 0x80000000 // Bit RMPS.

	// FDCAN_TTOCF: FDCAN TT Operation Configuration           Register
	FDCAN_FDCAN_TTOCF_OM_Pos    = 0x0       // Position of OM field.
	FDCAN_FDCAN_TTOCF_OM_Msk    = 0x3       // Bit mask of OM field.
	FDCAN_FDCAN_TTOCF_GEN_Pos   = 0x3       // Position of GEN field.
	FDCAN_FDCAN_TTOCF_GEN_Msk   = 0x8       // Bit mask of GEN field.
	FDCAN_FDCAN_TTOCF_GEN       = 0x8       // Bit GEN.
	FDCAN_FDCAN_TTOCF_TM_Pos    = 0x4       // Position of TM field.
	FDCAN_FDCAN_TTOCF_TM_Msk    = 0x10      // Bit mask of TM field.
	FDCAN_FDCAN_TTOCF_TM        = 0x10      // Bit TM.
	FDCAN_FDCAN_TTOCF_LDSDL_Pos = 0x5       // Position of LDSDL field.
	FDCAN_FDCAN_TTOCF_LDSDL_Msk = 0xe0      // Bit mask of LDSDL field.
	FDCAN_FDCAN_TTOCF_IRTO_Pos  = 0x8       // Position of IRTO field.
	FDCAN_FDCAN_TTOCF_IRTO_Msk  = 0x7f00    // Bit mask of IRTO field.
	FDCAN_FDCAN_TTOCF_EECS_Pos  = 0xf       // Position of EECS field.
	FDCAN_FDCAN_TTOCF_EECS_Msk  = 0x8000    // Bit mask of EECS field.
	FDCAN_FDCAN_TTOCF_EECS      = 0x8000    // Bit EECS.
	FDCAN_FDCAN_TTOCF_AWL_Pos   = 0x10      // Position of AWL field.
	FDCAN_FDCAN_TTOCF_AWL_Msk   = 0xff0000  // Bit mask of AWL field.
	FDCAN_FDCAN_TTOCF_EGTF_Pos  = 0x18      // Position of EGTF field.
	FDCAN_FDCAN_TTOCF_EGTF_Msk  = 0x1000000 // Bit mask of EGTF field.
	FDCAN_FDCAN_TTOCF_EGTF      = 0x1000000 // Bit EGTF.
	FDCAN_FDCAN_TTOCF_ECC_Pos   = 0x19      // Position of ECC field.
	FDCAN_FDCAN_TTOCF_ECC_Msk   = 0x2000000 // Bit mask of ECC field.
	FDCAN_FDCAN_TTOCF_ECC       = 0x2000000 // Bit ECC.
	FDCAN_FDCAN_TTOCF_EVTP_Pos  = 0x1a      // Position of EVTP field.
	FDCAN_FDCAN_TTOCF_EVTP_Msk  = 0x4000000 // Bit mask of EVTP field.
	FDCAN_FDCAN_TTOCF_EVTP      = 0x4000000 // Bit EVTP.

	// FDCAN_TTMLM: FDCAN TT Matrix Limits           Register
	FDCAN_FDCAN_TTMLM_CCM_Pos  = 0x0       // Position of CCM field.
	FDCAN_FDCAN_TTMLM_CCM_Msk  = 0x3f      // Bit mask of CCM field.
	FDCAN_FDCAN_TTMLM_CSS_Pos  = 0x6       // Position of CSS field.
	FDCAN_FDCAN_TTMLM_CSS_Msk  = 0xc0      // Bit mask of CSS field.
	FDCAN_FDCAN_TTMLM_TXEW_Pos = 0x8       // Position of TXEW field.
	FDCAN_FDCAN_TTMLM_TXEW_Msk = 0xf00     // Bit mask of TXEW field.
	FDCAN_FDCAN_TTMLM_ENTT_Pos = 0x10      // Position of ENTT field.
	FDCAN_FDCAN_TTMLM_ENTT_Msk = 0xfff0000 // Bit mask of ENTT field.

	// FDCAN_TURCF: FDCAN TUR Configuration           Register
	FDCAN_FDCAN_TURCF_NCL_Pos = 0x0        // Position of NCL field.
	FDCAN_FDCAN_TURCF_NCL_Msk = 0xffff     // Bit mask of NCL field.
	FDCAN_FDCAN_TURCF_DC_Pos  = 0x10       // Position of DC field.
	FDCAN_FDCAN_TURCF_DC_Msk  = 0x3fff0000 // Bit mask of DC field.
	FDCAN_FDCAN_TURCF_ELT_Pos = 0x1f       // Position of ELT field.
	FDCAN_FDCAN_TURCF_ELT_Msk = 0x80000000 // Bit mask of ELT field.
	FDCAN_FDCAN_TURCF_ELT     = 0x80000000 // Bit ELT.

	// FDCAN_TTOCN: FDCAN TT Operation Control           Register
	FDCAN_FDCAN_TTOCN_SGT_Pos  = 0x0    // Position of SGT field.
	FDCAN_FDCAN_TTOCN_SGT_Msk  = 0x1    // Bit mask of SGT field.
	FDCAN_FDCAN_TTOCN_SGT      = 0x1    // Bit SGT.
	FDCAN_FDCAN_TTOCN_ECS_Pos  = 0x1    // Position of ECS field.
	FDCAN_FDCAN_TTOCN_ECS_Msk  = 0x2    // Bit mask of ECS field.
	FDCAN_FDCAN_TTOCN_ECS      = 0x2    // Bit ECS.
	FDCAN_FDCAN_TTOCN_SWP_Pos  = 0x2    // Position of SWP field.
	FDCAN_FDCAN_TTOCN_SWP_Msk  = 0x4    // Bit mask of SWP field.
	FDCAN_FDCAN_TTOCN_SWP      = 0x4    // Bit SWP.
	FDCAN_FDCAN_TTOCN_SWS_Pos  = 0x3    // Position of SWS field.
	FDCAN_FDCAN_TTOCN_SWS_Msk  = 0x18   // Bit mask of SWS field.
	FDCAN_FDCAN_TTOCN_RTIE_Pos = 0x5    // Position of RTIE field.
	FDCAN_FDCAN_TTOCN_RTIE_Msk = 0x20   // Bit mask of RTIE field.
	FDCAN_FDCAN_TTOCN_RTIE     = 0x20   // Bit RTIE.
	FDCAN_FDCAN_TTOCN_TMC_Pos  = 0x6    // Position of TMC field.
	FDCAN_FDCAN_TTOCN_TMC_Msk  = 0xc0   // Bit mask of TMC field.
	FDCAN_FDCAN_TTOCN_TTIE_Pos = 0x8    // Position of TTIE field.
	FDCAN_FDCAN_TTOCN_TTIE_Msk = 0x100  // Bit mask of TTIE field.
	FDCAN_FDCAN_TTOCN_TTIE     = 0x100  // Bit TTIE.
	FDCAN_FDCAN_TTOCN_GCS_Pos  = 0x9    // Position of GCS field.
	FDCAN_FDCAN_TTOCN_GCS_Msk  = 0x200  // Bit mask of GCS field.
	FDCAN_FDCAN_TTOCN_GCS      = 0x200  // Bit GCS.
	FDCAN_FDCAN_TTOCN_FGP_Pos  = 0xa    // Position of FGP field.
	FDCAN_FDCAN_TTOCN_FGP_Msk  = 0x400  // Bit mask of FGP field.
	FDCAN_FDCAN_TTOCN_FGP      = 0x400  // Bit FGP.
	FDCAN_FDCAN_TTOCN_TMG_Pos  = 0xb    // Position of TMG field.
	FDCAN_FDCAN_TTOCN_TMG_Msk  = 0x800  // Bit mask of TMG field.
	FDCAN_FDCAN_TTOCN_TMG      = 0x800  // Bit TMG.
	FDCAN_FDCAN_TTOCN_NIG_Pos  = 0xc    // Position of NIG field.
	FDCAN_FDCAN_TTOCN_NIG_Msk  = 0x1000 // Bit mask of NIG field.
	FDCAN_FDCAN_TTOCN_NIG      = 0x1000 // Bit NIG.
	FDCAN_FDCAN_TTOCN_ESCN_Pos = 0xd    // Position of ESCN field.
	FDCAN_FDCAN_TTOCN_ESCN_Msk = 0x2000 // Bit mask of ESCN field.
	FDCAN_FDCAN_TTOCN_ESCN     = 0x2000 // Bit ESCN.
	FDCAN_FDCAN_TTOCN_LCKC_Pos = 0xf    // Position of LCKC field.
	FDCAN_FDCAN_TTOCN_LCKC_Msk = 0x8000 // Bit mask of LCKC field.
	FDCAN_FDCAN_TTOCN_LCKC     = 0x8000 // Bit LCKC.

	// CAN_TTGTP: FDCAN TT Global Time Preset           Register
	FDCAN_CAN_TTGTP_NCL_Pos = 0x0        // Position of NCL field.
	FDCAN_CAN_TTGTP_NCL_Msk = 0xffff     // Bit mask of NCL field.
	FDCAN_CAN_TTGTP_CTP_Pos = 0x10       // Position of CTP field.
	FDCAN_CAN_TTGTP_CTP_Msk = 0xffff0000 // Bit mask of CTP field.

	// FDCAN_TTTMK: FDCAN TT Time Mark Register
	FDCAN_FDCAN_TTTMK_TM_Pos   = 0x0        // Position of TM field.
	FDCAN_FDCAN_TTTMK_TM_Msk   = 0xffff     // Bit mask of TM field.
	FDCAN_FDCAN_TTTMK_TICC_Pos = 0x10       // Position of TICC field.
	FDCAN_FDCAN_TTTMK_TICC_Msk = 0x7f0000   // Bit mask of TICC field.
	FDCAN_FDCAN_TTTMK_LCKM_Pos = 0x1f       // Position of LCKM field.
	FDCAN_FDCAN_TTTMK_LCKM_Msk = 0x80000000 // Bit mask of LCKM field.
	FDCAN_FDCAN_TTTMK_LCKM     = 0x80000000 // Bit LCKM.

	// FDCAN_TTIR: FDCAN TT Interrupt Register
	FDCAN_FDCAN_TTIR_SBC_Pos  = 0x0     // Position of SBC field.
	FDCAN_FDCAN_TTIR_SBC_Msk  = 0x1     // Bit mask of SBC field.
	FDCAN_FDCAN_TTIR_SBC      = 0x1     // Bit SBC.
	FDCAN_FDCAN_TTIR_SMC_Pos  = 0x1     // Position of SMC field.
	FDCAN_FDCAN_TTIR_SMC_Msk  = 0x2     // Bit mask of SMC field.
	FDCAN_FDCAN_TTIR_SMC      = 0x2     // Bit SMC.
	FDCAN_FDCAN_TTIR_CSM_Pos  = 0x2     // Position of CSM field.
	FDCAN_FDCAN_TTIR_CSM_Msk  = 0x4     // Bit mask of CSM field.
	FDCAN_FDCAN_TTIR_CSM      = 0x4     // Bit CSM.
	FDCAN_FDCAN_TTIR_SOG_Pos  = 0x3     // Position of SOG field.
	FDCAN_FDCAN_TTIR_SOG_Msk  = 0x8     // Bit mask of SOG field.
	FDCAN_FDCAN_TTIR_SOG      = 0x8     // Bit SOG.
	FDCAN_FDCAN_TTIR_RTMI_Pos = 0x4     // Position of RTMI field.
	FDCAN_FDCAN_TTIR_RTMI_Msk = 0x10    // Bit mask of RTMI field.
	FDCAN_FDCAN_TTIR_RTMI     = 0x10    // Bit RTMI.
	FDCAN_FDCAN_TTIR_TTMI_Pos = 0x5     // Position of TTMI field.
	FDCAN_FDCAN_TTIR_TTMI_Msk = 0x20    // Bit mask of TTMI field.
	FDCAN_FDCAN_TTIR_TTMI     = 0x20    // Bit TTMI.
	FDCAN_FDCAN_TTIR_SWE_Pos  = 0x6     // Position of SWE field.
	FDCAN_FDCAN_TTIR_SWE_Msk  = 0x40    // Bit mask of SWE field.
	FDCAN_FDCAN_TTIR_SWE      = 0x40    // Bit SWE.
	FDCAN_FDCAN_TTIR_GTW_Pos  = 0x7     // Position of GTW field.
	FDCAN_FDCAN_TTIR_GTW_Msk  = 0x80    // Bit mask of GTW field.
	FDCAN_FDCAN_TTIR_GTW      = 0x80    // Bit GTW.
	FDCAN_FDCAN_TTIR_GTD_Pos  = 0x8     // Position of GTD field.
	FDCAN_FDCAN_TTIR_GTD_Msk  = 0x100   // Bit mask of GTD field.
	FDCAN_FDCAN_TTIR_GTD      = 0x100   // Bit GTD.
	FDCAN_FDCAN_TTIR_GTE_Pos  = 0x9     // Position of GTE field.
	FDCAN_FDCAN_TTIR_GTE_Msk  = 0x200   // Bit mask of GTE field.
	FDCAN_FDCAN_TTIR_GTE      = 0x200   // Bit GTE.
	FDCAN_FDCAN_TTIR_TXU_Pos  = 0xa     // Position of TXU field.
	FDCAN_FDCAN_TTIR_TXU_Msk  = 0x400   // Bit mask of TXU field.
	FDCAN_FDCAN_TTIR_TXU      = 0x400   // Bit TXU.
	FDCAN_FDCAN_TTIR_TXO_Pos  = 0xb     // Position of TXO field.
	FDCAN_FDCAN_TTIR_TXO_Msk  = 0x800   // Bit mask of TXO field.
	FDCAN_FDCAN_TTIR_TXO      = 0x800   // Bit TXO.
	FDCAN_FDCAN_TTIR_SE1_Pos  = 0xc     // Position of SE1 field.
	FDCAN_FDCAN_TTIR_SE1_Msk  = 0x1000  // Bit mask of SE1 field.
	FDCAN_FDCAN_TTIR_SE1      = 0x1000  // Bit SE1.
	FDCAN_FDCAN_TTIR_SE2_Pos  = 0xd     // Position of SE2 field.
	FDCAN_FDCAN_TTIR_SE2_Msk  = 0x2000  // Bit mask of SE2 field.
	FDCAN_FDCAN_TTIR_SE2      = 0x2000  // Bit SE2.
	FDCAN_FDCAN_TTIR_ELC_Pos  = 0xe     // Position of ELC field.
	FDCAN_FDCAN_TTIR_ELC_Msk  = 0x4000  // Bit mask of ELC field.
	FDCAN_FDCAN_TTIR_ELC      = 0x4000  // Bit ELC.
	FDCAN_FDCAN_TTIR_IWTG_Pos = 0xf     // Position of IWTG field.
	FDCAN_FDCAN_TTIR_IWTG_Msk = 0x8000  // Bit mask of IWTG field.
	FDCAN_FDCAN_TTIR_IWTG     = 0x8000  // Bit IWTG.
	FDCAN_FDCAN_TTIR_WT_Pos   = 0x10    // Position of WT field.
	FDCAN_FDCAN_TTIR_WT_Msk   = 0x10000 // Bit mask of WT field.
	FDCAN_FDCAN_TTIR_WT       = 0x10000 // Bit WT.
	FDCAN_FDCAN_TTIR_AW_Pos   = 0x11    // Position of AW field.
	FDCAN_FDCAN_TTIR_AW_Msk   = 0x20000 // Bit mask of AW field.
	FDCAN_FDCAN_TTIR_AW       = 0x20000 // Bit AW.
	FDCAN_FDCAN_TTIR_CER_Pos  = 0x12    // Position of CER field.
	FDCAN_FDCAN_TTIR_CER_Msk  = 0x40000 // Bit mask of CER field.
	FDCAN_FDCAN_TTIR_CER      = 0x40000 // Bit CER.

	// FDCAN_TTIE: FDCAN TT Interrupt Enable           Register
	FDCAN_FDCAN_TTIE_SBCE_Pos  = 0x0     // Position of SBCE field.
	FDCAN_FDCAN_TTIE_SBCE_Msk  = 0x1     // Bit mask of SBCE field.
	FDCAN_FDCAN_TTIE_SBCE      = 0x1     // Bit SBCE.
	FDCAN_FDCAN_TTIE_SMCE_Pos  = 0x1     // Position of SMCE field.
	FDCAN_FDCAN_TTIE_SMCE_Msk  = 0x2     // Bit mask of SMCE field.
	FDCAN_FDCAN_TTIE_SMCE      = 0x2     // Bit SMCE.
	FDCAN_FDCAN_TTIE_CSME_Pos  = 0x2     // Position of CSME field.
	FDCAN_FDCAN_TTIE_CSME_Msk  = 0x4     // Bit mask of CSME field.
	FDCAN_FDCAN_TTIE_CSME      = 0x4     // Bit CSME.
	FDCAN_FDCAN_TTIE_SOGE_Pos  = 0x3     // Position of SOGE field.
	FDCAN_FDCAN_TTIE_SOGE_Msk  = 0x8     // Bit mask of SOGE field.
	FDCAN_FDCAN_TTIE_SOGE      = 0x8     // Bit SOGE.
	FDCAN_FDCAN_TTIE_RTMIE_Pos = 0x4     // Position of RTMIE field.
	FDCAN_FDCAN_TTIE_RTMIE_Msk = 0x10    // Bit mask of RTMIE field.
	FDCAN_FDCAN_TTIE_RTMIE     = 0x10    // Bit RTMIE.
	FDCAN_FDCAN_TTIE_TTMIE_Pos = 0x5     // Position of TTMIE field.
	FDCAN_FDCAN_TTIE_TTMIE_Msk = 0x20    // Bit mask of TTMIE field.
	FDCAN_FDCAN_TTIE_TTMIE     = 0x20    // Bit TTMIE.
	FDCAN_FDCAN_TTIE_SWEE_Pos  = 0x6     // Position of SWEE field.
	FDCAN_FDCAN_TTIE_SWEE_Msk  = 0x40    // Bit mask of SWEE field.
	FDCAN_FDCAN_TTIE_SWEE      = 0x40    // Bit SWEE.
	FDCAN_FDCAN_TTIE_GTWE_Pos  = 0x7     // Position of GTWE field.
	FDCAN_FDCAN_TTIE_GTWE_Msk  = 0x80    // Bit mask of GTWE field.
	FDCAN_FDCAN_TTIE_GTWE      = 0x80    // Bit GTWE.
	FDCAN_FDCAN_TTIE_GTDE_Pos  = 0x8     // Position of GTDE field.
	FDCAN_FDCAN_TTIE_GTDE_Msk  = 0x100   // Bit mask of GTDE field.
	FDCAN_FDCAN_TTIE_GTDE      = 0x100   // Bit GTDE.
	FDCAN_FDCAN_TTIE_GTEE_Pos  = 0x9     // Position of GTEE field.
	FDCAN_FDCAN_TTIE_GTEE_Msk  = 0x200   // Bit mask of GTEE field.
	FDCAN_FDCAN_TTIE_GTEE      = 0x200   // Bit GTEE.
	FDCAN_FDCAN_TTIE_TXUE_Pos  = 0xa     // Position of TXUE field.
	FDCAN_FDCAN_TTIE_TXUE_Msk  = 0x400   // Bit mask of TXUE field.
	FDCAN_FDCAN_TTIE_TXUE      = 0x400   // Bit TXUE.
	FDCAN_FDCAN_TTIE_TXOE_Pos  = 0xb     // Position of TXOE field.
	FDCAN_FDCAN_TTIE_TXOE_Msk  = 0x800   // Bit mask of TXOE field.
	FDCAN_FDCAN_TTIE_TXOE      = 0x800   // Bit TXOE.
	FDCAN_FDCAN_TTIE_SE1E_Pos  = 0xc     // Position of SE1E field.
	FDCAN_FDCAN_TTIE_SE1E_Msk  = 0x1000  // Bit mask of SE1E field.
	FDCAN_FDCAN_TTIE_SE1E      = 0x1000  // Bit SE1E.
	FDCAN_FDCAN_TTIE_SE2E_Pos  = 0xd     // Position of SE2E field.
	FDCAN_FDCAN_TTIE_SE2E_Msk  = 0x2000  // Bit mask of SE2E field.
	FDCAN_FDCAN_TTIE_SE2E      = 0x2000  // Bit SE2E.
	FDCAN_FDCAN_TTIE_ELCE_Pos  = 0xe     // Position of ELCE field.
	FDCAN_FDCAN_TTIE_ELCE_Msk  = 0x4000  // Bit mask of ELCE field.
	FDCAN_FDCAN_TTIE_ELCE      = 0x4000  // Bit ELCE.
	FDCAN_FDCAN_TTIE_IWTGE_Pos = 0xf     // Position of IWTGE field.
	FDCAN_FDCAN_TTIE_IWTGE_Msk = 0x8000  // Bit mask of IWTGE field.
	FDCAN_FDCAN_TTIE_IWTGE     = 0x8000  // Bit IWTGE.
	FDCAN_FDCAN_TTIE_WTE_Pos   = 0x10    // Position of WTE field.
	FDCAN_FDCAN_TTIE_WTE_Msk   = 0x10000 // Bit mask of WTE field.
	FDCAN_FDCAN_TTIE_WTE       = 0x10000 // Bit WTE.
	FDCAN_FDCAN_TTIE_AWE_Pos   = 0x11    // Position of AWE field.
	FDCAN_FDCAN_TTIE_AWE_Msk   = 0x20000 // Bit mask of AWE field.
	FDCAN_FDCAN_TTIE_AWE       = 0x20000 // Bit AWE.
	FDCAN_FDCAN_TTIE_CERE_Pos  = 0x12    // Position of CERE field.
	FDCAN_FDCAN_TTIE_CERE_Msk  = 0x40000 // Bit mask of CERE field.
	FDCAN_FDCAN_TTIE_CERE      = 0x40000 // Bit CERE.

	// FDCAN_TTILS: FDCAN TT Interrupt Line Select           Register
	FDCAN_FDCAN_TTILS_SBCL_Pos  = 0x0     // Position of SBCL field.
	FDCAN_FDCAN_TTILS_SBCL_Msk  = 0x1     // Bit mask of SBCL field.
	FDCAN_FDCAN_TTILS_SBCL      = 0x1     // Bit SBCL.
	FDCAN_FDCAN_TTILS_SMCL_Pos  = 0x1     // Position of SMCL field.
	FDCAN_FDCAN_TTILS_SMCL_Msk  = 0x2     // Bit mask of SMCL field.
	FDCAN_FDCAN_TTILS_SMCL      = 0x2     // Bit SMCL.
	FDCAN_FDCAN_TTILS_CSML_Pos  = 0x2     // Position of CSML field.
	FDCAN_FDCAN_TTILS_CSML_Msk  = 0x4     // Bit mask of CSML field.
	FDCAN_FDCAN_TTILS_CSML      = 0x4     // Bit CSML.
	FDCAN_FDCAN_TTILS_SOGL_Pos  = 0x3     // Position of SOGL field.
	FDCAN_FDCAN_TTILS_SOGL_Msk  = 0x8     // Bit mask of SOGL field.
	FDCAN_FDCAN_TTILS_SOGL      = 0x8     // Bit SOGL.
	FDCAN_FDCAN_TTILS_RTMIL_Pos = 0x4     // Position of RTMIL field.
	FDCAN_FDCAN_TTILS_RTMIL_Msk = 0x10    // Bit mask of RTMIL field.
	FDCAN_FDCAN_TTILS_RTMIL     = 0x10    // Bit RTMIL.
	FDCAN_FDCAN_TTILS_TTMIL_Pos = 0x5     // Position of TTMIL field.
	FDCAN_FDCAN_TTILS_TTMIL_Msk = 0x20    // Bit mask of TTMIL field.
	FDCAN_FDCAN_TTILS_TTMIL     = 0x20    // Bit TTMIL.
	FDCAN_FDCAN_TTILS_SWEL_Pos  = 0x6     // Position of SWEL field.
	FDCAN_FDCAN_TTILS_SWEL_Msk  = 0x40    // Bit mask of SWEL field.
	FDCAN_FDCAN_TTILS_SWEL      = 0x40    // Bit SWEL.
	FDCAN_FDCAN_TTILS_GTWL_Pos  = 0x7     // Position of GTWL field.
	FDCAN_FDCAN_TTILS_GTWL_Msk  = 0x80    // Bit mask of GTWL field.
	FDCAN_FDCAN_TTILS_GTWL      = 0x80    // Bit GTWL.
	FDCAN_FDCAN_TTILS_GTDL_Pos  = 0x8     // Position of GTDL field.
	FDCAN_FDCAN_TTILS_GTDL_Msk  = 0x100   // Bit mask of GTDL field.
	FDCAN_FDCAN_TTILS_GTDL      = 0x100   // Bit GTDL.
	FDCAN_FDCAN_TTILS_GTEL_Pos  = 0x9     // Position of GTEL field.
	FDCAN_FDCAN_TTILS_GTEL_Msk  = 0x200   // Bit mask of GTEL field.
	FDCAN_FDCAN_TTILS_GTEL      = 0x200   // Bit GTEL.
	FDCAN_FDCAN_TTILS_TXUL_Pos  = 0xa     // Position of TXUL field.
	FDCAN_FDCAN_TTILS_TXUL_Msk  = 0x400   // Bit mask of TXUL field.
	FDCAN_FDCAN_TTILS_TXUL      = 0x400   // Bit TXUL.
	FDCAN_FDCAN_TTILS_TXOL_Pos  = 0xb     // Position of TXOL field.
	FDCAN_FDCAN_TTILS_TXOL_Msk  = 0x800   // Bit mask of TXOL field.
	FDCAN_FDCAN_TTILS_TXOL      = 0x800   // Bit TXOL.
	FDCAN_FDCAN_TTILS_SE1L_Pos  = 0xc     // Position of SE1L field.
	FDCAN_FDCAN_TTILS_SE1L_Msk  = 0x1000  // Bit mask of SE1L field.
	FDCAN_FDCAN_TTILS_SE1L      = 0x1000  // Bit SE1L.
	FDCAN_FDCAN_TTILS_SE2L_Pos  = 0xd     // Position of SE2L field.
	FDCAN_FDCAN_TTILS_SE2L_Msk  = 0x2000  // Bit mask of SE2L field.
	FDCAN_FDCAN_TTILS_SE2L      = 0x2000  // Bit SE2L.
	FDCAN_FDCAN_TTILS_ELCL_Pos  = 0xe     // Position of ELCL field.
	FDCAN_FDCAN_TTILS_ELCL_Msk  = 0x4000  // Bit mask of ELCL field.
	FDCAN_FDCAN_TTILS_ELCL      = 0x4000  // Bit ELCL.
	FDCAN_FDCAN_TTILS_IWTGL_Pos = 0xf     // Position of IWTGL field.
	FDCAN_FDCAN_TTILS_IWTGL_Msk = 0x8000  // Bit mask of IWTGL field.
	FDCAN_FDCAN_TTILS_IWTGL     = 0x8000  // Bit IWTGL.
	FDCAN_FDCAN_TTILS_WTL_Pos   = 0x10    // Position of WTL field.
	FDCAN_FDCAN_TTILS_WTL_Msk   = 0x10000 // Bit mask of WTL field.
	FDCAN_FDCAN_TTILS_WTL       = 0x10000 // Bit WTL.
	FDCAN_FDCAN_TTILS_AWL_Pos   = 0x11    // Position of AWL field.
	FDCAN_FDCAN_TTILS_AWL_Msk   = 0x20000 // Bit mask of AWL field.
	FDCAN_FDCAN_TTILS_AWL       = 0x20000 // Bit AWL.
	FDCAN_FDCAN_TTILS_CERL_Pos  = 0x12    // Position of CERL field.
	FDCAN_FDCAN_TTILS_CERL_Msk  = 0x40000 // Bit mask of CERL field.
	FDCAN_FDCAN_TTILS_CERL      = 0x40000 // Bit CERL.

	// FDCAN_TTOST: FDCAN TT Operation Status           Register
	FDCAN_FDCAN_TTOST_EL_Pos   = 0x0        // Position of EL field.
	FDCAN_FDCAN_TTOST_EL_Msk   = 0x3        // Bit mask of EL field.
	FDCAN_FDCAN_TTOST_MS_Pos   = 0x2        // Position of MS field.
	FDCAN_FDCAN_TTOST_MS_Msk   = 0xc        // Bit mask of MS field.
	FDCAN_FDCAN_TTOST_SYS_Pos  = 0x4        // Position of SYS field.
	FDCAN_FDCAN_TTOST_SYS_Msk  = 0x30       // Bit mask of SYS field.
	FDCAN_FDCAN_TTOST_GTP_Pos  = 0x6        // Position of GTP field.
	FDCAN_FDCAN_TTOST_GTP_Msk  = 0x40       // Bit mask of GTP field.
	FDCAN_FDCAN_TTOST_GTP      = 0x40       // Bit GTP.
	FDCAN_FDCAN_TTOST_QCS_Pos  = 0x7        // Position of QCS field.
	FDCAN_FDCAN_TTOST_QCS_Msk  = 0x80       // Bit mask of QCS field.
	FDCAN_FDCAN_TTOST_QCS      = 0x80       // Bit QCS.
	FDCAN_FDCAN_TTOST_RTO_Pos  = 0x8        // Position of RTO field.
	FDCAN_FDCAN_TTOST_RTO_Msk  = 0xff00     // Bit mask of RTO field.
	FDCAN_FDCAN_TTOST_WGTD_Pos = 0x16       // Position of WGTD field.
	FDCAN_FDCAN_TTOST_WGTD_Msk = 0x400000   // Bit mask of WGTD field.
	FDCAN_FDCAN_TTOST_WGTD     = 0x400000   // Bit WGTD.
	FDCAN_FDCAN_TTOST_GFI_Pos  = 0x17       // Position of GFI field.
	FDCAN_FDCAN_TTOST_GFI_Msk  = 0x800000   // Bit mask of GFI field.
	FDCAN_FDCAN_TTOST_GFI      = 0x800000   // Bit GFI.
	FDCAN_FDCAN_TTOST_TMP_Pos  = 0x18       // Position of TMP field.
	FDCAN_FDCAN_TTOST_TMP_Msk  = 0x7000000  // Bit mask of TMP field.
	FDCAN_FDCAN_TTOST_GSI_Pos  = 0x1b       // Position of GSI field.
	FDCAN_FDCAN_TTOST_GSI_Msk  = 0x8000000  // Bit mask of GSI field.
	FDCAN_FDCAN_TTOST_GSI      = 0x8000000  // Bit GSI.
	FDCAN_FDCAN_TTOST_WFE_Pos  = 0x1c       // Position of WFE field.
	FDCAN_FDCAN_TTOST_WFE_Msk  = 0x10000000 // Bit mask of WFE field.
	FDCAN_FDCAN_TTOST_WFE      = 0x10000000 // Bit WFE.
	FDCAN_FDCAN_TTOST_AWE_Pos  = 0x1d       // Position of AWE field.
	FDCAN_FDCAN_TTOST_AWE_Msk  = 0x20000000 // Bit mask of AWE field.
	FDCAN_FDCAN_TTOST_AWE      = 0x20000000 // Bit AWE.
	FDCAN_FDCAN_TTOST_WECS_Pos = 0x1e       // Position of WECS field.
	FDCAN_FDCAN_TTOST_WECS_Msk = 0x40000000 // Bit mask of WECS field.
	FDCAN_FDCAN_TTOST_WECS     = 0x40000000 // Bit WECS.
	FDCAN_FDCAN_TTOST_SPL_Pos  = 0x1f       // Position of SPL field.
	FDCAN_FDCAN_TTOST_SPL_Msk  = 0x80000000 // Bit mask of SPL field.
	FDCAN_FDCAN_TTOST_SPL      = 0x80000000 // Bit SPL.

	// FDCAN_TURNA: FDCAN TUR Numerator Actual           Register
	FDCAN_FDCAN_TURNA_NAV_Pos = 0x0     // Position of NAV field.
	FDCAN_FDCAN_TURNA_NAV_Msk = 0x3ffff // Bit mask of NAV field.

	// FDCAN_TTLGT: FDCAN TT Local and Global Time           Register
	FDCAN_FDCAN_TTLGT_LT_Pos = 0x0        // Position of LT field.
	FDCAN_FDCAN_TTLGT_LT_Msk = 0xffff     // Bit mask of LT field.
	FDCAN_FDCAN_TTLGT_GT_Pos = 0x10       // Position of GT field.
	FDCAN_FDCAN_TTLGT_GT_Msk = 0xffff0000 // Bit mask of GT field.

	// FDCAN_TTCTC: FDCAN TT Cycle Time and Count           Register
	FDCAN_FDCAN_TTCTC_CT_Pos = 0x0      // Position of CT field.
	FDCAN_FDCAN_TTCTC_CT_Msk = 0xffff   // Bit mask of CT field.
	FDCAN_FDCAN_TTCTC_CC_Pos = 0x10     // Position of CC field.
	FDCAN_FDCAN_TTCTC_CC_Msk = 0x3f0000 // Bit mask of CC field.

	// FDCAN_TTCPT: FDCAN TT Capture Time Register
	FDCAN_FDCAN_TTCPT_CT_Pos  = 0x0        // Position of CT field.
	FDCAN_FDCAN_TTCPT_CT_Msk  = 0x3f       // Bit mask of CT field.
	FDCAN_FDCAN_TTCPT_SWV_Pos = 0x10       // Position of SWV field.
	FDCAN_FDCAN_TTCPT_SWV_Msk = 0xffff0000 // Bit mask of SWV field.

	// FDCAN_TTCSM: FDCAN TT Cycle Sync Mark           Register
	FDCAN_FDCAN_TTCSM_CSM_Pos = 0x0    // Position of CSM field.
	FDCAN_FDCAN_TTCSM_CSM_Msk = 0xffff // Bit mask of CSM field.

	// FDCAN_TTTS: FDCAN TT Trigger Select           Register
	FDCAN_FDCAN_TTTS_SWTDEL_Pos = 0x0  // Position of SWTDEL field.
	FDCAN_FDCAN_TTTS_SWTDEL_Msk = 0x3  // Bit mask of SWTDEL field.
	FDCAN_FDCAN_TTTS_EVTSEL_Pos = 0x4  // Position of EVTSEL field.
	FDCAN_FDCAN_TTTS_EVTSEL_Msk = 0x30 // Bit mask of EVTSEL field.
)

// Bitfields for MDIOS: Management data input/output slave
const (
	// CR: MDIOS configuration register
	MDIOS_CR_EN_Pos           = 0x0    // Position of EN field.
	MDIOS_CR_EN_Msk           = 0x1    // Bit mask of EN field.
	MDIOS_CR_EN               = 0x1    // Bit EN.
	MDIOS_CR_WRIE_Pos         = 0x1    // Position of WRIE field.
	MDIOS_CR_WRIE_Msk         = 0x2    // Bit mask of WRIE field.
	MDIOS_CR_WRIE             = 0x2    // Bit WRIE.
	MDIOS_CR_RDIE_Pos         = 0x2    // Position of RDIE field.
	MDIOS_CR_RDIE_Msk         = 0x4    // Bit mask of RDIE field.
	MDIOS_CR_RDIE             = 0x4    // Bit RDIE.
	MDIOS_CR_EIE_Pos          = 0x3    // Position of EIE field.
	MDIOS_CR_EIE_Msk          = 0x8    // Bit mask of EIE field.
	MDIOS_CR_EIE              = 0x8    // Bit EIE.
	MDIOS_CR_DPC_Pos          = 0x7    // Position of DPC field.
	MDIOS_CR_DPC_Msk          = 0x80   // Bit mask of DPC field.
	MDIOS_CR_DPC              = 0x80   // Bit DPC.
	MDIOS_CR_PORT_ADDRESS_Pos = 0x8    // Position of PORT_ADDRESS field.
	MDIOS_CR_PORT_ADDRESS_Msk = 0x1f00 // Bit mask of PORT_ADDRESS field.

	// WRFR: MDIOS write flag register
	MDIOS_WRFR_WRF_Pos = 0x0        // Position of WRF field.
	MDIOS_WRFR_WRF_Msk = 0xffffffff // Bit mask of WRF field.

	// CWRFR: MDIOS clear write flag           register
	MDIOS_CWRFR_CWRF_Pos = 0x0        // Position of CWRF field.
	MDIOS_CWRFR_CWRF_Msk = 0xffffffff // Bit mask of CWRF field.

	// RDFR: MDIOS read flag register
	MDIOS_RDFR_RDF_Pos = 0x0        // Position of RDF field.
	MDIOS_RDFR_RDF_Msk = 0xffffffff // Bit mask of RDF field.

	// CRDFR: MDIOS clear read flag register
	MDIOS_CRDFR_CRDF_Pos = 0x0        // Position of CRDF field.
	MDIOS_CRDFR_CRDF_Msk = 0xffffffff // Bit mask of CRDF field.

	// SR: MDIOS status register
	MDIOS_SR_PERF_Pos = 0x0 // Position of PERF field.
	MDIOS_SR_PERF_Msk = 0x1 // Bit mask of PERF field.
	MDIOS_SR_PERF     = 0x1 // Bit PERF.
	MDIOS_SR_SERF_Pos = 0x1 // Position of SERF field.
	MDIOS_SR_SERF_Msk = 0x2 // Bit mask of SERF field.
	MDIOS_SR_SERF     = 0x2 // Bit SERF.
	MDIOS_SR_TERF_Pos = 0x2 // Position of TERF field.
	MDIOS_SR_TERF_Msk = 0x4 // Bit mask of TERF field.
	MDIOS_SR_TERF     = 0x4 // Bit TERF.

	// CLRFR: MDIOS clear flag register
	MDIOS_CLRFR_CPERF_Pos = 0x0 // Position of CPERF field.
	MDIOS_CLRFR_CPERF_Msk = 0x1 // Bit mask of CPERF field.
	MDIOS_CLRFR_CPERF     = 0x1 // Bit CPERF.
	MDIOS_CLRFR_CSERF_Pos = 0x1 // Position of CSERF field.
	MDIOS_CLRFR_CSERF_Msk = 0x2 // Bit mask of CSERF field.
	MDIOS_CLRFR_CSERF     = 0x2 // Bit CSERF.
	MDIOS_CLRFR_CTERF_Pos = 0x2 // Position of CTERF field.
	MDIOS_CLRFR_CTERF_Msk = 0x4 // Bit mask of CTERF field.
	MDIOS_CLRFR_CTERF     = 0x4 // Bit CTERF.

	// DINR0: MDIOS input data register 0
	MDIOS_DINR0_DIN0_Pos = 0x0    // Position of DIN0 field.
	MDIOS_DINR0_DIN0_Msk = 0xffff // Bit mask of DIN0 field.

	// DINR1: MDIOS input data register 1
	MDIOS_DINR1_DIN1_Pos = 0x0    // Position of DIN1 field.
	MDIOS_DINR1_DIN1_Msk = 0xffff // Bit mask of DIN1 field.

	// DINR2: MDIOS input data register 2
	MDIOS_DINR2_DIN2_Pos = 0x0    // Position of DIN2 field.
	MDIOS_DINR2_DIN2_Msk = 0xffff // Bit mask of DIN2 field.

	// DINR3: MDIOS input data register 3
	MDIOS_DINR3_DIN3_Pos = 0x0    // Position of DIN3 field.
	MDIOS_DINR3_DIN3_Msk = 0xffff // Bit mask of DIN3 field.

	// DINR4: MDIOS input data register 4
	MDIOS_DINR4_DIN4_Pos = 0x0    // Position of DIN4 field.
	MDIOS_DINR4_DIN4_Msk = 0xffff // Bit mask of DIN4 field.

	// DINR5: MDIOS input data register 5
	MDIOS_DINR5_DIN5_Pos = 0x0    // Position of DIN5 field.
	MDIOS_DINR5_DIN5_Msk = 0xffff // Bit mask of DIN5 field.

	// DINR6: MDIOS input data register 6
	MDIOS_DINR6_DIN6_Pos = 0x0    // Position of DIN6 field.
	MDIOS_DINR6_DIN6_Msk = 0xffff // Bit mask of DIN6 field.

	// DINR7: MDIOS input data register 7
	MDIOS_DINR7_DIN7_Pos = 0x0    // Position of DIN7 field.
	MDIOS_DINR7_DIN7_Msk = 0xffff // Bit mask of DIN7 field.

	// DINR8: MDIOS input data register 8
	MDIOS_DINR8_DIN8_Pos = 0x0    // Position of DIN8 field.
	MDIOS_DINR8_DIN8_Msk = 0xffff // Bit mask of DIN8 field.

	// DINR9: MDIOS input data register 9
	MDIOS_DINR9_DIN9_Pos = 0x0    // Position of DIN9 field.
	MDIOS_DINR9_DIN9_Msk = 0xffff // Bit mask of DIN9 field.

	// DINR10: MDIOS input data register 10
	MDIOS_DINR10_DIN10_Pos = 0x0    // Position of DIN10 field.
	MDIOS_DINR10_DIN10_Msk = 0xffff // Bit mask of DIN10 field.

	// DINR11: MDIOS input data register 11
	MDIOS_DINR11_DIN11_Pos = 0x0    // Position of DIN11 field.
	MDIOS_DINR11_DIN11_Msk = 0xffff // Bit mask of DIN11 field.

	// DINR12: MDIOS input data register 12
	MDIOS_DINR12_DIN12_Pos = 0x0    // Position of DIN12 field.
	MDIOS_DINR12_DIN12_Msk = 0xffff // Bit mask of DIN12 field.

	// DINR13: MDIOS input data register 13
	MDIOS_DINR13_DIN13_Pos = 0x0    // Position of DIN13 field.
	MDIOS_DINR13_DIN13_Msk = 0xffff // Bit mask of DIN13 field.

	// DINR14: MDIOS input data register 14
	MDIOS_DINR14_DIN14_Pos = 0x0    // Position of DIN14 field.
	MDIOS_DINR14_DIN14_Msk = 0xffff // Bit mask of DIN14 field.

	// DINR15: MDIOS input data register 15
	MDIOS_DINR15_DIN15_Pos = 0x0    // Position of DIN15 field.
	MDIOS_DINR15_DIN15_Msk = 0xffff // Bit mask of DIN15 field.

	// DINR16: MDIOS input data register 16
	MDIOS_DINR16_DIN16_Pos = 0x0    // Position of DIN16 field.
	MDIOS_DINR16_DIN16_Msk = 0xffff // Bit mask of DIN16 field.

	// DINR17: MDIOS input data register 17
	MDIOS_DINR17_DIN17_Pos = 0x0    // Position of DIN17 field.
	MDIOS_DINR17_DIN17_Msk = 0xffff // Bit mask of DIN17 field.

	// DINR18: MDIOS input data register 18
	MDIOS_DINR18_DIN18_Pos = 0x0    // Position of DIN18 field.
	MDIOS_DINR18_DIN18_Msk = 0xffff // Bit mask of DIN18 field.

	// DINR19: MDIOS input data register 19
	MDIOS_DINR19_DIN19_Pos = 0x0    // Position of DIN19 field.
	MDIOS_DINR19_DIN19_Msk = 0xffff // Bit mask of DIN19 field.

	// DINR20: MDIOS input data register 20
	MDIOS_DINR20_DIN20_Pos = 0x0    // Position of DIN20 field.
	MDIOS_DINR20_DIN20_Msk = 0xffff // Bit mask of DIN20 field.

	// DINR21: MDIOS input data register 21
	MDIOS_DINR21_DIN21_Pos = 0x0    // Position of DIN21 field.
	MDIOS_DINR21_DIN21_Msk = 0xffff // Bit mask of DIN21 field.

	// DINR22: MDIOS input data register 22
	MDIOS_DINR22_DIN22_Pos = 0x0    // Position of DIN22 field.
	MDIOS_DINR22_DIN22_Msk = 0xffff // Bit mask of DIN22 field.

	// DINR23: MDIOS input data register 23
	MDIOS_DINR23_DIN23_Pos = 0x0    // Position of DIN23 field.
	MDIOS_DINR23_DIN23_Msk = 0xffff // Bit mask of DIN23 field.

	// DINR24: MDIOS input data register 24
	MDIOS_DINR24_DIN24_Pos = 0x0    // Position of DIN24 field.
	MDIOS_DINR24_DIN24_Msk = 0xffff // Bit mask of DIN24 field.

	// DINR25: MDIOS input data register 25
	MDIOS_DINR25_DIN25_Pos = 0x0    // Position of DIN25 field.
	MDIOS_DINR25_DIN25_Msk = 0xffff // Bit mask of DIN25 field.

	// DINR26: MDIOS input data register 26
	MDIOS_DINR26_DIN26_Pos = 0x0    // Position of DIN26 field.
	MDIOS_DINR26_DIN26_Msk = 0xffff // Bit mask of DIN26 field.

	// DINR27: MDIOS input data register 27
	MDIOS_DINR27_DIN27_Pos = 0x0    // Position of DIN27 field.
	MDIOS_DINR27_DIN27_Msk = 0xffff // Bit mask of DIN27 field.

	// DINR28: MDIOS input data register 28
	MDIOS_DINR28_DIN28_Pos = 0x0    // Position of DIN28 field.
	MDIOS_DINR28_DIN28_Msk = 0xffff // Bit mask of DIN28 field.

	// DINR29: MDIOS input data register 29
	MDIOS_DINR29_DIN29_Pos = 0x0    // Position of DIN29 field.
	MDIOS_DINR29_DIN29_Msk = 0xffff // Bit mask of DIN29 field.

	// DINR30: MDIOS input data register 30
	MDIOS_DINR30_DIN30_Pos = 0x0    // Position of DIN30 field.
	MDIOS_DINR30_DIN30_Msk = 0xffff // Bit mask of DIN30 field.

	// DINR31: MDIOS input data register 31
	MDIOS_DINR31_DIN31_Pos = 0x0    // Position of DIN31 field.
	MDIOS_DINR31_DIN31_Msk = 0xffff // Bit mask of DIN31 field.

	// DOUTR0: MDIOS output data register 0
	MDIOS_DOUTR0_DOUT0_Pos = 0x0    // Position of DOUT0 field.
	MDIOS_DOUTR0_DOUT0_Msk = 0xffff // Bit mask of DOUT0 field.

	// DOUTR1: MDIOS output data register 1
	MDIOS_DOUTR1_DOUT1_Pos = 0x0    // Position of DOUT1 field.
	MDIOS_DOUTR1_DOUT1_Msk = 0xffff // Bit mask of DOUT1 field.

	// DOUTR2: MDIOS output data register 2
	MDIOS_DOUTR2_DOUT2_Pos = 0x0    // Position of DOUT2 field.
	MDIOS_DOUTR2_DOUT2_Msk = 0xffff // Bit mask of DOUT2 field.

	// DOUTR3: MDIOS output data register 3
	MDIOS_DOUTR3_DOUT3_Pos = 0x0    // Position of DOUT3 field.
	MDIOS_DOUTR3_DOUT3_Msk = 0xffff // Bit mask of DOUT3 field.

	// DOUTR4: MDIOS output data register 4
	MDIOS_DOUTR4_DOUT4_Pos = 0x0    // Position of DOUT4 field.
	MDIOS_DOUTR4_DOUT4_Msk = 0xffff // Bit mask of DOUT4 field.

	// DOUTR5: MDIOS output data register 5
	MDIOS_DOUTR5_DOUT5_Pos = 0x0    // Position of DOUT5 field.
	MDIOS_DOUTR5_DOUT5_Msk = 0xffff // Bit mask of DOUT5 field.

	// DOUTR6: MDIOS output data register 6
	MDIOS_DOUTR6_DOUT6_Pos = 0x0    // Position of DOUT6 field.
	MDIOS_DOUTR6_DOUT6_Msk = 0xffff // Bit mask of DOUT6 field.

	// DOUTR7: MDIOS output data register 7
	MDIOS_DOUTR7_DOUT7_Pos = 0x0    // Position of DOUT7 field.
	MDIOS_DOUTR7_DOUT7_Msk = 0xffff // Bit mask of DOUT7 field.

	// DOUTR8: MDIOS output data register 8
	MDIOS_DOUTR8_DOUT8_Pos = 0x0    // Position of DOUT8 field.
	MDIOS_DOUTR8_DOUT8_Msk = 0xffff // Bit mask of DOUT8 field.

	// DOUTR9: MDIOS output data register 9
	MDIOS_DOUTR9_DOUT9_Pos = 0x0    // Position of DOUT9 field.
	MDIOS_DOUTR9_DOUT9_Msk = 0xffff // Bit mask of DOUT9 field.

	// DOUTR10: MDIOS output data register 10
	MDIOS_DOUTR10_DOUT10_Pos = 0x0    // Position of DOUT10 field.
	MDIOS_DOUTR10_DOUT10_Msk = 0xffff // Bit mask of DOUT10 field.

	// DOUTR11: MDIOS output data register 11
	MDIOS_DOUTR11_DOUT11_Pos = 0x0    // Position of DOUT11 field.
	MDIOS_DOUTR11_DOUT11_Msk = 0xffff // Bit mask of DOUT11 field.

	// DOUTR12: MDIOS output data register 12
	MDIOS_DOUTR12_DOUT12_Pos = 0x0    // Position of DOUT12 field.
	MDIOS_DOUTR12_DOUT12_Msk = 0xffff // Bit mask of DOUT12 field.

	// DOUTR13: MDIOS output data register 13
	MDIOS_DOUTR13_DOUT13_Pos = 0x0    // Position of DOUT13 field.
	MDIOS_DOUTR13_DOUT13_Msk = 0xffff // Bit mask of DOUT13 field.

	// DOUTR14: MDIOS output data register 14
	MDIOS_DOUTR14_DOUT14_Pos = 0x0    // Position of DOUT14 field.
	MDIOS_DOUTR14_DOUT14_Msk = 0xffff // Bit mask of DOUT14 field.

	// DOUTR15: MDIOS output data register 15
	MDIOS_DOUTR15_DOUT15_Pos = 0x0    // Position of DOUT15 field.
	MDIOS_DOUTR15_DOUT15_Msk = 0xffff // Bit mask of DOUT15 field.

	// DOUTR16: MDIOS output data register 16
	MDIOS_DOUTR16_DOUT16_Pos = 0x0    // Position of DOUT16 field.
	MDIOS_DOUTR16_DOUT16_Msk = 0xffff // Bit mask of DOUT16 field.

	// DOUTR17: MDIOS output data register 17
	MDIOS_DOUTR17_DOUT17_Pos = 0x0    // Position of DOUT17 field.
	MDIOS_DOUTR17_DOUT17_Msk = 0xffff // Bit mask of DOUT17 field.

	// DOUTR18: MDIOS output data register 18
	MDIOS_DOUTR18_DOUT18_Pos = 0x0    // Position of DOUT18 field.
	MDIOS_DOUTR18_DOUT18_Msk = 0xffff // Bit mask of DOUT18 field.

	// DOUTR19: MDIOS output data register 19
	MDIOS_DOUTR19_DOUT19_Pos = 0x0    // Position of DOUT19 field.
	MDIOS_DOUTR19_DOUT19_Msk = 0xffff // Bit mask of DOUT19 field.

	// DOUTR20: MDIOS output data register 20
	MDIOS_DOUTR20_DOUT20_Pos = 0x0    // Position of DOUT20 field.
	MDIOS_DOUTR20_DOUT20_Msk = 0xffff // Bit mask of DOUT20 field.

	// DOUTR21: MDIOS output data register 21
	MDIOS_DOUTR21_DOUT21_Pos = 0x0    // Position of DOUT21 field.
	MDIOS_DOUTR21_DOUT21_Msk = 0xffff // Bit mask of DOUT21 field.

	// DOUTR22: MDIOS output data register 22
	MDIOS_DOUTR22_DOUT22_Pos = 0x0    // Position of DOUT22 field.
	MDIOS_DOUTR22_DOUT22_Msk = 0xffff // Bit mask of DOUT22 field.

	// DOUTR23: MDIOS output data register 23
	MDIOS_DOUTR23_DOUT23_Pos = 0x0    // Position of DOUT23 field.
	MDIOS_DOUTR23_DOUT23_Msk = 0xffff // Bit mask of DOUT23 field.

	// DOUTR24: MDIOS output data register 24
	MDIOS_DOUTR24_DOUT24_Pos = 0x0    // Position of DOUT24 field.
	MDIOS_DOUTR24_DOUT24_Msk = 0xffff // Bit mask of DOUT24 field.

	// DOUTR25: MDIOS output data register 25
	MDIOS_DOUTR25_DOUT25_Pos = 0x0    // Position of DOUT25 field.
	MDIOS_DOUTR25_DOUT25_Msk = 0xffff // Bit mask of DOUT25 field.

	// DOUTR26: MDIOS output data register 26
	MDIOS_DOUTR26_DOUT26_Pos = 0x0    // Position of DOUT26 field.
	MDIOS_DOUTR26_DOUT26_Msk = 0xffff // Bit mask of DOUT26 field.

	// DOUTR27: MDIOS output data register 27
	MDIOS_DOUTR27_DOUT27_Pos = 0x0    // Position of DOUT27 field.
	MDIOS_DOUTR27_DOUT27_Msk = 0xffff // Bit mask of DOUT27 field.

	// DOUTR28: MDIOS output data register 28
	MDIOS_DOUTR28_DOUT28_Pos = 0x0    // Position of DOUT28 field.
	MDIOS_DOUTR28_DOUT28_Msk = 0xffff // Bit mask of DOUT28 field.

	// DOUTR29: MDIOS output data register 29
	MDIOS_DOUTR29_DOUT29_Pos = 0x0    // Position of DOUT29 field.
	MDIOS_DOUTR29_DOUT29_Msk = 0xffff // Bit mask of DOUT29 field.

	// DOUTR30: MDIOS output data register 30
	MDIOS_DOUTR30_DOUT30_Pos = 0x0    // Position of DOUT30 field.
	MDIOS_DOUTR30_DOUT30_Msk = 0xffff // Bit mask of DOUT30 field.

	// DOUTR31: MDIOS output data register 31
	MDIOS_DOUTR31_DOUT31_Pos = 0x0    // Position of DOUT31 field.
	MDIOS_DOUTR31_DOUT31_Msk = 0xffff // Bit mask of DOUT31 field.
)

// Bitfields for OPAMP: Operational amplifiers
const (
	// OPAMP1_CSR: OPAMP1 control/status register
	OPAMP_OPAMP1_CSR_OPAEN_Pos    = 0x0        // Position of OPAEN field.
	OPAMP_OPAMP1_CSR_OPAEN_Msk    = 0x1        // Bit mask of OPAEN field.
	OPAMP_OPAMP1_CSR_OPAEN        = 0x1        // Bit OPAEN.
	OPAMP_OPAMP1_CSR_FORCE_VP_Pos = 0x1        // Position of FORCE_VP field.
	OPAMP_OPAMP1_CSR_FORCE_VP_Msk = 0x2        // Bit mask of FORCE_VP field.
	OPAMP_OPAMP1_CSR_FORCE_VP     = 0x2        // Bit FORCE_VP.
	OPAMP_OPAMP1_CSR_VP_SEL_Pos   = 0x2        // Position of VP_SEL field.
	OPAMP_OPAMP1_CSR_VP_SEL_Msk   = 0xc        // Bit mask of VP_SEL field.
	OPAMP_OPAMP1_CSR_VM_SEL_Pos   = 0x5        // Position of VM_SEL field.
	OPAMP_OPAMP1_CSR_VM_SEL_Msk   = 0x60       // Bit mask of VM_SEL field.
	OPAMP_OPAMP1_CSR_OPAHSM_Pos   = 0x8        // Position of OPAHSM field.
	OPAMP_OPAMP1_CSR_OPAHSM_Msk   = 0x100      // Bit mask of OPAHSM field.
	OPAMP_OPAMP1_CSR_OPAHSM       = 0x100      // Bit OPAHSM.
	OPAMP_OPAMP1_CSR_CALON_Pos    = 0xb        // Position of CALON field.
	OPAMP_OPAMP1_CSR_CALON_Msk    = 0x800      // Bit mask of CALON field.
	OPAMP_OPAMP1_CSR_CALON        = 0x800      // Bit CALON.
	OPAMP_OPAMP1_CSR_CALSEL_Pos   = 0xc        // Position of CALSEL field.
	OPAMP_OPAMP1_CSR_CALSEL_Msk   = 0x3000     // Bit mask of CALSEL field.
	OPAMP_OPAMP1_CSR_PGA_GAIN_Pos = 0xe        // Position of PGA_GAIN field.
	OPAMP_OPAMP1_CSR_PGA_GAIN_Msk = 0x3c000    // Bit mask of PGA_GAIN field.
	OPAMP_OPAMP1_CSR_USERTRIM_Pos = 0x12       // Position of USERTRIM field.
	OPAMP_OPAMP1_CSR_USERTRIM_Msk = 0x40000    // Bit mask of USERTRIM field.
	OPAMP_OPAMP1_CSR_USERTRIM     = 0x40000    // Bit USERTRIM.
	OPAMP_OPAMP1_CSR_TSTREF_Pos   = 0x1d       // Position of TSTREF field.
	OPAMP_OPAMP1_CSR_TSTREF_Msk   = 0x20000000 // Bit mask of TSTREF field.
	OPAMP_OPAMP1_CSR_TSTREF       = 0x20000000 // Bit TSTREF.
	OPAMP_OPAMP1_CSR_CALOUT_Pos   = 0x1e       // Position of CALOUT field.
	OPAMP_OPAMP1_CSR_CALOUT_Msk   = 0x40000000 // Bit mask of CALOUT field.
	OPAMP_OPAMP1_CSR_CALOUT       = 0x40000000 // Bit CALOUT.

	// OPAMP1_OTR: OPAMP1 offset trimming register in normal           mode
	OPAMP_OPAMP1_OTR_TRIMOFFSETN_Pos = 0x0    // Position of TRIMOFFSETN field.
	OPAMP_OPAMP1_OTR_TRIMOFFSETN_Msk = 0x1f   // Bit mask of TRIMOFFSETN field.
	OPAMP_OPAMP1_OTR_TRIMOFFSETP_Pos = 0x8    // Position of TRIMOFFSETP field.
	OPAMP_OPAMP1_OTR_TRIMOFFSETP_Msk = 0x1f00 // Bit mask of TRIMOFFSETP field.

	// OPAMP1_HSOTR: OPAMP1 offset trimming register in low-power           mode
	OPAMP_OPAMP1_HSOTR_TRIMLPOFFSETN_Pos = 0x0    // Position of TRIMLPOFFSETN field.
	OPAMP_OPAMP1_HSOTR_TRIMLPOFFSETN_Msk = 0x1f   // Bit mask of TRIMLPOFFSETN field.
	OPAMP_OPAMP1_HSOTR_TRIMLPOFFSETP_Pos = 0x8    // Position of TRIMLPOFFSETP field.
	OPAMP_OPAMP1_HSOTR_TRIMLPOFFSETP_Msk = 0x1f00 // Bit mask of TRIMLPOFFSETP field.

	// OPAMP2_CSR: OPAMP2 control/status register
	OPAMP_OPAMP2_CSR_OPAEN_Pos    = 0x0        // Position of OPAEN field.
	OPAMP_OPAMP2_CSR_OPAEN_Msk    = 0x1        // Bit mask of OPAEN field.
	OPAMP_OPAMP2_CSR_OPAEN        = 0x1        // Bit OPAEN.
	OPAMP_OPAMP2_CSR_FORCE_VP_Pos = 0x1        // Position of FORCE_VP field.
	OPAMP_OPAMP2_CSR_FORCE_VP_Msk = 0x2        // Bit mask of FORCE_VP field.
	OPAMP_OPAMP2_CSR_FORCE_VP     = 0x2        // Bit FORCE_VP.
	OPAMP_OPAMP2_CSR_VM_SEL_Pos   = 0x5        // Position of VM_SEL field.
	OPAMP_OPAMP2_CSR_VM_SEL_Msk   = 0x60       // Bit mask of VM_SEL field.
	OPAMP_OPAMP2_CSR_OPAHSM_Pos   = 0x8        // Position of OPAHSM field.
	OPAMP_OPAMP2_CSR_OPAHSM_Msk   = 0x100      // Bit mask of OPAHSM field.
	OPAMP_OPAMP2_CSR_OPAHSM       = 0x100      // Bit OPAHSM.
	OPAMP_OPAMP2_CSR_CALON_Pos    = 0xb        // Position of CALON field.
	OPAMP_OPAMP2_CSR_CALON_Msk    = 0x800      // Bit mask of CALON field.
	OPAMP_OPAMP2_CSR_CALON        = 0x800      // Bit CALON.
	OPAMP_OPAMP2_CSR_CALSEL_Pos   = 0xc        // Position of CALSEL field.
	OPAMP_OPAMP2_CSR_CALSEL_Msk   = 0x3000     // Bit mask of CALSEL field.
	OPAMP_OPAMP2_CSR_PGA_GAIN_Pos = 0xe        // Position of PGA_GAIN field.
	OPAMP_OPAMP2_CSR_PGA_GAIN_Msk = 0x3c000    // Bit mask of PGA_GAIN field.
	OPAMP_OPAMP2_CSR_USERTRIM_Pos = 0x12       // Position of USERTRIM field.
	OPAMP_OPAMP2_CSR_USERTRIM_Msk = 0x40000    // Bit mask of USERTRIM field.
	OPAMP_OPAMP2_CSR_USERTRIM     = 0x40000    // Bit USERTRIM.
	OPAMP_OPAMP2_CSR_TSTREF_Pos   = 0x1d       // Position of TSTREF field.
	OPAMP_OPAMP2_CSR_TSTREF_Msk   = 0x20000000 // Bit mask of TSTREF field.
	OPAMP_OPAMP2_CSR_TSTREF       = 0x20000000 // Bit TSTREF.
	OPAMP_OPAMP2_CSR_CALOUT_Pos   = 0x1e       // Position of CALOUT field.
	OPAMP_OPAMP2_CSR_CALOUT_Msk   = 0x40000000 // Bit mask of CALOUT field.
	OPAMP_OPAMP2_CSR_CALOUT       = 0x40000000 // Bit CALOUT.

	// OPAMP2_OTR: OPAMP2 offset trimming register in normal           mode
	OPAMP_OPAMP2_OTR_TRIMOFFSETN_Pos = 0x0    // Position of TRIMOFFSETN field.
	OPAMP_OPAMP2_OTR_TRIMOFFSETN_Msk = 0x1f   // Bit mask of TRIMOFFSETN field.
	OPAMP_OPAMP2_OTR_TRIMOFFSETP_Pos = 0x8    // Position of TRIMOFFSETP field.
	OPAMP_OPAMP2_OTR_TRIMOFFSETP_Msk = 0x1f00 // Bit mask of TRIMOFFSETP field.

	// OPAMP2_HSOTR: OPAMP2 offset trimming register in low-power           mode
	OPAMP_OPAMP2_HSOTR_TRIMLPOFFSETN_Pos = 0x0    // Position of TRIMLPOFFSETN field.
	OPAMP_OPAMP2_HSOTR_TRIMLPOFFSETN_Msk = 0x1f   // Bit mask of TRIMLPOFFSETN field.
	OPAMP_OPAMP2_HSOTR_TRIMLPOFFSETP_Pos = 0x8    // Position of TRIMLPOFFSETP field.
	OPAMP_OPAMP2_HSOTR_TRIMLPOFFSETP_Msk = 0x1f00 // Bit mask of TRIMLPOFFSETP field.
)

// Bitfields for SWPMI: Single Wire Protocol Master Interface
const (
	// CR: SWPMI Configuration/Control           register
	SWPMI_CR_RXDMA_Pos  = 0x0   // Position of RXDMA field.
	SWPMI_CR_RXDMA_Msk  = 0x1   // Bit mask of RXDMA field.
	SWPMI_CR_RXDMA      = 0x1   // Bit RXDMA.
	SWPMI_CR_TXDMA_Pos  = 0x1   // Position of TXDMA field.
	SWPMI_CR_TXDMA_Msk  = 0x2   // Bit mask of TXDMA field.
	SWPMI_CR_TXDMA      = 0x2   // Bit TXDMA.
	SWPMI_CR_RXMODE_Pos = 0x2   // Position of RXMODE field.
	SWPMI_CR_RXMODE_Msk = 0x4   // Bit mask of RXMODE field.
	SWPMI_CR_RXMODE     = 0x4   // Bit RXMODE.
	SWPMI_CR_TXMODE_Pos = 0x3   // Position of TXMODE field.
	SWPMI_CR_TXMODE_Msk = 0x8   // Bit mask of TXMODE field.
	SWPMI_CR_TXMODE     = 0x8   // Bit TXMODE.
	SWPMI_CR_LPBK_Pos   = 0x4   // Position of LPBK field.
	SWPMI_CR_LPBK_Msk   = 0x10  // Bit mask of LPBK field.
	SWPMI_CR_LPBK       = 0x10  // Bit LPBK.
	SWPMI_CR_SWPACT_Pos = 0x5   // Position of SWPACT field.
	SWPMI_CR_SWPACT_Msk = 0x20  // Bit mask of SWPACT field.
	SWPMI_CR_SWPACT     = 0x20  // Bit SWPACT.
	SWPMI_CR_DEACT_Pos  = 0xa   // Position of DEACT field.
	SWPMI_CR_DEACT_Msk  = 0x400 // Bit mask of DEACT field.
	SWPMI_CR_DEACT      = 0x400 // Bit DEACT.
	SWPMI_CR_SWPTEN_Pos = 0xb   // Position of SWPTEN field.
	SWPMI_CR_SWPTEN_Msk = 0x800 // Bit mask of SWPTEN field.
	SWPMI_CR_SWPTEN     = 0x800 // Bit SWPTEN.

	// BRR: SWPMI Bitrate register
	SWPMI_BRR_BR_Pos = 0x0  // Position of BR field.
	SWPMI_BRR_BR_Msk = 0xff // Bit mask of BR field.

	// ISR: SWPMI Interrupt and Status           register
	SWPMI_ISR_RXBFF_Pos  = 0x0   // Position of RXBFF field.
	SWPMI_ISR_RXBFF_Msk  = 0x1   // Bit mask of RXBFF field.
	SWPMI_ISR_RXBFF      = 0x1   // Bit RXBFF.
	SWPMI_ISR_TXBEF_Pos  = 0x1   // Position of TXBEF field.
	SWPMI_ISR_TXBEF_Msk  = 0x2   // Bit mask of TXBEF field.
	SWPMI_ISR_TXBEF      = 0x2   // Bit TXBEF.
	SWPMI_ISR_RXBERF_Pos = 0x2   // Position of RXBERF field.
	SWPMI_ISR_RXBERF_Msk = 0x4   // Bit mask of RXBERF field.
	SWPMI_ISR_RXBERF     = 0x4   // Bit RXBERF.
	SWPMI_ISR_RXOVRF_Pos = 0x3   // Position of RXOVRF field.
	SWPMI_ISR_RXOVRF_Msk = 0x8   // Bit mask of RXOVRF field.
	SWPMI_ISR_RXOVRF     = 0x8   // Bit RXOVRF.
	SWPMI_ISR_TXUNRF_Pos = 0x4   // Position of TXUNRF field.
	SWPMI_ISR_TXUNRF_Msk = 0x10  // Bit mask of TXUNRF field.
	SWPMI_ISR_TXUNRF     = 0x10  // Bit TXUNRF.
	SWPMI_ISR_RXNE_Pos   = 0x5   // Position of RXNE field.
	SWPMI_ISR_RXNE_Msk   = 0x20  // Bit mask of RXNE field.
	SWPMI_ISR_RXNE       = 0x20  // Bit RXNE.
	SWPMI_ISR_TXE_Pos    = 0x6   // Position of TXE field.
	SWPMI_ISR_TXE_Msk    = 0x40  // Bit mask of TXE field.
	SWPMI_ISR_TXE        = 0x40  // Bit TXE.
	SWPMI_ISR_TCF_Pos    = 0x7   // Position of TCF field.
	SWPMI_ISR_TCF_Msk    = 0x80  // Bit mask of TCF field.
	SWPMI_ISR_TCF        = 0x80  // Bit TCF.
	SWPMI_ISR_SRF_Pos    = 0x8   // Position of SRF field.
	SWPMI_ISR_SRF_Msk    = 0x100 // Bit mask of SRF field.
	SWPMI_ISR_SRF        = 0x100 // Bit SRF.
	SWPMI_ISR_SUSP_Pos   = 0x9   // Position of SUSP field.
	SWPMI_ISR_SUSP_Msk   = 0x200 // Bit mask of SUSP field.
	SWPMI_ISR_SUSP       = 0x200 // Bit SUSP.
	SWPMI_ISR_DEACTF_Pos = 0xa   // Position of DEACTF field.
	SWPMI_ISR_DEACTF_Msk = 0x400 // Bit mask of DEACTF field.
	SWPMI_ISR_DEACTF     = 0x400 // Bit DEACTF.
	SWPMI_ISR_RDYF_Pos   = 0xb   // Position of RDYF field.
	SWPMI_ISR_RDYF_Msk   = 0x800 // Bit mask of RDYF field.
	SWPMI_ISR_RDYF       = 0x800 // Bit RDYF.

	// ICR: SWPMI Interrupt Flag Clear           register
	SWPMI_ICR_CRXBFF_Pos  = 0x0   // Position of CRXBFF field.
	SWPMI_ICR_CRXBFF_Msk  = 0x1   // Bit mask of CRXBFF field.
	SWPMI_ICR_CRXBFF      = 0x1   // Bit CRXBFF.
	SWPMI_ICR_CTXBEF_Pos  = 0x1   // Position of CTXBEF field.
	SWPMI_ICR_CTXBEF_Msk  = 0x2   // Bit mask of CTXBEF field.
	SWPMI_ICR_CTXBEF      = 0x2   // Bit CTXBEF.
	SWPMI_ICR_CRXBERF_Pos = 0x2   // Position of CRXBERF field.
	SWPMI_ICR_CRXBERF_Msk = 0x4   // Bit mask of CRXBERF field.
	SWPMI_ICR_CRXBERF     = 0x4   // Bit CRXBERF.
	SWPMI_ICR_CRXOVRF_Pos = 0x3   // Position of CRXOVRF field.
	SWPMI_ICR_CRXOVRF_Msk = 0x8   // Bit mask of CRXOVRF field.
	SWPMI_ICR_CRXOVRF     = 0x8   // Bit CRXOVRF.
	SWPMI_ICR_CTXUNRF_Pos = 0x4   // Position of CTXUNRF field.
	SWPMI_ICR_CTXUNRF_Msk = 0x10  // Bit mask of CTXUNRF field.
	SWPMI_ICR_CTXUNRF     = 0x10  // Bit CTXUNRF.
	SWPMI_ICR_CTCF_Pos    = 0x7   // Position of CTCF field.
	SWPMI_ICR_CTCF_Msk    = 0x80  // Bit mask of CTCF field.
	SWPMI_ICR_CTCF        = 0x80  // Bit CTCF.
	SWPMI_ICR_CSRF_Pos    = 0x8   // Position of CSRF field.
	SWPMI_ICR_CSRF_Msk    = 0x100 // Bit mask of CSRF field.
	SWPMI_ICR_CSRF        = 0x100 // Bit CSRF.
	SWPMI_ICR_CRDYF_Pos   = 0xb   // Position of CRDYF field.
	SWPMI_ICR_CRDYF_Msk   = 0x800 // Bit mask of CRDYF field.
	SWPMI_ICR_CRDYF       = 0x800 // Bit CRDYF.

	// IER: SWPMI Interrupt Enable           register
	SWPMI_IER_RXBFIE_Pos  = 0x0   // Position of RXBFIE field.
	SWPMI_IER_RXBFIE_Msk  = 0x1   // Bit mask of RXBFIE field.
	SWPMI_IER_RXBFIE      = 0x1   // Bit RXBFIE.
	SWPMI_IER_TXBEIE_Pos  = 0x1   // Position of TXBEIE field.
	SWPMI_IER_TXBEIE_Msk  = 0x2   // Bit mask of TXBEIE field.
	SWPMI_IER_TXBEIE      = 0x2   // Bit TXBEIE.
	SWPMI_IER_RXBERIE_Pos = 0x2   // Position of RXBERIE field.
	SWPMI_IER_RXBERIE_Msk = 0x4   // Bit mask of RXBERIE field.
	SWPMI_IER_RXBERIE     = 0x4   // Bit RXBERIE.
	SWPMI_IER_RXOVRIE_Pos = 0x3   // Position of RXOVRIE field.
	SWPMI_IER_RXOVRIE_Msk = 0x8   // Bit mask of RXOVRIE field.
	SWPMI_IER_RXOVRIE     = 0x8   // Bit RXOVRIE.
	SWPMI_IER_TXUNRIE_Pos = 0x4   // Position of TXUNRIE field.
	SWPMI_IER_TXUNRIE_Msk = 0x10  // Bit mask of TXUNRIE field.
	SWPMI_IER_TXUNRIE     = 0x10  // Bit TXUNRIE.
	SWPMI_IER_RIE_Pos     = 0x5   // Position of RIE field.
	SWPMI_IER_RIE_Msk     = 0x20  // Bit mask of RIE field.
	SWPMI_IER_RIE         = 0x20  // Bit RIE.
	SWPMI_IER_TIE_Pos     = 0x6   // Position of TIE field.
	SWPMI_IER_TIE_Msk     = 0x40  // Bit mask of TIE field.
	SWPMI_IER_TIE         = 0x40  // Bit TIE.
	SWPMI_IER_TCIE_Pos    = 0x7   // Position of TCIE field.
	SWPMI_IER_TCIE_Msk    = 0x80  // Bit mask of TCIE field.
	SWPMI_IER_TCIE        = 0x80  // Bit TCIE.
	SWPMI_IER_SRIE_Pos    = 0x8   // Position of SRIE field.
	SWPMI_IER_SRIE_Msk    = 0x100 // Bit mask of SRIE field.
	SWPMI_IER_SRIE        = 0x100 // Bit SRIE.
	SWPMI_IER_RDYIE_Pos   = 0xb   // Position of RDYIE field.
	SWPMI_IER_RDYIE_Msk   = 0x800 // Bit mask of RDYIE field.
	SWPMI_IER_RDYIE       = 0x800 // Bit RDYIE.

	// RFL: SWPMI Receive Frame Length           register
	SWPMI_RFL_RFL_Pos = 0x0  // Position of RFL field.
	SWPMI_RFL_RFL_Msk = 0x1f // Bit mask of RFL field.

	// TDR: SWPMI Transmit data register
	SWPMI_TDR_TD_Pos = 0x0        // Position of TD field.
	SWPMI_TDR_TD_Msk = 0xffffffff // Bit mask of TD field.

	// RDR: SWPMI Receive data register
	SWPMI_RDR_RD_Pos = 0x0        // Position of RD field.
	SWPMI_RDR_RD_Msk = 0xffffffff // Bit mask of RD field.

	// OR: SWPMI Option register
	SWPMI_OR_SWP_TBYP_Pos  = 0x0 // Position of SWP_TBYP field.
	SWPMI_OR_SWP_TBYP_Msk  = 0x1 // Bit mask of SWP_TBYP field.
	SWPMI_OR_SWP_TBYP      = 0x1 // Bit SWP_TBYP.
	SWPMI_OR_SWP_CLASS_Pos = 0x1 // Position of SWP_CLASS field.
	SWPMI_OR_SWP_CLASS_Msk = 0x2 // Bit mask of SWP_CLASS field.
	SWPMI_OR_SWP_CLASS     = 0x2 // Bit SWP_CLASS.
)

// Bitfields for NVIC: Nested Vectored Interrupt Controller
const (
	// ISER0: Interrupt Set-Enable Register
	NVIC_ISER0_SETENA_Pos = 0x0        // Position of SETENA field.
	NVIC_ISER0_SETENA_Msk = 0xffffffff // Bit mask of SETENA field.

	// ISER1: Interrupt Set-Enable Register
	NVIC_ISER1_SETENA_Pos = 0x0        // Position of SETENA field.
	NVIC_ISER1_SETENA_Msk = 0xffffffff // Bit mask of SETENA field.

	// ISER2: Interrupt Set-Enable Register
	NVIC_ISER2_SETENA_Pos = 0x0        // Position of SETENA field.
	NVIC_ISER2_SETENA_Msk = 0xffffffff // Bit mask of SETENA field.

	// ICER0: Interrupt Clear-Enable           Register
	NVIC_ICER0_CLRENA_Pos = 0x0        // Position of CLRENA field.
	NVIC_ICER0_CLRENA_Msk = 0xffffffff // Bit mask of CLRENA field.

	// ICER1: Interrupt Clear-Enable           Register
	NVIC_ICER1_CLRENA_Pos = 0x0        // Position of CLRENA field.
	NVIC_ICER1_CLRENA_Msk = 0xffffffff // Bit mask of CLRENA field.

	// ICER2: Interrupt Clear-Enable           Register
	NVIC_ICER2_CLRENA_Pos = 0x0        // Position of CLRENA field.
	NVIC_ICER2_CLRENA_Msk = 0xffffffff // Bit mask of CLRENA field.

	// ISPR0: Interrupt Set-Pending Register
	NVIC_ISPR0_SETPEND_Pos = 0x0        // Position of SETPEND field.
	NVIC_ISPR0_SETPEND_Msk = 0xffffffff // Bit mask of SETPEND field.

	// ISPR1: Interrupt Set-Pending Register
	NVIC_ISPR1_SETPEND_Pos = 0x0        // Position of SETPEND field.
	NVIC_ISPR1_SETPEND_Msk = 0xffffffff // Bit mask of SETPEND field.

	// ISPR2: Interrupt Set-Pending Register
	NVIC_ISPR2_SETPEND_Pos = 0x0        // Position of SETPEND field.
	NVIC_ISPR2_SETPEND_Msk = 0xffffffff // Bit mask of SETPEND field.

	// ICPR0: Interrupt Clear-Pending           Register
	NVIC_ICPR0_CLRPEND_Pos = 0x0        // Position of CLRPEND field.
	NVIC_ICPR0_CLRPEND_Msk = 0xffffffff // Bit mask of CLRPEND field.

	// ICPR1: Interrupt Clear-Pending           Register
	NVIC_ICPR1_CLRPEND_Pos = 0x0        // Position of CLRPEND field.
	NVIC_ICPR1_CLRPEND_Msk = 0xffffffff // Bit mask of CLRPEND field.

	// ICPR2: Interrupt Clear-Pending           Register
	NVIC_ICPR2_CLRPEND_Pos = 0x0        // Position of CLRPEND field.
	NVIC_ICPR2_CLRPEND_Msk = 0xffffffff // Bit mask of CLRPEND field.

	// IABR0: Interrupt Active Bit Register
	NVIC_IABR0_ACTIVE_Pos = 0x0        // Position of ACTIVE field.
	NVIC_IABR0_ACTIVE_Msk = 0xffffffff // Bit mask of ACTIVE field.

	// IABR1: Interrupt Active Bit Register
	NVIC_IABR1_ACTIVE_Pos = 0x0        // Position of ACTIVE field.
	NVIC_IABR1_ACTIVE_Msk = 0xffffffff // Bit mask of ACTIVE field.

	// IABR2: Interrupt Active Bit Register
	NVIC_IABR2_ACTIVE_Pos = 0x0        // Position of ACTIVE field.
	NVIC_IABR2_ACTIVE_Msk = 0xffffffff // Bit mask of ACTIVE field.

	// IPR0: Interrupt Priority Register
	NVIC_IPR0_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR0_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR0_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR0_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR0_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR0_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR0_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR0_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR1: Interrupt Priority Register
	NVIC_IPR1_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR1_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR1_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR1_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR1_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR1_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR1_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR1_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR2: Interrupt Priority Register
	NVIC_IPR2_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR2_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR2_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR2_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR2_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR2_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR2_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR2_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR3: Interrupt Priority Register
	NVIC_IPR3_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR3_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR3_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR3_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR3_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR3_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR3_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR3_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR4: Interrupt Priority Register
	NVIC_IPR4_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR4_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR4_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR4_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR4_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR4_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR4_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR4_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR5: Interrupt Priority Register
	NVIC_IPR5_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR5_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR5_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR5_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR5_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR5_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR5_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR5_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR6: Interrupt Priority Register
	NVIC_IPR6_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR6_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR6_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR6_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR6_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR6_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR6_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR6_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR7: Interrupt Priority Register
	NVIC_IPR7_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR7_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR7_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR7_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR7_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR7_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR7_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR7_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR8: Interrupt Priority Register
	NVIC_IPR8_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR8_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR8_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR8_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR8_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR8_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR8_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR8_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR9: Interrupt Priority Register
	NVIC_IPR9_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR9_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR9_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR9_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR9_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR9_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR9_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR9_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR10: Interrupt Priority Register
	NVIC_IPR10_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR10_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR10_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR10_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR10_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR10_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR10_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR10_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR11: Interrupt Priority Register
	NVIC_IPR11_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR11_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR11_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR11_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR11_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR11_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR11_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR11_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR12: Interrupt Priority Register
	NVIC_IPR12_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR12_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR12_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR12_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR12_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR12_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR12_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR12_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR13: Interrupt Priority Register
	NVIC_IPR13_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR13_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR13_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR13_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR13_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR13_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR13_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR13_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR14: Interrupt Priority Register
	NVIC_IPR14_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR14_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR14_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR14_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR14_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR14_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR14_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR14_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR15: Interrupt Priority Register
	NVIC_IPR15_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR15_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR15_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR15_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR15_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR15_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR15_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR15_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR16: Interrupt Priority Register
	NVIC_IPR16_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR16_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR16_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR16_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR16_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR16_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR16_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR16_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR17: Interrupt Priority Register
	NVIC_IPR17_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR17_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR17_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR17_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR17_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR17_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR17_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR17_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR18: Interrupt Priority Register
	NVIC_IPR18_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR18_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR18_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR18_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR18_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR18_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR18_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR18_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR19: Interrupt Priority Register
	NVIC_IPR19_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR19_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR19_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR19_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR19_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR19_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR19_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR19_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR20: Interrupt Priority Register
	NVIC_IPR20_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR20_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR20_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR20_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR20_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR20_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR20_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR20_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR21: Interrupt Priority Register
	NVIC_IPR21_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR21_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR21_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR21_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR21_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR21_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR21_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR21_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR22: Interrupt Priority Register
	NVIC_IPR22_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR22_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR22_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR22_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR22_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR22_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR22_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR22_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR23: Interrupt Priority Register
	NVIC_IPR23_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR23_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR23_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR23_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR23_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR23_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR23_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR23_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR24: Interrupt Priority Register
	NVIC_IPR24_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR24_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR24_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR24_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR24_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR24_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR24_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR24_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR25: Interrupt Priority Register
	NVIC_IPR25_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR25_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR25_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR25_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR25_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR25_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR25_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR25_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR26: Interrupt Priority Register
	NVIC_IPR26_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR26_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR26_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR26_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR26_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR26_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR26_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR26_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR27: Interrupt Priority Register
	NVIC_IPR27_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR27_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR27_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR27_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR27_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR27_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR27_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR27_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR28: Interrupt Priority Register
	NVIC_IPR28_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR28_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR28_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR28_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR28_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR28_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR28_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR28_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR29: Interrupt Priority Register
	NVIC_IPR29_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR29_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR29_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR29_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR29_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR29_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR29_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR29_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR30: Interrupt Priority Register
	NVIC_IPR30_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR30_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR30_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR30_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR30_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR30_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR30_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR30_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR31: Interrupt Priority Register
	NVIC_IPR31_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR31_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR31_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR31_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR31_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR31_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR31_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR31_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR32: Interrupt Priority Register
	NVIC_IPR32_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR32_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR32_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR32_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR32_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR32_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR32_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR32_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR33: Interrupt Priority Register
	NVIC_IPR33_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR33_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR33_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR33_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR33_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR33_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR33_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR33_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR34: Interrupt Priority Register
	NVIC_IPR34_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR34_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR34_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR34_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR34_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR34_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR34_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR34_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR35: Interrupt Priority Register
	NVIC_IPR35_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR35_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR35_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR35_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR35_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR35_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR35_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR35_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR36: Interrupt Priority Register
	NVIC_IPR36_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR36_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR36_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR36_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR36_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR36_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR36_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR36_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR37: Interrupt Priority Register
	NVIC_IPR37_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR37_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR37_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR37_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR37_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR37_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR37_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR37_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR38: Interrupt Priority Register
	NVIC_IPR38_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR38_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR38_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR38_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR38_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR38_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR38_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR38_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.

	// IPR39: Interrupt Priority Register
	NVIC_IPR39_IPR_N0_Pos = 0x0        // Position of IPR_N0 field.
	NVIC_IPR39_IPR_N0_Msk = 0xff       // Bit mask of IPR_N0 field.
	NVIC_IPR39_IPR_N1_Pos = 0x8        // Position of IPR_N1 field.
	NVIC_IPR39_IPR_N1_Msk = 0xff00     // Bit mask of IPR_N1 field.
	NVIC_IPR39_IPR_N2_Pos = 0x10       // Position of IPR_N2 field.
	NVIC_IPR39_IPR_N2_Msk = 0xff0000   // Bit mask of IPR_N2 field.
	NVIC_IPR39_IPR_N3_Pos = 0x18       // Position of IPR_N3 field.
	NVIC_IPR39_IPR_N3_Msk = 0xff000000 // Bit mask of IPR_N3 field.
)

// Bitfields for MPU: Memory protection unit
const (
	// MPU_TYPER: MPU type register
	MPU_MPU_TYPER_SEPARATE_Pos = 0x0      // Position of SEPARATE field.
	MPU_MPU_TYPER_SEPARATE_Msk = 0x1      // Bit mask of SEPARATE field.
	MPU_MPU_TYPER_SEPARATE     = 0x1      // Bit SEPARATE.
	MPU_MPU_TYPER_DREGION_Pos  = 0x8      // Position of DREGION field.
	MPU_MPU_TYPER_DREGION_Msk  = 0xff00   // Bit mask of DREGION field.
	MPU_MPU_TYPER_IREGION_Pos  = 0x10     // Position of IREGION field.
	MPU_MPU_TYPER_IREGION_Msk  = 0xff0000 // Bit mask of IREGION field.

	// MPU_CTRL: MPU control register
	MPU_MPU_CTRL_ENABLE_Pos     = 0x0 // Position of ENABLE field.
	MPU_MPU_CTRL_ENABLE_Msk     = 0x1 // Bit mask of ENABLE field.
	MPU_MPU_CTRL_ENABLE         = 0x1 // Bit ENABLE.
	MPU_MPU_CTRL_HFNMIENA_Pos   = 0x1 // Position of HFNMIENA field.
	MPU_MPU_CTRL_HFNMIENA_Msk   = 0x2 // Bit mask of HFNMIENA field.
	MPU_MPU_CTRL_HFNMIENA       = 0x2 // Bit HFNMIENA.
	MPU_MPU_CTRL_PRIVDEFENA_Pos = 0x2 // Position of PRIVDEFENA field.
	MPU_MPU_CTRL_PRIVDEFENA_Msk = 0x4 // Bit mask of PRIVDEFENA field.
	MPU_MPU_CTRL_PRIVDEFENA     = 0x4 // Bit PRIVDEFENA.

	// MPU_RNR: MPU region number register
	MPU_MPU_RNR_REGION_Pos = 0x0  // Position of REGION field.
	MPU_MPU_RNR_REGION_Msk = 0xff // Bit mask of REGION field.

	// MPU_RBAR: MPU region base address           register
	MPU_MPU_RBAR_REGION_Pos = 0x0        // Position of REGION field.
	MPU_MPU_RBAR_REGION_Msk = 0xf        // Bit mask of REGION field.
	MPU_MPU_RBAR_VALID_Pos  = 0x4        // Position of VALID field.
	MPU_MPU_RBAR_VALID_Msk  = 0x10       // Bit mask of VALID field.
	MPU_MPU_RBAR_VALID      = 0x10       // Bit VALID.
	MPU_MPU_RBAR_ADDR_Pos   = 0x5        // Position of ADDR field.
	MPU_MPU_RBAR_ADDR_Msk   = 0xffffffe0 // Bit mask of ADDR field.

	// MPU_RASR: MPU region attribute and size           register
	MPU_MPU_RASR_ENABLE_Pos = 0x0        // Position of ENABLE field.
	MPU_MPU_RASR_ENABLE_Msk = 0x1        // Bit mask of ENABLE field.
	MPU_MPU_RASR_ENABLE     = 0x1        // Bit ENABLE.
	MPU_MPU_RASR_SIZE_Pos   = 0x1        // Position of SIZE field.
	MPU_MPU_RASR_SIZE_Msk   = 0x3e       // Bit mask of SIZE field.
	MPU_MPU_RASR_SRD_Pos    = 0x8        // Position of SRD field.
	MPU_MPU_RASR_SRD_Msk    = 0xff00     // Bit mask of SRD field.
	MPU_MPU_RASR_B_Pos      = 0x10       // Position of B field.
	MPU_MPU_RASR_B_Msk      = 0x10000    // Bit mask of B field.
	MPU_MPU_RASR_B          = 0x10000    // Bit B.
	MPU_MPU_RASR_C_Pos      = 0x11       // Position of C field.
	MPU_MPU_RASR_C_Msk      = 0x20000    // Bit mask of C field.
	MPU_MPU_RASR_C          = 0x20000    // Bit C.
	MPU_MPU_RASR_S_Pos      = 0x12       // Position of S field.
	MPU_MPU_RASR_S_Msk      = 0x40000    // Bit mask of S field.
	MPU_MPU_RASR_S          = 0x40000    // Bit S.
	MPU_MPU_RASR_TEX_Pos    = 0x13       // Position of TEX field.
	MPU_MPU_RASR_TEX_Msk    = 0x380000   // Bit mask of TEX field.
	MPU_MPU_RASR_AP_Pos     = 0x18       // Position of AP field.
	MPU_MPU_RASR_AP_Msk     = 0x7000000  // Bit mask of AP field.
	MPU_MPU_RASR_XN_Pos     = 0x1c       // Position of XN field.
	MPU_MPU_RASR_XN_Msk     = 0x10000000 // Bit mask of XN field.
	MPU_MPU_RASR_XN         = 0x10000000 // Bit XN.
)

// Bitfields for STK: SysTick timer
const (
	// CSR: SysTick control and status           register
	STK_CSR_ENABLE_Pos    = 0x0     // Position of ENABLE field.
	STK_CSR_ENABLE_Msk    = 0x1     // Bit mask of ENABLE field.
	STK_CSR_ENABLE        = 0x1     // Bit ENABLE.
	STK_CSR_TICKINT_Pos   = 0x1     // Position of TICKINT field.
	STK_CSR_TICKINT_Msk   = 0x2     // Bit mask of TICKINT field.
	STK_CSR_TICKINT       = 0x2     // Bit TICKINT.
	STK_CSR_CLKSOURCE_Pos = 0x2     // Position of CLKSOURCE field.
	STK_CSR_CLKSOURCE_Msk = 0x4     // Bit mask of CLKSOURCE field.
	STK_CSR_CLKSOURCE     = 0x4     // Bit CLKSOURCE.
	STK_CSR_COUNTFLAG_Pos = 0x10    // Position of COUNTFLAG field.
	STK_CSR_COUNTFLAG_Msk = 0x10000 // Bit mask of COUNTFLAG field.
	STK_CSR_COUNTFLAG     = 0x10000 // Bit COUNTFLAG.

	// RVR: SysTick reload value register
	STK_RVR_RELOAD_Pos = 0x0      // Position of RELOAD field.
	STK_RVR_RELOAD_Msk = 0xffffff // Bit mask of RELOAD field.

	// CVR: SysTick current value register
	STK_CVR_CURRENT_Pos = 0x0      // Position of CURRENT field.
	STK_CVR_CURRENT_Msk = 0xffffff // Bit mask of CURRENT field.

	// CALIB: SysTick calibration value           register
	STK_CALIB_TENMS_Pos = 0x0        // Position of TENMS field.
	STK_CALIB_TENMS_Msk = 0xffffff   // Bit mask of TENMS field.
	STK_CALIB_SKEW_Pos  = 0x1e       // Position of SKEW field.
	STK_CALIB_SKEW_Msk  = 0x40000000 // Bit mask of SKEW field.
	STK_CALIB_SKEW      = 0x40000000 // Bit SKEW.
	STK_CALIB_NOREF_Pos = 0x1f       // Position of NOREF field.
	STK_CALIB_NOREF_Msk = 0x80000000 // Bit mask of NOREF field.
	STK_CALIB_NOREF     = 0x80000000 // Bit NOREF.
)

// Bitfields for FPU_CPACR: Floating point unit CPACR
const (
	// CPACR: Coprocessor access control           register
	FPU_CPACR_CP_Pos = 0x14     // Position of CP field.
	FPU_CPACR_CP_Msk = 0xf00000 // Bit mask of CP field.
)

// Bitfields for SCB_ACTRL: System control block ACTLR
const (
	// ACTRL: Auxiliary control register
	SCB_ACTRL_DISFOLD_Pos        = 0x2    // Position of DISFOLD field.
	SCB_ACTRL_DISFOLD_Msk        = 0x4    // Bit mask of DISFOLD field.
	SCB_ACTRL_DISFOLD            = 0x4    // Bit DISFOLD.
	SCB_ACTRL_FPEXCODIS_Pos      = 0xa    // Position of FPEXCODIS field.
	SCB_ACTRL_FPEXCODIS_Msk      = 0x400  // Bit mask of FPEXCODIS field.
	SCB_ACTRL_FPEXCODIS          = 0x400  // Bit FPEXCODIS.
	SCB_ACTRL_DISRAMODE_Pos      = 0xb    // Position of DISRAMODE field.
	SCB_ACTRL_DISRAMODE_Msk      = 0x800  // Bit mask of DISRAMODE field.
	SCB_ACTRL_DISRAMODE          = 0x800  // Bit DISRAMODE.
	SCB_ACTRL_DISITMATBFLUSH_Pos = 0xc    // Position of DISITMATBFLUSH field.
	SCB_ACTRL_DISITMATBFLUSH_Msk = 0x1000 // Bit mask of DISITMATBFLUSH field.
	SCB_ACTRL_DISITMATBFLUSH     = 0x1000 // Bit DISITMATBFLUSH.
)

// Bitfields for PF: Processor features
const (
	// CLIDR: Cache Level ID register
	PF_CLIDR_CL1_Pos   = 0x0        // Position of CL1 field.
	PF_CLIDR_CL1_Msk   = 0x7        // Bit mask of CL1 field.
	PF_CLIDR_CL2_Pos   = 0x3        // Position of CL2 field.
	PF_CLIDR_CL2_Msk   = 0x38       // Bit mask of CL2 field.
	PF_CLIDR_CL3_Pos   = 0x6        // Position of CL3 field.
	PF_CLIDR_CL3_Msk   = 0x1c0      // Bit mask of CL3 field.
	PF_CLIDR_CL4_Pos   = 0x9        // Position of CL4 field.
	PF_CLIDR_CL4_Msk   = 0xe00      // Bit mask of CL4 field.
	PF_CLIDR_CL5_Pos   = 0xc        // Position of CL5 field.
	PF_CLIDR_CL5_Msk   = 0x7000     // Bit mask of CL5 field.
	PF_CLIDR_CL6_Pos   = 0xf        // Position of CL6 field.
	PF_CLIDR_CL6_Msk   = 0x38000    // Bit mask of CL6 field.
	PF_CLIDR_CL7_Pos   = 0x12       // Position of CL7 field.
	PF_CLIDR_CL7_Msk   = 0x1c0000   // Bit mask of CL7 field.
	PF_CLIDR_LoUIS_Pos = 0x15       // Position of LoUIS field.
	PF_CLIDR_LoUIS_Msk = 0xe00000   // Bit mask of LoUIS field.
	PF_CLIDR_LoC_Pos   = 0x18       // Position of LoC field.
	PF_CLIDR_LoC_Msk   = 0x7000000  // Bit mask of LoC field.
	PF_CLIDR_LoU_Pos   = 0x1b       // Position of LoU field.
	PF_CLIDR_LoU_Msk   = 0x38000000 // Bit mask of LoU field.

	// CTR: Cache Type register
	PF_CTR__IMINLINE_Pos = 0x0        // Position of _IMINLINE field.
	PF_CTR__IMINLINE_Msk = 0xf        // Bit mask of _IMINLINE field.
	PF_CTR_DMinLine_Pos  = 0x10       // Position of DMinLine field.
	PF_CTR_DMinLine_Msk  = 0xf0000    // Bit mask of DMinLine field.
	PF_CTR_ERG_Pos       = 0x14       // Position of ERG field.
	PF_CTR_ERG_Msk       = 0xf00000   // Bit mask of ERG field.
	PF_CTR_CWG_Pos       = 0x18       // Position of CWG field.
	PF_CTR_CWG_Msk       = 0xf000000  // Bit mask of CWG field.
	PF_CTR_Format_Pos    = 0x1d       // Position of Format field.
	PF_CTR_Format_Msk    = 0xe0000000 // Bit mask of Format field.

	// CCSIDR: Cache Size ID register
	PF_CCSIDR_LineSize_Pos      = 0x0        // Position of LineSize field.
	PF_CCSIDR_LineSize_Msk      = 0x7        // Bit mask of LineSize field.
	PF_CCSIDR_Associativity_Pos = 0x3        // Position of Associativity field.
	PF_CCSIDR_Associativity_Msk = 0x1ff8     // Bit mask of Associativity field.
	PF_CCSIDR_NumSets_Pos       = 0xd        // Position of NumSets field.
	PF_CCSIDR_NumSets_Msk       = 0xfffe000  // Bit mask of NumSets field.
	PF_CCSIDR_WA_Pos            = 0x1c       // Position of WA field.
	PF_CCSIDR_WA_Msk            = 0x10000000 // Bit mask of WA field.
	PF_CCSIDR_WA                = 0x10000000 // Bit WA.
	PF_CCSIDR_RA_Pos            = 0x1d       // Position of RA field.
	PF_CCSIDR_RA_Msk            = 0x20000000 // Bit mask of RA field.
	PF_CCSIDR_RA                = 0x20000000 // Bit RA.
	PF_CCSIDR_WB_Pos            = 0x1e       // Position of WB field.
	PF_CCSIDR_WB_Msk            = 0x40000000 // Bit mask of WB field.
	PF_CCSIDR_WB                = 0x40000000 // Bit WB.
	PF_CCSIDR_WT_Pos            = 0x1f       // Position of WT field.
	PF_CCSIDR_WT_Msk            = 0x80000000 // Bit mask of WT field.
	PF_CCSIDR_WT                = 0x80000000 // Bit WT.
)

// Bitfields for AC: Access control
const (
	// ITCMCR: Instruction and Data Tightly-Coupled Memory           Control Registers
	AC_ITCMCR_EN_Pos    = 0x0  // Position of EN field.
	AC_ITCMCR_EN_Msk    = 0x1  // Bit mask of EN field.
	AC_ITCMCR_EN        = 0x1  // Bit EN.
	AC_ITCMCR_RMW_Pos   = 0x1  // Position of RMW field.
	AC_ITCMCR_RMW_Msk   = 0x2  // Bit mask of RMW field.
	AC_ITCMCR_RMW       = 0x2  // Bit RMW.
	AC_ITCMCR_RETEN_Pos = 0x2  // Position of RETEN field.
	AC_ITCMCR_RETEN_Msk = 0x4  // Bit mask of RETEN field.
	AC_ITCMCR_RETEN     = 0x4  // Bit RETEN.
	AC_ITCMCR_SZ_Pos    = 0x3  // Position of SZ field.
	AC_ITCMCR_SZ_Msk    = 0x78 // Bit mask of SZ field.

	// DTCMCR: Instruction and Data Tightly-Coupled Memory           Control Registers
	AC_DTCMCR_EN_Pos    = 0x0  // Position of EN field.
	AC_DTCMCR_EN_Msk    = 0x1  // Bit mask of EN field.
	AC_DTCMCR_EN        = 0x1  // Bit EN.
	AC_DTCMCR_RMW_Pos   = 0x1  // Position of RMW field.
	AC_DTCMCR_RMW_Msk   = 0x2  // Bit mask of RMW field.
	AC_DTCMCR_RMW       = 0x2  // Bit RMW.
	AC_DTCMCR_RETEN_Pos = 0x2  // Position of RETEN field.
	AC_DTCMCR_RETEN_Msk = 0x4  // Bit mask of RETEN field.
	AC_DTCMCR_RETEN     = 0x4  // Bit RETEN.
	AC_DTCMCR_SZ_Pos    = 0x3  // Position of SZ field.
	AC_DTCMCR_SZ_Msk    = 0x78 // Bit mask of SZ field.

	// AHBPCR: AHBP Control register
	AC_AHBPCR_EN_Pos = 0x0 // Position of EN field.
	AC_AHBPCR_EN_Msk = 0x1 // Bit mask of EN field.
	AC_AHBPCR_EN     = 0x1 // Bit EN.
	AC_AHBPCR_SZ_Pos = 0x1 // Position of SZ field.
	AC_AHBPCR_SZ_Msk = 0xe // Bit mask of SZ field.

	// CACR: Auxiliary Cache Control           register
	AC_CACR_SIWT_Pos    = 0x0 // Position of SIWT field.
	AC_CACR_SIWT_Msk    = 0x1 // Bit mask of SIWT field.
	AC_CACR_SIWT        = 0x1 // Bit SIWT.
	AC_CACR_ECCEN_Pos   = 0x1 // Position of ECCEN field.
	AC_CACR_ECCEN_Msk   = 0x2 // Bit mask of ECCEN field.
	AC_CACR_ECCEN       = 0x2 // Bit ECCEN.
	AC_CACR_FORCEWT_Pos = 0x2 // Position of FORCEWT field.
	AC_CACR_FORCEWT_Msk = 0x4 // Bit mask of FORCEWT field.
	AC_CACR_FORCEWT     = 0x4 // Bit FORCEWT.

	// AHBSCR: AHB Slave Control register
	AC_AHBSCR_CTL_Pos       = 0x0    // Position of CTL field.
	AC_AHBSCR_CTL_Msk       = 0x3    // Bit mask of CTL field.
	AC_AHBSCR_TPRI_Pos      = 0x2    // Position of TPRI field.
	AC_AHBSCR_TPRI_Msk      = 0x7fc  // Bit mask of TPRI field.
	AC_AHBSCR_INITCOUNT_Pos = 0xb    // Position of INITCOUNT field.
	AC_AHBSCR_INITCOUNT_Msk = 0xf800 // Bit mask of INITCOUNT field.

	// ABFSR: Auxiliary Bus Fault Status           register
	AC_ABFSR_ITCM_Pos     = 0x0   // Position of ITCM field.
	AC_ABFSR_ITCM_Msk     = 0x1   // Bit mask of ITCM field.
	AC_ABFSR_ITCM         = 0x1   // Bit ITCM.
	AC_ABFSR_DTCM_Pos     = 0x1   // Position of DTCM field.
	AC_ABFSR_DTCM_Msk     = 0x2   // Bit mask of DTCM field.
	AC_ABFSR_DTCM         = 0x2   // Bit DTCM.
	AC_ABFSR_AHBP_Pos     = 0x2   // Position of AHBP field.
	AC_ABFSR_AHBP_Msk     = 0x4   // Bit mask of AHBP field.
	AC_ABFSR_AHBP         = 0x4   // Bit AHBP.
	AC_ABFSR_AXIM_Pos     = 0x3   // Position of AXIM field.
	AC_ABFSR_AXIM_Msk     = 0x8   // Bit mask of AXIM field.
	AC_ABFSR_AXIM         = 0x8   // Bit AXIM.
	AC_ABFSR_EPPB_Pos     = 0x4   // Position of EPPB field.
	AC_ABFSR_EPPB_Msk     = 0x10  // Bit mask of EPPB field.
	AC_ABFSR_EPPB         = 0x10  // Bit EPPB.
	AC_ABFSR_AXIMTYPE_Pos = 0x8   // Position of AXIMTYPE field.
	AC_ABFSR_AXIMTYPE_Msk = 0x300 // Bit mask of AXIMTYPE field.
)
